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OKI ML674000, ML674001, ML674002, ML674003 User`s Manual

1. Output Input Start Stop Restart Acknowledge Negative Acknowledge Negative sequence sequence sequence received acknowledge transmitted acknowledge received transmitted I2CSAD I2CDR I2CSAD sB BBBBBB 71615 4131211 716151413 2 110 7 6 15 4 13 12 1 71615 4 3 2 110 I2CIR 1 Ta 1 ag I2CAAK 0 I2CAAK 0 I2CDR 0 5 5 I2CSAD 1 PROD Di DOOR 2 xxx0x101b I2GDR 90000006b To receive continuously I2CCON xxx0x111b 20 16 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 3 7 Start byte transmit operation There are some I2C devices that require a unique start sequence in order to work properly This sequence can be supported in this I2C block by using the special start byte generation technique In this LSI the transmission of the start byte is accomplished by setting the START bit bit 4 of the I2CCON register to 1 To transfer 1 byte of data to a slave device that requires the start byte The I2CSAD register is set to 00000001 start byte pattern The I2CCON register is set to 1 110 following series of operation is automatically performed when both the STCM bit bit 2 of th
2. neweale laztLL2chR 4JIlIe LDeuzllll2 Lz pl l2zclE2z2cl2lzllbhzlzzl2clclhllb2zzoezdalzL lkl zl2dl brzl2c2c2zzplzz I p 4 4 4 4 4 4 4 4 4 m i i n misi itm mmm m R emA A hR 4J4 l L l L zz2c2z 2zz2zLE ljd Ll 2l 22z2z l 2 dl LE 22zl2cg L 2c2 L L lz dl L 2 lzL J2 cz zl d 2 p bR 1 4 4 f 4 F 1 4 FB bR 4 b 4 B 4 t 4 am p 4 4 4 4 4 4 4 4 4 gt Llzllz 2zh l2z l 2122 2 l z LE zl 2 L L IbE 2 I b2z2 2z L J22z 2L 2l 2p d bB 4 H d t d F 4 d b M B d b M B d t Qq a k min tn mp mm mmm qmm mm 25 1 PPE
3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DRPC 25 sos or E EE Se k After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ c 7 _ 205 205 _ _ 225 EN E 205 DRAMSPEC 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access 0x78180008 Address R W Access size 32 bits Note These bits are reserved for future expansion They return O for reads Writes to them are ignored Bit Descriptions DRAMSPEC 3 0 bits 0 to 3 These bits specify the DRAM access timing parameters in clock cycles DRAMSPEC 3 0 SDRAM operation EDO DRAM operation 3121110 tRCD RAS tRP tDPL ae tRCD E tRP 1 2 1 1 1 2 1 1 High Low 1 1 3 1 1 1 2 1 2 Speed frequency 0010 2 3 2 1 1 3 1 2 01011 1 2 4 2 1 1 3 1 3 2 4 2 2 1 3 2 3 0111011 2 5 2 1 1 4 2 4 011 110 2 5 2 2 1 5 2 5 011 1 1 2 5 3 1 2 4 2 4 1000 3 5 3 2 2 5 2 5 1001 3 6 3 2 2 6 2 6 Low High reserved 3 8 3 7 Speed frequency 1 0 1 1 reserved reserved 1 1 010 1 1 0 1 reserved reserved 1 1 1 0 reserved reserved 1 1 1 1 reserved reserved Notes 1 Operation is not guaranteed for
4. LA vm N 0 5 E 0 6 0 15 77070 SEATING PLANE gt Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating 25 Oki Electric Industry Co Ltd Package weight g 1 37 TYP Rev No Last Revised 5 Nov 28 1996 ML674001 Series ML675001 Series User s Manual Appendixes P LFBGA144 1111 0 80 1 0 0 80 E 0205 13 000000 000000 12 0 0000 0000 0000 00008 8 eeee ee 7 0000 0900 6 0000 5 4 0000000000000 3 2 opnooopoooooQ 1 JHGFEDCBA INDEX MARK INDEX MARK 0 5 0 1 Package material Epoxy resin Ball material Sn Pb Oki Electric Industry Co Ltd Package weight g 0 30 Rev No Last Revised 1 Aug 25 1999 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number pack
5. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB6001010 H Access R W Access size 16 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions e ADFAS bit 0 Setting this bit to 1 forces assertion of the interrupt signal This facility is for test purposes Writing 0 to this bit resets it 21 9 ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter 21 2 6 Analog to Digital Converter Result Registers ADRO to ADR3 These registers hold the result of converting the corresponding analog input The program has read write access to these registers The contents after a reset are 0 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ADRA ee Pera DTn 9 0 After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 0 to 3 Address 0xB6001014 ADRO 0xB6001018 ADR1 0xB600101C ADR2 0xB6001020 ADR3 Access R W Access size 16 bits Notes These bits reserved for future expansion They return 0 for reads Writes to them ignored Writing to result register ADRO to ADR3 while the analog to digital converter is in operation invalidates the contents of the entire set Bit Descriptions DTn bits 9 to 0 This is the result of converting the corresponding an
6. 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Address 0x7810000C Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored When switching operating frequencies adjust the contents of this register at the lower frequency that is AFTER a change from high speed to low speed and BEFORE one from low speed to high speed Bit Descriptions e JOOLTYPE 2 0 bits 0 to 2 These bits specify the access timing for I O bank 0 1 This table is applied only to ML674001 series 1001TYPE 2 0 Pulse width in clock cycles 2 1 o Address OR WE pulse cad off time mole setup time width 0 0 1 1 0 1 4 2 0 1 0 reserved Operation is not guaranteed for a setting labeled reserved 0 1 1 2 8 4 1 0 0 2 12 1 0 1 2 16 7 1 1 0 reserved Operation is not guaranteed for a setting labeled reserved 1 1 1 4 24 10 11 10 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller This table is applied only to ML675001 series IO01TYPE 2 0 Pulse width in clock cycles Notes 21110 Adoress Rule setup time width 0 0 0 1 1 0 0 1 4 3 0 1 0 reserved is not guaranteed for a setting labeled reserved 0 2 8 5 1 0 0 2 1
7. 3 6 3 4 1 5 3 6 342 Boot Control eee eet enim e o pee 3 7 343 Notesof Address dede del wl HO Red eed atio edge 3 7 3 4 4 Remap Setting REE 3 8 Chapter4 Chip Configuration Ai OVERVIEW aoa ete ne re rae hace nese Rebbe hee eu Bede Er E MT E u 4 1 PET Pith 4 1 42 er RR ER RR 4 1 Chapter 5 Clock Generator SiL OVERVIEW isi ee nionem ae tta ee toe hel rep et er Se ROS EE ERR anaes 5 1 5 1 1 Compon nts emet eo E oU enne e prO re tere sss 5 1 5 L2 Pin list usse HE eee dn 5 2 513 PLL Clock frequency setup ML675001 Series Only 5 2 52 Sample Crystal Connections palate ee ee e p ee ci ap e Masa ete 5 2 Chapter 6 Reset Control OVETVIE WR dion idee t 6 1 Pit List lise Anish dictt Aii tt idest 6 1 6 2 Reset Types iso hehe Amp Rr ae t a Assen tue a ADD E AI eA gn 6 1 6 24 External Reset iain preme e bep ero mp Aes 6 1 6 2 2 Watchdog Timer Overflow
8. T p b 1 4 4 f Q4 F 1 4 bR 4 B 4 FB 4 FB 4 t 4 4 4 4 arm7tdmi din 31 0 arm7tdmi mclk arm7tdmi a 31 0 arm7tdmi nrw o 31 0 htrans o 1 0 hburst o 1 0 hwrite o hready o hrdata o 31 0 xrame xao 31 0 xre xdi 31 0 G in the figure e During a non cacheable access the cache controller carries out an AHD access in the figure The waiting duration of the CPU varies depending on the previous access state in the figure and on the memory The CPU is kept waiting until the access is completed access duration in the figure The above example is of an operation when the succeeding access is a read hit 9 15 Chapter 10 Built In Memory ML674001 Series ML675001 Series User s Manual Chapter 10 Built In Memory Chapter 10 Built In Memory 10 1 Overview This LSI contains 32kilobytes 8K x 32 bits of built in SRAM and ROM Less or 256kilobytes 128K x 16 bits or 512kilobytes 256K x 16 bits of built in FLASH ROM 10 2 Built In SRAM The built in RAM has the following features e 32kilobytes 8K x 32 bits e Bus width 32 bits with 8 16 and 32 bit read write access Address map Access clock cycles Bank Mirro
9. 13 7 13 2 5 Port Interrupt Polarity Register GPIPA GPIPB GPIPC GPIPD and GPIPE 13 8 13 2 6 Port Interrupt Status Registers GPISA GPISB GPISC GPISD and 13 9 13 2 7 Port Function Select Register GPCTL nennen nnnm ener nnne nnne 13 10 13 3 Description of Operation 4 diede tenia t edet aie id ater te aide ale 13 14 19 3 1 Interrupt 13 14 13 3 2 Primary Secondary function configuration 13 15 Chapter 14 Watchdog Timer WDT IC MEM CN E feats 14 1 T4 1 1 Components eite tee e i Htec IR e rie eere 14 1 14 1 2 Neo et t e Pei E UE esteri iei 14 1 14 2 Register eret edt edo NE et e d reU 14 2 14 2 1 Watchdog Timer Control Register esee nennen nennen enne nennen 14 2 14 2 2 Time Base Counter Control Register WDTBCON sse eene nennen 14 3 14 2 3 Status Register 14 5 14 3 of
10. Afterareset 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 22 _ _ 2 _ vog AE EN i CKWT L L L 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Address 0xB800000C Access R W Access size 32 bits Notes These bits are for future expansion This register features write protection to prevent errant software from accidentally overwriting register contents The program must first write 0 0000003 to it immediately before updating its contents Bit 31 8 return 0 for reads Writes to them are ignored Bit 7 4 return 1 for reads and should be written 1 to them Bit Descriptions e CKWT bits 0 to 3 These bits specify the amount of time to wait after waking the LSI from the STANDBY mode for the oscillation to stabilize before restoring clock signals to the functional blocks The following Table gives rough values for operation The 0000 setting is for External clock input with wait of input clock to provide the chip internal clock ML674001 Series only The setting 1111 is for using Crystal Oscillator with a wait between 10 ms and 24 ms regardless of the clock frequency After a reset CKWT registor has no effect When the crystal is connected assert the reset signal more than 10 ms to stabilize an internal clock CKWT Wait Interval 3 2 1 0 ML674001 Series at 33MHz ML6750
11. enne nnne nennen trennen nre 18 15 18 2 9 Modem Status Register 8 2 1 21 4014 030 02140 000 00111000 nre ennt ener nennen nnne 18 18 18 2 10 Scratch Register 2 4 0 22000000 eene eren enne nennen 18 20 18 2 11 Divisor Latch LSB 18 21 18 2 12 Divisor Latch MSB UARTDLMB 18 22 18 3 Desciiption of Operation utt eee t ne ie pin davies EH ruo RS pa s s 18 23 18 3 1 Transmitting Data aa eene bep e RD aD IO pe hne e o eet a ais 18 23 18 3 2 Receiving Datas oss e perdre tnde tede eid alin ft e enun 18 24 18 3 3 Generating Baud Rate Clock 4 eii eter te ripe mee to 18 26 18 3 4 B ttered Operations m dat et Ree ei alin baypa usis 18 27 15 3 5 Queue Polled ena e hem ete e erae ee emi 18 28 IOS EIDI ELUCET E 18 29 18 3 7 Setup Procedure tede epe echt tu bees Apes e e i Went n Eee e iro 18 30 Chapter 19 Synchronous 510 19 OVerVIeW ya pa a ahua pre tere pU epi HE 19 1 19 1 T Configuration EUR p ER PU Re b ELDER Dp 19 1 19 12 East oE P nens ete EHE tr p E p RED REEL a ys 19 2 19 1 3 Eistof 19 2 19 2 Registets RU re pr FU
12. qus SES 432111 1113 tspxap XA 15 0 RA1 1 tspcsp tspcsp tspcsp tspcsp tspcsp tspcsp Mm lt gt lt 9 XSDCS N j tspRasp tsprasp tspRAsp tspRAsD tspRAsp XRAS N tspcasp tspcasp XCAS N tspwED tspwep lt gt XWE_N tsppovp gt XSDCKE tspxpis tspxpiH SDXDIH X XD 15 0 D1 1 D1 2 24 39 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics SDRAM Write Cycle Bus Width 16 bit SDRAM Word Access Ly lly n t span XA 15 0 RA1 tspcsp tspcsp tspcsp tspcsp tspcsp tspcsp tspcsp gt 4 gt lt gt 4 gt XSDCS N tepRAS tspRP x lt p 4 p tspRAsD tspRasD tsprasp tsprasp tspRasD XRAS N H gt t SDCASD spcAsD XCAS N t t spwED tspwED SDWED SDWED XWE_N t t SDDQMD tsppamp SDDQMD XDQNT 1 0 XSDCKE tspxpop lt b lt gt tspxpopE exor 5 lt XD 15 0 D1 1 24 40 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics EDO DRAM Read Cycle Bus Width 16 bi
13. BCKCTL 10 Description 0 Supply 1 Stop BCKCTL 11 bit 11 This bit controls the SSIO clock signal BCKCTL 11 Description 0 Supply 1 Stop BCKCTL 12 bit 12 This bit controls the I2C clock signal BCKCTL 12 Description 0 Supply 1 Stop 7 6 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 3 2 Clock Stop Register CLKSTP This register controls transitions to the HALT and STANDBY modes and the clock signals to two more functional blocks 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLKSTP ize Ex Lick 2203 con ED 42 229 zx x 229 c After areset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 7 6 5 4 3 2 1 0 a _ STBY TIC SIO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8000004 Access R W Access size 32 bits Notes These bits are for future expansion They return 0 for reads Writes to them are ignored This register features write protection to prevent errant software from accidentally overwriting register contents The program must first write 0x0000003C to it immediately before updating its contents Bit Descriptions e SIO bit 0 This bit controls the SIO block clock signal SIO De
14. IO23TYPE 2 0 Pulse width in clock cycles Notes Aadress pulse setup time width 0 1 1 1 4 2 0 4 0 reserved is not guaranteed for a setting labeled reserved 0 1 1 2 8 4 1 0 2 12 1 0 1 2 16 7 4 4 0 reserved Operation is not guaranteed for a setting labeled reserved 1 1 1 4 24 10 11 12 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller This table is applied only to ML675001 series IO23TYPE 2 0 Pulse width in clock cycles Notes 2 1 Address OEWE pulse Read off time setup time width 0 0 0 1 1 0 0 1 4 3 0 1 0 reserved Operation is not guaranteed for a setting labeled reserved 0 2 8 5 1 0 0 2 12 7 1 0 2 16 8 1 1 0 reserved Operation is not guaranteed for a setting labeled reserved 1 1 1 4 24 11 11 13 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 7 DRAM Bus Width Control Register DBWC This register specifies the bus width for the DRAM region The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 DBWC l l l l l l l l l l l l l l l l Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5
15. 16 7 15 0 84 7 5 The DRAMSPEC bits in the DRPC register specify a combination of access timing parameters tRCD tRAS tRP etc as shown in the table under the register description There is no way to specify these parameters individually Minimum Operating Frequencies Minimum Operating Frequencies HCLK ML674001 Series ML675001 Series SDRAM 2 56 MHz 2 56 MHz EDO DRAM 6 4 MHz 6 4 MHz SDRAM Access Timing Parameters and Operating Frequency Access Parameters clock Access Parameters clock os Access Parameters ns cycles at 16 7 uc cycles at 33 3 PCxx tRCD tRAS tDPL tRCD tRAS tRP tRCD tRAS tRP tDPL 133 15 45 15 10 1 2 1 1 1 2 1 1 133 20 45 20 10 1 2 1 1 1 2 1 1 133 20 45 20 15 1 2 1 1 1 2 1 1 125 20 48 20 8 1 2 1 1 1 2 1 1 125 20 48 20 10 1 2 1 1 1 2 1 1 125 20 50 30 8 1 2 1 1 1 2 1 1 125 24 48 24 10 1 2 1 1 1 2 1 1 100 20 50 20 10 1 2 1 1 1 2 1 1 100 20 50 20 15 1 2 1 1 1 2 1 1 100 20 50 20 20 1 2 1 1 1 2 1 1 100 30 50 30 15 1 2 1 1 1 2 1 1 100 30 60 30 10 1 2 1 1 1 2 1 1 100 30 60 30 15 1 2 1 1 1 2 1 1 83 35 70 45 24 1 2 1 1 2 3 2 1 66 30 60 30 15 1 2 1 1 1 2 1 1 66 30 70 30 15 1 2 1 1 1 3 1 1
16. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRQA uo Em X 36 mm 227 Bee irp Row E uo Afterarest 0 0 0 15144 19 12 1 10 9 8 7 6 5 4 3 2 1 0 IRQ 31 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 O Address Ox7BF00010 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions IRQI31 16 bits 0 to 15 When reading these bits return the status of pending interrupts Reading 1 in bit n indicates a pending interrupt request unmasked from the corresponding IRQ source The below table summarizes this IRQ 31 16 Description 0 No interrupt request pending 1 Interrupt request pending Writing a 1 to either of bits 6 10 12 and 15 resets it to 0 clearing the corresponding interrupt request but only if that external interrupt nIR22 nIR26 nIR28 and nIR31 is configured as edge triggered Such writes are ignored for level detection as are writes to the IRQ clear IRCL register Also writes to bits other than bit 6 10 12 and 15 are ignored The following table summarizes the effects of a write to bits 6 10 12 15 of this register IRQ 31 16 De
17. Instruction code Instruction Register to be selected IR2 IR1 IRO EXTEST Boundary scan register 0 0 0 SAMPLE Boundary scan register 0 1 0 IDCODE ID register 0 0 1 BYPASS Bypass register 1 1 1 EXTEST The EXTEST instruction is used for testing the connection status at board level It inputs the output signals of the boundary scan cells of the device in the previous step into the input boundary scan cells in the Capture DR state It outputs the data in the output boundary cells to the output pins in the Update DR state Because the core logic circuit and the boundary scan cells are disconnected the data that has been input is not transmitted to the core logic circuit but is input into the input boundary scan cells The data which has been input into the input boundary scan cells can be output from the TDO pin by repeating a shift operation SAMPLE The SAMPLE instruction is used to sample the status of input output pins during a normal operation It inputs input output signals into the input and output boundary scan cells in the Capture DR state The data that has been input is latched inside the boundary scan cells in the Update DR state Unlike the EXTEST instruction the core logic circuit and the boundary scan cells are connected in the case of the SAMPLE instruction However the status of input output data can be sampled during a normal operation via the boundary scan register without affecting system operati
18. Note The DRAM controller assumes tRC tRAS tRP so also check tRC if the SDRAM specifies tRC gt tRAS 11 31 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller EDO DRAM Access Timing Parameters and Operating Frequency Access Parameters ns Access Parameters clock Access Parameters clock tRAC cycles at 16 7 MHz cycles at 33 3 MHz ns tRAH tCAC tRAH tCAC tRAH tCAC tRCD tRCD tRP tRCD tRP tCAS tOEZ tCAS tOEZ tCAS tOEZ 50 7 37 13 30 1 2 1 1 1 2 1 1 50 8 35 15 30 1 2 1 1 1 2 1 1 50 8 37 13 30 1 2 1 1 1 2 1 1 50 10 36 20 40 1 2 1 1 1 2 1 2 50 15 45 15 40 1 2 1 1 1 2 1 2 60 10 40 20 40 1 2 1 1 1 2 1 2 60 10 45 15 40 1 2 1 1 1 2 1 2 60 20 50 20 50 1 2 1 1 1 2 1 2 70 10 50 20 40 1 2 1 1 1 2 1 2 70 10 50 20 50 1 2 1 1 1 2 1 2 70 13 50 20 50 1 2 1 1 1 2 1 2 70 20 60 20 60 1 2 1 1 1 2 1 2 80 10 60 15 60 1 2 1 1 1 2 1 2 100 25 75 25 70 1 2 1 2 1 3 1 3 11 32 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 3 6 Read off time Control The External Memory Controller automatically inserts as necessary read off time to avoid collisions between XD data from successive accesses to external ROM SRAM I O or DRAM Read off time is the minimum number of clock cycles between chip select signal going inactive until the next chip select
19. Function In Out Function In Out PIOC 7 In Out XWR Output GPCTLS bit 8 This bit controls the function of pin PIOE 2 0 Its secondary function is as SSIO GPCTL8 0 primary function 8 1 secondary function Function In Out Function In Out PIOE 0 In Out SCLK In Out PIOE 1 In Out SDI Input PIOE 2 In Out SDO Output 9 bit 9 This bit controls the function of pin PIOE 4 3 Its secondary function is as SSIO GPCTL9 0 primary function GPCTL9 1 secondary function Function In Out Function In Out PIOE 3 In Out SDA In Out PIOE 4 In Out SCL Output GPCTL10 bit 10 This bit controls the function of pin PIOE 5 Its secondary function is as EXINT 0 GPCTL10 z 0 primary function GPCTL10 1 secondary function Function In Out Function In Out PIOE 5 In Out 0 Input 11 bit 11 This bit controls the function of pin PIOE 6 Its secondary function is as EXINT 1 GPCTL11 0 primary function GPCTL11 1 secondary function Function In Out Function In Out PIOE 6 In Out EXINT 1 Input 12 bit 12 This bit controls the function of pin PIOE 7 Its secondary function is as EXINT 2 GPCTL12 0 primary function GPCTL12 1 secondary function Func
20. ns 1 tuc 1 5 txpopE 6 24 18 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B O Control signal timing 2 25 to 2 75 3 0 to 3 6V Ta 40 to 85 C IO 0 10 1 10 2 10 3 Condi Item Symbol tions Minimum Typical Maximum Unit Notes XIOCS N OJXIOCS N 1 IO01AC IO23ACX and access time 1 i 5 Pss IO23ACY registers specify external 0 1 2 and 3 XIOCSRI mores ot tue the OE WE pulse width READ ACCESS and read off time for XIOCS N OJXIOCS accessing external I O 0 1 access tima 2 5 2 nio tuc 2 and 3 respectively For external I O 0 1 2 and 3 XIOCSR2 luc 4 E n 2 section 11 2 5 and 11 2 BEAD ACHES of chapter 11 XA 23 0 access time external I O 0 1 2 and 3 res XBS N 1 0 access time external I O 0 1 2 and 3 txioss 1 3 Mior tHo 1 5 XWR delay t 0 a 35 external I O 0 1 2 and 3 XIOWRD XWR hold time 30 pF ica 2 033 hio Address Setup external 0 1 2 and 3 OE WE Pulse width XWAIT sampling timing delay 1 Riga Address Setup 1 xIOWAITD1 nio2 tuc kas nio2 tuc Pulse external 0 1 2 and 3 z ns width XWA
21. 1 neo tRCD EDO DRAM EDRAS ED7 tHC ED1 RAS precharge time EDO DRAM nens 4 2 tCAS CAS precharge time EDO DRAM luc 4 tRP XRAS N delay EDO DRAM 2 tuc 2 1 tCAS XOE N delay 1 ERG DIAM tepoEp1 nens 4 nens tuc nens XOE delay 2 EDO DRAM 2 2 1 Neva te epe CAC 1 delay 1 tepwep1 CL neps tuc 4 tuc 2 tRCD N tCAC 1 XWE_N delay 2 30 pF EDO DRAM teowev2 tuc 2 tuc Data Size Bus Width Row address hold time ns EDO DRAM 5 tuc 2 5 tuc 4 Column address delay EDO DRAM tEDCAD tuc 2 tuc 4 Column address hold time t 2 OR EDO DRAM EDCAH ED2 ED2 XD 15 0 sampling timing t 2 delay EDO DRAM EDXDSMPLD ED6 ED6 XD 15 0 input setup time t 16 2 2 EDO DRAM XD 15 0 input hold time t 0 EDO DRAM XD 15 0 output delay 1 t 0 2 6 EDO DRAM EDXDOD1 XD 15 0 output delay 2 t 0 5 6 EDO DRAM XD 15 0 output hold time t CL PES m 2 EDO DRAM EDXDOH 30 pF ED2 XD 15 0 output enable t 5 1 a 2 time EDO DRAM 1 XD 15 0 output disable t 2 time EDO DRAM
22. p 4 4 4 4 4 4 4 4 4 a i i ah wc a Sah il Al ah Sh Spm es i acl d P M E pasasqa aya 2 22 2p bB 4 4 4 4 bR 1 4 b 4 fL 4 FbR 4 t 4 b 4 F 4 4 4 4 4 4 4 inm Ran m tmm Sc hc es l l lh ah nl a PEEN St alt ka qasa a EA PETE a se a a kA ee 4 4 4 a 2 222pBp 2 2 2 2 LB 4 4 4 LE 4 F 4 tT 4 RB 4 tT 4 P 4 PL arm7tdmi mclk arm7tdmi a 31 0 arm7tdmi din 31 0 arm7tdmi nrw haddr o 31 0 htrans o 1 0 hburst_o 1 0 hwrite_o hready_o hrdata o 31 0 xrame xao 31 0 xre xdi 31 0 During a cache miss the cache controller carries out a 4 word wrap 4 AHB read access in the figure The waiting duration in the figure of the CPU varies depending on the previous access state in the figure and The CPU will be kept waiting until the access is completed on the memory access duration in the figur
23. FCR 1 Description 0 Normal operation 1 Clear receive queue Note This operation does not clear the receive shift register FCR 2 bit 2 XMIT queue reset Setting this bit to 1 clears the transmit queue FCR 2 Description 0 Normal operation 1 Clear transmit queue Note This operation does not clear the transmit shift register FCR 3 bit 3 DMA mode select Note This LSI does not support DMA transfers to or from the UART FCR 5 4 bits 5 to 4 Reserved ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte FCR 7 6 bits 7 to 6 RCVR queue interrupt trigger level These bits specify the trigger level for receive queue interrupts FCR 7 6 Description 7 6 0 0 1 byte 0 1 4byte 1 0 8byte 1 1 14 byte 18 10 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 6 Line Control Register UARTLCR This register specifies the character format The CPU has read write access to this register Allowing reads eliminates the need to save line characters separately in system memory The register contents after a reset are 0 00 7 6 5 4 3 2 1 0 UARTLCR LCR 7 0 After a reset 0 0 0 0 0 0 0 0 Address 0 7 0000 Access R W Access size 8 bits Bit Descriptions LCR 1 0 bits 1 to 0 These bits specify the character length
24. cerne q R 12 17 12 3 4 Ending DMA Transfer iecore eene i eene tere dete eed eo eee s 12 18 12 3 57 DMA Channel Priority n hei cie en RE aia ed te he ies 12 20 12 3 6 Important Usage Notes need en emo e o Dp ER DIT hire ain es tyr 12 21 12 4 DMA Tr nster err e dh Ee GI D etna db I p 12 22 124 1 Starting a Transfer i o8 em eere REP ep m ode d 12 22 12 4 2 Transfer Timing o eere e AT A e o atte 12 23 Chapter 13 GPIO 13 1 EE 13 1 13 1 1 lt 13 2 13 12 8 e Te pe p 13 3 18253 R sister Liste etate rtr 13 4 13 2 Regist r D SCIIDUOUS ep e poe 13 5 13 2 1 Port Output Registers GPPOA GPPOB GPPOC GPPOD and GPPOB 13 5 13 2 2 Port Input Registers GPPIA GPPIB GPPIC GPPID and GPPIE eese 13 5 13 2 3 Port Mode Registers GPPMA GPPMB GPPMD and GPPME eee 13 6 13 2 4 Port Interrupt Enable Registers GPIEA GPIEB GPIEC GPIED and
25. 14 6 14 3 1 Operation tete ru EU TR Cen E EU ER eb E E 14 6 ML674001 Series ML675001 Series User s Manual Table of Contents 14 3 2 Interval Timer Operatioh ee e Street Aree d e tetra 14 6 143 3 Watchdog Timer Operation exeo tee ett e a epo ee ee 14 6 14 3 4 Starting Ee ei p e 14 6 Chapter 15 Timers 15 T Overview iicet tectum REG re he ie EU P RO Eae e co EO TED OR ERE HE 15 1 15211 15 1 15 12 R rister Listu UT u p Sube BUR re EE 15 3 15 2 Register Descriptions eee Ben RR eH or E 15 4 15 2 1 System Timer Enable Register eese nne nutakuna ndau 15 4 15 2 2 System Timer Reload Register 2 40244 1 0000000000000000000000000000000000000 15 5 15 2 3 System Timer Overflow Register TMOVER 15 6 15 2 4 Timer Control Registers TIMECNTLO to TIMECNTL5 ener 15 7 15 2 5 Timer Base Registers TIMEBASEO to 8 5 15 9 15 2 6 Timer Counter Register TIMECNTO to TIMECNTS5 nnne 15 10 15 2 7 Ti
26. CCLKSEL HCLKSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8000008 Access R W Access size 32 bits Notes These bits are for future expansion They return 0 for reads Writes to them are ignored This register features write protection to prevent errant software from accidentally overwriting register contents The program must first write 0x0000003C to it immediately before updating its contents Bit Descriptions e HCLKSEL bits 0 to 2 and CCLKSEL bits 4 to 6 These bit fields respectively specify the HCLK and CCLK frequency divisors HCLKSEL Frequency divisor 2 1 0 0 0 0 1 1 0 0 1 1 2 0 1 0 1 4 0 1 1 1 8 1 0 0 1 16 1 0 1 1 32 675001 Series Only 1 1 0 reserved 1 1 1 reserved CCLKSEL Frequency divisor 6 5 4 0 0 0 1 1 0 0 1 1 2 0 1 0 1 4 0 1 1 1 8 1 0 0 1 16 1 0 1 1 32 ML675001 Series Only 1 1 0 reserved 1 1 1 reserved 7 9 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 3 4 Clock Wait Register CKWT This register specifies the interval to wait after waking the LSI from the STANDBY mode for the oscillation to stabilize before restoring clock signals to the functional blocks 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CKWT A E E E EE cx Ex 225 zl
27. eoe etre tdi eee e e etai 8 33 8 6 Int rrupt Acceptance Timing Charts usu be aD c e otii 8 34 8641 FIQ Interrupt Timing Chatt u iot RUD AC etl eap Eee 8 34 8 6 2 IRQ Interrupt Timing Chart nIRO to nIRI5 esssssssssseseeeeer eere 8 34 8 6 3 IRQ Interrupt Timing Chart nIR16 to nIR31 cece nnne 8 36 Chapter 9 Cache Memory 9 1 OVervIe Wa sinu scope Ie bee aue teta eel pe b ae 9 1 9 bl Configuration esee iren tee ei Roe e ere cr RR ra a a pah trug de s 9 9 1 2 Lastof Control Registers eee a tecto cae ei dette pt tr tace 9 2 9 2 Descrption of Control Registers i a e dau ias is 9 2 9 2 Cache Lock Control Register CONJ seaman nennen nnne uk q aa U MS ishq 9 2 922 Cacheable Register CACHE aute ae nth tiet Bette aet He T IRR TR IER dee 9 4 923 FEUSH Register FLUSH utt adt aec m te Dae i e 9 5 9 3 Description Operations dod et ate d eC hua qapas u uha Gu bu s 9 6 9 3 1 Initialization of Cache Memory u a a paqu sss asun u asua am u u u nennen ne Sisi ss 9 6 9 3 2 Cacheable Nonscaeheable SettIReru ama e uuu uui Sh 9 6 9 3 3 Description of operat ons one ek u u nO eere bte naa S Supap siga 9 6 iii ML674001 Series ML675001 Series User s Manual Table of Contents 923 4 Lock Function er ag io ret a REDI rte ep
28. request signal CH1 79 K13 PIOB 3 General port with interrupt function DREQCLR 1 DREQ Clear Signal CH1 80 J11 PIOB 4 y o General port with interrupt function TCOUT O O DMAC Terminal Count CHO 81 K12 PIOB 5 General port with interrupt function 1 DMAC Terminal Count 1 9 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Pin Primary Function Secondary Function LQFP BGA Symbol Description Symbol Description CH1 82 J13 PIOC O0 y o General port with interrupt function PWMOUTT O0 O PWM output CHO 83 J10 PIOC 1 General port with interrupt function PWMOUTT 1 O PWM output CH1 84 J12 GND GND GND 85 H13 XBS External bus byte select LSB 86 H12 XBS N 1 External bus byte select MSB 87 H10 VDD CORE VDD CORE power supply 88 H11 PIOD 0 y o General port with interrupt function XWAIT Wait input signal for I O Bank 0 1 2 3 89 G12 PIOD 1 y o General port with interrupt function XCAS N O Column address strobe SDRAM 90 G10 GND GND GND 91 G11 VDD IO VDD power supply 92 G13 PIOD 2 y o General port with interrupt function XRAS N O Row address strobe SDRAM EDO DRAM 93 F11 PIOD 3 y o Gener
29. 1 XWE_N delay 2 30 pF _ EDO DRAM teowev2 2 tuc tRCD N tCAC 1 Row address hold time EDO DRAM tEDRAH tuc 2 neps tuc 4 ns N Data Size Bus Width Column address delay EDO DRAM tepcap tuc 2 tuc 4 Column address hold time t PN PET ee ee EDO DRAM EDCAH ED2 ED2 tHC XD 15 0 sampling timing t ios delay EDO DRAM EDXDSMPLD ED6 ED6 XD 15 0 input setup time t 16 2 2 EDO DRAM XD 15 0 input hold time t 0 EDO DRAM ERAD XD 15 0 output delay 1 t 0 6 EDO DRAM EDXDOD1 XD 15 0 output delay 2 t 0 5 6 EDO DRAM EDXDOD2 XD 15 0 output hold time t CL TET EDO DRAM EDXDOH 30 pF ED2 XD 15 0 output enable t 5 1 E E time EDO DRAM 1 XD 15 0 output disable t E 2 time EDO DRAM m 0 5 24 13 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 24 4 2 AC Characteristics for ML675001 Series B Power Supply On OFF Timing 2 25 to 2 754 Vpp 3 0 to 3 6V Ta 40 to 85 C Item Symbol dod Minimum Typical Maximum Unit Notes AVDD Supply on Delay ON 0 zz ns VDD Supply on Delay 0 ns VDDcore Supply on tvDDCORE 0 ns Delay AVDD Supply off Delay AVDD_OFF 0 ns V
30. 1 the WDSTAT register 15 13 15 13 Rewrite the description of the section 15 3 1 16 2 16 2 Correct a misdescription in the pin list 18 24 18 24 a misdescription about baud rate Add a note about the frequency of CCLK 18 29 18 26 HCLK o Modify the operating clock SSIO from 19 9 19 9 CCLK to HCLK Correct a misdescription about the I2CEN 20 9 2058 bit of the 12 register 22 1 22 1 Add write protect unprotect time Add a sample connection programming 229 223 the FLASH memory 23 8 23 8 Add IDCODE 24 1 to 24 1 to M 24 42 24 48 Rewrite the electrical characteristics NOTICE 1 The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being referred to is up to date 2 The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs 3 When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature 4 Oki assumes no responsibility or liability whatsoever for any failure or unu
31. 12 4 12 1 3 List eee EEUU RECHT o ERU ERU ERE 12 4 122 Register Descriptions niente p UD t qeu d p Pe e UR OG 12 5 12 2 1 DMA Mode Register 22 00 12 5 122 2 Register DMASTA sitet repete ta i e oe ei 12 6 12 2 3 DMA Transfer Complete Status Register DMAINTD enne nennen 12 7 12 2 4 Channel Mask Registers 5 and DMACMSKHI sese 12 9 12 2 5 Transfer Mode Registers DMACTMODO and DMACTMOLD 12 10 12 2 6 DMA Transfer Source Address Registers DMACSADO and 12 12 12 2 7 DMA Transfer Destination Address Registers DMACDADO and DMACDAD 12 13 12 2 8 DMA Transfer Count Registers DMACSIZO and DMACSIZLI 12 14 12 2 9 DMA Transfer Complete Status Clear Registers DMACCINTO and 12 15 12 3 Operational Description 24255211 ere A bri eta bi 12 16 12 31 DMA Transfer Modes iere reete ter eie e eee er eb red ia eode e eee E pen 12 16 12 3 2 DMA RequestS OUrCeS decent bien eee olei Pb etie 12 16 12 3 3 Starting Transfer
32. 2 Notes 1 Minimum of 2 56 MHz Maximum of 390 6ns for external SDRAM Minimum of 6 4 MHz Maximum of 156ns for external EDO DRAM 2 Minimum of 2 MHz Maximum of 500ns for analog to digital converter 3 Refer to Chapter 5 about the relation of tc and tuc 24 15 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B Reset Interrupt DMA Timing 2 25 10 2 75V 3 0 to 3 6V Ta 40 to 85 C Item Symbol abd Minimum Typical Maximum Unit Notes Except for when power is first RESET N pulse width 1 trstw1 20 ns japplied or returning from STANDBY mode Oscillation When power is first applied or RESET N pulse width 2 trstw2 stabilization returning from STANDBY interval mode EFIQ N pulse width teFlaw 2 tuc EXINT pulse width 1 tExINTW1 2 tuc Except for STANDBY mode EXINT pulse width 2 texiNTW2 tuc Release from STANDBY mode DREQCLRO DREQCLR1 tpcLRD1 8 10 5 delay 1 ns TCOUTO TCOUT1 delay 1 ttcoutp1 Bite 8 thc 10 5 DREQCLRO DREQCLR1 30 pF tpcLRD2 2 tuc 11 delay 2 TCOUTO TCOUT 1 delay 2 2 2 tuc 11 DREQO DREQ1 hold time tuc 24 16 m SRAM ROM Control signal timing 2 25 to 2 75 3 0 to 3 6V T
33. These bits are reserved for future expansion Bit Descriptions PDCNT 3 0 bits 0 to 3 This number plus one specifies the number of idle cycles to wait before shifting DRAM to power down mode Writes to them are ignored PDCNT Description 3 2 1 0 0 0 0 0 Shift DRAM to power down mode after 1 or more cycles O 0 0 1 Shift DRAM to power down mode after 2 or more cycles 0 0 1 0 Shift DRAM to power down mode after 3 or more cycles 0 0 1 1 Shift DRAM to power down mode after 4 or more cycles 011 0 0 Shift DRAM to power down mode after 5 or more cycles 0 1 0 1 Shift DRAM to power down mode after 6 or more cycles 0 1 1 0 Shift DRAM to power down mode after 7 or more cycles 0 1 1 1 Shift DRAM to power down mode after 8 or more cycles 110 0 0 Shift DRAM to power down mode after 9 or more cycles 11010 71 Shift DRAM to power down mode after 10 or more cycles 110 1 0 Shift DRAM to power down mode after 11 or more cycles 1 0 1 1 Shift DRAM to power down mode after 12 or more cycles 1 1 0 0 Shift DRAM to power down mode after 13 or more cycles 11 1 0 1 Shift DRAM to power down mode after 14 or more cycles 11 1 1 0 Shift DRAM to power down mode after 15 or more cycles 1 1 1 1 Shift DRAM to power down mode after 16 or more cycles 11 24 11 3 11 3 1 1
34. tuc 0 5 24 22 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 24 4 3 Timing Charts B Power Supply On OFF Timing VDD IO ON tvppio_oFF lt AVDD PLL ON taVDD OFF VDD PLL 1 tvDDCORE ON PLL OFF VDD CORE 1 VDD for ML675001 Series only 24 23 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B Clock Timing tc icu tcr tcr 4 gt lt gt 5 0 tspc 7 tspcr 5 lt 9 XSDCLK CKO tuc HCLK tcc CCLK 24 24 B Control Signal Timing ML674001 Series ML675001 Series User s Manual trstw1 trstw2 RESET_N Chapter 24 Electrical Characteristics teriow texintw1 texintw2 EFIQ_N EXINT B DMA Timing DREQO DREQ1 DREQCLRO DREQCLR1 TCOUTO TCOUT1 tpcLRD1 24 25 tpcLRD2 lt ITU ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B External Bus Timing e External ROM RAM Read Cycle Bus Width 16 bit External ROM RAM Byte Half Word Access tcsnR1 tcsu1 4 gt XROMCS N XRAMCS N t
35. AGEN Flash memory only XWE_N WE Figure 11 19 Connecting 2M x 16 Bit ROM 4 MB 11 44 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller ML674001 Series ML675001 Series ROM x8 bits 18 23 21 XA22 XA1 CS OE sis dose WE ROM x8 bits 21 DQ7 DQO CS OE DRIVER E WE FLASH Memory Only Figure 11 20 Connecting Two 4M x 8 Bit ROMs 4 MB 11 45 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 6 2 Connecting SRAM ML674001 Series ML675001 Series SRAM x16 bits 18 23 17 0 XD15 XDO XD15 XD0 DQ15 DQ0 cs OE WE 5 0 LB XBS UB Figure 11 21 Connecting 256K x 16 Bit SRAM 512 KB Using Byte Select Signals 11 46 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller ML674001 Series ML675001 Series SRAM x8 bits 18 23 19 1 PY XD15 XDO 007 200 XRAMCS N CSO XOE N OE XBWE NI1 WE XBWE N 0 SRAM x8 bits A18 A0 DQ7 DQO CS0 OE WE Figure 11 22 Connecting Two 512K x 8 Bit SRAMs 512 KB 11 47 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller ML674001 Series ML675001 Series XA18 23 XA0 XD15 XDO XBWE_N 1 XBWE N 0 Figure 11 23 Connecting 256K x 16 Bit SRAM 512 KB Using Byte Write Enable Signals 11 6 3 Conn
36. MSR 3 Description 0 No change in DCD input 1 Change in DCD input MSR 4 bit 4 Clear to send CTS This bit the inverse of the CTS input from the modem indicates whether the modem is ready to receive data from the serial interface s transmit output SOUT pin In loop back mode MCR 4 717 this bit has the same value as MCR 1 MSR 4 Description 0 Modem is not ready to receive data from SOUT CTS 1 1 Modem is ready to receive data from SOUT CTS 7 0 MSR S5 bit 5 Data set ready DSR This bit the inverse of the DSR input from the modem indicates whether the modem is ready to transmit data to the serial interface s receive circuit In loop back mode MCR 4 1 this bit has the same value as MCR O MSR 5 Description 0 Modem is not ready to transmit data DSR 1 1 Modem is ready to transmit data DSR 0 MSR 6 bit 6 Ring indicator RI This bit is the inverse of the RI input from the modem In loop back mode MCR 4 717 this bit has the same value as MCR 2 MSR 6 Description 0 RI 1 1 RI 0 MSR 7 bit 7 Data carrier detect DCD This bit is the inverse of the DCD input from the modem In loop back mode MCR 4 1 this bit has the same value as MCR 3 MSR T7 Description 0 DCD 1 1 DCD 0 18 19 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte
37. These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions bit 4 This bit controls SIOBTC operation BGRUN Description 0 Stop counter 1 Start counter 17 8 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 2 5 Baud Rate Timer Register SIOBT This register holds the starting value that SIOBTC overflow automatically reloads into the baud rate timer counter SIOBTC register The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIOBT _ _ _ _ _ _ _ _ _ E _ _ _ After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 28 a SIOBT 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8002014 Access R W Access size 32 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored 17 9 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 2 6 SIO test control Register SIOTCN This register is for testing the SIO function The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIOTCN _
38. 1 Input level of pin is high 3 5 ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping 34 Remap Description 3 4 1 Remap Setting The following table shows a mapped device selected by RMPM 3 0 bits of the RMPCON register RSEL bit of the ROMSEL register and BSEL 1 0 pins BSEL T RMPN 3 0 Device in bank 0 MCU RSEL 1 0 3121110 1 0 0x0000 0000 0x03FF FFFF 0 0400 0000 0x07FF FFFF 01 x 0 X Bank 25 External ROM 01 1 X 9 1101010 X X X Bank 26 External SRAM 1101011 X X X Bank 24 External DRAM 2 11011101 X 10 d ML6740010nl ML675001 an reserved only Built in RAM ML6750010nly reserved 11 X X X Built in RAM ML6740010nly reserved ML6750010nly o 0 x x x 0 0 0 Bank 25 Builtin FLASH Bank25 External ROM memory 256K 512Kbyte Max 8Mbyte 0 x x x 1 0 0 Bank25 External ROM Bank25 Built in FLASH Max 8Mbyte memory 256K 512Kbyte 0 x x x 0 0 1 Bank25 External ROM Bank25 Built in FLASH Max 8Mbyte memory 256K 512Kbyte ML67Q4002 0 x x 1 0 1 Bank 25 Built in FLASH Bank 25 External ROM ML67Q4003 memory 256K 512Kbyte Max 8Mbyte ML67Q5002 0 x x x X 1 X Bank9 ML67Q5003 1 X X X Bank 26 External SRAM 1101011 X X X Bank 24 External D
39. 8 4 Notes 1 The program counter contains the address of the instruction triggering the branch software interrupt or undefined instruction exception 2 The program counter contains the address of the instruction superseded by acceptance of the interrupt request 3 The program counter contains the address of the load store instruction triggering the data abort 4 After a reset R14 svc contains an indeterminate value FIQ This exception for supporting a data transfer or channel process provides an abundance of private registers to reduce the need to save registers and thus the context switching overhead The FIQ exception handler must regardless of the original state ARM or THUMB terminate by executing the following instruction SUBS 14 4 Setting the CPSR bit to 1 disables FIQs Note however that this bit is not accessible in User mode IRQ This exception is for normal interrupt requests Such interrupt requests have a lower priority than FIQ so are masked during the FIQ sequence Setting the CPSR I bit to 1 disables IRQs Note however that this bit is only accessible in non user privileged modes The IRQ exception handler must regardless of the original state ARM or THUMB terminate by executing the following instruction SUBS 4 4 2 12 2 12 6 2 12 7 2 12 8 ML674001 Series ML675001 Series User s Manual Chapte
40. Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1514 43 12 1 10 9 8 7 6 5 4 3 2 1 0 5 51 11 51 51 11 1 WPERRMFERR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8002018 Access R W Access size 32 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions MFERR bit 0 Setting this bit to 1 during loopback testing LBTST 1 forces framing errors MFERR Description 0 Skip framing errors 1 Add framing errors MPERR bit 1 Setting this bit to 1 during loopback testing LBTST 1 forces parity errors MPERR Description 0 Skip parity errors 1 Add parity errors e LBTST bit 7 Setting this bit to 1 internally connects the transmitter outputs to the receiver inputs for testing LBTST Description 0 Disable loopback 1 Enable loopback 17 10 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 3 Description of Operation Settings in the SIOCON register specify the frame format character length number of stop bits and parity Figure 17 2 gives the register settings for sample formats 1 8 data bits 1 stop bit parity LN 0 TSTB 1 PEN 1 STRAY DO X D1 X D2 X D3 X D4 X D5 X D6 X 07 STOR START 2 8 d
41. SDP Description 0 Fixed address device The DMA controller always reads from the same address 1 Incremental address device The DMA controller increments the address by the transfer size in bytes after each successful read from the transfer source DDP bit 4 This bit specifies the device type for the transfer destination DDP Description 0 Fixed address device The DMA controller always writes to the same address 1 Incremental address device The DMA controller increments the address by the transfer size in bytes after each successful write to the transfer destination e bit 5 This bit specifies the bus request mode BRQ Description 0 Burst mode The DMA controller does not surrender bus access until the specified number of transfers are complete 1 Cycle stealing mode The DMA controller surrenders bus access after each individual DMA transfer bit 6 This bit specifies the interrupt mask IMK Description 0 Remove mask to enable interrupt requests 1 Mask stop interrupt requests 12 11 ML 674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 6 DMA Transfer Source Address Registers DMACSADO and DMACSAD1 These registers specify the transfer source address for the corresponding DMA channel The DMA controller starts reading data for the DMA transfer from the address in t
42. is read during reading and this bit is ignored during writing Explanation of Bits I2CDAK bit 0 This bit indicates the presence or absence of an acknowledge from the slave device for the data transmitted Once this bit is set to 1 it is not automatically cleared to 0 even if an acknowledge is received normally upon completion of the next transfer Therefore it is necessary to clear it to 0 by a program This bit is automatically cleared to 0 by writing 1 to the I2CIR bit of the I2CIR register 12CDAK Description 0 Normal reception of acknowledge for transmit data 1 Acknowledge error for transmit data I2CAAK bit 1 This bit indicates the presence or absence of an acknowledge from the slave device in response to the broadcasting of its address over the bus Once this bit is set to 1 it is not automatically cleared to 0 even after an acknowledge is received normally upon completion of the next transfer Therefore it is necessary to clear it to 0 by a program This bit is automatically cleared to 0 by writing 1 to the I2CIR bit of the I2CIR register 12CAAK Description 0 Normal reception of acknowledge for slave address 1 Receive error of acknowledge for slave address 20 7 ML674001 Seies ML675001 Series User s Manual Chapter 20 I2C 20 2 5 2C Bus Interrupt Request Register I2CIR The I2CIR register indicates the status of interrupts of the I2C block
43. l Ug co udo d UA armi timidi 51 9 Ae l ll 1 bod gd o e 122174 py ds 5 5415 22 21 1111 11 11 1 arm7tdmi mclk arm7tdmi nrw haddr o 31 0 htrans o 1 0 hburst o 1 0 hwrite o hready o hmaster 2 0 in the figure During a read hit the data is returned to the CPU in one mclk cycle Q in the figure e During a cache hit operation the cache controller does not require the memory access and bus access to the AHB During a write hit the write operation is completed within a maximum of 2 cycles The above example is one in which the succeeding access is a read hit 9 12 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY Example of cache miss operation bclk r 4 4 4 4 4 t 4 4 4 4 PEO AEA mmm Re Pee T s I iom ea m m mon m dm m m pi mm i mm mmm mom em mmm mmm mmm EA S m m 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Set PAEA EPEE a ae ee et ee ee eee be ee 52 2 22 E 2 22 eee ee eh idee eset
44. 18 2 10 Scratch Register UARTSCR This register is for use as temporary data storage It plays no role in ACE transfer operations The CPU has read write access to this register The register contents after a reset are indeterminate 7 6 5 4 3 2 1 UARTSCR SCR 7 0 After a reset Indeterminate Address 0xB7B0001C Access R W Access size 8 bits 18 20 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 11 Divisor Latch LSB UARTDLL This register contains the lower half of the 16 bit divisor latch for the baud rate generator For further details see the section on baud rate clock generation The CPU has read write access to this register when LCR 7 1 The register contents after a reset are indeterminate 7 6 5 4 3 2 1 0 UARTDLL DLL 7 0 DL 7 0 After a reset Indeterminate Address 0 7 00000 Access R W Access size 8 bits 18 21 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 12 Divisor Latch MSB UARTDLM This register contains the upper half of the 16 bit divisor latch for the baud rate generator For further details see the section on baud rate clock generation The CPU has read write access to this register when LCR 7 1 The register contents after a reset are indeterminate 7 6 5 4 3 2 1 0 UARTDLM DLM 7 0 DL 15
45. 37 N1 XA 6 External address output 38 7 External address output 39 L3 XA 8 External address output 40 9 External address output 1 8 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction LQFP Pin Primary Function Secondary Function BGA Symbol Description Symbol Description 41 L4 VDD IO VDD power supply 42 M3 XA 10 External address output 43 XA 11 External address output 44 L5 XA 12 External address output 45 MA XA 13 External address output 46 N5 XA 14 External address output 47 K5 GND GND GND 48 M5 XA 15 External address output 49 N6 XA 16 External address output 50 M6 XA 17 External address output 51 K6 GND GND GND 52 L6 XA 18 External address output 53 M7 PIOC 2 1 0 General port with interrupt function XA 19 O External address output 54 VDD IO VDD power supply 55 L7 PIOC 3 y o General port with interrupt function XA 20 O External address output 56 PIOC 4 y o General port with interrupt function XA 21 O External address output 57 L8
46. ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping The ROMSEL register controls mapping of bank 0 to built in RAM built in FLASH or external memory ROM DRAM SRAM with the RMPCON register described in the previous section after booting is complete 15 14 13 12 11 10 ROMSEL _ _ _ _ _ _ _ _ _ _ 220 _ RSEL BSEL Afterareset 0 0 0 0 0 0 Address 0 700000 Access R W Access size 16 bits Note These bits are for future expansion They return 0 for reads Writes to them are ignored This register features write protection to prevent errant software from accidentally overwriting register contents The program must first write to it immediately before updating its contents The value depends on the input level of BSEL 0 pin Bit Descriptions e RSEL bit 0 This bit remaps bank 0 to a different device after a boot A mapped device is selected by RMPM 3 0 bits RSEL bit and BSEL 1 0 pin For a complete description of RSEL settings and resulting effects refer to the table in Section 3 5 BSELM bit 1 This bit shows the input level of the BSEL 0 pin Writing this bit is ignored The software can use this bit to refer to the address arrangement of the built in FlashROM of bank 25 and external ROM BSELM Description 0 Input level of pin is low
47. 1 XDQMIOJXCAS N 0 XWE N XOE N XD 15 0 RAS A D A Figure 11 12 EDO DRAM Byte LSB Write 11 38 ML674001 Series ML675001 Series User s Manual External Memory Controller Chapter 11 11 4 1 4 SDRAM Access XSDCLK XA 23 0 XSDCS N XRAS N XCAS N XWE N XDQOM 1I XCAS XDQMIOJXCAS N 0 XD 15 0 XSDCLK XA 23 0 XSDCS N XRAS N XCAS N XWE N XDQM 1I XCAS XDQM OJXCAS 0 XD 15 0 ENS ED ON ae ae GUN 52027 Figure 11 13 SDRAM Word Read y 0 13 2 Figure 11 14 SDRAM Word Write 11 39 ML674001 Series ML675001 Series User s Manual Chapter 11 XSDCLK XA 23 0 XSDCS N XRAS N XCAS N XWE N XDQM 1 XCAS_N 1 XDQM 0 XCAS_N 0 XD 15 0 XSDCLK XA 23 0 XSDCS N XRAS N XCAS N XWE N XDQM 1I XCAS 1 XDQMIO XCAS 0 XD 15 0 External Memory Controller fe NEE ONG NY GES ES at Ee Ee gt Figure 11 15 SDRAM Half word Read gt V _ qD Figure 11 16 SDRAM Half word Write 11 40 XSDCLK XA 23 0 XSDCS N XRAS N XCAS N XWE N XDQM 1I XCAS XDQM OVXCAS 0 XD 15 0 XSDCLK XA 23 0 XSDCS N XRAS N XCAS N XWE N XDQM 1I XCAS XDQM OJXCAS 0 XD 15 0 ML674001 Series ML675001 Series User s Manual External Memory Controller
48. 111 8 4 3 1 Read off time is the interval measured from the time when Output Enable OE becomes inactive in one memory cycle to the time it becomes active in the next memory cycle 2 Read off timing is 3 in case of Accessing DMA ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller This table is applied only to ML675001 series RAMTYPE 2 0 Pulse width in clock cycles 0 0 0 1 1 1 1 0 0 1 2 2 2 0 1 0 reserved Operation is not guaranteed for a setting labeled reserved 0 1 5 3 3 1 0 0 2 8 4 5 1 0 2 10 5 6 Operation is not guaranteed for a 1 1 0 reserved 2 labeled 4 1 1 1 2 16 7 9 RAMBRST bit 4 Page Mode is set up RAMBRST Description 0 Page Mode off 1 Page Mode on 1 AMBRST exists only ML675001 series ML 674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 5 External Bank 0 1 Access Control Register 01 This register controls the access timing for I O bank 0 1 The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 IO01AC _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ 23 _ 275 0 _ _ _ _ e E 1 01 2 0
49. 12 8 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 4 Channel Mask Registers DMACMSKO and DMACMSK1 These registers control masking which blocks transfers on the corresponding channel The program has read write access to these registers The contents after a reset are 0x00000001 masking all channels 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMACMSKO to 1 cx zd NC EN Jes de Euri 20 0 aw After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s ode E IX E _ E 26 W _ 225 lt MSK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Address 0x7BE00100 CHO 0x7BE00200 CH1 Access R W Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Bit Descriptions e bit 0 This bit specifies the channel mask MSK Description 0 Remove mask to enable or restart DMA channel operation 1 Mask stop DMA channel operation 12 9 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 5 DMA Transfer Mode Registers DMACTMODO and DMACTMOD1 These registers specify the DMA transfer mode for the corresponding DMA channel request source transfer size device ty
50. 3 Carry out a data read operation for the addresses corresponding to the first 2k bytes among the addresses storing the instruction codes This causes the instruction codes to be locked to be loaded in Way 0 Since the reading is done in units of 16 bytes make sure that the total number of bytes is 2k bytes or less including the data before and after the starting address and the ending address of the data read operation Example When the starting address of data read is 0 4000 000 the address for loading will be 0x4000 0000 4 After the data reading in 3 is completed set 1 and 01 Way 1 in the cache lock control register 5 Carry out a data read operation the addresses corresponding to the remaining instruction codes for the addresses in which the instruction codes are stored This causes the instruction codes to be locked to be loaded in Way 1 Since the reading is done in units of 16 bytes make sure that the total number of bytes is 2k bytes or less including the data before and after the starting address and the ending address of the data read operation Example When the starting address of data read is 0x4000 080 the address for loading will be 0x4000 0800 6 After the data reading in 5 is completed the target instruction codes are locked in Way 0 and Way 1 by setting 0 and 10 in the cache lock control register An example is shown below of the procedure example of l
51. BSEL 1 0 MCU Boot device 1 0 0 X External ROM ML674001 ML675001 1 Boot loading mode 0 0 Built in FLASH ROM 256KB 512KB ML67Q4002 ML67Q4003 0 1 External ROM ML67Q5002 ML67Q5003 1 X Boot loading mode 3 4 3 Notes of Address map The arrangement of the built in Flash ROM and the external ROM in bank 25 varies according to the RSEL bit of the ROMSEL register and the input level of the 0 pin as the following table Table 3 1 address arrangement in bank 25 Bank 25 MCU RSEL BSEL 0 0xC800 0000 0xCBFF FFFF 0xCCO00 0000 0xCFFF FFFF ML674001 X X External ROM Max 16Mbyte ML675001 Built in FLASH ROM 0 0 External ROM Max 8Mbyte 256K 512Kbyte ML67Q4002 Built in FLASH ROM ML67Q4003 1 0 External ROM Max 8Mbyte 256K 512Kbyte ML67Q5002 Built in FLASH ROM ML67Q5003 0 1 External ROM Max 8Mbyte 256K 512Kbyte Built in FLASH ROM 1 1 256K 512Kbyte External ROM Max 8Mbyte 3 7 ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping 3 4 4 Remap Setting Example ML67Q4003 ML67Q5003 ML67Q4003 ML67Q5003 RMPM 3 0 Oxxx RMPM 3 0 Oxxx BSEL 1 0 00 BSEL 1 0 00 RSEL 0 RSEL 1 or or RMPM 3 0 0xxx RMPM 3 0 0xxx BSEL 1 0 01 BSEL 1 0 01 RSEL 1 RSEL 0 Ox07FF_FFF reserved 0 0500 0000 External 8 0 0400 0000 reserved OxO7FF FFFF reserved Built in Flash 512KB 0x0407 FFFF 0x0400
52. ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping 3 3 Register Descriptions 3 3 1 Remap Control Register RMPCON The RMPCON register controls mapping of bank 0 to built in SRAM built in FLASH ROM or external memory ROM DRAM SRAM with the ROMSEL register described in the next section after booting is complete 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RMPCON 5 _ _ _ _ _ _ _ _ _ _ _ _ After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 10 5 0 011 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8000010 Access R W Access size 32 bits Note These bits are for future expansion They return 0 for reads Writes to them are ignored This register features write protection to prevent errant software from accidentally overwriting register contents The program must first write Ox3C to it immediately before updating its contents Bit Descriptions e RMPM 3 0 bits 0 to 3 This bit remaps bank 0 to a different device after a boot A mapped device is selected by RMPM 3 0 bits RSEL bit and BSEL 1 0 pin For a complete description of RMPM 3 0 settings and resulting effects refer to the table in Section 3 5 3 4 3 83 2 ROM Select Register ROMSEL
53. ML674001 Series ML675001 Series User s Manual Chapter 23 JTAG 23 3 3 TAP Controller The TAP controller generates signals that control the operations of the instruction register and data register boundary scan register by a state machine of 16 states The TAP controller s transition states are mainly divided into two paths for the instruction register and for the data register boundary scan register Figure 23 4 shows the TAP controller s state transition diagram this diagram each of the labels enclosed by a frame represents a state name and the number 0 or 1 surrounding each frame indicates the value of the TMS signal when the state makes a transition Each state transition is determined by the value of the TMS signal at the rising edge of the TCK signal In addition the state name ending with DR controls the data register and the state name ending with IR controls the instruction register nTRST 0 1 db Test Logic Reset 0 0 Run Test Idle 1 1 1 Select DR Scan Select IR Scan 0 0 1 Capture DR Capture IR 0 eme 0 1 0 1 0 1 1 0 1 Figure 23 4 Controller State Transition Diagram 23 7 ML674001 Series ML675001 Series User s Manual Chapter 23 JTAG 23 3 4 Instructions The instructions supported by the boundary scan function of this LSI are as follows The INTEST and RUNBIST instructions which are optional instructions in the JTAG standard are not supported
54. etd ttp e e t ete 6 1 6 3 Operational Description hee ber pe t e D Rr i ERE 6 2 Chapter7 Power Management TI OVerVISW ku pa 7 1 7 22 Power Management EUnctions icit reto Qn 7 1 Wid Resister ente 7 3 753 Register 7 4 7 3 1 Block Clock Control Register 7 4 13 2 Clock stop Register CEKSTD tpe tme Gee ebat e 7 7 7 3 3 Clock Gear Control Register 22 2 022220 42 60100000000000000000000 00 0 7 9 7 3 4 Clock Wait Register CK WT 222222224 1 00010000000000000000000000000000000500055000 7 10 7 3 5 Stopping Clock Signals to Functional 7 11 13 6 Glock Gears det Role he das hil dena mera dente edet 7 11 13 89 HALT una amiga edente aba edet tp eat 7 12 13 8 STANDBY Modein aa dida bre tte tire D Re ai sq tte tetra 7 12 7 4 Using Power Management with 7 13 7 4 1 Activating Self Refresh 2 7 13 7 4 2 Deactivating Self Refresh Operation esses nennen eene 7 13 ML674001 Series ML675001 Series User s Manual Table of Contents Chapter8 Interrupt Controller
55. to ch3 0 gt 1 gt 2 gt 3 0 1 ch1 to ch3 ch1 ch2 ch3 1 0 ch2 to ch3 ch2 ch3 1 1 ch3 to ch3 ch3 These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Do not change this setting while the analog to digital converter is in operation Writes only take effect when ADRUN bit 4 is 0 ADRUN bit 4 This bit turns the analog to digital converter operation on and off in scan mode ADRUN Description 0 Stop analog to digital converter 1 Start analog to digital converter 21 3 Note that the ADRUN bit is a control bit It in not a flag bit indicating the current analog to digital converter status converting idle ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter SCNC bit 6 This bit specifies the action to take after one cycle through the specified channels SCNC Description 0 Cycle back to first channel after one cycle through the specified channels analog to digital converter 1 Stop after one cycle through the specified channels analog to digital converter If SCNC is 1 setting INTSN the bit in the ADINT register indicating that the cycle is complete to 0 is sufficient to start the next cycle because the ADRUN bit remains at 1 Note If SCNC is 1 stopping conversion the middle requires simultaneously setting both SCNC an
56. too lt lt I P 1 1 DAT 2 DAI 3 1 4 24 46 XSDCLK CAS before RAS CBR Refresh Operation tsDRASD XRAS N XCAS 1 Self Refresh Operation XSDCLK EU 1 XSDCKE XRAS_N XCAS_N 1 0 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics tspRASD tspcAsp J tsDCKED 5 spRAsD tspcasp tspcasp ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 24 5 Analog to Digital Converter Characteristics m Analog to Digital Converter Characteristics 2 50V 3 3V 250 Item Symbol Conditions Minimum Typical Maximum Unit Resolution n 10 bit Linearity error EL t3 Differential linearity error Ep 2 3 LSB Zero scale error Ezs Ri lt 1kO 3 Full scale error Ers 3 Conversion time 5 HS Throughput 10 200 kHz Notes VDD io and AVDD should be supplied separately B Definition of Terms 1 2 3 4 5 Resolution Minimum input analog value recognized For 10 bit resolution this is VREF Aground 1024 Linearity error Difference between the theoretical and actual co
57. 0 06404 0116 0 07994 2000 0753 0 00000 0407 0 02425 0271 0 00000 OOFA 0 00000 2400 061A 0 03200 035 0 04366 0209 0 03199 0000 0 16026 3600 0412 0 03200 0230 0 01454 0158 0 06404 0088 0 07994 4800 0300 0 03200 O1AE 0 07267 0104 0 16026 0068 0 16026 7200 0209 0 03200 011 0 16026 OOAE 0 22340 0045 0 64412 9600 0187 0 09600 0007 0 07267 0082 0 16026 0034 0 16026 19200 00C3 0 16000 0068 0 39428 0041 0 16026 001A 0 16026 38400 0062 0 35200 0036 0 53530 0021 1 35732 0000 0 16026 56000 0043 0 05333 0025 0 45849 0016 1 46104 0009 0 79365 115200 0021 1 37600 0012 0 53530 0008 1 35732 Note for the notation of CCLK 60MHZ only in the case of ML675001 series 18 26 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 3 4 Buffered Operation Received Data Available Interrupts Enabling both the receive queue and receive interrupts produces a received data available interrupt when the number of characters in the queue exceeds the specified trigger level The hardware immediately clears this interrupt when the number of characters in the queue falls back to this trigger level The received data available bit in IIR is similar in operation It goes to 1 when the number of characters in the queue exceeds the specified trigger level and returns to 0 when the num
58. 1 5 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 Pins 1 3 1 Pin Layout 1 3 1 1 LFBGA 13 12 11 xiocs _ PIOCI4 N xe wor XEAN xana 6 M _ ye poce NI2 N 0 E XWR 23 17 15 13 10 4 5 L REDE PIOB 2 0 XROMC _ PIOCISY PIOCISY kis ol GND Rio DREOI DREQU S XA 20 18 8 2 PIOB 3 PIOBIS VES 10 GND VbD IO GND XA xato XD 13 xan LR 1 PIOBIAJ PIOCH J PwMou TCoUTI PWMOU VDD 10 15 XD 14 T 0 0 5 N PIOD OJ VDD C VDD C H 7 i C PIoD 2y PIOD 1 144pin LFBGA NC G VDD 1 GND IO CLKMD1 xDI9 XRAS TOP VIEW PIOD 5 PIODIA 8 PIOE B EXINT 2 EXINT 3 EXINT O NC 0 PIOE 6 PIOE 9 PIOE 2 PON so EXINTH N spo 0801 AINI0 VREFN VDD 10 GND VDD IO 1 1 VDD C 5 BELTS PIoA oy REF PIOA S PIOA 7 PIOE 4J 7 GND AGND GND pan a 280 NC BOU
59. 16 3 Description of Operation ieget eme ode pes E e a RED e DE DRE ERE 16 8 16 31 oco rte p ee oe pee e p PEE RR ERE eat 16 8 16 3 2 Timing 16 8 Chapter 17 SIO IF MES UID SH C 17 1 LAETI Components ge RR eer de e de ire 17 1 177152 pea 17 2 17253 Control Register e eer ERR e E I A Ee EE Se Pte te ie P ERE den 17 2 17 2 Control Register 6 i ere n eI bep IE RD ee bee EP abies 17 3 17 2 1 Transfer Buffer Register 4222 000000 00000000000000000000000000000000000 17 3 17 2 2 SIO Status Register SIOSTA 17 4 17 2 3 SIO Control Register SIOG QNIN suite q entere E e ete ente rd eee p vede pue ee od 17 6 17 2 4 Baud Rate Control Register 1 entente en nnne 17 8 17 2 5 Baud Rate Timer Register SIOBT eene nennen trennen rre 17 9 17 2 6 SIO test control Register nennen enne enne tnter 17 10 17 3 Description OF Operatiott e iti e eie t ee md 17 11 17 92 Transmitting Data nonne e te UR Ho ERE 17 11 17 3 2 Receiving Data eee ee mn e ie Pret Ree Ree bir entres 17 11 17 33 Generating Baud Rat
60. 3 and 3 WRITE ACCESS XIOCS N O XIOCS N 1 access time 2 external I O 0 1 2 txiocsw2 TM SUD AEN and 3 WRITE ACCESS 3 3 24 10 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics IO 0 IO 1 10 2 10 continued external 0 1 2 and 3 Item Symbol nel Minimum Typical Maximum Unit Notes 2 2 txiowELHD nio4 tuc 2 nio4 tuc 1 2 2 1 5 1 5 XBWE N 1 0 hold time Paton CL 4 05 external 0 1 2 and 3 30 pF XBS N 1 0 delay _4 2 external 0 1 2 and 3 XBS N 1 0 output hold time 229 external 0 1 2 and 3 XA 23 0 dela du and 3 239 ES XA 23 0 output hold time 1 0 external 0 1 2 and 3 XA 23 0 output hold time 2 2 ES 2 t external 0 1 2 and 3 XD 15 0 input setup time TENE 20 2 m external 0 1 2 and 3 XD 15 0 input hold time cs 0 _ external 0 1 2 and 3 uae pos 3 tuc 5 tuc 2 XD 15 0 output Enable time T _ EN external 0 1 2 and 3 XD 15 0 output Disable time CL 6 external 0 1 2 and 3 30 pF XD 15 0 output hold time E 3 external 0 1 2 and 3 XIOCS N
61. BC L u 8 1 S l Components ien recedet oe ri td ite e e pi i edet pte 8 2 8 12 s una M 8 3 82 3 Register 88 52 PELLE 8 3 8 2 Interrupt SOULCES eee t C Ee e ere pt pite rte REX e e be ERR een 8 4 6 241 External Fast Interr pt BEIQ ND suci eret ete 8 4 8 22 External Interrupts EXINT n i ier rre eee ee tnr EXPE RR RR ERE ERR 8 4 8 2 3 Internal Interrupts ARQON 2 FE ter RR 8 4 82 4 Interr pt Source Last 5 ua su eme ete E D p e ea 8 5 8 3 Interrupt hee iere eee BRE POPE Oe emer eie Re 8 6 84 8 7 8 4 1 IRQ Register Road al n Rasa alate ie etate ad avin 8 7 8 4 2 Software Interrupt Register IRQS nn nnne 8 8 8 4 3 FIQ Register uident iere Heec n pee e e bete eer re Poen 8 9 844 Register 8 10 8 4 5 Enable Register FIQEN 2 2 0020 4000000000000000000000000000000000000000000000000000000000000 8 11 8 4 6 IRQ Number Register 2 1 40 20040000000000000000000000000000000000000000 8 12 8 4 7 Current Interrupt Level Register CIL eese nete rennen
62. GPPMD 7 0 Description 9 0 0 Input 1 Output ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 2 4 Port Interrupt Enable Registers GPIEA GPIEB GPIEC GPIED GPIEE GPIEA GPIEB GPIEC GPIED GPIEE These registers enable or disable the interrupt detection for the corresponding GPIO pins interrupt function only works if the particular PIO pin is configured as input GPPMx register This interrupt detection requires that the desired trigger edge polarity be specified in the GPIPx register There are no such interrupt requests for pins configured for output If configured as output the interface ignores the corresponding bits in these registers The CPU has read write access to these registers register contents after a reset are 0x0000 GPIEA 7 0 GPIEB 7 0 GPIEC 7 0 GPIED 7 0 GPIEE 9 0 GPPEE uses bit9 amp bit8 For other GPPEx bit9 amp bit8 are Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7A0100C GPIEA 0xB7A0102C GPIEB 0xB7A0104C GPIEC 0xB7A0106C GPIED 0xB7A0108C GPIEE Access R W Access size 16 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored pin input restarts the clock releasing the LSI from STANDBY mode if the pin is configured for input and interrupts are enabled The outside source must however mainta
63. ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 3 3 Banks Control 1 access I O Banks set the I O Banks bus width to 8 16 bits in the BWC register 2 Specify the XOE N XWE N pulse width in the IO01AC or IO23ACX IO23ACY register O23ACX is for ML674001 series only IO23ACY is for ML675001 series only XWR Indicates the direction of data transfer on XD Data Bus for I O Banks Low read from the external I O device to the chip High write from the chip to the external device n the ML675001 series XWR is available for only I O 0 1 XWAIT For I O Bank 0 1 2 3 XWAIT input is for extending the I O device access time XWAIT is sampled one system clock before XOE N XWE N is de asserted If XWAIT is at high level at sampling time the XOE N XWE N pulse width will be extended for additional time based on parameters specified in IO01AC IO23ACX IO23ACY register When XWAIT is at low level at sampling time XOE N XWE N pulse width is not extended An example is shown below when OE WE pulse width is set as 8 clocks in the IOO1AC register No extension XOW N XWE N pulse width by XWAIT 1 8 hclk XWE_N XA 23 0 lt Valid XIOCS_N O XD 15 0 4 lt XWAIT X
64. TEST Test mode Positive TEST1 Test mode ML675001Series only Positive FWR Test mode Positive JSEL JTAG select signal L onboard debug H boundary scan Power supplies VDD CORE Core power supply VDD IO power supply GND GND for core and I O PLLVDD PLL power supply ML675001Series Only PLLGND PLL power supply ML675001Series Only ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 4 Pin States Table 1 1 summarizes the output states for output and I O pins during a reset Table 1 2 for STANDBY mode Table 1 1 Output States During Reset Pin Name Reset with DRAM controller Reset with DRAM controller disabled enabled PIOA 7 0 High impedance High impedance PIOB 7 0 High impedance High impedance PIOC 7 0 High impedance High impedance PIOD 7 XDQM 0J XCAS_N 0 High impedance High level PIOD 6 XDQM 1 XCAS_N 1 High impedance High level PIOD 5 XSDCKE High impedance High level PIOD 4 XSDCS_N High impedance High level PIOD 3 XSDCLKk High impedance Low level PIOD 2 XRAS_N High impedance High level PIOD 1 XCAS_N High impedance High level PIOD 0 XWAIT High impedance High impedance PIOE 9 0 High impedance High impedance XD 15 0 High impedance High impedance XA 18 0 Low level Low level XOE N High level High level
65. These bits specifiy the slave address of the communication destination 20 5 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 20 2 3 12C Bus Transfer Speed Register I2CCLR The I2CCLR register sets the communication speed mode of the I2C bus The data in this register can be read and written by programs The value at the time of reset is 0x00 Always set the IDCCLR register before setting the I2CCON register 7 6 5 4 3 2 1 0 I2CCLR I2CMD At reset 0 0 0 0 0 0 0 0 Address OxB7800008 Access R W Access size 8 bits Note This is a reserved bit for future expansion In this LSI 0 is read during reading and this bit is ignored during writing Explanation of Bits e 2CMD bits 0 This bit selects Standard mode or Fast mode 12CMD Description 0 Selects Standard mode 100 kHz 1 Selects Fast mode 400 kHz 20 6 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 2 4 2C Bus Status Register I2CSR The I2CSR register indicates the status of the I2C bus The data in this register can only be read by a program value at the time of reset is 0 00 7 6 5 4 3 2 1 0 I2CSR 12 I2CDAK At reset 0 0 0 0 0 0 0 0 Address 0 780000 Access DR Access size 8 bits Note This is a reserved bit for future expansion In this LSI
66. 16 7 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator 16 3 16 3 1 16 3 2 Description of Operation PWM Operation This block provides two output pins PWMOUTO and PWMOUTI To start PWM output write 1 to PWxR which will in turn start the counter PWCx and set the output flip flop automatically to 1 to drive the PWMOUTx pin output at High level When the PWCx contents match those of PWRx the output flip flop switches to 0 to drive the PWMOUTKx pin output at Low level If INTIEx is 1 PWCxOV is 0 an interrupt request will signal this transition The hardware repeats the above two steps producing PWMOUTNX pin output whose duty is under program control until the program resets PWxR to 0 Notes Depending the operating clock selected the PWM output duty is sometimes less than specified for the first cycle immediately after starting output Setting both PWCx PWRx to 0x0000 produces an output duty High level pulse width of 1 65536 Increasing PWRx increases the output duty The maximum value OxFFFF produces an output duty of 65536 65536 or 100 The PWM generator cannot produce 0 65536 0 duty Timing Examples Figure 16 2 summarizes basic output operation Figure 16 3 shows the results of changing PWM output timing Notes Write to PVC PWCY PWR under PWM stop state Next PWM interrupt will be merged if the interrupt occurs
67. 322 58 645 16 806 45 1064 52 129 03 161 29 322 58 403 23 532 26 64 52 80 65 161 29 201 61 266 13 51 28 64 10 128 21 160 26 211 54 32 13 40 16 80 32 100 40 132 53 25 64 32 05 64 10 80 13 105 77 20 51 25 64 51 28 64 10 84 62 15 53 19 42 38 83 48 54 64 08 12 82 16 03 32 05 40 06 52 88 10 26 12 82 25 64 32 05 42 31 8 54 10 67 21 34 26 68 35 22 7 77 9 71 19 42 24 27 32 04 4 27 5 34 10 67 13 34 17 61 The shading indicates recommended settings Note The user application system must modify the contents of this register each time that it changes the CCLK frequency with the clock gear 11 23 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 14 DRAM Power Down Control Register RDWC This register specifies the number of idle cycles to wait before shifting DRAM to power down mode The program has only write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ _ _ _ _ _ _ _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ E _ ore _ 225 225 PDCNT 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Address 0x78180018 Access w Access size 32 bits Note
68. C800 0000 External ROM 000 0000 External DRAM B800 0000 Core I O 000 0000 Standard 800 0000 000 0000 esames 9800 0000 reserved 9000 0000 reserved 8800 0000 reserved 8000 0000 eserves C00 0000 1 1 reserved 7830 0000 AHB standard IO 7800 0000 uPlatCore O 7000 0000 eee 6800 0000 reserved 6000 0000 5800 0000 reserved 5000 0000 reserved 4800 0000 reserved 4000 0000 emel 3800 0000 reserved reserved Internal RAM mirror of bank 2 External SRAM mirror of bank 26 3000 0000 2800 0000 2000 0000 reserved Internal RAM 1800 0000 1000 0000 reserved Remappable ROM RAM AHB Ext 0800 0000 0000 0000 F8UU_UUUU External I O External 2 External 1 External 0 F400_0000 F200_0000 FUUU 0000 DUUU UUUU External ROM MCP Flash ROM refer to table 00 0000 2 MCP Flash ROM External ROM refer to table UUUU C000 0000 8800 2020 B800 2000 B800 1020 B800 1000 B800 0020 B800 0000 B800 0000 7 0000 B7EO 0000 700 0000 PWMcocontroregister n B7BO 1000 B7BO 0000 7 1000 B780 1000 B780 0000 B710 0000 reserved B700 0000 Chip configuration control register B600 2000 B600 1000 Analog to digital converter control register 000 0000 reserved 8000 0000 7 00 0000 0000 Expansion interrupt cont
69. N polling can be used to detect the end of an erase or program cycle During an erase cycle 0 is read into DQ7 and upon completion of the erase cycle 1 is read into DQ7 During a program cycle an inverted value of the data loaded last is read into DQ7 and upon completion of the program cycle the value of data loaded last is read into DQ7 DATA polling can be monitored any time during an erase or program cycle It is recommended to verify the detection by DATA N polling twice continuously in order to avoid erroneous detections Note that in order to make DATA N polling function correctly it is necessary to erase the existing program first before programming The following shows the flowchart for detecting the end of a program cycle by using DATA N polling Start program cycle Read DQ7 from selected block sector or chip Is DQ7 write data End program cycle Note For 007 see Figure 22 1 22 12 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 2 Toggle Bit The toggle bit can be used to detect the end of an erase or program cycle During an erase or program cycle 0 and 1 are continuously read out from DQ6 alternately When an erase or program cycle finishes toggling stops and the cycle returns to the normal read cycle The toggle bit can be monitored any time during an erase or program cycle It is recommended to verify the detection by the toggle bit t
70. PWM counter 0 PWCO R W 16 0x0000 16 5 0xB7D0000C PWM control register 0 PWCONO R W 16 0x0000 16 6 0xB7D00020 PWM register 1 PWR1 R W 16 0x0000 16 3 0 7000024 PWM period register 1 PWCY1 R W 16 0 0000 16 4 0xB7D00028 PWM counter 1 PWC1 R W 16 0x0000 16 5 0xB7D0002C PWM control register 1 PWCON1 R W 16 0x0000 16 6 0xB7D0003C PWM Interrupt status register PWINTSTS R W 16 0x0000 16 7 0 7 00000 Watchdog timer control register WDTCON 8 14 2 0 7 00004 Time base counter control register WDTBCON R W 8 0x00 14 3 0xB7E00014 Status register WDSTAT R W 8 0x00 14 5 OxB7F00000 Timer 0 control register TIMECNTLO R W 16 0x0000 15 7 OxB7F00004 Timer 0 base register TIMEBASEO R W 16 0 0000 15 9 0 7 00008 Timer 0 counter register TIMECNTO R 16 0x0000 15 10 0 7 0000 Timer 0 compare register TIMECMPO R W 16 OxFFFF 15 11 OxB7F00010 Timer 0 status register TIMESTATO R W 16 0 0000 15 12 OxB7F00020 Timer 1 control register TIMECNTL1 R W 16 0 0000 15 7 OxB7F00024 Timer 1 base register TIMEBASE1 R W 16 0 0000 15 9 OxB7F00028 Timer 1 counter register TIMECNT 1 R 16 0x0000 15 10 OxB7F0002C Timer 1 compare register TIMECMP1 R W 16 OxFFFF 15 11 OxB7F00030 Timer 1 status register TIMESTAT1 R W 16 0 0000 15 12 OxB7F00040 Timer 2 control register TIMECNTL2 R W 16 0 0000 15 7 OxB7F00044 Timer 2 base register TIMEBASE2 R W 16 0 0000 15 9 OxB7F000
71. Valid gt i Low level Extension XOE_N XWE_N pulse width by XWAIT 1 8 1 8 hclk 1 1 XOE N XWE_N 1 1 1 1 T T Valid XA 23 0 23 0 XIOCS N 0 XD 15 0 lt Valid 2 High level 1 Y XWAIT 7 N Low level 11 26 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 3 4 DRAM Control DRAM Controller disable by DRAME_N pin For the DRAM controller to be operational the DRAME_N Pin of the MCU should be configured so as to enable the DRAM controller The DRAME_N Pin configuration is described in Chapter 4 Chip Configuration of this manual When the DRAME N Pin of the MCU is configured so as to disable the DRAM controller the DRAM controller registers will become inaccessible as well DRAM initialization by software DRAM must be initialized when the power is first applied with a sequence similar to the following 1 Wait at least 200 us after the end of the reset sequence before enabling DRAM access by writing a nonzero bus width to the DBWC register This interval is actually only necessary when the power is first applied but taking this approach simplifies the program Specify the DRAM access timing parameters in
72. and storage of 8 bit data transmitted from the slave device into the I2CDR register Also when the I2COC bit bit 1 of the 2 register is set to 0 a negative acknowledge for received data as well as the stop sequence are successively transmitted the bus is released and communication is then finished At this point the I2CIR bit is set to 1 indicating that the reception of 1 byte of data has been finished data received can be retrieved by reading the I2CDR register If an acknowledge for the address transmitted has not been returned normally the 2 bit is set to 1 upon completion of reception if BOB B K P Output Input Start Stop Restart Acknowledge Negative Acknowledge Negative sequence sequence sequence received acknowledge transmitted acknowledge received transmitted 12 5 I2CD sBBBIBIBBB AP BBBBB BAp 716 5 41312 1 7 5 3 2 110 jouw I2CIR 1 R B 4 12 0 Reception complete Register I2CSAD 10 settings I2CCON xxx0x100b Flag 20 13 ML674001 Seies ML675001 Series User s Manual Chapter 20 I2C 20 3 3 Transmit operation transfer of 2 or more bytes from master to slave in 7 bit address mode Repeat step from section 20 3 1 Repeat step
73. bit 7 This bit controls watchdog timer interval timer operation WDHLT Description 0 Start Enable 1 Stop 14 4 ML674001 Series ML675001 Series User s Manual Chapter 14 Watchdog Timer WDT 14 2 3 Status Register WDSTAT This register gives the status of the watchdog timer interrupt and system reset requests The CPU has read write access to this register The register contents after a reset are 0 00 7 6 5 4 3 2 1 0 RST WDSTAT IVTIIST WDTIST STATUS After a 0 0 0 0 0 0 0 0 Address 0xB7E00014 Access R W Access size 8 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions e RSTSTATUS bit 0 This bit gives the reset source Once this bit goes to 1 it does not return to 0 until there is RESET_N input RSTSTATUS Description 0 Power on reset 1 Watchdog timer reset WDTIST bit 4 A 1 in this bit indicates an interrupt request from the watchdog timer Writing 1 to this bit resets it to 0 Note Failure to clear this bit after a interrupt reset request produces a series of such requests Clearing this bit requires up to 20 HCLK cycles 1 so always wait at least 20 HCLK cycles 1 before clearing the interrupt controller 1 40HCLK cycles for ML675001 series WDTST Description 0
74. from section 20 3 1 The I2CCON register is set to 110 The following series of operations is automatically performed when the STCM bit bit 2 of the register is set to 1 Transmission of the start sequence transmission of the slave address and the transfer direction specified to the I2CSAD register confirmation of an acknowledge from the slave device for the address transmitted transmission of the transmit data specified to the I2CDR register and confirmation of an acknowledge from the slave device for the data transmitted Here because the I2COC bit bit 1 of the IZCCON register is set to 1 the stop sequence will not be transmitted the bus remains busy and the command wait state is activated At this point the I2CIR bit is set to 1 indicating that the transmission of 1 of data has been finished If acknowledges for the address and data transmitted have not been returned normally both the I2CAAK and I2CDAK bits are set to upon completion of transmission At this stage the application program must monitor I2CAAK and I2CDAK bits for proper error handling and recovery from I2C bus errors Also the application program should reset the I2CIR bit as necessary Multiple bytes are transmitted by repeating from step O to the required number of times To transmit the last byte after multiple bytes have been transmitted step G at the time of 1 byte transmit operation is performed first Next the
75. lt 23 0 A1 A2 txiossp txioss txioBsH lt XBS_N 1 0 bxiooED bxooEWEW bxiooE WEW XOE bxoWRD bxiowRH lt XWR taops lt gt XD 15 0 D1 D2 24 34 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e External 0 1 2 3 Write Cycle Bus Width 16 bit External I O 0 1 2 3 Word Access Bus Width 8 bit External 0 1 2 3 Half Word Access P txiocsw1 buocewo bxiocsH XIOCS 2 XIOCS N 1 XIOCS N 2 XIOCS txioxaH2 txioxaH2 lt o XA 23 0 A1 A2 bxioBsp bxioBsH XBS_N 1 0 AL txiowED txiooEwEw txiooEwEw XWE N XIOWELHD txiowELHH XIOWELHH XBWE N 1 0 txiowrD txIOwRH XWR txiopop txiopop bxopopE 24 35 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e XWAIT Signal Input Timing XWAIT sampling timing XIOWAITD1 1 XIOCS_NI0 1 XOE N 1 L bxowATS gt I XWAIT e XWAIT Signal Input Timing XWAIT sampling timing txiowAITD2 1 XIOCS N 0 N txiowAITS txiowArTH XWAIT
76. of the bus clock 17 1 1 Components Figure 17 1 is a block diagram showing asynchronous serial interface components Wite 11 control signals to Function registers registers Receiver bus signals SIOBUF APB bus interface SIOSTA SIOCON Receive shift clock Register settings SIOBCN SIOBT SIOTCN Baud rate clock Sioint n Transmitter sio apb pclk synchronization Transmit shift clock Baud clock Baud rate clkstp sio generator Reset HALT Baud rate clock hresetn control SIOBTC sio sys sio br clk sio br synchronization Figure 17 1 Block Components 17 1 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 1 2 Pin List Pin Name 1 0 Description STXD O SIO transmitter output Secondary function for PIOB 6 SRXD SIO receiver input Secondary function for PIOB 7 17 1 3 Control Register List Address Name Abbreviation R W Size Initial Value 0xB8002000 SIO transfer buffer register SIOBUF R W 32 0x00000000 0xB8002004 SIO status register SIOSTA R W 32 0x00000000 0xB8002008 SIO control register SIOCON R W 32 0x00000000 0xB800200C Baud rate control register SIOBCN R W 32 0x00000000 0xB8002010 reserved 32 0x00000000 0xB8002014 Baud rate timer register SIOBT R W 32 0x00000000 0xB8002018 SIO test contro
77. of the memory space that is the target of caching the cacheable memory area Description of operations e Cache hit operation Read hit Data is returned from the cache memory to the CPU when there is a cache hit of the read access from the CPU Write hit Data is written into the cache memory when there is a write access from the CPU e Cache miss operation Read miss When there is a cache miss of the read access from the CPU the cache controller carries out an AHB bus access to read out one block 16 bytes of data from the main memory and stores that data in the cache memory and also returns that data to the CPU Write miss When there is a cache miss of the write operation from the CPU the cache controller carries out an AHB bus access to read out one block 16 bytes of data from the main memory and stores it in the cache memory and also stores the write data from the CPU e Replacement operation When there is no free space for storing within the cache memory in the case of a cache miss one block 16 bytes of the data storage area that has not been used recently will be over written by the newly required data If the data that is over written has been updated the cache memory controller carries out first a write back operation to free the storage area and then carries out the above cache miss operation This type of operation is called a replacement operation Non cacheable access operation When an access is made to an addr
78. 0 7 00000 Transmitter Holding Register UARTTHR 8 Indeterminate 18 5 0xB7B00004 Divisor Latch MSB UARTDLM R W 8 Indeterminate 18 22 0 7 00004 Interrupt Enable Register UARTIER R W 8 0x00 18 6 0xB7B00008 FIFO Control Register UARTFCR 8 0x00 18 9 0 7 00008 Interrupt Identification Register UARTIIR R 8 0x01 18 7 0xB7BO0000C Line Control Register UARTLCR R W 8 0x00 18 11 0xB7B00010 Modem Control Register UARTMCR R W 8 0x00 18 13 0xB7B00014 Line Status Register UARTLSR R W 8 0x60 18 15 0xB7B00018 Modem Status Register UARTMSR Be on pin states 0xB7B0001C Scratch Register UARTSCR R W 8 Indeterminate 18 20 A 3 ML674001 Series ML675001 Series User s Manual Appendixes Address Name Abbreviation R W Size Initial Value Ref Pages 0xB7B01000 transmitreceive SSIOBUF Rw 8 19 3 0xB7B01004 Synchronous SIO status register SSIOST R W 8 0x00 19 3 0xB7B01008 SSIOINT RW 8 19 4 0xB7B0100C SSIOINTEN 8 0 00 19 5 0xB7B01010 2 transmitreceiye SSIOCON 8 19 6 0xB7B01014 Synchronous SIO test control register SSIOTSCON R W 8 0x00 19 7 0xB7D00000 PWM register O PWRO R W 16 0x0000 16 3 0xB7D00004 PWM period register O PWCYO R W 16 0x0000 16 4 0xB7D00008
79. 0 6 5 4 3 42 gt 9 I2CIR 1 I2CIR 1 Flag 1 4 IBCDAK 0 I2CAAK 0 Transmission complete 4 Register I2CSAD 00000001b I2CSAD xxxxxxx0b 12 xxx1x110b I2CDR xxxxxxxxb settings I2CCON xxx0x101b 20 17 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 3 E B 8 BH Output Input Start Stop Restart Acknowledge Negative Acknowledge Negative sequence sequence sequence received acknowledge transmitted acknowledge received transmitted I2CDR I2CDR 7 6 5 4 3 21 ou Arslan I2CIR 1 A I2CIR 1 1 I2CAAK 1 I2CDR 1 I2CDR 1 IBCDR 1 1 byte Transmission 1 byte transmission complete transmission finishes finishes A Waits for waits for I2CCON setting 2 setting I2CDR I2CDR xxxxxxxxb I2CCON 1 106 I2CCON xxx0x100b 20 18 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 3 8 7 bit Address Mode and 10 bit Address Mode There are two types of slave add
80. 1 0018 1 low priority 0 0 0 Interrupts masked 8 16 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller The following Table summarizes the mappings of nIRO to nIR7 to the fields in this register nIR 8 ILR8 ILC1 2 0 nIR 9 ILR9 ILC1 6 4 nIR 10 ILR10 ILC1 10 8 nIR 11 ILR11 ILC1 14 12 nIR 12 ILR12 ILC1 18 16 nIR 13 ILR13 ILC1 22 20 nIR 14 ILR14 ILC1 26 24 nIR 15 ILR15 ILC1 30 28 8 17 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 10 Current Interrupt Level Clear Register Writing to this register clears the highest 1 bit in the current interrupt level CIL register indicating to the interrupt controller s priority judgment circuitry that processing of the current interrupt is complete The data written does not matter The CPU has only write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CILCL don t care 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 don t care L L J l L L L 1 1 1 1 1 1 1 Address 0x78000028 Access Access size 32 bits Note An interrupt handler before returning must reset the highest 1 bit in CIL to 0 either by writing to this register or by writing 1 to the corresponding CIL bit 8 18 ML674001 Series ML675001 Series User s
81. 1 1 1 1 Address 0 7 0000 CHO 0xB7F0002C CH1 0xB7F0004C CH2 OxB7F0006C CH3 0xB7F0008C CH4 OxB7FOOOAC CH5 Access R W Access size 16 bits 15 11 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 8 Timer Status Registers TIMESTATO to TIMESTATS The STATUS bit in this register goes to 1 to indicate a match between the counter and compare registers The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMESTATO to 5 _ STATUS Address 0xB7F00010 CHO OxB7F00030 CH1 0xB7F00050 2 7 200070 CH3 0xB7F00090 CH4 7 000 0 CH5 Access R W Access size 16 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions e STATUS bit 0 This bit goes to 17 to indicate a match between the counter and compare registers Writing 1 to this bit resets it to 0 Writes of 0 are ignored STATUS Description 0 No match 1 Match 15 12 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 3 Description of Operation 15 3 1 System Timer 1 Reload timer operation The System Timer operates independently from the six Auto Reload Timers The three re
82. 24 2 24 3 Blectrical CharacteristiCs rene ott fe he ee thee e ee eee fae ie opta 24 3 24 3 1 DC Characteristics for ML674001 Series 24 3 24 3 2 DC Characteristics for ML675001 ener trennen enne nennen nre 24 4 24 4 AC Characteristics ceguera eed be i aee do tite ale edge pedes tue ape tefie ee eden 24 5 2441 Characteristics for ML674001 24 5 244 2 Characteristics for ML675001 Sertes nee nennen entren 24 14 244 3 Charts oor rrt teet eoe e Rb dote et e eds 24 23 24 5 Analog to Digital Converter Characteristics 24 48 Appendixes Appendix A gt Register LISttu u ree Dee A 1 Appendix DImensIOns eee toD e Hebe lee Eel nete e EB e A 6 Revision History Revision HIStory eid UR eio ata AU ayqi ta Aa e R 1 Chapter 1 Introduction ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Chapter 1 Introduction 1 1 Features This high performance CMOS 32 bit micro controller combines the 32 bit ARM7TDMI core a RISC CPU developed by Advanced RISC Machines Limited ARM with a DMA controller serial ports PWM generator analog to digital converter 16 bit timers and other peripheral functions on a single LSI In addition to 32
83. 24 36 SDRAM Control Signal Timing SDRAM Read Cycle Bus Width 16 bit SDRAM Byte Half Word Access ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics XSDCLK tspxap lt XA 15 0 RA1 CA1 SDCSD SDCSD socsp socsp XSDCS_N tspRas tsprasp _ XRAS N teDRCD tspcasp tspcasp XCAS N XWE N tsppavp 5 5 0 0 XSDCKE tspxpis tepxpiH XD 15 0 D1 1 24 37 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics SDRAM Write Cycle Bus Width 16 bit SDRAM Byte Half Word Access XSDCLK TE XA 15 0 RMI tspcsp tspcsp tspcsp tspcsp tspcsp tspcsp 4 gt 4 XSDCS N tspRas tspRP tspRASD tspRAsD lspRASD tsoRAsD gt XRAS N 5 tspcasp XCAS_N tspwep 6 XWE_N tsppamp 5 gt gt XDOM 1 XSDCKE tspxpop gt tspxpoE XD 15 0 D1 1 24 38 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics SDRAM Read Cycle Bus Width 16 bit SDRAM Word Access
84. 33 MHz 19200 16 MHz to 60 MHz 38400 33 MHz 38400 33 MHz to 60 MHz 22 7 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 22 4 SDP Command Sequence Control for Built In Flash Memory 22 4 1 Operational Description Built in flash memory is equipped with a command register to facilitate interface and control Read erase program and other functions required for built in flash memory are executed via the command register Commands are written into the command register by the SDP Software Data Protect command sequence employing standard commands command list and the functional descriptions of the commands shown below Command Sequence List Req 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle Command cycle Address Data Address Data 5 Data Data Address Data Address Data Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note 2 Note 1 Note2 Note 1 Note2 1 XXX FO Read Reset C ee RA RD 3 555 2 55 555 FO Noted Gs d Software ID Entry Verify 3 555 AA 2 55 555 90 RD Protect ii M Word PA PD Program 4 555 AA 2AA 55 555 0 Mice d 6 555 2AA 55 555 80 555 2AA 55 SA rase Note 3 Block Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 E 50 Chip Erase 6 555 AA
85. 4 0xB7800008 I2C bus transfer speed register I2CCLR R W 8 0x00 20 5 0xB780000C I2C bus status register I2CSR R 8 0x00 20 6 0xB7800010 12 bus interrupt request register I2CIR RAW 8 0x00 20 7 0xB7800014 12 bus interrupt mask register I2CIMR R W 8 0x01 20 7 0xB7800018 I2C bus transmit receive data register I2CDR R W 8 0x00 20 8 0xB780001C 12 bus transfer speed counter 2 R W 8 0x00 20 8 0xB7A01000 Port A output register GPPOA R W 16 Indeterminate 13 5 0xB7A01004 Port A input register GPPIA R 16 2 PM 13 5 A 2 ML674001 Series ML675001 Series User s Manual Appendixes Address Name Abbreviation R W Size Initial Value 9 Pages 0xB7A01008 Port A mode register GPPMA R W 16 0 0000 13 6 0 7 0100 Port A interrupt enable register GPIEA R W 16 0 0000 13 7 0xB7A01010 Port A interrupt polarity register GPIPA R W 16 0x0000 13 8 0xB7A01014 Port A interrupt status register GPISA R W 16 0 0000 13 9 0xB7A01020 Port B output register GPPOB R W 16 Indeterminate 13 5 0xB7A01024 Port B input register GPPIB R 16 Pad 2 13 5 0xB7A01028 Port B mode register GPPMB R W 16 0x0000 13 6 0xB7A0102C Port B interrupt enable register GPIEB R W 16 0 0000 13 7 0xB7A01030 Port B interrupt polarity register GPIPB R W 16 0x
86. 4 0 0 0 0 A 17 A 18 XA 17 Ha 25 Ha 25 4 Ha 26 26 4 0 0 A 16 A 17 XA 16 Ha 24 24 4 25 25 4 Ha 26 Ha 26 4 A 15 A 16 XA 15 Ha 23 23 4 Ha 24 24 4 Ha 25 Ha 25 4 A 14 A 15 XA 14 Ha 22 22 4 Ha 23 Ha 23 4 Ha 24 A 13 A 14 XA 13 Ha 21 21 4 22 22 4 Ha 23 23 4 A 12 A 13 XA 12 Ha 20 Ha 20 Ha 21 Ha 21 Ha 22 Ha 22 A 11 A 12 XA 11 Ha 19 Ha 11 3 20 ha 11 3 Ha 21 Ha 11 3 A 10 3 A 11 XA 10 Ha 18 Ha 10 Ha 19 Ha 10 Ha 20 Ha 10 A 9 A 10 XA 9 Ha 17 Ha 9 Ha 18 Ha 9 Ha 19 Ha 9 A 8 A 9 XA 8 Ha 16 Ha 8 Ha 17 Ha 8 Ha 18 Ha 8 A 7 A 8 XA 7 Ha 15 Ha 7 Ha 16 Ha 7 Ha 17 Ha 7 A 6 A 7 XA 6 Ha 14 Ha 6 Ha 15 Ha 6 Ha 16 Ha 6 A 5 A 6 XA 5 Ha 13 Ha 5 Ha 14 Ha 5 Ha 15 Ha 5 A 4 A 5 4 Ha 12 Ha 4 Ha 13 Ha 4 Ha 14 Ha 4 A 3 A 4 XA 3 Ha 11 Ha 3 Ha 12 Ha 3 Ha 13 Ha 3 A 2 A 3 XA 2 Ha 10 Ha 2 Ha 11 Ha 2 Ha 12 Ha 2 A 1 A 2 XA 1 Ha 9 Ha 1 Ha 10 Ha 1 Ha 11 Ha 1 A 0 A 1 XA 0 Ha 8 Ha 0 Ha 9 Ha 0 Ha 10 Ha 0 N C 0 Notes Ha stands for host address the address used by the program 1 The BWDRAM bit in the DBWC register specifies the data bus width and thus the mapping of the signals to the DRAM address pins regardless of the column length SDRAM cannot use an 8 bit bus 2 The AMUX bits in the DRMC register speci
87. 4 3 2 1 0 BWDRAM 72 E E E 22 52 11 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Address 0x78180000 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored The contents of this register do not affect the SDRAM clock output XSDCLK Bit Descriptions BWDRAM bits 0 and 1 These bits specify the bus width for the DRAM region BWDRAM 1 0 Description 1 0 0 0 Not physically present Access produces error response 0 1 8 bits only possible for EDO DRAM 1 0 16 bits 1 1 reserved 11 14 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 8 DRAM Control Register DRMC This register specifies the DRAM type access timing and other settings The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 M 20 19 18 17 16 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRMC gt RF PRE 5 DWN LAT ARCH AMUX 1 0 Address 0x78180004 Access R W Access size 32 bits Note These bits are reserved for future expansion They ret
88. 5 5 Output leak current Vo Vpp io 50 50 Input pin capacitance Ci 6 Output pin capacitance Co 9 pF pin capacitance Cio 10 Analog to digital gt 2 320 650 Analog reference power converter operative supply current Analog to digital 2 1 2 converter stopped Current consumption Ipps coRE 25 20 100 STANDBY nsa 5 20 Current consumption IDDH_CORE 20 40 HALT fosc 33 MHz 5 10 EX Current consumption RUN CL 30pF 40 70 fete 18 30 Notes 1 All output pins except XA 15 0 2 XA 15 0 3 Allinput pins except RESET N 4 RESET N pin with 50 kO pull up resistance 5 Analog input pins AINO to AIN3 6 Analog to Digital Converter operation ratio is 20 7 io or 0 V for input ports no load for other pins 8 DRAM Controller blocks stopped by DRAME pin setting 9 External ROM used 24 3 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 24 3 2 DC Characteristics for ML675001 Series 2 25 to 2 75 3 0 to 3 6V Ta 40 to 85 Symbol Conditions Minimum Typical Maximum Unit High level input voltage Vpp 10X0 8 10 0 3 Low level input voltage 0 3 Vpp 10 0 2 BUR Bus 1 6 2
89. 8 bits of a 10 bit address a 10 bit address Register settings I2CSAD 11110xx0b Setting the higher 2 bits of an address 12 Setting the lower 8 bits of an address 0 1100 20 19 Chapter 21 Analog to Digital Converter ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter Chapter 21 Analog to Digital Converter 21 1 Overview The built in 4 channel 10 bit resolution analog to digital converter supports two modes of operation Scan mode sequentially converts input from the selected range of channels select mode converts input from a single channel The conversion from an analog quantity to a digital one uses consecutive comparison with a sample and hold function At the user s option the analog to digital converter issues an interrupt request after one cycle through the specified channels in scan mode and after each conversion in the select mode 21 1 1 Components Figure 21 1 shows the analog to digital converter components AVDD AGND VREF 7 Analog 211 selector Analog to dig ital converter AIN3 gt Interrupt request Control circuitry ADCONO 1 ADCON2 ADINT Internal bus AINO to AIN3 Analog input pins ADRO to ADR3 Converter 10 bit result registers ADINT Analog to digital converter interrupt control register ADCONO
90. Access Control Register RAMAC This register controls SRAM access timing The program has read write access to this register RAMAC es 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E 2 E E E E E E E E Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAM _ _ _ _ _ _ _ _ _ _ _ _ RAMTYPE 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Address 0x78100008 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored When switching operating frequencies adjust the contents of this register at the lower frequency that is AFTER a change from high speed to low speed and BEFORE one from low speed to high speed Bit Descriptions e 2 0 bits 0 to 2 These bits specify the SRAM access timing This table is applied only to ML674001 series RAMTYPE 2 0 Pulse width in clock cycles OE WE pulse Read off Notes 2 1 0 npa width timing 0 0 0 1 0 0 0 1 2 0 0 1 0 3 2 0 1 1 4 2 1 0 0 reserved is not guaranteed for a setting labeled reserved 1 0 1 reserved Operation is not guaranteed for a setting labeled reserved 1 1 0 reserved Operation is not guaranteed for a setting labeled reserved
91. Bus Width 16 bit External I O 0 1 2 3 Byte Half Word Access XIOCS NI O XIOCS N 1 XIOCS N 2 XIOCS N 3 XA 23 0 XBS_N 1 0 XOE_N XWR XD 15 0 txiocsr1 txiocsH lt txioxaD txioacc txloxAH1 lt gt txioBsp txioBs txioBsH gt lt gt txiooED bxiooE wEW lt gt txiowRD txiowRH txiopis txIoDIH gt 4 gt 24 32 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e External 0 1 2 3 Write Cycle Bus Width 16 bit External I O 0 1 2 3 Byte Half Word Access txiocsw1 txiocsH lt beat gt XIOCS N O XIOCS_N 1 XIOCS_N 2 XIOCS_N 3 txioxAD txioxAH2 XA 23 0 txioBsD txioBsH XBS N 1 0 txiowED gt txiowELHD txiowELHH m N 1 0 txiowRD txiowRH XWR baopop txiopoH txiopoE lt txiopopE lt XD 15 0 24 33 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e External 0 1 2 3 Read Cycle Bus Width 16 bit External I O 0 1 2 3 Word Access Bus Width 8 bit External I O 0 1 2 3 Half Word Access bxioCsRt j bxiocsH XIOCS 5 XIOCS 2 XIOCS txIoxAD txioacc txioxaHt txioacc txioxaHt lt gt
92. CACH Base 0 7820 0000 9 2 1 Cache Lock Control Register CON The CON register is used for setting the locking operation of the cache memory While the cache memory 18 split into four ways storage locations it is possible to lock the cache memory contents in units of one way by setting LCK 1 0 Further by using the BNK 1 0 and settings it is possible to load instructions or data to the way to be locked Set the value 0x0000 0000 in this register when not using the locking function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ LC K _ _ _ _ sie _ E Value atreset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value atreset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address CACH Base 0x04 Access R W Access size 32 bits Note indicates a reserved bit Always write 0 to the bit If a 1 is written to this bit the operations cannot be guaranteed Description of bits e Selects the way of the cache memory to be locked LK Cache Cache No way locked Cache Locked One way locked Locked Locked Two ways locked Locked Locked Three ways locked Note Alocked way will not be flushed even when a flushing operation is made using the FLUSH register 9 2 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY F Sets the cache memory in the Load mode When 0 is set normal cache operatio
93. Chapter 11 PNIS NO EN NES WIE 7 0 gt Figure 11 17 SDRAM Byte LSB Read _ _ cVIoA 5 Figure 11 18 SDRAM Byte LSB Write 11 41 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 5 DRAM Power Management Using STANDBY or HALT mode requires program manipulation of the DRAM controller For further details see Chapter 7 Power Management 11 42 ML674001 Series ML675001 Series User s Manual External Memory Controller Chapter 11 11 6 Sample External Memory Connections The following pages give connection examples for each device type Devices differ as to signal names and other points so refer also to the data sheet for the actual intended device As the number of devices increases insert buffer elements and other components to ensure adequate drive power load capacity etc We recommend pull up resistors on the XD pins Pin Name yo function ROM SRAM 9 SDRAM BDO 0 1 2 3 DRAM XA 23 19 O External address bus 3 3 3 XA 18 0 O External address bus O O O O O O XD 15 0 External data bus XROMCS N O External ROM chip select O XRAMCS N External RAM chip select O XIOCS N 0 I O 0 chip select O XIOCS
94. Controller 8 4 5 FIQ Enable Register FIQEN Bit O in this register controls masking of the external fast interrupt request EFIQ pin input The CPU has read write access to this register 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FIQEN Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _ _ _ _ _ E _ _ _ _ _ _ _ _ _ FIQEN Address 0x78000010 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions FIQEN bit 0 This bit controls masking of the external fast interrupt request EFIQ pin input FIQEN Description 0 Disable FIQ requests 1 Enable FIQ requests ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller 846 IRQ Number Register IRN This register gives the interrupt source number for the IRQ request with the highest priority Reading this register clears it to zero and sets the current interrupt level CIL register bit corresponding to the interrupt level to 1 masking pending interrupt requests at or below that level When an interrupt request with a higher interrupt level subsequently arrives the interrupt controller writes its inte
95. Converter control register 0 Converter control register 1 ADCON2 Converter control register 2 AVDD Analog VDD pin AGND Analog ground pin VREF Analog reference voltage Figure 21 1 Analog to Digital Converter Components ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter 21 1 2 Pin List Pin Name Description AVDD VDD Power supply for the analog to digital converter VREF High Reference voltage for the analog to digital converter 1 VREFP High Reference voltage the analog to digital converter 2 VREFN Low Reference voltage for the analog to digital converter 2 AIN 0 Analog to digital converter analog input port 0 AIN 1 Analog to digital converter analog input port 1 AIN 2 Analog to digital converter analog input port 2 AIN 3 Analog to digital converter analog input port 3 AGND GND Ground for the analog to digital converter 1 ML674001 Series only 2 ML675001 Series only 21 1 3 Control Register List Address Name Abbreviation R W Size Initial Value 0xB6001000 Analog to digital converter control register O ADCONO R W 16 0x0000 0xB6001004 Analog to digital converter control register 1 ADCON1 R W 16 0x0000 0xB6001008 Analog to digital converter control register 2 ADCON2 R W 16 0x0003 0xB600100C Analog to digital converter interrupt control
96. Digital Converter Flowcharts Specify clock frequency Disable interrupts Specify starting channel Specify action after scan Start conversion No Figure 21 5 Scan Mode Example Operating conditions Operating clock 1 8 CCLK e Interrupt requests No e Scan channels 1to3 21 12 ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter Specify clock frequency Disable interrupts Specify channel Start conversion No Yes Read result register Figure 21 6 Select Mode Example Operating conditions e Operating clock 1 8 CCLK e Interrupt requests No e Channel 2 Sample Pin Circuit VREF 33V 72277 VREFP AVDD 10 0 1 uF ML674001 Series ML675001 Series 3 3V Analog AIN 3 0 Input AGND VREFN Figure 21 7 Sample Analog to Digital Converter Connections 21 13 Chapter 22 Built In Flash Memory ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory Chapter 22 Built In Flash Memory 22 1 Overview This LSI has built in flash memory The flash memory is electrically programmable non volatile memory thus this LSI provides simple and powerful multiple programming methods The features of built in flash memory are as follows 1 The ML674001 and ML675001 have no built in flash memory Features e Size of built in flash memory ML67Q4002 256 Kbyte 128K x 16 bits ML6
97. If the clock signal to a functional block is stopped shifting to HALT or STANDBY mode and back again restarts the clock signal only if the wake up signal is a reset Clock Gear Modifying the CCLK or HCLK divisor in the clock gear control CGBCNTO register dynamically changes the corresponding clock frequency to 1 1 1 2 1 4 1 8 1 16 or 1 32 times the base frequency Changing the CCLK frequency with the clock gear affects the system timer serial I O SIO block watchdog timer WDT timers PWM block UART and DRAM refresh clock changing the HCLK frequency does not If the clock gear is producing lower clock frequencies shifting to HALT or STANDBY mode and back again restores the 1 1 settings only if the wake up signal is a reset Always switch DRAM to self refresh operation before reducing the clock signal frequency below the minimum specified for reliable operation Notes 1 1 32 M675001 Series only Notes for each function in using Clock Gear SIO When changing the CCLK the communication through SIO should be stopped UART When changing the CCLK the communication through UART should be stopped WDT The WDT interval will be changed when CCLK Clock Gear is changed DRAM Refresh cycle setting should be set based on final CCLK frequency before changing clock If refresh cycle is changed dynamically must be set CCLK 1 1 of clock gear temporally PWM The PWM frequency is changed when the CCLK clock frequency is changed AD con
98. Memory Controller ROM access Supports 16 bit devices Supports Flash memory SRAM access Supports 16 bit devices Supports Asynchronous SRAM DRAM access Supports EDO DRAM and SDRAM Supports 16 bit and 8 bit only possible for EDO DRAM devices Supports distributed CAS before RAS CBR refresh External I O banks access Four banks of external I O space Supports 8 and 16 bit devices Supports external WAIT input signal XW SIO Full duplex asynchronous operation Built in baud rate generator Synchronous SIO Choice of Master or Slave operation Choice of LSB or MSB fast operation Dc Master mode only Supports fast mode 400Kbps standard mode 100Kbps UART 16550A compatible asynchronous communications 6 byte FIFO each for transmit and receive operations Full duplex collision operation Built in baud rate generator Clock Signal Connects to crystal ML674001 series 16 MHz to 33 MHz ML675001 series SMHz to 14 MHz Also supports direct external clock input 1 2 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Power Management STANDBY mode Stop clock in software HALT mode Stop clock signals to CPU and other key components in software Clock gear clock change is dynamically possible in the division ratio of clock input frequency ML 674001 series 1 1 1 2 1 4 1 8 or 1 16 ML 675001 series 1 1 1 2
99. Protect The protect operation disables erase and program operations in the specified areas There are two types of protect block protect and chip protect Each type of protect is activated by entering an SDP command of four cycles the Block Protect or Chip Protect command to the command register Block protect function protects an address space of 16KB 8 sectors from the top address side and chip protect function protects the address space of the entire chip area Neither protect is canceled even if the power is turned off 2247 Protect Cancel Protect is cancelled by entering an SDP command of four cycles the Cancel Protect command to the command register The execution of the Cancel Protect command cancels both block protect and chip protect at the same time 22 0 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory Protected Areas ML67Q4002 ML67Q5002 Block protect Address Chip protect Address 0 3 FFFF 0 3 FFFF Ox3 C000 0 3 BFFF 240KB 120 sectors 0 0 0000 ML67Q4003 ML67Q5003 Block protect Chip protect Address Address Ox7_FFFF 0x7_C000 0 7_ 496KB 248 sectors 0 0 0000 0 0 0000 22 10 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 22 4 8 Product Identification Software ID The product identification software ID operation outputs the manufacturer code and device code which are then ready by the programm
100. SDRAM x8 bits 11 0 DQ7 DQO CS WE RAS CAS CLK CKE DQM SDRAM x8 bits 11 0 DQ7 DQO CS WE RAS CAS CLK CKE DQM Figure 11 27 Connecting Two x 1M x 8 Bit SDRAMs 4 MB 11 51 Chapter 12 Direct Memory Access Controller DMAC ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC Chapter 12 Direct Memory Access Controller DMAC 12 1 Overview This 2 channel direct memory access controller DMAC transfers data directly between memory and memory between an I O device and memory and between I O devices reducing the CPU load and thus boosting overall LSI operational efficiency Features e Number of channels 2 e Channel Priority Fixed mode Channel priority never changes channel 0 channel 1 Round robin mode Last channel used has lower priority e Maximum number of transfers 65 536 e Transfer sizes byte halfword and word 8 16 and 32 bits e Dual address access A read from the transfer source is independent from a write to the transfer destination e Bus Access Cycle stealing mode The DMA controller surrenders bus access after each individual DMA transfer Burst mode The DMA controller does not surrender bus access until the specified number of transfers are complete e DMA Transfer Requests Software request mode The DMA controller generates transfer requests until the specified number of transfers ar
101. The data in this register can be read and written by programs value at the time of reset is 0 00 7 6 5 4 3 2 1 0 I2CIR I2CIR At reset 0 0 0 0 0 0 0 0 Address OxB7800010 Access R W Access size bits Note This is a reserved bit for future expansion In this LSI is read during reading and this bit is ignored during writing Explanation of Bits e bit 0 This bit indicates the pesence of an interrupt request When 1 is written to this 12 1 bit the 12 and I2CDAK bits of the I2CSR register are cleared When the I2CDAK bit is set to 1 this bit is immediately set to 1 However when the I2CAAK bit is set to 1 this bit is set to 1 after the transmission reception of 1 byte of data following the transmission of slave address I2CIR Description 0 No interrupt request 1 Interrupt request pending 20 8 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 2 6 12 Bus Interrupt Mask Register I2CIMR The I2CIMR register masks the interrupt cause of the I2C bus written by programs value at the time of reset is 0 01 The data in this register can be read and Set the IDCIMR register before setting the I2CCON register 7 6 5 4 3 2 1 0 I2CMR I2CMF At reset 0 0 0 0 0 0 0 1 Address OxB7800014 Access R W Access size
102. The port function control register GPCTL defines whether each pin should be used in its primary mode as an I O pin or in the secondary multiplexed mode in its secondary role For example PIOA 7 0 pins function as port A GPIO pins in primary mode But when port function control register configures these pins for their secondary role GPCTL 0 1 these pin take on the role of the UART signals PIOD 7 1 are configured by DRAME N pin for DRAM access function as explained in Chapter 4 Chip Configuration of this manual By configuring the DRAME N pins so as to disables the DRAM controller the processor will be configured to use the pins PIOD 7 1 in their primary function thus as GPIOs By setting the DRAME N pins in a configuration to enable the DRAM controller the pins PIOD 7 1 will be configured in their secondary function which is as control signals for the DRAM bank 13 15 Chapter 14 Watchdog Timer WDT ML674001 Series ML675001 Series User s Manual Chapter 14 Watchdog Timer WDT Chapter 14 Watchdog Timer WDT 14 4 Overview The 16 bit watchdog timer monitors whether the program has run out of control Alternatively it can be used as an interval timer Counter overflow produces an interrupt request or for the watchdog timer configuration a forced system reset 14 1 1 Components CCLK 32 PEN TMRSTN system reset bit watchdo CCLK 64 9 IVTINTN interrupt request CCLK 128 Timer WDTINTN interrupt reque
103. W 16 0 0000 15 12 0xB8000004 Clock stop register CLKSTP R W 32 0 00000000 7 7 0xB8000008 Clock gear control register CGBCNTO RW 32 0 00000000 7 9 0xB800000C Clock wait register CKWT R W 32 0 000000 7 10 0xB8000010 Remap control register RMPCON R W 32 0 00000000 3 4 0xB8001004 System timer enable register TMEN RW 32 0 00000000 15 4 0xB8001008 System timer reload register TMRLR R W 32 0 00000000 15 5 0xB8001010 System timer overflow register TMOVFR R W 32 0 00000000 15 6 0xB8002000 SIO transfer buffer register SIOBUF R W 32 0 00000000 17 3 0xB8002004 SIO status register SIOSTA R W 32 0 00000000 17 4 0xB8002008 SIO control register SIOCON R W 32 0 00000000 17 6 0xB800200C Baud rate control register SIOBCN R W 32 0 00000000 17 8 0xB8002014 Baud rate timer register SIOBT R W 32 0 00000000 17 9 0xB8002018 SIO test control register SIOTCN R W 32 0x00000000 17 10 5 ML674001 Series ML675001 Series User s Manual Appendixes Appendix B Package Dimensions LQFP144 P 2020 0 50 K 022 0 0 2 020 0 0 1 0 22 0 05 10 1008 047 0 05 ERN INDEX MARK Mirror finish 1 25 1 7 MAX
104. XD 15 0 input setup time SRAM ROM txpis 17 DMAC ACCESS XD 15 0 input hold time SRAM ROM XD 15 0 output delay SRAM ROM 14 5 ARM ACCESS XD 15 0 output delay SRAM ROM txpop tuc 7 5 DMAC ACCESS XD 15 0 output Enable txDoE ns time SRAM ROM 1 1 5 XD 15 0 output Disable time SRAM ROM i i 5i XD 15 0 output hold time CL SRAM ROM buon 0 5 ARM ACCESS XD 15 0 output hold time SRAM ROM txpoH 0 5 tuc 5 5 DMAC ACCESS XROMCS N XRAMCS N output hold time 1 Nri 1 5 mE SRAM ROM XROMCS N XRAMCS N Output hold time 2 tcsu2 0 5 tuc 0 5 SRAM ROM 24 0 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B O Control signal timing 2 25 to 2 75 3 0 to 3 6V Ta 40 to 85 C IO 0 10 1 10 2 10 3 Condi Item Symbol tions Minimum Typical Maximum Unit Notes XIOCS_N 0 XIOCS_N 1 The 1001 23 access time 1 t Te IO23ACY registers specify external I O 0 1 2 and 3 READ 05 the OE WE pulse width ACCESS and read off time for XIOCS N O
105. XIOCS N 1 accessing external I O 0 1 access time 2 2 2 nioi tuc 2 and 3 respectively For external 1 0 1 2 and 3 XIOCSR2 Zn tHe 1 further details refer to READ ACCESS sections 11 2 5 and 11 2 6 XA 23 0 access time external t ipfos of chapter 11 0 4 2 3 101 101 XBS_N 1 0 access time external I O 0 1 2 and 3 txioss Riot inge Mor tHo 1 5 XWR delay t 0 35 Address Setup external 1 0 1 2 and 3 XIOWRD oL OE WE Pulse width XWR hold time 30 pF ED B potu Address Setup 1 external I O 0 1 2 and 3 MP OE WE Pulse XWAIT sampling timing delay 1 ied 2 e width external 0 1 2 and 3 XIOWAITD1 102 102 ns XWAIT sampling timing delay 2 t dece e in Address Setup external 0 1 2 3 XIOWAITD2 101 101 XWAIT setup time t 20 2 2 Address Setup 1 external 0 1 2 and 3 TE XWAIT hold time towan 0 2 _ Nios OE WE pulse width external 0 1 2 and 3 delay txiooED nios tuc 2 tuc 1 Address Setup 1 external 0 1 2 3 Pulse width XWE N delay 1 external P 1 2 and 3 nios thet 1 5 pa Nio7 Address Setup 2 XIOCS N O XIOCS N 1 CL OE WE Pulse width access time 1 external I O 0 1 2 txiocsw1 30 pF Nios tuc nioe tuc
106. and TIMECMPx TMINTN Figure 15 3 One Shot Operation Interval timer operation A match between TIMECNTx and reloads TIMECNTx from TIMEBASEx but does not reset the START bit to 0 so counting continues The timer then generates an interrupt request if interrupts are enabled Note however that the hardware does not automatically cancel this interrupt request The interrupt handler must do so by writing 1 to the STATUS bit 2 SIR 12 103 X 104 K 105 X 106107 102 Match between TIMECNTx TIMECMP 107 and TIMECMPx reloads TIMECNTx from TIMEBASEx TIMEBASE TMINTN TMINTN asserted if IE 1 Figure 15 4 Interval Timer Operation 15 14 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 3 3 Specifying Clock and Starting Auto Reload Timers The CLKSEL 2 0 bits in a timer control register TIMECNTLx specify for the corresponding timer the frequency divisor for deriving the operating clock from CCLK The choices available are 1 2 4 8 16 and 32 Writing 1 to the START bit in the same register starts the timer For one shot operation a match between the counter and compare registers automatically resets the START bit to 0 to stop counting Interval timer operation does not clear START so counting continues Notes 1 Operation is not guaranteed for cloc
107. be configured ML675001 Series only For further details on the clock gear see Chapter 7 Management 5 1 1 Components Figure 5 1 gives a block diagram for the clock generator 1 ML674001Series Only dramc BootROM SRAM 1 bclk uPLAT EXPIOC 2 exintc dfslv apbif SRAM Ee 2 2 ML675001Series Only clkgen Figure 51 Clock Generator Block Diagram The block clock control BCKCTL register controls the clock signals to the functional blocks using the OR gates shown in the clock lines 5 1 ML674001 Series ML675001 Series User s Manual Chapter 5 Clock Generator 5 1 2 Pin List Pin Name Description OSCO Crystal connection or external clock input OSC1 Crystal connection Leave this pin unconnected if using external clock input CLKMDO Clock mode 0 input ML675001series only CLKMD1 Clock mode 1 input ML675001series only 5 1 3 PLL Clock frequency setup ML675001 Series Only PLL can be built in and the clock frequency to an inside can be set up by doubler setup of the input frequency from crystal connection terminals and PLL PLLoperation CLKMD 1 0 Cryetal connection a amat elock terminals input Note mode setup frequency clock frequency 8 time mode 11 5 to 7 5MHz 40 to 60MHz 4 time m
108. bit data processing this LSI includes internal RAM and onboard peripherals that make it ideal for such embedded control applications as PC peripherals and communication terminals Finally there is a built in external memory controller for directly connecting ROM SRAM SDRAM other memory types and peripheral devices The following is a list of features CPU 32 bit RISC CPU ARM7TDMI Built in 8KB unified cache ML675001 series only Little endian byte order Operating frequency ML674001 series 1 MHz to 33 MHz ML675001 series 1 MHz to 60 MHz Instruction set Free switching between a highly dense 32 bit instruction set and a 16 bit subset offering higher object code efficiency General purpose registers 32 bit x 31 Barrel shifter Simultaneous ALU and barrel shift operations in the same instruction Multiplier 32 bit x 8 bit JTAG interface for debugging Built in Memory SRAM 32Kbytes 8K x 32bits 1 cycle access FLASH memory ML674001 ROM less version ML67Q4002 256Kbytes 128K x 16615 ML67Q4003 512Kbytes 256K x 16bits ML675001 ROM less version ML67Q5002 256Kbytes 128K x 16bits ML67Q5003 512Kbytes 256K x 16bits e Interrupt Controller One fast interrupt source external 27 interrupt IRQ sources 23 internal and 4 external Independent masking for each FIQ and IRQ source Independent interrupt priority level settings for each IRQ source Priorit
109. bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions PRI bit 0 This bit specifies DMA channel priority PRI Description 0 Fixed channel 0 channel 1 1 Round robin Last channel used has lower priority 12 5 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 2 Status Register DMASTA This register gives the transfer status for each DMA channel A 1 in a bit indicates that the transfer count register DMACSIZ for the channel contains nonzero value The bit returns to 0 when the specified number of transfers are complete normal termination or an error condition forces an abnormal termination 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMASTA he E mi EE iew S 273 EN 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Il _ _ _ i coe ee _ _ _ az mU E STA1 STAO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 7 0004 Access R Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Bit Descriptions STAO bit 0 This bit gives the transfer status for DMA channel 0 STAO Description 0 Idle no data
110. both instructions and data Features Cash memory with a capacity of 8k bytes that contains both instructions and data Write back method 4 way set associative 16 byte block size Cacheable non cacheable setting can be made in units of 128M byte banks Lock setting of the cache memory is possible in units of a way It is possible to hold in the cache memory the high speed processing programs such as interrupt processing etc e Flush control by software 9 1 1 Configuration Figure 9 1 shows the cache memory configuration DataRAM way0 SRAM 512x32 CPU Interface TagRAM way0 SRAM 128x23 TagRAM 1 SRAM 128x23 TagRAM way2 SRAM 128x23 TagRAM way3 SRAM 128x23 AHB Bridge Cache Controller AHB Bus Figure 91 Cache Memory Configuration Diagram 9 1 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 1 2 List of Control Registers Address Abbreviation R W Name brief description Initial value 0x7820_0004 CON R W Cache lock control register 0x0000_0000 0x7820_0008 CACHE R W Cacheable register 0x0000_0000 0x7820_001C FLUSH FLUSH register Undefined 9 2 Description of Control Registers In this description of registers the offset value expression method is used for giving the addresses absolute address is calculated by adding the offset address to the base address of each module e Base address value of cache memory controller
111. byte to the transmit queue resets this bit to 0 If the IER 1 bit enables THRE interrupts this transition produces an interrupt of priority 3 in the UARTIIR register If THRE is the source for the interrupt indicated by the UARTIIR register reading the UARTIIR register resets this bit to 0 SOUT Start Data bit 8 X Stop 1 or 2 THRE RDN IIR Read tIRS lt 16 Baud rate Clocks 151 8 to 16 Baud rate Clocks 5 8 Baud rate Clocks Figure 18 2 Transmit Timing 18 23 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 3 2 Receiving Data Figure 18 4 gives the timing for receiving data Figure 18 5 that for reading the first byte from the receive queue Figure 18 6 that for reading the last byte The baud rate is generated by dividing baud rate clock by 16 A sampling is performed by 8th clock of a baud rate clock When the hardware detects the start bit from the SIN pin it first latches the data bits into the receive shift register It then transfers the received character from the shift register to the UARTRBR register via the receive queue When the character reaches the UARTRBR register the LSR 0 bit in the UARTLSR register goes to 1 to indicate that there is valid data in UARTRBR register Reading the UARTRBR register resets this bit to 0 Baud rate Clock Sample Clock Figure 18 3 Baud Rate and Samplin
112. control register RDWC 32 0x00000003 11 24 0x7818001C DRAM refresh cycle control register 1 RFSH1 RW 32 0x00000000 11 22 0 7 000 DMA mode register DMAMOD R W 32 0x00000000 12 5 0 7 00004 DMA status register DMASTA R 32 0x00000000 12 6 0x7BE00008 DMA transfer complete status register DMAINT R 32 0x00000000 12 7 0 7 100 DMA channel mask register DMACMSKO R W 32 0x00000001 12 9 0 7 104 DMA transfer mode register DMACTMODO R W 32 0x00000040 12 10 Ox7BE00108 transfer source address register DMACSADO R W 32 0 00000000 12 12 0 7 0010 DMACDADO RW 32 0 00000000 12 13 0x7BE00110 DMA transfer count register DMACSIZO RW 32 0 00000000 12 14 ML674001 Series ML675001 Series User s Manual Appendixes y Ref Address Name Abbreviation R W Size Initial Value Pages 0x7BE00114 PMA transfer complete status clear DMACCINTO w 32 2 12 15 register 0 7 0200 channel mask register DMACMSK1 R W 32 0 00000001 12 9 0x7BE00204 DMA transfer mode register DMACTMOD1 R W 32 0x00000040 12 10 0x7BE00208 DMA transfer source address register DMACSAD1 R W 32 0 00000000 12 12 0 7 20 201 DMACDAD1 RW 32 0 00000000 12 13 0x7BE00210 DMA transfer count register DMACSIZ1 RW 32 0 00000000
113. e teg irato d 9 6 9 3 5 LoadMode 4 aho dr tee t Beto ut ee aime eet i pagu S 9 7 9 6 Blushung Function obe roc nU eti Bette Pra erit dete Ee y e Au rte eet 9 7 924 Precautions 06 et de true RR e DR 9 8 9 4 1 Precautions when Using DMA Transfer sees nennen enne nennen trennen enne 9 8 94 2 Precautions rio aee trit ER qa epe ui qr pee d 9 8 9 5 Examples Of eoe Hecuba esiti 9 9 9 5 1 Example of Cache Memory Initialization esee nennen nennen nennen rennen inet 9 9 9 5 2 Example of Cache Memory Flushing Requiring Data Write Back sese 9 9 9 5 3 Bxample of Lock Setting Procedure o eren eere be e erem idet rem to dr iere med 9 10 9 6 Typical Operation Iimin6s ay tette ere e eet a r 9 12 Chapter 10 Built In Memory 1021 Me LE 10 1 10 2 B lltsInSRAM L ay Ce 10 1 10 3 Built In EEASH tte n I a ev 10 1 Chapter 11 External Memory Controller RI gone E e n ES 11 1 14 11 CS TOON a Sua 11 1 11 1 2 Register 11 2 17 2 tbe deme ed 11 3 11 2 1 Bus Width Control Register eene nennen nennen ener enne
114. ener etre eene nennen 8 13 8 4 8 Interrupt Level Control Register 0 ILCO eese nennen 8 14 8 4 0 Interrupt Level Control Register 1 8 16 8 4 10 Current Interrupt Level Clear Register ener 8 18 8 4 11 Current Interrupt Level Encode Register CILE nennen 8 19 84 12 IR Clear Register IRCE i e e D OR 8 20 84 13 IRQA Register RQA L unu susan akpi rts 8 21 8 4 14 IRQ Detection Mode Setting Register IDM enne 8 23 8 4 15 Interrupt Level Control Register ILC eese eene ener ennennen enne rennen ennt 8 24 8 4 16 Register Settings for Interrupt Sources 8 26 8 5 Description of Operation mette iet entree c qme nee fere petat trien 8 27 9 2 1 External Fast Interr upt BEIQ 8 27 8 5 2 External and Internal Interrupts 8 28 8 5 3 Nested Interrupts and Re Entrant Interrupt Service Routines eese 8 30 84 Important Notes on Interrupt ie eee ete Abb peg E ede te uds 8 31 8 5 5 Waking from HALT and STANDBY 8 32 8 5 6 Brror Response eoe RR ERU UR REI th oerte rette i n e de us 8 33 85 7 Interrupt Response
115. for STANDBY mode EXINT pulse width 2 texiNTW2 tuc Release from STANDBY mode DREQCLRO DREQCLR1 tpcLRD1 8 10 5 delay 1 ns TCOUTO TCOUT1 delay 1 ttcoutp1 Bite 8 thc 10 5 DREQCLRO DREQCLR1 30 pF tpcLRD2 2 tuc 11 delay 2 TCOUTO TCOUT 1 delay 2 2 2 tuc 11 DREQO DREQ1 hold time tuc 24 7 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics m SRAM ROM Control signal timing 2 25 to 2 75 Vpp 3 0 to 3 6V Ta 40 to 85 C SRAM ROM Condi TE Symbol tions Minimum Maximum Unit Notes XROMCS_N XRAMCS_N The ROMAC and RAMAC access time1 t 1 tuc 2 1 tuc registers specify the OE WE SRAM ROM PM 42 2 pulse width and read off time READ ACCESS for ROM and SRAM access XROMCS N XRAMCS N respectively For further details access time2 1 2 1 2 1 refer to sections 11 2 3 and SRAM ROM CSR2 tuc 2 tuc 2 11 2 4 of chapter 11 READ ACCESS XA 23 0 access time t 1 tuc 1 tuc 0 CPU Access SRAM ROM ARS 2 5 0 5 XBS_N 1 0 access time t nmi tuc 1 1 Access SRAM ROM gt
116. i 05 N pulse width SRAM ROM toewew 4 2 XOE N pulse width SRAM ROM toew 2 ng2 tuc 4 2 ng2 tuc 1 ARM ACCESS XBS N 1 0 delay E m 2 SRAM ROM XBS N 1 0 output hold 2 time 1 SRAM ROM XBS N 1 0 output hold i m E time 2 SRAM ROM einn PS 23 0 delay SRAM ROM txan 09 n 9 XA 23 0 output hold time t 0 XAH1 1 SRAM ROM 24 17 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics SRAM ROM continued Item Symbol fe Minimum Maximum Unit Notes XA 23 0 output hold time 2 SRAM ROM XD 15 0 input setup time SRAM ROM txpis 19 ARM ACCESS XD 15 0 input setup time SRAM ROM txpis 17 DMAC ACCESS XD 15 0 input hold time SRAM ROM XD 15 0 output delay SRAM ROM txpop ng2 tuc 14 5 ARM ACCESS XD 15 0 output delay SRAM ROM txpop ng2 tuc 7 5 DMAC ACCESS XD 15 0 output Enable E time SRAM ROM XD 15 0 output Disable time SRAM ROM XD 15 0 output hold time CL SRAM ROM txpou 30 pF tuc ARM ACCESS XD 15 0 output hold time SRAM ROM txpoH tuc 5 5 DMAC ACCESS XROMCS N XRAMCS N output hold time 1 tuc 1 5 LI SRAM ROM XROMCS_N XRAMCS_N Output hold time 2 2 tuc 0 5 SRAM ROM txaH2 tuc 0
117. indicating the results of arithmetic and bitwise operations The CPU tests these to determine whether to execute instructions All ARM state instructions feature conditional execution The only THUMB state instructions with it are conditional branches 2 9 2 Control Bits A program status register s lowest eight bits I T and M 4 0 are collectively called control bits These change in response to exceptions Software can manipulate them in privileged user modes e Tobit This bit specifies the operation state 1 for THUMB 0 for ARM Note that modifying this bit in software risks sending the CPU into an unpredictable state e Interrupt disable bits Setting the I or bit to 1 disables IRQ or interrupts respectively e Mode bits These five bits specify the CPU operating mode as shown in Table 2 1 Note that not all combinations produce valid operating modes Specifying one not listed risks sending the CPU into an unpredictable state 2 7 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU Table 2 1 PSR Mode Bits M 4 0 THUMB State Registers ARM State Registers 10000 User R7 RO R14 R0 LR SP PC CPSR PC CPSR 10001 FIQ R7 RO R7 RO LR_fiq SP_fiq R14_fiq R8_fiq PC CPSR SPSR fiq PC CPSR SPSR fiq 10010 R7 RO R12 R0 LR_irq SP_irq R14 irq R13 irq PC CPSR SPSR irq PC CPSR SPSR irq 10011 Supervisor R7 RO R12 R0 LR svc SP svc R14 svc R13 s
118. interrupt 3 External input choice of edge or level sensing 8 5 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 3 Interrupt Levels Each IRQ source has its own interrupt level setting The higher the numerical value the higher the priority A setting of zero on the other hand masks interrupts from that source Setting and Priority Interrupt level setting Priority 7 High 1 Low 0 Interrupts masked 8 6 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 Register Descriptions 8 4 4 IRQ Register IRQ A 1 in bit n indicates a pending unmasked interrupt request from the corresponding IRQ source nIRn The CPU has only read access to this register 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRQ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000000 Access R Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Bit Descriptions e 1 0 15 0 bits 0 to 15 A 1 in bit n indicates a pending unmasked interrupt request from the corresponding IRQ source nIRn IRQ 15 0 D
119. is the address of lowest byte Figure 2 1 Little Endian Byte Addresses Within Words Note The CPU architecture supports both big and little endian byte orders but this LSI uses only the little endian order 2 5 Instruction Length The instruction length is either 32 bits ARM state or 16 THUMB state 2 6 Data Types This LSI supports the data types byte 8 bits halfword 16 bits and word 32 bits Words must be aligned at 4 byte boundaries halfwords at 2 byte ones 2 7 Processor Modes This LSI supports seven processor modes User usr Normal program execution state fiq High speed interrupt handling IRQ General purpose interrupt handling Supervisor svc Protected mode for the operating system Abort abt Prefetch abort data or instruction processing System sys Privileged user mode for the operating system Undefined und Undefined instruction exception processing Mode changes are either under software control or in response to an interrupt or exception Most application programs run primarily in user mode switching to non user privileged modes only in interrupt and exception handlers or to access protected resources 2 2 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 8 Registers The CPU has a total of 31 general purpose 32 bit registers and six status registers Not all registers are available simultaneously however The registers which a program can acce
120. level 1 Drive RTS pin output at Low level MCR 2 bit 2 Reserved Note This LSI does not support OUTI e MCR 3 bit 3 Reserved Note This LSI does not support OUT2 18 13 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte MCRIA bit 4 LOOPBACK control The loop back configuration drives SOUT at High level and connects the transmitter shift register output to the receiver shift register input MCR 4 Description 0 Normal operation 1 Loop back operation MCR 7 5 bits 7 to 5 Unused These return 0 for reads 18 14 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 8 Line Status Register UARTLSR This register displays the line status It is normally the first register that the CPU reads to determine the interrupt source or to poll the serial interface status The CPU has read write access to this register The register contents after a reset are 0x60 7 6 5 4 3 2 1 0 UARTLSR LSR 7 0 After a reset 0 1 1 0 0 0 0 0 Address 0xB7B00014 Access R W Access size 8 bits Bit Descriptions LSR 0 bit 0 Data ready bit This bit goes to 1 when an input character is ready for reading from the UARTRBR register Reading UARTRBR resets this bit to 0 LSR 0 Description 0 UARTRBR does not contain valid data 1 UARTRBR contains valid dat
121. modem status interrupt of priority 4 The CPU has read write access to this register The register contents after a reset depend on the input pin states 7 6 5 4 3 2 1 0 UARTMSR MSR 7 0 After a reset Contents depend on pin states Address 0xB7B00018 Access R W Access size 8 bits Bit Descriptions MSR 0 bit 0 Delta clear to send DCTS A 1 in this bit indicates a change in the CTS input state since the last time that the CPU read that state MSR 0 Description 0 No change in CTS input 1 Change in CTS input MSRI I bit 1 Delta data set ready DDSR A 1 in this bit indicates a change in the DSR input state since the last time that the CPU read that state MSR 1 Description 0 No change in DSR input 1 Change in DSR input MSR 2 bit 2 Trailing edge of ring indicator TERI A 1 in this bit indicates a change from Low level to High in the RI input state since the last time that the CPU read that state A transition from High level to Low does not affect this bit MSR 2 Description 0 No change in RI input 1 Change in RI input 18 18 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte MSR 3 bit 3 Delta data carrier detect DDCD A 1 in this bit indicates a change in the DCD input state since the last time that the CPU read that state
122. of the procedure example of locking in Way 0 for locking instruction codes up to 2048 contiguous bytes in the cache is explained below 1 Make cacheable setting for the bit in the cacheable register corresponding to the bank in which the instruction codes to be locked are stored 2 Set F 1 and 00 Way 0 in the cache lock control register 3 Carry out a data read operation for the addresses in which the instruction codes are stored This causes the instruction codes to be locked to be loaded in Way 0 Since the reading is done in units of 16 bytes make sure that the total number of bytes is 2kB or less including the data before and after the starting address and the ending address of the data read operation Example When the starting address of data read is 0 4000 000C the address for loading will be 0 4000 0000 4 After the data reading in 3 is completed the target instruction codes are locked in Way 0 by setting 0 and LCK 01 in the cache lock control register An example is shown below of the procedure example of locking in Way 0 and Way 1 of locking in the cache the instruction codes contiguous 2049 bytes or more but less than or equal to 4096 bytes 1 Make cacheable setting for the bit in the cacheable register corresponding to the bank in which the instruction codes to be locked are stored 2 Set F 1 and 00 Way 0 in the cache lock control register
123. provides both slave and master interfaces e Slaveinterface program uses this to access DMA controller registers both global and channel e Master interface The DMA controller uses this for DMA transfers 12 3 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 1 2 Pin List Pin Name y o Description DREQO request signal channel 0 DREQCLRO DREQ clear request signal channel 0 DREQ1 request signal channel 1 DREQCLR1 DREQ clear request signal channel 1 TCOUTO O DMA transfer complete signal channel 0 TCOUT1 O DMA transfer complete signal channel 1 12 1 3 Register List CH agarose Name Abbreviation R W Size nitial Value H H Global 0x7BE00000 DMA mode register DMAMOD R W 32 0x00000000 0x7BE00004 DMA status register DMASTA R 32 0x00000000 0x7BE00008 DMA transfer complete status register DMAINT R 32 0x00000000 Channel 0 0x7BE00100 DMA channel mask register RW 32 0x00000001 0x7BE00104 DMA transfer mode register DMACTMODO RW 32 0x00000040 Ox7BE00108 DMA transfer source address register DMACSADO R W 32 0x00000000 Ox7BE0010C DMA transfer destination address register DMACDADO R W 32 0x00000000 0x7BE00110 DMA transfer count register DMACSIZO RW 32 0x00000000 0x7BE00114 DMA trans
124. register specifies the 3 bit interrupt levels for IRQ request sources nIRO to nIR7 in four groups The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ILCO Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000020 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions bits 0 to 2 ILR1 bits 4 to 6 ILR4 bits 16 to 18 ILR6 bits 24 to 26 ILRn specifies the 3 bit interrupt level for IRQ request source nIRn and any others in its group The higher the numerical value the higher the priority A setting of zero on the other hand masks interrupts from that source ILR m 1 Interrupt Level Priority 1 1 1 1118 7 high priority 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0018 1 low priority 0 0 0 Interrupts masked 8 14 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller The following Table summarizes the mapping of nIRO to nIR7 to the four groups and the four fields in this register nIR O ILRO ILCO 2 0 nIR 1 ILR1 ILCO 6 4 nIR 2 nIR 3 nIR 4 ILR4 ILCO 18 16 n
125. s Manual Chapter 18 UART with FIFO 16byte 18 3 7 Setup Procedure Initialize UART Configure ports Configure UART control register Specify buffer trigger levels Set bit 0 in the port control register GPCTL to 1 Choose buffered 16550 or unbuffered 16450 operation Specify format character length number of stop bits and parity in the line control register Specify UART baud rate Setthe divisor latch access bit bit 7 in the line control register to 1 Specifythe divisor in DLL and DLM Setthe divisor latch access bit bit 7 in the line control register to 0 Configure UART transfer control Enable or disable interrupts as desired Configure interrupt control Specify the level and other parameters for the UART interrupt NIR9 to the interrupt controller End of UART initialization 18 30 Chapter 19 Synchronous SIO ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 Chapter 19 Synchronous SIO 19 1 Overview This LSI has one built in 8 bit clock synchronous SIO channel Features e Operating clock selectable at 1 8 1 16 or 1 32 the frequency of the HCLK Configurable as LSB first or MSB first Configurable as Master or Slave Generates transmit receive complete interrupts and transmit receive buffer empty interrupts Built in test function that loops back the tra
126. signal goes active actual number of cycles depends on the type of preceding and successive accesses The following Table summarizes the insertion of read off time for all combinations of access to external ROM SRAM I O or DRAM for ML674001 series and ML675001 series O in the table means that read off time is inserted according to the setting of the ROMAC RAMAC IO23ACX or IO23ACY register Space in the table means that read off time is not inserted for the combination of the accesses Current Cycle Following Cycle ARM DMA ARM amp DMA ROM RAM RAM IO SDRAM EDO DRAM R w R w R W R W R w R W ARM ROM Read O O O O O O O O Write RAM Read O Write 10 Read Write DMA RAM Read 00000 Write IO Read O Write ARM SDRAM Read E Write DMA EDO Read O O0 0 0 0 0 07 DRAM Write Note The read off time for ROM RAM IO is specified by ROMAC RAMAC 1O01AC IO23ACX IO23ACY registers And that time for EDO DRAM is specified by tOEZ of DRAMSPEC register There is no specified Read off time for SDRAM 11 33 ML 674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 4 Access Timing 11 4 1 Accessing External Devices 11 4 1 1 External ROM RAM Access
127. specified at the port level ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 1 1 Components Figure 13 1 illustrates the internal architecture of the GPIO ports both the 10 bit and the 8 bit ports Since all of the pins of the GPIO ports have exactly the same internal structure only 0 is shown in detail below RADDR js Pin 0 Circuit RD 01 4 POE 0 WD 0 POUT 0 PIO 0 HCLK PIOINTN 4 q PIN 0 stopack CLK POE 1 IS 1 4 Pin 1 Circuit RD 1 POUT 1 WD 1 Same as Pin 0 circuit Pins 2 through 9 have the same structure Figure 13 1 PIOx Block Diagram ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 1 2 Pin List Pin Name yo Primary Function Secondary Function Pin Name PIOA O0 General purpose port A bit 0 SIN PIOA 1 General purpose port A bit 1 SOUT PIOA 2 General purpose port A bit 2 CTS PIOA 3 General purpose port A bit 3 DSR PIOA 4 General purpose port A bit 4 DCD PIOA 5 I O General purpose port A bit 5 DTR PIOA 6 General purpose port A bit 6 RTS P
128. state running a 32 bit instruction set and the THUMB state running an alternate 16 bit set 2 2 CPU Operation States The CPU operates in either the ARM or THUMB state Switching states does not affect the CPU operating mode or register contents e ARM state The CPU executes ARM instructions aligned at 32 bit word boundaries THUMB state The CPU executes THUMB instructions aligned at 16 bit halfword boundaries 2 2 1 State Transitions The CPU changes processor states in two ways e BXinstruction The program changes between ARM and THUMB states with a Branch and Exchange BX instruction e Exception processing The CPU always processes exceptions in the ARM state If it was in the THUMB state when it accepted the exception it automatically returns to THUMB state when it returns from the exception handler 2 3 Address Space This LSI uses 32 bit addresses to access a flat 4 gigabyte address space This single address space contains both instructions and data 2 1 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 4 Memory Format Memory consists of bytes numbered sequentially from zero Bytes 0 to 3 contain the first word of data bytes 4 to 7 the second The bytes making up a word are stored in little endian format Higher address 31 24 23 16 15 8 7 0 Word address m e p s b 7 6 5 4 4 s eo e k Lower address e The lowest byte is stored at the lowest address e The address of a word
129. the other unused pins according as the section 1 3 6 ML 674001 Series ML 675001 Series SIN SOUT CLKMODO CLKMOD1 Figure 22 2 Example of a Connection for programinng the flash memory use of boot loading function 22 5 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 3 Description of the Flash Memory Programming Procedure Step 1 Initial Status Provide the flash memory program routine and application codes to be written to flash memory on the host Step2 Downloading the flash memory program routine Set the pins in such a way that the built in boot program is executed at the time of reset The built in boot program downloads the flash memory program routine via the UART to built in RAM Step 3 Erasing Flash Memory The built in boot program starts the flash memory program routine that has been downloaded to built in RAM The flash memory progarm routine erases the contents of flash memory Step 4 Writing Application Codes The flash memory program routine loads the application codes to be written to flash memory via the UART and then writes them to built in flash memory After writing is finished apply protect to flash memory as necessary Note Please obtain the flash memory program routine in advance By changing the flash memory program routine it is possible to program flash memory mounted on the board in addition to built in flash memory 22 6 ML674001 Series ML675
130. the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions IRQS bit 1 This bit controls the software interrupt request signal IRQS Description 0 Negate software interrupt request 1 Assert software interrupt request 8 8 ML674001 Series ML675001 Series User s Manual Interrupt Controller Chapter 8 8 4 3 Register A 1 in bit O indicates a pending fast interrupt request FIQ from the external fast interrupt request EFIQ pin The CPU has only read access to this register 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D FiQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000008 Access R Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Bit Descriptions FIQ bit 0 This bit indicates a pending fast interrupt request FIQ from the external fast interrupt request EFIQ N pin FIQ Description 0 No FIQ request pending 1 FIQ request pending The following Table summarizes how the bit FIQ 0 co
131. the program so that it consists of only instruction fetches with no data accesses for the instruction codes for executing the above locking procedure ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 6 Typical Operation Timings Example of cache hit operation bclk 1 1 1 1 r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 2 2p F 4 L 4 S bed p Re lh mmu emus r ease 1 J Las 42 22 I 1 2 222p J LR 4 LB 4 Seca poses oc 8 ey ET EEES PEPES kusala css Lu 1 22p J L 4 LB 4 ee Se bee el us PTEE 1 OAE EEY a 1 1 222R 2J L 1 LB d arm7tdmi a 31 0 arm7tdmi dout 31 0 bor Jo rdg eis ye bor Eod Ku 54 24 452 qe bor D dco bor
132. to transfer 1 Busy transferring data STAI bit 1 This bit gives the transfer status for DMA channel 1 5 1 Description 0 Idle no data to transfer 1 Busy transferring data 12 6 Chapter 12 ML 2674001 Series ML675001 Series User s Manual Direct Memory Access Controller DMAC 12 2 3 DMA Transfer Complete Status Register DMAINT This register gives the source for an interrupt request indicating the end of a DMA transfer the channel number the termination reason normal or error and the cycle read from transfer source or write to transfer destination Writing anything to an interrupt clear register or DMACCINTI resets the IREQ ISTA and ISTP bits for the corresponding channel to 0 The program has only read access to this register The contents after a reset are 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAINT JSTPTISTPO Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSTAM IISTAO IREQ1 IREQO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 7 0008 Access R Access size 32 bits Notes These bits are reserved for futur
133. written to a destination address in the next cycle device will initially signal a request to the DMA controller e g by asserting the DREQ signal In response the DMA controller will grant the device or memory access to the bus by causing the OUTPUT ENABLE or WRITE ENABLE and CS strobes of the device or memory to be asserted thus giving the device or memory access to the bus 12 3 1 Transfer Modes bit 5 in the DMA transfer mode register or DMACTMOD1 offers a choice of two DMA transfer modes for the corresponding DMA channel 1 Cycle stealing mode The DMA controller surrenders bus access after each individual DMA transfer and waits for another transfer request before acquiring bus access for the next transfer This start and stop process repeats until the specified number of transfers are complete or there is an error 2 Burst mode The DMA controller does not surrender bus access until the specified number of transfers are complete or there is an error 12 3 2 Request Sources ARQ bit 0 in DMA transfer mode register DMACTMODO or offers a choice of two sources for DMA transfer requests external and internal 1 External input DREQ The trigger here is a rising edge in the input signal DREQ The external source must then negate falling edge DREQ for each individual transfer in cycle stealing mode Burst mode ignores this input until the specified number of tr
134. 0 0 0 0 0 0 Address 0xB8001010 Access R W Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions e OVF bit 0 A 1 in this bit indicates counter overflow Writing 1 to this bit resets it to 0 Writes of 0 are ignored OVF Description 0 No overflow detected 1 Overflow detected Note Failure to clear this bit after a interrupt reset request produces a series of such requests 15 6 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 4 Timer Control Registers TIMECNTLO to TIMECNTL5 These registers control timer operation specifying the operating clock enabling and disabling interrupts starting and stopping the timer and specifying the timer operation mode The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMECNTLO to 5 CLKSEL 2 0 START MODE Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7F00000 CHO 0xB7F00020 CH1 0xB7F00040 2 OxB7F00060 CH3 0xB7F00080 CH4 OxB7F000A0 CH5 Access R W Access size 16 bits Note CLKSEL should be set before START bit setting if application need correct timer interval Because timer start count with maximum 6 count by the clock tha
135. 0 0 Not physically present Access to bank region disabled Access from DMA controller produces error response 0 1 8 bits 0 16 bits 1 1 reserved Note Operation is not guaranteed for a setting labeled reserved This IO23BW 1 0 register exists only in ML675001 series ML 674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 3 External ROM Access Control Register ROMAC This register controls ROM access timing The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ROMAC Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROM _ _ _ _ _ _ _ _ _ _ _ _ ROMTYPE 2 0 Address 0x78100004 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored When switching operating frequencies adjust the contents of this register at the lower frequency that is AFTER a change from high speed to low speed and BEFORE one from low speed to high speed Bit Descriptions ROMTYPE 2 0 bits 0 to 2 These bits specify the ROM access timing This table is applied only to ML674001 series ROMTYPE 2 0 Pulse width in cl
136. 0 pF XD 15 0 output enable t 05 time SDRAM SDADOE pata XD 15 0 output disable poupar di tspxpopE O 5tspc 8 time SDRAM 24 12 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 2 25 10 2 75V Vpp 3 0 to 3 6V Ta 40 to 85 C EDODRAM Item Symbol tons Minimum Typical Maximum Unit Notes RASCAS delay t ec g 2 Resp eds The DRPC register specifies the EDO DRAM EDO DRAM access parameters CAS pulse width tRAH tCAC tCAS tRCD tRP EDO DRAM tepcas 4 tuc 2 For further details refer to RAS pulse width 30 owe section 11 2 9 of chapter 11 EDO DRAM EDRAS ED7 RAS precharge time tuc 4 RCD CAS precharge time 2 EDO DRAM nens tuc 4 tCAS XRAS delay u EDO DRAM tEDRASD 2 2 tRP XOE N delay 1 DRAM tepoep1 tuc 4 5 tuc tCAC 1 tCAS XOE delay 2 EDO DRAM tepoEp2 tuc 2 tuc 5 XWE N delay 1 EDO DRAM tepwep1 cis neps tuc 4 tuc 2
137. 0000 reserved 0x0100 0000 External ROM 8MB 0x0000 0000 0x0008 000Q 0x0007 FFFI 0x0000 0000 Built in Flash 512KB 3 8 Chapter 4 Chip Configuration ML674001 Series ML675001 Series User s Manual Chapter 4 Chip Configuration Chapter 4 Chip Configuration 4 1 Overview This LSI provides the following selection pins controlling the use of the clock output and the use of the DRAM controller blocks 4 1 1 Pin List Pin Name 1 0 Description DRAME_N DRAM controller enable CKOE N Clock output enable 4 2 Pin Description A high level DRAME N input disables the DRAM controller reducing power consumption by cutting off the clock signal to the DRAM controller block DRAME N Description H Disable the DRAM controller function L Enable the DRAM controller function A low level CKOE N input enables output of HCLK to the CKO external pin CKOE N Description H Does not output HCLK to the CKO external pin L Output HCLK to the CKO external pin 4 1 Chapter 5 Clock Generator ML674001 Series ML675001 Series User s Manual Chapter 5 Clock Generator Chapter 5 Clock Generator 5 1 Overview This block supplies two clock signals HCLK to the CPU and CPU interfaces and CCLK to the timer and other counters The clock gear provides software control of the frequency divisors for each signal The choices are 1 2 4 8 16 and 32 Note 82 can
138. 0000 13 9 0xB7A01034 Port B interrupt status register GPISB R W 16 0x0000 13 10 0xB7A01040 Port C output register GPPOC R W 16 Indeterminate 13 5 0xB7A01044 Port C input register GPPIC R 16 212 4 13 6 0xB7A01048 Port C mode register GPPMC R W 16 0 0000 13 7 0xB7A0104C Port C interrupt enable register GPIEC R W 16 0x0000 13 8 0xB7A01050 Port C interrupt polarity register GPIPC R W 16 0x0000 13 9 0 7 01054 Port C interrupt status register GPISC R W 16 0x0000 13 10 0xB7A01060 Port D output register GPPOD R W 16 Indeterminate 13 5 0xB7A01064 Port D input register GPPID R 16 2 13 6 0xB7A01068 Port D mode register GPPMD R W 16 0 0000 13 7 0xB7A0106C Port D interrupt enable register GPIED R W 16 0x0000 13 8 0xB7A01070 Port D interrupt polarity register GPIPD R W 16 0 0000 13 9 0 7 01074 Port D interrupt status register GPISD R W 16 0x0000 13 10 0xB7A01080 Port E output register GPPOE R W 16 Indeterminate 13 5 0xB7A01084 Port E input register GPPIE R 16 dan 13 6 0xB7A01088 Port E mode register GPPME R W 16 0 0000 13 7 0xB7A0108C Port E interrupt enable register GPIEE R W 16 0 0000 13 8 0xB7A01090 Port E interrupt polarity register GPIPE R W 16 0x0000 13 9 0xB7A01094 Port E interrupt status register GPISE R W 16 0x0000 13 10 0xB7B00000 Divisor Latch LSB UARTDLL R W 8 Indeterminate 18 21 0xB7B00000 Receiver Buffer Register UARTRBR R 8 Indeterminate 18 4
139. 000000 0x78000018 Current interrupt level register CIL R W 32 0 00000000 0x7800001C Reserved 0x78000020 ae evel contol 32 0 00000000 0x78000024 ANA 32 000000000 0 78000028 Current interrupt level clear W 32 2 register Current interrupt level encode 0x7800002C CILE R 32 0x00000000 register Ox7BF00000 Reserved Ox7BF00004 IRQ clear register IRCL 32 Ox7BF00010 IRQA register IRQA R W 32 0 00000000 e dafection RW 32 0x00000000 register Ox7BF00018 Interrupt level control register ILC R W 32 0x00000000 8 3 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 2 Interrupt Sources 8 2 1 External Fast Interrupt EFIQ_N The external fast interrupt request EFIQ pin is a high priority interrupt request normally assigned to a single time critical source If FIQEN bit 0 in the FIQEN register does not mask the interrupt request the interrupt controller asserts the fast interrupt request nFIQ signal to the CPU in response to detecting an incoming interrupt at the EFIQ_N input pin of this LSI 822 External Interrupts EXINT n There are four external interrupt request inputs available EXINT 0 to EXINT 3 nIR 22 26 28 31 Each has its own register settings for selecting edge or level detection and specifying polarity 8 2 3 Internal
140. 001 Series User s Manual Chapter 22 Built In Flash Memory 22 3 Built in Boot Program 22 3 4 Functional Description The built in boot program is the software that downloads the programs you created to built in RAM via the UART and executes them With the built in boot program writing to built in flash memory can be performed by executing the flash writing program you created Note however that programs that will be downloaded to this built in RAM must be in the Intel HEX format 22 3 2 Operating Procedure The built in boot program runs the programs you created on this LSI according to the following procedure Start this LSI from boot ROM Transmit binary 0 data from terminal software to this LSI via the UART Download the program you created from terminal software to built in RAM via the UART Following the instructions of the built in boot program start the program you created 22 3 3 Operating Environment 1 Devices Equipped with This LSI 1 Operating Frequency ML674001 Series 8 to 33 MHz ML675001 Series 8 to 60 MHz 2 UART port 1 channel Connect PIOA O SIN and PIOA 1 SOUT to the serial port of the host 2 Host PC etc 1 Software Software that supports serial communication with the settings list in the table below 2 Serial port 1 channel List of Settings for Serial Communication Software ML674001 Series ML675001 Series 9600 8 MHz to 33 MHz 9600 8 MHz to 60 MHz Baud rate 19200 16 MHz to
141. 001 Series User s Manual Table of Contents 202 1 122 Bus Control Register I2CCON au nih ae edi d re AE E i G eed 20 3 20 2 2 I2C Bus Slave Address Mode Register 2 5 20 5 20 2 3 I2C Bus Transfer Speed Register IDCCLR 20 6 20 2 4 I2C Bus Status Resister I2CS aciei hat etre m e tea diee Ge Ee ded 20 7 20 2 5 I2C Bus Interrupt Request Register I2CIR eese nennen ene nennen nre 20 8 20 2 6 I2C Bus Interrupt Mask Register IZCIMR 20 9 20 2 7 I2C Bus Transmit Receive Data Register I2CDR sse 20 10 20 2 8 I2C Bus Transfer Speed Counter I2CBO ener 4 20 11 PI M SUSCI E PE 20 12 20 3 1 Transmit operation transfer of 1 byte from master to slave in 7 bit address mode 20 12 20 3 2 Receive operation transfer of 1 byte from slave to master in 7 bit address 20 13 20 3 3 Transmit operation transfer of 2 or more bytes from master to slave in 7 bit address mode 20 14 20 3 4 Receive operation transfer of 2 byte or more from slave to master in 7 bit address mode 20 15 20 3 5 Restart sequence transmit operation 20 16 20 3 6 To receive 1 of data from another slave device after transmitting 1 byte of data 20 16 20 3 7 Start byte transmit Operati
142. 01 Series at 60MHz 0 0 0 0 30 3 ns reserved for External clock input to OSCI 0 0 0 1 reserved reserved 10 ms to 24 ms waiting for Crystal Oscillator 7 10 7 3 5 7 3 6 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management Stopping Clock Signals to Functional Blocks This LSI provides software control over the clock signals to individual functional blocks The following Table lists the functional blocks with clock signal control Block In software With DRAME N Notes pins SIO TIC SSIO 2 Do not stop the clock signal while transfer is in progress DRAMC Always switch DRAM to self refresh operation before stopping the clock signal in software TIMER Stopping the clock signal suspends the counter If each timer the timer is operational restoring the clock signal individually causes counting to resume with that counter value PWM Stopping the clock signal suspends the counter If the PWM block is operational restoring the clock signal causes counting to resume with that counter value A D Stop conversion before stopping the clock signal Do not access a functional block while its clock signal is stopped Accessing the DMA controller or DRAM controller triggers an abort exception Accessing other functional blocks risks unreliable operation
143. 014 IRQ number register IRN R 32 0x00000000 8 12 0x78000018 Current interrupt level register CIL R W 32 0 00000000 8 13 0x78000020 Interrupt level control register O ILCO RW 32 0x00000000 8 14 0x78000024 Interrupt level control register 1 ILC1 RW 32 0x00000000 8 16 0x78000028 Current interrupt level clear register CILCL 32 8 18 0x7800002C Current interrupt level encode register CILE R 32 0x00000000 8 19 0x78100000 Bus width control register BWC R W 32 0 00000008 11 3 0x78300000 External I O bank 2 3 Bus width control IO23BWC R W 32 0 00000000 11 5 register ML675001 Series only 0x78100004 External ROM access control register ROMAC RW 32 0 00000007 11 6 0x78100008 External RAM access control register RAMAC R W 32 0x00000007 11 8 0x7810000C R W 32 0x00000007 11 10 0x78100010 2 RW 32 0x00000007 11 12 e M 2 11 2 RW 32 0x00000007 11 12 0x78180000 DRAM bus width control register DBWC R W 32 0 00000003 11 14 0x78180004 DRAM control register DRMC R W 32 0x00000000 11 15 0x78180008 DRAM characteristics control register DRPC R W 32 0 00000000 11 17 0 7818000 SDRAM mode register SDMD R W 32 0 00000001 11 18 0x78180010 DRAM command register DCMD R W 32 0x00000000 11 20 0 78180014 DRAM refresh cycle control register 0 RFSHO RW 32 0 00000000 11 21 0x78180018 DRAM power down
144. 1 only if the corresponding interrupt level is nonzero 8 22 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 14 IRQ Detection Mode Setting Register IDM This register specifies the interrupt detection modes level or edge detection and polarities negative or positive logic for interrupt request pairs from nIR22 nIR26 nIR28 and nIR31 The CPU has read write access to this register 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDM Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDMP30 IDM30 IDMP28 IDM28 IDMP26 IDM26 IDMP22 IDM22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Ox7BF00014 Access R W Access size 32 bits Notes 1 When switching triggers to edge detection write to either the IRQ clear IRCL register or the IRQ register A IRQA to initialize the edge detection circuitry before disabling masking 2 Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions e IDM22 bit 6 IDMP22 bit 7 IDM26 bit 10 IDMP26 bit 11 IDM28 bit 12 IDMP28 bit 13 IDM30 bit 14 IDMP30 bit 15 IDMn n 22 26 28 or 30 specifies the detect
145. 1 2221 Block ecce aterert eei Peu 22 2 22 2 Hlash Memory Programming nter ee eee P ede p ED Pe amin dece rt p een 22 3 22 2 1 General Description of Flash Memory Programming seen nennen 22 3 22 2 2 Flash Memory Programming Method Using the JTAG Debug Function eee 22 3 22 2 3 Flash Memory Programming Method Using the Built in Boot Program eee 22 5 223 Built in Boot Programi oct ete repperit Dr q e re eoe PE et rco S 22 7 223 1 Functional Description ideae ese 22 7 22 3 2 Operating Procedure bd aaa cedente du aa e ded teet t apad 22 7 22 3 3 Operating Environment ree tte pe Pp ee rito ea dri ha ia huayusa d 22 7 224 SDP Command Sequence Control for Built In Flash eene 22 8 224 1 Operational Description eo beo Rae trit rte ot P 22 8 22 4 2 Command Entries iine m te rhe i baie erit ees pi nA e ertet 22 0 2243 Read Reset Software Reset enda aet tenti Gus Geb u kusi FD E 22 9 22 44 Erase iiie este eem eei eoa m Ae de ite ry die on n I aiti 22 0 2245 edat ente eee euis qe oc ira diete 22 0 22 4 6 a AT E n Ie a te 22 0 224 7 IPro
146. 1 chmitt Input Buffer Threshold Voltage o r 121 Vuys 0 4 0 5 V 100 pA Vpp 0 2 High level output voltage H 4 mA 2 35 Low level output voltage lo 100 pA 0 2 Low level output voltage VoL lou 4 0 45 Low level output voltage lo 6 mA 0 45 Input leak current _ OV Vpp io 50 50 Vi OV Input leak current Pull up resistance of 200 3 10 50 gt Input leak current li Vi AVpp 5 5 Output leak current lio Vo Vpp io 50 50 Input pin capacitance Ci 6 Output pin capacitance Co 9 pF pin capacitance Cio 10 Analog to digital 5 320 650 Analog reference power converter operative supply current iss Analog to digital 1 2 converter stopped i Ipps 20 150 Current consumption 5 25 7 STANDBY 10 40 Current consumption IDDH_CORE 37 55 HALT io fosc 60 MHz 6 10 2 Current consumption RUN Ibo CL 30pF 75 120 x9 Ipp io 17 25 Notes XA 15 0 output pins except XA 15 0 All input pins except RESET RESET N pin with 50 pull up resistance Analog input pins AINO to AIN3 Analog to Digital Converter operation ratio is 2096 io or 0 V for input ports no load for other pins DRAM Controller bloc
147. 1 0 bits 2 and 3 These bits specify the bus width for the ROM region ROMBW 1 0 RT Description 3 2 0 0 Not physically present Access to bank region disabled Access from CPU produces abort response 0 1 8 bits only for ML675001 series reserved for ML674001 series 0 16 bits 1 1 reserved Note The only bus width supported is 16 bits Operation is not guaranteed for a setting labeled reserved ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller e RAMBWTL I 0 bits 4 and 5 These bits specify the bus width for the SRAM region RAMBWT 1 0 ees Description 5 4 0 0 Not physically present Access to bank region disabled Access from CPU produces abort response Access from DMA controller produces error response 0 1 8 bits only for ML675001 series reserved for ML674001 series 0 16 bits 1 1 reserved Note The only bus width supported is 16 bits Operation is not guaranteed for a setting labeled reserved e IO01BWI 1 0 bits 6 and 7 These bits specify the bus width for I O bank 0 1 IO01BW 1 0 END Description 7 6 0 0 Not physically present Access to bank region disabled Access from DMA controller produces error response 0 1 8 bits 1 0 16 bits 1 1 reserved Note Operation is not guaranteed for a setting labeled reserved IO23BW 1 0 bits 8 and 9 Thes
148. 1 0 output hold time 5 tuc 2 24 11 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics m DRAM Access Timing 2 25 to 2 75V 3 0 to 3 6V Ta 40 to 85 C SDRAM I Item Symbol tons Minimum Typical Maximum Unit Notes XSDCS N dela SDRAM j tspcsp 0 5 0 550 5 The DRPC register specifies the SDRAM access parameters XSDCKE delay SDRAM tspcxep 0 5tspc O 5tspc 5 tRAS tRCD tRP tDPL For del ar T further details refer to section elay 9150 11 2 9 of chapter 11 SDRAM pF 021506 5 5 O 5tspc XRAS N delay SDRAM tepRAsD O 5tspc 5 5 Nsp1 tRCD O 5tspc XCAS N delay SDRAM tepcAsp O 5tspc 45 Nsp2 tRAS RASCAS minimum delay SDRAM Nspitspc tRP RAS active time t 20 2 E SDRAM SDRAS SD2 SDC RAS precharge time t SS B SDRAM SDRP SD3 SDC ns XWE N delay SDRAM tspwep 30 pF 0 5tspc 0 5tspc 4 XD 15 0 input setup time t 14 SDRAM SDXDIS XD 15 0 input hold time t 0 2 _ SDRAM SDXDIH XA 15 0 output dela CORAM 5 0 5tspc O 5tspc 5 XD 15 0 output delay SDRAM O 5tspc O 5tspc 6 XD 15 0 output hold time t 08 2 SDRAM SDXDOH 3
149. 1 3 2 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller Operational Description Bus Width The bus width control BWC register offers two bus width settings 0 and 16 for the external ROM and SRAM banks regions and three 0 8 and 16 for the external I O banks Note A bus width setting of 0 means not present After a reset the contents 0x0008 specify that only ROM is present accessible over a 16 bit bus banks regions support 16 bit access The table shows which addressable regions support 8 bit access as well Operation is not guaranteed for a bank region with an X in the 8 bit column Bus Width Bank Region 8 bits 16 bits ML674001Series ML675001Series ML674001Series ML675001Series ROM X O RAM X O O O 100 101 102 SDRAM X X EDO DRAM If the data size differs from the bus width access uses the bus width A word 32 bit read over a 16 bit bus for example becomes two reads first the lower 16 bits and then the upper ones As a result this 32 bit access produces two XOE N or XWE N output signals For further details see the timing charts in Figure 11 1 Figure 11 2 etc ROM SRAM Control 1 Toaccess SRAM set the SRAM bus width to 16 bits in the BWC register 2 Specify the XOE N XWE N pulse width in the ROMAC or RAMAC register After a reset the ROM bus width is 16 bits 11 25
150. 1 4 1 8 1 16 or 1 32 Functional blocks Stop clock signals to individual function blocks 1 3 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 2 Functional Blocks 1 2 1 ML674001 series Block Diagram 5 PIOC 6 2 XA 23 19 TDO XA 18 0 XD 15 0 PIOC 7XWR TEK InternalRAM XOE N 32KB XWE N InternalFlash ROM XBWE N 1 0 ML67Q4002 256KB 7 I 5 XIOCS_NI2 XIOCS NI3 XBS N 1 0 PIODJOJ XWAIT PIOD TI XCAS PIOD 2 XRAS_N PIOD 3 XSDCLK PIOD A XSDCS PIOD BI XSDCKE PIOD 8 XDQM 1 XCAS_NI 1 PIOD 7 XDQM 0 XCAS_N 0 Internal amp External Memory controller AMBA AHB bus PIOB 0 DREQ 0 PIOB 2 DREQ 1 PIOB 1 DREQCLR O PIOB 3 DREQCLR 1 PIOB b 4 TCOUT 1 0 PIOC 1 0 PWMOUT 1 0 RESET N PIOB GJ STXD PIOB 7 SRXD PIOA OJ SIN WDT PIOAHT SOUT PIOA 2 CTS PIOA 3 DSR 8 _ PIOAMIIDCD dd PIOA BJDTR PIOA G RTS PIOA 7 RI 5 AIN 3 0 VREF OSCO OSC1_N Al PIOE 9 FIQ N mmm 4 ncnronous PIOE 8 5 EXINT 3 0 y S10 u PIOE 1 SDI PIOE 2 SDO gu PIOE O J SCLK m 2 PIOE 3 SDA CKD PIOE 4 SCL AVDD 42 PIOA 7 0 AGND GPIO PIOB 7 0 TEST PIOC 7 0 CKOE N PIOD 7 0 CKO PIOE 9 0 DRAME N BSEL 1 0 FWR JSEL Figure 1 1 ML674001 series Block Diagram 1 2 2 TDI TDO nTRST TMS TCK Cache Mem 8KB Cache Cont AHB Bridge AMBA AHB bus IRC AMBA AP
151. 11 12 12 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 7 Transfer Destination Address Registers DMACDADO and DMACDAD1 These registers specify the transfer destination address for the corresponding DMA channel The DMA controller starts writing data for the DMA transfer to the address in this register The DMA controller increments the address by the transfer size in bytes after each successful write if the transfer destination is an incremental address device For a fixed address device however the address does not change The program has read write access to these registers The contents after a reset are 0x00000000 DMACDADO to 1 After a reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CDAD 31 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CDAD 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x7BE0010C 0x7BE0020C CH1 Access R W Access size 32 bits Notes The DMA controller increments the destination address DMACDADO or 1 by the transfer size in bytes if the corresponding device type so specifies The hardware enforces alignment by internally ignoring the lowest address bits as appropriate for the transfer size but reading an address register returns those bits exactly as written Example Writing add
152. 11 2 12 DRAM Refresh Cycle Control Register 0 RFSHO This register specifies the DRAM refresh period relative to that specified in the RFSHI register double or same The program has read write access to this register Access size 32 bi Notes ts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RFSHO PEL Liw E IIS pei de Ik Lw red n cava E s E Aftera reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 crt 205 25 EE _ _ mee _ _ _ _ RCCON 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78180014 Access R W These bits are reserved for future expansion They return 0 for reads Writes to them are ignored DRAM controller operation is not guaranteed after writes to this register when there is no DRAM physically present DBWC 0 Bit Descriptions RCCON bit 0 This bit specifies the DRAM refresh period relative to that specified in the RFSHI register RCCON Description 0 Refresh using twice clock period specified in RFSH1 register 1 Refresh using the clock period specified in RFSH1 register 11 21 ML 674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 13 DRAM Refresh Cycle Control Register 1 RFSH1 This register specifies the divider for deriving the DR
153. 12 14 0x7BE00214 DMA transfer complete status clear DMACCINT1 w 32 2 12 15 register Ox7BF00004 IRQ clear register IRCL 32 8 20 Ox7BF00010 IRQA register IRQA R W 32 0x00000000 8 21 Ox7BF00014 IRQ detection mode setting register IDM R W 32 0 00000000 8 23 Ox7BF00018 Interrupt level control register ILC R W 32 0 00000000 8 24 6x6001000 A Aog digia converter conto ADCONO RW 16 0 0000 21 3 register 0 pontrol ADCON1 RW 16 0 0000 21 5 register 1 001008 9 996 digital converter control ADCON2 RW 16 0x0003 21 6 register 2 18109 10 019181 converter interrupt RW 16 0 0000 217 control register 010107 converte orcad ADFINT RW 16 0 0000 21 9 interrupt register 1044 Pag diga converter result ADRO RW 16 0 0000 21 10 register 0 xB6001016 converter result ADR1 RW 16 0 0000 21 10 register 1 alooto digital converter result ADR2 RW 16 0 0000 21 10 register 2 08600 020 P result ADR3 RW 16 0 0000 21 10 register 3 0xB7000000 Port function select register GPCTL R W 16 0x0000 13 10 0xB7000004 Block clock control register BCKCTL R W 16 0x0000 7 4 0xB700000C ROM select register ROMSEL RW 16 0 0000 3 5 0xB7800000 12 bus control register I2CCON R W 8 0x00 20 3 0xB7800004 I2C bus slave address mode register I2CSAD R W 8 0x00 20
154. 15 0 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7F00004 CHO 0xB7F00024 CH1 0xB7F00044 CH2 OxB7F00064 CH3 0xB7F00084 OxB7F000A4 CH5 Access R W Access size 16 bits 15 9 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 6 Timer Counter Register TIMECNTO to TIMECNTS These registers represent the 16 bit up counters for the timers Reading one returns the current counter contents The CPU has only read access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMECNTO to 5 TIMECNT 15 0 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7F00008 CHO 0xB7F00028 CH1 0xB7F00048 2 OxB7F00068 CH3 0xB7F00088 CH4 OxB7F000A8 CH5 Access R Access size 16 bits 15 10 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 7 Timer Compare Registers TIMECMPO to TIMECMP5 A match between the contents of a timer counter register TIMECNTX and those of the corresponding TIMECMPx register triggers an interrupt request and reloads from the corresponding timer base register TIMEBASEX The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMECMPO to 5 TIMECMPT 15 0 Afterareset 1 1 1 1 1 1 1 1 1 1 1 1
155. 19 2 Transmit Operation Timing Diagram LSB First SSIOBUF write signal SSIOBUF read signal Www BUSY flag ITP Si hi ES s Internal shift counter 0 1 2 3 4445 6 AOXI A2 A3 X4 X5 A6 AT Receive data SDI pin 03 04663666 vor 61961 0120 361901901967 Transfer signal to SSIOBUF Oo Receive complete interrupt r Figure 19 3 Receive Operation Timing Diagram LSB First 19 12 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 3 4 Interrupt Signal Figure 19 4 shows the logic of the interrupt signal The interrupt causes bit 2 to bit 0 of the SSIOINT register are masked or enabled by bit 2 to bit 0 of the SSIOINT register respectively and the outputs bit 2 to bit 0 are ORed The logically ORed output is the synchronous SIO interrupt signal 0 1 2 SSIOINT Interrupt signal nIR14 0 1 2 SSIOINTEN Figure 19 4 Logic of Interrupt Signals 19 13 Chapter 20 I2C ML674001 Seies ML675001 Series User s Manual Chapter 20 DC Chapter 20 2 20 1 Overview This LSI has one channel of built in I2C bus interface that conforms to the standard I2C bus specifications The I2C block is designed to work as a single master Features Communication mode Master transmitter master receiver no slave function Communication speed 100 Kbps Standard mode 400 Kbps Fast mode Addressing format 7 bits 10
156. 2 2 6 D D ote a p E eame Hat b n e A E 2 3 2 8 1 ARM State Registers eain cities da eto n EC me d p E o Pn 2 3 2 8 2 THUMB State Registers een mato Een PERDE 2 5 2 8 3 Relationships Between ARM and THUMB State Registers eese 2 6 2 8 4 Accessing Upper Registers from THUMB nre 2 6 2 9 Program Status Registers rea op ete cer re oh p EE e eterne ier eden 2 7 2 9 1 Condition Code eoe eere ite pe pre Ea ee eere op 2 7 2 9 2 Control nene ori eee a EO 2 2 93 R serv d Bits eee decis delebo denis EAE SE pee ei a ipee eere 2 8 210 Instruction Set Features eile tete du etie tete e e Ha o 2 9 2 10 1 ARM Instruction Set uite eel Ere tete tna ee etnies 2 9 2 10 2 THUMB Instr uction Set ertet tear 2 9 2 11 Addressing Modes on oU REIR EEUU Soha eo eb baeo tere bade doch eR 2 10 211 1 Load StoreInstrictions soi s aD tete E EEE eee he EE ES RE ELSE RENE 2 10 2 11 2 Multiple Load Store Instructions ia sninen eiere ereer a EEES SEEE E EE A E 2 10 2 12 Ex epti onSu E 2 11 2 12 1 Switching to Exception Handler roe 2 11 2 12 2 Returning from Exception 4 2 11 2 12 3 Summary of Exception Switching eese eene nennen e
157. 2 5 3 XOE N delay 0 5 CPU Access SRAM ROM toep 1 tuc 1 tuc R27 1 SRAM ROM twED 2 2 XROMCS N XRAMCS N nea OE WE pulse width access time1 _ tuc SRAM ROM 5 2 5 WRITE ACCESS OE WE pulse width 0 5 XROMCS N XRAMCS N access time2 nns nga nns ngo nrs 2 OE WE pulse width SRAM ROM CSW2 CL tuc 3 5 nas ns 05 WRITE ACCESS 30 pF XBWE N 1 0 dela 4 twELHD ng2 4 tuc 2 XBWE N 1 0 hold time SRAM ROM Oe vr 9 2 XWE_N pulse width SRAM ROM toEwEW luc 4 luc 2 XOE N pulse width SRAM ROM toew 2 Nr3tuc 4 2 1 ARM ACCESS XBS N 1 0 delay i 24 5 SRAM ROM oi XBS N 1 0 output hold TCR B time 1 SRAM ROM RUNS 5 N 1 0 output hold I time 2 SRAM ROM din ose 23 0 delay SRAM ROM txan um 9 XA 23 0 output hold time t 1 SRAM ROM d TRU XA 23 0 output hold time t 05t 2 HC 2 SRAM ROM 24 8 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics SRAM ROM continued Item Symbol Minimum Maximum Unit Notes XD 15 0 input setup time SRAM ROM txpis 19 ARM ACCESS
158. 2 7 1 0 2 16 8 1 1 0 reserved Operation is not guaranteed for a setting labeled reserved 1 1 1 4 24 11 11 11 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 6 External I O Bank 2 3 Access Control Register IO23ACX 1 IO23ACY 2 2 After reset This register controls the access timing for I O bank 2 3 The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ 23 _ 275 0 _ _ _ _ e E 1 23 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Address 0x78100010 IO23ACX 1 0x7830000C IO23ACY 2 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored When switching operating frequencies adjust the contents of this register at the lower frequency that is AFTER a change from high speed to low speed and BEFORE one from low speed to high speed 1 ML674001 Series only 2 ML675001 Series only Bit Descriptions IO23TYPE 2 0 bits 0 to 2 These bits specify the access timing for I O bank 2 3 This table is applied only to ML674001 series
159. 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mp E 2I c En _ e _ CIL 7 1 225 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000018 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions e CIL 7 1 bits 1 to 7 A 1 in bit n indicates that a level n interrupt request is currently being processed CIL 7 CIL 6 CIL 5 CIL 4 CIL 3 CIL 2 CIL 1 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt level 7 level 6 level 5 level 4 level 3 level 2 level 1 The interrupt controller masks pending interrupt requests at or below the level corresponding to the highest 1 bit in this set CIL n goes to 1 when the program reads the interrupt source number for a level n interrupt request from the IRN register CIL n returns to 0 when the program writes 1 to it Alternatively writing to the current interrupt level clear CILCL register clears the highest 1 bit in this set An interrupt handler must use one of these two writes to reset the highest 1 bit to 0 before returning 8 13 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 8 Interrupt Level Control Register O ILCO This
160. 25 11 3 3 Banks Control nce eee i tee bene t DE RD ed Ebr re o debet e dee PS 11 26 11 34 DRAM 11 27 11 3 5 Access Timing Parameters for DRAM 11 31 114 Access Timing usa dO ap het bake G A bee tr P P RR be ber trei edes 11 34 114 1 Accessing External Devices eed tte bte ar Lx bless cede deter et edge hod 11 34 ITE T 1 External ROM RAM treat eter dtr tee d uta iet 11 34 113 12 External Bank Access nint SS Sasam AA 11 35 11 4 1 5 DRAM ACCESS erect ete e IE m ide tuU a ts 11 37 14 24 SDRAM ACCESS ana ama he tut in ae een iw a nire 11 39 11 5 DRAM Power Management 11 42 11 6 Sample External Memory Connections 11 43 11 6 1 GQonn c ng ROM obedece rae i aee trit i eite aequa rutas 11 44 11 6 2 Connecting SRAM e oC RGB t niin B u Gas a Saa uqata 11 46 116 3 Connecting EDO DRAM et eet RR 11 48 11 6 4 Connecting SDRAM notae rettet ecrit hi fes eeepc be surest Probe dc e 11 50 ML674001 Series ML675001 Series User s Manual Table of Contents Chapter 12 Direct Memory Access Controller DMAC lamp 12 1 1231 1 7 Components eee eee ette spec ate etia nni entere n id reete 12 2 1212 PIL LIS iion hane i nd pec oo augu ree
161. 2AA 55 555 80 555 AA 2AA 55 555 10 4 555 2 55 555 EO XXX 00 Protect Chip Protect 4 555 AA 2AA 55 555 DO XXX 00 DIOS 4 555 2 55 555 EO XXX 01 Cancel Note 1 Address format XA11 to hexadecimal notation XA17 to XA12 are don t cares Note 2 Data format DQ7 to 000 hexadecimal notation 0015 to 008 are don t cares Note 3 RA Read address PA Program address SA Sector address XA17 to XA11 RD Read data PD Program data SD Sector data Note 4 e RA Read address RD Read data Refer to section 22 4 8 or 22 4 9 Caution Be sure to use half word 16 bit access for the command sequence 22 8 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 22 4 2 Command Entries For command entries use the JEDEC conformed SDP command sequence After the SDP command sequence is finished the selected operation is initiated automatically If an incorrect address or data is entered in the SDP command sequence the SDP command sequence is suspended and the mode returns to read mode 2243 Read Reset Software Reset The Read Reset command is used to end Software ID Entry Verify Protect or stop an erase or program operation A Read Reset operation is performed by entering an SDP command of either one cycle or three cycles to the command register and the mode returns to the read m
162. 48 Timer 2 counter register TIMECNT2 R 16 0x0000 15 10 OxB7F0004C Timer 2 compare register TIMECMP2 R W 16 OxFFFF 15 11 OxB7F00050 Timer 2 status register TIMESTAT2 R W 16 0 0000 15 12 OxB7F00060 Timer 3 control register TIMECNTL3 R W 16 0 0000 15 7 OxB7F00064 Timer 3 base register TIMEBASE3 R W 16 0 0000 15 9 0 7 00068 Timer counter register TIMECNT3 R 16 0x0000 15 10 OxB7F0006C Timer compare register TIMECMP3 R W 16 OxFFFF 15 11 OxB7F00070 Timer 3 status register TIMESTAT3 R W 16 0 0000 15 12 OxB7F00080 Timer 4 control register TIMECNTL4 R W 16 0 0000 15 7 OxB7F00084 Timer 4 base register TIMEBASE4 R W 16 0 0000 15 9 OxB7F00088 Timer 4 counter register TIMECNT4 R 16 0x0000 15 10 4 ML674001 Series ML675001 Series User s Manual Appendixes Address Name Abbreviation R W Size Initial Value Ref Pages OxB7F0008C Timer 4 compare register TIMECMP4 R W 16 OxFFFF 15 11 OxB7F00090 Timer 4 status register TIMESTAT4 R W 16 0 0000 15 12 OxB7FOOOAO Timer 5 control register TIMECNTL5 R W 16 0 0000 15 7 OxB7F000A4 Timer 5 base register TIMEBASE5 R W 16 0 0000 15 9 OxB7F000A8 Timer 5 counter register TIMECNT5 R 16 0x0000 15 10 OxB7F000AC Timer 5 compare register 5 R W 16 OxFFFF 15 11 OxB7FOOOBO Timer 5 status register 5 R
163. 5 to 8 bits LCR 1 0 ee Description LCR 1 LCR 0 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits LCR 2 bit 2 This bit specifies the number of stop bits for transmitting characters LCR 2 Description 0 1 stop bit 1 2 stop bits 1 5 for character length 5 LCR 3 bit 3 This bit controls the use of parity LCR 3 Description 0 No parity 1 Parity used LCR A4 bit 4 This bit specifies even or odd parity This setting is only valid however when parity is enabled LCR 3 717 LCR 4 Description 0 Odd parity 1 Even parity 18 11 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte LCR 5 bit 5 LCR 5 bit 5 Stick parity A 17 in this bit sets all parity bits to a fixed value the inverse of the bit in LCR 4 This setting is only valid however when parity is enabled LCR 3 1 The receiver can therefore check the parity using a known state LCR 5 3 2 Description LCR 5 LCR 4 LCR 3 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Fixed parity 1 1 1 1 Fixed parity 0 LCR 6 bit 6 Break control Setting this bit to 1 sends a break signal by driving the serial output SOUT at Low level or spacing state Setting this bit to 0 disables the break This break control function affects only SOUT maski
164. 6 us Table 18 1 Sample CCLK ACKSEL Combinations CCLK ACKSEL MHz 01 10 11 60 133 ns 1 33 120 ns 1 240 ns 20 100 ns 1 200 ns 400 ns 16 120 ns 1 240 ns 480 ns 8 250 ns 500 ns 1000 ns 2 1000 ns Note The shading indicates combinations that produce periods out of range 1 ML675001 series can be set up 21 6 ML674001 Seies ML675001 Series User s Manual Analog to Digital Converter Chapter 21 21 2 4 Analog to Digital Converter Interrupt Control Register ADINT ADINT After a reset This register contains analog to digital converter interrupt settings The program has read write access to this register The contents after a reset are 0 0000 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 _ s _ _ _ _ ADSNIE INTST INTSN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB600100C H Access R W Access size 16 bits Note Bit Descriptions INTSN bit 0 A in this bit indicates completion of one cycle through the specified channels that is that channel 3 conversion in scan mode is complete These bits are reserved for future expansion They return 0 for reads Writes to them are ignored INTSN Description 0 Scan not complete channel 3 conversion in scan mode not complete 1 Scan complete channel 3 conversion in scan mode com
165. 7A01010 GPIPA 0xB7A01030 GPIPB 0xB7A01050 GPIPC 0xB7A01070 GPIPD 0xB7A01090 GPIPE Access R W Access size 16 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions e GPIPA 7 0 GPIPB 7 0 GPIPC 7 0 GPIPD 7 0 bits 0 to 7 GPIPE 9 0 bits 0 to 9 These bits specify the triggering edge for the corresponding GPIO pin at the individual pin level GPIPA 7 0 GPIPB 7 0 GPIPC 7 0 GPIPD 7 0 Description GPIPE 9 0 0 Falling edge of input signal triggers interrupt request 1 Rising edge of input signal triggers interrupt request ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 2 6 Port Interrupt Status Registers GPISA GPISB GPISC GPISD and GPISE These registers contain flags indicating the sources for pending interrupt requests Writing 1 to a bit resets it to 0 Writes of 0 are ignored The register contents after a reset are 0 0000 GPISA GPISB GPISA 7 0 GPISB 7 0 GPISC 7 0 GPISD 7 0 GPISE 9 0 GPISC GPISD BR 222 5 GPISE GPISE uses bit9 amp bit8 For other GPISx bit9 amp bit8 are Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 7 01014 GPISA 0xB7A01034 GPISB 0xB7A01054 GPISC 0xB7A01074 GPISD 0xB7A01094 GPISE Access R W Access size 16 bits Note These bits are reserved
166. 7FFFFFF is mapped to the FLASH ROM for use as the boot device after a reset Settings to the remap control RMPCON register and the ROM select register ROMSEL can remap bank 0 to built in FLASH ROM 10 2 Chapter 11 External Memory Controller Chapter 11 11 1 Overview ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller External Memory Controller The external memory controller built into this LSI is for connecting DRAM ROM SRAM I O devices and other external devices to this LSI Supported devices include the following e Asynchronous ROM e Asynchronous SRAM e Flash memory e O devices SDRAM EDODRAM 11 1 1 Pin List Table 11 1 lists the pins for connecting devices to this controller Table 11 1 Pin Name y o Function 2 XA 23 19 O External address bus PIOC 6 2 XA 18 0 O External address bus XD 15 0 External data bus XROMCS O External ROM chip select XRAMCS External RAM chip select XIOCS I O Ochip select XIOCS N 1 O 1 chip select XIOCS N 2 I O 2 chip select XIOCS N 3 l O3chip select Output enable XWE Write enable XBS N 1 0 External bus XBUS byte select XBWE 0 Write enable LSB XBWE N 1 O Write enable MSB XSDCS O SDRAM chip select PIOD 4 XSDCLK O SDR
167. 7Q4003 512 Kbyte 256K x 16 bits ML67Q5002 256 Kbyte 128K x 16 bits ML67Q5003 512 Kbyte 256K x 16 bits e Flash memory can be read and programmed with a single power supply e Built in flash memory programming methods Programming of flash memory using the JTAG Joint Test Action Group debug function Programming of flash memory using the built in boot program e Programming unit 2 bytes e Erasing units Sector erase 2 Kbyte sector Block erase 64 Kbyte block Chip erase Entire area in a batch e High speed programming Programming time 2 bytes 20 usec e High speed erasing Erase time Sector erase block erase 25 msec Chip erase 100 msec e Write protect function Block protect 16 Kbyte on the top address side Chip protect Entire flash memory area e Write protect unprotect time Block protect chip protect 20 usec Block unprotect chip unprotect 25 msec e Control by JEDEC conformed SDP Software Data Protect command sequence e Highly reliable reading writing Sector writing 1000 times Data holding period 10 years 22 1 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 2211 Block Diagram Figure 22 1 gives a block diagram for the Built In Flash Memory FlashROM Figure 22 1 Block Diagram for the Built In Flash Memory 22 2 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 22 2 Flash Memory Programming 22 2 1 General Descript
168. 8 After a reset Indeterminate Address 0 7 00004 Access R W Access size 8 bits 18 22 18 3 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte Description of Operation The registers LCR IER DLL DLM and MCR control serial interface operation These control registers specify the character length number of stop bits parity baud rate modem interface and other parameters They can be written to in any order except that IER must come last because it enables interrupts Once the serial interface has been configured for operation these registers can be updated anytime that the interface is not transferring data 18 3 1 nUARTINT WR THR Transmitting Data Figure 18 2 gives the timing for transmitting data Writing data to the UARTTHR register sends that data to the transmit shift register via the transmit queue Within 16 baud rate clock cycles after the THRE bit goes to 1 the hardware transmits the start bit and the data bits one bit at a time from the lowest bit If the character length is 7 bits the hardware does not transmit the top bit If the LCR 3 bit in the UARTLCR register enables parity the hardware then transmits the parity bit Finally the hardware transmits a stop bit to complete the frame When the hardware finishes transmitting the data the LSR 5 bit in the UARTLSR register goes to 17 to indicate that the hardware is ready to transmit more data Writing a
169. 8 bits Note This is a reserved bit for future expansion during writing In this LSI O is read during reading and this bit is ignored Explanation of Bits e 12 bit 0 This bit masks the I2C interrupt request I2CMF Description 0 Interrupt enabled 1 Interrupt masked 20 9 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 20 2 7 I2C Bus Transmit Receive Data Register I2CDR The I2CDR register sets transmit data or stores received data data in this register can be read and written by programs The value at the time of reset is 0 00 When reading received data read it before transmitting or receiving the next data Set or read the IDCDR register before setting the I2CCON register Read the I2CDR register following completion of byte data transfer after setting the I2CCON register 7 6 5 4 3 2 1 0 I2CDR I2CD 7 0 At reset 0 0 0 0 0 0 0 0 Address 0 7800018 Access R W Access size 8 bits 20 10 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 2 8 2C Bus Transfer Speed Counter I2CBC The I2CBC register sets counter values in the counter that generates the transfer timing from HCLK to the I2C bus The data in this register can be read and written by programs The value at the time of reset is 0x00 7 6 5 4 3 2 1 0 2 I2CBC 6 0 At reset 0 0 0 0 0 0 0 0 A
170. 818000C SDRAM mode register SDMD R W 32 0 00000001 0x78180010 DRAM command register DCMD R W 32 0 00000000 0x78180014 DRAM refresh cycle control register 0 RFSHO R W 32 0x00000000 0x78180018 DRAM power down control register RDWC Ww 32 0x00000003 0x7818001C DRAM refresh cycle control register 1 RFSH1 RAW 32 0x00000000 1 ML675001 Series only 2 ML674001 Series only ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 Register Descriptions 11 2 1 Bus Width Control Register BWC This register specifies the external data bus widths for four banks regions The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ _ _ _ _ oe bz ue ce 2 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32852 IO01BWI1 0 RAMBW 1 0 1 01 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Address 0x78100000 Access R W Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored 1 This IO23BW 1 0 register exists only in ML674001 series In ML675001 series it becomes the treatment of reserved Bit Descriptions e ROMBWT I
171. ADINT R W 16 0x0000 register 0xB6001010 Analog to digital converter forced interrupt ADFINT R W 16 0x0000 register 0xB6001014 Analog to digital converter result register 0 ADRO R W 16 0x0000 0xB6001018 Analog to digital converter result register 1 ADR1 R W 16 0x0000 0xB600101C Analog to digital converter result register 2 ADR2 R W 16 0x0000 0xB6001020 Analog to digital converter result register 3 ADR3 R W 16 0x0000 Note Writing to a result register ADRO to ADR7 while the analog to digital converter is in operation invalidates the contents of the entire set 21 2 21 2 Control Register Descriptions 21 2 1 ADCONO After a reset ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter Analog to Digital Converter Control Register 0 ADCONO This register controls scan mode operation The program has read write access to this register The contents after a reset are 0 0000 15 14 13 12 11 10 9 8 7 6 5 4 1 0 mU qum seem 2 5 ADRUN ADSNM 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB6001000 H Access R W Access size 16 bits Note It needs 2HCLK 2CCLK for ADCONO register write recovery time Bit Descriptions ADSNM 1 0 bits 1 to 0 This field specifies the first channel to scan The last is always 7 ADSNM B Channels Scan order 0 0
172. AM clock PIOD 3 XSDCKE O SDRAM clock enable PIOD 5 XCAS_N O SDRAM column address strobe PIOD 1 XRAS N Row address strobe PIOD 2 Data mask for SDRAM or MSB column address strobe XDQM 1 XCAS N 1 for EDO DRAM PIOD 6 Data mask for SDRAM or LSB column address strobe 0 5 N 0 for EDO DRAM PIOD 7 XWAIT Memory wait indicator PIOD 0 XWR O External bus XBUS transfer direction ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 1 2 Register List Address Name Abbreviation R W Size Setting 0x78100000 Bus width control register BWC R W 32 0x00000008 0x78300000 1 External bank 2 3 Bus width control register IO23BWC R W 32 0 00000000 0x78100004 External ROM access control register ROMAC R W 32 0 00000007 0x78100008 External SRAM access control register RAMAC R W 32 0x00000007 0x7810000C External I O bank 0 1 access control register 1001AC RW 32 0x00000007 0x78100010 2 External bank 2 3 access control register X 1 23 RAW 32 0x00000007 0x7830000C 1 External I O bank 2 3 access control register Y 1 2 R W 32 0x00000007 0 78180000 DRAM bus width control register DBWC R W 32 0x00000003 0x78180004 DRAM control register DRMC R W 32 0 00000000 0x78180008 DRAM characteristics control register DRPC R W 32 0x00000000 0x7
173. AM refresh period from the CCLK period The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ue ize E e Ex cun ED 42 229 EX l After 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 6 5 4 RFSEL1 10 0 0 0 0 0 0 0 0 0 0 0 Address 0x7818001C Access R W Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them ignored Bit Descriptions RFSEL1 10 0 bits 0 to 10 These bits specify the divider for deriving the DRAM refresh period from the CCLK frequency using the following formula refresh clock period CCLK RFSEL1 10 0 Note The RFSH1 register should be set before modifying CCLK divider settings 11 22 CCLK MHz ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller The following table lists the results for typical combinations of the setting and CCLK frequency The setting must be within the range shown in this Table 0x00000008 to 0x00000406 Choose it to produce a refresh frequency of at least 32 kHz or 64 kHz RFSEL1 setting Divisor 1000 00 1250 00 2500 00 3125 00 4125 00 500 00 625 00 1250 00 1562 50 2062 50 258 06
174. Access size 32 bits Bit descriptions The cache memory is initialized flushed when any value is written into the FLUSH register Notes The cache memory is not initialized for the ways that have been locked e Since no write back operation is made during initialization of the cache memory if it is necessary to return the data in the cache memory to the actual memory it will be necessary to carry out the writing back using a separate software procedure See Section 9 5 2 Since the CPU will be made to wait until the cache memory initialization has been completed instruction of writing to the FLUSH register will take about 128 instruction cycles 9 5 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 3 Description of Operations 9 3 1 9 3 2 9 3 3 9 3 4 Initialization of Cache Memory It is necessary to initialize the cache memory before using this cache controller If the cacheable setting is made without initializing the cache correct values may not be written to or read from the memory Cacheable Non cacheable Setting In this LSI the entire memory space 4GB of the CPU is split into 128MB segments called banks There are 32 banks from Bank 0 to Bank 31 See Chapter 3 Address Map The cacheable non cacheable setting by the CACHE register can be made for each bank separately banks for which the cacheable setting can be made are the banks Bank 0 8 to 13 24 to 29
175. B bus RESET N PIOB 6 TXD PIOB 7 RXD 05000 OSC1_N PIOE 9 FIQ_N PIOE 8 5 EXINT N 3 0 VDD CORE VDD 10 GND AVDD AGND PLLVDD PLLGND TEST TEST CKOE N CKO DRAME N BSEL 1 0 FWR JSEL CLKMD 1 0 7 ML674001 Series ML675001 Series User s Manual ML675001 series Block Diagram Internal MCP FLASH ROM ML67Q5002 256KB ML67Q5003 512KB External Memory controller Internal RAM 32KB Boot ROM DMAC 4 Exp Bridge PWM WDT 2 16550 bus 4 N 16bit x 2ch N e 0 N BB i a Chapter 1 Introduction PIOC 6 2 XA 23 19 XA 18 0 XD 15 0 PIOC 7 XWR XBWE N 1 0 XROMCS N N XIOCS N 3 0 XBS 1 0 PIOD 0 XWAIT PIOD 1 PIOD 2 XRAS_N PIOD 3 XSDCLK XSDCS PIOD 5 XSDCKE PIOD 7 6 XDQM 1 0J XCAS N 1 0 ExplOC 2 PIOB 0 0 PIOB 2 DREQ 1 2 PIOB 1 DREQCLR 0 PIOB 3 DREQCLR 1 PIOB 4 5 TCOUT 1 0 16bit x 6ch PIOC 1 0 PWMOUT 1 0 PIOA 0 SIN PIOA 1 SOUT PIOA 2 CTS PIOA 3 DRS 8 PIOA 4 DCD PIOA 5 DTS PIOA 6 RTS PIOA 7 RI PIOE 0 SCLK PIOE 1 SDI PIOE 2 SDO PIOE 3 SDA PIOE 4 SCL AIN 3 0 VREFP VREFN PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 PIOE 9 0 Figure 1 2 ML675001 series Block Diagram
176. C to the WDTCON register then starts counting up from zero Additional writes of the same value reset the counter to zero Failure to reset the counter in a timely fashion produces overflow and an interrupt request This configuration does not generate system reset signals Watchdog Timer Operation Setting the ITM bit in the WDTBCON register to 0 produces watchdog timer operation Writing 0x3C to the WDTCON register then starts counting up from zero After that alternately writing 0xC3 0 3 resets the timer to zero Failure to reset the counter in a timely fashion produces overflow and an interrupt or system reset request In a typical application timer overflow should be avoided entirely except as an indication that the program has run out of control Starting Timer Specifying the operation mode and other settings in the count operation WDTBCON register and then writing 0x3C to the watchdog timer control WDTCON register starts counter operation From that point onward the program must reset the counter to zero at regular intervals by writing to WDTCON 0xC3 and 0x3C alternately for watchdog timer operation or just Ox3C for interval timer operation Failure to reset the counter in a timely fashion produces overflow and an interrupt or system reset request as specified by the OFINTMODE bit in the WDTBCON register Note however that interval timer operation only produces interrupt requests Watchdog timer operation continue
177. DD IO VDD IO power supply 6 C2 XDIO y o External data bus 7 D1 XD 1 y o External data bus 8 XD 2 y o External data bus 9 02 XD 3 External data bus 10 E1 XD 4 External data bus 11 E4 GND GND GND 12 E2 NC NC ML674001Series CLKMDO Clock mode input ML675001Series 13 F1 y o External data bus 14 F2 XDI6 y o External data bus 15 F4 GND GND GND 16 XD 7 y o External data bus 17 G2 NC NC ML674001Series CLKMD1 Clock mode input ML675001Series 18 G4 VDD IO VDD power supply 19 G3 XD 8 y o External data bus 20 G1 XD 9 y o External data bus 21 H3 XD 10 External data bus 22 4 VDD CORE VDD CORE power supply 23 H2 NC NC 24 J2 XD 11 External data bus 25 H1 XD 12 y o External data bus 26 4 VDD IO VDD power supply 27 K2 XD 13 External data bus 28 J1 XD 14 External data bus 29 J3 XD 15 y o External data bus 30 External address output 31 K1 XA 1 External address output 32 L2 XA 2 External address output 33 XA 3 External address output 34 L1 GND GND GND 35 M2 XA 4 External address output 36 M1 XA 5 External address output
178. DD pll Supply off Delay tvDDPLL_OFF 0 ns VDDio Supply off Delay tvppio_oFF 0 ns 24 14 B Clock Timing 2 25 to 2 75 Vpp 3 0 to 3 6V Ta 40 to 85 C ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics Item Symbol Minimum Typical Maximum Unit Notes Input Clock frequency fc 5 56 MHz Input Clock cycle time tc 17 9 200 Input Clock High level tou 7 pulse width Input Clock Low level n ns pulse width tor Input Clock Rise time tcn 4 For external clock input Input Clock Fall time tcr 4 XSDCLK frequency fspc 0 625 60 MHz The same frequency as HCLK XSDCLK cycle time tspc v 16 7 1600 XSDCLK High level pulse width 1 m XSDCLK Low level pulse 30 ns width pF f XSDCLK Rise time tspcr 2 XSDCLK Fall time tspcF 2 HCLK frequency fuc 0 625 60 MHz HCLK cycle time 16 7 1600 ns CCLK frequency fcc 0 625 60 MHz CCLK cycle time tcc 16 7 1600 7 ns CKO frequency 0 625 60 MHz The same frequency as HCLK CKO cycle time 16 7 1600 High level pulse i 6 2 2 width Low level pulse tow 00730 6 2 2 ns width pF CKO Rise time tckR 2 Fall time tckr
179. DMA to the internal SRAM from extarnal IO module only ML674001 series When DMA contoller transmits to internal RAM from the external or the external 102 3 in the setting of IOOITYPE 111 of or IO23TYPE 111 of IO23AC the DMA transfer in cycle steal mode cannot carry out Because access to an external bus from CPU cannot be performed until all transmission is completed even if DMA transfer is set as cycle steal mode Since it may be in a deadlock state do not set the above setting 12 21 ML674001 Chapter 12 Series ML675001 Series User s Manual Direct Memory Access Controller DMAC 12 4 DMA Transfer Timing 12 4 1 Starting a Transfer At least five clock cycles elapse between a transfer request and the actual start of the DMA transfer 1 Bus access for cycle stealing mode with auto request Transfer request autoreq 1 Bus access X om X CPUX nne CPUX em CPUX CPU X 2 Bus access for cycle stealing mode with external requests Transfer request DREQ N A N DREQCLR output Final transfer start signal TCOUT E Bus access CPUX CPUX sem X CPUX CPU CPU X CPUX omar omm CPUX CPUX 3 Bus access for burst mode with external requests Transfer request DREQ DREQCLR output Final transfer start signal TCOUT xis N Bus access CRUX X o X nn n
180. DMAC 4 1 i testa 4 CSR2 l lt gt txap tacc 1 tacc txaH1 Pid lt 1 2 tBsp tss tBsH1 M toEwEW toewew lxpis txpis 4 24 29 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e External ROM RAM Write Cycle Bus Width 16 bit External ROM RAM Word Access from CPU ese gt e gt XROMCS N XRAVCSN y bore bore XN23 0 tes 9 XS N 1 0 togwew MEN tva twa gt 7 boob boob 24 30 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e External ROM RAM Write Cycle Bus Width 16 bit External ROM RAM Word Access from DMAC le tcm ica gt NX XROVCS N V XRAMCS tap bero bore XN23 0 tesp tese N 1 0 logwew N1 0 I 24 31 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics External I O 0 1 2 Read Cycle
181. E N High level XBWE 01 High level XBWE N 1 High level XROMCS N High level XRAMCS N High level XIOCS N 3 0 High level XBS N 1 0 High level TDO High impedance TDO pin is always high impedance outside JTAG mode ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 5 Pin Structure and Treatment Table 1 3 summarizes the structures Table 1 3 ML675001 Series Pin Structures EFIQ EXINT3 2 1 0 BSEL 1 0 TCK gt CLKMD 1 0 ML675001Seir es Only TTL input DRAME N CKOE N TEST nTRST 2 TEST1 ML675001Seires Only TTL Schmitt input TDI TMS VDD 1 TTL input with 50 pull up resistance RESET N VDD o 1 kQ TTL Schmitt input with 50 pull up resistance JSEL FWR 50 TTL input with 50 pull down resistance to AINO AL 4 Channel select 1115 Channel select Analog to digital converter input XA 18 0 XWE N XOE N XBWE N 1 0 XROMCS XRAMCS Do XIOCS N 3 0 5 N 1 0 amp CKO 5 TDO Output Enable 1 18 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction pins PIOA 7 0 PIOB 7 0 gt 5 PIOC 7 0 PIOD 7 0 504 PIOE 9 0 XD 15 0 Enable 2 TTL Schmitt ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 6 Treatment of Unused Pins Table 1 4 specifie
182. E PIoA 2 PIOAey PIOE 3 ProBrey _ NC PLLGND JSEL OSCO TEST 5 pcp mrs spa TST 11 Notes NC Pins is not electrically connected inside PKG A1 NC ML674001Series TEST1 ML675001Series 2 NC ML674001Series CLKMDO ML675001Series G2 NC ML674001Series CLKMD1 ML675001Series A13 NC ML674001Series PLLVDD ML675001Series A12 NC ML674001Series PLLGND ML675001Series B7 VREF ML674001Series VREFP ML675001 Series D6 NC ML674001Series VREFN ML675001Series BSEL 0 GN XD 2 cubo XDI4 nrRsT NC PLLVDD 13 Figure 1 3 Pin Layout LFGBA 1 6 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 1 2 LQFP 2 cz 44 gt mer D 2 88 55 Foss IEEE E 1 DoOBRBO Yoon 85 9084 44 83588484 0855 2 883 2228 gg S 5 2582 85 aa 9 a EFRR 88808 8 S E 8 3 8 Secondary Primary Primary Secondary function function function function NC PLLVDD XIOCS N 3 NC PLLGND XIOCS N 2 XIOCS N 1 JSEL GND TMS XIOCS N 0 TCK XRAMCS N DRAME N XROMCS N CKOE N XBWE N 1 GND XBWE N 0 osco XWE_N OSC1_N VDD_IO VDD_IO XOE N TEST PIOC 7 XWR SIN PIOA 0 PIOC 6 XA 23 SOUT PIOA 1 144pin LQFP VDD CORE AVDD PIOC 5 XA 22 VREF VREFP TOP VIEW PIOC 4 XA 21 AIN 0 PIOC 3 XA 20 AIN 1
183. I2CSAD I2CDR I2CDR I2CDR 7161514131211 71615 4 3 2 110 716151413 21110 716543 2 1110 Interrupt 1 byte reception 1 byte reception Reception complete A omplete Waits for Waits for I2CDR Read data Register I2CSAD xxxxxxx1b I2CCON setting I2CCON setting settings 12 xxx0x110b I2CDR Read data I2CDR Read data I2CCON xxx00110b 12 xxx01100b 20 15 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 20 3 5 Restart sequence transmit operation To change the communication destination or the transfer direction in the middle of transmission reception of continuous data without releasing the bus it is necessary to transmit the restart sequence followed by a new slave address and a transfer direction this LSI the transmission of the restart sequence is designated by setting the I2CEN bit bit 0 of the I2CCON register to 1 20 3 6 To receive 1 byte of data from another slave device after transmitting 1 byte of data Step Oat the time of 1 byte transmit operation is performed Step at the time of transmit operation of 2 or more bytes is performed To specify a new communication destination th
184. IOA 7 General purpose port A bit 7 RI PIOB O General purpose port B bit 0 DREQO PIOB 1 General purpose port B bit 1 DREQCLRO PIOB 2 General purpose port B bit 2 DREQ1 PIOB 3 VO General purpose port B bit 3 DREQCLR1 PIOB 4 General purpose port B bit 4 TCOUTO PIOB 5 General purpose port B bit 5 TCOUT1 PIOB 6 General purpose port B bit 6 STXD PIOB 7 General purpose port B bit 7 SRXD PIOC 0 General purpose port C bit 0 PWMOUTO PIOC 1 General purpose port C bit 1 PWMOUT1 PIOC 2 General purpose port C bit 2 XA19 PIOC 3 General purpose port C bit 3 XA20 PIOC 4 General purpose port C bit 4 XA21 PIOC 5 General purpose port C bit 5 XA22 PIOC 6 I O General purpose port C bit 6 XA23 PIOC 7 General purpose port C bit 7 XWR General purpose port D bit 0 XWAIT PIOD 1 General purpose port D bit 1 XCAS N PIOD 2 General purpose port D bit 2 XRAS N PIOD 3 General purpose port D bit 3 XSDCLK PIOD 4 General purpose port D bit 4 XSDCS N PIOD 5 General purpose port D bit 5 XSDCKE PIOD 6 General purpose port D bit 6 XDQM 1I XCAS N 1 PIOD 7 General purpose port D bit 7 XDQM OJ XCAS 01 0 General purpose port E bit 0 SCLK PIOE 1 General purpose port E bit 1 SDI PIOE 2 General purpose port bit 2 SDO PIOE 3 General purpose port E bit 3 SDA PIOE 4 General purpose port E bit 4 SCL PIOE 5 General
185. IOBT 3 Setthe BGRUN bit in the SIOBCN register to 1 to start counting by the SIOBTC register and thus baud rate clock output The interface is ready to transfer data once five baud rate clock cycles have elapsed 17 3 4 Receive Interrupts A receive ready interrupt request indicates that the interface has transferred data from the receive shift register to the receive buffer SIOBUF register signaled any errors detected by writing 1 to the corresponding bits PERR OERR and FERR in the SIOSTA register and set the RVIRQ bit in the SIOSTA register to 1 This signal remains asserted until the program writes 0 to RVIRQ to negate the interrupt request Assertion takes precedence over negation if there is any conflict 17 12 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 3 5 Transmit Interrupts A transmit ready interrupt request indicates that the interface has transferred data from the transmit buffer SIOBUF register to the transmit shift register and set the TRIRQ bit in the SIOSTA register to 1 This signal remains asserted until the program writes 0 to TRIRQ to negate the interrupt request Assertion takes precedence over negation if there is any conflict 17 13 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 4 Important Usage Notes 1 Initialize the baud rate generator by writing to the baud rate timer SIOBT and baud rate control SIOBCN regis
186. IR 5 nIR 6 ILR6 ILCO 26 24 nIR 7 8 15 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 9 Interrupt Level Control Register 1 ILC1 This specifies the 3 bit interrupt levels for IRQ request sources nIR8 to nIR15 The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I I I I I I ILC1 ILR15 ILR14 ILR13 ILR12 I After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILR11 ILR10 ILR9 ILR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000024 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions ILRS bits 0 to 2 ILR9 bits 4 to 6 ILR10 bits 8 to 10 ILR11 bits 12 to 14 ILR12 bits 16 to 18 ILR13 bits 20 to 22 ILR14 bits 24 to 26 ILR15 bits 28 to 30 ILRn specifies the 3 bit interrupt level for IRQ request source nIRn The higher the numerical value the higher the priority A setting of zero on the other hand masks interrupts from that source ILR8 to 15 Interrupt Level Priority 2 1 0 1 1 1 1118 7 high priority 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0
187. IT sampling timing delay 2 t nes a nios Address Setup external 0 1 2 3 XIOWAITD2 101 101 XWAIT setup time t 20 E 2 Address Setup 1 external 1 0 1 2 and 3 KONATI XWAIT hold time t 0 Nios OE WE pulse width external 0 1 2 and 3 XOE N delay t e ER nioe Address Setup 1 external 0 1 2 and 3 ul OE OE WE Pulse width XWE delay 1 t MEC CREER nio Address Setup 2 external 1 0 1 2 and 3 SED tee an ME OE WE Pulse width XIOCS N OJ XIOCS N 1 access time 1 i CL external 1 0 1 2 3 WRITE ACCESS XIOCS N O XIOCS N 1 access time 2 t nioetnio7 tuc nioe nior tuc XIOCSW2 mE external 0 1 2 and 3 WRITE ACCESS 3 3 24 19 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics IO 0 IO 1 10 2 10 continued Item Symbol Minimum Typical Maximum Unit Notes 11214 3 txiowELHD nio4 tuc 2 nio4 tuc 1 Pd txiooe wew 1 5 1 5 XBWE N 1 0 hold time dmm CL 4 05 external 0 1 2 and 3 30 pF XBS N 1 0 delay _4 2 external 0 1 2 and 3 XBS N 1 0 output hold time 229 external 0 1 2 and 3 XA 23 0 d
188. Interrupts IRQn There are internal interrupts from the following functional blocks See Table in Section 8 2 4 Interrupt Source List System timer Watchdog timer Watchdog timer interval timer operation General purpose I O ports GPIOA GPIOB GPIOC GPIOD GPIOE Software interrupt requests UART Serial I O SIO Synchronous Serial I O SSIO Inter Integrated Circuit I2C Analog to digital converter PWM outputs 0 and 1 Timers 0 to 5 DMA channels 0 and 1 8 4 8 2 4 Interrupt Source List ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller Interrupt Source Number Interrupt Source Notes nFIQ nFIQ External input EFIQ_N nIRO System timer nIR1 Watchdog timer nIR2 Watchdog timer interval timer operation nIR3 unused nIR4 GPIOA nIR5 GPIOB nIR6 GPIOC nIR7 GPIOD GPIOE nIR8 Software interrupt requests nIR9 UART nIR10 SIO nIR11 AD nIR12 PWM output 0 nIR13 PWM output 1 nIR14 SSIO nIR15 2 nIR16 Timer 0 nIR17 Timer 1 nIR18 Timer 2 nIR19 Timer 3 nIR20 Timer 4 nIR21 Timer 5 nIR22 External interrupt 0 2 choice of edge or nIR23 unused nIR24 channel 0 nIR25 DMA channel 1 nIR26 External interrupt 1 2 choice ot edge Of nIR27 unused nIR28 External interrupt 2 4 choice of edge or nIR29 unused nIR30 unused nIR31 External
189. K 115 A10 DRAME N DRAM enable 116 C9 CKOE N Clock out enable 117 B10 GND GND GND 118 A9 OSCO Oscillation input pin 119 09 5 1 Oscillation output pin 120 B9 VDD IO VDD IO power supply ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Pin Primary Function Secondary Function LQFP BGA Symbol Description Symbol Description 121 A8 TEST Test mode input 122 B8 PIOA 0 General port with interrupt function SIN UART Serial Data In 123 08 PIOA 1 General port with interrupt function SOUT O UART Serial Data Out 124 C8 AVDD A D CONVERTER power supply 125 B7 VREF A D CONVERTER Reference voltage ML674001Series VREFP A D CONVERTER Reference voltage ML675001Series 126 D7 A D CONVERTER analog input port 127 A D CONVERTER analog input port 128 AIN 2 A D CONVERTER analog input port 129 C6 AIN 3 A D CONVERTER analog input port 130 D6 NC NC ML674001Series VREFN A D CONVERTER Reference GND ML675001 Series 131 B6 AGND GND for A D CONVERTER 132 B5 GND GND 133 A6 PIOA 2 General port with interrupt function CTS Clear To Send 134 D5 VDD I
190. M Half Word Access Bus Width 16 bit EDO DRAM Word Access EDCAH XA 15 0 1 2 XRAS N tEDRCD tepcas tencas o gt m_ om teDwED1 tepwep2 4 0 XWE 2 lt lt teDxDOH lt teDxDODE XD 15 0 DA1 1 DA1 2 24 44 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics EDO DRAM Read Cycle Bus Width 8 bit EDO DRAM Word Access two temp gt i 4 CAI 2 1 3 XN150 150 sampling sanpling Deta sampling Deta sampling timing timing timing timing 24 45 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 154 XRAS N XCAS XCAS NO X315 EDO DRAM Write Cycle Bus Width 8 bit EDO DRAM Word Access tmo 1 3 CAI 4 tras tws tws tme EDCAS ttt EDWEDI gt tooo tooo tooo gt e gt e
191. MACCINTO or DMACCINT1 for the channel to clear the status bits Abnormal termination 1 The program sets the bit in the DMA transfer mode register or DMACTMODI to 1 to mask channel operation The program reads the status bits IREQ ISTA and ISTP from the DMA transfer complete status register DMAINT The program writes to DMA interrupt clear register DMACCINTO or DMACCINT1 for the channel to clear the status bits The program processes the error in accordance with the needs of the user application system 12 18 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC Table 12 1 summarizes register contents during and after a transfer Table 12 1 Register Contents during and after Transfer Register 1 During 2 After normal 3 After abnormal 4 After forced operation termination termination termination Status register DMASTA 1 Busy 0 7 Idle 0 7 Idle 1 Busy transferring data no data to transfer no data to transfer transferring data Interrupt status IREQ 0 effect 1 1 1 1 0 no effect register DMAINT ISTA 0 no effect 0 normal 1 abnormal 0 no effect termination termination ISTP 0 effect 0 initial state 0 error from 0 no effect transfer source 1 error from transfer destination Transfer address registers Transferring Address fo
192. ML675001 Series User s Manual Chapter 1 Introduction Pin Name y o Description ed d Logic Secondary External Bus XA 23 19 Address bus to external RAM external ROM external I O banks and Secondary Positive external DRAM After a reset these pins are configured for their primary function PIOC 6 2 XA 18 0 Address bus to external RAM external ROM external banks and Positive external DRAM XD 15 0 Data bus to external RAM external ROM external I O banks and external Positive DRAM External bus control signals ROM SRAM IO XROMCS N ROM bank chip select Negative XRAMCS N SRAM bank chip select Negative XIOCS N 0 IO chip select 0 Negative XIOCS N 1 IO chip select 1 Negative XIOCS N 2 IO chip select 2 Negative XIOCS IO chip select 3 Negative XOE N Output enable Read enable Negative XWE N Write enable Negative XBS N 1 0 Byte select XBS N 1 is for MSB XBS N 0 is LSB Negative XBWE N O0 LSB Write enable Negative XBWE N 1 MSB Write enable Negative XWR Data transfer direction for external bus used when connecting to Motorola Secondary devices This represent the secondary function of pin PIOC 7 For ML675001 series this pin is available for 1 L read H write XWAIT External bank 0 1 2 3 WAIT signal Se
193. Manual 8 4 11 Current Interrupt Level Encode Register CILE Chapter 8 Interrupt Controller This register gives as a binary value the bit position for the highest 1 bit in the current interrupt level CIL register and thus the interrupt level for the current interrupt request The CPU has only read access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CIL E zs no E 9 Ue _ aoe te oe Euri Lx aw After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 imn zz _ _ ES x _ _ _ _ CILE 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x7800002C Access R Access size 32 bits Notes Bits labeled return 0 for reads but we them or adopt other don t care measures Bit Descriptions e CILE 2 0 bits 0 to 2 These bits give the bit position and thus the interrupt level recommend that the program not assume 0 and mask CIL 7 1 CILE 2 0 Interrupt Level from CILE 2 0 0000000 000 No interrupts pending 0000001 001 1 000001X 010 2 00001XX 011 3 0001XXX 100 4 001XXXX 101 5 01 110 6 1XXXXXX 111 7 8 19 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller 8 4 12 IRQ Clear Register IRCL Writing an interrupt source numbe
194. N 1 I O 1 chip select XIOCS N 2 2 chip select O XIOCS N 3 I O 3 chip select Output enable XWE N O Write enable O 1 1 XBS_N 1 0 O External bus byte select 1 O 1 1 XBWE _ 0 Write enable LSB 2 2 2 2 XBWE N 1 O Write enable MSB 2 2 2 2 XSDCS N O SDRAM chip select O XSDCLK O SDRAM clock O XSDCKE O SDRAM clock enable O XCAS N O SDRAM column address strobe XRAS N O Row address strobe O O XDQM 1 O Data I O mask for SDRAM XCAS_N 1 or MSB column address O O strobe for EDO DRAM XDQM 0 O Data I O mask for SDRAM 0 or LSB column address O O strobe for EDO DRAM XWAIT Memory wait indicator O O XWR bus data transfer O 4 5 Notes 1 For devices using byte select signals for byte access 2 For devices using byte write enable signals for byte access There is no XA 23 19 output during the boot sequence so user application systems with devices needing these outputs must provide an external mechanism for fixing these pins at Low level until the secondary XA function takes effect 3 4 Use as necessary 5 Only ML674001 series 11 43 ML 674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 6 1 Connecting ROM ML674001 Series ML675001 Series ROM x16 bits XA21 XA1 SUM 0015 000
195. No watchdog timer interrupt request pending 1 Watchdog timer interrupt request pending e IVTIST bit 5 A 1 in this bit indicates an interrupt request from the interval timer Writing 1 to this bit resets it to 0 Note Failure to clear this bit after a interrupt reset request produces a series of such requests Clearing this bit requires up to 20 HCLK cycles 1 so always wait at least 20 HCLK cycles 1 before clearing the interrupt controller 1 40HCLK cycles for ML675001 series IVTST Description 0 No interval timer interrupt request pending 1 Interval timer interrupt request pending 14 5 ML674001 Series ML675001 Series User s Manual Chapter 14 Watchdog Timer WDT 14 3 Description of Operation The watchdog timer allows the programmer to detect when the program has run out of control by having counter overflow generate an interrupt or system reset request If the design does not call for a watchdog timer this timer is available for use as an interval timer 14 3 1 14 3 2 14 3 3 14 3 4 Operation Modes The ITM bit in the WDTBCON register specifies the operation mode watchdog timer or interval timer The WDCLKT 1 0 bits in the WDTBCON register specify the frequency divisor for deriving the operating clock from CCLK Interval Timer Operation Setting both the ITM and ITEN bits in the WDTBCON register to 1 produces interval timer operation Writing 0x3
196. O IO power supply 135 B4 PIOA 3 General port with interrupt function DSR UART Set Ready 136 A5 PIOA 4 General port with interrupt function DCD UART Carrier Detect 137 C5 VDD CORE CORE power supply 138 C4 PIOA 5 General port with interrupt function DTR O UART Data Terminal Ready 139 A4 PIOA 6 General port with interrupt function RTS UART Request To Send 140 B3 PIOA 7 General port with interrupt function RI UART Ring Indicator 141 04 GND GND GND 142 A3 PIOE 3 y o General port with interrupt function SDA I2C Data In Out 143 B2 PIOE 4 General port with interrupt function SCL 12C Clock out 144 A2 PIOB 6 General port with interrupt function STXD O SIO send data output ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 3 Pin Descriptions vo Description qas Secondary System RESET_N Negative BSEL 1 0 Boot device select signal Positive BSEL 1 BSEL 0 Boot device 0 0 Internal Flash 0 1 External ROM 1 ii Boot mode The selected device is mapped to BANKO 0 0000 0000 0x07 FF FFFF after reset CLKMD 1 0 Clock mode input Positive OSCO Crystal connection or external clock input Connect a crystal if used to OSCO and OSC1 N ML674001Series 16 MHz to 33 MHz ML675001Series 5 MHz to 14 MHz It is also possi
197. PIOC 5 1 0 General port with interrupt function XA 22 O External address output 58 K8 VDD CORE VDD CORE power supply 59 M8 PIOC 6 y o General port with interrupt function XA 23 O External address output 60 M9 PIOC 7 General port with interrupt function XWR O Transfer direction of external bus 61 N8 XOE N Output enable excluding SDRAM 62 K9 DD IO VDD power supply 63 M10 XWE N Write enable 64 N9 XBWE 0 Byte write enable LSB 65 L9 XBWE N 1 Byte write enable MSB 66 L10 XROMCS N External ROM chip select 67 N10 XRAMCS N External RAM chip select 68 M11 XIOCS 0 IO chip select 0 69 K10 GND GND GND 70 N11 XIOCS N 1 IO chip select 1 71 M12 XIOCS NI 2 IO chip select 2 72 N12 XIOCS 3 IO chip select 3 73 N13 PIOD 6 General port with interrupt function INPUT OUTPUT S mask CAS MSB 74 M13 PIOD 7 General port with interrupt function XDQMI OJ XCA INPUT OUTPUT S NI 0 mask CAS LSB 75 L11 PIOB O y o General port with interrupt function DREQ O request signal CHO 76 113 PIOB 1 General port with interrupt function DREQCLR O0 O DREQ Clear Signal CHO 77 K11 VDD IO VDD power supply 78 112 2 y o General port with interrupt function DREQ 1
198. PWRx at PWM output falling edge 1 PWCx overflow at PWM output rising edge 16 6 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator 16 2 5 PWM Interrupt Status Register PWINTSTS This register gives the status of PWM output interrupt requests and provides bits for clearing them The CPU has read write access to this register 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 PWINTSTS INTIS Nos _ NTICLR NTOCLR Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address OxB7D0003C Access R W Access size 16 bits Notes These bits are reserved for future expansion They return for reads Writes to them are ignored Writes to bits 2 to 15 in this register are ignored Bit Descriptions INTOCLR bit 0 Writing 1 to this bit clears the PWM output 0 interrupt request INTOS Writes of 0 are ignored Reads always return 0 INTICLR bit 1 Writing 1 to this bit clears the PWM output 1 interrupt request INTIS Writes of 0 are ignored Reads always return 0 INTOS bit 8 This flag gives the interrupt request status for PWM output 0 INTOS Description 0 No interrupt pending 1 Interrupt pending INTIS bit 9 This flag gives the interrupt request status for PWM output 1 INT1S Description 0 No interrupt pending 1 Interrupt pending
199. Program Counter System amp User FIQ Supervisor Abort IRQ Undefined RO RO R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 R6 R6 R7 R7 SP svc SP und LR svc LR und PC PC THUMB State Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR fiq SPSR svc SPSR abt SPSR irq SPSR und Banked register Figure 2 3 THUMB State Registers 2 5 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 8 3 Relationships Between ARM and THUMB State Registers The THUMB state registers have the following relationships with the ARM state ones The THUMB state general purpose registers RO to R7 are the same registers as their ARM state counterparts e The THUMB state status registers CPSR and SPSR are the same registers as their ARM state counterparts The THUMB state stack pointer SP corresponds to the ARM state R13 register THUMB state link register LR corresponds to the ARM state R14 register The THUMB state program counter PC corresponds to the ARM state R15 register Figure 2 4 summarizes these relationships THUMB State ARM State a o c R10 R11 D R12 2 Stack pointer SP Stack pointer R13 o Link register LR Program counter PC CPSR SPSR SPSR Link register R14 Program counter R15 CPSR Figure 2 4 Mapping THUMB State Registers to ARM State Ones 2 8 4 A Accessing Upper Re
200. RAM 11011101 X X X 10 reserved ML67Q4002 ML67Q4003 Built in RAM ML67Q5002 ML67Q5003 1 0 111 X X X reserved 11 x x X X X 2 Built in RAM ML67Q4002 ML67Q4003 reserved ML67Q5002 ML67Q5003 Note Operation is not guaranteed for a setting labeled reserved Any program that is to modify RMPCON or ROMSEL registers must be running out of a memory region outside of bankO After setting an expected value as this register before of this LSI changes it takes worst 4 clock time When accessing after a setup after performing dummy read out to this register once after a register setup it recommends accessing Banko For remapping several clocks are required after writing the RMPCON register In order to guarantee the required number of clocks it is recommended to access BANKO after performing the dummy read to the same register RMPCON 3 6 3 4 2 Boot Control ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping The boot control features of this MCU enable it to map either the external ROM or built in Flash memory to bank 0 0x00000000 to Ox07FFFFFF to be used as the boot device or to set the MCU to the boot loading mode The external BSEL 1 0 pins of the MCU must be configured so as to determine which memory bank is to be The BSEL 1 0 pin input levels must not be changed after a reset used as the boot memory after a reset
201. RXCMP Description 0 Reception not complete 1 Reception complete TREMP bit 2 This bit indicates that transmit data has been transferred from the transmit receive buffer register to the shift register and the transmit receive buffer register is now empty TREMP Description 0 Transmit data not transferred 1 Transmit data transferred 19 5 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 2 4 Synchronous SIO Interrupt Enable Register SSIOINTEN SSIOINTEN is the register that enables the synchronous SIO interrupt cause The SSIOINTEN register can be read or written using a program 7 6 5 4 3 2 1 0 SSIOINTEN 2 8 gt TREMPE RXCMPE TXCMPE At reset 0 0 0 0 0 0 0 0 Address OxB7B0100C Access R W Access size 8 bits NOTE denotes a reserved bit Always write O to the bit If 1 is written normal operation is not guaranteed Explanation of Bits e TXCMPEN bit 0 This bit enables transmit complete interrupt requests TXCMPEN Description 0 Transmit complete interrupt request masked 1 Transmit complete interrupt request enabled RXCMPEN bit 1 This bit enables receive complete interrupt requests RXCMPEN Description 0 Receive complete interrupt request masked 1 Receive complete interrupt request enabled TREMPEN bit 2 This bit enables transmit rec
202. Secondary Logic SIO STXD SIO transmit signal Secondary Positive SRXD SIO receive signal Secondary Positive 2 SDA I2C Data This pin operates as NMOS open drain connect pull up Secondary Positive resistor SCL O I2C Clock This pin operates as NMOS open drain connect pull up Secondary Positive resistor Synchronous SIO SCLK Serial clock Secondary SDI Serial receive data Secondary Positive SDO Serial transmit data Secondary Positive PWM signals PWMOUTT 0 PWM output of CHO Secondary Positive PWMOUTT1 PWM output of CH1 Secondary Positive Analog to digital converter AIN O analog input AIN 1 Ch1 analog input AIN 2 Ch2analog input AIN 3 Ch3 analog input VREF Analog to digital converter convert reference voltage VDD ML674001Series only VREFP Analog to digital converter convert reference voltage VDD ML675001Series only VREFN Analog to digital converter convert reference voltage GND ML675001Series only AVDD Analog to digital converter power supply AGND Analog to digital converter ground Interrupt signals EXINT 3 0 External interrupt input signals Secondary Positive Negative EFIQ N External fast interrupt input signal Secondary Negative Interrupt controller connects this to CPU FIQ input MODE configuration DRAME N DRAM enable mode Negative
203. T 1 O Indicates to Ch 1 DMA device that last transfer has started Secondary Positive UART SIN 510 receive signal Secondary Positive SOUT O SIO transmit signal Secondary Positive CTS Clear To Send Secondary Negative Indicates that modem or data set is ready to transfer data Bit 4 in modem status register reflects this input DSR Data Set Ready Secondary Negative Indicates that modem or data set is ready to establish a communications link with UART Bit 5 in modem status register reflects this input DCD Data Carrier Detect Secondary Negative Indicates that modem or data set has detected data carrier signal Bit 7 in modem status register reflects this input Data Carrier Detect DTR Data Terminal Ready Secondary Negative Indicates that UART is ready to establish a communications link with modem or data set Bit 0 in modem control register controls this output RTS O Request To Send Secondary Negative Indicates that UART is ready to transfer data to modem or data set Bit 1 in modem control register controls this output RI Ring Indicator Indicates that modem data set has received Secondary Negative telephone ring indicator Bit 6 in modem status register reflects this input ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Primary Pin Name y o Description
204. TCM bit bit 2 of the I2CCON register is set to 1 Transmission of the start sequence transmission of the slave address and the transfer direction specified to the I2CSAD register confirmation of an acknowledge from the slave device for the address transmitted storage of 8 bit data transmitted from the slave device into the I2CDR register and transmission of an acknowledge for the data received because the I2COC bit bit 1 of the I2CCON register is set to 1 the stop sequence will not be transmitted the bus remains busy and the command wait state is activated At this point the I2CIR bit is set to 1 indicating that the reception of 1 byte of data has been finished data received can be retrieved by reading the I2CDR register If an acknowledge for the address transmitted has not been returned normally the 12 bit is set to 1 upon completion of reception Multiple bytes are received by repeating step O the required number of times To receive the last byte after multiple bytes have been received step Next an acknowledge is transmitted for the data received the stop sequence is transmitted the bus 15 released after the last byte is received and reception is then finished 3 p E W BH A Output Input Start Stop Restart Acknowledge Negative Acknowledge Negative sequence sequence sequence received acknowledge transmitted acknowledge received transmitted
205. VDD IO AIN 2 PIOC 2 XA 19 AIN 3 XA 18 NC VREFN GND AGND XA 17 GND XA 16 CTS PIOA 2 XA 15 VDD IO GND DSR PIOA 3 XA 14 DCD PIOA 4 XA 13 VDD CORE XA 12 DTR PIOA 5 XA 11 RTS PIOA 6 XA 10 RI PIOA 7 VDD IO GND XA 9 SDA PIOE 3 XA 8 SCL PIOE 4 XA 7 STXD PIOB 6 XA 6 123456 7 8 91011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 function TEST1 Primary Secondary function Notes NC Pins is not electrically connected inside PKG 1 NC ML674001Series TEST1 ML6750018Series 12 NC ML674001Series CLKMD0O ML675001 Series 17 NC ML674001Series CLKMD1 ML675001 Series 109 NC ML674001Series PLLVDD ML675001Series 110 NC ML674001Series PLLGND ML675001 Series 125 VREF ML674001Series VREFP ML675001 Series 130 NC ML674001Series VREFN ML675001 Series Figure 1 4 Pin Layout LQFP ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction 1 3 2 Pin List Pin Primary Function Secondary Function LQFP BGA Symbol Description Symbol Description 1 A1 NC NC ML674001Series TEST1 TEST Mode ML675001Series 2 B1 PIOB 7 General port with interrupt function SRXD 510 receive signal 3 C3 FWR TEST Mode 4 C1 RESET N Reset input 5 D3 V
206. XWE N High level High level XBWE 01 High level High level XBWE N 1 High level High level XROMCS N High level High level XRAMCS N High level High level XIOCS N 3 0 High level High level XBS N 1 0 High level High level TDO High impedance High impedance DRAME N pin input during a reset switches the DRAM controller on and off e DRAM controller disabled DRAME N High DRAM controller enabled DRAME Low TDO pin is always high impedance outside JTAG mode ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Table 1 2 Output States in STANDBY Mode Pin Name STANDBY Mode PIOA 7 0 primary function No change PIOA 7 0 secondary function No change PIOB 7 0 primary function No change PIOC 7 0 primary function No change PIOC 6 2 Secondary function XA 23 19 Low level PIOC 7 Secondary function XWR High level PIOD 7 0 primary function No change PIOD 7 secondary function XDQM O XCAS N 0 High level PIOD 6 secondary function XDQOM 1 XCAS N 1 High level PIOD 5 secondary function XSDCKE High level PIOD 4 secondary function XSDCS N High level PIOD 3 secondary function XSDCLK Low level PIOD 2 secondary function XRAS_N High level PIOD 1 secondary function High level PIOE 9 0 primary function No change XD 15 0 High impedance XA 18 0 Low level XOE N High level XW
207. _N delay SDRAM tepRAsD O 5tspc 55 Nsp2 tRAS XCAS delay SDRAM tspcasp 0 5tspc 4 nsns RASCAS minimum delay t oeuf E x SDRAM SDRCD SD1 SDC RAS active time t 2 2 2 SDRAM SDRAS SD2 SDC RAS precharge time t M u 2 SDRAM SDRP SD3 SDC s CL XWE_N delay SDRAM tspwep 30 pF 0 5tspc 0 5tspc 4 XD 15 0 input setup time t 14 2 SDRAM SDXDIS XD 15 0 input hold time t 0 A SDRAM SDXDIH XA 15 0 output delay SDRAM 0 5tspc O 5tspc 5 XD 15 0 output delay SDRAM 5 0 5tspc 0 5tspc 6 XD 15 0 output hold time t CL 0 5t 2 2 SDRAM SDXDOH 30 pF JISDC XD 15 0 output enable t 05 2 e time SDRAM SEN TUR XD 15 0 output disable time SDRAM tspxpopE 0 5tspc 8 24 21 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 2 25 10 2 75V 3 0 to 3 6V Ta 40 to 85 C EDODRAM Item Symbol tons Minimum Typical Maximum Unit Notes RASCAS delay The DRPC register specifies the EDO DRAM tEDRcD Nen the 2 ne the 2 EDO DRAM access parameters tRAH tCAC tCAS tRCD tRP CAS pulse width eu ned tied nenz tue 2 For further details refer to the EDO DRAM CL table on page 19 10 RAS pulse width t
208. a LSR I bit 1 A 1 in this bit indicates an overrun error For unbuffered 16450 operation this indicates that the hardware has overwritten the contents of the UARTRBR register with a new character before the CPU read the former character For buffered operation this indicates that the queue is full when the next character is completely received Reading the UARTLSR register clears the error Note that the contents of the shift register are not stored in the queue but overwritten by the next character Reading the UARTLSR register resets this bit to 0 LSR 1 Description 0 No overrun error pending 1 Overrun error pending LSR 2 bit 2 A 1 in this bit indicates a parity error This setting is only valid however when parity is enabled LCR 3 1 Reading the UARTLSR register resets this bit to 0 For buffered operation this indicates a parity error in the data at the head of the queue Note that parity errors for other characters in the queue do not affect LSR 2 contents LSR 2 Description 0 No parity error pending 1 Parity error pending 18 15 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte LSR 3 bit 3 A 1 in this bit indicates a framing error A framing error indicates that the corresponding character was not followed by a valid stop bit This bit goes to 1 when the bit following the l
209. a 40 to 85 C ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics SRAM ROM Condi Item Symbol Minimum Maximum Unit Notes tions XROMCS N XRAMCS N The ROMAC and RAMAC access time1 t 1 ng2 tuc EN ng ng2 tuc registers specify the OE WE SRAM ROM PM 22 2 pulse width and read off time READ ACCESS for ROM and SRAM access XROMCS N XRAMCS N respectively For further details access time2 1 2 000 2 refer to sections 11 2 3 and SRAM ROM CSR2 tuc 2 tuc 2 11 2 4 of chapter 11 READ ACCESS XA 23 0 access time t 1 ng2 tuc 1 tuc nni address setup SRAM ROM ARE 2 5 0 5 XBS_N 1 0 access time t nmi OE WE pulse width SRAM ROM i 2 5 3 delay SRAM ROM toep 1 tuc 1 nRa tuc 3 XWE_N delay SRAM ROM twED 1 tuc nRa tuc 2 XROMCS_N XRAMCS_N access time t ng2 tuc tuc SRAM ROM 5 2 5 WRITE ACCESS XROMCS N XRAMCS N 2 ner n access time2 CL 2 ngi 2 tcsw2 0 5 tuc ns SRAM ROM 30 pF 3 5 0 5 tuc WRITE ACCESS XBWE N 1 0 dela 4 twELHD luc 4 tuc 2 XBWE N 1 0 hold time SRAM ROM ii
210. a setting labeled reserved 2 Choose a setting with a combination satisfying the access timing parameters tRAS tRP etc appearing in the DRAM data sheet 11 17 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 10 SDRAM Mode Register SDMD This register specifies the SDRAM CAS latency The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SDMD ci P ED EE m 22 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE LT E E gt E WR 7 7 MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Address 0x7818000C Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them ignored Writing 1 to MODEWR in this register produces an SDRAM setting cycle MODEWR always returns 0 for reads Bit Descriptions LTMODE bit 0 This bit specifies the SDRAM CAS latency in clock cycles LTMODE Description 0 1 MODEWR bit 7 Writing 1 to this bit produces an SDRAM setting cycle It always returns 0 for reads MODEWR Description 0 Ign
211. able signal CKE output at Low level to shift SDRAM to power down mode conserving power when the number of idle cycles specified in the RDWC register have elapsed and there are no DRAM access requests that is no DRAM space access requests or error responses either no DRAM register space access requests and no distributed CBR refresh requests The DRAM controllers switches back if any of the above conditions are not met Switching back carries with it a penalty an additional memory access overhead of three clock cycles Signal outputs in power down mode SDRAM clock signal SDCLK output Stopped fixed at Low level Clock enable signal output Disabled fixed at Low level Notes 1 After a power on reset do not shift SDRAM to power down mode until the SDRAM initialization sequence is complete 2 EDO DRAM does not provide an equivalent to SDRAM power down mode 11 30 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 3 5 Access Timing Parameters for DRAM The following Table lists DRAM device speeds compatible with various operating frequencies Figuring out the necessary DRAMSPEC bit settings in the DRPC register is left as an exercise for the reader Operating SDRAM EDO DRAM Trac ns Frequency MHz PC133 125 100 PC33 PC66 50 60 70 80 100 60 0 33 3 30 0
212. acc gt lt p lt XA 23 0 tes tBsH1 gt lt gt XBS N 1 0 toE w Ew gt _ txpis txpiH pia XD 15 0 24 26 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics External ROM RAM Write Cycle Bus Width16 bit External ROM RAM Byte Half Word Access tcsw1 2 lt gt lt gt XROMCS N N y XRAMCS_N txap txaH2 lt XA 23 0 2 gt lt 5 1 0 twep toewew lt gt XWE P twELHD t weLHH lt gt XBWE N 1 0 iE txpopE amp 4 gt lt gt gt XD 15 0 N 24 27 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics e External ROM RAM Read Cycle Bus Width16 bit External ROM RAM Word Access from CPU k tcsR1 tosr2 tcsH1 XROMCS N N XRAMCS_N tacc tacc Pid gt lt XA 23 0 A1 A2 1 XBS_N 1 0 2 toew XOE_N lxpis txpis Vae 4 XD 15 0 D1 D2 24 28 XROMCS N XRAMCS N XA 23 0 XBS_N 1 0 XOE_N XD 15 0 e External ROM RAM Read Cycle ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics Bus Width16 bit External ROM RAM Word Access from
213. ady Secondary function for PIOA 3 DCD UART data carrier detect Secondary function for PIOA 4 DTR O UART data terminal ready Secondary function for PIOA 5 RTS O UART request to send Secondary function for PIOA 6 RI UART ring indicator Secondary function for PIOA T Note The interface does not support OUT1 and OUT2 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 1 3 Register List Address Name Symbol R W Size Initial Value 0 7 00000 Receiver Buffer Register UARTRBR R 8 Indeterminate 0xB7B00000 Transmitter Holding Register UARTTHR 8 Indeterminate 0xB7B00004 Interrupt Enable Register UARTIER R W 8 0x00 0xB7B00008 Interrupt Identification Register UARTIIR R 8 0x01 0xB7B00008 FIFO Control Register UARTFCR 8 0x00 0 7 0000 Line Control Register UARTLCR R W 8 0x00 0xB7B00010 Modem Control Register UARTMCR R W 8 0x00 0xB7B00014 Line Status Register UARTLSR R W 8 0x60 0xB7B00018 Modem Status Register UARTMSR Rw 8 20 0 7 0001 Scratch Register UARTSCR R W Indeterminate 0xB7B00000 Divisor Latch LSB UARTDLL R W Indeterminate 0xB7B00004 Divisor Latch MSB UARTDLM R W Indeterminate 18 3 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 Register Descriptions 18 2 1 Receiver Buffer Register UARTRBR This data registe
214. age code and desired mounting conditions reflow method temperature and times A 7 Revision History ML674001 Series ML675001 Series User s Manual Revision History Revision History Document Page No Date Previous Current Description Edition Edition PEUL675001 01 Apr 16 2003 Preliminary edition 1 Final edition 1 Correct a misdescription about the size of 31 36 31 36 the ROMSEL register to 16 bit Change the structure of sections 3 4 103 8 3 410 3 8 section 3 4 3 Notes of Address 3 6 3 5 Add the BSELM bit to the ROMSEL register 3 7 3 6 Correct misdescriptions in the table Add the CLKMD 1 and CLKMD 0 pins for 5 2 5 2 ML675001 series in the Pin list Add note about CLKMD 1 0 pins 7 10 7 10 Add a description about the CKWT register after a reset Modify the table of the condition that each 8 22 8222 IRQ n bit is set or cleared Correct a misdescription in the table about 9 4 9 4 cacheable control 10 1 10 1 Modify access clocks of built in SRAM and built in FLASH ROM 11 2 to 11 2 to Add 8 bit bus width setting to ROMBW and 11 3 11 3 RAMBW bit field of the BWC register for ML675001 series Add a note about XWR for ML675001 FEUL675001 01 Jan 31 2004 eges Correct a misdescription about XWAIT 12 21 12 21 Add notes about DMA Add notes to WDTIST and IVTIST bit field of
215. al port with interrupt function XSDCLK O Clock for SDRAM 94 F10 PIOD 4 General with interrupt function XSDCS N O Chip select for SDRAM 95 F12 PIOD 5 y o General port with interrupt function XSDCKE O Clock enable SDRAM 96 E12 BSEL 0 Select boot device 97 F13 BSEL 1 Select boot device 98 E10 PIOE 5 General port with interrupt function EXINT 0 Interrupt input 99 D12 PIOE 6 1 0 General port with interrupt function EXINT 1 Interrupt input 100 E13 PIOE 7 General port with interrupt function EXINT 2 Interrupt input 101 E11 PIOE 8 General port with interrupt function EXINT 3 Interrupt input 102 D11 PIOE 9 General port with interrupt function EFIQ N FIQ input 103 D13 PIOE 0 y o General port with interrupt function SCLK SSIO clock 104 C12 PIOE 1 General port with interrupt function SDI 5510 Serial Data In 105 D10 PIOE 2 y o General port with interrupt function SDO O SSIO Serial Data Out 106 C13 TDI JTAG Data Input 107 B12 TDO JTAG data out 108 B13 nTRST JTAG reset 109 A13 NC NC ML674001Series PLLVDD VDD PLL power supply ML675001Series 110 A12 NC NC ML674001Series PLLGND GND PLL GND ML675001Series 111 C11 CKO Clock output 112 A11 JSEL JTAG select 113 C10 TMS JTAG mode select 114 B11 TC
216. alog input 21 10 ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter 21 3 Operational Description The analog to digital converter supports two modes of operation Scan mode sequentially converts input from the selected range of channels select mode converts input from a single channel These two modes cannot be used simultaneously Do not change modes while the analog to digital converter is in operation Changing modes invalidates the contents of the result registers ADRO to ADR3 21 3 1 Scan Mode Scan mode sequentially converts input from the selected channel 0 to 3 through channel 3 The program has a choice of stopping conversion or cycling back to the first channel when channel 3 conversion is complete Figure 21 2 and Figure 21 3 illustrate scan mode operation Start Stop Ch1 Ch2 Ch3 Interrupt request Figure 21 2 Sample Scan Mode Operation over Channels 1 to 3 Stopping after Cycle SCNC 1 Start Ch1 Ch2 Ch3 Chi Ch2 ch3 Ch1 Ch2 7 Interrupt request Interrupt request Figure 21 3 Sample Scan Mode Operation over Channels 1 to 3 Recycling SCNC 0 21 3 2 Select Mode Select mode converts input from a single channel Figure 21 4 illustrates select mode operation Start Stop Ch2 gt Interrupt request Figure 21 4 Sample Select Mode Operation Using Channel 2 21 11 ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to
217. als RUN All functional blocks operative RUN Stop clock signals to individual functional Software control Software blocks RUN Clock gear Software control Software HALT Stop clock signals to CPU system bus etc Software control Interrupt or reset STANDBY Stop clock oscillation Software control External interrupt port input or reset Note HALT mode stops the clock signals to the following functional blocks CPU system bus bus control circuitry and memory controller interfaces to built in RAM and external memory 7 1 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management Clock Clock Gear signals TIC SIO UART 1 1 1 2 1 4 1 8 1 16 1 32 CPUBUS enabled Clock Gear CCLK 1 1 1 2 1 4 1 8 1 16 1 32 1 32 ML675001 Series Only Register Write Clock signals TIC SIO UART stopped External interrupt port input or reset Interrupt or Register Write Register Write reset HALT CPU amp SystemBus STANDBY Figure 7 1 State Transition Diagram Figure 7 2 illustrates the timing for shifting to and from the HALT and STANDBY modes Base clock Oscillation stabilization Minimum of 9 clock cycles interval specified in Maximum depends on next access CKWT lt lt lt gt Set STBY bit to 1 Extemal interrupt request Figure 7 2 Timing Chart Notes 1 The delay between setting the STBY bit in the CLKSTP register to 1 and stopping the clock depends on the conten
218. ame of data has been transmitted no transmit complete interrupt is generated 19 9 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 Transmit operation flow SSIO Trasmit Operation Write Tx data to SSIOBUF Busy set SSIOST 0 1 1 Clk later SSIOBUF data moved to SSIOREG SSIOINT 2 1 The program may jump to previous step and write new Tx data to SSIOBUF for continuous write operation Clock output from SCLK pin Serial data out from SDO pin SSIOBUF written by program Busy flag clear SSIOST 0 0 Transmit complete interrupt Transmit complete SSIOINT O 0 End Notes In the above flow diagram all tasks are implemented automatically in hardware except for writes to the SSIOBUF Write operations to the SSIOBUF are done by the application program If the Synchronous SIO is working in slave mode the synchronous clock signal will be an input to the SCLK pin and will be monitored by Synchronous SIO for synchronous operation 19 10 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 3 3 Receive Operation Writing of dummy data to the synchronous SIO transmit receive buffer register SSIOBUF initiates the receive operation The BUSY flag of the synchronous SIO status register SSIOST is set to 1 when data is written to SSIOBUF Data input from the SDI pin is shifted into the transmit receive shift re
219. and stops counting by the timer counter TMC register The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMEN EM E ES LAM ned _ ES A 530 Mesi 22 EP L Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E _ _ m TES ul TE _ _ ESL m _ _ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8001004 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored If the timer s operating clock CCLK with no frequency division is slower than the bus clock HCLK leave the following interval between successive writes to this register Otherwise because such writes are synchronized with CCLK not HCLK the data for the second write might arrive before the hardware has properly latched that for the first write n x HCLK 32 x CCLK where n 16 x HCLK frequency CCLK frequency Bit Descriptions TCEN bit 0 This bit controls system timer operation TCEN Description 0 Stop system timer 1 Start system timer 15 4 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 2 System Timer Reload Register TMRLR This register specifies the timer counter reload val
220. andler The interrupt controller hardware clears the IRN register to zero sets the current interrupt level CIL register bit corresponding to the interrupt level to 1 masking pending interrupt requests at or below that level negates the interrupt request nIRQ signal to the CPU and writes that interrupt level as a binary value to the current interrupt level CIL register 8 28 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller The interrupt handler software before returning resets the corresponding bit in the IRQ register A IRQA to O if the external interrupt nIR22 nIR26 nIR28 nIR31 uses edge detection as the trigger 5 Return from interrupt software Writing to the current interrupt level clear CILCL register resets the highest 1 bit in CIL the one indicating the interrupt level currently being processed to 0 The data written does not matter The interrupt handler terminates by executing a return from interrupt instruction which restores the instruction address and CPSR contents from the link R14 irq and program status SPSR irq registers Note For further details on CPU processing of IRQ exceptions refer to the ARM7TDMI data sheet 8 29 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller 8 5 3 Nested Interrupts and Re Entrant Interrupt Service Routines Setting I bit 7 in the CPU s current program status CPSR regist
221. ansfers are complete The output signal DREQCLR indicates when the DMA controller is ready for such DREQ edges The external source must assert DREQ when DREQCLR is at Low level and negate DREQ when DREQCLR is at High level Note that the DREQCLR timing differs between cycle stealing and burst modes For cycle stealing mode DREQCLR goes to High level after each individual transfer byte halfword or word so the external source must wait for TCOUT the final transfer start signal to also go to High level before starting any cleanup operations For burst mode DREQCLR and TCOUT to High level simultaneously after the specified number of transfers are complete Negating DREQ does not cancel a DMA transfer already in progress The DMA controller retains bus access as described above DREQCLR and TCOUT to High level regardless of whether DREQ is already negated Ensure that the external source wait for DREQCLR to go to High level before negating DREQ 2 Software request mode For memory to memory transfers and transfers between memory and I O modules that cannot generate DREQ transfer requests the program sets a bit to have the DMA controller generate internal requests until the specified number of transfers are complete As long as this bit remains set the DMA controller automatically performs DMA transfers each time that it is started 12 16 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controlle
222. ansmitter holding register empty interrupt when the transmit queue is empty Writing a character to the transmit queue or reading IIR clears this interrupt This interrupt is delayed by the time equivalent of the frame less the final stop bit when the following conditions are met e There is only a single character in the queue after the transmitter holding register empty THRE bit goes to 1 e The THRE bit goes to 1 18 27 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 3 5 Queue Polled Mode Enabling buffering but disabling interrupts by setting the IER 3 0 bits all to 0 produces queue polled mode operation The receive and transmit blocks have independent controls so can use separate queue polled modes Because there are no interrupts the CPU must check the status of these two blocks by reading LSR A 1 in LSR 0 indicates that there is at least one character in the receive queue LSR 4 1 indicate any errors Note that setting IER 2 to 0 means that such errors neither produce interrupts nor update the contents of IIR A 1 in LSR 5 indicates that the transmit queue is empty 1 in LSR 6 indicates that the transmit queue and transmit shift register are both empty A 17 in LSR 7 indicates an error receiving at least one character in the receive queue This mode uses the queue but does not detect the trigger level or timeouts because those functio
223. are register 1 16 OxFFFF 0xB7F00030 Timer 1 status register TIMESTAT1 R W 16 0x0000 0xB7F00040 Timer 2 control register TIMECNTL2 R W 16 0x0000 0xB7F00044 Timer 2 base register TIMEBASE2 R W 16 0x0000 0 7 00048 Timer 2 counter register TIMECNT2 R 16 0x0000 OxB7F0004C Timer 2 compare register TIMECMP2 16 OxFFFF 0xB7F00050 Timer 2 status register TIMESTAT2 R W 16 0x0000 0xB7F00060 Timer 3 control register TIMECNTL3 R W 16 0x0000 0xB7F00064 Timer 3 base register TIMEBASE3 R W 16 0x0000 0xB7F00068 Timer 3 counter register TIMECNT3 R 16 0x0000 0xB7F0006C Timer 3 compare register TIMECMP3 R W 16 OxFFFF 0xB7F00070 Timer 3 status register R W 16 0x0000 0xB7F00080 Timer 4 control register TIMECNTL4 R W 16 0x0000 0xB7F00084 Timer 4 base register TIMEBASE4 R W 16 0x0000 0xB7F00088 Timer 4 counter register TIMECNT4 R 16 0x0000 OxB7F0008C Timer 4 compare register TIMECMP4 R W 16 OxFFFF 0xB7F00090 Timer 4 status register TIMESTAT4 R W 16 0x0000 0xB7F000A0 Timer 5 control register TIMECNTL5 R W 16 0x0000 0xB7F000A4 Timer 5 base register TIMEBASE5 R W 16 0x0000 0xB7F000A8 Timer 5 counter register TIMECNT5 R 16 0x0000 0xB7F000AC Timer 5 compare register TIMECMP5 R W 16 OxFFFF 0 7 000 0 Timer 5 status register TIMESTAT5 R W 16 0x0000 15 3 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 Register Descriptions 15 2 1 System Timer Enable Register TMEN This register starts
224. ary function GPCTL3 1 secondary function Function In Out Function In Out PIOB 0 In Out DREQO Input PIOB 1 In Out DREQCLRO Output PIOB 4 In Out TCOUTO Output GPCTL4 bit 4 This bit controls the function of pins PIOB 5 and PIOB 3 2 Their secondary function is as DMA channel 1 GPCTL4 0 primary function GPCTL4 1 secondary function Function In Out Function In Out PIOB 2 In Out DREQ1 Input PIOB 3 In Out DREQCLR1 Output PIOB 5 In Out TCOUT1 Output GPCTLS bit 5 This bit controls the function of pins PIOC 1 0 Their secondary function is as PWM outputs GPCTL5 0 primary function GPCTL5 1 secondary function Function In Out Function In Out PIOC 0 In Out PWMOUTO Output PIOC 1 In Out PWMOUT 1 Output GPCTL6 bit 6 This bit controls the function of pin PIOD 0 Its secondary function is as external bus WAIT input GPCTL6 0 primary function 6 1 secondary function Function In Out Function In Out PIOD O In Out XWAIT Input 13 11 GPCTL7 bit 7 This bit controls the function of pin PIOC 7 Its secondary function is as external bus data direction ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO GPCTL7 0 primary function GPCTL7 1 secondary function
225. ast data bit or parity bit is 0 spacing level not 1 stop bit Reading the UARTLSR register resets this bit to 0 For buffered operation this bit goes to 1 when the character with the framing error reaches the head of the queue LSR 3 Description 0 No framing error pending 1 Framing error pending LSR 4 bit 4 LSR 4 bit 4 A 17 in this bit indicates a break interrupt 0 spacing level input for one frame interval start bit data bits parity bit and stop bit This bit goes to 1 immediately for unbuffered operation For buffered operation the interface first adds a zero byte to the queue Later when that character reaches the head of the queue the interface sets this bit to 1 and sets the parity framing and overrun error bits LSR 3 1 to 0 if the CPU has not already done so by reading the UARTLSR register Reading the UARTLSR register resets this bit to 0 LSR 4 Description 0 No break interrupt pending 1 Break interrupt pending LSR 1 to LSR 4 transitions to 1 represent sources for receiver line status interrupts priority 1 interrupts in the interrupt identification register IIR Setting IER 2 in the UARTIER register to 1 enables this interrupt LSR 5 bit 5 Transmitter holding register empty THRE 17 in this bit indicates that the ACE is ready to read a new character to transmit T
226. ata bits 1 stop bit no parity LN 0 TSTB 1 PEN 0 STRAY DO X D1 X D2 D3 X D4 X D5 X D6 X 07 STOR START 3 8 data bits 2 stop bits parity LN 0 TSTB 0 PEN 1 STRAY D1 D2 D3 D4 D5 D6 07 5 4 7 data bits 1 stop bit parity LN 1 TSTB 1 PEN 1 STRAY DO X X D2 X X X 05 X 06 X P STOR START 17 3 1 17 3 2 Figure 17 2 Sample Frame Formats Transmitting Data Writing 8 bit data to the transmit buffer SIOBUF register starts a transmit operation Note that the interface does not transmit the top bit if the character length is 7 bits When the interface transfers the SIOBUF contents to the transmit shift register it generates a transmitter ready interrupt request and sets the TRIRQ bit in the SIOSTA register to 17 to indicate that SIOBUF is now empty ready for the next write of transmit data to SIOBUF The interface then transmits the frame one bit at a time as specified by the SIOCON register settings start bit seven or eight data bits optional parity bit and one or two stop bits Receiving Data When the interface detects the start bit for a new frame it begins latching the data bits into the receive shift register as specified by the frame format in the SIOCON register When the interface detects a stop bit it transfers the received data from the shift register to the receive buffer SIOBUF register signals any err
227. before clearing the status bit of previous interrupt 16 8 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator PWCx contents contents PWRx PWCx vaue gt PWC PWR PWC PWR PWC PWR PWM output waveform Write 1 to RUN bit PWCx overflow PWCx overflow Figure 16 2 Basic Output Operation 16 9 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator PWM clock 1 4CPUCLK PWCYx contents PWRx contents 0 100 PWC PWRn match signal PWM output pin level Figure 16 3 Changing PWM Output Timing 16 10 Chapter 17 SIO ML674001 Series ML675001 Series User s Manual Chapter 17 SIO Chapter 17 SIO 17 1 Overview This serial port transfers data synchronizing individual characters A dedicated baud rate generator provides program control over a baud rate clock that determines the transfer speed independently of the bus clock Frame parameters available include the character length number of stop bits and parity Features Full duplex asynchronous operation Sampling rate baud rate x 16 Data bits 7 or 8 Stop bits 1 or 2 Parity even odd or none Error detection parity framing and overrun errors Loopback function ON OFF control plus forced addition of parity framing and overrun errors Baud rate Dedicated baud rate generator with 8 bit counter providing a baud rate clock that is independent
228. ber of characters in the queue falls back to this trigger level It goes to 1 immediately after the hardware transfers the triggering data from the receive shift register to the queue and returns to 0 when the queue becomes empty Receiver line status interrupts have higher priority than these interrupts Character Timeout Interrupts Enabling both the receive queue and receive interrupts produces a character timeout interrupt when the following conditions are met e There is at least one character in the receive queue e The time equivalent of at least four characters has elapsed since the last character was received If the frame format specifies two stop bits the timer starts after the first stop bit or since the last character was read off the queue If the frame format specifies one start bit eight character bits one parity bit and two stop bits for example the timeout interval for a transfer speed of 300 baud is approximately 160 ms The clock used to calculate the character time is CCLK Reading a character from the queue clears the character timeout interrupt and resets the timeout detection timer If there is no character timeout interrupt pending the hardware resets the timeout detection timer each time that the CPU reads a character from the queue or the interface receives a new character Transmitter Holding Register Empty Interrupts Enabling both the transmit queue and receive queue interrupts produces a tr
229. bit 5 This bit selects LSB first or MSB first for the transmit receive data SLMSB Description 0 LSB first 1 MSB first 19 7 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 2 6 Synchronous SIO Test Control Register SSIOTSCON SSIOTSCON is a register designed to simplify the synchronous SIO internal tests The SSIOTSCON register can be read or written using a progam In normal operation set SSIOTSCON to 0x00 Do not rewrite the content of this register while transmitting or receiving data 7 6 5 4 3 2 1 0 SSIOTSCON LBTST gt At reset 0 0 0 0 0 0 0 0 Address OxB7B01014 Access R W Access size 8 bits NOTE denotes a reserved bit Always write 0 to the bit If 1 is written normal operation is not guaranteed Explanation of Bits e LBTST bit 7 This bit enables the loop back test function When the loop back test function is enabled transmit signals are returned as receive signals LBTST Description 0 Loop back test function disabled normal mode 1 Loop back test function enabled test mode 19 8 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 3 Operations 19 3 1 Master Mode Slave Mode There two modes for transmission and reception the master mode and the slave mode mode to be used for transmission and reception is selected by the SFTSLV bit of
230. bits 20 1 1 Configuration Figure 20 1 shows the configuration of the I2C bus interface DATA BUS APB BUS I2CINT Control circuit I2CSAD SCL SCL SDA generation SDA circuit Figure 20 1 Configuration of I2C Bus Interface 20 1 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 20 1 2 List of Pins Pin name Function SDA 1 0 Serial data Input output pin This is a secondary function of PIOE 3 SCL O Serial data Transfer clock This is a secondary function of PIOE 4 This SDA and SCL terminal carry out logic operation of NMOS open drain output at the time of secondary functional operation For the reason please attach external Pull Up resistor for an 12C function at the time of use 20 1 3 List of Registers value 0xB780_0000 12C bus control register IICCON RW 8 0x00 0xB780 0004 12C bus slave address mode register IICSAD RW 8 AN 0x00 0xB780 0008 I2C bus transfer speed register I2CCLR R 0xB780 0018 I2C bus transmit receive data register 2 RW 8 EM 0xB780 001C I2C bus transfer speed counter 2 RAN 20 2 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 2 Registers 20 2 1 12C Bus Control Register 2 The I2CCON register controls the transmission and reception of the I2C bus read and written by programs The value at the time of reset is 0x00 The data in this register ca
231. ble to input a direct clock ML674001Series 1 MHz to 33 MHz ML675001Series 5 MHz to 14 MHz 20MHz to 56MHz OSC1 N Oscillation output pin When not using a crystal leave this pin unconnected CKO Clock out CKOE N Clock out enable Negative Debugging support TCK Debugging pin Normally connect to ground level TMS Debugging pin Normally drive at High level Positive nTRST Debugging pin Normally connect to ground level Negative TDI Debugging pin Normally drive at High level Positive TDO Debugging pin Normally leave open Positive General purpose ports PIOA 7 0 General purpose port Primary Positive Not available for use as port pins when secondary functions are in use PIOB 7 0 General purpose port Primary Positive Not available for use as port pins when secondary functions are in use PIOC 7 0 General purpose port Primary Positive Not available for use as port pins when secondary functions are in use PIOD 7 0 General purpose port Primary Positive Not available for use as port pins when secondary functions are in use Note that enabling DRAM controller with DRAME_N inputs permanently configures PIOD 7 0 for their secondary functions making them unavailable for use as port pins PIOE 9 0 General purpose port Primary Positive Not available for use as port pins when secondary functions are in use ML674001 Series
232. ch problems The lock function puts a part of the cache memory in the locked state so that the instructions and data in that part of the cache memory is retained Since such locked instructions and data will always result in a cache hit operation it is possible to carry out high speed access at all times While the cache memory is divided into four ways storage locations it is possible to lock the contents of the cache memory in units of a way by setting the bits Further using the BNK 1 0 and bits it is possible to load instructions or data to a locked way Caution The load operation is given priority when the target way of the load operation has been locked Example When 00 F 1 and LCK 01 the target way Way 0 of the load operation will be the same as the target way Way 0 of the lock operation Note that Way 3 cannot be locked Load Mode The load mode is that of storing data in the specified way of the cache memory by accessing the data in the main memory instruction fetch accesses will be non cacheable accesses On the other hand the operations for all data accesses will be made in the normal manner according to the setting of the cacheable register cacheable or non cacheable AII storing to the cache memory is made forcibly to the way selected by BNK 1 0 by the setting of the F bit By setting the BNK 1 0 and F bits of the cache lock control register CON it i
233. clock HCLK after the transmit data is written the transmit data is transferred from SSIOBUF to the synchronous SIO transmit receive shift register SSIOREG At the same time the TREMP bit of the synchronous SIO interrupt request register SSIOINT is set to 1 allowing the next transmit data to be written The synchronous clock is then output from the SCLK pin only if Synchronous SIO is in master mode and the transmit data is output from the SDO pin either as LSB first or MSB first in synchronization with the falling edge of the synchronous clock After that transmit data is output in synchronization with the synchronous clock according to the specification of the synchronous clock SIO control register SSIOCON and one frame of data is transmitted If there is no new transmit data written to the transmit buffer register the BUSY flag is cleared to 0 and at the same time the TXCMP bit of the SSIOINT register is set to 1 to complete the transmit operation Continuous transmit operation Steps to of Section 19 3 2 are performed If the next transmit data is written to SSIOBUF from the time TREMP 1 is set in to when the transmit operation is completed when the current transmit operation is completed the next transmit data is automatically transferred to SSIOREG and data is transmitted continuously Transmission is completed with step in Section 19 3 2 If the next data has been written to the transmit buffer when one fr
234. clock cycles in the DRPC register Write 0x00000004 to the DCMD register to pre charge the DRAM all banks for SDRAM Write 0x00000005 to the DCMD register eight times to produce CAS before RAS CBR refresh operations Specify the DRAM type SDRAM or EDO DRAM and the column length for address multiplexing in the DRMC register For SDRAM also specify the SDRAM pre charge latency and whether to automatically shift SDRAM to power down mode For SDRAM specify the SDRAM CAS latency in the SDMD register Specify the DRAM refresh periods in the RFSHO and RFSHI registers Specify the number of idle cycles to wait before shifting DRAM to power down mode in the RDWC register Write DRAM commands to the DCMD register pre charge CBR refresh start end self refresh etc 11 27 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller Address Outputs and Bus Width The following Table summarizes the relationships between address outputs XA and the DRAM address pins A 1 0 00 1 0 01 AMUX 1 0 10 DRAM address Column length 8 Column length 9 Column length 10 shifting with bus width 52 52 52 1 Row Column Row Column Row Column 16 bits 8 bits XA 23 0 0 0 0 0 0 A 22 A 23 XA 22 0 0 0 0 0 0 A 21 A 22 XA 21 0 0 0 0 0 0 A 20 A 21 XA 20 0 0 0 0 0 0 A 19 A 20 XA 19 0 0 0 0 0 0 A 18 A 19 XA 18 Ha 26 Ha 26
235. condary Positive This input permits access to devices slower than register settings External bus control signals DRAM XRAS N Row address strobe Used for both EDO DRAM and SDRAM Secondary Negative XCAS N Column address strobe signal SDRAM Secondary Negative XSDCLK SDRAM clock same frequency as internal HCLK Secondary XSDCKE Clock enable SDRAM Secondary XSDCS Chip select SDRAM Secondary Negative XDQM IJXCAS 11 Connected to SDRAM DQM MSB Secondary Positive Connected to EDO DRAM column address strobe signal MSB Negative XDQM O XCAS N 0 Connected to SDRAM LSB Secondary Positive Connected to EDO DRAM column address strobe signal LSB Negative ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction Pin Name Description ERU Logic Secondary DMA control signals DREQ 0 Ch 0 DMA request signal used when controller configured for Secondary Positive DREQ type DREQCLR O0 Ch 0 DREQ signal clear request The DMA device responds to this Secondary Positive output by negating DREQ TCOUT O0 Indicates to Ch 0 device that last transfer has started Secondary Positive DREQ 1 Ch 1 DMA request signal used when controller configured for Secondary Positive DREQ type DREQCLR 1 Ch 1 DREQ signal clear request The DMA device responds to this Secondary Positive output by negating DREQ TCOU
236. current operating mode The FIQ mode has seven bank registers R8 fiq to R14 fiq mapped to R8 to R14 Having these registers available means that many FIQ handlers do not have to save registers to the stack The User IRQ Supervisor Abort and Undefined modes have two bank registers mapped to R13 and R14 These modes use these registers as a private stack pointer and a link register 2 3 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU ARM State General Registers and Program Counter System amp User FIQ Supervisor Abort IRQ Undefined RO RO RO R2 R2 R3 R3 R4 R4 R5 R5 R6 R6 R8 R8 R8 RO RO R10 R10 RT R11 R12 R12 R12 R13 svc R13 abt R13 irq R15 PC R15 PC R15 PC R15 PC R15 PC 15 ARM State Program Status Registers CPSR CPSR CPSR CPSR CPSR CPSR SPSR fiq SPSR svc PF SR abt SPSR irq SPSR und Banked register Figure 2 2 ARM State Registers ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 8 2 THUMB State Registers The THUMB state uses a subset of the ARM state register set The programmer has direct access to eight general purpose registers RO to R7 the program counter PC stack pointer SP link register LR and CPSR The privileged user modes access three private registers stack pointer link register and save program status register SPSR Figure 2 3 summarizes these registers THUMB State General Registers and
237. d ADRUN to 0 with the same write Simultaneously setting both back to 1 then restarts conversion Note that stopping conversion this way invalidates the contents of the result register for the current channel 21 4 ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter 21 2 2 Analog to Digital Converter Control Register 1 1 1 After a reset This register controls select mode operation The program has read write access to this register The contents after a reset are 0 0000 15 14 13 12 11 10 9 7 6 4 1 0 EE ME EM EE E d i STS ADSTM 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 6001004 H Access R W Access size 16 bits Note Bit Descriptions ADSTM 1 0 bits 1 to 0 This field specifies the channel These bits are reserved for future expansion They return 0 for reads Writes to them are ignored It needs 2HCLK 2CCLK for ADCONI register write recovery time ADSTM Channel 1 0 0 0 0 1 ch1 1 0 ch2 1 1 ch3 Do not change this setting while the analog to digital converter is in operation Writes only take effect when STS bit 4 is 0 STS bit 4 This bit turns the analog to digital converter operation on and off in select mode STS Description 0 Stop analog to digital converter 1 Start analog to di
238. ddress OxB780001C Access R W Access size bits Note This is a reserved bit for future expansion In this LSI 0 is read during reading and this bit is ignored during writing The bit 6 of an I2CBC register does not exist in ML674001 series In ML674001 series I2CBC bits 6 becomes the treatment of 2CBC bits 6 to 0 The relationships between the setting values of the I2CBC register and the transfer speed of the I2C bus are as follows 12 bus transfer speed Hz HCLK frequency I2CBC setting value x 8 Thus 12 HCLK frequency 12 bus transfer speed bps x 8 The following table shows some examples for setting I2CBC register values HCLKfrequency I2CBC I2CBC 60 MHz 1 75 0x4B 19 0x13 33 MHz 42 0x2A 11 0 0 25 MHz 32 0x20 08 0x08 20 MHz 25 0x19 07 0x07 1 Forl2C bus operating at 100 Kbps Thus I2CCLR 0x00 2 Forl2C bus operating at 400 Kbps Thus I2CCLR 0x01 Note When the I2CBC register is set to 0 the timing generating counter stops Note Set the above I2CBC register before setting both the I2CCLR and I2CCON registers 1 This setting condition is applied only to ML675001 series 20 11 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 20 3 Operations The following is a function description of the I2C block operation Through out this section I2C bus transfer illustrations are used as visual aides Us
239. determines the channel priority when it acquires bus access from the CPU A burst mode transfer over the lower priority channel therefore continues through to completion even if there is a transfer request on the other channel 12 20 12 3 6 1 2 3 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC Important Usage Notes When setting up a DMA transfer always take into consideration bus width address alignment and any other access restrictions in effect for the source and destination devices There can be no DMA transfers in HALT mode because the CPU is not available to grant bus access The DMA controller increments the source DMACSADO or DMACSADI and destination DMACDADO or DMACDAD1 addresses by the transfer size in bytes if the corresponding device type so specifies The hardware enforces alignment by internally ignoring the lowest address bits as appropriate for the transfer size but reading an address register returns those bits exactly as written Example Writing address of 0x1000001 1 Word 32 bit transfer The controller internally forces the lowest 2 bits to 00 for an effective address of 0x10000000 Reading the register however returns 0x10000011 The controller internally forces the lowest bit to 0 for an effective address of 0x10000010 Reading the register however returns 0x10000011 DMA transfers are not possible between certain combinations
240. dware If the interrupt request is an external interrupt nIR22 nIR26 nIR28 nIR31 using edge detection as the trigger the interrupt controller sets the corresponding bit in the IRQ register A IRQA to 1 2 Relay exception request to CPU hardware If the interrupt request has an interrupt level higher than the contents of the current interrupt level encode CILE register which gives the bit position for the highest 1 bit in the current interrupt level CIL register the interrupt controller writes the highest interrupt number for interrupt requests at that higher interrupt level to the IRQ number IRN register and asserts the interrupt nIRQ signal to the CPU If the interrupt level is less than or equal to that in CIL and CILE however there is no IRQ exception and IRN goes to zero 3 Accept request hardware If I bit 7 in the CPU s current program status CPSR register enables IRQ exceptions the CPU saves the address of the next instruction in the link R14 irq register saves the CPSR contents in the program status SPSR register and sets I bit 6 in the CPU s current program status CPSR register to 1 to block acceptance of IRQ exceptions by the CPU Control then passes to the IRQ exception handler 4 Process interrupt software amp hardware The IRQ exception handler software reads the interrupt source number from the IRQ number IRN register and branches to the corresponding interrupt h
241. e The AHB read access is made not only in the case of a read miss operation but also in the case of a write miss operation in the figure The above example is one in which there is no write back and is a read miss operation in the case of a succeeding read hit 9 13 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY Example of replacement operation Write back operation is present bclk Larzzlzzlzlk2elz2lc 2z222zle2cljecz 41 4 4 4 4 4 EAN SEIAS he as zs 4 4 UR ES Par am oL E ssec ele sep Lus 48 arm7tdmi a 31 0 arm7tdmi dout 31 0 arm7tdmi mclk arm7tdmi nrw haddr o 31 0 htrans o 1 0 hburst o 1 0 hwrite o hready o hrdata o 31 0 hwdata 0o 31 0 xrame xao 31 0 xre xwe xdi 31 0 xdo 31 0 During a cache miss operation the cache controller carries out a 4 word wrap 4 AHB Read access in the figure e The CPU will be kept waiting until the access is completed in the figure in the figure of the CPU varies depending on the previous access state in the figure the The waiting duration presence or absence of write back operat
242. e Clock asua EHE REX EORR EEVA RAEE Reti HERRERA 17 12 11 34 Receive Interr pts iie epe 17 12 vi ML674001 Series ML675001 Series User s Manual Table of Contents 17 3 5 Transmit Interrupts nuwasisa cinerea dees Sines ere cipi a er a od aaa tras 17 13 17 4 Important Usage Notes vse ite aeter B o a e e ee a res 17 14 Chapter 18 UART with FIFO 16byte INEO NI 18 1 181 1 Components eee Eme ERE E I ELE tH EORR Tri Sueded sgevens er RE 18 2 EMAIL 18 2 18153 Register nee Ee pr RC UT pr Pb eG E 18 3 18 2 Register DESCIHDpLODS oer e ERE HD OU d P P RH EGRE 18 4 18 2 1 Receiver Buffer Register UARTRBR J 1 2 001000000000000000000000000000000000000800 18 4 18 2 2 Transmitter Holding Register 22222 00 00 00000000000 18 5 18 2 3 Interrupt Enable Register UARTIER 18 6 18 2 4 Interrupt Identification Register UARTIIR eese enne enne rennen 18 7 18 2 5 FIFO Control Register 18 9 18 2 6 Line Control Register UARTLCR n nennen nnnm nennen enne tnit ener nnne 18 11 18 2 7 Modem Control Register UARTMCR n nnnm 18 13 18 2 8 Line Status Register UARTLSR
243. e I2CCON register and the START bit bit 4 of the I2CCON register are set to 1 Transmission of the start sequence to attain bus access and transmission of the start byte pattern specified to the I2CSAD register Step at the time of 1 byte transmit operation is performed Step at the time of 1 byte transmit operation is performed The I2CCON register is to 101 following series of operations is automatically performed when the I2CEN bit bit 0 of the I2CCON register and the STCM bit bit 2 of the I2CCON register are set to 1 Transmission of the restart sequence transmission of the slave address and the transfer direction specified to the I2CSAD register confirmation of an acknowledge from the slave device for the data transmitted transmission of the transmit data specified to the I2CDR register and confirmation of an acknowledge from the slave device for the data transmitted Also when the I2COC bit bit 1 of the I2CCON register is set to 0 the stop sequence is successively transmitted the bus is released and communication is then finished At this point the I2CIR bit is set to 1 indicating that the transmission of 1 byte of data has been finished If acknowledges for the address and data transmitted have not been returned normally both the I2CAAK and I2CDAK bits are set to 1 upon completion of transmission I2CSAD I2CSAD I2CDR ped 765432 1 0 11 17 61514131211
244. e address of the new communication destination slave is specified to SAD 6 0 of the I2CSAD register and to set the transfer direction as reception the I2CRW bit is set to I received by the master device The I2CCON register is set 101 The following series of operations is automatically performed when both the 12 bit bit 0 of the I2CCON register and STCM bit bit 2 of the I2CCON register set to 1 Transmission of the restart sequence transmission of the new slave address and the transfer direction specified to the I2CSAD register confirmation of an acknowledge from the slave device for the address transmitted and storage of 8 bit data transmitted from the slave device into the I2CDR register Also transmission of an acknowledge for the subsequent data received if the I2COC bit bit 1 of the I2CCON register is set to for continuous communication stop sequence is transmitted the bus is released and communication is then finished At this point the I2CIR bit is set to 1 indicating that the reception of 1 byte of data has been finished The data received can be retrieved by reading the I2CDR register If an acknowledge for the address transmitted has not been returned normally the I2CAAK bit is set to 1 upon completion of reception i B m H N A Qoo
245. e b RETE EL HERD ER ERRORS 19 3 19 2 1 Synchronous SIO Transmit Receive Buffer Register SSIOBUP sse 19 3 19 2 2 Synchronous SIO Status Register SSIOST n eene nennen nennen 19 4 19 2 3 Synchronous SIO Interrupt Request Register SSIOINT essent 19 5 19 2 4 Synchronous SIO Interrupt Enable Register SSIOINTEN eee 19 6 19 2 5 Synchronous SIO Control Register 55 2 2 04 2 22 2 2 0000000000000000000000 090 19 7 19 2 6 Synchronous SIO Test Control Register SSIOTSCON a a 19 8 19 3 Operations Sa aU aped eame GDA edente au bate eb te edP Sine 19 9 19 3 1 Master Mode Slave Mode eee decem edere RRE 19 9 19 3 2 Transmit Operation terit t dt e te roter nro cet 19 9 19 3 3 Receive Operation o booa ee RR np trece emo cote i gs 19 11 19 3 4 Interrupt Signal a A aa EM Sas etes 19 13 Chapter 20 I2C 20 OVERVIEW err i et ei teer ce e sd test dui cn hene 20 1 20 11 Configuration recede iei Iit ee de e ee e tot 20 1 20512 OE PIS sonne edet te I e tide i e oi ede teet 20 2 20 1 3 Iasto enr 20 2 20 2 RegISterSi a nhan dre E dedo P Ee E ete E re Eee 20 3 vii ML674001 Series ML675
246. e bits specify the bus width for I O bank 2 3 IO23BW 1 0 EN Description 9 8 0 0 Not physically present Access to bank region disabled Access from DMA controller produces error response 0 1 8 bits 1 0 16 bits 1 1 reserved Note Operation is not guaranteed for a setting labeled reserved 1 This IO1BW 1 0 register exists only in ML674001 series 1 In ML675001 series it becomes the treatment of reserved ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 2 External bank 2 3 Bus Width Control Register 23 1 ML675001 Series only This register specifies the external data bus widths for I O bank 2 3 The program has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IO23BWC 7 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ ot _ 2208 _ 1023BW 1 0 _ _ E _ _ 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78300000 Access R W Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions e IO23BW 1 0 bits 7 and 6 These bits specify the bus width for I O bank 2 3 IO23BW 1 0 Description 9 8
247. e complete External request mode The DMA controller generates transfer requests at rising edges in the external request signals DREQO or DREQ1 for the channel e Interrupt requests The DMA controller sends interrupt requests to the CPU when the specified number of transfers are complete or there is an error nonexistent address specified for transfer destination or transfer source There are separate interrupt request signals for each channel and these can be masked by channel 12 1 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 1 1 Components Figure 12 1 shows DMA controller components Figure 12 2 DMAC peripheral components AMBAAHB bus dreq O DMA transfer control Master interface dreq 1 dreqclro control tco 1 0 dreqclro 1 0 Figure 12 1 DMA Controller Block Diagram 12 2 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC ML674001 Series ML675001 Series Master Slave I F UPLAT7B 7D EXINTRC ARMT7TDMI chintm 1 0 Intemal Extemal dreqi 1 0 dreqciro 1 0 tc 1 0 Memory Controller External memory bus TCOUTO TCOUT 1 DREQCLRO External DREQCLR 1 memory Figure 12 2 DMA Controller Peripheral Block Diagram AHB Interface The DMA controller features a 32 bit connection to the AMBA AHB bus The DMA controller
248. e execute the aborted instruction e Prefetch abort SUBS PC R14 abt 4 Data abort SUBS PC R14 abt 8 Software Interrupts A software interrupt SWI instruction switches the CPU to Supervisor mode normally to request a special supervisory function The SWI handler must regardless of the original state ARM or THUMB terminate by executing the following instruction MOV 14 Undefined Instructions Attempting to execute an instruction not supported by the CPU triggers an undefined instruction trap This mechanism allows the programmer to expand the THUMB or ARM instruction set using software emulation The trap handler after emulating the failed instruction must regardless of the original state ARM or THUMB terminate by executing the following instruction MOVS PC 14 This instruction restores the current program status register CPSR and returns to the instruction following the undefined one 2 13 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 12 9 Exception Vectors Table 2 3 lists exception vector addresses Table 2 3 Exception Vectors Exception Starting Mode 0x00000000 Reset Supervisor 2 12 10 Exception Priority Order A fixed priority system determines the order in which simultaneous exceptions are accepted Highest priority 1 Reset 2 Data abort 3 FIQ 4 IRQ 5 Prefetch abort Lowest priority 6 Undefined instruction software interrupt No
249. e expansion They return 0 for reads These status bits remain 1 until the program explicitly resets them to 0 Bit Descriptions IREQO bit 0 This bit gives the transfer complete status for DMA channel 0 IREQO Description 0 No request DMA transfer is not complete or has not started 1 Request pending DMA transfer is complete IREQI bit 1 This bit gives the transfer complete status for DMA channel 1 IREQ1 Description 0 No request DMA transfer is not complete or has not started 1 Request pending DMA transfer is complete ISTAO bit 8 This bit gives the termination reason for DMA channel 0 ISTAO Description 0 Normal termination 1 Error 12 7 ML 674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC ISTAI bit 9 This bit gives the termination reason for DMA channel 1 ISTA1 Description 0 Normal termination 1 Error e ISTPO bit 16 This bit gives the cycle in which the DMA channel 0 error occurred It is only valid when ISTAO 1 ISTPO Description 0 Read from transfer source 1 Write to transfer destination e ISTPI bit 17 This bit gives the cycle in which the DMA channel 1 error occurred It is only valid when ISTAI 1 ISTP1 Description 0 Read from transfer source 1 Write to transfer destination
250. e it to remap any of the available memory banks to bank 0 addresses 0x00000000 to OxO7FFFFFF The remapping of bank 0 can be achieved either by hardware configuration of some of the external pins or through software register settings after boot up In hardware the BSEL 1 0 external pins can be configured to select external ROM or internal FLASH memory as the memory region to be mapped to bank 0 for use as the boot device or boot loading mode after a reset After booting the MCU the remap control register together with ROM select register can be used to remap an internal or external memory to bank 0 3 1 1 Pin List Pin Name Description BSEL 1 Select boot device BSEL 0 Select a boot device 3 1 2 Register List Address Name Abbreviation R W Size Initial Value 0xB8000010 Remap control register RMPCON R W 32 0x00000000 0xB700000C ROM select register ROMSEL R W 16 0x0000 3 1 ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping 3 2 Address Map 3 2 1 ML674001 series address map Bank 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Note External APB Processor Address FFFF F800 0000 reserved 400 0000 External 1 0 2 3 0000 External 1 0 0 1 E800 0000 reserved E000 0000 15555 0800 0000 reserved D000 0000 External SRAM
251. e the following legend for all of the illustrations in this section 20 3 1 Transmit operation transfer of 1 byte from master to slave 7 bit address mode To identify the communication destination the address of the communication destination slave is written to SAD 6 0 of the I2CSAD register and to set the transfer direction as transmission the I2CRW bit is set to 0 transmitted by the master device Write transmit data to the I2CDR register The I2CCON register is set to 100 following series of operations is automatically performed when the STCM bit bit 2 of the I2CCON register is set to 1 Transmission of the start sequence to attain bus access transmission of the slave address and the transfer direction specified to the I2CSAD register confirmation of an acknowledge from the slave device for the address transmitted transmission of the transmit data written to the I2CDR register and confirmation of an acknowledge from the slave device for the data transmitted Also when the I2COC bit bit 1 of the I2CCON register is set to 0 the stop sequence is successively transmitted the bus is released and communication is then finished At this point the bit is set to 1 indicating that the transmission of 1 byte of data has been finished If acknowledges for the address and data transmitted have not been returned normally both the I2CAAK and I2CDAK bits are set to 1 upon completion of transmissi
252. ead from register T Write to CIL or CILCL register Clock operational 8 34 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller CLKEN nIR N ILRN 0xh000 IRQIN IRL 2 0 IRN 6 0 WKUPRQ nIRQ STOP RUN CLKEN HCLK nIR N ILRN Oxh000 IRQ N IRL 2 0 IRN 6 0 WKUPRQ nIRQ HRESET Write to ILCO or ILC1 register Sleep RUN 8 35 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 6 3 IRQ Interrupt Timing Chart nIR16 to nIR31 CLKEN x HCLK nIR N x EXTINR 6 0 x EXTLVL 2 0 IRL 2 0 IRN 6 0 WKUPRQ nIRQ CIL 7 1 CILE 2 0 t Readfrom IRN register Write to CIL or CILCL register Clock operational nIR16 to nIR21 nIR24 nIR25 EC CLKEN HCLK External fast interrupt request EFIQ N EXTINR 6 0 EXTLVL 2 0 IRL 2 0 IRN 6 0 WKUPRQ nIRQ ciL 7 1 CILE 2 0 Read from IRN register Write to CIL or CILCL register Clock operational nIR22 nIR26 nIR28 nIR31 8 36 Chapter 9 Cache Memory ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY Chapter 9 Cache Memory This chapter is applied only to ML675001 series ML674001 series do not have the built in cache memory 9 1 Overview ML675001 series has an 8k byte cache memory unified cache that contains
253. eady TRIRQ bit 5 This bit indicates the transmitter ready status This bit goes to 1 when the interface transfers data from the transmit buffer SIOBUF to the transmit shift register Branching to an interrupt handler or writing transmit data to SIOBUF does not automatically reset this bit to 0 The program must reset it to 0 by writing 1 to it TRIRQ Description 0 Transmitter not ready 1 Transmitter ready 17 5 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 2 3 SIO Control Register SIOCON This register specifies the frame format for transfers over the asynchronous serial SIO interface The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIOCON _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ ES ENS _ _ _ 27 06 _ _ _ TSTB EVN PEN LN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8002008 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Operation is not guaranteed when the program changes the contents of this register during a transmit or receive operation Bit Descriptions e LN bit 0 This bit specifies the numbe
254. eady status and ones indicating errors detected during receive operations The CPU has read write access to this register The interface updates the lowest three bits at the end of each receive operation to indicate any errors detected Once an error bit goes to 1 to indicate detection of a receive error it remains 1 until the program writes 0 to it It does not automatically return to 0 if the next receive operation is free of the corresponding error The program is also responsible for resetting the transmitter and receiver ready flags to 0 by writing 1 to them Writes of 0 are ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 TRIRQRVIRQ PERROERRFERR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8002004 Access R W Access size 32 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions FERR bit 0 A 1 in this bit indicates detection of a framing error This error flag goes to 1 when a stop bit of 0 instead of 1 is detected which indicates a loss of frame synchronization FERR D
255. ecting EDO DRAM ML674001 Series ML675001 Series XA18 23 XA0 XD15 XDO XRAS N XDQM 1I XCAS N 1 XDQMIOVXCAS 0 XOE N XWE N XA18 XA1 XA12 XA1 SRAM x16 bits A17 A0 DQ15 DQO CS OE EDO DRAM x16 bits A11 A0 DQ15 DQO RAS UCAS LCAS OE WE Figure 11 24 Connecting 1M x 16 Bit EDO DRAM 2 MB 11 48 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller ML674001 Series EDO DRAM ML675001 Series x8 bits XA12 XA1 18 23 A11 A0 XD15 XD8 22 XDQM 1JXCAS 1 XDQMIOJXCAS N 0 XWE N EDO RAM x8 bits XA12 XA1 AT CAG DQ7 DQO RAS CAS OE WE Figure 11 25 Connecting Two 2M x 8 Bit EDO DRAMs 2 MB 11 49 ML 674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 6 4 Connecting SDRAM ML674001 Series ML675001 Series SDRAM x16 bits 18 23 13 0 XD15 XDO DQ15 DQO XSDCS N CS XWE N WE XRAS N XCAS N XDQM 1I XCAS N 1 XDQMIOJXCAS 0 XSDCLK XSDCKE Figure 11 26 Connecting 1M x 16 Bit SDRAM 8 MB 11 50 ML674001 Series ML675001 Series 18 23 XD15 XDO XSDCS_N XWE_N XRAS_N XCAS_N XSDCLK XSDCKE XDQM 1 XCAS_N 1 XDQM O XCAS N 0 ML674001 Series ML675001 Series User s Manual Chapter 11 XA12 XA1 XD15 XD8 XA12 XA1 XD7 XDO External Memory Controller
256. eive buffer empty interrupt requests TREMPEN Description 0 Transmit receive buffer empty interrupt request masked 1 Transmit receive buffer empty interrupt request enabled 19 6 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 2 5 Synchronous SIO Control Register SSIOCON SSIOCON is the register that controls transmit receive operations The SSIOCON register can be read or written using a program the SSIOCON register is to be modified make those changes after transmission or reception is completed If the SSIOCON register is modified during transmission or reception the current transmission or reception will not be performed correctly 7 6 5 4 3 2 1 0 SSIOCON SLMSB SFTSLV mE SFTCLK 1 0 At reset 0 0 0 0 0 0 0 0 Address OxB7B01010 Access R W Access size 8 bits NOTE denotes a reserved bit Always write O to the bit If 1 is written normal operation is not guaranteed Explanation of Bits e SFTCLK 1 0 bit 1 to bit 0 These bits select the synchronous clock in the master mode and are disabled in the slave mode SFTCLK 1 0 Description 0 0 1 8 HCLK 0 1 1 16 HCLK 1 X 1 32 HCLK See Chapter 7 Power Consumption Control for HCLK e SFTSLV bit 4 This bit selects the master or the slave mode SFTSLV Description 0 Master mode 1 Slave mode e SLMSB
257. ela du and 3 239 ES XA 23 0 output hold time 1 0 external 0 1 2 and 3 XA 23 0 output hold time 2 2 ES 2 t external 0 1 2 and 3 XD 15 0 input setup time TENE 20 2 m external 0 1 2 and 3 XD 15 0 input hold time cs 0 _ external 0 1 2 and 3 uae pos 3 tuc 5 tuc 2 XD 15 0 output Enable time T _ EN external 0 1 2 and 3 XD 15 0 output Disable time CL 6 external 0 1 2 and 3 30 pF XD 15 0 output hold time E 3 external 0 1 2 and 3 XIOCS N 1 0 output hold time 5 tuc 2 external 0 1 2 and 3 24 20 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics m DRAM Access Timing 2 25 10 2 75V Vpp 3 0 to 3 6V Ta 40 to 85 C SDRAM Item Symbol tions Minimum Typical Maximum Unit Notes XSDCS_N delay t 05 2 0 5tenc 5 The DRPC register specifies the SDRAM Kasa SDRAM access parameters tRAS tRCD tRP tDPL For XSDCKE delay SDRAM 0 5tspc O 5tspc 5 further details refer to section 11 2 9 of chapter 11 CL XDQNM O XDQM 1 dela O 5tspc 1 u 30 pF 0 5tspc Nsp1 tRCD O 5tspc XRAS
258. em that does not need the DRAM controller can save energy by disabling this unit through configuring the Mode Selection pins as explained in chapter 4 of this manual This has the effect of disable the clock signal input to this block and thus shutting them down Note however that this modification cannot be undone in software Furthermore manipulating the input signals in hardware after the MCU has been powered up not only does not work but also risks unreliable operation Note For further details on the DRAME N signals see Chapter 4 Chip Configuration Two CPU modes allow software to selectively reduce power consumption STANDBY stops the system clock oscillation entirely HALT mode stops the clock signals to the following functional blocks CPU system bus bus control circuitry and memory controller interfaces to built in RAM and external memory The software can save energy by stopping clock signals to individual function blocks The software can also save energy by dynamically changing the HCLK or CCLK frequency to 1 1 1 2 1 4 1 8 1 16 or 1 32 times the base frequency 1 32 ML675001 Series only Note For further details see Clock Gear below Power Management Functions The following Table summarizes the power management functions available to software Figure 7 1 gives a state transition diagram Operating Stopping or Restarting clock Mode Changing Clock sign
259. eptions An exception indicates the need to temporarily suspend normal program flow to process an interrupt request from a peripheral The CPU must therefore save the current CPU state before switching to the exception handler and subsequently restore it when the handler returns If there are simultaneous exceptions a fixed priority system determines the order in which they are accepted For further details see Section 2 12 10 Exception Priority Order 2 12 1 2 12 2 Switching to Exception Handler Switching to an exception handler involves the following operations 1 The CPU saves the return address in the corresponding link register R14 xxx This return address is the current program counter PC contents plus an offset 2 4 or 8 depending on the exception type and the CPU state at the time of the exception For further details see Table 2 2 Returning from Exception Handlers In the ARM state the return address is simply the address of the next instruction In the THUMB state however the offset sometimes changes to allow the exception handler to return with the same instruction MOVS PC R14 svc for a software interrupt for example regardless of the original state The CPU copies the current program status register CPSR contents to the corresponding save program status register SPSR xxx The CPU sets the CPSR mode bits to the exception handler s operating mode To prevent multiple exceptions from interferi
260. er to 0 disables masking allowing interrupt request with an interrupt level higher than that for the one currently being processed to take control and thus facilitating interrupt nesting Before an interrupt handler enables interrupt nesting however it must first save to the stack the contents of the link R14 irq and program status SPSR registers because the CPU hardware overwrites them when it accepts such a nested IRQ exception If the interrupt handler calls subroutines it must also protect the subroutine s return address in R14 irq from the overwrite inherent in accepting such a nested IRQ exception by shifting to system mode System mode uses the same register bank as user mode but allows the same access as IRQ mode to status registers and the like Note that an interrupt handler running in this or user mode must save to the stack the contents of the link R14 irq register and any work registers that it uses The following outlines the procedure Save contents of R14 SPSR irq and any necessary work registers Read IRN Switch to system mode and enable IRQ exceptions Save contents of system user mode link register and any necessary work registers Execute body of interrupt handler Restore contents of system user mode registers Disable IRQ exceptions and switch back to IRQ mode Clear corresponding bit in CIL register Restore contents of work registers SPSR irq and R14 irq Return from int
261. errupt Qv oc peu Bas gt 8 30 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 5 4 Important Notes on Interrupts Reading IRN Reading the IRN register clears it to zero e Invalid Interrupts Loss of the interrupt trigger after the interrupt controller asserts the interrupt request nIRQ signal to the CPU sometimes causes the read from the IRQ number IRN register to return 0 the interrupt source number assigned to the system timer interrupt The IRQ exception handler must therefore cross check the system timer interrupt status and branch to the corresponding interrupt handler only if the interrupt request is valid Otherwise it must ignore the invalid interrupt and simply return Interrupt exception to CPU Read interrupt source number Branch to corresponding interrupt handler Valid system timer interrupt Branch to system timer Return from interrupt interrupt handler 8 31 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 5 5 Waking from HALT and STANDBY Modes The following Figures represent timing charts for waking the CPU from HALT or STANDBY mode with interrupt requests HCLK CLKEN nIRx nIRQ IRN 6 0 IRL 2 0 HALT STANDBY STOP RUN for interrupt requests nIRO to nIR15 asynchronous clock HCLK CLKEN nIRx nIRQ IRN 6 0 IRL 2 0 b HALT STANDBY STOP RUN for interrupt requ
262. es to them are ignored The maximum possible setting for this register is 0x00010000 65 536 Operation is not guaranteed for higher values 12 14 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 9 DMA Transfer Complete Status Clear Registers DMACCINTO DMACCINT1 These registers are for clearing the DMA transfer complete status for the corresponding DMA channel Writing a 32 bit value to one resets the following bits in the corresponding DMAINTO or DMAINTI register DMA transfer complete IREQO or IREQ1 termination reason ISTAO or ISTA1 and abnormal termination cycle ISTPO or ISTP1 The program has only write access to these registers 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMACCINTO to 1 CCINT 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCINT 15 0 Address 0x7BE00114 CHO 0x7BE00214 CH1 Access Access size 32 bits 12 15 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 122 Operational Description A transfer request starts DMA transfers The DMA controller automatically stops when the specified number of transfers are complete The DMA controller utilizes Dual Address Mode transfer This type of transfer involves two memory or I O cycles The data being transferred is first read from a source address and subsequently
263. escription 0 No framing error detected 1 Framing error detected OERR bit 1 A 1 in this bit indicates detection of an overrun error This bit goes to 1 if the CPU has not read the previously received byte from the receive buffer SIOBUF register when the interface transfers the next one there from the receive shift register invalidating the previous data OERR Description 0 No overrun error detected 1 Overrun error detected PERR bit 2 A 1 in this bit indicates detection of a parity error This bit goes to 1 if the parity bit received does not match the parity calculated for the data bits received 17 4 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO PERR Description 0 No parity error detected 1 Parity error detected RVIRQ bit 4 This bit indicates the receiver ready status This bit goes to 1 when the interface updates the contents of the receive buffer SIOBUF from the receive shift register Branching to an interrupt handler or reading the received byte from SIOBUF does not automatically reset this bit to 0 The program must reset it to 0 by writing a 1 to it Note that the interface always updates SIOBUF and sets this bit to 1 whenever a receive operation is complete regardless of any framing overrun or parity errors detected RVIRQ Description 0 Receiver not ready 1 Receiver r
264. escription 0 No interrupt request pending 1 Interrupt request pending The following Table summarizes how for interrupt source number n the bit IRQ n contents depend on the nIRn source and the interrupt level setting from the interrupt level control registers ILCO and ILC1 nlRn Source Interrupt Level Setting from ILCx Bit IRQ n X 0 0 1 Nonzero 1 to 7 0 0 Nonzero 1 to 7 1 8 7 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 2 Software Interrupt Register IRQS Writing 1 to bit 1 in this register generates a software interrupt request which the interrupt controller maps to nIR8 This interrupt request has the interrupt source number 8 interrupt level setting from interrupt level control register 1 Writing 0 to this bit cancels the interrupt request The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRQS l _ _ _ _ 1 _ _ _ _ _ _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e e a E P e e _ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000004 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that
265. ess in a bank for which the cacheable setting has not been made the cache controller does not carry out the hit miss judgment for the access made by the CPU but always carries out an access to the actual memory This type of access operation is called a non cacheable access operation Lock Function Locking is the function of retaining the contents of the cache memory within the cache memory itself as follows When there is a cache hit the normal cache hit operation is made e When there is a cache miss the contents of the locked cache memory is retained by carrying out a cache miss operation to a way that has not been locked 9 6 9 3 5 9 3 6 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY In general in the cache memory while there is the action of shortening the average access time of instructions and data it also has the nature of lengthening the access time in the worst case when considered in the instantaneous behaviour This is because accesses occur that are not intended by the software such as the occurrence of a read access of one block when there is a cache read miss or the occurrence of a write access due to a write back operation when there is a cache write miss In the case of programs in which the timing is very critical such as in some types of interrupt servicing this instantaneous increase in the access time can create problems lock function is used to reduce the effect of su
266. ests nIR16 to nIR31 asynchronous clock EXTINR 6 0 EXTLEXILVL 2 0 nFIQ nIRQ c RUN synchronous clock 8 32 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 5 6 Error Response Accessing addresses 0x78000030 to Ox780FFFFF in the region assigned to the interrupt controller INTRC produces a data abort exception 8 5 7 Interrupt Response Times Fast interrupt nFIQ 4 clock cycles from EFIQ N external interrupt input to CPU FIQ input Interrupt request sources nIRO to nIR15 2 clock cycles from IRQ request to CPU IRQ input Interrupt request sources 3 clock cycles from IRQ request to CPU IRQ input nIR16 to nIR21 nIR24 nIR25 Interrupt request sources 5 clock cycles from EXINTx external interrupt input to CPU nIR22 nIR26 nIR28 nIR31 IRQ input Note For the delays between the IRQ or FIQ exception request to the CPU and the actual start of the corresponding exception handler refer to the ARM7TDMI data sheet 8 33 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 6 Interrupt Acceptance Timing Charts 8 6 1 FIQ Interrupt Timing Chart FIQEN 0 External fast interrupt request EFIQ_N nEFIQ INTRC nFIQ Clock operational 8 6 2 IRQ Interrupt Timing Chart nIRO to nIR15 CLKEN x HCLK nIR N x ILRN IRQ N x IRL 2 0 IRN 6 0 x WKUPRQ nIRQ x CIL 7 1 CILE 2 0 R
267. eviation R W Size Initial Value 0xB7D00000 PWM register 0 PWRO R W 16 0x0000 0xB7D00004 PWM period register 0 PWCYO R W 16 0x0000 0xB7D00008 PWM counter 0 PWCO R W 16 0x0000 0xB7D0000C PWM control register O PWCONO R W 16 0x0000 0xB7D00020 PWM register 1 PWR1 R W 16 0x0000 0xB7D00024 PWM period register 1 PWCY1 R W 16 0x0000 0xB7D00028 PWM counter 1 PWC1 R W 16 0x0000 0xB7D0002C PWM control register 1 PWCON1 R W 16 0x0000 0xB7D0003C Interrupt status register PWINTSTS R W 16 0x0000 16 2 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator 16 2 Register Descriptions 16 2 1 PWM Registers PWRO PWR1 These registers specify the duty the High level pulse width for the corresponding PWM outputs Note that the setting must be less than that in the corresponding PWM period register PWCYx which specifies the PWM output frequency and thus the period See register description below Duty PWCY 1 65536 PWCY x 100 The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWRO to 1 PWR 15 0 1 1 1 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7D00000 CHO 0xB7D00020 CH1 Access R W Access size 16 bits 16 3 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator 16 2 2 PWM Period Registers PWCYO and PWCY1 These registers specify the periods for the corresponding PWM outputs according t
268. fast interrupt request FIQ The interrupt controller assigns priority of execution to simultaneous interrupt requests by comparing their interrupt levels If a new interrupt request has a higher interrupt level than the one currently being processed the interrupt controller asserts the interrupt request nIRQ signal to the CPU The IRQ exception handler reads the interrupt source number and level from interrupt controller registers Assigning Priority to Interrupt Requests 1 The higher the numerical value the higher the priority 2 If two interrupt requests have the same interrupt level priority goes to the one with the higher interrupt source number 3 Reading the IRN register in response to an IRQ exception masks interrupt requests at or below the new interrupt level External Internal Interrupt Sequence 0 Specify interrupt level software Setting 1 bit 7 in the CPU s current program status CPSR register to 0 and specifying a nonzero interrupt level for the interrupt disables masking An interrupt level of zero masks interrupts Note Sources nIR22 nIR26 nIR28 nIR31 require an additional preliminary step specifying the detection mode and polarity in the IRQ detection mode setting register IDM When switching triggers to edge detection write to either the IRQ clear IRCL register or the IRQ register A IRQA to initialize the edge detection circuitry before disabling masking 1 Wait for interrupt har
269. fer complete status clear register DMACCINTO 32 Channel 1 0 7 200 DMA channel mask register DMACMSK1 R W 32 0x00000001 0x7BE00204 DMA transfer mode register DMACTMOD1 R W 32 0 00000040 0x7BE00208 DMA transfer source address register DMACSAD1 R W 32 0x00000000 0 7 0020 DMA transfer destination address register DMACDAD1 RW 32 0x00000000 0x7BE00210 DMA transfer count register DMACSIZ1 RW 32 0x00000000 0 7 00214 DMA transfer complete status clear register DMACCINT 1 32 16 bit access Note These registers require word 32 bit access Operation is not guaranteed for byte 8 bit or halfword 12 4 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 Register Descriptions 12 2 1 DMA Mode Register DMAMOD This register is for specifying DMA channel priority The program has read write access to this register The contents after a reset are 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMAMOD _ _ _ _ _ _ EN EN i _ _ _ _ _ _ _ _ After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 7 0000 Access R W Access size 32 bits Note These
270. ffered 16450 operation For buffered operation this bit goes to 1 when there is a data error parity error framing error break interrupt anywhere in the queued data Reading the data with the error from RBR or discarding it by clearing the entire queue and then reading LSR resets this bit to 0 LSR 7 Description 0 No data errors buffered operation 1 Parity error framing error or break interrupt buffered operation 18 17 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 9 Modem Status Register UARTMSR This register allows the CPU to monitor the status of four control signal inputs from the modem or peripheral equipment CTS DSR RI and DCD The CPU uses the UARTMSR register to access the ACE data bus interface and read these inputs In addition to the four bits giving the current status this register also provides four delta bits indicating whether these inputs have changed since the CPU last read this register delta bit goes to 17 if the corresponding control signal has changed since the last read and returns to 0 when the CPU reads this register Bits MSR 4 to MSR 7 monitor CTS DSR RI and DCD respectively 1 indicates Low level input 0 High If IER 3 in the interrupt enable register is 1 enabling modem status interrupts a 0 to 1 transition in the corresponding delta bits MSR 0 to MSR 3 produces a
271. for future expansion They return O for reads Writes to them are ignored Bit Descriptions e GPISA 7 0 GPISB 7 0 GPISC 7 0 GPISD 7 0 bits 0 to 7 GPISE 9 0 bits 0 to 9 A 1 in a bit indicates an interrupt request pending from the corresponding pin GPISA 7 0 GPISB 7 0 GPISC 7 0 GPISD 7 0 Description GPISE 9 0 0 No interrupt pending 1 Interrupt request pending Example GPISA bit 0 goes to 1 a at a rising edge of an input signal going to PIOA 0 pin when the following register combination is set GPIPA 0 1 plus GPPMA 0 0 and GPIEA 0 1 b at a falling edge of an input signal going to PIOA 0 pin when the following register combination is set GPIPA 0 0 plus GPPMA 0 0 and GPIEA 0 1 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 2 7 Port Function Select Register GPCTL GPCTL This register configures groups of GPIO pins within each GPIO port as their primary or secondary functions The CPU has read write access to this register The register contents after a reset are 0 0000 15 14 13 12 11 10 9 7 6 5 2 1 _ 14 0 After a reset 0 0 0 0 0 0 0 0 0 0 0 0 Address Access R W Access size 16 bits Note 0xB7000000 These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptio
272. for the data to be received next RESTR Description 0 Acknowledge signal transmission 1 No acknowledge signal transmission 20 3 ML674001 Seies ML675001 Series User s Manual Chapter 20 12 e START bit 4 This bit indicates the presence or absence of a start byte in the I2CSAD register set the START bit to 1 set the I2CSAD slave address mode setting register to 0000 0001b the start byte pattern defined by the I2C specification in advance START Description 0 No START byte 1 START byte 20 4 ML674001 Seies ML675001 Series User s Manual 20 2 2 2C Bus Slave Address Mode Register I2CSAD Chapter 20 DC The I2CSAD register sets the address of the slave device as well as the data transfer direction transmission reception The data in this register can be read and written by programs time of reset is 0x00 Set the I2CSAD register before setting the I2CCON register the following a general call address to the I2CDR register The value at the Specify the address of 7 6 5 4 0 I2CSAD 0 6 0 I2CRW At reset 0 0 0 0 0 Address OxB7800004 Access R W Access size 8 bits Explanation of Bits 12 CRW bit 0 The I2CRW bit designates the communication direction transmission reception to slave device I2ZCRW Description 0 Transmission 1 Reception e SAD 6 0 bits 7 to 1
273. fy the column length the dividing line 8 to 10 bits for address multiplexing of the row and column address outputs to the XA pins DRAM cannot use column lengths of 11 and higher 3 This bit represents a column address bit during EDO DRAM column output During SDRAM operation however it specifies auto pre charge going to 0 during column output to disable auto pre charge during READ and WRITE commands 4 For SDRAM ACT READ and WRITE commands the XA 18 12 outputs have the same value the bank number during both row and column output 11 28 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller Distributed CAS before RAS CBR Refresh The DRAM controller provides a facility for automatically performing distributed CBR refresh operations at regular intervals e Specify the distributed refresh periods in the RFSHO and RFSHI registers e Start and stop operation by changing the RFRSH bit in the DRMC register Note that manual refresh operation is available at any time by writing the CBR refresh command to the DCMD register Self Refresh SDRAM self refresh operation is used for example as part of power management Start and stop operation by writing the corresponding commands to the DRCMD bits in the DCMD register start SDRAM self refresh and end SDRAM self refresh The start command stops the SDRAM clock fixing the SDCLK output at High level the stop command restarts output Operat
274. g Clocks SIN Start Data bit 5 to 8 Stop Sample CLK f f nUARTINT Received Data Available nUARTINT Received Line Status RD LSR read RBR read tSINT MAX 1000ns tRINT 1 Baud rate Clock Figure 18 4 Receive Timing 18 24 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte Z SIN Stat Data bit s 08 Stop Sample CLK 7 FIFO below Trigger Level nUARTINT Received Data Available FIFO at or above tSINT tRINT Trigger Level nUARTINT Received Line Status tRINT RD LSR read RBR read tSINT MAX 3 Buad rate Clocks tRINT 1 Baud rate Clock Figure 18 5 Reading First Byte from Receive Queue Setting RDR 2 SIN Start 1 Data 0145 to 8 X Parity Stop Sample CLK JL FIFO below Trigger Level nUARTINT Z Received Data Available tSINT y E tRINT FIFO at or above ME des Trigger Level nUARTINT Received Line Status RD RBR read LSR read RBR read Previous Byte read from FIFO tSINT 3 Buad rate Clocks For a timeout 8 Baud rate Clocks 1 Baud rate Clock Figure 18 6 Reading Last Byte from Receive Queue 18 25 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 3 3 Generating Baud Rate Clock The following is the formu
275. gister has elapsed The maximum such interval is approximately 24 ms The following Table summarizes the events producing shifts to and from this mode Shift to STANDBY mode Wake from STANDBY mode Write 1 to STBY bit Unmasked interrupt request e GPIO e External interrupt request configured for level detection Reset Notes In order to use the External Interrupt Request for exiting STANDBY mode the EXINT should be configured for LEVEL Detection If using GPIOs the GPIO interrupt signal should be held active until exiting STANDBY 7 12 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 4 Using Power Management with DRAM Writing 1 to BCKCTL 8 to stop the clock signal to DRAM controller does not automatically activate DRAM self refresh operation The software must explicitly request activation and deactivation by writing 110 and 111 respectively to the DRCMD bits in the DRAM command DCMD register For SDRAM self refresh operation stops XSDCLK output Accessing the DRAM address space during self refresh operation triggers an abort exception 7 4 1 Activating Self Refresh Operation The following is the procedure for activating self refresh operation before stopping the clock signal to the DRAM controller or switching to STANDBY mode 1 Write 110 in the register DRCMD bits to activate self refresh operation The DRAM controller then suspends dist
276. gister on the rising edge of the synchronous clock After that data reception continues and when one frame of data has been received the content of SSIOREG are transferred to SSIOBUF At the same time the BUSY flag is cleared to 0 and the receive complete flag RXCMP of the synchronous SIO interrupt request register SSIOINT is set to LAS data is received before the previously received data is read out of the transmit receive buffer register SSIOBUF an overrun error will occur the previously received data will be overwritten Receive operation flow SSIO Receive Operation Write Tx data to SSIOBUF Busy set SSIOST 0 1 Program may write ne SDI data shifted into SSIOREG Tx data to SSIOBUF far continuous read SSIOREG data moved to SSIOBUF operation Busy flag clear SSIOST 0 0 Receive complete SSIOINT 1 Receive Complete RXCMP 1 Interrupt Note In the above flow diagram all tasks are implemented automatically in hardware Once a frame of data has been received and written to SSIOBUF the application program should read this data from SSIOBUF 19 11 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 SSIOBUF write signal TEE i BUSY flag 31 SSIOREG data transfer signal a 01111 Buffer empty interrupt sstcok o Internal shift counter D D D D D D D D Transmit data SDO pin Transmit complete interrupt UNIES 00yb01xb02 503xD04YD05 D06 D Figure
277. gisters from THUMB State The THUMB state does not include the upper registers R8 to R15 as part of the standard register set Assembly language programs can however obtain limited access to them for use as high speed temporary storage There are special MOV instructions for transferring data from a lower register to an upper one and in the reverse direction The CMP and ADD instructions also accept an upper register for comparison with or addition to a lower register 2 6 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 9 Program Status Registers The CPU has six status registers the current program status register CPSR and five save program status registers SPSRs These registers have the following functions e Status flags indicate the results of the last arithmetic instruction executed by the ALU e Control bits enable and disable interrupts e Mode bits specify the CPU operating mode Figure 2 5 gives the bit positions in a program status register Condition code flags Reserved Control bits 31 30 29 28 27 26 25 24 23 8 7 6 5 4 3 2 1 0 JE i e wi wo Overflow Mode bits Carry borrow expansion Operating state 1 5 Zero FIQ disable Negative Less than IRQ disable Figure 2 5 Program Status Register Format 2 9 1 Condition Code Flags The N Z C and V bits are condition code flags
278. gisters that control this timer are outlined in the Register List table on page 15 3 The System Timer is organized around a 16 bit counter The input time base to the System Timer block is the CCLK The CCLK input is divided by a factor of 16 and this forms the time base for the counter Once enabled by writing a 1 to the Timer Enable Register TMEN the counter counts up each cycle of the CCLK 16 input signal starting from the initial value programmed in to the Timer Counter Register TMC Note that when the user program sets the Timer Reload Register TMRLR the hardware simultaneously copies the contents of TMRLR to the Timer Counter TMC register The user program does not have direct access to the TMC register The value of the counter is incremented at each cycle of the clock When the counter has reached the value of OXFFFF an overflow occurs and bit OVF of the System Timer Overflow Register TMOVER is set to 1 thus asserting an interrupt request signal In the next processor clock cycle the timer counter is reloaded with the program specified value from TMRLR register and continues counting up The interval of the System Timer Overflow is defined as follows Interval uSEC 16 x 65536 TMRLR 15 0 CCLK MHz The time base for System Timer is CCLK and as noted in Chapter 7 CCLK can be divided by setting the Clock Gear Control Register CGBCNTO as necessary The user should note that changing CGBCNTO register wil
279. gital converter The hardware automatically resets this bit to 0 when conversion is complete 21 5 ML674001 Chapter 21 Seies ML675001 Series User s Manual Analog to Digital Converter 21 2 3 1 After a reset Analog to Digital Converter Control Register 2 ADCON2 This register specifies the operating clock frequency for the analog to digital converter register The program has read write access to this register The contents after a reset are 0x0003 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ _ _ _ 220 _ _ _ _ _ _ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Address 0xB6001008 H Access R W Access size 16 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions ACKSEL 1 0 bits 1 and 0 This field specifies the divisor for deriving the operating clock from CCLK ACKSEL Channel 1 0 0 0 Reserved 0 1 CCLK 2 1 0 CCLK 4 1 1 CCLK 8 Notes In ML674001 series choose the divisor so that the period to produce is 200 1000 ns In ML675001 series choose the divisor so that the period to produce is 80 1250 ns The conversion time 25 clock cycles depends on the operating frequency and ACKSEL The combination of 33 MHz for CCLK and 118 for ACKSEL for example yields one of 240 25
280. her counter overflow produces an interrupt request or a system reset watchdog timer operation only The CPU has read write access to this register A write protection function shields the contents from random writes The program must first write and then the new value The register contents after a reset are 0 00 7 6 5 4 3 2 1 0 OFINT WDTBCON WDHLT MODE WDCLK 1 0 0 0 0 0 0 0 0 0 Address OxB7EO00004 Access R W Access size 8 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions WDCLK 1 0 bits 0 and 1 These bits specify the frequency divisor for deriving the operating clock from CCLK WDCLK 1 0 12 2 Description 1 0 0 0 CCLK 32 0 1 CCLK 64 1 0 CCLK 128 1 1 CCLK 256 ITM bit 3 This bit specifies the operation mode watchdog timer or interval timer ITM Description 0 Watchdog timer 1 Interval timer e bit 4 This bit controls interval timer ITM 1 operation ITEN Description 0 Stop 1 Start Enable 14 3 ML674001 Series ML675001 Series User s Manual Chapter 14 Watchdog Timer WDT e OFINTMODE bit 6 This bit specifies the action after counter overflow watchdog operation only OFINTMODE Description 0 Interrupt request 1 System reset e WDHLT
281. his bit goes to 1 when the current character moves from the UARTTHR register to the transmitter shift register Writing to the UARTTHR register resets this bit to 0 Reading the UARTLSR register does not For buffered operation this bit goes to 1 when the transmit queue is empty Writing a byte to the transmit queue resets this bit to 0 If IER 1 is 1 enabling THRE interrupts the transition to 1 produces a THRE interrupt of priority 3 in the UARTIIR register If THRE is the source for the interrupt indicated by the UARTIIR register reading the UARTIIR register resets this bit to 0 LSR 5 Description 0 UARTTHR contains transmit data 1 UARTTHR ready to accept data 18 16 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte LSR 6 bit 6 Transmitter empty This bit goes to 1 when the UARTTHR and transmitter shift TSR registers both empty Writing a character to the UARTTHR register clears the UARTLSR register to 0 driving SOUT at Low level until the hardware transmits that character Reading the UARTLSR register does not reset this bit to 0 For buffered operation this bit goes to 1 when the transmit queue and the shift register are both empty LSR 6 Description 0 There is data in either UARTTHR or TSR 1 UARTTHR and TSR are both empty LSR 7 bit 7 This bit is always 0 during unbu
282. his register The DMA controller increments the address by the transfer size in bytes after each successful read if the transfer source is an incremental address device For a fixed address device however the address does not change The program has read write access to these registers The contents after a reset are 0x00000000 to 1 After a reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSAD 31 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSAD 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x7BE00108 CHO 0x7BE00208 CH1 Access R W Access size 32 bits Note The DMA controller increments the source address DMACSADO or DMACSAD 1 by the transfer size in bytes if the corresponding device type so specifies The hardware enforces alignment by internally ignoring the lowest address bits as appropriate for the transfer size but reading an address register returns those bits exactly as written Example Writing address of 0x1000001 1 Word 32 bit transfer The controller internally forces the lowest 2 bits to 00 for an effective address of 0x10000000 Reading the register however returns 0x10000011 Halfword 16 bit transfer The controller internally forces the lowest bit to 0 for an effective address of 0x10000010 Reading the register however returns 0x100000
283. ication Codes The flash memory program routine loads the application codes to be written to flash memory via the JTAG interface and then writes them to built in flash memory After writing is finished apply protect to flash memory as necessary Note By changing the flash memory program routine it is possible to program flash memory mounted on the board in addition to built in flash memory 22 4 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 22 2 3 Flash Memory Programming Method Using the Built in Boot Program This method is used to program flash memory using a serial interface This method is used to start the built in boot program load the flash memory program routine via the UART to built in RAM execute the routine and program flash memory Flash memory is programmed when the flash memory program routine issues a command conforming to the JEDEC standard SDP command sequence 1 Pin Settings The following table lists the pin settings necessary to start the built in boot program at the time of reset As for the JTAG pin set it to the setting when it is not used Pin name Setting JSEL L BSEL 1 H BSEL 0 L or 2 Example of a Connection Circuit Connect the UART with the host such as a PC Serial intaerface eg RS 232C HOST Computer etc Force the pins according chapter 5 e d fe Eun ee iral m Set
284. in the input signal at the specified level until clock supply resumes For further details on starting and stopping the clock signal see Chapter 7 Power Management Bit Descriptions e GPIEA 7 0 GPIEB 7 0 GPIEC 7 0 GPIED 7 0 bits 0 to 7 GPIEE 9 0 bits 0 to 9 These bits control the masking of interrupt requests from the corresponding port pins PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 GPIEA 7 0 GPIEB 7 0 GPIEC 7 0 GPIED 7 0 Description GPIEE 9 0 0 Disable interrupts 1 Enable interrupts ML674001 Series ML675001 Series User s Manual Chapter 13 13 2 5 Port Interrupt Polarity Register GPIPA GPIPB GPIPC GPIPD and GPIPE These registers specify the triggering edge for interrupt requests from the corresponding port pins PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 Detection of an edge with the specified polarity in the input from a PIOx pin configured GPPMXx register for input with interrupts enabled GPIEx register triggers an interrupt request The CPU has read write access to these registers The register contents after a reset are 0 0000 GPIPA 7 0 GPIPB 7 0 GPIPC 7 0 GPIPD 7 0 GPIPE 9 0 GPIPC GPIPD 4 GPIPE uses bit9 amp bit8 For other GPIPx bit9 amp bit8 are After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB
285. ing 0 to this bit will clear to 0 but writing 1 will set to 1 OERR Description 0 No overrun error 1 Overrun error e SFTCT 2 0 bit 7 to bit 5 These bits indicate the count value of the 3 bit shift counter when transmitting or receiving data While data is not being transmitted or received the counter indicates O00 binary Each time the transmit receive data is shifted by one bit the counter increments by 1 counter returns to 000 binary when the transmit or receive operation is completed or when 0 is written to the BUSY bit during reception 19 4 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 2 3 Synchronous SIO Interrupt Request Register SSIOINT The SSIOINT register indicates a synchronous SIO interrupt request The SSIOINT register can be read or written using a program Writing 1 to a bit clears that bit 7 6 5 4 3 2 1 0 SSIOINT TREMP RXCMP TXCMP At reset 0 0 0 0 0 0 0 0 Address OXB7B01008 Access R W Access size 8 bits NOTE denotes a reserved bit Always write 0 to the bit If 1 is written normal operation is not guaranteed Explanation of Bits e TXCMP bit 0 This bit indicates that data transmission is complete TXCMP Description 0 Transmission not complete 1 Transmission complete e RXCMP bit 1 This bit indicates that data reception is complete
286. ing with XWAIT Memory Wait Cycles 5 0 XA 23 0 XWE N XBWE_N 1 XBWE 0 XBS_N 1 XBS 0 XOE N XWAIT XD 15 0 External Memory Controller 7 2 E g gt ae Gn gt Figure 11 6 External Bank 16 Bit External Bus Half word Write OE WE Pulse Width 1 Minimum Setting with XWAIT Memory Wait Cycles 11 36 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 4 1 3 EDO DRAM Access XA 23 0 XRAS N XDQNM 1 XCAS N 1 XDQM O XCAS NI0 XWE N XOE N 2 jQ 0 2 XD 15 0 Figure 11 7 EDO DRAM Word Read XA 23 0 XRAS N XDQM 1yXCAS N 1 1 a XDQM O XCAS N 0 XWE N XOE N XD 15 0 D A Figure 11 8 EDO DRAM Word Write XA 23 0 CAS A XRASN 8 NI XDQM XCAS NO KX XWEN 444 XEN D A XD 15 0 Figure 11 9 EDO DRAM Half word Read 11 37 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller XA 23 0 RAS N XDQOM 1I XCAS XDQMIOJXCAS 0 XWE N XOE N XD 15 0 CAS A EL Figure 11 10 EDO DRAM Half word Write XA 23 0 XRAS N XDQM 1I XCAS XDQMIOJXCAS N 0 XWE N XOE N XD 15 0 CAS A TNs A 7i M S Figure 11 11 EDO DRAM Byte LSB Read XA 23 0 RAS N XDQM 1I XCAS
287. ing device making it possible to select erase and programming algorithms suitable for the device The manufacturer code and device code are output by an SDP command of four cycles the Software ID command to the command register The following contents are output by the last read operation ________________ Output Description 0x0000 0x0062 Manufacturer code A 0x0001 0x0046 Device code ML67Q4002 ML67Q5002 0x0002 Device code ML67Q4003 ML67Q5003 The operation ends when the Read Reset command is entered 22 4 9 Verify Protect Whether or not flash memory is protected is verified by entering an SDP command of four cycles the Verify Protect command to the command register The following contents are output by the last read operation Address Output 0x0002 0x0001 Block Protected ML67Q4002 ML67Q4003 0 0000 Not Block protected ML67Q5002 ML67Q5003 0x0003 0x0001 Chip Protected 0x0000 Not Chip protected The operation ends when the Read Reset command is entered 22 4 10 Hardware Reset The hardware reset operation resets an erase operation stops a program operation or cancels the mode entered by an SDP command 22 11 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 22 4 11 Detecting the End of an Erase or Program Cycle The end of an erase or program cycle can be detected by DATA N polling or the toggle bit 1 DATA N Polling DATA
288. interrupt sources are coming from internal peripherals such UART SIO etc The other four interrupt sources from external inputs EXINTO EXINT2 and EXINT3 addition it supports one external fast interrupt source through the pin EFIQ The 8 level priority control feature allows the customer to define the interrupt priority level for the different interrupt sources External interrupt sources can be configured to be edge triggered or level triggered Also for edge triggered devices the customer can configure the interrupt controller to trigger either on the negative or positive edge of the input is falling edge triggered The following is an overview of main features of the interrupt controller Features One fast interrupt FIQ source external 27 interrupt IRQ sources external and internal Independent masking for each FIQ and IRQ source Independent interrupt priority level settings for each IRQ source Priority control blocking IRQ requests with priority levels at or below those for interrupt requests currently being processed e Choice of level or edge sensing for external IRQ sources EXINTO to EXINT3 nIR22 nIR26 nIR28 and nIR31 e Conversion of external interrupt requests to wake up requests for restarting the clock and thus waking the LSI from STANDBY mode 8 1 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 1 1 Com
289. ion and on the memory access duration in the figure The wite back operation is in the The above example is of an operation when the succeeding access is a read hit figure 9 14 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY Example of non cacheable operation bclk excu de ERI Eu eee eLeESeeuem ee I I 2p d bB 4 4 d t d F 4 d b M B d b M B d t Q L22l2Rp 222 l L 41 L 4j Jd LP 1 Jj L L rF 4j r rF 4 t 4 zzxLL Ilzg 2 Lb ll LlL 2 2 l l zLEz lI 2 2L L b l Lb2z z 2 Lb l2 2 Ll l T p bB 1 4 4 f Q4 F 1 4 FB 4 4 bB 4 FB 4 t 4 Bp 2I 2 2 LB i L 4 rR Jd L 4 4 L L 4 LR L F 4 T 4 LL LR 41 l rl l I L l21 L l LRLR 2 l LR LI L 2j rIlI ties I 2p d bB 4 H d t d F 4 d b M B d b M B d t Qq 4 2 lt lt 4 lt
290. ion is not guaranteed if the program writes any other command to the DCMD register between the start and end commands During Self Refresh changes to SDMD register or other SDRAM settings will have unpredictable results SDRAM Commands The DRAM controller provides the following SDRAM command outputs Command Abbreviatio x xe n 5 9 O Address 9 z z Z 1 n A11 A10 A9 0 Mode register set MRS H H L L L L H OPECODE CBR auto refresh REFH H H LIL H H X X X Start self refresh SELF H L L L L H H X X X End self refresh SREX L H X X X L X X X Pre charge all banks PALL H H L L H L H X H X Bank active ACT H H H BA RA RA Write 2 WRIT H H L CA Read 2 READ H H L CA No operation NOP H H H X X X Deselect device DESL H H X H X X X Power down 1 X L X X X Continue self refresh 1 L L L L L X H X X X H High level L Low level X Don t care level High or Low BA Bank number RA Row address CA Column address Notes 1 These represent pseudo commands defined for purposes of explication 2 Unnecessary byte lanes are all at High level masked state 11 29 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller SDRAM Power Down Mode The DRAM controller drives the clock en
291. ion mode for nIRm m 22 26 28 or 31 IDMPn n 22 26 28 or 30 specifies the polarity for nIRm m 22 26 28 31 IDMn IDMPn Detection Mode Polarity Level detection Low level input High level input Edge detection Falling edge Rising edge Notes If the External Interrupt EXINT is going to be used for exiting STANDBY mode it must be configured for LEVEL detection 8 23 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 15 Interrupt Level Control Register ILC This register specifies the 3 bit interrupt priority levels for interrupt request pairs from nIR16 to nIR31 The CPU has read write access to this register 31 30 29 28 27 26 25 24 21 17 16 1 1 1 1 1 1 ILC _ ILC30 _ ILC28 ILC26 ILC24 After a reset 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 5 1 0 _ ILC22 _ ILC20 ILC18 ILC16 0 0 0 0 0 0 0 0 0 0 0 Address Ox7BF00018 Access R W Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Always write 0 to these bits Bit Descriptions ILCI6 bits 0 2 ILCIS bits 4 to 6 ILC20 bits 8 to 10 ILC22 bits 12 to 14 ILC24 bits 16 to 18 ILC26 bits 20 to 22 28 bits 24 to 26 ILC30 bits 28 to 30 ILCn specifies the 3 bi
292. ion of Flash Memory Programming The following two methods are available to program built in flash memory of this LSI 22 2 2 Programming flash memory using the JTAG debug function This method is used to program flash memory using the JTAG debug function This method allows the on board programming of flash memory Using the built in debug function this method is used to load the flash memory program routine to built in RAM or external SRAM on the board via the JTAG interface execute the routine and program flash memory Programming flash memory using the built in boot program This method is used to program flash memory using a serial interface This method allows on board programming of flash memory In this method the built in boot program loads the flash memory program routine via the universal asynchronous receiver transmitter UART to built in RAM executes the routine and programs flash memory Flash Memory Programming Method Using the JTAG Debug Function This method programs flash memory using the JTAG debug function This method is used to load the flash memory rewrite routine to built in RAM or external SRAM on the board via the JTAG interface execute the routine and program flash memory Flash memory is programmed when the flash memory program routine issues a command conforming to the standard SDP command sequence downloading and starting of the flash memory program routine and the transfer of applicati
293. k CLKSEL 2 0 settings 110 and 111 2 Do not change the clock CLKSEL 2 0 setting while the timer is in operation 15 15 Chapter 16 PWM Generator ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator Chapter 16 PWM Generator 16 1 Overview This block provides two pulse width modulation PWM outputs PWMOUTO PWMOUT I that support changing the duty under program control with each cycle These outputs have a resolution of 16 bits 16 1 1 Components The block diagram in Figure 16 1 illustrates the different components within the PWM Generator PWCYO 1 1 CCL n ees S PWCO q Pwwouro 1 16 CCLK 8 1 32 1 lt gt interrupt request PWRO 70 z n PWCY1 2 1 1 CCLK 90 PWC1 Q 1 16 CCL 8 8 1 32 CCLK gcc gt PWMI interrupt request PWR1 Figure 16 1 PWM Generator Components 16 1 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator 16 1 2 Pin List Pin Name 1 0 Description PWMOUTO PWM output 0 Secondary function for general purpose port PIOC O PWMOUT 1 O PWM output 1 Secondary function for general purpose PIOC 1 16 1 3 Register List Address Name Abbr
294. ks stopped by DRAME pins settings Cacheable setting and External ROM used 24 4 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 24 4 AC Characteristics 24 4 1 AC Characteristics for ML674001 Series B Power Supply On OFF Timing 2 25 to 2 75 3 0 to 3 6V Ta 40 to 85 C Item Symbol s Minimum Typical Maximum Unit Notes AVDD Supply on Delay tavpp 0 ns VDDcore Supply on tvDDCORE e 0 ns Delay ON AVDD Supply off Delay 0 ns VDDio Supply off Delay tvppio_oFF 0 ns 24 5 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B Clock Timing 2 25 to 2 753 Vpp 3 0 to 3 6V Ta 40 to 85 C Item Symbol Condi Typical Maximum Unit Notes tions Input Clock frequency fc 1 33 333 MHz Input Clock cycle time tc 30 1000 Input Clock High level t 44 pulse width EM Input Clock Low level ns 14 pulse width Input Clock Rise time tcn 4 For external clock input Input Clock Fall time tcr 4 XSDCLK frequency fspc 1 33 333 MHz The same frequency as HCLK XSDCLK cycle time tspc 30 1000 XSDCLK High level
295. l affect the operation of other peripherals in this LSI To avoid timing conflicts in the System Timer block the program must leave the following interval between successive writes to TMRLR register n x HCLK 79 x CCLK The System Timer operation can be stopped at anytime by writing a 0 to the System Timer Enable Register TMEN Timer overflow interrupt Timer counter overflow triggers an interrupt request and sets the OVF bit in the counter overflow register TMOVER to 1 Writing 1 to TMOVER clears the interrupt request 15 13 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 3 2 Auto Reload Timers There are six auto reload timers each with its own counter and settings for such parameters as operating clock frequency and operation mode 1 One shot operation A match between the counter TIMECNTx and compare TIMECMPx registers reloads TIMECNTx from the corresponding timer base register TIMEBASEx and resets the START bit to 0 to stop counting The timer then generates an interrupt request if interrupts are enabled Note however that the hardware does not automatically cancel this interrupt request The interrupt handler must do so by writing 1 to the STATUS bit mek TLE LULU UU UU UU START TIMECNT 100 101 V102 V 103 V104 V 105 V 106 y 107 100 lt START bit automatically TIMECMP EE goes to o after match TIMEBASE 0 0 between TIMECNTx
296. l register SIOTCN R W 32 0x00000000 17 2 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 2 Control Register Descriptions 17 2 1 SIOBUF After a reset Transfer Buffer Register SIOBUF This register holds transfer data The CPU has read write access to this register but the same register has two separate functions It functions as a receive buffer for reads and as a transmit buffer for writes When a receive operation ends the interface transfers the contents of the receive shift register to the receive buffer and generates a receive interrupt request The receive buffer contents remain valid until the end of the next receive operation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIOBUF 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8002000 Access R W Access size 32 bits Note These bits are reserved for future expansion They return O for reads Writes to them are ignored 17 3 ML674001 Chapter 17 Series ML675001 Series User s Manual SIO 17 2 2 SIOSTA After a reset SIO Status Register SIOSTA This register contains flags indicating asynchronous serial SIO interface transmitter and receiver r
297. la for calculating the baud rate frequency Baud rate frequency CCLK DL 15 0 x 16 Maximum baud rate clock depends on the software the application the system load and etc But there is the capability of the transmit receive baud rate with DL 2 setting in an ideal condition ex UART test as long as in a small value of the baud rate deviation Note A divisor DL 15 0 of 1 is not allowed The setting must be either O to stop the clock or a value of 2 or more The frequency of CCLK should be set up less than or equal to the frequency of HCLK The following Table lists DL settings for CPU clock and baud rate combinations Baud CCLK 60MHz CCLK 33MHz CCLK 20MHz CCLK 8MHz Deviatio Deviatio Deviatio Deviatio Rate DL H n 96 DL H n 96 DL H n 96 DL H n 99 50 122 0 00000 61A8 0 00000 2710 0 00000 75 C350 0 00000 6B6C 0 00000 411B 0 00200 1A0B 0 00500 110 8528 0 00027 493E 0 00000 2C64 0 00320 11C1 0 01000 134 5 6 9 0 00015 3BE7 0 00279 244E 0 00344 OE85 0 01270 150 61A8 0 00000 35B6 0 00000 208D 0 00400 0005 0 01000 300 30D4 0 00000 1ADB 0 00000 1047 0 00800 0683 0 02000 600 186A 0 00000 OD6E 0 01454 0823 0 01600 0341 0 04002 1200 0C35 0 00000 0687 0 01454 0412 0 03199 01A1 0 07994 1800 0823 0 01600 047A 0 01454 0286
298. llowing Address for error Address following DMACSADO or DMACSAD1 Address that for final transfer that at which DMACDADO or DMACDAD1 transfer was interrupted Transfer count register Number of 0 2 Number of DMACSIZO or DMACSIZ1 transfers transfers remaining remaining Notes 1 The IREQ bit goes to 1 regardless of the interrupt mask IMK setting in the corresponding transfer mode register 2 The contents depend on which cycle triggered the error because the DMA controller decrements the transfer count register DMACSIZ only after a successful read from the transfer source 12 19 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 3 5 DMA Channel Priority The PRI bit in the DMA mode register DMAMOD specifies the strategy for assigning priority when there are simultaneous transfer requests for both channels 0 and 1 fixed priority or round robin e Fixed mode Channel priority never changes channel 0 gt channel 1 e Round robin mode Last channel used has lower priority Initial state gt CH1 Transfer over channel 0 Priority after channel 0 transfer CHO lt CH1 Transfer over channel 1 Priority after channel 1 transfer CHO gt CH1 Transfer over channel 0 Priority after channel 0 transfer CHO lt CH1 Transfer over channel 1 Priority after channel 1 transfer CHO gt CH1 Figure 12 3 Round Robin Operation The DMA controller
299. lt 2 HCLK XROMCS N XRAMCS N N XA 23 0 A1 XWE N XBWE N 1 XBWE 0 XBS N 1 N XBS_N 0 N XOEN N XD 15 0 Figure 11 1 External ROM RAM Word Read OE WE Pulse Width 1 Minimum Setting 4 4 HCLK XROMCS N XRAMCS N XA 23 0 WEN NG 0c XBWE NI N X 7 XBWENO N Z XBS N 1 N 5 N 0 N 2 XD 15 0 D A1 2 Figure 11 2 External ROM RAM Word Write OE WE Pulse Width 1 Minimum Setting 11 34 11 4 1 2 External Bank Access XIOCS N OJ XIOCS N 1 XA 23 0 XWE N XBWE_N 1 XBWE N 0 XBS_N 1 XBS 0 XOE N XWAIT XD 15 0 Figure 11 3 External Bank 16 Bit External Bus Half word Read OE WE Pulse Width ML674001 Series ML675001 Series User s Manual External Memory Controller Chapter 11 gt 1 Minimum Setting without XWAIT Memory Wait Cycles XIOCS N OJ XIOCS N 1 XA 23 0 XWE N XBWE_N 1 XBWE 0 XBS XBS 0 XOE N XWAIT XD 15 0 Figure 11 4 External Bank 16 Bit External Bus Half word Write OE WE Pulse Width EA s C gt 1 Minimum Setting without XWAIT Memory Wait Cycles 11 35 ML674001 Series ML675001 Series User s Manual Chapter 11 0 XA 23 0 XWE N XBWE_N 1 0 XBS_N 1 XBS 0 XOE N XWAIT XD 15 0 Figure 11 5 External Bank 16 Bit External Bus Half word Read OE WE Pulse Width 1 Minimum Sett
300. luding the data before and after the starting address and the ending address of the data read operation Example When the starting address of data read is 0x4000 080C the address for loading will be 0x4000 0800 6 After the data reading in 5 is completed set F 1 and BNK 10 Way 2 in the cache lock control register 7 Carry out a data read operation the addresses corresponding to the remaining instruction codes for the addresses in which the instruction codes are stored This causes the instruction codes to be locked to be loaded in Way 2 Since the reading is done in units of 16 bytes make sure that the total number of bytes is 2k bytes or less including the data before and after the starting address and the ending address of the data read operation Example When the starting address of data read is 0 4000 100 the address for loading will be 0 4000 1000 8 After the data reading in 7 is completed the target instruction codes are locked in Way 0 Way 1 and Way 2 by setting F 0 and 11 in the cache lock control register Caution All data reads carried out during the load mode will be targets for the Load operation Therefore when executing the above locking procedure take the following precautions in order to prevent loading of the data that are not to be locked Either set to 0 the cacheable bit of the bank storing the instruction codes for executing the above locking procedure or prepare
301. mer Compare Registers TIMECMPO to 5 1 15 11 15 2 8 Timer Status Registers TIMESTATO to 8 5 222 2 2 02 204 0 00 15 12 15 3 Description of Operation a nece eden de ee 15 13 15 3 1 System TIMET sa nte edes mee bae etatem eed ol eb ete ER 15 13 153 2 Auto Reload Timers y sissies et BH A tete e e de olei beta eee idee 15 14 15 3 3 Specifying Clock and Starting Auto Reload Timers eese 15 15 Chapter 16 PWM Generator TOL OVERVIEW iss ui 16 1 16 11 Components nno vede detected 16 1 16 1 27 Pm 16 2 16 1 3 Register DASt aeree did eiie eie ee eb 16 2 16 2 Register DESCHploDS u n ns Qh eben ele de quite e ifo eerte 16 3 16 2 1 PWM Registers PWRO and 224 4 1 2 1000000000000 00000000 trennen 16 3 16 2 2 PWM Period Registers PWCYO and 2 41 2 4 4000 16 4 16 2 3 PWM Counter and irre E Re LEER ER HERE 16 5 16 2 4 PWM Control Registers PWCONO and 1 sees ener enne 16 6 16 2 5 PWM Interrupt Status Register 5 4002222 4 0 1000000000000 enne 16 7
302. n Remapping After the cacheable setting is made for a remapped bank after remapping do not access the bank before remapping For example when the external SRAM of Bank 26 for which the non cacheable setting has been made is remapped to Bank 0 and Bank 0 is set cacheable do not access the Bank 26 before remapping thereafter This is because since the cache is used at the time of accessing Bank 0 the contents of the memory will always be the continually updated data but that latest data will not be updated in Bank 26 but only the old data will be remaining in it When setting cacheable so that the same memory is visible in several banks by remapping always be sure to set only one of them cacheable and the other bank non cacheable Also always be sure to access the bank for which the cacheable has been made Otherwise there will be mismatch in the contents of the memory as described above 9 8 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 5 Examples of Setting 9 5 1 9 5 2 Example of Cache Memory Initialization Before using this cache controller it is necessary to initialize the cache memory using the following procedure The values of memory read and write will not be correct when cacheable setting is made without initializing it 1 Write 0 0000 0000 in the cacheable register and set non cacheable for all banks 2 Write 0x0000 0000 in the cache lock control register and disable the lock conditio
303. n be 7 6 5 4 3 2 1 0 I2CCON START RESTR STCM 12 12 At reset 0 0 0 0 0 0 0 0 Address OxB7800000 Access R W Access size 8 bits Note This is a reserved bit for future expansion during writing Explanation of Bits I2CEN bit 0 In this LSI 0 is read during reading and this bit is ignored This bit designates the transmission of the restart sequence The I2CEN bit is not cleared automatically Writing 0 to this bit resets it to 0 I2CEN Description 0 No restart sequence transmission 1 Restart sequence transmisson e I2COC bit 1 This bit designates the transmission of the stop sequence after data is transmitted or received bit is not cleared automatically The I2COC I2COC Description 0 Stop sequence transmission 1 No stop sequence transmission e STCM bit 2 This bit designates the transmission reception of 1 byte data The transmission reception of 1 byte data includes the transmission of the slave address the transmission reception of data and the transmission reception of an acknowledge or negative acknowledge is transmitted or received This bit is automatically cleared to 0 after data STCM Description 0 No data transmission reception 1 Data transmission reception RESTR bit 3 This bit controls the transmission of an acknowledge signal
304. n of all ways 3 Write any value in the FLUSH register and initialize the cache memory Note No write back operation is made during the cache initialization The instruction of writing to the FLUSH register takes about 128 instruction cycles Example of Cache Memory Flushing Requiring Data Write Back When it is necessary to write back the data in the cache memory to the main memory before flushing the cache memory it is necessary to carry out the write back operation separately by software Sample procedure 1 Acquire a dummy data of 8kB in continuous addresses of a cacheable space Example Acquire 8kB of dummy data in Bank 26 so that the low order 13 bits of the address are 0x0000 1FFC 2 Make the cacheable setting for the bank storing the dummy data by setting the cacheable register 3 After putting Way 0 in the Load mode by setting the cache lock control register carry out the read of 2kB of dummy data Example By reading 2kB of dummy data which the low order 13 bits of the address being 0x0000 0x07FC write back to the main memory the data in Way 0 that needs to be written back 4 Similarly put Way 1 Way 2 and Way 3 in the Load mode by setting the cache lock control register and also read 2kB of dummy data All data will be written back by the data read operation of the dummy data 9 9 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 5 3 Example of Lock Setting Procedure An example
305. nIR2 Watchdog timer interval timer operation ILR1 nIR3 unused nIR4 GPIOA ILR4 nIR5 GPIOB ILCO nIRG GPIOC ILR6 nIR7 GPIOD GPIOE nIR8 Software interrupt requests ILR8 nIR9 UART ILR9 nIR10 SIO ILR10 nIR11 AD ILR11 ILC1 nIR12 PWM output 0 ILR12 nIR13 PWM output 1 ILR13 nIR14 SSIO ILR14 nIR15 2 ILR15 nIR16 Timer 0 ILC16 nIR17 Timer 1 nIR18 Timer 2 ILC18 nIR19 Timer 3 nIR20 Timer 4 ILC20 nIR21 Timer 5 nIR22 External interrupt 0 IDM22 ILC22 IDM nIR23 unused ILC IDMP22 nIR24 DMA channel 0 ILC24 nIR25 DMA channel 1 nIR26 External interrupt 1 IDM26 ILC26 nIR27 unused IDMP26 nIR28 External interrupt 2 IDM28 ILC28 IDM nIR29 unused IDMP28 nIR30 unused IDM30 ILC30 nIR31 External interrupt 3 IDMP30 8 26 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 5 Description of Operation 8 5 1 External Fast Interrupt EFIQ The external fast interrupt request EFIQ_N pin is a high priority interrupt request normally assigned to a single time critical source If FIQEN bit 0 in the FIQEN register does not mask the interrupt request the interrupt controller asserts the fast interrupt request nFIQ signal to the CPU in response to a detected interrupt trigger External Fast Interrupt EFIQ_N Sequence 0 Remove FIQ interrupt mask Setting F bit 6 in the CPU s current program status CPSR register to 0 and FIQEN bit 0 in the FIQEN register t
306. nable register GPIEC R W 16 0x0000 0xB7A01050 Port C interrupt polarity register GPIPC R W 16 0x0000 0xB7A01054 Port C interrupt status register GPISC R W 16 0x0000 0xB7A01060 Port D output register GPPOD R W 16 Indeterminate 0xB7A01064 Port D input register GPPID R 16 Reflects pin states 0xB7A01068 Port D mode register GPPMD R W 16 0x0000 0xB7A0106C Port D interrupt enable register GPIED R W 16 0x0000 0xB7A01070 Port D interrupt polarity register GPIPD R W 16 0x0000 0xB7A01074 Port D interrupt status register GPISD R W 16 0x0000 0xB7A01080 Port E output register GPPOE R W 16 Indeterminate 0xB7A01084 Port E input register GPPIE R 16 Reflects pin states 0xB7A01088 Port E mode register GPPME R W 16 0x0000 0xB7A0108C Port E interrupt enable register GPIEE R W 16 0x0000 0xB7A01090 Port E interrupt polarity register GPIPE R W 16 0x0000 0xB7A01094 Port E interrupt status register GPISE R W 16 0x0000 0xB7000000 Port function select register GPCTL R W 16 0x0000 13 4 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 132 Register Descriptions 13 2 1 Port Output Registers GPPOA GPPOB GPPOC GPPOD and GPPOE These registers specify the output levels for the corresponding port pins PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 A pin only has the specified output level however when both the GPCTL register configures it for its primary function and the cor
307. ndary scan cells Each of the boundary scan cells is placed between an I O pad and the core logic circuit Each of the boundary scan cells has the shift register function boundary scan register they are connected so as to form a scan chain surrounding the core logic circuit In a normal operation input output signals are input to and output from the core logic circuit via the boundary scan cells During a boundary scan test only test signals are input to and output from the core logic circuit via the boundary scan chain and JT AG interface pins 23 4 ML674001 Series ML675001 Series User s Manual Chapter 23 JTAG 23 3 1 Boundary Scan Control Circuit The boundary scan control circuit consists of a TAP controller an instruction register a bypass register and an IDCODE register Bypass register TDI TDO Boundary scan nTRST control circuit ML674001 Series ML675001 Series 1 The IDCODE register is equipped in the ML674001 series only Figure 23 3 Boundary Scan Control Circuit 23 5 ML674001 Series ML675001 Series User s Manual Chapter23 23 3 2 Registers The following three registers are built in the boundary control circuit Register Bit length Function Instruction register 3 Reads and decodes instructions for the TAP controller IDCODE register 32 Retains codes for identifying devices Bypass register 1 Provides the shortest route from TDI to TDO 23 6
308. ne 11 3 11 2 2 External I O bank 2 3 Bus Width Control Register IO23BWC 1 ML675001 Series only 11 5 11 2 3 External ROM Access Control Register ROMAOQ nennen enne enne 11 6 11 2 4 External SRAM Access Control Register 2 1 41 60000000000000000000000000 000000000004 11 8 11 2 5 External I O Bank 0 1 Access Control Register 11 10 11 2 6 External I O Bank 2 3 Access Control Register IO23ACX 1 IO23ACY 2 11 12 11 2 7 DRAM Bus Width Control Register DBWC ener nenne 11 14 11 2 8 DRAM Control Register 11 15 11 2 9 DRAM Characteristics Control Register 2 2 12 41 10800000000000000000000000000000000000003 1 11 17 11 2 10 SDRAM Mode Register SDMD 11 18 11 2 11 DRAM Command Register 11 20 11 2 12 DRAM Refresh Cycle Control Register 0 RFSHO eese eene enne 11 21 11 2 13 DRAM Refresh Cycle Control Register 1 RFSHLI eese ener nennen 11 22 11 2 14 DRAM Power Down Control Register RDWC enne nennen enne enne 11 24 11 3 Operational Description 4 etiain eel t lees heated 11 25 11 31 ere ra eU 11 25 11 3 2 ROM SRAM Conttol nero treo 11
309. nel are complete The DMA controller sets IREQO or IREQI in the DMA transfer complete interrupt status register DMAINT to 1 but does not change the ISTAO and ISTA1 bits If the bit in the DMA transfer mode register DMACTMODO or DMACTMODI is 0 the DMA controller generates an interrupt request Abnormal termination An error response during the cycle reading from the transfer source or the one writing to the transfer destination immediately terminates the DMA transfer The DMA controller sets IREQO or IREQI in the DMA transfer complete interrupt status register DMAINT to 1 sets ISTAO or ISTAI to 1 and indicates which cycle triggered the error in ISTPO or ISTP1 If the bit in the DMA transfer mode register DMACTMODO or DMACTMODI is 0 the controller generates an interrupt request Forced termination Setting the bit in the DMA transfer mode register DMACTMODO or DMACTMODI to 1 during a DMA transfer suspends operation after the write cycle There is no interrupt The program can restart operation by releasing the mask The program uses an interrupt handler or polling to determine termination and branches according to the DMA transfer complete status Normal termination 1 2 The program sets the bit in the DMA transfer mode register or DMACTMODI to 1 to mask channel operation The program writes to DMA interrupt clear register D
310. ng SOUT output The transmit operation continues internally The CPU can use this break control function to send a warning to the computer communications system terminal LCR 6 Description 0 Normal operation 1 Transmit break signal LCR 7 bit 7 Divisor latch access bit DLAB This bit switches access between UARTDLL and UARTDLM and UARTRBR UARTTHR and UARTIER LCR 7 Description 0 Normal operation accessing UARTRBR UARTTHR UARTIIR 1 Divisor latch UARTDLL and UARTDLM access 18 12 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 7 Modem Control Register UARTMCR This register controls the modem and data set interface The CPU has read write access to this register This register provides direct control over RTS and output Writing 1 to the corresponding bit drives the pin output at Low level its active state The register contents after a reset are 0 00 7 6 5 4 3 2 1 0 UARTMCR 7 0 After a reset 0 0 0 0 0 0 0 0 Address 0xB7B00010 Access R W Access size 8 bits Bit Descriptions MCR 0 bit 0 Data terminal ready DTR output control MCR O0 Description 0 Drive DTR pin output at High level 1 Drive DTR pin output at Low level bit 1 Request to send RTS output control MCR 1 Description 0 Drive RTS pin output at High
311. ng a program SFTCT 2 0 bits of this register are read only Writes to these bits are invalid When writing to SFTCT 2 0 bits write 0 7 6 5 4 3 2 1 0 SSIOST SFTCT 2 0 BUSY At reset 0 0 0 0 0 0 0 0 Address OxB7B01004 Access R W Access size 8 bits NOTE ox denotes a reserved bit Always write to the bit If 1 is written normal operation is not guaranteed Explanation of Bits e BUSY bit 0 This bit indicates that data is being transmitted or received This bit is automatically set to 1 when data transmission or reception begins and is cleared to 0 when the transmission or receiption is completed When this bit is 1 it means that data is being transferred By writing 0 to the BUSY bit during data transfer it is possible to abort the transmit or receive operation and initialize the synchronous SIO If 1 is written during transmit and receive idle the write operation is invalid BUSY Description 0 Transmit receive idle 1 Transmit receive in progress OERR bit 1 This bit indicates the presence or absence of an overrun error If the previously received data has not been read by the CPU the bit is set to 1 Once set to 1 the bit is not cleared to 0 even if there have been no overrun errors at the end of the next receive operation Therefore it is necessary to clear the bit to 0 with a program Writ
312. ng with proper system control the hardware also sets both interrupt disable bits to 1 The CPU loads the exception handler s entry point from the corresponding exception vector into PC to transfer control If the CPU is in the THUMB state this step simultaneously switches it to the ARM state Returning from Exception Handler Returning from an exception handler involves the following operations 1 CPU subtracts the specified offset 0 4 or 8 from the link register contents and loads the result into the program counter PC This offset depends on the exception type 2 CPU copies the save program status register SPSR x contents back into the current program status register CPSR Note This copy restores the interrupt disable bits to the states that they had prior to the exception It also restores the T bit so it is not necessary for the software to switch back to the THUMB state ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 12 3 2 12 4 2 12 5 Summary of Exception Switching Table 2 2 summarizes the instructions for returning from exception handlers and the return addresses saved in the corresponding R14 register Table 2 2 Returning from Exception Handlers Return Address Return Instruction 1 1 1 2 2 1 3 IRQ SUBS 14 4 4 4 5085 R14 abt 4 4 4 DABT SUBS PC R14 abt 8 8
313. ns e GPCTLO bit 0 This bit controls the function of pins PIOA 7 0 Their secondary function is as a UART interface GPCTLO 0 primary function GPCTLO 1 secondary function Function In Out Function In Out PIOA 0 In Out SIN Input PIOA 1 In Out SOUT Output PIOA 2 In Out CTS Input PIOA 3 In Out DSR Input PIOA 4 In Out DCD Input PIOA 5 In Out DTR Output PIOA 6 In Out RTS Output PIOA 7 In Out RI Input GPCTLI bit 1 This bit controls the function of pins PIOB 7 6 Their secondary function is as serial interface GPCTL1 0 primary function GPCTL1 1 secondary function Function In Out Function In Out PIOB 6 In Out STXD Output PIOB T In Out SRXD Input 13 10 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO GPCTL2 bit 2 This bit controls the function of pins PIOC 6 2 Their secondary function is as an external bus GPCTL2 0 primary function GPCTL2 1 secondary function Function In Out Function In Out PIOC 2 In Out XA 19 Output PIOC 3 In Out XA 20 Output PIOC 4 In Out XA 21 Output PIOC 5 In Out XA 22 Output PIOC 6 In Out XA 23 Output GPCTL3 bit 3 This bit controls the function of pins PIOB 4 and PIOB 1 0 Their secondary function is as DMA channel 0 GPCTL3 0 prim
314. ns use interrupts which are all disabled 18 28 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 3 6 Error Status Overrun error The LSR 1 bit in the UARTLSR register goes to 1 to indicate that the hardware has overwritten the contents of the UARTRBR register with a new character before the CPU read the former character 1 Parity error The LSR 2 bit in the UARTLSR register goes to 1 to indicate that the parity calculated from the received data does not match that received with the data This only applies however when parity is enabled LCR 3 1 For buffered operation LSR 2 indicates an error in the data at the head of the queue Parity errors for other characters in the queue do not affect its contents 2 Framing error The LSR 3 bit in the UARTLSR register goes to 1 to indicate that the bit following the last data bit or parity bit is 0 spacing level not 1 stop bit For buffered operation LSR 3 goes to 1 when the character with the framing error reaches the head of the queue 3 Break interrupt The LSR 4 bit in the UARTLSR register goes to 1 to indicate that the input is 0 spacing level for one frame interval start bit data bits parity bit and stop bit For buffered operation LSR 4 goes to 1 when the character with the break interrupt reaches the head of the queue 18 29 ML674001 Series ML675001 Series User
315. ns will be made For details please refer to Section 9 3 When 1 is set all store operations to the cache memory will be made forcibly to the way selected by BNK Also in this case all instruction fetch accesses will be non cacheable accesses the other hand all data accesses will be made in the normal manner according to the setting of the cacheable register setting cacheable or non cacheable F Description 0 Sets to normal cache operation default setting 1 Sets cache to the Load mode operation BNK Selects the way of the cache memory in which loading is to be made This setting is valid if the bit has been set to 1 BNK Description 00 Way 0 selected 01 Way 1 selected 10 Way 2 selected 11 Way 3 selected 9 3 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 2 2 Cacheable Register CACHE The CACHE register is used for making the cacheable non cacheble setting for each memory bank 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ _ _ _ C 0 Value at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C31 C30 C29 C28 C27 C26 C25 C24 C15 C14 C13 C12 C11 C10 C9 C8 Value at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address CACH Base 0x08 Access R W Access size 32 bits Note indicates a reserved bit Alwa
316. nsmit output of the Synchronous SIO back to the receive input of 1t 19 1 1 Configuration The configuration of the synchronous SIO is shown in Figure 19 1 Internal bus SSIOBUF SSIOCON SSIOST SSIOREG 1 SDO Shift register SSIOINT 050 SSIOINTEN SSIOTSCON Interrupt signal nIR14 lt 3 bit counter 1 8HCLK 1 16HCLK 15 10 1 32HCLK Control circuit Figure 19 1 Synchronous SIO Block Diagram SSIOCON Synchronous SIO control register SSIOST Synchronous SIO status register SSIOINT Synchronous SIO interrupt request register SSIOINTEN Synchronous SIO interrupt enable register SSIOBUF Synchronous SIO transmit receive buffer register SSIOREG Synchronous SIO transmit receive shift register SSIOTSCON Synchronous SIO test control register 19 1 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 1 2 List of Pins Function Receive data input O ransmit data output ransmit receive data synchronous clock input and output 19 1 3 List of Registers OxB7BO 1000 Synchronous SIO transmit receive SSIOBUF R W 0x00 buffer register OxB7BO 1004 Synchronous SIO status register SSIOST OxB7BO 1008 Synchronous SIO interrupt request SSIOINT R 5 jo register o SDI SCLK OxB7BO 100C Synchronous SIO interrupt enable SSIOINTEN P register Synchronous SIO transmit receive SSIOCON R 0xB7B0_1014 S
317. ntents depend on the bit in the FIQRAW register and FIQEN bit 0 in the FIQEN register FIQRAW 0 FIQEN 0 FIQ 0 x 0 0 0 0 1 1 1 8 9 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 844 FIQRAW Register FIQRAW A 1 in bit indicates a raw fast interrupt request FIQ from the external fast interrupt request EFIQ pin Here raw means not masked by FIQEN bit 0 in the FIQEN register The CPU has only read access to this register 31 30 29 28 27 26 25 24 23 22 20 19 18 17 16 FIQRAW ae oe ae E 9 Ue _ aoe Rowe c m 25 aw After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ _ _ _ _ _ _ 25 _ _ _ _ FIQRAW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O Note2 Address 0x7800000C Access R Access size 32 bits Notes 1 Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures 2 The initial value reflects the EFIQ_N interrupt input Bit Descriptions e FIQRAW bit 0 This bit reflects the EFIQ_N interrupt input FIQRAW Description 0 No FIQ request pending 1 FIQ request pending 8 10 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt
318. ntren trennen eterne enne 2 12 25 12 45 LO uiae RIBUS UR B n ERE 2 12 2125 hayu hani ha qhasa akhu a h phawa 2 12 2 12 6 nete eb e ete de do f e e ot bee P Sas ua 2 13 2 1257 Software Interr pts ho dete ee id do ipte eerte vu aes dece eem h Q u eto 2 13 2126 Undefined Instr ctiotis 5 o ioter fte de d ie foede e tide edet 2 13 2 12 9 Exception V ctoIS sinh d eee n te dot iei lid os deseo dii e 2 14 2 12 10 Exception Priority Order ede nd ee do hie t dedo ede Pe ob 2 14 2513 m 2 15 ML674001 Series ML675001 Series User s Manual Table of Contents Chapter 3 Address Mapping 3 1 3 1 1 Su au Naa E 3 1 34E 2 Register Dist ite ete tete rot dec 3 1 3 2 Address Map oe ocho ette te e Ha e ER y beer reta ees 3 2 321 674001 series address map ote petere rre at e ESNE ERES len 3 2 32 2 ML675001 series address un eredi epe HE aae 3 3 3 3 Register Descriptions scitote eee RU awaspa e SER 3 4 3 3 1 Remap Control Register 022000024 0 2000000000000000 000550515 ene 3 4 3 32 Select Register ROMSBL a ta e EURO EHE Qn 3 5 34
319. nversion characteristics Note that it does not include quantization error The theoretical conversion characteristic divides the voltage range between VREF and AGND into 1024 equal steps Differential linearity error Difference between the theoretical and actual input voltage change producing 1 bit change in the digital output anywhere within the conversion range This is an indicator of conversion characteristic smoothness The theoretical value is VREF Aground 1024 Zero scale error Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from 0x000 to 0x001 Full scale error Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from Ox3FE to Ox3FF 24 48 Appendixes ML674001 Series ML675001 Series User s Manual Appendixes Appendixes Appendix A Register List Address Name Abbreviation R W Size Initial Value Ref Pages 0x78000000 IRQ register IRQ R 32 0x00000000 8 7 0x78000004 Software interrupt register IRQS R W 32 0 00000000 8 8 0x78000008 register FIQ R 32 0x00000000 8 9 0x7800000C FIQRAW register FIQRAW R 32 2 8 10 0x78000010 enable register FIQEN R W 32 0 00000000 8 11 0x78000
320. o 1 disables masking Wait for interrupt External fast interrupt request input from the EFIQ_N pin sets bit 0 in the FIQRAW register to 1 Relay exception request to CPU The interrupt controller sets bit 0 in the FIQ register to 1 and asserts the fast interrupt request nFIQ signal to the CPU HCLK 4 External fast interrupt request EFIQ nEFIQ 0 FIQEN 0 FIQ 0 9 nFIQ 3 Accept request If F bit 6 in the CPU s current program status CPSR register enables FIQ exceptions the CPU saves the address of the next instruction in 14 fiq saves the CPSR contents in SPSR fiq and sets the CPSR F bit6 and I bit7 to 1 to block acceptance of both FIQ and IRQ exceptions by the CPU 4 Process interrupt The FIQ exception handler must negate the FIQ request from the source before returning 5 Return from interrupt The FIQ exception handler terminates by executing a return from interrupt instruction which restores the instruction address and CPSR contents from 14 fiq and SPSR_fiq Note For further details on CPU processing of exceptions refer to the ARM7TDMI data sheet 8 27 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller 8 52 External and Internal Interrupts IRQn These are regular interrupt requests with lower priority than the
321. o the following formula Tpwmeye 65536 PWCY Xx frequency divisor from PWCKx CCLK sec where the PWCKx bits in the corresponding PWM control PWCONX register specify the frequency divider for CCLK For example when CCLK is 16 67 MHz and PWCKx is set to 01 divisor is 1 4 and PWCYx is set to Oxffff the period for the corresponding PWM output can be calculated as below Toy 65536 65535 1 4 x 16 67 x 109 sec 239 952 nsec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWCYO to PWCY 15 0 1 1 1 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7D00004 CHO 0xB7D00024 Access R W Access size 16 bits Note Note that the setting must be greater than that in the corresponding PWM register PWRx which specifies the duty 16 4 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Generator 16 2 3 PWCO to 1 After a reset PWM Counter PWCO and PWC1 These up counters automatically reload from the corresponding PWM period register PWCYx when they overflow The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWC 15 0 L L L L L L L L L L L L L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 7000008 0xB7D00028 1 Access R W Access size 16 bits Note Writing to PWCx simultaneously writes the same value to PWCYx 16 5 ML674001 Series ML675001 Series User s Manual Chapter 16 PWM Gene
322. ock cycles OE WE pulse Read off Notes 2 1 0 ER width timing 0 0 0 1 0 0 0 1 2 0 0 1 0 3 2 0 1 1 4 2 1 0 0 reserved Operation is nor guaranteed for a setting labeled reserved 1 0 1 reserved Operation is not guaranteed for a setting labeled reserved 1 1 0 reserved Operation is nop guaranteed for a setting labeled reserved 1 1 1 8 4 1 Read off time is the interval measured from the time when Output Enable OE becomes inactive in one memory cycle to the time it becomes active in the next memory cycle ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller This table is applied only to ML675001 series ROMTYPE 2 0 Pulse width in clock cycles 2 1 0 Address OE WE pulse Read off Burst time Notes setup time width time 0 0 0 1 1 1 1 0 0 1 2 2 2 0 1 0 reserved Operation is not guaranteed for a setting labeled reserved 0 1 5 3 3 1 0 0 2 8 4 5 1 0 2 10 5 6 Operation is not guaranteed for 0 reserved a das labeled 1 1 1 2 16 7 9 e ROMBRST bit 4 Page Mode is set up ROMBRST Description 0 Page Mode off 1 Page Mode on 1 This ROMBRST register exists only in ML675001 series In ML674001 series it becomes the treatment of reserved ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 4 External SRAM
323. ocking in Way 0 Way 1 and Way 2 of locking in the cache the instruction codes contiguous 4097 bytes or more but less than or equal to 6144 bytes 1 Make cacheable setting for the bit in the cacheable register corresponding to the bank in which the instruction codes to be locked are stored 2 Set F 1 and 00 Way 0 in the cache lock control register 3 Carry out a data read operation for the addresses corresponding to the first 2k bytes among the addresses storing the instruction codes This causes the instruction codes to be locked to be loaded in Way 0 Since the reading is done in units of 16 bytes make sure that the total number of bytes is 2k bytes or less including the data before and after the starting address and the ending address of the data read operation Example When the starting address of data read is 0 4000 000 the address for loading will be 0x4000 0000 4 After the data reading in 3 is completed set F 1 and 01 Way 1 in the cache lock control register 5 Carry out a data read operation for the addresses corresponding to the next 2K bytes among the addresses in which the instructions codes are stored This causes the instruction codes to be locked to be loaded in Way 1 9 10 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY Since the reading is done in units of 16 bytes make sure that the total number of bytes is 2k bytes or less inc
324. ode The flash memory is automatically set in read mode when the power is turned on 2244 Erase An erase operation is executed by entering an SDP command of six cycles the sector erase command block erase command or chip erase command to the command register and is ended automatically by the control of the internal timer within the flash memory During an erase operation DATA_N poling that performs the detection of internal operations the toggle bit hardware reset and software reset become valid The Sector Erase command places the selected 2KB memory array in the state of 1 The Block Erase command places the selected 64KB memory array in the state of 1 The Chip Erase command places the entire memory array area in the state of 1 224 5 Program A program operation is performed by entering an SDP command of four cycles the Program command to the command register and is ended automatically by the control of internal timing During a program operation DATA_N poling that performs the detection of internal operations the toggle bit hardware reset and software reset become valid Please note however that the memory arrays of addresses to be programmed must be placed in the erase state prior to programming Programming is performed in units of 16 bits 2 bytes Caution It is prohibited to re program an address that has already been programmed once without erasing the existing program first 22 4 6
325. ode 10 5 to 14MHz 20 to 56MHz 1 time mode 01 20 to 56MHz 20 to 56MHz weg lease use an external clock Reserved 00 ML674001 Series does not have PLL Internal clock frequency is same as OSC input clock frequency n ML675001 series PLL operation mode must not be changed during operation 5 2 Sample Crystal Connections ML674001 ML67Q4002 ML67Q4003 ML675001 ML67Q5002 ML67Q5003 C1 T OSCO Rf C2 OSC1_N e e Rd ML674001 Series Base clock to CLKGEN Block ML675001 Series 7 Base clock PLL Block Figure 5 2 Sample Crystal Connections 5 2 Chapter 6 Reset Control ML674001 Series ML675001 Series User s Manual Chapter 6 Reset Control Chapter 6 Reset Control 61 Overview The RSTSTATUS bit in the watchdog status WDSTAT register indicates to the software the reason for the reset external reset RESET pin input or watchdog timer overflow The minimum RESET N pulse width for triggering a system reset initialization is 20 clock cycles 6 1 1 Pin List Pin Name 1 0 Description RESET_N External reset input 6 2 Reset Types 6 2 1 6 2 2 External Reset Input Driving the RESET N pin at Low level for a pulse width at least 20 clock cycles triggers a reset When first applying the power or waking the LSI from STANDBY mode however increase the pulse width to at least 10 ms to all
326. of source and destination devices Built in peripheral registers for example SIO UART with FIFO and I2C can not be set as source or destination of a DMA transfer Table 8 2 lists the choices available for the transfer size TSIZ field in the DMA transfer mode register DMAMODO or DMAMOD1 for the channel Halfword 16 bit transfer Internal device internal SRAM Incremental address device External device Transfer destination Incremental address Fixed address device device Transfer source Bus width 32bit 8bit 16bit 8bit 16bit Internal device internal SRAM Incremental address device 32 bit W H B W H B W H B External device Incremental 8 bit W H B W H B W H B address device Fixed address device 16 bit W H B W H B W H B 8 bit 16 bit Word 32 bit transfer Halfword 16 bit transfer Byte 8 bit transfer Invalid combination Restriction of DMA to External ROM area DMA controller can not access external ROM area BANK25 This restriction applies to external ROM area when it is remapped to BANKO as well Thus the DMA registers DMACSADO0 1 and DMACDADO l should never be set to addresses for BANK25 0xC800 0000 0xCFFF FFFF or BANKO 0x0000 0000 0x07FF FFFF These restrictions were implemented in order to optimize efficiency during processor access to external ROM area Restrictions of
327. on BH h Output Input Start Stop Restart Acknowledge Negative Acknowledge Negative sequence sequence sequence received acknowledge transmitted acknowledge received transmitted I2CSAD I2CDR S BIBIB BIBIBIB BRA 7161514 31211 716 15 14 13121110 I2CIR 1 I2CAAK 0 Flag 4 IZCDAK 0 Transmission complete I2CSAD xxxxxxx0b Register I2CDR settings I2CCON xxx0x100b 20 12 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 3 2 Receive operation transfer of 1 byte from slave to master in 7 bit address mode specify the communication destination the address of the communication destination slave is written to SAD 6 0 of the I2CSAD register and to set the transfer direction as reception the I2CRW bit is set to 1 received by the master device The I2CCON register is set to XXX0X100 The following series of operations is automatically performed when the STCM bit bit 2 of the I2CCON register is set to 1 Transmission of the start sequence to attain bus access transmission of the slave address and the transfer direction specified to the I2CSAD register confirmation of an acknowledge from the slave device for the address transmitted
328. on aote ipte per rp 20 17 20 3 8 7 bit Address Mode and 10 bit Address Mode sss nre 20 19 Chapter 21 Analog to Digital Converter OVERVIEW ctm toe tee tete e eene I eoe lena etel 21 1 2T 1 1 Components Roe aee mte b eaten taies 21 1 21 1 2 a tr e e m OE 21 2 212153 Control Register List o e EF e aad rt 21 2 212 Control Register Descriptions iot e f epe he seh dis m e E te desided 21 3 21 2 1 Analog to Digital Converter Control Register 0 ADCONO essere 21 3 21 2 2 Analog to Digital Converter Control Register 1 ADCONI eese enne 21 5 21 2 3 Analog to Digital Converter Control Register 2 2 21 6 21 2 4 Analog to Digital Converter Interrupt Control Register 21 7 21 2 5 Analog to Digital Converter Forced Interrupt Register 21 9 21 2 6 Analog to Digital Converter Result Registers to ADR3 eene 21 10 21 3 Operational Description eee tette re ocio bees ese en tative 21 11 21 3 T Scam Mode RR A RU Et ente c RU 21 11 21 32 Select Mode c ie ee in 21 11 Chapter 22 Built In Flash Memory 2221 Overview eee be Rte E o eR n ete EE PD Pe ERE tet 22
329. on They return 0 for reads Writes to them ignored Bit Descriptions DRCMD 2 0 bits 0 to 2 These bits specify the DRAM command to execute DRCMD 2 0 i 0 SDRAM Operation EDO DRAM Operation 0 0 0 No Operation No Operation 0 0 1 reserved reserved 0 1 0 reserved reserved 0 1 1 reserved reserved 1 0 0 PALL pre charge all SDRAM banks EDO DRAM pre charge 1 0 1 REF SDRAM CBR refresh EDO DRAM CBR refresh 1 1 0 SELF start SDRAM self refresh Start EDO DRAM self refresh 1 1 1 SREX end SDRAM self refresh End EDO DRAM self refresh Notes 1 Operation is not guaranteed for a setting labeled reserved 2 During self refresh operation operation is not guaranteed for commands other than the end self refresh command 3 The SDRAM clock output SDCLK Stops Low level for EDO DRAM operation ARCH bit in DRMC register 7 1 Stops Low level after SELF command Resumes after SREX command 4 The hardware blocks access to this register until the specified command finishes execution 5 According to JEDEC standards a DRAM chip requires 8 cycles of CBR to get properly initialized Thus when initializing a JEDEC standard DRAM the application software must write 0 05 eight times to this register to initialize CBR for DRAM 11 20 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller
330. on data to be written to flash memory are controlled by using the built in debug function via the JTAG interface 22 3 ML674001 Series ML675001 Series User s Manual Chapter 22 Built In Flash Memory 1 2 3 Pin Settings The following table lists the pin settings necessary to use the JTAG debug function see Chapter 23 Pin name Setting JSEL L BSEL 1 see BSEL 0 L or H Connection Method Connect the JTAG pin with the host such as a PC or JTAG compatible Flash Programmer via a JTAG debug interface tool For more information about the connections of the JTAG connectors on the user board see Chapter 23 Description of the Flash Memory Programming Procedure Step 1 Initial Status Provide the flash memory program routine and application codes to be written to flash memory on the host Step 2 Downloading the flash memory program routine Download the flash memory program routine to built in RAM using the built in debug function via the JTAG interface Note In the case of on board programming if external SRAM has been mounted on the board the routine can be downloaded to external SRAM instead of to built in RAM Step 3 Erasing Flash Memory Start up the flash memory program routine which has been downloaded to built in RAM using the built in debug function via the JTAG interface flash memory program routine erases the contents of flash memory Step 4 Writing Appl
331. ons adversely The data which has been input into the boundary scan cells can be output from the TDO pin by repeating a shift operation IDCODE The IDCODE instruction is used to select an ID register in which device information including serial numbers and parts numbers is stored Using this instruction whether or not correct parts are mounted on the board can be verified by testing The IDCODE of ML674001 series is 0000 0000 0010 0000 0000 0000 0101 1101 From MSB version 000 parts No 0000 0010 0000 0000 Manufacturer ID 0000 0101 110 1 fixed value The IDCODE of ML675001 series is undefined BYPASS The BYPASS instruction is used to shorten the serial boundary scan chain if it is not necessary to test this LSI when testing the connection status at board level Only the 1 bit BYPASS register is connected between the TDI pins By setting BYPASS mode the test data which has been input to the TDI pin is output to the TDO pin without routing through the boundary scan chain 23 8 Chapter 24 Electrical Characteristics ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics Chapter 24 Electrical Characteristics 24 1 Absolute Maximum Ratings Item Symbol Conditions Rating Unit Digital power supply _ 0 3 to 3 6 voltage core Digital power supply 0 3 to 4 6 voltage I O PLL
332. or testing the following e Equality and inequality e Inequality lt lt gt or gt after signed or unsigned arithmetic e Individual condition code flags THUMB Instruction Set Each 16 bit THUMB instruction has a corresponding 32 bit ARM instruction with the same effect on the processor model The twin design goals here are to boost performance in user applications using a 16 bits wide or smaller memory data bus and to increase code density THUMB instructions retain the same 32 bit architecture as ARM instructions in particular 32 bit arithmetic and 32 bit addresses for data access instructions and instruction fetch They are however subject to a few access limitations THUMB instructions share the first eight general purpose registers RO to R7 with ARM instructions The upper eight R8 to R15 are generally off limits but certain THUMB instructions have access to the program counter ARM register 15 link register ARM register 14 and stack pointer ARM register 13 ARM register 15 holds the program counter in bits 31 to 1 Bit 0 returns 0 for reads Writes to bit 0 are ignored There are no THUMB analogs for the ARM instructions MSR and MRS for direct transfers to and from current program status register CPSR and saved program status registers SPSR 2 9 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 11 Addressing Modes This CPU provides a rich selection of addressing modes fo
333. ore new settings 1 Use new settings 11 18 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller This setting cycle has the following format A11 A10 8 AT A6 A5 A4 A3 A2 A1 0 OPECODE LTMODE WT BL Axxare the SDRAM input address signals Field Function Setting Meaning OPCODE Mode option 00000 Burst Read amp Burst Write 010 2 clock cycles or LTMODE CAS latency 011 3 clock cycles WT Wrap type 0 Sequential Wrap Around BL Burst length 011 Burst length 8 Note LTMODE is the only field that varies and then only by a single bit 11 19 ML674001 Chapter 11 Series ML675001 Series User s Manual External Memory Controller 11 2 11 DCMD After a reset DRAM Command Register DCMD Writing to this register executes the specified command SDRAM or produces the corresponding access EDO DRAM The program has read write access to this register 31 30 22 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ 22 _ _ E _ 4 _ E _ _ _ DRCMD 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78180010 Access R W Access size 32 bits Note These bits are reserved for future expansi
334. oring function it will be possible to set the buffer area for DMA transfer within a bank for which the non cacheable setting is made The external memory controller of this LSI mirrors Bank 26 external SRAM area to Bank 29 Bank 25 external ROM area to Bank 28 and Bank 24 external DRAM area to Bank 27 For example it is possible to access a physically single external SRAM using different addresses of Bank 26 and Bank 29 setting one of these banks say Bank 26 cacheable and the other bank that is Bank 29 non cacheable it is possible to provide a cacheable area the address area of Bank 26 and a non cacheable area Bank 29 in a single external SRAM In this example the program and data of the CPU that need to be accessed at high speed using the cache function are placed in the addresses of Bank 26 and the buffer for DMA transfer is placed in the addresses in Bank 29 By doing this since the program and data of the CPU are in Bank 26 they will be cacheable while on the other hand since the buffer accessed by DMA and ARM is in Bank 29 it will be non cacheable DMA controller Bank 29 Non cacheable Memory not installed Access prohibited mee Access prohibited Master transfer External SRAM Buffer read write Bank 26 Cacheable Buffer area Non cacheable gt ARM program data area Cacheable Program data access Memory map 9 4 2 Precautions i
335. ors detected by writing 1 to the corresponding bits OERR and FERR the SIOSTA register sets the RVIRQ bit in the SIOSTA register to 1 and generates a receive ready interrupt request to indicate that the receive shift register is empty ready to receive the next frame 17 11 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 3 8 Generating Baud Rate Clock Figure 17 3 gives a block diagram showing the following registers for the baud rate generator block e Baudrate timer counter SIOBTC with 8 bit counter e Baudrate timer SIOBT register e Baud rate control SIOBCN register Baud rate generator generates the baud rate for serial communication by dividing baud rate clock specified by SIOBT Writing to SIOBT simultaneously writes the same value to SIOBTC The baud rate control register SIOBCN controls start stop of a baud rate Overflow Baud rate clock SIOBTC Baud rate 16 SIOBCN Figure 17 3 Baud Rate Generator Block Diagram The following is the procedure for specifying the baud rate 1 Calculate the starting value D from the desired baud rate frequency B and the baud rate clock frequency f using the following formula Note however that D must be between 0 and 255 fp 1 1 16xB 8 4 16 D 256 f Input counter clock frequency CCLK Hz D Reload value 0 to 255 2 Write the starting value D to S
336. ort pin PIOA 7 0 PIOB 7 O PIOC 7 0 PIOD 7 O PIOE 9 0 input levels Address 0xB7A01004 GPPIA 0xB7A01024 GPPIB 0 7 01044 GPPIC 0xB7A01064 GPPID 0xB7A01084 GPPIE Access R Access size 16 bits ML674001 Series ML675001 Series User s Manual Chapter 13 13 2 3 Port Mode Registers GPPMA GPPMB GPPMC GPPMD GPPME These registers specify the I O directions for the corresponding port pins PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 at the individual pin level The CPU has read write access to these registers The register contents after a reset are 0 0000 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 GEENA SEP ME GPPMA 7 0J GPPMB 7 0 GPPMC 7 0 GPPMD 7 0 GPPME 9 0 GPPMC GPPMD 5 gie GPPME uses amp bit8 For other GPPMXx bit9 amp bit8 are GPPME Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7A01008 GPPMA 0xB7A01028 GPPMB 0xB7A01048 GPPMC 0xB7A01068 GPPMD 0xB7A01088 GPPME Access R W Access size 16 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions e GPPMA 7 0 GPPMB 7 0 GPPMC 7 0 GPPMD 7 0 bits 0 to 7 GPPME 9 0 bits 0 to 9 These bits specify the I O directions for the corresponding port pins GPPMA 7 0 7 01 GPPMC 7 0
337. ow the crystal oscillator sufficient time to stabilize This type of reset leaves 0x0000 in the WDSTAT register Watchdog Timer Overflow Setting the ITM and OFINTMODE bits in the watchdog time base counter control WDTBCON register to 0 and 1 respectively causes watchdog timer overflow to trigger a system reset This type of reset leaves 0x0001 in the WDSTAT register This type also leaves the following LSI settings unchanged I O port direction input output I O port function primary secondary I O port output levels and the oscillation stabilization interval specified in the clock wait CKWT register 6 1 ML674001 Series ML675001 Series User s Manual Chapter 6 Reset Control 6 3 Operational Description RESET N When power is first applied e Z 2 g LSI from STANDBY ode with reset signal input Figure 61 Reset Signal Timing Chapter 7 Power Management ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management Chapter 7 Power Management T 1 7 2 Overview This LSI was designed with advanced power saving features to enable flexibility in optimizing power consumption As such a great level of configurability has been built into the power management block This is achieved by varying the frequency of clock signal to different blocks or by stopping the clock signal entirely to certain designated blocks To save power a user application syst
338. pes and whether there is an interrupt when the specified number of transfers are complete The program has read write access to this register The contents after a reset are 0x00000040 31 30 22 28 27 26 25 24 23 22 21 20 19 18 17 16 DMACTMOD0tol After a reset 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IMK BRQ DDP SDP TSIZ jara 0 0 0 0 0 0 0 0 0 1 Address 0x7BE00104 CHO 0x7BE00204 1 Access R W Access size 32 bits Notes 0 0 0 0 0 0 These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Certain restrictions apply For further details see Section 8 3 6 Important Usage Notes Bit Descriptions e bit 0 This bit specifies the transfer request source ARQ Description 0 External input DREQ 1 Software request mode e TSIZ bits 2 and 1 This field specifies the transfer size TSIZ Description Byte 8 bits Halfword 16 bits Word 32 bits o o m 4 4 Setting not allowed 12 10 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC SDP bit 3 This bit specifies the device type for the transfer source
339. plete The program must explicitly reset this bit to 0 by writing 17 to it INTST bit 1 A 1 in this bit indicates completion of select mode conversion INTST Description 0 Select mode conversion not complete 1 Select mode conversion complete The program must explicitly reset this bit to 0 by writing 17 to it ADSNIE bit 2 Setting this bit to 1 produces an interrupt request when one cycle through the specified channels is complete that is when channel 3 conversion in scan mode is complete ADSNIE Description 0 Disable interrupt after scan 1 Enable interrupt after scan 21 7 ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter ADSTIE bit 3 Setting this bit to 1 produces an interrupt request when select mode conversion is complete ADSTIE Description 0 Disable interrupt after conversion 1 Enable interrupt after conversion 21 8 21 2 5 ADFINT After a reset ML674001 Seies ML675001 Series User s Manual Chapter 21 Analog to Digital Converter Analog to Digital Converter Forced Interrupt Register ADFINT This register is for forcing an analog to digital converter interrupt The program has read write access to this register The contents after a reset are 0 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADFAS
340. ponents Figure 8 1 shows the interrupt controller components Interrupt controller INTRC FIQRW i FIQEN Two stage nEFIQ nIR 15 4 nIR 2 0 FIQ acceptance circuitry FIQ and IRQ exception generators FIQ IRQ priority control i Ras EXTINR 6 0 _ 100 2111 101 M e o CILCL o 3 S Q o M 4 nIR 16 21 nIR 24 25 EXINTO I i IRN EXINT1 gt EXINT2 w EXINT3 nIR 22 26 28 31 System bus STANDBY mode bypasses this flip flop IRL is an internal register Figure 8 1 Interrupt Controller Components 8 2 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller 8 1 2 Pin List Pin Name Description EXINTO Interrupt input O EXINT1 Interrupt input 1 EXINT2 Interrupt input 2 EXINT3 Interrupt input 3 EFIQ N FIQ input negative logic 8 1 3 Register List Address Name Abbreviation R W Size Initial Value 0x78000000 IRQ register IRQ R 32 0x00000000 0x78000004 Software interrupt register IRQS R W 32 0 00000000 0x78000008 FIQ register FIQ R 32 0x00000000 0x7800000C FIQRAW register FIQRAW ll ae interrupt input 0x78000010 FIQ enable register FIQEN R W 32 0x00000000 0x78000014 IRQ number register IRN R 32 0x00
341. ponents for the system timer Figure 15 2 one for an auto reload timer CCLK TMOVFR Interrupt request TTTTTTTTTTTTTT OVF CCLK 16 Figure 15 1 System Timer Components 15 1 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers Interrupt request TMINTN CCLK 2 CCLK A Reload Interrupt CCLK 8 Enable CCLK 16 Timer counter CCLK 32 C Status omparator register Compare register register Figure 15 2 Auto Reload Timer Components 15 2 15 1 2 Register List ML674001 Series ML675001 Series User s Manual Chapter 15 Timers Address Name Abbreviation R W Size Initial Value 0xB8001004 System timer enable register TMEN R W 32 0x00000000 0xB8001008 System timer reload register TMRLR R W 32 0x00000000 0xB8001010 System counter overflow register TMOVFR R W 32 0x00000000 0 7 00000 Timer 0 control register TIMECNTLO R W 16 0x0000 0xB7F00004 Timer 0 base register TIMEBASEO R W 16 0x0000 0xB7F00008 Timer 0 counter register TIMECNTO R 16 0x0000 OxB7F0000C Timer 0 compare register TIMECMPO R W 16 OxFFFF 0xB7F00010 Timer 0 status register TIMESTATO R W 16 0x0000 0xB7F00020 Timer 1 control register TIMECNTL1 R W 16 0x0000 0xB7F00024 Timer 1 base register TIMEBASE1 R W 16 0x0000 0 7 00028 Timer 1 counter register TIMECNT1 R 16 0x0000 0xB7F0002C Timer 1 comp
342. power supply voltage PLL 0 3 to 3 6 Input voltage 0 3 to Vpp 0 3 Output voltage Vo GND AGND 0 V 0 3 to Vpp 10 0 3 Analog power supply 0 V 0 3 10 Vpp 10 0 3 voltage 25 Analog reference voltage VREF 0 3 to Vpp 0 3 and 0 3 to AVpp 0 3 Analog input voltage VAI 0 3 to VREF Input current li 10 to 10 Output current lo 20 to 20 mA Output current 30 to 30 Power losses Pp 85 C 680 LFBGA mW per package 1000 LQFP Storage temperature Tstc 50 to 150 Note 1 ML675001 Series only 2 All output pins except XA 15 0 3 XA 15 0 24 1 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics 24 2 Operating Conditions GND 0 V Item Symbol Conditions Minimum Typical Maximum Unit Digital power supply voltage VDD CORE 225 25 275 core Digital power s ly voltage MBPLIO VEI CORE 3 0 3 3 3 6 I O PLL power supply voltage 2 25 2 5 2 75 Power Avpp 3 0 3 3 3 6 voltage Analog reference voltage VREF Vrer Avpp io 3 0 3 3 3 6 Operating frequency for _ 2 25 to 2 75 E ML674001 Series fosc 10 3 0 to 3 6 33 333 MHz Operating frequency for _ 2 25 to 2 75 v ML675001 Serie
343. proval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these 8 No part of the contents contained herein may be reprinted or reproduced without our prior permission Copyright 2003 Oki Semiconductor 44424 Oki REGIONAL SALES OFFICES Northwest Area 785 N Mary Avenue Sunnyvale CA 94085 Tel 408 720 1900 Fax 408 720 8965 Northeast Area Shattuck Office Center 138 River Road Andover 01810 Tel 978 688 8687 Fax 978 688 8896 North Central Area 1450 East American Lane Suite 1400 Schaumburg IL 60173 Tel 847 330 4494 Fax 847 330 4491 Southwest and South Central Area 1902 Wright Place Suite 200 Carlsbad CA 92008 Tel 760 918 5830 Fax 760 918 5505 Southeast Area 4800 Whitesburg Drive 30 PMB 263 Huntsville AL 35802 Tel 256 468 7037 Oki Web Site http www okisemi com us February 2004 Oki Semiconductor Corporate Headquarters 785 N Mary Avenue Sunnyvale CA 94085 2909 Tel 408 720 1900 Fax 408 720 1918
344. pulse 12 E width XSDCLK Low level pulse 30 ns 12 width pF XSDCLK Rise time tspcR 2 XSDCLK Fall time tspcF 2 HCLK frequency fuc 0 125 33 333 MHz HCLK cycle time tuc 30 8000 ns CCLK frequency foc 0 125 33 333 MHz CCLK cycle time tcc 30 8000 ns CKO frequency fox 0 125 7 33 333 MHz The same frequency as HCLK CKO cycle time tox 30 8000 High level pulse t 12 2 2 width xd CKO Low level pulse t 30 12 2 ns width E pF CKO Rise time tckR 2 Fall time 2 Notes 1 Minimum of 2 56 MHz Maximum of 390 6ns for external SDRAM Minimum of 6 4 MHz Maximum of 156ns for external EDO DRAM 2 Minimum of 2 MHz Maximum of 500ns for analog to digital converter 24 6 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics B Reset Interrupt DMA Timing 2 25 10 2 75V 3 0 to 3 6V Ta 40 to 85 C Item Symbol abd Minimum Typical Maximum Unit Notes Except for when power is first RESET N pulse width 1 trstw1 20 ns applied or returning from STANDBY mode Oscillation When power is first applied or RESET N pulse width 2 trstw2 stabilization returning from STANDBY interval mode EFIQ N pulse width teFlaw 2 tuc EXINT pulse width 1 tExINTW1 2 tuc Except
345. purpose port E bit 5 EXINT O0 PIOE 6 General purpose port E bit 6 EXINT 1 PIOE 7 General purpose port E bit 7 EXINT 2 PIOE 8 General purpose port E bit 8 EXINT 3 PIOE 9 General purpose port E bit 9 EFIQ N 13 3 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 1 3 Register List Address Name Abbreviation R W Size Initial Value 0xB7A01000 Port A output register GPPOA R W 16 Indeterminate 0xB7A01004 Port A input register GPPIA R 16 Reflects pin states 0xB7A01008 Port A mode register GPPMA R W 16 0x0000 0xB7A0100C Port A interrupt enable register GPIEA R W 16 0x0000 0xB7A01010 Port A interrupt polarity register GPIPA R W 16 0x0000 0xB7A01014 Port A interrupt status register GPISA R W 16 0x0000 0xB7A01020 Port B output register GPPOB R W 16 Indeterminate 0xB7A01024 Port B input register GPPIB R 16 Reflects pin states 0xB7A01028 Port B mode register GPPMB R W 16 0x0000 0xB7A0102C Port B interrupt enable register GPIEB R W 16 0x0000 0xB7A01030 Port B interrupt polarity register GPIPB R W 16 0x0000 0xB7A01034 Port B interrupt status register GPISB R W 16 0x0000 0xB7A01040 Port C output register GPPOC R W 16 Indeterminate 0xB7A01044 Port C input register GPPIC R 16 Reflects pin states 0xB7A01048 Port C mode register GPPMC R W 16 0x0000 0xB7A0104C Port C interrupt e
346. r read write Bank ML674001 ML67Q4002 0x10000000 to 1 1 word access Bank 2 Bank 5 ML67Q4003 0x10007FFF 2 half word access 2 byte access ML675001 ML67Q5002 0x50000000 to 3 non cacheable Bank 10 ML67Q5003 0x50007FFF Writing 0 000 to the remap control RMPCON register remaps bank 0 to built in RAM for ML674001 Series Writing 0x000A to the remap control RMPCON register remaps bank 0 to built in RAM for ML675001 Series 10 3 Built In FLASH ROM The built in FLASH ROM has the following features e Bus width 16 bits with 8 16 and 32 bit read access e Sample setting of memory access clock cycles HCLK frequency MHz Access clock cycles OE WE pulse width ML674001Series ML675001 Series 1 13 3 1 1 13 3 26 7 2 2 26 7 33 3 3 3 33 3 40 3 40 53 3 5 53 3 60 5 In order to set up the number of clock cycles for access of FlashROM please set ROMTYPE 2 0 of a ROMAC register as OE WE pulse width Refer to section 11 2 3 List of Flash ROM capacity Flash ROM capacity Address map Bank 25 ML674001 ML675001 ROM Less ML67Q4002 ML67Q5002 256kilobytes 128K 16 bits 0xC8000000 to 0xC803FFFF ML67Q4003 ML67Q5003 512kilobytes 256K 16 bits 0xC8000000 to 0xC807FFFF 10 1 ML674001 Series ML675001 Series User s Manual Chapter 10 Built In Memory If the BSEL 1 0 external pin input levels are LL bank 0 0x00000000 to 0x0
347. r DMAC 12 3 3 Starting a DMA Transfer The following is the procedure for starting a DMA transfer 1 Set the bit in the DMA transfer mode register DMACTMODO DMACTMODI for the channel to 1 to mask channel operation This step is not necessary if the channel is currently masked Write to the DMA interrupt clear register DMACCINTO or DMACCINTI for the channel to clear the status bits ready for a new transfer This step is not necessary if there is no interrupt request pending from the last DMA transfer Configure the DMA transfer mode register DMACTMOD0 or DMACTMODI for the channel Load the DMA transfer source address register DMACSADO or DMACSADI for the channel Load the DMA transfer destination address register DMACDADO or DMACDADI for the channel Load the DMA transfer count register DMACSIZO or DMACSIZ1 for the channel Set bit in the DMA transfer mode register DMACTMODO or DMACTMOD1 for the channel to 0 to release the mask Note DMA transfers do not start however if the DMA transfer complete status is not clear step 2 12 17 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 3 4 Ending a DMA Transfer DMA transfers end in one of three ways 1 Normal termination The DMA transfer automatically ends when the number of transfers specified in the DMA transfer count register DMACSIZO or DMACSIZ1 for the DMA chan
348. r nIR22 nIR26 nIR28 nIR31 to this register resets the corresponding interrupt request bit to 0 but only if the specified external interrupt nIR22 nIR26 nIR28 nIR31 uses edge detection as the trigger Such writes are ignored for level detection The CPU has only write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRCL wx EDS 2 _ 225 ask 2759 E 9 i _ icp Ro ENSE uw 25 SK Address Ox7BF00004 Access Access size 32 bits Notes Always write 0 to these bits Bit Descriptions IRCL 6 0 bits 0 to 6 These bits correspond to the interrupt source number for external interrupts nIR22 nIR26 nIR28 nIR31 For edge triggered interrupts writing an interrupt source number to these bits will de assert the corresponding interrupt 8 20 8 4 13 Register ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller Reading this register returns 1 bits for pending interrupt requests Writing 1 to a bit resets it to 0 clearing the corresponding interrupt request but only if that external interrupt nIR22 nIR26 nIR28 and nIR31 uses edge detection as the trigger Such writes are ignored for level detection The CPU has read write access to this register subject to write restrictions noted below
349. r 2 CPU Aborts An abort indicates failure to complete the current memory access The CPU detects abort exceptions during the memory access cycle There are two types of aborts e Prefetch abort during instruction prefetch e Data abort during data access A prefetch abort marks the instruction as invalid but the exception is not processed until the instruction reaches the head of the pipeline If an intervening branch or other cause prevents execution there is no abort exception The handling of a data abort depends on the instruction type A single data transfer instruction LDR or STR proceeds as far as the base register update if specified The abort handler must watch out for this e swap instruction SWP aborts without doing anything at all e block data transfer instruction LDM or STM runs to completion updating the base register if specified If the instruction overwrites the base register contents with data that is includes the base register in the transfer list the overwrite is aborted Detection of an abort blocks all such register overwrites One important consequence is that an aborted LDM instruction always preserves the contents of R15 the last register to be transferred The exception handler after removing the cause of the abort must regardless of the state ARM or THUMB execute the appropriate instructions to restore the program counter PC and current program status CPSR register and r
350. r accessing memory 2 11 1 2 11 2 Load Store Instructions Load store instructions offer three basic addressing modes each specifying a base register and an offset Offset addressing mode The memory address consists of the offset added to or subtracted from the base register contents Preindex addressing mode The memory address is the same as for the offset addressing mode This address then overwrites the base register contents Postindex addressing mode The memory address is the base register contents The hardware then updates the base register by adding or subtracting the offset The offset is either an immediate value or the contents of an index register There are options for shifting the contents of an index register before the addition or subtraction Multiple Load Store Instructions Multiple load instructions load two or more general purpose registers from memory Multiple store instructions store two or more general purpose registers in memory These instructions offer four addressing modes Increment after The base register contents are incremented after the transfer Increment before IB The base register contents are incremented before the transfer Decrement after DA The base register contents are decremented after the transfer Decrement before DB The base register contents are decremented before the transfer 2 10 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 12 Exc
351. r holds 5 to 8 bits of data depending on the character length Data transfers always start from the lowest bit bit 0 in the serial data Double buffering allows the software to read ACE data registers even while the UART is converting data between parallel and serial formats The CPU has only read access to this register The register contents after a reset are indeterminate 7 6 5 4 3 2 1 0 UARTRBR RBR 7 0 After a reset Indeterminate Address 0xB7B00000 Access R Access size 8 bits ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 2 Transmitter Holding Register UARTTHR This data register holds 5 to 8 bits of data depending on the character length If the character length is less than 8 bits the bits must be at the low end because data transfers always start from the lowest bit bit 0 Double buffering allows the software to read ACE data registers even while the UART is converting data between parallel and serial formats The CPU has only write access to this register 7 6 5 4 3 2 1 0 UARTTHR THR 7 0 After a reset Indeterminate Address 0 7 00000 Access Access size 8 bits ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 3 Interrupt Enable Register UARTIER This register is for independently enabling four serial interface interrupts The CPU has read
352. r of data bits for SIO transfers LN Description 0 8 data bits 7 data bits bit 1 This bit controls the use of parity bits during SIO transfers Setting this bit to 1 adds a parity bit to outgoing frames and checks parity for incoming ones PEN Description 0 Disable parity 1 Enable parity e EVN bit 2 This bit specifies the parity logic odd or even for SIO transfers It is only valid however when PEN is 1 EVN Description 0 Odd parity 1 Even parity e TSTB bit 3 This bit specifies the number of stop bits for SIO transfers 17 6 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO TSTB Description 2 stop bits 1 stop bit 17 7 ML674001 Series ML675001 Series User s Manual Chapter 17 SIO 17 2 4 Baud Rate Control Register SIOBCN This register starts and stops the baud rate timer counter SIOBTC The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIOBCN _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ _ _ _ _ _ 213 _ _ ER BGRUN _ as _ _ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB800200C Access R W Access size 32 bits Note
353. rator 16 2 4 PWM Control Registers PWCON 1 These registers start and stop the PWM counter specify the operating clock and specify the interrupt source The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ol 1 251 PwcoovNTIEO n PWCKO PwoR PWCONO PWCOV 0 PW1R L Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 700000 CHO 0xB7D0002C CH1 Access R W Access size 16 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored Bit Descriptions PWOR PWIR bit 0 This bit controls PWM counter operation PWOR PW1R Description 0 Stop PWCx counter 1 Start enable PWCx counter e PWCK0 PWCK1 bits 1 and 2 These bits specify the frequency divisor for deriving the PWCx operating clock from CCLK PWCKO PWCK1 Description 2 1 0 0 1 1CCLK 0 1 1 4CCLK 1 0 1 16CCLK 1 1 1 32CCLK INTIEO INTIEI bit 6 This bit controls interrupt requests INTIEO INTIE1 Description 0 Disable interrupts 1 Enable interrupts e PWC0OOV PWCIOY bit 7 This bit specifies the interrupt request trigger and output timing PWCOOV PWC1OV Description 0 When PWCx
354. reserved B7EO 0000 WDT control register 9800 0000 B7DO 0000 PWM control register B7BO 1000 Synchronous SIO control register a000 ooo 8780 0000 DART Sona B7A0_ 1000 Port control register 8800_0000 Pied B780 1000 B780 0000 2 control register 16 8000 0000 reserved B710 0000 7 00 0000 B700 0000 Chip configuration control register 15 7830 0000 AHB standard 10 7800 0000 uPlat Core B600 2000 B600 1000 Analog to digital converter control register 14 7000 0000 reserved reserved 13 6800 0000 reserved 000 0000 12 I 6000 0000 reserved 11 lt d 8000 0000 5800 0000 esemed CEU 10 Internal RAM 7 00 0000 5000 0000 0000 Expansion interrupt control register 9 reserved 7BEO 0000 DMA controller control register 4800 0000 7840 0000 reserved 7830 0000 External 1 0 access control register bank31 8 4000 0000 7820_0000 Cache memory control register 7818 0000 DRAM controller control register 4 3800_0000 reserved 7810 0000 External memory and 1 0 access control register bank30 7800 0030 6 3000 0000 1800 0000 Interrupt control register 5 2800 0000 reserved o 4 2000 0000 reserved o 3 1800 0000 2 1000_0000 reserved 5000 0000 esere reserved Remappable ROM RAM 4800 1000 0000 0000 AHB Ext 4800 0000 Note Do not carry out access to the reserved regions in the address Operation is not guaranteed when accessing 3 3
355. responding port mode GPPMx register configures it for output The CPU has read write access to these registers The register contents after a reset are indeterminate 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T T T T T T T T T T T T T T GPPONGPPOB GPPOA 7 0 GPPOB 7 0 GPPOC 7 0 GPPOD 7 0 GPPOE 9 0 GPPOC GPPOD _ _ _ _ _ 3 GPPOE uses bit9 amp bit8 For other GPPOX bit9 4 bit8 are GPPOE After a reset indeterminate Address 0xB7A01000 GPPOA 0xB7A01020 GPPOB 0xB7A01040 GPPOC 0xB7A01060 GPPOD 0xB7A01080 GPPOE Access R W Access size 16 bits Note These bits are reserved for future expansion They return for reads Writes to them are ignored 13 2 2 Port Input Registers GPPIA GPPIB GPPIC GPPID and GPPIE These registers reflect the input levels for the corresponding port pins PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 If a pin is configured for output however the corresponding bit reflects its output level The CPU has only read access to these registers The register contents after a reset reflect the port pin PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 input levels 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 T T T T T T T T T T T T T T GPPIA GPPIB GPPIC GPPID GPPIE GPPIA 7 0 GPPIB 7 0 GPPIC 7 0 GPPID 7 0 GPPIE 9 0 GPPIE uses bit9 amp bit8 For other GPPlx 519 8 bit8 are After a reset P
356. ress of 0x1000001 1 Word 32 bit transfer The DMA controller internally forces the lowest 2 bits to 00 for an effective address of 0x10000000 Reading the register however returns 0x1000001 1 Halfword 16 bit transfer controller internally forces the lowest bit to 0 for an effective address of 0x10000010 Reading the register however returns 0x1000001 1 12 13 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 2 8 Transfer Count Registers DMACSIZO and DMACSIZ1 These registers specify the transfer count for the corresponding DMA channel The DMA controller decrements this count after each successful read from the transfer source Note that this count represents the number of transfers not the total size of the transfer The maximum possible setting for this register is 00010000 65 536 The program has read write access to this register The contents after a reset are 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMACSIZ0to 1 CSIZ16 After a reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSIZ 15 0 Address 0x7BE00110 CHO Ox7BE00210 CH1 Access R W Access size 32 bits Notes These bits are reserved for future expansion They return 0 for reads Writ
357. ress specification methods 7 bit address mode and 10 bit address mode In 7 bit address mode set an address in the higher 7 bits of the I2CSAD register namely SAD 7 1 Then set the data transfer direction transmission or reception in the least significant bit SADO In 10 bit address mode set an address in the higher 2 bits of the I2CSAD register namely SAD 2 1 as well as in the lower 8 bits of the I2CDR register namely XXXX 7 0 Then set a fixed value of 11110 which indicates that succeeding addresses are in 10 bit address mode in the higher 5 bits of the I2CSAD register namely SAD 7 3 Furthermore set the data transfer direction transmission or reception in the least significant bit SADO of the I2CSAD register 7 bit Address Mode I2CSAD I2CDR SB BB B BIBB AB BBBI B BIBB AISIBIBIB 7 6 5 4 131211 716 151413121110 1 171615 7 bit address Data Register settings I2CSAD xxxxxxx0b Setting an address I2CDR xxxxxxxxb lt Setting data I2CCON xxx0x110b 10 bit Address Mode 12 5 I2CDR I2CDR B B B B B B B 5 5 321 7651413121110 11 17 615 716154 UU Fixed value 11110 Higher 2 bits of Lower
358. ributed CAS before RAS CBR refresh operation and stops the SDRAM clock signal XSDCLK until the next deactivate request 2 Stop the clock signal to the DRAM controller in software or shift to STANDBY mode 7 4 2 Deactivating Self Refresh Operation When the software or return from STANDBY mode restarts the clock signal to the DRAM controller write 111 in the DCMD register DRCMD bits to deactivate self refresh operation The DRAM controller then restarts both the SDRAM clock signal XSDCLK and distributed CAS before RAS CBR refresh operation 7 13 Chapter 8 Interrupt Controller ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller Chapter8 Interrupt Controller 8 1 Overview This LSI has an 8 level priority individually maskable highly configurable interrupt controller The interrupt controller features are designed to provide flexibility to software programmer for designing an efficient interrupt handling routine The interrupt controller is connected to the nFIQ fast interrupt request and nIRQ interrupt request inputs of the ARM7TDMI processor processor nFIQ is only asserted in response to an external request through the pin EFIQ N The processor nIRQ is asserted in response to interrupt requests from internal peripherals or external pins EXINTO EXINT3 In total the interrupt controller supports 23 interrupt IRQ sources and 1 fast interrupt source Nineteen of the
359. ription 0 Supply 1 Stop bit 1 This bit controls the PWM block clock signal BCKCTL 1 Description 0 Supply 1 Stop BCKCTL 2 bit 2 This bit controls the timer 0 clock signal BCKCTL 2 Description 0 Supply 1 Stop BCKCIL 3 bit 3 This bit controls the timer 1 clock signal BCKCTL 3 Description 0 Supply 1 Stop 7 4 4 bit 4 This bit controls the timer 2 clock signal ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management BCKCTL 4 Description 0 Supply 1 Stop 5 bit 5 This bit controls the timer 3 clock signal BCKCTL 5 Description 0 Supply 1 Stop BCKCTL 6 bit 6 This bit controls the timer 4 clock signal BCKCTL 6 Description 0 Supply 1 Stop BCKCTL 7 bit 7 This bit controls the timer 5 clock signal BCKCTL 7 Description 0 Supply 1 Stop BCKCTLIS bit 8 This bit controls the DRAM controller clock signal BCKCTL 8 Description 0 Supply 1 Stop BCKCTL 9 bit 9 This bit controls the DMA controller clock signal BCKCTL 9 Description 0 Supply 1 Stop 7 5 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management BCKCTL 10 bit 10 This bit controls the UART clock signal
360. rol register 0000 DMA controller control register 7830 0000 reserved 7820 0000 reserved 7818 0000 DRAM controller control register 7810 0000 External memory and 1 0 access control register 7800 0030 reserved 0000 reserved 4800 1000 4800 0000 Banks 4 5 respectively mirror banks 26 external SRAM and internal RAM so that software can treat the two as a single contiguous memory region map Operation is not guaranteed when accessing Do not carry out access to the reserved regions in the address ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping 3 2 2 ML675001 series address map Bank Address FFFF FFFF 31 00 0000 External I O 3 F800 0000 External 2 30 F400 0000 External I O 1 F000 0000 External 0 29 External SRAM E800 0000 mirror of bank 26 8 xternal ROM D000 0000 E000 0000 mirror of bank 25 External ROM MCP Flash ROM refer to table 3 27 E External DRAM 0000 1 w D800 0000 mirror of bank 24 MCP Flash ROM External ROM refer to table 3 26 External SRA ae 1 0000 0000 TEND 25 C800 0000 External ROM C000_0000 24 Core APB IO B800_2000 SIO control register 2 B800 0000 B800 1020 B800 1000 System timer control register 22 000 0000 Standard APB IO B800 0020 reserved B800 0000 System control register 21 A800 0000 reserved B800 0000 20 A000_0000 B7F0 0000 Auto reload timer control register 49
361. rrupt source number to this register and asserts the interrupt request nIRQ signal to the CPU The CPU has only read access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IRN 22 _ _ _ _ _ _ _ _ _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Iu E ane HEN _ _ _ IRN 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0x78000014 Access R Access size 32 bits Notes Bits labeled return 0 for reads but we recommend that the program not assume 0 and mask them or adopt other don t care measures Bit Descriptions e IRN 6 0 bits 0 to 6 These bits give the interrupt source number for the IRQ request with the highest priority For the mapping of interrupt sources to source numbers see Section 8 2 4 Interrupt Source List 8 12 8 4 7 CIL Current Interrupt Level Register CIL ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller This register indicates the interrupt levels for interrupts currently being processed that is whose interrupt source numbers have been read from the IRN register The CPU has read write access to this register After a reset 0 31 30 29 28 27 26 25 24 23 22 21
362. rupt Identification Register UARTIIR This register indicates whether there is a prioritized interrupt pending and if so the source for that interrupt The IIR field gives the source for the interrupt with the highest priority The hardware does not recognize other interrupts until the CPU processes the current interrupt The CPU has only read access to this register The register contents after a reset are 0 01 7 6 5 4 3 2 1 0 UARTIIR IIR 7 0 After a reset 0 0 0 0 0 0 0 1 Address 0xB7B00008 Access R Access size 8 bits Bit Descriptions IIR 0 bit 0 This bit indicates whether there is an interrupt pending IIR O Description 0 There is an interrupt pending 1 There are no interrupts pending IIR 3 1 bits 3 to 1 These bits indicate the interrupt source Interrupt Setting and Resetting Interrupt Notes Priority Resetting 3 1 level Interrupt Flag Interrupt Source Interrupt 011 1 Receiver Line OverrunError ParityError Read LSR Status FlamingError Breaklnterrupt 010 2 Received Data Unbuffered 16450 operation Read RBR Available Receive data available until queue Buffered operation Trigger level below trigger reached level 110 2 Character There is at least one character in Read RBR Buffered Timeout the receive queue and there has operation Indication been no data movement into or off only the receive queue for the equivalent of fo
363. s 2 fosc Vo 0 3 0 to 3 6 60 MHz Ambient temperature Ta 40 25 85 C Note 1 Applied for ML675001 Series 2 Crystal frequencies between 16 MHz and 33 MHz for ML674001 Series 3 Crystal frequencies between 5 MHz and 14 MHz for ML675001 Series 4 Minimum of 2 56 MHz for external SDRAM Minimum of 6 4 MHz for external EDO DRAM 2 MHz for analog to digital converter 24 2 Minimum of 24 3 24 3 1 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics Electrical Characteristics DC Characteristics for ML674001 Series 2 25 to 2 75 3 0 to 3 6V Ta 40 to 85 Symbol Conditions Minimum Typical Maximum Unit High level input voltage Vpp 10X0 8 10 0 3 Low level input voltage Vit 0 3 Vpp 10 0 2 Schmitt Input Buffer mE a Mi td us Vuys 0 4 0 5 High level output voltage Vou ME 4 mA 2 35 Low level output voltage lo 100 pA 0 2 Low level output voltage VoL lo 4 0 45 Low level output voltage lo 6 mA 0 45 Input leak current Vi OV Vpp io 50 50 Vi 20V Input leak current li Pull up resistance of 200 66 10 50 Input leak current y li Vi AVpp OV
364. s Manual Table of Contents Table of Contents Chapter 1 Introduction 18 01 ED E T T E T EE MERE EE 1 1 1 2 Functional Blocks s tenete nb a ES 1 4 12 1 ME67400I senes Block Diagram er eL E ERR DRE OR 1 4 12 2 ME67500I senes Block Diagram nro epe anc RD Ee OR ra 1 5 153 1 6 13 1 1 6 13 121 1 6 1 3 1 2 1 3 2 ERO tM ie d 13 3 Descriptions ue ee bred aieo o te hoe eerte UR UD rA RE Rd 1 12 1 3 4 IPI States Sky u de eee 1 16 1 35 and Treatment eere Erie a ARA 1 18 1 3 6 Unused D Sau pu tereti eee eee 1 20 Chapter2 CPU 221 OVERVIEW ouest E HER i UR de tete RE ee Mags ee te EUR ree 2 1 2 2 CPU Operation States oce eet de e e RO Ao cete da emet to dete Lees 2 1 2 2211 State Tans tons c tent eta 2 1 2 3 Address Space eR een ern ira tette nete 2 1 2 Format icti e ER E ERRARE HERE ERE RE io 2 2 2 5 Instruction Den tli o oar i og o CE eic 2 2 2 6 Types asocio omo ep n eee cbe ee bee b p EO T 2 2 2 7 Processor MOdeS tea oa ib 2
365. s even after the CPU shifts to HALT mode If this behavior is not desirable set the ITM and ITEN bits in the WDTBCON register to 1 and 0 respectively to switch to interval timer operation and stop the counter When the CPU leaves HALT mode write 0 to the ITM bit to resume watchdog timer operation and restart the counter STANDBY mode suspends watchdog timer operation 14 6 Chapter 15 Timers ML674001 Series ML675001 Series User s Manual Chapter 15 Timers Chapter 15 Timers 15 1 Overview This LSI features one 16 bit System timer and a Timer Counter block which includes six identical 16 bit timer counter channels The System Timer is internal to the core block of the MCU and is ideal for handling system tasks The Auto Reload Timer channels are each programmed independently to perform a wide variety of tasks In addition each Timer drives an internal interrupt signal which can be programmed to generate processor interrupts The following list summarizes the main features of the System Timer and the Auto Reload Timers System Timer 6 bit counter nterrupt request on overflow Count clock is CCLK 16 nterval timer operation e Auto Reload Timers 16 bit counters for each timer Interrupt request on compare match Independent clock settings for each timer Choice of one shot or interval timer operation for each timer 15 1 1 Components Figure 15 1 is a block diagram giving com
366. s possible to load data into a way that is to be locked data so loaded can be handled as instructions or data Flushing Function The flushing function initializes the control information within the cache memory cache memory is flushed by writing any data in the FLUSH register Since the cache memory is flushed by this flushing operation after this operation there will be no instructions or data in the cache memory Since no write back operation is made during flushing the cache memory will be initialized without writing back the latest instructions and data present in the cache memory into the actual memory Further since the cache memory is not initialized flushed at the time this LSI is reset be sure to flush the cache memory by software after resetting the LSI Examples of setting Section 9 7 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 4 Precautions in Use 9 4 1 Precautions when Using DMA Transfer A bank for which the cacheable setting has been made should not be set as the buffer area for carrying out transfer reason for this is that while transfer is made with the actual memory since the accesses from the CPU are made to the cache memory setting a cache memory bank as a buffer for DMA transfer can cause mismatches in the contents of the memory Therefore use only a non cacheable bank as the buffer area for DMA transfers By using the memory mirr
367. s the treatment of unused pins Table 1 4 Treatment of Unused Pins Pin Name Treatment TDI TMS High level nTRST TCK Low level TDO Open PIOA 7 0 PIOB 7 0 Configured for input High or Low level PIOC 7 0 PIOD 7 0 PIOE 9 0 Configured for output open AVDD VDD 10 VREF VDD ML674001 Series Only VREFP VDD 10 ML675001 Series Only VREFN GND ML675001 Series Only to VREF or AGND AGND GND EXINT3 2 1 0 High level Note EFIQ_N High level XA 18 0 Open XWE_N XBWE N 1 0 Open XRAMCS N XIOCS N 3 0 XBS N 1 0 DRAME N DRAM function enabled Low level DRAM function disabled High level CKOE N CKO output enabled Low level CKO output disabled High level TEST Low level TEST1 Low level ML675001 Series Only JSEL Low level FWR Low level CKO Open The EXINT3 2 1 0 pins default to Low level interrupts so drive them at High level immediately after a reset to prevent spurious interrupt requests If the user application system subsequently switches to High level interrupts drive them at Low level 1 20 Chapter 2 CPU ML674001 Series ML675001 Series User s Manual Chapter 2 CPU Chapter2 CPU 2 1 Overview This LSI features the ARM7TDMI core a RISC CPU developed by Advanced RISC Machines Limited ARM The ARM7TDMI core allows user application programs to freely switch as necessary between the ARM
368. scription 0 No effect 1 Clear interrupt request bit 8 21 ML674001 Series ML675001 Series User s Manual Chapter 8 Interrupt Controller The following table shows the condition that each IRQ n n 16 to 31 bit is set if the interrupt uses level detection as the trigger Interrupt Request State in the table is interrupt request signal from each internal device or external interrupt pin Interrupt Level Setting is a value of interrupt level in the ILCI register Interrupt Request State Interrupt Level Setting IRQ n 0 L 0 0 1 Nonzero 1 to 7 1 The following table shows the condition that each IRQ n n 22 26 28 31 bit is set or cleared if the interrupt uses edge detection as the trigger IRQA register provides two ways to clear the corresponding bit for an external interrupt IRQ 22 IRQ 26 IRQ 28 IRQ 31 that is using edge detection as the trigger Event Polarity Interrupt Level IRQ n Writing 1 to IRQ n Clear to 0 Writing corresponding interrupt number in IRCL register id Rising edge in interrupt request 0 Not set 0 Rising edge signal 1107 Set to 1 Falling edge Not set 0 Sz O Rising edge Not set 0 a ing edge in interrupt reques 0 Not set 0 signal Falling edge 1107 Set to 1 goes to
369. scription 0 Supply 1 Stop e bit 1 This bit controls the TIC block clock signal TIC is the AMBA Test Interface Controller which is not used in a microcontroller environment and thus can be safely disabled by setting this bit to 1 TIC Description 0 Supply 1 Stop e HALT bit 2 Setting this bit to 1 shifts to HALT mode stopping the clock signals to the following functional blocks CPU system bus bus control circuitry and memory controller interfaces to built in RAM and external memory HALT Description 0 Normal operation 1 Shift to HALT mode ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management STBY bit 7 Setting this bit to 1 shifts to STANDBY mode stopping the system clock oscillation entirely STANDBY Description 0 Normal operation 1 Shift to STANDBY mode 7 8 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 3 3 Clock Gear Control Register CGBCNTO This register specifies the divisors for deriving the HCLK and CCLK clock signals from base clock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2 _ Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
370. ss depends on the CPU operation state and operating mode 2 8 1 ARM State Registers The ARM state provides access to 16 general purpose registers and the current program status CPSR register at all times Non user privileged modes access their own private register banks and usually a private save program status register SPSR Figure 2 2 indicates these private registers with shaded triangles The ARM state provides direct access to the sixteen registers to R15 but R15 general purpose registers There is also a seventeenth register CPSR which contains control and status information Register 14 This register functions as the subroutine link register because the branch with link BL instruction automatically copies the contents of R15 here When not used for this purpose this register is available for use as a general purpose register The corresponding bank registers 14 R14 irq R14 fiq 14 abt and R14 und hold the return address for an interrupt or exception handler or a BL instruction executed within such a handler Register 15 This register is reserved for use as the program counter PC In the ARM state the program counter is in bits 31 to 2 and bits 0 and 1 are always zero In the THUMB state the program counter is in bits 31 to 1 and bit 0 is always zero Register 16 This is the current program status register CPSR It contains the four condition code flags and bits specifying the
371. st CCLK 256 WDTBCON 25 Reset timer by alternately writing Reset WDTCON 0xC3 and 0x3C watchdog or just 0x3C interval Figure 14 1 Watchdog Timer Components 14 1 2 Register List Address Name Abbreviation R W Size Initial Value 0xB7E00000 Watchdog timer control register WDTCON w 8 0xB7E00004 Time base counter control register WDTBCON R W 8 0x00 0xB7E00014 Status register WDSTAT R W 8 0x00 14 1 ML674001 Series ML675001 Series User s Manual Chapter 14 Watchdog Timer WDT 14 2 Register Descriptions 14 2 1 Watchdog Timer Control Register WDTCON This register is for resetting the watchdog timer to zero The CPU has only write access to this register To start the timer after system reset write 0 3 to this register From that point onward the program must reset the counter to zero at regular intervals by writing to this register and 0x3C alternately for watchdog timer operation or just 0x3C for interval timer operation 7 6 5 4 3 2 1 0 WDTCON WDTCON T 0 Address OxB7EO00000 Access Access size 8 bits 14 2 ML674001 Series ML675001 Series User s Manual Chapter 14 Watchdog Timer WDT 14 2 2 Time Base Counter Control Register WDTBCON This register controls watchdog timer operation specifying such things as the operating clock frequency the operation mode interval timer or watchdog timer and whet
372. stop sequence is transmitted the bus is released after the last byte is transmitted and transmission is then finished Output Input Start Stop Restart Acknowledge Negative Acknowledge Negative sequence sequence sequence received acknowledge transmitted acknowledge received transmitted I2CSAD I2CDR I2CDR I2CDR _ BBIBBBIBIBIB BE EHE B 1716 514131211 7 6 5 4 3 211 0 11615 413 211 10 1161514131211 0 2 1 A CIR 1 1 Flag 2 0 1 byte transmission 1 transmission Transmission finishes finishes complete I2CSAD xxxxxxx0b Waits for Waits for I2CDR xxxxxxxxb I2CCON setting I2CCON setting Register _ I2CDR xxxxxxxxb I2CDR xxxxxxxxb 12 xxx0x110b settings I2CCON xxx0x110b 12 xxx0x100b 20 14 ML674001 Seies ML675001 Series User s Manual Chapter 20 DC 20 3 4 Receive operation transfer of 2 byte or more from slave to master in 7 bit address mode Repeat step from section 20 3 2 The I2CCON register is set to 110 The following series of operations is automatically performed when the S
373. sual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range 5 Neither indemnity against nor license of a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not unless specifically authorized by Oki authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipment safety devices aerospace equipment nuclear power control medical equipment and life support systems 7 Certain products in this document may need government ap
374. t EDO DRAM Byte Half Word Access tEDRAH lEpcap XA 15 0 tepRasD tEDRAS tepRP pid lt tEDRCD tencas lt NI teDoeD1 2 lt XOE N teDxDsMPLD gt tepxpis tEDxDIH XD 45 0 Data sampling timing 24 41 ML 674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics EDO DRAM Write Cycle Bus Width 16 bit EDO DRAM Byte Half Word Access tEpRAH tepcap tiEpcAH XA 15 0 tepRP XRAS N XCAS 1 tepweEp2 XWE N XD 15 0 24 42 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics EDO DRAM Read Cycle Bus Width 8 bit EDO DRAM Half Word Access Bus Width 16 bit EDO DRAM Word Access tEDRAH XA 15 0 RAT 1 1 1 2 EDRASD teDRAS tepRP XRAS N tencas tencas mM gt XCAS_NI1 XCAS tEpoED1 2 lt 4 XOE N tEpxpsMPLD tEpxpsMPLD amp 4 n tepxpis gt lt XD 15 0 DA1 1 DA1 2 Data sampling Data sampling timing timing 24 43 ML674001 Series ML675001 Series User s Manual Chapter 24 Electrical Characteristics EDO DRAM Write Cycle Bus Width 8 bit EDO DRA
375. t all exceptions can occur at once Undefined instruction and software interrupt share a level because they are mutually exclusive featuring nonoverlapping opcodes If a data abort occurs at the same time as FIQ and FIQs are enabled that is the CPSR s flag is CPU proceeds to the data abort handler and then immediately to the FIQ vector Returning normally from the FIQ handler thus causes the data abort handler to resume execution Data abort has a higher priority than FIQ to ensure detection of transfer errors The time for this exception entry should be added to worst case FIQ latency calculations 2 14 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 13 Resets The following operations follow a system reset 1 2 3 4 The CPU copies the current contents of the program counter PC and current program status register CPSR to R14 svc and SPSR_svc overwriting the latter with indeterminate values The CPU loads CPSR with 10011 Supervisor mode in M 4 0 1 in the I and F bits and 07 in the T bit The CPU loads PC from address 0x0000 to fetch the next instruction The CPU resumes execution in the ARM state 2 15 Chapter 3 Address Mapping ML674001 Series ML675001 Series User s Manual Chapter 3 Address Mapping Chapter3 Address Mapping 3 1 Overview This LSI has a 4 gigabyte address space divided into 32 equal banks The flexible features of this MCU enabl
376. t enable GPIEx registers controlling interrupt requests e The port interrupt polarity GPIPx registers specifying the edge trigger polarity for interrupts 13 3 1 Interrupt Requests Figure 13 2 illustrates interrupt operation for 0 pins operate exactly the same way As an example for a given configuration as follows 1 PIOA 0 pin is configured for primary function GPCTL 0 0 2 PIOA 0 is configured as an input pin GPPMA 0 0 3 PIOA 0 interrupt is enabled GPIEA 0 1 4 PIOA 0 triggering edge has been set to falling edge GPIPA 0 0 If the falling edge of an input signal is detected at the PIOA 0 pin of the MCU the interrupt status bit will be asserted GPISA 0 1 thus asserting the interrupt signal PIOINTAN signal to the interrupt controller The above scenario is illustrated in the left timing diagram shown in Figure 13 2 HCLK HCLK PIOA 0 PIOA 0 GPIPA 0 GPIPA 0 GPIEA 0 GPIEA 0 GPISA 0 GPISA 0 PIOINTAN PIOINTAN GPIPA 0 0 GPIPA 0 1 Figure 13 2 Interrupt Operation 13 14 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 3 2 Primary Secondary function configuration PIOA 7 0 PIOB 7 0 PIOC 7 0 PIOD 7 0 and PIOE 9 0 are multiplexed pins that have secondary functions as well These pins can be configured for their primary or secondary function by setting the port function control register GPCTL as described in this chapter
377. t interrupt priority level for IRQn and IRQn 1 The higher the numerical value the higher the priority A setting of zero on the other hand masks interrupts from that source ILC Interrupt Level Priority 2 1 0 1 1 1 1118 7 high priority 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0018 1 low priority 0 0 0 Interrupts masked 8 24 The above settings apply to two interrupt requests each IRQn and IRQn 1 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller Interrupt Sources Interrupt Priority Level Interrupt Sources Interrupt Priority Level ILC16 ILC24 IRQ17 IRQ25 IRQ18 IRQ26 s ILC18 5 ILC26 IRQ19 IRQ27 IRQ20 IRQ28 S ILC20 Q ILC28 IRQ21 IRQ29 IRQ22 IRQ30 2 ILC22 5 ILC30 IRQ23 IRQ31 8 25 ML674001 Series ML675001 Series User s Manual Chapter8 Interrupt Controller 8 4 16 Register Settings for Interrupt Sources The following Table summarizes the register settings for configuring interrupt requests Interrupt Interrupt Level Detection Mode Source Interrupt Source 4 Number Register Bit Register Bit nFIQ nFIQ nIRO System timer ILRO nIR1 Watchdog timer ILCO
378. t selected by CLKSEL before this register write These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions MODE bit 0 This bit specifies the timer operation mode MODE Description 0 Interval timer 1 One shot timer e START bit 3 This bit controls timer operation START Description 0 Stop timer 1 Start timer IE bit 4 This bit controls interrupt requests IE Description 0 Disable interrupts Enable interrupts 15 7 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers e CLKSEL bit 5 to 7 These bits specify as a power of two the frequency divisor for deriving the operating clock from CCLK CLKSEL cii Description 7 6 5 0 0 0 CCLK 0 0 1 CCLK 2 0 1 0 CCLK 4 0 1 1 CCLK 8 1 0 0 CCLK 16 1 0 1 CCLK 32 1 1 0 reserved 1 1 1 reserved 15 8 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 5 Timer Base Registers TIMEBASEO to TIMEBASES These registers specify the counter contents at the start of operation for the corresponding timer Writing to one simultaneously writes the same value to the corresponding timer counter register TIMECNTO to TIMECNT 5 The CPU has read write access to these registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMEBASEO to TIMEBASE
379. tect Cancela 5 ice RI ee ERR e RH EUH ERE et Ere re Uere pt 22 0 22 4 8 Product Identification Software ID oo ee 22 11 viii ML674001 Series ML675001 Series User s Manual Table of Contents 224 9 Protect ua ea i e Een ree ein rte cip a rt ad e e ote pic arin 22 11 22 4 10 Hardware Reset i ae ean e t e ea Aute ee te ide irs 22 11 22 4 11 Detecting the End of an Erase or Program Cycle 22 12 Chapter 23 JTAG 23 T sspe vipera tee te RE e REED RES 23 1 23 1 1 Configur ti n te 23 1 23 12 emos ERR RU pe Pee UTR e R P 23 2 23 2 On Board Deb g E nctl D oio trem eu a deed o pente ene 23 3 23 2 1 Necessary Conditions s ote RD Sa as OS EU Pub up RE Pene 23 3 23 22 Gornmectionis oerte p Ren E RO 23 3 23 3 Boundary Scan E nctl n UD e UTR P P Fee 23 4 23 3 1 Boundary Scan Control nint me e e dpi rpg E Pee ete eene 23 5 23 3 2 Re ISteIS By artes apa oot RAE Aid DARA ei eus tee Hel e ee 23 6 23 3 3 ole eee E a 23 7 23 3 4 Instructions ucc epp eo be telen m ec e 23 8 Chapter 24 Electrical Characteristics 24 1 Absolute Maximum Ratings R aS Q n en netter SS QS terrere 24 1 24 2 Operating Conditionis 25225522 840 dte eem d et eter e e bei P er ee eed
380. ters in that order After the write to SIOBCN the interface allows five baud rate clock cycles for the clock period to stabilize before starting clock output 2 Operation is not guaranteed if the program changes the SIOCON register settings after transfers start 3 The interrupt handler must respond and complete its processing within the interval for transferring a single frame 4 The interrupt handler must clear the interrupt source flag before reading from or writing to the SIOBUF register 5 Leave at least five baud rate clock cycles between successive writes to the SIOBT register 6 Register access from the bus must use word access 17 14 Chapter 18 UART with FIFO 16byte ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte Chapter 18 UART with FIFO 16byte 18 1 Overview The UART built into the LSI is an asynchronous communication element ACE functionally equivalent to the industry standard 16550A with separate 16 byte queues for both transmitting and receiving This UART functions as an I O interface converting serial data from a modem or other peripheral equipment into parallel data and converting parallel data from the CPU into serial data After a reset the UART registers function as an industry standard 16450 During buffered 16550A operation each queue holds up to 16 bytes of data The receive queue provides three error bits for each byte of data The CPU can read the ACE sta
381. th JTAG pins for connecting debuggers and the like The JTAG connector on the board provides access to these pins for onboard debugging Onboard debugging requires the following e A standard JTAG to JTAG ICE hardware such as ARM Multi ICE ARM s software development tools or other debugger software compatible with the JTAG ICE hardware being utilized Development host with the above debugger installed e Appropriate connector cables 23 2 2 Connections The following Figure gives the circuits for connecting this LSI to the JTAG ICE hardware Adaptive off The following are only the most important usage notes For full details refer to the JTAG ICE manual and other references 20 pin JTAG Connector Voo Voo ML674001 Series A A A ML675001 Series 5 5 gt 28 TDO nSRST DBGREQ DBGACK 4 6 8 10 12 14 16 18 20 RESET N GND SYSTEM RESET N Figure 23 2 circuits for connecting this LSI to the JTAG ICE hardware 23 3 ML674001 Series ML675001 Series User s Manual Chapter 23 JTAG 23 3 Boundary Scan Function The boundary scan function built in this LSI conforms with the JTAG Boundary Scan Standard IEEE1149 199 By using the boundary scan function testing and failure diagnostics at chip level and board level are facilitated The boundary scan circuit consists of five JTAG interface pins a boundary scan control circuit and bou
382. the synchronous SIO control register SSIOCON In the master mode a synchronous clock with 1 8 1 16 or 1 32 the frequency of HCLK is output from the SCLK and data is transmitted and received in synchronization with that clock synchronous clock is sellected by the SFTCLK 1 0 bits of the synchronous SIO control register SSIOCON In the slave mode an external synchronous clock is input from the SCLK pin and data is transmitted and received in synchronization with that clock When operating in slave mode the synchronous input clock SCLK must have a frequency equal to or less than 1 8 the frequency of HCLK The communication functionlity when operating in slave mode or master mode is nearly the same The only difference is that during master mode operation the SSIO outputs its clock from the SCLK pin During slave mode operation the SCLK pin works as an input for the clock signal coming from an external syschronous I O NOTE 1 The transmit data output from the SDO pin in the slave mode is output for synchronization after two cycles of HCLK from the falling edge of the synchronous clock input from the SCLK pin The setup of data receiving on the master side is time critical by two cycles of HCLK 19 3 2 Transmit Operation Writing of transmit data to the synchronous SIO transmit receive buffer register SSIOBUF triggers data transmission and the synchronous SIO status register SSIOST BUSY flag is set to 1 One
383. tion In Out Function In Out PIOE 7 In Out EXINT 2 Input 13 12 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO e GPCTL13 bit 13 This bit controls the function of pin PIOE 8 Its secondary function is as EXINT 3 GPCTL13 0 primary function GPCTL13 1 secondary function Function In Out Function In Out PIOE 8 In Out EXINT 3 Input GPCTLIA bit 14 This bit controls the function of pin PIOE 9 Its secondary function is as EFIQ_N GPCTL14 0 primary function GPCTL14 1 secondary function Function In Out Function In Out PIOE 9 In Out EFIQ N Input 13 13 ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO 13 3 Description of Operation This MCU has 42 multiplexed input output pins designed to be easily software configurable to meet various application requirements set of registers defined in this section can configure the I O pins to work in either primary or secondary mode PIO mode these pins can be configured as input or outputs When in input mode the ports can be set as interrupt inputs with configurable edge triggering When configured in their primary function as PIO pins three sets of registers provide control at the individual pin level The port mode GPPMx registers specifying the pin I O directions e port interrup
384. ts of the ARM pipeline Completing the next instruction s accesses takes a minimum of 9 clock cycles 2 Waking from HALT mode takes only 3 to 6 clock cycles because there is no need to wait for the oscillation to stabilize before restoring clock signals to the functional blocks The exact number depends on the wake up signal 7 2 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 2 1 Register List Address Name Abbreviation R W Size Initial Value 0xB7000004 Block clock control register BCKCTL R W 16 0x0000 0xB8000004 Clock stop register CLKSTP R W 32 0x00000000 0xB8000008 Clock select register CGBCNTO R W 32 0x00000000 0xB800000C Clock wait register CKWT R W 32 0x000000FF 7 3 ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 3 Register Descriptions 7 3 1 Block Clock Control Register BCKCTL The block clock control BCKCTL register controls the clock signals to the functional blocks 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BCKCTL eg BCKCTL 12 0 1 1 1 1 1 1 1 1 1 1 1 1 Aftera 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB7000004 Access R W Access size 16 bits Note These bits are for future expansion They return 0 for reads Writes to them are ignored Bit Descriptions e BCKCTL O bit 0 This bit controls the analog to digital converter clock signal BCKCTL 0 Desc
385. tus at any time The status information available includes the type and status of transfer operations in progress parity overrun framing and other errors and the status of break and other interrupts Features Full duplex operation Reporting functions for all states 16 byte queues for both transmitting and receiving Transmit receive and line status data set interrupts plus independent control over each queue Modem control signals CTS DCD DSR DTR RI and RTS Programmable serial interface Choice of 5 6 7 or 8 bits per character Choice of odd even or no parity 1 1 5 2 stop bits ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 1 1 Components Figure 18 1 shows the interface components Pin Name 19522 pue sng Jexe dnjnuu pee 20 IER FCR e 0 HD RSR SIN 16Byte FIFO Receiver Baud rate generator Transmitter control TSR SOUT __ gt RTS 4 DTR Modem trol contro CTS DCD DSR RI Interrupt __y Interrupts control Figure 18 1 Asynchronous Serial Interface Components 18 1 2 Pins Pin Name Direction Description SIN UART serial data in Secondary function for PIOA 0 SOUT O UART serial data out Secondary function for PIOA 1 CTS UART clear to send Secondary function for PIOA 2 DSR UART data set re
386. ue Writing to this register simultaneously writes the same value to the timer counter TMC register The CPU has read write access to this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TMRLR _ _ _ _ _ _ _ _ ET _ _ _ _ _ ES Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 d4 143 12 0 9 8 7 6 5 4 3 2 14 O TMRLR 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0xB8001008 Access R W Access size 32 bits Note These bits are reserved for future expansion They return 0 for reads Writes to them are ignored Leave the following interval between successive writes to this register n x HCLK 79 x CCLK 15 5 ML674001 Series ML675001 Series User s Manual Chapter 15 Timers 15 2 3 System Timer Overflow Register TMOVFR The OVF bit in this register goes to 1 when timer counter TMC overflow generates a system counter overflow interrupt request The CPU has read write access to this register 31 30 29 28 27 260 25 24 23 22 20 19 18 17 16 TMOVFR rei ESL EN Ir E pen E ME 25 d 53 Afterareset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 _ _ mL _ axe _ _ _ EN I Ed ro _ OVF 0 0 0 0 0 0 0 0 0 0
387. uns cane on on CPU 1 Setting bit in the DMA transfer mode register DMACTMODO or DMACTMOD 1 for the channel automatically generates this internal transfer request signal 2 The DMA controller uses dual address mode Figure 12 1 Transfer Start Timing 12 22 ML674001 Series ML675001 Series User s Manual Chapter 12 Direct Memory Access Controller DMAC 12 4 2 Transfer Timing Figure 12 2 shows the timing for transferring data from an I O device on the external bus to memory using cycle stealing mode and DREQ triggers External memory bus width is set as 16 bits the times of the shortest access HCLK DREQO dreqi 0 XOE N XWE N XD DRQCLRO TCOUTO Tdreq the delay between the external request DREQ and acceptance of the internal one dreqi is a maximum of two clock cycles Figure 12 2 Timing for a Transferring Half Word from External I O Device to Memory Using Cycle Stealing Mode and DREQ Triggers 12 23 Chapter 13 GPIO ML674001 Series ML675001 Series User s Manual Chapter 13 GPIO Chapter 13 GPIO 13 1 Overview The four 8 bit GPIO PIOA PIOB PIOC PIOD and one 10 bit GPIO PIOE ports have the following features Ports five The direction is specified at the individual pin level After reset all GPIO pins are configured as inputs by default e Edge detection triggers for interrupts interrupt masks and interrupt modes settings are
388. ur characters 001 3 Transmitter Unbuffered 16450 operation Itis Read IIR or Holding safe to write to THR write to THR Register Empty Buffered operation Transmit THRE queue is empty 000 4 Modem Status CTS DSR RI or DCD Read MSR 18 7 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte IIR 5 4 bits 5 to 4 Unused These return 0 for reads IIR 7 6 bits 7 to 6 These bits indicate buffered operation IIR 7 6 Description 7 6 0 0 Unbuffered 16450 operation 0 1 Unused 1 0 Unused 1 1 Buffered operation ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte 18 2 5 FIFO Control Register UARTFCR This register enables buffered operation clears the queues and specifies the trigger level for the receive queue The CPU has only write access to this register UARTFCR FCR 7 0 7 6 5 4 3 2 1 0 After a reset 0 0 0 0 0 0 0 0 Address 0xB7B00008 Access Access size 8 bits Bit Descriptions FCR 0 bit 0 This bit switches buffered operation on 1 and off 0 FCR 0 Description 0 Unbuffered 16450 operation 1 Buffered operation Note Changing this bit automatically clears both queues bit 1 RCVR queue reset Setting this bit to 1 clears the receive queue
389. urn 0 for reads Writes to them are ignored Bit Descriptions e 1 0 bits 0 and 1 These bits specify the column length which is the dividing line for address multiplexing AMUX 1 0 Description 1 0 Column length RAS address CAS address 0 0 8 bits A 23 8 A 7 0 0 1 9 bits A 23 9 A 8 0 1 0 10 bits A 23 10 A 9 0 1 1 reserved e ARCH bit 2 This bit specifies the DRAM type ARCH Description 0 SDRAM 1 EDO DRAM PRELAT bit 4 This bit specifies the SDRAM pre charge latency PRELAT Description 0 Fixed at 2 clock cycles 1 Use CAS latency setting 11 15 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller PDWN bit 6 This bit controls automatic shifting to SDRAM power down mode PDWN Description 0 Disable automatic shift 1 Enable automatic shift RFRSH bit 7 This bit controls distributed CAS before RAS refresh operation RFRSH Description 0 Stop distributed CBR refresh 1 Enable distributed CBR refresh 11 16 ML674001 Series ML675001 Series User s Manual Chapter 11 External Memory Controller 11 2 9 DRAM Characteristics Control Register DRPC This register specifies the DRAM access timing parameters in clock cycles The program has read write access to this register
390. vc PC CPSR SPSR svc PC CPSR SPSR svc 10011 Abort R7 RO R12 R0 LR_abt SP_abt R14_abt R13_abt PC CPSR SPSR_abt PC CPSR SPSR_abt 11011 Undefined R7 RO R12 RO LR und SP und R14 und R13 und PC CPSR SPSR und PC CPSR 11111 System R7 RO R14 R0 LR SP PC CPSR PC CPSR 2 9 3 Reserved Bits Remaining program status register bits are reserved Be careful not to modify their contents when changing the condition code flags or control bits 2 8 ML674001 Series ML675001 Series User s Manual Chapter 2 CPU 2 10 Instruction Set Features There are two instruction sets 32 bit ARM instructions and 16 bit THUMB ones 2 10 1 2 10 2 ARM Instruction Set The ARM instruction set contains the following six main instruction types Branch instructions Data processing instructions Status register transfer instructions Load store instructions Coprocessor instructions Exception generation instructions Most data processing instructions and one class of coprocessor instructions sometimes update the four condition code flags sign zero carry and overflow in the current program status CPSR Almost all ARM instructions include a 4 bit condition field One such code Always specifies unconditional execution The others specify execution only if the corresponding condition is valid at the start of instruction execution There is no execution if the condition is not met There are 14 such codes f
391. verter The AD conversion should be stopped when changing CCLK clock frequency ML674001 Series ML675001 Series User s Manual Chapter 7 Power Management 7 3 7 7 3 8 HALT Mode HALT mode stops the clock signals to the following functional blocks CPU system bus bus control circuitry and memory controller interfaces to built in RAM and external memory External interrupt requests wake the LSI from HALT mode and restart the clock signals Recovery requires a maximum of 10 clock cycles Functional blocks whose clock signals do not stop remain operational so most can also provide such interrupt requests The DMA controller is an exception however because it cannot transfer data while the system bus is disabled It is not possible for example to wait in HALT mode for a DMA transfer to end and wake the LSI with an interrupt request The following Table summarizes the events producing shifts to and from this mode Shift to HALT mode Wake from HALT mode Write 1 to HALT bit Unmasked interrupt request e SIO e System Timer e UART Timer e PWM e A D e GPIO e External interrupt request Reset STANDBY Mode STANDBY mode stops the system clock oscillation entirely stopping all internal clock signals and greatly reducing power consumption When the LSI wakes from STANDBY mode it does not restart these internal clock signals until the oscillation stabilization interval specified in the clock wait CKWT re
392. w USER S MANUAL ARM BASED MICROCONTROLLER PRODUCTS ML674001 ML675001 Series January 31 2004 advantage microcontrollers Oki Semiconductor Preface This Development Specification contains hardware and software specifications of Oki Electric s ML674001 Series ML675001 Series 32 bit microcontroller The manuals shown below are also available and should be consulted necessary ARM Architecture Reference Manual Description of ARM instruction set architecture 7 Data Sheet Description of ARM7TDMI instruction set Description of ARM7TDMI operation The above documents are published by ARM Corporation Please ensure that you refer to the latest versions This manual uses the following notational conventions Type Notation Notation Meaning Bl Numerals Address Units Terms Oxnn Oxnnnn nnnn word WORD byte BYTE M mega K Kilo k kilo m milli u micro n nano 5 H level L level Hexadecimal number Hexadecimal number It s means Oxnnnnnnnn 1 word 32 bits 1 byte 8 bits 10 2 1024 10 1000 10 second s The VIH or VOH voltage level stipulated in the Electrical Characteristics as the voltage high signal level The VIL or VOL voltage level stipulated in the Electrical Characteristics as the voltage low signal level ML674001 Series ML675001 Series User
393. wice continuously in order to avoid erroneous detections The following shows the flowchart for detecting the end of a cycle by using the toggle bit Start erase or program cycle Read DQ6 from selected block sector or chip Read DQ6 again at the same address Is DQ6 the same data End erase or program cycle Note For DQ6 see Figure 22 1 22 13 Chapter 23 JTAG ML674001 Series ML675001 Series User s Manual Chapter 23 JTAG Chapter 23 JTAG 23 1 Overview This LSI provides the following functions via the JTAG interface e On board debug function e Boundary scan function 23 1 1 Configuration Figure 23 1 shows the configuration of the JTAG interface circuit ML674001 Series ML675001 Series CoreLogic ARM7TDMI TDI TDO TMS Boundary nTRST scan TCK control circuit JSEL Boundary scan cell Boundary scan chain I O pad Figure 23 1 JTAG Interface Circuit ML674001 Series ML675001 Series User s Manual Chapter23 23 1 2 Pin List Pianane 16 TD I Testdata input TDO 0 Testdata output nTRST controller reset signal TMS 1 Testmode select 1 Test clock Mode setting signal JSEL 0 When performing on board debugging 1 When performing boundary scanning 23 2 ML674001 Series ML675001 Series User s Manual Chapter 23 JTAG 23 2 On Board Debug Function 23 2 1 Necessary Conditions This LSI has built in debugging support wi
394. write access to this register The register contents after a reset are 0 00 7 6 5 4 3 2 1 0 UARTIER IER 7 0 After a reset 0 0 0 0 0 0 0 0 Address 0xB7B00004 Access R W Access size 8 bits Bit Descriptions IER 0 bit 0 This bit enables disables received data available interrupts plus character timeout interrupts during buffered operation IER 0 Description Disable received data available interrupts plus character timeout interrupts during 9 buffered operation Enable received data available interrupts plus character timeout interrupts during buffered operation IER I bit 1 This bit enables disables transmitter holding register empty interrupts IER 1 Description 0 Disable transmitter holding register empty interrupts 1 Enable transmitter holding register empty interrupts IER 2 bit 2 This bit enables disables receiver line status interrupts IER 2 Description 0 Disable receiver line status interrupts 1 Enable receiver line status interrupts IER 3 bit 3 This bit enables disables modem status interrupts IER 3 Description 0 Disable modem status interrupts 1 Enable modem status interrupts IER 7 4 bits 7 to 4 Unused These return 0 for reads 18 6 18 2 4 ML674001 Series ML675001 Series User s Manual Chapter 18 UART with FIFO 16byte Inter
395. y control blocking IRQ requests with priority levels at or below those for interrupt requests currently being processed Choice of level or edge sensing for external IRQ sources EXINTO to EXINT3 e Timers One 16 bit system timer Six 16 bit auto reload timers Independent clock settings for each timer Independent choice of one shot or interval timer operation for each timer Maximum period 30 ms or more e Watchdog Timer One 16 bit timer Choice of interval or watchdog timer operation Choice of interrupt or reset upon overflow Maximum period 200 ms or more 1 1 ML674001 Series ML675001 Series User s Manual Chapter 1 Introduction GPIO Four 8 bit ports One 10 bit port Individual settings for pin I O direction Individual settings for pin interrupt requests PWM Two outputs with 16 bit resolution Maximum period 30 ms or more Analog to Digital Converter Four channels of 10 bit resolution each using consecutive comparison Sample and hold function Choice of scan or select operation Conversion time ML674001 series 5 us to 25 us ML 675001 series 2 us to 25 us DMA Controller Two channels Choice of fixed or round robin mode for channel priority order Choice of cycle steal or burst mode for requesting bus access Choice of software or external DMA transfer requests Maximum transfer count 65 536 Data transfer sizes 8 16 and 32 bit External
396. ynchronous SIO test control register SSIOTSCON 0x00 0xB7B0_1010 control register 19 2 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 2 Registers 19 2 1 Synchronous SIO Transmit Receive Buffer Register SSIOBUF The SSIOBUF register holds transmit receive data in transmit receive operations The SSIOBUF register can be read written using a program When writing the register acts as a transmit buffer and when reading the register acts as a receive buffer When receiving the contents of SSIOBUF are held until the next receive operation is completed The SSIOREG register in the configuration diagram in Figure 19 1 is a shift register that converts parallel transmit data to serial data and converts serial receive data to parallel data When transmit data is written to SSIOBUF in a transmit operation the SSIOBUF data is automatically transferred to SSIOREG In a receive operation the SSIOREG data is transferred to SSIOBUF after the final bit has been received The SSIOREG register cannot be read written using a program 7 6 5 4 3 2 1 0 SSIOBUF SSIOBUF 7 0 At reset 0 0 0 0 0 0 0 0 Address 0 7 01000 Access R W Access size 8 bits 19 3 ML674001 Seies ML675001 Series User s Manual Chapter 19 Synchronous 510 19 2 2 Synchronous SIO Status Register SSIOST The SSIOST register indicates the operating state of the synchronous SIO OERR and BUSY can be read written usi
397. ys write 0 to the bit Ifa 1 is written to this bit the operations cannot be guaranteed Bit descriptions C8 C9 C10 C12 C13 C24 C25 C26 C28 C29 CO The cacheable register allows cacheable non cacheable setting for each bank Each of these bits sets the enable or disable condition for the following banks respectively C8 Bank8 C9 Bank9 C10 Bank10 C11 Bank11 C12 Bank12 C13 Bank13 C24 Bank24 C25 Bank25 C26 Bank26 C27 Bank27 C28 Bank28 C29 Bank29 Cn Description 0 Sets the corresponding bank non cacheable 1 Sets the corresponding bank cacheable n 8 9 10 11 12 13 24 25 26 27 28 29 0 C14 C15 C30 C31 These bits are all fixed at 0 Always write Os to these bits when writing to the register operations cannot be guaranteed if a 17 is written to any of these bits 9 4 ML674001 Series ML675001 Series User s Manual Chapter 9 CACHE MEMORY 9 2 3 FLUSH Register FLUSH This FLUSH register is used for carrying out a flushing operation of the cache memory cache memory is initialized flushed by writing any value in the FLUSH register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 don t care 1 Value at reset x x x x x x x x x x x x x x x x 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 don t care 1 Value at reset x x x x x x x x x x x x x x x x Address CACH Base 0x1C Access W

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