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Inverter Control by V850 Microcontrollers 6

1. Compare register value setting TMPO A D converter 1 conversion start trigger value setting compare match occurs 1 us later 20 TMQO control register 0 TQOCTLO Set the TQOCTLO register as follows TQOCTLO register OOH TQOCTLO Address FFFFF5COH 1 After reset 0 0 Bit name TQOCKS2 TQOCKS1 Set value 0 0 TMQO operation control TM O operation disabled TMQO reset asynchronously TQOCKS2 TQOCKS1 TQOCKSO Internal count clock selection Note The TQOOPTO TQOOVF bit and 16 bit counter are reset simultaneously Moreover timer outputs TOQOO to TO O3 and TOQ10 pins are reset to the TQOIOCO register set status at the same time as the 16 bit counter Caution Be sure to set bits 3 to 6 to 0 Application Note U18600EJ1VOAN 31 CHAPTER 2 CONTROL METHOD 21 TMQO control register 1 TQOCTL1 Set the TQOCTL1 register as follows TQOCTL1 register 07H TQOCTL1 Address FFFFF5C1H 1 After reset 0 0 0 0 Bit name TQOEST TQOEEE TQOMD2 TQOMD1 Set value 0 0 1 1 TQOEST Software trigger control 0 No software trigger operation TQOEEE Count clock selection 0 Disable operation with external event count input EVTQO pin Perform counting with the count clock selected by the TQOCTLO TQOCKSO to TQOCTLO TQOCKS2 bits 1 1 1 6 phase PWM output mode Caution Be sure to set bits 3 4 and 7 to 0 22
2. 0 Set the PCC register after the PLL mode is selected PLLCTL SELPLL bit 1 Application Note U18600EJ1VOAN 21 CHAPTER 2 CONTROL METHOD 5 Power save control register PSC Set the PSC register as follows PSC register 00H PSC Address FFFFF1FEH After reset Bit name Set value INTM Standby mode control by maskable interrupt request INTxxNote 0 Standby mode release by INTxx request enabled STB Operation mode selection 0 Normal mode Note For details see Table 17 1 Interrupt Source List in the V850E IA3 V850E IA4 Hardware User s Manual U16543E Cautions 1 The PSC register is a special register Data can be written to this register only in a combination of specific sequences For details refer to 3 4 8 Special registers in the V850E IA3 V850E IA4 Hardware User s Manual U16543E Be sure to set bits 0 2 3 and 5 to 7 to 0 6 Power save mode register PSMR Set the PSMR register as follows PSMR register 00H PSMR Address FFFFF820H After reset Bit name Set value Operation specification in software standby mode 0 IDLE mode Cautions 1 Be sure to set bits 1 to 7 to 0 2 The PSMO bit is valid only when the PSC STB bit is 1 22 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 7 Oscillation stabilization time select register OSTS Set the OSTS register as follows OSTS register
3. RAM section allocation e Interrupt handler registration e Prototype declaration 5 2 Global Variable Processing common c The flowchart of the global variable processing common c is shown below Figure 5 2 Global Variable Processing common c START e define definition e RAM section allocation 62 Application Note U18600EJ1VOAN CHAPTER 5 FLOWCHART 5 3 Global Variable Processing common h common h is externally defined by the EXTERN instruction common h is called by main c pt unit c init c and sin2 c The flowchart of global variable processing common h is shown below Figure 5 3 Global Variable Processing common h START e define definition e RAM section external declaration allocation 5 4 MAIN Processing The MAIN processing initializes the hardware and global variables of the 3 phase PWM driver The following flowchart illustrates the MAIN processing Figure 5 4 MAIN Processing START hinit Hardware initialization ainit Global variable initialization Interrupt enabled Yes Application Note U18600EJ1VOAN 63 CHAPTER 5 FLOWCHART 5 5 PWM Processing Three modes of PWM processing are available direct mode dq conversion mode and output lock mode The 3 phase PWM driver writes the TQOCCRO to TQOCCR3 TQOOPT1 TPOCCRO and TPOCCR1 registers all at once when the TMQO valley interrupt INTTQOOV is generated after the
4. V850E IA4 uPD70F3186GC 8EU A PDLO to PDL15 Function For debugging used only for debugging not used for any other purpose Timer QO TMOO TMQO option TMQOPO Timer PO TMPO PWM output ANIOO Motor drive current for A D converter 0 ANI10 Motor drive current for A D converter 1 16 On chip debug function 1 Description of on chip peripheral I O function a Output ports for debugging Using on chip debug unit Ports used in program debugging Do not input output for any other purpose b PWM output e TMQO Sets the PWM timer count and duty factor in 6 phase PWM output mode e TMQOPO Appends a dead time to PWM generated by TMQO e TMPO Synchronizes TMQO and TMPO and generates the start trigger for conversion of A D converters 0 and 1 PWM settings by the 3 phase PWM driver are as follows Carrier frequency 20 kHz Dead time 4 us Culling rate 1 1 Table 1 3 PWM Output Pin Output Level TOQOT1 to TOQOT3 TOQOB1 to TOQOB3 Output Level Before execution of CALL instruction for 3 phase High impedance PWM While 3 phase PWM driver is operating High impedance high level low level c ANIOO In response to the trigger from TMPO performs A D conversion of the ANIOO value After the A D conversion completes generates the A DO conversion completion interrupt INTADO of the priority level 4 ANIOO Oto 45 V Synchronization trigger timing 1 us after the
5. 2 256 2 128 Therefore TQODTC 128 3 5 Determining PWM Pulse The relationship between the duty ratios of phase U V and W and the values of the TQOCCR1 to TAOCCR3 registers is shown below 1 Calculating output width of upper arm phase The output widths of phases U V and W are calculated by the following expressions including dead time U phase output width TQOCCRO 1 TQOCCR1 x 2 TQODTC x TMQO count clock period V phase output width TQOCCRO 1 TQOCCR2 x 2 TQODTC x TMQO count clock period W phase output width TQOCCRO 1 TQOCCR3 x 2 TQODTC x TMQO count clock period 54 Application Note U18600EJ1VOAN CHAPTER 3 PROGRAM CONFIGURATION 2 Calculating output width of lower arm phase The output widths of phases U V and W are calculated by the following expressions including dead time U phase output width TQOCCRO 1 TQOCCR1 x 2 TQODTC x TMQO count clock period V phase output width TQOCCRO 1 TQOCCR2 x 2 TQODTC x TMOO count clock period W phase output width TQOCCRO 1 TAOCCR3 x 2 TQODTC x TMQO count clock period Figure 3 2 Pulse Calculation in 6 Phase PWM Output Mode Dead time Dead time m LL l Upper arm output width phases U V and W Upper arm phases U V and W Lower arm output width phases U V and W Lower arm phases U V and W App
6. Bitname TQOOVIF TQOOVMK TQOOVPR2 TQOOVPR1 Set value 0 0 0 0 TQOOVIF Interrupt request flagNete 0 Interrupt request signal not issued TQOOVM Interrupt mask flag 0 Interrupt servicing enabled TQOOVPR2 TQOOVPR1 TQOOVPRO Interrupt priority specification bit 0 o 1 Specifies evel 1 Note The interrupt request flag is reset automatically by the hardware if an interrupt request signal is acknowledged Application Note U18600EJ1VOAN 45 CHAPTER 2 CONTROL METHOD 44 Interrupt mask register 0 IMRO Set the IMRO register as follows IMRO register FBFFH 1 2 Address IMRO FFFFF100H IMRO IMROH IMROL IMROL FFFFF100H IMROH FFFFF101H 6 5 4 3 2 1 After reset Bit name TQ0 Tao Tao Tao TQO PMK6PMK5 PMK3 CCMK3CCMK2ICCMK1 CCMKO OVMK 1 1 1 0 Set value Interrupt mask flag setting INTTQ1OV interrupt servicing disabled Interrupt mask flag setting INTTQOCC3 interrupt servicing disabled Q0CCMK2 Interrupt mask flag setting 1 INTTQOCC2 interrupt servicing disabled QOCCMK1 Interrupt mask flag setting 1 INTTQOCC1 interrupt servicing disabled 0CCMKO Interrupt mask flag setting 1 INTTQOCCO interrupt servicing disabled QOOVMK Interrupt mask flag setting INTTQOOV interrupt servicing enabled Interrupt mask flag setting INTCMP 1 interrupt servicing disabled Interrupt mask flag setting INTCMPO interrupt servicing disab
7. TMAO I O control register 0 TAOIOCO Set the TAOIOCO register as follows TQOIOCO register 55H TQOIOCO Address FFFFF5C2H 1 0 After reset 0 0 0 0 0 0 0 0 Bit name TQOOL3 TAOOE3 TQOOL2 TQOOE2 TQOOL1 TQOOE1 TQOOLO TOOOEO Set value 0 1 0 1 0 1 0 1 TQOOLm Output level setting of TOQOm and TOQOTb pins m 0 to 3 b 1 to 3 0 TOQOm and TOQOTb pins start output at high level TQOOEm Output setting of TOAOM and TOQOTb pins m 0 to 3 b 1 to 3 1 Timer output enabled A pulse is output from the TOQOm and TOQOTb pins 32 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 23 TMAO I O control register 1 TAOIOC1 Set the TQOIOC1 register as follows TQOIOC1 register OOH TQOIOC1 After reset Bit name Set value 0 0 0 0 0 Address FFFFF5C3H 0 1 0 0 0 TQOIS7 TQOIS6 TQOIS5 TQOIS4 TQOIS3 TQOIS2 TQOIS1 TQOISO 0 0 0 0 0 0 0 0 TQOIS7 TQOIS6 Capture trigger input signal TIQOS pin valid edge setting 0 0 No edge detection capture operation invalid TQOIS5 TQOIS4 Capture trigger input signal TIQO2 pin valid edge setting 0 0 No edge detection capture operation invalid TQOIS3 TQOIS2 Capture trigger input signal TIAO1 pin valid edge setting 0 0 No edge detection capture operation invalid TQOIS1 TQOISO Capture trigger input signal TIQOO pin valid edge setting 0 0 No edg
8. TMQO valley interrupt INTTQOOV of carrier cycle A D conversion completion time 1 94 us Application Note U18600EJ1VOAN CHAPTER 1 HARDWARE CONFIGURATION d ANI10 e In response to the trigger from TMPO performs A D conversion of the ANI10 value After the A D conversion completes generates the A D1 conversion completion interrupt INTAD1 of the priority level 4 ANI10 0to 5V Synchronization trigger timing 1 ws after the TMQO trough interrupt INTTQOOV of carrier cycle A D conversion completion time 1 94 us On chip debug function The V850E IA4 uPD70F3186GC 8bEU A includes an on chip debug unit and implements the on chip debugging by itself using the on chip debug emulator connected For how to connect to the on chip debug emulator refer to manuals of the debugger used Application Note U18600EJ1VOAN 17 CHAPTER 2 CONTROL METHOD 2 1 Control Block The control block diagram of the 3 phase PWM driver is shown below Figure 2 1 3 Phase PWM Driver Control Block Diagram Control by microcontroller Converted value elt EE conversion Converted value EI conversion Phase U PWM setting Lg Ke Ei E Is g S 8 5 o c Oo 2 S Ke 2 gt o 9 d E md gt e Retention PWM Remark Processing enclosed by broken lines indicates the processing by software Processing of the driver denoted by a heavy solid line varies dep
9. TQOCCR1 register is written Therefore be sure to call the PWM processing with the tmq zero processing when setting the registers in the PWM processing after the TQOCCR1 register is written the next writing of a register is prohibited until the TMQO valley interrupt INTTQOOV is generated The flowchart of the PWM processing is shown below Figure 5 5 PWM Processing START PWM output enabled Yes N o What is operation mode of 3 phase PWM driver Direct mode dq conversion mode Output lock mode e Phase V Previous V phase duty e Phase W lt Previous W phase dut e V phase duty set e W phase duty set 3 phase fixed conversion PWM value set U phase duty set y e Phase U lt Previous U phase duty PWM maximum value check Maximum pulse set d li V W and U phase values are set to TQOCCR2 TAOCCR3 and TQOCCR1 registers V W and U phase values are backed up Is PWM outpu pin in high impedance state Yes High impedance state is canceled High impedance state is backed up RET 64 Application Note U18600EJ1VOAN CHAPTER 5 FLOWCHART 5 6 High Impedance Setting Processing The flowchart of high impedance setting processing is shown below Figure 5 6 High Impedance Setting Processing Setting high impedance High impedance High impedance setting requested setting
10. completion interrupt INTADO interrupt INTAD1 adO function ad1 function 66 Application Note U18600EJ1VOAN CHAPTER 5 FLOWCHART 5 9 sin2 Calculation Processing This function executes sin calculation by Taylor s expansion The following flowchart illustrates the sin2 calculation processing Figure 5 9 sin2 Calculation Processing Masks argument with maximum value 1st quadrant Yes 1st quadrant calculation RET answer 2nd quadrant Yes 2nd quadrant calculation RET answer 3rd quadrant Yes RET answer sins 4th quadrant calculation RET answer E sins E Refer to Figure 5 10 sins Calculation Processing a sins E Refer to Figure 5 10 sins Calculation Processing E 3rd g a rent calculation H Refer to Figure 5 10 sins Calculation Processing Refer to Figure 5 10 sins Calculation Processing Application Note U18600EJ1VOAN 67 CHAPTER 5 FLOWCHART 5 10 sins Calculation Processing This function executes sins calculation by Taylor s expansion It is called by sin2 The following flowchart illustrates the sins calculation processing Figure 5 10 sins Calculation Processing Local variable declaration Calculation 0 to 44 0 to 44 calculation 45 to 89 calculation 68 Application Note U18600EJ1VOAN CHAPTER 6 SETTINGS 6 1 Settings of 3 Phase PWM Driver The settings of the 3
11. fxx 8 fxx 16 fxx 32 fxx 64 fxx 128 A D converters 0 1 Remark fxx Analog input Total of two circuits 8 ch A D converter 0 4 ch A D converter 1 4 ch Total of two circuits 6 ch A D converter 0 2 ch A D converter 1 4 ch Total of two circuits 8 ch A D converter 0 4 ch A D converter 1 4 ch Operational amplifier for input level amplification Total of two circuits 6 ch A D converter 0 3 ch A D converter 1 3 ch Total of two circuits 5ch A D converter 0 2 ch A D converter 1 3 ch None Overvoltage detection comparator Total of two circuits 6 ch A D converter 0 3 ch A D converter 1 3 ch Total of two circuits 5ch A D converter 0 2 ch A D converter 1 3 ch AVopo AVppt AVrero AVREF1 Alternate function pin Peripheral clock frequency Alternate function pin Application Note U18600EJ1VOAN Independent pin Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents related to V850E IA3 V850E IA4 V850ES IK1 and V850ES IE2 Document Name Document No V850E1 Architecture User s Manual U14559E V850E IA3 V850E IA4 Hardware User s Manual U16543E V850ES Architecture User s Manual U15943E V850ES IK1 Hardware User s Manual U16910E V850ES IE2 Hardware User s Manual U17716E Inverter Control by
12. momo nan nana 11 Tel Operation nanang nan Naa hn mahoni an nan 11 1 2 System Configuration ooooooo o o oo oo nan ana 11 L CPU BOCK epu TCI 12 1 3 1 Memory MTM 12 1 3 2 PIN ASSIQHIMOG Mb M a 13 1 3 3 On hipperiphera AOA Ae rm fh diee a E E RR TR BAR 16 CHAPTER 2 CONTROL METHOD ooo oo mom momo nan an nan nana 18 2 1 Control BIO Kon tee Ne iii 18 2 2 3 Phase Voltage CONVeFSION oooooo oo oo an naa 19 2 3 Register Seting DE 20 CHAPTER 3 PROGRAM CONFIGURATION oo Wo om nan anna 50 31 Configuration of 3 Phase PWM Driver oo oom anna 50 CN OR 51 3 8 Definitions of Constants 1e enne eiie EE eese EE 53 3 4 Setting Dead TIME ea See Eesen ana 54 3 5 Determining PWM PUIS oom en in inne sain nns inse nns ena 54 3 6 JA D Gonversion aa T Ee 56 3 6 1 Conversion start trigger timing of A D converters 0 and 1 for synchronization operation 56 3 6 2 A D conversion completion me 57 TEE lee uc na ema nan am mh an hn 58 CHAPTER A FILE CONFIGURATION oo om oom oma nan natn nnne snas nana 60 41 File Configuration err erento EEN an ma ENEE SE 60 4 2 Explanation of Source Files oom anna REENEN en 61 CHAPTER 5 FLOWCHART sae ana naa anna ilang laman nba 62 5 1 Initialization Processing o oo oo nenen ena 62 5 2 Global Variable Processing COMMON C Woo om anna 62 5 3 Global Variable Processing Common h o oo oo
13. phase PWM driver are shown below Table 6 1 Settings of 3 Phase PWM Driver Parameter Set Value Operating clock of microcontroller 64 MHz input clock 8 MHz PWM output pin TOQOT1 to TOQOT3 TOQOB1 to TOQOB3 Carrier frequency 20 kHz Culling rate 1 1 Dead time 4 us A D conversion start trigger timing of ANIOO 1 us after TMQO valley interrupt INTTQOOV of carrier period A D conversion start trigger timing of ANI10 1 us after TMQO valley interrupt INTTQOOV of carrier period A D conversion completion time of ANIOO 1 94 us A D conversion completion time of ANI10 1 94 us Priority level of A DO conversion completion interrupt INTADO of ANIOO Level 4 Priority level of A D1 conversion completion interrupt INTAD1 of ANI10 Level 4 Buffer mode of A D converters 0 and 1 1 buffer mode Synchronization operation Performed Application Note U18600EJ1VOAN 69 APPENDIX A INTERFACE BETWEEN MODULES The following table shows the interfaces between the modules of the 3 phase PWM driver Table A 1 Interfaces Between Modules of 3 phase PWM Driver 1 2 Transmission Interface Module Mode setting Explanation For setting 3 phase PWM mode 0x00 Direct mode 0x01 dq conversion mode 0x02 Output lock mode Output enable pwm flag Enables PWM output 0x00 Changes mode of PWM output pin to high impedance mode 0x01 Changes mode of
14. phase u signed int Holds duty ratio of phase U 0 to 800 bk_phase_v signed int Holds duty ratio of phase V 0 to 800 bk_phase_w signed int Holds duty ratio of phase W 0 to 800 test_pwm_mode unsigned char For debugging usually commented out 0 Direct mode 1 dq conversion mode 2 Output lock mode test_pwm_flag unsigned char For debugging usually commented out 0 PWM output disabled 1 PWM output enabled test_valueO signed int For debugging usually commented out In direct mode 0 to 800 In dq conversion mode 400 to 400 test valuel signed int For debugging usually commented out In direct mode 0 to 800 In dg conversion mode 400 to 400 test value2 signed int For debugging usually commented out Application Note U18600EJ1VOAN In direct mode 0 to 800 In dg conversion mode 400 to 400 51 52 CHAPTER 3 PROGRAM CONFIGURATION Explanation of global variables 1 2 3 4 5 6 7 8 9 bk_hi_z This variable holds the status of the PWM output pin when the 3 phase PWM driver was previously driven bk_phase_u This variable holds the set value of the TQOCCR1 register U phase duty ratio when the 3 phase PWM driver was previously driven in the output lock mode bk_phase_v This variable holds the set value of the TQOCCR2 register V phase duty ratio when the 3 phase P
15. result Maximum value 0x3fff Minimum value 0xffffc001 Passes x value for sins calculation processing 0 to 2 499 sinanswer Returns sins calculation result Maximum value Ox3fff Minimum value 0xffffc001 Remark B Byte type W Word type LW Local word type Application Note U18600EJ1VOAN 71 For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0 511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 M nchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691 133 Succursale Francaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 3067 5800 Sucursal en Espana Juan Esplandiu 15 28007 Madrid Spain Tel 091 504 2787 Tyskland Filial Taby Centrum Entrance S 7th floor 18322 Taby Sweden Tel 08 638 72 00 F
16. 04H OSTS Address FFFFF6COH After reset Bit name Set value Selection of oscillation stabilization time fx 8 MHz 214 fx 2 05 ms Caution Be sure to set bits 4 to 7 to 0 8 Clock monitor mode register CLM Set the CLM register as follows CLM register 00H CLM Address FFFFF870H After reset Bit name Set value CLME Clock monitor operation control 0 Clock monitor operation disabled Caution The CLM register is a special register Data can be written to this register only in a combination of specific sequences For details refer to 3 4 8 Special registers in the V850E IA3 V850E IA4 Hardware User s Manual U16543E Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 9 Port 1 mode control register PMC1 Set the PMC1 register as follows PMC1 register 3FH PMC1 After reset Bit name Set value 24 Address FFFFF442H PMC17 Specification of operating mode of P17 pin 0 O port PMC16 Specification of operating mode of P16 pin 0 UO port PMC15 Specification of operating mode of P15 pin TO OB3 output TRGQO input PMC14 Specification of operating mode of P14 pin TOQOTS output EVTQO input PMC13 Specification of operating mode of P13 pin TOQOB2 output TIQOO input PMC12 Specification of operating mode of P12 pin TOQOT2 output TIQ0O3 input TOQOS output PMC11 Specification of operating m
17. 0E IA3 V850ES IK1 and V850ES IE2 2 Download the sample program used in this Application Note from the NEC Electronics Website http www necel com 3 When using sample programs reference the following startup module and link directive file and adjust them if necessary e Startup module ia4crt s e Link directive file ia4pwm dir 4 This sample program is provided for reference purposes only and operations are therefore not subject to guarantee by NEC Electronics Corporation When using sample programs customers are advised to sufficiently evaluate this product based on their systems before use Target Readers This Application Note is intended for users who understand the functions of the V850E IA3 V850E IA4 V850ES IK1 and V850ES IE2 and who design application systems that use these microcontrollers The applicable products are shown below e V850E IA3 UPD703183 70F3184 e V850E IA4 UPD703185 703186 70F3186 e V850ES IK1 UPD703327 703329 70F3329 e V850ES IE2 UPD70F3713 70F3714 Purpose This Application Note explains for your reference how to set a 6 phase PWM output Organization mode and A D conversion starting trigger timing using 16 bit timer event counter QO TMQO timer QO option TMQOPO 16 bit timer event counter PO TMPO and A D converters 0 and 1 which are necessary for inverter control of a 3 phase motor by the V850E IA3 V850E IA4 V850ES IK1 or V850ES IE2 This Application Note is divided into the follow
18. 1VOAN These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of March 2007 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconducto
19. 5 VDC debugging PWM signal 6 Motor drive current IGBT driver Note Output port signal for debugging q 2 UI Q io ag ug 212 eo v 25 N Q A E Note Used only for debugging Not used for any other purpose Application Note U18600EJ1VOAN 11 CHAPTER 1 HARDWARE CONFIGURATION 1 3 CPU Block The 3 phase PWM driver inputs an 8 MHz clock to the V850E IA4 uPD70F3186GC 8EU A and operates at 64 MHz by multiplying the clock by eight The internal RAM size of the V850E IA4 uPD70F3186GC 8bEU A can be changed between 6 KB and 12 KB Set the internal RAM size to 12 KB for the 3 phase PWM driver 1 3 1 Memory map The memory map is shown below Figure 1 2 Memory Map xFFFFFFFH On chip peripheral UO area FFFFO00H Aun 3 URN xFFFDAOCH x xFFFD80CH SV xFFFD800H P i xFFFC004H xFFFCOO0H xFFFCO00H xFFFBFFFH Access prohibited X0040000H X003FFFFH Internal ROM area X0000000H 12 Application Note U18600EJ1VOAN CHAPTER 1 HARDWARE CONFIGURATION 1 3 2 Pin assignment Pin assignments of the V850E IA4 uPD70F3186GC 8EU A are shown below Pin Name ANIOO Table 1 1 V850E IA4 uPD70F3186GC 8EU A Pin Assignment 1 3 UO Mode Setting Signal Name Motor drive current for A D converter 0 Active Level Oto 45V ANIO1 ANIO2 AINOS P70 P71 P72 P73 Unused Kelte Me W SSEN AJOJN Avon Positive pow
20. AN CHAPTER 2 CONTROL METHOD 31 TMQO option register 2 TAOOPT2 Set the TQOOPT2 register as follows TQOOPT2 register 84H TQOOPT2 Address FFFFF5E1H 1 After reset 0 0 0 0 0 0 0 Bit name TQORDE TQODTM TQOATMO3TQOATMO2 TQOATOS TQOATO2 TQOATO1 Set value 1 0 0 0 0 1 0 TQORDE Transfer culling enable Culls transfer at the same interval as interrupt culling set by the TQnOPT1 register TQODTM Dead time counter operation mode selection m 1 to 3 Dead time counter counts up normally and if TOQOm output of TMQO is at a narrow interval TOQOm output width dead time width the dead time counter is cleared and counts up again TQOATMO3 TQOATMOS3 mode selection Outputs A D trigger signal TQTADTOO for INTTPOCCH interrupt while dead time counter is counting up TQOATMO2 TQOATMO 2 mode selection Outputs A D trigger signal TQTADTOO for INTTPOCCO interrupt while dead time counter is counting up TAOATO3 A D trigger output control 3 0 Disables output of A D trigger signal TQTADTOO for INTTPOCC1 interrupt TQOATO2 A D trigger output control 2 Enables output of A D trigger signal TQTADTOO for INTTPOCCO interrupt TQOATO1 A D trigger output control 1 Disables output of A D trigger signal TQTADTOO for INTTQOCCO crest interrupt TQOATOO A D trigger output control 0 Disables output of A D trigger signal TQTADTOO for INTTQOOV valley interrupt Application Note U18600EJ1
21. Bit name Set value Compare register value setting 800 counts 28 TMQO capture compare register 2 TQOCCR2 Set the TQOCCR2 register as follows TQOCCR2 register 0320H TQOCCR2 Address FFFFF5CAH 2 1 0 After reset Bit name Set value Compare register value setting 800 counts Application Note U18600EJ1VOAN 35 CHAPTER 2 CONTROL METHOD 29 TMQO capture compare register 3 TAOCCR3 Set the TQOCCRS register as follows TQOCCRG3 register 0320H TQOCCR3 Address FFFFF5CCH 2 1 0 After reset Bit name Set value Compare register value setting 800 counts 30 TMQO option register 1 TQOOPT1 Set the TQOOPT1 register as follows TQOOPT1 register 40H TQOOPT1 Address FFFFF5E0H 1 0 After reset 0 0 0 0 0 0 0 Bit name TQOICE TQOIOE TQOID4 TQOID3 TQOID2 TQOID1 TQOIDO Set value 0 1 0 0 0 0 0 TQOICE Crest interrupt INTTQOCCO signal enable 0 Do not use INTTQOCCO signal do not use it as count signal for interrupt culling TQOIOE Valley interrupt INTTQOOV signal enable 1 Use INTTQOOV signal use it as count signal for interrupt culling TQOID4 TQOID3 TQOID2 TQOID1 TQOIDO Number of times of interrupt ojojo 0 0 Not culled all interrupts are output 36 Application Note U18600EJ1VO
22. Bit name Set value Control of on chip pull up resistor connection n 0 to 7 0 No connection 12 TMPO control register 0 TPOCTLO Set the TPOCTLO register as follows TPOCTLO register OOH TPOCTLO Address FFFFF640H 1 After reset 0 0 Bit name TPOCKS2 TPOCKS1 Set value 0 0 TMPO operation control TMPO operation disabled TMPO reset asynchronously TPOCKS2 TPOCKS1 TPOCKSO Internal count clock selection o o jm Note The TPOOPTO TPOOVF bit and 16 bit counter are reset simultaneously Moreover timer outputs TOPOO TOPO1 TOP21 and TOP31 pins are reset to the TPOIOCO register set status at the same time as the 16 bit counter Caution Be sure to set bits 3 to 6 to 0 26 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 13 TMPO control register 1 TPOCTL1 Set the TPOCTL1 register as follows TPOCTL1 register 85H TPOCTL1 After reset Bit name Set value Address FFFFF641H 1 0 TPOMD1 TPOEST Software trigger control 0 No software trigger operation TPOEEE Count clock selection Disables operation with external event count input TIPOO pin Performs counting with the count clock selected by the TPOCTLO TPOCKSO to TPOCTLO TPOCKS 2 bits Caution Be sure to set bits 3 and 4 to 0 Application Note U18600EJ1VOAN 27 CHAPTER 2 CONTROL METHOD 14 TMPO I O control regis
23. C After reset Bit name Set value Wait for bus access to the on chip peripheral I O register 4 waits in 64 MHz operation Caution Set the VSWC register by using the startup module ia4crt s 2 Internal memory size switching register IMS Set the IMS register as follows IMS register 01H IMS Address FFFFF9FOH After reset Bit name Set value Specification of internal RAM size 1 12 KB FFFCOOOH to FFFEFFFH Caution Set the IMS register by using the startup module ia4crt s 20 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 3 PLL control register PLLCTL Set the PLLCTL register as follows PLLCTL register 03H PLLCTL After reset Bit name Set value Address FFFFF82CH 1 0 SELPLL 1 SELPLL CPU operation clock selection 1 PLL mode Caution Be sure to set bits 7 to 2 to 0 and set bit 0 to 1 4 Processor clock control register PCC Set the PCC register as follows PCC register 00H PCC After reset Bit name Set value Address FFFFF828H Clock selection fcuk fceu Cautions 1 The PCC register is a special register Data can be written to this register only in a combination of specific sequences For details refer to 3 4 8 Special registers in the V850E IA3 V850E IA4 Hardware User s Manual U16543E Be sure to set bits 2 to 7 to
24. Input Input Input Input Input Input Input Input Unused Input output in debugging Input output in debugging Output port for debugging H in debugging H in debugging Positive power supply for internal unit 2 5 V Ground potential for internal unit GND Input output in debugging Input output in debugging Input output in debugging Input output in debugging Input output in debugging Input output in debugging Output port for debugging H in debugging H in debugging H in debugging H in debugging H in debugging H in debugging Ground potential for external pin GND Positive power supply for external pin 5 V Input output in debugging Input output in debugging Input output in debugging Input output in debugging Input output in debugging Remark L low level H high level 14 Input output in debugging Input output in debugging Output port for debugging Application Note U18600EJ1VOAN H in debugging H in debugging H in debugging H in debugging H in debugging H in debugging H in debugging CHAPTER 1 HARDWARE CONFIGURATI
25. ON Table 1 1 V850E IA4 y PD70F3186GC 8bEU A Pin Assignment 3 3 Pin Name UO Mode Setting Signal Name Active Level Input output in debugging Output port for debugging H in debugging Input Debug data input for on chip debug L emulator used only in debugging Input Debug clock input for on chip debug emulator used only in debugging Input Debug mode select for on chip debug emulator used only in debugging Vss Ground potential for internal unit Von Positive power supply for internal unit FLMDO Input Flash memory programming mode setting pin TOQOT1 Output U phase output TOQOB1 Output U phase output TOQOT2 Output V phase output EVss Ground potential for external pin EVop Positive power supply for external pin TOQOB2 Output V phase output TO OT3 Output W phase output TOQOB3 Output W phase output P16 Input Unused P17 Input DDO Output Debug data output for on chip debug emulator used only in debugging DRST Input Debug reset input for on chip debug emulator used only in debugging PLLSIN Input Output frequency select signal input in PLL mode Remark L low level H high level Application Note U18600EJ1VOAN 15 CHAPTER 1 HARDWARE CONFIGURATION 1 3 3 On chip peripheral I O The following peripheral I Os are used in the 3 phase PWM driver Table 1 2 On Chip Peripheral I Os Used On Chip Peripheral I O Function Name
26. PWM output pin to PWM output mode value0 Control value 0 In direct mode U phase duty 0 to 800 In dq conversion mode d axis current 400 to 400 value1 Control value 1 In direct mode V phase duty 0 to 800 In dq conversion mode q axis current 400 to 400 value2 Control value 2 In direct mode W phase duty 0 to 800 In dq conversion mode Rotor rotation position 0 to 9 999 Reception Module Remark B Byte type W Word type LW Local word type Passes x value of sin2 calculation processing 0 to 9 999 70 Application Note U18600EJ1VOAN APPENDIX A INTERFACE BETWEEN MODULES Table A 1 Interfaces Between Modules of 3 phase PWM Driver 2 2 Transmission Interface Explanation Reception Module Module pt unit status pwm output Passes status after pwm processing 0x00 to 0x03 Oxff Return value from hi z function Passes x value of sin2 calculation processing 0 to 9 999 High impedance Enables high impedance mode mode setting 0x00 High impedance mode 0x01 Cancels high impedance mode hi_z flag High impedance mode setting change flag 0x00 High impedance state is not changed 0x01 Changing high impedance state is enabled High impedance hi_z output Passes status after high impedance processing state 0x00 High impedance state 0x01 Cancels high impedance state 0x02 None 0x03 Other mode sin2answer sin2 output Returns sin2 calculation
27. Processing and Figure 5 10 sins Calculation Processing Remark A program must be developed by the user 50 Application Note U18600EJ1VOAN CHAPTER 3 PROGRAM CONFIGURATION Figure 3 1 3 Phase PWM Driver Configuration 2 2 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt KIS 8 Mode identification Holding PWM 3 phase voltage conversion Direct output High impedance setting sin calculation processing A D converters 0 and 1 conversion completion processing Interrupt servicing that occurs after completion TMOO valley interrupt INTTQOOV processing Identifies the operation mode of the 3 phase PWM driver Sets in the output lock mode the PWM duty ratio previously set by the 3 phase PWM driver Performs 3 phase voltage conversion in the dq conversion mode Individually sets values of phases U V and W Switches the port state of the U U V V W and W phase pins between the high impedance state and PWM output state sin calculation by Taylor s expansion Called by 3 of conversion by A D converters 0 and 1 TMOO valley interrupt INTTQOOV processing Used for debugging 3 2 Global Variables The global variables used for the 3 phase PWM driver are listed below unsigned char Table 3 1 Global Variables Set Value 0 PWM output pin is in a high impedance state Flag holding high impedance state 1 PWM output pin is ready for PWM output bk
28. To our customers Old Company Name in Catalogs and Other Documents On April 17 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is g
29. V850 Series Vector Control by Hole Sensor Application Note U17338E Inverter Control by V850 Series Vector Control by Encoder Application Note U17324E Inverter Control by V850 Series 120 Excitation Method Control by Zero Cross Detection Application Note U17209E Manual for Using Sample Program Functions Note Serial Communication VARTA Application U18233E Manual for Using Sample Program Functions Note Serial Communication CSIB Application U18234E Manual for Using Sample Program Functions DMA Functions Application Note U18235E Manual for Using Sample Program Functions Timer M Application Note U18236E Manual for Using Sample Program Functions Watchdog Timer Application Note U18237E Manual for Using Sample Program Functions Timer P Application Note U18238E Manual for Using Sample Program Functions Timer Q Application Note U18239E Manual for Using Sample Program Functions Timer ENC Application Note U18240E Manual for Using Sample Program Functions Port Functions Application Note U18241E Manual for Using Sample Program Functions Clock Generator Application Note U18242E Manual for Using Sample Program Functions Standby Function Application Note U18243E Manual for Using Sample Program Functions Interrupt Functions Application Note U18244E Manual for Using Sample Program Functions A D Converters 0 and 1 A
30. VOAN 37 CHAPTER 2 CONTROL METHOD 32 TMQO option register 3 TAOOPT3 Set the TQOOPTS register as follows TQOOPTS register OOH TQOOPT3 Address FFFFF5E3H 1 After reset 0 0 0 0 0 Bit name TQOATM13 TQOATM12 TQOAT13 TQOAT12 TQOAT11 Set value 0 0 0 0 0 TQOATM13 TQOATM13 mode selection Outputs A D trigger signal TQTADTO1 of INTTPOCC1 interrupt while dead time counter is counting up TQOATM12 TQOATM12 mode selection Outputs A D trigger signal TQTADT01 of INTTPOCCO interrupt while dead time counter is counting up TQOAT13 A D trigger output control 3 Disables output of A D trigger signal TQTADTO1 for INTTPOCC1 interrupt TQOAT12 A D trigger output control 2 Disables output of A D trigger signal TQTADTO1 for INTTPOCCO interrupt TQOAT11 A D trigger output control 1 Disables output of A D trigger signal TQTADTO 1 for INTTQOCCO interrupt crest interrupt TQOAT10 A D trigger output control 0 Disables output of A D trigger signal TQTADTO1 for INTTQOOV interrupt valley interrupt 38 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 33 TMAO I O control register 3 TAOIOC3 Set the TAOIOC3 register as follows TQOIOC3 register FCH TQOIOCS3 Address FFFFF5E2H After reset 1 0 1 0 1 0 Du name TQOOLB3TQOOEB3 TQOOLB2ITQOOEB2 TQOOLB1 TQOOEB1 Set value 1 1 1 1 1 1 TQOOLBm Setting of TOQOBm pin output level m 1 to 3 1 En
31. WM driver was previously driven in the output lock mode bk_phase_w This variable holds the set value of the TQOCCR3 register W phase duty ratio when the 3 phase PWM driver was previously driven in the output lock mode test pwm mode This variable is a RAM area that is used for debugging the 3 phase PWM driver It specifies pwm mode to the pwm function in the tmp zero function It is usually commented out test pwm flag This variable is a RAM area that is used for debugging the 3 phase PWM driver It specifies pwm flag to the pwm function in the tmp zero function It is usually commented out test valueO This variable is a RAM area that is used for debugging the 3 phase PWM driver It specifies pwm valueO to the pwm function in the tmp zero function It is usually commented out test value1 This variable is a RAM area that is used for debugging the 3 phase PWM driver It specifies pwm value1 to the pwm function in the tmp zero function It is usually commented out test value2 This variable is a RAM area that is used for debugging the 3 phase PWM driver It specifies pwm value2 to the pwm function in the tmp zero function It is usually commented out Application Note U18600EJ1VOAN CHAPTER 3 PROGRAM CONFIGURATION 3 3 Definitions of Constants The constants used for the 3 phase PWM driver are listed in the following table MAXPULSE Resolution of motor rotation angle Table 3 2 Constants Constant SGETA s
32. ables inversion of output of TOQOBm pin TQOOEBm Setting of TOQOBm pin output Enables TOQOBm pin output 34 TMQO dead time compare register TQODTC Set the TQODTC register as follows TQODTC register 0080H TQODTC Address FFFFF5E4H 2 1 After reset TQO TQO TQO TO0 DTC8DTC7 DTC5 DTC3 0 1 0 0 Bit name Set value Dead time value specification Application Note U18600EJ1VOAN 39 CHAPTER 2 CONTROL METHOD 35 High impedance output control register 00 HZAOCTLO Set the HZAOCTLO register as follows HZAOCTLO register 80H 88H HZAOCTLO Address FFFFF5FOH 0 After reset 0 0 0 0 0 0 0 Bit name HZAODCEO HZAODCMO HZAODCNO HZAODCPO HZAODCTO HZAODCCO HZAODCFO Set value 1 0 0 0 0 1 0 0 HZAODCEO High impedance output control 1 Enables high impedance output control operation HZAODCMO Condition of clearing high impedance state by HZAODCCO bit 0 Setting of the HZAODCCO bit is valid regardless of the TOQOOFF pin input TOQOOFF pin input edge specification No valid edge setting the HZAODCFO bit by TOQOOFF pin input is prohibited HZAODCTO High impedance output trigger bit 0 No operation Pins are made to go into a high impedance state by software and the HZAODCFA bit is set to 1 HZAODCCO High impedance output control clear bit 0 No operation HZAODCFO High impedance output status flag 0 Indicates tha
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34. change flag OFF Normal operation High impedance High impedance cancellation setting processing 0 processing 1 Normal operation High impedance setting High impedance Canceling high change flag OFF canceled impedance requested Application Note U18600EJ1VOAN 65 CHAPTER 5 FLOWCHART 5 7 TMO Valley Interrupt INTTQOOV Servicing This processing is performed when the TMO valley interrupt INTTQOOV of carrier period is generated It is used by the 3 phase PWM driver only for debugging and is not usually used Therefore program description is commented out When using the 3 phase PWM driver delete the program for debugging Note that the priority level of the TMQO valley interrupt INTTQOOV is 1 The following flowchart illustrates the TMQO valley interrupt INTTQOOV servicing Figure 5 7 MOO Valley Interrupt INTTQOOV Servicing TMQO valley interrupt INTTQOOV S Program for debugging usually commented out 5 8 A D Converters 0 and 1 Conversion Completion Processing This function is called after conversion by A D converters O and 1 is completed The 3 phase PWM driver programs nothing in the function The priority level of the A Dn conversion completion interrupt INTADn is 4 n 0 or 1 The following flowchart illustrates the A D converters 0 and 1 conversion completion processing Figure 5 8 A D Converters 0 and 1 Conversion Completion Processing A DO conversion completion A D1 conversion
35. e detection capture operation invalid 24 TMAO I O control register 2 TAOIOC2 Set the TQOIOC2 register as follows TQOIOC2 register OOH TQOIOC2 After reset Bit name Set value 0 0 Address FFFFF5CAH 1 0 TQOEES1 TQOEESO TQOETS1 TQOEES1 TQOETS1 TQOEESO TQOETSO 0 0 0 External event count input signal EVTQO pin valid edge setting 0 0 No edge detection external event count invalid External trigger input signal TRGQO pin valid edge setting 0 0 No edge detection external trigger invalid Application Note U18600EJ1VOAN 33 CHAPTER 2 CONTROL METHOD 25 TMQO option register 0 TQOOPTO Set the TQOOPTO register as follows TQOOPTO register OOH TQOOPTO Address FFFFF5C5H 1 0 After reset 0 0 Bit name TQOCUF TQOOVF Set value Caution Be sure to set bit 3 to 0 26 TMQO capture compare register 0 TAOCCRO Set the TQOCCRO register as follows TQOCCRO register 031FH TQOCCRO Address FFFFF5C6H 2 1 0 After reset Bit name Set value Compare register value setting 50 us 799 counts 34 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 27 TMQO capture compare register 1 TQOCCR1 Set the TAOCCRI register as follows TQOCCR1 register 0320H TQOCCRI1 Address FFFFF5C8H 2 1 0 After reset
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37. een the V850E IA4 and the V850E IA3 V850ES IK1 and V850ES IE2 related to 16 bit timer event counter Q TMQ timer Q option TMQOP 16 bit timer event counter P TMP and A D converters 0 and 1 are shown below TOQ10 pin V850E IA4 Available V850E IA3 None V850ES IE2 V850ES IK1 Available TRGQO pin Available Available None TOQHO01 to TOQHO3 pins None None Available TO OO pin TOQOO TOQOO TOQO0 CLMER Count clock fxx 2 fxx 4 fxx 8 fxx 16 fxx 32 fxx 64 fxx 128 fxx 256 fxx 2 fxx 4 fxx 8 fxx 16 fxx 32 fxx 64 fxx 128 fxx 256 fxx fxx 2 fxx 4 fxx 8 fxx 16 fxx 32 fxx 64 fxx 128 TOQOT1 to TOQOTS pins Available Available None TOQOB1 to TOQOB3 pins Available Available None TOQI1T1 to TO 1T3 pins Available None Available TOQ1B1 to TOQ1B3 pins Available None Available TOQOOFF Available Available None TOQ1OFF Available None Available TOPSOFF Available None Available TOQHOOFF None None Available Forced output stop function at overvoltage detection by comparator function of A D converter block Available Available None TOP31 pin Available None Available Count clock fxx 2 fxx 4 fxx 8 fxx 16 fxx 32 fxx 64 fxx 128 fxx 256 fxx 2 fxx 4 fxx 8 fxx 16 fxx 32 fxx 64 fxx 128 fxx 256 fxx fxx 2 fxx 4
38. ending on the driving motor used so the driver should be designed by users 18 Application Note U18600EJ1VOAN 1 2 3 4 CHAPTER 2 CONTROL METHOD Mode identification Mode of the 3 phase PWM driver can be identified in accordance with the software state Modes of the 3 phase PWM driver are as follows e Direct mode PWM duty ratio set by valueO to value2 is used as the PWM voltage e dq conversion mode PWM voltage is determined by d axis voltage q axis voltage and rotation position 6 e Output lock mode PWM voltage previously set by the 3 phase PWM driver is output 3 phase voltage conversion Coordinate transformation processing is performed in the dq conversion mode Retention PWM PWM voltage previously set by the 3 phase PWM driver is retained PWM setting PWM voltage is calculated and output to registers of the V850E IA4 uPD70F3186GC 8EU A 2 2 3 Phase Voltage Conversion The following shows the formula to convert the dq axes voltage into the 3 phase coordinate Phase U voltage d axis voltage x sin 90 q axis voltage x sin 6 Phase V voltage d axis voltage x sin 330 q axis voltage x sin 240 Phase W voltage Phase U voltage Phase V voltage Application Note U18600EJ1VOAN 19 CHAPTER 2 CONTROL METHOD 2 3 Register Settings 1 System wait control register VSWC Set the VSWC register as follows VSWC register 13H Address FFFFFO6EH VSW
39. er supply for A D converters 0 to 2 E o AVss Ground potential for A D converters 0 to 2 CMPREF Unused E N AVss Ground potential for A D converters 0 to 2 E wo Avon Positive power supply for A D converters 0 to 2 A A P74 E oa P75 E o P76 N P77 Unused E ANI10 Motor drive current for A D converter 1 Oto 5 V E o ANI11 N o ANI12 MN pre ANI13 N N POO N LA P01 N Ka P02 M oa P03 N o P04 N P05 N P06 N Ke Unused CO o Positive power supply for internal unit w A Ground potential for internal unit CA N CA C ken E CA oa CO o wo Ly Unused Co Positive power supply for external pin CO o Ground potential for external pin Application Note U18600EJ1VOAN 13 Pin Name CHAPTER 1 HARDWARE CONFIGURATION UO Mode Setting Signal Name Table 1 1 V850E IA4 yPD70F3186GC 8bEU A Pin Assignment 2 3 Active Level Power supply for oscillator and PLL System clock Ground potential for oscillator and PLL System reset input Unused Positive power supply for internal unit Ground potential for internal unit Input Input
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42. in jack up constant CARRIERPULSE Carrier frequency set value of TQOCCRO register Explanation of constants 1 2 3 MAXPULSE This constant indicates the resolution of the motor rotation angle and is used with the sin2 function It expresses 0 to 360 at a resolution of 10 000 SGETA This is a jack up constant for the sins function CARRIERPULSE This is a set value of carrier frequency The TMQO count clock period can be calculated by the expression below 2 TMQO count clock period rem XX Remark fxx Peripheral clock The carrier period can be calculated by this expression Carrier period Set value of TQOCCRO register 1 x 2 x TMQO count clock period Example Set value of carrier frequency where the carrier frequency is 20 kHz carrier period 50 ws and the peripheral clock fxx is 64 MHz Set value of TQOCCRO register Carrier period x fxx 2 x 2 1 50x64 4 1 3200 4 1 800 1 799 Therefore TQOCCRO CARRIERPULSE 799 Application Note U18600EJ1VOAN 53 CHAPTER 3 PROGRAM CONFIGURATION 3 4 Setting Dead Time The dead time is set by using the TQODTC register and is calculated by the following expression Dead time Set value of TQODTC register x TMQO count clock period Example Set value of the TQODTC register when the dead time is 4 ws and the peripheral clock fxx is 64 MHz TQODTC Dead time x fxx 2 24x64
43. ing sections e Hardware configuration e File configuration e Control method e Flowchart e Program configuration e Settings Application Note U18600EJ1VOAN 5 How to Use This Manual Conventions It is assumed that the reader of this Application Note has general knowledge in the fields of electrical engineering logic circuits and microcontrollers For details of hardware functions especially register functions setting methods etc and electrical specifications See the V850E IA3 V850E IA4 Hardware Users Manual V850ES IK1 Hardware User s Manual and V850ES IE2 Hardware User s Manual For details of instruction functions See the V850E1 Architecture User s Manual and V850ES Architecture User s Manual Data significance Higher digits on the left and lower digits on the right Active low representation xxx overscore over pin or signal name Memory map address Higher addresses on the top and lower addresses on the bottom Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefix indicating the power of 2 address space memory capacity K kilo 2 1 024 M mega 2 1 024 G giga 2 1 024 Data type Word 32 bits Halfword 16 bits Byte 8 bits Application Note U18600EJ1VOAN Product Differences The differences betw
44. its 1 to 3 and 7 to 0 Application Note U18600EJ1VOAN 43 CHAPTER 2 CONTROL METHOD 41 Operational amplifier n control register 1 OPnCTL1 Set the OPnCTL1 register as follows OPnCTL1 register OOH OPnCTL1 Address OPOCTL1 FFFFF261H OP1CTL1 FFFFF269H n 2 0 1 4 After reset 0 0 0 Bit name OPnCENZI OPnCENT1 OPnCENO Set value 0 0 0 OPnCEN2 Operation control of comparator 2 0 Disables operation OPnCEN1 Operation control of comparator 1 0 Disables operation OPnCENO Operation control of comparator 0 0 Disables operation OPnCMP Comparator output status 0 Comparator output 0 no overvoltage detection 44 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 42 Interrupt control register ADnIC Set the ADnIC register as follows ADnIC register 04H ADnIC Address ADOIC FFFFF180H AD1IC FFFFF182H 2 1 0 After reset 1 1 1 Bit name ADnPR2 ADnPR1 ADnPRO Set value 1 0 0 Interrupt request flagNete 0 Interrupt request not issued ADnMK Interrupt mask flag 0 Interrupt servicing enabled ADnPR2 ADnPR1 ADnPRO Interrupt priority specification bit Note The interrupt request flag is reset automatically by the hardware if an interrupt request signal is acknowledged 43 Interrupt control register TAOOVIC Set the TQOOVIC register as follows TQOOVIC register 01H TQOOVIC Address FFFFF124H 1 After reset 0 1 1 1
45. led Interrupt mask flag setting INTP7 interrupt servicing disabled Interrupt mask flag setting INTP6 interrupt servicing disabled Interrupt mask flag setting INTP5 interrupt servicing disabled 46 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD Interrupt mask flag setting INTP4 interrupt servicing disabled Interrupt mask flag setting INTP3 interrupt servicing disabled Interrupt mask flag setting INTP2 interrupt servicing disabled Interrupt mask flag setting INTP1 interrupt servicing disabled Interrupt mask flag setting INTPO interrupt servicing disabled 2 2 Application Note U18600EJ1VOAN 47 CHAPTER 2 CONTROL METHOD 45 Interrupt mask register 3 IMR3 Set the IMR3 register as follows IMR3 register FCFFH 1 2 Address IMR3 FFFFF106H IMR3 IMR3H IMR3L IMR3L FFFFF106H IMR3H FFFFF107H 7 6 5 4 3 2 1 After reset Bit name Set value Interrupt mask flag setting INTTMOEQO interrupt servicing disabled Interrupt mask flag setting INTAD2 interrupt servicing disabled Interrupt mask flag setting INTAD1 interrupt servicing enabled Interrupt mask flag setting INTADO interrupt servicing enabled CB1TMK Interrupt mask flag setting 1 INTCB1T interrupt servicing disabled CB1RMK Interrupt mask flag setting 1 INTCB1R interrupt servicing disabled CB1REMK Interrupt mask flag setting 1 INTCB1RE interrupt ser
46. library 2 libc a Standard library 3 ia4crt s Startup module of 3 phase PWM driver 4 ia4pwm dir Link directive file of 3 phase PWM driver Note libm a and libc a are libraries that are automatically allocated by the project manager when a project is generated 60 Application Note U18600EJ1VOAN CHAPTER 4 FILE CONFIGURATION 4 2 Explanation of Source Files Source File Name Function Name Explanation main MAIN processing Nothing is written in the main routine of the 3 phase PWM driver adO function Conversion completion processing of A D converter 0 adi function Conversion completion processing of A D converter 1 tmq_zero Interrupt servicing of carrier period pt_unit c pwm Driver that performs 3 phase PWM control hi_z Driver that controls the output pin for 3 phase PWM hinit Initializes the on chip peripheral I O of the V850E IA4 uPD70F3186GC 8EU A ainit Initializes the global variables used for the 3 phase PWM driver common c Defines constants and declares a global variable area sin2 c sin2 Executes sin calculation sins Executes sin calculation Application Note U18600EJ1VOAN 61 5 1 CHAPTER 5 FLOWCHART This chapter explains each processing of the 3 phase PWM driver by using flowcharts Initialization Processing The flowchart of the initialization processing is shown below Figure 5 1 Initialization Processing START
47. lication Note U18600EJ1VOAN 55 CHAPTER 3 PROGRAM CONFIGURATION 3 6 A D Conversion 3 6 1 Conversion start trigger timing of A D converters 0 and 1 for synchronization operation The 3 phase PWM driver implements a synchronization operation by using TMQ0 TMQOPO and TMPO Therefore any timing can be set for the conversion start trigger of A D converters 0 and 1 Because the timing of comparison match of TMPO during a synchronization operation is synchronized with the operating clock of TMQO it is calculated by using the TMQO count clock period The timing of the conversion start trigger of A D converters 0 and 1 can be calculated by the following expression Conversion start trigger timing of A D converter n TPOCCRn x TMQO count clock period Remark n 0Oor 1 Example TMPO comparison match timing where the timing of the conversion start trigger of A D converter n is 1 us after the TMQO valley interrupt INTTQOOV of carrier period and the peripheral clock fxx is 64 MHz Set value of TPOCCRn register Conversion start trigger timing of A D converter n x fxx 2 1x64 2 32 Figure 3 3 Conversion Start Trigger Source of A D Converters 0 and 1 of 3 Phase PWM Driver Trigger is generated 1 us after generation of valley interrupt A D converter 0 INTTQOOV Timer TMQO TMQOPO TMPO TATADTOO TTRGOO TATADTO1 A D converter 1 Trigger is generated 1 us after generation of valley interrup
48. mode W phase output width Set this value in a range of 0 to 800 CARRIERPULSE 1 Executes 3 phase voltage conversion used for vector calculation This value is equivalent to the rotation coordinate 6 This value is set in a range of 0 to MAXPULSE 1 None This argument is not used in the output lock mode Note The PWM pulse duty ratio may exceed 10096 in the dq conversion mode depending on the d and q axes and the rotation coordinate 0 Therefore thoroughly evaluate the values of value0 value1 and value2 Application Note U18600EJ1VOAN 59 CHAPTER 4 FILE CONFIGURATION This chapter explains the file configuration of the 3 phase PWM driver 4 1 File Configuration The 3 phase PWM driver consists of the following 10 files 1 Source files 1 main c MAIN processing 2 pt unit c 3 phase PWM driver file 3 init c Initialization processing lt 4 gt common c Definitions of constants and global variable declaration 5 sin2 c sin calculation processing 2 Include file common h This is a header file that allows other files to access the global variables defined by common c by using the EXTERN instruction Read this header file to use definitions of constants and global variables with the other file by dividing the file If definitions of constants or a global variable is used the user should define both the common c and common h files 3 Project related files Note 1 libm a Mathematic
49. n valid edge setting 0 0 No edge detection external event count invalid TPOETS1 TPOETSO External trigger input signal TIPOO pin valid edge setting 0 0 No edge detection external trigger invalid Application Note U18600EJ1VOAN 29 CHAPTER 2 CONTROL METHOD 17 TMPO option register 0 TPOOPTO Set the TPOOPTO register as follows TPOOPTO register 00H TPOOPTO Address FFFFF645H 0 After reset 0 0 0 Bit name TPOCCS1 TPOCCSO TPOOVF Set value 0 0 0 TPOCCS1 TPOCCR1 register capture compare selection 0 Compare register selected TPOCCSO TPOCCRO register capture compare selection 0 Compare register selected TPOOVF TMPO overflow detection flag Reset 0 0 written to TPnOVF bit or TPOCTLO TPOCE bit 0 Caution Be sure to set bits 1 to 3 6 and 7 to 0 18 TMPO capture compare register 0 TPOCCRO Set the TPOCCRO register as follows TPOCCRO register 0020H TPOCCRO Address FFFFF646H 2 1 0 After reset Bit name Set value Compare register value setting TMPO A D converter 0 conversion start trigger value setting compare match occurs 1 us later 30 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 19 TMPO capture compare register 1 TPOCCR1 Set the TPOCCRI register as follows TPOCCRI register 0020H TPOCCR1 Address FFFFF648H 2 1 0 After reset Bit name Set value
50. nics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Application Note 434 NESAS Inverter Control by V850 Microcontrollers 6 Phase PWM Output Control by Timer Q Timer Q Option Timer P A D Converters 0 and 1 V850E IA3 V850E IA4 V850ES IK1 V850ES IE2 Document No U18600EJ1VOANOO 1st edition Date Published April 2007 N CP K NEC Electronics Corporation 2007 Printed in Japan MEMO 2 Application Note U18600EJ1VOAN NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vi MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bi
51. ode of P11 pin TOQOB1 output TIAO2 input TOQ02 output PMC10 Specification of operating mode of P10 pin TOQOT1 output TIQO1 input TOQO 1 output Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 10 Port 1 function control register PFC1 port 1 function control expansion register PFCE1 Set the PFC1 and PFCE1 registers as follows PFC1 register COH PFCE1 register 00H PFCE1 After reset Bit name Set value PFC1 After reset Bit name Set value 0 Address FFFFF702H 1 0 0 0 PFCE12 PFCE11 PFCE10 0 0 0 Address FFFFF462H PFC17 Specification of alternate function of P17 pin TIP21 input PFC16 Specification of alternate function of P16 pin TIP20 input PFC15 Specification of alternate function of P15 pin 0 TOQOBS3 output PFC14 Specification of alternate function of P14 pin 0 TOQOTS output PFC13 Specification of alternate function of P13 pin 0 TOQOB2 output PFCE12 PFC12 Specification of alternate function of P12 pin 0 0 TOQOT2 output PFCE11 PFC11 Specification of alternate function of P11 pin 0 0 TOQOB1 output PFCE10 PFC10 Specification of alternate function of P10 pin 0 0 TOQOT1 output Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 11 Pull up resistor option register 1 PU1 Set the PU1 register as follows PU1 register OOH PU1 Address FFFFFC42H After reset
52. on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an UO pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Application Note U18600EJ
53. oo Wo Women an naa 63 5 4 MAIN Processing Ae en aa aan aa Anna 63 55 PWM Processing Ee 64 5 6 High Impedance Setting ProceSSIng o oooooom oom anna 65 5 7 TMO Valley Interrupt INTTQOOV Servicing oooo oo oom nennen nnn nnns 66 5 8 A D Converters 0 and 1 Conversion Completion Processing eene 66 5 9 sin2 Calculation Processing oooooo o oo oom nenen nana 67 5 10 sins Calculation Processing ooooo oo oom nan anna 68 CHAPTER 6 SETTINGS Keamanan esa ngan aan 69 6 1 Settings of 3 Phase PWM DFiVeF oooooooo Wo oom nan an naa 69 APPENDIX A INTERFACE BETWEEN MODULES o ddo mmm nan nan naa 70 10 Application Note U18600EJ1VOAN CHAPTER 1 HARDWARE CONFIGURATION This chapter describes the hardware configuration of the 3 phase PWM driver 1 1 Operation The following shows the main functions of the 3 phase PWM driver e Pulse duty for U V and W phases can be set freely by specifying the d axis q axis and rotational coordinates 6 e PWM pulse of the same duty can be continuously output in output lock mode e PWM output pins TOQOT1 to TOQOT3 TOQOB1 to TOQOB3 can be set to high impedance state by software e The start trigger for conversion of A D converters 0 and 1 can be generated in synchronization with carrier cycles 1 2 System Configuration The system configuration is shown below Figure 1 1 System Configuration Diagram 3 phase PWM driver I O signal for
54. polar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power Source is turned ON devices with reset functions have not yet been initialized Hence power
55. pplication Note U18245E Manual for Using Sample Program Functions A D Converter 2 Application Note U18246E Inverter Control by V850 Microcontrollers 6 Phase PWM Output Control by Timer Q Timer Q Option Timer P A D Converters 0 and 1 Application Note Application Note U18600EJ1VOAN This document Documents related to development tools user s manuals Document Name Document No QB V850EIA4 In circuit emulator for V850E IA3 V850E IA4 V850ES IK1 U17167E QB V850ESIX2 In circuit emulator for V850ES IE2 U17909E QB V850MINI On chip debug emulator for V850E IA4 U17638E CA850 Ver 3 00 C compiler package Operation U17293E C Language U17291E Assembly Language U17292E Link Directive U17294E PM Ver 6 00 Project manager U17178E ID850 Ver 3 00 Integrated debugger Operation U17358E ID850QB Ver 3 20 Integrated debugger Operation U17964E TW850 Ver 2 00 Performance analysis tuning tool U17241E RX850 Ver 3 20 Real time OS Basics U13430E Installation U17419E Technical U13431E Task Debugger U17420E RX850 Pro Ver 3 20 Real time OS Basics U13773E Installation U17421E Technical U13772E Task Debugger U17422E AZ850 Ver 3 30 System performance analyzer U17423E PG FP4 Flash Memory Programmer U15260E Application Note U18600EJ1VOAN 9 CONTENTS CHAPTER 1 HARDWARE CONFIGURATION woo
56. quipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1 Application Note U18600EJ1VOAN INTRODUCTION Cautions 1 This Application Note explains a case where the V850E IA4 uPD70F3186GC 8EU A is used as a representative microcontroller Use this Application Note for your reference when using the V850E IA4 other than the PD70F3186GC 8EU A V85
57. r may generate heat and be damaged Therefore set the output lock mode after thoroughly evaluating the pulse duty ratio in the overall system Explanation of arguments 1 pwm mode This argument sets a mode of the 3 phase PWM driver 2 pwm flag This argument sets the output status of the PWM output pin 3 valued This argument is a set value in each mode In direct mode In dq conversion mode U phase output width Set this value in a range of 0 to 800 CARRIERPULSE 1 Executes 3 phase voltage conversion used for vector calculation This value is equivalent to d axis current in the dq conversion mode This value is set in a range of 400 to 400 In output lock mode None This argument is not used in the output lock mode Remark Refer to the next page for Note 58 Application Note U18600EJ1VOAN Note 4 5 value1 CHAPTER 3 PROGRAM CONFIGURATION This argument is a set value in each mode In direct mode In dq conversion mode In output lock mode value2 V phase output width Set this value in a range of 0 to 800 CARRIERPULSE 1 Executes 3 phase voltage conversion used for vector calculation This value is equivalent to q axis current in the dq conversion mode This value is set in a range of 400 to 400 None This argument is not used in the output lock mode This argument is a set value in each mode In direct mode In dq conversion mode In output lock
58. r product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual e
59. ranted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
60. t INTTQOOV TTRG10 With the 3 phase PWM driver the timing of conversion start trigger of A D converters 0 and 1 is the same To change the conversion start time set the TPOCCRO and TPOCCRI registers in accordance with the above expression 56 Application Note U18600EJ1VOAN CHAPTER 3 PROGRAM CONFIGURATION 3 6 2 A D conversion completion time With the 3 phase PWM driver the ADAOM register is set as follows ADAOM1 0x01 A DO conversion clock 124 1 94 us The A D conversion clock time is 124 clocks and the A D conversion completion time is 1 94 ws Application Note U18600EJ1VOAN 57 3 7 Arguments CHAPTER 3 PROGRAM CONFIGURATION The arguments used in the 3 phase PWM driver are listed in the table below unsigned char Table 3 3 Arguments Sets 3 phase PWM mode Set Value Direct mode dq conversion mode Output lock mode pwm flag unsigned char PWM output flag PWM output disabled high impedance state 1 PWM output enabled PWM output value0 signed int Set value 0 In direct mode 0 to 800 In dq conversion mode 400 to 400 value1 signed int Set value 1 In direct mode 0 to 800 In dq conversion mode 400 to 400 value2 signed int Set value 2 In direct mode 0 to 800 In dq conversion mode 0 to MAXPULSE Note f the output is locked in the output lock mode at a high pulse duty ratio the IGBT drive
61. t output of the target pin is enabled This bit is cleared to 0 when the HZAODCEO bit 0 This bit is cleared to 0 when the HZAODCCO bit 1 40 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 36 A D converter n mode register 0 ADAnMO Set the ADAnMO register as follows ADAnMO register 22H A2H ADAnMO n 0 1 After reset Bit name Set value 0 0 Address ADAOMO FFFFF200H ADA1MO FFFFF220H 4 0 3 0 0 1 0 0 0 ADAnCE ADAnMD1 ADAnMDO ADAnETS1 ADAnETSO ADAnTMD ADAnEF 0 1 1 0 0 0 1 0 ADAnCE A D conversion operation control Stop conversion operation Start conversion operation ADAnMD1 ADAnMDO Operation mode specification One shot select mode ADAnETS1 ADAnETSO Specification of external trigger ADTRGn valid edge 0 0 No edge detection external trigger invalid ADAnTMD Trigger mode specification Hardware trigger mode ADAnEF Status of A D converter n 0 A D conversion stopped Application Note U18600EJ1VOAN 41 CHAPTER 2 CONTROL METHOD 37 A D converter n mode register 1 ADAnM1 Set the ADAnM1 register as follows ADAnM1 register 01H ADAnM1 Address ADAOM1 FFFFF201H ADA1M1 FFFFF221H n 0 1 1 0 After reset 0 Bit name ADAnFR1 Set value 0 ADAnFRO Specification of number of conversion clocks 1 1 94 us Caution Be sure to set bits 2 to 7
62. ter 0 TPOIOCO Set the TPOIOCO register as follows TPOIOCO register 00H TPOIOCO Address FFFFF642H 1 0 After reset 0 0 0 0 Bit name TPOOL1 TPOOE1 TPOOLO TPOOEO Set value 0 0 0 0 TPOOL1 TOPOT pin output level setting 0 TOP01 pin starts output at high level TPOOE1 TOPOT pin output setting 0 Timer output prohibited Low level is output from the TOP01 pin TPOOLO TOPOO pin output level setting 0 TOPOO pin starts output at high level TPOOEO TOPOO pin output setting 0 Timer output prohibited Low level is output from the TOPOO pin 28 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 15 TMPO I O control register 1 TPOIOC1 Set the TPOIOC1 register as follows TPOIOC1 register OOH TPOIOC1 Address FFFFF643H 1 0 After reset 0 0 0 0 Bit name TPOIS3 TPOIS2 TPOIS1 TPOISO Set value 0 0 0 0 TPOIS3 TPOIS2 Capture trigger input signal TIPO1 pin valid edge setting 0 0 No edge detection capture operation invalid TPOIS1 TPOISO Capture trigger input signal TIPOO pin valid edge setting 0 0 No edge detection capture operation invalid 16 TMPO I O control register 2 TPOIOC2 Set the TPOIOC2 register as follows TPOIOC2 register 00H TPOIOC2 Address FFFFF644H 1 After reset 0 0 0 Bit name TPOEES1 TPOEESO TPOETS1 Set value 0 0 0 TPOEES1 TPOEESO External event count input signal TIPOO pi
63. to 0 38 A D converter n channel specification register ADAnS Set the ADAnS register as follows ADAnS register 00H ADAnS Address ADAOS FFFFF202H ADA1S FFFFF222H n 0 1 2 1 0 4 After reset 0 0 0 0 Bit name 0 ADAnS2 ADAnS1 ADAnSO 0 0 0 0 Set value ADAnS2 ADAnS1 ADAnSO Select mode 0 0 0 Caution Be sure to set bits 3 to 7 to 0 42 Application Note U18600EJ1VOAN CHAPTER 2 CONTROL METHOD 39 A D converter n mode register 2 ADAnM2 Set the ADAnM2 register as follows ADAnM2 register 01H ADAnM2 Address ADAOM2 FFFFF203H ADA1M2 FFFFF223H n 0 1 1 0 After reset 0 0 Bit name ADAnBS ADAnTMD1 Set value 0 0 ADAnBS Buffer mode specification 0 1 buffer mode ADAnTMD1 ADAnTMDO Hardware trigger mode specification Timer trigger mode 0 40 Operational amplifier n control register 0 OPnCTLO Set the OPnCTLO register as follows OPnCTLO register 00H OPnCTLO Address OPOCTLO FFFFF260H OP1CTLO FFFFF268H n 2 0 1 4 After reset 0 0 0 Bit name OPnOEN2 OPnOEN1 OPnOENO Set value 0 0 0 PnOEN2 Operation control of operational amplifier 2 0 Disables operation OPnOEN1 Operation control of operational amplifier 1 0 Disables operation OPnOENO Operation control of operational amplifier O 0 Disables operation OPnGAO Gain specification of operational amplifier Caution Be sure to set b
64. vicing disabled UA1TMK Interrupt mask flag setting 1 INTUA1T interrupt servicing disabled 48 Application Note U18600EJ1VOAN UA1RMK 1 UATREMK 1 CBOTMK 1 CBORMK 1 CHAPTER 2 CONTROL METHOD Interrupt mask flag setting INTUATR interrupt servicing disabled Interrupt mask flag setting INTUA1RE interrupt servicing disabled Interrupt mask flag setting INTCBOT interrupt servicing disabled Interrupt mask flag setting INTCBOR interrupt servicing disabled Application Note U18600EJ1VOAN 2 2 49 CHAPTER 3 PROGRAM CONFIGURATION This chapter explains the program configuration of the 3 phase PWM driver The user should set the PWM pulse 3 1 Configuration of 3 Phase PWM Driver The configuration of the 3 phase PWM driver is illustrated below Figure 3 1 Phase PWM Driver Configuration 1 2 No Pulse enabled Yes 1 Mode identification 3 3 phase voltage 2 Holding PWM 4 Direct output a lt 5 gt High impedance setting 7 A D converters 0 and 1 conversion Refer to Figure 5 8 A D Converters 0 and 1 Conversion completion processing Completion Processing ope IMS valley interrupt INTTOQOV Refer to 5 7 TMQO Valley Interrupt INTTQOOV Processing processing for debugging 6 sin calculation processing Note This processing is used only for debugging and is not usually used Refer to Figure 5 9 sin2 Calculation

Inverter Control by V850 Microcontrollers 6

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