A Tour Beyond BIOS Creating the Intel® Firmware Support Package
Contents
1. For more detail please refer to user manual https github com tianocore edk2 IntelFspPkg tree master Tools UserManuals PatchFvUserManual docx 1 Patch FspInfoHeader 2 Patch VPD base 3 Pace persists FD postbuila BuildFv cmd Final FD postbuild Config Data FV MAP _TempRamInitApi _FsplnitApi _NotifyPhaseApi VPD info UPD info 22 Figure 8 Postbuild tool PatchFv py Dual FSP Support Dual FSP means there could be two FSP images at different locations in a flash one factory version default and updatable version updatable TempRamInit FspMemoryInit and TempRamExit are always executed from factory version FspSiliconInit and NotifyPhase can be executed from updatable version if it is available FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version In order to support Dual FSP user need define 2 FV and combine those 2 FV into one FD in FDF file One BFV contains VPD region SecCore PeiCore and MemoryInit module The other silicon FV contains FspInfoHeader Dxelpl and SiliconInit module This FD could be factory FSP binary For updatable FSP binary only silicon FV can be updated there See example below PlatformFspPkg fdf FD SIFSP BaseAddress FLASH BASE gIntelFspPkgTokenSpaceGuid PcdFspAreaBaseAddress Size FLASH SIZE gIntelFspPkgTokenSpaceGuid PcdFspAreaSize ErasePolarity 1 BlockSize FLASH2. CurPtr EndPtr GetFspInfoHeaderFromApiContext r gt Signature FSPH_SIGNATURE ERROR The signature of FspInfoHeader is invalid n FspInfoHeader gt ImageBase FspInfoHeader gt ImageSize 1 EndPtr EFI_FIRMWARE VOLUME HEADER CurPtr EFI_FVH_SIGNATURE if FvHeader gt ExtHeaderOffset 0 Searching for the Silicon FV in the FSP image FwVolExtHeader gt ExtHeaderOffset if CompareGuid amp FwVolExtHeader gt FvName EFI FIRMWARE VOLUME EXT HEADER UINT8 FvHeader FvHeader amp gFspSiliconFvGuid PeiServicesInstallFvInfoPpi NULL VOID FvHeader 22 UINTN FvHeader gt FvLength NULL NULL CurPtr FvHeader gt FvLength return EFI SUCCESS EFI_STATUS EFIAPI MemoryDiscoveredPpiNotifyCallback IN EFI PEI SERVICES PeiServices IN EFI PEI NOTIFY DESCRIPTOR NotifyDescriptor IN VOID Ppi DEBUG DEBUG_INFO DEBUG_INIT Memory Discovered Notify invoked Build PEI Reserve memory HOB MemBase GetUsableLowMemTop GetHobList MemSize PcdGet32 PcdFspReservedMemoryLength BuildResourceDescriptorWithOwnerHob FI RESOURCE MEMORY RESERVED a RESOURCE ATTRIBUTE PRESENT 7 RESOURCE ATTRIBUTE TESTED zj j 3 7 lt mE a a eee MemBase MemSize MemSize RESOURCE ATTRIBUTE INITIALIZED RESOURCE ATTRIBUTE UN
3. D9093578 08EB 44DF B9D8 DOC1D3D55D96 SECTION RAW FspDescription FspDescription txt FSP_INFO_HEADER FSP_INFO_HEADER must be the 1 firmware file within the FSP firmware volume We can use below way to ensure that First we define a FSP_INFO_HEADER structure in C style file and use ASLC as file name extension We must define ReferenceAcpiTable function referring to this global data structure or this global data will be optimized at link phase We also need FSP_INFO_EXTENDED_HEADER for FSP1 1 FSP_PATCH_TABLE is FSP implementation specific table It is put here because we want to reserve space in FSP binary to let platform refer patch information FspHeader aslc typedef struct FSP_INFO_ HEADER FspInfoHeader FSP_INFO EXTENDED_HEADER FspInfoExtendedHeader FSP PATCH TABLE FspPatchTable TABLES TABLES mTable FspInfoHeader 0x48505346 UINT32 Signature FSPH sizeof FSP INFO HEADER UINT32 HeaderLength 0x00 0x00 0x00 UINT8 Reserved1 3 FixedPcdGet8 PcdFspHeaderRevision UINT8 HeaderRevision FixedPcdGet32 PcdFspImageRevision UINT32 ImageRevision 19 UINT64 TO BYTE ARRAY FixedPcdGet 64 PcdFspImageldString FixedPcdGet32 PcdFspAreaSize FixedPcdGet32 PcdFspAreaBaseAddress 0x00000000 0x12345678 0x12345678 0x00000006 0x12345678 0x12345678 0x12345678 0x12345678 0
4. TARGET TOOL CHAIN TAG FV VPD TOOL GUID bin SECTION RAW OUTPUT DIRECTORY TARGET TOOL CHAIN TAG FV UPD TOOL GUID bin In FDF file we put VPD binary and UPD binary together into one file section Prebuild GenCfgOpt After VPD UPD is defined in dsc file GenCfgOpt py tool https github com tianocore edk2 IntelFspPkg tree master Tools GenCfgOpt py will create corresponding VPD UDP header file for bootloader developer The content in VpdHeader file is like below VpdHeader h typedef struct _VPD DATA REGION UINT64 PcdVpdRegionSign Offset 0x0000 UINT32 PcdImageRevision Offset 0x0008 UINT32 PcdUpdRegionOffset Offset 0x000C UINT8 PcdSerialloUartDebugEnable Offset 0x0030 VPD_DATA REGION typedef struct _UPD DATA REGION UINT64 Signature Offset 0x0000 UINT64 Reserved Offset 0x0008 UINT32 TsegSize Offset 0x0100 UPD_DATA REGION This GenCfgOpt py tool runs before formal EDKII build That is why we call it as prebuild tool For more detail please refer to user manual https github com tianocore edk2 Intel FspPkg tree master Tools UserManuals GenCfgOptUserManual docx 17 1 UPDTXT 2 HEADER GenCfgOpt py 1 SUPD GUID txt BuildFv cmd 2 VpdHeader h FSP_ PKG NAME bsf prebuild Figure 7 Prebuild tool GenCfgOpt py
5. Update policy based on U EGION UpdDataRgnF EGION GetFspUpdDataPointer PD data 21 MemoryDiscoveredPpiNotifyCallback for FSP 1 1 In FSP 1 1 mode we need use Pei2LoaderSwitchStack API defined in FspSwitchStackLib https github com tianocore edk2 Intel FspPkg tree master Include Library FspSwitchStackLib h to switch back to bootloader Some sample code for MemoryDiscoveredPpiNotifyCallback below UINT32 GetUsableLowMemTop CONST VOID EFI_PEI_HOB_POINTERS UINT32 Hob Raw MemLen while 0x100000 END OF HOB HobStart Hob MemLen VOID HobStart LIST Hob if Hob Header gt HobType EFI HOB TYPE RESOURCE DESCRIPTOR if Hob ResourceDescriptor gt ResourceType EFI RESOURCE SYSTEM MEMORY if Hob ResourceDescriptor gt PhysicalStart gt 0x100000 amp amp Hob ResourceDescriptor gt PhysicalStart lt MemLen Hob Raw return MemLen EFI_ STATUS GET_NEXT_HOB EFI_PHYSICAL ADDRESS 0x100000000 UINT32 Hob ResourceDescriptor gt ResourceLength Hob ReportAndInstallFspSiliconFv VOID EFI FIRMWARE VOLUME EXT HEADER FSP INFO HEADER EFI FIRMWARE VOLUME HEADER UINT8 UINT8 FspInfoHeader if FspInfoHeade DEBUG CurPtr EndPtr UINT8 CurPtr while FvHeader CurPtr lt if FvHeader gt Signature break DEBUG FwVolExtHeader FspInfoHeader FvHeader
6. 4 www uefi org 33 Authors Jiewen Yao jiewen yao intel com is EDKII BIOS architect EDKII FSP package maintainer with Software and Services Group SSG at Intel Corporation Vincent J Zimmer vincent zimmer intel com is a Senior Principal Engineer with the Software and Services Group SSG at Intel Corporation based in Seattle WA Ravi P Rangarajan ravi p rangarajan intel com is BIOS architect in the Internet of Things IOT Group IOTG at Intel Corporation Maurice Ma maurice ma intel com is BIOS architect in the Internet of Things IOT IOT Group IOTG at Intel Corporation David Estrada david c estrada intel com is BIOS architect in the Client Components Group CCG at Intel Corporation Giri Mudusuru giri p mudusuru intel com is BIOS architect and Principal Engineer in the Client Components Group CCG at Intel Corporation 34 This paper is for informational purposes only THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY NONINFRINGEMENT FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein Intel the Intel logo Intel
7. BLOCK_SIZE NumBlocks FLASH NUM BLOCKS SET gIntelFspPkgTokenSpaceGuid PcdFspBootFirmwareVolumeBase FLASH BASE FLASH REGION FSP SILICON FV_ SIZE FSP Silicon FLASH REGION FSP SILICON _FV_OFFSET FLASH_ REGION FSP SILICON_FV_SIZE gSiFspPkgTokenSpaceGuid PcdFlashFspSiliconFvBase gSiFspPkgTokenSpaceGuid PcdFlashFspSi liconFvSize FV SIFSP Silicon FSP BFV S FLASH REGION FSP BFV OFFSET FLASH REGION FV FSP BFV SIZE gSiFspPkgTokenSpaceGuid PcdFlashFspBfvBase gSiFspPkgTokenSpaceGuid PcdFlashFspBfvSize FV SIFSP BFV FV SIFSP BFV BlockSize 0x00001000 FvAlignment 16 ERASE POLARITY 1 EMORY MAPPED TRUE STICKY WRITE TRUE LOCK CAP TRUE LOCK STATUS TRUE WRITE DISABLED CAP TRUE WRITE ENABLED CAP TRUE WRITE STATUS TRUE WRITE LOCK CAP TRUE WRITE LOCK STATUS TRUE READ DISABLED CAP TRUE READ ENABLED CAP TRUE READ STATUS TRUE READ LOCK CAP TRUE READ LOCK STATUS TRUE FvNameGuid 12345678 1234 1234 1234 1234567890CD 26 Core comp onents INF IntelFspPkg FspSecCore FspSecCore inf INF MdeModulePkg Core Pei PeiMain inf INF MdeModulePkg Universal PCD Pei Pcd inf VPD UPD r FILE RAW SECTION OUTPUT _DI SECTION OUTPUT _DI Memory In egion 12345678 1234 1234 1234 1234567890A
8. FSP Global Data CoreStack FSP Patch Tb FSP Platform Data PcdVpdBase Code Cache i lout FSP Header Ptr UPD Data Rgn Ptr Host Memory Perf Data PD Override UPD Offset H UPD Default gt od Figure 4 FSP runtime data structure 10 During runtime FspSecCore https github com tianocore edk2 IntelFspPkg tree master FspSecCore will setup FSP Global Data The Global Data area contains below important data structure 1 CoreStack This is context stack used by FSP The context includes all general purpose register So that the FSP API can do SetJump LongJump like context switch to original FSP API caller provided stack from FSP internal stack 2 PlatformData This area record the Microcode and CodeCache region passed from TempRamInit API Also an FSP specific implementation can save its own private data pointer to DataPtr field of PlatformData 3 FspInfoHeader This is pointer to FSP binary on flash 4 UpdDataRgnPtr This is pointer to user provided UPD region to override the default UPD data region in VPD If caller provides valid value for UpdDataRgnPtr of FSP_INIT_RT_COMMON_BUFFER this new UPD will be used If UpdDataRgnPtr is NULL the FSP will assume default UPD at UpdRegionOffset OxOC of VPD CfgRegion Every FSP implementation should follow this way to put UPD data pointer there 5 API Mode 0 means FSP1 0 flow 1 means FSP1 1 flow 6 PerfData Record
9. MODULE_TYPE FspHeader inf 20 Then we add this module in FDF file as first module of FSP FV and use build rule override FSPHEADER to extract global data section only PlatformFspPkg fdf FV SIFSP BlockSize 0x00001000 FvAlignment 16 ERASE POLARITY 1 MEMORY MAPPED TRUE STICKY WRITE TRUE LOCK CAP TRUE LOCK STATUS TRUE IRITE DISABLED CAP TRUE VRITE ENABLED CAP TRUE VRITE STATUS TRUE WRITE LOCK CAP TRUE WRITE LOCK STATUS TRUE READ DISABLED CAP TRUE READ ENABLED CAP TRUE READ STATUS TRUE READ LOCK CAP TRUE READ LOCK STATUS TRUE FvNameGuid 12345678 1234 1234 1234 1234567890CD INF RuleOverride FSPHEADER S FSP_PACKAGE FspHeader FspHeader inf Rule Common USER DEFINED FSPHEADER FILE RAW NAMED GU D RAW BIN acpi Convert VPD UPD to Policy Then we need a platform module to convert VPD UPD data to the silicon policy PPI For example to use GetFspUpdDataPointer API defined in FspCommonLib https github com tianocore edk2 IntelFspPkg tree master Include Library FspCommonLib h Some sample code to consume GetFspUpdDataPointer below UPD_DATA RI UpdDataRgn Ptr UPD DATA R
10. MemoryDiscoveredPpiNotifyCallback function This function does switch stack back to bootloader after memory initialization done After bootloader calls 2 API TempRamExit in SecCore this API switches back to MemoryDiscoveredPpiNotifyCallback run next instruction to reset cache and switches back to bootloader again Then bootloader call qu 12 API FspSiliconInit in SecCore it switches back to MemoryDiscoveredPpiNotifyCallback run rest code of system initialization Flash Memory CONTEXT STACK FSP Global Data Figure 6 FSP API Flow in FSP 1 1 Summary This section has a generic overview of FSP binary infrastructure including FSP binary layout runtime data structure and API flow for both 1 0 and 1 1 In next sections we will discuss detail step by step on how to create a FSP binary and release it 13 Step 1 Put silicon initialization module to PI PEI Silicon code V S Generic code V S Platform code Since FSP is for silicon initialization so the first step is to find what and where is silicon code There is one way to identify silicon code If the code is written according to Intel silicon external design specification most likely it is silicon code For example MemoryInit Cpulnit SmartTimer and Smbus are silicon code The silicon code might need rewritten if silicon hardware is upgraded But it should be same if only platform or board is changed Generic code means the code can be used on almos
11. User configuration BSF BCT GenCfgOpt py too also creates BSF configuration file user can use BCT tool www intel com fsp to do configuration after FSP binary is generated The content in BSF file is like below FSP bsf VPD data region Find SI_VPD S gPlatformFspPkgTokenSpaceGuid PcdImageRevision 4 bytes DEFAULT 0x00070100 Skip XX bytes S gSiFspPkgTokenSpaceGuid PcdSerialloUartDebugEnable 1 bytes DEFAULT 0 UPD data region Find SI_UPDS Skip XX bytes gSiFspPkgTokenSpaceGuid_ TsegSize 4 bytes DEFAULT _ 0x01000000 Show configuration Page Platform Combo gSiFspPkgTokenSpaceGuid_PcdSeriallIoUartDebugEnable UART Debug amp gSiPkgTokenSpaceGuid_ PcdSerialloUartDebugEnable Help Select UART Debug enable disable Summary This section describes how to user VPD UPD to expose silicon configuration in FSP package 18 Step 3 Build with IntelFspPkg FSP binary includes silicon modules and FspSecCore and FspDxelpl in IntelFspPkg https github com tianocore edk2 IntelFspPkg But they are not enough We should include below components to make a full solution FSP Description File The FSP binary may optionally include an FSP description file This file will provide information about the FSP including information about different silicon revisions the FSP supports See below sample in FDF file PlatformFspPkg fdf Description file FILE RAW
12. artifacts and the EDKII open source are using in the FSP production The topic of this paper is Intel FSP binary We will discuss how to create Intel FSP binary the producer by using EDKII environment in more detail Introduction to FSP 1 1 FSP version 1 1 supports two boot flows See below figure Boot Flow 1 is simpler for the boot loader It provides the compatible support as FSP version 1 0 Boot Flow 2 increases flexibility and control for the boot loader It splits FspInit API to 3 different APIs Fsp Memory Init TempRamExit and FspSiliconInit so that boot loader always keeps control of the boot flow The two boot flows are mutually exclusive Boot Flow 1 Boot Flow 2 Switch to 32 bit Mode TempRaminit Switch to 32 bit Mode Find FSP_INFO_HEADER Load mieracode Find FSP_INFO_HEADER Call to TempRaminit API Enable CAR Call to TempRaminit API Pre Memory Init EspMemorvinit Pre Memory Init Call Fspinit API Memory Init Call EspMemoryinit API Pass Continuation Func Switch Stack amp Temp RAM migration Call TempRamExit API JempRameExit Tear down CAR Fspinit Memory Chipset amp CPU Init Continuation Func Parse FSP Return Data EspSiliconinit CPU Chipset Init Call to FspSiliconinit API Bus and Device Init Bus and Device Init Call NotifyPhase NotifyPhase e Call NotifyPhase PostPciEnumeration z pie nit PostPciEnumeration Lock settings lt 2 a E o fe E fe ho ln G E f
13. io g 8 w 2 a Boot Device Init A A Boot Device Init Call NotifyPhase Joti z y VPD UPD Data Call NotifyPhase ReadyToBoot Load OS or other payload Load OS or other payload Figure 2 1 FSP 1 1 architecture FSP 1 1 also provides graphic support If BITO GRAPHICS_ SUPPORT of the Image Attribute field in the FSP_INFO_HEADER is set the FSP include graphics initialization capabilities When graphics capability is included in FSP and enabled FSP produces a EFI_PEI_GRAPHICS_INFO_HOB as described in the PI Specification which provides information about the graphics mode and framebuffer So that the boot loader may have a generic driver to produce EFI_GRAPHICS_OUTPUT_PROTOCOL defined in UEFI specification Introduction to EDKIl EDKII is open source implementation for UEFI firmware which can boot multiple UEFI OS This document will introduce how to use EDKII as FSP producer module to build an FSP binary Summary This section provided an overview of Intel FSP and EDKII FSP Component In EDKII there are 2 different FSP related packages One is producer IntelFspPkg it is used to produce FSP bin together with other EDKII package and silicon package The other is consumer IntelFspWrapperPkg it will consume the API exposed by FSP bin This paper only focuses on IntelFspPkg on how to use IntelFspPkg to create FSP bin This paper will not describe IntelFspWrapperPkg on how it consumes FSP bin which is described
14. B RAW RAW it modu le INF lt MemoryInit gt inf Descripti FILE RAW ECTION n FV SIFSP_S BlockSize FvAlignment ERASE POLAR EMORY MAPP LOCK_CAP LOCK STATUS WRITE DISAB STICKY WRITE on file RECTORY TARGET TOOL CHAIN TAG FV VPD TOOL GUID bin RECTORY TARGET TOOL CHAIN TAG FV UPD TOOL GUID bin D9093578 08EB 44DF B9D8 DOC1D3D55D96 FSP PACKAGE FspDescription FspDescription txt RAW ilicon ITY ED m ja ED_CAP WRITE ENAB WRITE STATU WRITE LOCK WRITE LOCK EAD DISAB ED_CAP S CAP STATUS ED_CAP R READ ENABLE READ STATUS R R EAD LOCK S FvNameGuid FSP Info INF RuleOve D CAP EAD LOCK CAP TATUS header rride 16 TR U TR U TR U 0x00001000 TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU TRU 12345678 1234 1234 1234 1234567890EF HA AAAA AAA FSPHEADER FSP PACKAGE FspHeader FspHeader inf INF IntelFspPkg FspDxeIp1 FspDxelIpl inf Silicon Init module INF lt SiliconInit gt inf Then in MemoryDiscoveredPpiNotifyCallback user can call ReportAndInstallFspSiliconFv to install the silicon FV then all the modules in silicon FV will be dispatched by PEI Core Summary This section describes the additional com
15. BaseAddress 0x000000B0 VPD PCD offset 24 12345678 1234 1234 1234 1234567890AB 0x28 12345678 1234 1234 1234 1234567890AB 0x18 0x00000003 amp OxOOFFFFFC 12345678 1234 1234 1234 1234567890AB 0x1C UPD Region offset In VPD UPD data are in file section so final 4 entries patch VPD region offset and UPD region offset The FSP_PATCH_TABLE is also patched here For example offset 0x00000100 is 2 4 FSP_PATCH_TABLE patch entry It means VPD PCD offset 2 Patch FspInfoHeader relative offset python IntelFspPkg Tools PatchFv py SOUT_DIR FSP_ PKG NAME BD TARGETS STOOL CHAIN TAG FV SIFSP FspSecCore FspInfoHeaderRelativeOff FspSecCore GetFspBaseAddress 912740BE 2284 4734 B971 84B027353F0C 0x1C FSP Header Offset The FspInfoHeaderRelativeOff is the symbol in FspSecCore https github com tianocore edk2 IntelFspPkg tree master FspSecCore la32 FspHelper asm It is used to calculate FspBase Address 3 Patch VPD base into the PcdPeim module patchable PCD python IntelFspPkg Tools PatchFv py SOUT_DIR FSP_ PKG NAME BD TARGETS TOOL CHAIN TAG S FV SIFSP PcdPeim gPcd_BinaryPatch_PcdVpdBaseAddress 0x000000B8 VPD PCD base The offset of VPD region data is at FSP_INFO_HEADER so we need patch the value into PcdVpdBaseAddress of PcdPeim This PatchFv py tool runs after formal EDKII build and it will patch final FD binary that is why we call it as postbuild tool
16. CACHEABLE RESOURCE ATTRIBUTE WRITE COMBINEABLE RESOURCE ATTRIBUTE WRITE THROUGH CACHEABLE _RESOURCE ATTRIBUTE WRITE BACK CACHEABLE amp gFspReservedMemoryResourceHobGuid Get system memory from HOB FspGetSystemMemorySize amp LowMemoryLength amp HighMemoryLength FSP reserved memory is immediately folowing all availabel system memory regions sued VIE ONG so we should add it back to ensure this reserved region is cached LowMemoryLength PcdGet32 PcdFspReservedMemoryLength Migrate BootLoader data before destroying CAR ff FspMigrateTemporaryMemory ApiMode GetFspApiCallingMode if ApiMode 0 7 Calling use FspMemoryInit API Return the control directly FspMemoryInitParams FSP MEMORY INIT PARAMS GetFspApiParameter if FspMemoryInitParams gt HobListPtr NULL FspMemoryInitParams gt HobListPtr VOID GetHobList 23 This is the end of the FspMemoryInit API Give control back to the boot loader DEBUG DEBUG INFO DEBUG INIT FspMemoryInitApi End n SetFspApiReturnStatus EFI SUCCESS Pei2LoaderSwitchStack Disable CAR ResetCacheAttributes if ApiMode 0 This is the end of the TempRamExit API Give control back to the boot loader DEBUG DEBUG INFO DEBUG INIT TempRamExitApi End n SetFspApiReturnStatus Pei2LoaderSwi
17. White Paper A Tour Beyond BIOS Creating the Intel Firmware Support Package Version 1 1 with the EFI Developer Kit II Jiewen Yao Intel Corporation Vincent J Zimmer Intel Corporation Ravi Rangarajan Intel Corporation Maurice Ma Intel Corporation David Estrada Intel Corporation Giri Mudusuru Intel Corporation April 2015 Executive Summary This paper presents details on how to create an Intel Firmware Support Package FSP conformant FSP EAS binary by using in EDKII EDK2 After this FSP Production then the resultant Intel FSP binary can be integrated into any boot loader FSP Consumer Prerequisite This paper assumes that the audience has EDKII UEFI firmware development experience He or she should be familiar with UEFI PI firmware infrastructure e g SEC PED and know the UEFI PI firmware boot flow e g normal boot S3 Capsule update recovery UEFI UEFI Book gt 11 Table of Contents OVER 5 Introduction To ESP a E E 5 Introduction t FSP A sia ts 6 Introduction to EDK arde 7 A a A EE E E E E E ere ert Eee r rr 8 FSP Infrastructur AE 9 RR ee aia eaei aa aiae eaaa eaaa a EE a EE 9 FSP runtime data StrUCtUTS iscsncscavusndicssnrSeacedsyetvasebidsteniesunndvcaesnpidieseomianenteedeeamenbied 10 FSP Pa o AAA E E PEO OI E EEE 11 FSP API Flow in FSP Wa rossins iia 12 Step 1 Put silicon initialization module to PI PEL ccccccccccccsccsscsscsecseesscsssescesceseeaes 14 Silic
18. d chipset complex We refer to the entities that create the FSP binary as the FSP Producer and the developer who integrates the FSP into some platform firmware as the FSP Consumer Despite the variability of the FSP binaries the FSP API caller aka FSP consumer could be a generic module to invoke the three APIs defined in FSP EAS External Architecture Specification to finish silicon initialization FSP EAS The flow below describes the FSP with the FSP binary from the FSP Producer in green and the platform code that integrates the binary or the FSP Consumer in blue a Switch to Protected Mode Continuation Fn Parse FSP return Data TempRaminit Bus and Devices Init Find FSP Header Call NotifyPhase PostPciEnumeration Jump to Te Raminit 3 empRaminit API Boat Device init Pre Memory Initialization Call NotifyPhase ReadyToBoot Load OS or Payload Call Fspinit API Intel FSP Binary Binary Configuration Utility Figure 1 FSP architecture The FSP EAS describes both the API interface to the FSP binary that the consumer code will invoke but it also describes the hand off state from the execution of the FSP binary The latter information is conveyed in Hand Off Blocks or HOB s Both the HOB definition and the binary layout of the FSP bin namely as a Firmware Volume FV are the same as that defined in the UEFI PI specification Both the reuse of the PI specification
19. he firmware volume See UEFI PI Specification FSP Intel Firmware Support Package FSP Consumer the entity that integrates the FSP bin such as EDKII or other firmware like coreboot FSP Producer the entity that creates the FSP binary such as the CPU and chipset manufacturer e g Silicon Vendor Bootloader another name for an FSP Consumer as distinct from a MBR based loader for PC AT BIOS or the OS loader as a UEFI Executable for UEFI UEFI Overview FV Firmware Volume a logical firmware device See UEFI PI Specification INF EDKII Module Information File See EDKII specification PCD Platform Configuration Database See UEFI PI Specification PI Platform Initialization Volume 1 5 of the UEFI PI specifications SMM System Management Mode x86 CPU operational mode that is isolated from and transparent to the operating system runtime 31 UEFI Unified Extensible Firmware Interface Firmware interface between the platform and the operating system UPD Updatable Product Data Configuration data region in FSP binary which can only be configured statically for default value but also can be overwritten during boot at runtime See FSP EAS VPD Vital Product Data Configuration data region in FSP binary which can only be configured statically See EDKII specification DSC format and FSP EAS VTF Volume Top File a file that must be located such that the last b
20. in FSP Consumer EDKII Pkg IntelRcPkg EDKII Pkg PlatformFspPkg PlatformPkg Figure 2 FSP component Summary This section describes the FSP component in EDKII FSP infrastructure Binary layout According to the FSP EAS an FSP binary contains 1 FSP_INFO_HEADER structure providing information about FSP It can be found in firmware section data of 1 firmware file in the FSP firmware volume 2 Initialization code and data needed by the Intel silicon supported The silicon initialization processes are exposed by APIs defined in FSP_INFO_HEADER For example FSP_INFO_HEADER has offset of FspInit API The caller can find the API offset and use C style function to call FspInit then after return the silicon initialization work is done 3 Configuration region that allows the bootloader developer to customize some of the settings The configuration region is exposed by CfgRegionOffset in FSP_INFO_HEADER Firmware Volume Firmware File Firmware Volume Firmware File Header lo Header Firmware Section Header Firmware Section Data FSP_INFO_ HEADER 1 Firmware File Signature Configuration Region Configuration Region Offset TempRaminit Offset FspInit Offset NotifyPhase Offset TempRaminit K Entrypoint Fsplnit Entrypoint NotifyPhase r Entrypoint J Silicon Module Figure 3 FSP b
21. inary layout FSP runtime data structure Current FSP binary is built in flash region and can be executed in flash region On SPI NOR flash those data can be accessed directly via MMIO In FSP_INFO_HEADER https github com tianocore edk2 Intel FspPkg tree master Include FspInfoHeader h ImageBase is a pointer to FSP binary base address CfgRegion is a pointer to configuration region And there are 6 offset of API entrypoint in FSP header TempRamtInit FspInit NotifyPhase FspMemoryInit TempRamExit FspSiliconInit Those entrypoint will be invoked during boot We will discuss detail API flow in next section and we will discuss how to build FSP_INFO HEADER in step 4 Build with IntelFspPkg The configurable data region has two sets of data 1 VPD Vital Product Data which can only be configured statically 2 UPD Updatable Product Data which can be configured statically for default values but also can be overwritten during boot at runtime Both the VPD and the UPD parameters can be statically customized using a separate tool There will be a Boot Setting File BSF provided along with FSP binary to describe the configuration options within the FSP We will discuss detail on how to expose silicon configuration in step 3 Expose silicon configuration Flash Memory Code Cache Area FSP Memory MMIO Microcode CONTEXT STACK ESSE PcdGlobalData FspInfoHeader PointerAddress ApiRet ApiParam
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23. mageld the last byte should be different to avoid multiple instance matches SF e BSF FIND SSI_VPD gSiFspPkgTokenSpaceGuid PcdVpdRegionSign 0x0000 VPD Region Revision BSF NAME PcdImageRevision TYPE None gSiFspPkgTokenSpaceGuid PcdImageRevision 0x0008 This is a offset pointer to the UCD regions used by FSP The offset will be patched to point to the actual region during the build process gSiFspPkgTokenSpaceGuid PedUpdRegionOffset 0x000 BSF NAME PcdSerialloUartDebugEnable TYPE Combo BSF OPTION EN_DIS BSF HELP Enable Seriallo Uart Debug gSiFspPkgTokenSpaceGuid PcdSerialloUartDebugEnable 0x0030 PcdsDynamicVpd Upd BSF FIND SI_UPD gSiFspPkgTokenSpaceGuid Signature 0x0000 0x08 0x245053464C4B5324 gSiFspPkgTokenSpaceGuid Reserved 0x0008 0x08 0x0000000000000000 16 BSF NAME Tseg Size TYPE Combo BSF OPTION SEN _DIS BSF HELP Size of SMRAM memory reserved gSiFspPkgTokenSpaceGuid TsegSize 0x0100 0x04 0x01000000 The first section defines VPD data and the second section defines UPD data NOTE It is required to put PcedUpdRegionOffset at offset OxOOOC for all FSPs PlatformFsp fdf FILE RAW 12345678 1234 1234 1234 1234567890AB SECTION RAW OUTPUT DIRECTORY
24. n to bootloader Then bootloader continues device and bus initialization then notify the NotifyPhase FSP API on AfterPciEnumeration phase or ReadyToBoot phase The entrypoint of NotifyPhase API is still in FspSecCore but it will use switch stack again to 1 save caller context 2 jump to 11 previous context FspDxelpl Then FspDxelpl can continue running code to notify silicon module on AfterPciEnumeration or ReadyToBoot Flash Memory FSP Memory CONTEXT STACK FSP Global Data Figure 5 FSP API Flow FSP API Flow in FSP 1 1 Between FSP1 0 and FSP1 1 the major difference of API flow is that FspInit API is split to 3 FspMemoryInit TempRamExit and FspSiliconInit One potential problem of FSP1 0 is that FspInit will teardown temporary ram unconditionally so the previous context in temporary ram cannot be preserved FSP1 1 resolved the problem After FspMemoryInit API initializes the memory subsystem it gives control back to bootloader and let bootloader migrate its stack and heap data from temporary ram to system memory Then bootloader can call TempRamExit API to teardown temporary ram setup by TempRamInit API Finally bootloader need call FspSiliconInit API to initialize the processor and the chipset including the IO controllers in the chipset to enable normal operation of these devices Since FSP need return to caller after FspMemoryInit this work must be done in a platform defined
25. on code V S Generic code V S Platform COde eee cceeeecetceeceeeeeeeeeeeeeeeeeees 14 Silicon Initialization Module V S Silicon Function Module ccceseeeeeeeeeeeeeeeees 14 Put silicon initialization module to PEI ooonoiioniciccncninicincnnoncnnonnoncnnnnnannrnnonnnrnnrrnnnanonncanos 14 Step 2 Expose silicon configuration cccccccccsscsscsscesccsccssesscsscssesssessessesesascaesecesseseeaes 16 Expose configuration V POV UIP Dy a ai 16 Prebuild Gn Oran 17 User configuration BSF BG TA ad 18 Step 3 Build with IntelFspPKkg 0 A A omensaders 19 ESP Description IG sc ars 19 ESP INFO HEADER our 19 Convert VPD UPD to Py a 21 MemoryDiscoveredPpiNotifyCallback for FSP 1 1 sessssssssssssssssssssssrssssisrrnsrssssessnsesrss 22 Postbu ildi Pai train 24 Dual PSPS OUI ee citi pease avatar cect caine eda E E E E es 26 Step ROSE Mira 29 Package Conte diia ed a eee eee 29 CONCISA dr 30 MOSS iaa 31 111 References iv Overview Introduction to FSP The Intel Firmware Support Package Intel FSP FSP provides key programming information for initializing Intel silicon and can be easily integrated into a firmware boot environment of the developer s choice Different Intel hardware devices may have different Intel FSP binary instances so a platform user needs to choose the right Intel FSP binary release The FSP binary should be independent of the platform design but specific to the Intel CPU an
26. ponents and steps needed to build FSP binary 2 28 Step 4 Release it Package content Finally the release package should include but not limit to 1 Binary file FSP fd 2 Source header file FspUpdVpd h 3 Tool configuration file FSP bsf 4 Document lt Silicon gt _FSP_Integration_Guide Congratulations 29 Conclusion FSP provides a simple to integrate solution that reduces time to market and it is economical to build IntelFspPkg is the core infrastructure of FSP producer in EDKII to support building FSP binary This paper describes detail work flow and how to use IntelFspPkg to build FSP binary 30 Glossary ACPI Advanced Configuration and Power Interface Describe system configuration that is not discoverable and provide runtime interpreted capabilities BCT Binary Configuration Tool The tool to patch FSP binary BSF Boot Setting File The configuration file used by BCT tool BFV Boot Firmware Volume See UEFI PI Specification CAR Cache As RAM Use of the processor cache as a temporary memory stack store DEC EDKII Package Declaration File See EDKII specification DSC EDKII Platform Description File See EDKII specification FD EDKII Flash Device binary image defined in FDF FDF EDKII Flash Descirption File See EDKII specification FFS firmware file system describes the organization of files and optionally free space within t
27. t silicon or platform For example PEI Core PCI Bus and USB bus are generic code Platform code is the code binding to platform board hardware For example GPIO setting and ACPI table are platform code Platform code can also be generic code used for some platforms but not for all platforms For example EfiVariable and SetupBrowser driver are also platform code Here for FSP we only focus on first category silicon code Silicon Initialization Module V S Silicon Function Module There are 2 types of silicon code initialization module and function module Initialization module means the module to initialize memory subsystem processor and the chipset including the IO controllers in the chipset to enable normal operation of these devices For example MemoryInit and Cpulnit are initialization modules The code runs once After initialization the code is never used any more Function module means the module to provide functionality of chipset For example SmartTimer provides EFI_TIMER_ARCH_PROTOCOL service abstraction Smbus provides EFI_PEI_SMBUS2_PPI service abstraction These services are always available in memory after they are provided Here for FSP we only focus on first category silicon initialization module Put silicon initialization module to PEI After we find out silicon initialization modules we need put these modules into PEI phase For UEFI PI BIOS there might be some cases that the original initializa
28. tchStack EFI_ SUCCESS O Install FSP silicon FV To Support Dual FSP Only if NeedSupportDualFsp ReportAndInstallFspSiliconFv if Set the code region as cachable for performance DEBUG DEBUG_INFO DEBUG INIT Memory Discovered Notify completed XA NOTE In order to support dual FSP this module will call ReportAndInstallFspSiliconFv in the middle so that PEI Core will find Silicon FV location Postbuild PatchFv Finally FSP FD will be generated But it is not enough We need patch the pointer referred in binary 1 Patch API offset python IntelFspPkg Tools PatchFv py SOUT_DIRSASFSP_P G_NAMESASBD TARGETS STOOL CHAIN TAGSIFV SIFSP OxFFFFFFFC 0x000000B0 FVBASE OxFFFFFFEO lt PeiCore ModuleEntryPoint gt PeiCore Entry 0x000000C4 lt FspSecCore TempRamInitApi gt TempRamInit API 0x000000C8 lt FspSecCore FspInitApi gt FspInit API 0x000000CC lt FspSecCore NotifyPhaseApi gt NotifyPhase API 0x000000D0 lt FspSecCore FspMemoryInitApi gt FspMemoryInit API 0x000000D4 lt FspSecCore TempRamExitApi gt TempRamExit API 0x000000D8 lt FspSecCore FspSiliconInitApi gt FspSiliconInit API 0x000000B8 12345678 1234 1234 1234 1234567890AB 0x1C VPD Region offset 0x000000BC 12345678 1234 1234 1234 1234567890AB 0x14 OxF800001C VPD Region size 0x00000100 PcdPeim gPcd_BinaryPatch_PcdVpd
29. the performance data Totally 32 entry available The location of this Global Data area is recorded into PcdGlobalDataPointerAddress defined in https github com tianocore edk2 IntelFspPkg tree master IntelFspPkg dec In most current platforms it is an MMIO based scratch register FSP API Flow After system power on bootloader will call FSP TempRamiInit API in FspSecCore https github com tianocore edk2 IntelFspPkg tree master FspSecCore Ia32 FspApiEntry asm before memory and stack are available This FSP API loads the microcode update enables code caching for a region specified by the bootloader and sets up a temporary stack to be used prior to main memory being initialized Then bootloader setups stack in temporary ram run C code and call FspInit API This FSP API initializes the memory the processor and the chipset to enable normal operation of these devices It starts from FspSecCore then call PeiCore in FSP binary https github com tianocore edk2 IntelFspPkg tree master FspSecCore SecMain c Then PeiCore dispatches all silicon PEI modules one by one After all modules are dispatched PeiCore will invoke EFLDXE_IPL_PPIEntry The FspDxelpl https github com tianocore edk2 IntelFspPkg tree master FspDxelpl is different with normal Dxelpl After FspDxelpl installs EndOfPei it means FspInit is done Then FspDxelpl will use switch stack to 1 save current execution context 2 jump back to bootloader stack and retur
30. tion code is in DXE phase For example part of Platform Control Hub PCH initialization and System Agent SA initialization are in DXE phase If so these module need to be ported from PEI to DXE 14 Summary This section describes how to find silicon initialization modules and put them into PEI phase 15 Step 2 Expose silicon configuration Expose configuration VPD UPD Silicon initialization might need some configuration or policy For example SMRAM TSEG size or UART debug enable disable These data can be set in FSP configuration region The configurable data region has two sets of data 1 VPD Vital Product Data which can only be configured statically 2 UPD Updatable Product Data which can be configured statically for default values but also can be overwritten during boot at runtime The silicon vendor can create VPD or UPD based on the need In most case if a configuration can be set by end user via bootloader setup page it should be in UPD region For example SMRAM TSEG size can be changed from 8M to 16M by user for validation purpose If a configuration does not need to be changed by end user but bootloader maker it can be in VPD region For example UART debug enable disable can be chosen by bootloader maker but not end user See below sample PlatformFsp dsc PcdsDynamicVpd VPD Region Signature FSB VPDS Need to be in sync with FspHeader Imageld The first 7 bytes should match with I
31. x12345678 0x12345678 he FspExtendedHeader 0x45505346 sizeof FSP INFO EXTENTED H EADE FSPE_ HEADER REVISION 1 0x00 OEM ID 0x00000001 0x00000000 FspPatchTable 0x50505346 sizeof FSP PATCH TABLE FSPP_ HEADER REVISION 1 0x00 2 OxFFFFFFFC 0x12345678 y VOID ReferenceAcpiTable VOID HHHHHHH NT32 NT16 NT8 NT8 NT32 NT32 NT32 CHAR8 Imageld 8 UINT32 ImageSize UINT32 ImageBase UINT32 ImageAttribute UINT32 CfgRegionOffset UINT32 CfgRegionSize UINT32 ApiEntryNum UINT32 NemInitEntry UINT32 FspInitEntry UINT32 NotifyPhaseEntry UINT32 FspMemoryInitEntry UINT32 TempRamExitEntry UINT32 FspSiliconInitEntry UINT32 Signature FSPE UINT32 Length UINT8 Revision UINT8 Reserved CHAR8 FspProducerld 6 UINT32 FspProducerRevision I NT32 FspProducerDataSize Signature FSPP HeaderLength HeaderRevision Reserved PatchEntryNum Patch FVBASE at end of FV Patch module patchable PCD VpdBase Reference the table being generated to prevent the optimizer from removing the data structure from the executable return VOID amp mTable After that we need create INF file and use USER_ DEFINED as
32. yte of the file is also the last byte of the firmware volume See UEFI PI Specification 32 References ACPI Advanced Configuration and Power Interface vesion 6 0 www uefi org COREBOOT coreboot firmware www coreboot org EDK2 UEFI Developer Kit www tianocore org EDKII specification A set of specification describe EDKII DEC INF DSC FDF file format as well as EDKII BUILD http tianocore sourceforge net wiki EDK_II_ Specifications FSP Intel Firmware Support Package http www intel com content www us en intelligent systems intel firmware support package intel fsp overview html FSP EAS FSP External Architecture Specification http www intel com content www us en embedded software fsp fsp architecture spec v 1 1 html FSP Consumer Yao Zimmer Rangarajan Ma Estrada Mudusuru A _Tour_Beyond_BIOS_ Using the_Intel_Firmware_Support_Package_with_the_EFI_Develop er_Kit_II_ FSP1 1 http firmware intel com UEFI Unified Extensible Firmware Interface UEFD Specification Version 2 5 www uefi org UEFI Book Zimmer et al Beyond BIOS Developing with the Unified Extensible Firmware Interface 2 edition Intel Press J anuary 2011 UEFI Overview Zimmer Rothman Hale UEFI From Reset Vector to Operating System Chapter 3 of Hardware Dependent Software Springer February 2009 UEFI PI Specification UEFI Platform Initialization PI Specifications volumes 1 5 Version 1
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