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P89C669 USER MANUAL - NXP Semiconductors

1. lt 2 S Slave Address R W A DATA A DATA A A P e 0 Write Data Transferred 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 55 Format in the master transmitter mode 6 7 7 MASTER RECEIVER MODE In the master receiver mode the data are received from a slave transmitter The transfer initialized as the same as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to IC Data Register I2DAT The SI bit must be cleared before the data transfer can continue 73 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status code are 40H 48H or 38H For slave mode the possible status code are 68H 78H or BOH Refer to Table 19 for details 4 Em S Slave Address R A DATA A DATA A P R 0 Write Data Transferred 1 Bead n By
2. Transition Detector CONTROL EXEN2 Figure 38 Timer 2 in Baud Rate Generator Mode The baud rate generation mode is like the auto reload mode when a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in modes 1 and 3 are determined by Timer 2 s overflow rate given below Modes 1 and 3 Baud Rates Timer 2 Overflow Rate 16 The timer can be configured for either timer or counter operation In many applications it is configured for timer operation C T2 0 Timer operation is different for Timer 2 when it is being used as a baud rate generator Usually as a timer it would increment every machine cycle i e 1 6 the oscillator frequency As a baud rate generator it increments at the oscillator frequency Thus the baud rate formula is as follows Modes 1 and 3 Baud Rates Oscillator Frequency 16 X 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L The content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer The Timer 2 as a baud rate generator mode is valid only if RCLK and or TCLK 1 in T2CON register Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Thus the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Also if the EXEN2 T2 external enable flag is set a 1 to 0 transition in T2EX Timer counter 2
3. cpsi ceso ecr On WEITE TO ccAP4L RESET 0 0 0 0 0 0 0 0 0 0 0 0 0L WAIE is CCAPnH CCAPnL MODULE 4 1 0 ENABLE 16 BIT COMPARATOR MERE o o p RESET CH CL PCA TIMER COUNTER ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn e A 0 0 1 0 Figure 74 PCA Watchdog Timer Module 4 only Module 4 can be configured in either compare mode and the WDTE bit in CMOD must also be set The user s software then must periodically change CCAP4H CCAP4L to keep a match from occurring with the PCA timer CH CL This code is given in the WATCHDOG routine shown above In order to hold off the reset the user has three options 1 periodically change the compare value so it will never match the PCA timer 2 periodically change the PCA timer value so it will never match the compare values or 3 disable the watchdog by clearing the WDTE bit before a match occurs and then re enable it The first two options are more reliable because the watchdog timer is never disabled as in option 3 If the program counter ever goes astray a match will eventually occur and cause an internal reset The second option is also not recommended if other PCA modules are being used Remember the PCA timer is the time base for all modules changing the time base for other modules would not be a good idea Thus in most applications the first solution is the best option 95 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51
4. MXCON Address FFh 51MX Extended SFR Space Not bit addressable T 6 5 4 3 2 1 0 Reset Value 00h EAM ESMM EIFM BIT SYMBOL FUNCTION MXCON 7 3 Reserved Programs should not write a 1 to these bits MXCON 2 EAM Enables Extended Addressing Mode This bit determines whether code and data addressing beyond 64 kB is allowed or not When O all addressing on chip and off chip is limited to 64 kB each of code and data When 1 P89C669 addressing capabilities are extended beyond boundary of 64 kB up to 8 MB each of code and data and upper address bits are multiplexed on Port 2 for external code and or data accesses Refer to the External Bus section for additional details EAM must be set to EAM 1 if at least one of the next two statements is true there is an executable code or constant s in CODE space above 64kB address of data byte that has to be accessed in HDATA is above 64kB MXCON 1 ESMM Enables the Extended Stack Memory Mode When ESMM 0 the Stack Pointer is 8 bits in width and the stack is located in the IDATA memory space When ESMM 1 the Stack Pointer is increased to 16 bits in width and the stack may be located anywhere in the EDATA space ESMM is independent of EAM and EIFM bits MXCON 0 EIFM Enables the Extended Interrupt Frame Mode When EIFM 0 an interrupt service will cause only the lower 16 bits of the PC to be pushed onto the stack and an RETI instruction will rest
5. Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 19 Master Receiver Mode STATUS STATUS OF THE APPLICATOPN SOFTWARE RESPONSE NEXT ACTION TAKEN BY I2C CODE I2C BUS IPSTAT HARDWARE TOFROMDDAT TODCON HARDWARE A START condition has been Load SLA R x x transmitted SLA R will be transmitted ACK bit will be received condition has been transmitted Arbitration lost in NOT ACK bit SLA R has been transmitted ACK has been received SLA R has been transmitted NOT ACK has been received Data byte has been received ACK has been returned Data byte has been received ACK has been returned Load SLA W no I2DAT action or no I2DAT action no I2DAT action or no
6. F8h Bit addressing allows direct control and testing of bits in those SFRs All 51MX devices also have additional 128 bytes of extended SFRs as discussed in the 51MX Architecture Reference Figures 8 and 9 show the SFR and the Extended SFR maps for P89C669 part 1 9 2 A 3 B 4 C 5 D MEM EEE ent ew Cone foca cows oon CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 econ GOD cose CAPT conem CORPUS conus Pew L Ld o E o EE 0 0l IPOH Ew O z pa wes senj 1 T Bit Addressable SFRs Figure 8 Standard SFR map for the P89C669 Figure 9 shows the extended SFR map for the P89C669 17 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM T Bit Addressable SFRs Figure 9 Extended SFR map for the P89C669 2 4 EXTERNAL DATA MEMORY XDATA The XDATA space on the 51MX is the same as the 64 kB external data memory space on the classic 80C51 On chip XDATA memory can be disabled under program control via the EXTRAM bit in the AUXR register Accesses above implemented on chip XDATA will be routed to the external bus by default If on chip XDATA memory is disabled all XDATA accesses will be routed to the external bus P89C669 has 768 bytes of on chip XDATA 2 5 HIGH DATA MEMORY HDATA The 51MX architecture supports up to an 8 MB data memo
7. Figure 52 C Slave Address Register 6 7 3 I C CONTROL REGISTER The CPU can read and write this register There are two bits affected by hardware SI bit and STO bit SI bit is set by hardware and STO bit is cleared by hardware CRSEL determines the SCL frequency when the I C is in master mode in slave mode this bit is ignored and will automatically synchronize with any clock frequency up to 400kHz from master IC device When CRSEL 1 I C uses Timer1 overflow rate divided by 2 for IC clock rate Timer 1 is in 8 bit auto reload mode Mode 2 Data rate of C Timer overflow rate 2 fosc 8 256 reload value If fose 12MHz reload value is 0 255 so I C data rate range is 5 86 1500kbits sec Note To run the I C at a rate not to exceed 1Mbits sec at fosc 12MHz the smallest reload value is 254 which will result in a data rate of 750Kbits sec When CRSEL 0 I C uses internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 STA bit is START flag Setting this bit causes I C entering master mode and transmitting a START condition or transmitting a repeated START condition when it is already in master mode STO bit is STOP flag Setting this bit causes I C transmitting a STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the 1 C bus if it is in master mode and
8. INTEGRATED CIRCUITS USER MANUAL P89C669 USER MANUAL Preliminary 2003 Sep 16 Supersedes data of 2003 Jul 30 Philips PHILIPS Semiconductors FA l LI DS Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Lo INTRODUCTION Stee erisso essi b aa RR CORR SAPE NRI SM MEN aro PRISE SUAE oE Soone Ee aeS oia Seaia as 3 1 1 The SIMX CPU CORE Latus petii r teas ae en bcce mt a aiai 3 1 2 P89C669 microcontrollers sites rtv etapa Vesvecadaveeaedusaeasvaspanadalnsaeeesnneadtasoesndeeasaees 3 1 3 P89C069 Logic Symbol sci aesteetepes cohetes o ar ea aa eese ke dE tes 6 LA P89C669 Block Diagram oit SERV EUR Ia ULTIO R E R N 7 PNE outs Organizati Nn PR 8 2 1 Programimer s Models and Memory Maps aset sense sortes sls estt ee pe sven cule Ne guess oee Deo aee 8 2 2 Data Memory DATA IDATA and EDATA e eeeeseeeseeeeee eene eene eene nennen neni 9 2 2 1 Registers RO dq 10 22 2 Bit Addressable RAM eean erte e E E Ue uus E S a E 10 2 2 3 Extended Data Memory EDATA ssssssesssessessrsessrrsrrrsreseesresreseesreseeeseeseesrreseses 11 2 2 4 Mire mM ME HE PE 11 2 2 5 MX Control Register M XC ON ssssssssessesssesssssessseessresseessesessessseessesseesseessres 12 2 2 6 General Purpose RAM teet dde SUIS UI ann a PRECES RU a i s 14 2 3 Special Function Registers SERS
9. 8 LE C 099 re 8 CE 6 6 UARTS The P87C51Mx2 includes two enhanced UARTs with one independent Baud Rate Generator They are compatible with the enhanced UART based on the 8xC51Rx except the baud rate generator The first UART UART 0 can select Timer 1 overflow Timer 2 overflow or the independent Baud Rate Generator The second UART UART 1 uses the independent Baud Rate Generator only to generate its baud rate Besides the baud rate generation enhancements over the standard 8051 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The two UARTs are called UART 0 and 1 to correspond to the serial port assignments Each serial port can be operated in one of 4 modes 6 6 1 MODE 0 Serial data enters and exits through RxD n TxD_n outputs the shift clock Only 8 bits are transmitted or received LSB first The baud rate is fixed at 1 6 of the CPU clock frequency UART configured to operate in this mode outputs serial clock on TxD line no matter wether it sends or receives data on RxD line 6 6 2 MODE 1 10 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first and a stop bit logical 1 When data is received the stop bit is stored in RB8 0 RB8 1 in Special Function Register SOCON S1CON For UART 0 the 55 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller w
10. Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low 40 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg LSB Value DF DE DD DC DB DA D9 D8 PCA Counter High PCA Counter Low Data Pointer 2 bytes Data Pointer High Data Pointer Low Extended Data Pointer Low Extended Data Pointer Middle Extended Data Pointer High I C Control Register EN CRSEL IC Data Register 12C Clock Generator High Register 12C Clock Generator Low Register AF AE AD AC AB AA A9 A8 Interrupt Enable 1 ES1 BF BE BD BC BB BA B9 B8 Interrupt Priority PSO OLDER HOE Uh 1 PPCH PT2H S PTIH PxiH PTOH PXOH Interrupt Priority 1 PS1 Interrupt Priority 1 High PS1H PI2CH PS1TH PSOTH PS1RH 41 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg LSB Value pu 87 86 85 84 83 82 81 80 or noe Aes T 7 T 99 T e T Ts 97 96 95 94 93 92 91 90 A7 A6 A5 A4 A3 A2 A1 AO AD14 ADA13 AD20 AD11 AD10 AD9
11. TO or T1 In this function the external input is sampled once every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in the register in the machine cycle following the one in which the transition was detected Since it takes 2 machine cycles 12 oscillator periods for 1 to 0 transition to be recognized the maximum count rate is 1 12 of the oscillator frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select The Timer or Counter function is selected by control bits C T in the Special Function Register TMOD These two Timer Counters have four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 are the same for both Timers Counters Mode 3 is different The four operating modes are described in the following text TMOD Address 89h 7 6 5 4 3 2 1 0 Not bit addressable TIGATE T1C T T1iM1 T1MO TOGATE TOC T TOM1 TOMO Reset Source s Any source Reset Value 00000000B T1 TO Bits controlling Timer1 TimerO GATE Gating control when set Timer Counter x is enabled only while INTx pin is high and TRx
12. control pin is set when cleared Timer x is enabled whenever TRx control bit is set C T Gating Timer or Counter Selector cleared for Timer operation input from internal system clock Set for Counter operation input from Tx input pin M1 MO OPERATING MODE 0 0 8048 Timer TLx serves as 5 bit prescaler 1 16 bit Timer Counter THx and TLx are cascaded there is no prescaler 0 2 8 bit auto reload Timer Counter THx holds a value which is to be reloaded into TLx each time it overflows 1 1 3 Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by Timer 1 control bits 1 1 3 Timer 1 Timer Counter 1 stopped Figure 27 Timer Counter Mode Control Register TMOD 46 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM TCON Address 88h 7 6 5 4 3 2 1 0 Bit addressable TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset Source s Any reset Reset Value 00000000B BIT SYMBOL FUNCTION TCON 7 TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to Timer 1 Interrupt routine or by software TCON 6 TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TCON 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cle
13. trigger input will set EXF2 T2 external flag but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Therefore when Timer 2 is in use as a baud rate generator T2EX can be used as an additional external interrupt if needed When Timer 2 is in the baud rate generator mode one should not try to read or write TH2 and TL2 Under these conditions a read or write of TH2 or TL2 may not be accurate The RCAP2 registers may be read but should not be written to because a write might overlap a reload and cause write and or reload errors The timer should be turned off clear TR2 before accessing the Timer 2 or RCAP2 registers Table 13 shows commonly used baud rates and how they can be obtained from Timer 2 54 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 5 5 SUMMARY OF BAUD RATE EQUATIONS Timer 2 is in baud rate generating mode If Timer 2 is being clocked through pin T2 P1 0 the baud rate is Baud Rate Timer 2 Overflow Rate 16 If Timer 2 is being clocked internally the baud rate is Baud Rate fosc 16 x 65536 RCAP2H RCAP2L Where fosc Oscillator Frequency To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as RCAP2H RCAP2L 65536 fosc 16 x Baud Rate Table 13 Timer 2 Generated Commonly Used Baud Rates Baud Rate Osc Freq Timer 2 RCAP2H RCAP2L Ba M ECL S 89 tee
14. 1 29 1 1 39 1 1 49 1 1 59 1 1 69 1 1 79 2 DEC ADD ADDC ORL ANL XRL MOV R1 A R1 A R1 A R1 A R1 A R1 R1 d8 1 2A 1 1 3A 1 1 4A 1 1 5A 1 1 6A 1 1 7A 2h DEC ADD ADDC ORL ANL XRL MOV R2 A R2 A R2 A R2 A R2 A R2 R2 d8 2B 1 1 3B 1 1 4B 1 1 5B 1 1 6B 1 1 7B 2 1 DEC ADD ADDC ORL ANL XRL MOV R3 A R3 A R3 A R3 A R3 R3 d8 2C 1 4 3C 1 1 4C 1 1 1 1 7C 2 1 DEC ADD ADDC ORL XRL MOV A R4 A R4 A R4 A R4 R4 d8 1 1 3D 1 1 4D 1 1 141 7D 2 1 ADDC XRL MOV A R5 A R5 R5 d8 1 1 7E 2 1 XRL MOV A R6 R6 d8 1 1 7F 2 1 XRL MOV A R7 R7 d8 30 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 82 2 2 92 2 2 A2 2A B2 2H C2 ANL MOV MOV CPL C bit bit C C bit bit 84 1 4 94 2H A4 1 4 B4 3 2 C4 1 4 D4 DIV SUBB MUL CJNE SWAP AB A d8 AB A d8 rel8 A Table 7 51MX operation code chart part 2 80 2 2 90 3 2 A0 2 2 BO 2 2 CO 2 2 DO 2 2 EO 1 2 FO 1 2 SJMP MOV ORL ANL PUSH POP MOVX MOVX rel8 DPTR d16 C bit C bit dir dir A DPTR DPTR A 81 2 2 91 2 2 A1 2 2 B1 2 2 C1 2 2 D1 2 2 E1 2 2 F1 2 2 AJMP ACALL AJMP ACALL AJMP ACALL AJMP ACALL addr11 addr11 addr11 addr11 addr11 addr11 addr11 addr11 2 1 D2 2A E2 1 2 F2 1 2 SETB MOVX MOVX bit A RO R0 A CLR bit CLR C 1 1 D3 SETB C DA A 1 1 ES 1 2 F8 1 2 MOVX MOVX A R1 R1 A 1 1 E4 1 1 F4 1 1
15. 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM IENO Address A8h Bit addressable Reset Value 00h BIT SYMBOL IENO 7 EA IENO 6 EC IENO 5 ET2 IENO 4 ESO ESOR IENO 3 ET1 IENO 2 EX1 IENO 1 ETO IENO O EXO 7 6 5 4 3 2 1 0 EA EC ET2 ESO ESOR ET1 EX1 ETO EXO FUNCTION Interrupt Enable Bit EA 1 interrupt s can be serviced EA 0 interrupt servicing disabled PCA Interrupt Enable bit Timer 2 Interrupt Enable Serial Port 0 Combined Tx Rx Interrupt Enable SOSTAT 5 0 Serial Port 0 Receive Interrupt Enable SOSTAT 5 1 Timer1 Overflow Interrupt Enable External Interrupt 1 Enable Timer 0 Overflow Interrupt Enable External Interrupt 0 Enable Figure 20 Interrupt Enable Register IENO IEN1 Address E8h Bit addressable Reset Value 00h BIT SYMBOL IEN1 7 5 IEN1 4 EI2C IEN1 3 IEN1 2 ES1T IEN1 1 ESOT IEN1 0 ES1 ES1R El2c E ES1T ESOT ESIESIR FUNCTION Reserved for future use Should be set to 0 by user programs IC Interrupt Enable Reserved for future use Should be set to 0 by user programs If STSTAT 5 1 it is Serial Port 1 Transmit Interrupt Enable If S1STAT 5 0 this interrupt is disabled anyway If SOSTAT 5 1 it is Serial Port O Transmit Interrupt Enable If SOSTAT 5 0 this interrupt is disabled anyway Ser
16. 23 bit value into the EPTR Load a 16 bit address into the F Load a 23 bit address into the Program oe Counter from the EET Counter from the Stack Add an immediate data value from 1 to 4 to the specified Universal Pointer This is a 24 bit addition C ET Load the Accumulator with the value from Logically OR Register n to the bens the Universal Memory Map at the address ORL ARN Accumulator EMOV A PRi disp formed by PRO or PRiplus the displacement a value from 0 to 3 Load the Universal Memory Map address Logically AND Register n to the n formed by PRO or PR1 plus the ANGS NAMN Accumulator EMOV PRi disp A displacement a value from 0 to 3 with the contents of the Accumulator XRL A Rn Exclusive OR Register n to the Accumulator ADD PRi data2 27 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 3 1 INSTRUCTION SET SUMMARY The following table summarizes the entire 51MX instruction set The instructions are grouped by the type and instructions that share operand formats are combined 51MX extended instructions and operand combinations are designated by bold text Table 5 51MXilnstruction set summary Data Movement Arithmetic amp Logic Program Control Bit Operations A Rn A Rn A direct A direct A Ri A QRi A data A data Rn A A Rn direct Rn bit rel Rn data direct direct A Ri direct Rn direct direct DPT
17. 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM The following shows the code for initializing the watchdog timer INIT WATCHDOG MOV MOV MOV ORL CCAPM4 04Ch Module 4 in compare mode CCAP4L 0FFh Write to low byte first CCAP4H 0FFh Before PCA counts up to FFFFh these compare values must be changed CMOD 040h Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD CALL the following WATCHDOG subroutine periodically CLR MOV MOV SETB RET EA Hold off interrupts CCAP4L 00 Next compare value is within 255 counts of current PCA timer value CCAP4H CH EA Re enable interrupts This routine should not be part of an interrupt service routine because if the program counter goes astray and gets stuck in an infinite loop interrupts will still be serviced and the watchdog will keep getting reset Thus the purpose of the watchdog would be defeated Instead call this subroutine from the main program within 2 18 count of the PCA timer 96 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 7 FLASH MEMORY GENERAL DESCRIPTION The P89C669 Flash memory augments EPROM functionality with in circuit electrical erasure and programming The Flash can be read and written as bytes The Chip Erase operation will erase the entire program memory The Block Erase function can erase any Flas
18. E utn doli A OE cakes 42 632 uldie Mode ee eR eat et Ree A O S 42 6 3 3 Power Down Mode ser P t UG RIS a a a EN aaas 42 6 24 Power On Flafi neninn dis tsp sutfs ecd uitia t bob ede 43 6 4 Timers Counters 0 and 1 eee atre m re e TAUN ue Rea URB UE PA STU EEEE Ue eg PU bun 43 6 4 1 Mod 0 oae ous dad ada A Toa MENT pu E Ani HCM np dq E MEME 45 B I2 NOU e esce suaNoM ux Pai t csapts telae tie A S 46 64 3 Mode cancer concerned sak tutes de agn A edet E EN n eA E Trete 46 On MEMMCI M 47 2 2003 Sep 16 4 10 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 5 6 6 6 7 6 8 6 9 6 10 j ngere E DP E 47 6 5 1 Capture MOUG es anenee a sacs eli touto Gods o ots ct td s e def 49 6 5 2 Auto Reload Mode Up or Down Counter essere 49 6 5 3 Prosrammable GlIoCk QUE oett erbe get ean a etse Roe le MIS ase oed a e 51 6 5 4 Baud Rate Generator Mode For UART O0 Serial Port 0 sssss 51 6 5 5 Summary OF Baud Rate Equations 36 coperta dasa ole e Ue Ea epa e Rot eS 53 TARS a a e E A A aC te I oae 53 6 6 1 Mode Oiar are err Rare E ne Rae E A E t E A RE E 53 6 6 2 Mode bust myene a i a a a a tds 53 6 6 3 Mode 2er ea aaa a e aA A TEE aTa Ea a ETE A E a a eS 54 66A Mode 3 siere iiite ia nue Hassles es a eeii atie ie oet deo tags 54 6 6 5 SFR and Extended SFR Spaces cs eto asm
19. Extended SFRs IDATA includes DATA Special Function 556 Byte On Chip Register hice ee Data Memory stack and indirect addressing DATA 64kB l On Chip Code 128 Byte On Chip 00 0300h Data Memory XDATA 00 02FFh Memory stack direct and indirect 768 Bytes On Chip addressing Data Memory Four Register Banks 00 0000h RO R7 00 0000h 8 MB Code Data Memory Space 8 MB 64 kB External Memory Space DATA IDATA EDATA Data Memory Space XDATA HDATA Figure 3 P89C669 programmer s model and memory map 10 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Detailed descriptions of each of the various 51MX memory spaces may be found in the following summary DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space 00h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it EDATA Extended Data This is a superset of DATA and IDATA areas P89C669 has 1280 bytes of SRAM in EDATA memory The added area may be accessed only as Stack and via indirect addressing using Universal Pointers The Stac
20. Figure 5 Extended return address storage on the stack The second stack option Extended Stack Memory Mode allows for stack extension beyond the 256 byte limit of the classic 80C51 family Stack extension is accomplished by increasing the Stack Pointer to 16 bits in size and allowing it to address the entire EDATA memory rather than just the standard 256 byte internal data memory Stack extension has no effect on the data that is stored on the stack it will continue to be stored as shown on in figures 4 and 5 The Extended Stack Memory Mode is enabled by setting the ESMM bit in the MXCON register If the Stack Pointer is not initialized by software the stack will begin at on chip RAM address 8 just as for the 80C51 Also note that in Extended Stack Memory Mode P89C669 part has 1024 bytes of RAM on the top of DATA IDATA space available for the stack The stack mode bits ESMM and EIFM are shown in Figure 6 Note that the stack mode bits are intended to be set once during program initialization and not altered after that point Changing stack modes dynamically may cause stack synchronization problems 2 2 5 MX CONTROL REGISTER MXCON MX family of microcontrollers was developed with an idea to provide 80C51 users with the part that will allow applications to grow in different directions While improving a number of characteristics it had to keep full compatibility with its predecessors Two major areas for improvement were identified as microcon
21. I2DAT action or No I2DAT action or no I2DAT action or no I2DAT action or Read data byte read data byte Read data byte or read data byte or read data byte SLA W will be transmitted I2C will be switches to master transmitter mode I2C will be released it will enter a slave mode A START condition will be transmitted when the bus becomes free Data byte will be received NOT ACK bit will be returned Data byte will be received ACK bit will be returned Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset Data byte will be received NOT ACK bit will be returned Data byte will be received ACK bit will be returned Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 20 Slave Receiver Mode STATUS STATUS OF THE CODE 12C BUS I2STAT HARDWARE Own SLA W has been received ACK has been received Arbitration lost in SLA R Was master Own SLA W has been received ACK returned General call address 00H has been received ACK has been returned Arbitration lost in SLA R
22. I2DAT has been No I2DAT action Switched to not addressed SLA mode no transmitted AA 0 or recognition of own SLA or General call ACK has been address received Switched to not addressed SLA mode Own no I2DAT action or slave address will be recognized General call address will be recognized if IZADR 0 1 Switched to not addressed SLA mode no recognition of own SLA or General call no I2DAT action or address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 A START condition will be transmitted when the bus becomes free no I2DAT action For more information about I7C interface refer to I C specification 6 8 WATCHDOG TIMER The watchdog timer subsystem protects the microcontroller system from incorrect code execution over a longer period of time by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count For the P87C51Mx2 the watchdog timer is compatible with the watchdog timer in 89C51Rx2 In addition it has a prescaler of up to 1024 times default without prescaling that supports longer watchdog timeout The WDT consists of a 14 bit counter and Watchdog Timer Reset WDTRST SFR The prescaler is determined by the watchdog control WDCON SFR in the MX extended SFR space
23. IENO or IEN1 respectively The IENO register also contains a global disable bit EA which disables all interrupts at once Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the IPO IPOH IP1 and IP1H registers An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source So if two requests of different priority levels are received simultaneously the request of higher priority level is serviced Priority level 00 is the lowest possible one while priority level 11 is the highest possible one For example priority level of TimerO Interrupt is determined with bits PTOH and PTO Content PTOH 1 and PTO 0 determine level 10 i e level 2 If requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level Table 10 summarizes the interrupt sources flag bits vector addresses enable bits priority bits polling priority and whether each interrupt may wake up the CPU from Power Down mode or not Table 10 Summary of Interrupts Flag Bit s Address Enable Bit s Priority Priority Wakeup mero
24. JBC JB JNB bit rel8 bit rel8 bit rel8 02 5 4 12 5 4 42 3 2 52 3 2 62 3 2 3 3 EJMP ECALL ORL ANL XRL addr23 addr23 dir A dir A dir A 43 4 3 53 4 3 63 4 3 73 2 2 ORL ANL XRL JMP dir d8 dir d8 dir d8 A EPTR 05 3 2 15 3 2 25 3 2 35 3 2 45 3 2 55 3 2 65 3 2 75 4 3 INC DEC ADD ADDC ORL ANL XRL MOV dir dir A dir A dir A dir A dir A dir dir d8 48 2 4 58 2 4 68 2 4 EMOV EMOV ADD A PR0 0 QPRO 0 A PRO 4 2 49 59 2 4 EMOV EMOV ADD PR0 1 A PRO 1 2 4 5A 2 4 EMOV EMOV ADD A PR0 2 A PRO 2 5B 2 4 EMov EMOV ADD A L PR0 3 A PRO 3 5C uem EMOV ADD PNTIOA PR1 4 5D 2 4 EMOv EMOV ADD PR1 1 A PR1 1 5E eo EMOV ADD PRIA2A PR1 2 5F d EMOV ADD A PR1 3 PRI3A PR1 3 32 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 9 51MX operation code chart part 4 90 5 4 A0 3 3 BO 3 3 CO 3 3 DO 3 3 EO 2 4 FO 2 4 MOV ORL ANL PUSH POP MOVX MOVX EPTR d23 C bit C bit dir dir A EPTR EPTR A MOV bit C 93 2 4 MOVC A A EPTR 85 4 3 95 3 2 B5 4 3 C5 3 2 D5 4 3 E5 3 2 F5 3 2 MOV SUBB CJNE XCH DJNZ MOV MOV dir dir A dir A dir rel8 A dir dir rel8 A dir dir A 86 3 3 A6 3 3 MOV MOV dir ORO OQ RO dir 87 38 A7 3 3 MOV MOV dir R1 QR1 dir 88 3 3 A8 3
25. PC value used is that of the instruction following MOVC MOVX DPTR A The active DPTR points to an address in the 64 kB XDATA memory MOVX A DPTR The active DPTR points to an address in the 64 kB XDATA memory Replaces the lower 16 bits of the Program Counter with a 16 bit address from the Stack This RET instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary When the Extended Interrupt Frame Mode is not enabled this instruction replaces the lower 16 bits of the Program Counter with a 16 bit address from the Stack This will cause a 64 kB boundary to RETI be crossed if the instruction is located such that the next instruction in sequence is across the boundary If the extended interrupt frame mode is enabled a 23 bit address is loaded into the PC from the stack LCALL addri6 Replaces the lower 16 bits of the Program Counter with the 16 bit address This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary Replaces the lower 16 bits of the Program Counter with the 16 bit address This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary ACALL addr11 LJMP addr16 26 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 4 Enhancem
26. TL2 and TH2 in this mode Even when a capture event occurs from T2EX the counter keeps on counting T2 pin transitions or fo sc 6 pulses Since once loaded contents of RCAP2L and RCAP2H registers are not protected once Timer2 interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs Otherwise the next falling edge on T2EX pin will initiate reload of the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to previously reported interrupt 6 5 2 AUTO RELOAD MODE UP OR DOWN COUNTER In the 16 bit auto reload mode Timer 2 can be configured as either a timer or counter via C T2 in T2CON then programmed to count up or down The counting direction is determined by bit DCEN Down Counter Enable which is located in the T2MOD register see Figure 34 When reset is applied DCEN 0 and Timer 2 will default to counting up If the DCEN bit is set Timer 2 can count up or down depending on the value of the T2EX pin Figure 36 shows Timer 2 counting up automatically DCEN 0 51 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM p C T2 0 es TL2 TH2 8 bit 8 bit A C T2 1 T2 Pin Timer 2 Interrupt Transition Detector RCAP2L RCAP2H T2EX Pi ae oo l CONTROL EXEN2 Figure 36 Timer 2 in Auto Reload
27. edge that a capture input will be active on The CAPN bit enables the negative edge and the CAPP bit enables the positive edge If both bits are set both edges will be enabled and a capture will occur for either transition The last bit in the register ECOM CCAPMn 6 when set enables the comparator function There are two additional registers associated with each of the PCA modules They are CCAPnH and CCAPnL and these are the registers that store the 16 bit count when a capture occurs or a compare should occur When a module is used in the PWM mode these registers are used to control the duty cycle of the output 89 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM CF CR ccr CCF3 ccm ccri ccro CCON D8h Z He E e CE pM IENO 6 IENO 7 EC EA TO t i PRIORITY i SOLE ES DECODER Jm gt a ae 3 CMOD 0 ECF CCAPMn 0 Figure 66 PCA Interrupt System CMOD 7 6 5 4 3 2 1 0 Address D9H CIDL WDTE CPS1 CPSO ECF Not bit addressable Reset Value 00h BIT SYMBOL FUNCTION CMOD 7 CIDL Counter Idle Control CIDL 0 programs the PCA Counter to continue functioning during Idle Mode CIDL 1 programs it to be gated off during idle CMOD 6 WDTE Watchdog Timer Enable WDTE 0 disables watchdog timer function on m
28. emp mo owe trouNoy Pona Pon 2 Wo E IM SML EN a ee NC E Serial Port 0 Tx and Rx TI 0 amp RI NILUM GEIELRGRTOTE STO Wigan ESOESOR ll aA Serial Port 0 Rx RO IENO 4 Timer 2 Interrupt TF2 EXF2 002Bh ET2 IENO 5 IPOH 5 IPO 5 Pe Mo PCA interrupt CF CCFn 0033h EC IENO 6 IPOH 6 IPO 6 S Serial Port 1 Tx and Rx2 TI 1 amp RI 19 REE er ee a en Serial Port 1 Rx IEN1 0 Serial Port 0 Tx 003Bh ESOT IEN1 1 IP1H 1 IP1 1 Serial Port1 Txt Port 1 Tx n 1 0043h ES1T IEN1 2 IP1H 2 IP1 2 a Sn XAR cul l C Interrupt 005Bh EI2C IEN1 4 IP1H 4 IP1 4 lowest ad SOSTAT 5 0 selects combined Serial Port 0 Tx and Rx interrupt SOSTAT 5 1 selects Serial Port 0 Rx interrupt only and TX interrupt will be different see Note 3 below S1STAT 5 0 selects combined Serial Port 1 Tx and Rx interrupt S1STAT 5 1 selects Serial Port 1 Rx interrupt only and TX interrupt will be different see Note 4 below This interrupt is used as Serial Port 0 Tx interrupt if and only if SOSTAT 5 1 and is disabled otherwise This interrupt is used as Serial Port 1 Tx interrupt if and only if STSTAT 5 1 and is disabled otherwise If SOSTAT O 1 the following Serial Port 0 additional flag bits can cause this interrupt FE 0 BR 0 OE O If S1STAT O 1 the following Serial Port 1 additional flag bits can cause this interrupt FE 1 BR 1 OE 1 36 20083 Sep
29. extended addressing and are modified versions of classic 80C51 instructions These instructions allow access to the expanded SFR space These are not actually new instructions but are classic 80C51 instructions whose function are altered by the A5h opcode Operand Definitions Used in the Tables addr11 11 bit address bit addressable bit d8 8 bit immediate data addri6 16 bit address dir direct address d16 16 bit immediate data addr23 23 bit address rel8 8 bit relative address d23 23 bit immediate data 29 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 6 51MX operation code chart part 1 12 3 2 22 1 2 32 1 2 42 2H 52 2A 62 2H 72 2 2 LCALL RET RETI ORL ANL XRL ORL addr16 dir A dir A dir A C bit 13 1 1 23 1 1 43 3 2 53 3 2 63 3 2 73 1 2 RRC ORL ANL XRL JMP A dir d8 dir d8 dir d8 A DPTR 2 1 2 1 54 2 1 64 2 1 74 2 1 DEC ANL XRL MOV A d8 A d8 A d8 2 1 55 2 1 65 2 1 75 3 2 DEC ANL XRL MOV dir i i i A dir A dir dir d8 1 1 1 56 1 1 66 1 1 76 2 DEC ORL ANL XRL MOV RO A RO A RO A RO A RO A RO RO d8 1 1 27 1 1 37 1 1 47 1 1 57 1 1 67 14 77 2 DEC ADD ADDC ORL ANL XRL MOV RI1 A R1 A R1 A R1 A R1 A R1 R1 d8 1 1 28 1 1 38 1 71 48 1 1 58 1 1 68 1 71 78 2 DEC ADD ADDC ORL ANL XRL MOV RO A RO A RO A RO A RO A RO RO d8 1
30. fa MF ul EN ice PRATES TG igsc BRATE 16 UART 1 has the same receive and transmit baud rate Table 16 Baud Rate Generation for UART 1 58 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM BRGCON Address 85h MX Extended SFR Space Not bit addressable Reset Value 00h BIT SYMBOL BRGCON 7 2 BRGCON 1 SOBRGS BRGCON O BRGEN 7 6 4 3 2 1 0 SOBRGS BRGEN FUNCTION Reserved for future use Should be set to 0 by user programs For UART 0 only Used in combination with the RCLK and TCLK in deciding the receive and transmit baud rates to UART 0 in modes 1 amp 3 see Table 15 for details 0 Disable Baud Rate Generator 1 Enable Baud Rate Generator Baud rate SFRs BRGR1 and BRGRO can only be written when BRGEN is 0 Figure 41 BRGCON Register Timer 1 Overflow Baud Rate Generator SMOD1 0 SOBRGS 1 O Timer 2 Overflow QUARTO Transmit Baud Rate Modes 1 and 3 RCLK 1 TCLK 20 TCLK 1 SOBRGS 0 UART 0 Receive Baud Rate Modes 1 and 3 UART 1 Receive and Transmit Baud Rate Modes 1 2 and 3 Figure 42 Baud Rate Generations for UART 0 Modes 1 3 and UART 1 Modes 1 2 3 59 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontrolle
31. i s epesteseeesn esed ttes See e sees eS EP hee RUINIS ROPA M RU ER e Eee qu 15 2 4 External Data Memory CXDATA ssoccscsisissascasasessaccessaccesasdevednasvercceesaccsaataseessctessaceestscassandesse 16 2 High Data Memory DATA inedite eire ea i dpa ee eee 16 2 67 Program Memory CODE emnt mdi estate Tories necat ius E aE ERES 18 2 T Universal P Oite tects nies etd do Ado de deste edu i E E a doter cU utat E Dies 19 Do SIMX Instructions ores dor eo eoa eye RAP NOE UE RES ER CHE MY SR PER SERE PEYENR o ssia E Sca DIS Te UR iiaeie MESE Pe pe TU siss 24 3 1 Instr ction S t Summary edes tudo cest tui a a E a ee A E E E a 26 3 2 5IMX Operation Code Charts oe dace a ae teta qe Ae AA 27 NEED osiciBi eec S 32 4 1 Multiplexed External BUS eren e Pen IR RS PAESE ARE Iud ee asa e e esu euo cite EUR Pea SR p 32 5 T terrupt PEOCCSSWIE 2 iie dei eio Ho rk biv Ere redegi c eeu PeP e Voss oe dedV ida cea ako CR ba pU d Ray VERE S PESCE A Rd E baee 34 6 P89C669 Ports Power Control and Peripherals eere ecce ee eee eee ee eren eere seen ee en nae 38 6 1 Spectal Function KREIS LEDS ue ee cdpn ae pe diee t decode dde ED cR o addu 38 6 2 JP89 609 POI Lione beu lo nghiep ig eap atas od Ur aaa a DUIS ue dui assum NS 4 6 2 1 ION INK p a a A AE TE ER a NaS 41 ACE o E EEE EE E SE AEE E E A 42 6 3 P89C669 Low Power Modes un ctio ttt medion trend drania oiean eniras pasi rai s 42 6 3 1 DIOP Clock MOOS sinodoan a a a
32. ies M ERN LM Mp MUT eae RS EIE naf 54 6 6 6 Baud Rate Generator and Selection ed sca aches ol oxi taa pvo SE RUD id qe E NNUS 35 6 6 7 Eram BIEGD eoo tuendae utei EL tecta 58 6 6 8 Status RE SISter sisi 59 6 6 9 More A bout UART Mode Liniers iiaa E ir e E aS S 60 6 6 10 More About UART Modes 2 and 3 eeeeseesseeeeeeeeee eene tenente nnnen nn 61 6 6 11 Examples of UART Data Transfer Using Different Modes 61 6 0 12 Double a Be Ue a hss eom tete dba uet Emp adus aat Foren oec 62 6 6 13 Transmit Interrupts with Double Buffering eeeeeeeeeeeeneeenrenenns 63 6 6 14 The 9th Bit Bit 8 in Double Buffering sese 64 6 6 15 Multiprocessor Communications eese 64 6 6 16 Automatic Address Recognition eeeeeseeeseseeesee eene eene entente nnne nnne 64 I2 6 Serial TIM SCAG She Ge aeos scree vay outs e t tad tre tem Mus ned b tq eR 66 6 7 1 DE Data Res ister iste te een ea te usato di ec Qe dads 67 6 1 2 AWC Slave Address Re eis er 5o EN DINE Er RR ELO Ap s IS UR RD p E IURE 67 6 7 3 PG Control Register P 68 G4 TAC SAIS Resister eooe des IN COSE taies qu pei eti bu aie save sed OES det vi aset MIA iN QUE 69 6 7 5 PC SCL Duty Cycle Register I2SCLH and I2SCLL eeeeeeeeee 70 6 7 6 Master Transmitter Mod eost oe oO alana jet uars c
33. mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 A START condition will be transmitted when the bus becomes free 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 20 Slave Receiver Mode Continued STATUS STATUS OF THE APPLICATOPN SOFTWARE RESPONSE NEXT ACTION TAKEN BY I2C CODE IPSTAT 12C BUS HARDWARE TOFROMI2DAT TOI2CON HARDWARE Previously s addressed with Read data byteor x 0 Pata pyte wil sat a SN NOT ACK will General call Data has been received ACK has been read data byte x 1 Data byte will be received and ACK will be returned returned Previously Switched to not addressed SLA mode no addressed with Dn e recognition of own SLA or General call General call Data address has been received Switched to not addressed SLA mode Own NOT ACK has been read data byte slave address will be recognized General returned call address will be recognized if IDADR 0 1 Switched to not addressed SLA mode no recognition of own SLA or General call read data byte address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized G
34. must be set to start the timer The Clock Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in this equation OscillatorFrequency 2x 65536 RCAP2H RCAP2L Where RCAP2H RCAP2L the content of RCAP2H and RCAP2L taken as a 16 bit unsigned integer In the Clock Out mode Timer 2 roll overs will not generate an interrupt This is similar to when it is used as a baud rate generator 6 5 4 BAUD RATE GENERATOR MODE FOR UART 0 SERIAL PORT 0 When serial port 0 UART 0 doesn t use the independent baud rate generator SOBRGS 0 SOBRGS is BRGCON 1 bits TCLK and or RCLK in T2CON allow the serial port 0 UART 0 transmit and receive baud rates to be derived from either Timer 1 or Timer 2 refer to the section on UARTS for details Assume that SOBRGS 0 when TCLK 0 Timer 1 is used as the UART 0 transmit baud rate generator When TCLK 1 Timer 2 is used as the UART 0 transmit baud rate generator RCLK has the same 53 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM effect for the UART 0 receive baud rate With these two bits the serial port can have different receive and transmit baud rates Timer 1 Timer 2 or baud rate generator Figure 6 6 shows Timer 2 in baud rate generator mode TX RX Baud Rate See section Baud Rate Generator and Selection
35. n 1 Rx and Tx interrupts are separate SnSTAT 4 DBISEL_n Double buffering transmit interrupt select used only if double buffering is enabled DBMOD n set to 1 must be 0 when double buffering is disabled 0 There is only one transmit interrupt generated per character written to SnBUF 1 One transmit interrupt is generated after each character written to SnBUF and there is also one more transmit interrupt generated at the STOP bit of the last character sent i e no more data in the buffer Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO n When the first character is written the transmit interrupt is generated immediately after the SnBUF is written SnSTAT 3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame It is also set with BR n if a break is detected Must be cleared by software SnSTAT 2 BR n Break Detect flag is set if a character is received with all bits including STOP bit being logic 0 Thus it gives a Start of Break Detect on bit 8 for Mode 1 and bit 9 for Modes 2 and 3 The break detect feature operates independently of the UARTs and provides the START of Break Detect status bit that a user program may poll Cleared by software SnSTAT 1 OE n Overrun Error flag is set if a new character is received in the receiver buffer while it is still full i e when bit 8 of a new by
36. number of data bytes in record middle and low bytes of address of first byte in record high byte set via segment record rec type 04 function code for program code memory data bytes checksum End of File EOF no operation Format 00xxxx0lcc Where 00 number of data bytes in record XXXX required field but value is a don t care 01 function code for EOF ca checksum 100 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 24 List of Commands Record Types P89C669 Accepts in ISP Mode Commands Record type Function sent by host Write Functions Format nnxxxx03ffssddcc Where nn number of data bytes in record don t care 03 function code for write functions tf subfunction code SS selection code dd data if needed co checksum Subfunction Code z 01 Erase Blocks ff 01 SS high byte of block address dd middle byte of block address ssdd 0000 block 0 0020 block 1 0100 block 8 0120 block 9 0160 block 11 Subfunction Code 04 Erase Boot Vector Status Byte ff 04 ss don t care Subfunction Code 05 Program Security Bits ff 05 ss 00 program security bit 1 01 program security bit 2 02 program security bit 3 Subfunction Code 06 Program Special Cells ff 06 ss 00 program status byte 01 program boot vector middle 02 program boot vector hi
37. push the entire 23 bit Program Counter onto the stack as three bytes and the RETI instruction to pop all 23 bits as a return address as shown in Figure 5 The upper bit of the stack byte containing the most significant byte of the Program Counter is forced to a 1 to be consistent with Universal Pointer addressing Storing the full 23 bit Program Counter value is a requirement for systems that include more than 64 KB of program since an interrupt could occur at any point in the program The Extended Interrupt Frame Mode changes the operation of interrupts and the RETI instruction only while other calls and returns are not affected Special extended call and return instructions allow large 13 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM programs to traverse the entire code space with full 23 bit return addresses The Extended Interrupt Frame Mode is enabled by setting the EIFM bit in the MXCON register This figure applies to interrupt services in Extended Interrupt Frame 0083h Mode as well as the ECALL instruction in all modes PCE PC 22 16 0082h 4 8 Final SP Value after PCH PC 15 8 0081h ECALL or interrupt The upper bit of the byte containing PCE is forced to a 1 in order to be PCL PC 7 0 0080h consistent with Universal Pointers 007Fh Initial SP Value before i i ECALL or interrupt
38. rate divisor bits 7 0 Figure 39 BRGRO Register BRGR1 Address 87h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h BRATE15BRATE14BRATE13BRATE12BRATE 11BRATE10 BRATE9 BRATE8 BIT SYMBOL FUNCTION BRGR1 7 0 BRATE15 8 Baud rate divisor bits 15 8 Figure 40 BRGR1 Register Updating the BRGR1 and BRGRO SFRs The effective baud rate is a 16 bit value The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is 0 This avoids the loading of an interim value when only one of BRGR1 and BRGRO is written to the baud rate generator CAUTION If any of BRGRO or BRGR is written if BRGEN 1 result is unpredictable 57 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM SO0CON 7 SOCON 6 pa a PCON 7 BRGCON 1 Receive Transmit Baud Rate Number of data bits SMO 0 SM1 0 SMOD1 SOBRGS for UART 0 in transfer TCLK Transmit ee ee A 7L w Lp I IL ce 39 39 px p om o9 3 px p ee L3 DX T3 ee Receiver and transmit clocks can be different Table 15 Baud Rate Generation for UART 0 Use T2CON 5 RCLK in Receive Baud Rate Selection T2CON 4 TCLK in Transmit Baud Rate Selection S1CON 7 S1CON 6 Number of data bits p uw O aaa ee U qm ws 7
39. rate for UART 1 In all four modes transmission is initiated by any instruction that uses SOBUF S1BUF as a destination register Reception is initiated in Mode 0 by the condition RI O RI 12 0 and REN O REN 1 1 In all other modes reception is initiated by the incoming start bit if REN O REN 1 1 6 6 5 SFR AND EXTENDED SFR SPACES The regular UART 0 SFRs and control bits are in the regular SFR space However extended control and UART 1 registers are in the MX extended SFR space Troon reet 98 BL ww mens 98 Ssxowswaww some 3 sur swamenomamse Wu Sw same semen TO sw smamw sementem mm Lwemrsmmeosme TO Lscow swamrowe 4 smy swwmrommme TO Sinoom same 8 sme swamwrrwmentam 0 98 semrwmmnsms TO wmm smsmweGmew menu mom ead rae Cerea tae tore 88 Eswcow smecmaeGmewrome TC Table 14 SFR Extended SFR Locations for UARTs 56 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 6 6 BAUD RATE GENERATOR AND SELECTION The P87C51Mx2 enhanced UARTS have one associated independent Baud Rate Generator Baud rate generator implemented in P87C51Mx2 family of microcontrollers is the device that easily produces desire
40. serial port O UART 0 to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3 unless SBRGS BRGCON 1 is set to 1 TCLK 0 causes Timer 1 overflows to be used for the transmit clock See UARTS T2CON 3 EXEN2 Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX T2CON 2 TR2 Start stop control for Timer 2 A logic 1 enables the timer to run T2CON 1 C T2 Timer or counter select Timer 2 0 Internal timer fosc 6 1 External event counter falling edge triggered external clock s max rate fosc 12 T2CON 0 CP RL2 Capture Reload flag When set captures will occur on negative transitions at T2EX if EXEN2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 33 Timer Counter 2 T2CON Control Register T2MOD Address C9h Not bit addressable 7 6 5 4 3 2 1 0 Reset Value XX000000B T2OE DCEN BIT SYMBOL FUNCTION T2MOD 7 2 Reserved for future use Should be set to 0 by user programs T2MOD 1 T20E Timer 2 Output Enable bit Used in programmable clock out mode only T2MOD 0 DCEN Down Count Enable bit W
41. than any interrupt currently in progress While having the MX part in Power Down Mode and driving Reset high or external interrupt line low the oscillator dedicated analog subsystem inside of the microcontroller will be enabled However only when the wake up pulse on reset external interrupt 44 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM line is ended the rest of microcontroller will be supplied with the system clock and continue to operate The duration of an input pulse on reset external interrupt pin in order to wake the part from Power Down Mode depends solely on external oscillator s circuit components At the end of wake up procedure reset external interrupt line can be brought to non active level as soon as input at XTAL1 pin achieves stable frequency duty cycle and amplitude If an external interrupt caused the part to wake up execution of forced jump that directs code execution to the proper interrupt service routine will end Power Down Mode By exiting Power Down mode via external interrupt the core automatically clears the PD bit and thus enables a new entry into Power Down Mode Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down Mode External reset by default clears PD bit and enables the next Power Down In Power Down mo
42. the number of Tx interrupts must be the same as the number of characters sent If 1 an additional interrupt is sent at the beginning INTLO_n 0 or the end INTLO n 1 of the STOP bit when there is no more data in the double buffer This last interrupt can be used to indicate that all transmit operations are over STINT n n 0 1 If 1 FE n BR n and OE ncan cause interrupt refer to Figure 44 Bits DBMOD n and DBISEL n are discussed further in section Double Buffering INTLO n behaves in the same manner regardless of single of double buffering but the first interrupt occurs different This topic is also covered in section Double Buffering CIDIS n is not related to double buffering 61 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM SnSTAT SOSTAT Address 8Ch MX Extended SFR Space S1STAT Address 84h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h DBMOD n INTLO n CIDIS n DBISEL n FE n BR n OE n STINT n BIT SYMBOL FUNCTION SnSTAT 7 DBMOD n 0 Double buffering disabled 1 Double buffering enabled SnSTAT 6 INTLO n Transmit interrupt position for UART mode 1 2 or 3 0 Tx interrupt is issued at the beginning of stop bit 1 Tx interrupt is issued at end of stop bit Must be 0 for mode 0 SnSTAT 5 CIDIS n 0 Combined Tx Rx interrupt for Serial Port
43. transmits a START condition after If it is in slave mode an internal STOP condition will be generated but is not transmitted to the bus 70 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM I2CON Address 91h Bit addressable Reset Source s Any reset Reset Value x00000x0B BIT SYMBOL I2CON 7 I2CON 6 I2EN I2CON 5 STA I2CON 4 STO I2CON 3 SI I2CON 2 AA I2CON 1 I2CON O CRSEL I2EN STA STO SI AA CRSEL FUNCTION Reserved for future use Should not be set to 1 by user programs IC Interface Enable When clear I C function is disabled P1 7 SDA and P1 6 SCL can be used as general I O When set enable I C function The Start Flag STA 1 the I C enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits fora STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When I C is already in master mode and some data are transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when C is in an addressed slave mode STA 0 no START condition or repeated START condition will be generated The STOP Flag STO 1 In master mode a STOP condition is transmitted to the I C bus When the bus dete
44. 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM WDPRE2 WDPRE1 WDPREO Prescale Factor Table 22 WDT Prescale Selection 6 8 5 READING FROM THE WDCON SFR It should be noted that value written to the WDCON register will not be immediately available to be read until after a successful feed sequence Any read before a feed sequence will fetch the old value 6 8 6 SOFTWARE RESET VIA WATCHDOG TIMER FEED SEQUENCE The following instructions will result in a software reset via the watchdog timer reset even if one or more interrupts occur during those instructions MOV WDTRST 01Eh Feed sequence first part MOV WDTRST 0AAh Any pattern other than 1Eh or Eth not necessarily AAh will perform a WDT reset This software reset will be performing the same function as a WDT reset where a reset pulse will also be generated to reset external circuitries 85 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Any Reset WDT disabled Wait for next write to the WDTRST SFR ritten 01Eh to the WDTRST SFR es WDT disabled Wait for next write to the WDTRST SFR 1Eh alue written to the WDTRST SFR Elh Start WDT WDT enabled Wait for next write to the WDTRST SFR Time out gt Elh alue written to
45. 3 MOV MOV dir RO RO dir 89 e A9 3 3 MOV MOV dir R1 R1 dir 8A 3 3 AA 3 3 MOV MOV dir R2 R2 dir 8B 3 3 AB 3 3 MOV MOV dir R3 R3 dir 8C 3 3 AC 3 3 MOV MOV dir R4 R4 dir 8D 3 3 AD 3 3 MOV MOV dir R5 R5 dir 8b 3 3 AE 3 3 MOV MOV dir R6 R6 dir 8F 3 3 AF 3 3 MOV MOV dir R7 R7 dir 33 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 4 EXTERNAL BUS The external bus provides address information to external devices and initiates code read data read or data write operations In 51MX devices the external bus duplicates the classic 80C51 multiplexed external bus allowing increased address output to 23 bits 4 1 MULTIPLEXED EXTERNAL BUS The 51MX external bus supports 8 bit data transfers and up to 23 address lines The number of address lines available is configurable and depends on the setting of the EAM bits in the MXCON register The default for an unprogrammed part following reset is 16 address bits This provides drop in compatibility in existing 80C51 sockets Software may write 1 to EAM bit in MXCON changing the default external bus configuration Typically this would be done once It is not recommended to change the address configuration dynamically during program execution for example changing EAM 1 to EAM 0 changes external memory bus interface and prevents core from executing external code a
46. 51MX was to keep the same timing relationship of existing 80C51 instructions to existing devices Any 80C51 instruction executed on the 51MX will take the same number of machine cycles to execute Table 3 Instructions affected by extended address space 80C51 Instruction Effect of Extended Addressing Includes SJMP and all conditional branches These instructions may cross a 64 kB boundary if they Allrelative branches are located within branch range of the boundary This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary If ECRM 1 this instruction will act as MX s specific ECALL This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence AJMP addri1 is across the boundary The lower 16 bits of the Program Counter are replaced with the value formed by the sum of the JMP A DPTR Accumulator and the active DPTR This instruction will cross a 64 kB boundary if it is located such that the next instruction in sequence is across the boundary The address formed by replacing the lower 16 bits of the Program Counter with the value formed MOVC A A DPTR by the sum of the Accumulator and the active DPTR is used to access code memory The PC value used is that of the instruction following MOVC MOVC A A PC The sum of the Accumulator and the 23 bit Program Counter forms the 23 bit address used to read the code memory The
47. 6 8 1 WATCHDOG FUNCTION The time interval of the watchdog timer can be calculated as timeoutperiod 16383 x prescalefactor x 6 fosc In other words after a feed sequence the watchdog timer time out will occur after 16383 x prescalefactor machine cycles and will cause a watchdog reset unless the next feed sequence occurs before the time out 83 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 8 2 FEED SEQUENCE WDT is disabled after reset of the microcontroller To enable the WDT user must write 01EH and 0E1H in sequence to the WDTRST register Once the WDT is enabled user must feed the watchdog in by writing 01EH and OE1H to WDTRST before a WDT timeout to avoid WDT overflow When WDT overflows it will drive an reset HIGH pulse at the RST pin After WDT is enabled it cannot be disabled unless system is resetted The following code is recommended for a feed sequence CLR EA Disable all interrupts avoid interrupt in between two parts of feed sequence MOV WDTRST 01Eh Feed sequence first part MOV WDTRST 0E1h Feed sequence second part SETB EA Enable interrupts Note that Upon a power up or any reset including WDT reset the watch dog timer is disabled Executing the feed sequence once will start the WDT Once started it cannot be disabled until reset again The watchdog is enabled by a write of 1Eh followed by a wr
48. AD8 ADIS AD22 AD21 AD19 AD18 AD17 AD16 B7 B6 B5 B4 B3 B2 B1 BO Timer2 Capture High Timer2 Capture Low 9F 9E 9D 9C 9B 9A 99 98 Serial Port 0 Control SMO_O EU peu pene peu peu mo wo Serial Port 0 Data Buffer Register Serial Port 0 Address Register Serial Port 0 Address Enable Serial PORE Stalls ii dn INTLO 0 cibis 0 DBISEL 0 STINT 0 Serial Port 1 Control m Bucolica aset M erasa Cage ea Serial Port 1 Data buffer Register Serial Port 1 Address Register Serial Port 1 Address Enable Serial Port status iun INTLO 1 CIDIS_1 DBISEL1 STINT 1 Stack Pointer or Stack Pointer Low Byte When EDATA Supported 42 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Special Function Registers Continued DIRECT BIT ADDRESS SYMBOL OR ALTERNATE PORT FUNCTION Reset SYMBOL DESCRIPTION ADDRESS msg LSB Value Stack Pointer High Timer Control Register Timer2 Control Register Timer2 Mode Control Timer 0 High Timer 1 High Timer 2 High Timer 0 Low Timer 1 Low Timer 2 Low WDTRST Watchdog Timer Reset Notes SFRsare bit addressable 4 SFRs are modified from or added to the 80C51 SFRs f Extended SFRs accessed by preceding the instruction with MX escape opcode A5h Reserved bits must be written with 0 s amp Power on reset is 10H Other reset is 00H 96 The unimplemented bit
49. ASH with 2kB RAM All of the modules will have the same frequency of output because they all share one and only PCA timer The duty cycle of each module is independently variable using the module s capture register CCAPnL When the value of the PCA CL SFR is less than the value in the module s CCAPnL SFR the output will be low when it is equal to or greater than the output will be high When CL overflows from FF to 00 CCAPnL is reloaded with the value in CCAPnH this allows updating the PWM without glitches The PWM and ECOM bits in the module s CCAPMn register must be set to enable the PWM mode 6 10 5 PCA WATCHDOG TIMER An on board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count Watchdog timers are useful for systems that are susceptible to noise power glitches or electrostatic discharge Module 4 is the only PCA module that can be programmed as a watchdog However this module can still be used for other modes if the watchdog is not needed Figure 74 shows a diagram of how the watchdog works The user pre loads a 16 bit value in the compare registers Just like the other compare modes this 16 bit value is compared to the PCA timer value If a match is allowed to occur an internal reset will be generated This will not cause the RST pin to be driven high CIDL woe
50. ATA HDATA and CODE spaces The SFR space is the only space that may not be accessed using the Universal Pointer mode The Universal Pointer addressing mode uses a new set of pointer registers for two reasons The first is that 24 bit pointers are needed in order to allow addressing both the 8 MB code space and the 8 MB data space The other reason is that it is much more 21 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM efficient to manipulate multi byte pointer values in registers than it is in SFRs C compilers typically already perform pointer manipulation in registers then move the result to a Data Pointer for use Two Universal Pointers are supported PRO and PR1 The pointer PRO is composed of registers R1 R2 and R3 of the current register bank while PR1 is composed of registers R5 R6 and R7 of the current register bank as shown in Figure 15 Figure 15 Universal pointer registers In order to access all of the various memory spaces in a single unified manner they must all be mapped into a new view that allows 16 MB of total memory space This new view is called the Universal Memory Map The XDATA space is placed at the bottom of this new address map The HDATA space continues above XDATA The standard internal data memory spaces DATA and IDATA are above HDATA followed by the remainder of the EDATA space Finally the code mem
51. CLR CPL A 3 2 95 2h A5 BS 3 2 C5 2 1 D5 3 2 E5 2 1 F5 2 SUBB MX extension CJNE XCH DJNZ MOV MOV A dir prefix A dir rel8 A dir dir rel8 A dir dir A 2 2 96 1 1 A6 2 2 B6 3 2 C6 1 1 D6 1 1 E6 1 1 F6 1 MOV SUBB MOV CJNE XCH XCHD MOV MOV dir RO A RO RO dir RO d8 rel8 A RO A RO A RO QRO A 7 2 2 97 14 A7 2 2 B7 3 2 C7 1 1 D7 1 1 E7 1 1 F7 1 MOV SUBB MOV CJNE XCH XCHD MOV MOV dir R1 A R1 R1 dir R1 d8 rel8 A R1 A R1 A R1 QR1 A 8 2 2 2 2 OV ir R1 2 2 OV ir R2 2 2 OV ir R3 31 F8 1 MOV R0 A F9 1 MOV R1 A FA 1 MOV R2 A FB 1 MOV R3 A 2 2 9C 1 1 2 2 BC 3 2 CC 1 1 DC 2 2 EC 1 1 FC 1 OV SUBB MOV CJNE XCH DJNZ MOV MOV ir R4 A R4 R4 dir R4 d8 rel8 A R4 R4 rel8 A R4 R4 A 2 2 9D 1 1 AD 2 2 BD 3 2 CD 1 1 DD 2 2 ED 1 1 FD 1 OV SUBB MOV CJNE XCH DJNZ MOV MOV ir R5 A R5 R5 dir R5 d8 rel8 A R5 R5 rel8 A R5 R5 A 8E 2 2 9E 1 1 AE 2 2 BE 3 2 CE 1 1 DE 2 2 EE 1 1 FE 1 MOV SUBB MOV CJNE XCH DJNZ MOV MOV dir R6 A R6 R6 dir R6 d8 rel8 A R6 R6 rel8 A R6 R6 A 8F 2 2 9F 1 1 AF 2 2 BF 3 2 CF 14 DF 2 2 EF 1 1 FF 1 MOV SUBB MOV CJNE XCH DJNZ MOV MOV dir R7 A R7 R7 dir R7 d8 rel8 A R7 R7 rel8 A R7 R7 A 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 8 51MX operation code chart part 3 10 4 3 20 4 3 30 4 3
52. Combined Tx Rx Interrupt SOSTAT 5 0 Receive Interrupt SOSTAT 5 1 Priority High Bit Timer 1 Interrupt Priority High Bit External Interrupt 1 Priority High Bit Timer 0 Interrupt Priority High Bit External Interrupt O Priority High Bit Figure 23 Interrupt Priority High Byte IPOH 38 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM IP1 Address F8H 7 6 5 4 3 2 1 0 PIERDE essaie 2 PI2C psit PSOT PSyPSIR Reset Value 00h BIT SYMBOL FUNCTION IP1 7 5 Reserved for future use Should be set to 0 by user programs IP1 4 PI2C 2C Interrupt Priority Low Bit IP1 3 Reserved for future use Should be set to 0 by user programs IP1 2 PS1T Serial Port 1 transmit Interrupt S1STAT 5 1 Priority Low Bit IP1 1 PSOT Serial Port 0 transmit Interrupt SOSTAT 5 1 Priority Low Bit IP1 0 PS1 PS1R Serial Port 1 combined Tx Rx Interrupt S1STAT 5 0 receive Interrupt S1STAT 5 1 Priority Low Bit Figure 24 Interrupt Priority Register 1 IP1H Address F7H 7 6 5 4 3 2 1 0 MOL agalese see Pich PstrH PSOTH PsinpsiRH Reset Value 00h BIT SYMBOL IP1H 7 5 IP1H 4 PI2CH IP1H 3 3 IP1H 2 PS1TH IP1H 1 PSOTH IP1H 0 PS1H PS1RH FUNCTION Reserved for future use Should be set to 0 by user programs 2C Interrupt Priorit
53. DATA memory 2 2 4 STACK The processor stack provides a means to store interrupt and subroutine return addresses as well as temporary data The stack grows upwards from lower addresses towards higher addresses The current Stack Pointer always points to the last item pushed on the stack unless the stack is empty Prior to a push operation the Stack Pointer is incremented then data is written to memory When the stack is popped the reverse procedure is used First data is read from memory then the Stack Pointer is decremented The default configuration of the 51MX stack is identical to the classic 80C51 stack implementation When interrupt or subroutine addresses are pushed onto the stack only the lower 16 bits of the Program Counter are stored This default 80C51 mode stack operation is shown in Figure 4 0083h 0082h This figure applies to the ACALL and PCH PC 15 8 0081h amp Final SP Value after ACALL LCALL instructions in all modes In LCALL or Interrupt 80C51 stack mode it also applies to PCL PC 7 0 0080h interrupt processing 007Fh 8 Initial SP Value before ACALL LCALL or interrupt Figure 4 Return address storage on the stack 80C51 Mode There are two configuration options for the stack For purposes of backward compatibility with the classic 80C51 all two additional modes are disabled by a chip reset The first option Extended Interrupt Frame Mode causes interrupts to
54. FFFh 00 F000h Block 7 8KB 00 E000h 00 DFFFh Block 6 8KB sca hi 00 C000h MUS 00 BFFFh 00 A000h 00 9FFFh Block 4 8KB POSER 00 8000h Bite 00 7FFFh 00 6000h 00 5FFFh Block 2 8KB Ones 00 4000h 00 3FFFh Block 1 8KB as 00 2000h 00 1FFFh Block 0 8KB Cones 00 0000h Figure 75 Flash Memory Configuration 7 2 4 POWER ON RESET CODE EXECUTION The P89C669 contains two special Flash elements the BootVector and the Status Byte The BootVector is 16 bits and consists of the BootVector High byte BVH and the BootVector Middlebyte BVM At the falling edge of reset the P89C669 examines the contents of the Status Byte If the Status Byte is set to zero power up execution starts at location 00 0000H which is the normal start address of the user s application code When the Status Byte is set to a value other than zero the contents of the BVH is used as the high byte of the execution address A22 A16 the contents of BVM is used as the middle byte of the execu tion address A15 A8 and the low byte is set to OOH A7 A0 The factory default setting is BVH 00h amp BVM FCh corre 98 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM sponding to the address 00 FCOOh for the Boot Flash ISP boot loader A custom boot loader can be written with the Boot Vector set to the custom boot loader NOTE When eras
55. LL and SCLH to select properiate data rate I2SCLH defines the number of fosc cycles for SCL high I2SCLL defines the number of fosc cycles for SCL low The frequency is determined by the following formula Bit Frequency fosc IPSCLH I2SCLL Where fosc is the oscillator frequency The values for I2SCLL and I2SCLH don t have to be the same user can give different duty cycle s SCL by setting these two register But the value of the register must ensure that the data rate is in the IC data rate range of 0 400kHz So the value of I2SCLL and I2SCLH has some restrictions values for both registers greater than 3 are recommended Table 17 I C clock rates selection Bit Data Rate kbits sec At fosc SS LER 250 0 96 48 24 1 23 4 6000Kbps 11 7 3000Kbps 5 86 1500Kbps timer1 in mode 2 timer1 in mode 2 timer1 in mode 2 I C operation modes are described in following chapters 72 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 7 6 MASTER TRANSMITTER MODE In this mode data are transmitted from master to slave Before the master transmitter mode can be entered I2CON must be initialized as follows 7 6 5 4 3 2 1 0 I2CON 91h I2EN STA STO SI AA CRSEL 1 0 0 0 0 bit rate CRSEL defines the bit rate I2EN must be set to 1 to enable I C function If the AA b
56. Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 1 4 P89C669 BLOCK DIAGRAM High Performance 80C51 CPU 96kB Code FLASH Internal Bus 2kB Data RAM Baud Rate Generator TimerO Timer1 Watchdog Timer PCA Programmable Counter Array Timer2 Crystal or Oscillator Resonator Figure 2 P89C669 block diagram 9 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 2 MEMORY ORGANIZATION 2 1 PROGRAMMER S MODELS AND MEMORY MAPS The P89C669 retains all of the 80C51 memory spaces Additional memory space has been added transparently as part of the means for allowing extended addressing The basic memory spaces include code memory which may be on chip off chip or both external data memory Special Function Registers and internal data memory which includes on chip RAM registers and stack Provision is made for internal data memory to be extended allowing a larger processor stack The P89C669 programmer s model and memory map is shown in Figure 3 7F FFFFh Two 24 bit Universal Pointers 7E FFFFh HDATA includes XDATA 23 bit Program Counter 23 bit Extended Data Pointer Two 16 bit DPTRs 16 bit Stack Pointer EDATA includes DATA amp IDATA On Chip and or PAENG eO Dd On Chips and or Memory Off Chip stack and indirect Off Chip Code Memory addressing Data Memory
57. Mode DCEN 0 In this mode there are two options selected by bit EXEN2 in T2CON register If EXEN2 0 then Timer 2 counts up to OFFFFH and sets the TF2 Overflow Flag bit upon overflow This causes the Timer 2 registers to be reloaded with the 16 bit value in RCAP2L and RCAP2H The values in RCAP2L and RCAP2H are preset by software means Auto reload frequency when Timer 2 is counting up can be determined from this formula SupplyFrequency 65536 RCAP2H RCAP2L where SupplyFrequency is either fog 6 C T2 0 or frequency of signal on T2 pin C T2 1 If EXEN2 1 a 16 bit reload can be triggered either by an overflow or by a 1 to 0 transition at input T2EX This transition also sets the EXF2 bit The Timer 2 interrupt if enabled can be generated when either TF2 or EXF2 is 1 Microcontroller s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 1 in the first machine cycle pin T2EX has to be sampled as 1 in the second machine cycle it has to be sampled as O and in the third machine cycle EXF2 will be set to 1 In Figure 37 DCEN 1 and Timer 2 is enabled to count up or down This mode allows pin T2EX to control the direction of count When a logic 1 is applied at pin T2EX Timer 2 will count up Timer 2 will overflow at OFFFFH and set the TF2 flag which can then generate an interrupt if the interrupt is enabled This timer overflow also causes the 16 bit value in RCAP2L a
58. Must be cleared by software PCA Module 3 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software PCA Module 2 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software PCA Module 1 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software PCA Module 0 Interrupt Flag Set by hardware when a match or capture occurs Must be cleared by software Figure 68 PCA Counter Control Register 91 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM CCAPMn 7 6 5 4 3 2 1 0 Address CCAPMO ODAH ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPM1 ODBH CCAPM2 0DCH CCAPM3 0DDH CCAPM4 0DEH Not bit addressable Reset Value 00h BIT SYMBOL FUNCTION CCAPMn 7 Reserved for future use Should be set to 0 by user programs CCAPMn 6 ECOMn Enable Comparator ECOMn 1 enables the comparator function CCAPMn 5 CAPPn Capture Positive CAPPn 1 enables positive edge capture CCAPMn 4 CAPNn Capture Negative CAPNn 1 enables negative edge capture CCAPMn 3 MATn Match When MATn 1 a match of the PCA counter with this module s compare capture register causes the CCFn bit in CCON to be set flagging an interrupt CCAPMn 2 TOGn Toggle When TOGn 1 a match of the PCA counter with this module s compare captur
59. R A DPTR direct Ri EPTR A EPTR direct data Ri A PRi data2 A direct rel Ri direct A data rel Ri data AB Rn data rel DPTR data16 Ri data rel EPTR data23 Rn rel A A DPTR direct rel A A PC A A EPTR addr11 A Ri A DPTR addr16 Ri A DPTR A A EPTR A Rn addr23 EPTR A A direct A Ri A PRi disp A data PRi disp A direct A direct data direct A Ri 28 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 3 2 51MX OPERATION CODE CHARTS This 51MX opcode chart consists of four pages The first two pages are identical to a classic 80C51 opcode chart except that the A5h opcode is marked as the MX extended instruction prefix value The third and fourth pages show instruction encoding that follows the A5h prefix These instructions are unique to the 51MX and are divided into several types as shown below Contents of Each Table Entry opcode bytes cycles instruction mnemonic operand s 51MX Extended Instruction Types Unmodified 80C51 Instruction New MX Instructions Extended Addressing Instructions Extended SFR Addressing These instructions are identical to classic 80C51 instructions and thus appear only on the first two pages of the opcode chart These instructions are new to the 51MX All are related to the Universal Pointers These instructions incorporate
60. UF is written as TB8 n will be double buffered together with SnBUF data The operation described in the section Transmit Interrupts with Double Buffering becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SnBUF The SnBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately If there is more data go to 7 else continue on 6 If there is no more data then If DBISEL nis 0 no more interrupt will occur If DBISEL nis 1 and INTLO nis 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shift register which is also the last data If DBISEL nis 1 and INTLO nis 1 UART mode 1 2 or 3 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shift register which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SnBUF again Then If INTLO nis 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur rently in the shift register IFINTLO nis 1 UART mode 1 2 or 3 only the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shift register Go to 4 Note that if DBISEL nis 1 and when the CPU is writing to SnBUF about the same time the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx int
61. W as master General call address has been received ACK bit has been returned Previously addressed with own SLA address Data has been received ACK has been returned Previously addressed with own SLA address Data has been received NOT ACK has been returned APPLICATOPN SOFTWARE RESPONSE no I2DAT action or no I2DAT action No I2DAT action or no I2DAT action No I2DAT action or no I2DAT action no I2DAT action or no I2DAT action Read data byte or read data byte Read data byte or read data byte or read data byte or read data byte 80 NEXT ACTION TAKEN BY I2C HARDWARE Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned SLA W will be transmitted l2C will be switches to master transmitter mode Data byte will be received and ACK will be returned 12C will be released it will enter a slave mode Data byte will be received and ACK will be returned A START condition will be transmitted when the bus becomes free Data byte will be received NOT ACK bit will be returned Switched to not addressed SLA mode no recognition of own SLA or general address Switched to not addressed SLA mode Own SLA will be recognized general call address will be recognized if I2ADR 0 1 Switched to not addressed SLA
62. are The PCA is shut off by clearing this bit The CF bit CCON 7 is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set The CF bit can only be cleared by software Bits 0 through 4 of the CCON register are the flags for the modules bit 0 for module 0 bit 1 for module 1 etc and are set by hardware when either a match or a capture occurs These flags can only be cleared by software All the modules share one interrupt vector The PCA interrupt system is shown in Figure 66 Each module in the PCA has a special function register associated with it These registers are CCAPMO for module 0 CCAPM1 for module 1 etc The registers contain the bits that control the mode that each module will operate in The ECCF bit from CCAPMn 0 where n 0 1 2 3 or 4 depending on the module enables the CCFn flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module see Figure 66 PWM CCAPMn 1 enables the pulse width modulation mode The TOG bit CCAPMn 2 when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module s capture compare register The match bit MAT CCAPMn 3 when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module s capture compare register The next two bits CAPN CCAPMn 4 and CAPP CCAPMn 5 determine the
63. ared by hardware when the processor vectors to Timer 0 Interrupt routine or by software TCON 4 TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off TCON 3 IE1 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge low level is detected Cleared by hardware when the interrupt is processed or by software TCON 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level that triggers external interrupt 1 TCON 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge low level is detected Cleared by hardware when the interrupt is processed or by software TCON 0 ITO Interrupt O Type control bit Set cleared by software to specify falling edge low level that triggers external interrupt O Figure 28 Timer Counter Control Register TCON 6 4 1 MODE 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a fixed divide by 32 prescaler Figure 29 shows Mode 0 operation TLn THn 5 bits 8 bits Overflow Interrupt TRn TnGate INTn Pin Figure 29 Timer Counter 0 or 1 in Mode 0 13 Bit Counter In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either GATE 0 or INTn 1 Setting GATE 1 allo
64. ased hap ee ES 71 6 7 7 Master Receiver Meu S eere etui uu i dE dtes 71 6 7 8 Slave Receiver MOU sooo eR user dieit ad bae touc cup a eta ees T2 6 7 9 slave Transmitter MOS eoe era ie ter AD adir DR ER EERGNANO NO Que Str iNi 73 Watchdog Bind ste 81 6 8 1 Watchdog BUBellOfis sabios d ru Iota eere fede ab i roce ape casae ve begve CU DEREN R US 8l 6 9 2 Feed SeguelloE ood cile datu epo debou Wacate dut pep bsec C e e 82 6 8 3 MET OMG 43s ootetipie setti aati ate Matra dites ua reat e Md Lomas ed deer Saal 82 6d WaulchiDos Reset Wd sc sso eU REC p Du e RS Ia Heu E e up ea e us 82 6 8 5 Reading from the WDCON SER 5 estesa t ente hen tene eee SERES YR Ge ee HS Qu S 83 6 8 6 Software Reset Via WatchDog Timer Feed Sequence sess 83 toI IC BSc P 85 6 9 1 Expanded Data RAM Adres sims cuore pu icing au eva eara oasis VEU YR ed y NE gU 85 692 JWD ual Dati POLlBIGDSonoscuane d etel imet ata eta PIRE AN DM EAS 86 Programmable Counter Array PCA insect oe decide nadie ter ten ede tuuc us 86 6 I0 TL PCA Capture Mode miersii ied as bot die tv Ea E ECES 90 3 2003 Sep 16 4 10 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 10 2 16 bit Software Timer Mode unite oleo bea cede adiu BAS 91 6 10 3 High Speed Output Mode 5 152 454 cenas olo ee bie dm aer dt
65. ata byte Load data byte or load data byte Load data byte or load data byte No I2DAT action or no I2DAT action or no I2DAT action or no I2DAT action 82 NEXT ACTION TAKEN BY I2C HARDWARE Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted ACK will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted ACK bit will be received Last data byte will be transmitted and ACK bit will be received Data byte will be transmitted ACK will be received Switched to not addressed SLA mode no recognition of own SLA or General call address Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IDADR 0 1 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IDADR 0 1 A START condition will be transmitted when the bus becomes free 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 21 Slave Transmitter Mode Continued STATUS STATUS OF THE APPLICATOPN SOFTWARE RESPONSE NEXT ACTION TAKEN BY I2C CODE I2C BUS Last data byte in
66. better done with the Framing Error flag When UART receives data in mode 1 and SM2 n 1 the receive interrupt will not be activated unless a valid stop bit is received 6 6 16 AUTOMATIC ADDRESS RECOGNITION Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled for UARTn by setting the SM2 n bit in SnCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI n will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two Special 66 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used a
67. bove the 64 kB boundary When the full 23 bit address is multiplexed on Port 2 EAM 1 in MXCON the high order address information bits A22 through A16 must be latched externally in the same manner as the low order bits A7 through AO are latched on Port 0 The middle address bits A15 through A8 appear on Port 2 after ALE goes low If extended addressing is not enabled with EAM 1 Port 2 behaves just as in case of classic 80C51 An example of Port 2 address multiplexing is shown in Figure 19 There are two special cases for Port 2 multiplexing when extended addressing is enabled MOVX Ri and MOVX DPTR These instructions do not supply a source for a full 23 bit external address Where program memory is involved jumps and MOVC any missing address bits are supplied by the Program Counter see Table 3 For MOVX the additional bits are forced to zeroes to complete the address since XDATA accessed with this instruction is on the very bottom of the data space see Figure 3 Figure 16 and Figure 17 So MOVX Ri will output a 23 bit address composed of seven zeroes for the most significant bits of the address Port 2 SFR contents for the middle byte of the address and Ri contents for the bottom byte of the address Similarly MOVX DPTR will output a 23 bit address composed of seven zeroes for the upper address and the current DPTR contents for the middle and bottom bytes of the address Everything stated in this paragraph related to MOVX instruct
68. chitecture that executes instructions at twice the rate of standard 80C51 devices The linear unsegmented address space of the 51MX core has been expanded from the original 64 kilobytes kB limit to support up to 8 megabytes MB of program memory and 8 MB of data memory It retains full program code compatibility to enable design engineers to reuse 80C51 development tools eliminating the need to move to a new unfamiliar architecture The 51MX core retains 80C51 bus compatibility to allow for the continued use of 80C51 interfaced peripherals and Application Specific Integrated Circuits ASICs However by entering the Extended Addressing Mode in order to access either data or code beyond 64 kB the bus interface changes The 51MX core is completely backward compatible with the 80C51 code written for the 80C51 may be run on 51MX based derivatives with no changes Summary of differences between the classic 80C51 architecture and the 51MX core Program Counter The Program Counter is extended to 23 bits Extended Data Pointer A 23 bit Extended Data Pointer called the EPTR has been added in order to allow simple adjustment to existing assembly language programs that must be expanded to address more than 64 KB of data memory Stack Two independent alternate Stack modes are added The first causes addresses pushed onto the Stack by interrupts to be expanded to 23 bits The second allows Stack extension into a larger memory space Instructi
69. ciency for code sizes below 64 kB The P89C669 device contains a non volatile Flash program memory that is both parallel programmable and serial In System and In Application Programmable In System Programming ISP allows the user to download new code while the microcontroller sits in the application In Application Programming IAP means that the microcontroller fetches new program code and reprograms itself while in the system This allows for remote programming over a modem link A default serial loader boot loader program in ROM allows serial In System programming of the Flash memory via the UART without the need for a loader in the Flash code For In Application Programming the user program erases and reprograms the Flash memory by use of standard routines contained in ROM 5 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM KEY FEATURES Extended features of the 51MX Core 23 bit program memory space and 23 bit data memory space linear program and data address range expanded to sup port up to 8 MB each Program counter expanded to 23 bits Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation New 23 bit extended data pointer and two 24 bit universal pointers greatly improve C compiler code eficiency in using pointers to access variables in different spaces 10096 binary compatibility with the classic 80C51 so
70. ck erase times including preprogramming time Block Erase 8KB in 1 second Full Erase 96KB in 1 second Parallel programming with 87C51 like hardware interface to programmer Programmable security for the code in the Flash 10000 minimum erase program cycles for each byte 10 year minimum data retention 7 2 CAPABILITIES OF THE PHILIPS 89C51 FLASH BASED MICROCONTROLLERS 7 2 1 FLASH ORGANIZATION The P89C669 contains 96 kbytes of Flash program memory This memory is organized as 12 separate blocks each block con taining 8KB Table 75 depicts the Flash memory configurations 7 2 2 FLASH PROGRAMMING AND ERASURE There are three methods of erasing or programming of the Flash memory that may be used First the Flash may be pro grammed or erased in the end user application by calling low level routines through a common entry point in the BootFlash The end user application though must be executing code from a different block than the block that is being erased or programmed Second the on chip UARTO ISP boot loader may be invoked This ISP boot loader will in turn call low level routines through 97 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM the same common entry point in the BootFlash that can be used by the end user application Third the Flash may be pro grammed or erased using the parallel method by using a commercial
71. cori coro SSON r o p gt PCA INTERRUPT TO CCFn PCA TIMER COUNTER CH CL o oco i emer N CAPTURE 5 oco CCAPnH CCAPnL l l CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn C2H C6H 0 0 0 0 Figure 70 PCA Capture Mode If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated 6 10 2 16 BIT SOFTWARE TIMER MODE The PCA modules can be used as software timers Figure 71 by setting both the ECOM and MAT bits in the modules CCAPMn register The PCA timer will be compared to the module s capture registers and when a match occurs an interrupt will occur if the CCFn CCON SFR and the ECCFn CCAPMn SFR bits for the module are both set CF CR CCF4 CCF8 CCF2 CCFi ccro on WRITE TO CCAPnL RESET SHE CCAPnH CCAPnL TO CCFn oco P PCA INTERRUPT 1 0 ENABLES 16 BIT COMPARATOR MATCH Lees CH CL PCA TIMER COUNTER CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn C2H C6H Figure 71 PCA Compare Mode 93 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 10 3 HIGH SPEED OUTPUT MODE In this mode Figure 72 the CEX o
72. cted the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically C Interrupt Flag This bit is set when one of the 25 possible I C states is entered Typically the I C interrupt should only be used to indicate a start condition at an idle slave device or a stop condition at an idle master device if it is waiting to use the I C bus When EA bit and EI2C IEN1 0 bit are both set an interrupt is requested when SI 1 This bit is cleared by software by writing O to this bit The Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The own slave address has been received 2 The general call address has been received while the general call bit GC in I2ADR is set 3 A data byte has been received while the I C is in the master receiver mode 4 A data byte has been received while the I2C is in the addressed slave receiver mode When set to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the I C is in the ma
73. ctions 2 2 1 REGISTERS RO R7 General purpose registers RO through R7 allow quick efficient access to a small number of internal data memory locations For example the instruction MOV A RO uses one byte of code and executes in one machine cycle Using direct addressing to accomplish the same result as in MOV A 10h requires two bytes of code memory and executes in two machine cycles Indirect addressing further requires setup of the pointer register etc These registers are banked There are four groups of registers any one of which may be selected to represent RO through R7 at any particular time Desired register bank is selected using bits RS1 and RSO in PSW SFR This feature may be used to minimize the time required for context switching during an interrupt service or a subroutine or to provide more register space for complicated algorithms The registers are no different from other internal data memory locations except that they can be addressed in shorthand notation as RO R1 etc Instructions addressing the internal data memory by other means such as direct or indirect addressing are quite capable of accessing the same physical locations as the registers in any of the four banks Table 2 Selection of the working register bank RO R7 memory segment in DATA OOh 07h O8h 0Fh 10h 17h 18h 1Fh 2 2 2 BIT ADDRESSABLE RAM Internal data memory locations 20 hex through 2F hex may be acces
74. d baud rate with higher resolution than it could be achieved with standard timers sourcing clocks for UARTs The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs in the extended SFR space BRGR1 7 0 and BRGRO 7 0 together form a 16 bit baud rate divisor value BRATE15 0 that works in a similar manner as Timer 1 2 If the baud rate generator is used Timer 1 2 can be used for other timing functions UART 0 can use either Timer 1 2 see T2CON 5 4 or the baud rate generator output as determined by BRGCON 1 0 in the extended SFR space while UART 1 uses only the baud rate generator Note that in UART 0 Timer 1 is further divided by 2 if the SMOD bit PCON 7 is cleared Timer 2 for UART 0 and the independent Baud Rate Generator for both UARTs will be used as is without the divided by 2 option see Figure 42 UART 0 can have different baud rates for transmission and reception of data In such application one of the clocks must be based on Timer 1 while the second clock is derived from either Timer 2 or Baud rate generator It is not possible to have Timer 2 and Baud rate generator supplying different baud rates at the same time for UART 0 see Table 15 and Figure 42 BRGRO Address 86h MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h BRATE7 BRATE6 BRATE5 BRATE4 BRATE3 BRATE2 BRATE1 BRATEO BIT SYMBOL FUNCTION BRGRO 7 0 BRATE7 0 Baud
75. de the power supply voltage may be reduced to the RAM keep alive voltage VgAw This retains the RAM contents at the point where Power Down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vram Since RAM and SFRs are built using different processes Therefore it is recommended to wake up the processor via Reset in this case since Reset redefines all SFRs including PD bit but doesn t change on chip RAM Vpp must be raised to within the operating range before the Power Down mode is exited PCON Address 87h 7 6 5 4 3 2 1 0 Not bit addressable SMOD 1 SMODO POF GF1 GFO PD IDL Reset Value 00 X0000B BIT SYMBOL FUNCTION PCON 7 SMOD1 Baud Rate Control bit for serial port 0 When 0 the baud rate for UART 0 will be the input rate T1 timer or baud rate generator as determined by the BRGCON extended SFR divided by two When 1 the baud rate for UART 0 will be the input rate T1 timer or baud rate generator UART 1 is not affected by this bit PCON 6 SMODO Framing Error Location When 1 bit 7 of SOCON and S1CON will be used for framing error status for UART 0 and 1 respectively When 0 these bits will function as SMO for UARTs 0 and 1 respectively PCON 5 Reserved for future use Should not be set to 1 by user programs PCON 4 POF Power On Flag Reset value 1 for power on reset only all other reset sources POF 0 PCON 3 GF1 General purpose flag 1 May be read or writt
76. dge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the I C bus will not be released This device provides a byte oriented I C interface It has four operation modes master transmitter mode master receiver mode slave transmitter mode and slave receiver mode the detail will be discussed in the following 68 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM SDA IC Bus SCL P1 7 SDA P1 6 SCL Other Device with 12C Other Device with I2C 89C51MX w l2C Interface Interface Figure 50 IC bus configuration The CPU interfaces with I2C bus through six Special Function Registers SFRs IZCON I C Control Register I2DAT I2C Data Register I2STAT I C Status Register IPADR I C Slave Address Register I2SCLH SCL Duty Cycle Register High Byte and I2SCLL SCL Duty Cycle Register Low Byte 6 7 1 I C DATA REGISTER The I2DAT register contains the data to be transmitted or the data just been received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte That
77. directly and indirectly can 128 be used as stack 7F 0000 7F 007F IDATA superset of DATA memory that can be addressed indirectly where 256 direct address for upper half is for SFR only can be used as stack 7F 0000 7F 00FF EDATA superset of DATA IDATA memory that can be addressed indirectly 1280 using Universal Pointers PRO 1 can be used as stack 7F 0000 7F 04FF XDATA memory on chip External Data that is accessed via the MOVX 768 instructions using DPTR EPTR 00 0000 00 02FF CODE code memory used for program storage and data access using MOVC 65536 and EMOV 80 0000 80 FFFF code memory used for program storage data access can be 98304 accomplished using Universal pointers PRO 1 and EMOV 80 0000 81 7FFF 2 2 DATA MEMORY DATA IDATA AND EDATA The standard 80C51 internal data memory consists of 256 bytes of DATA IDATA RAM and is always entirely on chip In this space are the data registers RO through R7 the default stack a bit addressable RAM area and general purpose data RAM On 11 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM the top of the DATA IDATA memory space is a 1024 bytes block of RAM that can be accessed as stack or via indirect addressing Altogether this forms EDATA RAM of 1280 bytes The different portions of the data memory are accessed in different manners as described in the following se
78. e register causes the CEXn pin to toggle CCAPMn 1 PWMn Pulse Width Modulation Mode PWMn 1 enables the CEXn pin to be used as a pulse width modulated output CCAPMn 0 ECCFn Enable CCF Interrupt Enables compare capture flag CCFn in the CCON register to generate an interrupt Figure 69 CCAPMn PCA Modules Compare Capture Registers Po po 9 fo 0 0 0 NoOperaion T 1 T 16 bit capture by a positive edge trigger on CEXn x 1 x 16 bit capture by a negative edge trigger on CEXn M 1 16 bit capture by any transition on CEXn BEAR I ee del ae Ae ee ee FL 3 3 055 o 9 o Waterco tine Table 23 PCA Module Modes CCAPMn Register a RE RER EET E 6 10 1 PCA CAPTURE MODE To use one of the PCA modules in the capture mode Figure 70 either one or both of the CCAPM bits CAPN and CAPP for that module must be set The external CEX input for the module on port 1 is sampled for a transition When a valid transition occurs the PCA hardware loads the value of the PCA counter registers CH and CL into the module s capture registers CCAPnL and CCAPnH 92 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM CF CR ccF4 ccra ccre
79. e o edit idt 92 6 10 4 Pulse Width Modulator Mode 5 1 eire rece etie cei atop detiene 92 6 10 5 PCA Watchdog DITE uuu eiie tot bete hee eoe sti veto de Fenton st qe toov dite 93 7 Flash Memory General Description ecce eee eee sees eere sete seen setas etas e etos etas ease eee seen setas eoa 95 7 1 Features In System Programming ISP and In Application Programming IAP 95 7 20 Capabilities of the Philips 89C51 Flash based Microcontrollers esses 95 7 2 1 Flas OFS ANIA ALON e a Qut ides E a E ti p E put EES 95 7 2 2 Plash Programming and Erasure ces secsicectonssessen eects eciehhtei nee aceon 95 71 2 3 jojo e BET pM 96 7 2 4 Power On Reset Code EXecutloIr oett Les terno strlonlec e Mad eee ad 96 71 3 Hardware Activation of the Boot Loader sssssenssesssesessseessesseesseressetesstesseesseesseeesseessessee 97 Job In System Programmmg ISP 5s s e eu e etie s 97 7 4 1 Using the In System Programming ISP eere 98 7 4 0 In Application Programming Method eere 101 7 4 3 Usimgthe Watchdog Timer WDT iie eterna unease 101 4 2003 Sep 16 4 10 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 1 INTRODUCTION 1 1 THE 51MX CPU CORE Philips Semiconductor s 51MX Memory eXtension core is based on an accelerated 80C51 ar
80. ed by C T2 in the special function register T2CON Timer 2 has four operating modes Capture Auto reload up or down counting Clockout and Baud Rate Generator which are selected according to Table 12 using T2CON and T2MOD figures 33 and 34 Table 12 Timer 2 operating mode RCLKTCLK CPIAL2 mor woo EET a NEGO OE CRUS RSS ee ee 49 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM T2CON Address C8h Bit addressable Reset Value 00h 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 BIT SYMBOL FUNCTION T2CON 7 TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK or TCLK 1 or when Timer 2 is in Clock out Mode T2CON 6 EXF2 Timer 2 external flag is set when Timer 2 is in capture reload or baud rate mode EXEN2 1 and a negative transition on T2EX occurs If Timer 2 interrupt is enabled EXF2 1 causes the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software T2CON 5 RCLK Receive clock flag When set causes the serial port O UART 0 to use Timer 2 overflow pulses for its receive clock in modes 1 and 3 unless SBRGS BRGCON 1 is set to 1 RCLK 0 causes Timer 1 overflow to be used for the receive clock See UARTS T2CON 4 TCLK Transmit clock flag When set causes the
81. em The In System Program ming ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote program ming of the P89C669 through the UARTO serial interface This firmware is provided by Philips and embedded within each P89C669 device The Philips In System Programming ISP facility has made in circuit programming in an embedded applica tion possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins TXDO RXDO Vss Vcc and Vpp see Figure 76 Only a small connector needs to be available to interface your application to 99 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM an external circuit in order to use this feature The Vpp supply should be adequately decoupled and Vpp not allowed to exceed datasheet limits 7 4 1 USING THE IN SYSTEM PROGRAMMING ISP The UARTO ISP provides user with a number of features among which is the specialy defined protocol that enables communi cation with the host over UARTO In most cases PC compatible computer would be the host it would send commands over serial port to P89C669 and wait for microcontroller s response Table 24 List of Commands Record Types P89C669 Accepts in ISP Mode Commands Record type Function sent by host Program Code Memory Format nnaaaa00dd ddcc Where nn
82. en by user software but has no effect on operation PCON 2 GFO General purpose flag 0 May be read or written by user software but has no effect on operation PCON 1 PD Power Down control bit Setting this bit activates Power Down mode operation Cleared when the Power Down mode is terminated see text PCON 0 IDL Idle mode control bit Setting this bit activates Idle mode operation Cleared when the Idle mode is terminated see text Figure 26 Power Control Register PCON 6 3 4 POWER ON FLAG The Power On Flag POF is set by on chip circuitry when the Vpp level on the P87C51Mx2 rises from OV The POF bit allows user to determine if the reset is the result of a power on or a warm start after the powerdown The POF bit can be cleared by software only 6 4 TIMERS COUNTERS 0 AND 1 The two 16 bit Timer Counter registers Timer 0 and Timer 1 can be configured to operate either as timers or event counters see Figure 27 45 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM In the Timer function the register is incremented every machine cycle Thus one can think of it as counting machine cycles Since a machine cycle consists of 6 oscillator periods the count rate is 1 6 of the oscillator frequency In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin
83. eneral read data byte call address will be recognized if IDADR 0 1 A START condition will be transmitted when the bus becomes free A STOP condition or Switched to not addressed SLA mode no repeated START No I2DAT adion recognition of own SLA or General call condition has been address received while still I2DAT action Switched to not addressed SLA mode Own addressed as SLA bd slave address will be recognized General REC or SLA TRX call address will be recognized if IZADR 0 1 Switched to not addressed SLA mode no recognition of own SLA or General call REED Sehen address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be recognized General no I2DAT action call address will be recognized if IZADR 0 1 A START condition will be transmitted when the bus becomes free 81 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 21 Slave Transmitter Mode STATUS STATUS OF THE CODE IPSTAT I2C BUS HARDWARE Own SLA R has been received ACK has been returned Arbitration lost in SLA R W as master Own SLA R has been received ACK has been returned Data byte in I2DAT has been transmitted ACK has been received Data byte in I2DAT has been transmitted NOT ACK has been received APPLICATOPN SOFTWARE RESPONSE Load data byte or load d
84. ents to the 80C51 instruction set enabled by the prefix byte 51MX Enhancement these instructions use 51MX Effect with Prefix the prefix byte 51MX Effect 80C51 Instruction Without Prefix Load a 16 bit address into the Load a 23 bit address into the Program LGALE adari Program Counter ECALL ddr29 Counter Load a 16 bit address into the Load a 23 bit address into the Program ESAE MOIS Program Counter adea The lower 16 bits of the Program Counter are replaced The Program Counter is loaded with the JMP A DPTR with the sum of the JMP A EPTR value formed by the sum of the Accumulator Accumulator and the active and the EPTR DPTR Code memory is accessed using tneadaress formed by Code memory is accessed using the MOVC A A DPTR_ ePlacing the lower 16 bits of MOVC A A EPTR address formed by the sum of the the Program Counter with the Accumulator and the EPTR sum of the Accumulator and the active DPTR The active DPTR points to an The EPTR points to an address anywhere in MOVX DPTR A address in the 64 kB XDATA MOVX EPTR A HDATA memory not DATA IDATA or memory EDATA The active DPTR points to an The EPTR points to an address anywhere in MOVX A QDPTR address in the 64 kB XDATA MOVX A EPTR HDATA memory not DATA IDATA or memory EDATA INC DPTR DOTO Sn iesus STING EPTR Increment the 23 bit EPTR ointer Load a 16 bit value into the MOV DPTR data16 active Data Pointer MOV EPTR data23 Load a
85. er Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Memory Space Addressing Modes PC PC relative addressing DPTR lower 64 kB of Code EPTR Universal Pointers PRO PR1 Up to 8 MB on chip and or off chip program memory 64 kB on chip and or off chip program memory Up to 64 kB 256 bytes on chip and or off chip data Stack SPE SP accessed as Stack and via Universal Pointers PRO PR1 Universal Pointer only 7F 0100h Upper 128 bytes 7F 00FFh on chip indirectly addressed RAM 7F 0080h Lower 128 bytes 7F 007Fh Direct addressing on chip directly amp indirectly RO R1 indirect addressed RAM 7F 0000h Stack SPE SP 7E FFFFh Universal Pointers PRO PR1 RO R1 Stack SPE SP Universal Pointers PRO PR1 Up to 8 MB 128 kB data accessed via MOVX generally off chip data RO R1 lower 256 bytes on chip lower 64 kB off chip via use of P2 DPTR XDATA access only EPTR HDATA access Universal Pointers PRO PR1 Up to 64 kB on chip and or off chip data accessed via MOVX Figure 16 Universal memory map 23 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM scm 0 Standard Memory Map 24 bit Addressing using PRO and PR1 Figure 17 Mapping of other addressing modes to universal pointer addressing 24 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Man
86. errupt is generated already with the UART not knowing whether there is any more data following DOT EEO 6 6 15 MULTIPROCESSOR COMMUNICATIONS UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8_n The UART can be programmed so that when the stop bit is received the serial port interrupt will be activated only if RB8_n 1 This feature is enabled by setting bit SM2_n in SnCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in a way that the 9 bit is 1 in an address byte and 0 in the data byte With SM2 n 1 no slave will be interrupted by a data byte i e the received 9 bit is 0 However an address byte having the 9 bit set to 1 will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed or not The addressed slave will clear its SM2 n bit and prepare to receive the data still 9 bits long that follow The slaves that weren t being addressed leave their SM2 n bits set and go on about their business ignoring the subsequent data bytes SM2 n has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit although this is
87. ffering Case Is Shown 6 6 12 DOUBLE BUFFERING When double buffering is enabled UART temporarily stores in the buffer register the latest data written to SnBUF while the current character is still being shifted out of the transmit shift register The advantage of double buffering is utilized in applications where string of characters with only a single Stop Bit between them is about to be transmitted In order to accomplish this original 80051 UART would load the next character while the Stop Bit of the previous character was being sent Double buffering allows the next character to be loaded at any time from the beginning of the Start bit to the end of the Stop Bit of the previous character i e anytime while the previous data is being shifted out Double buffering is enabled by setting the DBMOD n SnSTAT 7 SFR bit to 1 If double buffering is disabled DBMOD n 0 the P87C51Mx2 s UART is fully compatible with the conventional 80C51 UART 64 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 6 13 TRANSMIT INTERRUPTS WITH DOUBLE BUFFERING Without double buffering the transmit interrupt can be selected to occur at either the beginning or the end of the Stop Bit The purpose of the interrupt is to let the user program know when the UART can accept another character As a result the timing of the interrupt has been changed when double bu
88. ffering is enabled When double buffering is enabled an interrupt is generated each time data is transferred from the buffer register to the transmit shift register Thus if the UART transmitter is idle transmit shift register is empty an interrupt will be generated as soon as the buffer register is loaded since this data will immediately be transferred into the transmit shift register If the UART is transmitting a character when the buffer register is loaded an interrupt will not occur until the beginning end of the Stop Bit of the currently sent character specified by INTLO_n bit in SnSTAT Note that if the buffer is loaded anytime before the end of the Stop Bit characters will be transmitted without extra Stop Bit time Also if a character is loaded into the buffer during the stop bit the interrupt will occur when the buffer is loaded If DBISEL_n 0 an interrupt occurs only when data is transferred from the buffer register to the transmit shift register This way each character generates a single interrupt UART s behavior is identical if DBISEL_n 1 as long as the stop bit in the transmit shift register and empty buffer register situation is not reached i e the buffer register must be continuously filled to avoid this If DBISEL_n 1 and INTLO_n 1 an interrupt will occur at the end of the Stop Bit of the last character sent from the serial shift register if the buffer register is empty If DBISEL n 1 and INTLO_n 0 an interr
89. gh dd data to be programmed Subfunction Code 07 Full Chip Erase If 07 SS don t care dd don t care may optionally be omitted 101 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 24 List of Commands Record Types P89C669 Accepts in ISP Mode Commands Record type Function sent by host Set Segment for File Loading compatible with Intel 386 HEX format Format 02xxxx04xxhhcc Where 02 number of data bytes in record XXXX required field but contents are don t care 04 function code for set segment and file loading XX required field but contents are don t care hh high byte of load address typically 00 01 80 or 81 Gc checksum Read Functions Format 02xxxx05ffsscc Where 02 number of data bytes in record XXXX don t care 05 function code for read functions ffss subfunction and selection code 0000 read manufacturer id 0001 read device id 1 0002 read device id 2 0003 read ISP version 0004 read IAP version 0700 read security bits 0701 read status byte 0702 read boot vector middle 0703 read boot vector high checksum Direct Load of Baud Rate Format 02xxxx06hhllcc Where 02 number of data bytes in record XXXX don t care 06 function code for direct load of baud rate hh high byte of Timer2 ll low byte of Timer2 ce checksum 102 2003 Sep 16 4 12 pm Phil
90. h byte block In system programming and standard parallel programming are both available On chip erase and write timing generation contribute to a user friendly programming interface The P89C669 Flash reliably stores memory contents even after 10 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms In addi tion the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling The P89C669 uses a 5 V Vpp supply to perform the Program Erase algorithms 7 1 FEATURES IN SYSTEM PROGRAMMING ISP AND IN APPLICATION PROGRAMMING IAP Flash internal program memory with Block Erase Internal 4kB Boot Flash containing low level in system programming routines and a default UARTO loader User program can call these routines to perform In Application Programming IAP The BootFlash can be turned off to provide access to the full 8MB memory space Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space This configuration provides flexibility to the user Default loader in BootFlash allows programming via the UARTO interface without the need for a user provided loader Up to 8MB of external program memory if the internal program memory is disabled EA 0 5 V programming and erase voltage Read Programming Erase using ISP IAP Byte Programming 20 us Typical qui
91. he 80C51 and thus the 51MX are Harvard architectures meaning that the code and data spaces are separated If there is a single byte of executable code above 64 kB EAM bit in MXCON sfr must be set to EAM 1 Also if there is constant in CODE space above 64 kB boundary that is read by the application EAM bit must be set to EAM 1 too The 51MX architecture expands the 80C51 Program Counter to 23 bits providing a contiguous unsegmented linear code space that may be as large as 8 MB On chip space begins at code address 0 and extends to the limit of the on chip code memory Above that code will be fetched from off chip The 51MX architecture allows for an external bus which supports Mixed mode some code and or data memory off chip Single chip operation no external bus connection ROMIess operation no use of on chip code memory In some cases code memory may be addressed as data Extended instruction address modes provide access to the entire code space of 8 MB through the use of indexed indirect addressing The currently active DPTR the EPTR a Universal Pointer or the Program Counter may be used as the base address Examples of the various code memory addressing modes are shown in figures 12 through 14 Following a reset the P89C669 begins code execution like a classic 80C51 at address 00 0000h Similarly the interrupt vectors are placed just above the reset address starting at address 00 0003h It is important to note that fi
92. he data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Rightto make changes Philips Semiconductors reserves the right to make changes in the products inc
93. hen set this allows timer2 to be configured as an up down counter Figure 34 Timer 2 Mode T2MOD Control Register 50 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 5 1 CAPTURE MODE In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 is a 16 bit timer or counter as selected by C T2 in T2CON which upon overflowing sets bit TF2 the Timer 2 overflow bit The capture mode is illustrated in Figure 36 GE T2 Pin t___ Timer 2 Interrupt 3 CAPTURE Transition Detector RCAP2L RCAP2H T2EX Pi o P ote EXF2 l CONTROL EXEN2 Figure 35 Timer 2 in Capture Mode This bit can be used to generate an interrupt by enabling the Timer 2 interrupt bit in the IENO register If EXEN2 1 Timer 2 operates as described above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt There is no reload value for
94. ial Port 1 Combined Tx Rx Interrupt Enable S1STAT 5 0 Serial Port 1 Receive Interrupt Enable S1STAT 5 1 Figure 21 Interrupt Enable Register IEN1 37 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM IPO Address B8h Bit addressable Reset Value 00h BIT SYMBOL IPO 7 IPO 6 PPC IPO 5 PT2 IPO 4 PSO PSOR IPO 3 PT1 IPO 2 PX1 IPO 1 PTO IPO 0 PXO PPC PT2 PSOPSO PT1 PX1 PTO PXO FUNCTION Reserved for future use Should be set to 0 by user programs PCA Interrupt Priority bit Low Bit Timer 2 Interrupt Priority Low Bit Serial Port 0 Combined Tx Rx Interrupt SOSTAT 5 0 Receive Interrupt SOSTAT 5 1 Priority Low Bit Timer 1 Interrupt Priority Low Bit External Interrupt 1 Priority Low Bit Timer 0 Interrupt Priority Low Bit External Interrupt O Priority Low Bit Figure 22 Interrupt Priority Register IPO IPOH Address B7H Not bit addressable Reset Value 00h BIT SYMBOL IPOH 7 IPOH 6 PPCH IPOH 5 PT2H IPOH 4 PSOH PSORH IPOH 3 PT1H IPOH 2 PX1H IPOH 1 PTOH IPOH O PXOH 7 6 5 4 3 2 1 0 A PPCH PT2H PSOHPSORH PT1H PX1H PTOH PXOH FUNCTION Reserved for future use Should be set to 0 by user programs PCA Interrupt Priority bit High Bit Timer 2 Interrupt Priority High Bit Serial Port 0
95. il the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode I C switches to the slave mode immediately and can detect its own slave address in the same serial transfer 75 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Q S Slave Address R A DATA A DATA E P 2 EY Data Transferred 0 Write n Bytes Acknowledge Read A Acknowledge SDA low A Not Acknowledge SDA high S START condition P STOP Condition From Master to Slave From Slave to Master Figure 59 Format of slave transmitter mode 76 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Figure 60 I C Bus Serial Interface Block Diagram Z For E r P1 7 Address Register I2ADR Input Comparator Filter P1 7 SDA Output E Shift Register ACK Stage I2DAT Timing amp Control Logic Bit Counter Arbitration amp Sync Logic CCLK Input P1 6 SCL Filter Internal Bus p Interrupt Output Stage Serial Clock Generator Timer 1 T Overflow P1 6 I2CON Control Register amp SCL Duty Wes ees I2SCLH Cycle Registers I2SCLL Statu
96. ing the Status Byte or Boot Vector all three bytes are erased at the same time It is necessary to reprogram the Boot Vector bytes after erasing and updating the Status Byte 7 3 HARDWARE ACTIVATION OF THE BOOT LOADER The boot loader can also be executed by holding PSEN LOW EA greater than Vi such as 5 V and ALE HIGH or not con nected at the falling edge of RESET This is the same effect as having a non zero status byte This allows an application to be built that will normally execute the end user s code but can be manually forced into ISP operation If the factory default setting for the Boot Vector 00 FC is changed it will no longer point to the ISP BootFlash loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Status Byte After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s appli cation code beginning at address 00 0000H 5V A ao VPP 6V RST vec L 5V X1 TXD0 x2 Figure 76 In System Programming with a Minimum of Pins 7 4 IN SYSTEM PROGRAMMING ISP The In System Programming ISP is performed without removing the microcontroller from the syst
97. ions is valid in case EAM 1 since this is the only case when we have 23 bit wide external memory interface Otherwise external memory interface is only 16 bits wide Software has to be written with special considerations if user s application requires 23 bit wide address interface and accesses off chip code If an application is set in a way that the initial part of the code executed upon reset is off chip the instruction that sets the EAM bit in MXCON to EAM 1 must be located at or below address OOFBh This is to prevent the external bus from supplying a 16 bit address when a 23 bit address is required If the Program Counter would reach address 0100h while EAM 0 the apparent address to external hardware that is pre wired to expect a 23 bit address would become 01 0100 Therefore EAM bit must be configured while the high byte and the middle byte of executed instruction address are 0 since in this case both 16 and 23 bit wide address interface access the same memory location When application having 23 bit wide address interface with intention to use 51 interface toward memory mapped device is developed some coding rules have to be applied 23 bit address interface using external memory interface requires EAM 1 configuration If memory mapped device address is determined using address on P2 and RD WR control lines no changes in the code are required compared to the regular 51 since the device is going to be addressed using only the bottom 16 bits
98. ips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 24 List of Commands Record Types P89C669 Accepts in ISP Mode Commands Record type Function sent by host Display Device data or Blank Check Format 07xxxx07sssssseeeeeeffcc Where 07 number of data bytes in record XXXX don t care 07 function code for display blank check SSSSSS starting address MSB first eeeeee ending address MSB first ff subfunction 00 display data 01 blank check checksum More details on how ISP operates can be found in application note AN461 In circuit and In application programming of the 89C51Rx Rx2 66x microcontrollers 7 4 2 IN APPLICATION PROGRAMMING METHOD Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors All calls are made through a common interface PGM_MTP The programming functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at 00 FFFOh Results are returned in the registers The IAP calls are shown in Table 25 7 4 3 USING THE WATCHDOG TIMER WDT The P89C669 supports the use of the WDT in IAP The user specifies that the WDT is to be fed by setting the most significant bit of the function passed in R1 prior to calling PGM_MTP Requesting a WDT feed during IAP should only be performed in applica tions
99. ister or as two independent 8 bit registers Selection of the active DPTR may be changed by altering the Data Pointer Select DPS bit The DPS bit occupies the bottom bit of the AUXR1 register The DPS bit applies only to the two DPTRs not to the EPTR In the indirect addressing mode the currently active DPTR or the EPTR provides a data memory address for accessing the XDATA and HDATA space respectively When the DPTR is used for addressing only the XDATA space is available When the EPTR is used for addressing the entire HDATA space which includes the XDATA space may be accessed If the EPTR value exceeds 7E FFFF the limit of HDATA data accesses using EPTR will yield undefined results The reason for limiting HDATA addresses is to keep the addressing uniform for EPTR addressing and Universal Pointer addressing which is explained in a later section of this document Example Instruction External Data MOVX DPTR A Memory Data Pointers RIEN Location 0 Ai7ch 00 A17Ch Accumulator 1 2962h Figure 10 External data memory access using indirect addressing with DPTR Example Instruction External Data MOVX A EPTR Memory Location 01 1034h Accumulator 01 1034h Figure 11 External data memory access using indirect addressing with EPTR 19 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 2 6 PROGRAM MEMORY CODE T
100. it is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus so it can not enter slave mode STA STO and SI bit must be set to 0 The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 which means Write Thus the first byte transmitted is SLA W Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer IC will enter master transmitter mode by setting STA bit The I C logic will send the START condition as soon as the bus is free After the START condition is transmitted SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine where the user should load slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status code now is 18h 20h or 38h for the master mode and also 68h 78h or OBOh if the slave mode was enabled setting AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 18
101. ite of E1h to the WDTRST register Before the first 1Eh is written to WDTRST a write of any pattern other than 1Eh will not cause a reset Once an 1Eh is written to the WDTRST register any write of a pattern other than 1Eh or E1h to the WDTRST register will cause a watchdog reset The triggering event to restart the WDT is the second part writing E1h to the WDTRST SFR of the feed sequence Refer to Figure 62 for details of WDT operations including effects of illegal feed patterns to the WDTRST SFR 6 8 3 WDT CONTROL The P87C51Mx2 has a control register in the MX extended SFR space It has a 3 bit prescaler control to select the prescale factor for the watchdog timer clock WDCON should be loaded with selected value before WDT is turned on Writing to WDCON while WDT is enabled will result in unpredictable behavior 6 8 4 WATCHDOG RESET WIDTH When the WDT times out a reset will occur and the external reset RST pin will be driven high for 98 clock cycles WDCON Address 8Fh MX Extended SFR Space Not bit addressable 7 6 5 4 3 2 1 0 Reset Value 00h 2 WDPRE2 WDPRE1 WDPREO BIT SYMBOL FUNCTION WDCON 7 3 Reserved for future use Should be set to 0 by user programs WDCON 2 0 WDPRE2 0 Select WDT prescale factor Note that the value written to these bits will not be immediately available to be read until after a WDT feed sequence Figure 61 WDCON Register 84 2003 Sep 16 4
102. ith extended memory and 96kB FLASH with 2kB RAM baud rate is variable and is determined by the Timer 1 2 see T2CON 5 4 overflow rate or the Baud Rate Generator described later in section on Baud Rate Generator and Selection The Baud Rate Generator is the only source for baud rate for UART 1 6 6 3 MODE 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 When data is transmitted the 9th data bit TB8 n in SnCON can be assigned the value of 0 or e g the parity bit P in the PSW could be moved into TB8 n When data is received the 9th data bit goes into RB8 n in Special Function Register SOCON S1CON while the stop bit is ignored For UART 0 the baud rate is programmable to either 1 16 or 1 32 of the CPU clock frequency as determined by the SMOD1 bit in PCON For UART 1 the baud rate is from the Baud Rate Generator 6 6 4 MODE 3 11 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first a programmable 9th data bit and a stop bit logical 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate For UART 0 the baud rate in Mode 3 is variable and is determined by the Timer 1 2 see T2CON 5 4 overflow rate or the Baud Rate Generator described later in section on Baud Rate Generator and Selection Baud Rate Generator is the only source for baud
103. k may reside in the extended area if enabled to do so EDATA content can be accessed anytime using EMOV instruction regardless of bit EAM in MXCON SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing addresses in range 80h FFh This includes the new 51MX extended SFRs XDATA External Data Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR EPTR RO or R1 On chip XDATA can be disabled under program control Also XDATA may be placed in external devices P89C669 has 768 bytes of on chip XDATA memory space HDATA High Data This is a superset of XDATA and may include up to 8 323 072 bytes 8 MB 64 kB of memory space addressed via the MOVX instruction using the EPTR DPTR RO or R1 Non XDATA portion of HDATA is placed in external devices CODE 64 kB of internal code memory space 0000h FFFFh used for program storage and data accessed via MOVC ECODE Up to 8 MB of Code memory accessed as part of program execution and via the MOVC instruction All of these spaces except the SFR space may also be accessed through use of Universal Pointer addressing with the EMOV instruction This feature is detailed in a subsequent section Table 1 Sizes of on chip available memory segments for P89C669 Size Bytes and MX UniversalMemory Map Range Type Description P89C669 DATA data memory that can be addressed both
104. lained in 51MX Architecture Reference The device has on chip data memory that is mapped into the following segments Address 0000H 007FH are directly and indirectly addressable DATA memory Address 0080H 00FFH are indirectly addressable as RAM IDATA memory Note When 000080H 0000FFH is directly addressed SFRs will be accessed Address 0100H 01FFH for MB2 MC2 are extended indirectly addressable RAM part of EDATA memory There are also 1536 bytes of XDATA memory locations 000000H 0005FFH for MB2 and 2560 bytes of XDATA memory locations 000000H 0009FFH for MC2 If EXTRAM 0 this internal XDATA memory location is selected in a MOVX instruction to from locations 000000H 0005FFH for MB2 or 000000H 0009FFH for MC2 and external memory will be accessed above these locations If EXTRAM 1 the internal XDATA RAM will not be used and every MOVX instructions will always access external data memory RAM addressing described here is available in MX2 parts marked as P87C51Mx2 02 However earlier MX parts marked as P87C51MB2 and P87C51MC2 had slightly different RAM addressing Address 0100H 04FFH for MB2 MC2 were extended indirectly addressable RAM part of EDATA memory There were also 768 bytes of XDATA memory locations 000000H 0002FFH for MB2 and 1792 bytes of XDATA memory locations 000000H 0006FFH for MC2 Both new and old parts have the same amount of on chip RAM available for user s application Code writ
105. ll wait until it is addressed by its own address or general address followed by the data direction bit which is O W If the direction bit is 1 R it will enter slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 20 for the status codes and actions R S Slave Address WwW A DATA A DATA A A P RS s Data Transferred n Bytes Acknowledge 0 Write 1 Read A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition RS Repeated START condition Figure 58 Format of slave receiver mode 6 7 9 SLAVE TRANSMITTER MODE The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 7 SDA while the serial clock is input through P1 6 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application IPC may operate as a master and as a slave In the slave mode the I C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits unt
106. luding circuits standard cells and or software described or contained herein in order to improve design and or performance When the productis in full production status Production relevant changes will be communicated viaa Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Koninklijke Philips Electronics N V 2003 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 431 40 27 24825 Date of release 09 03 Document order number 9397 750 12083 Lett make things beter ness S PHILIPS For sales offices addresses send e mail to sales addresses www semiconductors philips com
107. ly available EPROM programmer The parallel program ming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmer will need to have support for these devices 7 2 3 BOOT FLASH When the microcontroller programs its own Flash memory all of the low level details are handled by code that is contained in a 4kB BootFlash that is separate from the Flash memory A user program simply calls the common entry point with appropriate parameters in the BootFlash to accomplish the desired operation BootFlash operations include things like erase block pro gram byte verify byte program security lock bit etc The BootFlash overlays the program memory space from addresses 00 F000 to 00 FFFF hex when it is enabled The default boot vector location which is the start of the ISP routines is 00 FCOO The BootFlash may be turned off ENBOOT 0 so that the upper 4kB of program memory are accessible for execution NOTE In order to access the BootFlash call to 00 F000 must with ACALL LCALL instruction since RET is used for return from the BootFlash Furthermore this restricts address from which call to the BootFlash can be made to the bottom 64K in the mem ory map Block 11 8KB 01 7FFFh 01 6000h 01 5FFFh Block 10 8KB pidas 01 4000h 01 3FFFh Block 9 8KB ibd 01 2000h Block 8 8KB o RUE 00 FFFFh Boot Block 4KB 00 F
108. means you can only access this register when SI bit is set Data in I2DAT remains stable as long as SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT I2DAT Address 93H Not bit addressable 7 6 5 4 3 2 1 0 Reset Source s Any reset I2DAT 7 I2DAT 6 I2DAT 5 I2DAT 4 I2DAT3 I2DAT2 I2DAT 1 I2DAT O Reset Value 00000000B Figure 51 I C Data Register 6 7 2 I C SLAVE ADDRESS REGISTER I2ADR register is readable and writable and is only used when the C is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized 69 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM I2ADR Address 94H Not bit addressable Reset Source s Any reset f 6 4 3 2 a Reset Value 00000000B IPADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR2 I2ADR 1 I2ADR O GC BIT SYMBOL FUNCTION I2ADR7 1 I2ADR 6 0 7 bit own slave address When in master mode the contents of this register has no effect I2ADR7 0 GC General call bit When set the general call address 00H is recognized otherwise it is ignored
109. mended that SMO n and SM1_n SnCON 7 6 are set up before SMODO is set to 1 It should also be noted that a break detect setting of BR n also sets FE n 60 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 6 8 STATUS REGISTER Each of the enhanced UARTS contains a status register The status register also contains some control bits DBMOD n n 0 1 The enhanced UART includes double buffering In order to be compatible with existing 80C51 devices this bit is reset to 0 to disable double buffering INTLO n For modes 1 2 and 3 the UART allows Tx interrupt to occur at the beginning or at the end of the STOP bit This bit is reset to 0 to select Tx interrupt to be issued at the beginning of the STOP bit Note that in the case of single buffering if Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit For UART mode O this bit must be cleared to 0 CIDIS n n 2 0 1 The UART can issue combined Tx Rx interrupt conventional 80C51 UART or have separate Tx and Rx interrupts This bit is reset to 0 to select combined interrupt e DBISEL n n 2 0 1 This bit is used only when the corresponding DBMOD n 1 If DBMOD n 0 this bit must be cleared to 0 for future compatibility This bit controls the number of interrupts that can occur when double buffering is enabled If O
110. mined with EAM 1 enables on chip code to go beyond 64 kB and utilize 96 kB of available code space Interface to external memory is through standard 51 external bus 16 bits address and 8 bits wide In this configuration PC is internally 23 bits wide and special attention is needed when EIFM Extended Interrupt Frame bit is configured If executable on chip code goes beyond 64 kB and this code can be interrupted EIFM must be set to 1 since address of interrupted instruction might be of 01 xxxx type Keeping EIFM 0 in application when PC crosses 64 kB will result in pushing of only 2 bytes of address to the stack Consequently after invoked interrupt service routine ISR is finished RETI instruction will direct further code execution to 00 xxxx due to popping only 2 bytes from the stack which can result in unpredicted system behavior If on chip memory code space above 64 kB is used for storage of constants only e g look up tables EIFM can be 0 since any address of executed code can be represented with only two bytes and it is sufficient to push only these two bytes onto the stack which is default for P89C669 part Once code starts from on chip code space no external code can be executed address bus enables access up to 64 kB of external RAM only Due to only 16 bits wide address bus in this mode even if EMOV instruction points to location above 64 kB e g yz xxxxx external memory will recognize this as address under 64 kB 00 xxxx
111. nd RCAP2H to be reloaded into the timer registers TL2 and TH2 52 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM TOGGLE DOWN COUNTING RELOAD VALUE EXF2 EI T he Pe m UNDERFLOW Timer 2 Oo TF2 P Interrupt OVERFLOW C T2 1 CONTROL VE T2Pin j TR2 A COUNT DIRECTION 1 UP 0 DOWN RCAP2L RCAP2H UP COUNTING RELOAD VALUE T2EX PIN Figure 37 Timer 2 in Auto Reload Mode DCEN 1 When a logic 0 is applied at pin T2EX this causes Timer 2 to count down The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H Timer 2 underflow sets the TF2 flag and causes OFFFFH to be reloaded into the timer registers TL2 and TH2 The external flag EXF2 toggles when Timer 2 underflows or overflows This EXF2 bit can be used as a 17th bit of resolution if needed 6 5 3 PROGRAMMABLE CLOCK OUT A 50 duty cycle clock can be programmed to come out on pin T2 P1 0 This pin besides being a regular I O pin has two additional functions It can be programmed 1 To input the external clock for Timer Counter 2 or 2 To output a 50 duty cycle clock ranging from 122Hz to 8MHz at a 16MHz operating frequency To configure the Timer Counter 2 as a clock generator bit C T2 in T2CON must be cleared and bit T20E in T2MOD must be set Bit TR2 T2CON 2 also
112. nd which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others MX2 part uses schemes presented in Figure 49 to determine if an Given or Broadcast address has been received or not rx byte 7 saddr 7 saden 7 Given address match ap saddr 0 rx byte 0 saden 0 Logic used by P87C51Mx2 UARTS to detect Given Address in received data saddr 7 saden 7 rx byte 7 Broadcast address match saddr 0 saden 0 rx byte 0 Logic used by P87C51Mx2 UARTS to detect Given Address in received data Figure 49 Schemes used by P87C51Mx2 UARTS to detect Given and Broadcast addresses when multiprocessor communications is enabled The following examples will help to show the versatility of this scheme Slave 0 SADDR 1100 0000 SADEN 1111 1101 Given 21100 00X0 Slave 1 SADDR 1100 0000 SADEN 1111 1110 Given 21100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires aO in bit O and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001
113. ning up counting 16 bit PCA timer The PCA timer is a common time base for all five modules and can be programmed to run at 1 6 the oscillator frequency 1 2 the oscillator frequency the Timer 0 overflow or the input on the ECI pin P1 2 The timer count source is determined from the CPS1 and CPSO bits in the CMOD SFR see Figure 67 88 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM l 16BITS MODULEO P1 3 CEXO MODULEI P1 4 CEX1 L 16BITS 4 PCA TIMER COUNTER MODULE2 P1 5 CEX2 TIME BASE FOR PCA MODULES MODULES _____ _ P16 CEX3 MODULE FUNCTIONS 16 BIT CAPTURE 16 BIT TIMER MODULE4 PL7 CEX4 16 BIT HIGH SPEED OUTPUT 8 BIT PWM WATCHDOG TIMER MODULE 4 ONLY Figure 65 Programmable Counter Array PCA In the CMOD SFR there are three additional bits associated with the PCA They are CIDL which allows the PCA to stop during idle mode WDTE which enables or disables the watchdog function on module 4 and ECF which when set causes an interrupt and the PCA overflow flag CF in the CCON SFR to be set when the PCA timer overflows The watchdog timer function is implemented in module 4 of PCA The CCON SFR contains the run control bit for the PCA CR and the flags for the PCA timer CF and each module CCF4 0 To run the PCA the CR bit CCON 6 must be set by softw
114. nternal data memory space IDATA may be accessed using indirect addressing For example the instruction sequence MOV RO 90h MOV A RO will cause the contents of location 90 hex to be loaded into the accumulator It is typical with the classic 80C51 to cause the stack to be located in the upper area leaving more general purpose RAM in the lower area that may be accessed using both direct and indirect addressing With the 51MX the stack may be extended and moved completely out of the lower 256 bytes of memory Undedicated Area Bit Addressable Segment Register Banks Figure 7 Internal data memory lower 128 Bytes 16 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 2 3 SPECIAL FUNCTION REGISTERS SFRS Special Function Registers SFRs provide a means for the processor to access internal control registers peripheral devices and I O ports An SFR address is always contained entirely within an instruction The standard SFR space is 128 bytes in size SFRs are implemented in each 51MX device as needed in order to provide control for peripherals or access to CPU features and functions Undefined SFRs are considered reserved and should not be accessed by user programs Sixteen addresses in the SFR space are both byte and bit addressable The bit addressable SFRs are those whose address ends in Oh or 8h i e 80h 88h
115. odule 4 WDTE 1 enables it CMOD 5 3 Reserved for future use Should be set to 0 by user programs CMOD 2 1 CPS1 CPSO PCA Count Pulse Select CMOD 0 EC a CPS1 CPSO Select PCA Input 0 0 0 Internal Clock fosc 6 0 1 1 Internal Clock fosc 2 1 0 2 Timer 0 Overflow 1 1 3 External Clock at ECI P1 2 pin max rate fosc 4 interrupt ECF 0 disables that function PCA Enable Counter Overflow Interrupt ECF 1 enables CF bit in CCON to generate an Figure 67 CMOD PCA Counter Mode Register 90 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM CCON Address 0D8H Bit addressable Reset Value 00h BIT CCON 7 CCON 6 CCON 5 CCON 4 CCON 3 CCON 2 CCON 1 CCON 0 SYMBOL CF CR CCF4 CCF3 CCF2 CCF1 CCFO 7 6 5 4 3 2 1 0 CF CR CCF4 CCF3 CCF2 CCF1 CCFO FUNCTION PCA Counter Overflow Flag Set by hardware when the counter rolls over CF flags an interrupt if bit ECF in CMOD is set CF may be set by either hardware or software but can only be cleared by software PCA Counter Run Control Bit Set by software to turn the PCA counter on Must be cleared by software to turn the PCA counter off Reserved for future use Should be set to 0 by user programs PCA Module 4 Interrupt Flag Set by hardware when a match or capture occurs
116. odules 6 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Low EMI inhibit ALE Watchdog timer with programmable prescaler for different time ranges compatible with 8xC66x with added prescaler 80C51 COMPATIBILITY FEATURES OF THE 51MX CORE 100 binary compatibility with the classic 80C51 so that existing code is completely reusable Linear program and data address range expanded to support up to 8 MB each Program counter and data pointers expanded to 23 bits Stack pointer extended to 16 bits 7 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 1 3 P89C669 LOGIC SYMBOL MBs eS l 4 T2 Address bus 0 7 a 4 T2EX lt _ _ 5 gt ECI Data bus E Eo CEX0 q lt Q Q 4 CEX1 P 4 CEX2 gt 4 SCL is L lt SDA RXDO E E A TXD0 4 as lt Te gt gt INTO EEG P89C669 Address Bus INTI gt Ir QN 16 23 CEX3 TO0 O rd NEG CEX4 TI amp O gt E AUR RD gt L L TDI Address Bus 8 15 RST XTAL2 EA Vpp PSEN XTAL1 ALE PROG Figure 1 P89C669 logic symbol 8 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User
117. on set A small number of instructions have extended addressing modes to allow full use of extended code and data addressing Addressing Modes A new addressing mode Universal Pointer Mode is added that allows accessing all of the data and code areas except for SFRs using a single instruction This mode produces major improvements in size and performance of compiled programs Six clock cycles per machine cycle The 51MX core is described in more details in the 51MX Architecture Reference 1 2 P89C669 MICROCONTROLLERS The P89C669 represents the first FLASH microcontroller based on the Philips Semiconductor s new 51MX core The P89C669 features 96 kB of FLASH program memory and 2 kB of data SRAM In addition this device is equipped with a Programmable Counter Array a watchdog timer that can be configured to different time ranges as well as two enhanced UARTS and byte based Fast I C serial interface 400 kb s The P89C669 provides greater functionality increased performance and overall lower system cost By offering an embedded memory solution combined with the enhancements to manage the memory extension the P89C669 eliminates the need for software workarounds The increased program memory enables design engineers to develop more complex programs in a high level language like C for example without struggling to contain the program within the traditional 64 kB of program memory These enhancements also greatly improve C language effi
118. ontrol the part will execute several instructions after the point in code when the Idle mode was invoked i e the device normally resumes program execution from where it left off On chip hardware inhibits access to the internal RAM during this time but access to the port pins is not inhibited so insertion of 3 NOP instructions is recommended following the instruction that invokes idle mode To eliminate the possibility of unexpected outputs at the port pins in general the instruction following the one that invokes Idle mode should not be the one that writes to a port pin or to external data RAM 6 3 3 POWER DOWN MODE To save even more power a Power Down mode see Table 11 can be invoked by software In this mode the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed This mode stops the oscillator in order to absolutely minimize power consumption Power Down mode is entered by setting the PD bit in the PCON register Table 11 External Pin Status During Idle and Power Down Modes Program Memory PSEN PORT 0 PORT 1 PORT 2 9 omm 3 3 om a ee 9e we mw 3 0 p rem ses eem ce Teen mew 3 3 m om om Dm Poverbow mw s 3 p rem me Des Dus The processor can be made to exit Power Down mode via Reset or one of the external interrupt inputs INTO INT1 configured to be level sensitive only This will occur if the interrupt is enabled and its priority is higher
119. ontroller with extended memory and 96kB FLASH with 2kB RAM The signal to load SBUF and RB8 RB8 0 for UART 0 or RB8 1 for UART 1 and to set RI RI 0 for UART 0 or RI 1 for UART 1 will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 SM2 0 for UART 0 or SM2_1 for UART 1 0 or the received stop bit 1 If either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated 6 6 10 MORE ABOUT UART MODES 2 AND 3 Reception is performed in the same manner as in mode 1 The signal to load SBUF and RBS8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF 6 6 11 EXAMPLES OF UART DATA TRANSFER USING DIFFERENT MODES Figures 45 to 47 show how single byte is transmitted over UART depending on the chosen mode Double buffering was not used in modes 1 2 and 3 st i se s t se s ni sejs1 se s se s Y se s se s n se s a se s E se s se s se s se Wri
120. ore only the lower 16 bits of the PC When EIFM 1 an interrupt service will cause all 23 bits of the PC to be pushed onto the stack while an RETI instruction will restore all 23 bits of the PC EIFM must be set to one if the application allows execution beyond the first 64 kB of code memory Figure 6 MX Configuration Register MXCON EAM bits control access to CODE ECODE and XDATA HDATA space EDATA memory space can fully be accessed anytime with EMOV instruction regardless of the value of EAM bits 15 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 2 2 6 GENERAL PURPOSE RAM Portions of the internal data memory that are not used in a particular application as registers stack or bit addressable locations may be considered general purpose RAM and used in any desired manner The lower 128 bytes of the internal data memory DATA may be accessed using either direct or indirect addressing Direct addressing incorporates the entire address within the instruction For example the instruction MOV 31h 10 will store the value 10 decimal in location 31 hex Direct addresses above 128 will access the Special Function Registers rather than the internal data memory Indirect addressing takes an address from either RO or R1 of the current register bank and uses it to identify a location in the internal data memory The entire 256 byte i
121. ortion of the address for the next bus operation This may be either a data address or a code address PSEN Program Store Enable Indicates that the processor is reading code from the bus Typically connected to the Output Enable pin of external EPROMs or other memory devices External bus addresses for code memory may range from 00 0000 through 7F FFFF In the Universal Memory Map these correspond to addresses 80 0000 through FF FFFF RD Read The external data read strobe Typically connected to the RD pin of external peripheral devices WR Write The write strobe for external data Typically connected to the WR pin of external peripheral devices External bus addresses for data memory may range from 00 0000 through 7E FFFF which matches Universal Memory Map addresses If on chip XDATA is enabled it will cause an addressing discontinuity in the external data address space The DATA and IDATA spaces are always on chip and therefore always create such an addressing discontinuity 35 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 5 INTERRUPT PROCESSING The P87C51Mx2 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P87C51Mx2 has eleven interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers
122. ory occupies the top of the map Thus the most significant bit of the Universal Pointer determines whether code or data memory is accessed By placing the XDATA space at the bottom of the Universal Memory Map Universal Pointer addresses 00 0000 through 00 FFFF can correspond to the classic 80C51 external data memory space This allows for full backward compatibility for code that does not need more than 64 kB of external data space The Universal Memory Map is shown in Figure 16 while the standard view of the memory spaces and how they relate to Universal Pointer values are shown in Figure 17 The Universal Pointers are used only by a new 51MX instruction called EMOV The EMOV instruction allows moving data via one of the Universal Pointers into or out of the accumulator In either case a displacement of 0 1 2 or 3 may also be specified which is added to the pointer prior to its use The displacement allows C compiler access of variables of up to 4 bytes in size e g Long Integers without the need to alter the pointer value An example of Universal Pointer usage is shown in Figure 18 Note that it is not possible to store a value to the CODE area of the Universal Memory Map Another new instruction is added to allow incrementing one of the Universal Pointers by a value from 1 to 4 This allows the pointer to be advanced past the last data element accessed to the next data element 22 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 Us
123. present on the 23 bit wide address bus However if memory mapped device uses falling edge on ALE control line to latch its 16 bit address MOVX Ri DPTR instruction can not be used but EMOV PRi Falling edge on ALE will enable address 7 0 to be fetched on PO but at the same time bits address 22 16 will be present on P2 The right value that memory mapped device is expecting is available on falling edge of RD WR when address 15 8 bits are available on P2 In the system with 23 address bits MOVX Ri DPTR instruction outputs leading zeros for address 22 16 which may cause problem for targeted device In order to avoid this situation instruction EMOV PRi 34 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM has to be used with R3 R2 when PRO is used or R7 R6 when PR1 is used By doing this output on P2 will be the same both on falling edge of ALE and falling edge of RD WR and consequently memory mapped device will recognize its address when required Detailed waveforms on external memory access can be found in the data sheet written for the desired MX part Figure 19 Example of external code memory read cycles using 23 address bits The standard control signals and their functions for the external bus are as follows Signal name Function ALE Address Latch Enable This signal directs an external address latch to store the multiplexed p
124. r with extended memory and 96kB FLASH with 2kB RAM SnCON SOCON Address 98h Conventional SFR Space S1CON Address 80h MX Extended SFR Space Bit addressable Reset Value 00h BIT SnCON 7 SnCON 6 SnCON 5 SnCON 4 SnCON 3 SnCON 2 SnCON 1 SnCON 0 SYMBOL SMO n FE n SM1_n SMO n SM1 n 00 0 1 10 11 SM2 n REN n TB8 n RB8 n TI n RI n 7 6 5 4 3 2 1 0 SM0 nFE n SM1_n SM2_n REN_n TB8 n RBB n TI n Rin FUNCTION The usage of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is SMO n which with SM1 n defines the serial port mode If SMODO 1 this bit is FE n Framing Error FE n is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but can only be cleared by software Note It is recommended to set up UART mode bits SMO n and SM1 n before setting SMODO to 1 With SMO n defines the serial port mode see table below UART Mode UART 0 Baud Rate UART 1 Baud Rate 0 shift register CPU clock 6 CPU clock 6 1 8 bit UART Variable see Table 15 Baud Rate Generator see Table 16 2 9 bit UART CPU clock 32 or CPU clock 16 Baud Rate Generator see Table 16 3 9 bit UART Variable see Table 15 Baud Rate Generator see Table 16 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 nis set to 1 then RI n will not be activa
125. re 31 Timer Counter 0 or 1 in Mode 2 8 Bit Auto Reload 48 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 4 4 MODE 3 When Timer 1 is in Mode 3 it is stopped holds its count The effect is the same as setting TR1 O Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 and Timer 0 is shown in Figure 32 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P87C51Mx2 can look like it has an additional Timer Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt Osc 6 C T 0 Sis TLO s o cela We Interrupt r 8 bits TO Pin L e CT 1 Control i TRO TnGate INTO Pin THO Overflow Osc 2 e o 8 bits W Interrupt Control TR1 Figure 32 Timer Counter 0 Mode 3 Two 8 Bit Counters 65 TIMER 2 Timer 2 is a 16 bit Timer Counter which can operate as either an event timer or an event counter as select
126. rst instruction located at address 0 should not be an EJMP instruction EJMP is a 5 byte instruction and would overlap any instructions intended for the external interrupt O vector address residing at 00 0003 Example Instruction MOVC A A PC Accumulator Location 3E 97FFh 3E 98D2h 3E 98D2h Accumulator Figure 12 Code memory access using Indexed indirect addressing with the Program Counter 20 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Example Instruction MOVC A A DPTR executed at address 01 59B3 Accumulator Upper 7 bits of Program Counter 01h Data Pointers Location 0 C340h 01 FFAEh Accumulator 1 FFOCh 01 FFAEh Figure 13 Code memory access using indexed indirect addressing with DPTR Example Instruction MOVC A A EPTR Accumulator Location 12 B109h 12 B1D6h 12 B1D6h Accumulator Figure 14 Code memory access using indexed indirect addressing with EPTR 2 7 UNIVERSAL POINTERS A new addressing mode called Universal Pointer mode has been added to the 51MX specifically for the purpose of greatly enhancing C language code density and performance This addressing mode allows access to any of the on chip or off chip code and data spaces using one instruction without the need to know in advance which of the different spaces the data will reside in This includes the DATA IDATA EDATA XD
127. rt of UART1 Both of them have internal pull up resistor 6 3 P89C669 LOW POWER MODES 6 3 1 STOP CLOCK MODE The static design enables the clock speed to be reduced down to 0 MHz stopped When the oscillator is stopped the RAM and Special Function Registers retain their values This mode allows step by step utilization and permits reduced system power consumption by lowering the clock frequency down to any value For lowest power consumption the Power Down mode is suggested 6 3 2 IDLE MODE In the idle mode see Table 11 the CPU puts itself to sleep while all of the on chip peripherals stay active The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated The CPU contents the on chip RAM and all of the special function registers remain intact during this mode Idle mode is entered by setting the IDL bit in the PCON register There are two ways to terminate the Idle mode Activation of any enabled interrupt will cause IDL to be cleared by hardware terminating the Idle mode The interrupt is serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle Hardware reset is the second way to exit Idle mode and the processor continues in the same manner as in case of power on reset Hardware reset by default clears IDL bit to 0 Before reset really occurs and internal reset algorithm takes c
128. ry space using 23 bit addressing The entire 8 megabyte space except for the 64 kB EDATA space is called HDATA The XDATA space comprises the lower 64 kB of HDATA Data Pointers The 51MX adds an additional 23 bit Extended Data Pointer EPTR in order to allow a simple method of extending existing 80C51 programs to use more than 64 kB of data memory If we want to access a single data byte from HDATA RAM located above the first 64 kB EAM bit in MXCON sfr must be set to EAM 1 All 80C51 instructions that use the DPTR have an 51MX variant that uses the EPTR The 23 bit EPTR is comprised of in order EPH EPM and EPL sfrs Figures 10 and 11 show examples of indirect accesses to data memory using the DPTR and the EPTR respectively Since the EPTR is a 23 bit value the 8th bit of EPH is not used If read it returns a 1 like other unimplemented bits in sfrs EPTR can be manipulated as 23 bit register or as three independent 8 bit registers Use of the EPTR allows access to the entire HDATA space including XDATA 18 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM At any point in time one specific Data Pointer is active and is used by instructions that reference the DPTR Active Data Pointer DPTR consists of a high byte DPH sfr and a low byte DPL sfr and its intended function is to hold 16 bit address however it may be manipulated as a 16 bit reg
129. s labeled in the SFRs are X s unknown at all times 1 s should NOT be written to these bits as they may be used for other purposes in future derivatives The reset values shown for these bits are 0 s although they are unknown when read 96 The unimplemented bits labeled in the SFRs are X s unknown at all times 1 s should NOT be written to these bits as they may be used for other purposes in future derivatives The reset values shown for these bits are O s although they are unknown when read 6 2 P89C669 PORTS 6 2 1 X PORTS 0 1 2 3 Ports 0 1 2 3 are the same as the ports in a conventional 80C51 device They are located at the same bit addressable locations of 80H 90H AOH and BOH in the conventional SFR space Observed port s output is logical and of port s sfr and microcontroller s peripheral that is using that port In order to allow peripheral to fully control dedicated pin corresponding bit s in port s sfr must be 1 Otherwise if some of port s bits are Os output of peripherals using those pins will not be able to change output which is going to be low all the time due to port bit s 0 43 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 2 2 PORT 4 The P89C669 has an additional port called Port 4 This port is not available as general purpose I O It hosts pins RXD1 P4 0 and TXD1 P4 1 that are pa
130. s Bus Status Decoder I2STAT Status Register 77 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 18 Master Transmitter Mode STATUS STATUS OF THE CODE IPSTAT I2C BUS HARDWARE A START condition has been transmitted A repeat START condition has been transmitted SLA W has been transmitted ACK has been received SLA W has been transmitted NOT ACK has been received Data byte in I2DAT has been transmitted ACK has been received Data byte in I2DAT has been transmitted NOT ACK has APPLICATOPN SOFTWARE RESPONSE TOFROMI2DAT Load SLA W Load SLA W or Load SLA R Load data byte or no I2DAT action or no I2DAT action or no I2DAT action Load data byte or no I2DAT action or no I2DAT action or no I2DAT action Load data byte or no I2DAT action or no I2DAT action or no I2DAT action Load data byte or no I2DAT action or no I2DAT action or NEXT ACTION TAKEN BY I2C HARDWARE SLA W will be transmitted ACK bit will be received As above SLA W will be transmitted 12C will be switches to master receiver mode Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag will be reset STOP condition followed by a START condition will be transmitted STO flag will be reset
131. sed as both bytes and bits This allows a convenient and efficient way to manipulate individual flag bits without using much memory space The bottom bit of the byte at address 20h is bit number OOh the next bit in the same byte is bit number 01h etc The final bit bit 7 of the byte at address 2Fh is bit number 7Fh 127 decimal Bit numbers above this refer to bits in Special Function Registers This code SETB 20h 1 CPL 20h 2 JNB 20h 2 LABEL1 sets bit 1 at address 20 hex complements bit 2 in the same byte then branches if the second bit is not equal to 1 In an actual program these bits would normally be given names and referred to by those names in the bit manipulation instructions 12 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 2 2 3 EXTENDED DATA MEMORY EDATA The 51MX architecture allows for extension of the internal data memory space beyond the traditional 256 byte limit of classic 80C51s This space can be used as an extended or alternative processor stack space or can be used as general purpose storage under program control Other than Stack Pointer based access to this space which is automatic if Extended Stack Memory Mode is enabled see the following Stack section this memory is addressed only using the new Universal Pointer feature Universal Pointers are described in a later section P89C669 has 1280 bytes of SRAM in E
132. since a 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 67 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Slave 0 SADDR 1110 0000 SADEN 1111 1001 Given 21110 0XX0 Slave 1 SADDR 1110 0000 SADEN 1111 1010 Given 21110 0X0X Slave 2 SADDR 1110 0000 SADEN 1111 1100 Given 21110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast addre
133. ss of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 6 7 I C SERIAL INTERFACE I C bus uses two wires SDA and SCL to transfer information between devices connected to the bus and it has the following features Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I C bus may be used for test and diagnostic purposes A typical I C bus configuration is shown in Figure 50 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus Datatransfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowle
134. ster receiver mode 2 A data byte has been received while the I C is in the addressed slave receiver mode Reserved for future use Should not be set to 1 by user programs SCL clock selection When CRSEL 1 Timer1 overflow generates SCL when CRSEL 0 Internal SCL generator is used base on values of I2SCLH and I2SCLL Figure 53 I2C Control Register 6 7 4 I C STATUS REGISTER This is a read only register It contains the status code of I C The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined I C states When any of these states is entered SI bit will be set Refer to Table 18 to Table 21 for details 71 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM I2STAT Address 92h Not bit addressable Reset Source s Any reset 7 6 2 4 3 2 g Reset Value 11111000B STA 4 STA 3 STA 2 STA 1 STA 0 0 0 0 BIT SYMBOL FUNCTION I2STAT7 3 STA 4 0 12C the status code I2STAT2 0 These three bits are not used and always set to 0 Figure 54 I C Status Register 6 7 5 IC SCL DUTY CYCLE REGISTER I2SCLH AND I2SCLL When internal SCL generator is selected for I C interface by setting CRSEL 0 in I2CON register user must set values for register SC
135. t Parameters R1 05h EPL 00h PROGRAM SECURITY BITS READ DEVICE DATA program Olh program 02h program Return Parameter ACC 00 if passed Input Parameters R1 03h EPTR Return Parameter ACC value of byte security bit 1 security bit 2 security bit 3 00 if failed address of byte to read read 105 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 25 IAP calls IAP Function IAP CALL PARAMETER Input Parameters R1 00h EPL 00h manufacturer ID 01h device ID 41 02h device ID 2 80h ROM code version Return Parameter ACC value of byte read READ ID BYTES Input Parameters R1 07h EPL 00h status byte Oih boot sector 0 02h boot sector 1 READ SPECIAL CELL 03h reserved 04h config byte 05h security bits Return Parameter ACC value of byte read 106 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Purchase of Philips 12C components conveys a license under the Philips 12C patent to use the components in the 12C system provided the system conforms to the 12C specifications defined by Philips This specification can be ordered using the code 9398 393 40011 Definitions Short form specification T
136. te is received while RI in SnCON is still set If an overrun occurs SnBUF retains the old data and the new character received is lost Cleared by software SnSTAT O STINT_n Status Interrupt Enable 0 FEn BR n OE_n cannot cause any interrupt 1 FE n BR n OE ncan cause interrupt The interrupt used is shared with RI n CIDIS_n 1 or combined TI n RI n CIDIS n 0 Figure 44 Serial Port Status Register SnSTAT 6 6 9 MORE ABOUT UART MODE 1 Reception is initiated by a detected 1 to 0 transition at RxD For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16ths At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the unit goes back to looking for another 1 to 0 transition This is to provide rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed 62 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microc
137. te to SBUF fl Shift 1 1 1 1 n 1 1 1 TxD Shift Clock TI AENEID n Transmit Write to SCON Clear RI RI l Shift l l l l l l l 1 Receive RxD DO D1 D2 D3 D4 D5 D6 D7 Data In i i i i i TxD Shift Clock Figure 45 Serial Port Mode 0 Only Single Transmit Buffering Case Is Shown 63 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM TX Clock I l Il l 1 I JL T IL dL dL mL Imm IL Write to SBUF fl S Shift I I I I I I IL mL Inm S Transmit TD StatBij XDI X D2 X D3 X D4 X D5 X D6 X D7 Y StopBit TI INTE n 0 INTO n 1 RX Clock fl l 1 Il l fl l I l l fl l fl l RxD 16 Reset gt Star Bi DO X Di X D2 X Ds X D4 X D5 X D6 X D7 Y SoB Shift rl rl rl j fl fl Receive RI Figure 46 Serial Port Mode 1 Only Single Transmit Buffering Case Is Shown TX Clock 1 1 1 1 1 I I IT j Im mnm Idm Im IL Write to SBUF l Shift I IL n m nm m nm m m Transmit TS StatBij DO X D X D2 X D3 X D4 X D5 X D6 X D7 X TB8 Stop Bit T ee INTEO_n 0 INILO n 1 RX Clock fl 1 fl fl 1 1 MNM IL mL mL m I gm IL RxD 16 Reset Start Bit lt DO X D1 X D2 X D3 X D4 X D5 X D6 X D7 X RBB8 X Stop Bit Shift I 1 MN MNM TE AM NM NM M M RI Receive MODO SMODO 1 Figure 47 Serial Port Mode 2 or 3 Only Single Transmit Bu
138. ted if the received 9th data bit RB8 n is 0 In Mode 1 if SM2_n 1 then RI n will not be activated if a valid stop bit was not received In Mode 0 SM2 n should be 0 Enables serial reception Set by software to enable reception Clear by software to disable reception The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired In Modes 2 and 3 is the 9th data bit that was received In Mode 1 it SM2 nz0 RB8 nis the stop bit that was received In Mode 0 RB8 n is undefined Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the the stop bit see description of INTLO n bit in SnSTAT register in the other modes in any serial transmission Must be cleared by software Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO 0 it is set near the middle of the 9th data bit bit 8 if SMODO 1 itis set nearly the middle of the stop bit See SM2 n for exceptions Must be cleared by software 6 6 7 Figure 43 Serial Port Control Register SnCON FRAMING ERROR Framing error FE n is reported in the status register SnSTAT In addition if SMODO PCON 6 is 1 framing errors for VARTs 0 and 1 can be made available to the SOCON 7 and S1CON 7 respectively If SMODO is 0 SOCON 7 and S1CON 7 are SMO for UARTS 0 and 1 respectively It is recom
139. ten for older revisions can easily be recompiled for the new one variables stored in EDATA space above 01FF have to be moved to added portion of XDATA memory space 87 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM AUXR1 Address A2h 7 6 5 4 3 2 1 0 Not bit addressable ENBOOT GF2 0 DPS Reset Value 00h BIT SYMBOL FUNCTION AUXR1 7 6 Reserved for future use Should be set to 0 by user programs AUXR1 5 ENBOOT Determines whether the BOOTROM is enabled or disabled For details see chapter on Flash Memory AUXR1 4 Reserved for future use Should be set to 0 by user programs AUXR1 3 GF2 General purpose user defined flag AUXR1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register AUXR1 1 Reserved for future use Should be set to 0 by user programs AUXR1 0 DPS Data Pointer Select Chooses one of two Data Pointers for use by the program See text for details Figure 64 AUXR1 Register 6 9 2 DUAL DATA POINTERS The dual Data Pointer DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is
140. tes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 56 Format of master receiver mode After a repeated START condition Ic may switch to the master transmitter mode e S SLA R A DATA A DATA A RS SLA W A DATA A P ze Data Transferred n Bytes Acknowledge A Acknowledge SDA low A Not Acknowledge SDA high S START condition P STOP Condition SLA Slave Address RS Repeat START condition From Master to Slave From Slave to Master Figure 57 A master receiver switch to master transmitter after sending repeated START 6 7 8 SLAVE RECEIVER MODE In the slave receiver mode data bytes are received from a master transmitter To initialize the slave receiver mode user should write the Slave Address Register I2ADR and the I C Control Register I2CON should be configured as follows 7 6 5 4 3 2 1 0 I2CON 91h I2EN STA STO SI AA CRSEL 1 0 0 0 1 74 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM CRSEL are not used for slave mode I2EN must be set to 1 to enable I C function AA bit must be set to 1 to acknowledge its own slave address or the general call address STA STO and SI are set to O After I2ADR and I2CON are initialized it wi
141. that existing code is completely reusable Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 kB of on chip program FLASH 2 kB of on chip data RAM Programmable Counter Array PCA Two full duplex enhanced UARTs byte based I C serial interface KEY BENEFITS Increases program data address range to 8 MB each Enhances performance and efficiency for C programs Fully 80C51 compatible microcontroller Provides seamless and compelling upgrade path from classic 80C51 Preserves 80C51 code base investment knowledge and peripherals amp ASICs Supported by 80C51 development and programming tools The P89C669 makes it possible to develop applications at a lower cost and with a reduced time to market COMPLETE FEATURES Fully static Up to 24 MHz CPU clock with 6 clock cycles per machine cycle 96 kB of on chip FLASH with In System Programming ISP and In Application Programming IAP capability 2 kB of on chip RAM 23 bit program memory space and 23 bit data memory space Four level interrupt priority 32 I O lines 4 ports Three Timers TimerO Timer1 and Timer2 Byte based I C serial interface Two full duplex enhanced UARTS with baud rate generator Framing error detection Automatic address recognition Power control modes Clock can be stopped and resumed Idle mode Power down mode Second DPTR register Asynchronous port reset Programmable Counter Array PCA compatible with 8xC51Rx with five Capture Compare m
142. that use the WDT since the process of feeding the WDT will start the WDT if the WDT was not running 103 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 104 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Table 25 IAP calls IAP Function IAP CALL PARAMETER Input Parameters R1 02h EPTR address of byte to program ACC byte to program Return Parameter ACC 00 if passed PROGRAM DATA BYTE 00 if failed Input Parameters R1 OCh EPH 00h EPM 00 20 40 60 80 AO CO EO 0 8 16 24 32 40 48 56 loc loc loc loc loc loc loc lock ERASE BLOCK DDDDDDD D5S oooovcoo0o 0 YAO 50NPDG CO VON AN ON ON ON AW AW 00 20 40 60 Return Parameter ACC 00 if passed 64 72 80 88 k 8 k 9 k10 k11 to to to to Br D 100 if failed Input Parameters R1 04h Return Parameter ACC 00 if passed ERASE STATUS BYTE amp BOOT VECTOR BYTES 00 if failed Input Parameters R1 06h EPL 00h olih 02h program status byte program boot vector 0 program boot vector 1 03h reserved 04h program config byte to program PROGRAM SPECIAL CELL ACC Return Parameter ACC 00 if passed 00 if failed Inpu
143. the Neither 1Eh nor Elh Ri WDTRST SFR 1Eh WDT enabled Wait for next write to the WDTRST SFR Time out P Ehh ritten OEIh to the Neither 1Eh nor Elh WDTRST SFR Elh Restart WDT Neither 1E h nor El WDT Reset Figure 62 Watchdog Timer State Transitions 86 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 9 ADDITIONAL FEATURES AUXR Address 8EH 7 6 5 4 3 2 1 0 Not bit addressable EXTRAM AO Reset Value 00h BIT SYMBOL FUNCTION AUXR 7 2 Reserved for future use Should be set to 0 by user programs AUXR 1 EXTRAM Internal External RAM access using MOVX Ri DPTR When 0 core attempts to access internal XRAM with address specified in MOVX instruction If address supplied with this instruction exceeds on chip available XRAM off chip XRAM is going to be selected and accessed When 1 every MOVX Ri DPTR instruction targets external data memory by default Refer to 51MX Architecture Reference AUXR O AO ALE Off disables enables ALE AO 0 results in ALE emitted at a constant rate of 1 2 the oscillator frequency In case of AO 1 ALE is active only during a MOVX EMOV or MOVC Figure 63 AUXR Register 6 9 1 EXPANDED DATA RAM ADDRESSING The P87C51Mx2 has expanded data RAM addressing capability Details of the data memory structure are exp
144. toggled Specific instructions affected by the Data Pointer selection are e INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A QDPTR Move data byte from data memory relative to DPTR to the accumulator MOVX QDPTR A Move data byte from the accumulator to data memory relative to DPTR Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 6 10 PROGRAMMABLE COUNTER ARRAY PCA The Programmable Counter Array available on the P87C51Mx2 is compatible with 89C51Rx2 The PCA includes a special 16 bit Timer that has five 16 bit capture compare modules associated with it Each of the modules can be programmed to operate in one of four modes rising and or falling edge capture software timer high speed output or pulse width modulator Each module has a pin associated with it in port 1 Module 0 is connected to P1 3 CEXO module 1 to P1 4 CEX1 etc Registers CH and CL contain current value of the free run
145. troller s internal resources and microcontroller s interface to external world with address and data bus MX part brings larger on chip code and data space available compared to previous 80C51 compatible microcontrollers In order to enable these enhancements to be used MX specific features had to be added and consequently instruction set had to be enriched MX Control Register MXCON determines mode of 669 s operation Although it is possible change of this register during application s execution is not advised Structure of MXCON is shown in Figure 6 Total of two operational modes are available using bit EAM EAM 0 After reset bit EAM 0 default value places P89C669 part in fully pin to pin 80C51 binary compatible micro Its interface with external world is with 16 bits wide address bus and 8 bits wide data bus PC is 16 bits wide and therefor on chip executable code can not go beyond 64 KB Use of MX specific instructions that relay on PC e g EMOV is limited to values contained in the lowest 14 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 16 bits of PC upper 7 bits are considered to be Os This is why EMOV instruction can not fetch content from internal code space above 64 kB boundary Once code starts from on chip code space no external code can be executed address bus enables access up to 64 kB of RAM only EAM 1 Mode deter
146. ual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Example Instruction Universal EMOV PR0 1 A Memory Map Location 12 C340h 12 C341h 12 C341h Accumulator Figure 18 Memory Access using Universal Pointer Addressing Universal Pointers are designed primarily to facilitate addressing in Extended Addressing Mode with the EAM bit in MXCON set to EAM 1 However Universal Pointers may still be used when EAM O In this case Universal Pointer addressing can access only the bottom 64 kB of Code space and the bottom 64 kB of XDATA space The Universal Pointer values that point to these areas do not change When EAM 0 Universal Pointer accesses outside of these areas are not accessible and will return a value of FF hex 25 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 3 51MX INSTRUCTIONS The 51MX instruction set is a a true binary level superset of the classic 80C51 designed to be fully compatible with previously written 80C51 code The changes to the instruction set are all related to the expanded address space Some details of existing instructions have been altered and some instructions have had an extended mode added In the latter case the alternate mode of the instruction is activated by preceding the instruction with a special one byte prefix code A5h An important goal in the implementation of the
147. upt will be generated at the beginning of the Stop Bit of the last character sent from the serial shift register if the transmit buffer register is empty Note that in this case if the transmit buffer is loaded before the end of the stop bit another interrupt will be generated and the UART will transmit this new character without lengthening the Stop Bit Write to l it if if l SnBUF Tx Interrupt t t t t Single Buffering DBMOD_n SnSTAT 7 0 Early Interrupt INTLO_n SnSTAT 6 0 is Shown Write to M it if SnBUF Tx Interrupt 1 ji 1 1 Double Buffering DBMOD n SnSTAT 7 1 Early Interrupt INTLO_n SnSTAT 6 0 is Shown No Ending Tx Interrupt DBISEL_n SnSTAT 4 0 me Wr 1 1 Tx Interrupt 1 1 1 1 1 Double Buffering DBMOD n SnSTAT 7 1 Early Interrupt INTLO_n SnSTAT 6 0 is Shown With Ending Tx Interrupt DBISEL n SnSTATA 1 Figure 48 Transmission with and without Double Buffering 8 Bit Case 65 20083 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 6 14 THE 9TH BIT BIT 8 IN DOUBLE BUFFERING If double buffering is disabled and 9 bit of data are to be transmitted bit TB8_n MUST be loaded before write access to SnBUF is performed since write to SnBUF results in loading of all 9 transfer data bits into UART s shift register If double buffering is enabled TB8 n MUST be updated before SnB
148. utput on port 1 associated with the PCA module will toggle each time a match occurs between the PCA counter and the module s capture registers To activate this mode the TOG MAT and ECOM bits in the module s CCAPMn SFR must be set CF CR CCF4 ccr3 CCF2 CCFi CCFO CONT WRITE TO CCAPnL RESET y capa CCAPnH CCAPnL TO CCFn oo gt PCA INTERRUPT 1 0 ENABLE 46 BIT COMPARATOR MATCH oo a al TOGGLE oo X p CEXn PCA TIMER COUNTER CCAPMn n 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn iHe A 0 0 1 1 0 Figure 72 PCA High Speed Output Mode All of the PCA modules can be used as PWM outputs Figure 73 Output frequency depends on the source for the PCA timer CCAPnH WEITE TO A CCAP4L RESET WEITE TO CCAPnL CCAP4H o gt 1 9 ENABLE CL CCAPnL p 8 BIT COMPARATOR CL gt CCAPnL jue CL PCA TIMER COUNTER ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 1 0 0 0 0 CCAPMn n 0 to 4 C2H C6H CEXn Figure 73 PCA PWM Mode 94 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FL
149. ws the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Figure 28 The GATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers 47 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM Mode 0 operation is the same for Timer 0 and Timer 1 see Figure 29 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 6 4 2 MODE 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 31 TLn THn 8 bits 8 bits TRn TnGate INTn Pin Overflow Interrupt Figure 30 Timer Counter 0 or 1 in Mode 1 16 Bit Counter 6 4 3 MODE 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 31 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 SE 2 Rd Overflow 59 Bw Interrupt Tn Pin CT 24 Control TRn TnGate INTn Pin Figu
150. y High Bit Reserved for future use Should be set to 0 by user programs Serial Port 1 transmit Interrupt S1STAT 5 1 Priority High Bit Serial Port 0 transmit Interrupt SOSTAT 5 1 Priority High Bit Serial Port 1 combined Tx RxInterrupt S1STAT 5 0 receive Interrupt S1STAT 5 1 Priority High Bit Figure 25 Interrupt Priority Register 1 High Byte 39 2003 Sep 16 4 12 pm Philips Semiconductors P89C669 User Manual 80C51 8 bit microcontroller with extended memory and 96kB FLASH with 2kB RAM 6 P89C669 PORTS POWER CONTROL AND PERIPHERALS 6 1 SPECIAL FUNCTION REGISTERS Note Special Function Registers SFRs accesses are restricted in the following ways 1 User must NOT attempt to access any SFR locations not defined 2 Accesses to any defined SFR locations must be strictly for the functions for the SFRs 3 SFR bits labeled 0 or 1 can ONLY be written and read as follows MUST be written with O but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with 0 and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read Special Function Registers E7 E6 E5 E4 E3 E2 E1 E0 Accumulator a ae gemmis ies Ee NEN CR F7 F6 F5 F4 F3 F2 F1 FO Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High

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