TIP501 - powerbridge.de
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1. N Write to CONVERT starts conversion N Start and shifts result of convesion N 1 conversion into the DATAREG Select new Select a new channel and a new gain gain amp new during conversion proceeds by a write channel access to CONTREG Pipeline Active 4 ADC y Read bit 1 of the STATREG Busy to check for end of conversion N Read data of Read result of the conversion N 1 conversion N 1 from DATAREG Figure 6 3 Flowchart Normal Mode with Data Pipeline For conversions without channel and gain change it is not necessary to observe the Settle Busy flag in the ADC STATREG register TIP501 User Manual Issue 1 1 7 Page 19 of 27 TEWSS TECHNOLOGIES 6 3 Automatic Mode Any write access to the ADC CONTREG register where bit 7 is set to 1 selects the Automatic Mode with the selected input channel input channel mode and gain The data conversion is started automatically by hardware when the settling time expires The conversion data is available in the ADC DATAREG register when the ADC Busy flag in the ADC STATREG is read as 0 If interrupts are enabled an interrupt is generated when the data conversion is done 6 3 1 State Diagram Automatic Mode no cycle next ADC busy 1 Figure 6 4 State Diagram Automatic Mode In Automatic Mode the ADC busy flag is active during the whole cycle of channel gain select settling time and data conversion When the ADC bu2. Automatic Mode with Data Pipeline CONTREG Bit 7 0 CONTREG Bit 7 1 Normal Mode Automatic Mode CONTREG Bit 8 0 Awrite access to the ADC After the settling time has Data Pipeline OFF CONVERT register starts expired conversion N is conversion N and shifts the started and the result of result of conversion N into conversion N is shifted into the ADC DATAREG register the ADC DATAREG register CONTREG Bit 8 1 Awrite access to the ADC After the settling time has Data Pipeline ON CONVERT register starts expired conversion N is conversion N and shifts the started and the result of result of conversion N 1 into conversion N 1 is shifted into the ADC DATAREG register the ADC DATAREG register Table 6 1 Operating Modes In Normal Mode the Settle Busy flag in the ADC STATREG register must be read 0 before a conversion is started TIP501 User Manual Issue 1 1 7 Page 16 of 27 TEWSS TECHNOLOGIES 6 2 Normal Mode Any write access to the ADC CONTREG register where bit 7 is set to 0 selects the Normal Mode with the selected input channel input channel mode and gain As long as the analog input path settling time has not expired the Settle Busy flag in the ADC STATREG register is read as 1 After the settling time has expired a conversion can be started by writing to the ADC CONVERT register The conversion data is available in the ADC DATAREG register when the ADC Busy flag in the ADC STA
3. TIP501 20 10V OV to 10V gain 1 5V OV to 5V gain 2 2V OV to 2V gain 5 1V OV to 1V gain 10 TIP501 11 TIP501 21 10V OV to 10V gain 1 5V OV to 5V gain 2 2 5V OV to 2 5V gain 4 1 25V OV to 1 25V gain 8 Input Overvoltage Protection up to 70Vpp Input ADC 16 bit ADC Data acquisition and conversion time up to 12 5 without channel gain change and up to 14 5us with channel gain change mode dependent Calibration Data Stored in ID PROM for gain and offset correction Accuracy For all TIP501 modules 4LSB after calibration Linearity For all TIP501 modules 4LSB No Missing Code Minimum 15 bit Power Requirements 380mA typical 5V DC TIP501 User Manual Issue 1 1 7 Page 7 of 27 TEWSS TECHNOLOGIES Physical Data Temperature Range Operating 40 to 85 Storage 45 to 125 C MTBF 637000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Humidity 5 95 non condensing Weight 31g TIP501 User Manual Issue 1 1 7 Table 2 1 Technical Specification Page 8 of 27 TEWSS TECHNOLOGIES 3 Functional Description 3 1 Ana
4. own ground in single ended mode or with shorted inputs in differential mode This error is corrected by subtracting the known error from all readings The second error is the gain error Gain error is the difference between the ideal gain and the actual gain of the programmable gain amplifier and the ADC It is corrected by multiplying the data value by correction factor The data correction values are obtained during factory calibration and are stored in the modules individual version of the ID PROM The ADC has a pair of offset and gain correction values for each of the programmable gains The correction values are stored in the ID PROM as two s complement 16 bit values in the range 32768 to 32767 For higher accuracy they are scaled to 1 4 LSB 3 2 1 ADC Correction Formula The basic formula for correcting any ADC reading for the TIP501 10 11 bipolar input voltage range is Value Reading 1 Gaincor 131072 Offseteor 4 The basic formula for correcting any ADC reading for the TIP501 20 21 unipolar input voltage range is Value Reading 1 Gaincor 262144 Offseteor 4 Value is the corrected result Reading is the data read from the ADC data register Gaincor and are the correction factors from the ID PROM Gaineor and Offsetco correction factors are stored for each gain factor Floating point arithmetic or scaled integer arithmetic is necessary to avoid rounding errors while
5. settling time has expired and shifts the result of conversion 1 into DATAREG Bit 1 of STATREG indicates ADC busy during the whole cycle Read data of the conversion N 1 from DATAREG Figure 6 6 Flowchart Automatic Mode with Data Pipeline TIP501 User Manual Issue 1 1 7 Page 22 of 27 TEWSS TECHNOLOGIES 7 Pin Assignment I O Connector 7 1 Analog Input Connections Pin Single ended Mode Differential Mode 01 ADC Input 1 02 ADC Input 1 04 ADC Input 2 05 ADC Input 2 07 ADC Input 3 08 ADC Input 3 10 ADC Input 4 11 ADC Input 4 13 ADC Input 5 14 ADC Input 5 16 ADC Input 6 17 ADC Input 6 19 ADC Input 7 20 ADC Input 7 22 ADC Input 8 23 ADC Input 8 24 AGND AGND Table 7 1 Analog Input Connections TIP501 User Manual Issue 1 1 7 Page 23 of 27 TEWSS TECHNOLOGIES 7 2 Power Input Connections Pin Signal 44 AGND 45 15V 46 AGND 47 15V 48 AGND 49 5V 50 AGND Table 7 2 Power Input Connections The power input connections are reserved for special versions of the TIP501 without an on board DC DC converter On the standard TIP501 board options 10 11 20 21 I O pins 45 47 and 49 not connected I O pins 44 46 48 and 50 are not connected to any on board signal but are connected to each other TIP501 User Manual Issue 1 1 7 Page 24 of 27 TEWSS TECHNOLOGIES 7 Connector Orientation Pi
6. 5 GAINO 01 G2 01 G2 10 G5 10 G4 11 610 11 G8 4 DIF Differential Mode Selection R W 0 0 Single ended Mode 16 single ended channels 1 16 are available 1 Differential Mode 8 differential channels 1 8 are available Channels 9 16 are used as 2 input for channels 1 8 3 CS3 Channel Selection input channel selection for data conversion R W 0 2 CS2 Single ended Differential 1 CS1 0000 CH1 0000 CH1 0 50 1111 CH16 0111 CH8 Table 5 2 CONTREG ADC Control Register Address 0x00 TIP501 User Manual Issue 1 1 7 Page 13 of 27 TEWSS TECHNOLOGIES 5 1 2 ADC Data Register Address 0x02 The ADC Data Register DATAREG contains the converted data value The 16 bit ADC value allows direct processing of the data as 16 bit two s complement integer value for the TIP501 10 11 and 16 bit straight binary for TIP501 20 21 Description ADC Data Value Binary two s complement Straight binary TIP501 10 11 TIP501 20 21 Full Scale FS 1LSB Ox7FFF OxFFFF Midscale 0x0000 0x8000 1 LSB Below Midscale OxFFFF Ox7FFF Full Scale 0x8000 0x0000 Table 5 3 ADC Data Coding The content of ADC DATAREG is only valid when the ADC Busy Flag is read as 0 5 1 3 ADC Status Register Address 0x05 Bit 0 and bit 1 of the ADC Status Register STATREG reflect the status for an A D conversion Bit Symbol Description Access Reset Value 7 2
7. ADC Data Ready event will create an individual interrupt An IP Interrupt Acknowledge cycle acknowledges and clears the interrupt Bit Symbol Description Access Reset Value 7 1 Interrupt vector loaded by software R W 0x00 0 Read as 1 for an interrupt from a settling time ready event R 0 Normal Settling Time Mode only Read 0 for an interrupt from an Data Ready event For example If the vector register is loaded with 0x60 Settling Time Ready event will create an interrupt vector 0x61 and a ADC Data Ready event will create an interrupt vector 0x60 In IP I O space bit 0 of the INTVEC is always read as 0 Table 5 5 INTVEC Interrupt Vector Register Address 0x09 The Settling Time Ready interrupt is generated on the falling edge of the Settle Busy status flag and uses IP INTREQ1 It is generated in Normal Settling Time Mode only The ADC Data Ready interrupt is generated on the falling edge of the ADC Busy status flag and uses IP INTREQO TIP501 User Manual Issue 1 1 7 Page 15 of 27 TEWSS TECHNOLOGIES 6 Operating Modes The TIP501 supports four operating modes selected by bit 7 Normal Automatic Settling Time Mode and bit 8 No Pipeline Mode Pipeline Mode of the ADC CONTREG register 6 1 Mode Overview Normal Mode without Data Pipeline Automatic Mode without Data Pipeline e Normal Mode with Data Pipeline
8. CONTENT 0 1 TABLE 5 1 REGISTER SET die Geena TABLE 5 2 CONTREG ADC CONTROL REGISTER ADDRESS 0X00 TABLE 5 3 ADC DATA TABLE 5 4 STATREG ADC STATUS REGISTER ADDRESS 0 05 TABLE 5 5 INTERRUPT VECTOR REGISTER ADDRESS 0 09 TABLE 6 1 OPERATING TABLE 7 1 ANALOG INPUT TABLE 7 2 POWER INPUT CONNEGCTIONS 2 TIP501 User Manual Issue 1 1 7 TEWSS TECHNOLOGIES Page 5 of 27 TEWSS TECHNOLOGIES 1 Product Description TIP501 is an IndustryPack compatible module providing 16 single ended or 8 differential channels of isolated 16 bit A D conversion The data acquisition and conversion time is up to 12us without channel gain change and up to 14 5us with channel gain change The input multiplexer offers analog overvoltage protection of up to 70Vpp programmable gain amplifier supports various input voltage ranges The input voltage range depends on the board option and the programmed gain factor Board Option Gain Factors Input Voltage Range TIP501 10 1 2 5 10 10V for gain 1 TIP501 11 1 2 4 8 10V for gain 1 TIP501 20 1 2 5 10 OV to 10V for gain 1 TIP501 21 1 2 4 8 OV to 10V for gain 1 Table 1 1 Board Option Overview The analog part and the ADC device are isolated from the system
9. TEWSS The Embedded I O Company TECHNOLOGIES TIP501 Optically Isolated 16 Channel 16 Bit ADC Version 1 1 User Manual Issue 1 1 7 January 2010 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com 501 10 Optically isolated 16 channel 16 bit ADC input voltage range 10V gain 1 2 5 10 TIP501 11 Optically isolated 16 channel 16 bit ADC input voltage range 10V gain 1 2 4 8 TIP501 20 Optically isolated 16 channel 16 bit ADC input voltage range OV to 10V gain 1 2 5 10 TIP501 21 Optically isolated 16 channel 16 bit ADC input voltage range OV to 10V gain 1 2 4 8 TIP501 User Manual Issue 1 1 7 TEWSS TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0 029 that means hexadecimal value 029 For signals on hardware products an Active Low is represented
10. TREG is read as 0 It is also possible to select a next channel and or gain by writing to the ADC CONTREG register immediately after the actual conversion has been started by writing to the ADC CONVERT register In this mode the settling time for the next channel and the conversion time of the actual channel proceed simultaneously As long as the ADC Busy flag in the ADC STATREG register is read as 1 the actual conversion is still in progress Reading the ADC Busy flag as 0 indicates that the conversion result is available in the ADC DATAREG register If interrupts are enabled two interrupts will be generated the first interrupt when the settling time is done after writing to the ADC CONTREG register the second interrupt when the data conversion is done after writing to the ADC CONVERT register 6 2 1 State Diagram Normal Mode ADC busy 1 Settle busy 1 A Write access to CONTREG B Settling time expired C Write access to CONVERT D ADC ready conversion result in DATAREG no cycle next Figure 6 1 State Diagram Normal Mode TIP501 User Manual Issue 1 1 7 Page 17 of 27 TEWSS TECHNOLOGIES 6 2 2 Normal Mode without Data Pipeline If Normal Mode without Data Pipeline is selected the result of the actual conversion is shifted into the ADC DATAREG register In this mode it is possible that the settling time and conversion time proceed simultaneously The total acquisition and conver
11. Undefined bits R undefined ADC ADC Busy R 0 Busy Indicates if an actual data conversion is still in progress In Automatic Settling Time mode the ADC Busy bit is 1 during the settling time and the conversion time The ADC Busy bit must be read as 0 before the data is read from the ADC DATAREG register 0 Settle Settling Time Busy R 0 Busy Indicates if the settling time count is still in progress In Normal Settling Time mode after writing to the ADC CONTREG register the Settle Busy bit must be read as 0 before a conversion is started by writing to the ADC CONVERT register Table 5 4 STATREG ADC Status Register Address 0x05 TIP501 User Manual Issue 1 1 7 Page 14 of 27 TEWSS TECHNOLOGIES 5 1 4 ADC Convert Start Register Address 0x07 If the TIP501 is configured for Normal Settling Time mode writing any value into the ADC Convert Register CONVERT starts data conversion immediately In Normal Settling Time mode it is in the responsibility of the user to observe the Settle Busy flag and the ADC Busy flag in the ADC STATREG register Writes to the ADC CONVERT register during ADC Busy 1 are ignored 5 1 5 Interrupt Vector Register Address 0x09 There are two possible interrupt sources A Settling Time Done event and an ADC Data Ready event The Interrupt Vector Register is shared between both interrupt sources but the Settling Time Ready event and the
12. ated when the settling time is done IP INTREQO is generated when data conversion is done In Automatic Settling Time mode only INTREQO is generated TIP501 User Manual Issue 1 1 7 Page 12 of 27 TEWSS TECHNOLOGIES Bit Symbol Description Access Reset Value 8 PIPL Pipeline Mode Control R W 0 0 No Pipeline Mode 1 Pipeline Mode In pipeline mode the result from the conversion N 1 is shifted into the DATAREG during the conversion 7 ASTCE Automatic Settling Time Mode Control R W 0 0 Normal Settling Time Mode In this mode first the input channel and gain is selected by writing the ADC CONTREG register The data conversion is started by writing to the ADC CONVERT register The Settle Busy bit in the ADC STATREG register must be 0 for every write to the ADC CONVERT register The ADC Busy bit in the ADC STATREG register must be 0 for reading the ADC DATAREG register 1 Automatic Settling Time Mode In this mode the data conversion is started by the write to the ADC CONTREG register where this bit is set The data conversion is delayed by hardware control until the settling time has expired The ADC Busy bit in the ADC STATREG register must be 0 for reading the ADC DATAREG register The settling time for all TIP501 modules is appr 10us for all gains 6 GAIN1 Gain Selection input voltage amplifier R W 0 TIP501 10 20 TIP501 11 21 00 G1 00 G1
13. by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 2010 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 27 TEWSS TECHNOLOGIES Issue Description Date 1 0 First Issue March 1997 1 1 Formula Correction and General Revision November 2002 1 2 Correction Technical Specification and Flowcharts November 2002 1 3 Added Programming Note and Installation Note October 2004 1 4 Correction ADC Data Coding description November 2004 1 5 New address TEWS LLC Special I O pin connection clarified new July 2007 MTBF number 1 1 6 New Notation for User Manual and Engineering Documentation January 2009 1 1 7 Added Analog Input Impedance January 2010 TIP501 User Manual Issue 1 1 7 Page 3 of 27 TEWSS TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION Luma 6 2 TECHNICAL 7 3 FUNCTIONAL DESCRIPTION sunde 9 3 1 Analog 9 3 2 Corretto sso n 10 3 2 1 ADC Correction Formula raannvnnonvvnnnvrnnnnvnnannvnnnnrnnnnrnnnnnnnnnenrennnrrrannrnnannnnnenres
14. computing above formula TIP501 User Manual Issue 1 1 7 Page 10 of 27 4 Address Function Contents 0 01 ASCII T 0x49 0x03 ASCII P 0x50 0x05 ASCII A 0x41 0x07 ASCII C 0x43 0x09 Manufacturer ID 0xB3 0x0B Model Number 0x22 0x0D Revision 0x10 Ox0F Reserved 0x00 Ox11 Driver ID low byte 0x00 0x13 Driver ID high byte 0x00 0x15 Number of bytes used 0x1D 0x17 CRC Variable 0x19 Board Option 501 10 0 TIP501 11 0x0B TIP501 20 0x14 TIP501 21 0x15 0x1B Offset Error for gain 1 low byte Board dependent 0x1D Offset Error for gain 1 high byte Board dependent 0x1F Offset Error for gain 2 low byte Board dependent 0x21 Offset Error for gain 2 high byte Board dependent 0x23 Offset Error for gain 4 5 low byte Board dependent 0x25 Offset Error for gain 4 5 high byte Board dependent 0x27 Offset Error for gain 8 10 low byte Board dependent 0x29 Offset Error for gain 8 10 high byte Board dependent 0x2B Gain Error for gain 1 low byte Board dependent 0x2D Gain Error for gain 1 high byte Board dependent 0x2F Gain Error for gain 2 low byte Board dependent 0x31 Gain Error for gain 2 high byte Board dependent 0x33 Gain Error for gain 4 5 low byte Board dependent 0x35 Gain Error for gain 4 5 high byte Board dependent 0x37 Gain Error for gai
15. ith Data 2 22 7 PIN ASSIGNMENT I O CONNECTOR 23 7 1 Analog Input 22 23 7 2 Power Input ConnectionS rsssrrnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnr 24 7 3 IP Connector Orientation rrssvrnnnvnnnnnvnnnnnvnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 25 8 PROGRAMMING NOTES LL 26 9 INSTALLATION NOTES Linser 27 TIP501 User Manual Issue 1 1 7 Page 4 of 27 List of Figures FIGURE 1 2 BLOCK FIGURE 6 2 STATE DIAGRAM NORMAL MODE FIGURE 6 3 FLOWCHART NORMAL MODE WITHOUT DATA PIPELINE FIGURE 6 4 FLOWCHART NORMAL MODE WITH DATA PIPELINE FIGURE 6 5 STATE DIAGRAM AUTOMATIC FIGURE 6 6 FLOWCHART AUTOMATIC MODE WITHOUT DATA PIPELINE FIGURE 6 7 FLOWCHART AUTOMATIC MODE WITH DATA PIPELINE FIGURE 6 2 IP CONNECTOR List of Tables TABLE 1 1 BOARD OPTION TABLE 2 1 TECHNICAL TABLE 3 1 BOARD OPTION TABLE 4 1 ID PROM
16. log Input The TIP501 provides 16 single ended or 8 differential multiplexed analog inputs The desired input channel and mode single ended or differential is selected by programming the input multiplexer programmable gain amplifier allows direct connection for wide range of sensors and instrumentation Board Option Gain Factors Input Voltage Range TIP501 10 1 2 5 10 10V for gain 1 TIP501 11 1 2 4 8 10V for gain 1 TIP501 20 1 2 5 10 OV to 10V for gain 1 TIP501 21 1 2 4 8 OV to 10V for gain 1 Table 3 1 Board Option Overview The ADC device is 16 bit ADS7809 with a maximum sample and conversion time of 10us Since the TIP501 is a multiplexed analog input system a settling time is required to pass after changing the input channel and or gain The TIP501 provides a status bit for polling the settling time status An automatic settling time control mode is also provided In this mode data conversion is automatically started after the settling time has expired The absolute accuracy of the module can be increased by performing a data correction in software using the factory calibration factors stored in the on board ID PROM TIP501 User Manual Issue 1 1 7 Page 9 of 27 TEWSS TECHNOLOGIES 3 2 Data Correction There are two errors which affect the DC accuracy of the ADG The first is the zero error offset This is the data value when converting with the input connected with its
17. logic power supply by opto couplers and a DC DC converter Interrupts are supported indicating available sampling data when conversion is done Each TIP501 is factory calibrated The calibration information is stored the Identification PROM unique to each IP 16 bit A D PGA Converter gain1 2 5 10 with S H or gain 1 2 4 8 Optocoupler 16 Channel Input Multiplexer Industry Pack I O Interface 8 2 8 5 E DC DC Converter Figure 1 1 Block Diagram TIP501 User Manual Issue 1 1 7 Page 6 of 27 TEWSS TECHNOLOGIES 2 Technical Specification IP Interface Interface Single Size IndustryPack Logic Interface compliant to ANSI VITA 4 1995 ID ROM Data Format I Space Used with 0 wait states Memory Space not used Interrupts INTREQO and INTREQ1 used DMA Not supported Clock Rate 8 MHz Module Type Type I On Board Devices ADC ADS7809 16 Bit ANALOG TO DIGITAL CONVERTER I O Interface Interface Connector 50 conductor flat cable Analog Inputs 16 single ended channels or 8 differential channels Input Impedance Typically 1012 4nA leakage current Input Isolation All channels are galvanically isolated from the IP interface DC DC converter on board Input Gain Amplifier TIP501 10 20 Programmable for gain 1 2 5 10 TIP501 11 21 Programmable for gain 1 2 4 8 Input Voltage Range TIP501 10
18. n 8 10 low byte Board dependent 0x39 Gain Error for gain 8 10 high byte Board dependent 0x3B 0x3F Not used TIP501 User Manual Issue 1 1 7 Table 4 1 ID PROM Content TIP501 TEWSS TECHNOLOGIES Page 11 of 27 TEWSS TECHNOLOGIES 5 IP Addressing The TIP501 is controlled by a set of registers which are directly accessible in the I O address space of the IP module Address Symbol Description Size Bit Access 0x00 CONTREG ADC Control Register 16 R W 0x02 DATAREG _ ADC Data Register 16 R W 0x05 STATREG ADC Status Register 8 R 0x07 CONVERT ADC Convert Start Register 8 W 0x09 INTVEC Interrupt Vector Register 8 R W 0x0B IDWRENA ID PROM write enable 8 W Table 5 1 Register Set IDWRENA is for factory use only Do not write to this register 5 1 ADC Register Set The ADC of the TIP501 is controlled by set of 4 registers All registers are cleared by IP RESETt ADC Control Register ADC Data Register Status Register ADC Convert Start Register 5 1 1 ADC Control Register Address 0x00 The ADC Control Register CONTREG is used to select the input channel gain and mode for the next data conversion Bit Symbol Description Access Reset Value 15 10 Unused bits Read access undefined Write access don t care R W 0 9 INTENA Interrupt Enable R W 0 0 Interrupts disabled 1 Interrupts enabled IP INTREQ1 is gener
19. n 25 O Ba BA z g 8 8 aaj Component Side View 5 9 He ma CE WY O Pin 26 Pin 1 Pin 26 Pin 1 5 Solder Side View 9 50 25 Figure 7 1 IP Connector Orientation TIP501 User Manual Issue 1 1 7 Page 25 of 27 TEWSS TECHNOLOGIES 8 Programming Notes After power up the on board ADC device is random state and requires two dummy conversions before operating correctly This is based on the chip design of the ADC device Software should ignore the data of the first two ADC conversions after power up The software drivers from TEWS TECHNOLOGIES already include these two dummy conversions TIP501 User Manual Issue 1 1 7 Page 26 of 27 TEWSS 9 Installation Notes Make sure that all unused analog input pins are tied to the AGND signal level or any other valid signal level within the analog input voltage range This is required even if the unused channels are turned off by software If unused analog inputs are left floating they could badly degrade the performance of the active channels TIP501 User Manual Issue 1 1 7 Page 27 of 27
20. nnrnsennnnnennsene 10 4 DRM CONTENT vr 11 IP ADDRESSING iscsi 12 5 1 ADG Register 12 5 1 1 ADC Control Register Address 0 00 12 5 1 2 ADC Data Register Address 0 02 20440 440 0 000 14 5 1 3 ADC Status Register Address 0X05 14 5 1 4 ADC Convert Start Register Address 0 07 15 5 1 5 Interrupt Vector Register Address 0 09 15 OPERATING MODES 16 6 1 Mode 16 6 2 Normal 17 6 2 1 State Diagram Normal 9 9 17 6 2 2 Normal Mode without Data 2 18 6 2 3 Normal Mode with Data Pipeline 19 6 3 Automatic Mod rn 20 6 3 1 State Diagram Automatic 04 444424 000 0 20 6 3 2 Automatic Mode without Data Pipeline 21 6 3 3 Automatic Mode w
21. sion time in this mode is 22us Stat 2 I Write access to CONTREG Select gain amp channel Read bit 0 of STATREG to check for end of settling time N Write to CONVERT starts conversion Start and shifts result of convesion conversion into the DATAREG Select a new channel and a new gain during conversion proceeds by write 9 access to CONTREG ADC y Read bit 1 of the STATREG to check Busy for end of conversion N Read data of Read result of the conversion conversion from DATAREG Figure 6 2 Flowchart Normal Mode without Data Pipeline For conversions without channel and gain change it is not necessary to observe the Settle Busy flag in the ADC STATREG register TIP501 User Manual Issue 1 1 7 Page 18 of 27 TEWSS TECHNOLOGIES 6 2 3 Normal Mode with Data Pipeline If Normal Mode with Data Pipeline is selected during conversion the result of conversion N 1 is shifted into the ADC DATAREG register In this mode it is possible that the settling time and conversion time proceed simultaneously The total acquisition and conversion time in this mode is 12us with no change of channel gain and 14 5us with change of channel gain Select gain amp Write access to CONTREG channel Pipeline Active Y Read bit 0 of STATREG to check for end of settling time
22. sy clears to 0 the conversion result is accessible in the ADC DATAREG register and an interrupt will be generated if interrupts are enabled ADC busy 0 write access to CONTREG TIP501 User Manual Issue 1 1 7 Page 20 of 27 TEWSS TECHNOLOGIES 6 3 2 Automatic Mode without Data Pipeline If Automatic Mode without Data Pipeline is selected the result of the actual conversion is shifted into the ADC Data Register DATAREG The acquisition and conversion time in this mode is 3215 a Start Select new gain amp channel Auto active ADC Y Busy Read data of conversion n Write to CONTREG starts automatically conversion after settling time has expired and shifts the result into DATAREG Bit 1 of STATREG indicates ADC busy during the whole cycle Read data of the actual conversion from DATAREG Figure 6 5 Flowchart Automatic Mode without Data Pipeline TIP501 User Manual Issue 1 1 7 Page 21 of 27 TEWSS TECHNOLOGIES 6 3 3 Automatic Mode with Data Pipeline If Automatic Mode with Data Pipeline is selected during conversion the result of conversion N 1 is shifted into the ADC Data Register DATAREG The acquisition and conversion time in this mode is 208 Auto amp Pipeline active Read data of conversion N 1 Write to CONTREG starts automatically conversion N after
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