DKAN0011A - Digi-Key
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1. header h O El Pin_Assignments csv 1c SDRAM c Fiter Types Select al Deselect l webean Figure 36 Import Files Digi Key Corporation Page 32 of 35 Setting Up a Nios H System with SDRAM on the DE2 System Library Configuration Before the program can be run it is necessary to adjust the system library properties Right click on the Tutorial_SDRAM folder and select System Library Properties A new window opens Select sdram_0 in the Program memory text drop down menu Also select sdram_0 for the Read only data memory rodata drop down menu Do not change any of the other default settings Click OK Refer to Figure 37 Properties for Tutorial_SDRAM_syslib SEE type Filter text System Library Info Target Hardware Builders ClC Build SOPC Builder System cea ep Cic File Types CiC Include Paths ari System Library Contents Linker Script Cic Indexer mol Custom linker script CiC Make Project RTOS none single threaded w O F CiC Project Paths Ty nones o z Project References _ Refactoring History stdout jtag_uart_O w Use auto generated linker script System Library stderr jtag_uart_O he Program memory t kext Iscram_0 stdin itag_uart_o a Read only data memory rodata sdram_O system clock timer Readiwrite data memory radatal onchip_memory2_0 w Timestamp timer none 2a Heap memory onchip_memory2_0 Ww Max File descriptors a2 St2. Include Mri Family Cyclone Il cpuid 0 Only include the MMU when using an operating system that explicitly supports an MMU Fast TLE Miss Exception Vector Memory Offset pn Include MPU Figure 17 SDRAM Configuration Digi Key Corporation Page 16 of 35 Setting Up a Nios If System with SDRAM on the DE2 Assign Base Addresses To avoid conflicts between system components set their base addresses To auto assign the base addresses select System gt Auto Assign Base Addresses Refer to Figure 18 System Contents HI Component Lib i Mios I Processor H Bridges and Adapters ntertace Protocols H Legacy Components Memories and Memory Controller DMA G Flash E On Chip SDRAM os DOR SDRAM Controll DDR SDRAM High Pe e DOR SDRAM Contro DDR2 SDRAM High F DDR SDRAM High F SDRAM Controller Auto Assign B Auto Sesign Rds Insert Avalon 5T Adapters Device Family Cyclone ll wt Mios Il Help ase Addresses C f Cor Module Mame z1 cpu 0 instruction master data master flag_debug module E jtag_uart_0 avalon _jtag slave El led Figure 18 Auto Assign Base Addresses Change the interrupt request IRQ priorities for the JTAG UART Click the IRQ value for the Clock Settings Mame Description Avalon Memory Mapped Slave Mios I Processor Avalon Memory tapped baster Avalon Memory tapped baster Avalon Memory Mapped S
3. Click Finish and the Nios II processor is added to the system See Figure 6 Nios Il Processor cpu_0 gt lt Nios II Processor ill Documentation Parameter Settings s Core Mios I gt Caches and Memory Interfaces gt Advanced Features MMU and MPL Settings N JTAG Debug Module gt Custom Instructions gt Core Nios lIl Select a Hios Il core Nios Il e lios ll s Nios Il f P RISC RISC RISC Nios Il 32 bit 32 bit 32 bit Selector Guide Instruction Cache Instruction Cache Branch Prediction Branch Prediction Hardware Multiply Hardware Multiply system 50 0 MHz Hardware Divide Hardware Divide Barrel Shifter Data Cache Dynamic Branch Prediction Upto 51 OMIPS Family Cyclone Il chuid 0 Performance at 50 0 MHz Ug ta 5 DMIFS Logic Usage 600 700 LEs 1200 1400 LEs 1400 1600 LEs Memory Usage Two Maks Cor equiv Twa Maks cache Three biks cache angen Men Include Mhil Only include the MMU when using an operating system that explicitly supports an MML Fast TLE Miss Exception Vector Memory Offset Include MPU Figure 6 Nios II Processor Setup Digi Key Corporation Page 6 of 35 Setting Up a Nios H System with SDRAM on the DE2 Add a JTAG UART In order to communicate to the Nios II processor through the USB Blaster add the JTAG UART to the system In the upper left corner of the SOPC window under Component Library expand Interface Protocols expand Serial
4. Output ports only Output Port Reset Value Output Register F Enable individual bit settingiclearing Figure 13 PIO Red LED Setup Digi Key Corporation Page 13 of 35 Setting Up a Nios II System with SDRAM on the DE2 Add the seven segment displays to the system Expand Peripherals expand Microcontroller Peripherals select PIO Parallel I O and click Add Set the Width to 16 and click Finish Repeat the previous step three more times to set up all eight of the seven segment displays Refer to Figure 14 To ensure proper functionality rename the pio_0 3 that were generated Select pio_0 3 right click on them select Rename and rename them to seven_seg_01 seven_seg_23 seven_seg_45 and seven_seg_ 67 PIO Parallel 1 0 pio_1 Eg TE PIO Parallel 1 0 Parameter Settings Basic Settings Input Options Simulation Width Width 1 32 bits Direction Bidirectional tristate ports Input ports only Both input and output ports Output ports only Output Port Reset value Output Register F Enable individual bit settingiclearing Figure 14 PIO Seven Segment Display Setup Add SDRAM To add the SDRAM expand Memories and Memory Controllers expand SDRAM select SDRAM Controller and click Add Set Presets to Custom change the Bits to 16 and click Finish Do not change any of the other values Refer to Figure 15 Digi Key Corporation Page 14 of 35 Setting Up a Nios I System with SDRAM on
5. select PIO Parallel I O and click Add When the window opens set the Width to 18 set the Direction to input ports only and click Finish Refer to Figure 9 Rename the pio_0 that was generated to ensure proper functionality Select pio_0 right click on it select Rename rename it to switch and press Enter PIO Parallel 1 0 switch Eg s PIO Parallel I O S Farameter Settings ENRE TEN ses fe Basic Settings Input Options Simulation i Width wean sobs fie Direction E Bidirectional tristate ports Input ports only Both input and output ports Output ports only Output Port Reset Value Deen Output Register Enable individual bit settingiclearing Ny Warning PIO inputs are not hardwired in test bench Undefined values will be read from Pl input Figure 9 PIO Switch Setup Digi Key Corporation Page 9 of 35 Setting Up a Nios H System with SDRAM on the DE2 Add the pushbuttons next Similar to the switches expand Peripherals expand Microcontroller Peripherals select PIO Parallel I O and click Add When the window opens set the Width to 4 and set the Direction to input ports only Go to the Input Options tab check the synchronously capture box and select Falling edge Also underneath in the Interrupt section check Generate IRQ select Edge and then click Finish Refer to Figures 10 and 11 Rename the pio_0 that was generated to ensure proper functionality Select pio_0 right c
6. 27 MegaWizard Plug In Manager Page 7 Digi Key Corporation Page 24 of 35 Setting Up a Nios H System with SDRAM on the DE2 Click Next on pages 8 and 9 and click Finish on page 10 The Symbol window opens again Click OK and place the newly created pll_block to the left of the NiosII_Processor block Refer to Figure 28 i Quartus II C Tutorial_Files SDRAM SDRAM SDRAM SDRAM bdf File Edit Yiew Project Processing Tools Window inclkO frequency 50 000 MHz Operation Mode Normal Cik Ratio Ph dg DC cs UE ce LCD_E_from_the_Icd co 2 1 0 00 50 00 LCD_RS_from_the_led fet 141 54 00 50 00 LCD_RW_from_the_led LCD_data_to_and_from_the_Icq 0 Cyclone II 4411 o gt 7a zs_addr_from_the_sdram_0O 11 0 zs_ba_from_the_sdram_Of1 0 zs_cas_n_from_the_sdram_0O zs_cke_from_the_sdram_O zs_cs_n_from_the_sdram_0O zs_dq_to_and_from_the_sdram_0 15 0 zs_dqm_from_the_sdram_0O 1 0 Zs_ras_n_from_the_sdram_O zs_we_n_from_the_sdram_0O in_port_to_the_switch 1 0 For Help press F1 Figure 28 PLL Block Placement Digi Key Corporation Page 25 of 35 Setting Up a Nios II System with SDRAM on the DE2 Right click somewhere in the block diagram and click Insert gt Symbol Expand the c altera libraries folder expand primitives expand pin select input and click OK Click to place this pin to the left of the inclk0 terminal on the pll_block Double click the newly created input pi
7. CLOCK_50 0x00811090 CLOCK_50 0x00811000 CLOCK_50 0x00811010 CLOCK_50 0x00811020 CLOCK_50 0x00811030 CLOCK_50 000811040 CLOCK_50 0x00811050 CLOCK_50 0x00811060 CLOCK 50 02003811070 Figure 19 JTAG UART IRQ Setup Generate System Finally generate the system Click the Generate button on the bottom of the screen If prompted to save the changes do so When the system generation is complete a message entitled Info System Fitter Default OxO0081107f Tags IRQ generation was successful appears in the message box Upon successful system generation close the SOPC Builder window Digi Key Corporation Page 17 of 35 Setting Up a Nios H System with SDRAM on the DE2 Block Diagram Design in Quartus Il Add Processor Now that the SOPC system is built implement it in the block diagram file Open the Quartus II window Right click on the blank block diagram within the SDRAM bdf tab Click Insert gt Symbol A Symbol window opens In the Libraries pane expand Project select NiosII_Processor and click OK Refer to Figure 20 LODE from_the_Icd LOD_RS_fram_the_Icd LOD RV from_the_Icd Libraries E EE Project m Mioell Processor c altera 90ep1 Aquartuslibraries 3 LOD data_to_and_from_the_led 0 zs _addr_from_the_sdram_0O 11 0 zs_bha_from_the_sdram_O 1 0 zs cas _n_from_the_sdram_O ze _cke_from_the_sdram_O re cs n_from_the_sdram_O Fe dq to_and_fram_the_sdram_O 15 0 ze_d
8. Key s standard Terms amp Conditions which can be found at www digi key com by clicking on the Terms amp Conditions link at the bottom of the web page No license whether express implied arising by estoppel or otherwise is granted under any intellectual property or other rights of Digi Key or others Trademarks DIGI KEY is a registered trademark of Digi Key Corporation All other trademarks service marks and product names contained herein are the sole property of their respective owner and their use is for informational purposes only and does not imply any endorsement recommendation sponsorship or approval by the trademark owner of the contents Copyright Use of this document is limited to customer s internal business use for the evaluation and purchase of products No permission is granted to the user to copy print store distribute transmit display in public or modify the content of this document in any way for any other purpose Copyright 2009 Digi Key Corporation All rights reserved Digi Key Corporation Page 35 of 35
9. and hold in order to draw a line connecting reset_n to the closest vec Let go of the mouse as soon as a small box shape appears on vec Click and hold vec in order to move it When vec is moved the line that was just drawn follows vee If the line moves with vec there is a proper connection If not click and drag the mouse to connect the line between reset_n and vee Connect both of the output pins to the other vee following these same steps Double click one of the output pins to open the Pin Properties window In the Pin name s section rename the pin to LCD_ON and click OK Rename the other pin LCD_BLON Refer to Figure 21 Pin Properties General Format To create multiple pins enter a name in AHOL bus notation for example hamels 0l or enter a comma separated list of names Fin namefs LCD_ON Figure 21 Rename Output Pins Add a PLL Right click somewhere in the block diagram again and click Insert gt Symbol Click on the MegaWizard Plug In Manager button In the new window select Create a new custom megafunction variation and click Next Refer to Figure 22 Digi Key Corporation Page 19 of 35 Setting Up a Nios H System with SDRAM on the DE2 MepaWizard Plug In Manager page 1 The Megawizard Plug In Manager helps you create or modify design files that contain custom varnations of megatunctions Which action do you want to perto 0 Edit an existing custom megafunction variation C C
10. in SOPC Builder The next step is to build a Nios II processor system Select Tools gt SOPC Builder In the pop up window set the System Name to NiosII_Processor and the Target HDL to either Verilog or VHDL Select OK It is not necessary to know VHDL or Verilog to continue so select either one Refer to Figure 3 Create New System System Mame Niosll_Frocessor Target HDL Verilog VHDL Figure 3 Create New Nios II System Error and warning messages appear and disappear sporadically in the information box on the bottom of the screen while performing the following steps Ignore these errors they disappear upon successful completion of the Nios II system Clock Settings In the Clock Settings pane double click clk_0 and rename it CLOCK_50 Press Enter The SDRAM requires another clock to be added to the system so click the Add button to the right of the Clock Settings pane Once a new clock appears double click on it and rename it CLOCK_100 To the right of this new clock under MHz double click on the 50 and change it to 100 Refer to Figure 4 Clock Settings Name Source MHZ Add CLOCK_50 External 50 0 CLOCK_100 External 100 0 Figure 4 External System Clocks Add On Chip Memory On the upper left side of the SOPC Builder window under Component Library expand the Memories and Memory Controllers column then expand On Chip and select On Chip Memory RAM or ROM Click the Add button and the Meg
11. 6F1F2 FFFFFFFF O O O O O O oe Auto Detect Kose B Change Fie eee po Pom For Help press F1 Figure 32 Programmer Window The window shown in Figure 33 opens This window confirms that the FPGA on the DE2 board successfully configured OpenCore Plus Status Click Cancel to stop using UpenCore Plus IP Time remaining unlimited Figure 33 Successful Connection Window Digi Key Corporation Page 29 of 35 Setting Up a Nios H System with SDRAM on the DE2 Software Design in the Nios II IDE Creating a New C C Application Next implement a software application for the Nios II system Open the Nios II IDE Under the File menu select New gt Nios II C C Application to open the New Project window In the Name section type Tutorial SDRAM In the SOPC Builder System PTF File browse to the location where the NiosII_Processor was saved when created with SOPC builder and open it Under Select Project Template select Blank Project Click Finish Refer to Figure 34 New Project Nios II C C Application Click Finish to create application with a default system library as C Tutorial _FilesiSDR AM software Tutorial SDRAM Mame Tutorial_SDRAM Specify Location Select Target Hardware SCPC Builder System PTF File C Tutorial_ Files SDRAMIMiosII_ Processor ptf CPU cou 0 Select Project Template Blank Project Description Board Diagnostics Coun Binary Hello Freestanding Details
12. A A Warning switch PIO inputs are not hardwired in test bench Undefined values will be read from PIO inputs during simulation Ay Warning pb PIO inputs are not hardwired in test bench Undefined values will be read from PIO inputs during simulation Figure 16 SDRAM CLOCK_50 To run the application from SDRAM instead of On chip memory specify it in the cpu_0 MegaWizard Select cpu_0 in the Module Name list right click on it and select edit Set the Reset Vector and the Expansion Vector to sdram_0 as shown in Figure 17 Select Finish Nios Il Processor cpu_0O Ed Nios II Processor Parameter Settings ka C ka a Na m w _ ia Core Mios I Caches and Memory Interfaces Advanced Features gt MMU and MPU Settings gt JTAG Debug Module gt Custom Instructions gt Core Nios Il Select a Nios Il core ONios Il e lor s II s ONios IIA RISC RISC RISC Nios Il 32 bit 32 bit 32 bit Selector Guide Instruction Cache Instruction Cache Branch Prediction Branch Prediction Hardware Multiply Hardware Multiply foystem 100 0 MHz Hardware Divide Hardware Divide Barrel Shifter Data Cache Dynamic Branch Prediction Performance at 100 0 MHz Ug to 9 DMIFS Up 5 Up to 101 DMIPS Logic Usage 00 700 LEs 1400 1800 LEs Memory Usage Tyo Maks Cor equiv Pwo MWAKE cache Three M4Ks cache RDA P EREN Reset Vector Memory scram OFFS oxo fo 2000000 Exception Vector Memory Reet ae Offset 002000020
13. Cancel Back Next gt Figure 23 MegaWizard Plug In Manager Page 2 Digi Key Corporation Page 20 of 35 Setting Up a Nios H System with SDRAM on the DE2 On the ALTPLL page leave the speed grade set to 6 Change the frequency of the inclockO input to 50 MHz Click Next Refer to Figure 24 MepgaWizard Plug In Manager page 3 of 10 E a x ish ALTPLL Parameter Settings Currently selected device Family W Match project default naki frequency 50 000 Mike 4ble bo implement the requested PLL Operation Wiode Monmal Cik Ratio Ph dof OC C 3 ped 17 ooo 50 00 Which device speed grade will you be using O Use military temperature range devices only What is the Frequency of the inclocko input 20 00 O Set up PLL in LDS mode ata rate 300 000 Mbps PLL type Which PLL type will you be using Fast PLL 2 Enhanced PLL Select the PLL type automatically Operation mode How will the PLL outputs be generated os Use the Feedback path inside the PLL In Normal Mode 2 In Source Synchronous Compensation Made 2 In Zero Delay Buffer Made CI Connect the Fornimic port bidirectional Co With no compensation C Create an Fbin input for an external Feedback External Feedback Made Which output clock will be compensated For c a Figure 24 MegaWizard Plug In Manager Page 3 Digi Key Corporation Page 21 of 35 Setting Up a Nios II System with SDRAM on the DE2 On p
14. External Output Clock oll block Able to implement the requested PLL inclk frequency 50 000 kHz M3 Use this clock Operation blode Normal Clock Tap Settings Requested settings Actual settings Cik Ratio Ph cigah OC c olan om ow X Enter output clock parameters Clock multiplication Factor Clock division Factor Clock phase shift Clock duty cycle 3 More Details gt gt Per Clock Feasibility Indicators GES Sidhe jee Figure 26 MegaWizard Plug In Manager Page 6 Digi Key Corporation Page 23 of 35 Setting Up a Nios II System with SDRAM on the DE2 On page 7 check Use this clock On the Clock phase shift option change the Requested settings to 3 00ns The deg might need to be changed to ns before selecting 3 00 Verify that the value is negative Click Next Refer to Figure 27 MepgaWizard Plug In Manager page 7 of 10 gee _ ALTPLL Parameter 2 Output S EDA ai summary Settings Clocks clk cO clk c2 cl Core External Qutput Clock pll block Able to implement the requested PLL inclkO frequency 50 000 kHz M Use this clack Operation Mode Normal Clock Tap Settings Requested settings Actual settings Enter output clack frequency 100 0000000 50 000000 oe Enter output clack parameters Clock multiplication Factor Clock division Factor Clock phase shift Clock duty cycle 3 More Details gt gt Per Clock Feasibility Indicators EES 2c Ee Figure
15. Hello Micro o5 I1 Hello world Blank Project creates an empty project to which vou can add Hello World Small your code Memory Test Simple art Saiar This software example runs on the Following Mios I hardware Web Server designs Standard Full Featured Creates a blank project Emish Figure 34 New C C Application Window Digi Key Corporation Page 30 of 35 Setting Up a Nios I System with SDRAM on the DE2 Importing Source and Header Files Select the Tutorial_ SDRAM folder in the Nios II C C Projects pane In the File menu select Import In the Import window select File System as shown in Figure 35 and click Next Browse to the folder containing the example files accompanying this tutorial Check SDRAM c and header h as shown in Figure 36 and click Finish SDRAM c and header h should now appear in the Tutorial SDRAM folder in the Nios II IDE SS _OCS Select Import resources From the local file system into an existing project Select an import source type filter text E General IEJ Archive File sis B Breakpoints i Existing Projects into Workspace E File System LS Preferences H E Altera Mios II H E C C H E cs H E Team F Back Finish Cancel Figure 35 Import File System Digi Key Corporation Page 31 of 35 Setting Up a Nios II System with SDRAM on the DE2 Import File system Import resources From the local File system CSDRAM_ Tutorial x
16. P gt DKANOOT1A OigKoy P Setting Up a Nios Il System with CORPORATION SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies Inc s DE2 Altera Development and Education Board The system includes an interface to the board s 8MB SDRAM chip and runs the application program from SDRAM It also sets up and implements the LCD seven segment displays red and green LEDs switches and pushbuttons Background Nios II is a 32 bit RISC CPU designed for implementation as a soft core in Altera FPGAs Altera s System on a Programmable Chip SOPC Builder allows users to design Nios II systems easily by selecting Nios II processors setting up the associated memory and adding any desired standard and or custom peripherals Once generated the system is incorporated into an FPGA design with Altera s Quartus II software and instantiated on the FPGA Altera provides the Nios II Integrated Development Environment IDE for application software development This tutorial includes instructions for running an example C application from SDRAM Application DE2 Setup This tutorial assumes that the user is familiar with the DE2 board and already has the USB Blaster device installed Refer to the Getting Started with Altera s DE2 Board tutorial for more information on installing the USB Blaster driver Also these programs are case sensitive If a compone
17. aWizard appears Set Block Type to M4K set Total Memory Size to 20 and select Kbytes Do not change any other default settings Click Finish Refer to Figure 5 Errors may occur after adding the On chip memory Ignore these errors because they disappear as more components are added to the system Digi Key Corporation Page 4 of 35 Setting Up a Nios II System with SDRAM on the DE2 On Chip Memory RAM or ROM onchip_memory _0 Eg tz On Chip Memory mw RAM or ROM Farameter Settings hemor type RAM Cyvritable O ROM Read only Dual port access Read During Write Mode DONT CARE Block type het hi Initialize memory content Memory wil be initialized trom onchip_memory z 0 hex Size Data wwictth a5 we Total memory size F Minimize memory block usage may impact trax Memory initialization Enable non defautt initialization tile User created initialization file onchip memorya 0 hex F Enable In System Memory Content Editor feature Figure 5 On Chip Memory Setup Digi Key Corporation Page 5 of 35 Setting Up a Nios H System with SDRAM on the DE2 Add a Nios Il Processor Now add the Nios II processor to the system In the upper left corner of the SOPC window under Component Library select Nios II Processor and click the Add button In the middle of the MegaWizard window select Nios II s as a Nios II core Set Hardware Multiply to None Do not change any other of the default values
18. ack memar onchip memory2 Oo 7 Program never exits Clean exit Flush buffers Flees eeparare E Support Reduced device drivers Lightweight device driver API Small library Link with profiling library ModelSin only no hardware support TPS e a SSS C Unimplemented instruction handler C Run time stack checking Software Components Exception stack memory Restore Defaults Figure 37 System Library Properties Digi Key Corporation Page 33 of 35 Setting Up a Nios II System with SDRAM on the DE2 Running the Software Finally run the program Right click on the Tutorial_SDRAM folder and select Run As gt Nios H Hardware If prompted to save changes click Yes It may take some time for the program to build but upon successful completion a message similar to the following displays in the Console tab nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB 0 device 1 instance 0 nios2 terminal Use the IDE stop button or Ctrl C to terminate The DE2 board should be running the program If the sample code was used the LCD should display You Are AWESOME LCD Works The seven segment displays count in hexadecimal and the green LEDs count in binary If a switch is switched to the up position the red LED above the switch turns on If the pushbutton KEY0O is pressed all of the devices count down instead of up If KEY1 is pressed th
19. age 4 deselect Create an areset input to asynchronously reset the PLL and also deselect Create locked output Click Next Refer to Figure 25 MegaWizard Plug In Manager page 4 of 10 Sees Se ALTPLL about Bocneretion Parameter Settings General Modes ts a 2 Clock switchover 4ble to implement the requested PLL Optional inputs inclkO frequency 50 000 hiHz au i Dr E NauaA Create an pllena input to selectively enable the PLL Create an areset input to asynchronously reset the PLL ik Ratio Ph Gay OC Cay T on Y Feo J at o oo s0 00 L Create an pfdena input to selectively enable the phase freg detector Lock output Create locked output Ll Enable selfF reset on loss of lock Advanced PLL parameters Using these parameters is recommended for advanced users only Create output file s using the Advanced PLL parameters Configurations with outout clock s that use cascade counters are not supported Figure 25 MegaWizard Plug In Manager Page 4 Digi Key Corporation Page 22 of 35 Setting Up a Nios H System with SDRAM on the DE2 Click Next on page 5 On page 6 select Enter output clock parameters and verify that 100 MHz is in the Requested settings Click Next Refer to Figure 26 MegaWizard Plug In Manager page 6 of 10 E ALTPLL About Documentation MES Parameter Output LL Sonnet i Settings Clocks clk cl clk c2 cO Core
20. e devices resume counting up Each time KEY2 is pressed the devices count incrementally faster Likewise each time KEY3 is pressed the devices count incrementally slower If any changes are made to the code right click on Tutorial_SDRAM and select Run As gt Nios II Hardware to run the new code Conclusion This application note explains how to set up a Nios II system that uses the SDRAM on Terasic Technologies Inc s DE2 board The LCD controller pushbuttons seven segment displays switches and red and green LEDs on the DE2 board are also used Additional Information Getting Started with Altera s DE2 Board Altera Corporation 2008 DE2 User Manual Altera Corporation 2005 Nios II Processor Reference Handbook Altera Corporation 2009 Nios II Software Developer s Handbook Altera Corporation 2009 Quartus II Handbook Volume 5 Embedded Peripherals Altera Corporation 2009 Digi Key Corporation Page 34 of 35 Setting Up a Nios II System with SDRAM on the DE2 Disclaimer This document is for informational use only and is subject to change without prior notice Digi Key makes no commitment to update or keep current the information contained herein Digi Key does not guarantee or warrant that any information provided is accurate complete or correct and disclaims any and all liability associated with the use of the information contained herein The use of this information and Digi Key s liability is subject to Digi
21. herals select PIO Parallel I O and click Add Do not change any of the default settings The interface is set up for an 8 bit output only PIO which is needed to use the green LEDs Click Finish Refer to Figure 12 To ensure proper functionality rename the pio_0 that was generated Select pio_0 right click on it select Rename rename it to ledg and press Enter PIO Parallel 1 0 pio_0 fx TR PIO Parallel I O AJ Parameter Settings Basic Settings gt Input Options gt Simulation Width Width 1 32 bits Direction O Bidirectional tristate ports Input ports only Both input and output ports Output Port Reset Value Reset Value Output Register F Enable individual bt settingiclearing Figure 12 PIO Green LED Setup Digi Key Corporation Page 12 of 35 Setting Up a Nios II System with SDRAM on the DE2 Add the red LEDs next Expand Peripherals expand Microcontroller Peripherals select PIO Parallel I O and click Add Set the Width to 18 and click Finish Refer to Figure 13 To ensure proper functionality rename the pio_0 that was generated Select pio_0 right click on it select Rename rename it to ledr and press Enter PIO Parallel 1 0 ledr Ta PIO Parallel 1 0 Parameter Settings Basic Settings Input Options gt Simulation width Width 1 32 bits Direction O Bidirectional tristate ports Input ports only Both input and output ports
22. lave JT CLOCK_50 CLOCK_100 Als UART Altera SOPC Builder Nios Il_Processor sopc C Tutorial_Files SDRAM WiosII_Processor sopc Fie Edit Module eri View Tools Avalon Memory Mapped Slave Character LOD jtag_uart_0 component to select it Type 16 and press Enter to assign it a new IRQ value Refer to Figure 19 Use Connec Module Name E onchip_memory2_0 To 31 cpu_0 instruction_master g data_master P jtag_debug_module E jtag_uart_0 avalon_jtag_slave E Ied_0 control_slave E switch s1 E pb s1 E ledg s1 E ledr s1 E seven_seg01 s1 E seven_seg23 31 E seven_seg45 Description On Chip Memory RAM or ROM Avalon Memory Mapped Slave Nios Il Processor Avalon Memory Mapped Master Avalon Memory Mapped Master Avalon Memory Mapped Slave JTAG UART Avalon Memory Mapped Slave Character LCD Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Mapped Slave PIO Parallel 0 Avalon Memory Mapped Slave PIO Parallel 0 Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Mapped Slave PIO Parallel 0 Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Mapped Slave PIO Parallel 1 0 Avalon Memory Manned Slave JHE i Address Map End Ox0080cfft IRQ 31 OxO0sloftt 0x00811097 0x0081100f Ox0081101f Ox0081102f Ox0081103 f 0x0081104f 0x0081105f 0x0081106f Clock Base CLOCK_50 0x008038000 CLOCK_50 IRQ 0 0x00810800
23. lick on it select Rename rename it to pb and press Enter PIO Parallel 1 0 pio_0 Eg TEk PIO Parallel 1 0 Parameter Settings Basic Settings Input Options Simulation Width Width 1 32 bits Direction b Bidirectional tristate ports Input ports only Both input and output ports Output ports only Output Port Reset Yale Reset Value Output Register Enable individual bit setting clearing iN Warning PIO inputs are not hardwired in test bench Undefined values will be read trom Pl input Figure 10 PIO Pushbutton Setup Digi Key Corporation Page 10 of 35 Setting Up a Nios II System with SDRAM on the DE2 PIO Parallel 1 0 pio_0 fx TR PIO Parallel I O kon Parameter Settings Basic Settings i Input Options Simulation Edge capture register synchronously capture Rising edge Falling edge Either edge d Enable bit clearing for edge capture register Interrupt Generate IRG C Level interrupt CPU when any unmasked WO pin i logic true Edge Unterrupt CPU when any unmasked bit in the edge capture register iS logic true fy Warning PIO inputs are not hardwired in test bench Undetined values vill be read from PIO input Figure 11 PIO Pushbutton Interrupt Setup Digi Key Corporation Page 11 of 35 Setting Up a Nios H System with SDRAM on the DE2 The green LEDs are added next Expand Peripherals expand Microcontroller Perip
24. m_0 zs_cs_n_from_the_sdram_0 zs_dq_to_and_from_the_sdram_O 15 0 zs_dqm_from_the_sdram_Of 1 0 Zs_ras_n_from_the_sdram_0 zs_we_n_from_the_sdram_0 out_port_from_the_seven_seqg_01 15 0 out nnt from the seven sen 2315 MI a5 For Help press F1 238 432 Figure 29 pll_block Connections Digi Key Corporation Page 26 of 35 Setting Up a Nios II System with SDRAM on the DE2 Pin Generation Right click on the NiosII_Processor block and click Generate Pins for Symbol Ports Input and output pins are automatically generated for the rest of the Nios II system Verify that the newly generated pins do not cover the vee placed earlier Move vec to a different location if it is covered Refer to Figure 30 for the completed block diagram i Quartus II C Tutorial_Files SDRAM SDRAM SDRAM SDRAM bdf File Edit Yiew Project Processing Tools Window inclkO frequency 50 000 MHz Operation hode Normal Ck Ratio Ph dg DC 50 00 oo 271 e1 11 5400 50 00 Cyclone II i For Help press F1 Figure 30 Complete Quartus II System Digi Key Corporation CLOCK 100 CLOCK_50 lreset_n LCD_E_from_the_Icd 2 LCD_RS_from_the_Icd LCD_RVV_from_the_Icd LCD_data_to_and_from_the_Ica 0 out_port_from_the_ledg 0 in_port_to_the_pb 3 0 zs_addr_from_the_sdram_0 11 0 zs_ba_from_the_sdram_O 1 0 zs_cas_n_from_the_sdram_O zs_cke_from_the_sdram_0 zs_cs_n_from_the_sdram_0O zs_d
25. n to open the Pin Properties window In the Pin name s section rename the pin to CLOCK_50 and click OK Right click somewhere in the block diagram and click Insert gt Symbol Expand the c altera libraries folder expand primitives expand pin select output and click OK Click to place this pin to the left of the CLOCK_50 terminal on the NiosII_Processor Double click the newly created output pin to open the Pin Properties window In the Pin name s section rename the pin to SDRAM_CLK and click OK Move the mouse to the blue inclkO line on the pll_block The mouse cursor should change into a cross hair shape Click and hold to draw a line connecting inclkO to the CLOCK_50 Let go of the mouse when a small box shape appears on CLOCK_50 If a small X appears it is not connected properly Following the same procedure connect cl on the pll_block to CLOCK_50 on the NiosII Processor block connect c0 and Clock_100 and connect SDRAM_ CLK to the line between CLOCK_50 and cl Refer to Figure 29 i Quartus II C Tutorial_Files Test2 SDRAM SDRAM SDRAM SDRAM bdf File Edit View Project Processing Tools Window inclkO frequency 50 000 MHz Operation Mode Normal LCD_E_from_the_Icd LCD_RS_from_the_Icd LCD_RV _from_the_Icd LCD_data_to_and_from_the_Icq 0 Cyclone Il J out_port_from_the_leda 0 zs_addr_from_the_sdram_O 11 0 zs_ba_from_the_sdram_0Of1 0 zs_cas_n_from_the_sdram_O zs_cke_from_the_sdra
26. nt is named or renamed it needs to match what is written in this tutorial exactly or it may not work Starting a New Project in Quartus I Open the Quartus II software and create a new project by selecting File gt New Project Wizard Create a new folder on the C drive called Tutorial Files and create another folder inside of that one called SDRAM Specify the SDRAM folder as the working directory for this project Also in the second box call the project name SDRAM The top level entity on the third line automatically fills in See Figure 1 Page 1 of 35 Setting Up a Nios H System with SDRAM on the DE2 New Project Wizard Directory Name Top Level Entity page 1 of 5 Wi hat is the working directory for this project CAT Utorial FilessSO RAM a What is the name of this project soraw SSS What iz the name of the top level design entity for this project This name is case sensitive and must exact match the entity name in the design file SDRAM Use Existing Project Settings Next gt Finish Cancel Figure 1 New Project Wizard Make sure the new folders were created directly on the C drive and that there are no spaces in the folder names This ensures that there are no spaces in the directory path Folders created in the My Documents folder cause errors For instance C Documents and Settings Firstname_Lastname My Documents causes an error because of the spaces in the directory path Digi Key Corpo
27. opy an existing custom megafunction variation Copyright C 1991 2009 Altera Corporation Figure 22 MegaWizard Plug In Manager Page 1 On the left side under Installed Plug Ins expand I O and click on ALTPLL On the right side where it asks for the name browse to where the project is stored and name it pll_block If it was created on the C drive as described in this tutorial the path name should be C Tutorial_Files Test2 SDRAM pll_block Click Next Refer to Figure 23 MepaWizard Plug In Manager page a Which megarunction would you like to customize Which device family will you be Cyclone T using Select a megatunction from the list below J Arithmetic Which type of output file do you want to create a Communications 0 AHDL Eg DSP n Ga Gat f VHDL ales 10 C Verilog HDL ws y What name do you want for the output fle Browse E ALTASMI PARALLEL CA Tutorial Files SDRAM SpIL black ALTCLECTAL ALTCLELOCE ALTODIO_BIDIF ALTDODIC_IN Return to this page for another create operation ALTODIO OUT Note To compile a project successfully in the Quartus Il software A ALTDO pour design files must be in the project directory in the global user au gt branes specified in the Options dialog box Tools menu or a user library specited in the User Libraries page of the Settings dialog 4 ALTDUS bow Assignments menu Your curent user librar directories are 7 ALTLVDS AeL TPL
28. q_to_and_from_the_sdram_O 15 0 zs_dqm_from_the_sdram_Of1 0 zs_ras_n_from_the_sdram_O zs_we_n_from_the_sdram_0O out_port_from_the_seven_seg_01 15 0 out_port_from_the_seven_seg_23 15 0 out_port_from_the_seven_seg_45 15 0 out_port_from_the_seven_seg_67 15 0 in_port_to_the_switch 17 0 r gt LCD_RS_trom_the_lcd gt 2s_cas_n_from_the_sdram_0 gt 2s_cke_from_the_sdram_0 gt 2s_ s_n_from_the_sdram_0 RIE lt z2s_dq_to_and_from_the_sdram_0 15 0 Eo SK annman a gt 2s_dqm_from_the_sdram_O 1 0 i gt 2s_ras_n_trom_the_sdram_0 pee 767 575 Page 27 of 35 Setting Up a Nios II System with SDRAM on the DE2 Analysis and Elaboration The next step is Analysis and Elaboration Under the Processing menu select Start gt Start Analysis amp Elaboration Choose to save changes if prompted Upon completion of the process a message window appears Ignore the warnings and click OK Pin Assignments Make the pin assignments for the devices Under the Assignments menu select Import Assignments Click the box to the right of the File name section and browse for the Pin_Assignments csv file that accompanies this tutorial Select Open and click OK Verify that the pins are named correctly Under the Assignments menu select Pins In the Filter menu choose Pins unassigned Only 8 pins should appear in the list pins 7 and 15 from each of the pin groups out_por
29. qm_from_the_sdram_Of 0 lt Name Zs_ras_n_tfrom_the_sdram_O z we n from the sdram 0 Niosll_Processor ns S e_N trom The _ a Repeat insert mode Insert symbol as black MegaWizard Plug In Manager Cancel Figure 20 Insert Nios II Processor Add VCC Click to place the symbol somewhere in the block diagram window Right click on the block diagram window again and click Insert gt Symbol Expand the c altera libraries folder expand primitives expand other select vec check the box labeled Repeat insert mode and click OK Place vee somewhere on the left side of the NiosII_ Processor block near reset_n Place another vec somewhere on the bottom right side of the block The initial placements of vee are not important as they can be moved later Hit the Esc key on the keyboard after both instances of vee are placed Digi Key Corporation Page 18 of 35 Setting Up a Nios II System with SDRAM on the DE2 Add Output Pins Right click somewhere in the blank space again and click Insert gt Symbol Expand the c altera libraries folder expand primitives expand pin and select output Check the box called Repeat insert mode and click OK Place two output pins just below the NiosII_Processor block After both output pins are placed hit Ese on the keyboard Move the mouse to the blue line coming from reset_n on the block diagram The mouse cursor should change into a cross hair shape When this happens click
30. ration Page 2 of 35 Setting Up a Nios II System with SDRAM on the DE2 Click the Next button and click Next again on page 2 On the third page select the EP2C35F672C6 chip as the target device as shown in Figure 2 This is the FPGA on the DE2 board Click Next on the remaining two screens and click Finish New Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family Show in Available device list Family Cyclone Package Any Pin count Ari Target device Speed grade Anp C Auto device selected by the Fitter Mw Show advanced devices f Specific device selected in Available devices list oO Available devices Embed PLL EP2C35F454C 453040 EP2C39F 464C 4o3040 EP2 l sor 4e46 4o3040 EP2C35F6 2C6 ZV fl EPA lsSke fel 4o3040 EP2C35F672C6 4o3040 EP l sore fle 4o3040 EP2C350U464C6 4os040 COWIE ADAT Ao 70d z Back Finish Cancel Figure 2 FPGA Selection Create a new block diagram by selecting File gt New selecting Block Diagram Schematic File and clicking OK To save this file select File gt Save As not to be confused with Save Project call it SDRAM and click Save Naming it SDRAM ensures that this block diagram file is the top most entity of the project as specified in Figure 1 Digi Key Corporation Page 3 of 35 Setting Up a Nios II System with SDRAM on the DE2 Nios Il System Design
31. select JTAG UART and click Add Do not change any of the default settings Click Finish Refer to Figure 7 JTAG UART jtag_uart_0 x JTAG UART Parameter Settings Configuration gt Simulation Write FIFO Data trom Avalon to JTAG EA F Construct using registers instead af memory blocka Read FIFO Data trom JTAG to Avalon C Construct using registers instead af memory blocka Figure 7 JTAG UART Setup Digi Key Corporation Page 7 of 35 Setting Up a Nios II System with SDRAM on the DE2 Add an LCD To add the LCD expand Peripherals then expand Display select Character LCD and click Add There are no settings to modify so select Finish Refer to Figure 8 Rename the Icd_0 that was generated to ensure proper functionality Select Icd_0 right click on it select Rename rename it to Icd and press Enter Character LCD Icd_0 Character LCD Parameter Settings The Optrex 16207 LCD Controller core provides the hardware interface required for a Mios ll processor to display characters on an Optrex 16207 for equivalent 16x2 character LCD panel Device drivers are provided inthe HAL system library for the Mios ll processor There are no user contiqurable settings Figure 8 LCD Controller Setup Digi Key Corporation Page 8 of 35 Setting Up a Nios H System with SDRAM on the DE2 Add Parallel I O PIO Add switches to the system Expand Peripherals then expand Microcontroller Peripherals
32. t_from_the_seven_seg_XX where XX is 01 23 45 67 If there are more than eight pins listed check the SOPC builder section of this tutorial again to ensure that all of the devices are named exactly as specified in this tutorial Close the Pins window Compilation Compile the design Under Processing select Start Compilation The success message in Figure 31 appear upon completion Ignore the warnings that are listed and click OK Quartus Il Figure 31 Successful Compilation Window Digi Key Corporation Page 28 of 35 Setting Up a Nios H System with SDRAM on the DE2 System Programmer Plug the power supply and USB Blaster cable into the DE2 board Hit the red power button to turn on the DE2 board Under the Tools menu select Programmer If a pop up window appears click OK In the Programmer window choose Hardware Setup Verify that the USB Blaster USB 0 is selected and click Close Verify that the Mode selected is JTAG Set switch SW19 on the DE2 board next to the LCD to Run Click Start in the programmer window Refer to Figure 32 for the programmer setup Tim al W Quartus II C Tutorial_Files Flash_Memory Flash_Memory Flash_Memory Flash_Memory_time_limited cdf fal File Edit Processing Tools Window a Hardware Setup USB Blaster 15B 0 Made JTAG Progress Enable real time ISP to allow background programming for MAS Il devices asa e pe po jo dd Ee Flash_Memory_time_limit EP2C35F672 OO5
33. the DE2 SDRAM Controller sdram_O Eg r SDRAM Controller S Parameter Settings Memory Profile gt Timing Data width Architecture Address widths Share pins via tristate bridge F Controller shares dofdame addr W2 pins Tristate bridge selection Generic memory model simulation onki Include a functional memory model in the system testbench Memory size 6 MBytes 41943504 x 16 64 MBits Figure 15 SDRAM Setup The SDRAM operates at a different clock speed than the rest of the system Under the Clock column change the sdram_0 clock to CLOCK_590 Do this by clicking on the Clock_100 across from the SDRAM and then choose CLOCK_50 from the drop down menu Refer to Figure 16 Digi Key Corporation Page 15 of 35 Setting Up a Nios II System with SDRAM on the DE2 Microc Snir oller Peripheral s1 Avalon Memory Mapped Slave CLOCK_100 0201011050 0x0101105f Interval Timer E seven_seg 23 PIO Parallel 0 PIO Parallel VO s1 Avalon Memory Mapped Slave CLOCK_100 001011060 Ox0101106 Multiprocessor Coordinatic E seven_seg_ PIO Parallel 1 0 PLL 1 Avalon Memory Mapped Slave CLOCK_100 0201011070 Ox0101107 USB v E seven_seg_67 PIO Parallel I O lt i gt s1 Avalon Memory Mapped Slave px01011080 0x0101108f zan E sdram_0 SDRAM Controller s z Avalon Memory Mapped Slave CLOCK 50 0 00800000 OxDOffffff wJ e e G e L
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