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1. seas qansesens cersaececesensaeeneae 4 5 1 15 2 25 Time sec Figure 54 Collected result from PNP transistor 6 E F F s 4 5 3 n a 2 5 1 a 1 r E r r r r o 0 05 0 1 0 15 0 2 025 03 0 35 0 4 0 45 Time sec Figure 55 Collected result from microcontroller As it shown in figure 54 the switching frequency of the transistor is lower than that of the PIC microcontroller Accordingly the transistor was not able to operate properly for the required application due to its low switching rate MRes Thesis Mersedeh Maksabi October 2013 47 Experimental Setup and Practical Results MRes In Railway System Integration 6 1 2 Experimental Setup second phase Following the first chapter the last objective of the defined project is to identify the state of each lever normal reverse and effectively demonstrate 2 aspects of signalling based on the operational logic of each lever through an electrical circuit Accordingly the adopted strategy to achieve this task is to use a magnet and reed switch The magnet can easily attract the levers as they are constructed of metal The propagated magnetic field by magnets will be sensed by an internal switch of the reed switch magnetic contact Subsequently activation of the internal switch indicates that the corresponding lever has been reversed or unlocked and ul
2. cC Ini In3 15 Behavel Behave Behave 4 BehaveS Behaved 0 0 0 0 1 0 dis dis en en en en P 0 0 0 0 1 1 dis dis en dis dis en 0 0 0 1 0 0 dis en en en ds en 0 0 0 pg 1 dis dis jen jen 0 0 0 TS mac T ee 265 0 0 0 EIL 0 0 1 0 0 0 dis en en en dis en 0 0 1 0 0 1 dis dis en en dis en 0 0 0 dis dis en en dis en 0 0 1 0 1 1 95 ds dis dis en 0 0 1 110 0 dis en en en dis en 0 0 1 1 9 1 dis dis en en dis en 0 0 1 1 1 0 Re 0 0 1 1 1 1 t Geet 0 1 0 0 0 0 dis en en en ds dis 0 1 0 1 Aaa ee 1 0 0 1 0 oe 2 0 1 0 0 1 I1 aS e 0 1 0 110 0 dis en en en dis dis 0 1 0 1 0 1 L ced E E 0 1 0 1 1 0 Lm S Eee 0 1 0 1 1 Fea 22 0 1 88 ES So 0 jen en dis dis 0 1 1 0 0 SEN 225 s ues Pl 0 1 1 0 1 238 Pe 0 1 1 0 1 1 gt 5 5 0 1 1 1 0 0 en en en en dis i 0 1 1 1 0 1 0 1 1 1 1 0 Figure 24 Simulation model for the reverse route Figure 25 is presenting the formula node for the second simulation Accoding to figure 24 there are 18 if statements inside the control unit which will disabele enable each push button by giving them value 2 and value zero to their corresponding outputs MRes Thesis
3. 1 Clock nibble into LCD DelayFor18TCY E PIN 20 ifdef UPPER Upper nibble interface TRIS DATA PORT Oxf0 else Lower nibble interface TRIS DATA PORT l OxOf endif endif return MRes Thesis Mersedeh Maksabi October 2013 103 Appendix B MRes In Railway System Integration Appendix B Electrical components datasheets e Microcontroller PIC18f452 Pin connection Top view PIC18F442 PIC18F452 Absolute maximum rating Ambient temperature under bias P PEEPAR EEE TA AE N 5590 to 125 Storage temperature 960 194 Voltage on any pin with respect to V amp 5 except VDD MGLA and 4 sss to 0 3 Voltage on VDD with respact V88 D 3V to 47 5V Voltage on MGLA with respect to VSS Note 2 OV 9 418 26 Voltage on 4 with respect to Wes cscs a D 10 5 Total power dissipation Note 1 Maximum current out of Vss ms cunt nio 250 Input clamp currant WK VI lt or Vi gt t20 mA Output damp current lex V
4. 25 4 Simulation results using Proteus 1618 25 4 System 202 25 4 2 Weston Deser puoi 27 421 Desist 30 CHAPTER FIVE 32 5 Introduction to Linear Machine and PECO Turnout 32 SL AIM as 32 SJ Working 33 212 Linear o og eed un nel eile ieee 35 5 2 PECO MOLDE 36 5 3 Software Implementation he peo RU LORI FAEERE RR 38 5 4 Hardware ImplementattOR 39 5 5 Introduction to Circuit Components sas 41 Sodo 2 41 3 5 24 41 08 HEN 43 CHAPTER SEX gene 40 44 6 Experimental Setup and Practical 44 NN EE 46 6 1 2 Experimental Setup second eee eee entente nent ene 48 6 2 Overview of Components in Final Circuit eee 48 6 2 1 Introduction to magnetic actuators and magnetic sensor 48 520 dase SU 49 6 2 3 Sensitivity Evaluation of Magnetic 49 624 Switch B
5. eed tese ced ania 27 Figure 30 Activation of levers for normal 28 Figure 31 Activation of levers for reverse route 28 Figure 32 Activation of lever 4 i uni eii pei i Lee meta eee 29 Figure 33 Design Evaluation te eiue io La d ah Que aes 30 Figure 34 Leyers mechans iiss aee desideras podes 31 Figure 35 Linear machine Chapman 1999 22222222 4 1 1 0000000 0 0103332 32 Figure 36 Starting a linear machine Chapman 1999 eee 33 Figure 37 Linear motor Chapman 1999 35 38 PL I e PECO MOLON sir erae oa 37 Figure 39 PECO motor with bended central 1625 37 Figure 40 Illustration of switches and part of the track layout on the baseboard 37 Figure Ale Pulse Sener atl LE 38 Figure 42 Pulse generating 39 Figure 43 Circuit block diagram ea recien tdi p e 40 Figure PE NC and zie us ooo eiu ed ocius 4 45 Op amp Symbol 41 Figure 46 Negative feedback network Se ee ed 42 Figure 47 LM741 intemal architecture oec duce 42 Figure 48 Position of op amp reed relay and 43 Figure 49 Demonstration of prelimin
6. 53 Interlocking a tal steve i fedus 53 Position of magnetic 54 54 Station STETIT ous omoes 54 Distant steal eg ea as 55 Station started signal for the reverse 55 Shutting signal and 55 Shunting signal and point 56 LCD simulation result ore 57 Mersedeh Maksabi October 2013 ix Preliminaries List of Abbreviations Term Explanation Meaning Definition AC ac Alternating Current Back EMF Back Electromotive force BR British Railway DC de Direct Current GWR Great Western Railway KVL Kirchhoff Voltage Low LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode Op Amp Operational Amplifier PCB Printed Circuit board PIC Peripheral Interface Controller SSI Solid State Interlocking TFMs Trackside Functional Modules MPM Multi Processor Module Mersedeh Maksabi October 2013 CHAPTER ONE MRes In Railway System Integration CHAPTER ONE 1 Introduction 1 1 Motivation for Building Interlocking Machines In the first years of the railway industry signals and switches were distributed over a predefined area in the vicinity of the stations Switch tender or signalmen had to walk a long distance when signal
7. MU Author M Maksabi MT MH Levers mechanism due to the reverse route TH Device PIC 18F452 include lt p18f452 h gt EE EEE Configuration Bits kk kk k pragma config OSC XT pragma config PWRT Power up timer disabled pragma config OFF Brown out reset disabled pragma config LVP OFF Low voltage disabled pragma config WDT OFF Watch dog timer disabled pragma config DEBUG OFF Background debugger disabled F XXE AR A A kk kkk kkk and Definitions pragma code define Lever4LowerLimit PORTBbits RBO Anput define Lever4UpperLimit PORTBbits RB1 input define Lever4GoUp PORTBbits RB2 hinput define Lever4GoDown PORTBbits RB3 define Lever4IsUp PORTBbits RB4 output define Lever4IsDown PORTBbits RB5 output define Lever5LowerLimit PORTBbits RB6 define Lever5UpperLimit PORTBbits RB7 input define Lever5GoUp PORTCbits RCO define Lever5GoDown PORTCbits RC1 define 5 5 PORTCbits RC2 output define Lever5IsDown PORTCbits RC3 output define Lever6LowerLimit PORTCbits RC4 input define Lever6UpperLimit PORTCbits RCS input define Lever6GoUp PORTCbits RC6 MRes Thesis Mersedeh Maksabi October 2013 70 Appendix A MRes In Railway System Integration define Lever GoDown PORTCbits RC7 input define Lever6IsUp PORTDbits RDO
8. Single In Line Reed Relays DESCRIPTION Single In Line Reed Relays reduce the required t space to a minimum Requiring only half the PCB t area of the DIP or DIL series the SIL relays offer all the advantages of Reed Technology CHARACTERISTICS FEATURES High resistance coils of up to 2000 Q at 12 VDC Magnetic shield available Breakdown voltage coil contact of up to 4 25 kVDC High resistance version Contact form 1A 1B or 1C Other coil resistances available Option with coax screen for 2 50 Ohm Impedance DIMENSIONS All dimensions in mm inch With magnetic shield rat roe tof Send 545 925 0 2101 Without magnetic shieki PIN OUT View from top of component 2 54mm 0 10 pitch grid 1 MRes Thesis Mersedeh Maksabi October 2013 107 Appendix B Dimensions mmilnch de 1108 Teuma gem VN 1522 Nike MRes In Railway System Integration laamatric Malum 27 MEDER electronic SILOS TAT2 TID Conditions Typ Uni 450 50 NENNEN MRes Thesis Mersedeh Maksabi October 2013 108 MRes In Railway System Integration Appendix B magnetic proximity sensor actuator 10 51135 500 CaM LON Tuc 20 BIKI AINO 153600380 umuy VOUS sey
9. Magnetic field into page Switch Figure 36 Starting a linear machine Chapman 1999 Figure 36 shows the linear machine under starting conditions As the switch closes the current flows in the bar this triggers the machine to work The current is given by Kirchhoff s voltage law ind 5 Vi eina 0 When the bar is at rest hence l T this moves down through the bar MRes Thesis Mersedeh Maksabi October 2013 33 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor According to equation 1 the current flows through the wire due to the presence of a magnetic field which ultimately induces a force on the wire and based on the geometry of the machine this force can be calculated by the formula Fina UB eq 6 Based on above equation and Newton s law the bar will accelerate to the right Voltage will appear across the bar as the velocity of the bar starts to increase The voltage can be determined by equation 2 which will reduce due to the geometry of the device to VBI eq 7 According to Kirchhoff s voltage law the voltage will reduce as the current flow in the bar Vp einat i Se eq 8 R The current will decrease as increases Will increase to be equal to accordingly the net force on bar will reduce to zero and the bar will reach a constant steady state speed The speed of the moving bar can be determi
10. char data Holds the data retrieved from the LCD ifdef BIT8 8 bit interface RW 1 Set control bits for the read RS_PIN 0 DelayFor18TCY 1 Clock data out of the LCD controller DelayFor18TCY data DATA_PORT Save the data in the register E 0 RW PIN 0 Reset the control bits else 4 bit interface RW_PIN 1 Set control bits for the read RS_PIN 0 DelayFor18TCY E_PIN 1 Clock data out of the LCD controller DelayFor18TCYY ifdef UPPER Upper nibble interface data DATA PORT amp OxfO Read the nibble into the upper nibble of data else Lower nibble interface data _ lt lt 4 amp 0 Read the nibble into the upper nibble of data endif E_PIN 0 Reset the clock MRes Thesis Mersedeh Maksabi October 2013 92 Appendix A MRes In Railway System Integration DelayFor18TCYY E PIN 1 Clock out the lower nibble DelayFor18TCY ifdef UPPER Upper nibble interface data I DATA PORT 24 amp 0x0f Read the nibble into the lower nibble of data else Lower nibble interface data DATA_PORT amp OxOf Read the nibble into the lower nibble of data endif E 0 RW PIN 0 Reset the control lines endif return data amp 0x7f Return the address Mask off the busy bit MRes Thesis Mersedeh Maksabi October 2013 93 Appendix A MRes In Railway System Integration include lt p18F452 h gt include xl
11. pp 255 258 LawrenceAndyAn Introduction to Railway Signalling and Equipments Online 18 August 2011 Cited 24 5 2014 http cs swan ac uk csal Talks Railwaytalk 1 pdf Macdougall A railway signalling system EP0341826GB 1994 MRes Thesis Mersedeh Maksabi October 2013 63 Appendix A MRes In Railway System Integration MacmillanB E Amplifier circuit and method for providing negative feedback 2001071905 A3United state 2002 Microchip 28 40 44 Enhanced Flash Microcontrollers s l Microchip Technology Inc 2004 MPLAB C18 c compiler libraries s l Microchip Technology Inc 2005 NewmanG D Railway signalling system 5 437 422United State 1995 Principle of interlocking Online 2004 Cited 25 7 2013 http mysite du edu etuttle rail lock html SignallingUKThe Development and Principles of UK Signalling Online 2013 Cited 26 02 2013 Jhttp www railway technical com sigtxt1 shtml Silicon germanium base heterojunction bipolar transistirs PATTONG L1988 Vol 9 pp 165 167 Solid state interlocking SSI an integrated electronic signalling system for mainline railways CribbensAmay 1987 1987 Railway electrification and transportation signalling Electronic circuits pp 148 158 WallerJSolid state interlocking Railway control systems london A amp C Black 1991 21 31 MRes Thesis Mersedeh Maksabi October 2013 64 Appendix A MRes In Railway System Integration
12. w e Sea m Typical 94 10 Resonant Frequency ps nme e omes Operating Temp a e ERO 99m Storage Temp t et ee im rues __ E IN GE Au ore E Protection Regulation Typical frequency response curve VOLTAGE SOUND PRESSURE VOLTAGE CURRENT CONSUMPTION 3 35 4 45 5 55 6 65 W 3 35 4 45 5 55 6 65 TW MRes Thesis Mersedeh Maksabi October 2013 111 Appendix B MRes In Railway System Integration e LCD PC1602F B Hi us 0 3 61 0 x 15 8 5 1 9 7 __ 0 58 x 0 88 5 DR ELS MRes Thesis Mersedeh Maksabi October 2013 112 Appendix B MRes In Railway System Integration e PNP Transistor CBC212L BC212 BC212B BC213 BC214 Amplifier Transistors PNP Silicon February 2001 Rev 1 MRes Thesis Mersedeh Maksabi October 2013 113 Appendix B MRes In Railway System Integration Electrical characteristics lg 10 wide 0 CHARACTERISTICS 258 le 2 0 Veg 5 0 Vidc le 100 5 0 Mote 1 le ly 0 5 mich le 100 mAdc ly 5 0 Note 1 Baso Emitter Saturation Voltage le 100 m de Ip 5 0 mAdc Base Emitiar On Vnitaga Curreni Gai
13. AL Figure 33 Design Evaluation As is obvious lever 4 cannot get reversed unless lever 5 is reversed and lever 6 is locked In figure 33 the red circle shows that Lever5UpperLimit switch is not active which means lever 4 is in normal state and hence there is no signal 4 2 1 Design Optimisation The functionality of the mechanical lever frame has been simulated trough two sets of design concerning both straight and reverse routes The adopted logic has been extended both through MPLAB and Proteus in order to simulate the behaviour of all the levers in one workspace Figure 34 determines the final simulation model concerning bith the straight and reverse route through the proteus software As it is understood so far lever 5 pursues independent operation which means it can move freely without any restriction However to clear the reverse route lever 5 needs to be unlocked to allow proceeding in the shunt neck Hence the switches which simulate the normal state of lever 5 have been omitted from the design MRes Thesis Mersedeh Maksabi October 2013 30 MRes In Railway System Integration Simulation results using Proteus ISIS Figure 34 Lever s mechanism MRes Thesis 31 Mersedeh Maksabi October 2013 CHAPTER FIVE MRes In Railway System Integration CHAPTER FIVE 5 Introduction to Linear Machine and PECO Turnout Motor 5 1 Linear Machine A linear machine is about the simplest version of the machines which o
14. Function Name SetDDRamAddr Return Value void Parameters CGaddr display data address Description This routine sets the display data address T of the Hitachi HD44780 LCD controller The user must check to see if the LCD controller P is busy before calling this routine k fe k k k kk k k k k k k kk k k k KK void SetDDRamAddr unsigned char DDaddr X X X X ifdef BIT8 8 bit interface TRIS DATA PORT 0 Make port output DATA PORT DDaddr 0b10000000 Write cmd and address to port RW PIN 0 Set the control bits RS PIN 0 DelayFor18TCY E_PIN 1 Clock the cmd and address in DelayFor18TCY E PIN 0 DelayFor18TCY TRIS DATA PORT Oxff Make port input else 4 bit interface ifdef UPPER Upper nibble interface TRIS DATA PORT amp OxOf Make port output DATA PORT amp OxOf and write upper nibble DATA PORT DDaddr 0610000000 amp Oxf0 else Lower nibble interface TRIS_DATA_PORT amp Oxf0 Make port output DATA PORT amp Oxf0 and write upper nibble DATA PORT DDaddr 0b10000000 gt gt 4 amp OxOf endif RW PIN 0 Set control bits RS_PIN 0 DelayFor18TCY 1 Clock the cmd and address in DelayFor18TCY E PIN 0 ifdef UPPER Upper nibble interface DATA PORT amp OxOf Write lower nibble DATA PORT DDaddr 4 amp
15. Mistoty of dere 6 2 3 Past Interlocking Machines scissscasastesarsasteaseandvevnetabsageadassooesssaasbacvaduasessaevstanasees 8 Z3 8 2 9 PX NEMO Gd a E 9 px MSS 10 2 3 3 na 10 PT JUNCHON TL S 11 Zl Mocking 12 23 8 12 A MES Jr erm 13 230 Saxby and Farmer Rocker 13 2 29 11 Saxby Gridiron 14 2 4 Present Day Interlocking Machines 15 2 4 1 Safe Data SIRE T T 15 DPR 15 2 4 3 The Interlocking Cubicle usines pitt itt beali ben du esae tes 16 244 Multi Processor Module irte 18 23 Chapter 18 Mersedeh Maksabi October 2013 iv Preliminaries CHAPTER THR EE 19 3 Visualisation of Interlocking Systems through LabVIEW ee eee 19 3 Testing over Straight Route set from 20 3 2 Testing over Reverse Route set from C to D 20 3 3 Logical Simulation of the Normal 21 3 4 Logical Simulation of the Reverse Route eene 23 CHAPTER
16. define LeverlIsUp PORTBbits RB2 output define Lever2UpperLimit PORTBbits RB3 input define Lever2GoUp PORTBbits RB4 define Lever2IsUp PORTBbits RB5 output define Lever3UpperLimit PORTBbits RB6 input define Lever3GoUp PORTBbits RB7 define Lever3IsUp PORTCbits RCO output define Lever4LowerLimit PORTCbits RC1 input define Lever4UpperLimit PORTCbits RC2 input define Lever4GoUp PORTCbits RC3 define Lever4GoDown PORTCbits RC4 input define Lever4IsUp PORTCbits RC5 output define Lever4IsDown PORTCbits RC6 output define Lever5UpperLimit PORTCbits RC7 input define Lever5GoUp PORTDbits RDO define 5 PORTDbits RD1 output define Lever6LowerLimit PORTDbits RD2 input define Lever6UpperLimit PORTDbits RD3 input define Lever6GoUp PORTDbits RD4 define Lever6GoDown PORTDbits RD5 nput define Lever6IsUp PORTDbits RD6 output define Lever6IsDown PORTDbits RD7 output MRes Thesis Mersedeh Maksabi October 2013 82 Appendix A MRes In Railway System Integration void main TRISB 0xDB TRISC 0x9E TRISD 0x3D PORTB PORTC PORTD 0 while 1 if Lever2UpperLimit amp amp Lever3UpperLimit if UpperLimit amp amp Leverl GoUp Lever lIsUp 1 else LeverlIsUp 0 if Lever3UpperLimit amp amp Lever3GoUp Lever3IsUp 1 else Lever3IsUp 0 if Lever2UpperLimit amp amp Lever2Go
17. output define Lever6IsDown PORTDbits RD1 output The code works as next if LeverSUpperLimit 1 and Lever4lowerLimit 1 that is lever5 is lifted and lever4 is in normal state locked then lever 6 can be lifted More over if upper limit is reached Go up button is invalid and vice versa void main TRISB 0xCF TRISC 0xF3 TRISD 0xFC PORTB PORTC PORTD 0 reset all the ports while 1 if LeverSUpperLimit amp amp Lever4LowerLimit if Lever6UpperLimit amp amp Lever6GoUp Lever6IsUp 1 Lever6IsDown 0 lelse Lever6IsUp 0 if Lever6LowerLimit amp amp Lever6GoDown Lever6IsUp 0 Lever6IsDown 1 else Lever6IsDown 0 else Lever6IsUp Lever6IsDown 0 MRes Thesis Mersedeh Maksabi October 2013 71 Appendix A MRes In Railway System Integration if Lever5UpperLimit amp amp Lever6LowerLimit if Lever4UpperLimit amp amp Lever4GoUp Lever4IsUp 1 Lever4IsDown 0 else Lever4IsUp 0 if Lever4LowerLimit amp amp Lever4GoDown Lever4IsUp 0 Lever4IsDown 1 else Lever4IsDown 0 MRes Thesis Mersedeh Maksabi October 2013 72 Appendix A MRes In Railway System Integration Author M Maksabi MII HII LED and Switches MINIT Device PIC 18F452 MINIT IM I include lt p18f452 h gt include lt delays h gt Configuration bits pragma config OSC AMHz Crystal XT oscillator pragma config PWRT OFF Power up t
18. queuing Are 2299151594 PU uinulpxey peuojtag 9181990 eBwj oA peuojg 19501194 921 queiin 21810514 664 858 ON DUC WXAOLSOO CATINON UAJASNVUL NOLLONYLSNOD SLNVNOdWOO SY UAINOLSNI UOLVAL V NOSN3S 4 JLAN VH NOILAINOSAA 00G6 GETAG OT uO Peso OOG SETLS OT ON Baq MRes Thesis 109 Mersedeh Maksabi October 2013 MRes In Railway System Integration Appendix B e Reed switch Sensor GANNIL LON COXXXX GaddIyLS 205 5168 NOWVH 796 70352 xz x 8611015 91 80 X SZE NOLLVOIJILN3GI XBW WYO 002 SW OV SE O OG v SWH OV 5 0 OG v xen rz ezl ost t 3 OG A 05 ul 168781 ose XEN OV 000 SELZS 2G Z L1n das OL y 7951415313 b c0S SEL6S O1G YOSNAS ZOS SEL6S ON spea Buipniour eouejsises PJU 3uaun2 Buryoymg ueunD uwop eaug MRes Thesis 110 Mersedeh Maksabi October 2013 Appendix B MRes In Railway System Integration Buzzer Specification Condition E om oc
19. y BRE CD T swor 1 7 T c gue ga R2ISDOVVN LEVERJ GODOWN mi fos ep ower nat ovem na eus ow sFor Figure 28 Levers are reversed MRes Thesis Mersedeh Maksabi October 2013 26 Simulation results using Proteus ISIS MRes In Railway System Integration 4 2 Design Description In this model lever GoDown switch is activated from the beginning which means corresponding green LED is blinking this indicates the first lever is locked by default Hence to reverse lever 1 the GoUp switch has to be activated which means Lever2UpperLimit and Lever3UppeLimit have to be achieved first Figure 29 shows independent logical operation within both lever 2 and lever 3 As is obvious from the figure both blue LEDs corresponding to Lever 2 and Lever 3 is ON through activation of Lever 2 GoUp and Lever 3 GoUp This means that the levers can get reversed independently Accordingly the Lever 1 GoUp switch is ON but the corresponding blue LED is OFF which means that lever 1 is still locked and the distant signal blue LED is not clear yet Figure 29 First shot from simulation Figure 30 presents activation of LeverlGoUp switch based on activation of Lever2UpperLimit and Lever3UpperLimit SPDT switc
20. 2 20 amp amp Inb 1 E Outl 2 Out2 2 Out3 0 Out4z0 Out5z2 Out6 0 75 Disabled if Ind 0 amp amp In2 0 amp amp In3 1 amp amp Ind 0 amp amp InS 1 amp amp In6 0 01 2 Out2 2 Out3 0 Out4 z0 Outd 2 006 0 i Ind 0 amp amp In2 0 88113 51 amp amp Ind 0 amp amp InS 1 amp amp In6 1 m Outl 2 Out2 2 Out3 0 004 0 045 2 006 0 cenas In 0 amp amp In2 0 amp amp In3 1 amp amp Ind 1 amp amp In5 20 amp amp In6 0 Outl 2 Out2 0 Out3 0 Out4z0 Out5z2 Out6z0 1 0 amp amp In2 0 amp amp In32 21 amp amp Indz z1 amp amp In5z 20 amp amp In6z 1 Outl 2 Out2z2 Out3 0 Out4z0 Out5z2 006 0 if nlzz0 amp amp In2 1 amp amp In32 20 amp amp IM 0 amp amp In5z 20 amp amp In6z 20 Outl 2 Out2 0 Out3 0 Out4 z0 Out522 Out6z2 if Ind 0 amp amp In2221 amp amp In32 20 amp amp Inda 21 amp amp In52 20 amp amp 1n62 20 Outl 2 Out2 0 Out3 0 Out4z0 Out5z2 Out6 2 if Ind 0 amp amp In2 1 amp amp In3 1 amp amp Ind 0 amp amp In5 0 amp amp In6 0 Outi 0 Out2 0 Out3 0 0 4 0 lt 2 Out6z2 ma annt ar Figure 25 Control unit for the reverse route MRes Thesis Mersedeh Maksabi October 2013 24 CHAPTER FOUR MRes In Railway System Integration CHAPTER FOUR 4 Simulation results usin
21. According to the preliminary locking all locking procedures have to be finished prior to the movement of the lever and all unlocking procedures have to be done afterwards The preliminary locking in lever locking cannot be achieved precisely but in catch locking it can 2 4 Present Day Interlocking Machines 2 4 1 Safe Data Transmission Railway signalling is a main example of data transmission between different places Hence system reliability is dependent upon the information received being similar to the one sent in the context of fail safe system Over the years since the advent of computer based safety systems well developed techniques have been used to protect data which is sent over serial telecommunication channels Waller 1991 2 4 2 SSI System Up until the 1980s the functionality of the relays was well defined Whilst the behaviour of electronic was not The mentioned situation has been reviewed by advent of microprocessors Hence a new generation of SSI Solid State Interlocking was designed The designed system was very much safer in compare with corresponding relay counterparts SSI system mainly consists of two parts a control centre and line side subsystems An important part of the control centre is interlocking in which an essential logic is implemented to provide safety commands for the other parts of the SSI system line side subsystem Moreover a secure communication line between interlocking has been provide
22. Mersedeh Maksabi October 2013 23 Visualisation of Interlocking Systems through MRes In Railway System Integration LabVIEW Formula Node TO ever Lever1 if nd 0 amp amp In2 0 amp amp In3 0 amp amp Ind 0 amp amp InS 0 amp amp In6 0 TN Y Em Out z2 Out2 0 Out3 0 0 4 0 Out5z0 0 6 0 Disabled 1 0 Inl if Inlz z0 amp amp In2 0 amp amp In32 20 amp amp IM 0 amp amp In z 20 amp amp In6z 21 Out 22 Out2z2 Out3 0 Out4z0 Out5z2 Out6 0 L ever Leni if Inl 20 amp amp In2e 0 amp amp In3 0 881 0 amp i amp InS 1 In 20 2 Outl 2 Out2 2 Out3 0 Out4z0 0 5 0 006 0 2 0 amp amp In2 0 amp amp In3 0 amp amp Ind 0 amp amp In52 21 amp amp In6 1 Outl 2 Out2 2 Out3 0 0 4 2 2 0 6 0 Lever Lever3 77 3 0 amp amp In2 0 amp amp In3 0 amp amp Ind 1 amp amp Ind 0 amp amp 0 Disabled ipi Outl 2 0402 0 Out3 0 Out4 0 Out5 2 006 0 0 amp amp In2 0 amp amp In3 0 amp amp Ind 1 amp amp In5 0 amp amp In6z 21 Leverd Leverd Outl 2 Out2 2 Out3 0 004 0 OutS 2 0 6 0 Um Ind if n1zz0 amp amp In2 0 amp amp 3 1 amp amp Indz z0 amp amp 5 0 amp amp Inb 0 Outl 2 Out2 0 Out3 0 Out4z0 Out5z2 Out6 0 Lever5 if Ind 0 amp amp In22 20 amp amp In3221 amp amp Ind 0 amp amp In
23. Multi Processor Module Multi processor module is the name of software which is applied in SSI systems for a railway network The MPM software may contains one processor for receiving commands by considering the operating parts of trackside equipment and also transporting other corresponding commands relates to present state of other trackside equipment The second processor will be applied to achieve the final commands from the first one which ultimately would have an effect on operation within trackside equipments through a data link The first processor runs a higher speed as its clock speed is more than that of in the second processor However the speed of the first processor for some of the program which interface with the second processor has been arranged to be slower 2 5 Chapter Summary The history of interlocking control systems from the earliest days of the railway industry when fairly safe distances between trains in operation were governed by signalmen with their rudimentary tools to complicated signalling operating systems has been covered in this chapter In addition various types of locking machines invented from the earliest days of railway industry to the present interlocking and computer based signalling systems which are applied to the modern railway industry have been introduced The functionalities and weaknesses of each invented locking machine as well as their working mechanisms are described MRes Thesis Mersede
24. O0xf0 else Lower nibble interface DATA_PORT amp Oxf0 Write lower nibble DATA PORT DDaddr amp OxOf endif DelayFor18TCY 1 Clock the cmd and address in MRes Thesis Mersedeh Maksabi October 2013 98 Appendix A MRes In Railway System Integration DelayFor18TCYY E PIN 20 ifdef UPPER Upper nibble interface TRIS DATA PORT Oxf0 Make port input else Lower nibble interface TRIS DATA PORT OxOf Make port input endif endif return MRes Thesis Mersedeh Maksabi October 2013 99 Appendix A MRes In Railway System Integration include lt p18F452 h gt include xlcd h 78 7 7 2 E 2 k Function Name WriteCmdXLCD Return Value void Parameters cmd command to send to LCD Description This routine writes a command to the Hitachi HD44780 LCD controller The user must check to see if the LCD controller is busy before calling this routine K k k K K k K K K void WriteCmdXLCD unsigned char cmd X X x X X Xo x X X Xx ifdef BIT8 8 bit interface TRIS_DATA_PORT 0 Data port output DATA_PORT cmd Write command to data port RW PIN 0 Set the control signals RS PIN 0 for sending a command DelayFor18TCY E 1 Clock the command in DelayF
25. Set DD Ram address to 0 while BusyXLCD Wait if LCD busy SetDDRamAddr 0x80 Set Display data ram address to 0 return MRes Thesis Mersedeh Maksabi October 2013 89 Appendix A MRes In Railway System Integration include lt p18f452 h gt include xlcd h 2 2 E ae 2 ae fe k k k k k k k k k k k k kk k kk k k k k k KK k KK k k K K k K K K Function putrsXLCD Return Value void i Parameters buffer pointer to string Description This routine writes a string of bytes to the Hitachi HD44780 LCD controller The user gt must check to see if the LCD controller is 7 busy before calling this routine The data is written to the character generator RAM or y the display data RAM depending on what the T previous SetxxRamAddr routine was called 3 k k kk void putrsXLCD const char buffer unsigned char val 0 while buffer Write data to LCD up to null while BusyXLCDQ Wait while LCD is busy SetDDRamAddr val WriteDataXLCD buffer Write character to LCD buffer Increment buffer val return MRes Thesis Mersedeh Maksabi October 2013 90 Appendix A MRes In Railway System Integration inc inc RR lude lt p18F452 h gt lude xlcd h Function Name putrsXLCD R
26. a short period of time with maximum voltage of 16 VAC Therefore to energise the motor momentarily the idea is to generate a square wave with 50 ms duty cycle In order to avoid winding and prevent getting warm 2 seconds delay will come up after each clock rising edge Left winding Right winding 1 Voltage V 4 4 8 sec 4sec 8 NEL Time second Figure 41 Pulse generation To perform this task PIC microcontroller PIC 18F2550 has been programmed through the MPLAB IDE v8 84 C18 compiler software The idea is to define two variables output left and output right Each output variable has two states of ON and OFF Accordingly the state of each output variable was examined and based on that they will get a delay of 2 seconds The code for square pulse generation is presented in Appendix A MRes Thesis Mersedeh Maksabi October 2013 38 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor Figure 42 Pulse generating flowchart 5 4 Hardware Implementation In order to energise the motor and to trigger the switch to move the track to left and right directions two output pins of the PIC microcontroller have to be connected to two operational amplifiers The amplifiers have to be connected in such a manner as to provide negative feedback as oncoming
27. all consumes in the bar and eventually will be replaced by mechanical power F qv The bar will operate as a motor as its power changes from electrical form to mechanical form A dc motor operates in an analogous fashion as it is loaded which means as the load enters the shaft the internal voltage will decrease and the current flow will increase and the motor starts to slow down As a result of increased current the induced torque will increase The induced torque will equal the load torque of the motor at a lower speed The converted power from electrical form to mechanical form for a real rotating motor can be determined by Poonv Tina eq 14 From equation 14 induced torque is the rotational analogue form of Fina induced force and the w angular velocity is the rotational analogue of the linear velocity v To summarize the behaviour of a linear machine e attached in opposite direction of motion which triggers the Fnetto be in opposite direction of motion e The shaft will slow down due to a negative acceleration by Fret 15 15 induced voltage will decrease through eina v Bland according to that current will increase by i Vg eina 1 R The induced force will increase by since at a lower speed Fing Fioaal e Ultimately which is the electrical power will convert to mechanical and through that the mac
28. and five locking bars at above flop or gridiron gt locked free link tail Figure 15 Saxby Gridiron locking Calvert 2008 In this method of locking the locking bar was motivated to move by means of a pin and one gridiron s driver Moreover a gridiron was either driven freely to rotate or to be prohibited from any movement by locking dogs which were located on the locking bars Figure 15 clearly indicates both locked and free gridirons The catch of a locked gridiron cannot be released This locking mechanism was fully approved and accepted in France However in Britain and America the provided model was changed by inserting tappet locking around The MRes Thesis Mersedeh Maksabi October 2013 14 Literature Review MRes In Railway System Integration gridiron interlocking has been known as an adequate interlocking Besides there is no need for having a lever to exert force This is made in a smaller size and lighter weight compared to lever locking Moreover this locking was located on the operating level behind the levers whilst the lever locking interlocking which is heavier has to be located under the operating floor The general logic behind the gridiron locking is almost the same as the suggested locking frame by John Imray In Imray s Locking frame rotating cylinders get blocked by located locking dogs on locking bars Ultimately the locking mechanism before lever movement is known as preliminary locking
29. same as the Saxby machine but the tappet locking was organized to locate vertically and the links were placed under the lever The inventor of this idea was J A Bonnell In 1865 Michael Lane who was a railway engineer and worked on the Great Western Railway devised a new frame In his frame a rack was attached on the lever and a MRes Thesis Mersedeh Maksabi October 2013 7 Literature Review MRes In Railway System Integration pinion was driven by the means of that rack and the rotation of the shaft was from left to right Although the provided frame by Lane was a fairly safe locking it was unable to produce early and last motion within the lever Consequently if two unlocked and contradictory levers were applied the result was a jammed frame In 1860 the Great Western Railway s locking machine was installed at the junction of Paddington GWR 2013 In 1863 T Blackall devised a frame which was made in Reading and was applied to the departure part of Paddington station In 1885 all the Great Western Railway s signal machinery was made in Reading with the efforts of T Blackall In 1872 Tom Gooderson invented a single twist frame which supplied a quick first motion and improved Lane s machine Both first and last motions were introduced by double twist machines which were improved by Great Western Railway The improved twist frame a twisted bar was rotated corresponding to the lever s motion and locking was driven by the rotation of a tw
30. the intended PIC was more than that of in transistor The MRes Thesis Mersedeh Maksabi October 2013 58 Conclusion MRes In Railway System Integration general study on the other electrical components introduced operational amplifier as an alternative solution The adopted amplifier module LM 741 is connected in non inverting manner to the output of the PIC in order to provide enough amount of current for activating the corresponding relay module for each motor The motor s winding will then activated for a short period of time and provide linear motion due to the bar movement 7 3 Review of Approach The overall objective of this project was to understand the control logic and effectively analyse the working mechanism of the interlocking lever frame and design a virtual simulation based signalling control system which is operated in parallel with the behaviour of each lever and all existing restrictions within the interlocking This work utilises 6 magnetic sensors which are placed underneath each lever to extract data about state of each lever Accordingly this project has greatly benefited from an electronic circuit which has been applied to read the status of each lever in binary format The proposed circuit was designed using a high performance PIC microcontroller The intended microcontroller analyses the oncoming data from the mechanical unit interlocking and generates the corresponding output through the status of each lever in th
31. the upper or lower 4 bits of a port These pins are made into inputs ifdef BITS 8 bit mode use whole port DATA PORT 0 TRIS_DATA_PORT 0x00 else 4 bit mode ifdef UPPER Upper 4 bits of the port DATA PORT amp OxOf TRIS DATA PORT amp OxOF else Lower 4 bits of the port DATA_PORT amp Oxf0 TRIS DATA PORT amp OxFO0 endif endif TRIS RW 0 All control signals made outputs TRIS RS 0 TRIS E 0 RW PIN 0 R W pin made low RS_PIN 0 Register select pin made low E_PIN 0 Clock pin made low Delay for 15ms to allow for LCD Power on reset DelayPORXLCD MRes Thesis Mersedeh Maksabi October 2013 88 Appendix A MRes In Railway System Integration WriteCmdXLCD 0x30 Delay 1OKTCYx 0x05 WriteCmdXLCD 0x30 Delay 1 OKTCYx 0x01 WriteCmdXLCD 0x32 while Set data interface width lines font while BusyXLCD Wait if LCD busy WriteCmdXLCD Icdtype Function set cmd Turn the display on then off while BusyXLCD Wait if LCD busy WriteCmdXLCD DOFF amp CURSOR_OFF amp BLINK_OFF Display OFF Blink OFF while BusyXLCD Wait if LCD busy WriteCmdXLCD DON amp CURSOR_ON amp BLINK_ON Display ON Blink ON Clear display while BusyXLCD Wait if LCD busy WriteCmdXLCD 0x01 Clear display Set entry mode inc no shift while BusyXLCD Wait if LCD busy WriteCmdXLCD SHIFT CUR LEFT Entry Mode
32. 0 or V 120 Maximum output cumant sunk by any VO 22 22 42 2422 2220 204110148860 9 Maximum output current sourced by any H1 Maximum current sunk by PORTA PORTB and PORTE Note 3 combined H Maximum current sourced by PORTA PORTB and PORTE Note 3 combined 200 mA Maximum current sunk by PORTC and PORTD Note 3 2 2 0 0 Maximum current sourced by and PORTD Note 3 combined 00 mA MRes Thesis Mersedeh Maksabi October 2013 104 Appendix B MRes In Railway System Integration Block diagram EN MRes Thesis Mersedeh Maksabi October 2013 105 Appendix B MRes In Railway System Integration e LM741 Pin connection Top view OFFSET HOLL AVERTING HiH FINERTHZ OUTFUT KAT MULL Absolute maximum rating T oe 7 a Pas ae mm m _ vi Ra iy awe xe ze Electrical characteristics MRes Thesis Mersedeh Maksabi October 2013 106 Appendix B MRes In Railway System Integration e Reed Relay SIL05 1A72 71D SIL Series MEDER electronic
33. 2_pressed void if PORTDbits RD1 0 delay_ms 10 if PORTDbits RD1 0 return 1 return 0 return 0 if the switch is not pressed MRes Thesis Mersedeh Maksabi October 2013 79 Appendix A MRes In Railway System Integration this routine is to examine that switch 3 is pressed or not No input err If sw2 is pressed gt output 1 if not output 0 TOI o o k k k kk k k k k unsigned char is_sw3_pressed void if PORTDbits RD2 0 delay_ms 10 if PORTDbits RD2 0 return 0 returnO if the switch is not pressed FR E SES sese oe oe oe k k k k k Per This routine is to examine that switch 4 is pressed or not fpe No input uy If sw2 is pressed gt output 1 if not output 0 EE E ER SR SESS osse o oe o k k k kk k k kk k k k kk unsigned char is_sw4_pressed void if PORTDbits RD3 0 delay_ms 10 if PORTDbits RD3 0 return 1 return 0 return 0 if the switch is not pressed MRes Thesis Mersedeh Maksabi October 2013 80 Appendix A MRes In Railway System Integration k k kk k kkk k k k kk peor this routine is to examine that switch 5 is pressed or not Lae No input err If sw2 is pressed gt output 1 if not o
34. 44780 LCD controller The user must check to see if the LCD controller is 2 busy before calling this routine The data 2 i is written to the character generator RAM or lt the display data RAM depending what the previous SetxxRamAddr routine was called void WriteDataXLCD char data ifdef BIT8 8 bit interface TRIS DATA PORT 0 Make port output DATA PORT data Write data to port RS 1 Set control bits RW PIN 0 DelayFor18TCYY E_PIN 1 Clock data into LCD DelayFor18TCY E PIN 0 RS 0 Reset control bits TRIS DATA PORT Oxff Make port input else 4 bit interface ifdef UPPER Upper nibble interface TRIS DATA PORT amp OxOf DATA PORT amp OxOf DATA PORT l data amp Oxf0 else Lower nibble interface TRIS_DATA_PORT amp Oxf0 DATA_PORT amp Oxf0 DATA PORT l data gt gt 4 amp 0x0Of endif RS_PIN 1 Set control bits RW PIN 0 DelayFor18TCY E_PIN 1 Clock nibble into LCD DelayFor18TCYY E PIN 0 ifdef UPPER Upper nibble interface DATA PORT amp OxOf DATA PORT l data lt lt 4 amp 0xf0 else Lower nibble interface MRes Thesis Mersedeh Maksabi October 2013 102 Appendix B MRes In Railway System Integration DATA PORT amp 0 DATA PORT l data amp 0x0f endif DelayFor18TCY
35. Appendix A e Codes and comments MINT Author M Maksabi Function pulse generating Device PIC 18F2550 MITT include lt p18f2550 h gt include lt timers h gt errr ees onfi guration Drs ak ey pragma config FOSC XT XT Crystal oscillator pragma config PWRT OFF Power up timer disabled pragma config BOR OFF Brown out reset disabled pragma config LVP OFF Low voltage programming disabled pragma config WDT OFF Watch dog timer disabled pragma config DEBUG OFF Background debugger disabled Cog pragma code define ON 0 define OFF 1 define left 1 define right 2 define OutputLeft PORTBbits RB7 output pin define OutputRight PORTBbits RB6 output pin void direction int dir if check the current direction RB gets logic 1 Delay 1KTCYx 50 for 50 milliseconds OutputLeft OFF returns back to logic 0 else MRes Thesis Mersedeh Maksabi October 2013 65 Appendix A MRes In Railway System Integration OutputRight ON RB6 gets logic 1 Delay 1KTCYx 50 for 50 milliseconds OutputRight OFF returns back to logic 0 void main void TRISB 0 II PORTE the output port while 1 direction left Delay lOKTCYx 200 Delay10K TCYx 200 direction right Delay10
36. Eo beeen MEN d _ pese 17 e 5 Figure 21 Truth table for lever frame working mechanism 3 3 Logical Simulation of the Normal Route For further understanding and to show how a 2 aspects signalling with mechanical interlocking operates the behaviour of each lever due to the state Lock Unlock of other levers has been examined Figure 22 shows the first simulation model for the straight route using three levers Figure 22 Simulation model for the straight route MRes Thesis Mersedeh Maksabi October 2013 21 Visualisation of Interlocking Systems through MRes In Railway System Integration LabVIEW The model has 3 inputs due to associated levers and eight possible outputs In the design levers are designed as push button so two states of each push button 0 and 1 model the functionality of each lever ON and OFF 0 and 1 The outputs of the system show each lever s moving ability Hence based on three inputs and two states eight conditions have been tesed on the first three levers in which 6 states out of 8 are experimentaly acheivable however not all of them are logically safe Ini if In12 20 amp amp In2 0 amp amp In3 0 In 1 Outlz2 Out2 0 Out3 0 uH s75 Lm Inlzz0 amp amp In2 0 amp amp In3 1 In 2 Outl 22 Out2z0 Out3 0 PDisabled pum CA 71 0 In3 0 In3 Ou
37. K TCYx 200 Delay10KTCYx 200 MRes Thesis Mersedeh Maksabi October 2013 66 Appendix A MRes In Railway System Integration HII Author M Maksabi MMT Levers mechanism due to the straight route HII Device PIC 18F452 include lt p18f452 h gt Configuration pragma config PWRT pragma config BOR OFF pragma config LVP OFF pragma config WDT OFF Power up timer disabled Brown out reset disabled Low voltage disabled Watch dog timer disabled pragma config DEBUG OFF Background debugger disabled Fee A HE modes and Definitions pragma code define LeverlLowerLimit PORTBbits RBO input define Leverl UpperLimit PORTBbits RB1 define Leverl1GoUp PORTBbits RB2 define Lever GoDown PORTBbits RB3 define LeverlIsUp PORTBbits RB4 output define LeverlIsDown PORTBbits RB5 output define Lever2LowerLimit PORTBbits RB6 input define Lever2UpperLimit PORTBbits RB7 define Lever2GoUp PORTCbits RCO define Lever2GoDown PORTCbits RC1 hnput define Lever2IsUp PORTCbits RC2 output define Lever2IsDown PORTCbits RC3 output define Lever3LowerLimit PORTCbits RC4 input define Lever3UpperLimit PORTCbits RC5 input define Lever3GoUp PORTCbits RC6 hnput define Lever3GoDown PORTCbits RC7 linput define Lever3IsUp POR
38. MRes in Railway Systems Engineering and Integration College of Engineering School of Civil Engineering University of Birmingham AD ARDUA ALTA Integration of a Mechanical Interlocking Lever Frame into a Signalling Demonstrator By Mersedeh Maksabi Supervisor Prof Felix Schmid DATE SUBMITTED 2013 10 30 UNIVERSITYOF BIRMINGHAM University of Birmingham Research Archive e theses repository This unpublished thesis dissertation is copyright of the author and or third parties The intellectual property rights of the author or third parties in respect of this work are as defined by The Copyright Designs and Patents Act 1988 or as modified by any successor legislation Any use made of information contained in this thesis dissertation must be in accordance with that legislation and must be properly acknowledged Further distribution or reproduction in any format is prohibited without the permission of the copyright holder Preliminaries Executive Summary Railway signalling has experienced numerous changes and developments most of which were associated with its long evolutionary history These changes have occurred gradually from the earliest days of the railway industry when fairly safe distances between the trains were controlled by signalmen with their rudimentary tools to multiple aspects colour light signalling systems and complicated operating systems as well as computerised traffic information syste
39. October 2013 50 Experimental Setup and Practical Results MRes In Railway System Integration 6 2 4 Switch Bounce and Filter Circuit The switches are connected to the input pins of the microcontroller As the switch locates in a close proximity to the magnet the internal contacts will activate Hence there is a finite amount of time up to 20 mS due to microcontroller oscillation which is called switch bounce 5 VDC Pull up resistor 10K Input pin Magnetic contact PIC18F452 ground Figure 61 Pull up connection During this time the contacts will operate very fast and generate a lot of on and off transitions which introduce more than one output pulse to the system These pulses are not visible in the electrical circuit But the fast digital circuit will respond to all unwanted pulses which will cause mis operation Bounce Bounce E eee off off Figure 62 Switch bounce MRes Thesis Mersedeh Maksabi October 2013 51 Experimental Setup and Practical Results MRes In Railway System Integration To eliminate these false pulses an alternative is to use delay routine inside the microcontroller program Accordingly the status of the switch will be checked after 10 mS delay and due to that either logic 1 or logic 0 will generate as returning value to the microcontroller This routine is to examine that switch 2 is pressed or not No input If sw2 is pre
40. TDbits RDO output define Lever3IsDown PORTDbits RD1 outpu MRes Thesis Mersedeh Maksabi October 2013 67 Appendix A MRes In Railway System Integration The code works as next if Lever2UpperLimit 1 and Lever3UpperLimit 1 that is lever2 and lever3 are lifted then lever 1 can be lifted More over if upper limit is reached Go up button is invalid and vice versa xi void main TRISB 0xCF TRISC 0xF3 TRISD 0xFC PORTB PORTC PORTD 0 reset all the ports while 1 if Leve else MRes Thesis r2UpperLimit amp amp Lever3UpperLimit if Leverl UpperLimit Leverl GoUp Lever lIsUp 1 Lever 1IsDown 0 else Lever 1IsUp 0 if Leverl LowerLimit amp amp Leverl GoDown Lever 1IsUp 0 Lever 1IsDown 1 else LeverlIsDown 0 Mersedeh Maksabi October 2013 68 Appendix A MRes In Railway System Integration Lever 1IsUp Lever 1IsDown 0 if Lever3UpperLimit amp amp Lever3GoUp Lever3IsUp 1 Lever3IsDown 0 else Lever3IsUp 0 if Lever3LowerLimit amp amp Lever3GoDown Lever3IsUp 0 Lever3IsDown 1 else Lever3IsDown 0 if Lever2UpperLimit amp amp Lever2GoUp Lever2IsUp 1 Lever2IsDown 0 else Lever2IsUp 0 if Lever2LowerLimit amp amp Lever2GoDown Lever2IsUp 0 Lever2IsDown 1 else Lever2IsDown 0 MRes Thesis Mersedeh Maksabi October 2013 69 Appendix A MRes In Railway System Integration
41. Up Lever2IsUp 1 else Lever2IsUp 0 if Lever5UpperLimit amp amp Lever4LowerLimit if Lever6UpperLimit amp amp Lever6GoUp Lever6IsUp 1 Lever6IsDown 0 else Lever6IsUp 0 if Lever6LowerLimit amp amp Lever6GoDown Lever6IsUp 0 Lever6IsDown 1 MRes Thesis Mersedeh Maksabi October 2013 83 Appendix A MRes In Railway System Integration else Lever6IsDown 0 else if 5 amp amp Lever5GoUp 5150 1 else LeverSIsUp 0 Lever6IsUp Lever6IsDown 0 if LeverSUpperLimit amp amp Lever6LowerLimit if Lever4UpperLimit amp amp Lever4GoUp Lever4IsUp 1 Lever4IsDown 0 else Lever4IsUp 0 if Lever4LowerLimit amp amp Lever4GoDown Lever4IsUp 0 Lever4IsDown 1 else Lever4IsDown 0 else Lever4IsUp Lever4IsDown 0 MRes Thesis Mersedeh Maksabi October 2013 84 Appendix A MRes In Railway System Integration I I Ill Author Mersedeh Maksabi Ill Name LCD CODE lll Ill Date 24 08 2013 at 20 12 lll VII MT T T include lt p18f452 h gt include lt delays h gt include lt xlcd h gt ifdef UPPER undef UPPER endif ifdef BIT8 undef BIT8 endif void main const char arr 16 route is clear 0 OpenXLCD FOUR_BIT amp LINES 5X7 putrsXLCD arr while 1 void DelayPORXLCD Delay100TCYx 250 delay for 2 5 ms on 40 MHz Delay100TCYx 250 D
42. ally closed relays obeys the same principles for activation however they exhibit an opposite operation due to their different switch architecture 5 5 2 Operational Amplifier Operational amplifiers are essential components in analogue electronic circuits with the ability of amplifying analogue signals An op amp is usually formed by three terminals which are two high impedance inputs inverting and non inverting inputs and an output which is able to sink voltage or current However the majority of the circuits require op amp for voltage amplification Figure 45 Op amp Symbol MRes Thesis Mersedeh Maksabi October 2013 41 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor An ideal op amp has particular characteristics as follows e Infinite open loop gain e Infinite input resistance e Zero output resistance Bandwidth from 0 to oo e Zero offset As is obvious from figure 46 the operational amplifier is connected in such a manner to provide negative feedback Negative feedback is defined as a process in which part of the output voltage will be return back to the input with a phase angle that opposes the input signal Accordingly the output is not driven into saturation and more realistic gain is achievable Internal inversion makes V 180 out of phase with Vin Figure 46 Negative feedback network The applied IC package for this project is LM741 which is a single device w
43. ary 44 Figure 50 Negative voltage square pulse from the microcontroller 44 Figure 51 Detected pulse from output 45 Figure 525 Experimental Setup aces Oates 45 Figure 53 Illustration of PNP transistor toe er ei e a 46 Figure 54 Collected result from PNP transistor nud ri rite eos 47 Figure 55 Collected result from microcontroller esee 47 Figure 56 Demonstration of finial aided ee 48 Mersedeh Maksabi October 2013 Vili Preliminaries Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Magnetic actuator block diagram seen 48 Magnetic sensor block diagram eee teorie eat 49 Reed switch sesitivity eene eene enne nnne 49 The layout of the Cir Cult a oo ee LO RE RAE ase euet eii aaa 50 Pull up cormecton 1 2 tar alin eee 51 SWiteh eee lane edu Rede 51 Delay routine a es 52 EE 52 Two aspects of signalling fisrt
44. bble DelayFor18TCY E PIN 20 RW PIN 0 Reset control line return 1 Return TRUE else Busy bit is low E 0 Reset clock line MRes Thesis Mersedeh Maksabi October 2013 86 Appendix A MRes In Railway System Integration DelayFor18TCY E 1 Clock out other nibble DelayFor18TCY E PIN 20 RW PIN 0 Reset control line return 0 Return FALSE endif MRes Thesis Mersedeh Maksabi October 2013 87 Appendix A MRes In Railway System Integration include lt p18f452 h gt include delays h include xlcd h 78 7 7 3 k k k k k k kk Function Name OpenXLCD T Return Value void Parameters lcdtype sets the type of LCD lines Description This routine configures the LCD Based on the Hitachi HD44780 LCD controller The routine will configure the I O pins of the microcontroller setup the LCD for 4 or 8 bit mode and clear the display The user must provide three delay routines DelayFor18TCY provides a 18 Tcy delay DelayPORXLCD provides at least 15ms delay DelayXLCDQ provides at least 5ms delay k k k void OpenXLCD unsigned char Icdtype X X 0X X X X X X X X X OK ye The data bits must be either 8 bit port or
45. bey the same principles and exhibit the same behaviour as real generators and motors Figure 35 illustrates a linear machine As is obvious a battery and resistance are connected with a switch to a pair of frictionless rails Magnetic field into page Figure 35 Linear machine Chapman 1999 The railroad track along the bed is constant as the magnetic field goes into the page of the bar which is made by a conducting metal laid across the tracks The working mechanism of this device can be described through the use of the four following fundamental equations Chapman 1999 e Calculation of force on the wire according to produced magnetic field i x B eq 1 Where F force on wire i magnitude of current in wire I length of wire direction of I defined to be in the direction of current flow B magnetic flux density vector e The induced voltage on a wire in the presence of magnetic field vX B 1 2 Where v velocity of the wire MRes Thesis Mersedeh Maksabi October 2013 32 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor B magnetic flux density vector I length Calculation of Kirchhoff s voltage law for figure 35 Vs iR eima 0 eq 3 Vg eina 0 e Newton s law for the bar across the tracks Fret ma eq 4 Where vector sum of forces m object mass a acceleration vector a of subject 5 1 1 Working Mechanism
46. cd h 78 7 7 2 2 k kk k k k k k Function Name ReadDataXLCD Return Value char data byte from LCD controller Parameters void Description This routine reads data byte from the Hitachi HD44780 LCD controller The user must check to see if the LCD controller is busy before calling this routine The data is read from the character generator RAM or the display data RAM depending on what the previous SetxxRamAddr routine was called j k k k k k k k k kk k k k k k kK k k K k k k K char ReadDataXLCD void x char data ifdef BIT8 8 bit interface RS_PIN 1 Set the control bits RW_PIN 1 DelayFor18TCY E PIN 1 Clock the data out of the LCD DelayFor18TCY data DATA PORT Read the data E PIN 20 RS PIN 0 Reset the control bits RW PIN 0 else 4 bit interface RW_PIN 1 RS_PIN 1 DelayFor18TCY E PIN 1 Clock the data out of the LCD DelayFor18TCY ifdef UPPER Upper nibble interface data DATA PORT amp OxfO Read the upper nibble of data else Lower nibble interface data DATA_PORT lt lt 4 amp 0Oxf0 4 the upper nibble of data endif E_PIN 0 Reset the clock line DelayFor18TCYY E PIN 1 Clock the next nibble out of the LCD DelayFor18TCY ifdef UPPER Upper nibbl
47. ch is connected to interlocking components Railway Interlocking Physical Railway Figure 3 Railway interlocking and main communication line MRes Thesis Mersedeh Maksabi October 2013 5 Literature Review MRes In Railway System Integration 2 2 History of Interlocking At the beginning of the railway industry signalmen were in charge of operating signals by pressing down the stirrups with their foot The stirrups were arranged at Bricklayer s Arms junction by Charles Hutton Gregory in 1843 As one stirrup was pressed it interfered with other stirrups hence there was not any contradictory signal and the installed points on the ground were operated separately from the signals In 1856 for the first time both points and signals levers were arranged to install in a row by means of spring catch The invented frame by Saxby was installed at Keyham Junction in Brighton Although it was the first interlocking which connected both signals and points in terms of the operation principles it was completely different from a modern interlocking Accordingly as a point lever was pulled for a specific route at the same time the corresponding signals were operated On the other hand in modern interlocking signals will operate once the operation of points is completed A great improvement of Saxby s machine which was installed at Keyham and moved both signals and points at the same time appeared in 1860 According to this new technology th
48. ch was based on that the catch rod motivates the rocker or link to move As the lever is in the normal state the depressed catch handle drives rear end of the link up and eventually supplies half of the first motion Both lever and link slot have the same centre of curvature Therefore as lever moves from normal to reverse state the link remains in static mode The second and final half of the MRes Thesis Mersedeh Maksabi October 2013 13 Literature Review MRes In Railway System Integration first motion occurs as the front part of the link becomes more depressed through the downward motion of the catch rod and the released catch handle caon nanda rocz Figure 14 Saxby and Farmer Rocker Calvert 2008 Based on the above two general ideas are identified e Locking levers through locking their catches e Motion of catch rod which drives interlocking The inventor of the first idea was Easterbrook whilst the locking operation by the catch rod was suggested by Saxby 2 3 11 Saxby Gridiron Locking The gridiron interlocking was an initial catch locking machine without tappet interlocking With the help of cranks the provided locking machine moves the links by the catch handle rods known as gridirons flops As all levers enter in a normal state the gridirons will be horizontal In figure 15 upward view of the locking machine only the upper locking bar is illustrated which shows five slots gridiron with five locking bars at below
49. cted to this pin PortC as output LED2 is connected to this pin PortC as output LED3 is connected to this pin Set wise LEDI Set wise LED2 Set wise LED3 LED 4 wise LED4 Mersedeh Maksabi October 2013 74 Appendix A MRes In Railway System Integration TRISBbits TRISB6 0 LEDS TRISBbits TRISB7 0 wise LEDS TRISEbits TRISEO 0 LED6 TRISEbits TRISE1 0 wise LED6 TRISCbits TRISC6 0 MOTOR output Left TRISCbits TRISC7 0 MOTOR 1 output Right TRISDbits TRISD4 0 MOTOR2 output Left TRISDbits TRISD520 MOTOR2 output Right PORTCbits RCO 0 turn off LED1 PORTCbits RC 1 0 turn off LED2 PORTCbits RC2 0 turn off LED3 PORTCbits RC3 0 WISE LEDI PORTCbits RC4 0 WISE LED2 PORTCbits RC5 0 WISE LED3 PORTAbits RAO 0 turn off LED4 PORTBbits RB5 0 turn off wise LED4 PORTBbits RB6 0 turn off LEDS PORTBbits RB7 0 turn off wise LED5 PORTEbits REO 0 turn off LED6 PORTEbits RE1 0 turn off wise LED5 PORTCbits RC6 1 winding 1 for motor is on PORTCbits RC7 1 winding 2 for motor is on PORTDbits RD4 1 the winding 1 for motor2 is on PORTDbits RD5 1 the winding 2 for motor2 is on TRISDbits TRISDO 1 set SWITCHI pin as input TRISDbits TRISDI 1 set SWITCH2 pin as input TRISDbits TRISD2 1 set SWITCHG pin as input TRISDbits TRISD3z1 set SWITCH4 pin as input TRISDbits TRISD6z1 set SWITCHS pin as input MRes Thesis Me
50. d by the means of an internal network on the control centre part which is based on information corresponding to each signalling area that will be exchanged in a secure manner In line side subsystem a fail safe LAN has been formed by the lineside data cable and TFMs This effectively drives signals points and other signalling equipment according to command MRes Thesis Mersedeh Maksabi October 2013 15 Literature Review MRes In Railway System Integration telegrams generated by interlocking and transfers back to the interlocking information from track circuits points and other equipment Waller 1991 Figure 16 illustrates the schematic form of SSI system as well as communication line between subsystems PANEL MULTIPLEX CONTROL CENTRE TECHNICIAN S TO TRAIN TERMINAL _ DESCRIBER Etc Mae ee Mae own DIRECT CONNEC TIONS TO SIGNALS POINTS TRACK CIRCUITS Etc Figure 16 SSI System Waller 1991 2 4 3 The Interlocking Cubicle Figure 17 shows a common SSI installation The important equipment of interlocking is accommodated in a cubicle with a 19 inch size MRes Thesis Mersedeh Maksabi October 2013 16 Literature Review MRes In Railway System Integration TRACKSIDE LOCATION DIRECT CONNECTIONS TO POINT SIGNALS TRACK CIRCUITS TRACKSIDE DATA LINKS OF INTERLOCKING B Figure 17 Entire Installation of SSISystem Wall
51. d on their polarity The reed switches are connected to a microcontroller Each individual lever status reverse normal will be sent to that microcontroller PIC as a system input Consequently due to the activation of the levers the corresponding electrical signal outputs will be generated from the PIC which have sufficient amount of current to activate the related LED A track layout with two switch points is designed and fixed on a wooden board which has two holes at the switches location The directions of the switches are controlled by two AC motors which are connected to the switches and are energised by the PIC and reed relays for a short period of time 1 4 Methodology According to the scope of the project several phases are covered The objective of this project is to obtain information from the interlocking lever frame in order to illustrate two aspects of signalling To determine the scope of the research methodology the main issues are as follows e Comprehensive literature review about railway signalling e Visualisation of the interlocking system through Lab VIEW e Signalling based simulation on the control logic of interlocking and behaviour of every single lever e Investigating appropriate solutions for real time data acquisition e Demonstrating two aspects of signalling due to the obtained data through an electronic circuit The following block diagram illustrates the procedure in its entirety MRes Thesis Mersede
52. e locking bar at the top of the frame is driven with the movement of each lever The essential levers are locked in the upper jog so the middle part the locking bar is static Whereas in the lower jog the essential levers are free to move which introduces early and late motion within the levers frame The Saxby and Farmer Hook Interlocking were installed at the new Victoria Station London This machine was the first interlocking machine imported into United State and installed at Trenton in 1870 In 1874 a rocker type with gridiron locking machine was used for East Newark for the first time Figure 4 Old Interlocking Lawrence 2011 MRes Thesis Mersedeh Maksabi October 2013 6 Literature Review MRes In Railway System Integration In 1859 the points and signals operated independently one after the other It was the first modern sense of interlocking introduced by Steven and Sons in collaboration with Austin Chambers Based on the provided interlocking machine signal stirrups get into the holes with the usage of rods and move by the means of point levers Therefore signals were only cleared as the rod gets into all the plates In 1880 the invented machine by Steven and Sons earned good reputation as it was simple and easy to maintain Calvert 2008 Chambers idea was improved by Pierre Auguste Vignier who was the inventor of the interlocking between points and signals for four junctions The devised machine by Vignier was simi
53. e form of electrical signals The generated signal from PIC has enough current to turn on a LED as the maximum sunk current from each output pin of the PIC is 25 mA and the required operating current for the intended LED is 15 mA Apart from that a track layout with two switches has been designed The direction of each switch is governed by two motors Subsequently as each motor energises for a short period of time a quick linear motion will be created due to each accomplished winding As the system starts to run the motor will be activated twice for a short period of time at the same time Once when the distant signal is cleared and the other time when the shunting signal is cleared and the corresponding signal to point which is controlled by lever 5 will indicate that proceeding in shunt neck is hazard free Ultimately the designed circuit and the provided electromechanical modelling approach can effectively show the working mechanism and control logic of the entire system through 2 aspects of railway signalling which can be used as a new training electronic based tool for students who are willing to know about railway signalling operating systems 7 4 Areas for Further Work The next stage for this project is to extend the adopted approach to a new microprocessor based electronic circuit The proposed circuits will be formed by two processor units and one comparator unit which determines a fail safe comparison of the output signals of two
54. e interface data l DATA PORT 24 amp 0x0f Read the lower nibble of data else Lower nibble interface data I DATA_PORT amp OxOf Read the lower nibble of data MRes Thesis Mersedeh Maksabi October 2013 94 Appendix A MRes In Railway System Integration endif E PIN 0 RS 0 Reset the control bits RW PIN 0 endif return data Return the data byte MRes Thesis Mersedeh Maksabi October 2013 95 Appendix A MRes In Railway System Integration include lt p18F452 h gt include xlcd h k k Function Name SetCGRamAddr Return Value void P Parameters CGaddr character generator ram address Description This routine sets the character generator T address of the Hitachi HD44780 LCD controller The user must check to see if the LCD controller is busy before calling this routine k k k k k k k kk k kkk k k kk k kk k kk k k kK k k k void SetCGRamAddr unsigned char CGaddr ifdef BITS 8 bit interface TRIS DATA PORT 0 Make data port ouput DATA_PORT CGaddr 0b01000000 Write cmd and address to port RW PIN 0 Set control signals RS_PIN 0 DelayFor18TCY E_PIN 1 Clock cmd and address in DelayFor18TCY E PIN 206 D
55. e system has 12 inputs and 6 outputs for every lever 4 inputs and 2 outputs have been assigned For example lever 1 has 4 inputs which are LeverlUpperLimit LeverlLowerLimit and LeverlGoDown The outputs are LeverlIsUp and LeverlIsDown which shows the reversed and normal states through two aspects signalling Lever 2 input pins OSCI CLKI RCO TIOSO TICKI MCLRIVPP RCI TIOSU CCP2A CRYSTAL Rcoccp 17 OU Verre output pins PROPERTY VALUE RAD ANO RC3 SCK SCL m RAT ANI RC4 SDUSDA RAQ AN2 VREF RC5S SDO RAG ANS VREF RCG TXICK _ RC7 RX DT RAS AN4 SS LVDIN RAB OSC2 CLKO RDO PSPO 3 RD1 PSP1 Lever 1 input pins RDA PSPA i Lever 3 output pins RD5 PSP5 RD6 PSP6 RD7 PSP7 Lever 2 input pins REO RDIANS RE1ANR ANG RE2 CSIAN PIC18F452 PROPERTY VALUE Figure 27 Demonstration of preliminary setup The outputs are controlled by GoUp and GoDown SPDT switches To simulate each lever 4 switches SW SPDT have been intended through Proteus software and they create 3 input chains corresponding to 3 levers The outputs are the LEDs The blue LED will come up as each lever GoUp switch is activated and the green one will be blinking as the GoDown switches are activated Poe EGER SARAS 4 5522254 5 LEVER UPPERLIMIT LEVERZUPPERLIMIT jun pws SPOT t mE LEVERSGOUP LEVERTISUP LEVER iBVERZISUP LEVERSISUP
56. e to safety reasons preventing accidents and providing collision free operation the platform needs to be clear Hence lever 3 has to get unlocked to make the station started signal to green Ultimately lever 1 has to get reversed which makes the distant signal turn double yellow This is the normal and safe approach of setting the route for trains to pass from departure A to destination B DOWN SHUNTING NECK Figure 19 Straight route set from A to 3 2 Testing over Reverse Route set from C to D Figure 20 presents a track layout with an interlock and flank locked in the routes that are set in a reverse direction In order to protect the route and control the oncoming trains from the forward direction both the distant signal and the home signal have to be red Moreover the station started signal has to be green to clear the route for the train coming from point C The shunt points 5 are flank locked reverse main line and normal sidings and then the shunting signal will set to green which allows the train to reach destination D T mmu SHUNTING NECK 1 Figure 20 Reverse route set from C to D MRes Thesis Mersedeh Maksabi October 2013 20 Visualisation of Interlocking Systems through MRes In Railway System Integration LabVIEW Figure 21 explains the working mechanism of mechanical interlocking lever frame 2 Distant ee Home Down TE
57. edeh Maksabi October 2013 77 Appendix A MRes In Railway System Integration PORTEbits RE1 1 j SS Sos sese oe oe oe k k k k k k k k k k k k k k k k k k k k kkk delay routine EEE FEX Delay in miliseconds is required pret No Output KEE SE Sos sese oe oe ok ok ok o k k k k k k k k k k kk k k kK 2 void delay_ms unsigned int duration delay in miliseconds for 4 0MHZ crystal unsigned int 1 for duration 0 duration forG 0 1 lt 50 i _asm nop nop nop endasm _asm nop nop endasm MRes Thesis Mersedeh Maksabi October 2013 78 Appendix A MRes In Railway System Integration EE E se sese se o k k k k k k k k k k k k k kk k kkk k k k k 2 2s eee This routine is to examine that switch 2 is pressed or not fone No input If sw2 is pressed gt output 1 if not output 0 Te unsigned char is_sw1_pressed void if PORTDbits RDO 0 delay_ms 10 if PORTDbits RDO 0 return 1 return 0 return 0 if the switch is not pressed k k k k k k k k k kk k K This routine is to examine that switch 2 is pressed not Tow bere No input FE ee If sw2 is pressed gt output 1 if not output 0 TOME unsigned char is_sw
58. elay100TCYx 250 Delay100TCYx 250 Delay100TCYx 250 Delay100TCYx 250 Delay100TCYx 250 delay for 2 5 ms on 40 MHz Delay100TCYx 250 Delay100TCYx 250 Delay100TCYx 250 Delay100TCYx 250 Delay100TCYx 250 j void DelayFor18TCY Delay100TCYx 250 MRes Thesis Mersedeh Maksabi October 2013 85 Appendix A MRes In Railway System Integration include lt p18f452 h gt include xlcd h Function Name BusyXLCD Return Value char busy status of LCD controller Parameters void xi Description This routine reads the busy status of the Hitachi HD44780 LCD controller d 2 28 k k unsigned char BusyXLCD void RW_PIN 1 Set the control bits for read RS_PIN 0 DelayFor18TCY E PIN 1 Clock in the command DelayFor18TCYY ifdef BIT8 8 bit interface if DATA_PORT amp 0x80 Read bit 7 busy bit If high E_PIN 0 Reset clock line RW PIN 0 Reset control line return 1 Return TRUE else Bit 7 low E_PIN 0 Reset clock line RW PIN 0 Reset control line return 0 Return FALSE else 4 bit interface ifdef UPPER Upper nibble interface if DATA_PORT amp 0x80 else Lower nibble interface if DATA_PORT amp 0x08 endif PIN 20 Reset clock line DelayFor18TCY E_PIN 1 Clock out other ni
59. elayFor18TCY TRIS DATA PORT Oxff Make data port inputs else 4 bit interface ifdef UPPER Upper nibble interface TRIS DATA PORT amp OxOf Make nibble input DATA PORT amp OxOf and write upper nibble DATA PORT l CGaddr 0501000000 0 10 else Lower nibble interface TRIS_DATA_PORT amp Oxf0 Make nibble input DATA_PORT amp Oxf0 and write upper nibble DATA PORT l CGaddr 0 01000000 gt gt 4 amp OxOf endif MRes Thesis Mersedeh Maksabi October 2013 96 Appendix A MRes In Railway System Integration RW PIN 0 Set control signals RS_PIN 0 DelayFor18TCY E_PIN 1 Clock cmd and address in DelayFor18TCY E PIN 0 ifdef UPPER Upper nibble interface DATA PORT amp 0 0 Write lower nibble DATA PORT l CGaddr 4 amp Oxf0 else Lower nibble interface DATA_PORT amp Oxf0 Write lower nibble DATA PORT CGaddr amp 0x0f endif DelayFor18TCY 1 Clock cmd and address in DelayFor18TCY E PIN 0 ifdef UPPER Upper nibble interface TRIS DATA PORT Oxf0 Make inputs else Lower nibble interface TRIS DATA PORT I OxOf Make inputs endif endif return include lt p18F452 h gt include xlcd h MRes Thesis Mersedeh Maksabi October 2013 97 Appendix A MRes In Railway System Integration 78 7 7 2 E k k k k k k k k k k k k k k
60. er 1991 The size of the controlled area by each interlocking is dependent on the number of trackside equipment To extend the areas more than one interlocking is required since each interlocking is only capable of controlling 20 to 40 sets of points and managing 40 signals in total The following are the equipment which is located in the interlocking cubicle Three interlocking multi processor modules e Two panel processor modules e The diagnostic multi processor module e Data link modules and power supplies The interlocking cubicle wiring to multi processor module includes an 8 bit binary address Each wire link is specified for one bit address and is made to either high or low voltage 1 or 0 Five bits represent the system identity and identify the individual interlocking within the control centre The remaining three bits are available to distinguish successive versions of geographical data The designed interlocking requires power at 110 VAC and the amount of power consumption for each interlocking cubicle is 375 watts approximately In addition the MRes Thesis Mersedeh Maksabi October 2013 17 CHAPTER THREE MRes In Railway System Integration hardware of the SSI system is managed by the software named by MPM which provides a safe operation and secure data transmission The MPM software is divided into programs providing initialisation redundancy management interfacing with panel processors and communications links 2 4 4
61. erning the straight route is different from that in reverse route Secure train operation will be achievable through the operation of first three levers The distant signal double yellow signal will be clear due to operation of the first lever However it is restricted by the second and third levers which control the home and platform started signal respectively But in the reverse route safe operation will be controlled through the operation of the last four levers lever 3 lever 6 lever 5 and lever 4 Signal operation due to the reverse route is separate and completely different from that of the straight route It was suggested by the author to provide an LCD unit to indicate the status of the route due to the operated signals The applied LCD unit has been programmed through MPLAB software The LCD routine will be called twice inside the code Firstly the distant signal gets clear and secondly the direction of the switches has been changed due to activation of motor 1 and motor 2 The LCD will be activated due to these two events and a message will be displayed which indicates that the route is clear The LCD code hex file has been exported from the MPLAB programming software and imported into the MRes Thesis Mersedeh Maksabi October 2013 56 Experimental Setup and Practical Results MRes In Railway System Integration corresponding library inside the simulating software Proteus ISIS Figure 74 demonstrates the simulation result thro
62. eturn Value void E Parameters buffer pointer to string Description This routine writes a string of bytes to 5 Hitachi HD44780 LCD controller The user 2 must check to see if the LCD controller is d busy before calling this routine The data is written to the character generator RAM the display data RAM depending on what the previous SetxxRamAddr routine was called T k void MRes Thesis putsXLCD char buffer while buffer Write data to LCD up to null while BusyXLCD Wait while LCD is busy WriteDataXLCD buffer Write character to LCD buffer Increment buffer return Mersedeh Maksabi October 2013 91 Appendix A MRes In Railway System Integration include lt p18F452 h gt include xlcd h Function Name ReadAddrXLCD d Return Value char address from LCD controller Parameters void Description This routine reads an address byte from the Hitachi HD44780 LCD controller The user 5 must check to see if the LCD controller is i busy before calling this routine The address T T is read from the character generator RAM or the display data RAM depending on what the 2 previous SetxxRamAddr routine was called n unsigned char ReadAddrXLCD void
63. frames as it was huge and required significant space Accordingly a Railway signal company in Liverpool found an alternative where the lever moves a cam plate that then moved the locking bars the inventor of this idea is George Edwards The early and late motions are provided by the S shaped cam slot Calvert 2008 In 1904 this method was applied on the Great Western Railway s HT and VT tappet interlocking frames GWR 2013 lever travel 8 9 to t locking bar T travel to locking bar Figure 13 Illustration of Cam Plate Calvert 2008 The general logic behind the provided method is based on locked levers as a lever gets locked small trail movement can identify that Despite all the locking has to be made very large and bulky and has to be installed underneath the operating level in a vertical manner Further electric locks are located at the end of each tappet blade 2 3 10 Saxby and Farmer Rocker It is not required to mechanically interfere with movement of lever as it is enough to avoid the catch dog to run off from the quadrant Moreover as the catch handle is released the movement of catch rod is sufficient enough to force the interlocking to work In addition the motion of catch dog which happened at the start and end of each lever movement can perfectly assure both early and late motion Earlier than any motion of the levers locking is actuated Accordingly a skilful arrangement was provided by Saxby whi
64. g Calvert 2008 sade 11 Figure 10 Junction Calvert 200805554 RR RO 11 Figure 11 Locking Sheet Calvert 2008 une eto MR 12 Figure 12 Fisrt Motion Calvert 2008 4 sdaseco psu a e ei persa 12 Figure 13 Illustration of Cam Plate Calvert 2008 eee 13 Figure 14 Saxby and Farmer Rocker Calvert 2008 sess 14 Figure 15 Saxby Gridiron locking Calvert 2008 sss 14 Figure 16 SSI System Waller 1991 RIEN 16 Figure 17 Entire Installation of SSI System Waller 1991 17 Figure 18 Track layout with signals and points 19 Figure 19 Straight route set from A TO Beau 20 Figure 20 Reverse route set from to D o Ce ed 20 Figure 21 Truth table for lever frame working mechanism 2l Figure 22 Simulation model for the straight 21 Figure 23 Control unit for the straight route ioco 22 Figure 24 Simulation model for the reverse 23 Figure 25 Control unit for the reverse route 24 Figure 26 Simulation model concerning the straight route esee 25 Figure 27 Demonstration of preliminary setup 26 Mersedeh Maksabi October 2013 Vil Preliminaries Lrgute 25 Levers dte Teversed Cd E eti LC 26 Figure 29 First shot from simulation
65. g Proteus ISIS 4 1 System Approach In order to model the working mechanism of the interlocking and to show how two aspect signalling red green is created based on the state lock unlock of each lever a set of codes have been written through MPLAB software The selected PIC microcontroller is PIC18F452 which has 40 pins and 5 ports The idea is to consider virtual locks between the levers and control the signalling based on the actual logic behind each lever s movement The code has been compiled by using C18 compiler and the provided hex file has been imported to corresponding library of the simulator to know whether the code makes sense experimentally or not Figure 26 presents the first simulation model due to straight route The codes are provided in Appendix A 4 LEVERQUPPERLIMIT LEVER UPPERLIMIT war 2 2 LEVERSGOUP LEVERTISUP LEVERIGOUP LEVER3ISUP s SE E man cim Em en L 8 J d LEVER1ISDOWN LEVER2ISDOWN LEVERSISDOWN E LEVERI GODOWN LEVER2GODOWN m e uxo UU Sa CES pd wem E Lm LEVER LOWERLIMIT mwa E 4 m 9 he ce td ae 1 p wenn Figure 26 Simulation model concerning the straight route MRes Thesis Mersedeh Maksabi October 2013 25 Simulation results using Proteus ISIS MRes In Railway System Integration Th
66. h Maksabi October 2013 18 CHAPTER THREE MRes In Railway System Integration CHAPTER THREE 3 Visualisation of Interlocking Systems through LabVIEW This chapter explains the working mechanism of the mechanical interlocking lever frames The idea is to identify the general logic behind each lever s movement and then to simulate the behaviour of the levers with respect to both straight and reverse route through LabVIEW software Testing procedure of the mechanical interlocking lever frame is performed twice with regards to straight and reverse route using a shunt neck Figure 18 below shows a track layout with an interlock which is divided into two separate routes 1 5 DOWN 5 SHUNTING NECK le Lever Number Control Signal Lever 1 Distant Signal Lever 2 Home Signal Lever 3 Station started Signal Lever 4 Shunting Signal Lever 5 Shunt Point Lever 6 Shunting Signal Figure 18 Track layout with signals and points MRes Thesis Mersedeh Maksabi October 2013 19 Visualisation of Interlocking Systems through MRes In Railway System Integration LabVIEW 3 1 Testing over Straight Route set from A to B The first test requires levers 1 2 and 3 to be unlocked in order to clear the route by making distant signal home signal and station started signal to green respectively However based on the working mechanism of the interlocking frame lever 2 has to get reversed first to clear the home signal to green Du
67. h Maksabi October 2013 2 Introduction MRes In Railway System Integration Investigating the control logic Visualisation of interlocking system through LabVIEW Figure 1 Project block diagram 1 5 Thesis Layout This thesis is organised into seven chapters Chapter one briefly explains the aim and objectives of the project as well as the project s scope and methodology Chapter two contains a literature review and history of the interlocking machine Chapter three concentrates on system visualisation and demonstrates functionality of the lever frame due to both straight and reverse route which is accomplished by LabVIEW software Chapter four presents the operation mechanism of the mechanical interlocking lever frame through three MRes Thesis Mersedeh Maksabi October 2013 3 Introduction MRes In Railway System Integration different simulation models In chapter five basic principles characteristics and the working mechanism of the linear machine are discussed The analysis of the experimental setup practical results the schematic of the entire system and the finalised circuit are discussed in chapter six Chapter seven includes the conclusion problems and future work and suggestions MRes Thesis Mersedeh Maksabi October 2013 4 CHAPTER TWO MRes In Railway System Integration CHAPTER TWO 2 Literature Review 2 1 Configuration and application of Interlocking Interlocking has been introduced as the most vital sec
68. hankful to Dr Charles Watson for his efforts and great company He has always been accessible and provided me with great information resources superior teaching and good advice He showed me the right way and I would have been lost without him I would like to thank all the members of the Electronic Electrical and Computer Engineering Department in particular Mrs Joy Grey and Mr Andy Dunn Ultimately I dedicate my dissertation to my father who always supported me and encouraged me throughout my way my mother who has always been a source of love to me and my beloved sister Mahsa None of this would have been possible without their love support and patience Mersedeh Maksabi October 2013 11 Preliminaries Table of Contents Executive n i List of Ninrajrin p X 555555 4 1 Mini 1 1 1 Motivation for Building Interlocking 1 1 2 Objectives of an nterlocking 1 2 2 1 Thesis Tey OM 3 CHAPTER 5 2 Literature 5 2 1 Configuration and application of Interlocking eese 5 2 2
69. he interlocking lever frame Figure 65 Two aspects of signalling fisrt shot Figure 65 shows associated LEDs to each lever According to the figure the black circle indicates the associated LEDs to lever 2 which is controlled by first magnetic contact The orange circle shows associated LEDs to lever 3 which is governed by second magnetic contact The green and the red circles show the corresponding signals to third and fourth levers respectively The LEDs inside the blue and yellow circles are controlled by the fifth and sixth levers Figure 66 Interlocking top view MRes Thesis Mersedeh Maksabi October 2013 53 Experimental Setup and Practical Results MRes In Railway System Integration Figure 67 Position of magnetic contact In order to control train operation concerning the straight route three signals need to get clear through activation of first three levers The first step is to clear home signal by reversing lever 2 Figure 68 illustrates home signal due to activation of lever 2 In here lever 1 is locked Figure 69 Station started signal MRes Thesis Mersedeh Maksabi October 2013 54 Experimental Setup and Practical Results MRes In Railway System Integration The next step is to clear station started signal which is control by lever 3 Figure 69 shows home and station started signal due to activation of lever 2 and lever 3 lever 1 can get reverse now The last step is to clear distant sig
70. hes MRes Thesis Mersedeh Maksabi October 2013 27 Simulation results using Proteus ISIS LED EXT LEVERJ GODOWN LEVER2UPPERLIMIT SPDT LEVER2ISUP id LEVER2ISDOWN GREEN MRes In Railway System Integration LEVERSUPPERLIMIT pus 5 0 LEVER3ISUP Le0 BLUE SW SPOT t LEVERSGODOWN LEVER3LOWERLIMIT Figure 30 Activation of levers for normal route The same approach has been adopted to simulate lever s working mechanism due to the reverse route Figure 31 shows the system approach for the reverse route In this model states of lever 4 5 and 6 have been examined Levers 4 and 6 create a shunting signal and they cannot get reversed at the same time LEVERgUPPERLIMIT Md SW SPOT T LEVER4ISUP LEVERSISUP TE LEO BLUE Sw SPOT LEVER4ISDOWN Nest 246 LEVER6ISUP Figure 31 Activation of levers for reverse route MRes Thesis Mersedeh Maksabi October 2013 28 Simulation results using Proteus ISIS MRes In Railway System Integration To clear the reverse route the station started signal has to be green first Subsequently the shunting signal will be clear as Levers 4 and 6 get reversed However they cannot get reversed at the same time Hence the shunting signal due to lever 6 will be clear and according to that the shunt point which is cont
71. hey are allowed to be reversed and are permitted to have corresponding movement Based on the above as lever 2 is reversed lever 1 is locked to the normal state 2R 1N and vice versa 1R 2N this indicates the reciprocal relation between each pair In addition the locking might be termed exclusion In such a case lever 2 reversing is locked by lever 1 normal and vice versa 1N 2R and 2N 1R Usually all the levers can MRes Thesis Mersedeh Maksabi October 2013 9 Literature Review MRes In Railway System Integration hold the normal state at the same time in such a case exclusion does not exist Calvert 2008 2 Home 1 Distant 1 gt 1 gt Figure 7 Exclusion Calvert 2008 2 3 4 Conditional Locking Figure 8 illustrates conditional locking which became possible through the tappet locking Figure 8 Conditional Locking Calvert 2008 1 gt 3 1 gt As the above diagram shows at the left the lever 2 gets reversed both the lever 1 and lever 3 are free to move in any way The movable portion will be located between two tappets 1 and 3 once lever 2 get locked into the normal state This will allow lever 1 to locks lever 3 to normal state and vice versa Indeed whenever lever 2 get normal lever 2 will get lock to normal by lever 1 Hence the position of lever 2 is governing the relation and state of lever 1 and 3 Indeed once lever 2 3 5 Crossing Having home signal for each di
72. hine starts to operate as a motor 5 2 PECO Turnout Motor The intended motor for this project is turnout peco motor PL 10e which is using for low voltage applications The motor should be energized momentarily and the maximum operating voltage is 16v AC The motor is formed by two windings and a shaft in the middle part MRes Thesis Mersedeh Maksabi October 2013 36 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor Figure 38 PL 10e PECO motor The recommended track type this motor is N 009 H0e which has two holes on each side and one hole in the middle to fit the tie bar To fix the motor to the switch the centre legs of the motor have to be bent over so the tie bar in the middle moves and accordingly changes direction of switch to left and right Figure 39 PECO motor with bended central legs A track layout with two points has been designed and fixed on a wooden board that is 1 5 metres in length and 0 35 metres in width The baseboard has two holes with size of 40mm 24mm where points are located and motors will be passed through the holes and connected to the switches Figure 40 Illustration of switches and part of the track layout on the baseboard MRes Thesis Mersedeh Maksabi October 2013 37 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor 5 3 Software Implementation As mentioned above the motor has to energise for
73. ice versa 6 2 3 Sensitivity Evaluation of Magnetic Contact In order to test the adopted magnetic contact the reed switch was connected to a digital multimetre with the lowest selected resistance range ohms At the beginning the multimetre indicated 1 mega ohms As the magnet was brought into proximity of the switch the reed which is ferromagnetic was closed and the digital multimetre indicated 0 2 ohms The sensitivity of the switch has been examined due to the different distance and orientation which confirms that the maximum distance between the magnet and reed switch has to be less than 15 mm Figure 59 Reed switch sesitivity evaluation MRes Thesis Mersedeh Maksabi October 2013 40 Experimental Setup and Practical Results MRes In Railway System Integration R7 10K Decoupling capacitor R8 10K M 100nF R12 10K RI 10K LED R2 330 Ky Crystal gt d 96 amp m Oscillator 4 MHZ Cl 15 pF g J Buzzer 2 LED 11 LED2 R3330 a R17 330 LED 9 R16 330 5 a ca Switchl Negative feedbac Op Amp Rectifier E 12VAC le LED 10 Switch 2 Input 12 VAC Negative feedback Op Amp 12 Motor 6 Figure 60 The layout of circuit MRes Thesis Mersedeh Maksabi
74. igure 10 shows junction Although both the distant signals and the facing point lock are not presented here but they will normally nominated Figure 10 Junction Calvert 2008 The distant signal have only one arm and it will be cleared once the straight route with all the corresponding field elements were completely set Accordingly lever 1 and 2 will be pulled for straight through movement and also movement to the branch respectively The mentioned movements cannot happen at the same time as the corresponding arms for them arms 1 and 2 cannot get lowered at the same time The situation will fully different for the arms 1 and 3 as they both can get lowered reversed once the lever 5 gets lock to the normal state Therefore as the lever 5 gets reversed arms 2 and 4 will get lowered MRes Thesis Mersedeh Maksabi October 2013 11 Literature Review MRes In Railway System Integration 2 3 7 Locking Sheet Figure 11 presents a locking sheet for the mentioned interlocking In this locking sheet the reversed lever is presented by a circle around the lever s number lever when locks 1 5234 2 5334 3 5 4 Figure 11 Locking Sheet Calvert 2008 The above locking sheet can be read as follow e Levers 2 3 4 and 5 will be locked to normal state once lever 1 reversed e Levers 3 and 4 will be reversed and the fifth lever will locked to normal once lever 2 reversed e Levers 5 and 4 will be locked to normal a
75. imer disabled pragma config BOR OFF Brown out reset disabled pragma config LVP OFF Low voltage disabled pragma config WDT OFF Watch dog timer disabled pragma config DEBUG OFF Background debugger disabled F XXE kkk kk kkk kk Codes and Definitions pragma code define ON 0 define OFF 1 define left 1 Left winding motor1 define right 2 Right winding motor1 define left 3 Left winding motor2 define right 4 Right winding motor2 void delay ms unsigned int duration unsigned char is swl1 pressed void unsigned char is sw2 pressed void unsigned char is sw3 pressed void unsigned char 15 sw4 pressed void unsigned char is_sw5_pressed void unsigned char is_sw6_pressed void void direction int dir if dir left MRes Thesis Mersedeh Maksabi October 2013 73 Appendix A PORTCbits RC6 ON DelayI KTCYx 50 PORTCbits RC6 OFF else PORTCbits RC7 ON DelayIKTCYx 50 PORTCbits RC7 OFF if dir left1 PORTDbits RD4 ON Delay 1KTCYx 50 PORTDbits RD4 OFF else PORTDbits RD5 ON DelayI KTCYx 50 PORTDbits RDS OFF void main TRISCbits TRISCO 0 TRISCbits TRISC1 0 TRISCbits TRISC2 0 TRISCbits TRISC3 0 TRISCbits TRISC4 0 TRISCbits TRISC5 0 TRISAbits TRISAO 0 TRISBbits TRISB5 0 MRes Thesis MRes In Railway System Integration PortC as output LED1 is conne
76. isted bar HT3 was the last form of the mechanical interlocking machine which was used by the Great Western Railway 1906 1926 The HT3 locking machine included locking trays which were located in both a vertical and a horizontal manner and driven by the means of bell cranks Moreover each tappet blade of the HT3 machine had three bridles 5 was another version of the HT3 locking machine with 5 bridles on each tappet blade appeared in 1926 1966 In the 5 machine the lever was driven by the motion of both tappet blade and cam plate In 1943 the largest VT5 frame with 222 levers was At Reading Main Line West GWR 2013 2 3 Past Interlocking Machines 2 3 1 Tappet Interlocking In 1870 James Deakin created an effective and straightforward method for interlocking the levers which is tappet interlocking Based on this method the levers force the notched tappet blades sword irons or plungers to move directly or with the help of any other intervening mechanisms The bridles or locking bars are perpendicularly located on the tappet blades which are capable of moving sideways see figure 5 The tappets were riveted to the bridles and fixed in the locking bars through the notches The tappet is engaged with blades and as the blades move the tappet will move to the right or left accordingly Sometimes the tappets MRes Thesis Mersedeh Maksabi October 2013 8 Literature Review MRes In Railway System Integration are occupied with
77. ith a single op amp inside Input Offset 8 NC inverting Input Supply Non inverting Input Output Supply Input Offset Figure 47 LM741 internal architecture MRes Thesis Mersedeh Maksabi October 2013 42 CHAPTER SIX MRes In Railway System Integration 5 5 3 Diode Indeed when the relay is released from its energised state there is a risk of damage for the op amp or microcontroller which drives the relay Therefore to protect the circuit from back emf it is vital to connect a rectifier in reverse bias manner across the relay coil Accordingly the diode will short out the Back emf created by the coil when it turned off from on state Figure 48 Position of op amp reed relay and diodes Figure 48 demonstrates the connection between circuit components from output of the microcontroller blue wire to inverting input of negative feedback op amp and from output of op amp to applied diodes across relay coil MRes Thesis Mersedeh Maksabi October 2013 43 CHAPTER SIX MRes In Railway System Integration CHAPTER SIX 6 Experimental Setup and Practical Results Following to the previous chapter an electronic circuit has been designed and examined in a real experimental situation The aim of this experiment was to energise the motor based on a correct communication between the control unit microcontroller and other adopted electrical components a 44694 Figure 49 Demonst
78. l The intended diodes protected the microcontroller and op amp from the harmful effects of back emf Besides both current and voltage will be reduced due to the internal resistance of the rectifiers Therefore a secure amount of dc voltage was provided for the reed relay to operate Figure 52 Experimental setup MRes Thesis Mersedeh Maksabi October 2013 45 Experimental Setup and Practical Results MRes In Railway System Integration Figure 52 demonstrates the first experimental setup within the project As is obvious from the figure the motor was fixed to the switch point of the track Hence by arriving at each oncoming square pulse the internal switch of the reed relay was activated and the direction of the switch was changed due to a short linear movement created by the motor Each winding of the motor has a ground and a source pin which indicates yellow and red wires The yellow wires were connected to the ground of voltage supplier and the red wires were connected to the first pin of the relay Besides the fourth pin of the relay was connected directly to a voltage supplier in order to provide the required voltage for the motor to operate 6 1 1 Case Study As mentioned the relay coil requires more than 100mA current On the other hand the maximum output current sunk by each output of the microcontroller is 25mA Hence an alternative was to use PNP transistor this is to drive the relay and to make sure that the relay will
79. lar to Chambers but both rods and holes were redesigned and moved underneath the floor where the cabin was positioned In 1874 the levers were combined with a large rotating motion around the axis which is known as Rapiers locking The locking was located in the middle of notches and locking bars The related locking bar to each lever is driven with the use of a cam All the interlocked levers with certain levers are locked at the occurrence of the first motion of the levers and at the last motion of the levers the required levers are unlocked An 80 levers frame of Rapier was installed at Lincoln In on the fixed signals of railways 1874 The first American interlocking machine was designed in 1870 by Toucey and Buchanan and it was installed at Duyvil at the north end of Manhattan in 1875 In 1888 a locking machine similar to that of Saxby and Farmer s machine was designed by Arthur Henry Johnson with the cooperation of his nephew C R Johnson However in this machine the links were connected in reversed manner and under the ground Moreover the Webb and Thompson electric train staff machine was introduced in the United States by Johnson in 1892 Calvert 2008 The devised machine by Johnson was applied for the first time between Savanna Illinois and Sabula lowa The American Interlocking Machine was either like the Saxby and Farmer machine or the Johnson machine The produced machine by National Signal Company was almost the
80. larity The reed switches are connected to a microcontroller Each lever status reverse normal will be sent to the microcontroller as an input Consequently the corresponding output due to activation of each lever will be generated from PIC microcontroller as an electrical signal with enough amount of current to activate the related LED A track layout with two switch points has also been designed and fixed on a wooden board which has two holes at the location of the switches The directions of the switches are controlled by Mersedeh Maksabi October 2013 i Preliminaries two AC motors which are connected to the switches and energised with the help of a microcontroller and reed relays for a short period of time Mersedeh Maksabi October 2013 11 Preliminaries Acknowledgments It is a pleasure to thank those who made this work possible this project would not have been possible without their help and support Firstly I would like to show my gratitude to Prof Felix Schmid for his superior supervision throughout the whole period of this project He was always willing to guide me from the initial to the final stage of the project He encouraged me to be an independent thinker and have an engineering point of view I owe sincere and earnest thankfulness to him for his support careful guidance and understanding I am sure it would have not been possible to complete my project without his great efforts I am truly indebted and t
81. ms Nowadays signalling technology is largely affected by the presence of high performance electromechanical relays which provide the required logic on one hand and securely control the train movement on the other However this kind of control system is bulky and requires large space to accommodate Therefore such a technology will be expensive as it requires intensive efforts for manufacturing installation and maintenance The mechanical interlocking is an alternative substitution for the electromechanical relay based systems All interlocking systems have been developed by considering all the safety issues and existing standards within the railway signalling The current project introduces a new electromechanical approach which utilises the real time data from a mechanical unit and produces the outputs in the form of electrical signals To achieve this an electronic circuit has been designed to use the extracted data to represent the status of each lever within the mechanical interlocking Ultimately this electronic circuit determines two aspects of signalling concerning straight and reverse route This procedure is performed with the aid of magnetic contacts which are formed by two parts magnet and reed switch The magnets are fixed underneath each lever As a lever is reversed the reed switch will move to close proximity to the magnet and a propagated magnetic field by the magnet will trigger the internal switch to close based on their po
82. n Bandaidth Product ilc 10 made 5 0 Vide T 100 10 Vide le 17 1 0 Noise Figure lc 0 2 mAdc 5 0 Vie Rs ZO kit f 10kHz BC214 ile 0 2 mAdc 5 0 Vide Fig 2 0 kia 1 1 0 kHz f 200 Hz BC212 213 le 2 0 made Veg 5 0 Vide 17 1 0 kHz 1 Pulsa Test Tp 300 Duty Cycle 2 0 MRes Thesis Mersedeh Maksabi October 2013 114 Appendix B MRes In Railway System Integration z U wera wf ene IE IUE DS m j pu Wy g ZEE B us m MO C 4 SELL T DU EE DU E O N gt A hi 42 445 40 20 5D 0 9 COLLECTOR CURRENT jc Tye UTE Pug MRes Thesis Mersedeh Maksabi October 2013 115 Appendix B MRes In Railway System Integration MRes Thesis Mersedeh Maksabi October 2013 116 Appendix B MRes In Railway System Integration MRes Thesis Mersedeh Maksabi October 2013 117 Appendix B MRes In Railway System Integration MRes Thesis Mersedeh Maksabi October 2013 118
83. nal which is supervised by lever 1 Figure 70 Distant signal Train operation in the reverse route supervises by 4 signals that are control by the last four levers Accordingly the first step is to clear station started signal which means the third lever has to get reverse Figure 71 Station started signal for the reverse route Then it requires shunting signal to get clear before the points start to operate and change the direction of the track Figure 72 Shunting signal and point MRes Thesis Mersedeh Maksabi October 2013 55 Experimental Setup and Practical Results MRes In Railway System Integration The shunting signal control by lever six and station started signal cannot get clear at the same time because of the safety issues Hence as one lever gets lock the other one will return back to it s normal state Figure 73 Shunting signal and point 2 Subsequently as the points 5 get active and the track s direction changed the shunting signal will clear due to activation of lever 4 before lever 4 gets reverse the lever 6 needs to return back to it s normal state 6 2 6 Circuit Enhancement The provided interlocking operates by considering all the safety issues and existing standards within railway signalling Hence levers cannot operate individually as some of them are internally locked by other levers and these locks will not allow the lever to move freely The working mechanism of the levers conc
84. nal of engineering research amp technology Vol 1 1 7 CalvertJ BRailway history signalling engineering Online 2008 Cited 22 04 2013 http www railway technical com Changing track moving block railway signalling LockyearM J1996 ChapmanS J Electric machinery fundamentals s l MC Graw Hill third 1999 Cribbens Railway signalling systems 5 242 136United kingdom 1993 electronicsLabcentre ntelligent schematic input system 2002 GWRGtreat western railway 3 bar tappet lever frame Online 2013 Cited 21 07 2013 http www s r s org uk research html In on the fixed signals of railways RapierR CNew York Institution of civil engineers 1874 InstumentsNational LabVIEW user manual Austin Texas National Instruments corporate Headquarters 2003 JohnsonA HThe development of fixed signals on railways Railroad Gazette 7 April 1893 pp 255 258 LawrenceAndyAn Introduction to Railway Signalling and Equipments Online 18 August 2011 Cited 24 5 2014 http cs swan ac uk csal Talks Railwaytalk 1 pdf Macdougall A railway signalling system EP0341826GB 1994 MacmillanB E Amplifier circuit and method for providing negative feedback wo 2001071905 A3United state 2002 MRes Thesis Mersedeh Maksabi October 2013 61 References MRes In Railway System Integration Microchip 28 40 44 Pin Enhanced Flash Microcontrollers s l Microchip Technology Inc 2004 MPLAB 8 c compiler libra
85. nd reverse state respectively as the lever 3 get reversed e The when column is empty as there is not any conditional locking 2 3 8 First Motion In order to move the tappet from the notch and lock related levers motion of locking bars within one half of the tappet is required In last moving part of the locking bars all the associated levers are completely unlocked It is important to bear in mind that both first and last motion of the locking bars is necessary for having a safe operation of the frame Figure 12 Fisrt Motion Calvert 2008 Assume a short distance in one lever s movement an effective attempt to move the second lever if the second lever is not locked could conflict the routes The frame can get damaged in the case of considerable leverage as the locking bars are moved by levers directly Thereby it is necessary for all the levers that are going to be locked to be locked in the first motion of the lever and all the levers that need to be unlocked to get unlocked on the last motion MRes Thesis Mersedeh Maksabi October 2013 12 Literature Review MRes In Railway System Integration In order to provide an early and last movement the easiest solution is to create the stroke of the locking bar larger than the width of the tappet which was done by Steven and sons through a small frame which was often used in ground frames 2 3 9 Cam Plate The provided lever locking model by Steven was inappropriate for small
86. ned by Vg eina eq 9 ss eq 10 The bar will continue to move at this no load speed until an external force interrupts it MRes Thesis Mersedeh Maksabi October 2013 34 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor 5 1 2 Linear Motor A force is applied in an opposite direction to the bar The direction of net force on the bar will be in the opposite direction of motion as the bar was running under no load steady state Fret Fina eq 11 The bar will slow down due to the presence of external force and the induced voltage across the bar will drop due toe g v Bl The current in the bar will increase according to the reduction of induced voltage eindl i t ee eq 12 Hence the induced forces will increase by Fina i IB The induced force will increase as far as it is equal and opposite to the load force therefore the bar slowly goes to steady state Magnetic field into page Switch Figure 37 Linear motor Chapman 1999 The induced force is in the same direction as the motion of the bar and the bar will continue to move as the power converts from electrical form to mechanical form by Feonv eq 13 MRes Thesis Mersedeh Maksabi October 2013 35 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor The electrical power is equal to einai and it
87. onic circuit to use the extracted data from the mechanical unit and generate the desired output as electrical signals e Extending the code in order to energise the intended motor which has a prototype switching function at the junctions in parallel with two aspects of signalling e Enhancing the designed circuit by utilising LCD and buzzers which operate as two additional events as each route get clear by its corresponding control signals 72 Recommendation All the mentioned tasks have been performed successfully through three different software LabVIEW MPLAB and Proteus ISIS The most important problem during the work was circuit isolation as two parts of the circuit were supplied by two different voltage suppliers The motor part of the project required 12 VAC whilst the signalling part was supplied by 5 VDC The designed circuit accomplished only one PIC which was in charge of controlling all the events within the entire system Hence it is obvious that the control logic for the energising motor came from the PIC output which operates with a 5VDC and a 25 mA current which was not enough to energise the motor s windings To overcome this issue and guarantee fairly safe communication between circuit components a PNP transistor was used firstly Low speed switching frequency of the intended PNP transistor confirmed that it cannot provide the required voltage for the motor due to each oncoming pulse from PIC because the switching frequency of
88. or18TCY E PIN 20 DelayFor18TCY TRIS DATA PORT Oxff Data port input else 4 bit interface ifdef UPPER Upper nibble interface TRIS DATA PORT amp OxOf DATA PORT amp OxOf DATA PORT cmd amp Oxf0 else Lower nibble interface TRIS DATA PORT amp Oxf0 DATA PORT amp Oxf0 DATA PORT cmd gt gt 4 amp 0xOf endif RW PIN 0 Set control signals for command RS_PIN 0 DelayFor18TCY 1 Clock command in DelayFor18TCY E PIN 20 ifdef UPPER Upper nibble interface DATA PORT amp OxOf DATA PORT cmd lt lt 4 amp 0xf0 else Lower nibble interface DATA_PORT amp Oxf0 MRes Thesis Mersedeh Maksabi October 2013 100 Appendix A MRes In Railway System Integration DATA PORT l cmd amp OxOf ftendif DelayFor18TCY 1 Clock command in DelayFor18TCY E PIN 0 ifdef UPPER Make data nibble input TRIS DATA PORT l Oxf0 else TRIS DATA PORT l OxOf endif endif return MRes Thesis Mersedeh Maksabi October 2013 101 Appendix A MRes In Railway System Integration include lt p18F452 h gt include xlcd h 75 7 7 2 2 2 kkk k k k k k k k kk Function Name WriteDataXLCD Return Value void Parameters data data byte to be written to LCD Description This routine writes a data byte to the Hitachi 0
89. ounce and Filter Circuit do Deas eit 51 6 25 Real lime Data AGquisIUOD 53 Mersedeh Maksabi October 2013 V Preliminaries 6 2 6 gt c Circuit Enbange melios sedeo eee 56 CHAPTER SEVEN sniene cuori eas neve enn S ERIT 58 rece TX RS 58 Jl 58 T2 RE COMMIS IAG ler dida 58 Ta REVIEW OLA 59 7 4 Areas for Further 59 DESEE Coche 60 61 m NEU inm 61 8 2 Web Site TAKS onere desi ote als nb 62 dHBHOSEADHYS s entes ode stub ae pef 63 Appendix 65 Appendix va Cond Pla 104 Mersedeh Maksabi October 2013 vi Preliminaries List of Figures Figure 1 Project block diagram eee one ton eee 3 Figure 2 General objectives of Interlocking Systems see 5 Figure 3 Railway interlocking and main communication line 5 Figure 4 Old Interlocking Lawrence 2011 eto 6 Figure 5 Tappet Interlocking Calvert 2008 9 Figure 6 Mutual Locking Calvert 2008 9 Figure 7 Exclusion Calvert 2008 DADA 10 Figure 8 Conditional Locking Calvert 2008 sse 10 Figure 9 Crossin
90. processors The obtained data from the interlocking will be stored in the first processor in MRes Thesis Mersedeh Maksabi October 2013 59 Conclusion MRes In Railway System Integration binary format The stored data in the first processor and the random data from the second processor will be transmitting to a comparator unit Subsequently the first input from the advance processor first processor will be compared to the first generated data packet from the second processor and so on Accordingly any mismatch between generated data packets from the first processor and the second processor will trigger the comparator to provide a safety command to check the signals that affect system safety Such a system will require tightly synchronised architecture as two processors needs to be checked at the same time A fai safe interlocking system for railways 1985 7 5 Word count There are 11484 words from chapter one to the end of chapter seven MRes Thesis Mersedeh Maksabi October 2013 60 References MRes In Railway System Integration 8 References 8 1 Documents A fai safe interlocking system for railways VermaM R1985 fail safe system design pp 58 65 AdamsB BThe block systemof signalling on american railroads The Railroad Gazette 1901 pp 173 226 al Rylandet Interlocking for a railway system 6 308 117 Blunited state 2001 Automation of Railway Gate Control Using Microcontroller DewanganA K3 2012 International Jour
91. pulses from the outputs of the PIC held negative value The output of negative feedback op amp will go to the relay Ultimately as each 5 VDC pulse arrives at the internal switch of the relay the switch will be closed due to different polarity and eventually the motor will be energised for a short period of time changing the direction of the switch MRes Thesis Mersedeh Maksabi October 2013 39 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor Peco Motor Figure 43 Circuit block diagram MRes Thesis Mersedeh Maksabi October 2013 40 Introduction to Linear Machine and PECO MRes In Railway System Integration Turnout Motor 5 5 Introduction to Circuit Components 5 5 1 Reed Relay Reed relay is a switch formed by two internal iron stripes which are covered by coils of wire When the coil is supplied with power the wire will generate a magnetic field and the propagated magnetic field will be sensed by two iron stripes inside the relay s body and ultimately the relay will be operated as a mechanical switch Coil Contacts Contact a Open Reed Contact Hermetic Seal b Closed Reed Contact Figure 44 NC and NO relays The internal switch in NO or normally open relays is open by default Hence the internal switch will be closed and the circuit will be connected due to activation of the relay according to the presence of the magnetic field The NC or norm
92. ration of preliminary circuit The intended motor was energising due to the activation of a reed relay The intended reed relay required 3 5 VDC to operate However the generated square wave from the microcontroller was not able to provide the required current for the relay for switching gt e 5 e 5 e f id 0 0 05 0 1 0 15 02 0 25 0 35 04 0 45 0 5 Time sec Figure 50 Negative voltage square pulse from the microcontroller MRes Thesis Mersedeh Maksabi October 2013 44 Experimental Setup and Practical Results MRes In Railway System Integration To energise the motor the relay has to be activated first which means the internal switch has to be closed Hence an amplifier with negative feedback has been applied Accordingly the output pin of the microcontroller was connected to inverting input of the op amp At the same time the output of the operational amplifier was connected to the non inverting input which caused internal phase inversion by 180 degrees Therefore the generated negative voltage square pulse from the microcontroller was changed to positive voltage square pulse Op Amp Output V i H 70 0 05 01 0 15 0 2 0 25 03 0 35 04 0 45 0 5 Time sec Figure 51 Detected pulse from output of op amp The 5 VDC square pulses were passed from output of the op amp to two rectifiers which were connected across the relay coi
93. rection and a unique distant signal for each home signal is required to protect level crossing properly as shown in figure 9 In this case we consider home distant signal with two aspects of signalling Although eight levers will be required in reality to make it simpler let us assume there are only four levers which can combine home and distant signals Accordingly the two home signals cannot be reversed simultaneously and a distant signal should be reversed whenever the related home signal is reversed Assuming levers1 2 3 and 4 as home signals lever 1 is reversed and locks lever 2 3 and 4 normal This indicates that lever 1 will be locked to normal by lever 2 reversed Moreover lever 2 reversed locks levers 3 and 4 to normal Ultimately lever 4 should be locked to normal state by lever MRes Thesis Mersedeh Maksabi October 2013 10 Literature Review MRes In Railway System Integration 3 As is illustrated in figure 9 as the signal lever is reversed all the other levers will be locked to the normal state Figure 9 Crossing Calvert 2008 In fact we need to consider locking with higher numbered signals Correspondingly when considering the switches there is a need to consider locking with higher numbered switches Consequently switch levers are locked by signal levers Based on the above each pair of levers will be considered once to avoid the provision of superfluous interlocking Calvert 2008 2 3 6 Junction F
94. ries s l Microchip Technology Inc 2005 NewmanG D Railway signalling system 5 437 422United State 1995 Principle of interlocking Online 2004 Cited 25 7 2013 http mysite du edu etuttle rail lock html SignallingUKThe Development and Principles of UK Signalling Online 2013 Cited 26 02 2013 Jhttp www railway technical com sigtxt1 shtml Silicon germanium base heterojunction bipolar transistirs PATTONG L1988 Vol 9 pp 165 167 Solid state interlocking SSI an integrated electronic signalling system for mainline railways CribbensAmay 1987 1987 Railway electrification and transportation signalling Electronic circuits pp 148 158 WallerJSolid state interlocking Railway control systems london A amp C Black 1991 21 31 8 2 Web Site Links Calvert 2008 Railway history signalling engineering Online Available at http www railway technical com Accessed 22 04 2013 GWR 2013 Great western railway 3 bar tappet lever frame Online Available at http www s r s org uk research html Accessed 21 07 2013 Principle of interlocking 2004 Online Available at http mysite du edu etuttle rail lock html Accessed 25 7 2013 Railway systems technologies and operation across the world 2013 Online Available at http www railway technical com sigtxtl shtml Accessed 26 02 2013 An Introduction to Railway Signalling and Equipment 2011 Online MRe
95. rolled by lever 5 will change track direction through activating the switches Refer to chapter 5 Ultimately lever 6 will get normal locked and a corresponding shunting signal to lever 4 will come up As is clear from figure 31 Lever 5 s Upper Limit switch is active this means that lever 5 is reversed and Lever 4 s Lower Limit switch is active which means lever 4 is locked Thus as Lever 6 GoUp operates the blue signal corresponding to lever 6 will come up Figure 32 presents the activation of lever 4 through opposite operation LEVERAUPPERLIMIT LEVERBUPPERLIMIT LEVERALOWERUMIT W SPOT Figure 32 Activation of lever 4 As is obvious from figure 32 the corresponding shunting signal to lever 4 has been turned on This is governed by two pre defined variables namely Lever 5 Upper Limit and Lever 6 Lower Limit which means lever 4 can be reversed if lever 6 gets locked and accordingly lever 5 get reversed To evaluate the presented design the simulation has been run under activation of Lever 5 Upper Limit switch this is to show the effect of Lever 6 Lower Limits on the LED response MRes Thesis Mersedeh Maksabi October 2013 29 Simulation results using Proteus ISIS MRes In Railway System Integration Figure 33 shows the LED response due to activation of Lever 5 Upper Limit switch and deactivation of Lever 6 Lower Limit LEVERSUPPERDMIT LEVERAUPPERLIMIT LEVER4ISDOWN LED OREEN LEVERALOWERUMIT
96. rsedeh Maksabi October 2013 75 Appendix A MRes In Railway System Integration TRISDbits TRISD7 1 set SWITCH6 pin as input while 1 if is_swl_pressedQ 1 check switch 1 PORTCbits RCO 1 turn ON LED 1 PORTCbits RC3 0 else PORTCbits RCO 0 turn off LEDI PORTCbits RC3 1 if is_sw2_pressed 1 check switch 2 PORTCbits RC1 1 turn on LED PORTCbits RC4 0 else PORTCbits RC120 turn off LED PORTCbits RC4 1 if is sw3 pressed 2 1 check the switch 3 PORTCbits RC2 1 turn ON LED PORTCbits RC5 0 turn OFF LED else PORTCbits RC2 0 turn off LED2 PORTCbits RC5 1 direction left Delay lOKTCYx 20 MRes Thesis Mersedeh Maksabi October 2013 76 Appendix A MRes In Railway System Integration Delay lOKTCYx 20 direction left1 Delay lJOKTCYx 20 Delay lOKTCYx 20 if is_sw4_pressed 1 check switch 4 PORTAbits RAO 1 turn off LED6 PORTBbits RB5 0 turn off wise LEDS else PORTAbits RAO 0 turn off LED6 PORTBbits RB5 1 if is sw5 pressed 2 1 is switch 5 pressed gt if yes ree turn off LEDS PORTBbits RB7 0 turn off wise LEDS else PORTBbits RB6 0 turn off LEDS PORTBbits RB7 1 turn off wise LEDS if is_sw6_pressed 1 is switch 6 pressed PORTEbits REO 1 PORTEbits RE1 0 turn ON LED 1 else hf not PORTEbits REO 0 turn off LEDI MRes Thesis Mers
97. s Thesis Mersedeh Maksabi October 2013 62 References MRes In Railway System Integration Available at http cs swan ac uk csal Talks Railwaytalk 1 pdf Accessed 24 05 2014 8 3 Bibliography A fai safe interlocking system for railways VermaM R1985 fail safe system design pp 58 65 AdamsB BThe block systemof signalling on american railroads The Railroad Gazette 1901 pp 173 226 al Rylandet nterlocking for a railway system 6 308 117 Blunited state 2001 Automation of Railway Gate Control Using Microcontroller DewanganA K3 2012 International Journal of engineering research amp technology Vol 1 1 7 CalvertJ BRailway history signalling engineering Online 2008 Cited 22 04 2013 http www railway technical com Changing track moving block railway signalling LockyearM J1996 ChapmanS J Electric machinery fundamentals s l MC Graw Hill third 1999 Cribbens Railway signalling systems 5 242 136United kingdom 1993 electronicsLabcentre ntelligent schematic input system 2002 GWRGtreat western railway 3 bar tappet lever frame Online 2013 Cited 21 07 2013 http www s r s org uk research html In on the fixed signals of railways RapierR CNew York Institution of civil engineers 1874 InstumentsNational LabVIEW user manual Austin Texas National Instruments corporate Headquarters 2003 JohnsonA HThe development of fixed signals on railways Railroad Gazette 7 April 1893
98. s used to be operated at their locations An obvious problem was that each signalman was able to cover only a limited number of signals Therefore the switch levers were connected to the switches by rods and placed in an elevated platform Signals on top of the elevated platform were operated by stirrups to keep them clear A constant effort and supervision was required Although the suggested system was affordable at first sight it was impregnated with dangerous hazards Calvert 2008 The hazardous conditions occurred due to errors in operation of both signals and switches because it was not possible to identify which lever relates to which switch and signal Besides signalmen were unable to observe the switches in operation Consequently they could not locate the operated signals and switches fitted for the certain route In addition if the driver could identify the applied signal he was still in doubt for the proper place to stop Hence to mitigate hazardous situations in railway signalling systems and in order to have a safe and more logical operation it is necessary to connect signals and switches together 1 2 Objectives of an Interlocking Signalling is known as the most vital section of the railway system because controlling and management and safe movements of trains are dependent on it Signalling and train control systems have been improved over the years and recently they have developed as an extremely technical and complex indu
99. ssed gt output 1 if not output 0 J S hee eee ESSERE 4445 unsigned char is_sw2_pressed void if PORTDbits RD1 0 is switch 2 pressed if yes delay ms 10 wait 10milisecond if PORTDbits RD1 0 check the state of switch after 10 mS delay Avoid switch bounce if it pressed return 1 return valuel return 0 return 0 if the switch is not pressed Figure 63 Delay routine Another method to overcome switch bounce within the circuit is to use filter circuit which consists of a resistor and a capacitor The capacitor will be charged and discharged through a 10K resistor based on activation and deactivation of the magnetic contact This will remove bounces within the output pulse and a clean single pulse will be achievable Figure 64 Filter circuit MRes Thesis Mersedeh Maksabi October 2013 52 Experimental Setup and Practical Results MRes In Railway System Integration 6 2 5 Real Time Data Acquisition As mentioned earlier in this chapter the magnets and reed switches have been used to extract information about the status of the levers from the interlocking box The microcontroller operates as a control protocol between LEDs and magnetic contacts which effectively guarantee accurate real time communication between the mechanical interlocking lever frame and the electrical circuit The following figures demonstrate 2 aspects of signalling based on obtained data from t
100. stay on when the microcontroller sends 5 VDC to the base pin of the transistor In the practical test a PNP transistor was connected in series with PIC microcontroller the output pin of the microcontroller was connected to transistor base pin and the emitter pin of the transistor was connected to the source through a 1KQ resistor which was used to reduce the amount of sunk current from voltage supplier The black circle in figure 53 shows the transistor unit As uu nn _ 3 25 x LIT Figure 53 Illustration of PNP transistor The PNP transistor has been intended to make sure that the reed relay will be activated only due to presence of logic 1 at the microcontroller output However interface between PIC microcontroller and PNP transistor in the real experimental situation confirmed that the switching frequency of the transistor is lower than that of in PIC microcontroller Figure 54 shows the generated square pulse from the transistors MRes Thesis Mersedeh Maksabi October 2013 46 Experimental Setup and Practical Results MRes In Railway System Integration amp 1 1 M sees
101. stry In the mid 19th Century mechanical interlocking was introduced in which signals and points were connected together to perform more secure and logical operation However there was no connection between signals and switches As a result certain routes were conflicted by different contradictory signals and train collision would ultimately occur The purpose of such a safety feature in the railway industry was to provide a clear and safe operation by preventing the route for a train being set up and its MRes Thesis Mersedeh Maksabi October 2013 1 Introduction MRes In Railway System Integration protecting signal cleared if there was already another signal in operation Signalling 2013 1 3 Project Scope The aim of this project is to introduce a new electromechanical approach that uses the real time data from a mechanical unit and demonstrates system outputs as electrical signals An electronic circuit is designed to extract the information about the status of each lever within interlocking made by Atkins and effectively indicate the two aspects of signalling concerning both the straight and reverse route This task has been performed with the aid of magnetic contacts which are formed by two parts magnet and reed switch The former is fixed underneath each lever and as the lever gets reverse the latter part will move to a close proximity to the magnet The propagated magnetic field will trigger the internal switch to close base
102. the blades and the bridle cannot be moved In such a case the blades will not move as movement of blades is dependent on the movement of the bridle Calvert 2008 N tappet bridle 1 Distant 2 Home locking bar 2 1 2 1 2 Figure 5 Tappet Interlocking Calvert 2008 2 3 2 Mutual Locking Figure 6 illustrates the interlocking mechanism of levers based on both home signal and distant signal As it can be seen as far as the home signal 2 is normal at stop the distant signal 1 does not have the ability to be cleared ZN 1N As soon as the home signal becomes reversed the distant signal lever can be operated if required The distant signal lever 1 is locked by the home signal lever 2 Therefore as long as lever 1 distant signal is reversed lever 2 is locked 1R 2R The interlocked levers are always considered as pairs and a reciprocal relation always exists between them Once the distant signal is reversed the home signal 2 is not able to return back to normal state which is known as back locking In back locking a clear distant signal cannot be followed by a stop signal Calvert 2008 ra 1 Distant 2 Home Figure 6 Mutual Locking Calvert 2008 2 3 3 Exclusion Figure 7 clearly shows that the levers can be reversed at the same time as they are both able to operate signals and consequently conflicting routes However they can be in the normal state at the same time and t
103. til 22 Out2 0 Out3 0 if In12 20 amp amp In2 1 amp amp In3 1 Outl 0 Out2 0 Out3 0 e if In1221 amp amp In22 0 amp amp In3 0 Outi 0 Out2 2 Out3 2 if Inl 1 amp amp 2 1 amp amp In3 1 Outl 0 Out2 2 Out3 2 In 1 In 2 In 3 Behavl Behav Behav3 IX Figure 23 Control unit for the straight route As is obvious from figure 23 the states of the push buttons are governed by six if statements due to 6 possible outputs inside a formula node Let us consider the first and fourth if statement inside a box The first if statement disabled In 1 by giving its corresponding ouput value 2 and it also enabled both In 2 and In 3 when all the push buttons are disabled In the fourth if statement both In 2 and In 3 are enabled Therefore In 1 will be enabled which shows that the state of the first pushbottom is governed by state of the second and third one MRes Thesis Mersedeh Maksabi October 2013 22 Visualisation of Interlocking Systems through LabVIEW 3 4 MRes In Railway System Integration Logical Simulation of the Reverse Route The same strategy has been adopted to simulate the functionality of the levers due to reverse route Figure 24 shows the second model in which 64 states need to be examined Only 18 states out of 64 states could physically happen However not all of them are certain to happen
104. timately the related signal to each particular lever will come up as a blinking LED Figure 56 Demonstration of finial circuit 6 2 Overview of Components in Final Circuit 6 2 1 Introduction to magnetic actuators and magnetic sensor Magnetic actuators are able to convert electrical energy input voltage current which converts to magnetic energy Electrical input Magnetic Magnetic Figure 57 Magnetic actuator block diagram Position or other mua Mechanical Output force MRes Thesis Mersedeh Maksabi October 2013 48 Experimental Setup and Practical Results MRes In Railway System Integration The energy flow in the magnetic sensor is different from the magnetic actuator The input in the magnetic sensor is mechanical energy velocity energy Mechanical energy will be converted to magnetic field and the output will be an electrical signal which is very small due to the signal s small current Hence magnetic devices with large amounts of electrical energy at the output are not classified as sensors Mechanical input Position velocity Magnetic field Electrical Output Gus mms Electrical or magnetic input energy Figure 58 Magnetic sensor block diagram 6 2 2 Magnetic Contact The majority of magnetic contacts are NC Normally Close They are formed of two parts magnet and reed switch As the switch is brought into a close proximity of the magnet the switch will active and v
105. tion for train control movements as it determines fairly safe operation by considering and managing of signals point machines crossings at grade and movable bridges as well as other field elements Fundamental principles of an interlocking are listed as below Pre defined restrictions for signal operation in which signals may not operate at the same time to allow conflicting train movements to take a place e Points and other field elements in the route need to be in position or set properly prior any permission for train operation e As route get sets and train receives the corresponding signal Train can proceed over that route safely Whilst all other movable appliances are locked on their location e the locked components in the route need to hold locked until the train pass that portion of route or either the signal to proceed is withdrawn Therefore enough time has been given to guarantee that the approaching train from the route has got enough time to proceed over the route and stop before passing signal Figure 2 determines general objectives of interlocking systems Development of Interlocking Prevents the signaling system entering an unsafe state Physically locks levers in to signal box Levers can only be moved if it is safe to do so Figure 2 General objectives of Interlocking Systems The status information of each field elements will be transferred to train control systems whi
106. ugh the activation of the LCD LCD1 Lib 16L OSCI CLM RCD TIOSO TICH 288 2 85888885 RCITIOSICCP2A RC2 CCPI RC3 SCKISCL RC4 SDUSDA RAZ AN2MREF RCSSDO RCT RXUT RAG ANASSILVDIN RAG 0SC2 CLKO ROO PSPO 1 1 RBO INTD RD2 PSP2 RB1 INTI RD3 PSP3 RB2 INT2 RD4 PSP4 RB3 CCP2B RD5 PSP5 RB4 RD6 PSP6 RB5 PGM RD PSP RBE PGC RB PGD Figure 74 LCD simulation result MRes Thesis Mersedeh Maksabi October 2013 57 CHAPTER SEVEN MRes In Railway System Integration CHAPTER SEVEN 7 Conclusion 7 1 Findings All parts of this project were practically implemented and tested and they work as expected The adopted strategy to run the project has been performed step by step and the expected results have been obtained and presented through the report The performed tasks are as follows Acomprehensive literature review about the railway signalling operating system e Visualisation of the interlocking system through LabVIEW and logical simulation concerning signalling within both straight and reverse routes e Introducing the operational logic based status of each single lever within the interlocking working mechanism through both straight and reverse routes e System optimisation by considering the safety issues restriction and existing standards e Investigating solutions for real time data acquisition e Designing an electr
107. utput 0 TOI PERE RE E E E E E E E E k k k k k k k k k k k k k k k k k k k kk k unsigned char is_sw5_pressed void if PORTDbits RD6 0 delay_ms 10 if PORTDbits RD6 0 return 1 return 0 returnO if the switch is not pressed k kk This routine is to examine that switch 6 is pressed or not ieee No input TK Je If sw2 is pressed gt output 1 if not output 0 k kkk unsigned char is_sw6_pressed void if PORTDbits RD7 0 delay_ms 10 if PORTDbits RD7 0 return 1 return 0 return 0 if the switch is not pressed MRes Thesis Mersedeh Maksabi October 2013 81 Appendix A MRes In Railway System Integration Ill Author Mersedeh Maksabi lll Ill Name Design Optimization Date 12 07 2013 at 20 12 MM MM TH include lt p18f452 h gt Configuration Bits k pragma config PWRT Power up timer disabled pragma config BOR Brown out reset disabled pragma config LVP OFF Low voltage disabled pragma config WDT Watch dog timer disabled pragma config DEBUG OFF Background debugger disabled F XXE kkk kk A AE KEK CO des and Definitions pragma code define LeverlUpperLimit PORTBbits RBO input define LeverIGoUp PORTBbits RB1 hnput

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