EVALSTGAP1S - STMicroelectronics
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1. 1 This configuration is preferred but not mandatory to avoid dissipating power on shunt resistors ky DociD027168 Rev 1 5 18 Connection of two EVALSTGAP1S boards UM1839 2 6 18 Connection of two EVALSTGAP1S boards It is possible to connect two EVALSTGAP1S boards through connectors J1 and J5 the lower board master shall be connected to the uC and the other one slave is configured through the daisy chain connection of the SPI bus Figure 4 Relevant jumper and connector locations for 2 board configuration N J3 slave JP3 slave J2 slave J3 master JP1 JP2 master J2 master J P3 master Connecting two EVALSTGAP1S boards allows implementing independent half bridge or interleaved configuration of power switches Q1 and Q1 The logic side power supply VDD shall be fed to the J6 of the master board that will also supply the slave board through J1 J5 connectors The jumper JP4 and JP6 of each board shall be properly set see Table 4 A setting of the JP4 jaye is not relevant Positive VH and optional negative VL power supplies for each board shall be independently provided by different sources to connectors J2master aNd J2sjaye unless an interleaved operation is required in which case VH GNDISO and VL nets of each board shall be externally connected The jumper JP5 of each board shall be properly configured see Table 5 Table 8 Jumper configurations for SPI settings usin2. November 2014 DoclD027168 Rev 1 1 18 www st com Contents UM1839 Contents 1 Hardware description and configuration 3 2 Connection of two EVALSTGAP1S boards 20220005 6 3 Getting Started 2 22 is ieee Sw lade behets ete de NANG 10 3 1 Using EVALSTGAP1S in standalone mode 005 10 3 1 1 Check AA aE R 10 3 1 2 EVALSTGAP1S board setup example 0200005 10 3 1 3 EVALSTGAP1S board in standalone mode 10 3 1 4 EVALSTGAP1S default parameters nannan aaa 11 3 2 Using EVALSTGAP1S with STEVAL PCC009V2 and STGAP1S evaluation software ee ee eens 11 3 2 1 CHECK MISE mGA NAMA TE DARAGA NAA MAD ga NA ad a ee 11 3 2 2 Single EVALSTGAP1S board setup example 11 3 2 3 Connection to STEVAL PCC009V2 interface board 12 3 2 4 Using two EVALSTGAP1S boards in daisy chain configuration 15 4 REVISION history 2am GRASS BIDANG NAB PRBRASALTEDE HANGA KARERA 17 2 18 DocID027168 Rev 1 KYJ UM1839 Hardware description and configuration 1 Hardware description and configuration The STGAP1S features an SPI interface that is used to set the device parameters enable or disable the device functions and for advanced diagnostic However for an easy device evaluation it is also possible to operate the STGAP1S without using the SPI interface In this case the driver works with default configuration value
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4. 7 or Windows XP PC with a free USB port e EVALSTGAP 1S board e STEVAL PCCOO9V2 interface board e gapDRIVE evaluation software the right version for your OS e Power supply e PWM function generator e 10 pin flat cable and USB MiniUSB cable Single EVALSTGAP1S board setup example VDD 3 3 V from the STEVAL PCC009V2 closing JP4 and JP6 VH from external power supply J2 connector VL GNDISO JP5 closed PWM input signals can be applied to the J3 connector IN IN SOON DoclD027168 Rev 1 11 18 Getting started UM1839 If you have only one PWM signal available To have gate output in phase with input command PWM on IN and IN GND To have gate output out of phase with input command PWM on IN and IN VDD 3 2 3 Connection to STEVAL PCC009V2 interface board The EVALSTGAP1S shall be connected to the interface board and the following steps performed 1 Connect the interface board to the PC through the USB cable the red LED POWER D2 turns on 2 Connect the interface board 10 pin connector to the EVALSTGAP1S J4 connector through the 10 pin flat cable The DIAG1 red LED DL2 on the EVALSTGAP1S turns on 3 Connect the power supply to VH of the EVALSTGAP1S J2 connector and turn it on 4 Start the EVALSTGAP1S evaluation software 5 Click the icon Connect on the top left side of the GUI window to establish a connection between the EVALSTGAP1S and interface boards see Figure 9 Th
5. ky life augmented UM1839 User manual EVALSTGAP1S demonstration board for STGAP1S galvanically isolated single gate driver Introduction The STGAP1S gapDRIVE is a galvanically isolated single gate driver for N channel MOSFETs and IGBTs with advanced protection configuration and diagnostic features The architecture of the STGAP1S isolates the channel from the control and the low voltage interface circuitry through a true galvanic isolation The EVALSTGAP1S board allows evaluating all of the STGAP1S features while driving a power switch with a voltage rating up to 1500 V Power switches in both TO 220 and TO 247 packages can be evaluated and the board allows the connection of a heatsink in order to exploit the ability of the STGAP1S to handle very high power applications In combination with the STEVAL PCCO09V2 communication board and the gapDRIVE TM evaluation software the board allows to easily enable configure or disable all of the driver s protection and control features through the SPI interface Advanced diagnostic is also available thanks to the driver s status registers that can be accessed through the SPI Multiple boards can be connected together and share the same logic supply voltage and control signals in order to evaluate half bridge interleaved or even more complex topologies The board allows implementing the SPI daisy chain when more than one device is used Figure 1 EVALSTGAP1S demonstration board
6. set the driven device number using the drop down list in the software main panel Figure 11 How to drive two EVALSTGAP1S boards with STGAP1S evaluation software Select the daisy chain configuration Single gt One evaluation board Dual gt Two evaluation boards o DIAG2 Remote D Standby V Auto refresh s 200 w ms SW Version 1 3 5431 19010 FW Version UNK When the Dual option is selected the devices parameters can be set independently selecting the Device 1 or Device 2 in the STGAP1S configuration panel Otherwise it is possible to set some parameter values on both devices ticking one or more push pin boxes refer to Figure 12 DoclD027168 Rev 1 15 18 3 Getting started UM1839 Figure 12 How to set the same parameters in both devices Use CRC check 7 eget SD srl clases Destine Miller clamp enabled 2 level tm PD 2LTO Time 2LTO Di 2LTO is performed at each tum OFF 2 70 Tres SENSE GD SENSE Enabled F DESAT ED DESAT Enabled SENSEth DESAT our 16 18 DocID027168 Rev 1 3 UM1839 Revision history 4 3 Revision history Table 10 Document revision history Date 19 Nov 2014 Revision 1 Initial release Changes DocID027168 Rev 1 17 18 UM1839 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST
7. PI and diagnostic interfacing Connector is suitable for interfacing to the STEVAL PCC009V2 universal interface board J5 Board extension connector Used to connect the master EVALSTGAP1S board in 2 board configuration J6 Power supply connector Used to feed supply voltage VDD to the logic control side C plate E plate Load connection Load connection A plate hole for the load current input path IGBT collector A plate hole for the load current output path IGBT emitter 3 DocID027168 Rev 1 3 18 Hardware description and configuration UM1839 In applications requiring galvanic isolation VH and VL must be generated by an isolated power supply If a power supply with suitable isolation is not available the gate driver s supply voltages can be provided through a battery In case the evaluation of driver s performance does not require galvanic isolation any power supply with suitable functional isolation may be used Figure 2 Jumper and connector locations top side pihdhiigjidi Figure 3 Jumper locations bottom side 3 4 18 DoclD027168 Rev 1 UM1839 Hardware description and configuration Table 3 Jumper descriptions Name Type Function JP1 JP2 Configuration jumpers IN and IN sharing in 2 board configuration JP3 Configuration jumper For SPI daisy chaining in 2 board configuration JP4 Configuration jumpe
8. SICs BU amp APPLICATION control INM__ gt O signals INPr VH master JP1 amp JP2 open MASTER JP3 open for daisy chain LIL JL JL JL J p VDD 4 IH TPC INDUSTRIAL i BU Rev2 0 SYSTEM amp APPLICATI a DociD027168 Rev 1 9 18 Getting started UM1839 3 3 1 3 1 1 10 18 Getting started Using EVALSTGAP1S in standalone mode The STGAP1S device can work also without SPI programming using the device default values Check list e EVALSTGAP 1S board e Two power supplies VDD and VH supply voltage Power supply for negative gate driving voltage VL is optional e PWM function generator EVALSTGAP 1S board setup example 1 VDD 3 3 V or 5 V from external power supply J6 connector 2 VH from external power supply J2 connector 3 VL GNDISO JP5 closed 4 PWM input signals can be applied to J3 connector IN IN If you have only one PWM signal available To have gate output in phase with input command PWM on IN and IN GND To have gate output out of phase with input command PWM on IN and IN VDD EVALSTGAP 1S board in standalone mode 1 Connect the power supply to the EVALSTGAP1S VDD J6 connector and turn it on The DIAG1 LED DL2 on the EVALSTGAP1S is turned on The status of the DIAG2 depends on the voltage level forced on the IN pin 2 Connect the power supply to the EVALSTGAP1S VH J2 connector and turn it on Set the SD pin low for at least 105
9. e DIAG1 LED DL2 on the EVALSTGAP1S is switched off 6 Press the Refresh button and verify all fault lights are off If OK jump to the next point otherwise two options are available to clear the faults and make the device operative a Perform a double transition on SD high gt low gt high clicking on the SD button b Perform a status reset clicking on the Reset button and after set the SD button to High 7 Setthe SD button to High 8 Connect IN to GND and applying the PWM on IN the device outputs will follow the input signal In order to read the device status use the Refresh button to update the status indicators according to driver s status registers To customize the device parameters and functions open the STGAP1S configuration panel pushing the relative toolbar icon refer to Figure 9 3 12 18 DocID027168 Rev 1 UM1839 Getting started Figure 9 STGAP1S evaluation software screenshot E SPlfreq BRIMHz Chain Dual Y connect icon p tatus MM CRC eror 4 gapDRIVE configuration oe V Auto refresh CJ 200 w ms SW Version 1 3 5431 19010 FW Version UNK In the new window shown in Figure 10 it is possible to enable or disable the device functionalities and set the device parameters ky DocID027168 Rev 1 13 18 Getting started UM1839 Figure 10 STGAP1S configuration panel Use CRC check F IN deglitch fitter SD soa deo
10. g two EVALSTGAP1S boards Name Function Jumper configurations JP3 master SPI daisy chain configuration OPEN JP3slave SPI daisy chain configuration CLOSED Lines SD and DIAG1 of both STGAP1S drivers are shared whereas it is possible to independently control IN and IN DIAG2 pins of each driver through appropriate lines of the J3master ANd J3slave DocID027168 Rev 1 ky UM1839 Connection of two EVALSTGAP1S boards If the STGAP1S devices are used in single input configuration both IN DIAG2 lines are independently present on the J4master for interfacing with the uC and diagnostic purposes If the two boards are used in half bridge configuration GNDISOgjaye and C master Plate holes shall therefore be connected it is possible to achieve cross conduction prevention by driving both drivers with only two uC lines as shown in Figure 5 Figure 5 Half bridge configuration with hardware shoot through protection gapDRIVE HS gapDRIVE LS In order to use this configuration the STGAP1S shall be used as 2 input device and the JP1 and JP2 jumpers shall be properly set see Table 9 Table 9 Jumper configurations for input signal settings Gate driving configuration Source of IN and IN control signals Jumper configurations JP1 master DON T CARE i R J Single driver Figure 6 3 JP2 maso DON T CARE Half bridge with hardware JP1 master CLOSED shoot through protecti
11. on J3 master _ Figure 7 JP2 master CLOSED Half bridge with independent J3 master for master board JP1 master OPEN input signals Figure 8 J3 slave for slave board JP2 master OPEN 3 DocID027168 Rev 1 7 18 Connection of two EVALSTGAP 1S boards UM1839 Figure 6 Single driver configuration VH control signals INP JP1 amp JP2 don t care ws Ta ag tae 1 j Re E p CAB a JP3 close C IS JE IG Ib gap DRIVE TQPC INDUSTRIAL amp ASICs BU SYSTEM amp APPLICATION Figure 7 Half bridge with hardware shoot through protection configuration VH_slave ig Z krhke Q bi OV vegas FET 1 pa ht e ae E p a k Fay ie bs 3 JP3 closed D TE d for daisy chain b JE db LIL yo I8PC INDUSTRIAL amp ASICs BU Ka SYSTEM amp APPLICATION control j INM gt O T signals NPA VH master JP1 amp JP2 closed R3 Re JP3 open ANNE Ph cate ob MASTER for daisy chain L gt 8 18 A r P i y L JL JL JL 4b 4 VDD TT gapDRIVE I8PC INDUSTRIAL amp ASICs BU SYSTEM amp APPLICATION DocID027168 Rev 1 3 UM1839 Connection of two EVALSTGAP1S boards Figure 8 Half bridge with independent input signal configurations VH_slave control INM iu signals INP gt OU maoy Ip ue To T J SLAVE at JP3 closed Di 3 F for daisy chain I LIHA JL 4 INDUSTRIAL amp A
12. r To feed the STGAP1S with VDD voltage coming from the uC board JP5 Configuration jumper To connect VL and GNDISO if an optional negative power supply VL is not used JP6 Configuration jumper To connect VDD and Vreg when working with VDD 3 3 V JP7 Configuration jumper To bypass shunt resistors when SENSE is not used Table 4 Jumper configurations for VDD power supply Operating voltage Supply voltage source Jumper configurations 7 External power supply JP4 OPEN NDDS AN from J6 JP6 OPEN External power supply JP4 OPEN HAD SN from J6 JP6 CLOSED a HC supply voltage JP4 CLOSED YODER IN from J4 JP6 CLOSED 1 Input signals logic levels shall be coherent with VDD voltage 3 3 5 V Table 5 Jumper configurations for VL power supply Operating voltage 10V lt VL lt 0V Supply voltage source External power supply J2 Jumper configurations JP5 OPEN VL not used VL GNDISO JP5 CLOSED Table 6 Jumper configurations for SPI and input signals settings single EVALSTGAP1S Name Function Jumper configurations IN connection to the optional slave i dp EVALSTGAP1S DONT CARE IN DIAG2 connection to the optional i ae slave EVALSTGAP1S DON TOARE JP3 Connects the SDO to the uC CLOSED Table 7 Jumper configurations for SENSE SENSE function Jumper configurations Used JP7 OPEN Not used JP7 CLOSED
13. s and protections For more details refer to Section 3 1 Using EVALSTGAP1S in standalone mode on page 10 Table 1 STGAP1S electrical specifications Symbol Parameter Min Max Unit VH Positive supply voltage VH vs GNDISO 4 5 1 202 V VL Negative supply voltage VL vs GNDISO GNDIS0 10 GNDISO V VHL _ Differential supply voltage VH vs VL 36 V 4 Integrated 3 3 V voltage regulator input voltage vs 4 5 5 54 VDD V Viocic Logic pins voltage vs GND VDD 0 3 V VjoRM Maximum working voltage across isolation 1500 V Voollector Maximum COLLECTOR GNDISO voltage 12006 v 1 When UVLO is enabled this value is VHon_ max 2 This value is limited by maximum gate source voltage of Q1 3 When UVLO is enabled this value is VLon_ max 4 When JP6 OPEN VDD is not connected to VREG pin refer to STGAP1S DS 5 When JP6 CLOSED VDD is connected to VREG pin refer to STGAP1S DS 6 This value is limited by the voltage rating of Q1 and D5 Table 2 Connector descriptions Name J1 Type Board extension connector Function Used to connect an optional slave EVALSTGAP1S board J2 Power supply connector Used to feed supply voltage VH and optional negative supply voltage VL to the gate driving side J3 Control signals connector Used for control logic inputs and fault signals interfacing J4 Control signals connector Used for the STGAP1S S
14. taka Destine Miller clamp enabled V 2leveltum off 7 2LTO Time 2LTO Disabled ZNO ls petomed at ATO Tre SENSE 3 SENSE Enabled SENSEth DESAT 2 DESAT Enabled 7 DESAT th DESAT avr UVLO on Vdd F VL on vot Latch VH and VL UVLO failures 7 VH on vott Enable VH and VL OVLO protection Z DIAG outputs management 3 Supply voltages protections 3 Use IN as DIAG2 F DIAG1 V SPI and register errors E SPI and register errors 7 VDD supply failure TF VDD supply failure E UVLO of VH or VL UVLO of VH or VL T OVLO of VH or VL FT OVLO of VH or V DESAT or SENSE F DESAT or SENSE E ASC or dead time violation E ASC or dead time violation V Thermal shutdown E Thermal shutdown E Thermal waming Thermal waming P GON GOFF DESAT comp T SENSE resistor SENSE comp Note The CRC error light will blink if the CRC check is not used Use CRC check not ticked in the gapDRIVE configuration panel as in the default settings 14 18 DocID027168 Rev 1 ky UM1839 Getting started 3 2 4 Using two EVALSTGAP 1S boards in daisy chain configuration If you want to drive two EVALSTGAP1S boards refer to dedicated Section 2 Connection of two EVALSTGAP1S boards on page 6 for the board s connection and jumper s settings then follow the steps of Section 3 2 3 Connection to STEVAL PCCO09V2 interface board up to point 5 It is possible to
15. us to clear the fault J3 connector 4 Set the SD pin to the High logic level which depends on VDD value the DIAG1 LED DL2 is switched off 5 The device outputs will now follow the input signals coming from IN and IN bang 3 DocID027168 Rev 1 UM1839 Getting started 3 1 4 3 2 3 2 1 3 2 2 3 EVALSTGAP 1S default parameters e IN DIAG2 configured as input e Active Miller clamp enabled e Desaturation detection enabled Vpesarth 7 V and Ipesa t 250 pA e VDD OVLO function enabled e Thermal shutdown protection enabled e The DIAG1 pin reports the following faults event DESAT events VDD supply failures Missing VH Thermal shutdown Register error R and L e All others features are disabled Using EVALSTGAP1S with STEVAL PCC009V2 and STGAP41S evaluation software Using the EVALSTGAP1S board in connection with the STGAP1S evaluation software and the STEVAL PCC009V2 interface board it is possible to evaluate the device functionalities and driving two EVALSTGAP1S boards implementing independent half bridge or interleaved configuration of power switches The software allows saving the device parameters configuration in a dedicated file that can be reloaded whenever it is necessary for example after the board power on The Save and Load buttons on the bottom left side of the STGAP1S configuration panel Figure 10 have these functions Check list e Microsoft Windows
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