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Infineon C164CM, C164SM User`s Manual

1. Name Physical 8 Bit Description Reset Address Addr Value SP FE12y 09 CPU System Stack Pointer Register FCOO SSCBR FOB4 E 5A SSC Baudrate Register 00004 SSCCON b FFB2 D94 SSC Control Register 00004 SSCEIC b FF76 BB SSC Error Interrupt Control Register 0000 SSCRB FOB2 E594 SSC Receive Buffer XXXXy SSCRIC b FF74 BA SSC Receive Interrupt Control Register 0000 SSCTB FOBO E58 SSC Transmit Buffer 00004 SSCTIC b FF72 B9 SSC Transmit Interrupt Control Register 0000 STKOV FE144 OA CPU Stack Overflow Pointer Register FAOOW STKUN FE16y OB CPU Stack Underflow Pointer Register FCOOy SYSCON b FF124 89 CPU System Configuration Register 0xx0 SYSCON1 b F1iDC E EE CPU System Configuration Register 1 0000 SYSCON2 b F1DO E E8 CPU System Configuration Register 2 0000 SYSCON3 b F1D4 E EA CPU System Configuration Register 3 00004 T121C b F190 E C8 CAPCOM 6 Timer 12 Interrupt Ctrl Reg 00004 T120F F034 E 1A4 CAPCOM 6 Timer 12 Offset Register 0000 T12P F030 E18 CAPCOM 6 Timer 12 Period Register 00004 T131C b F198 E CC CAPCOM6 Timer 13 Interrupt Ctrl Reg 00004 T13P F032 E 19 CAPCOM6 Timer 13 Period Register 00004 T14 FOD2 E 69 HTC Timer 14 Register no T14REL FODO E684 RTC Timer 14 Reload Register no T2 FE40y 20 GPT1 Timer 2 Register 0000 T2CON b FF40 AO GPT1 Timer 2 Control Register 00004 T2IC b FF604 BO GPT1
2. PSW Program Status Word SFR FF10 884 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN uso MB E z vc N rwh rw rw rwh rwh rwh rwh rwh rwh Bit Function N Negative Result Set when the result of an ALU operation is negative C Carry Flag Set when the result of an ALU operation produces a carry bit V Overflow Result Set when the result of an ALU operation produces an overflow Z Zero Flag Set when the result of an ALU operation is zero E End of Table Flag Set when the source operand of an instruction is 80004 or 80p MULIP Multiplication Division In Progress 0 There is no multiplication division in progress 1 A multiplication division has been interrupted USRO User General Purpose Flag May be used by the application software ILVL IEN Interrupt Control Fields Define the response to interrupt requests Described in Chapter 5 ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status after the most recently performed ALU operation They are set by most of the instructions according to specific rules which depend on the ALU or data movement operation performed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags cannot be interpreted as described below because any explicit write to the PSW User s Ma
3. Name Physical 8 Bit Description Reset Address Addr Value CC24IC b F170 E B8 CAPCOM Reg 24 Interrupt Ctrl Reg 0000 CC25IC b F172 E B94 CAPCOM Reg 25 Interrupt Ctrl Reg 0000 CC26IC b F1744 E BAy CAPCOM Reg 26 Interrupt Ctrl Reg 00004 CC271C b F1i76 E BBy CAPCOM Reg 27 Interrupt Ctrl Reg 0000 T7IC b F17Ay E BDy CAPCOM Timer 7 Interrupt Ctrl Reg 0000 T8IC b F17C E BEy CAPCOM Timer 8 Interrupt Ctrl Reg 00004 CC6CIC b Fi7E E BF CAPCOM 6 Interrupt Control Register 0000 XPOIC b F186 E C3 4 CAN1 Module Interrupt Control Register 0000 CC6EIC b F188 E C4 CAPCOM 6 Emergency Interrupt 0000 Control Register XP1IC b F18E E C7 4 Unassigned Interrupt Control Reg 0000 T121C b F190 E C8 amp CAPCOM 6 Timer 12 Interrupt Ctrl Reg 00004 T13IC b F198 E CC CAPCOM 6 Timer 13 Interrupt Ctrl Reg 00004 SOTBIC b F19C E CE Serial Channel 0 Transmit Buffer 00004 Interrupt Control Register XP3IC b F19E ECF PLL RTC Interrupt Control Register 0000 EXICON b F1CO E E0O External Interrupt Control Register 00004 SYSCON2 b F1DO E E8 CPU System Configuration Register 2 00004 SYSCON3 b F1D4 E EA CPU System Configuration Register 3 0000 ODP8 b F1D6 E EB Port 8 Open Drain Control Register 00H EXISEL b F1DA E ED External Interrupt Source Select Reg 0000 SYSCON1 b FiDC EEE CPU System Configuration Register 1 0000 ISNC b F1DE E EF Interrupt S
4. On Chip XBUS 16 Bit Demux id CAN Rev 2 0B active ADC ASCO SSC 10 Bit USART SPI 8 EBC Channels XBUS Control External Bus Contro o d Port 5 t iQ MCB04323_4cm Figure 2 1 C164CM Functional Block Diagram User s Manual 2 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 1 Big Performance in a Small Package It seemed not feasible to put a 16 bit microcontroller into a tiny package such as the TQFP 64 when the Infineon C166 Family was created In the meantime however several improvements were added to the architecture which when combined allow high performance operation of a 16 bit microcontroller in a 64 pin package The combination of the following features was the basis for the realization of a compact microcontroller such as the C164CM Single Chip Mode without reset configuration via PORTO removes the need for configuration devices pull ups pull downs on the PORTO pins so now they can be effectively used for peripherals or IO functions e Serial Interfaces on PORTO allow the removal of Port 3 while retaining the peripherals functionality This reduces the pin count e Modified multiplexed bus mode with 8 bit data and 11 bit address enables the concurrent operation of serial interfaces see above and the external bus interface CAN interface on Port 8 allows the removal of Po
5. Infineon C164CM C164SM technologies Derivatives Parallel Ports Internal Bus CCx g Write Read z Port Output Direction Latch Latch AltDir AItEN AltDataOut AltDatalN Latch lt AltDatalN Pin lt Input Latch MCD04467 P1H 7 0 x 27 24 31 28 Figure 7 7 Block Diagram of a PORT1 Pin with Address and CAPCOM Function User s Manual 7 19 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports Internal Bus lt gt Port Output Direction Latch Latch AltDir 1 AItEN AltDataOut Driver Clock Input Latch MCB04348 P1H 3 0 P1L 7 0 Figure 7 8 Block Diagram of a PORT1 Pin with Address and Alternate Input Output Function User s Manual 7 20 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports 7 5 Port 5 This 8 bit input port can only read data There is no output latch or direction register Data written to P5 will be lost P5 Port 5 Data Register SFR FFA24 D1 Reset Value XXXX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 r r r r r r r r Bit Function P5 y Port data register P5 bit y Read only Alternate Functions of Port 5 Each
6. Table 11 4 ASCO Asynchronous Baudrate Generation for fcpy 33 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 1 031 Mbit s 0 0 00004 19 2 kbit s 1 38 0 5 00344 00354 2 3 0 5 00224 00234 9600 bit s 0 4 0 5 006A 006B 0 9 0 5 00464 00474 4800 bit s 0 4 0 1 00D5 00D6 0 2 0 5 008E 008F 2400 bit s 0 2 0 1 01AC 01AD 0 2 0 2 011D 011E 1200 bit s 0 0 0 1 035A 035B 0 2 0 0 023B 023Cy 600 bit s 0 0 0 0 06B5 06B6 0 1 0 0 04784 04794 125 bit s 7 1 1FFF 0 0 157C4 84 bit s 0 996 1FFF User s Manual 11 13 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Asynchronous Synchronous Serial Interface Synchronous Mode Baud Rates For synchronous operation the baud rate generator provides a clock with 4 times the rate of the established baud rate The baud rate for synchronous operation of serial channel ASCO can be determined by the following formula SOBRL cPU 4 x 2 lt SOBRS gt x Bgync fopu s Bs ee PERRA Syne 4x 2 lt SOBRS gt x lt SOBRL gt 1 lt SOBRL gt represents the contents of the reload register taken as unsigned 13 bit integers lt SOBRS gt represents the value of bit SOBRS either 0 or 1 taken as integ
7. MCT02605 User s Manual 17 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 5 Capture Mode Each of the three capture compare channels can be programmed individually for capture mode via bitfields CMSELx in register CC6MSEL In capture mode the contents of timer T12 are copied to the channel s compare register CC6x upon a selectable transition rising falling or both at the associated pin CC6x Capture mode can be enabled either in edge aligned mode or in center aligned mode Interrupts may be generated selectively at each transition of the capture input signal Pins CC6x used as inputs in capture mode are sampled every CPU clock period When evaluating a series of capture events it must be noted that every capture event overwrites the previous value in the respective register CC6x The control software must be designed to retrieve the capture values before they are overwritten User s Manual 17 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 6 Combined Multi Channel Modes Note Multi channel modes are available in the full function module only When operating in a combined multi channel mode the output signals CC6x and COUTE6x are controlled by the compare timers and additional conditions Multi channel modes are selected via register CC6MCON In these modes a prede
8. Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Bit Function BCEN Block Commutation Enable 0 The multi channel PWM modes of the 16 bit capture compare channels selected by bitfield MPWM are disabled J The multi channel PWM modes are enabled Note Before bit BCEN is set all required PWM compare outputs should be programmed to operate as compare outputs by writing to register CC6MSEL BCERR Block Commutation Mode Error Flag 0 No error condition 1 An error condition in rotate right or rotate left mode has occurred After a transition at CC6POSx all CC6POSx inputs are at high or low level A wrong follower condition has occurred see description of bit BCEM If the block commutation interrupt is enabled EBCE 1 aCAPCOM6 emergency interrupt will also be generated BCERR must be cleared by software EBCE Enable Block Commutation Mode Error Interrupt 0 Block commutation mode error does not generate an interrupt p The emergency interrupt is activated for a block commutation mode error Refer to the description of bits BCERR and BCEM MPWM Multi channel PWM Mode Selection This bitfield selects the output signal pattern in all multi channel PWM modes also refer to bitfield BCM 00 Three phase block commutation mode 01 Four phase multi channel PWM mode 10 Five phase multi channel PWM mode 11 Six phase multi channel PWM mode
9. Infineon C164CM C164SM technologies Derivatives System Reset 20 3 Application Specific Initialization Routine After a reset the modules of the C164CM must be initialized to enable their operation on a given application This initialization depends on the task to be performed by the C164CM in that application and on some system properties such as operating frequency external circuitry connected etc Typically the following initializations should be done before the C164CM is prepared to run the actual application software Memory Areas The external bus interface can be reconfigured after an external reset because register BUSCONO is initialized to the slowest possible bus cycle configuration The programmable address windows can be enabled in order to adapt the bus cycle characteristics to various memory areas or peripherals Also after a single chip mode reset the external bus interface can be enabled and configured The internal program memory if available can be enabled and mapped after an external reset in order to use the on chip resources After a single chip mode reset the internal program memory can be remapped or disabled in order to utilize external memory partially or completely Programmable program memory can be programmed for instance with data received over a serial link Note Initial Flash or OTP programming will rather be done in bootstrap loader mode System Stack The default setup for the
10. a b c d POH 7 SCLK D15 SCLK AD15 POH 6 MTSR D14 MTSR AD14 POH 5 MRST D13 MRST AD13 POH POH 4 RxDO D12 RxDO AD12 POH 3 TxDO D11 TxDO AD11 POH 2 D10 A10 AD10 POH 1 D9 AQ AD9 POH O D8 A8 AD8 Port 0 POL 7 D7 D7 AD7 AD7 POL 6 D6 D6 AD6 AD6 POL 5 D5 D5 AD5 AD5 POL 4 D4 D4 AD4 AD4 POL POL 3 D3 D3 AD3 AD3 POL 2 D2 D2 AD2 AD2 POL 1 D1 D1 AD1 AD1 POL O DO DO ADO ADO General Purpose 8 Bit 16 Bit 8 Bit 16 Bit Input Output Demux Bus Demux Bus MUX Bus MUX Bus MCA05129 Figure 7 4 PORTO IO and Alternate Functions Figure 7 5 shows the structure of a PORTO pin User s Manual 7 14 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives Parallel Ports Internal Bus Write Read Direction Port Output Latch Latch AltDir AItEN AltDataOut Driver Clock AltDatalN 4 Input Latch MCB04345 POH 7 0 POL 7 0 Figure 7 5 Block Diagram of a PORTO Pin User s Manual 7 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports 7 4 PORT1 The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halves of PORT1 can be written e g via a PEC transfer without affecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DP1H and DP1L P1L PORT1 Low Regi
11. 11 8 7 4 3 0 Value POCON20 FOAA 55 P20 12 P20 8 P20 5 4 P20 1 0 0000 RSTOUT CLKOUT ALE WR RD FOUT POCON8 FO92 49 P8 3 0 00224 POCON1H F086 43 P1H 7 4 P1H 3 0 40011 POCONIL F084 42 P1L 7 4 P1L 3 0 10011 POCONOH F082 414 POH 7 4 POH 3 0 0011 POCONOL F080 40 POL 7 4 POL 3 0 10011 User s Manual 7 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports Port Driver Temperature Compensation The temperature compensation for the port drivers provides driver output characteristics which are stable within a certain band of parameter variation over the specified temperature range e g 40 C 125 C The drive capability of the output drivers is reduced when the temperature is not in the upper range to improve the EME behavior The temperature compensation is based on a reference clock signal which is derived from the CPU clock by a programmable divider see Figure 7 3 an P face Prog Divider Reference Clock N TCDIV 1 MCB05124 Figure 7 3 Temperature Compensation Clock Generation The clock divider is programmed via bitfield TCDIV in register PTCR TCDIV can be calculated using the following formula TCDIV Integer fcpu x 6 7 2 fepy in MHz Example for fcp 25 MHz TCDIV Integer 25 x 6 7 2 165 A5 Generally temperature compensati
12. In Center Aligned Mode the compare timer T12 counts up starting at 00004 Upon reaching the period value stored in register T12P the count direction is reversed and the timer counts down The output signals are switched to their active passive state upon a match with the compare value while counting up down Center aligned mode is supported by compare timer T12 only The compare timers T12 and T13 are free running timers which are clocked with a programmable frequency of fcpy to fcpu 128 The respective output signals are changed if appropriate when the timer reaches the programmed compare value For switching the output signals COUT60 COUT62 the contents of the timer plus the offset value are compared against the compare value Timer T12 can operate in either edge aligned or center aligned PWM mode see Figure 17 3 with or without a constant edge delay a or b in Figure 17 3 Timer T13 can operate in edge aligned mode without edge delay Compare Timer T12 in Edge Aligned Mode a Standard PWM b Standard PWM with dead time torr Period Value Period Value Compare Compare Value Value 0000 Offset CC6x CC6x COUT6x COUT6x MCB04110 Compare Timer T12 in Center Aligned Mode c Symmetrical PWM d Symmetrical PWM with dead time toff Period Value Period Value Compare Value Compare Value 0000 Offset CC6x CC6x Initial value 0 COUT6x
13. Infineon C164CM C164SM technologies Derivatives Table of Contents Page 19 1 Functional Blocks of the CAN Module 000e ee eae 19 2 19 2 General Functional Description 00 00 cee eee eee 19 7 19 2 1 CAN Interrupt Handling 00 c ee eee 19 9 19 2 2 Configuration of the Bit Timing 0 0 eee eee eee 19 11 19 2 3 Mask Registers ac chetaderearast ig A Ei eeeted B RR RAS aod 19 15 19 3 The Message Object issseecus causae uy RE EUR E pe RE 19 18 19 4 Controlling the CAN Module leeeeselleesenne 19 30 19 5 Configuration Examples for Message Objects 19 34 19 6 CAN Application Interface 0 0 ee 19 36 20 System Reset i cx case x xxu p tar xx RERO LIOS OCDE Gp d 20 1 20 1 Reset SourceS 4233 xi ea e cox d Be ee Phe ee eee ee ace GR En 20 2 20 2 Status After Reset 0 000 cee ee 20 5 20 3 Application Specific Initialization Routine 0 000 20 9 20 4 System Startup Configuration 0 0 0 eee eee 20 12 20 4 1 System Startup Configuration upon an External Reset 20 13 20 4 2 System Startup Configuration at Single Chip Mode Reset 20 19 20 5 System Configuration via Software 0 00 eee 20 21 21 Power Management 00000 0c cece eee 21 1 21 1 lel T ae a a ee er ee ee ee ere ere 21 4 21 2 Sleep Mode 2 s ctectiuaateuded X RR SN NRW RODA RR ER Pa E 21 6 21 3 Power Down Mode 3 x
14. P Interrupt p Request Mode 1 CCMODx Input Port Ji Clock Toggle Latch h Cexo Mode 0 CCMODz Compare Reg CCz Interrupt gt Request X 19 16 not all channels are connected to port pins and interrupt nodes y 7 8 Z 27 24 MCB05122 Figure 16 10 Double Register Compare Mode Block Diagram User s Manual 16 20 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 In this configuration example the same timer allocation was chosen for both compare registers but each register may also be allocated individually to one of the two timers of the CAPCOM unit In the timing example for this compare mode Figure 16 11 the compare values in registers CCx and CCz are not modified Note The pins CCzlO which do not serve for double register compare mode may be used for general purpose IO Contents of Ty FFF Compare Value CCz Compare Value CCx Reload Value lt TyREL gt 0000 Interrupt Requests i i TyIR CCxIR CCxIR TyIR CCxIR CCxIR TyIR State of CCxlO fF l S e 686 x 19 16 y 7 8 Z 27 24 MCB05123 Figure 16 11 Timing Example for Double Register Compare Mode Note Double Register Compare Mode is reasonable only on channel pairs with an associated output pin User s Manual 16 21 V1 0 2002 02 Infineon C164CM C164SM tech
15. _ Infineon C164CM C164SM technologies Derivatives Architectural Overview Peripheral Timing Internal operation of the CPU and peripherals is based on the CPU clock fep The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal gated to the peripherals is independent from the clock signal that feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections describing each peripheral Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The following addressing mechanisms allow access to the SFRs Indirect or direct addressing with 16 bit mem addresses must guarantee that the used data page pointer DPPO DPP3 selects data page 3 Accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers Short 8 bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area Short 8 bit reg addresses to the extended ESFR area require switching to the 512 Byte Extended SFR area Th
16. Bit Function CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode i e the mechanism by which the internal CPU clock is generated from the externally applied XTAL1 input clock Note RPOH is initialized during the reset configuration and permits to check the current configuration This configuration can be changed via register RSTCON see Section 20 5 The layout of register RPOH is the same as for other devices of the C166 Family Precautions and Hints The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set e PORT1 will output the intra segment address as long as at least one of the BUSCON registers selects a demultiplexed external bus even for multiplexed bus cycles Not all address windows defined via registers ADDRSELx may overlap each other The operation of the EBC will be erroneous in such a case See Address Window Arbitration on Page 9 21 The address windows defined via registers ADDRSELx may overlap internal address areas Internal accesses will be executed in this case For any access to an internal address area the EBC will remain inactive see Section 9 5 User s Manual 9 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 5 EBC Idle State When the external bus interface is enabled but no external access is currently executed the EBC is idle
17. Infineon C164CM C164SM technologies Derivatives Register Set 23 Register Set This chapter summarizes all registers implemented in the C164CM and explains the description format used in the chapters which describe the functions and layout of the Special Function Registers SFRs For easy reference the registers are ordered according to two different keys except for GPRs Ordered by address to identify which register a given address references Ordered by register name to find the location of a specific register 23 1 Register Description Format In their respective chapters the functions and the layout of the SFRs are described in a specific format which provides various details about each special function register The example below shows how to interpret these details REG NAME Name of Register E SFR A16 A8 Reset Value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read empty for byte registers std hw ys js E bitfield D E F rw wh rw r Ww rw Bit Function bit field name Explanation of bit field name Description of the functions controlled by the different possible values of this bit field Elements REG NAME Short name of this register A16 A8 Long 16 bit address Short 8 bit address SFR ESFR XReg Register space SFR ESFR or External XBUS Register CNR Register contents after reset 0 1 defined value X unde
18. The C164CM provides 2 KBytes of IRAM OO FFFF OO FFFF IRAM SFR 00 F000 X Peripherals e di 00 E000 o Oo aii S c A 00 F600 Reserved H V 00 F200 00 C000 00 F000 00 EF00 CN o D a Ext Memory GS Reserved Oo a 00 8000 00 E000 Note New XBUS peripherals will be preferably placed into the reserved areas which now access external memory bus cycles executed MCA05132 Figure 3 3 System Memory Map User s Manual 3 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization Note The upper 256 Bytes of the SFR area the ESFR area and the Internal RAM are bit addressable see shaded blocks in Figure 3 3 Code accesses are always made on even byte addresses The highest possible code storage location in the Internal RAM is either O0 FDFE for single word instructions or 00 FDFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from Internal RAM to the SFR area is not supported and causes erroneous results Any word and byte data in the Internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the internal RAM is 00 FDFE F
19. 12 12 User s Manual 16 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 16 1 CAPCOM2 Timers The primary use of the timers T7 and T8 is to provide two independent time bases 16 TCL maximum resolution for the capture compare registers of the CAPCOM2 unit but they may also be used independent of the capture compare registers The basic structure of the two timers is identical but the selection of input signals is different for timer T7 and timer T8 see Figure 16 3 and Figure 16 4 Reload Reg TXREL Input Control ceu GPT1 Timer T3 Over Underflow Interrupt Request Txl TxM x27 TXxl MCB05088 Figure 16 3 Block Diagram of CAPCOM Timer T7 Reload Reg TXREL fopu CAPCOM Timer Tx Abba GPT1 Timer T3 q Over Underflow x 8 TxM MCB05089 Figure 16 4 Block Diagram of CAPCOM Timer T8 User s Manual 16 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 The functions of the CAPCOM timers are controlled via the bit addressable 16 bit control register T78CON The high byte of T78CON controls T8 the low byte of T78CON controls T7 The control options are identical for both timers except for external input T78CON CAPCOM Timer 7 8 Ctrl Reg SFR FF20 90 Reset Value 0000
20. After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the initial CPU activity Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the C164CM s address space thus it is not directly accessible by the programmer However the IP can be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations IP Instruction Pointer Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ip r w h Bit Function ip Specifies the intra segment offset from which the current instruction is to be fetched IP refers to the current segment lt SEGNR gt User s Manual 4 19 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Code Segment Pointer CSP This non bit addressable register selects the code segment being used at run time to access instructions The lower 8 bits of register CSP select one of up to 256 segments of 64 KBytes each the upper 8 bits are reserved for future use du Segment Pointer SFR FE08 044 Reset Valu
21. BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change Interrupt value in the Interrupt Register if it is pending Using byte accesses to the lower half will avoid this User s Manual 19 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 2 1 CAN Interrupt Handling The on chip CAN module has one interrupt output It is connected through a synchronization stage to a standard interrupt node in the C164CM in the same manner as all other interrupts of the standard on chip peripherals All control options are available for this interrupt such as enabling disabling level and group priority and interrupt or PEC service see note below The on chip CAN module is connected to an XBUS interrupt control register As for all other interrupts the node interrupt request flag is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels can execute only single predefined data transfers there are no conditional PEC transfers PEC service can be used only if the respective request is known to be generated by one specific source and on condition that no other interrupt request will be gen
22. SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 625 kbit s 0 0 0000 19 2 kbit s 1 7 1 4 001F 0020 3 3 1 4 00144 00154 9600 bit s 0 2 1 4 00404 00414 1 0 1 4 002Ap 002B4 4800 bit s 0 2 0 6 00814 00824 1 0 0 2 0055 0056 2400 bit s 0 2 0 2 01034 01044 0 4 0 2 OOAC 0O0AD 1200 bit s 0 2 0 4 02074 02084 0 1 0 2 015A 015By 600 bit s 0 1 0 0 0410 0411 0 1 0 1 02B5 02B6 75 bit s 1 7 1FFF 0 0 0 0 15B2 15B3y 50 bit s 1 796 1FFF User s Manual 11 12 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Asynchronous Synchronous Serial Interface Table 11 3 ASCO Asynchronous Baudrate Generation for fcpy 25 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 781 kbit s 0 2 0000 19 2 kbit s 1 7 0 8 00274 00284 0 5 3 1 001A 001B 9600 bit s 0 5 0 8 0050 0051 0 5 1 4 00354 00364 4800 bit s 0 5 0 2 00A1 00A2 4 0 5 0 5 006B 006C 2400 bit s 0 2 0 2 0145 0146 0 0 0 5 00D8 00D9 1200 bit s 0 0 0 2 028A 028B 0 0 0 2 01B1 01B2 600 bit s 0 0 0 1 0515 0516 0 0 0 1 03634 03644 95 bit s 0 4 1FFF 0 0 0 0 1569 156A 63 bit s 1 0 1FFF
23. The devices may be offered in different packages temperature ranges and speed classes Additional standard and application specific derivatives are planned and are in development Note Not all derivatives will be offered in all temperature ranges speed classes packages or program memory variations Information about specific versions and derivatives will be made available with the devices themselves Contact your Infineon representative for up to date material Note As the architecture and the basic features such as the CPU core and built in peripherals are identical for most of the currently offered versions of the C164CM descriptions within this manual that refer to the C164CM also apply to the other variations unless otherwise noted User s Manual 1 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Introduction 1 2 Summary of Basic Features The C164CM devices are very compact members of the Infineon family of full featured 16 bit single chip CMOS microcontrollers The C164CM combines high CPU performance up to 12 5 million instructions per second with high peripheral functionality and provides a means for power reduction Several key features contribute to the high performance of the C164CM the indicated timings refer to a CPU clock of 25 MHz High Performance 16 bit CPU with Four Stage Pipeline e 80 ns minimum instruction cycle time with most instructions executed in 1 cycle
24. The lower 4 pins of Port P1H P1H 3 P1H 0 can be programmed individually to this fast interrupt mode where the trigger transition rising falling or both also can be selected The External Interrupt Control register EXICON controls this feature for all 4 pins EXICON External Intr Ctrl Reg ESFR F1CO E0 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E EXISES EXI2ES EXHES EXIOES rw rw rw rw Bit Function EXIxES External Interrupt x Edge Selection Field x 7 0 00 Fast external interrupts disabled standard mode 01 Interrupt on positive edge rising 10 Interrupt on negative edge falling 11 Interrupt on any edge rising or falling Note The fast external interrupt inputs are sampled every 2 TCL The interrupt request arbitration and processing however is executed every 8 TCL The interrupt control registers listed below CC11IC CC8IC control the fast external interrupts of the C164CM These fast external interrupt nodes and vectors are named according to the C167 s CAPCOM channels CC11 CC8 so interrupt nodes receive identical names throughout the architecture See register description below User s Manual 5 27 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions CCxIC CAPCOM x Intr Ctrl Reg SFR See Table 5 9 Reset Value 00 15 14 1
25. User s Manual 17 27 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Bit Function BCPOL Machine polarity Valid only in multi channel PWM mode 0 Only the COUT6n outputs are switched to the timer T13 output signal during the active phase in multi channel PWM mode CMSELn3 must be set for that functionality 1 All enabled compare outputs COUT6n and CCe6n are switched to the timer T13 output signal during their active phase in multi channel PWM mode BCEM Error mode select bit Valid only in block commutation mode 0 A wrong follower condition is not notified as an error T A wrong follower condition in rotate right or rotate left mode sets flag BCERR if EBCE is set Note When a multi channel PWM mode is initiated the first time after reset CCOMCON must be written twice The first write operation is with bit BCEN cleared and all other bits set cleared as required BCM must be 00 for idle mode the second write operation has the same CC6MCON bit pattern as the first write operation but with BCEN set After this second CC6MCON write operation timer T12 can be started setting CT12R in CTCON and thereafter BCM can be put into a mode other than the idle mode User s Manual 17 28 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives CC6MSEL Capture Compare Unit CAPCOM6 CAPCOM6 Mode Select Reg ESFR F036 1B Rese
26. 0E Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL4 Address Select Register 4 SFR FE1E 0F Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw Bit Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONX ADDRSELx register pair See Table 9 3 RGSAD Range Start Address Defines the upper bits of the start address of the respective address area See Table 9 3 Note There is no register ADDRSELO because register BUSCONO controls all external accesses outside the four address windows of BUSCONA BUSCON1 within the complete address space User s Manual 9 19 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Definition of Address Areas The four register pairs BUSCON4 ADDRSEL4 BUSCON1 ADDRSEL1 allow definition of four separate address areas within the address space of the C164CM Within each of these address areas external accesses can be controlled by one of the four different bus modes They are independent of each other and of the bus mode specified in register BUSCONO Each ADDRSELx register so to say cuts out an address window within which the parameters in register BUSCONx are used to control external accesses The range start address of such a window defines the upper address bits which are not used within the address window of the specified
27. 8 16 32 64 128 256 512 1024 Input Frequency 4 125 2 063 1 031 515 63 257 81 128 91 64 453 32 227 MHz MHz MHz kHz kHz kHz kHz kHz Resolution 242 485 970 1 94 3 88 7 76 15 52 31 03 ns ns ns us us us us us Period 15 89 31 78 63 55 127 10 254 20 508 40 1 017 2 034 ms ms ms ms ms ms S S User s Manual 16 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Counter Mode The bits TxM in SFR T78CON select between timer mode or counter mode for the respective timer In Counter mode TxM 1 the input clock for a timer can be derived from the overflows underflows of timer T3 in block GPT1 Additionally timer T7 can be clocked by external events Either a positive a negative or both a positive and a negative transition at pin T7IN alternate port input function can be selected to cause an increment of T7 When T8 is programmed to run in counter mode bit field Txl is used to enable the overflows underflows of timer T3 as the count source This is the only option for T8 and it is selected by the combination Txl 000g When bit field Txl is programmed to any other valid combination the respective timer will stop When T7 is programmed to run in counter mode bit field Txl is used to select the count source and transition if the source is the input pin which should cause a count trigger see description of T78CO
28. Note In emulation mode pin PO 15 POH 7 is inverted i e the configuration 111 would select direct drive in emulation mode o Emulation mode can only be activated upon an external reset EA 0 Pin POL O is not evaluated upon a single chip reset EA 1 User s Manual 20 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Adapt Mode Pin POL 1 ADP selects the Adapt Mode when latched low at the end of reset In this mode the C164CM goes into a passive state similar to its state during reset The pins of the C164CM float to tristate or are deactivated via internal pull up pull down devices as described for the reset state Additionally the RSTOUT pin floats to tristate rather than being driven low The on chip oscillator and the realtime clock are disabled This mode allows a C164CM mounted to a board to be virtually switched off This enables an emulator to control the board s circuitry even though the original C164CM remains in place The original C164CM may resume control of the board after a reset sequence with POL 1 high Please note that adapt mode overrides any other configuration via PORTO Default Adapt Mode is off Note When XTAL1 is fed by an external clock generator while XTAL2 is left open this clock signal may also be used to drive the emulator device However if a crystal is used the emulator device s oscillator can use this crystal only i
29. Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TxDO is configured as output so the C164CM can return the identification byte Note Even if the internal ROM OTP Flash is enabled no code can be executed out of it while the C164CM is in BSL mode 1 The external host should not send the zero byte before the end of the BSL initialization time see Figure 15 1 to ensure that it is correctly received User s Manual 15 3 V1 0 2002 02 _ e e Infineon technologies C164CM C164SM Derivatives Memory Configuration after Reset Bootstrap Loader After reset in Bootstrap Loader mode the configuration i e the accessibility of the C164CM s memory areas differs from the standard case Pin EA is not evaluated when BSL mode is selected and accesses to the internal code memory are partly redirected while the C164CM is in BSL mode see Table 15 1 All code fetches are made from the special Boot ROM while data accesses read from the internal code memory Data accesses will return undefined values on ROMless devices Note The code in the Boot ROM is not an invariant feature of the C164CM User software should not try to execute code from the internal ROM area while the BSL mode is still active as these fetches will be redirected to the Boot ROM The Boot ROM will also move to segment 1 when the internal ROM area is mapped to segment 1 Table
30. frSegi frSego min PB1 PB2 1 58 2x 43 x bit time PB2 _ S __ 2x 13x10us 4us 19 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 2 3 Mask Registers Messages can use either standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incoming message determines whether the standard 11 bit mask in Global Mask Short GMS or the 29 bit extended mask in Global Mask Long UGML amp LGML is to be used Bits holding a 0 are don t care that is do not compare the message s identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message UMLM amp LMLM for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of the identifier Note The Mask of Last Message is ANDed with the Global Mask that corresponds to the incoming message GMS Global Mask Short XReg EF06 Reset Value UFUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 1 1 1 1 1 ID28 21 rw r r r r r rw Bit Function ID28 18 Identifier 11 bit Mask to filter incoming messages with standard identifier User s Manual 19 15 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives
31. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T8R T8M T8l T7R T7M T7I z rw z rw rw z rw s rw rw Bit Function Txl Timer Counter x Input Selection Timer Mode TxM 0 Input Frequency fopy 2 X 9 See also table below for examples Counter Mode TxM 1 000 Overflow Underflow of GPT1 Timer 3 001 Positive rising edge on pin T7IN 010 Negative falling edge on pin T7IN 011 Any edge rising and falling on pin T7IN 1XX Reserved TxM Timer Counter x Mode Selection 0 Timer Mode Input derived from internal clock 15 Counter Mode Input from External Input or T3 TxR Timer Counter x Run Control 0 Timer Counter x is disabled 1 Timer Counter x is enabled 1 This selection is available for timer T7 Timer T8 will stop at this selection The timer run flags T7R and T8R allow the timers to be enabled or disabled The following description of the timer modes and operation always applies to the enabled state of the timers that is the respective run flag is assumed to be set to 1 In all modes the timers always count upwards The current timer values are accessible for the CPU in the timer registers Tx which are non bitaddressable SFRs When the CPU writes to a register Tx in the state immediately before the respective timer increment or reload is to be performed the CPU write operation has priority and the increment or reload is disabled to guarantee correct timer operation User s M
32. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O0 i i i i i i i i i i i i SLEEP CON a rw Bit Function SLEEPCON SLEEP Mode Configuration mode entered upon the IDLE instruction 00 Normal IDLE mode 01 SLEEP mode with RTC running 10 Reserved 11 SLEEP mode with RTC and oscillator stopped Note SYSCON I is write protected after the execution of EINIT unless it is released via the unlock sequence see Table 21 6 21 3 Power Down Mode The microcontroller can be switched to Power Down mode to reduce the power consumption to a minimum Clocking of all internal blocks is stopped RTC and oscillator optionally but the contents of the internal RAM are preserved through the voltage supplied via the Vpp pins The watchdog timer is stopped in Power Down mode This mode can be terminated by an external hardware reset only by asserting low level on the RSTIN pin This reset will initialize all SFRs and ports to their default state but will not change the contents of the internal RAM There are two levels of protection against unintentionally entering Power Down mode First the PWRDN Power Down instruction used to enter this mode has been implemented as a protected 32 bit instruction Second this instruction is effective only if the NMI Non Maskable Interrupt pin is externally pulled low while the PWRDN instruction is executed The microcontroller wi
33. A DPP register can be updated via any instruction capable of modifying an SFR Note Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction which updates the DPP register User s Manual 4 23 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives Central Processing Unit CPU DPP Registers Affer reset or with segmentation disabled the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases DPP3 11 14 Bit DPP2 10 Intra Page Address DPP1 01 content of DPPx DPP0 00 16 Bit Data Address 15 14 0 concatenated with MCA02264 Figure 4 6 User s Manual Addressing via the Data Page Pointers 4 24 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Context Pointer CP This non bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 wordwide and or bytewide GPRs inen Pointer SFR FE10 08 Reset Value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 cp 0 r r r r rw r Bit Function cp Modifiable portion of register CP Spec
34. Bit Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx Only the least significant two bits of DPPx are significant when segmentation is disabled The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended instructions and PEC data transfers After reset the Data Page Pointers are initialized in such a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows access to data pages 3 O within segment 0 as shown in Figure 4 6 If the user does not want to use data paging no further action is required Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DPP register selected by the upper two bits of the 16 bit address The contents of the selected DPP register specify one of the 1024 possible data pages This data page base address together with the 14 bit page offset forms the physical 24 bit address the selectable part is driven to the address pins In non segmented memory mode only the two least significant bits of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a non segmented memory model is selected to avoid unexpected results
35. Disconnects the CAN TXD output from the port logic Clears the error counters e Resets the busoff state e Switches the Control Register s low byte to 01 Leaves the Control Register s high byte and the Interrupt Register undefined Does not change other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state of course The value 01 in the Control Registers low byte prepares for the module initialization CAN Module Activation The CAN module is disabled after a reset Before it can be used to receive or transmit messages the application software must activate the CAN module Three actions are required for this purpose General Module Enable globally activates the CAN module by setting bit XPEN in register SYSCON after setting the corresponding selection bit in register XPERCON Pin Assignment selects a pair of port pins to connect the CAN module to the external transceiver This is done via bitfield IPC in register PCIR Module Initialization determines the functionality of the CAN module baudrate active objects etc This is the major part of the activation and is described below User s Manual 19 31 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Module Initialization Module initialization is enabled by setting bit INIT in the control register CSR
36. FBy CPU General Purpose Word Reg R11 UUUUL R12 CP 24 FC CPU General Purpose Word Reg R12 UUUU R13 CP 26 FDyg CPU General Purpose Word Reg R13 UUUU R14 CP 28 FE CPU General Purpose Word Reg R14 UUUU R15 CP 30 FFy CPU General Purpose Word Reg R15 UUUU User s Manual 23 2 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set The first 8 GPRs R7 RO may also be accessed bytewise Other than with SFRs writing to a GPR byte does not affect the other byte of the respective GPR The respective halves of the byte accessible registers receive special names Table 23 2 General Purpose Byte Registers Name Physical 8 bit Description Reset Address Address Value RLO CP 0 FOy CPU General Purpose Byte Reg RLO UU RHO CP 1 Fiy CPU General Purpose Byte Reg RHO UU RL1 CP 2 F2 CPU General Purpose Byte Reg RL1 UU RH1 CP 3 F3y CPU General Purpose Byte Reg RH1 UU RL2 CP 4 F4y CPU General Purpose Byte Reg RL2 UU RH2 CP 5 F5y CPU General Purpose Byte Reg RH2 UU RL3 CP 6 F6 CPU General Purpose Byte Reg RL3 UU RH3 CP 7 F7y CPU General Purpose Byte Reg RH3 UU RL4 CP 8 F8 CPU General Purpose Byte Reg RL4 UU RH4 CP 9 F9y CPU General Purpose Byte Reg RH4 UU RL5 CP 10 FAy CPU General Purpose Byte Reg RL5 UU RH5 CP 11 FB4 CPU General
37. RCS RTC Clock Source not affected by a reset 0 Main oscillator 1 Reserved SCS SDD Clock Source not affected by a reset 0 Main oscillator qs Reserved CLKCON Clock State Control 00 Running on configured basic frequency 01 Running on slow down frequency PLL remains ON 10 Running on slow down frequency PLL switched OFF 11 Reserved Do not use this combination CLKREL Reload Counter Value for Slowdown Divider SDD factor CLKREL 1 CLKLOCK Clock Signal Status Bit 0 Main oscillator is unstable or PLL is unlocked 15 Main oscillator is stable and PLL is locked Note SYSCON except for bitfield SYSRLS is write protected after the execution of EINIT unless it is released via the unlock sequence see Table 21 6 User s Manual 21 13 V1 0 2002 02 Infineon technologies 7 C164CM C164SM Derivatives Power Management State Transition when writing xx to CLKCON __ Automatic Transition after clock is stable i e CLKLOCK 1 01 00 MCA04478 Figure 21 4 Clock Switching State Machine Table 21 3 Clock Switching State Description State PLL f cPu CLK Note Number Status Source CON 1 Locked Basic 00 Standard operation on basic clock frequency 2 Locked SDD 01 SDD operation with PLL On Fast without delay or manual switch back from 5 to basic clock frequency 3 Transient SDD 00 Intermediate st
38. Reg ESFR F1D6 EBj Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP8 ODP8 ODP8 ODP8 3 2 1 0 ww Bit Function ODP8 y Port 8 Open Drain control register bit y ODP8 y 0 Port line P8 y output driver in push pull mode ODP8 y 1 Port line P8 y output driver in open drain mode Alternate Functions of Port 8 All Port 8 lines serve as capture inputs or compare outputs CCxlO for the CAPCOM2 unit see Table 7 5 When a Port 8 line is used as a capture input the state of the input latch representing the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input If an external capture trigger signal is used the direction of the respective pin must be set to input If the direction is set to output the state of the port output latch will be read because the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note that in the output configuration no external device may drive the pin otherwise conflicts would occur When a Port 8 line is used as a compare output compare modes 1 and 3 the compare event or the timer overflow in compare mode 3 directly affects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the
39. Request CCMODx Input Interrupt Clock CAPCOM Timer Ty Request x 27 24 19 16 y 7 8 MCB05120 Figure 16 5 Capture Mode Block Diagram Note Capture events can also be triggered by inputs CC311O CC28 0 However these channels have no dedicated interrupt request See Section 16 7 for a possible solution User s Manual 16 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 To use the respective port pin as external capture input pin CCxIO for capture register CCx this port pin must be configured as input that is the corresponding direction control bit must be set to 0 To ensure that a signal transition is properly recognized an external capture input signal should be held for at least eight CPU clock cycles before changing its level During these eight CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented in this process the new timer contents will already be captured for the remaining capture registers within the current scanning sequence Note When the timer modification can generate an overflow the capture interrupt routine should check if the timer overflow was serviced during these 8 CPU clock cycles If pin CCxIO is configured as output the capture function may be triggered by modifying the corresponding port output latch via software for testing purposes for example User s Man
40. Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f lube gp TAR TAM TAI E 5 rw rw rw rw rw User s Manual 10 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Bit Function Txl Timer x Input Selection Depends on the Operating Mode see respective sections TxM Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode 111 Reserved Do not use this combination TxR Timer x Run Bit 0 Timer Counter x stops 1 Timer Counter x runs TxUD Timer x Up Down Control TxUDE Timer x External Up Down Enable 1 For the effects of bits TXUD and TxUDE refer to Table 10 1 see T3 section Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3 The description and the table apply accordingly Timers T2 and TA in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch for T2 and T4 Timers T2 and T4 in Incremental Interface Mod
41. System Reset 20 4 1 System Startup Configuration upon an External Reset For an external reset EA 0 the startup configuration uses the pins of PORTO and pins RD and WR The value on the upper byte of PORTO POH is latched into register RPOH upon reset the value on the lower byte POL directly influences the BUSCONO register bus mode or the internal control logic of the C164CM H 7 H6 H5 H4 H3 H2 H1 HO L7 L6 L5 L4 L 1 Internal Control Logic only on Hardware Reset Clock Generator 5 C3 sow mee RD WR Figure 20 4 PORTO Configuration during Reset MCA05130 The pins which control operation of the internal control logic the clock configuration and the reserved pins are evaluated only during a hardware triggered reset sequence The pins which influence the configuration of the C164CM are evaluated during any reset sequence including software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in Chapter 9 Note Pin POH 0 must be held high upon an external reset The following descriptions refer to the various selections available for reset configuration The default modes refer to pins at high level without external pull down devices connected Please also consider the note above User s Manual 20 13 V1 0 2002 02 Infineon C164CM C164SM technologies Derivativ
42. T13IC CC6POS2 0 P1H 2 0 CTRAP P1L 7 COUT63 P1L 6 COUT62 CC62 P1L 5 P1L 4 COUT61 CC61 P1L 3 P1L 2 COUT60 CC60 P1L 1 P1L 0 CC6EIC CC6CIC E E CC6MCON CC6MSELE CC6MIC DP1HPort P1H Direction Control Register P1HPort P1H Data Register TxPCAPCONMG Timer x Period Register TI20FCAPCOMOG Timer T12 Offset Register CMP13CAPCOM6 Timer T13 Compare Register CTCONCAPCOMSG Timer Control Register CC60 62CAPCOM6 Register 0 2 TRCONCAPCOMSG Trap Control Register CC6MCONCAPCOM6 Mode Control Register CC6MSELCAPCOMSG Mode Select Register CC6MICCAPCOM6G Mode Intr Control Register CC6EICCAPCOM6 Emergency Intr Control Reg CC6CICCAPCOMG Channel Intr Control Register Note The resources marked in italic are available only in the full function CAPCOM MCAO5113 Figure 17 1 SFRs and Port Pins Associ User s Manual 17 1 ated with the CAPCOM6 Unit V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 The three 16 bit capture compare channels are driven via timer T12 and each can control two output lines see Port Control Logic The offset register T12OF full function module only allows shifting of the switching points of the COUT6x output line of each channel by shifting the respective compare value The 10 bit compare channel is driven via timer T13 and can control one output line Additional control logic allows the capture compare
43. T2CON 10 12 T2IC T3IC TAIC 10 20 T3CON 10 3 T4CON 10 12 T78CON 16 5 T7IC 16 9 T8IC 16 9 Temperature compensation 7 7 TFR 5 33 Timer 2 17 10 1 Auxiliary Timer 10 12 CAPCOM2 16 4 CAPCOMSG 17 3 Concatenation 10 16 Core Timer 10 3 Tools 1 7 Trap Function CAPCOM6 17 18 Traps 5 31 TRCON 17 25 Tri State Time 9 12 26 5 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives U UARn 19 21 UGML 19 16 UMLM 19 17 Unlock Sequence 21 22 V Visible mode 9 25 W Waitstate Memory Cycle 9 11 Tri State 9 12 XBUS peripheral 9 25 Watchdog 2 19 13 1 after reset 20 5 Oscillator 6 9 20 18 Reset 20 3 WDT 13 2 WDTCON 13 4 X XBUS 2 11 9 24 enable peripherals 9 25 external access 9 25 waitstates 9 25 Z ZEROS 4 33 User s Manual 26 6 Keyword Index V1 0 2002 02 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
44. Unit l Instr Ptr i General I Instr Reg l 32 T Purpose lage 16 bit ROM lt 7 Pipeline N Registers l Barrel Shifter PSW I l l l l l l l MCB02147 Figure 2 2 CPU Block Diagram To meet the demand for greater performance and flexibility a number of functional blocks of the CPU have been optimized These blocks are controlled by signals from the instruction decode logic Optimizations of the functional blocks are summarized below and described in detail in the following sections 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 3 Extended Bit Processing and Peripheral Control 4 High Performance Branch Call and Loop Processing 5 Consistent and Optimized Instruction Formats 6 Programmable Multiple Priority Interrupt Structure User s Manual 2 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 2 1 High Instruction Bandwidth Fast Execution Based on the hardware provisions most of the C164CM s instructions can be executed in just one machine cycle which requires two CPU clock cycles 2 x 1 fopy 4 TCL For example shift and rotate instructions are always processed within one machine cycle independent of the number of bits to be shifted Branch multiply and divide instructions normally take more than one machine cycle These instructions however h
45. are completed before entering the service routine Thus the actual execution time for these instructions e g waitstates influences the interrupt response time As shown in Figure 5 4 the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline replacing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if in segmented mode and fetches the first instruction I1 from the respective vector location All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine The minimum interrupt response time is 5 states 10 TCL This requires program execution from the internal code memory no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum interrupt response time under these conditions is 6 state times 12 TCL The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N User s Manual 5 19 V1 0 2002 02 _
46. e 400 ns multiplication 16 bit x 16 bit 800 ns division 32 bit 16 bit Multiple high bandwidth internal data buses Register based design with multiple variable register banks e Single cycle context switching support e 16 MBytes of linear address space for code and data Von Neumann architecture e System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code density e Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags e Hardware traps to identify exception conditions during runtime e HLL support for semaphore operations and efficient data access Power Management Features Programmable system slowdown via Slow Down Divider SDD Flexible management of peripherals can be individually disabled e Sleep mode supports wake up via external interrupts e Programmable frequency output Integrated On Chip Memory e 2 KBytes Internal RAM IRAM for variables register banks system stack and code e 32 KBytes on chip Program memory OTP or Mask ROM not for ROMIess devices External Bus Interface Multiplexed or demultiplexed bus configurations 8 bit or 16 bit data bus Buscycle characteristics selectable for five programmable address areas User s Manual 1 5 V1 0 2002 02 _ Infineon
47. insert the conversion of a specific channel into a group conversion auto scan A set of SFRs and port pins provide access to control functions and results of the ADC Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions ADDAT ADCON ADCIC P5DIDIS ADDAT2 E ADEIC P5 Port 5 Analog Input Port ADCON A D Converter Control Register ANO P5 0 AN7 P5 7 ADCIC A D Converter Interrupt Control P5DIDIS Port 5 Digital Input Disable Register Register End of Conversion ADDAT A D Converter Result Register ADEIC A D Converter Interrupt ADDAT2 A D Converter Channel Injection Control Register Result Register Overrun Error Channel Injection MCA05090 Figure 18 1 SFRs and Port Pins Associated with the A D Converter User s Manual 18 1 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Analog Digital Converter The external analog reference voltages Varner and VAgwp are fixed The separate supply for the ADC reduces the interference with other digital signals The sample time and the conversion time are programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply Conversion Control Interrupt Requests iul Result Reg ADDAT AN7 Result Reg ADDAT2 VaREF VAGND MCA05092 Figure 18 2 Analog Digital Converter Block Diagram User s Manual
48. may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority trap priority Il on the 3 7 rank are class B traps so a class A trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the NMI trap at the highest and the stack underflow trap at the lowest priority All class B traps have the same trap priority trap priority 1 When several class B traps become active at same time the corresponding flags in the TFR register are set and the trap service routine is entered Because all class B traps have the same vector the priority of service for simultaneously occurring class B traps is determined by software in the trap service routine A class A trap occurring during the execution of a class B trap service routine will be serviced immediately During the execution of a class A trap service routine however any class B trap occurring will not be serviced until the class A trap service routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost User s Manual 5 32 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions TFR Trap
49. minimum stepwidth for this clock information is determined by the input clock of timer T14 The maximum usable timespan is achieved when T14REL is loaded with 0000 and so T14 divides by 216 Cyclic Interrupt Generation The RTC module can generate an interrupt request whenever timer T14 overflows and is reloaded This interrupt request may be used for example to provide a system time tick independent of the CPU frequency without loading the general purpose timers or to wake up regularly from idle mode The interrupt cycle time can be adjusted via the timer T14 reload register T14REL Please refer to RTC Interrupt Generation below for more details 48 bit Timer Operation The concatenation of the 16 bit reload timer T14 and the 32 bit RTC timer can be regarded as a 48 bit timer which is clocked with the RTC input frequency divided by the fixed prescaler The reload register T14REL should be cleared to produce a 48 bit binary timer However any other reload value may be used The maximum usable timespan is 2 8 10 4 T14 input clocks which would equal more than 100 years at an oscillator frequency of 20 MHz User s Manual 14 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Real Time Clock RTC Register Access The actual value of the RTC is indicated by the three registers T14 RTCL and RTCH As these registers are concatenated to build the RTC counter chain internal overflows occur while the
50. or xx xxFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal Program Memory to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for internal ROM operands Any word data access is made to an even byte address The highest possible word data storage location in the internal Program Memory is xx xxFE For PEC data transfers the internal Program Memory can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The internal Program Memory is not provided for single bit storage and therefore it is not bit addressable Note The x in the locations above depend on the available Program Memory and on the mapping The internal Program Memory may be enabled disabled or mapped into segment 0 or segment 1 under software control Chapter 22 describes this and indicates precautions which must be taken to prevent system crashes User s Manual 3 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization 3 2 Internal RAM and SFR Area The IRAM SFR area is located within data page 3 and provides access to the Internal RAM IRAM organized as X x 16 and to two 512 Byte blocks of Special Function Registers SFRs
51. s enable bit and the global enable bit must both be set The Priority Level automatically selects a certain group of interrupt requests to be acknowledged and ignores all other requests The priority level of the source that won the arbitration is compared against the CPU s current level and the source is serviced only if its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or lower level An interrupt source assigned to level 0 will be disabled and will never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions This is useful for semaphore handling for example and does not require to re enable the interrupt system after the inseparable instruction sequence see Chapter 22 Interrupt Class Management An interrupt class covers a set of interrupt sources with the same importance i e the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The C164CM supports this function with two features Classes with up to four members can be established by using the same interrupt priority ILVL and assigning a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than four members can be established by using a number of adjacent
52. the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared Note that a division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid whether or not the V flag is set to 1 User s Manual 4 17 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Because logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as a Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result In conjunction with the V flag the C flag allows evaluation of the rounding error with a finer resolution see Table 4 2 For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represents the logical ORing of the two specified bits Table 4 2 Shift Right Rounding Error Evaluation C Flag V Flag Rounding Error Quantity 0 0 No rounding error 0 1 0 Rounding error lt gt LSB 1 0 Rounding error 1 3 LSB 1 1 Rounding error gt 1 3 LSB Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition a
53. the two timers T7 or T8 respectively A special combination of compare modes additionally allows implementation of a double register compare mode When capture or compare operation is disabled for one of the CCx registers it may be used for general purpose variable storage Capture Compare Mode Registers for the CAPCOM2 Unit The functions of the 16 capture compare registers are controlled by four identically organized bit addressable 16 bit mode control registers named CCM4 CCM7 see description below Each register contains bits for mode selection and timer allocation of four capture compare registers Capture Compare Mode Registers for the CAPCOM2 Unit CC16 CC31 CCM4 CAPCOM Mode Ctrl Reg 4 SFR FF22 91 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ccmopig CC ccwopis C ccwopi AGC ccmopie rw rw rw rw rw rw rw rw CCM5 CAPCOM Mode Ctrl Reg 5 SFR FF24 92 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ACC ACC ACC 4 ccMop23 ccMop22 X ccMoD21 X CCMOD20 nw nw nw nw nw nw nw nw CCM6 CAPCOM Mode Ctrl Reg 6 SFR FF26 934 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ACC ACC ACC 5 CCMOD27 CCMOD26 X CCMOD25 CCMOD24 rw rw rw rw rw rw rw rw User s M
54. 0 Message objects should have unique identifiers such that if some bits are masked out by the Global Mask Registers don t care bits then the identifiers of the valid message objects should differ in the remaining bits which are used for acceptance filtering If a received message data frame or remote frame matches with more than one valid message object it is associated with the object having the lowest message number Thus a received data frame is stored in the lowest object or the lowest object is sent in response to a remote frame The Global Mask is used for this matching User s Manual 19 20 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface After a transmission data frame or remote frame the transmit request flag of the matching object with the lowest message number is cleared The Global Mask is not used in this case When the CAN controller accepts a data frame the complete message is stored into the corresponding message object including the identifier also masked bits standard identifiers have bits ID17 0 filled with 0 the data length code DLC and the data bytes valid bytes indicated by DLC This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used When the CAN controller accepts a remote frame the corresponding transmit message object 1 14 remains unchanged except for bi
55. 00 00284 OAy Illegal Word Operand Access ILLOPA BTRAP 00 00284 OAy Illegal Instruction Access ILLINA BTRAP 00 0028 OA Illegal External Bus Access ILLBUS BTRAP 00 00284 OA Reserved 2Cy 3Cy OBy OF Software Traps Any Any Current TRAP Instruction 00 0000 00p 7Fy CPU 00 01F Cy Priority in steps of 4 User s Manual 5 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources requiring PEC or interrupt processing is selected according to its interrupt priority This priority of interrupts and PEC requests is programmable in two levels Each requesting source can be assigned to a specific priority A second level called group priority allows to specify an internal order for simultaneous requests from a group of different sources on the same priority level At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system This request will then be serviced if its priority is higher than the current CPU priority in register PSW Interrupt System Register Description Interrupt processing is controlled globally by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the differen
56. 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU The operand and instruction accesses listed below can extend the execution time of an instruction e Internal code memory operand reads same for byte and word operand reads e Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing e External operand reads External operand writes e Jumps to non aligned double word instructions in the internal ROM space Testing Branch Conditions immediately after PSW writes 4 5 CPU Special Function Registers The core CPU requires a set of Special Function Registers SFRs to maintain the system state information to supply the ALU with register addressable constants and to control system and bus configuration multiply and divide ALU operations code memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can be controlled simply by means of any instruction capable of addressing the SFR memory space significant flexibility has been gained without the need to create a set of system specific instructions Note however that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations The Instruction Pointer IP and Code Segmen
57. 02 _ Infineon C164CM C164SM technologies Derivatives System Reset 20 4 System Startup Configuration Although most of the programmable features of the C164CM are selected by software either during the initialization phase or repeatedly during program execution some features must be selected earlier because they are used for the first access of the program execution for example internal or external start selected via EA These configurations are accomplished by latching the logic levels at a number of pins at the end of the internal reset sequence During reset internal pull up pull down devices are active on those lines They ensure inactive default levels at pins which are not driven externally External pull down pull up devices may override the default levels in order to select a specific configuration Many configurations can therefore be coded with a minimum of external circuitry Note The load on those pins to be latched for configuration must be small enough for the internal pull up pull down device to sustain the default level or external pull up pull down devices must ensure this level Those pins whose default level will be overridden must be pulled low high externally Ensure that the valid target levels are reached by the end of the reset sequence There is a specific application note to illustrate this User s Manual 20 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives
58. 11 sorted by name 23 4 Reserved bits 2 13 Reset 20 1 Bidirectional 20 4 Configuration 20 7 20 12 Hardware 20 2 Output 20 8 Software 20 3 Source indication 13 6 Values 20 5 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives Watchdog Timer 20 3 ROM area 3 3 Protection 3 11 RPOH 9 22 RSTCON 20 22 RTC 2 16 14 1 S SOBG 11 11 SOCON 11 2 SOEIC SORIC SOTIC SOTBIC 11 15 SORBUF 11 7 11 9 SOTBUF 11 7 11 9 Security Mechanism 21 22 Segment boundaries 3 10 Segmentation 4 20 Enable Disable 4 15 Serial Interface 2 14 11 1 Asynchronous ASCO 11 5 CAN 2 15 19 1 Synchronous 11 8 Synchronous gt SSC 12 1 SFR 3 8 23 4 23 11 Sharing Interrupt Nodes 5 24 Single Chip Mode 9 2 startup configuration 20 19 Sleep Mode 21 6 Slow Down Mode 21 11 Software Reset 20 3 system configuration 20 21 Traps 5 31 Source Interrupt 5 2 Reset 13 6 SP 4 27 Special operation modes config 20 16 SSC 12 1 Baudrate generation 12 13 Error Detection 12 15 User s Manual Keyword Index Full Duplex 12 7 Half Duplex 12 10 SSCBR 12 13 SSCCON 12 2 12 4 SSCEIC SSCRIC SSCTIC 12 17 SSCRB SSCTB 12 8 Stack 3 5 4 27 22 4 Startup Configuration 20 7 20 12 external reset 20 13 single chip 20 19 via software 20 21 STKOV 4 28 STKUN 4 29 Subroutine 22 10 Synchronous Serial Interface gt SSC 12 1 SYSCON 4 13 9 15 SYSCON1 21 7 SYSCON2 21 13 SYSCONS 21 16 T T121C T13IC 17 33
59. 11 10 9 8 7 6 5 4 3 2 1 0 S AES ILVL GLVL mh rw rw rw CC6EIC ESFR F188 C4 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E EE ILVL GLVL z z mh rw rw rw CC6CIC ESFR F17E BFy Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E rr ILVL GLVL mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 17 33 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Analog Digital Converter 18 Analog Digital Converter The C164CM provides an Analog Digital Converter ADC with 10 bit resolution and a sample amp hold circuit on chip A multiplexer selects up to 8 analog input channels alternate functions of Port 5 either via software fixed channel modes or automatically auto scan modes To fulfill most requirements of embedded control applications the ADC supports the following conversion modes Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels Auto Scan Continuous Conversion repeatedly converts the selected group of channels Wait for ADDAT Read Mode start a conversion automatically when the previous result was read e Channel Injection Mode
60. 16 bit data or POL 8 bit data No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again Write cycles The command signal is now deactivated If a subsequent external bus cycle is required the EBC places the respective address on the address bus The data remain valid on the bus until the next external bus cycle is started 1 Bus Cycle Aadress P1 l CD02061M Figure 9 3 Demultiplexed Bus Cycle User s Manual 9 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Switching between Bus Modes The EBC allows switching between the different bus modes dynamically i e subsequent external bus cycles may be executed in different ways Certain address areas may use multiplexed or demultiplexed buses an 8 bit or 16 bit data bus or predefined waitstates
61. 18 2 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Analog Digital Converter 18 1 Mode Selection and Operation The analog input channels AN7 ANO are alternate functions of Port 5 which is an input only port The Port 5 lines may be used as either analog or digital inputs For pins to be used as analog inputs it is recommended to disable the digital input stage via register PSDIDIS This avoids undesired cross currents and switching noise when the analog input signal level is between Vi and Vi The functions of the A D converter are controlled by the bit addressable A D Converter Control Register ADCON Its bitfields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter ADCON ADC Control Register SFR FFAO D0j Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD AD AD AD AD ADCTC ADSTC CRQ CIN WR BSY ST ADM ADCH rw rw wh rw rw wh wh rw rw Bit Function ADCH ADC Analog Channel Input Selection Selects the first ADC channel to be converted ADM ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST ADC Start Bit 0 Stop a running conversion 1 Start conversion s ADBSY ADC Busy Flag 0 ADC is idle 1 A conversion is active AD
62. 2 9 bit addressable 3 4 Code memory handling 22 16 Cycle Time 9 11 External 3 9 OTP 3 12 26 3 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives RAM SFR 3 4 ROM area 3 3 Tri state time 9 12 Multi Channel Modes CAPCOM6 17 12 Multiplexed Bus 9 4 Multiplication 4 30 22 1 N NMI 5 1 5 34 Noise filter Ext Interrupts 5 30 O ODP8 7 25 ONES 4 33 OPCTRL 3 16 Open Drain Mode 7 3 Oscillator circuitry 6 3 measurement 6 3 Watchdog 6 9 20 18 OTP Programming 3 12 Protection 3 19 P POL POH 7 11 P1L P1H 7 16 P20 7 28 P5 7 21 P5DIDIS 7 23 P8 7 24 PCIR 19 10 PEC 2 9 3 7 5 11 Response Times 5 22 PECCx 5 11 Peripheral enable on XBUS 9 25 Enable Disable 21 15 Management 21 15 Summary 2 12 Phase Locked Loop gt PLL 6 1 Phase Sequences 17 14 Pins 8 1 User s Manual 26 4 Keyword Index configuration 25 2 in Idle and Power Down mode 21 10 Pipeline 4 3 Effects 4 6 PLL 6 1 20 18 POCON 7 5 Port 2 15 driver characteristic 7 4 edge characteristic 7 4 Temperature compensation 7 7 Power Down Mode 21 7 Power Management 2 19 21 1 Preferred external bus mode 9 3 Prescaler 6 7 Programming CPU Host Mode 3 14 External Host Mode 3 15 OTP 3 12 Protected Bits 2 21 4 10 instruction 24 4 Mask ROM 3 11 OTP memory 3 19 PSW 4 16 5 9 PTCR 7 8 R RAM internal 3 4 Read Write Delay 9 13 Real Time Clock gt RTC 14 1 Registers 23 1 sorted by address 23
63. 2 IN min 4 TCL MCT04112 Center Aligned Mode Count Value A T12 Start CC6x 1 T12P 2 EN Time min 4 TCL MCTO02604 Figure 17 7 Operation in Center Aligned Mode User s Manual 17 8 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Table 17 1 Compare Timer Resolution and Period Range as Function of the Internal Clock 9 fcpy 20 MHz Internal Cmp Timer Output Signal Period Range Txmin T12max T13max Clock Resolution Edge Aligned Mode Center Aligned Mode Jopu 50 ns 100ns 3 28ms 51 2us 200ns 655ms 102 4 us cpu 2 100 ns 200ns 655ms 102 4us 400ns 18 11ms 204 8 us Jopu 4 200 ns 400ns 13 11ms 204 8us 800ns 26 21ms 409 6 us cpu 8 400 ns 800ns 2621ms 409 6us 1 6us 52 483ms 819 2 us cpu 16 800 ns 1 6us 52 483ms 819 2us 3 22us 104 86 ms 1 64 ms cpu 32 1 6 us 3 2us 104 86ms 1 64ms 6 4us 209 72ms 3 28 ms cpu 64 32 us 6 4us 209 72ms 3 28ms 12 8us 419 43 ms 6 55 ms Jopu 128 6 4 us 12 8us 419 43ms 6 55ms 25 6us 838 86 ms 13 1 ms Compare timer Tx period and duty cycle values can be calculated using the formulas below The following abbreviations are used in these formulas pv period value stored in register TxP ov offset value stored in register T12OF cv compare value stored in register CC6x o
64. 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T2CON to 000g In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable prescaler which is selected by bit field T3l The input frequency frs for timer T3 and its resolution rr4 are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula f cPU us 8 x o T3l T3977 T3 T3 7 RAS Bx fopu MHz Interrupt p Request TxIR To auxiliary Timers MCB02028d T3EUD P5 2 x 3 n 3 10 Figure 10 3 Block Diagram of Core Timer T3 in Timer Mode Timer input frequencies resolution and periods resulting from the selected prescaler option are listed in Table 10 2 This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits User s Manual 10 5 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives General Purpose Timer Unit Table 10 2 GPT1 Timer Input Frequencies Resolution and Periods 20 MHz fcpu 20 MHz Timer Input Selection T2I TSI T4I 000 001 010g 011 1008 101 110 111 Prescaler 8 16 32 64 128 256 512 1024 Factor Input 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 Frequency MHz MHz kHz kHz kHz kHz kHz k
65. Accepted Active IDLE Instruction Idle Mode Mode Denied PEC Request Executed PEC Request MCA04407 Figure 21 2 Transitions between Idle Mode and Active Mode Idle mode can also be terminated by a Non Maskable Interrupt i e a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will only go back into Idle mode when the interrupt system is globally enabled IEN 1 and a PEC service on a priority level higher than the current CPU level is requested and executed Note An individually enabled interrupt request assigned to priority level O will terminate Idle mode The associated interrupt vector will not be accessed however The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows To prevent the watchdog timer
66. As long as only internal resources from an architecture point of view such as IRAM GPRs or SFRs etc are used the external bus interface does not change see Table 9 4 Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears like an external peripheral to the controller the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see Table 9 4 The address mentioned above includes PORT1 and ALE which also pulses for an XBUS cycle The external control signals RD and WR remain inactive high Table 9 4 Status Of The External Bus Interface During EBC Idle State Pins Internal Accesses only XBUS Accesses PORTO Tristated floating Tristated floating for read accesses XBUS write data for write accesses PORT1 Last used external address Last used XBUS address if used for the bus interface if used for the bus interface ALE Inactive low Pulses as defined for X Peripheral RD Inactive high Inactive high WR Inactive high Inactive high 1 Used and driven in visible mode User s Manual 9 23 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 6 The XBUS Interface The C164CM provides an on chip interface the XBUS interface via which integrated customer appl
67. BUSCONO register The configuration of the high byte of PORTO will be copied into the special register RPOH This read only register holds the selection for the number of chip selects User s Manual 7 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pull up devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra segment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 bit data bus mode two memory cycles are required for word accesses the first for the low byte and the second for the high byte of the word During write cycles PORTO outputs the data byte or word after outputting the address During external accesses in demultiplexed bus modes PORTO reads the incoming instruction or data word or outputs the data byte or word While external bus cycles are executed PORTO is controlled by the bus controller The port direction is determined by the type of the bus cycle the data are transferred directly from to the bus controller hardware The alternate output data can be the 16 bit intrasegment address or the 8 16
68. Bitfield TCV returns 00g when bit TCE 0 always after reset TCE Temperature Compensation Enable 0 The temperature compensation sensor is deactivated default The port drivers are not reduced TCV 00g 1 The temperature compensation is active TCC Temperature Compensation Control This value is fed to the port logic instead of the temperature compensation sensor value while bit TCS O Encoding equal to TCV TCS Temperature Compensation Source 0 Port logic is controlled by software via bitfield TCC 1 Port logic is controlled by the temperature compensation sensor TCDIV Temperature Compensation Clock Divider This value adjusts the temperature compensation logic to the selected operating frequency see description User s Manual 7 8 V1 0 2002 02 Infineon technologies 7 2 To maximize flexibility for different applications and their specific IO requirements port C164CM C164SM Derivatives Parallel Ports Alternate Port Functions lines have programmable alternate input or output functions associated with them Table 7 2 Summary of Alternate Port Functions Port Alternate Function s Alternate Signal s PORTO Address and data lines when accessing AD15 ADO external resources e g memory RxDO TxDO Input output functions of serial interfaces MTSR MRST SCLK PORT Capture inputs or compare outputs of the CC311O CC2410 CAPCOM units CT
69. C164CM C164SM Derivatives CC6MCON 17 26 CC6MIC 17 30 CC6MSEL 17 29 CCM4 CCM5 CCM6 CCM7 16 10 CCxIC 5 28 16 22 Center Aligned Mode CAPCOM6 17 7 Clock distribution 6 2 21 15 generator modes 6 8 20 18 output signal 21 17 Code memory handling 22 16 Compare modes 16 14 double register 16 19 Concatenation of Timers 10 16 Configuration Bus Mode 9 2 20 17 default 20 19 of pins 25 2 PLL 6 8 20 18 Reset 20 7 20 12 special modes 20 16 Context Pointer 4 25 Switching 5 18 Conversion Analog Digital 18 1 Auto Scan 18 7 timing control 18 13 Count direction 10 4 Counter 10 8 10 14 CP 4 25 CPU 2 3 4 1 Host Mode CHM 3 14 CSP 4 20 CSR 19 7 CTCON 17 23 D Data Page 4 22 22 14 boundaries 3 10 Default startup configuration 20 19 Delay User s Manual Keyword Index Read Write 9 13 Demultiplexed Bus 9 5 Development Support 1 7 Direct Drive 6 7 Direction count 10 4 Disable Interrupt 5 15 Peripheral 21 15 Segmentation 4 15 Division 4 30 22 1 Double Register compare 16 19 DPOL DPOH 7 12 DP1L DP1H 7 17 DP20 7 28 DP8 7 24 DPP 4 22 22 14 Driver characteristic ports 7 4 E Early WR control 9 13 Edge Aligned Mode CAPCOM6 17 5 Edge characteristic ports 7 4 Emulation Mode 20 14 Enable Interrupt 5 15 Peripheral 21 15 Segmentation 4 15 XBUS peripherals 9 25 Error Detection ASCO 11 10 CAN 19 4 SSC 12 15 EXICON 5 27 EXISEL 5 29 External Bus 2 11 Bus Characteristics 9 9 9 14 Bus Idle Stat
70. C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface Asynchronous transmission begins at the next overflow of the divide by 16 counter see Figure 11 4 provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic elements e the start bit e the data field 8 or 9 bits LSB first including a parity bit if selected e the delimiter 1 or 2 stop bits Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set before the last bit of a frame is transmitted that is before the first or the second stop bit is shifted out of the transmit shift register The transmitter output pin TXDO must be configured for alternate data output that is the respective port output latch and the direction latch must be 1 Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that bits SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the rate of the selected baud rate A majority decision of the 7 8 and 9 sample deter
71. C164CM provides a powerful set of on chip peripherals and on chip RAM and ROM OTP Flash except for ROMless versions areas these internal units cover only a small fraction of its address space of up to 16 MBytes The External Bus Interface allows access to external peripherals and additional volatile and non volatile memory The External Bus Interface supports a variety of configurations so it can be tailored to fit perfectly into a given application system Ports amp Direction Control Address Registers Mode Registers Control Registers Alternate Functions ADDRSEL4 BUSCON4 POL POH PORTO Data Register BUSCONx Bus Mode Control Register 0 4 P1L P1H PORT1 Data Register SYSCON System Control Register ADDRSELx Address Range Select RPOH Port POH Reset Configuration Register Register 1 4 MCA05127 Figure 9 1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONXx registers specify the external bus cycles in terms of address mux demux data width 16 bit 8 bit chip selects and length waitstates ALE RW delay These parameters are used for accesses within a specific address area as defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow defini
72. C164CM supports four different conversion modes In the standard Single Channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result In the Single Channel Continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention In the Auto Scan mode the analog levels on a prespecified number of channels are sequentially sampled and converted In the Auto Scan Continuous mode the prespecified channels are repeatedly sampled and converted In addition the conversion of a specific channel can be inserted injected into a running sequence without disturbing this sequence This is called Channel Injection Mode The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without requiring the overhead of entering and exiting interrupt routines for each data transfer Real Time Clock The C164CM contains a Real Time Clock RTC which serves different purposes e System clock to determine the current time and date even during idle mode and power down mode optionally Cyclic time based interrupt for example to provide a system time tick independent of the CPU frequency without loading the general purpose timers or to wake up regularly from idle mode 48 bit timer for long term measurements the maximum usable timespan is more than 100 years The RTC module
73. Changes to the external bus characteristics can be initiated in two different ways Switching between predefined address windows automatically selects the bus mode associated with the respective window Predefined address windows allow use of different bus modes without any overhead but restrict their number to the number of BUSCONSs However as BUSCONO controls all address areas which are not covered by the other BUSCONS this allows to have gaps between these windows which use the bus mode of BUSCONO PORT will output the intra segment address when any of the BUSCON registers selects a demultiplexed bus mode even if the current bus cycle uses a multiplexed bus mode This allows to have an external address decoder connected to PORT1 only while using it for all kinds of bus cycles The usage of the BUSCON ADDRSEL registers is controlled via the issued addresses When an access code fetch or data is initiated the respective generated physical address defines whether the access made internally uses one of the address windows defined by ADDRSELA 1 or it uses the default configuration in BUSCONO After initializing the active registers they are selected and evaluated automatically by interpreting the physical address No additional switching or selecting is necessary during run time except when more than the four address windows plus the default are to be used Reprogramming the BUSCON and or ADDRSEL registers allows either changing the
74. Derivatives High Speed Synchronous Serial Interface 12 3 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer It is only a matter of software how long a total data frame length can be This option can also be used to interface to byte wide and word wide devices on the same serial bus for example Note Of course total frame length can only occur in multiples of the selected basic data width as disabling enabling of the SSC would be required to reprogram the basic data width on the fly User s Manual 12 11 V1 0 2002 02 Infineon technologies 12 4 The SSC uses three pins of PORTO to communicate with the external world Pin POH 7 SCLK serves as the clock line while pins POH 5 MRST Master Receive Slave Transmit and POH 6 MTSR Master Transmit Slave Receive serve as the serial data input output lines Operation of these pins depends on the selected op
75. Flag Register SFR FFAC D6 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nui STK STK _ UND _ PRT ILL ILL ILL OF UF OPC FLT OPA INA BUS rwh rwh rwh wh rwh rwh rwh rwh Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted ILLOPA Illegal Word Operand Access Flag A word operand access read or write to an odd address has been attempted PRTFLT Protection Fault Flag A protected instruction with an illegal format has been detected UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid C164CM opcode STKUF Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN STKOF Stack Overflow Flag The current stack pointer value falls below the content of reg STKOV NMI Non Maskable Interrupt Flag m A negative transition falling edge has been detected on pin NMI Note The trap service routine must clear the respective trap flag otherwise a new trap Will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware In the case where e g an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the i
76. High Instruction Bandwidth Fast Execution 2 4 2 2 2 Programmable Multiple Priority Interrupt System 2 8 2 3 On Chip System Resources 000 cee eee eee 2 9 2 4 On Chip Peripheral Blocks 0 000 e eee ee eee 2 12 2 5 Power Management Features 0 c cece eee 2 19 2 6 Protected Bits iua y vong cox EU ops ca m o d nese a RC t coke een 2 21 3 Memory Organization lellll ellen 3 1 3 1 Internal ROM Area uiissess damas ke er ex REX RUE FE doRRE 5 3 3 3 2 Internal RAM and SFR Area 000 cee 3 4 3 3 External Memory Space 00s 3 9 3 4 Crossing Memory Boundaries llli eee ee eee 3 10 3 5 Protection of the On Chip Mask ROM slsesss 3 11 3 6 OTP Memory Programming sss axe AR ICE XR ER d Rx ages 3 12 3 6 1 Selecting an OTP Programming Mode sess 3 14 3 6 2 OTP Module Addressing uiae RE REF XA E SEDE RAS EE 3 16 3 6 3 Head Protection Control ius ico avi we ee x ale e ce c OA 3 19 4 Central Processing Unit CPU 0 02 4 1 4 1 Instruction Pipelining xs Coxexawkasasnmsr sa io wea eee CR 4 3 4 2 Particular Pipeline Effects 0 0 es 4 6 4 3 Bit Handling and Bit Protection aaua aaa 4 10 4 4 Instruction State Times 0 00 eee 4 11 4 5 CPU Special Function Registers 00 cece eee 4 12 5 Interrupt and Trap Functions Luuesssssn 5 1
77. I I DECODE L L L L Lr EXECUTE I L L L WRITEBACK I L L Time gt MCT04327 Figure 4 2 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed up sequential program processing If a branch is taken the instruction which has already been fetched is most likely not the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fetch the branch target instruction This extra machine cycle is provided by means of an injected instruction See Figure 4 3 1 Machine Cycle Injection e a FETCH BRANCH T IrARGET IrARGET H IrARGET 2 IrARGET 3 DECODE D BRANCH insect IraRGET TARGET IrARGET 2 EXECUTE in Is BRANCH insect IrARGET IrARGET H WRITEBACK i d J BRANCH Insect Tasas Time MCT04328 Figure 4 3 Standard Branch Instruction Pipelining User s Manual 4 4 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning of the next machine cycle after the decoding of the conditional branch instruction Cache Jump Instruction Processing The C164CM incorporates a jump c
78. Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits bytes and words Specific instructions support the conversion extension of bytes to words Various direct indirect and immediate addressing modes are provided to specify the required operands User s Manual 2 7 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 2 2 Programmable Multiple Priority Interrupt System The following enhancements within the C164CM allow processing of a large number of interrupt sources Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers between any two locations in segment 0 with an optional increment of either the PEC source or the destination pointer Only one cycle is stolen from the current CPU activity to perform a PEC service Multiple Priority Interrupt Controller This controller allows all interrupts to be assigned any specified priority Interrupts may also be grouped which enables
79. MCT04379 Figure 11 6 ASCO Interrupt Generation As shown in Figure 11 6 SOTBIR is an early trigger for the reload routine while SOTIR indicates the completed transmission Therefore software using handshake should rely on SOTIR at the end of a data block to ensure that all data has really been transmitted User s Manual 11 17 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface 12 High Speed Synchronous Serial Interface The high speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the C164CM and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication for baud rate ranges see formulas and tables in Section 12 5 The serial clock signal can be generated by the SSC itself master mode or can be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPI compatible devices Transmission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal Configuration of the high speed synchronous serial interface is very flexible so it can be used with other synchronous serial interfaces such as the ASCO in synchronous mode it can serve for master slave or multimaster interconnec
80. MICROSEC 010 Let VPP settle for 10 us PROG OTP WORD MOV DPP3 OPAD R1 Select current address MOV RO R2 Move source data word MOV DPP3 OPDAT RO to data register MOV R3 0001H 01H enable module WR active MOV DPP3 OPCTRL R3 Select OTP module for write access CALL MICROSEC 100 Keep the write signal low for 100 us MOV R3 0003H 03H enable module cmd idle MOV DPP3 OPCTRL R3 Trailing edge of write signal ALT VERIFY This block only for alternating verify BCLR VPP ENABLE External progr voltage Off CALL MICROSEC 010 Let VPP settle for 10 us MOV R3 0002H 02H enable module RD active MOV DPP3 OPCTRL R3 Select OTP module for read access MOV R3 0003H 03H enable module cmd idle MOV DPP3 OPCTRL R3 Trailing edge of read signal CMP RO DPP3 OPDAT Verify data reg with original data JMP cc NE PROG FAILED BSET VPP ENABLE External progr voltage ON CALL MICROSEC 010 Let VPP settle for 10 us User s Manual 3 17 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives Memory Organization PROG LOOP CMPI2 R1 BLOCK LIMIT Next OTP location JMP cc ULE PROG OTP WORD Repeat for the whole data block BCLR VPP ENABLE External progr voltage Off CALL MICROSEC 010 Let VPP settle for 10 us Block verification could be executed here MOV R3 0007H MOV DPP3 OPCTRL R3 OTP module deselected User s Manual 3 18 V1 0 2002 02 oe Infineon technologies C16
81. On the SSC a transmission and a reception always take place at the same time regardless of whether valid data has been transmitted or received This is different from asynchronous reception on ASCO User s Manual 12 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface Initialization of the SCLK pin on the master requires some attention to avoid undesired clock transitions which could disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This alternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock SSCPO 0 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence e Select the clock idle level SSCPO x Load the port output latch with the desired clock idle level POH 7 x e Switch the pin to output DPOH 7 1 Enable the SSC SSCEN 1 e f SSCPO 0 enable alternate data output POH 7 1 The same mechanism for selecting a slave for transmission Separate select lines or special commands may also be used to move the role of the master to another device in the network In this case the previous master and the future master previous slave will need to toggle their operating modes SSCMS and the direction of their por
82. One simply places the lowest negative number at the end of the specific table and specifies branching if neither its value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The terminating condition can then be tested e Compare and Increment or Decrement instructions The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction found in other microcontrollers The use of Compare and Increment or Decrement instructions enables the user to make comparisons to any value This allows loop counters to cover any range and is particularly advantageous in table searching The system state information is saved automatically on the internal system stack thus avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Additionally instructions have been provided to support indirect branch and call instructions This feature supports implementation of multiple CASE statement branching in assembler macros and high level languages User s Manual 2 6 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Architectural Overview Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design an instruction set has been design
83. POCONOH F082 E414 Port POH Output Control Register 0011 POCON1L F084 E424 Port P1L Output Control Register 00114 POCON1H F086 E434 Port P1H Output Control Register 00114 POCON8 F092 E494 Port P8 Output Control Register 00224 ADDAT2 FOAO E 50 A D Converter 2 Result Register 0000 POCON20 FOAA E554 Port P20 Output Control Register 0000 PTCR FOAE E 57 4 Port Temperature Compensation Reg 0000 SSCTB FOBO E58 SSC Transmit Buffer 00004 SSCRB FOB2 E594 SSC Receive Buffer XXXXy SSCBR FOB4 E 5A SSC Baudrate Register 00004 T14REL FODO E 68 HTC Timer 14 Reload Register no T14 FOD2 E69 RTC Timer 14 Register no RTCL FOD4 E 6A RTCLow Register no RTCH FOD6 E 6B RTC High Register no DPOL b F100 E 804 POL Direction Control Register 00H DPOH b F102 E 81 4 POH Direction Control Register 004 DP1L b F1044 E824 P1L Direction Control Register 004 DP1H b F106 E 834 P1H Direction Control Register 004 RPOH b F108 E 84 System Startup Config Reg Rd only XXy CCi6IC b F160 E BO CAPCOM Reg 16 Interrupt Ctrl Reg 0000 CC171C b F162 E Biy CAPCOM Reg 17 Interrupt Ctrl Reg 00004 CC18IC b F164 E B2 CAPCOM Reg 18 Interrupt Ctrl Reg 0000 CC19IC b F166 E B3y CAPCOM Reg 19 Interrupt Ctrl Reg 0000 User s Manual 23 12 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set Table 23 4 C164CM Registers Ordered by Name cont d
84. Period interrupt disabled 1 An interrupt from request flag CT12FP is enabled CCnR Capture Compare Rising Edge Interrupt Flag 0 Idle T The interrupt request flag is set as follows Capture mode upon a rising edge at the corresponding CC6n input Compare mode when T12 matches compare register CC6n while counting up in both operating modes of timer T12 CCnF Capture Compare Falling Edge Interrupt Flag 0 Idle T The interrupt request flag is set as follows Capture mode upon a falling edge at the corresponding CC6n input Compare mode when T12 matches compare register CC6n while counting down in center aligned mode timer T12 only User s Manual 17 30 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Bit Function CT12FC Timer T12 Count Direction Change Flag 0 Idle 1 An interrupt request is generated when T12 matches 0000 counting down in center aligned mode and changes to counting up There is no effect in edge aligned mode CT12FP Timer T12 Period Flag 0 Idle 1 An interrupt request is generated when T12 matches the period value Note All CAPCOM6 interrupt request bits in register CC6MIC must be cleared by software User s Manual 17 31 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM6 17 9 The CAPCOM6 Interrupt Structure Figure 17 13 summariz
85. Power Reduction Possibilities Intermittent operation alternating phases of high performance and power saving is supported by the cyclic interrupt generation mode of the on chip RTC Real Time Clock These three power reduction possibilities described above can be applied independently from each other and thus provide a maximum flexibility for each application For the basic power reduction modes Idle Power Down there are dedicated instructions while special registers control Sleep mode SYSCON 1 clock generation SYSCONO and peripheral management SYSCONS Three different general power reduction modes with different levels of power reduction have been implemented in the C164CM They may be entered under software control In Idle Mode the CPU is stopped while the enabled peripherals continue their operation Idle mode can be terminated by any reset or interrupt request In Sleep Mode both the CPU and the peripherals are stopped The real time clock and its selected oscillator may optionally be kept running Sleep mode can be terminated by any reset or interrupt request mainly hardware requests as stopped peripherals cannot generate interrupt requests User s Manual 21 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management In Power Down Mode both the CPU and the peripherals are stopped The real time clock and its selected oscillator may optionally be kept running Power Down
86. Purpose Byte Reg RH5 UU RL6 CP 12 FC CPU General Purpose Byte Reg RL6 UU RH6 CP 13 FDy CPU General Purpose Byte Reg RH6 UU RL7 CP 14 FEy CPU General Purpose Byte Reg RL7 UU RH7 CP 15 FFy CPU General Purpose Byte Reg RH7 UU User s Manual 23 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Register Set 23 3 Registers Ordered by Name Table 23 3 lists all registers implemented in the C164CM in alphabetical order The following markings assist in classifying the listed registers b in the Name column marks Bit addressable SFRs E in the Physical Address column marks E SFRs in the Extended SFR Space m in the Physical Address column marks SFRs without short 8 bit address X in the Physical Address column marks registers within on chip X Peripherals Table 23 3 C164CM Registers Ordered by Name Name Physical 8 Bit Description Reset Address Addr Value ADCIC b FF98 CC A D Converter End of Conversion 0000 Interrupt Control Register ADCON b FFAO DO A D Converter Control Register 0000 ADDAT FEAO 504 A D Converter Result Register 00004 ADDAT2 FOAO0 E504 A D Converter 2 Result Register 0000 ADDRSEL1 FE18 OC Address Select Register 1 0000 ADDRSEL2 FE1Ay OD Address Select Register 2 0000 ADDRSEL3 FE1C OE Address Select Register 3 0000 ADDRSEL4 FE1E OF Address Se
87. Read of ADDAT Channnel 0 Result of Channel 8X 3 9 41 Result Lost 3 Overrun Error Interrupt Request MCA02241 Figure 18 3 Auto Scan Conversion Mode Example User s Manual 18 7 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Analog Digital Converter Wait for ADDAT Read Mode In ADC default mode if a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete the previous result in register ADDAT is lost because it is overwritten by the new value and the A D overrun error interrupt request flag ADEIR will be set To avoid error interrupts and the loss of conversion results especially when using continuous conversion modes the ADC can be switched to Wait for ADDAT Read Mode by setting bit ADWR in register ADCON If the value in ADDAT has not been read by the time the current conversion is complete the new result is stored in a temporary buffer and the next conversion is suspended ADST and ADBSY will remain set in the meantime but no end of conversion interrupt will be generated After reading the previous value from ADDAT the temporary buffer is copied into ADDAT generating an ADCIR interrupt and the suspended conversion is restarted This mechanism applies to both single and continuous conversion modes Note In standard mode continuous conversions are executed at a fixed rate determined by the conversion time In Wait for AD
88. STKUN Stack Underflow Reg SFR FE16 0B Reset Value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 stkun 0 r r r r rw r Bit Function stkun Modifiable portion of register STKUN Specifies the upper limit of the internal system stack The Stack Underflow Trap entered when SP gt STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine Automatic system stack refilling allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap service routine and virtual stack management are given in Chapter 24 Scope of Stack Limit Control The Stack Limit Control implemented by the register pair STKOV and STKUN detects cases in which the Stack Pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit i e CALL or RET instructions This control mechanism is not triggered i e no stack trap is generated when The Stack Pointer SP is directly updated via MOV instructions The limits of the stack area STKOV STKUN are changed so that SP is outside the new limits User s Manual 4 29 V1 0 2002 02 _ Infineon C164CM C164SM technologies Deriva
89. TSUD When T3UDE 1 pin T3EUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in Table 10 1 If T3UD 0 and pin TSEUD shows a low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether or not the timer is running Table 10 1 GPT1 Core Timer T3 Count Direction Control Pin TXEUD Bit TXUDE Bit TxUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note Direction control works the same way for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and bits are named Tx User s Manual 10 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON T3OTL can also be set or reset by software Additionally T3OTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4 An internal connection is provided for this option Timer
90. Table 16 2 Table 16 4 The numbers for the timer periods are based on a reload value of 0000p Note that some numbers may be rounded to 3 significant digits User s Manual 16 6 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Table 16 2 Timer Input Frequencies Resolution and Period 20 MHz fcpu 20 MHz Timer Input Selection Txl 0008 001g 010 Olis 1005 101 110g 1118 Prescaler 1 N 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400 800 1 6 3 2 6 4 12 8 25 6 51 2 ns ns us us us us us us Period 26 52 5 105 210 420 840 1 68 3 36 ms ms ms ms ms ms S S Table 16 3 Timer Input Frequencies Resolution and Period 25 MHz fcpu 25 MHz Timer Input Selection Txl 0008 001g 010g Olis 1005 101g 110g 1118 Prescaler 1 N 8 16 32 64 128 256 512 1024 Input Frequency 3 125 1 563 781 25 390 63 195 31 97 656 48 828 24 414 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 320 640 1 28 2 56 5 12 10 24 20 48 40 96 ns ns us us us us us us Period 21 42 84 168 336 672 1 344 2 688 ms ms ms ms ms ms S S Table 16 4 Timer Input Frequencies Resolution and Period 33 MHz fcpu 33 MHz Timer Input Selection Tx 000 001 010 Olis 100 101 110 111g Prescaler 1 N
91. Table of Contents Page 23 2 CPU General Purpose Registers GPRS 02000055 23 2 23 3 Registers Ordered by Name 0 0 cece eee 23 4 23 4 Registers Ordered by Address 0 0c cece eee eens 23 11 23 5 Special Notes 22420442 ak acp eek ta oe Robes Edi 664 tah os 23 18 24 Instruction Set Summary 0 000 eee eee 24 1 25 Device Specification 0 0006 eee 25 1 26 Keyword Index iue ERAI ee RRGOUN E RC CR CR Rp Cn as 26 1 User s Manual l 5 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Introduction 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time critical operating environments for today s microcontrollers Complex control algorithms have to be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined maximum response time Embedded control applications also are often sensitive to board space power consumption and overall system cost Embedded control applications therefore require microcontrollers which e offer a high level of system integration eliminate the need for additional peripheral devices and the associated software overhead provide system security and fail safe mechanisms provide effective means to control and reduce the device s power consumption The increasing complexity
92. Timer 2 Interrupt Control Register 00004 T3 FE424 214 GPT1 Timer 3 Register 0000 T3CON b FF42 Alu GPT1 Timer 3 Control Register 0000 T3IC b FF624 Bi GPT1 Timer 3 Interrupt Control Register 0000 T4 FE444 224 GPT1 Timer 4 Register 00004 T4CON b FF44 A2 GPT1 Timer 4 Control Register 0000 T4IC b FF644 B2 GPT1 Timer 4 Interrupt Control Register 0000 User s Manual 23 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Register Set Table 23 3 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Address Addr Value T7 F050 E284 CAPCOM Timer 7 Register 00004 T78CON b FF204 90 CAPCOM Timer 7 and 8 Ctrl Reg 00004 T7IC b F17A E BDy CAPCOM Timer 7 Interrupt Ctrl Reg 0000 T7REL F054 Ej J2A CAPCOM Timer 7 Reload Register 00004 T8 F052 E29 CAPCOM Timer 8 Register 00004 T8IC b F17C E BEy CAPCOM Timer 8 Interrupt Ctrl Reg 00004 T8REL F056 E 2By CAPCOM Timer 8 Reload Register 00004 TFR b FFAC D64 Trap Flag Register 00004 TRCON b FF34 9A CAPCOM 6 Trap Enable Ctrl Reg OOXXy WDT FEAE 574 Watchdog Timer Register read only 00004 WDTCON FFAE D74 Watchdog Timer Control Register 2 00xx XPOIC b F186 E C34 CAN1 Module Interrupt Control Register 0000 XP1IC b F18E E C7 Unassigned Interrupt Control Reg 0000 XP3IC b F19E E CFy PLL RTC Interrupt Contr
93. User s Manual 19 28 V1 0 2002 02 technologies C164CM C164SM Derivatives On Chip CAN Interface Reset CPU releases Buffer 2 Buffer 1 Released Buffer 2 Released CPU access to Buffer 2 CPU allocates Buffer 2 CPU releases Buffer 1 Store received message into Buffer 1 Buffer 1 Released Buffer 2 Allocated CPU access to Buffer 2 Store received message into Buffer 1 Buffer 1 Allocated Buffer 2 Allocated CPU access to Buffer 2 Buffer 1 Allocated Buffer 2 Released CPU access to Buffer 1 Store received message into Buffer 2 Buffer 1 Allocated Buffer 2 Allocated CPU access to Buffer 1 Store received message into Buffer 2 MSGLST is set CPU releases CPU releases Buffer 2 Buffer 1 Store received message into Buffer 1 MSGLST is set NEWDAT 1 or RMTPND 1 NEWDAT 0 and RMTPND 0 Allocated Released MCA04400 Figure 19 11 Handling of the Last Message Object s Alternating Buffer User s Manual 19 29 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 4 Controlling the CAN Module The CAN module is controlled by the C164CM via hardware signals e g reset and via register accesses executed by software Accessing the On Chip CAN Module The CAN module is implemented as an X Peripheral and is therefore accessed like an exte
94. address and data a 16 bit data bus requires a word latch the least significant address line AO is not relevant for word accesses The EBC initiates an external access by generating the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the respective command signal RD WR Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deactivated The data remain valid on the bus until the next external bus cycle is started Bus Cycle ALE BUS P0 Address ms oM X MCTO02060M Figure 9 2 Multiplexed Bus Cycle User s Manual 9 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Demultiplexed Bus Modes In the demultiplexed bus modes the 16 bit intra segment address is permanently output on PORT1 and the data uses PORTO
95. address area should be made after an absolute branch to this area Note As a rule instructions that change external bus properties should not be executed from the respective external memory area Timing Instruction pipelining generally reduces the average instruction processing time significantly from four to one machine cycles However there are some rare cases in which a particular pipeline situation causes the processing time for a single instruction to be extended either by one half or by one machine cycle Although this additional time represents only a tiny part of the total program execution time it might be beneficial to avoid these pipeline caused time delays in time critical program modules Section 4 3 below provides a general execution time description and some hints on optimizing time critical program parts with regard to such pipeline caused timing issues User s Manual 4 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU 4 3 Bit Handling and Bit Protection The C164CM provides several mechanisms for bit manipulation These mechanisms either manipulate software flags within the internal RAM control on chip peripherals via control bits in their respective SFRs or control IO functions via port pins The instructions BSET BCLR BAND BOR BXOR BMOV BMOVN explicitly set or clear specific bits The instructions BFLDL and BFLDH allow manipulation of up to 8
96. all port lines having only an alternate input function Port lines having only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether or not the pin is accessible by the user software in the alternate function mode All port lines not used for these alternate functions may be used as general purpose IO lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers to avoid undesired transitions on the output pins This applies to single pins as well as to pin groups see examples below OUTPUT ENABLE SINGLE PIN BSET P8 0 Initial output level is high BSET DP8 0 Switch on the output driver OUTPUT ENABLE PIN GROUP BFLDL P8 05H 05H Initial output level is high BFLDL DP8 05H 05H Switch on the output drivers Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions which do not reference the respective port see Section 4 2 Each of these ports and the alternate input and output functions are described in detail in the following subsections User s Manual 7 10 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports 7 3 PORTO The two 8 bit ports POH and POL represent the higher and lower parts of PORTO respectively Both halves of PORTO can
97. alternate signals to make use of the on chip peripherals so the applicable bus modes are restricted Most of the CAPCOM signals use PORT1 so demultiplexed bus modes will only be used for specific applications The standard serial interfaces use the upper pins of PORTO so 16 bit bus modes can only be used if the application can do without this serial communication 8 bit multiplexed bus mode solves this contradiction by restricting the address width to 11 bits This provides communication via the standard serial interfaces and control of external peripherals or small memories at the same time Even though the C164CM s EBC supports all four bus modes providing access to up to 64 KBytes of external resources 8 bit multiplexed bus mode represents a good choice for many applications providing access to 2 KBytes of external resources most probably peripheral registers Note Please also refer to the description of PORTO in Section 7 3 User s Manual 9 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Multiplexed Bus Modes In the multiplexed bus modes both the 16 11 bit intra segment address and the data use PORTO The address is time multiplexed with the data and must be latched externally The width of the required latch depends on the selected data bus width that is an 8 bit data bus requires a byte latch the address bits A10 A8 on POH do not change while POL multiplexes
98. and a High Speed Synchronous Serial Channel SSC The ASCO is upward compatible with the serial ports of the Infineon 8 bit microcontroller families and supports full duplex asynchronous communication at up to 780 kbit s and half duplex synchronous communication at up to 3 1 Mbit s 9 25 MHz CPU clock A dedicated baud rate generator allows all standard baud rates to be set up without oscilator tuning Four separate interrupt vectors are provided for transmission reception and error handling In asynchronous mode 8 or 9 bit data frames are transmitted or received preceded by a start bit and terminated by one or two stop bits For multiprocessor communication a mechanism has been included to distinguish address bytes from data bytes 8 bit data plus wake up bit mode In synchronous mode the ASCO transmits or receives bytes 8 bits synchronously to a shift clock which is generated by the ASCO The ASCO always shifts the Least Significant Bit LSB first A loop back option is available for testing purposes Optional hardware error detection capabilities have been included to increase the reliability of data transfers A parity bit can be generated automatically on transmission or can be checked on reception Framing error detection allows data frames with missing stop bits to be recognized An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time that reception of a new
99. be written e g via a PEC transfer without affecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DPOH and DPOL POL PORTO Low Register SFR FF00 80 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POL POL POL POL POL POL POL POL i 6 5 4 3 2 1 0 x rw rw rw rw rw rw rw rw POH PORTO High Register SFR FF02 81 Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POH POH POH POH POH POH POH POH af 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Bit Function POX y Port data register POH or POL bit y User s Manual 7 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports DPOL POL Direction Ctrl Register ESFR F100 80 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOL DPOL DPOL DPOL DPOL DPOL DPOL DPOL af 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DPOH POH Direction Ctrl Register ESFR F102 81 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOH DPOH DPOH DPOH DPOH DPOH DPOH DPOH 4 6 5 4 3 2 1 0 r
100. bit Data 16 bit A15 AO Demultiplexed Addresses 01 8 bit Data 11 bit A10 AO Multiplexed Addresses 10 16 bit Data 16 bit A15 AO Demultiplexed Addresses 11 16 bit Data 16 bit A15 AO Multiplexed Addresses The bus configuration BTYP for the address windows BUSCON4 BUSCON71 is selected via software typically during the initialization of the system The bus configuration BTYP for the default address range BUSCONO is selected via PORTO during reset provided that pin EA is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16 MByte address space of the C164CM is divided into 256 segments of 64 KBytes each For multiplexed bus modes the 16 11 bit intra segment address is output on PORTO for demultiplexed bus modes the 16 bit intra segment address is output on PORT1 When segmentation is disabled only one 64 KByte segment can be used and accessed Note Bit SGTDIS of register SYSCON determines whether or not the CSP register is saved during interrupt entry segmentation active or segmentation disabled User s Manual 9 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Preferred External Bus Mode Due to the low pin count of the C164CM many alternate input output signals use the pins of PORTO and PORT1 thus competing with the External Bus Interface Many applications will require the
101. buffer is not empty at that time in the case of continuous transfers the busy flag is not cleared and the transfer goes on after moving data from the buffer to the shift register Software should not modify SSCBSY as this flag is hardware controlled Note Only one SSC etc can be master at a given time The transfer of serial data bits can be programmed in many respects e Data width can be chosen from 2 bits to 16 bits e Transfer may start with the LSB or the MSB e Shift clock may be idle low or idle high e Data bits may be shifted with the leading or trailing edge of the clock signal e Baudrate may be set within a wide range see baudrate generation e Shift clock may be generated master or received slave This flexibility allows adaptation of the SSC to a wide range of applications which require serial data transfer User s Manual 12 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface The Data Width Selection supports the transfer of frames of any length from 2 bit characters up to 16 bit characters Starting with the LSB SSCHB 0 allows communication with ASCO devices in synchronous mode C166 Family or 8051 like serial interfaces for instance Starting with the MSB SSCHB 1 allows operation compatible with the SPI interface Regardless of which data width is selected and whether the MSB or the LSB is transmitted first
102. bus mode for a given address window or changing the size of an address window using a certain bus mode Reprogramming allows a great number of different address windows to be used more than the BUSCONS available at the expense of the overhead for changing the registers and keeping appropriate tables Note Be careful when changing the configuration for an address area that currently supplies the instruction stream Due to the internal pipelining the first instruction fetch that will use the new configuration depends on the instructions prior to the configuration change Special care is required when changing bits like BUSACT in order not to cut the instruction stream inadvertently Only change the other configuration bits after checking that the respective application can cope with the intended modification s It is recommended to change ADDRSEL registers only while the respective BUSACT bit in the associated BUSCON register is cleared Switching from demultiplexed to multiplexed bus mode represents a special case The bus cycle is started by activating ALE and driving the address to PORT1 as usual if another BUSCON register selects a demultiplexed bus However in the multiplexed User s Manual 9 6 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives External Bus Interface bus modes the address is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle this del
103. context instruction This mechanism does not provide a method to recursively call a subroutine Saving and Restoring Registers To provide local registers the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values can be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two machine cycles per register stored on the system stack one cycle to PUSH the register and one cycle to POP the register Use of the System Stack for Local Registers It is possible to use the SP and CP to set up local subroutine register frames This enables subroutines to dynamically allocate local variables as needed within two machine cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see the example below Each local register is then accessed as if it were a normal register Upon exit from the subroutine first the old CP must be restored by popping it from the stack and then the number of used local registers must be added to the SP to re
104. dE am Ls e es Low Addresses 8 System Stack before b System Stack after b System Stack after Interrupt Entry Interrupt Entry Interrupt Entry Unsegmented Segmented MCD02226 Figure 5 3 Task Status Saved on the System Stack The interrupt request flag of the source being serviced is cleared The IP is loaded with the vector associated with the requesting source CSP is cleared in the case of segmentation and the first instruction of the service routine is fetched from the vector location which is expected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is exited RETI is executed the status information is popped from the system stack in the reverse order taking into account the value of bit SGTDIS User s Manual 5 17 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is spent saving and restoring To save time the C164CM allows switching the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New Bank pushes the content of the context pointer CP on the system sta
105. een ung sa Rees oe qa dos eeu Sa NE e Io aci qa 7 24 7 7 Poll 20 25sasdesusteradg xA ewe ine ds enw tern de ae kee oe ees 7 28 8 Dedicated Pins iiis oso teas e ews FRAT EL ERE RICE EE eV dope s 8 1 9 External Bus Interface 0 000 9 1 9 1 Single Chip Mode cece eee tte ees 9 2 9 2 External BUS Modes 4 cy duck ex EORR XC wal REN BHR ER Des 9 2 9 3 Programmable Bus Characteristics llle 9 9 9 4 Controlling the External Bus Controller llllllslssss 9 15 9 5 EBC Idle State riore qd Ex dO XI eS CRn ox dca RI CRURA eek 9 23 9 6 The XBUS Interface css Exe er Race BES ee hee kei be 9 24 9 6 1 Accessing the On chip XBUS Peripherals 9 25 9 6 2 External Accesses to XBUS Peripherals L 9 25 10 General Purpose Timer Unit 0000 10 1 10 1 Timer Block GPTT 24 nacen hh deed REIR ERE Ra RUE reno dmn 10 1 10 1 1 GPT1 Core Timer F3 sus rete det tn ERERERREDS ER wen ERE 10 3 10 1 2 GPT1 Auxiliary Timers T2 and T4 000 cee eee eee 10 12 10 1 3 Interrupt Control for GPT1 Timers 00000 cena 10 20 11 Asynchronous Synchronous Serial Interface 11 1 11 1 Asynchronous ODeratiolt iae axe sce x RR RE Rex xe D a 11 5 11 2 Synchronous Operation Jis xac c y EE rx REC ESO ADR E 11 8 11 3 Hardware Error Detection Capabilities lulu 11 10 11 4 ASCO Baud Rate Generation 0 0 0 ees 11 11 11 5 ASCO In
106. frequencies Table 12 2 SSC Bit Time Calculation Bit time for fcpy Reload Val 16 MHz 20 MHz 25 MHz 33 MHz SSCBR Reserved SSCBR must be gt 0 0000 250 ns 200 ns 160 ns 121 ns 00014 375 ns 300 ns 240 ns 182 ns 00024 500 ns 400 ns 320 ns 242 ns 00034 625 ns 500 ns 400 ns 303 ns 0004 1 00 us 800 ns 640 ns 485 ns 00074 1 25 us 1 us 800 ns 606 ns 0009 10 us 8 us 6 4 us 4 8 us 004F 125 us 10 Us 8 Us 6 1 Us 00634 15 6 us 12 5 us 10 us 7 6 us 007C 20 6 us 165 us 13 2 us 10 us 00A44 1 ms 800 us 640 us 485 us 1F3F4 User s Manual 12 13 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives High Speed Synchronous Serial Interface Table 12 2 SSC Bit Time Calculation cont d Bit time for fcpy Reload Val 16 MHz 20 MHz 25 MHz 33 MHz SSCBR 1 25 ms 1 ms 800 us 606 us 270Fy 1 56 ms 1 25 ms 1 ms 758 us 30D3y 8 2 ms 6 6 ms 5 2 ms 4 0 ms FFFFy Table 12 3 SSC Baudrate Calculation Baud Rate for fcpy Reload Val 16 MHz 20 MHz 25 MHz 33 MHz SSCBR Reserved SSCBR must be gt 0 00004 4 00 Mbit s 5 00 Mbit s 6 25 Mbit s 8 25 Mbit s 0001 2 67 Mbit s 3 33 Mbit s 4 17 Mbit s 5 50 Mbit s 0002 2 00 Mbit s 2 50 Mbit s 3 13 Mbit s 4 13 Mbit s 0003 1 60 Mbit s 2 00 Mbit s 2 50 Mbit s 3 30 Mbit s 0004 1 00 Mbit s 1 25 Mbi
107. from overflowing during Idle mode it must be programmed to a reasonable time interval before Idle mode is entered User s Manual 21 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 2 Sleep Mode To further reduce power consumption the microcontroller can be switched to Sleep mode Clocking of all internal blocks is stopped RTC and selected oscillator optionally The contents of the internal RAM however are preserved through the voltage supplied via the Vpp pins The watchdog timer is stopped in Sleep mode Sleep mode is selected via bitfield SLEEPCON in register SYSCON1 and is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed Sleep mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered regardless of bit IEN These are primarily external interrupts and the RTC if running Note The receive lines of serial interfaces may be internally routed to external interrupt inputs see EXISEL All peripherals except for the RTC are stopped and hence cannot generate an interrupt request The realtime clock RTC can be kept running in Sleep mode in order to maintain a valid system time as long as the supply voltage is applied This enables a system to determine the current time and the duration of the period in Sleep mod
108. function is enabled by bit ECT130 in register CTCON If the output function is disabled COUT63 drives the defined passive level Note Trap function and multi channel modes are available in the full function module only User s Manual 17 4 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 2 Edge Aligned Mode The compare timer counts up starting at 00004 When the timer contents match the respective compare value in register CC6x the associated output signal is switched to its active state Upon reaching the period value stored in register TxP the timer is cleared and repeats counting up At this time also the output signals are switched to their passive state In Figure 17 4 the selected edge offset is zero therefore the output signal refers to CC6x and or COUT6x T12 Value A CCP 7 T120F 0 Time A 0 0 0 T12 Start Duty Cycles CC 0 100 CC 1 87 5 lt CC 4 5096 CC 7 12 5 ce ue CC compare value in registers CC6x CCP period value in register T12P T13P MCTO04111 Output signal at pin CC6x or COUT6x selected as active high For an active low output the signals would appear inverted Figure 17 4 Operation in Edge Aligned Mode The example above shows how to generate PWM output signals with duty cycles between 0 and 100 inc
109. in column Read by Reg Register and Sh L Shadow latch Additionally there are four interrupt node control registers associated with the CAPCOMS unit however they are not part of the module see Page 17 33 User s Manual 17 21 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Shadow Latches for Synchronous Update The timer period offset and compare values are written to shadow latches rather than to the actual registers Also the initial value bits CCxI COUTxI in register CC6MCON are equipped with shadow latches Thus the values for a new output signal can be programmed without disturbing the currently generated signal s The transfer from the latches to the registers is enabled by setting the respective shadow latch transfer enable bit STEx in register CTCON If the transfer is enabled the shadow latches are copied to the respective registers the next time the associated timer reaches the value zero either being cleared in edge aligned mode or counting down from 1 in center aligned mode When timer T12 is operating in center aligned mode it will also copy the latches if enabled if it reaches the currently programmed period value counting up After the transfer the respective bit STEx is automatically cleared Note While T12 T13 is running the shadow latch transfer is controlled by bit STE 12 13 While T12 T13 is stopped the shadow latch tran
110. initialization of the C164CM into a defined default state The default state is invoked either by asserting a hardware reset signal on pin RSTIN Hardware Reset Input by executing the SRST instruction Software Reset or by an overflow of the watchdog timer Whenever one of these conditions occurs the microcontroller is reset into its predefined default state through an internal reset procedure When a reset is initiated pending internal hold states are cancelled and the current internal access cycle if any is completed An external bus cycle is aborted except for a watchdog reset see description Afterwards the bus pin drivers and the IO pin drivers are switched off tristate The internal reset procedure requires 516 CPU clock cycles in order to perform a complete reset sequence This 516 cycle reset sequence is started by a watchdog timer overflow by an SRST instruction or when the reset input signal RSTIN is latched low hardware reset The internal reset condition is active for at least the duration of the reset sequence and then until the RSTIN input is inactive and the PLL has locked if the PLL is selected for the basic clock generation When this internal reset condition is removed reset sequence complete RSTIN inactive PLL locked the reset configuration is latched from PORTO RD and ALE depending on the start mode Afterwards pins ALE RD and WR are driven to their inactive levels Note Bit ADP which selects th
111. instructions in particular General instruction timing is described including standard and exceptional timing While internal memory accesses are normally performed by the CPU itself external peripheral or memory accesses are performed by a particular on chip External Bus Controller EBC which is invoked automatically by the CPU whenever a code or data address refers to the external address space SYSCON Context Ptr BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr 3 Code Seg Ptr eo ee l i TE Internal SP RAM STKOV DL STKUN Exec Unit l Instr Ptr i General i Instr Reg I 32 TS Purpose lage 16 bit i ROM KT Pipeline N Registers l Barrel Shifter PSW I I I I I LIllc Ll ee MCB02147 Figure 4 1 CPU Block Diagram User s Manual 4 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Whenever possible the CPU continues operating while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is described in a separate chapter The on chip peripheral units of the C164CM work nearly independently of the CPU with a separate clock generator
112. intended operating frequency but guarantees a 50 duty cycle for the internal clock system independent of the input clock signal s waveform PLL Operation When PLL operation is configured via CLKCFG the C164CM s input clock is fed to the on chip Phase Locked Loop circuit which multiplies its frequency by a factor of F 21 5 5 selectable via CLKCFG see Table 6 1 and generates a CPU clock signal with 50 duty cycle i e fcpy fosc XF The on chip PLL circuit allows operation of the C164CM on a low frequency external clock while still providing maximum performance The PLL also provides fail safe mechanisms which allow detection of frequency deviations and execution of emergency actions in case of an external clock failure When the PLL detects a missing input clock signal it generates an interrupt request This warning interrupt indicates that the PLL frequency is no longer locked i e no longer stable This occurs when the input clock is unstable and especially when the input clock fails completely such as due to a broken crystal In this case the synchronization mechanism will reduce the PLL output frequency down to the PLL s base frequency 2 5 MHz The base frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock On power up the PLL provides a stable clock signal within about 1 ms after Vpp has reached the specified valid range even if there is no external clock s
113. internal RAM from 32 to 512 words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of bits VISIBLE ROMEN and ROMS is described in more detail in Chapter 9 User s Manual C164CM C164SM _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU System Clock Output Enable CLKEN The system clock output function is enabled by setting bit CLKEN in register SYSCON to 1 If enabled port pin P20 8 takes on its alternate function as CLKOUT output pin The clock output is a 50 duty cycle clock except for direct drive operation where CLKOUT reflects the clock input signal and for slowdown operation where CLKOUT mirrors the CPU clock signal whose frequency equals the CPU operating frequency four fcpu Note The output driver of port pin P20 8 is switched on automatically when the CLKOUT function is enabled The port direction bit is disregarded After reset the clock output function is disabled CLKEN 0 In emulation mode the CLKOUT function is enabled automatically Segmentation Disable Enable Control SGTDIS Bit SGTDIS allows selection of either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is restricted to 64 KBytes segment 0 thus 16 bits are sufficient to represent all code addresses For implicit stack operations CALL or RET t
114. interrupt priorities ILVL and the respective group levels four per ILVL Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level are blocked now i e no request of this class will be accepted User s Manual 5 15 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions The example shown below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority ILVL in class 2 Class 1 requests or PEC requests are still serviced in this case In this way the 24 interrupt sources excluding PEC requests are assigned to 3 classes of priority rather than to 7 different levels as the hardware support would do Table 5 6 Software Controlled Interrupt Classes Example ILVL GLVL Interpretation Priority 3 2 1 0 15 PEC service on up to 8 channels 14 13 12 X X X X Interrupt Class 1 11 X 5 sources on 2 levels 10 9 8 X X X IX Interrupt Class 2 7 X x x Ix 9 Sources on 3 levels 6 X 5 X X X X Interrupt Class 3 4 X 5 sources on 2 levels d 2 1 0 No service User s Manual 5 16 V1 0 2002 02 _
115. interrupt service routine Note PEC transfers are executed only if their priority level is higher than the CPU level that is only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for PEC service should use different channels Otherwise only one transfer will be performed for all simultaneous requests When COUNT is decremented to 00 and the CPU is to be interrupted an incorrect interrupt vector will be generated The source and destination pointers specify the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the eight PEC channels These pointers do not reside in specific SFRs but are mapped into the internal RAM of the C164CM just below the bit addressable area see Figure 5 2 O0 FCFE O0 FCEE 00 FCFC 00 FCEC O0 FCFA O0 FCEA OO FCF8 OO FCE8 OO FCF6 00 FCE6 4 00 FCF4 00 FCEA OO0 FCF2 O0 FCE2 OO FCFO SRCPO OO CEO MCA04331 Figure 5 2 Mapping of PEC Pointers into the Internal RAM User s Manual 5 13 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions PEC data transfers do not use the data page pointers DPP3 DPPO The PEC source and destination pointers are used as 16 bit intra segment addresses within segment 0 so data can be transferred between any two locations w
116. is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch User s Manual 7 9 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Parallel Ports On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however for which the direction of the port line is switched automatically For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output There is one basic structure for
117. is used directly as the 16 bit address User s Manual 4 21 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Data Page Pointers DPPO DPP1 DPP2 DPP3 These four non bit addressable registers select up to four different data pages to be active simultaneously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 KByte data pages the upper 6 bits are reserved for future use The DPP registers allow access to the entire memory space in pages of 16 KBytes each AU Pointer 0 SFR FE00 00 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E B 2 2 DPPOPN rw DPP1 Data Page Pointer 1 SFR FE02 01 Reset Value 0001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 z 3 DPP1PN rw DPP2 Data Page Pointer 2 SFR FE04 024 Reset Value 0002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8 B DPP2PN H rw DPP3 Data Page Pointer 3 SFR FE06 03 Reset Value 0003 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 amp T Weve ee ii ae ne DPP3PN User s Manual 4 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU
118. line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DPOH 7 0 The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins are determined by the master or slave operation of the individual device Note The shift direction shown in Figure 12 4 applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration select one device for master operation SSCMS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Chapter 12 4 Master Device 1 Device 2 Slave Shift Register MCS01963 Figure 12 4 SSC Full Duplex Configuration User s Manual 12 7 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives High Speed Sy
119. line of Port 5 is also connected to the input multiplexer of the Analog Digital Converter All port lines can accept analog signals ANx which can be converted by the ADC For pins to be used as analog inputs it is recommended to disable the digital input stage via register PSDIDIS see description below This avoids undesired cross currents and switching noise while the analog input signal level is between Vi and Vj Some pins of Port 5 also serve as external GPT timer control lines Table 7 4 summarizes the alternate functions of Port 5 Table 7 4 Alternate Functions of Port 5 Port 5 Pin Alternate Function a Alternate Function b P5 0 Analog Input ANO P5 1 Analog Input AN1 P5 2 Analog Input AN2 TSEUD Timer 3 ext Up Down Input P5 3 Analog Input AN3 T3IN Timer 3 Count Input P5 4 Analog Input AN4 T2EUD Timer 2 ext Up Down Input P5 5 Analog Input AN5 T4EUD Timer 4 ext Up Down Input P5 6 Analog Input AN6 T2IN Timer 2 Count Input P5 7 Analog Input AN7 T4IN Timer 4 Count Input User s Manual 7 21 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Parallel Ports Alternate Function a b rens P5 7 AN7 TAIN P5 6 AN6 T2IN P5 5 AN5 T4EUD P5 4 AN4 T2EUD P5 3 AN3 T3IN P5 2 AN2 T3EUD P5 1 AN1 P5 0 ANO General Purpose A D Converter Timer Control Input Input Input MCA05136 Figure 7 9 Port 5 10 and Alternate Functions Port 5 Digital Input Cont
120. modes pins RD and ALE ADP Adapt Mode Not possible PO 1 EMU Emulation Mode Not possible P0 0 OWD disable SYSCON OWDDIS 0 RD SYSCON OWDDIS i e OWD is active Port 20 enable Port 20 mode selected via SYSCON P20EN pin WR 1 Refers to the configuration pins which are replaced by the default values 2 Software can modify the default values via these bitfields Note Single chip mode reset cannot be selected on ROMless devices The attempt to read the first instruction after reset will fail in such a case User s Manual 20 19 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Single Chip Startup Modes The startup mode operation after reset of the C164CM can be configured during reset In single chip mode this configuration is selected via pins RD and ALE Pin RD selects start or boot mode instead of OWD control pin ALE selects one of two alternatives in each case Table 20 6 Startup Mode Configuration in Single Chip Reset Mode RD ALE Startup Mode Notes 1 0 Standard Start Execution starts at user memory location 00 0000 1 1 Alternate Start Operation not yet defined Do not use 0 0 Standard Bootstrap Load 32 bytes via ASCO Loader 0 1 Alternate Boot Mode Operation not defined Do not use Pin WR additionally selects the initial operating mode of the Port 20 pins Table 20 7 Initial Port 20 Mode Configuration i
121. must be 0 Synchronous reception is stopped by clearing bit SOREN A byte currently being received is completed including generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received byte has not been read out of the receive buffer register at the time that reception of the next byte is complete both the error interrupt request flag SOEIR and the overrun error status flag SOOE will be set provided the overrun check has been enabled by bit SOOEN User s Manual 11 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface 11 3 Hardware Error Detection Capabilities To enhance reliability of serial data exchange the serial channel ASCO provides an error interrupt request flag which indicates the presence of an error and three selectable error status flags in register SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive interrupt request flag SORIR if one or more of the following conditions are met e f the framing error detection enable bit SOFEN is set and any expected stop bit is not high the framing error flag SOFE is set indicating that the err
122. o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 4 Saving Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved together with the location at which execution of the interrupted task is to be resumed after returning from the service routine This return location is specified through the Instruction Pointer IP and in the case of a segmented memory model the Code Segment Pointer CSP Bit SGTDIS in register SYSCON controls how the return location is stored The system stack receives the PSW first followed by the IP unsegmented or followed by CSP and then IP segmented mode This optimizes the usage of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request to be serviced so the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to 1 In this case the return location saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction itself as this instruction has been interrupted and will be completed after returning from the service routine High Status of Addresses Interrupted Task Em
123. oe Infineon technologies C164CM C164SM Derivatives Asynchronous Synchronous Serial Interface 11 2 Synchronous Operation Synchronous mode supports half duplex communication primarily for simple IO expansion via shift registers Data is transmitted and received via pin RXDO while pin TXDO outputs the shift clock These signals are alternate port functions Synchronous mode is selected with SOM 000p 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is active only as long as data bits are transmitted or received Reload Register 2 EIL A SOR SOM 000B S0OE Receive Int SORIR Request Serial Port Control SOTIR Transmit Int Request Request Receive Shift Transmit Shift Register Register Transmit Receive Buffer Reg Transmit Buffer Reg SORBUF SOTBUF Ciera MCB02220 Figure 11 5 Synchronous Mode of Serial Channel ASCO User s Manual 11 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface Synchronous transmission begins within 4 state times after data has been loaded into SOTBUF provided that SOR is set and SOREN 0 half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift
124. of the port output latch is switched to the line connected to the internal bus The port output latch will receive the value from the internal bus and the hardware triggered change will be lost As with all other capture inputs the capture input function of the Port 8 pins can also be used as external interrupt input sample rate 16 TCL The CAN interface can use 2 pins of Port 8 to interface the CAN Module to an external transceiver In this case the number of possible CAPCOM IO lines is reduced Table 7 5 Alternate Functions of Port 8 Port 8 Pin Alternate Function P8 0 CC16lO Capture input compare output channel 16 or CAN P8 1 CC17lO Capture input compare output channel 17 or CAN P8 2 CC18lO Capture input compare output channel 18 or CAN P8 3 CC19IO Capture input compare output channel 19 or CAN Alternate Function a Port 8 P8 3 CC19lO CAN1_TxD P8 2 CC18lO CAN1_RxD P8 1 CC171O CAN1_TxD P8 0 CC16lO CAN1_RxD General Purpose CAPCOM2 CAN Interface Input Output Capt Inp Comp Outp MCA05084 Figure 7 11 Port 81O and Alternate Functions Note The usage of Port8 pins for CAN interface lines depends on the chosen assignment for the CAN module CAN interface lines will override general purpose IO and CAPCOM IO lines User s Manual 7 26 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports The pins of Port 8 combine internal bus
125. operation in the application This includes selecting the operating mode such as counter timer operating parameters such as baudrate enabling interface pins if required assigning interrupt nodes to the respective priority levels etc After these standard initialization actions application specific actions may be required such as asserting certain levels to output pins sending codes via interfaces latching input levels etc User s Manual 20 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Termination of Initialization The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction Execution of the EINIT instruction has the following effects Disables the action of the DISWDT instruction Disables write accesses to register SYSCON all configurations regarding register SYSCON enable CLKOUT stacksize etc must be selected before the execution of EINIT Disables write accesses to registers SYSCON2 and SYSCONS3 further write accesses to SYSCON2 and SYSCONS can be executed only using a special unlock mechanism Clears the reset source detection bits in register WDTCON Causes the RSTOUT pin to go high this signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware User s Manual 20 11 V1 0 2002
126. pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0 Pin RSTIN is an input only 1 Pin RSTIN is pulled low during the internal reset sequence after any reset OWDDIS Oscillator Watchdog Disable Bit 0 The on chip oscillator watchdog is enabled and active jh The on chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO or for signal FOUT 1 CLKOUT enabled pin outputs the system clock signal ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal program memory disabled accesses to the ROM area use the external bus ij Internal program memory enabled User s Manual 4 13 V1 0 2002 02 _ Infineon technologies Central Processing Unit CPU Bit Function SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7 FFF 4 1 Internal ROM area mapped to segment 1 01 0000 01 7 FFF STKSZ System Stack Size Selects the size of the system stack in the
127. programming cycle takes about 100 us OTP programming requires an external programming voltage of Vpp 11 5 V 5 which is applied to pin EA Vpp The OTP memory can be programmed in CPU Host Mode CHM via software or in External Host Mode EHM via external hardware ADDR 10 ns a 100 us 1 Earliest possible begin of next programming cycle Vpp must be switched off for verify accesses it may remain on for subsequent programming cycles The special signal RSEL must fulfill the same timing requirements as the address lines Note All timings represent minimum values 100 ns OTP Word Address DATA Programming Data 120 ns MCTO05093 Figure 3 5 User s Manual OTP Programming Cycle 3 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization Verify cycles may be executed to ensure correct programming Programming cycles and verify cycles may alternate in order to check each word immediately However the total programming time can be reduced by programming blocks of data continuously and then verifying the blocks this saves the Vpp settling time Note The programming voltage V pp must be applied for all programming cycles and must be removed for all other accesses i e verify cycles and standard read cycles The setting time is 10 us in each case In EHM this must be controlled by the external host in CHM the CPU may co
128. pull or open drain output mode Programmable port driver control Various Temperature Ranges e 0to 70 C e 40 to 85 C e 40to 4125 C User s Manual 1 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Introduction Infineon CMOS Process Low power CMOS technology enables power saving Idle Sleep and Power Down modes with flexible power management 64 Pin Plastic Metric Thin Quad Flat Pack TQFP Package e P TQFP 10 x 10 mm body 0 5 mm 19 7 mil lead spacing surface mount technology Complete Development Support For the development tool support of its microcontrollers Infineon follows a clear third party concept Currently around 120 tool suppliers world wide ranging from local niche manufacturers to multinational companies with broad product portfolios offer powerful development tools for the Infineon C500 and C166 microcontroller families guaranteeing a remarkable variety of price performance classes as well as early availability of high quality key tools such as compilers assemblers simulators debuggers or in circuit emulators Infineon incorporates its strategic tool partners very early into the product development process making sure embedded system developers get reliable well tuned tool solutions which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve The tool environment for the Infineon 1
129. register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous data is still going on The data bits are transmitted synchronous with the shift clock After the bit time for the 8 data bit both pins TXDO and RXDO will go high the transmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO must be configured for alternate data output that is the respective port output latch and the direction latch must be 1 in order to provide the shift clock Pin RXDO must also be configured for output output direction latch 1 during transmission Synchronous reception is initiated by setting bit SOREN 1 If bit SOR 1 the data applied at pin RXDO are clocked into the receive shift register synchronous to the clock output at pin TXDO After the 8 bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive interrupt request flag SORIR is set the receiver enable bit SOREN is reset and serial data reception stops Pin TXDO must be configured for alternate data output that is the respective port output latch and the direction latch must be 1 in order to provide the shift clock Pin RXDO must be configured as alternate data input that is the respective direction latch
130. register WDTCON will be set in this case In bidirectional reset mode pin RSTIN will also be pulled low for the duration of the internal reset sequence and a long hardware reset will be indicated instead A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence To prevent the watchdog timer from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 bit instruction Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON Servicing the watchdog timer will also reset bit WDTR After servicing the watchdog timer resumes counting up from the value lt WDTREL gt x 29 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer is minimized such as by fetching and executing a bit pattern from a wrong location When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered rather than executing the instruction User s Manual 13 3 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Watchdog Timer WDT WDTCON WDT Control Register SFR FFAE D7 R
131. setting or clearing user specific bits and conditionally branching based on these specific bits It is recommended that bit fields in control SFRs be updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur if BCLR BSET or AND OR instruction sequences are used 22 7 Trap Interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require the use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location at which the trap or interrupt occurred User s Manual 22 13 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives System Programming 22 8 Inseparable Instruction Sequences The instructions of the C164CM are very efficient most instructions execute in one machine cycle Even the multiplication and division are interruptible in order to minimize the response latency to interrupt requests internal and external This is vital in many microcontroller applications S
132. simultaneous the same number of bits are transmitted and received The major steps of the state machine of the SSC are controlled by the shift clock signal see Figure 12 2 In master mode SSCMS 1 two clocks per bit time are generated each upon an underflow of the baudrate counter In slave mode SSCMS 0 one clock per bit time is generated when the latching edge of the external SCLK signal has been detected Transmit data is written into the transmit buffer SSCTB When the contents of the buffer are moved to the shift register immediately if no transfer is currently active a transmit interrupt request SSCTIR is generated indicating that SSCTB may be reloaded again The busy flag SSCBSY is set when the transfer starts with the next following shift clock in master mode immediately in slave mode Note If no data is written to SSCTB prior to a slave transfer this transfer starts after the first latching edge of the external SCLK signal is detected No transmit interrupt is generated in this case When the contents of the shift register are moved to the receive buffer SSCRB after the programmed number of bits 2 16 have been transferred i e after the last latching edge of the current transfer a receive interrupt request SSCRIR is generated The busy flag SSCBSY is cleared at the end of the current transfer with the next following shift clock in master mode immediately in slave mode When the transmit
133. system stack size stackpointer upper and lower limit registers can be adjusted to application specific values After reset registers SP and STKUN contain the same reset value O0 FCOO while register STKOV contains 00 FA00 With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from 00 FBFE Note The interrupt system which is disabled upon completion of the internal reset should remain disabled until the SP is initialized Traps including NMI may occur although the interrupt system is still disabled Register Bank The location of a register bank is defined by the context pointer CP and can be adjusted to an application specific bank before the general purpose registers GPRs are used After reset register CP contains the value 00 FCOO i e the register bank selected by the CP grows upward from 00 FCO00 User s Manual 20 9 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives System Reset On Chip RAM Depending on the application the user may wish to initialize portions of the internal writable memory IRAM before normal program operation After the register bank has been selected by programming the CP register the desired portions of the internal memory can easily be initialized via indirect addressing Interrupt System After reset the individual interrupt nodes and the global interrupt system are d
134. the BUSCON registers A waitstate will be inserted if bit MTTCx is 0 default after reset Note External bus cycles in multiplexed bus modes implicitly add one tri state time waitstate in addition to the programmable MTTC waitstate User s Manual 9 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Read Write Signal Delay The C164CM allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the falling edge of ALE and the falling edge of the command Without read write delay the falling edges of ALE and command s coincide except for propagation delays With the delay enabled the command s become active half a CPU clock 1 TCL after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the C164CM s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay The read write delay is controlled via the RWDCx bits in the BUSCON registers The command s will be delayed if bit RWDCx is 0 default after reset Early WR Signal Deactivation The duration of an external write access can be shortened by one TCL The
135. the EINIT instruction 7 8 The shaded area designates the internal reset sequence which starts after synchronization of RSTIN A short hardware reset is extended until the end of the reset sequence in Bidirectional reset mode A software or WDT reset activates the RSTIN line in Bidirectional reset mode MCS02258 Figure 20 3 Reset Input and Output Signals User s Manual 20 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Ports and External Bus Configuration during Reset During the internal reset sequence all port pins of the C164CM are configured as inputs by clearing the associated direction registers and their pin drivers are switched to the high impedance state This ensures that the C164CM and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pull down and pins RD and WR are held high through internal pull ups The registers SYSCON and BUSCONO are initialized according to the configuration selected via PORTO When an external start is selected pin EA 0 Bus Type field BTYP in register BUSCONO is initialized according to POL 7 and POL 6 Bit BUSACTO in register BUSCONO is set to 1 Bit ALECTLO in register BUSCONO is set to 1 Bit ROMEN in register SYSCON will be cleared to 0 When an internal start is selected pin EA 1 e Register BUSCONO is initialized t
136. the message was being updated by the CPU the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the actual data has been transferred When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first This arbitration is done when several objects are requested for transmission by the CPU or when operation is resumed after an error frame or after arbitration has been lost Arbitration Registers The Arbitration Registers UARn amp LARn are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message with a matching identifier is accepted as a data frame matching object has DIR 0 orasa remote frame matching object has DIR 1 For matching the corresponding Global Mask must be considered the Mask of Last Message must also be considered for message object 15 Extended frames using Global Mask Long can be stored only in message objects with XTD 1 standard frames using Global Mask Short can be stored only in message objects with XTD
137. the transfer data is always right aligned in registers SSCTB and SSCRB and the LSB of the transfer data in bit O of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of SSCTB are ignored The unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine The Clock Control allows adaptation of transmit and receive behavior of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSCPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state Thus for an idle high clock the leading edge is a falling one a 1 to 0 transition Figure 12 3 provides a summary Serial Clock SSCPO SSCPH SCLK esr LX CC MTSR MRST First Last Bit i Transmit Data Bit Latch Data MCD01960 Shift Data Figure 12 3 Serial Clock Phase and Polarity Options User s Manual 12 6 V1 0 2002 02 Oo Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface 12 1 Full Duplex Operation The various devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit
138. the user to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bitfield After being accepted by the CPU an interrupt service can be interrupted only by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location Multiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM A single one machine cycle instruction allows register banks to switch from one task to another e Interruptible Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptible The C164CM is capable of reacting very quickly to non deterministic events because its interrupt response time is within a very narrow range of only 5 to 10 CPU clock cycles in the case of internal program execution Its fast external interrupt inputs are sampled every CPU clock cycle and allow even very short external signals to be recognized The C164CM also provides an excellent mechanism to identify and process exceptions or error conditions that arise during run time so called Hardware Traps A hardware trap causes an immediate non maskable system reaction which is simi
139. this state until the busoff recovery sequence is finished Additionally bit EWRN in the Status Register is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit User s Manual 19 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Bit Timing Logic The Bit Timing Logic BTL monitors the busline input CAN RXD and handles the busline related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of the BTL depends on the baudrate and on external physical delay times Intelligent Memory The Intelligent Memory CAM RAM Array provides storage for up to 15 message objects of 8 data bytes maximum length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions Organization of Registers
140. to a CAN transfer incident SIE must be set such as reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt The status partition of the Control Register must be read to update the INTID value 024 Message 15 Interrupt Bit INTPND in the Message Control Register of message object 15 last message has been set The last message object has the highest interrupt priority of all message objects 02 N Message N Interrupt Bit INTPND in the Message Control Register of message object N has been set N 1 14 Note that a message interrupt code is only displayed if there is no other interrupt request with a higher priority Example message 1 INTID 03 4 message 14 INTID 10 IPC Interface Port Control reset value 111g i e no port connection The encoding of bitfield IPC is described in Section 19 6 Note Bitfield IPC can be written only while bit CCE is set 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to 00 idle state User s Manual 19 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 2 2 Configuration of
141. transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode The CAPCOMSG unit provides three capture compare channels and one additional compare channel The three capture compare channels can control two output lines each which can be programmed to generate non overlapping pulse patterns The additional compare channel may either generate a separate output signal or modulate the output signals of the three other channels The active level for each output can be selected individually Versatile multichannel PWM signals can be generated controlled either internally via a timer or externally for example via hall sensors The trap function allows the outputs to be driven to a defined level in response to an external signal Note Multichannel PWM modes are only available in devices with a full function CAPCOM6 not in the reduced CAPCOMG User s Manual 2 18 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview Watchdog Timer The Watchdog Timer is one of the fail safe mechanisms implemented in the C164CM to prevent the controller from malfunctioning for longer periods of time T
142. transmission of a message currently being updated or to control the automatic response to remote requests TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet complete TXRQ can be disabled by CPUUPD 9 User s Manual 19 19 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives On Chip CAN Interface Bit Function RMTPND Remote Pending Used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ Bits RMTPND and TXRQ are cleared when the message object has been successfully transmitted 1 In message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 When the CAN controller writes new data into the message object unused message bytes will be overwritten by non specified values Usually the CPU will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this bit along with clearing bit CPUUPD This will ensure that if the message is actually being transmitted during the time
143. 0 CP 124 R9 lt CP gt 104 R8 CP OE RH7 RL7 R7 CP 0C RH6 RL6 R6 CP 0A RH5 RL5 R5 CP 08 RH4 RL4 R4 CP 06 RH3 RL3 R3 CP 044 RH2 RL2 R2 CP 024 RH1 RL1 R1 CP 00 RHO RLO RO The C164CM supports fast register bank context switching Multiple register banks can physically exist within the Internal RAM at the same time Only the register bank selected by the Context Pointer register CP is active at a given time however Selecting a new active register bank is done simply by updating the CP register A particular Switch Context SCXT instruction performs register bank switching and automatically saves User s Manual 3 6 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Memory Organization the previous context The number of implemented register banks arbitrary sizes is limited only by the size of the available internal RAM Details on using switching and overlapping register banks are described in Chapter 22 PEC Source and Destination Pointers The 16 word locations in the Internal RAM from 00 FCEO to 00 FCFE just below the bit addressable section are provided as source and destination address pointers for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word addres
144. 0 no EXTR required here Switch Unlock Unlock Unlock Single to ESFR space and lock sequence sequence step 1 1001B sequence step 2 0011B sequence step 3 0111B access to one locked register CLKCON 00B gt basic frequ start PLL Next access to ESFR space PLLIE 1 i e PLL interrupt enabled 21 24 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives L SDD EXIT MANUAL MOV SYSCON2 ZEROS EXTR 44H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 01H USER_CODE CLOCK OK EXTR 1H JNB MOV SYSCON2 ZEROS EXTR 4H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 00H EXTR 1H BSET ISNC 2 User s Manual 1 Power Management Currently running on SDD frequency Clear bits 3 0 Switch Unlock Unlock Unlock Single no EXTR required here to ESFR space and lock sequence sequence step 1 1001B sequence step 2 0011B sequence step 3 0111B access to one locked register CLKCON 01B gt stay on SDD start PLL 1 Space for any user code that must or can be executed before Switching back to basic clock Next access to ESFR space 1 Clear bits 3 0 Switch Unlock Unlock Unlock Single CLKCON 00B gt basic frequency SYSCON2 15 CLOCK OK Wait until clock OK CLKLOCK 1 no EXTR required here to ESFR s
145. 0 5 P20 4 P20 1 P20 0 Figure 7 14 Block Diagram of a Port 20 Pin with Alternate Input or Alternate Output Function Note Signal AItEN in the above figure equals the inverted Port 20 enable signal P20EN Not all pins of Port 20 have both alternate output functions and alternate input functions User s Manual 7 31 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports Internal Bus lt o o Ee So Direction Latch FOEN FOUT CLKEN CLKOUT Clock Input Latch P20 8 MCBO05118 Figure 7 15 Pin Control for Pin P20 CLKOUT FOUT Note Enabling the CLKOUT function automatically enables the P20 8 output driver Setting bit DP20 8 1 is not required For FOUT the pin driver must be enabled by setting bit DP20 8 User s Manual 7 32 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Dedicated Pins 8 Dedicated Pins Most of the input output or control signals of the C164CM are implemented as alternate functions of the parallel ports pins There are however a number of signals which use separate pins including the oscillator special control signals and the power supply Table 8 1 summarizes the 14 dedicated pins of the C164CM Table 8 1 C164CM Dedicated Pins Pin s Function NMI Non Maskable Interrupt Input XTAL1 XTAL2 Oscillator Input Outp
146. 1 Port line P1X y is an output Alternate Functions of PORT1 When a demultiplexed external bus is enabled PORT1 is used as address bus Note that demultiplexed bus modes use PORT1 as a 16 bit port Otherwise all 16 port lines can be used for general purpose IO The lower 11 pins of PORT1 P1H 2 P1L 0 serve as the inputs outputs for the CAPCOM6E unit Pins P1H 3 P1H 0 accept the fast external inputs P1H 3 also serves as input for timer T7 The upper eight pins of PORT1 P1H 7 P1H 0 also serve as capture inputs or compare outputs for the CAPCOM2 unit CC271O CC241O CC311O CC2810O As all other capture inputs the capture input function of pins P1H 7 P1H 0 can also be used as external interrupt inputs sample rate 16 TCL As a side benefit the capture input capability of these lines can also be used in the address bus mode In this way changes to the upper address lines could be detected and could trigger an interrupt request in order to perform some special service routines External capture signals can be applied only if no address output is selected for PORT1 During external accesses in demultiplexed bus modes PORT1 outputs the 16 bit intra segment address as an alternate output function User s Manual 7 17 V1 0 2002 02 e Infineon technologies During external accesses in multiplexed bus modes when no BUSCON register selects a demultiplexed bus mode PORT1 is not used and is ava
147. 10IC b FF8C4 C6 External Interrupt 2 Control Register 0000 CC111IC b FF8E C7 External Interrupt 3 Control Register 0000 CC16 FE60 304 CAPCOM Register 16 00004 CC16IC b F160 E BO CAPCOM Reg 16 Interrupt Ctrl Reg 0000 CC17 FE62y 314 CAPCOM Register 17 0000 CC171C b F162 E Biy CAPCOM Reg 17 Interrupt Ctrl Reg 00004 CC18 FE64 324 CAPCOM Register 18 0000 CC18IC b F164 E B2 CAPCOM Reg 18 Interrupt Ctrl Reg 0000 CC19 FE66 334 CAPCOM Register 19 00004 CC19IC b F166 E B34 CAPCOM Reg 19 Interrupt Ctrl Reg 0000 CC20 FE68y 344 CAPCOM Register 20 00004 CC21 FE6Ay 354 CAPCOM Register 21 00004 CC22 FE6Cy 364 CAPCOM Register 22 00004 CC23 FE6E 374 CAPCOM Register 23 00004 CC24 FE70y 384 CAPCOM Register 24 00004 CC24IC b F170 E B8 CAPCOM Reg 24 Interrupt Ctrl Reg 0000 CC25 FE72y 39 CAPCOM Register 25 00004 CC25IC b F172 E B94 CAPCOM Reg 25 Interrupt Ctrl Reg 0000 CC26 FE744 3A CAPCOM Register 26 0000 CC26IC b F1744 E BAy CAPCOM Reg 26 Interrupt Ctrl Reg 0000 CC27 FE76y 3By CAPCOM Register 27 0000 CC271C b F1i76 E BBu CAPCOM Reg 27 Interrupt Ctrl Reg 00004 CC28 FE78y 3C CAPCOM Register 28 00004 CC29 FE7A 3D CAPCOM Register 29 0000 CC30 FE7Cy 3E CAPCOM Register 30 00004 User s Manual 23 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Register Set Table 23 3 C164CM Registers Ordered by Name c
148. 15 1 BSL Memory Configurations 16 MBytes N Access to external bus disabled Ji 16 MBytes N Access to external bus enabled Ca j 59 gt 16 MBytes j N Depends on reset config EA PO LO Ke Int Int RM LE 2 RM Ll 9 E 1 1 f Ll gt O O Access to O O Access to O Depends R int ROM pa int ROM on reset S g enabled S g enabled g config eoa 2 m D MCA04383 MCA04384 MCA04385 BSL mode active Yes Yes No EA pin high low acc to application Code fetch from internal ROM area Boot ROM access Boot ROM access User ROM access Data fetch from internal ROM area User ROM access User ROM access User ROM access User s Manual 15 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Bootstrap Loader 15 2 Loading the Startup Code After sending the identification byte the BSL enters a loop to receive 32 bytes via ASCO These bytes are stored sequentially in locations 00 FA40 through OO FA5F of the internal RAM Up to 16 instructions may be placed in the RAM area To execute the loaded code the BSL then jumps to location 00 FA40 i e the first loaded instruction The bootstrap loading sequence is now terminated but the C164CM remains in BSL mode Most probably the initially loaded routine will load additional code or data as an av
149. 16 3 Capture Compare Registers 000 cece 16 10 16 4 Capture Mode 0 0 ccc eens 16 12 16 5 Compare Modes 0 0 00 eee eens 16 14 16 6 Capture Compare Interrupts lille 16 22 16 7 Interrupts for the Upper CAPCOM Channels 16 23 17 Capture Compare Unit CAPCOMG sss 17 1 17 1 Output Signal Level Control 0000 eee 17 4 17 2 Edge Aligned Mode essere erre 17 5 17 3 Center Aligned Mode sees 17 7 17 3 1 Timing Relationships llle 17 8 17 4 Burst Mode 1s kc n ache ee ae ARRA DOC wR ADR ee ee 17 10 17 5 Capture Mode 0 ess 17 11 17 6 Combined Multi Channel Modes 0000 cee ee eeeee 17 12 17 6 1 Output Signals in Multi Channel Mode 17 13 17 6 2 Block Commutation Mode 000 cece eee eee ee 17 16 17 7 Pap FUNCION denas aio treed es icq wae oe OL a eee as 17 18 17 8 Register Descriptions 42 0 euxx 0k evades d ex EXE ROO ERE 17 21 17 9 The CAPCOMG Interrupt Structure 0000 cee eee ee 17 32 18 Analog Digital Converter 00 0 ccc eee eee 18 1 18 1 Mode Selection and Operation ce eee eee eee 18 3 18 2 Conversion Timing Control 0 00 c eee eee 18 13 18 3 A D Converter Interrupt Control 00000 ee 18 15 19 On Chip CAN Interface 0 0 00 cece ee 19 1 User s Manual l 3 V1 0 2002 02 _
150. 171C F162 4 B14 ESFR CC18IC F1644 B2 ESFR CC19IC F166 B34 ESFR CC24IC F170 B84 ESFR CC25IC F1724 B94 ESFR CC26IC F174 BA ESFR CC271C F176 BBy ESFR User s Manual 16 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 16 7 Interrupts for the Upper CAPCOM Channels The upper four CAPCOM channels CC28I0 CC311O are not connected to the respective interrupt nodes CC28IC CC311C However these signals share the same pins as the fast external interrupts EXOIN EXS3IN Due to this fact the missing interrupt nodes can be replaced Instead of the dedicated interrupt nodes for the CAPCOM registers 28 31 the fast external interrupts O 3 can be enabled if the corresponding pin is used as capture input or compare output compare modes 1 and 3 Register EXICON selects the interrupt edge registers CC8IC CC111C control interrupt enables and levels This means that CAPCOM channel 28 triggers external interrupt signal EXOIN and requests an interrupt via node CC8IC The other three channels are associated accordingly see Table 5 9 User s Manual 16 23 V1 0 2002 02 _ C164CM C164SM Derivatives e e Infineon technologies Capture Compare Unit CAPCOM6 17 Capture Compare Unit CAPCOM6 The CAPCOM amp G unit of the C164CM has been designed for applications which require digital signal generation and or event capturing such as p
151. 2 02 _ Infineon C164CM C164SM technologies Derivatives Device Specification 25 Device Specification The device specification describes the electrical parameters of the device It lists DC characteristics such as input output voltages supply voltages input output supply currents as well as AC characteristics such as timing characteristics and requirements Other than the architecture the instruction set or the basic functions of the C164CM core and its peripherals these DC and AC characteristics are subject to change due to device improvements or development of specific derivatives of the standard device Therefore these characteristics are not contained in this Users Manual but are provided in device specific Data Sheets which can be updated more frequently Please refer to the current version of the Data Sheet of the respective device for all electrical parameters Note The specific characteristics of a device should always be verified before a new design is started to ensure use of the most current information Figure 25 1 shows the pin diagram of the C164CM It shows the location of the various supply and IO pins Detailed descriptions of all pins are also found in the Data Sheet Note Not all alternate functions shown in Figure 25 1 are supported by all derivatives Please refer to the corresponding descriptions in their data sheets User s Manual 25 1 V1 0 2002 02 C164CM C164SM Derivatives te
152. 21 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset RSTCON Reset Control Register mem F1E0 Reset Value 00XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SUE RSTLEN rw r rw rw Bit Function RSTLEN Reset Length Control duration of the next reset sequence to occur 00 1024 TCL standard duration corresponds to all other derivatives without control function 01 2048 TCL extended duration may be useful for example to provide additional settling for external configuration signals at high CPU clock frequencies 10 Reserved 11 Reserved SUE Software Update Enable 0 Configuration cannot be changed via software 1i Software update of configuration is enabled CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode i e the mechanism by which the internal CPU clock is generated from the externally applied XTAL1 input clock 000 PLL fx 2 5 100 PLL fx 5 001 Prescaler f 2 101 PLL f x 2 010 PLL fx 1 5 110 PLL fx 3 011 Direct Drive f f 111 PLL fx 4 1 RSTLEN is always valid for the next reset sequence An initial power up reset however is expected to last considerably longer than any configurable reset sequence Note RSTCON is write protected after the execution of EINIT unless it is released via the unlock sequenc
153. 24 27 are connected to interrupt nodes User s Manual 16 18 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Double Register Compare Mode In double register compare mode two compare registers work together to control one output pin This mode is selected by a special combination of modes for these two registers For double register mode the 16 capture compare registers of the CAPCOM2 unit are regarded as two banks of 8 registers each Registers CC16 CC23 form bank 1 while registers CC24 CC31 form bank 2 respectively For double register mode a bank 1 register and a bank 2 register form a register pair Both registers of this register pair operate on the pin associated with the bank 1 register pins CC161O CC19lO are available The relationships between the bank 1 and bank 2 registers of a pair and the affected output pins for double register compare mode are listed in Table 16 6 Table 16 6 Register Pairs for Double Register Compare Mode CAPCOM2 Unit Register Pair Associated Output Pin Bank 1 Bank 2 CC16 CC24 CC16lO CC17 CC25 CC171O CC18 CC26 CC18lO CC19 CC27 CC19IO CC23 CC20 CC31 CC28 The double register compare mode can be programmed individually for each register pair To enable double register mode the respective bank 1 register see Table 16 6 must be programmed to compare mode 1 and the correspondi
154. 3 may violate the deviation limit while an even higher baudrate marked II in Figure 15 3 stays very well below it Any baudrate can be used for the bootstrap loader provided that the following three prerequisites are fulfilled Baudrate is within the specified operating range for the ASCO External host is able to use this baudrate Computed deviation error is below the limit Table 15 2 Bootstrap Loader Baudrate Ranges fopy MHz 10 12 16 20 25 Bmax 312 500 375 000 500 000 625 000 781 250 Buigh 9 600 19 200 19 200 19 200 38 400 Bstpmin 600 600 600 600 600 BLow 172 206 275 343 429 User s Manual 15 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Bootstrap Loader Note When the bootstrap loader mode is entered via an internal reset EA 1 the default configuration selects the prescaler for clock generation In this case the bootstrap loader will begin to operate with fep fosc 2 which will limit the maximum baudrate for ASCO at low input frequencies intended for PLL operation Higher levels of the bootstrapping sequence can then switch the clock generation mode for example to PLL operation via register RSTCON to achieve higher baudrates for the subsequent download User s Manual 15 8 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM2 16 Capture Compare Unit CAPCOM2 The C164CM pro
155. 3 12 11 10 9 8 7 6 5 4 3 2 1 0 CCx CCx IR IE ILVL GLVL mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Table 5 9 Fast External Interrupt Control Register Addresses Register Address External Interrupt CC8IC FF88 C44 EXOIN CC9IC FF8A C5y EX1IN CC10IC FF8Cy C6 EX2IN CC111IC FF8E C7 EXSIN User s Manual 5 28 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions External Interrupt Source Control The input source for the fast external interrupts controlled via register EXICON can be derived either from the associated port pin EXnIN or from an alternate source This selection is controlled via register EXISEL Activating the alternate input source for example allows the detection of transitions on the interface lines of disabled interfaces Upon this trigger the respective interface can be reactivated and respond to the detected activity EXISEL Ext Interrupt Source Reg ESFR F1DA ED Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXHSS EXIOSS rw rw rw rw rw rw rw rw Bit Function EXIxSS External Interrupt x Source Selection Field x 7 0 00 Input from associat
156. 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 state times After a request for PEC service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal code memory or external memory and to write the destination operand over the external bus in an external program environment Note A bus access in this context includes all delays which can occur during an external bus cycle User s Manual 5 23 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 7 Interrupt Node Sharing Interrupt nodes may be shared among several module requests if either the requests are generated mutually exclusively or the requests are generated at a low rate If more than one source is enabled in this case the interrupt handler will first need to determine the requesting source However this overhead is not critical for low rate requests This node sharing is controlled via the sub node interrupt control register ISNC which provides a separate request flag and enable bit for each supported request source The interrupt level used for arbitration is determined by the node control register IC The specific request flags within ISNC must be reset by software If the respective request is likely to be activated either at the ti
157. 4 FEC8 644 SFR PECC1 FEC2 614 SFR PECC5 FECA 65 SFR PECC2 FEC4 624 SFR PECC6 FECC 66 SFR PECC3 FEC6 634 SFR PECC7 FECE 674 SFR User s Manual 5 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Byte Word Transfer bit BWT controls whether a byte or a word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the modified pointer Increment Control field INC controls whether one of the PEC pointers is incremented after the PEC transfer It is not possible to increment both pointers however If the pointers are not modified INC 00 the respective channel will always move data from the same source to the same destination Note The reserved combination 11 is changed to 10 by hardware However it is not recommended to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel The content of bit field COUNT selects the action to be taken at the time the request is activated COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all Table 5 5 summarizes how the COUNT field the interrupt requests flag IR and the PEC channel action depend on the previous content of COUNT Table 5 5 Influence of Bitfield COUNT Previous Modified IR after Action o
158. 4CM C164SM Derivatives Memory Organization 3 6 3 Read Protection Control The on chip OTP memory can be protected against unauthorized accesses read or execute When the read protection is active no programming cycles can be executed neither in EHM nor in CHM no verify cycles can be executed OTP locations can only be read by instructions fetched from the OTP itself The OTP read protection is activated by a specific programming cycle which has the register select signal RSEL active contrary to normal programming cycles This special cycle must write the value 0000p to register address OOO0E A verify cycle can be executed directly after activating the read protection i e without leaving programming mode The active read protection is indicated with data bit DO 0 Note OTP read protection is irreversible When the OTP read protection was activated once it remains active for each and every subsequent access Also subsequent programming cycles are no more possible OTP Read Protection Example The OTP read protection is activated in CHM executing the following procedure Note The example below assumes segment 0 RHO 00 MOV RO 0003H MOV DPP3 OPCTRL RO BSET VPP ENABLE Enable module cmd idle Initially enable the OTP module External progr voltage ON CALL MICROSEC 010 Let VPP settle for 10 us MOV RO 000EH Move special register address MOV DPP3 OPAD RO to address registe
159. 4CM C164SM technologies Derivatives Central Processing Unit CPU Multiply Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation Register MDC is updated by hardware during each single cycle of a multiply or divide instruction MDC Multiply Divide Control Reg SFR FF0E 874 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDR a HH quy uo ng ng z z r w h r w h r w h r w h r w h r w h r w h r w h Bit Function MDRIU Multiply Divide Register In Use 0 Cleared when register MDL is read via software af Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed Internal Machine Status The multiply divide unit uses these bits to control internal operations Never modify these bits without saving and restoring register MDC When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later Then it must be cleared to prepare it for the new calculation After completion of the new division or multiplication the state of the interrup
160. 5 1 Interrupt System Structure 20 0 cece 5 2 5 1 1 Interrupt Control Registers anaa aana aea 5 5 5 2 Operation of the PEC Channels 2 000 0c ee eee eee 5 11 5 3 Prioritization of Interrupt and PEC Service Requests 5 15 5 4 Saving Status during Interrupt Service 00 0c eee eee 5 17 5 5 Interrupt Response Times 0000 cee 5 19 5 6 PEG Response Times nciices nea deur ee eo eee doe RE AR RES EE RES ES 5 22 5 7 Interrupt Node Sharing 000 cece eee eee 5 24 5 8 External Interrupts lt tvscricdsc eda ex OR ET RA Geese RACATR eka we Ke 5 25 5 9 Trap FUNCHONS 22404 cerren nba Genre he oT Re SOR Rr ed e OEC bare 5 31 User s Manual l 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Table of Contents Page 6 Clock Generation 0 00 cece een 6 1 6 1 erro rnm 6 3 6 2 Frequency Control 24 4x ux opes d DRE ERR Rd oko RR dd d 6 5 6 3 Oscillator Watchdog assa op bee Eb oP ark EE ERORE REED E IRA 6 9 6 4 GOO DIVETS mmm 6 10 7 Parallel Ports 44 xx rx ox ECTETUR ECRIRE c RON Oct ac s 7 1 7 1 Output Driver Control 22250600 vas Ru dare kx Rs Fu RR RE n 7 3 7 2 Alternate Port Functions 0 0 ccc eee 7 9 7 3 PORTU oua adio ai eub eae dee et as dod ndr diac OEE 7 11 7 4 PORTI a ied kee dena dre d ea dae dca ees diac V dub ee eres 7 16 7 5 POMS eod redeas ae eade che oa oe RUBER dax ee ee eee 7 21 7 6 POM ooreen
161. 6 EB Port 8 Direction Control Register 00 1 The system configuration is selected during reset 2 User s Manual The reset value depends on the indicated reset source 23 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Register Set 23 5 Special Notes PEC Pointer Registers The source and destination pointers for the Peripheral Event Controller PEC are mapped to a special area within the internal RAM Pointers not occupied by the PEC may be used like normal RAM During Power Down mode or any warm reset the PEC pointers are preserved The PEC and its registers are described in Chapter 5 GPR Access in the ESFR Area The locations 00 F000 O0 FO1E within the ESFR area are reserved and allow to access the current register bank via short register addressing modes The GPRs are mirrored to the ESFR area to allow access to the current register bank even after switching register spaces see example below MOV R5 DP8 GPR access via SFR area EXTR 1 MOV R5 ODP8 GPR access via ESFR area Writing Bytes to SFRs All Special Function Registers may be accessed wordwise or bytewise some of them even bitwise Reading bytes from word SFRs is a non critical operation However when writing bytes to word SFRs the complementary byte of the respective SFR is cleared with the write operation User s Manual 23 18 V1 0 2002 02 _ Infineon C164CM C164SM technolog
162. 6 bit microcontrollers includes the following tools Compilers C MODULA2 FORTH Macro assemblers linkers locators library managers format converters Architectural simulators e HLL debuggers Real time operating systems e VHDL chip models e n circuit emulators based on bondout or standard chips Plug in emulators e Emulation and clip over adapters production sockets Logic analyzer disassemblers e Starter kits Evaluation boards with monitor programs e Industrial boards also for CAN FUZZY PROFIBUS FORTH applications Network driver software CAN PROFIBUS User s Manual 1 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Introduction 1 3 Abbreviations The following acronyms and terms are used within this document ADC Analog Digital Converter ALE Address Latch Enable ALU Arithmetic and Logic Unit ASC Asynchronous synchronous Serial Controller CAN Controller Area Network License Bosch CAPCOM CAPture and COMpare unit CISC Complex Instruction Set Computing CMOS Complementary Metal Oxide Silicon CPU Central Processing Unit EBC External Bus Controller ESFR Extended Special Function Register Flash Non volatile memory that may be electrically erased GPR General Purpose Register GPT General Purpose Timer unit HLL High Level Language IIC Inter Integrated Circuit Bus IO Input Output OTP One Time Programmable memory PEC Peripheral Event Controller P
163. 8 31 CAPCOM2 Register 28 31 CCM4 CAPCOM2 Mode Control Register 4 CCM5 CAPCOM2 Mode Control Register 5 CCM6 CAPCOM2 Mode Control Register 6 CCM7 CAPCOM2 Mode Control Register 7 MCA05137 Figure 16 1 SFRs and Port Pins Associated with the CAPCOM2 Unit User s Manual 16 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 The CAPCOM2 unit is typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur It also allows the implementation of up to 16 software timers The maximum resolution of the CAPCOM unit is 8 CPU clock cycles 2 16 TCL The CAPCOM2 unit consists of a bank of 16 dual purpose 16 bit capture compare registers CC16 through CC31 and two 16 bit timers T7 T8 Each has its own reload register TXREL The input clock for the CAPCOM2 timers is programmable to several prescaled values of the CPU clock or it can be derived from an overflow underflow of timer T3 in block GPT1 T7 may also operate in counter mode from an external input where it can be clocked by external events Each capture compare register may be programmed individually for the capture or compare function and each register may be allocated to either timer Eight capture compare registers have an associated port pin which serves as an input pin for the capture function or as an output
164. A Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE BSW EW MTT RWD S 5 rw rw rw rw rw rw rw rw BUSCON2 Bus Control Register 2 SFR FF16 8B Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE BSW EW MTT RWD 7 rw rw rw rw rw rw rw rw BUSCONS3 Bus Control Register 3 SFR FF18 8C Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE BSW EW MTT RWD C3 AT vic EN3 BTYP C3 C3 MCTC x rw rw rw rw rw rw rw rw BUSCON4 Bus Control Register 4 SFR FF1Ap 8Dp Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE BSW EW MTT RWD E S rw rw rw rw rw rw rw rw Note BUSCONO is initialized with O0CO if pin EA is high during reset If pin EA is low during reset bits BUSACTO and ALECTLO are set 1 and bit field BTYP is loaded with the bus configuration selected via PORTO User s Manual 9 17 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives External Bus Interface Bit Function MCTC Memory Cycle Time Control Number of memory cycle time wait states 0000 15 waitstates Number 15 lt MCTC gt 1111 No waitstates RWDCx _ Read Write Delay Control for BUSCONx 0 With rd wr delay activate command 1 TCL after falling edge of ALE i No rd wr delay activate command with falling edge of ALE MTTCx Memory Tristate Time Control 0 1 waitstate a No waitstate BTYP External Bus Configuration 00 8 bit Demult
165. AM provide fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data The CPU has an actual register context of up to 16 wordwide and or bytewide GPRs at its disposal which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by User s Manual 2 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview the CPU at a time The number of register banks is restricted only by the available internal RAM space For easy parameter passing a register bank may overlap other register banks A system stack of up to 1024 words is provided as storage for temporary data The System stack is also located within the on chip RAM area and it is accessed by the CPU via the Stack Pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions Fo
166. ASCO Receive SORIR SORIE SORINT 00 00AC 2By 43p ASCO Error SOEIR SOEIE SOEINT 00 00BO4 2C4 44p SSC Transmit SCTIR SCTIE SCTINT 00 00B44 2Dy 45p SSC Receive SCRIR SCRIE SCRINT 00 00B84 2Ey 46p SSC Error SCEIR SCEIE SCEINT 00 00BCy 2Fy 47p CAPCOM Register 16 CC16IR CC16lE CCI6INT 00 00C04 30 48p CAPCOM Register 17 CC17IR CC17IE CC17INT 00 00C44 314 49p CAPCOM Register 18 CC18IR CC18IE CC18INT 00 00C8 324 50p CAPCOM Register 19 CC19IR CC19IE CC19INT 0000CC 334 51p CAPCOM Register 24 CC24IR CC24IE CC24INT 00 00EO0y 384 560p CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E44 394 57p CAPCOM Register 26 CC26IR CC26IE CC26INT 00 00E8 3Ay 58p CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00EC4 3By 59p CAPCOM Timer 7 T7IR T7IE T7INT 00 00FA44 3Dy 61p CAPCOM Timer 8 T8IR T8IE T8INT 00 00F8 3E 4 62p CAPCOM6 Interrupt CC6IR CC6IE CC6INT 00 00FC 3Fy 63p CAN XPOIR XPOIE XPOINT 00 01004 404 64p PLL OWD RTC XPSIR XPSIE XPS3INT 00 010C4 434 67p via ISNC ASCO Transmit Buffer SOTBIR SOTBIE SOTBINT 00 011C4 474u 71p CAPCOMG Timer 12 T12IR T12lE T121NT 00 01344 4Dyu 77p CAPCOMG Timer 13 T13IR T1S3IE T13INT 000138 4Ej 78p CAPCOM6 Emergency CC6IR CC6IE CC6EINT 00 013Cy 4Fy 79p User s Manual 5 3 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Table 5 2 lists the vector locations for hardware tra
167. B4 5A Serial Channel 0 Baud Rate Generator 0000 Reload Register PECCO FECO 60 PEC Channel 0 Control Register 0000 PECC1 FEC2 614 PEC Channel 1 Control Register 00004 PECC2 FECA 624 PEC Channel 2 Control Register 00004 PECC3 FEC6 634 PEC Channel 3 Control Register 0000 PECCA FEC8 644 PEC Channel 4 Control Register 0000 PECC5 FECA 65 PEC Channel 5 Control Register 0000 PECC6 FECCy 664 PEC Channel 6 Control Register 0000 PECC7 FECE 67 PEC Channel 7 Control Register 0000 POL b FFOO 804 Port 0 Low Reg Lower half of PORTO 00H POH b FF02 814 Port 0 High Reg Upper half of PORTO 004 P1L b FF04 82 Port 1 Low Reg Lower half of PORT1 00H P1H b FFO6 8314 Port 1 High Reg Upper half of PORT 1 004 BUSCONO b FFOC 86 Bus Configuration Register 0 0000 MDC b FFOE 87 CPU Multiply Divide Control Register 00004 PSW b FF10 88 CPU Program Status Word 0000 SYSCON b FF124 89 CPU System Configuration Register 0xx0 BUSCON1 b FF14 8A Bus Configuration Register 1 00004 BUSCON 2 b FF16j 8B Bus Configuration Register 2 0000 BUSCON3 b FF18 8C Bus Configuration Register 3 0000 User s Manual 23 15 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set Table 23 4 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Add
168. C164CM C164SM technologies Derivatives Introduction 16 Priority Level Interrupt System e 32 interrupt nodes with separate interrupt vectors e 240 ns typical interrupt latency 400 ns maximum in case of internal program execution e Fast external interrupts 8 Channel Peripheral Event Controller PEC e Interrupt driven single cycle data transfer e Transfer count option standard CPU interrupt after programmable number of PEC transfers Overhead from saving and restoring system state for interrupt requests eliminated Intelligent On Chip Peripheral Subsystems e 8 channel 10 bit A D Converter with programmable conversion time 7 8 us minimum auto scan modes channel injection mode Two Capture Compare Units with independent time bases very flexible PWM unit event recording unit with different operating modes Multifunctional General Purpose Timer Unit with three 16 bit timers counters maximum resolution fcpu 8 e Asynchronous Synchronous Serial Channel USART with baud rate generator parity framing and overrun error detection High Speed Synchronous Serial Channel programmable data length and shift direction Controller Area Network CAN Module Rev 2 0B active with 15 Message Objects Full CAN Basic CAN Real Time Clock e Watchdog Timer with programmable time intervals Bootstrap Loader for flexible system initialization 50 IO Lines with Individual Bit Addressability e Tri stated in input mode e Push
169. C164SM technologies Derivatives Power Management FOCON Frequ Output Control Reg SFR FFAA D5 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FO FO FO EN SS FORV TL FOCNT wo rw rw mwh rwh Bit Function FOCNT Frequency Output Counter FOTL Frequency Output Toggle Latch Is toggled upon each underflow of FOCNT FORV Frequency Output Reload Value Is copied to FOCNT upon each underflow of FOCNT FOSS Frequency Output Signal Select 0 Output of the toggle latch duty cycle 50 1 Output of the reload counter duty cycle depends on FORV FOEN Frequency Output Enable 0 Frequency output generation stops when signal four is gets low 1 FOCNT is running four is gated to pin First reload after 0 1 transition Note It is not recommended to write to any part of bitfield FOCNT especially while the counter is running Writing to FOCNT prior to starting the counter is obsolete because it will be immediately reloaded from FORV Writing to FOCNT during operation may produce unintended counter values User s Manual 21 18 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Power Management Signal four in the C164CM is an alternate function of pin P20 8 CLKOUT FOUT Direction CLKEN FOUT_active PortLatch fout f CPU MCA04481 Figure 21 7 Connection to Port Lo
170. C1LGML EFOA X CAN Lower Global Mask Long UUUUJ C1UMLM EFOC X CAN Upper Mask of Last Message UUUU C1LMLM EFOE X CAN Lower Mask of Last Message UUUUJ C1MCRn EFnO X CAN Message Control Register msg n UUUU C1UARn EFn2 X CAN Upper Arbitration Register msg n UUUU C1LARn EFn4 X CAN Lower Arbitration Register msg n UUUU C1MCFGn EFn6 X CAN Message Configuration Register UU msg n T12P F030 E 18 CAPCOM 6 Timer 12 Period Register 0000 T13P F032 E 194 CAPCOM6 Timer 13 Period Register 0000 T120F F034 E 1A4 CAPCOM 6 Timer 12 Offset Register 00004 CC6MSEL F036 E 1By CAPCOM 6 Mode Select Register 00004 T7 F050 E284 CAPCOM Timer 7 Register 0000 T8 F052 E29 CAPCOM Timer 8 Register 00004 T7REL F054 EjJ2A CAPCOM Timer 7 Reload Register 00004 User s Manual 23 11 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives Table 23 4 C164CM Registers Ordered by Name cont d Register Set Name Physical 8 Bit Description Reset Address _ Addr Value T8REL F056 E 2By CAPCOM Timer 8 Reload Register 0000 IDMEM2 F076 E 3By_ Identifier 0000 IDPROG F078 E 3C _ Identifier XXXXy IDMEM FO7A E 3D4y_ Identifier X008 IDCHIP F07C E 3E _ Identifier XXXXy IDMANUF FO7E E 3F _ Identifier 18204 POCONOL FO80 E 40 Port POL Output Control Register 00114
171. COUT6x Initial value 1 A Interrupt can be generated MCB03356 Figure 17 3 CAPCOM6 Basic Operating Modes User s Manual 17 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 1 Output Signal Level Control The output signals generated by the CAPCOM6 unit are characterized by the duration of their active and passive phases which define the signals period and duty cycle In order to adapt these output signals to the requirements of a specific application the logic level of the passive state for each signal can be selected via register CC6MCON When using the trap function the outputs are switched to their trap level upon the activation of an external emergency signal The trap level is defined via the respective port output latches Note Changing the state levels during operation of CAPCOM6 will immediately affect the output signals It is recommended that the output levels be defined during initialization before the output signals are assigned and before the CAPCOM6 unit is started In burst and multi channel modes the signals generated by the capture compare channels may additionally be modulated by the signal generated by the 10 bit compare channel Optionally this compare channel signal may be inverted before modulating the other outputs The compare channels signal may be output on pin COUT63 This output
172. Chip CAN Interface Data Area The data area occupies 8 successive byte positions after the Message Configuration Register such that the data area of message object n covers locations 00 EFn7 through 00 EFnEy Location OO EFnF is reserved Message data for message object 15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one Handling of Message Objects Figure 19 6 through Figure 19 11 summarize the actions which must be taken to transmit and receive messages over the CAN bus The actions taken by the CAN controller are described as well as the actions to be taken by the CPU the servicing program The diagrams show these actions e CAN controller handling of transmit objects e CAN controller handling of receive objects e CPU handling of transmit objects e CPU handling of receive objects e CPU handling of last message object e Handling of the last message s alternating buffer User s Manual 19 23 V1 0 2002 02 technologies C164CM C164SM Derivatives On Chip CAN Interface yes Bus free yes NEWDAT 0 Load message into buffer no Transmission successful no lt D o lt lt D D o o INTPND 1 0 Reset 1 Set no TXRQ 0 RMTPND 0 no Received remote frame with same identifier as this
173. Cx is modified from cv1 to cv2 after compare event 1 Compare event 2 however will not occur until the next period of timer Ty Interrupt Request Set Port Mode 3 ee Ccoxio Reset CCMODx Compare Reg CCx C Interrupt Request X 2 81 16 not all channels are connected to port pins and interrupt nodes y 7 8 MCB02019a Figure 16 8 Compare Mode 2 and 3 Block Diagram Note The port latch and pin remain unaffected in compare mode 2 Contents of Ty FFFF Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000 Interrupt Requests TyIR CCxIR TyIR CCxIR TyIR State CCXO I I 1 0 time A Event 1 Event 2 CCx cv2 CCx cv1 Output pin CCxIO only effected in mode 3 No changes in mode 2 X 31 16 y 7 8 MCBO05121 Figure 16 9 Timing Example for Compare Modes 2 and 3 User s Manual 16 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Compare Mode 3 Compare mode 3 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 111g In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected the interrupt request flag CCxIR is set to 1 where connected and the output pin CCxIO alternate por
174. DAT Read Mode there may be delays due to suspended conversions However this affects the conversions only if the CPU or PEC cannot keep up with the conversion rate 3 2 1 wait 0 3 Chern OOOO O of Channel Write ADDAT X 3 2 1 0 3 ADDAT Full Temp Latch Full Generate Interrupt Hold Result in Request Temp Latch Read of ADDAT Result of Channel x 3 2 1 0 MCA01970 Figure 18 4 Wait for Read Mode Example User s Manual 18 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter Channel Injection Mode Channel Injection Mode allows conversion of a specific analog channel also while the ADC is running in a continuous or auto scan mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection Mode is enabled by setting bit ADCIN in register ADCON and requires the Wait for ADDAT Read Mode ADWR 1 The channel to be converted in this mode is specified in bitfield CHNR of register ADDAT2 Note Bitfield CHNR in ADDAT2 is not modified by the A D converter only the ADRES bit field is modified Because the channel number for an injected conversion is not buffered bit field CHNR of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is re
175. Data and control information are interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deterministic CPU action an on chip Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt will occur There are two basic types of interrupt processing e Standard interrupt processing forces the CPU to save the current program status and return address on the stack before branching to the interrupt vector jump table PEC interrupt processing steals only one machine cycle from the current CPU activity to perform a single data transfer via the on chip Peripheral Event Controller PEC System errors detected during program execution hardware traps and external non maskable interrupts are also processed as standard interrupts with a very high priority In contrast to other on chip peripherals there is a closer conjunction between the watchdog timer and the CPU If enabled the watchdog timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Thus the watchdog timer is able to prevent the CPU from going astray when executing erroneous code After reset the watchdog timer starts counting automatically but it can be disabled via software if desired In ad
176. E passive 1 IO O passive passive ACTIVE ACTIVE passive passive 1 1 O passive ACTIVE passive ACTIVE passive passive O 1 O passive ACTIVE passive passive passive ACTIVE O 1 1 ACTIVE passive passive passive passive ACTIVE O O 1 ACTIVE passive passive passive ACTIVE passive Rotate Right 1 1 O ACTIVE passive passive passive ACTIVE passive 1 O O ACTIVE passive passive passive passive ACTIVE 1 O 1 passive ACTIVE passive passive passive ACTIVE O O 1 passive ACTIVE passive ACTIVE passive passive O 1 1 passive passive ACTIVE ACTIVE passive passive O 1 O passive passive ACTIVE passive ACTIVE passive Rotate Left Jo lo lo passive passive passive passive passive passive Rotate Right 4 4 1 passive passive passive passive passive passive Slow Down X X X passive passive passive ACTIVE ACTIVE ACTIVE Idle X X X passive passive passive passive passive passive 1 If one of these two input signal combinations is detected in rotate left or rotate right mode bit BCERR is set If enabled an emergency interrupt is generated When these error states are encountered the idle state is entered immediately wY Idle state can only be left when the BCERR flag is cleared by software User s Manual 17 16 Idle state is entered when a wrong follower
177. E414 Port POH Output Control Register 0011 POCONOL F080 E404 Port POL Output Control Register 0011 POCON1H F086 E434 Port P1H Output Control Register 0011 POCON1L F084 E424 Port P1L Output Control Register 00114 POCON20 FOAA E554 Port P20 Output Control Register 00004 POCONS8 F092 E494 Port P8 Output Control Register 00224 PSW b FF10 88 CPU Program Status Word 0000 PTCR FOAE E574 Port Temperature Compensation Reg 0000 RPOH b F108 E 84 System Startup Config Reg Rd only XXy RSTCON b F1E0 m Reset Control Register 00XXy RTCH FOD6 Ej 6B RTCHigh Register no RTCL FOD4 E 6A RTC Low Register no SOBG FEB4y 5Ap Serial Channel 0 Baud Rate Generator 0000 Reload Register SOCON b FFBO D8 Serial Channel 0 Control Register 00004 SOEIC b FF70 B8 Serial Channel 0 Error Interrupt Ctrl 0000 Reg SORBUF FEB2 59 Serial Channel 0 Receive Buffer Reg XXXXy read only SORIC b FF6E B7 Serial Channel 0 Receive Interrupt 00004 Control Register SOTBIC b F19C E CE Serial Channel 0 Transmit Buffer 00004 Interrupt Control Register SOTBUF FEBO 584 Serial Channel 0 Transmit Buffer Reg 0000 write only SOTIC b FF6C B6 Serial Channel 0 Transmit Interrupt 0000 Control Register User s Manual 23 8 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set Table 23 3 C164CM Registers Ordered by Name cont d
178. EINT Read ADDAT2 y MCA01972 Figure 18 6 Channel Injection Example with Wait for Read User s Manual 18 11 V1 0 2002 02 _ e Infineon C164CM C164SM technologies Derivatives Analog Digital Converter Arbitration of Conversions Conversion requests activated while the ADC is idle immediately trigger the requested conversion If a conversion is requested while another conversion is already in progress the operation of the A D converter depends on the type of conversions involved either standard or injected Note A conversion request is activated if the respective control bit ADST or ADCRQ is toggled from 0 to 1 i e the bit must have been zero before being set Table 18 1 summarizes ADC operation in the situations possible Table 18 1 Conversion Arbitration Conversion New Requested Conversion in Progress stangard Injected Standard Abort running conversion Complete running conversion and start requested new start requested conversion after that conversion Injected Complete running conversion Complete running conversion start requested conversion after start requested conversion after that that Bit ADCRQ will be 0 for the second conversion however User s Manual 18 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter 18 2 Conversion Timing Control When a conversion is started
179. EN in register SYSCON to be set in order to be operable Control Registers Object Registers Core Registers within each module within each module Interrupt Control SYSCON SYSCONS E DP8 ODP8 E SYSCON System Configuration Register CSR Control Status Register SYSCONS Peripheral Management Control Reg PCIR Port Control Interrupt Register DP8 Port 8 Direction Control Register BTR Bit Timing Register ODP8 Port 8 Open Drain Control Register GMS Global Mask Short XPOIC CAN1 Interrupt Control Register U LGML Global Mask Long U LMLM Last Message Mask MCRn Configuration Register of Message n U LARn Arbitration Register of Message n MCA05126 Figure 19 1 Registers Associated with the CAN Module User s Manual 19 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit s The minimum CPU clock frequency to achieve 1 Mbit s is fopy 2 8 16 MHz depending on the activation of the CAN module s clock prescaler The CAN module uses two pins of Port 8 to interface to a bus transceiver The CAN module provides Full CAN functionality for up to 15 full sized message objects 8 data bytes each Message object 15 may be configured for Basic CAN functionality with a double buffered receive object The Full CAN and Basic CAN modes provide separate masks for acceptance filtering to accept
180. Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 bytes per entry All interrupt nodes which are currently not used by their associated modules or are not connected to a module in the actual derivative may be used to generate software controlled interrupt requests by setting the respective IR flag User s Manual 5 2 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives Table 5 1 Interrupt and Trap Functions C164CM Interrupt Nodes and Vectors Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number Fast External Interrupt O CC8IR CC8IE CC8INT 00 0060 184 245 Fast External Interrupt 1 CC9IR CC9IE CC9INT 00 0064y 194 25p Fast External Interrupt 2 CC10IR CC10IE CC10INT 00 00684 1A4 26p Fast External Interrupt 3 CC11IR CC111E CC11lINT 00 006C 1By 27p GPT1 Timer 2 T2IR T2lE T2INT 00 00884 224 34p GPT1 Timer 3 T3IR TSIE TSINT 00 008C 234 35p GPT1 Timer 4 T4IR T4IE TAINT 00 00904 244 36p A D Conversion Complete ADCIR ADCIE ADCINT 00 00A0 28 40p A D Overrun Error ADEIR ADEIE ADEINT O00 00A4y 294 41p ASCO Transmit SOTIR SOTIE SOTINT 00 00A84 2Ay 42p
181. FIE 8F Constant Value 1 s Register read only FFFF OPAD EDC2 X OTP Progr Interface Address Register 00004 OPCTRL EDCO X OTP Progr Interface Control Register 00074 OPDAT EDC4 X OTP Progr Interface Data Register 00004 POH b FFO2 814 Port 0 High Reg Upper half of PORTO 004 POL b FFOO 804 Port 0 Low Reg Lower half of PORTO 00H P1H b FFO6 8314 Port 1 High Reg Upper half of PORT 1 004 P1L b FF04 824 Port 1 Low Reg Lower half of PORT1 00H P5 b FFA2 Dip Port 5 Register read only XXXXy P5DIDIS _b FFA4 D2 Port 5 Digital Input Disable Register 0000 P20 b FFB4 DA Port 20 Register 6 bits 00H P8 b FFD44 EA Port8 Register 4 bits 00H PECCO FECO 60 PEC Channel 0 Control Register 0000 PECC1 FEC2 614 PEC Channel 1 Control Register 00004 PECC2 FEC4 62 PEC Channel 2 Control Register 0000 PECC3 FEC6 634 PEC Channel 3 Control Register 0000 User s Manual 23 7 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set Table 23 3 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Address Addr Value PECC4 FEC8 644 PEC Channel 4 Control Register 0000 PECC5 FECA 654 PEC Channel 5 Control Register 0000 PECC6 FECCy 664 PEC Channel 6 Control Register 0000 PECC7 FECE 67 PEC Channel 7 Control Register 0000 POCONOH F082
182. FR FEA0 50 Analog Digital Converter Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES rwh rwh ADDAT2 ADC Chan Inj Result Reg ESFR F0A0 50 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES rw rwh Bit Function ADRES A D Conversion Result The 10 bit digital result of the most recent conversion CHNR Channel Number identifies the converted analog channel User s Manual 18 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter A conversion is started by setting bit ADST 1 The busy flag ADBSY will be set Then the converter selects and samples the input channel specified by the channel selection field ADCH in register ADCON The sampled level will then be held internally during the conversion When the conversion of this channel is complete the 10 bit result and the number of the converted channel are transferred into the result register ADDAT and the interrupt request flag ADCIR is set The conversion result is placed into bitfield ADRES of register ADDAT If bit ADST is reset via software while a conversion is in progress the A D converter will stop after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Setting bit ADST wh
183. Hz Resolution 400 ns 800ns 1 6us 3 2us 6 4us 12 8 us 25 6 us 51 2 us Period 26 2 ms 52 5 ms 105 ms 210 ms 420 ms 840 ms 1 68s 3 36s Table 10 3 GPT1 Timer Input Frequencies Resolution and Periods 25 MHz Scpu 25 MHz Timer Input Selection T2I T3I T4I 000g 001g 010g 011g 100 101g 110 111g Prescaler 8 16 32 64 128 256 512 1024 Factor Input 3 125 1 56 781 25 390 62 195 3 97 65 48 83 24 42 Frequency MHz MHz kHz kHz kHz kHz kHz kHz Resolution 320 ns 640 ns 1 28 us 2 56 us 5 12 us 10 2 us 20 5 us 41 0 us Period 21 0 ms 41 9 ms 83 9 ms 168 ms 336 ms 671 ms 1 34 s 2 68s Table 10 4 GPT1 Timer Input Frequencies Resolution and Periods 33 MHz fcpu 33 MHz Timer Input Selection T2I TSI T4I 000g 001g 010g 011g 1008 101g 1105 111g Prescaler 8 16 32 64 128 256 512 1024 Factor Input 4 125 2 0625 1 031 515 62 257 81 128 91 64 45 32 23 Frequency MHz MHz MHz kHz kHz kHz kHz kHz Resolution 242 ns 485ns 970ns 1 94 us 3 88 us 7 76 us 15 5 us 31 0 us Period 15 9 ms 31 8 ms 63 6 ms 127 ms 254 ms 508 ms 1 02 s 2 03 s User s Manual 10 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 010 or 011 Bit T3M 0 T3CON 3 s
184. Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface En nudas Register XReg EF04 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TSEG2 TSEG1 SJW BRP r nw rw rw rw Bit Function BRP Baud Rate Prescaler To generate the bit time quanta the CPU frequency fcpy is divided by 2 1 CPS x BRP 1 See also the prescaler control bit CPS in register CSR SJW Re Synchronization Jump Width Adjust the bit time by maximum SJW 1 time quanta for resynchronization TSEG1 Time Segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 TSEG2 Time Segment after sample point There are TSEG2 1 time quanta after the sample point Valid values for TSEG2 are 1 7 Note This register can only be written if the config change enable bit CCE is set Hard Synchronization and Resynchronization To compensate for phase shifts between clock oscillators of different CAN controllers any CAN controller must synchronize on any edge from recessive to dominant bus level if the edge lies between a Sample Point and the next Synchronization Segment and on any other edge if it does not send a dominant level itself If the Hard Synchronization is enabled at the Start of Frame the bit time is restarted at the Synchronization Segment otherwise the Resynchronizat
185. L Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE User s Manual 22 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming The save sequence shown above and the restore sequence after COPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In this case the information required to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For division the user must first move the dividend into the MD register If a 16 16 bit division is specified only the low portion of register MD must be loaded The result is also stored into register MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds divisor JMPR cc_V ERROR Test for divide overflow MOV R3 MDH Move remainder to
186. LA Programmable Logic Array PLL Phase Locked Loop PWM Pulse Width Modulation RAM Random Access Memory RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real Time Clock SDD Slow Down Divider SFR Special Function Register SSC Synchronous Serial Controller XBUS Internal representation of the External Bus XRAM On chip extension RAM User s Manual 1 8 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 Architectural Overview The architecture of the C164CM core combines the advantages of both RISC and CISC processors in a very well balanced way The C164CM integrates this powerful CPU core with a set of powerful peripheral units into one chip and connects them very efficiently This combination of features results in a high performance microcontroller which is the right choice not only for today s applications but also for future engineering challenges One of the four buses used concurrently on the C164CM is the XBUS an internal representation of the external bus interface This bus provides a standardized method for integrating additional application specific peripherals into derivatives of the standard C164CM ProgMem C166 Core ROM OTP 2 YE Internal Instr Data 32 KByte liom N I External Instr Data T6 Level Interrupt Controller Priorit g Interrupt Bus Peripheral Data Bus
187. LL off the internal reset condition is extended so the PLL can lock before execution begins The reset condition is terminated prematurely if no stable oscillator clock is detected This ensures the operability of the device in case of a missing input clock signal Switching to Slow Down operation affects frequency sensitive peripherals such as serial interfaces timers PWM etc If these units are to be operated in Slow Down mode their precalers or reload values must be adapted Please note that the reduced CPU frequency decreases such things as timer resolution and increases the step width for example for baudrate generation The oscillator frequency in such a case should be chosen to accommodate the required resolutions and or baudrates User s Manual 21 12 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Power Management SYSCON2 System Control Reg 2 ESFR F1DO E8 Reset Value 00X0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gee CLKREL CLKCON SCS RCS PDCON SYSRLS rh rw rw rw rw rw rwh Bit Function SYSRLS Register Release Function Unlock field Must be written in a defined way in order to execute the unlock sequence See separate description Table 21 6 PDCON Power Down Control during power down mode 00 RTC On Ports On default after reset 01 RTC On Ports Off 10 RTC Off Ports On 11 RTC Off Ports Off
188. M Flash OTP where integrated internal RAM the internal Special Function Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals and external memory are mapped into one common address space The C164CM provides a total addressable memory space of 16 MBytes This address space is arranged as 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each see Figure 3 1 ER FFFFFF 254 129 800000 i 126 65 o 5 E 01 8000 62 12 7 oO OA Ain Alternate y ROM a Area 01 0000 08 0000 Data Page 3 Data Page 2 NEC HNEN ddl ROM O FFFF ambo Area Segment 0 000000 Total Address Space Segments 1 and 0 16 MByte Segments 255 0 64 64 KByte 64 KByte External Addressing Capability MCA05131 Figure 3 1 Address Space Overview User s Manual 3 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization Most internal memory areas are mapped into segment 0 the system segment The upper 4 KBytes of segment O 00 F000 OO FFFF hold the Internal RAM and Special Function Register Areas SFR and ESFR The lower 32 KBytes of segment 0 00 0000 00 7FFFp may be occupied by a portion of the on chip ROM Flash OTP memory and is called the Internal ROM area This ROM area can be remapped to segment 1 01 0000 01 7FFF j to enable externa
189. Manual 20 18 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset 20 4 2 System Startup Configuration at Single Chip Mode Reset For a single chip mode reset indicated by EA 1 the configuration via PORTO is replaced by a fixed configuration value In this case PORTO needs no external circuitry pull ups pull downs and also the internal configuration pull ups are not activated The necessary startup modes are configured via pins RD and ALE The operating mode for Port 20 pins can be configured via pin WR which is not necessarily used in single chip mode This fixed default configuration is activated after each Long Hardware Reset and selects a safe worst case configuration The initialization software can then modify these parameters and select the intended configuration for a given application Table 20 5 lists the respective default configuration values which are selected and the bitfields which permit software modification Table 20 5 Default Configuration for Single Chip Mode Reset Configuration Default Values External Software Access Parameter RPOH XX2D j Config CLKCFG Generation 001 Prescaler operation PO 15 13 RSTCON 15 13 mode of basic clock i e fcpu 7 fosc 2 BTYP Default bustype BUSCONO BTYP 11 P0 7 6 BUSCONO BTYP BUSCONO i e 16 bit MUX bus SMOD Special modes Startup modes selected via P0 5 2 start boot
190. Manual 6 5 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Clock Generation The internal operation of the C164CM is controlled by the internal CPU clock fcpy Both edges of the CPU clock can trigger internal operations example pipeline or external operations example bus cycles operations See Figure 6 5 Phase Locked Loop Operation fosc CL fo feru Direct Clock Drive CL fo forpu Prescaler Operation t t CL CL feru SDD Operation fee LI LI LILI LILI LILI Lit foru CLKREL 2 Direct Drive CL Jopu CLKREL 2 Prescaler MCD04459 Figure 6 5 Generation Mechanisms for the CPU Clock User s Manual 6 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Clock Generation Direct Drive When direct drive is configured CLKCFG 011g the C164CM s clock system is directly fed from the external clock input i e fopy fosc This allows operation of the C164CM with a reasonably small fundamental mode crystal The specified minimum values for the CPU clock phases TCLs must be respected Therefore the maximum input clock frequency depends on the clock signal s duty cycle Prescaler Operation When prescaler operation is configured CLKCFG 001p the C164CM s input clock is divided by 2 to generate the CPU clock signal i e fcpy fosc 2 This requires the oscillator or input clock to run on 2 times the
191. N for the possible selections Note To use pin T7IN as external count input pin the respective port pin must be configured as input the corresponding direction control bit must be cleared DPx y 0 If the respective port pin is configured as output the associated timer may be clocked by modifying the port output latches Px y via software such as for testing purposes The maximum external input frequency to T7 in counter mode is fcpu 16 To ensure that a signal transition is properly recognized at the timer input an external count input signal should be held for at least eight CPU clock cycles before it changes its level again The incremented count value appears in SFR T7 within eight CPU clock cycles after the signal transition at pin T7IN Reload In both modes a reload of a timer with the 16 bit value stored in its associated reload register is performed each time a timer would overflow from FFFFy to 00004 In such a case the timer does not wrap around to 0000 but rather is reloaded with the contents of the respective reload register TxREL The timer then resumes incrementing starting from the reloaded value The reload registers TxREL are not bit addressable User s Manual 16 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 16 2 CAPCOM2 Unit Timer Interrupts When a timer overflows the corresponding timer interrupt request flag TxIR for the respecti
192. ND Rn 04 Clear register CPLB Bit BMOVN Bit Bit Complement bit DEC Rn SUB Rn 14 Decrement register INC Rn ADD Rn 14 Increment register SWAPB Rn ROR Rn 84 Swap bytes within word Modification of System Flags is performed using bit set or bit clear instructions BSET BCLR All bit and word instructions can access the PSW register so instructions such as CLEAR CARRY or ENABLE INTERRUPTS are not required External Memory Data Access does not require special instructions to load data pointers or explicitly load and store external data The C164CM provides a Von Neumann memory architecture and its on chip hardware automatically detects accesses to internal RAM GPRs and SFRs Multiplication and Division Multiplication and division of words and double words are provided through multiple cycle instructions implementing a Booth algorithm Each instruction implicitly uses the 32 bit register MD MDL lower 16 bits MDH upper 16 bits The MDRIU flag Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide instruction is started It is cleared whenever the MDL User s Manual 22 1 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives System Programming register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require m
193. O Asynchronous Data Frames 8 bit data frames consist of either 8 data bits D7 DO SOM 001 or 7 data bits D6 DO plus an automatically generated parity bit SOM 011 Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 8 bit data mode The parity error flag User s Manual 11 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 7 1st 2nd Stop Stop Bit Bit MCT04377 Figure 11 3 Asynchronous 8 bit Data Frames 9 bit data frames consist of either 9 data bits D8 DO SOM 100 8 data bits D7 DO plus an automatically generated parity bit SOM 111p or 8 data bits D7 DO plus a wake up bit SOM 101 Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 8 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 9 bit data and wake up modes The parity error flag SOPE will be set along
194. O Error Interrupt Control Register MCA05133 Figure 11 1 SFRs and Port Pins Associated with ASCO User s Manual 11 1 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface The operating mode of the serial channel ASCO is controlled by its bit addressable control register SOCON This register contains control bits for mode and error check selection as well as status flags for error identification SOCON ASCO Control Register SFR FFBO D8 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soR S0 S0 SO _ so SO SO SO SO SO SO SO SOM LB BRS ODD OE FE PE OEN FEN PEN REN STP wo IW mw srw wh wh wh rw rw rw mh rw rw Bit Function SOM ASCO Mode Control 000 8 bit data synchronous operation 001 8 bit data asynchronous operation 010 Reserved Do not use this combination 011 7 bit data parity asynchronous operation 100 9 bit data asynchronous operation 101 8 bit data wake up bit asynchronous operation 110 Reserved Do not use this combination 111 8 bit data parity asynchronous operation SOSTP Number of Stop Bits Selection asynchronous operation 0 One stop bit 1 Two stop bits SOREN Receiver Enable Bit 0 Receiver disabled 1 Receiver enabled Reset by hardware after reception of byte in synchronous mode SOPEN Parity Check Enable Bit
195. O and SSC PORT1 provides input and output signals for the CAPCOM units Port 5 is used for timer control signals and for the analog inputs to the A D Converter Port 8 provides inputs outputs for the CAPCOM2 unit and for the CAN interface Port 20 includes control signals of the external bus interface the RSTOUT signal and the system clock output CLKOUT FOUT All port lines not used for these alternate functions may be used as general purpose I O lines User s Manual 2 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview A D Converter For analog signal measurement a 10 bit Analog Digital A D Converter with eight multiplexed input channels and a sample and hold circuit has been integrated on chip It uses the method of successive approximation The sample time for loading the capacitors and the conversion time are programmable and can so be adjusted to the external circuitry Overrun error detection protection is provided for the conversion result register ADDAT either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete or the next conversion is suspended in such a case until the previous result has been read For applications which require fewer analog input channels the remaining channel inputs can be used as digital input port pins The A D Converter of the
196. ON OPCTRL OTP Control Register XReg EDCO Reset Value 0007 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEGAD RS CEQ WRQ RDQ rw rw rw rw rw Bit Function RDQ Read Signal active low 0 OTP module selected for a verify read access p Read access is completed WRQ Write Signal active low 0 OTP module selected for a write access programming 1 Write access is completed CEQ OTP Module Enable Signal active low 0 OTP module is selected 1 OTP module is deselected no access RS Register Select Signal RSEL 0 Access the OTP memory module 1 Access the control section read protection control SEGAD Physical Segment Address Provides the upper physical address lines A23 A16 to the OTP memory module SEGAD must be 00 for the C164CM User s Manual 3 16 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives Memory Organization An OTP programming verify cycle is executed by a sequence of accesses to the programming interface which emulate the externally controlled cycles see example below OTP Programming Example The on chip OTP memory is programmed in CHM executing the following procedure Note The example below assumes segment 0 RH3 00 MOV R1 OTP START R1 OTP pointer MOV R2 DATA BLOCK R2 Source data pointer MOV R3 0003H 03H enable module cmd idle MOV DPP3 OPCTRL R3 Initially enable the OTP module BSET VPP ENABLE External progr voltage ON CALL
197. OUT deactivated by EINIT WDT WDTCON J RSTIN bidirectional reset only Figure 13 1 SFRs and Port Pins Associated with the Watchdog Timer MCA04381 The watchdog timer is a 16 bit up counter which is clocked with the prescaled CPU clock fcpu The prescaler divides the CPU clock by 2 WDTIN 0 WDTPRE 0 or by 4 WDTIN 0 WDTPRE 1 or e by 128 WDTIN 1 WDTPRE 0 or e by 256 WDTIN 1 WDTPRE 1 User s Manual 13 1 V1 0 2002 02 _ e Infineon C164CM C164SM technologies Derivatives Watchdog Timer WDT The 16 bit watchdog timer is implemented as two concatenated 8 bit timers see Figure 13 2 The upper 8 bits of the watchdog timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset after each service access WDTPRE WDTIN jai gt WDT Low Byte Clear WDT High Byte 1A Control WDTREL MCB04470 WDTR Rsrour Reset WDT Figure 13 2 Watchdog Timer Block Diagram User s Manual 13 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Watchdog Timer WDT 13 1 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register Operation of the Watchdog Timer is con
198. On Chip CAN Interface XReg EFn0 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSGLST RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND nw nw nw nw nw rw rw rw Bit Function INTPND Interrupt Pending Indicates whether this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the CPU RXIE Receive Interrupt Enable Defines whether bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines whether bit INTPND is set after successful transmission of a frame MSGVAL Message Valid Indicates whether the corresponding message object is valid The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all NEWDAT New Data Indicates whether new data has been written into the data portion of this message object by CPU transmit objects or CAN controller receive objects since this bit was last reset MSGLST Message Lost This bit applies to receive objects only Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set thus the previously stored message is lost CPUUPD CPU Update This bit applies to transmit objects only Indicates that the corresponding message object may not be transmitted now The CPU sets this bit to inhibit
199. P1H 7 4 CC27 241O CAPCOM Register 27 24 Capture Input CC27 CC24 P8 3 0 CC19 1610 CAPCOM Register 19 16 Capture Input CC19 CC16 P5 6 T21N Auxiliary timer T2 input pin T2CON P5 7 T4IN Auxiliary timer T4 input pin T4CON User s Manual 5 25 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions When port pins CCxIO are to be used as external interrupt input pins bit field CCMODx in the control register of the corresponding capture compare register CCx must select capture mode When CCMODx is programmed to 001g the interrupt request flag CCxIR in register CCxIC will be set on a positive external transition at pin CCxlO When CCMODx is programmed to 010g a negative external transition will set the interrupt request flag When CCMODx 011g both a positive and a negative transition will set the request flag In all three cases the contents of the allocated CAPCOM timer will be latched into capture register CCx independent of whether or not the timer is running When the interrupt enable bit CCxIE is set a PEC request or an interrupt request for vector CCxINT will be generated Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or TACON to 101g The active edge of the
200. P1L b F104 E 82 P1L Direction Control Register 004 DP20 b FFB6 DBy Port 20 Direction Control Register 00g DP8 b FFD6j EB Port 8 Direction Control Register 004 DPPO FEOO O0 CPU Data Page Pointer 0 Reg 10 bits 0000 DPP1 FEO2y Oi CPU Data Page Pointer 1 Reg 10 bits 0001 DPP2 FEO4 02 CPU Data Page Pointer 2 Reg 10 bits 0002 User s Manual 23 6 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Register Set Table 23 3 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Address _ Addr Value DPP3 FEO6 034 CPU Data Page Pointer 3 Reg 10 bits 0003 EXICON b F1CO E E0O External Interrupt Control Register 0000 EXISEL b F1DA E ED External Interrupt Source Select Reg 00004 FOCON b FFAA D5 Frequency Output Control Register 00004 IDCHIP F07C E 3E _ Identifier XXXXy IDMANUF FO7E E 3F _ Identifier 18204 IDMEM FO7A E 3D4 Identifier X008 IDPROG F078 E 3C _ Identifier XXXXy IDMEM2 FO76 E 3By_ Identifier 0000 ISNC b F1DE E EF Interrupt Subnode Control Register 0000 MDC b FFOE 87 CPU Multiply Divide Control Register 00004 MDH FEOC 06 CPU Multiply Divide Reg High Word 0000 MDL FEOE 07 CPU Multiply Divide Reg Low Word 00004 ODP8 b F1D6 E EB Port 8 Open Drain Control Register 00H ONES b F
201. P5 4 TSIN P5 3 T3EUD P5 2 TAIN P5 7 T4EUD P5 5 P5 Port 5 Data Register T2 GPT1 Timer 2 Register P5DIDIS Port 5 Digital Input Disable Register T3 GPT1 Timer 3 Register T4 GPT1 Timer 4 Register T2CON GPT1 Timer 2 Control Register T2IC GPT1 Timer 2 Interrupt Control Register T3CON GPT1 Timer 3 Control Register T3IC GPT1 Timer 3 Interrupt Control Register T4CON GPT1 Timer 4 Control Register T4IC GPT1 Timer 4 Interrupt Control Register MCA05135 Figure 10 1 SFRs and Port Pins Associated with Timer Block GPT1 User s Manual 10 1 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit All three timers of block GPT1 T2 T3 T4 can run in 4 basic modes timer gated timer counter and incremental interface mode All timers can count either up or down Each timer has an alternate input function pin TxIN associated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin Each overflow underflow of core timer T3 is latched in the toggle FlipFlop TSOTL and may be indicated on an alternate output function pin The auxiliary timers T2 and T4 may additionally be concatenated with the core timer or may be used as capture or reload registers for the core timer The current contents of each timer can
202. R3 MOV R4 MDL Move integer result to R4 Clears MDRIU Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the multiply divide instruction is re read from the location popped from the stack return address and will be completed after the RETI instruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupting routine does not return to the interrupted task for example scheduler switches to another task the MULIP flag must be set or cleared according to the context of the task to be executed next BCD Calculations No direct support for BCD calculations is provided in the C164CM BCD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10p Conversion from BCD data to binary data is enhanced by multiple bit shift instructions This provides similar performance compared to instructions directly supporting BCD data types without requiring additio
203. RAP CC6n COUT6n CC6POSn Fast external interrupt inputs EXSIN EXOIN CAPCOM timer input T7IN Port5 Analog input channels to the A D converter AN7 ANO Timer control signal inputs T2EUD T3EUD T4EUD T2IN T3IN TAIN Port 8 Capture inputs or compare outputs of the CC1910 CC161O CAPCOM2 unit CAN interface when assigned CAN1_TxD CAN1_RxD Port 20 Bus control signals RD WR ALE System clock or programmable frequency CLKOUT FOUT output reset output configuration input RSTOUT EA If an alternate output function of a pin is to be used the alternate data must be routed to the output driver and the driver must be enabled For some alternate output signals such as bus signals or X Peripheral signals this is done automatically via separate control lines indicated by control line AItEN in the subsequent port figures For the remaining alternate output signals this has to be accomplished by user software If the alternate signal is combined with the port latch signal the respective port latch must be set accordingly see individual port figures The output driver must be enabled by switching the pin to output DPx y 1 Otherwise the pin remains in the high impedance state and is not affected by the alternate output function If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction
204. RTC is running When reading or writing the RTC value such internal overflows must be taken into account to avoid reading writing corrupted values For example reading writing 0000 to RTCH and then accessing RTCL will produce a corrupted value as RTCL may overflow before it can be accessed In this case however RTCH would be 0001 The same precautions must be taken for T14 and T14REL RTC Interrupt Generation The RTC interrupt shares the XPER3 interrupt node with the PLL OWD interrupt This is controlled by the interrupt subnode control register ISNC The interrupt handler can determine the source of an interrupt request via the separate interrupt request and enable flags see Figure 14 3 provided in register ISNC Note If only one source is enabled no additional software check is required of course dod PLLIR eo Interrupt PLLIE Intr Request Intr Enable n Interrupt UP Controller Node Tia RTCIR eo Interrupt RTCIE Intr Request Intr Enable Register ISNC Register XP3IC MCA04464 Figure 14 3 RTC Interrupt Logic If T14 interrupts are to be used both stages the interrupt node XPSIE 1 and the RTC subnode RTCIE 1 must be enabled Please note that the node request bit XP3IR is automatically cleared when the interrupt handler is vectored to while the subnode request bit RTCIR must be cleared by software User s Manual 14 3 V1 0 2002 02 _ Infineon C164CM C164SM technol
205. System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction Bit SGTDIS controls the correct stack operation push pop of CSP or not during traps and interrupts The layout of the BUSCON registers and ADDRSEL registers is identical respectively Registers BUSCON4 BUSCON control the selected address windows and are completely under software control Register BUSCONO which for example is also used for the very first code access after reset is partly controlled by hardware that is it is initialized via PORTO during the reset sequence This hardware control allows defining an appropriate external bus for systems where no internal program memory is provided User s Manual 9 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface BUSCONO Bus Control Register 0 SFR FF0C 86 Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE BSW EW MTT RWD CO BE ws ENO BTYP CO CO MCTC rw mwh mh rw rwh Ww Iw rw BUSCON1 Bus Control Register 1 SFR FF14 8
206. TXRQ 1 lt 0 Reset 1 Set MCA04397 Figure 19 8 CPU Handling of Transmit Objects DIR 1 User s Manual 19 26 V1 0 2002 02 technologies C164CM C164SM Derivatives On Chip CAN Interface Power Up Initialization Process Start Process Process End 0 Reset 1 Set all bits undefined TXIE application cpecific RXIE application cpecific INTPNDd 0 RMTPND 0 TXRQ 0 MSGLST 0 Identifier application cpecific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application cpecific NEWDAT 0 Process message contents gt lt Restart process Request Update MCA04398 Figure 19 9 CPU Handling of Receive Objects DIR 0 User s Manual 19 27 V1 0 2002 02 C164CM C164SM Derivatives technologies On Chip CAN Interface Power Up all bits undefined RXIE application cpecific INTPND 0 RMTPND 0 MSGLST 0 Identifier application cpecific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application cpecific Initialization Process Start Process message contents NEWDAT 0 Process t i P Process End Restart process 0 Reset 1 Set MCA04399 Figure 19 10 CPU Handling of the Last Message Object
207. This can be done by the CPU via software or by the CAN controller automatically on a hardware reset or if the EML switches to busoff state While INIT is set All message transfer from and to the CAN bus is stopped The CAN transmit line CAN_TXD is 1 recessive Control bits NEWDAT and RMTPND of the last message object are reset Counters of the EML are left unchanged Additionally setting bit CCE permits configuration changes in the Bit Timing Register To initialize the CAN Controller the following actions are required Configure the Bit Timing Register CCE required e Set the Global Mask Registers Initialize each message object If a message object is not needed it is sufficient to clear its message valid bit MSGVAL that is to define it as not valid Otherwise the entire message object must be initialized After the initialization sequence has been completed the CPU clears bit INIT Now the BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits i e Bus Idle before it can take part in bus activities and start message transfers Initialization of the message objects is independent of the state of bit INIT and can be done on the fly The message objects should all be configured to particular identifiers or set to not valid before the BSP starts the message transfer however To change the configuration of a message object durin
208. UGML Upper Global Mask Long XReg EF08 On Chip CAN Interface Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 13 ID28 21 nw nw LGML Lower Global Mask Long XReg EFOA Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 b 4 3 2 1 0 IDA 0 0 0 0 ID12 5 rw r r r rw Bit Function ID28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier User s Manual 19 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Tees Mask of Last Message XReg EFO0C Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID17 13 ID28 21 rw rw rw LMLM Lower Mask of Last Message XReg EFOE Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDA 0 0 00 ID12 5 rw r r r rw Bit Function ID28 0 Identifier 29 bit Mask to filter the last incoming message Nr 15 with standard or extended identifier as configured User s Manual 19 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 3 The Message Object The message object is the primary means of communication between the CPU and the CAN co
209. UT62 01 10 00 11 0 passive passive passive passive 2 1 0 5 1 ACTIVE passive passive ACTIVE 4 2 0 5 2 ACTIVE ACTIVE passive passive 1 3 0 5 3 passive ACTIVE ACTIVE passive 2 4 0 5 4 passive passive ACTIVE ACTIVE 3 1 0 5 5 passive ACTIVE passive ACTIVE 2 1 0 5 Table 17 4 Five Phase PWM Sequence Table State Output Level Definition for actual state Follower State for BCM CC60 COUT61 CC62 COUT60 CC61 COUT62 01 10 00 passive passive passive passive passive ACTIVE passive passive passive ACTIVE ACTIVE ACTIVE passive passive passive passive ACTIVE ACTIVE passive passive passive passive ACTIVE ACTIVE passive passive passive passive ACTIVE ACTIVE o c1 5jo NN 2 o passive ACTIVE passive ACTIVE ACTIVE MP HR oO m eJ a PY RR oO M OOo oo o O o o 0 0 oO Oo Oo Oo Table 17 5 Six Phase PWM Sequence Table State Output Level Definition for actual state Follower State for BCM CC60 COUT61 CC62 COUT60 CC61 COUT62 01 10 00 11 passive passive passive passive passive passive ACTIVE ACTIVE passive passive passiv
210. User s Manual V1 0 Feb 2002 C164CM SM 16 Bit Single Chip Microcontroller Microcontrollers Never stop thinking Edition 2002 02 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 M nchen Germany Infineon Technologies AG 2002 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support dev
211. WM Mode CMSEL2 CMSEL1 CMSELO Block commutation mode 011g 011g 011g 4 phase multi channel PWM 011g 010g 001g 5 phase multi channel PWM 011g 010g 011g 6 phase multi channel PWM 011g 011g 011g Note Bit CMSELx3 burst mode bit defines whether or not the signal at the COUT6x pins is modulated by compare timer T13 CMSELxS 1 T13 modulation may be combined with T12 modulation Phase Sequence Tables The following tables list the phase sequences for the various multi phase modes The sequence is defined via the follower state for each state and also the output levels for each state are listed The states of a phase sequence are switched in one of two ways e Automatic switching on a T12 overflow e Software controlled by setting bit NMCS in register CC6MSEL Bit ESMC 1 enables software controlled state switching and disables automatic switching on T12 overflows Note The actual logic levels for active and passive state are defined in register CC6MCON In four phase five phase and six phase multi channel PWM mode all output signals can be modulated by timer T12 or timer T13 during their active phases User s Manual 17 14 V1 0 2002 02 e e Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM6 Table 17 3 Four Phase PWM Sequence Table g Output Level Definition for actual state Follower State for BCM a CC60 COUT61 CC62 COUT60 CC61 CO
212. WR ADC Wait for Read Control ADCIN ADC Channel Injection Enable ADCRQ ADC Channel Injection Request Flag User s Manual 18 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter Bit Function ADSTC ADC Sample Time Control Defines the ADC sample time in a certain range 00 1pgcx8 01 fpc X 16 10 tae x 32 11 tae x 64 ADCTC ADC Conversion Time Control Defines the ADC basic conversion clock fgc 00 fgc fcpu 4 01 fac fepu 2 10 fac fcpu 16 11 fac fcpu 8 Bitfield ADCH specifies the analog input channel to be converted first channel of a conversion sequence in auto scan modes Bitfield ADM selects the operating mode of the A D converter A conversion or a sequence is then started by setting bit ADST Clearing ADST stops the A D converter after a specified operation as determined by the selected operating mode The busy flag read only ADBSY is set as long as a conversion is in progress The result of a conversion is stored in the result register ADDAT or in register ADDAT2 for an injected conversion Note Bitfield CHNR of register ADDAT is loaded by the ADC to indicate the channel to which the result refers Bitfield CHNR of register ADDAT2 is loaded by the CPU to select the analog channel to be injected User s Manual 18 4 V1 0 2002 02 _ Infineon technologies ADDAT ADC Result Register C164CM C164SM Derivatives S
213. WR signal is activated driven low in the standard way but can be deactivated driven high one TCL earlier than defined in the standard timing In this case the data output drivers will also be deactivated one TCL earlier This is especially useful in systems which operate on higher CPU clock frequencies and employ external modules memories peripherals etc which switch on their own data drivers very quickly in response to signals such as a chip select Conflicts between the output drivers of the C164CM and the external peripheral s output drivers can be avoided by selecting early WR for the C164CM Note Ensure that the reduced WR low time still matches the requirements of the external peripheral memory Early WR deactivation is controlled via the EWENXx bits in the BUSCON registers The WR signal will be shortened if bit EWENXx is 1 default after reset is a standard WR signal that is EWENx 0 User s Manual 9 13 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives External Bus Interface xa Bus Cycle ALE YY EEUU ag BUS Po YK ML LU aam 0X BUS P0 XIX WR Read Write Early Write Delay MCTO04005M 1 The data drivers from the previous bus cycle should be disabled when the RD signal becomes active 2 Data drivers are disabled in an early write cycle 3 Data drivers are disabled in a demultiplexed normal wri
214. X Peripherals 1 When bit CAN1DIS is cleared the CAN module is re activated by an internal reset signal and must then be re configured in order to operate properly Note The allocation of peripheral disable bits within register SYSCONSGS is device specific and may be different in derivatives other than the C164CM SYSCONS is write protected after the execution of EINIT unless it is released via the unlock sequence see Table 21 6 When disabling the peripheral clock driver PCD the following details should be taken into account The clock signal for all connected peripherals is stopped Make sure that all peripherals enter a safe state before disabling PCD The output signal CLKOUT will remain HIGH FOUT will keep on toggling Interrupt requests will still be recognized even while PCD is disabled No new output values are gated from the port output latches to the output port pins and no new input values are latched from the input port pins No register access is possible for generic peripherals register access is possible for individually disabled generic peripherals no register access is possible for disabled X Peripherals User s Manual 21 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 6 Programmable Frequency Output Signal The system clock output CLKOUT can be replaced by the programmable frequency output signal four This sig
215. a byte to a word location with either sign or zero byte extension MOVBS MOVBZ Note The data movement instructions can be used with a variety of different addressing modes including indirect addressing and automatic pointer in decrementing System Stack Instructions e Pushing a word onto the system stack PUSH Popping a word from the system stack POP e Saving a word on the system stack and then updating the old word with a new value provided for register bank switching SCXT User s Manual 24 2 V1 0 2002 02 Infineon technologies _ C164CM C164SM Derivatives Jump Instructions Conditional jumping to either an absolutely indirectly or relatively addressed target instruction within the current code segment Unconditional jumping to an absolutely addressed target instruction within any code segment Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post inversion of the tested bit in the case of a jump taken Semaphore support Call Instructions Conditional calling of either an absolutely or indirectly addressed subroutine within the current code segment Unconditional calling of a relatively addressed subroutine within the current code segment Unconditional ca
216. a number of identifiers in Full CAN mode and disregard a number of identifiers in Basic CAN mode All message objects can be updated independent of the others during operation of the module and are equipped with buffers for the maximum message length of 8 Bytes 19 1 Functional Blocks of the CAN Module The CAN module combines several functional blocks see Figure 19 2 that work in parallel and contribute to the controllers performance These units and the functions they provide are described below Each of the message objects has a unique identifier and its own set of control and status bits Each object can be configured with its direction as either transmit or receive except for the last message which is only a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bits giving the CPU full flexibility in detecting when a remote data frame has been sent or received For general purposes two masks for acceptance filtering can be programmed one for identifiers of 11 bits and one for ide
217. accesses will occur when instructions N N 1 and N 2 are executed out of external memory instructions N 1 and N require external operand read accesses instructions N 3 through N write back external operands and the interrupt vector also points to an external location In this case the interrupt response time is the time to perform 9 word bus accesses because instruction 11 cannot be fetched via the external bus until all write fetch and read requests of preceding instructions in the pipeline are terminated e When the above example has the interrupt vector pointing into the internal code memory the interrupt response time is 7 word bus accesses plus 2 states because fetching of instruction 11 from internal code memory can start earlier e When instructions N N 1 and N 2 are executed from external memory and the interrupt vector also points to an external location but all operands for instructions N 3 through N are in internal memory the interrupt response time is the time needed to perform 3 word bus accesses e When the above example has the interrupt vector pointing into the internal code memory the interrupt response time is 1 word bus access plus 4 states User s Manual 5 20 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions After an interrupt service routine has been terminated by executing the RETI instruction and if further interrupts are pending the next interru
218. ache to optimize conditional jumps which are processed repeatedly within a loop Whenever a jump on cache is taken the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one machine cycle This performance is achieved by the following mechanism Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction of a cache jump instruction JMPA JMPR JB JBC JNB JNBS is additionally stored in the cache after having been fetched After each repeatedly following execution of the same cache jump instruction the jump target instruction is not fetched from program memory but rather is taken from the cache and is injected immediately into the decode stage of the pipeline see Figure 4 4 A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction unless an instruction having the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Injection of Cached In
219. al Bus Access Trap Whenever the CPU requests an external instruction fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap User s Manual 5 35 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Clock Generation 6 Clock Generation All activities of the C164CM s controller hardware and its on chip peripherals are controlled via the system clock signal fcpy This reference clock is generated in three stages as shown in Figure 6 1 Oscillator e Frequency Control Clock Drivers Oscillator The on chip Pierce oscillator can run with an external crystal and appropriate oscillator circuitry or it can be driven by an external oscillator or another clock source Frequency Control The input clock signal feeds the controller hardware Directly providing phase coupled operation on input frequency which is not too high Divided by 2 to obtain 50 duty cycle clock signal Via an on chip Phase Locked Loop PLL providing maximum performance on low input frequency Viathe Slow Down Divider SDD to reduce power consumption The resulting internal clock signal is referred to as CPU clock fep Clock Drivers The CPU clock is distributed via separate clock driv
220. ams above Note EHM is a variety of the emulation mode where pin PO 15 POL 7 is inverted during the reset configuration This influences the selected clock generation mode For EHM operation direct drive or prescaler mode must be configured If the on chip oscillator is not supplied with a clock signal the oscillator watchdog must not be User s Manual disabled so the PLL can provide the clock signal instead 3 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization 3 6 2 OTP Module Addressing When the OTP module is read in normal mode via its CPU interface it appears like a standard ROM within the internal ROM area and can also be mapped to the respective lower half of segment 0 or segment 1 For segment 0 mapping it uses locations 00 0000 to 00 7FFFy for segment 1 mapping it uses locations 01 0000 to 01 7FFFy In programming mode however the OTP module is addressed physically via the external interface or the OTP programming interface In this case the OTP module appears as a contiguous block using the physical addresses 00 0000 to 00 7FFF Note When entering a programming mode EHM or CHM the on chip OTP module is disabled independent from the selection via pin EA The programming software in CHM must not enable the OTP module s CPU interface by setting bit ROMEN in register SYSC
221. and Message Objects All registers and message objects of the CAN controller are located in the special CAN address area of 256 Bytes This area is mapped into segment 0 and uses addresses O00 EFOO through 00 EFFFy All registers are organized as 16 bit registers located on word addresses However all registers may be accessed bytewise in order to select special actions without affecting other mechanisms Register Naming reflects the specific name of a register as well as a general module indicator This results in unique register names Example module indicator C1 CAN module 1 and specific register type Control Status Register CSR produces unique register name C1CSR Note The address map shown in Figure 19 3 below lists the registers which are part of the CAN controller There are also C164CM specific registers associated with the CAN module User s Manual 19 5 V1 0 2002 02 technologies C164CM C164SM Derivatives On Chip CAN Interface EF00 EF10 EF20 EF30 EF40 EF50 EF60 EF70 EF80 EF90 EFAO EFBO EFCO EFDO EFEO EFFO General Registers Message Object 1 Message Object 2 Message Object 3 Message Object 4 Message Object 5 Message Object 6 Message Object 7 Message Object 8 Message Object 9 Message Object 10 Message Object 11 Message Object 12 Message Object 13 Message Object 14 Message Object 15 CAN Address Area Control Status EF00 Register CSR I
222. and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow trap will be entered when the SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of the underflow register whenever the SP is INCREMENTED either by a RET POP or ADD instruction An underflow trap will be entered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow underflow registers is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy approach which does not require special programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error User s Manual 22 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack O
223. and memory configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE Control defines the ALE signal length and the address hold time after its falling edge e Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time e Memory Tri State Time extendable with 1 waitstate defines the time for a data driver to float Read Write Delay Time defines when a command is activated after the falling edge of ALE Note Internal accesses are executed with maximum speed and therefore are not programmable External accesses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software ALE N ALECTL MCTC MTTC MCD02225 Figure 9 5 Programmable External Bus Cycle User s Manual 9 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1 external bus cycles accessing the respective address window will have their ALE signals prolonged by half a CPU clock 1 TCL Also the address hold time after the falling edge of ALE on a multiplexed bus will be prol
224. anual 16 10 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 CCM7 CAPCOM Mode Ctrl Reg 7 SFR FF28 94 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ACC ACC ACC CCMOD31 CCMOD30 g CCMOD29 CCMOD28 rw rw rw rw rw rw rw rw Bit Function CCMODx Mode Selection for Capture Compare Register CCx The available capture compare modes are listed in Table 16 5 ACCx Allocation Bit for Capture Compare Register CCx 0 CCx allocated to Timer T7 1 CCx allocated to Timer T8 Table 16 5 Selection of Capture Modes and Compare Modes CCMODx Selected Operating Mode 000 Disable Capture and Compare Modes The respective CAPCOM2 register may be used for general variable storage 001 Capture on Positive Transition Rising Edge at Pin CCxlO 010 Capture on Negative Transition Falling Edge at Pin CCxlO 0 1 1 Capture on Positive and Negative Transition Both Edges at Pin CCxlO 100 Compare Mode 0 Interrupt Only Several interrupts per timer period Enables double register compare mode for registers CC24 CC27 101 Compare Mode 1 Toggle Output Pin on each Match Several compare events per timer period This mode is required for double register compare mode for registers CC16 CC19 110 Compare Mode 2 Interrupt Only Only one interrupt per timer perio
225. anual 16 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Timer Mode The bits TxM in SFR T78CON select between timer mode or counter mode for the respective timer In timer mode TxM 0 the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler The different options for the prescaler are selected separately for each timer by the bit fields Txl The input frequencies fr for Tx are determined as a function of the CPU clock as follows where Txl represents the contents of the bit field Txl fopu o Txl 3 Stx When a timer overflows from FFFF to 0000 it is reloaded with the value stored in its respective reload register TXREL The reload value determines the period Pr between two consecutive overflows of Tx as follows 216 lt TxRELs x 2 lt TxI gt 3 fopu Prx After a timer has been started by setting its run flag TxR to 1 the first increment will occur within the time interval defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers of the CAPCOM2 unit are to be incremented or reloaded at the same time T7 is always serviced one CPU clock before T8 The timer input frequencies resolution and periods which result from the selected prescaler option in Txl when using a certain CPU clock are listed in
226. are units CAPCOM2 and CAPCOM6 A 10 bit Analog Digital Converter e A Real Time Clock e Five I O ports with a total of 50 I O lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between the CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt requests are generated by the peripherals based on specific events which occur during their operation such as operation complete error etc To interface with external hardware specific pins of the parallel ports are used when an input or output function has been selected for a peripheral During this time the port pins are controlled either by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose I O pin User s Manual 2 12 V1 0 2002 02
227. as four fcpu FORV 1 x 2 FOSS SO foUTmin fopy 128 FORV SFu FOSS 0 and JOUTmax fcPU 1 FORV 004 FOSS 1 Dy Table 21 5 Selectable Output Frequency Range for foyt fcPu four in kHz for FORV xx FOSS 1 0 FORV for four 1 MHz 0014 01 H 024 3Ey 3Fy FOSS 0 FOSS 1 4 MHz 4000 2000 1333 33 63 492 162 5 O14 03H 2000 1000 666 67 31 746 31 25 10 MHz 10000 5000 3333 33 158 73 156 25 044 09 5000 2500 1666 67 79 365 178 125 12MHz 12000 6000 4000 190 476 187 5 054 OBH 6000 3000 2000 95 238 93 75 16 MHz 16000 8000 5333 33 253 968 250 074 OF 8000 4000 2666 67 126 984 125 20 MHz 20000 10000 6666 67 317 46 312 5 09 134 10000 5000 3333 33 158 73 156 25 25 MHz 25000 12500 8333 33 396 825 390 625 OB 184 12500 6250 4166 67 198 413 195 313 1 04167 0C 0 96154 33 MHz 33000 16500 11000 523 810 515 625 OF 20 16500 8250 5500 261 905 257 816 1 03125 10 0 97059 User s Manual 21 21 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 7 Security Mechanism The power management control registers belong to a set of registers see Table 21 7 which control functions and modes critical to the C164CM s operation For this reason they are locked except for bitfield SYSRLS in register SYSCON2 after the execution of EINIT like register SYSCON to ensure that these vital system functions cannot be c
228. asynchronous operation 0 Ignore parity 1 Check parity SOFEN Framing Check Enable Bit asynchronous operation 0 Ignore framing errors 1 Check framing errors SOOEN Overrun Check Enable Bit 0 Ignore overrun errors 1 Check overrun errors User s Manual 11 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface Bit Function SOPE Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software SOFE Framing Error Flag Set by hardware on a framing error SOFEN 1 Must be reset by software SOOE Overrun Error Flag Set by hardware on an overrun error SOOEN 1 Must be reset by software SOODD Parity Selection Bit 0 Even parity parity bit set on odd number of 1 s in data iF Odd parity parity bit set on even number of 1 s in data SOBRS Baudrate Selection Bit 0 Divide clock by reload value constant depending on mode Ti Additionally reduce serial clock to 2 3 SOLB Loopback Mode Enable Bit 0 Standard transmit receive mode ub Loopback mode enabled SOR Baudrate Generator Run Bit 0 Baudrate generator disabled ASCO inactive T Baudrate generator enabled A transmission is started by writing to the Transmit Buffer register SOTBUF via an instruction or a PEC data transfer The number of data bits to be actually transmitted is determined by the operating mo
229. at for byte ports only two bitfields are provided see Table 7 1 POCON Port Output Ctrl Reg ESFR Table 7 1 Reset Value Table 7 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDM3N PDM2N PDM1N PDMON rw rw rw rw Bit Function PDMxN Port Driver Mode Nibble x Code Driver strength Edge shape 0000 Strong driver Sharp edge mode 0001 Strong driver Medium edge mode 0010 Strong driver Soft edge mode 0011 Weak driver no edge control 0100 Medium driver Sharp edge mode 0101 Medium driver Medium edge mode 0110 Medium driver Soft edge mode 0111 Weak driver no edge control 1xxx Reserved do not use Defines the current the respective driver can deliver to the external circuitry 2 Defines the switching characteristics to the respective new output level This also influences the peak currents through the driver when producing an edge i e when changing the output level 3 This is the driver s minimum strength No additional edge shaping can be selected at this level Table 7 1 lists the defined POCON registers and the allocation of control bitfields and port pins User s Manual 7 5 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Parallel Ports Table 7 1 Port Output Control Register Allocation Control Location Controlled Pins by POCONx y z Reset Register 1512
230. ata Multiplexed Addresses PORTO and PORT1 are automatically switched to the selected bus mode In multiplexed bus modes PORTO drives both the 16 bit intra segment address and the output data while PORT1 remains in high impedance state as long as no demultiplexed bus is selected via one of the BUSCON registers In demultiplexed bus modes PORT1 drives the 16 bit intra segment address while PORTO or POL according to the selected data bus width drives the output data Default 16 bit data bus with multiplexed addresses Note If an internal start is selected via pin EA these two pins are disregarded and bit field BTYP of register BUSCONO is cleared For most non single chip applications 8 bit multiplexed bus mode will be the best tradeoff between on chip peripheral functionality and external bus operation User s Manual 20 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Clock Generation Control Pins POH 7 POH 6 and POH 5 CLKCFG select the basic clock generation mode during reset The oscillator clock either directly feeds the CPU and peripherals direct drive is divided by 2 or is fed to the on chip PLL which then provides the CPU clock signal selectable multiple of the oscillator frequency i e the input frequency These bits are latched in register RPOH Table 20 4 C164CM Clock Generation Modes POH 7 5 CPU Frequency External Clock No
231. atchdog Timer WDT 13 2 Reset Source Indication Reset indication flags in register WDTCON provide information about the source of the last reset As the C164CM starts execution from location 00 0000 after any possible reset event the initialization software may check these flags to determine if the recent reset event was triggered by an external hardware signal via RSTIN by software or by an overflow of the watchdog timer The initialization and further operation of the microcontroller system can thus be adapted to the respective circumstances For instance a special routine may verify software integrity after a watchdog timer reset The reset indication flags are not mutually exclusive more than one flag may be set after reset depending on its source Table 13 2 summarizes the possible combinations Table 13 2 Reset Indication Flag Combinations Event Reset Indication Flags LHWR SHWR SWR WDTR Long Hardware Reset 1 1 1 0 Short Hardware Reset 1 1 0 Software Reset 1 Watchdog Timer Reset 1 1 EINIT instruction 0 0 0 SRVWDT instruction 0 1 Description of table entries 1 flag is set 0 flag is cleared flag is not affected x flag is set in bidirectional reset mode not affected otherwise Long Hardware Reset is indicated when the RSTIN input is still sampled low active at the end of a hardware triggered internal reset se
232. ate leading to state 1 Transient SDD 01 Intermediate state leading to state 2 5 Off SDD 10 SDD operation with PLL Off Reduced power consumption 1 The indicated PLL status applies only if the PLL is selected as the basic clock source If the basic clock source is direct drive or prescaler the PLL will not lock If the oscillator watchdog is disabled OWDDIS 1 the PLL will be off User s Manual 21 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 5 Flexible Peripheral Management The power consumed by the C164CM also depends on the amount of active logic Peripheral management enables the system designer to deactivate those on chip peripherals not required in a given system status such as a certain interface mode or standby All modules remaining active will continue with their usual performance If all modules fed by the Peripheral Clock Driver PCD are disabled and the other functions fed by the PCD are not required this clock driver itself may also be disabled to save additional power This flexibility is accomplished by distributing the CPU clock via several clock drivers each of which can be separately controlled and can also be smaller Idle Mode Clock Generation CPU PCDDIS Peripherals Ports Intr Ctrl Interface Peripherals FOUT MCA04479 Figure 21 5 CPU Clock Distribution Note The Real Time C
233. ation see Table 21 2 Note During Slow Down operation the entire device including bus interface and generation of signals CLKOUT or FOUT is clocked with the SDD clock see Figure 21 3 User s Manual 21 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management Table 21 2 PLL Operation in Slow Down Mode Advantage Disadvantage Oscillator Watchdog PLL Fast switching back to PLL adds to power Active if not running basic clock source consumption disabled via bit OWDDIS PLL PLL causes no PLL must lock before Disabled off additional power switching back to the consumption basic clock source if the PLL is the basic clock Source These clock options are selected via bitfield CLKCON in register SYSCON2 A state machine controls the switching mechanism itself and ensures a continuous and glitch free clock signal to the on chip logic This is especially important when switching back to PLL frequency after the PLL has temporarily been switched off In this case the clock source can be switched back either automatically as soon as the PLL is locked again indicated by bit CLKLOCK in register SYSCON2 or manually under software control after bit CLKLOCK has become 1 The latter way is preferable if the application requires a defined point at which the frequency changes Note When the PLL is the basic clock source and a reset occurs during SDD operation with the P
234. ation of application specific peripherals to boost system performance while minimizing the part count These efforts are supported by the XBUS defined for the Infineon 16 bit microcontrollers second generation The XBUS is an internal representation of the external bus interface which opens and simplifies the integration of peripherals by standardizing the required interface One representative taking advantage of this technology is the integrated CAN module The C165 type devices are reduced functionality versions of the C167 because they do not have the A D converter the CAPCOM units and the PWM module This results in a smaller package reduced power consumption and design savings User s Manual 1 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Introduction The C164 type devices the C167CS derivatives and some of the C161 type devices are further enhanced by a flexible power management and form the third generation of the 16 bit controller family This power management mechanism provides an effective means to control the power that is consumed in a certain state of the controller and thus minimizes the overall power consumption for a given application A variety of different versions is provided which offer various kinds of on chip program memory e Mask programmable ROM e Flash memory e OTP memory e ROMless without non volatile memory Also there are devices with specific functional units
235. atives On Chip CAN Interface 19 5 Configuration Examples for Message Objects The two examples below represent standard applications for using CAN messages Both examples assume that the identifier and direction have already been set up correctly The respective contents of the Message Control Register MCR are shown Configuration Example of a Transmission Object This object shall be configured for transmission It shall be transmitted automatically in response to remote frames but no receive interrupts shall be generated for this object MCR Data bytes are not written completely CPUUPD 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 10 0 1 10 0 1 0 1 0 1 RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND MCR Remote frame was received in the meantime RMTPND 1 TXRQ 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10 10 10 0 1 10 0 1 0 1 0 1 RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND After updating the message the CPU should clear CPUUPD and set NEWDAT The previously received remote request will then be answered If the CPU wants to transmit the message actively it should also set TXRQ otherwise TXRQ should be left unchanged User s Manual 19 34 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Configuration Exa
236. aused by a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON will be set to 1 This indicates the cause of the internal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset by servicing the watchdog timer or after EINIT After the internal reset is complete the operation of the watchdog timer can be disabled by the DISWDT Disable Watchdog Timer instruction This instruction has been implemented as a protected instruction For further security its execution is enabled only in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect Reset Values for the C164CM Registers During the reset sequence the registers of the C164CM are preset with a default value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule provide a first pre initialization which is either fixed or controlled by input pins DPP1 0001 points to data page 1 DPP2 00024 points to data page 2 DPP3 00034 points to data page 3 CP FCO00 STKUN FCOO STKOV FAOO SP FCOO WDTCON 00XX value depends on the reset source SORBUF XX undefined SSCRB XXXX undefined SYSCON 0OXXOj set accord
237. ave also been optimized For example branch instructions require an additional machine cycle only when a branch is taken Subsequent branches taken in loops require no additional machine cycles at all due to the Jump Cache feature A 32 bit 16 bit division requires 20 CPU clock cycles a 16 bit x 16 bit multiplication requires 10 CPU clock cycles The instruction cycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline provides the optimum balancing for the CPU core FETCH In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value DECODE In this stage the previously fetched instruction is decoded and the required operands are fetched EXECUTE In this stage the specified operation is performed on the previously fetched operands WRITE BACK In this stage the result is written to the specified location If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed Instruction Decoder Instruction decoding is generated primarily from Programmable Logic Array PLA outputs based on the selected opcode No microcode is used and each pipeline stage receives control signals staged in
238. ays the complete multiplexed bus cycle and extends the corresponding ALE signal see Figure 9 4 This extra time is required to allow the previously selected device via demultiplexed bus to release the data bus which would be available in a demultiplexed bus cycle Demultiplexed Bus Cycle ALE aseo KC baa Quy XC Multiplexed Bus Cycle Idle State MCD02234M Figure 9 4 Switching from Demultiplexed to Multiplexed Bus Mode Switching between external resources such as different peripherals may incur a problem if the previously accessed resource needs some time to switch off its output drivers after a read and the resource to be accessed next switches its output drivers on very quickly In systems running at higher frequencies this may lead to a bus conflict the switch off delays are normally independent from the clock frequency In such a case an additional waitstate can automatically be inserted when leaving a certain address window i e when the next cycle accesses a different window This waitstate is controlled in the same way as the waitstate when switching from demultiplexed to multiplexed bus mode see Figure 9 4 BUSCON switch waitstates are enabled via bits BSWCx in the BUSCON registers By enabling the automatic BUSCON switch waitstate BSWCx 1 there is no impact on the system performance as long as the external bu
239. be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 located in the non bitaddressable SFR space When any of the timer registers is written to by the CPU in the state immediately preceding a timer increment decrement reload or capture operation the CPU write operation has priority in order to guarantee correct results T2EUD i U D ger Interrupt Jopu f T2 GPT1 Timer T2 gt Request Mode T2IR T2IN E Control Interrupt gt Request foru T3IR Toggle FF NI T3 T3IN e Mode GPT1 Timer T3 S Control i T3EUD p Other Timers TAN TA Mode Interrupt cpu Control gt Request T4IR T4EUD s MCTO04825 4 n 3 10 Figure 10 2 GPT1 Block Diagram User s Manual 10 2 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit 10 1 1 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bitaddressable control register T3CON T3CON Timer 3 Control Register SFR FF42 A1 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T3 T3 T3 m m i OTL UDE UD T3R T3M T3l rwh rw mw rw rw rw Bit Function T3I Timer 3 Input Selection Depends on the operating mode see respective sections T3M Timer 3 Mode Control Basic Operating Mode 000 Timer Mode 001 Cou
240. bit data information While PORTO is not used by the bus controller it is controlled by its direction and output latch registers User software must therefore be very careful when writing to PORTO registers while the external bus is enabled In most cases keeping the reset values will be the best choice The upper 5 pins of PORTO additionally provide the interface lines for the serial interfaces SSC SCLK MTSR MRST and ASCO RxDO TxDO The output lines are ANDed with the respective port output latches as it is in Port 3 of other controllers In 8 bit multiplexed address mode PORTO only drives 11 address lines A10 ADO This reduces the external address space to 2 KBytes but frees the interface pins for the serial interfaces ASCO and SSC In this case the AItEN lines for the upper 5 pins are not activated i e the EBC does not control these pins Table 7 3 Alternate Functions of PORTO PORTO Pin s Alternate Function 8 Bit MUX Altern Function Others POH 7 SCLK SSC Shift Clock Input Output AD15 POH 6 MTSR SSC Master Transmit Slave Receive AD14 POH 5 MRST SSC Master Receive Slave Transmit AD13 POH 4 RxDO ASCO Receive Data Input AD12 POH 3 TxDO ASCO Transmit Data Output AD11 POH 2 0 A10 8 Upper three Address Lines AD10 8 POL 7 0 AD7 0 A Address Data Lines AD7 0 User s Manual 7 13 V1 0 2002 02 technologies C164CM C164SM Derivatives Parallel Ports Alternate Function
241. bits of a specific byte at one time The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the jump is to be taken Note Bit operations on undefined bit locations will always read a bit value of 0 while the write access will not affect the respective bit location All instructions that manipulate single bits or bit groups internally use a read modify write sequence that accesses the whole word containing the specified bit s This method has several consequences e Bits can be modified only within the internal address areas internal RAM and SFRs External locations cannot be used with bit instructions The upper 256 bytes of the SFR area the ESFR area and the internal RAM are bit addressable see Chapter 3 so the register bits located within those respective sections can be manipulated directly using bit instructions The other SFRs must be accessed byte word wise Note All GPHs are bit addressable independently from the allocation of the register bank via the Context Pointer CP Even GPHs which are allocated to non bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware affected bits In these cases the hardware may change specific bits while the read modify write operation is in progress thus t
242. cally upon entry into the error interrupt service routine but must be cleared by software KON Intr Ctrl Reg SFR FF6C B6 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nd ILVL GLVL mh rw rw rw SOTBIC ASCO Tx Buf Intr Ctrl Reg SFR FF9C CE Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i TBIR TBIE EXE GLVL mh rw rw rw SORIC ASCO Rx Intr Ctrl Reg SFR FF6E B74 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERE ILVL GLVL z t mh rw rw rw User s Manual 11 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface SOEIC ASCO Error Intr Ctrl Reg SFR FF70 B8 Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S0 SO mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Using the ASCO Interrupts For normal operation other than the error interrupt the ASCO provides three interrupt requests to control data exchange via this serial channel e SOTBIR is activated when data is moved from SOTBUF to the transmit shift register e SOTIR is activat
243. capable of correctly using a new SP register value which has been updated by an immediately preceding instruction Thus in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicitly SP writing and any subsequent use of the just mentioned implicitly SP using instructions as shown in the following example I MOV SP 0FA40H select a new top of stack D us must not be an instruction popping operands from the system stack Ina POP RO pop word value from new top of stack into RO Note Conflicts with instructions writing to the stack PUSH CALL SCXT are solved internally by the CPU logic Controlling Interrupts Software modifications implicit or explicit of the PSW are made in the execute phase of the respective instructions To maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes that means that an interrupt request may be acknowledged after the instruction which disables interrupts via IEN or ILVL or after the following instructions Time critical instruction sequences therefore should not begin directly after the instruction disabling interrupts as shown in the following examples INTERRUPTS OFF 3 BCLR IEN globally disable interrupts Instr non crit non critical instruction Instr lst crit gt begin of IE uninterruptable critical sequence Instr last crit en
244. cards the other However care must be taken when reading devices that change state when being read such as FIFOs interrupt status registers etc Writing bytes to an external 16 bit device should be avoided AO indicates the selected byte high or low but often is not used in 16 bit systems There is also no way to distinguish low byte writes from word writes due to the missing BHE The C164CM will write the respective byte value to both halves of the 16 bit data bus Table 9 2 Bus Mode versus Performance Bus Mode Transfer Rate System Requirements Free IO Speed factor for byte Lines word dword access 8 bit Multiplexed Very low 1 5 3 6 Low 8 bit latch byte bus P1H P1L POH 7 3 8 bit Demultipl Low 1 2 4 Very low no latch byte bus POH 16 bit Multiplexed High 1 5 1 5 3 High 16 bit latch word bus P1H P1L 16 bit Demultipl Very high 1 1 2 Low no latch word bus Note PORT1 becomes available for general purpose IO when none of the BUSCON registers selects a demultiplexed bus mode 1 Byte accesses are supported for on chip resources except for the SFRs User s Manual 9 8 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 3 Programmable Bus Characteristics Important timing characteristics of the external bus interface are user programmable to allow adaptation to a wide range of different external bus
245. ce ATOMIC e Switch reg bitoff and bitaddr addressing modes to the Extended SFR space EXTR e Override the DPP addressing scheme using a specific data page instead of the DPPs and optionally switch to ESFR space EXTP EXTPR e Override the DPP addressing scheme using a specific segment instead of the DPPs and optionally switch to ESFR space EXTS EXTSR Note The ATOMIC and EXT instructions provide support for uninterruptable code sequences e g for semaphore operations They also support data addressing beyond the limits of the current DPPs except ATOMIC This is advantageous for larger memory models in high level languages Refer to Chapter 22 for examples Protected Instructions Some instructions of the C164CM critical for the functionality of the controller are implemented as so called Protected Instructions These protected instructions use the maximum instruction format of 32 bits for decoding Regular instructions use only a portion of it such as the lower 8 bits with the other bits providing additional information such as indicating the involved registers Decoding all 32 bits of a protected doubleword instruction increases security in cases of data distortion during instruction fetching Critical operations such as a software reset are therefore executed only if the complete instruction is decoded without an error This enhances the safety and reliability of a microcontroller system User s Manual 24 4 V1 0 200
246. channel outputs to be combined with the compare channel output or with external signals Thus flexible and complex output patterns can be generated automatically with very little or no CPU action Mode l di 12 Select Register Trap Register CTRAP CC6MSEL l l l l l l l Offset Register CC Channel 0 CC60 5 T120F B CC60 MNA COUT60 Jou j S n CC Channel 1 CC61 ho ompare o CC61 T61 i E Timer T12 o CHUTE 16 Bit CC Channel 2 CC62 CC62 COUT62 l l Control Register l CTCON Le eng Sa ee eee ee ae Pepe S68 mE E B ompare foru o Timer T13 Compare Register I COUT63 D 10 Bit OMFS o CC6POS1 Period Register Control bird aide T13P CC6MCON H CC6POS2 l CCEPOSO I Commutation l l l MCB04109 1 These registers are not directly accessable The period and offset registers are loading a value into the timer registers Figure 17 2 CAPCOM6 Block Diagram Two basic operating modes are supported Edge Aligned Mode Center Aligned Mode In Edge Aligned Mode the compare timer counts up starting at 00004 Upon reaching the period value stored in register TxP the timer is cleared and repeats counting up At this time the output signals are also switched to their passive state Edge aligned mode is supported by both compare timers T12 and T13 User s Manual 17 2 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6
247. character is complete The SSC supports full duplex synchronous communication at up to 6 25 Mbit s 25 MHz CPU clock It may be configured so that it interfaces with serially linked peripheral components A dedicated baud rate generator allows set up of all standard baud rates without oscillator tuning Three separate interrupt vectors are provided for transmission reception and error handling The SSC transmits or receives characters of 2 16 bits length synchronously to a shift clock which can be generated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the Most Significant Bit MSB and allows selection of shifting and latching clock edges as well as the clock polarity A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers Transmit and receive error supervise the correct handling of the data buffer Phase and baudrate error detect incorrect serial data User s Manual 2 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview On Chip CAN Module The integrated CAN Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active i e the on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers The m
248. chnologies Device Specification P8 2 CC1810 CAN_RxD P8 1 CC171O CAN TxD P5 2 AN2 T3EUD P5 1 AN1 G P8 0 CC16IO CAN RxD P1 15 CC271O P1 14 CC2610 P1 13 CC2510 P1 12 CC241O Vss 1 XTAL1 XTAL2 VAREF Vand m P8 3 CC19IO CAN TxD ER P5 3 AN3 TSIN 11 O 48 1 Vop P5 4 AN4 T2EUD 2 47 1 P1 11 EX3IN T7IN CC3110 P5 5 AN5 T4EUD 13 46 1 P1 10 CC6POS2 EX2IN CC3010 P5 6 ANG T2IN 14 45 1 P1 9 CC6POS1 EX1IN CC29IO P5 7 AN7 T4IN TRSEL C15 44 1 P1 8 CC6POSO EXOIN CC28IO Vss L 6 43 E1 P1 7 CTRAP Voo C 7 42 1 P1 6 COUT63 P0 15 AD15 SCLK C18 41 O P1 5 COUT62 PO 14 AD14 MTSR C164CM 40 E1 P1 4 CC62 P0 13 AD13 MRST 39 1 P1 3 COUT61 P0 12 AD12 RxDO 38 1 P1 2 CC61 P0 11 AD11 TxDO 37 L1 P1 1 COUT60 P0 10 AD10 36 1 P1 0 CC60 P0 9 AD9 35 1 P20 12 RSTOUT P0 8 AD8 34 1 P20 8 CLKOUT FOUT Vop 16 Vss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Qr oundxowa omgzipus6s qgagagaaaaaa Lr a 9908005 5EF EES KEDIA ESR oOooooccocoo oc gow p Q 0 a n A O amp A a Ke o amp MCP04955 Figure 25 1 Pin Configuration for C164CM P MQFP 80 Package Note Port 8 pins can have CAN interface lines assigned to them Chapter 19 lists the possible assignments User s Manual 25 2 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives 26 Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the C164CM i
249. chronizes to the external clock signal Due to the fact that the external frequency is 1 F th of the PLL output frequency the output frequency may be slightly higher or lower than the desired frequency This jitter is irrelevant for longer time periods For short periods 1 4 CPU clock cycles it remains below 496 PLL Circuit Jin JoaL F X y gt fcpu Reset Reset PWRDN Sleep Lock XPSINT CLKCFG RPOH 7 5 MCB04339 Figure 6 6 PLL Block Diagram User s Manual 6 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Clock Generation 6 3 Oscillator Watchdog The C164CM provides an Oscillator Watchdog OWD which monitors the clock signal fed to input XTAL1 of the on chip oscillator either with a crystal or via external clock drive in prescaler or direct drive mode unless the PLL provides the basic clock For this operation the PLL provides a clock signal base frequency which is used to supervise transitions on the oscillator clock This PLL clock is independent of the XTAL1 clock When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock OWD interrupt node and supplies the CPU with the PLL clock signal instead of the selected oscillator clock see Figure 6 4 Under these circumstances the PLL will oscillate with its base frequency In direct drive mode the PLL base frequency is used directly fcpy 2 5 MHz In prescale
250. cient control optimized instruction set additional instructions for members of the second generation This allows easy and quick implementation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of IO pins The XBUS concept internal representation of the external bus interface provides a straightforward path for building application specific derivatives by integrating application specific peripheral modules with the standard on chip peripherals As programs for embedded control applications become larger high level languages are favored by programmers because high level language programs are easier to write to debug and to maintain The C166 Family supports this starting with its gnd generation The 80C166 type microcontrollers were the first generation of the 16 bit controller family These devices established the C166 architecture The C165 type and C167 type devices are members of the second generation of this family This second generation is even more powerful due to additional instructions for HLL support an increased address space increased internal RAM and highly efficient management of various resources on the external bus Enhanced derivatives of this second generation provide more features such as additional internal high speed RAM an integrated CAN Module an on chip PLL etc The design of more efficient systems may require the integr
251. cillator disabled the internal RAM is preserved down to a voltage of 2 5 V Note When the RTC remains active in Power Down mode the oscillator which generates the RTC clock signal will continue running If the supply voltage is reduced the specified maximum CPU clock frequency for this case must be taken into account The total power consumption in Power Down mode depends on the active circuitry whether the RTC is on or off and on the current flowing through the port drivers To minimize the consumed current the RTC and or all pin drivers can be disabled pins switched to tristate via a central control bitfield in register SYSCON2 If an application requires one or more port drivers to remain active even in Power Down mode individual port drivers can be disabled simply by configuring them for input The bus interface pins can be separately disabled by releasing the external bus disable all address windows by clearing the BUSACT bits and switching the ports to input if necessary Of course the required software in this case must be executed from internal memory User s Manual 21 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 3 1 Output Pins Status During Power Reduction Modes In Idle mode the CPU clocks are turned off and all peripherals continue their normal operation Therefore all port pins configured as general purpose output pins will output the last data value wri
252. ck and loads CP with the immediate value New Bank this in turn selects a new register bank The service routine may now use its own registers This register bank is preserved when the service routine terminates i e its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT instruction must not use a GPR Resources used by the interrupting program must eventually be saved and restored e g the DPPs and the registers of the MUL DIV unit User s Manual 5 18 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 5 Interrupt Response Times The interrupt response time defines the time from the setting of an interrupt request flag of an enabled interrupt source to fetching of the first instruction I1 from the interrupt vector location The basic interrupt response time for the C164CM is 3 instruction cycles Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 l1 DECODE N 1 N TRAP 1 TRAP 2 EXECUTE N 2 N 1 N TRAP WRITEBACK N 3 N 2 N 1 N Interrupt Response Time IR Flag MCT04332 Figure 5 4 Pipeline Diagram for Interrupt Response Time All instructions in the pipeline including instruction N during which the interrupt request flag is set
253. commended to change the channel number only when no injected conversion is running Ex x 1 x 2 X 3 X 4 i Conversion of Channel Write ADDAT x 1 X x x 2 x 3 x 4 ADDAT Full i A EE 8G Read ADDAT x 1 x x 1 x 2 x 3 X 4 i y Injected Channel Injection Conversion Request of Channel y Write ADDAT2 ADDAT2 Full Int Request ADEINT Read ADDAT2 MCA01971 Figure 18 5 Channel Injection Example User s Manual 18 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter A channel injection can be triggered in two ways e Set the Channel Injection Request bit ADCRQ via software nitiate a compare or a capture event of Capture Compare register CC27 of the CAPCOM unit this also sets bit ADCRQ The second method triggers a channel injection at a specific time either on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC27 This can be either the positive the negative or both the positive and the negative edges of an external signal Additionally this option allows the time at which this signal occurs to be recorded Note The channel injection request bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC27 regardless of whether or not the channel injection mode is enabled It is recommended to always clear bit ADCRQ before enabling the channel
254. consists of a chain of three divider blocks a fixed 8 1 divider the reloadable 16 bit timer T14 and the 32 bit RTC timer accessible via registers RTCH and RTCL Both timers count upwards User s Manual 2 16 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Architectural Overview General Purpose Timer GPT Unit The GPT1 unit utilizes a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication Each timer may operate independently in a number of different modes or may be concatenated with another timer of the same module Each timer can be configured individually for one of four basic modes of operation Timer Gated Timer Counter Mode and Incremental Interface Mode In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events via TxIN Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TxIN In Incremental Interface Mode the GPT1 timers can be directly connected to the incremental position sensor signals A and B via the respective inputs TxIN and TxEUD Direction and count signals are i
255. continuous data such as huge arrays in C EXTS 15 1 The override seg is 15 0F 0000H 0F FFFFH MOV RO R14 The 16 bit segment offset is stored in R14 MOV R1 R13 This instruction uses the std DPP scheme Note Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC As long as any Class B trap is pending any of the class B trap flags in register TFR is set the EXTend instructions will not work Clear the respective B trap flag at the beginning of a B trap routine if EXT shall be used within the routine Short Addressing in Extended SFR ESFR Space The short addressing modes of the C164CM REG or BITOFF implicitly access the SFR space The additional ESFR space would need to be accessed via long addressing modes MEM or Rw The EXTR extend register instruction redirects accesses in short addressing modes to the ESFR space for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space using a single instruction Note Instructions EXTR EXTPR and EXTSR inhibit interrupts the same way as ATOMIC instructions Switching to the ESFR area and data page overriding are checked by the development tools or are handled automatically Nested Locked Sequences Each described extension instruction and the ATOMIC instruction start an internal extension counter counting the effected inst
256. control bit ODPx y is 0 default after reset the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space A A External B Pullup Push Pull Output Driver Open Drain Output Driver MCS01975 Figure 7 2 Output Drivers in Push Pull Mode and in Open Drain Mode User s Manual 7 3 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Parallel Ports Driver Characteristic This defines the general driving capability of the respective driver Reducing the driver strength increases the output s internal resistance which attenuates noise that is imported exported via the output line For driving LEDs or power transistors however a stable high output current may still be required The controllable output drivers of the C164CM pins feature differently sized transistors for each direction push and pull The activation deactivation of these transistors determines the output characteristics of the respective port driver Three modes can be selected to adapt the driver characteristics to the application s requirements Strong Driver Mode Medium Driver Mode and Weak Driver Mode In Strong Driver Mode all transistors are activated In this case the driver provides maximum output current supporting high current applications such as LEDs or applications where fast signal t
257. control registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals User s Manual 2 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview High Function 8 bit and 16 bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16 bit ALU Additionally for byte operations signals are provided from bits 6 and 7 of the ALU result to set the condition flags correctly Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle Thus these operations use two coupled 16 bit registers MDL and MDH and require four and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the operands and th
258. controller was not acknowledged by another node 4 Bit1Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored bus value was dominant 5 BitOError During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicates that the bus is not stuck at dominant or continuously disturbed 6 CRCError The received CRC check sum was incorrect 7 Unused code may be written by the CPU to check for updates TXOK Transmitted Message Successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK Received Message Successfully This bit is set each time a message has been received successfully since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK is also set when a message is received that is not accepted i e stored EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96
259. d 111 Compare Mode 3 Set Output Pin on each Match Reset output pin on each timer overflow Only one interrupt per timer period The descriptions of the capture and compare modes are valid for all capture compare channels so the registers bits and pins are referenced only by the placeholder x User s Manual 16 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Note Capture compare channels 16 19 and 24 31 are connected to pins capture compare channels 16 19 and 24 27 are connected to and interrupt nodes A capture or compare event on channel 27 may be used to trigger a channel injection on the C164CM s A D converter if enabled 16 4 Capture Mode In response to an external event the contents of the associated timer T7 or T8 depending on the state of the allocation control bit ACCx are latched into the respective capture register CCx The external event causing a capture can be programmed to be a positive a negative or both a positive and a negative transition at the respective external input pin CCXxlO The triggering transition is selected by the mode bits CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the respective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled Edge Select Capture Reg CCx Interrupt
260. d a negative transition of T3OTL are used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer T3OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case Tyl Jeru Core Timer Ty TyOTL TyR Up Down Interrupt p Request Edge TyIR Select Interrupt Auxiliary Timer Tx Request TxIR TxR Tx Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL MCB02034b x 2 4 y 3 nz3 10 Figure 10 11 Concatenation of Core Timer T3 and an Auxiliary Timer User s Manual 10 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 100 In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register tr
261. d by an instruction that does not access the same port see example below PORT_INIT_WRONG BSET DP8 3 change direction of P8 3 to output BSET P8 2 P8 3 is still input rd mod wr reads pin P8 3 PORT_INIT_RIGHT BSET DP8 3 change direction of P8 3 to output NOP any instruction not accessing port 8 BSET P8 2 P8 3 is now output rd mod wr reads P8 3 s output latch Note Special attention must be paid to interrupt service routines that modify the same port as the software they have interrupted Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON e g the mapping of the internal ROM segmentation stack size cannot use the new resources e g ROM or stack In these cases an instruction which does not access these resources should be inserted Code accesses to the new ROM area are possible only after an absolute branch to this area Note As a rule instructions that change ROM mapping should be executed from internal RAM or external memory User s Manual 4 8 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU BUSCON ADDRSEL The instruction following an instruction that changes the properties of an external address area cannot access operands within the new area In these cases an instruction that does not access this address area should be inserted Code accesses to the new
262. d of critical sequence INTERRUPTS ON BSET IEN globally re enable interrupts CRITICAL SEQUENCE ATOMIC 3 immediately block interrupts BCLR IEN globally disable interrupts E os here is the uninterruptable sequence BSET IEN globally re enable interrupts Note The described delay of one instruction also applies for enabling the interrupts system i e no interrupt requests are acknowledged until the instruction following the enabling instruction User s Manual 4 7 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU External Memory Access Sequences The effect described here will become noticeable only when watching the external memory access sequences on the external bus by means of a Logic Analyzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may differ from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses 3st Write Data and Fetch Code grd Read Data Initialization of Port Pins Direction modification of port pins input or output become effective only after the instruction following the modifying instruction As bit instructions BSET BCLR use internal read modify write sequences which access the entire port instructions which modify the port direction should be followe
263. d one of the compare modes described in the following sections has been selected for this register The different compare modes which can be programmed for a given compare register CCx are selected by the mode control field CCMODx in the associated capture compare mode control register Each of the compare modes including the special double register mode is discussed in detail in the following sections Compare Mode 0 This is an interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100p In this mode the interrupt request flag CCxIR is set each time a match is detected between the contents of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare value in register CCx is updated during the timer period The corresponding port pin CCxIO is not affected by compare events in this mode and can be used as general purpose IO pin If compare mode O is programmed for one of the registers CC24 CC27 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 1 see Double Register Compare Mode on Page 16 19 1 Compare events are detected sequentially where a sequence checking 8 times 2 channels each takes 8 CPU clock cycles Ev
264. dard startup mode program execution will always begin out of external memory disregarding the level on pin EA V pp When CHM is enabled in bootstrap loader mode the programming routine s can be loaded via the serial interface This allows in system programming of an empty OTP module External Host Mode EHM is enabled by selecting emulation mode POL O 0 and also pulling low pin POL 5 Pins POL 5 O represent 01 1110g in this case CPU Host Mode Programming CHM is useful for in system programming especially combined with the bootstrap loader mode CHM programming cycles are controlled via the C164CM s programming interface which replaces the external bus interface signals Pin EA Vpp accepts the external programming voltage during programming cycles see diagram The programming interface is realized as an XBUS peripheral and uses the address area 00 EDCO 00 EDDF The interface is activated only in programming mode and cannot be accessed in all other cases The OTP module s interface signals are not externally asserted but rather controlled via three registers Table 3 3 OTP Programming Interface Registers Register Physical Description Reset Name Address Value OPCTRL EDCO Control register provides the control signals and the 00074 upper 8 address lines A23 A16 OPAD EDC2 Address register provides the lower 15 address lines 0000 of the physical OTP word address A15 A1 Note Address lin
265. data and alternate data output before the port latch input Internal Bus CCx 29 Sr Port Output Open Drain Latch Latch AltDir AItEN AltDataOut Driver AltDataln Latch lt Clock AltDatalN Pin lt Input Latch MCB04430 P8 3 0 Figure 7 12 Block Diagram of Port 8 Pins with an Alternate CAPCOM IO and CAN Interface Function User s Manual 7 27 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports 7 7 Port 20 If this 6 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP20 P20 Port 20 Data Register SFR FFBA DA Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 g P20 g _ P20 _ P20 P20 _ P20 P20 12 8 5 4 1 0 rw rw wo rw w rw Bit Function P20 y Port data register P20 bit y DP20 P20 Direction Ctrl Register SFR FFB6 DB Reset Value 10004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 g g _ DP20 a DP20 DPQODP20 _ DP20DP20 12 8 5 4 1 0 rw rw wo rw w rw 1 ROM version only No output driver for this pin in OTP devices Bit Function DP20 y Port direction register DP20 bit y 0 Port line P20 y is an input
266. de selected that is bits written to positions 9 through 15 of register SOTBUF are always insignificant After a transmission has been completed the transmit buffer register is cleared to 0000p Data transmission is double buffered so that a new character may be written to the transmit buffer register before the transmission of the previous character is complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable Bit SOREN After reception of a character has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the read only Receive Buffer register SORBUF Bits in the upper half of SORBUF not valid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bit SOOEN User s Manual 11 3 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR will be set if the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive bu
267. dition to its normal operation state the CPU has the following particular states Reset state Any reset hardware software watchdog forces the CPU into a predefined active state IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip peripherals keep running SLEEP state All of the on chip clocks are switched off RTC clock selectable external interrupt inputs are enabled e POWER DOWN state All of the on chip clocks are switched off RTC clock selectable all inputs are disregarded Transition to an active CPU state is forced by an interrupt if in IDLE or SLEEP mode or by a reset if in POWER DOWN mode The IDLE SLEEP POWER DOWN and RESET states can be entered by specific C164CM system control instructions User s Manual 4 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU A set of Special Function Registers is dedicated to the functions of the CPU core General System Configuration SYSCON RPOH e CPU Status Indication and Control PSW e Code Access Control IP CSP Data Paging Control DPPO DPP1 DPP2 DPP3 e GPRs Access Control CP e System Stack Access Control SP STKUN STKOV e Multiply and Divide Support MDL MDH MDC e ALU Constants Support ZEROS ONES 4 1 Instruction Pipelining The instruction pipeline of the C164CM partitions instruction processing into four stages each of
268. e When the auxiliary timers T2 and T4 are programmed to incremental interface mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly User s Manual 10 13 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 001 In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input pin TxIN or by a transition of timer T3 s output toggle latch T3OTL Edge Select Interrupt Auxiliary Timer Tx Request TxIR Up Dow n mcb02221 vsd Xx 2 4 Figure 10 10 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input pin or at the toggle latch T3OTL Bit field Txl in the respective control register TXCON selects the triggering transition see Table 10 8 User s Manual 10 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Table 10 8 GPT1 Auxiliary Timer Counter Mode Input Edge Selection T2l TAI Triggering Edge for Counter Increment Decrement X00 Non
269. e passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE passive passive passive passive passive ACTIVE ACTIVE ACTIVE passive passive passive passive ACTIVE N O 01 O NM O passive ACTIVE passive ACTIVE passive ACTIVE MO a R oO rms oO Oo oc 25 c nm o oO Oo oOoO o o o o o NENT NI NIN IN IN Note To change the rotation direction idle mode must be entered first User s Manual 17 15 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives 17 6 2 Block Commutation Mode Block commutation mode is a special variation of the multi channel modes in which the phase sequence is not controlled internally but rather by the three input signals CC6POS2 0 The state of the six output signals is derived from the pattern present on the input signals Table 17 6 summarizes the possible combinations Capture Compare Unit CAPCOM6 Table 17 6 Block Commutation Sequence Table Block Control Output Level Definition Commutation Inputs for actual state Mode BCM CC6POS 0 1 2 CC60 CC61 CC62 COUT60 COUT61 COUT62 Rotate Left 1 0 1 passive passive ACTIVE passive ACTIV
270. e oO oO c DiglnputEN Clock AltDataln lt e e Input Pin Latch ChannelSelect Analoglnput 4 MCB04357 P5 7 0 Figure 7 10 Block Diagram of a Port 5 Pin Note The AltDataln line does not exist on all Port 5 inputs User s Manual 7 23 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives 7 6 Port 8 If this 4 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP8 Each port line can be switched into push pull or open drain mode via the open drain control register ODP8 P8 Port 8 Data Register SFR FFD4 EA Parallel Ports Reset Value 00 15 14 13 12 11 10 9 8 7 6 3 2 1 0 P8 3 P8 2 P8 1 P8 0 rwh rwh rwh rwh Bit Function P8 y Port data register P8 bit y DP8 P8 Direction Ctrl Register SFR FFD6 EB Reset Value 00 15 14 13 12 11 10 9 8 7 6 3 2 1 0 a DP8 DP8 DP8 DP8 3 2 1 0 w w w mw Bit Function DP8 y Port direction register DP8 bit y DP8 y 0 Port line P8 y is an input high impedance DP8 y 1 Port line P8 y is an output User s Manual 7 24 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports ODP8 P8 Open Drain Ctrl
271. e 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 j je j 5b 2 1 SEGNR rh Bit Function SEGNR Segment Number Specifies the code segment from which the current instruction is to be fetched SEGNR is ignored when segmentation is disabled Code memory addresses are generated by directly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in Figure 4 5 For non segmented memory mode the content of this register is not significant because all code accesses are automatically restricted to segment O Note The CSP register can only be read but cannot be written by data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is set automatically to zero User s Manual 4 20 V1 0 2002 02 _ e e Infineon technologies C164CM C164SM Derivatives Central Processing Unit CPU Code Segment 15 CSP Register 0 15 IP Register 0 FF FFFF 77 255 254 FE 0000 1 A J 010000 24 20 18 Bit Physical Code Address 0 00 0000 A MCA02265 Figure 4 5 Addressing via the Code Segment Pointer Note When segmentation is disabled the IP value
272. e Counter Tx is disabled 00 1 Positive transition rising edge on TxIN 010 Negative transition falling edge on TxIN 0 1 1 Any transition rising or falling edge on TxIN 101 Positive transition rising edge of output toggle latch T3OTL 110 Negative transition falling edge of output toggle latch T3OTL 111 Any transition rising or falling edge of output toggle latch T3OTL Note Only state transitions of T30TL caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of TSOTL via software will NOT trigger the counter function of T2 T4 For counter operation pin TxIN must be configured as an input the respective direction control bit must be 0 The maximum input frequency allowed in counter mode is fcpu 16 To ensure that a transition of the count input signal which is applied to TxIN is recognized correctly its level should be held for at least 8 fcpy cycles before it changes User s Manual 10 15 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer This concatenation forms either a 32 bit or a 33 bit timer counter depending on which transition of T3OTL is selected to clock the auxiliary timer 32 bit Timer Counter If both a positive an
273. e addressing modes identified below are described in Chapter 24 Short 4 Bit GPR Addresses mnemonic Rw or Rb specify an address relative to the memory location specified by the contents of the CP register i e the base of the current register bank Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not before it is added to the content of register CP see Figure 4 8 Thus both byte and word GPR accesses are possible GPRs used as indirect address pointers are always accessed wordwise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The respective physical address calculation is identical to that for the short 4 bit GPR addresses Short 8 Bit Register Addresses mnemonic reg or bitoff within a range from FO to FF interpret the four least significant bits as short 4 bit GPR address the four most significant bits are ignored The respective physical GPR address calculation is identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word address is calculated as just described but the position of the bit within the word is specified by a separate additional 4 bit value User s Manual 4 26 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Specified by r
274. e by comparing the current time with a timestamp stored when Sleep mode was entered The supply current in this case remains well below 1 mA During Sleep mode the voltage at the Vpp pins can be lowered to 2 7 V while the RTC and its selected oscillator will continue running and the contents of the internal RAM will be preserved With the RTC and oscillator disabled the internal RAM is preserved down to a voltage of 2 5 V Note When the RTC remains active in Sleep mode the oscillator which generates the RTC clock signal will also continue running If the supply voltage is reduced the specified maximum CPU clock frequency for this case must be taken into account For wakeup input edge recognition and CPU start the power level must be within the specified limits The total power consumption in Sleep mode depends on the active circuitry whether the RTC is on or off and on the current flowing through the port drivers Individual port drivers can be disabled simply by configuring them for input The bus interface pins can be separately disabled by releasing the external bus disable all address windows by clearing the BUSACT bits and switching the ports to input if necessary The required software in this case must be executed from internal memory User s Manual 21 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management SYSCON1 System Control Reg 1 ESFR F1DC EE Reset Value 00004
275. e number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables respectively MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc SGT LOOP Test whether target has not been found Note The last entry in the table must be greater than the largest possible target MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc NET LOOP Test whether target is not found AND j the end of table has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000 22 5 Floating Point Support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR This result can then be used to rotate the floating point result accordingly The second feature assists in properly rounding the result of normalized floating point numbers through the overflow V flag in t
276. e result Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response Instructions have been provided as well to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements A set of consistent flags is updated automatically in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 bit barrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing These instructions provide efficient control and testing of peripherals while enhancing data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the bit addressable space without requiring them to be moved into temporary flags The same logical instructions available for words and bytes are also support
277. e see Section 21 7 RSTCON can be accessed only via its long mem address User s Manual 20 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 Power Management An increasingly important objective for microcontroller based systems is the significant reduction of power consumption A contradictory objective is to reach a certain level of system performance Besides optimization of design and technology a microcontroller s power consumption can generally be reduced by lowering its operating frequency and or by reducing the clocked circuitry The architecture of the C164CM provides three major means of reducing its power consumption under software control see Figure 21 1 Reduction of the CPU frequency for Slow Down operation Flexible Clock Generation Management e Selection of the active peripheral modules Flexible Peripheral Management e Special operating modes to deactivate CPU ports and control logic Idle Sleep Power Down This enables the application i e the programmer to choose the optimum constellation for each operating condition so the power consumption can be adapted to conditions like maximum performance partial performance intermittent operation or standby User s Manual 21 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management Power No of act Peripherals MCA04476 Figure 21 1
278. e 13 1 lists the possible ranges depending on the prescaler bits WDTPRE and WDTIN for the watchdog time which can be achieved using a certain CPU clock Table 13 1 Watchdog Time Ranges CPU Clock Prescaler Reload Value in WOTREL fcpu E Bu wor FFy 7Fy 00 2zznu 0 0 fopyu 2 42 67 us 5 50 ms 10 92 ms 0 1 f cpu 4 85 33 us 11 01 ms 21 885 ms 12 MHz 1 0 f cpu 128 2 73 ms 352 3 ms 699 1 ms 1 1 cpu 256 5 46 ms 704 5 ms 1398 ms 0 0 fopyu 2 32 00 us 4 13 ms 8 19 ms 0 1 fcpu 4 64 00 us 8 26 ms 16 38 ms 16 MHz 1 0 fcpu 128 2 05 ms 264 2 ms 524 3 ms 1 1 fopu 256 4 10 ms 528 4 ms 1049 ms 0 0 fopyu 2 25 60 us 3 30 ms 6 55 ms 0 1 4 51 20 S 6 61 ms 13 11 ms 20 MHz Jopu 1 0 f cpu 128 1 64 ms 211 4 ms 419 4 ms 1 1 fopu 256 3 28 ms 422 7 ms 8389 ms 0 0 fopyu 2 20 48 us 2 64 ms 5 24 ms 0 1 4 40 96 s 5 28 ms 10 49 ms 25 MHz lepu E 1 0 f cpu 128 1 31 ms 169 1 ms 335 5 ms 1 1 fopy 256 2 62 ms 338 2 ms 671 1 ms 0 0 fcPu 2 15 52 us 2 00 ms 3 97 ms 0 1 4 31 03 s 4 00 ms 7 94 ms 33 MHz Jopu Hu 1 0 fcpu 128 0 99 ms 128 1 ms 254 2 ms 1 1 fopy 256 1 99 ms 256 2 ms 508 4 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the watchdog timer is serviced User s Manual 13 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives W
279. e 9 23 Bus Mode preferred 9 3 Bus Modes 9 2 9 8 Fast interrupts 5 27 26 2 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives Host Mode EHM 3 15 20 16 Interrupt source control 5 29 Interrupts 5 25 Interrupts during sleep mode 5 30 startup configuration 20 13 F Fast external interrupts 5 27 Flags 4 16 4 19 FOCON 21 18 Frequency output signal 21 17 Full Duplex 12 7 G GMS 19 15 GPR 3 6 4 25 23 2 GPT 2 17 GPT1 10 1 H Half Duplex 12 10 Hardware Reset 20 2 Traps 5 31 l Idle Mode 21 4 State Bus 9 23 Incremental Interface 10 9 Indication of reset source 13 6 Inseparable instructions 22 14 Instruction 22 1 24 1 Bit Manipulation 24 2 Branch 4 4 inseparable 22 14 Pipeline 4 3 protected 24 4 Timing 4 11 Interface CAN 2 15 19 1 External Bus 9 1 serial async gt ASCO 11 1 User s Manual Keyword Index serial sync gt SSC 12 1 Internal RAM gt IRAM 3 4 Interrupt CAPCOM 16 22 16 23 during sleep mode 5 30 Enable Disable 5 15 External 5 25 Fast external 5 27 Handling CAN 19 9 Node Sharing 5 24 Priority 5 7 Processing 5 1 5 5 Response Times 5 19 RTC 14 3 source control 5 29 Sources 5 2 System 2 8 5 2 Vectors 5 2 IP 4 19 IRAM 3 4 status after reset 20 8 ISNC 5 24 L LARn 19 21 LGML 19 16 LMLM 19 17 M Management Peripheral 21 15 Power 21 1 MCFGn 19 22 MCRn 19 19 MDC 4 32 MDH 4 30 MDL 4 31 Memory
280. e AO is not evaluated OPDAT EDC4 _ Data register provides the word to be stored or read 0000 from the module User s Manual 3 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization External Host Mode Programming In this mode the signals to control a programming cycle are generated by an external host using the C164CM s bus interface The external host provides the data to be programmed The C164CM itself is switched off and its OTP module can be accessed like standalone memory In External Host Mode the following port pins represent the interface to the C164CM s OTP module Table3 4 External Host Mode Interface Signals Signal Pin Description ADDR P1H 7 P1L 1 Physical OTP word address address line AO is not evaluated DATA POH 7 POL O Word to be programmed or verified RD P20 0 RD Verify cycle control WR P20 1 WR Programming cycle control CE P5 6 OTP enable signal RSEL P5 7 Control signal RSEL used for protection lock control must be 0 for OTP programming cycles RSTOUT RSTOUT Must be held high pullup resistor Vpp P20 5 EA Vpp__ External programming voltage 1 The specific behavior of the C164CM in emulation mode prerequisite for EHM is described in Section 20 4 1 The access cycles generated by the external host must fulfill the timing requirements shown in the timing diagr
281. e Adapt mode is latched with the rising edge of RSTIN After the internal reset condition is removed the microcontroller will either start program execution from external or internal memory or it will enter boot mode RSTOUT External Hardware RSTIN a External Reset JI Reset Ib Sources 8 Generated Warm Reset b Automatic Power ON Reset MCA04483 Figure 20 1 External Reset Circuitry User s Manual 20 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset 20 1 Reset Sources Several external or internal sources can generate a reset for the C164CM Software can identify the respective reset source via the reset source indication flags in register WDTCON Generally any reset causes the same actions on the C164CM s modules The differences are described in the following sections Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is latched low To ensure the recognition of the RSTIN signal latching it must be held low for at least 100 ns plus 2 CPU clock cycles input filter plus synchronization Shorter RSTIN pulses may also trigger a hardware reset if they coincide with the latch s sample point The actual minimum duration for a reset pulse depends on the current CPU clock generation mode The worst case is generating the CPU clock via the SlowDown Divider using the maximum factor while the config
282. e injected automatically into the decode stage of the pipeline and then they pass through the remaining stages like every standard instruction Program interrupts are performed by means of injected instructions as well Although these internally injected instructions will not be noticed in reality they are introduced here to ease the explanation of the pipeline in the following sections User s Manual 4 3 V1 0 2002 02 _ e Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Sequential Instruction Processing Each single instruction must pass through each of the four pipeline stages regardless of whether or not all possible stage operations are actually performed Because passing through one pipeline stage takes at least one machine cycle any isolated instruction takes at least four machine cycles to be completed Pipelining however allows parallel simultaneous processing of up to four instructions Thus most of the instructions seem to be processed in one machine cycle as soon as the pipeline has been filled once after reset see Figure 4 2 Instruction pipelining increases the average instruction throughput considered over a certain period of time In the following any execution time specification for an instruction always refers to the average execution time due to pipelined parallel instruction processing 1 Machine Cycle FETCH L I L L
283. e must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed User s Manual 5 34 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto the system stack for the protection fault trap is the address of the instruction which caused the trap Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Illegal Instruction Access Trap Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction Illegal Extern
284. e state before stopping their clock signal The port input and output values will not change while PCD is disabled ASCO and SSC will still operate if active CLKOUT will be high if enabled Please also utilize the hints given in Section 21 5 User s Manual 6 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports 7 Parallel Ports In order to accept or generate single external control signals or parallel data the C164CM provides up to 50 parallel IO lines organized as follows four 8 bit IO ports PORTO made of POH and POL PORT1 made of P1H and P1L one 6 bit IO port Port 20 one 4 bit IO port Port 8 and one 8 bit input port Port 5 These port lines may be used for general purpose Input Output functions controlled via software or may be used implicitly by the C164CM s integrated peripherals or by the External Bus Controller All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers excluding Port 5 which is an input only port The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of Port 8 can be configured pin by pin for push pull operation or open drain operation via a control register The logic level of a pin is clocked into the input latch once per state time regardless of whether the port is config
285. e value of CCnl when the compare timer T12 is not running CCnl represents the passive output level for an enabled compare channel Note The initial values are valid only for capture compare outputs which are enabled for compare mode operation compare output COUTnI Compare Output COUT6n Initial Value n 0 2 The compare output COUT6n drives the value of COUTnI when the compare timer T12 is not running COUTnI represents the passive output level for an enabled compare channel Note The initial values are valid only for capture compare outputs which are enabled for compare mode operation compare output COUTXI COUTS6n Inversion Control 0 T13 s output signal is directly connected to compare outputs COUTS6n in burst or multi channel mode n 0 2 1 T13 s output signal is inverted and then connected to compare outputs COUT6n in burst or multi channel mode n O 2 COUTSI Compare Output COUT63 Initial Value This bit defines the initial logic state of the output COUT63 before timer T13 is started the first time Further COUTSI defines the logic state of COUT63 when bit ECT130 is reset COUT63 disabled BCM Multi channel PWM Mode Output Pattern Selection This bitfield selects the output signal pattern in all multi channel PWM modes also refer to bitfield MPWM 00 Idle mode 01 Rotate right mode 10 Rotate left mode 11 Slow down mode User s Manual 17 26 V1 0 2002 02
286. echnologies Derivatives Memory Organization 3 1 Internal ROM Area The C164CM may reserve an address area of variable size depending on the version for on chip mask programmable ROM Flash OTP memory organized as X x 32 The lower 32 KBytes of this on chip memory block are referred to as Internal ROM Area Internal ROM accesses are globally enabled or disabled via bit ROMEN in register SYSCON This bit is set during reset according to the level on pin EA or may be altered via software If enabled the internal ROM area occupies the lower 32 KBytes of either segment 0 or segment 1 alternate ROM area This mapping is controlled by bit ROMS1 in register SYSCON Note The size of the internal ROM area is independent of the actual size of the implemented Program Memory Also devices with less than 32 KBytes of Program Memory or without any Program Memory will have this 32 KByte area occupied if the Program Memory is enabled Devices with a larger Program Memory provide the mapping option only for the internal ROM area Devices with a Program Memory size above 32 KBytes expand the ROM area from the middle of segment 1 starting at address 01 8000 The internal Program Memory can be used for both code instructions and data constants tables etc storage Code fetches are always made on even byte addresses The highest possible code storage location in the internal Program Memory is either xx xxFE for single word instructions
287. ecrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T3l in control register T3CON selects the triggering transition see Table 10 5 Edge Select Timers Up Down Txl Interrupt p Request TxIR MCB02030c TSIN P5 3 T3EUD P5 2 x 3 Figure 10 5 Block Diagram of Core Timer T3 in Counter Mode Table 10 5 GPT1 Core Timer T3 Counter Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled 00 1 Positive transition rising edge on T3IN 010 Negative transition falling edge on T3IN 0 1 1 Any transition rising or falling edge on T3IN 1XX Reserved Do not use this combination For counter operation pin T3IN must be configured as input the respective direction control bit DPx y must be set to 0 The maximum input frequency allowed in counter mode is fcpy 16 To ensure that a transition of the count input signal applied to T3IN is recognized correctly its level should be held high or low for at least 8 fcpy cycles before it changes User s Manual 10 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Timer 3 in Incremental Interface Mode Incremental Interface Mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 110g In incremental interface mode the two in
288. ed 1 Timer Tn is cleared when it is stopped and the compare outputs are set to their defined idle state Note For capture mode T12 only Clearing CT12R after a capture event while CT12RES 1 will destroy the value stored in the capture register CC6x all shadow registers are transparent Keep CT12RES 0 in capture mode STE12 Timer T12 Shadow Latch Transfer Enable 0 Transfer from the shadow latches to the initial value bits and the period compare and offset registers T12P CC6x T12OF of timer T12 is disabled 1 Timer T12 s initial value bits and the period compare and offset registers are loaded from their shadow latches when T12 reaches 0000 cleared in edge aligned mode counting down in center aligned mode In center aligned mode the registers are also loaded when T12 reaches the period value Note STE12 is cleared by hardware after the shadow latch transfer User s Manual 17 23 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Bit Function ETRP Emergency Trap Interrupt Enable 0 The emergency interrupt for the CAPCOM6 trap signal is disabled 1s The emergency interrupt for the CAPCOM6 trap signal is enabled CTM T12 Operating Mode 0 Edge Aligned Mode count up 1 Center Aligned Mode count up down STE13 Timer T13 Shadow Latch Transfer Enable 0 Transfer from the shadow latches to the period and compare regis
289. ed EXXxIN pin 01 Input from alternate pin 10 Input from pin EXxIN ORed with alternate pin 11 Input from pin EXxIN ANDed with alternate pin The Table 5 10 summarizes the association of the bitfields of register EXISEL with the respective interface input lines Table 5 10 Connection of Interface Inputs to External Interrupt Nodes Bitfield Associated Interface Line Notes EXIOSS CAN1_RxD CAN C164CM The used pin depends on the assignment for the module EXI2SS RxDO ASCO EXI3SS SCLK SSC User s Manual 5 29 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions External Interrupts During Sleep Mode During Sleep Mode all peripheral clock signals are deactivated This also disables the standard edge detection logic for the fast external interrupts However transitions on these interrupt inputs must be recognized in order to initiate the wakeup Therefore during Sleep Mode special edge detection logic for the fast external interrupts EXzIN is activated which requires no clock signal therefore also works in Sleep mode and is equipped with an analog noise filter This filter suppresses spikes generated by noise up to 10 ns Input pulses with a duration of 100 ns minimum are recognized and generate an interrupt request This filter delays the recognition of an external wakeup signal by approximately 100 ns but the spike suppression ensures
290. ed XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers Registers ADDRSEL2 and ADDRSEL4 are evaluated before ADDRSEL1 and ADDRSEL3 respectively A match with one of these registers directs the access to the respective external area using the corresponding BUSCONXx register and ignoring registers ADDRSEL1 3 see Figure 9 9 A match with registers ADDRSEL1 or ADDRSELS directs the access to the respective external area using the corresponding BUSCONXx register If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCONO XBCONO BUSCON2 BUSCON1 Buscono E gt L Active Window E Inactive Window H _ BUSCON4 E 3 O m suscows i MCA04368 Figure 9 10 Address Window Arbitration Note Only the indicated overlaps are defined All other overlaps lead to erroneous bus cycles for example ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1 The hardwired XADRSx registers are defined as non overlapping User s Manual 9 21 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface iia Value of POH SFR F108p 84p Reset Value XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG rh
291. ed before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted e SORIR is activated when the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single transfers it is sufficient to use the transmitter interrupt SOTIR which indicates that the previously loaded data has been transmitted except for the last bit of an asynchronous frame For multiple back to back transfers it is necessary to load the subsequent piece of data at last until the last bit of the previous frame has been transmitted In asynchronous mode this leaves only one bit time for the handler to respond to the transmitter interrupt request In synchronous mode this makes response impossible Using the transmit buffer interrupt SOTBIR to reload transmit data provides the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the previous data is still being transmitted User s Manual 11 16 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface SOTIR SOTIR SOTIR SOTBIR SOTBIR SOTBIR Idle L Asynchronous Mode SORIR SORIR SORIR SOTIR SOTIR SOTIR SOTBIR SOTBIR SOTBIR Idle Idle Synchronous Mode SORIR SORIR SORIR
292. ed for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These instructions are also performed in a single machine cycle Bit field instructions have been provided as well to allow the modification of multiple bits from one operand in a single instruction User s Manual 2 5 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Architectural Overview High Performance Branch Call and Loop Processing Due to the high percentage of branching in controller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided e Single cycle branch execution after the first iteration of a loop The first solution provides that only one machine cycle is lost during the execution of the entire loop In loops which fall through upon completion no machine cycles are lost when exiting the loop No special instructions are required to perform loops and loops are automatically detected during execution of branch instructions Detection of the end of a table The second loop enhancement avoids the use of two compare instructions embedded in loops
293. ed which incorporates concepts from Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions required by microcontroller users The instruction set was designed to meet the following goals Provide powerful instructions for frequently performed operations which traditionally have required sequences of instructions Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines Avoid complex encoding schemes by placing operands in consistent fields for each instruction and avoid complex addressing modes which are not frequently used Consequently the instruction decode time decreases and the development of compilers and assemblers is simplified Provide most frequently used instructions with one word instruction formats All other instructions use two word formats This allows all instructions to be placed on word boundaries this alleviates the need for complex alignment hardware It also has the benefit of increasing the range for relative branching instructions The high performance of the CPU hardware can be utilized efficiently by a programmer by means of the highly functional C164CM instruction set which includes the following instruction classes Arithmetic
294. eg or bitoff 4 Bit GPR Context Pointer Internal RAM Must be within the internal RAM area For byte GPR For word GPR accesses accesses MCD02005 Figure 4 8 Implicit CP Use by Short GPR Addressing Modes Stack Pointer SP This non bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Because the least significant bit of register SP is tied to 0 and bits 15 through 12 are tied to 1 by hardware the SP register can contain values from F000 to FFFE only This allows access to a physical stack within the internal RAM of the C164CM A virtual stack usually bigger can be implemented via software This mechanism is supported by registers STKOV and STKUN see respective descriptions below The SP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not immediately follow an instruction which updated the SP register SP Stack Pointer Register SFR FE12 09 Reset Value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 sp 0 r r r r rwh r Bit Function sp M
295. elects the active level of the gate input The same options for the input frequency are available in gated timer mode as in timer mode However the input clock to the timer in this mode is gated by the external input pin T3IN Timer T3 External Input To enable this operation pin T3IN must be configured as input that is the corresponding direction control bit must contain O Txl To auxiliary Timers Interrupt gt Request TxIR TxEUD e TxUDE MCB02029b TSIN P5 3 X23 TSEUD P5 2 n 3 10 Figure 10 4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timer Additionally the timer can be turned on or off by software using bit T3R The timer will only run if T3R 1 and the gate is active It will stop if either T3R 0 or the gate is inactive Note A transition of the gate signal at pin T3IN does not cause an interrupt request User s Manual 10 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 001 In counter mode timer T3 is clocked by a transition at the external input pin TSIN The event causing an increment or d
296. els Otherwise an incorrect PEC channel may be activated User s Manual 5 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Interrupt Control Register PEC Control PEC Channel MCA04330 Figure 5 1 Priority Levels and PEC Channels The Table 5 3 shows in a few examples which action is executed with a given programming of an interrupt control register Table 5 3 Interrupt Priority Examples Priority Level Type of Service ILVL GLVL COUNT 004 COUNT 00 1111 11 CPU interrupt PEC service level 15 group priority 3 channel 7 1111 10 CPU interrupt PEC service level 15 group priority 2 channel 6 1110 10 CPU interrupt PEC service level 14 group priority 2 channel 2 1101 10 CPU interrupt CPU interrupt level 13 group priority 2 level 13 group priority 2 0001 11 CPU interrupt CPU interrupt level 1 group priority 3 level 1 group priority 3 0001 00 CPU interrupt CPU interrupt level 1 group priority O level 1 group priority O 0000 XX No service No service Note Requests on levels 13 1 cannot initiate PEC transfers They are always serviced by an interrupt service routine no PECC register is associated and no COUNT field is checked User s Manual V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Interrupt Control Functio
297. en if more sequences are executed before the timer increments lower timer frequency a given compare value only results in one single compare event User s Manual 16 14 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM2 Interrupt Request gt Compare Reg CCx Input Interrupt Clock Request X 81 16 not all channels are connected to port pins and interrupt nodes y 7 8 MCB02016a Figure 16 6 Compare Mode 0 and 1 Block Diagram Note The port latch and pin remain unaffected in compare mode 0 In the example shown in Figure 16 7 the compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and 4 etc This results in periodic interrupt requests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 Contents of Ty FFFF Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000 Interrupt Requests TyIR CCxIR CCxiIR TyIR CCxIR CCxIR TyIR t Event 1 Event 2 Event 3 Event 4 CCx cv2 CCx cv1 CCx 2 cv2 CCx cv1 Output pin CCxIO only effected in mode 1 No changes in mode 0 X 2 31 16 y 7 8 MCBO05119 Figure 16 7 Timing Example for Compare Modes 0 and 1 User s Manual 16 15 V1 0 2002 02 _ Infineon C164CM C164SM tec
298. ent position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods User s Manual 10 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit 10 1 2 GPT1 Auxiliary Timers T2 and T4 Auxiliary timers T2 and T4 have exactly the same functionality They can be configured for timer gated timer counter or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 4 counting modes the auxiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer The individual configurations for timers T2 and T4 are determined by their bitaddressable control registers T2CON and T4CON which are organized identically Note that functions present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers Note The auxiliary timers have no output toggle latch and no alternate output function Tes Control Register SFR FF40 A0 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f luz UB ter T2M T2I z rw rw rw rw rw T4CON Timer 4 Control Register SFR FF44 A2
299. ep if any OR command is used 2 Usually byte accesses should not be used for Special Function Registers 3 SYSRLS is cleared by hardware if unlock sequence and write access were successful Otherwise SYSRLS shows the last value written User s Manual 21 22 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives Power Management The following registers are secured by the described unlock sequence Table 21 7 Special Registers Secured by the Unlock Sequence Register Name Description SYSCON 1 Controls sleep mode SYSCON2 Controls clock generation SDD and the unlock sequence itself SYSCON3 Controls the flexible peripheral management RSTCON Controls the configuration of the C164CM basic clock generation mode CS lines segment address width and the length of the reset sequence Code Examples The code examples below show how the unlock sequence is used to access register SYSCON marked in the comment column in an application in order to change the basic clock generation mode Examples where the PLL keeps running 1 ENTER_SLOWDOWN Currently running on basic clock frequ MOV SYSCON2 ZEROS Clear bits 3 0 no EXTR required here EXTR 4H Switch to ESFR space and lock sequence BFLDL SYSCON2 0FH 09H Unlock sequence step 1 1001B MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to one locked
300. epends on the Phase Buffer Segment 1 PB1 the Phase Buffer Segment 2 PB2 and the Resynchronization Jump Width SJW df lt min PB1 PB2 if 2x 13 x bit time PB2 AND fsjw d lt Sox bittime The following examples illustrate bit timing calculations under specific circumstances User s Manual 19 13 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives On Chip CAN Interface Bit Timing Example for High Baudrate This example makes the following assumptions e XCLK frequency 20 MHz e BRP 00 CPS 0 Baudrate 1 Mbit s t bus driver delay receiver circuit delay bus line 40 m delay t Prop TSuW ITSeg1 TSeg2 Sync fgit tolerance for fci 100 ns 2x xcLK 50 ns 30 ns 220 ns 600ns 6x fq 100ns 1xfy 700 ns Prop Isjw 200ns Information Processing Time 100ns 1xf 1000 NS sync frSegt TSeg2 B min PB1 PB2 2x 13x bit time PB2 _ O tus 2x 13x1us 0 2us 0 39 Bit Timing Example for Low Baudrate This example makes the following assumptions e XCLK frequency 4 MHz e BRP 01 CPS 0 e Baudrate 100 kbit s fq bus driver delay receiver circuit delay bus line 40 m delay t Prop fSJw fTSegt TSeg2 Sync fpit tolerance for fxci User s Manual 1 us 4 x txcLk 200 ns 80 ns 220 ns 1 us 1xf 4us 4x fq 5 uS fprop suw 4 us Information Processing Time 2 x tg 1 us 1xf 10us Sync
301. er Table 11 5 gives the limit baudrates depending on the CPU clock frequency and bit SOBRS Table 11 5 ASCO Synchronous Baudrate Generation CPU clock SOBRS 0 SOBRS 1 fcPu Min Baudrate Max Baudrate Min Baudrate Max Baudrate 16 MHz 244 bit s 2 000 Mbit s 162 bit s 1 333 Mbit s 20 MHz 305 bit s 2 500 Mbit s 203 bit s 1 666 Mbit s 25 MHz 381 bit s 3 125 Mbit s 254 bit s 2 083 Mbit s 33 MHz 504 bit s 4 125 Mbit s 336 bit s 2 750 Mbit s User s Manual 11 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface 11 5 ASCO Interrupt Control Four bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error interrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit buffer interrupt vector SORINT is the receive interrupt vector and SOEINT is the error interrupt vector The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrast to the error interrupt request flag SOEIR the error status flags SOFE SOPE SOOE are not reset automati
302. er 2 00004 CMP13 FE36y 1By CAPCOM 6 Timer 13 Compare Reg 0000 T2 FE40y 20 GPT1 Timer 2 Register 0000 T3 FE424 214 GPT1 Timer 3 Register 00004 T4 FE444 224 GPT1 Timer 4 Register 00004 CC16 FE60 304 CAPCOM Register 16 00004 CC17 FE62y 314 CAPCOM Register 17 0000 CC18 FE644 324 CAPCOM Register 18 00004 CC19 FE66 334 CAPCOM Register 19 00004 CC20 FE68y 344 CAPCOM Register 20 00004 CC21 FE6Ay 354 CAPCOM Register 21 00004 CC22 FE6C 36 CAPCOM Register 22 0000 CC23 FE6E 374 CAPCOM Register 23 00004 CC24 FE70y 384 CAPCOM Register 24 00004 CC25 FE72y 394 CAPCOM Register 25 00004 CC26 FE74u 3AQ CAPCOM Register 26 00004 CC27 FE764 3B CAPCOM Register 27 0000 CC28 FE78y 3C CAPCOM Register 28 00004 User s Manual 23 14 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set Table 23 4 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Address Addr Value CC29 FE7AyW 3D CAPCOM Register 29 0000 CC30 FE7Cy 3Ey CAPCOM Register 30 00004 CC31 FE7E 3Fy CAPCOM Register 31 00004 ADDAT FEAO 504 A D Converter Result Register 0000 WDT FEAE 574 Watchdog Timer Register read only 00004 SOTBUF FEBO 584 Serial Channel 0 Transmit Buffer Reg 0000 write only SORBUF FEB2 594 Serial Channel 0 Receive Buffer Reg XXXXy read only SOBG FE
303. er CSR in the case of a status change interrupt The updating of INTID is done by the CAN state machine and takes up to 6 CAN clock cycles depending on current state of the state machine 1 CAN clock cycle 1 or 2 CPU clock cycles as determined by the prescaler bit CPS Note A worst case condition can occur when BRP 00 AND the CAN controller is storing a message just received AND the CPU is executing consecutive accesses to the CAN module In this rare case the maximum delay may be 26 CAN clock cycles The impact of this delay can be minimized by clearing bit INTPND atan early stage User s Manual 19 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface of interrupt processing and if required restricting CPU accesses to the CAN module until the anticipated update is complete PCIR Port Control Interrupt Register XReg EF02 Reset Value XXXX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IPC INTID rw rh Bit Function INTID Interrupt Identifier This number indicates the cause of the interrupt if pending 00H Interrupt Idle There is no interrupt request pending 014 Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or
304. erage application is likely to require substantially more than 16 instructions This second receive loop may use the pre initialized interface ASCO directly to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly execute the final application In all cases the C164CM will continue to run in BSL mode with the watchdog timer disabled and limited access to the internal code memory All code fetches from the internal ROM area 00 0000 00 7FFF or 01 0000 01 7FFFy if mapped to segment 1 are redirected to the special Boot ROM Data fetches access will access the internal code memory of the C164CM if any is available but will return undefined data on ROMless devices Note Data fetches from a protected ROM will not be executed 15 3 Exiting Bootstrap Loader Mode In order to execute a program in normal mode i e watchdog timer active full access to user memory etc the BSL mode must first be terminated The C164CM exits BSL mode in two ways upon a software reset ignoring the external configurat
305. erated in between In practice this seems to be rare Because an interrupt request of the CAN module can be generated by various conditions the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request The interrupt identifier INTID a number in the Port Control Interrupt Register PCIR indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00 4 If the value in INTID is not 00 then there is an interrupt pending If bit IE in the control status register is also set the interrupt signal to the CPU is activated The interrupt signal to the interrupt node remains active until INTID becomes OO all interrupt requests have been serviced or until interrupt generation is disabled CSR IE 0 Note The interrupt node is activated only upon a 0 1 transition of the CAN interrupt signal The CAN interrupt service routine should only be exited after INTID has been verified to be 00 The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one INTID is also updated after the respective source request has been processed This is indicated by clearing the INTPND flag in the respective object s message control register MCRn or by reading the status partition of regist
306. erating mode master or slave In order to enable the alternate output functions of these pins instead of the general purpose IO operation the respective port latches must be set to 1 because the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing IO operations via the port latch The direction of the port lines depends on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins however must be programmed by the user as shown in the following tables Table 12 1 summarizes the required values for the various modes and pins C164CM C164SM Derivatives High Speed Synchronous Serial Interface Port Control Table 12 1 SSC Port Control Pin Master Mode Slave Mode Function Port Latch Direction Function Port Latch Direction SCLK Serial POH 7 1 DPOH 7 1 Serial POH 7 x DPOH 7 0 Clock Clock Output Input MTSR _ Serial POH 6 1 DPOH 6 1 Serial POH 6 x DPOH 6 0 Data Data Output Input MRST Serial POH 5 x DPOH 5 0 Serial POH 5 1 DPOH 5 1 Data Data Input Output Note In Table 12 1 an x means that the actual value is irrelevant in the respective mode however it is recommended to
307. ers which feed the CPU and two groups of peripheral modules The Real Time Clock is fed with the prescaled oscillator clock farc via a separate clock driver so it is not affected by the clock control functions User s Manual 6 1 V1 0 2002 02 C164CM C164SM Derivatives Clock Generation Prescaler PLL SDD SIM Bi M B MN Idle Mode PCDDIS Peripherals Ports Intrl Ctrl Interfaces P D Mode Oscillator Frequency Control Clock Drivers MCD04457 User s Manual CPU Clock Generation Stages V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Clock Generation 6 1 Oscillator The main oscillator of the C164CM is a power optimized Pierce oscillator providing an inverter and a feedback element Pins XTAL1 and XTAL2 connect the inverter to the external crystal The standard external oscillator circuitry see Figure 6 2 comprises the crystal two low end capacitors and a series resistor Rx2 to limit the current through the crystal The additional LC combination is only required for 3 overtone crystals to suppress oscillation in the fundamental mode A test resistor Ro may be temporarily inserted to measure the oscillation allowance of the oscillator circuitry XTAL1 XTAL2 Ro Rx2 arin T L1 Figure 6 2 External Oscillator Circuitry MCS04335 The on chip oscillator is optimized for an input frequency range o
308. es System Reset Emulation Mode Pin POL O EMU selects the Emulation Mode when latched low at the end of reset Because this mode is used for special emulation and testing purposes and is of minor use for standard C164CM applications POL O should be held high Emulation Mode provides access to integrated XBUS peripherals via the external bus interface pins direction reversed of the C164CM The CPU and the generic peripherals are disabled all modules connected via the XBUS are active Ensure that all required input pins are driven accordingly see Table 20 1 and no driver conflicts exist on the respective output pins The other pins retain their original function or are unused Unused pins are switched to input and should be pulled to a stable level to avoid switching noise Table 20 1 Emulation Mode Summary Pin s Function Notes PORTO Data input output PORT1 Address input NMI XBHE Must be driven externally can be kept low P20 0 RD Control signal input P20 1 WR Control signal input P20 4 ALE input unused Hold LOW RSTOUT _ Reset input Drive externally for an XBUS peripheral reset RSTIN Reset input Standard reset for complete device P5 1 CScan input Enables module CAN1 in emulation mode P20 8 CLKOUT Automatically enabled Port 8 XBUS peripheral P8 0 CAN1 interrupt output P8 1 not used always High P8 2 not used always High P8 3 PLL Default Emulation Mode is off
309. es interrupt generation on a change of bit BOFF or EWRN in the status partition CPS Clock Prescaler Control Bit 0 Standard mode the input clock is divided 2 1 The minimum input frequency to achieve a baudrate of 1 Mbit s is fepy 16 MHz T Fast mode the input clock is used directly 1 1 The minimum input frequency to achieve a baudrate of 1 Mbit s is fcp j 8 MHz CCE Configuration Change Enable Allows or inhibits CPU access to the Bit Timing Register BTR and the Interface Port Control bit field IPC in register PCIR TM Test Mode must be 0 This bit must always be cleared when writing to the Control Register as this bit controls a special test mode used for production testing only During normal operation use of this test mode may lead to undesired behavior of the device User s Manual 19 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Bit Function Control Bits LEC Last Error Code This field holds a code indicating the type of error which last occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared 0 No Error 1 Stuff Error More than 5 equal bits in a sequence have occurred ina part of a received message where this is not allowed 2 Form Error Wrong format in fixed format part of a received frame 3 AckError The message transmitted by this CAN
310. es the CAPCOM6 s interrupt sources and the related status and control flags and shows the association with the four CAPCOM6 interrupt nodes CAPCOMSG Intr Contr CC60 f CCOR ero lt gt Input CCOREN Reg CC60 CCOFEN Compare Event CC6CIC CC61 CC1R eo 1 jo m Input CC1REN x R qM Reg CC61 CC1FEN Compare Event CC62 CC2R eo Input CC2REN CC2F eo Reg CC62 CC2FEN Compare Even CC6EIC TRF eo 1 Emergency ETRP l o L Interrupt i R i i BCERR eo Gon E EBCE Id ene CT12FP eo 1 Timer T12 ECTP I Events i R i CT12FC eo e j ECTC T13IC Co RNE I l Timer T13 Period CT13P f R iE 3 L as l 1 Internal capture event in case of block commutation mode Use only CCOR in this case MCS04935 Figure 17 13 CAPCOM6 Interrupt Structure User s Manual 17 32 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Interrupt Node Control Registers T121C ESFR F190 C8 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e ae ILVL GLVL S z z mh rw rw rw T13IC ESFR F198 CC Reset Value 00004 15 14 13 12
311. eset Value 00XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDT LHW SHW SW WDT WDT nurse PRE RR RR IN nw rh rh rh rh rw Bit Function WDTIN Watchdog Timer Input Frequency Select Controls the input clock prescaler See Table 13 1 WDTR Watchdog Timer Reset Indication Flag Cleared by a hardware reset or by the SRVWDT instruction SWR Software Reset Indication Flag SHWR Short Hardware Reset Indication Flag LHWR Long Hardware Reset Indication Flag WDTPRE Watchdog Timer Input Prescaler Control Controls the input clock prescaler See Table 13 1 WDTREL Watchdog Timer Reload Value for the high byte of WDT Note The reset value depends on the reset source see description below The execution of EINIT clears the reset indication flags The time period for an overflow of the watchdog timer is programmable in two ways Input frequency to the watchdog timer can be selected via a prescaler controlled by bits WDTPRE and WDTIN in register WDTCON to be fcPu 2 fcpu 4 fcpu 128 or fopy 256 Reload value WDTREL for the high byte of WDT can be programmed in register WDTCON The period Pyypr between servicing the watchdog timer and the next overflow can therefore be determined by the following formula o lt WDTPRE gt lt WDTIN gt x 6 x 216 lt WDTREL gt x 28 PwpT 9 CPU User s Manual 13 4 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Watchdog Timer WDT Tabl
312. eset values STKOV FAO04 STKUN FCOO SP FCOO0 STKSZ 000p map the virtual stack area directly to the physical stack area and allow use of the internal system stack without any changes provided that the 256 word area is not exceeded FBFE 1 1 1 1 FB80 1111 FB80 aa After PUSH FBFE 11 1 1 H FBFE 1111 FB7E 1011 1011 1 OnE 1011 1 1011 000 0000 Phys A 000 0000 lt SP gt Phys A 1111 1011 0111 1110 SP 64 words FBFE 101 FA00 101 F800 100 After PUSH FBFE FBFE F7FE Stack Size 1 guy quu 0 0000 0000 0 0000 0000 1 duum du 1 1111 1110 1 1111 1110 256 words MCA04408 Figure 22 1 Physical Stack Address Generation The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the following instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV PUSH R1 PUSH R2 User s Manual SP HOF802H Set SP before last entry 0f physical stack of 256 words SP F802H Physical stack addr SP F800H Physical stack addr SP F7FEH Physical stack addr 22 6 FAO2H FAOO0H FBFEH V1 0 2002 02 _ Infineo
313. ess via the Context Pointer CP register is mostly incapable of using a new CP value which has been updated by an immediately preceding instruction Thus to ensure that the new CP value is used at least one instruction must be inserted between a CP changing instruction and a subsequent GPR using instruction as shown in the following example La SCXT CP 0FCOOh select a new context Tua bes must not be an instruction using a GPR Ius MOV RO datax write to GPR 0 in the new context Data Page Pointer Updating An instruction which calculates a physical operand address via a particular Data Page Pointer DPPn register n 0 to 3 is mostly incapable of using a new DPPn register value which has been updated by an immediately preceding instruction Thus to ensure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the following example Ia MOV DPPO 4 select data page 4 via DPPO Iud f s must not be an instruction using DPPO Ls MOV DPP0 0000H R1 move contents of R1 to location 01 00004 in data page 4 supposed segment is enabled User s Manual 4 6 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP instructions is
314. essed via indirect and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address allows word SFRs and their respective low bytes to be addressed However this does not work for the respective high bytes Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit addressable so the respective control status bits can be modified directly or checked using bit addressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR instruction is required beforehand to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect addresses The GPRs H15 RO are duplicated i e they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching ESFR SWITCH EXAMPLE EXTR 4 Switch to ESFR area for next 4 instr MOV ODP8 datal ODP2 uses 8 bit reg addressing BFLDL DP8 mask data8 Bit addressing for bit fields BSET DPI 7 Bit addressing for single bits MOV T8REL R1 T8REL uses 16 bit mem address R1 is duplicated into the ESFR space EXTR is not required for this access po o P 222 2 The scope of the EXTR 4 instruction ends here MOV T8REL R1 T8REL uses 16 bit mem address R1 is accessed via the SFR space In order to minimize
315. essing Unit CPU Multiply Divide Low Register MDL This register is part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the low order 16 bits of the 32 bit result For long divisions the MDL register must be loaded with the low order 16 bits of the 32 bit dividend before the division is started After any division register MDL represents the 16 bit quotient Mut DIVINIS Low Reg SFR FEOE 07 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mdl rwh Bit Function mdl Specifies the low order 16 bits of the 32 bit multiply and divide reg MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDL must be saved along with registers MDH and MDC to avoid erroneous results A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in Chapter 22 User s Manual 4 31 V1 0 2002 02 _ Infineon C16
316. est in any case The occurrence of an interrupt request can so be polled via xxIR even while the node is disabled Note In this case the interrupt request flag xxIR is not cleared automatically but must be cleared via software User s Manual 5 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests The priority increases with the numerical value of ILVL so 0000g is the lowest and 1111g is the highest priority level When more than one interrupt request on a specific level becomes active at the same time the values in the respective bit fields GLVL are used for second level arbitration to select one request to be serviced Again the group priority increases with the numerical value of GLVL so 00g is the lowest and 11g is the highest group priority Note All interrupt request sources enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Upon entry into the interrupt service routine the priority level of the source that won the arbitration and whose priority level is higher than the current CPU level is copied into bit field ILVL of register PSW after pushing the old PSW contents onto the stack The in
317. eup from Idle mode via RTC timer The listed features provide effective means to realize standby conditions for the system with an optimum balance between power reduction standby time and peripheral operation system functionality User s Manual 2 19 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview Flexible Clock Generation The flexible clock generation system combines a variety of improved mechanisms partly user controllable to provide the C164CM modules with clock signals This is especially important in power sensitive modes such as standby operation The power optimized oscillator generally reduces the amount of power which is consumed in order to generate the clock signal within the C164CM The clock system efficiently controls the amount of power which is consumed in order to distribute the clock signal within the C164CM Slowdown operation is achieved by dividing the oscillator clock by a programmable factor 1 32 resulting in a low frequency device operation which significantly reduces the overall power consumption Flexible Peripheral Management Flexible peripheral management provides a mechanism to enable and disable each peripheral module separately In each situation such as several system operating modes standby etc only those peripherals may be kept running which are required for the specified functionality All others may be switched off It also allo
318. external input signal is determined by bit fields T2l or T41 When these fields are programmed to X01g interrupt request flags T2IR or TAIR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or TAIN respectively When T2l or T4l is programmed to X10p then a negative external transition will set the corresponding request flag When T21l or T4l is programmed to X115 both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or TAIN When the interrupt enable bits T2IE or T4IE are set a PEC request or an interrupt request for vector T2INT or TAINT will be generated Note The non maskable interrupt input pin NMI sample rate 2 TCL and the reset input RSTIN provide another possibility for the CPU to react to an external input signal NMI and RSTIN are dedicated input pins which cause hardware traps User s Manual 5 26 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Fast External Interrupts Input pins which may be used for external interrupts are sampled every 16 TCL that is external events are scanned and detected in time frames of 16 TCL The C164CM provides 4 interrupt inputs that are sampled every 2 TCL so external events are captured faster than with standard interrupt inputs
319. f 4 to 16 MHZ An external clock signal e g from an external oscillator or from a master device may be fed to the input XTAL1 The Pierce oscillator then is not required to support the oscillation itself but is rather driven by the input signal In this case the input frequency range may be 0 to 50 MHz please note that the maximum applicable input frequency is limited by the device s maximum CPU frequency Note Oscillator measurement within the final target system is recommended to determine the actual oscillation allowance for the oscillator crystal system The measurement technique examples for evaluated systems and recommendations are provided in a specific application note about oscillators available via your representative or WWW User s Manual 6 3 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Clock Generation For input frequencies above 25 30 MHz the oscillator s output should be terminated as shown in Figure 6 3 at lower frequencies it may be left open This termination improves the operation of the oscillator by filtering out frequencies above the intended oscillator frequency XTAL1 XTAL2 Uu pF Input Clock 3 kQ MCS04336 Figure 6 3 Oscillator Output Termination Note It is strongly recommended to measure the oscillation allowance or margin in the final target system layout to determine the optimum parameters for the oscillator operation User s Man
320. f PEC Channel COUNT COUNT PEC Service and Comments FFy FFy 0 Move a Byte Word Continuous transfer mode i e COUNT is not modified FEy 024 FDy O14 0 Move a Byte Word and decrement COUNT 014 004 T Move a Byte Word Leave request flag set which triggers another request 00H 00H 1 No action Activate interrupt service routine rather than PEC channel The PEC transfer counter allows service of a specified number of requests by the respective PEC channel and then when COUNT reaches 00 activation of the interrupt service routine associated with the priority level After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced User s Manual 5 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions Continuous transfers are selected by the value FFy in bit field COUNT In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again When COUNT is decremented from 01 to 00 after a transfer the request flag is not cleared This generates another request from the same source When COUNT already contains the value 004 the respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows choosing whether a level 15 or 14 request should be serviced by the PEC or by the
321. f at least XTAL2 of the original device is disconnected from the circuitry the output XTAL2 will be driven high in Adapt Mode Adapt mode can be activated only upon an external reset EA 0 Pin POL 1 is not evaluated upon a single chip reset EA 1 User s Manual 20 15 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives System Reset Special Operation Modes Pins POL 5 to POL 2 SMOD select special operation modes of the C164CM during reset see Table 20 2 Make sure to select only valid configurations to ensure proper operation of the C164CM Table 20 2 Definition of Special Modes for Reset Configuration P0 5 2 POL 5 2 Special Mode Notes 111 1 Normal Start Default configuration mu Begin of execution as defined via pin EA 1110 CPU Host Mode Programming mode for OTP memory via the CHM C164CM s CPU 1101 Reserved Do not select this configuration 1100 Reserved Do not select this configuration 101 1 Standard Bootstrap Load an initial boot routine of 32 Bytes via Loader interface ASCO 1010 Bootstrap Loader Serial programming of OTP memory via CPU Host Mode ASCO using the bootstrap loader 100 1 Alternate Boot Operation not yet defined Do not use 1000 Reserved Do not select this configuration 0 11 1 No emulation mode Operation not yet defined Do not use Alternate Start Emulation mode Programming mode for OTP memory via Ex
322. f other logic gates see a in Figure 20 1 See also Bidirectional Reset on Page 22 4 in this case Note A power on reset requires an active time of two reset sequences 1036 CPU clock cycles after a stable clock signal is available about 10 50 ms depending on the oscillator frequency to allow the on chip oscillator to stabilize User s Manual 20 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Software Reset The reset sequence can be triggered at any time via the protected instruction SRST Software Reset This instruction can be executed deliberately within a program such as to exit bootstrap loader mode or upon a hardware trap that reveals a system failure Note A software reset only latches the configuration of the bus interface BUSTYP from PORTO in case of an external reset If bidirectional reset is enabled a software reset is executed like a long hardware reset Watchdog Timer Reset If the Watchdog Timer WDT is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence Other than after hardware and software reset the watchdog reset completes a running external bus cycle Then the internal reset sequence is started Note A watchdog reset only latches the configuration of the bus interface BUSTYP from PORTO in case of an external reset If bidirectional reset is enabled a watchdo
323. ferent available temperature ranges and packages For simplicity these various device types are referred to by the collective term C164CM throughout this manual The complete pro electron conforming designations are listed in the respective data sheets Some sections of this manual do not refer to all of the C164CM derivatives which are currently available or planned such as devices with different types of on chip memory or peripherals These sections contain respective notes wherever possible User s Manual 1 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Introduction 1 1 Members of the 16 bit Microcontroller Family The microcontrollers in the Infineon 16 bit family have been designed to meet the high performance requirements of real time embedded control applications The architecture of this family has been optimized for high instruction throughput and minimized response time to external stimuli interrupts Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent This also minimizes the need for communication via the external bus interface The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive industrial control or data communications The core of the 16 bit family has been developed with a modular family concept in mind All family members execute an effi
324. ffer is overwritten The Loop Back option selected by bit SOLB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test serial communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the Port pins are not necessary Note Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit SOR is set to 1 Otherwise the serial interface is idle To avoid unpredictable behavior of the serial interface do not program the mode control field SOM in register SOCON to one of the reserved combinations User s Manual 11 4 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface 11 1 Asynchronous Operation Asynchronous mode supports full duplex communication in which both transmitter and receiver use the same data frame format and the same baud rate Data is transmitted on pin TXDO and received on pin RXDO These signals are alternate port functions Reload Register it gt er 2r Baud Rate Timer SOR SOPE SOM SOSTP SOFE 4 SOOE Clock SORIR Receive Int Request Serial Port Control SOTIR Transmit Int Pa Request Error Int Shift Clock SOEIR Request TXDO Internal Bus MCB02219 Figure 11 2 Asynchronous Mode of Serial Channel ASC
325. fined U unchanged undefined X after power up r w Access modes can be read and or write h Bits that are set cleared by hardware are marked with a shaded access box and an h in it User s Manual 23 1 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set 23 2 CPU General Purpose Registers GPRs The General Purpose Registers GPRs form the register bank with which the CPU works This register bank may be located anywhere within the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks can reside only within the internal RAM All GPRs are bit addressable Table 23 1 General Purpose Word Registers Name Physical 8 bit Description Reset Address _ Address Value RO CP 0 FOH CPU General Purpose Word Reg RO UUUU H1 CP 2 F1 CPU General Purpose Word Reg R1 UUUU R2 CP 4 F2y CPU General Purpose Word Reg R2 UUUU R3 CP 6 F3y CPU General Purpose Word Reg R3 UUUU R4 CP 8 F4u CPU General Purpose Word Reg R4 UUUU R5 CP 10 F5 CPU General Purpose Word Reg R5 UUUU R6 CP 12 F6 CPU General Purpose Word Reg R6 UUUU R7 CP 14 F7 CPU General Purpose Word Reg R7 UUUU R8 CP 16 F8 CPU General Purpose Word Reg R8 UUUU R9 CP 18 F94 CPU General Purpose Word Reg R9 UUUU R10 CP 20 FA CPU General Purpose Word Reg R10 UUUU R11 CP 22
326. fined signal pattern sequence is driven to the output lines Note Compare timer T12 must be enabled CT12R 1 in order to enable proper operation of the multi channel modes Multi phase modes allow the effective generation of output signal patterns for 4 6 phase unipolar drives for example The phase sequence can be controlled automatically by T12 overflows or by software Block Commutation mode is a special multi channel mode which especially supports the control of brushless DC drives In this mode the phase sequence is controlled by three input signals CC6POSx generated by the drive via hall sensors for instance In all modes the output signals can be modulated during their active phases Emergency Interrupt Trap Control CTRAP CC6POSO Multi CC6POS1 Channel CC6POS2 Control CC60 CC61 CC62 COUT60 Capture PWM COUT61 Event COUT62 Channel 0 in Capture Mode Period Timer T13 gt COUT63 Match Interrupt MCB04113 Figure 17 9 Multi Channel Mode Control User s Manual 17 12 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 6 1 Output Signals in Multi Channel Mode In multi channel mode the output signals are controlled primarily by the selected phase sequence see sequence tables below Each output is active for two phases and remains passive for all other phases of a sequence The active phases of each out
327. for implementation of a circular stack with hardware supported system stack flushing and filling except for option 111 The technique for implementing the circular stack is described in Chapter 22 User s Manual 3 5 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Memory Organization General Purpose Registers The General Purpose Registers GPRs use a block of 16 consecutive words within the Internal RAM The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 Word GPRs RO R1 R15 and or of up to 16 Byte GPRs RLO RHO RL7 RH7 The sixteen Byte GPRs are mapped onto the first eight Word GPRs see Table 3 2 In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Bytes The GPRs are accessed via short 2 4 or 8 bit addressing modes using the Context Pointer CP register as base address independent of the current DPP register contents Additionally each bit in the currently active register bank can be accessed individually Table 3 2 Mapping of General Purpose Registers to RAM Addresses Internal RAM Address Byte Registers Word Register lt CP gt 1E R15 lt CP gt 1Cy R14 CP 1Ay R13 CP 184 R12 lt CP gt 164 R11 lt CP gt 144 R1
328. frames match with receive objects only remote frames match with transmit objects only When the CAN controller stores a data frame it will write all the eight data bytes into a message object If the data length code was less than 8 the remaining bytes of the message object will be overwritten by non specified values MCFGn Message Configuration Reg XReg EFn6 Reset Value UU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Byte 0 DLC DIR XTD O 0 nw nw nw nw r r Bit Function XTD Extended Identifier 0 Standard This message object uses a standard 11 bit identifier 1i Extended This message object uses an extended 29 bit identifier DIR Message Direction 0 Receive Object On TXRQ a remote frame with the identifier of this message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object 1 Transmit Object On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND bits of this message object are set DLC Data Length Code Defines the number of valid data bytes within the data area Valid values for the data length are O 8 Note The first data byte occupies the upper half of the message configuration register User s Manual 19 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On
329. g a second level loader routine ROM memory internal or external is not necessary However it may be used to provide lookup tables or to provide core code a set of general purpose subroutines for IO operations number crunching system initialization etc RSTIN POL 4 or RD RxDO CSP IP 32 bytes Int Boot ROM BSL routine User Software BSL initialization time lt 70 fopy us fepy in MHz 2 Zero byte 1 start Bit eight 0 data Bits 1 stop Bit sent by host 3 dentification byte sent by microcontroller 4 32 bytes of code data sent by host 9 Caution TxDO is only driven a certain time after reception of the zero byte lt 40 fopy US fopy in MHz 9 Internal Boot ROM MCT04465 Figure 15 1 Bootstrap Loader Sequence The Bootstrap Loader may be used to load the complete application software into ROMless systems it may load temporary software into complete systems for testing or calibration or it may be used to load a programming routine for Flash devices The BSL mechanism may be used for standard system startup or for special occasions such as system maintenance firmware update end of line programming or testing User s Manual 15 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Bootstrap Loader 15 1 Entering the Bootstrap Loader The C164CM enters BSL mode triggered by external configuration during a hardware reset when pin POL 4
330. g normal operation the CPU first clears bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again User s Manual 19 32 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Busoff Recovery Sequence If the device goes busoff it will set bit BOFF and bit INIT of its own accord stopping all bus activities For the CAN module to take part in the CAN bus activities again the bus off recovery sequence must be started by clearing the bit INIT via software After INIT has been cleared the module will then wait for 129 occurrences of Bus idle before resuming normal operation At the end of the busoff recovery sequence the Error Management Counters will be reset This will automatically clear bits BOFF and EWRN During the waiting time after the resetting of INIT each time a sequence of 11 recessive bits has been monitored a BitOError code is written to the Control Register enabling the CPU to determine whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the progress of the busoff recovery sequence Note An interrupt can be generated when entering the busoff state if bits IE and EIE are set The corresponding interrupt code in bitfield INTID is O1 The busoff recovery sequence cannot be shortened by setting or resetting INIT User s Manual 19 33 V1 0 2002 02 _ Infineon C164CM C164SM technologies Deriv
331. g timer reset is executed like a long hardware reset The watchdog reset cannot occur while the C164CM is in bootstrap loader mode User s Manual 20 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Bidirectional Reset In a special bidirectional reset mode the C164CM s line RSTIN normally an input may be driven active by the chip logic This is useful for instance to support external equipment required for startup such as flash memory RSTIN gt Internal Circuitry Reset Sequence Active BDRSTEN MCS04403 Figure 20 2 Bidirectional Reset Operation Bidirectional reset reflects internal reset sources software watchdog to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON it changes RSTIN from a pure input to an open drain IO line When an internal reset is triggered by the SRST instruction by a watchdog timer overflow or by a low level applied to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence After that it is released and is then controlled solely by the external circuitry The bidirectional reset function is useful for applications in which external devices require a defined reset signal but which cannot be connected to the C164CM s RSTOUT signal for example an externa
332. gic Functional Approach A priority ranking determines which function controls the shared pin Table 21 4 Priority Ranking for Shared Output Pin Priority Function Control 1 CLKOUT CLKEN 1 FOEN x 2 FOUT CLKEN 0 FOEN 1 3 General purpose IO CLKEN 0 FOEN 0 Note For the generation of foyr pin FOUT must be switched to output i e DP20 8 1 While four is disabled the pin is controlled by the port latch see Figure 21 7 The port latch P20 8 must be 0 in order to maintain the four inactive level on the pin User s Manual 21 19 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management Jopu HLLELFLFLELELELELELELELE LL 1 Sout FORV 0 2 1 Sout FORV 2 2 1 four FORV 5 2 FOEN 1 FOEN gt 0 1 FOSS 1 Output of Counter t 2 FOSS 0 Output of Toggle Latch The counter starts here The counter stops here MCT04482 Figure 21 8 Signal Waveforms Note The output signal for FOSS 1 is high for the duration of one fep cycle for all reload values FORV gt 0 The output signal corresponds to fcpy for FORV 0 User s Manual 21 20 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Power Management Output Frequency Calculation The output frequency can be calculated
333. gies Derivatives System Programming Linear Stack The C164CM also offers a linear stack option STKSZ 1115 in which the system stack may use the entire internal RAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may be effectively consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bits of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 FOOO up to OO FFFE the physical system stack must be located within the internal RAM and therefore may use only the address range 00 F200 700 F600 00 FA00 to 0O0 FDFE It is the user s responsibility to restrict the system stack to the range of the internal RAM Note Avoid stack accesses below the IRAM area ESFR space and reserved area and within address range 00 FEO0 and OO FFFE SFR space Otherwise unpredictable results will occur User Stacks User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both bytes and words onto a user stack but is responsible for using the appropriate instructions when popping data from the specific user stack No
334. h Non zero Offset Note Offset operation is only available in the full function module and is possible for the three capture compare channels on timer T12 only The compare channel on timer T13 does not provide an offset register and has no second output signal User s Manual 17 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 3 Center Aligned Mode The three capture compare channels associated with T12 may operate in center aligned mode The compare timer T12 counts up starting at 0000 When the timer contents match the respective compare value in register CC6x the associated output signal CC6x is switched to its active state while counting up Upon reaching the period value stored in register T12P the count direction is reversed and the timer counts down When the timer contents match the respective compare value in register CC6x the associated output signal CC6x is switched to its passive state while counting down The output signals COUT6x are switched upon matches of register CC6x with T12 T12OF Non zero offset values shift the COUT6x edges symmetrically against the CC6x edges see Figure 17 6 This allows the generation of non overlapping signal pairs CC6x COUT6x with arbitrary active levels These signal pairs may e g be used to drive the high and low side switches of a power bridge without the risk of a branch shortcut prevented by the programmable dead time
335. hanged inadvertently by software errors However because these registers control important functions e g the power management they need to be accessed during operation to select the appropriate mode The system control software gains this access via a special unlock sequence which allows one single write access to one register of this set when executed properly This provides maximum security Note All these registers may be read at any time without restrictions The unlock sequence is executed by writing defined values to bitfield SYSRLS using defined instructions see Table 21 6 The instructions of the unlock sequence including the intended write access must be secured with an EXTR instruction switch to ESFR space and lock interrupts Note The unlock sequence is aborted if the locked range EXTR does not cover the complete sequence The unlock sequence provides no write access to register SYSCON Table 21 6 Unlock Sequence for Secured Registers Step SYSRLS Instruction Notes 00005 Status before release sequence 1 10015 BFLDL OR ORB2 Read Modify Write access XOR XORB 2 0011g MOV MOVB MOVBS Write access MOVBZ 3 0111 BSET BMOV2 BMOVN2 Read Modify Write access BOR BXOR bit instruction 4 Single read modify write access to one of the secured registers 0000 Status after release sequence 1 SYSRLS must be set to 0000g before the first st
336. hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one byte or word from a user stack This mode is available to most instructions but only GPRs RO R3 can be specified as the user stack pointer Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer User s Manual 22 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming 22 2 Register Banking Register banking provides the user with an extremely fast method for switching user context A single machine cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task After the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area each bank pointer is then assigned Thus upon entry into a new task the appropria
337. he CSP register is totally ignored and only the IP is saved to and restored from the stack In segmented memory mode SGTDIS 0 it is assumed that the entire address space is available for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls whether the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt service routine is left again System Stack Size STKSZ This bitfield defines the size of the physical system stack located in the internal RAM of the C164CM An area of 32 512 words or all of the internal RAM may be dedicated to the system stack A so called circular stack mechanism allows use of a bigger virtual stack than this dedicated RAM area These techniques and the encoding of bitfield STKSZ are described in more detail in Chapter 22 User s Manual 4 15 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Processor Status Word PSW This bit addressable register reflects the current state of the microcontroller Two groups of bits represent the current ALU status and the current CPU interrupt status A separate bit USRO within register PSW is provided as a general purpose user flag
338. he PSW This flag is set when a one is shifted out of the carry bit during shift right operations The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm User s Manual 22 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming 22 6 Peripheral Control and Interface All communication between peripherals and the CPU is performed by either PEC transfers to and from internal memory or by explicit addressing of the SFRs associated with the specific peripherals After resetting the C164CM all peripherals except the watchdog timer are disabled and initialized to default values A desired configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs Specific control flags may also be altered via bit instructions Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be polled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bits in SFRs To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made bit addressable to allow user semaphores Instructions have also been provided to lock out tasks via software by
339. he Watchdog Timer is always enabled after a reset of the chip and can be disabled only for the time interval before the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored The software must be designed to service the Watchdog Timer before it overflows If the software fails to do So due to either hardware or software related failures the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low to allow external hardware components to reset The Watchdog Timer is a 16 bit timer clocked with the CPU clock divided by 2 4 128 or 256 The high byte of the Watchdog Timer register can be set to a prespecified reload value stored in WDTREL to allow further variation of the monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 21us and 671ms can be monitored 25 MHz The default Watchdog Timer interval after reset is 5 2 ms 25 MHz 2 5 Power Management Features The basic power reduction modes Idle and Power Down are enhanced by additional power management features see below These features can be combined to reduce the controller s power consumption to correspond to the application s possible minimum e Flexible clock generation Flexible peripheral management peripherals can be dis enabled separately or in groups Periodic wak
340. he pipeline suspending instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected PEC transfer and resumes the execution of instruction N 1 All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note If instruction N reads any of the PEC control registers PECC7 PECCO when a PEC request wins the current round of prioritization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 states 6 TCL This requires program execution from the internal code memory no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum PEC response time under these conditions is 4 state times 8 TCL The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer including N User s Manual 5 22 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions e When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur the minimum PEC response time may be extended by 1 state time for each of these conditions e When instruction N reads an operand from the inte
341. he writeback would overwrite the new bit value generated by the hardware The solution is provided by either the implemented hardware protection see below or through special programming see Section 4 2 Protected bits are not changed during the read modify write sequence such as when hardware sets an interrupt request flag between the read and the write of the read modify write sequence The hardware protection logic guarantees that only the intended bit s is are affected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit A summary of the protected bits implemented in the C164CM can be found at the end of Chapter 2 User s Manual 4 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU 4 4 Instruction State Times The time to execute an instruction depends primarily on where the instruction is fetched from and where the possible operands are read from or written to The fastest processing mode of the C164CM is execution of a program fetched from the internal code memory In this case most of the instructions can be processed within just one machine cycle which is also the general minimum execution time All external memory accesses are performed by the C164CM s on chip External Bus Controller EBC
342. her devices supporting the serial communication This baudrate deviation is a nonlinear function depending on the CPU clock and the baudrate of the host The maxima of the function Fp increase with the host baudrate due to the smaller baudrate prescaler factors and the implied higher quantization error see Figure 15 3 User s Manual 15 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Bootstrap Loader gt Bios B bign ee B vos ay MCA02260 Figure 15 3 Baudrate Deviation between Host and C164CM The minimum baudrate B ow in Figure 15 3 is determined by the maximum count capacity of timer T3 when measuring the zero byte thus it depends on the CPU clock The minimum baudrate is obtained by using the maximum T3 count 21 in the baudrate formula Baudrates below B o would cause T3 to overflow In this case ASCO cannot be initialized properly and the communication with the external host is likely to fail The maximum baudrate By in Figure 15 3 is the highest baudrate at which the deviation still does not exceed the limit thus all baudrates between B ow and Byigh are below the deviation limit Buig marks the baudrate up to which communication with the external host will work properly without additional tests or investigations Higher baudrates however may be used if the actual deviation does not exceed the indicated limit A certain baudrate marked l in Figure 15
343. heral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0 Pin RSTIN is an input only 1 Pin RSTIN is pulled low during the internal reset sequence after any reset OWDDIS Oscillator Watchdog Disable Bit 0 The on chip oscillator watchdog is enabled and active i The on chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input CLKEN System Clock Output Enable CLKOUT 0 CLKOUT disabled pin may be used for general purpose IO or for signal FOUT 1 CLKOUT enabled pin outputs the system clock signal User s Manual 9 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Bit Function ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal program memory disabled accesses to the ROM area use the external bus 1 Internal program memory enabled SGTDIS Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7F FF 1 Internal ROM area mapped to segment 1 01 0000 01 7FFF STKSZ
344. high impedance d Port line P20 y is an output Note After reset the output driver of pin P20 12 is enabled i e DP20 12 1 Note The output driver of pin P20 5 EA is implemented only in the ROM version In the OTP version pin P20 5 EA must accept the 12 V programming voltage and therefore cannot provide an output driver User s Manual 7 28 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports Alternate Functions of Port 20 The pins of Port 20 serve for various functions which include bus interface command lines and several system control lines Table 7 6 summarizes the alternate functions of Port 20 Table 7 6 Alternate Functions of Port 20 Port 20 Pin Alternate Function P20 0 RD Read command signal P20 1 WR Write command signal P20 4 ALE Address latch enable signal P20 5 EA External access control input P20 8 CLKOUT System Clock Output FOUT Programmable Frequency Output P20 12 RSTOUT Reset indication output Port 20 provides a set of general system control signals in particular in case of an external bus interface To ensure proper operation of these signals most of the Port 20 alternate functions are enabled after reset contrary to the other ports The general purpose IO functions are selected by the Port 20 enable bit P20EN SYSCON 5 The reset value of bit P2OEN depends on the reset configuration After an external reset EA 0 P20EN is a
345. hnologies Derivatives Capture Compare Unit CAPCOM2 Compare Mode 1 Compare mode 1 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 101p When a match between the content of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag CCxIR is set to 1 where connected and the corresponding output pin CCxIO alternate port output function is toggled For this purpose the state of the respective port output latch not the pin is read inverted and then written back to the output latch Compare mode 1 allows several compare events within a single timer period An overflow of the allocated timer has no effect on the output pin nor does it disable or enable further compare events In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 1 this port pin must be configured as output i e the corresponding direction control bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 1 the port latch is toggled upon each compare event see Figure 16 7 If compare mode 1 is programmed for one of the registers CC16 CC19 the double register compare mode becomes enabled for this register if the corresponding bank 2 register is pr
346. ication specific peripherals can be connected to the standard controller core The XBUS is an internal representation of the external bus interface and is operated in the same way For each peripheral on the XBUS X Peripheral there is a separate address window controlled by a register pair XBCONX XADRSx similar to registers BUSCONx and ADDRSELx Because an interface to a peripheral is represented in many cases by just a few registers the XADRSx registers partly select smaller address windows than the standard ADDRSEL registers As the XBCONx XADRSx register pairs control integrated peripherals rather than externally connected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals may be bytewide or wordwide Because the on chip connection can be implemented very efficiently for performance reasons X Peripherals are implemented only with a separate address bus in demultiplexed bus mode Interrupt nodes are provided for X Peripherals to be integrated Note If you plan to develop a peripheral of your own to be integrated into a C164CM device to create a customer specific version please ask for the specification of the XBUS interface and for further support User s Manual 9 24 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 6 1 Accessing the On chip XBUS Peripheral
347. ices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered User s Manual V1 0 Feb 2002 C164CM SM 16 Bit Single Chip Microcontroller Microcontrollers eo Infineon technologies Never stop thinking C164CM Revision History V1 0 2002 02 Previous Version Page Subjects major changes since last revision Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com pz _ C Infineon C164CM C164SM technologies Derivatives Table of Contents Page Introduction m m 1 1 Members of the 16 bit Microcontroller Family 1 3 1 2 Summary of Basic Features 0 0 0 0 ee eee 1 5 1 3 ADBIBUIBEIOPIS siias dt Re Re et RAS oe e dod Rod dabo eol REDI OE SS 1 8 2 Architectural Overview 0 00 cece ees 2 1 2 1 Big Performance in a Small Package nnaa anaana 2 2 2 2 Basic CPU Concepts and Optimizations ss 2 3 2 2 1
348. ides an immediate overview of the available registers and control status bits in a specific derivative C164CM C164SM Derivatives Capture Compare Unit CAPCOM6 Register Descriptions Table 17 7 summarizes the available registers The control registers are described in detail in the following sections of this chapter Data registers such as period or compare registers are excluded from the detailed description Please note that the timer registers T12 T13 are not directly accessible Table 17 7 CAPCOM6 Register Summary Name Description Address Read T12P E Timer T12 period register F0304 184 Sh L T120F E Timer T12 offset register F0344 1Ay Sh L T13P E Timer T13 period register F032 4 19 Sh L CMP13 Compare register for compare channel FE36y 1B Sh L CC60 Compare register for capture compare channel 0 FE30 184 Reg CC61 Compare register for capture compare channel 1 FE32 19 Reg CC62 Compare register for capture compare channel 2 FE344 1Ap Reg CTCON Compare timer control register FF30 984 Reg TRCON Trap enable register FF344 9A4 Reg CC6MCON CAPCOM6 mode control register FF324 99 Reg CC6MSEL E CAPCOM6 mode select register F036 1By Reg CC6MIC CAPCOM6 interrupt control register FF36y 9By Reg Note When reading these registers either the register itself or its shadow latch is accessed see description below This is indicated
349. ies Derivatives Instruction Set Summary 24 Instruction Set Summary This chapter briefly summarizes the C164CM s instructions by instruction classes This provides a basic description of the C164CM s instruction set the power and versatility of the instructions and their general usage Detailed descriptions of each individual instruction including its operand data type condition flag settings addressing modes length number of bytes and object code format are provided in the Instruction Set Manual for the C166 Family This manual also provides tables listing the instructions according to various criteria to facilitate quick information access Summary of Instruction Classes Grouping the various instructions into classes assists in identifying similar instructions such as SHR ROR and variations of instructions such as ADD ADDB This provides an easy access to the possibilities and power of the instructions of the C164CM Note The used mnemonics refer to the detailed description Arithmetic Instructions e Addition of two words or bytes ADD ADDB Addition with Carry of two words or bytes ADDC ADDCB e Subtraction of two words or bytes SUB SUBB e Subtraction with Carry of two words or bytes SUBC SUBCB 16x16 bit signed or unsigned multiplication MUL MULU 16 16 bit signed or unsigned division DIV DIVU e 32 16 bit signed or unsigned division DIVL DIVLU e 1 s complement of a word or byte CPL CPLB e 2 s c
350. ies Derivatives Interrupt and Trap Functions 5 2 Operation of the PEC Channels The C164CM s Peripheral Event Controller PEC provides 8 PEC service channels which move a single byte or word between two locations in segment O data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request for example serial channels etc Each channel is controlled by a dedicated PEC Channel Counter Control register PECCx and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action performed by the respective PEC channel E M Reg SFR FECy 6z see Table 5 4 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INC BWT COUNT rw rw rw Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel s action see Table 5 5 BWT Byte Word Transfer Selection 0 Transfer a Word 1 Transfer a Byte INC Increment Control Modification of SRCPx or DSTPx 00 Pointers are not modified 01 Increment DSTPx by 1 or 2 BWT 10 Increment SRCPx by 1 or 2 BWT 11 Reserved Do not use this combination changed to 10 by hardware Table 5 4 PEC Control Register Addresses Register Address Reg Space Register Address Reg Space PECCO FECO 60 SFR PECC
351. ifies the word base address of the current register bank When writing a value to register CP with bits CP 11 CP 9 000 bits CP 11 CP 10 are set to 11 by hardware In all other cases all bits of the bit field cp receive the written value Note It is the user s responsibility to ensure that the physical GPR address specified via CP register plus short GPR address is always an internal RAM location If this condition is not met unexpected results may occur e Do not set CP below the IRAM start address i e 00 FA00 00 F600 00 F200 referring to an IRAM size of 1 2 3 KByte Do not set CP above O0 FDFE e Be careful using the upper GPRs with CP above 00 FDE0 The CP register can be updated via any instruction capable of modifying an SFR Note Due to the internal instruction pipeline a new CP value is not yet usable for GPR adaress calculations of the instruction immediately following the instruction which updated the CP register The Switch Context instruction SCXT allows saving the content of register CP on the stack and updating it with a new value in only one machine cycle User s Manual 4 25 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Internal RAM Context Pointer Figure 4 7 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations Th
352. iggered by one of two different signals The trigger signal is selected the same way as the clock source for counter mode see Table 10 8 i e a transition of the auxiliary timer s input or the output toggle latch T3OTL may trigger the reload Note When programmed for reload mode the respective auxiliary timer T2 or T4 stops independently of its run flag T2R or TAR Source Edge Select Reload Register Tx Interrupt p Request Law TxIR Interrupt Request TSIR Input Clock Core Timer T3 Up Down x 2 4 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL MCB02035b Figure 10 12 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal the interrupt request flag T3IR will also be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 User s Manual 10 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit The reload mode triggered by T3OTL can be used in a number of different configurations The following functions can be performed depending on the selected active transition If both a positive a
353. ignal in this case the PLL will run on its base frequency of 2 5 MHz The PLL starts synchronizing with the external clock signal as soon as it is available Within about 1 ms after stable oscillations of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F x fosc meaning that the PLL locks to the external clock When PLL operation is selected the CPU clock is a selectable multiple of the oscillator frequency i e the input frequency Table 6 1 lists the possible selections User s Manual 6 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Clock Generation Table 6 1 C164CM Clock Generation Modes RPOH 7 5 CPU Frequency External Clock Notes POH 7 5 fcpu fosc xF Input Range 1 1 fosc x 4 2 5 to 6 25 MHz Default configuration 1 110 fosc x3 3 33 to 8 88 MHz 10 1 fosc x2 5 to 12 5 MHz 100 fosc x5 2 to 5 MHz 011 fosc X 1 1 to 25 MHz Direct drive 010 fosc x 1 5 6 66 to 16 6 MHz 0 0 1 fosc 2 2 to 50 MHz CPU clock via prescaler 000 fosc x 2 5 4 to 10 MHz 1 The external clock input range refers to a CPU clock range of 10 25 MHz The maximum frequency depends on the duty cycle of the external clock signal In emulation mode pin P0 15 POH 7 is inverted i e the configuration 111 would select direct drive in emulation mode The PLL constantly syn
354. ilable for general purpose IO When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data is the 16 bit intrasegment address While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user become active C164CM C164SM Derivatives Parallel Ports Alternate Function a b c P1H 7 A15 CC2710 P1H 6 A14 CC26lO P1H 5 A13 CC2510 P1H P1H 4 A12 CC2410 P1H 3 A11 CC3110 EXSIN T7IN P1H 2 A10 CC6POS2 CC30IO EX2IN P1H 1 AQ CC6POS1 CC29IO EX1IN Port 1 P1H 0 A8 CC6POSO CC28IO EXOIN P1L 7 A7 CTRAP P1L 6 A6 COUT63 P1L 5 A5 COUT62 P1L 4 A4 CC62 PIL P1L 3 A3 COUT61 P1L 2 A2 CC61 P1L 1 A1 COUT60 P1L 0 AO CC60 General Purpose 8 16 Bit CAPCOM Fast Ext Interrupt Input Output Demux Bus Inputs Outputs or Timer Input MCA05128 Figure 7 6 PORT1 IO and Alternate Functions The figures below show the structure of PORT1 pins The upper 4 pins of PORT1 combine internal bus data and alternate data output before the port latch input User s Manual 7 18 V1 0 2002 02 ol
355. ile a conversion is running will abort this conversion and start a new conversion with the parameters specified in ADCON Note Abort and restart are triggered by bit ADST changing from 0 to 1 thus ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection field ADCH may be changed ADM will be evaluated after the current conversion ADCH will be evaluated after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Fixed Channel Conversion Modes These modes are selected by programming the mode selection bitfield ADM in register ADCON to O0g single conversion or to 01 continuous conversion After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new conversion of the channel specified in ADCH ADCIR will be set after each completed conversion When bit ADST is reset by software while a conversion is in progress the converter will complete the current conversion and then stop and reset bit ADBSY User s Manual 18 6 V1 0 2002 02 o Infineon C164CM C164SM tech
356. in Table 19 2 Table 19 2 CAN Interface Signals CAN Signal Port Pin Function CAN1 RxD Controlled via Receive data from the physical layer of the CAN bus 1 CAN1_TxD CIPCIR IPC Transmit data to the physical layer of the CAN bus 1 A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level Connection to an External Transceiver The CAN module of the C164CM can be connected to an external CAN bus via a CAN transceiver Note It is also possible to connect several CAN modules directly on board without using CAN transceivers CAN_RxD CAN Transceiver a CAN 1 CAN_TxD Physical S Layer MCS04401 Figure 19 12 Connection to a Single CAN Bus User s Manual 19 36 V1 0 2002 02 Infineon technologies Port Control The receive data line and the transmit data line of the CAN module are alternate port functions To enable proper reception please ensure that the respective port pin for the receive line is switched to input The respective port driver for the transmit will automatically be switched ON C164CM C164SM Derivatives On Chip CAN Interface This provides a standard pin configuration without additional software control It also works in emulation mode where the port direction registers cannot be controlled The receive and transmit line of the CAN module may be assigned
357. ing the internal ROM area to segment 1 Due to instruction pipelining any new ROM mapping will at the earliest become valid for the second instruction after the instruction which has changed the ROM mapping To enable accesses to the ROM area after mapping a branch to the newly selected ROM area JMPS and reloading of all data page pointers is required This also applies to re mapping the internal ROM area to segment O Enabling the internal code memory after reset When enabling the internal code memory after having booted the system from external memory note that the C164CM will then access the internal memory using the current segment offset rather than accessing external memory Disabling the internal code memory after reset When disabling the internal code memory after having booted the system from there note that the C164CM will not access external memory before a jump to segment O in this case is executed General Rules When mapping the code memory no instruction or data accesses should be made to the internal memory otherwise unpredictable results may occur To avoid these problems the instructions which configure the internal code memory should be executed from external memory or from the on chip RAM Whenever the internal code memory is disabled enabled or remapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal and or external memory User s Manual 22 18 V1 0 2002 02 _
358. ing to reset configuration BUSCONO OXX0O set according to reset configuration RPOH XXy reset levels of POH ONES FFFF fixed value User s Manual 20 5 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives System Reset The C164CM s Pins after Reset After the reset sequence the various groups of pins of the C164CM are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORTO so either external accesses can take place or the external control signals will be inactive The general purpose IO pins remain in input mode high impedance until reprogrammed via software see Figure 20 3 The RSTOUT pin remains active low until the end of the initialization routine see description Internal Reset Condition 9 Initialization RSTIN Internal Reset Condition Initialization When the internal reset condition is extended by RSTIN the activation of the output signals is delayed until the end of the internal reset condition 1 Current bus cycle is completed or aborted 2 Switches asinchronously with RSTIN sinchronously upon software or watchdog reset 3 The reset condition ends here The C 167CR starts program execution 4 Activation of the IO pins is controlled by software Execution of
359. injection mode After the completion of the current conversion if any is in progress the converter will start inject the conversion of the specified channel When the conversion of this channel is complete the result will be placed into the alternate result register ADDAT2 A Channel Injection Complete Interrupt request will also be generated which uses the interrupt request flag ADEIR the Wait for ADDAT Read Mode is required for this reason Note If the temporary data register used in Wait for ADDAT Read Mode is full the next conversion either standard or injected will be suspended The temporary register can hold data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion User s Manual 18 10 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives Analog Digital Converter X x 1 x 2 i x 3 ji Conversion of Channel Wait until NENNEN EE Y ADDAT2 is Write ADDAT 4 x 1 EX x1 read 8x2 x 3 ADDAT Full Goa al Ex J L Read ADDAT dx Hx x 1 X 2 X 3 Injected Conversion Channel Injection Ooo o Write ADDAT2 ofChanneky Request is is ADDAT2 Full EE Int Request ADEINT Read ADDAT2 iz y Temp Latch Ss Full Ex x x 2 i x 3 amp Conversion of Channel Write ADDAT ADDAT Full Read ADDAT Temp Latch Full Channel Injection Request Wait until ADDAT 2 is Write ADDAT2 ADDAT2 Full read Int Request AD
360. input frequency is too low or for intermittent failure only A broken crystal cannot be detected by software OWD interrupt server as no SDD clock is available in such a case User s Manual 6 9 V1 0 2002 02 _ Infineon technologies 6 4 C164CM C164SM Derivatives Clock Drivers Clock Generation The operating clock signal fcpy is distributed to the controller hardware via several clock drivers which are disabled under certain circumstances The Real Time Clock RTC is clocked via a separate clock driver which delivers the prescaled oscillator clock contrary to the other clock drivers Table 6 2 summarizes the different clock drivers and their functions especially in power reduction modes Table 6 2 Clock Drivers Description Clock Driver Clock Active Idle Power Connected Circuitry Signal Mode Mode Down and Sleep Mode CCD cPU ON Off Off CPU CPU internal memory modules Clock Driver IRAM ROM OTP Flash ICD cPU ON ON Off ASCO WDT SSC Interface interrupt detection Clock Driver circuitry PCD cPU Controlvia Controlvia Off X Peripherals timers Peripheral PCDDIS PCDDIS etc except those driven Clock Driver by ICD interrupt controller ports RCD nTC ON ON Controlvia Real Time Clock RTC PDCON Clock Driver SLEEP CON Note Disabling PCD by setting bit PCDDIS stops the clock signal for all connected modules Ensure that all these modules are in a saf
361. ion POL 4 or RD e upon a hardware reset not configuring BSL mode After the non BSL reset the C164CM will start executing out of user memory as externally configured via PORTO or RD ALE depending on EA User s Manual 15 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Bootstrap Loader 15 4 Choosing the Baudrate for the BSL Calculation of the serial baudrate for ASCO from the length of the first zero byte received allows the bootstrap loader of the C164CM to operate with a wide range of baudrates However the upper and lower limits must be maintained in order to ensure proper data transfer B a u C164CM 32x SOBRL 1 The C164CM uses timer T3 to measure the length of the initial zero byte The quantization uncertainty of this measurement implies the first deviation from the real baudrate The next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association T3 18 44 9 cru SOBRL 36 8 Buost For a correct data transfer from the host to the C164CM the maximum deviation between the internal initialized baudrate for ASCO and the real baudrate of the host should be below 2 5 The deviation Fp in percent between host baudrate and C164CM baudrate can be calculated via the formula below Bcontr E Buost Contr x100 Fgx2 596 Note Function Fg does not consider the tolerances of oscillators and ot
362. ion Jump Width SJW defines the maximum number of time quanta by which a bit time may be shortened or lengthened during one Resynchronization The current bit time is adjusted by to jw SUW 1 x ty Note SJW is the programmed numerical value from the respective field of the Bit Timing Register User s Manual 19 12 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Calculation of the Bit Time Programming the bit time according to the CAN Specification depends on the desired baudrate the XCLK frequency and the external physical delay times of the bus driver the bus line and the input comparator These delay times are summarized in the Propagation Time Segment fp op where tprop S two times the maximum of the sum of physical bus delay the input comparator delay and the output driver delay rounded up to the nearest multiple of ty To fulfill the requirements of the CAN specification the following conditions must be met reo 92 22x tq Information Processing Time gt ITSeg B ISJW 2 ITSeg 23x fa t t gt TSeg1 ISJW t Prop Note In order to achieve correct operation according to the CAN protocol the total bit time should be at least 8 t i e TSEG1 TSEG2 gt 5 Thus to operate with a baudrate of 1 MBit s the XCLK frequency must be at least 8 16 MHz depending on the prescaler control bit CPS in register CSR The maximum tolerance df for XCLK d
363. ion starts only if SSCEN 1 Depending on the selected clock phase a clock pulse will also be generated on the SCLK line With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses have occurred via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and in all slaves the contents of the shift register are copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first bit MSB or LSB of the transfer data at pin MRST when the contents of the transmit buffer are copied into the slave s shift register It will not wait for the next clock from the baudrate generator as the master does The reason for this is that depending on the selected clock phase the first clock edge generated by the master may be used already to clock in the first data bit So the slave s first data bit must already be valid at this time Note
364. ion to ensure that the controller executes the desired operations Memory Areas are partitions of the address space assigned to different kinds of memory if provided at all These memory areas are the Internal RAM SFR area the internal ROM Flash OTP if available the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations which belong to different memory areas is no problem However when executing code the different memory areas must be switched explicitly via branch instructions Sequential boundary crossing is not supported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment O Segments are contiguous blocks of 64 KBytes each They are referenced via the Code Segment Pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do this In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment to prevent the prefetcher from trying to leave the current segment Data Pages are contiguous blocks of 16 KBytes each They are referenced via the data page pointers DPP3 DPPO and via an explicit data page nu
365. iplexed Bus 01 8 bit Multiplexed Bus 10 16 bit Demultiplexed Bus 11 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset EWENx Early Write Enable 0 Normal WR signal _ 1s Early write The WR signal is deactivated and write data is tristated one TCL earlier ALECTLx ALE Lengthening Control 0 Normal ALE signal 14 Lengthened ALE signal BUSACTXx Bus Active Control 0 External bus disabled a External bus enabled within respective address window ADDRSEL BSWCx BUSCON Switch Control 0 Address windows are switched immediately di A tristate waitstate is inserted if the next bus cycle accesses a window different from the one controlled by this BUSCON register 1 A BUSCON switch waitstate is enabled by bit BUSCONx BSWCx of the address window that is left User s Manual 9 18 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives External Bus Interface ADDRSEL1 Address Select Register 1 SFR FE18 0C Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL2 Address Select Register 2 SFR FE1A 0D Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL3 Address Select Register 3 SFR FE1C
366. is detected if bit BCEM 1 or in case of an illegal input pattern see note 1 When idle state is entered the BCERR flag is always set V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 In block commutation mode CAPCOM channel 0 is automatically configured for capture mode Any signal transition at inputs CC6POS2 0 generates a capture pulse for CAPCOM channel 0 and sets the interrupt request flag CCOR A rising edge at output pin CC60 does not generate an interrupt request in block commutation mode The values provide a measurement of the rotation speed of the connected drive When evaluating the values captured from the free running timer T12 the timer must not be stopped as this would disturb the operation of block commutation mode Note Modulation of the active phase via T12 is not supported PWM via T13 is possible on COUT6x The block commutation input signals are available for the full function module only User s Manual 17 17 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM6 17 7 Trap Function The trap function switches selectable output lines of the CAPCOM6 to predefined levels simultaneously The trap function is triggered by an external signal connected to input CTRAP This feature provides a very efficient means of protecting external circuitry such as power bridges for inverters or mo
367. is is done via the EXTension instructions EXTR EXTP R EXTS R Byte write operations to wordwide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can access only the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits Reserved Bits Some of the bits which are contained in the C164CM s SFRs are marked as Reserved User software should never write 1 s to reserved bits These bits are currently not implemented and may be used in future products to invoke new functions In that case the active state for those new functions will be 1 and the inactive state will be O Therefore writing only O s to reserved locations allows portability of the current software to future devices After read accesses reserved bits should be ignored or masked out User s Manual 2 13 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with different functionality an Asynchronous Synchronous Serial Channel ASCO
368. is sampled low at the end of an external reset EA 0 e when pin RD is sampled low at the end of an internal reset EA 1 In this case the built in bootstrap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM no part of the standard mask ROM OTP or Flash memory area is required for this The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 or RD for systems that use this feature upon every hardware reset You may want to use a switchable solution via jumper or an external signal for systems that only temporarily use the bootstrap loader RD Ext 2 j 4 Signal ae Start e y Boot POL 4 Proposal for Internal Reset Proposal for Internal Reset Proposal for Combined Circuitry EA 1 EA 0 MCA04466 Figure 15 2 Hardware Provisions to Activate the BSL The ASCO receiver is only enabled after the identification byte has been transmitted A half duplex connection to the host is therefore sufficient to feed the BSL Note The proper reset configuration for BSL mode requires more pins to be driven besides POL 4 or RD For an external reset EA 0 bitfield SMOD must be configured as 1011p see Section 20 4 1 For an internal reset EA 1 pin ALE must be driven to a defined level e g ALE 0 for the standard bootstrap loader see Section 20 4 2 Use
369. isabled In order to enable interrupt requests the nodes must be assigned to their respective interrupt priority levels and must be enabled The vector locations must receive pointers to the respective exception handlers The interrupt system must globally be enabled by setting bit IEN in register PSW To avoid such problems as the corruption of internal memory locations caused by stack operations using an uninitialized stack pointer care must be taken not to enable the interrupt system before the initialization is complete Watchdog Timer After reset the watchdog timer is active and counting its default period If the watchdog timer is to remain active the desired period should be programmed by selecting the appropriate prescaler value and reload value Otherwise the watchdog timer must be disabled before EINIT Ports Generally all ports of the C164CM are switched to input after reset Some pins may be automatically controlled such as bus interface pins for an external start TxD in Boot mode etc Pins to be used for general purpose IO must be initialized via software The required mode input output open drain push pull etc depends on the intended function for a given pin Peripherals After reset the C164CM s on chip peripheral modules enter a defined default state see respective peripheral description in which they are disabled from operation In order to use a certain peripheral it must be initialized according to its intended
370. istics of the output driver via the following mechanisms Open Drain Mode The upper push transistor is always disabled Only 0 is driven actively an external pull up is required Driver Characteristic The driver strength delivered current can be selected Edge Characteristic The shape of an output signal can be selected Open Drain Mode In the C164CM certain ports provide Open Drain Control which allows switching the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line to either a high or a low level In open drain mode the upper transistor is always switched off and the output driver can actively drive the line to a low level only When writing a 1 to the port latch the lower transistor is switched off and the output enters a high impedance state The high level must then be provided by an external pull up device With this feature it is possible to connect several port pins together to a Wired AND configuration saving external glue logic and or additional software overhead for enabling disabling output signals This feature is controlled through the respective Open Drain Control Registers ODPx provided for each port which has this feature implemented These registers allow the individual bit wise selection of the open drain mode for each port line If the respective
371. it Do not write to SSCTE SSC Transmit Error Flag 1 Transfer starts with the slave s transmit buffer not being updated SSCRE SSC Receive Error Flag 1 Reception completed before the receive buffer was read SSCPE SSC Phase Error Flag ab Received data changes around sampling clock edge SSCBE SSC Baudrate Error Flag 1 More than factor 2 or less than factor 0 5 between Slave s actual and expected baudrate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 1 Transmission and reception enabled Access to status flags and Master Slave M S control Note The target of an access to SSCCON control bits or flags is determined by the state of SSCEN prior to the access for instance writing C0574 to SSCCON in programming mode SSCEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 7 When writing to SSCCON make sure that reserved locations receive zeros User s Manual 12 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic see block diagram Transmission and reception of serial data is synchronized and
372. it field is updated with the priority level of the request being serviced The PSW is saved on the system stack before the request is serviced The CPU level determines the minimum interrupt priority level which will be serviced Any request on the same or a lower level will not be acknowledged The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority i e 15 so no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed Note The TRAP instruction does not change the CPU level so software invoked trap service routines may be interrupted by higher requests Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU When IEN is cleared no new interrupt requests are accepted by the CPU However requests already in the pipeline at that time will be processed When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bits in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit User s Manual 5 10 V1 0 2002 02 Infineon C164CM C164SM technolog
373. ithin the first four data pages 3 0 The pointer locations for inactive PEC channels may be used for general data storage Only the required pointers occupy RAM locations Note If word data transfer is selected for a specific PEC channel i e BWT 0 the respective source and destination pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used User s Manual 5 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 3 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so their requests are disregarded and not serviced Enabling and disabling interrupt requests may be done via three mechanisms e Control Bits e Priority Level e ATOMIC and EXTended Instructions Control Bits allow switching of each individual source ON or OFF so that it may generate a request or not The control bits xxIE are located in the respective interrupt control registers All interrupt requests may be enabled or disabled generally via bit IEN in register PSW This control bit is the main switch which selects if requests from any source are accepted or not For a specific request to be arbitrated the respective source
374. ity over every other CPU activity If several hardware trap conditions are detected within the same instruction cycle the highest priority trap is serviced see Table 5 2 User s Manual 5 31 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level level 15 disabling all interrupts The CSP is set to code segment zero if segmentation is enabled A trap service routine must be terminated with the RETI instruction The eight hardware trap functions of the C164CM are divided into two classes Class A traps are External Non Maskable Interrupt NMI e Stack Overflow e Stack Underflow trap These traps share the same trap priority but have individual vector addresses Class B traps are Undefined Opcode Protection Fault e Illegal Word Operand Access e Illegal Instruction Access llegal External Bus Access Trap These traps share the same trap priority and the same vector address The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 The reset functions hardware software watchdog
375. jection Target Instruction 1 Machine Cycle y FETCH Tuo IrangET TARGET Da2 LrARGET 1 I ranGET 2 DECODE Cache Jmp insect IARGET Cache Jmp IARGET L RGET 1 EXECUTE L Cache Jmp Inject I Cache Jmp ager WRITEBACK ids I Cache Jmp A I Cache Jmp 1st Loop Iteration Repeated Loop Iteration MCT04329 Figure 4 4 Cache Jump Instruction Pipelining User s Manual 4 5 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU 4 2 Particular Pipeline Effects Because up to four different instructions are processed simultaneously additional hardware has been used in the C164CM to consider all causal dependencies which may exist on instructions in different pipeline stages This functionality is provided without a loss of performance This extra hardware for forwarding operand read and write values resolves most of the possible conflicts such as multiple usage of buses in a time optimized way thus in most cases the pipeline operates without being noticeable to the user However there are some very rare circumstances in which the C164CM as a pipelined machine requires attention by the programmer In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance Context Pointer Updating An instruction which calculates a physical GPR operand addr
376. l Flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT The following behavior differences must be observed when using the bidirectional reset feature in an application Bit BDRSTEN in register SYSCON cannot be changed after EINIT Bit BDRSTEN is cleared after a reset The reset indication flags always indicate a long hardware reset The PORTO configuration is treated as on a hardware reset Especially the bootstrap loader may be activated when POL 4 or RD is low Pin RSTIN may only be connected to external reset devices with open drain output driver A short hardware reset is extended to the duration of the internal reset sequence User s Manual 20 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset 20 2 Status After Reset Most units of the C164CM enter a well defined default status after a reset is completed This ensures repeatable start conditions and avoids spurious activities after reset Watchdog Timer Operation after Reset The watchdog timer starts running after the internal reset is complete It will be clocked with the internal system clock divided by 2 fcpy 2 and its default reload value is 00 Thus a watchdog timer overflow will occur 131 072 CPU clock cycles 2 x 216 after completion of the internal reset unless it is disabled serviced or reprogrammed in the meantime If the system reset was c
377. l Interface 12 7 SSC Interrupt Control Three bit addressable interrupt control registers are provided for serial channel SSC Register SSCTIC controls the transmit interrupt SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector The cause of an error interrupt request receive phase baudrate transmit error can be identified by the error status flags in control register SSCCON Note In contrast to the error interrupt request flag SSCEIR the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software SSCTIC SSC Transmit Intr Ctrl Reg SFR FF72 B9 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 peus ILVL GLVL z nw nw nw nw SSCRIC SSC Receive Intr Ctrl Reg SFR FF74 BAg Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 det ILVL GLVL rw rw rw rw SSCEIC SSC Error Intr Ctrl Reg SFR FF76 BByj Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P EN ILVL GLVL Ww r
378. l accuracy of the RTC can be further increased via software for specific applications that demand a high time accuracy The key to the improved accuracy is knowledge of the exact oscillator frequency The relation of this frequency to the expected ideal frequency is a measure of the RTC s deviation The number of cycles N after which this deviation causes an error of 1 cycle can be easily computed So the only action is to correct the count by 1 after each series of N cycles This correction may be applied to the RTC register as well as to T14 Also the correction may be made cyclically for instance within T14 s interrupt service routine or by evaluating a formula when the RTC registers are read for this the respective last RTC value must be available somewhere Note For the majority of applications however the standard accuracy provided by the RTC s structure will be more than sufficient User s Manual 14 4 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Bootstrap Loader 15 Bootstrap Loader The built in bootstrap loader of the C164CM provides a mechanism to load the startup program which is executed after reset via the serial interface In this case no external memory or an internal ROM OTP Flash is required for the initialization code The bootstrap loader moves code data into the internal RAM but it is also possible to transfer data via the serial interface into an external RAM usin
379. l memory access in the lower half of segment 0 or the internal ROM may be disabled completely Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Note Accesses to the internal ROM area on ROMless devices will produce unpredictable results Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address followed by the high byte at the next odd byte address Double words code only are stored in ascending memory locations as two subsequent words Single bits are always stored in the specified bit position at a word address Bit position O is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a portion of the Special Function Registers a portion of the internal RAM and for the General Purpose Registers XXXX6 H XXXX5 H XXXX4 H XXXX3 H XXXX2 H XXXX1 H Word Low Byte 3x0 H MCD01996 Figure 3 2 Storage of Words Bytes and Bits in a Byte Organized Memory Note Byte units forming a single word or a double word must always be stored within the same physical internal external ROM RAM and organizational page segment memory area User s Manual 3 2 V1 0 2002 02 _ Infineon C164CM C164SM t
380. lar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register TFR Unless another higher prioritized trap service is in progress a hardware trap will interrupt any current program execution In turn a hardware trap service can normally not be interrupted by a standard or PEC interrupt Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number User s Manual 2 8 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 3 On Chip System Resources The C164CM controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resources results in the high performance of the members of this controller family Peripheral Event Controller PEC and Interrupt Control The Peripheral Event Controller enables response to an interrupt request with a single data transfer word or byte which consumes only one instruction cycle and does not require saving and restoring the machine status Each interrupt source is prioritized for every machine cycle in the interrupt control block If PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PSW register is tested to determine whe
381. le mode all port pins configured as general purpose output pins will output the last data value written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off Note All pin drivers can be switched off by selecting the general port disable function prior to entering Power Down mode When the supply voltage is lowered in Power Down mode the high voltage of output pins will decrease accordingly User s Manual 21 9 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Power Management Table 21 1 State of C164CM Output Pins in Idle and Power Down Modes C164CM External Bus Enabled No External Bus Output Pin s idie Mode Sleep and Idle Mode Sleep and Power Down Power Down CLKOUT Active toggling High Active toggling High FOUT Active toggling Hold high low Active toggling Hold high low ALE Low Low RD WR High High POL Floating Port Latch Data POH A10 A8 Float Port Latch Data PORT1 Last Address Port Latch Data Port Latch Data RSTOUT High if EINIT was executed before entering Idle or Power Down mode Low otherwise Other Port Port Latch Data Alternate Function Output Pins 1 For multiplexed buses with 8 bit data bus 2 User s Manual For demultiplexed b
382. lect Register 4 0000 ADEIC b FF9A CD A D Converter Overrun Error Interrupt 0000 Control Register BUSCONO b FFOC 86 Bus Configuration Register 0 0000 BUSCON1 b FF14 8A Bus Configuration Register 1 0000 BUSCON2 b FF16 8By Bus Configuration Register 2 0000 BUSCON3 b FF18 8C Bus Configuration Register 3 0000 BUSCON4 b FF1A 8D Bus Configuration Register 4 0000 C1BTR EFO4 X CAN1 Bit Timing Register UUUU C1CSR EFOO X CAN1 Control Status Register XX014 C1GMS EFO6 X CAN1 Global Mask Short UFUU C1LARn EFn4 X CAN Lower Arbitration Register msg n UUUU C1LGML EFOA X CAN Lower Global Mask Long UUUUJ C1LMLM EFOE X CAN Lower Mask of Last Message UUUUJ C1MCFGn EFn6 X CAN Message Configuration Register UU msg n User s Manual 23 4 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Register Set Table 23 3 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Address Addr Value CiMCRn EFnO X CAN Message Control Register msg n UUUU C1PCIR EFO2 X CAN 1 Port Control Interrupt Register XXXXy C1UARn EFn2 X CAN Upper Arbitration Register msg n UUUU C1UGML EFO8 X CAN Upper Global Mask Long UUUU C1UMLM EFOC X CAN Upper Mask of Last Message UUUU CC
383. line Alternate Latch Data Input is inverted and then written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occurs the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The direction of the pin should be set to output by the user otherwise the pin will be in the high impedance state and will not reflect the state of the output latch As can be seen from the port structure below the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs but is toggled instead User s Manual 7 25 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports If the user wants to write to the port pin at the same time that a compare trigger tries to clock the output latch the write operation of the user software has priority Each time a CPU write access to the port output latch occurs the input multiplexer
384. ll enter Power Down mode after the PWRDN instruction is completed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontroller will enter the NMI trap routine which can save the internal state into RAM After the internal state has been saved the trap routine may then execute the PWRDN instruction If the NMI pin is still low at this time Power Down mode will be entered otherwise program execution continues The initialization routine executed upon reset can check the reset identification flags in register WDTCON to determine whether the controller was initially switched on or whether it was properly restarted from Power Down mode User s Manual 21 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management If the supply voltage continues to be applied the realtime clock RTC can be kept running in Power Down mode to maintain a valid system time This enables a system to determine the current time and the duration of the period in Power Down mode by comparing the current time with a timestamp stored when Power Down mode was entered The supply current in this case remains well below 1 mA During power down the voltage at the Vpp pins can be lowered to 2 7 V while the RTC and its selected oscillator continue running and the contents of the internal RAM will be preserved With the RTC and os
385. lling of an absolutely addressed subroutine within any code segment Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack Unconditional branching to the interrupt or trap vector jump table in code segment 0 Return Instructions Returning from a subroutine within the current code segment Returning from a subroutine within any code segment Returning from a subroutine within the current code segment plus an additional popping of a selectable register from the system stack Returning from an interrupt service routine User s Manual 24 3 Instruction Set Summary JMPA JMPI JMPR JMPS JB JNB JBC JNBS CALLA CALLI CALLR CALLS PCALL TRAP RET RETS RETP RETI V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Instruction Set Summary System Control Instructions Resetting the C164CM via software SRST Entering the Idle mode IDLE Entering the Power Down mode PWRDN e Servicing the Watchdog Timer SRVWDT e Disabling the Watchdog Timer DISWDT e Signifying the end of the initialization routine pulls pin RSTOUT high and disables the effect of any later execution of a DISWDT instruction EINIT Miscellaneous Null operation which requires two bytes of storage and the minimum time for execution NOP Definition of an inseparable instruction sequen
386. lock RTC is fed by a separate clock driver so it can be kept running even in Power Down mode while all the other circuitry is disconnected from the clock The registers of the generic peripherals can be accessed even while the respective module is disabled as long as PCD is running The registers of peripherals connected to ICD can be accessed even in this case of course The registers of X peripherals cannot be accessed while the respective module is disabled by any means While a peripheral is disabled its output pins remain in the state they had at the time of disabling This flexible peripheral management is controlled by software via register SYSCONG in which each control bit is associated with an on chip peripheral module User s Manual 21 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management SYSCONS3 System Control Reg 3 ESFR F1D4 EA Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCD _ leami _ _ _ _ CC6 CC2 _ _ _ GPT ssc anc DIS DIS DIS DIS DIS DIS DIS DIS rw rw rw rw rw rw rw rw Bit Function associated peripheral module ADCDIS Analog Digital Converter ASCODIS USART ASCO SSCDIS Synchronous Serial Channel SSC GPTDIS General Purpose Timer Blocks CC2DIS CAPCOM2 Unit CC6DIS CAPCOMSG Unit CAN1DIS On chip CAN Module 1 PCDDIS Peripheral Clock Driver also
387. luding the corner values The duty cycle directly corresponds to the programmed compare value The indicated output signals can be output on the respective pin CC6x or COUT6x or both The pin allocation is controlled via bitfields CMSELx in register CC6MSEL Register CC6MCON selects the passive level for enabled outputs The example above uses active high signals the passive level is low the associated select bit is 0 User s Manual 17 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 In Figure 17 5 a non zero offset value is used In this case the compare value is not compared with the timer contents directly but rather with timer contents plus offset As a consequence the active edge of signal COUT6x is shifted against CC6x Figure 17 5 shows some of the output signals that can be generated compare value P a Standard output signal using T12 directly active high b Shifted output signal using T12 T12OF active high c Same signal as b but active low d 0 output signal compare value in CC6x gt T12P T120F e 100 output signal compare value in CC6x T120F Count Value T12 T120 A F T12P 27 T120F 2 Time gt T12 Start Q 0 d 100 e MCT02602 Figure 17 5 Operation wit
388. lue O0 after reset Converter Timing Example Assumptions cpu 25 MHz i e tcpy 40 ns ADCTC 00 ADSTC 00 Basic clock fac fcpu 4 6 25 MHz i e tac 160 ns sample time tg tpo X8 1280 ns Conversion time f 2 tg 40 tgc 2 tcpy 1280 6400 80 ns 7 76 us Note For the exact specification please refer to the data sheet of the selected derivative User s Manual 18 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter 18 3 A D Converter Interrupt Control At the end of each conversion the interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from register ADDAT and stores it into a table in the internal RAM for later evaluation for example The interrupt request flag ADEIR in register ADEIC will be set if either a conversion result overwrites a previous value in register ADDAT error interrupt in standard mode or if the result of an injected conversion has been stored into ADDAT2 end of injected conversion interrupt This interrupt request may be used to cause an interrupt to vector ADEINT or it may trigger a PEC data transfer ADCIC ADC Conversion In
389. lways cleared that means the IO functions are always disabled After an internal reset EA 1 P20EN is initialized with the inverted value latched from pin WR This means the IO functions of Port 20 can be enabled by pulling pin WR low at the end of reset Note The operating mode of Port 20 can be selected by software via bit PAOEN any time before the execution of EINIT User s Manual 7 29 V1 0 2002 02 _ e e Infineon technologies C164CM C164SM Derivatives Parallel Ports Alternate Function P20 12 Port 20 rave P20 5 P20 4 P20 1 P20 0 General Purpose Input Output RSTOUT CLKOUT FOUT a ALE WR RD During Operation b EA B St Mode P20 OFF ON Boot Start Reset Configuration MCA05116 Figure 7 13 Port 20 IO and Alternate Functions The port structure of the Port 20 pins depends on their alternate function see Figure 7 14 Note Enabling the CLKOUT function automatically enables the P20 8 output driver Setting bit DP20 8 1 is not required The CLKOUT function is automatically enabled in emulation mode User s Manual 7 30 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports Internal Bus i o o E zc Port Output Direction Latch Latch e AltDir AItEN AltDataOut Clock o Input AltDataln Latch MCBO05117 P20 12 P2
390. mber for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register which is used for the current access is selected via the two upper bits of the 16 bit data address Therefore subsequent 16 bit data addresses which cross the 16 KByte data page boundaries will use different data page pointers while the physical locations need not be subsequent within memory User s Manual 3 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization 3 5 Protection of the On Chip Mask ROM The on chip mask ROM of the C164CM can be protected against read accesses of both code and data ROM protection is established during the production process of the device a ROM mask can be ordered with a ROM protection or without it No software control is possible i e the ROM protection cannot be disabled or enabled by software When a device has been produced with ROM protection active the ROM contents are protected against unauthorized access by the following measures No data read accesses to the internal ROM are permitted by any instruction which is executed from any location outside the on chip mask ROM including IRAM XRAM and external memory A program cannot read any data out of the protected ROM from outside The read data will be replaced by the default value 009B for any read access to any location No codes fetches from the inte
391. me the request flag is cleared or shortly thereafter the request flag should be cleared together with the corresponding enable bit The enable bit can then be set again This avoids undetected requests caused by pulses at the interrupt node being too short ISNC Interrupt Sub Node Ctrl Reg ESFR F1DEJEF Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 z a s PLL PLL RTC RTC IE IR IE IR z x z rw wh rw wh Bit Function xxIR Interrupt Request Flag for Source xx 0 No request from source xx pending 1 Source xx has raised an interrupt request xxlE Interrupt Enable Control Bit for Source xx 0 Source xx interrupt request is disabled 1 Source xx interrupt request is enabled Table 5 7 Sub node Control Bit Allocation Bit Position Interrupt Source Associated Node 15 4 Reserved Reserved 312 PLL OWD XP3IC 110 RTC XP3IC Note In order to ensure compatibility with other derivative devices application software should never set reserved bits within register ISNC User s Manual 5 24 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 8 External Interrupts Although the C164CM has no dedicated INTR input pins it supports many possibilities to react to external asynchronous events It does this by using a number
392. message object no yes TXRQ 1 RMTPND 1 no yes INTPND 1 MCA04395 Figure 19 6 CAN Controller Handling of Transmit Objects DIR 1 User s Manual 19 24 V1 0 2002 02 technologies C164CM C164SM Derivatives On Chip CAN Interface yes no TXRQ 1 CPUUPD 0 yes NEWDAT 0 Load identifier and control into buffer Send remote frame no Transmission successful yes TXRQ 0 RMTPND 0 Medo yes INTPND 1 Bus idle MSGLST 1 Received frame with same identifier as this message object no yes yes no Store message NEWDAT 1 TXRQ 0 RMTPND 0 INTPND 1 0 Reset 1 Set MCA04396 Figure 19 7 CAN Controller Handling of Receive Objects DIR 0 User s Manual 19 25 V1 0 2002 02 technologies C164CM C164SM Derivatives On Chip CAN Interface Power Up Initialization Update Start all bits undefined application cpecific application cpecific INTPND 0 RMTPND 0 TXRQ 0 CPUUPD 1 Identifier application cpecific TXIE RXIE NEWDAT 0 Direction transmit DLC application cpecific MSGVAL 1 XTD application cpecific CPUUPD 1 NEWDAT 1 Update Write calculate message contents Update End CPUUPD 0 gt Want to send
393. mines the effective bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to O transition at pin RXDO If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register When the last stop bit has been received the content of the receive shift register is transferred to the receive data buffer register SORBUF Simultaneously the receive interrupt request flag SORIR is set after the gth sample in the last stop bit time slot as programmed whether or not valid stop bits have been received The receive circuit then waits for the next start bit 1 to 0 transition at the receive data input pin The receiver input pin RXDO must be configured for input that is the respective direction latch must be 0 Asynchronous reception is stopped by clearing bit SOREN A frame currently being received is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Start bits following this frame will not be recognized Note In wake up mode received frames are transferred to the receive buffer register only if the 9f pit the wake up bit is 1 If this bit is 0 no receive interrupt request Will be activated and no data will be transferred User s Manual 11 7 V1 0 2002 02
394. mmunication between the C164CM and other microcontrollers microprocessors or external peripherals The ASCO supports both full duplex asynchronous communication and half duplex synchronous communication for baud rate ranges see formulas and tables in Section 11 4 In synchronous mode data are transmitted or received synchronous to a shift clock generated by the C164CM In asynchronous mode selection of 8 or 9 bit data transfer parity generation and the number of stop bits can be made Parity framing and overrun error detection are provided to increase the reliability of data transfers Transmission and reception of data are double buffered For multiprocessor communication a mechanism is provided to distinguish address bytes from data bytes Testing is supported by a loop back option A 13 bit baud rate generator provides the ASCO with a separate serial clock signal Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions DPOH E SOBG SOCON SOTIC POH SOTBUF SORIC SORBUF SOEIC RXDO POH 4 TXDO POH 3 ine DPOH Port 0 Direction Control Register POH Port 0 Data Register High SOBG ASCO Baud Rate Generator Reload Reg SOCON ASCO Control Register SOTBUF ASCO Transmit Buffer Register SORBUF ASCO Receive Buffer Register read SOTIC ASCO Transmit Interrupt Control Register only SOTBIC ASCO Transmit Buffer Interrupt Ctrl Reg SORIC ASCO Receive Interrupt Control Register SOEIC ASC
395. mode can be terminated by a hardware reset only Note All external bus actions are completed before a power saving mode is entered In addition the power management selects the current CPU frequency and controls which peripherals are active During Slow Down Operation the basic clock generation path is bypassed and the CPU clock is generated via the programmable Slow Down Divider SDD from the selected oscillator clock signal Peripheral Management disables and enables the on chip peripheral modules independently reducing the amount of clocked circuitry including the associated clock drivers User s Manual 21 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 1 Idle Mode Power consumption of the C164CM microcontroller can be decreased by entering Idle mode In this mode all enabled peripherals continue to operate normally including the watchdog timer only the CPU operation is halted and the on chip memory modules are disabled Note Peripherals that have been disabled via software also remain disabled after entering Idle mode Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed bitfield SLEEPCON in register SYSCON must be 00pg To prevent unintentionally entering Idle mode the IDLE instruction has been implemented as a protected 32 bit instruction Idle mode is terminated by interrupt
396. mple of a Reception Object This object shall be configured for reception A receive interrupt shall be generated each time new data comes in From time to time the CPU sends a remote request to trigger the sending of this data from a remote node MCR Message object is idle i e waiting for a frame to be received 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 0 1 10 0 1 10 0 1 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND MCR A data frame was received NEWDAT 1 INTPND 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01 01 01 10 10 01 10 10 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND To process the message the CPU should clear INTPND and NEWDAT process the data and verify that NEWDAT is still clear after that If it is not clear the processing should be repeated To send a remote frame to request the data bit TXRQ simply needs to be set This bit will be cleared by the CAN controller after the remote frame has been sent or if the data is received before the CAN controller could transmit the remote frame User s Manual 19 35 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 6 CAN Application Interface The on chip CAN module of the C164CM is connected to the external physical layer i e the CAN bus via two signals as shown
397. n Control Internal Bus MCB01957 Figure 12 2 Synchronous Serial Channel SSC Block Diagram The operating mode of the serial channel SSC is controlled by its bit addressable control register SSCCON This register serves two purposes e During programming SSC disabled by SSCEN 0 it provides access to a set of control bits During operation SSC enabled by SSCEN 1 it provides access to a set of status flags Register SSCCON is shown below in each of the two modes SSCCON SSC Control Reg Pr M SFR FFB2 D9 Reset Value 00004 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC EN MS BN BEN PEN REN TEN PO PH HB seem rw rw x nw nw rw rw rw rw rw rw rw rw User s Manual 12 2 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface Bit Function Programming Mode SSCEN 0 SSCBM SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 bit lt SSCBM gt 1 SSCHB SSC Heading Control Bit 0 Transmit Receive LSB First 1 Transmit Receive MSB First SSCPH SSC Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge af Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock P
398. n terms of its architecture its functional units or functions This helps to quickly find the answer to specific questions about the C164CM A Access to X Peripherals 9 25 Acronyms 1 8 Adapt Mode 20 15 ADC 2 16 18 1 ADCIC ADEIC 18 15 ADCON 18 3 ADDAT ADDAT2 18 5 Address Arbitration 9 21 Area Definition 9 20 Boundaries 3 10 ADDRSELx 9 17 9 21 ALE length 9 10 Alternate signals 7 9 ALU 4 16 Analog Digital Converter 2 16 18 1 Arbitration Address 9 21 ASCO 11 1 Asynchronous mode 11 5 Baudrate 11 11 Error Detection 11 10 Interrupts 11 15 Synchronous mode 11 8 Bit addressable memory 3 4 Handling 4 10 Manipulation Instructions 24 2 protected 2 21 4 10 reserved 2 13 Block Commutation Mode 17 16 Bootstrap Loader 15 1 20 16 Boundaries 3 10 BTR 19 12 Burst Mode CAPCOM6 17 10 Bus CAN 2 15 19 1 19 36 Demultiplexed 9 5 Idle State 9 23 Mode Configuration 9 2 20 17 Mode preferred 9 3 Multiplexed 9 4 BUSCONx 9 16 9 21 C CAN Interface 2 15 19 1 activation 19 31 port control 19 37 Asynchronous Serial Interface gt ASCO CAPCOM 2 18 11 1 Auto Scan conversion 18 7 B Baudrate ASCO 11 11 Bootstrap Loader 15 6 SSC 12 13 Bidirectional reset 20 4 User s Manual interrupt 16 22 16 23 timer 16 4 Trap Function 17 18 unit 16 1 17 1 Capture Mode CAPCOM2 16 12 CAPCOMSG 17 11 GPT1 10 19 Capture Compare unit 16 1 17 1 CC6IC CCGEIC 17 33 26 1 V1 0 2002 02 _ Infineon technologies
399. n C164CM C164SM technologies Derivatives System Programming The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism requires moving only that portion of stack data which is really to be re used the upper part of the defined stack area instead of the entire stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the Stack Pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000 to 100g it does not work with option STKSZ 111g which uses the complete internal RAM for system stack In the latter case the address transformation mechanism is deactivated When a boundary is reached the stack underflow or overflow trap is entered in which the user moves a predetermined portion of the internal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of the internal stack After the transfer is complete the boundary pointers are updated to reflect
400. n Single Chip Reset Mode WR Port 20 Mode Notes 1 Port 20 is disabled the Software may enable and use the external respective pins retain their bus interface at any time alternate functions 0 Port 20 is enabled the This corresponds to an active write signal respective pins switch to and indicates that no external system is input except for RSTOUT present 1 In all other cases Port 20 remains disabled after reset Care must be taken if designing an external read only system e g EPROM where the active write signal does not conflict with the system A pull up may be required for the output enable signal Note Startup mode configuration and Port 20 mode configuration are independent of each other User s Manual 20 20 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset 20 5 System Configuration via Software The system configuration selected via hardware after reset latched pin levels or default value can be changed via software by executing a specific code sequence The respective control bits are located within registers SYSCON BUSCONx and RSTCON Register SYSCON can be modified only before the execution of instruction EINIT while registers BUSCONx and RSTCON using the specific sequence can be modified repeatedly at any time The clock generation mode CLKCFG is controlled by register RPOH RPOH is initialized according to the selected reset mode pi
401. n as unsigned 13 bit integer lt SOBRS gt represents the value of bit SOBRS either 0 or 1 taken as integer The tables below list various commonly used baud rates and the required reload values and deviation errors compared to the intended baud rates for a number of CPU frequencies Note The deviation errors given in the tables below are rounded Using a baudrate crystal such as 18 432 MHz will provide correct baud rates without deviation errors User s Manual 11 11 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Asynchronous Synchronous Serial Interface Table 11 1 ASCO Asynchronous Baudrate Generation for fcpy 16 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 500 kbit s 0 0 0000 19 2 kbit s 0 2 3 5 0019 001A 2 1 3 5 00104 00114 9600 bit s 0 2 1 7 00334 00344 2 1 0 8 00214 00224 4800 bit s 0 2 0 8 00674 00684 0 6 0 8 0044 00454 2400 bit s 0 2 0 3 OOCF OODO 0 6 0 1 0089 008A 1200 bit s 0 4 0 1 019F 01A0 0 3 0 1 01144 01154 600 bit s 0 0 0 1 03404 03414 0 1 0 1 022A 022B 61 bit s 0 1 1FFF 0 0 0 0 115Bp 115C4 40 bit s 1 796 1FFF Table 11 2 ASCO Asynchronous Baudrate Generation for fep 20 MHz Baud Rate SOBRS 0
402. n be achieved by programming the respective times to a higher value or to the possible maximum This is preferred when using analog sources and an analog supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may be considerably lower however The conversion time is programmed via the upper two bits of register ADCON Bitfield ADCTC conversion time control selects the basic conversion clock fgc used for the operation of the A D converter The sample time is derived from this conversion clock Table 18 2 lists the possible combinations The timings refer to CPU clock cycles where tepu 1 fcpu The limit values for fgc see data sheet must not be exceeded when selecting ADCTC and fcpy Table 18 2 ADC Conversion Timing Control ADCON 15114 A D Converter ADCON 13112 Sample Time ts ADCTC Basic Clock fac ADSTC 00 fcpu 4 00 tac x 8 01 cpu 2 01 tac x 16 10 fopu 16 10 tac x 32 11 fcpu 8 11 tac x 64 User s Manual 18 13 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Analog Digital Converter The time for a complete conversion includes the sample time ts the actual conversion and the time required to transfer the digital value to the result register 2 topy as shown in the example below Note The non linear decoding of bit field ADCTC provides compatibility with 80C 166 designs for the default va
403. n or mask generation It can be accessed via any instruction capable of addressing an SFR ONES Ones Register SFR FF1E 8Fy Reset Value FFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r r r r r r r r r r r r r r r r User s Manual 4 33 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 Interrupt and Trap Functions The architecture of the C164CM supports several mechanisms for fast and flexible response to service requests from various sources internal or external to the microcontroller These mechanisms include Normal Interrupt Processing Interrupt Processing via the Peripheral Event Controller Trap Functions and External Interrupt Processing Normal Interrupt Processing The CPU temporarily suspends current program execution and branches to an interrupt service routine to service an interrupt requesting device Current program status IP PSW also CSP in segmentation mode is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt Processing via the Peripheral Event Controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the C164CM s integrated Peripheral Event Con
404. nal can be controlled via software unlike CLKOUT and so can be adapted to the requirements of connected external circuitry The programmability extends power management to the system level as circuitry external to the C164CM can be influenced Peripherals for instance can run at a scalable frequency or can be switched off temporarily This clock signal is generated via a reload counter so the output frequency can be selected in small steps An optional toggle latch can provide a clock signal with a 5096 duty cycle FOEN Jopu FOSS MCA04480 Figure 21 6 Clock Output Signal Generation Signal four always provides complete output periods see Signal Waveforms below e When four is started FOEN gt 1 FOCNT is loaded from FORV e When four is stopped FOEN gt 0 FOCNT is stopped when four has reached or is 0 Signal four is independent of the peripheral clock driver PCD While CLKOUT will stop if PCD is disabled four will continue to toggle Thus external circuitry may be controlled independently from on chip peripherals Note Counter FOCNT is clocked with the CPU clock signal f cpy see Figure 21 6 and therefore will also be influenced by the SDD operation Register FOCON provides control over the output signal generation frequency waveform activation as well as all status information counter value FOTL User s Manual 21 17 V1 0 2002 02 Infineon C164CM
405. nal hardware User s Manual 22 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming 22 1 Stack Operations The C164CM supports two types of stacks the system stack and the user stack The system stack is used implicitly by the controller and is located in the internal RAM The user stack provides stack access to the user in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses Internal System Stack A system stack is provided to store return vectors segment pointers and processor status for procedures and interrupt routines A system Stack Pointer register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of words only Bytes must either be converted to words or the respective other byte must be disregarded Register SP can be loaded with even byte addresses only The LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer
406. nchronous Serial Interface The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There is an easy way to avoid collisions on the receive line caused by data from multiple slaves Only one slave drives the line i e enables the driver of its MRST pin All the other slaves have to program their MRST pins to input So only one slave can put its data onto the master s receive line Only receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a deselection signal or command After performing all necessary initializations of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either O or 1 until the first transfer starts When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register SSCTB This value is copied into the shift register which is assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the baudrate generator transmiss
407. nd a negative transition of T3OTL are selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard reload mode reload on overflow underflow If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using this single transition mode for both auxiliary timers allows very flexible Pulse Width Modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of TSOTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers Note Although possible selecting the same reload trigger event for both auxiliary timers should be avoided In such a case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4 is reloaded User s Manual 10 18 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 101p In capture mode the contents of the core timer are latched int
408. nd subtraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is provided to support multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag represents the logical NORing of the two specified bits For the prioritized ALU operation the Z flag indicates whether the second operand was zero E Flag The E flag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000 for the word data type or 80 for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whethe
409. ng bank 2 register see Table 16 6 must be programmed to compare mode 0 If the respective bank 1 compare register is disabled or programmed for a mode other than mode 1 the corresponding bank 2 register will operate in compare mode 0 interrupt only mode In the following example a bank 2 register programmed to compare mode O will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx User s Manual 16 19 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 When a match is detected for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin CCxlO corresponding to bank 1 register CCx is toggled The generated interrupt always corresponds to the register that caused the match Note If a match occurs simultaneously for register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two separate compare interrupt requests will be generated one for vector CCxINT and one for vector CCZINT To use the respective port pin as compare signal output pin CCxlO for compare register CCx in double register compare mode this port pin must be configured as output the corresponding direction control bit must be set to 1 With this configuration the output pin has the same characteristics as in compare mode 1
410. nly the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This approach assumes no error but requires a set of control routines see below Circular Virtual Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary is reached since the stack empties upward to higher memory locations Entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate flushing and filling normally occur very infrequently If this is not true for a specific program environment this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation via hardware of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined physical stack area within the internal RAM This virtual stack area covers all possible locations to which SP can point i e 00 F000 through OO FFFE Registers STKOV and STKUN acce
411. nologies Derivatives Analog Digital Converter Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 10 single conversion or to 115 continuous conversion Auto Scan modes automatically convert a sequence of analog channels beginning with the channel specified in bit field ADCH and ending with channel 0 without requiring software to change the channel number After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit field ADCH will be converted After the conversion is complete the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the next lower channel ADCIR will be set after each completed conversion The current sequence is complete after conversion of channel 0 In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH When bit ADST is reset by software while a conversion is in progress the converter will complete the current sequence including conversion of channel 0 and then stop and reset bit ADBSY 3 2 1 0 3 2 im Edd T T T T le dbe 8 W h da d Write ADDAT ix 3 2 1 0 3 ADDAT Ful LC pP p L___ Generate Interrupt Request ADDAT Full
412. nologies Derivatives Capture Compare Unit CAPCOM2 16 6 Capture Compare Interrupts Upon a capture or compare event on channels 16 19 and 24 27 the interrupt request flag CCxIR for the respective capture compare register CCx is set to 1 This flag can be used to generate an interrupt or to trigger a PEC service request when enabled by the interrupt enable bit CCxIE Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred see also Section 5 8 Each of the 8 capture compare registers listed above has its own bit addressable interrupt control register CC271C CC241C CC19IC CC161C and its own interrupt vector CC27INT CC24INT CC19INT CC16INT These registers are organized the same way as all other interrupt control registers The basic register layout is shown here Table 16 7 lists the associated addresses CCxIC CAPCOM Intr Ctrl Reg ESFR See Table 16 7 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCx CC R E ILVL GLVL mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Table 16 7 CAPCOM2 Unit Interrupt Control Register Addresses CAPCOM2 Unit Register Name Address Register Space CC16IC F160 BOH ESFR CC
413. ns in the PSW The Processor Status Word PSW is functionally divided into two parts the lower byte of the PSW basically represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the C164CM and the arbitration mechanism for the external bus interface Note Pipeline effects must be considered when enabling disabling interrupt requests via modifications of register PSW see Chapter 4 PSW Processor Status Word SFR FF10 88 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN UBR MUL E z vje n rwh rw rw rwh rwh rwh rwh rwh rwh Bit Function N C V Z E CPU status flags Described in Chapter 4 MULIP USRO Define the current status of the CPU ALU multiplication unit IEN Interrupt Enable Control Bit globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled ILVL CPU Priority Level Defines the current priority level for the CPU Fu Highest priority level O4 Lowest priority level User s Manual 5 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions CPU Priority ILVL defines the current level for the operation of the CPU This bit field reflects the priority level of the routine currently executed Upon entry into an interrupt service routine this b
414. ns or default The respective configuration bitfields can be copied from register RSTCON upon entering Slow Down Divider mode if enabled by bit SUE 1 The following steps must be taken to change the current configuration see software example as well Write intended configuration value to RSTCON e Enter SDD mode e Return to basic clock mode CHANGE CLOCK CONFIGURATION RSTCON is a mem address no SFR MOV R15 11100001xxxxxxxxB Load a GPR with the target value MOV RSTCON R15 Enable update with PLL factor 4 EXTR 2 ESFR access to SYSCON2 MOV SYSCON2 0100H SDD mode PLL on factor 1 RSTCON 15 9 is copied to RPOH 15 9 MOV SYSCON2 0400H Switch to basic clock mode System will run on PLL factor 4 after PLL has locked Note This software example assumes execution before EINIT Otherwise the unlock sequence must be executed prior to each access to RS8TCON SYSCONA Entering SDD mode temporarily ensures a correct clock signal synchronization in cases where the clock generation mode is changed PLL factor for example If the target basic clock generation mode uses the PLL the C164CM will run in direct drive mode until the PLL has locked Software modification of system configuration values is protected by the following features e SYSCON is locked after EINIT e RSTCON requires the unlock sequence after EINIT Copying RSTCON to RPOH must be explicitly enabled by setting bit SUE User s Manual 20
415. nstruction with the undefined opcode is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap User s Manual 5 33 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions External NMI Trap Whenever a high to low transition on the dedicated external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI pin is sampled with every CPU clock cycle to detect transitions Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremented by a subtract instruction the IP value pushed represents the address of the instruction after the instruc
416. nstruction first pushes the reg operand and the IP contents onto the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program User s Manual 22 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of the CALLS call inter segment subroutine instruction This instruction preserves both the CSP Code Segment Pointer and the IP on the system stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment Note It is possible to use CALLS within the same segment but two words of the stack are still used to store both the IP and CSP Providing Local Registers for Subroutines The following methods are provided for subroutines which require local storage Alternate Banks of Registers e Saving and Restoring Registers Use of the System Stack for Local Registers Alternate Bank of Registers Upon entry into a subroutine it is possible to specify a new set of local registers by executing the SCXT switch
417. nter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reserved Do not use this combination 101 Reserved Do not use this combination 110 Incremental Interface Mode 111 Reserved Do not use this combination T3R Timer 3 Run Bit 0 Timer Counter 3 stops 1 Timer Counter 3 runs T3UD Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable TSOTL Timer 3 Output Toggle Latch Toggles on each overflow underflow of T3 Can be set or reset by software 1 For the effects of bits T3UD and T3UDE refer to the direction Table 10 1 Timer 3 Run Bit The timer can be started or stopped by software through bit T3R Timer T3 Run Bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will run only if T3R 1 and the gate is active high or low as programmed User s Manual 10 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input an alternate input function of port pin P5 2 These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is provided by software bit T3UDE 0 the count direction can be altered by setting or clearing bit
418. nterface mainly for accessing small external memories or for controlling external peripherals Two memory sizes are supported e 8 bit Multiplexed Bus 2 KBytes with A10 AO on PORTO e Any other bus mode 64 KBytes with A15 AO on PORTO or PORT1 Memory model and bus mode are selected during reset by pin EA and PORTO pins For further details about the external bus configuration and control please refer to Chapter 9 External word and byte data can only be accessed via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any word data access is made to an even byte address For PEC data transfers the external memory in segment O can be accessed independently of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and therefore it is not bitaddressable 1 This bus mode offers lowest performance but allows concurrent operation of external bus interface and standard serial interfaces User s Manual 3 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization 3 4 Crossing Memory Boundaries The address space of the C164CM is implicitly divided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attent
419. nternally derived from these two input signals so the contents of timer Tx corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate tasks such as position tracking The core timer T3 has an output toggle latch TSOTL which changes its state on each timer overflow underflow The state of this latch may be used internally to concatenate the core timer with the respective auxiliary timers resulting in 32 33 bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be selected to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of toggle latch T3OTL The maximum resolution of the timers in module GPT1 is 8 CPU clock cycles 2 16 TCL User s Manual 2 17 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Architectural Overview Capture Compare CAPCOM Units The CAPCOM units are typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PWM Digital to Analog D A conversion software timing or time recording relative to external events A number of dedicated timers with reload registers provide independent time bases for the capture c
420. nterrupt Register EFO2 IR Bit Timing Register EF04 BTR Global Mask Short EF06 GMS Global Mask Long LGML UGML Mask of Last Message LMLM UMLM General Registers EF08 EFOC MCA04392 Figure 19 3 CAN Module Address Map User s Manual 19 6 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 2 General Functional Description The Control Status Register CSR accepts general control settings for the module and provides general status information CSR Control Status Register XReg EF00 Reset Value XX01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B E RX TX OFF WRNI OK OK LEC TM CCE O CPS EIE SIE IE INIT rh rmn r rwh rwh rwh w w r w rw rw rw wh Bit Function Control Bits INIT Initialization Starts the initialization of the CAN controller when set INIT is set after a reset when entering the busoff state by the application software IE Interrupt Enable Enables or disables interrupt generation from the CAN module via the signal XINTR Does not affect status updates SIE Status Change Interrupt Enable Enables or disables interrupt generation when a message transfer reception or transmission is successfully completed or a CAN bus error is detected and registered in the status partition EIE Error Interrupt Enable Enables or disabl
421. ntifiers of 29 bits However the CPU must configure bit XTD Normal or Extended Frame Identifier for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system The object layer architecture of the CAN controller is designed to be as regular and orthogonal as possible This makes it easy to use User s Manual 19 2 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives On Chip CAN Interface CAN_TxD CAN_RxD BTL Configuration Y Timing Generator Tx Rx Shift Register k Clocks Messages Handlers Intelligent Memory to all Interrupt Control Register Status Control Status Register id to XBUS MCB04391 Figure 19 2 CAN Controller Block Diagram User s Manual 19 3 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to allow parallel access to the entire data frame or remote frame for the acceptance match test and parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The Bit Stream Processor BSP is a sequencer controlling the sequential data s
422. ntrol Vpp via an output port line 50 ns 15ns j 50 ns NL 10us Vpp EA Vpp lt Vop MCT05094 The special signals CE and RSEL must fulfill the same timing requirements as the address lines Note All timings represent minimum values Figure 3 6 OTP Verify Read Cycle The programming cycles can be controlled in two different ways In CPU Host Mode CHM the CPU of the C164CM itself controls the programming cycles via the OTP programming interface The programming routine must be fetched from outside the OTP memory on chip RAM or external memory In External Host Mode EHM the C164CM is put into emulation mode where the CPU and the generic peripherals are disabled The on chip OTP memory can be accessed by an external master via the C164CM s bus interface The bus interface signals change their direction in this mode User s Manual 3 13 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization 3 6 1 Selecting an OTP Programming Mode Both programming modes can only be enabled via reset configuration CPU Host Mode CHM is enabled after an external reset by pulling low pin POL 2 in either standard startup mode or in bootstrap loader mode Pins POL 5 O here represent 1171011 standard or 1010115 BSL After a single chip mode reset CHM is automatically enabled without additional control Note When CHM is enabled in stan
423. ntroller Each of the 15 message objects uses 15 consecutive bytes see Figure 19 5 and starts at an address that is a multiple of 16 Note All message objects must be initialized by the CPU before clearing the INIT bit even those which are not going to be used Offset Message Control MCR 0 lt Object Start Address EFnO H 2 Arbitration UAR amp LAR H4 Message Object 1 EF10 H 6 Message Object 2 EF20 H 10 Message Object 14 EFEO H 12 Message Object 15 EFFO H MCA04394 Figure 19 5 Message Object Address Map The general properties of a message object are defined via the Message Control Register MCR There is a dedicated register MCRn for each message object n Each element of the Message Control Register consists of two complementary bits This special mechanism allows the selective setting or resetting of specific elements leaving others unchanged without requiring read modify write cycles None of these elements will be affected by reset Table 19 1 shows the functions and meanings of these 2 bit fields Table 19 1 MCR Bitfield Encoding Value Function on Write Meaning on Read 0 0 Reserved Reserved 0 Reset element Element is reset 1 0 Set element Element is set 1 Leave element unchanged Reserved User s Manual 19 18 V1 0 2002 02 _ Infineon technologies MCRn Message Control Register C164CM C164SM Derivatives
424. ntroller is not stopped while sending a dominant level 0 on the CAN bus the CPU should set bit INIT in the Control Register prior to entering Power Down mode The CPU can determine if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down mode via hardware reset the CAN module must be reconfigured User s Manual 19 30 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Disabling the CAN Modules When the CAN module is disabled by setting bit CAN1DIS in register SYSCONS3 peripheral management no register accesses are possible The module s logic blocks are also stopped so no CAN bus transfers are possible When the CAN module is re enabled CAN1DIS 0 it must be reconfigured as after return from Power Down mode Note Incoming message frames can still be recognized not received in this case by monitoring the receive line CAN1 RXD For this purpose the receive line CAN1 RXD can be connected to a fast external interrupt via register EXISEL CAN Module Reset The on chip CAN module is connected to the XBUS Reset signal This signal is activated when the C164CM s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN module s reset line triggers a hardware reset This hardware reset has the following effects
425. nual 4 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status bits are cleared N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000 to 7FFF for the word data type or from 80 to 7F for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XORing of the two specified bits C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry f
426. ny Class B trap is pending any of the class B trap flags in register TFR is set the ATOMIC instruction will not work Clear the respective B trap flag at the beginning of a B trap routine if ATOMIC shall be used within the routine 22 9 Overriding the DPP Addressing Mechanism The standard mechanism for accessing data locations uses one of the four data page pointers DPPx which selects a 16 KByte data page and a 14 bit offset within this data page The four DPPs allow immediate access to up to 64 KBytes of data In applications with large data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single accesses User s Manual 22 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming The EXTP extend page instruction allows switching to an arbitrary data page for 1 4 instructions without changing the current DPPs EXTP R15 1 The override page number is stored in R15 MOV RO R14 The 14 bit page offset is stored in R14 MOV R1 R13 This instruction uses the std DPP scheme The EXTS extend segment instruction allows switching to a 64 KByte segment oriented data access scheme for 1 4 instructions without changing the current DPPs In this case all 16 bits of the operand address are used as segment offset with the segment taken from the EXTS instruction This greatly simplifies address calculation with
427. o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions e When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the minimum interrupt response time may be extended by 1 state time for each of these conditions e When instruction N reads an operand from the internal code memory or when N is a call return trap or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 state times during internal code memory program execution Incase instruction N reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extended by 2 state times The worst case interrupt response time during internal code memory program execution adds to 12 state times 24 TCL Any reference to external locations increases the interrupt response time due to pipeline related access priorities The following conditions must be considered e Instruction fetch from an external location Operand read from an external location e Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external
428. o O0CO e Bit ROMEN in register SYSCON will be set to 1 The other bits of register BUSCONO and the other BUSCON registers are cleared This default initialization selects the slowest possible external accesses using the configured bus type When the internal reset is complete the configuration of PORTO and PORT1 depends on the bus type selected during reset If any of the external bus modes was selected during reset PORTO will operate in the selected bus mode When the on chip bootstrap loader was activated during reset pin TxDO alternate port function will be switched to output mode after the reception of the zero byte All other pins remain in the high impedance state until they are changed by software or peripheral operation Note If Port 20 operation is selected after reset by pulling pin WR low auring an internal reset with EA 1 pins RD WR and ALE switch to input when the internal reset is complete User s Manual 20 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset Reset Output Pin The RSTOUT pin generates a reset signal for the system components other than the controller RSTOUT will be driven active low at the begin of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low beyond the end of the internal reset sequence until the protected EINIT End of Initialization instruction is executed
429. o an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin TxIN The capture trigger signal can be a positive a negative or both a positive and a negative transition The two least significant bits of bit field Txl are used to select the active transition see Table 10 8 while the most significant bit Txl 2 is irrelevant for capture mode It is recommended to keep this bit cleared TxlI 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independently of its run flag T2R or T4R Edge lect aplec Capture Register Tx Interrupt p Request TxIR Input Txl Interrupt Clock Core Timer T3 p Request TSIR Up Down T30TL MCB02038b Figure 10 13 GPT1 Auxiliary Timer in Capture Mode Upon a trigger selected transition at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set Note To ensure correct edge detection the direction control bits for T2IN and T4IN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 fcpy cycles before it changes User s Manual 10 19 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit 10 1 3 Interrupt Control for GPT1 Timers When a timer overfl
430. oder can be connected directly to the C164CM without external interface logic In a standard system however comparators will be employed to convert the encoder s differential outputs such as A A to digital signals such as A This greatly increases noise immunity Note The third encoder output TopO which indicates the mechanical zero position may be connected to an external interrupt input and trigger a reset of timer T3 for example via PEC transfer from ZEROS Signal Conditioning Encoder Controller TSInput TS3Input Interrupt MCS04372 Figure 10 7 Connection of the Encoder to the C164CM For incremental interface operation the following conditions must be met e Bitfield T3M must be 110p e Both pins T3IN and T3EUD must be configured as input e g the respective direction control bits must be 0 Bit T3UDE must be 1 to enable automatic direction control The maximum input frequency allowed in incremental interface mode is fcpy 16 To ensure that a transition of any input signal is recognized correctly its level should be held high or low for at least 8 fcpy cycles before it changes As in Incremental Interface Mode two input signals with a 90 phase shift are evaluated their maximum input frequency can be fcpu 32 In Incremental Interface Mode the count direction is automatically derived from the sequence in which the input signals change which corresponds to the rotation direc
431. odifiable portion of register SP Specifies the top of the internal system stack User s Manual 4 27 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Stack Overflow Pointer STKOV This non bit addressable register is compared against the SP register after each operation which pushes data onto the system stack e g PUSH and CALL instructions or interrupts and after each subtraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Because the least significant bit of register STKOV is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKOV register can contain values from FOOO to FFFE only STKOV Stack Overflow Reg SFR FE14 0A Reset Value FA00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 stkov 0 r r r r rw Bit Function stkov Modifiable portion of register STKOV Specifies the lower limit of the internal system stack The Stack Overflow Trap entered when SP lt STKOV may be used in two different ways Fatal error indication treats the stack overflow as a system error through the associated trap service routine Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow
432. odule provides Full CAN functionality on up to 15 message objects Message object 15 may be configured for Basic CAN functionality Both modes provide separate masks for acceptance filtering which allows acceptance of a number of identifiers in Full CAN mode and also allows a number of identifiers in Basic CAN mode to be disregarded All message objects can be updated independently from the other objects and are equipped for the maximum message length of 8 bytes The bit timing is derived from the CPU clock and is programmable up to a data rate of 1 Mbit s The CAN Module uses two pins configurable to interface to a bus transceiver Parallel Ports The C164CM provides up to 50 I O lines which are organized into four input output ports and one input port All port lines are bit addressable and all input output lines are individually programmable bit wise as inputs or outputs via direction registers The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of one I O port can be configured pin by pin for push pull operation or open drain operation via a control register During the internal reset all port pins are configured as inputs All port lines have programmable alternate input or output functions associated with them PORTO and PORT1 may be used as address and data lines when accessing external memory PORTO pins are also used for the standard serial interfaces ASC
433. of IO lines for interrupt input The interrupt function may be either combined with the pin s main function or used instead of it if the main pin function is not required Interrupt signals may be connected to e EXSIN EXOIN the fast external interrupt input pins e CC27IO CC2410 capture input compare output lines of the CAPCOM2 unit e CC191O CC161O capture input compare output lines of the CAPCOM2 unit TAIN T2IN the timer input pins For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as an external interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control register DPx Table 5 8 Pins Usable as External Interrupt Inputs Port Pin Original Function Control Register P1H 3 0 EX3 0IN Fast external interrupt input pin EXICON
434. of embedded control applications requires microcontrollers for new high end embedded control systems to possess a significant increase in CPU performance and peripheral functionality over conventional 8 bit controllers To achieve this high performance goal Infineon has decided to develop its family of 16 bit CMOS microcontrollers without the constraints of backward compatibility Nonetheless the architecture of the 16 bit microcontroller family pursues successful hardware and software concepts which have been established in Infineon s popular 8 bit controller families User s Manual 1 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Introduction About this Manual This manual describes the functionality of a number of 16 bit microcontrollers of the Infineon C166 Family the C164 group The derivatives described here offer high performance features in an extremely compact package These microcontrollers provide identical functionality to a large extent but each device type has specific unique features as indicated here The descriptions in this manual cover a superset of the provided features and refer to the following derivatives C164CM 4R 32 KByte Program ROM full function CAPCOMG CAN module C164SM 4R 32 KByte Program ROM full function CAPCOM6 C164CM 4E 32 KByte Program OTP full function CAPCOM6 CAN module This manual is valid for these derivatives and describes all variations of the dif
435. oftware and generates an interrupt request An interrupt is generated if the corresponding interrupt node is enabled If bit CT12RES in register CTCON is set timer T12 is cleared upon a trap event otherwise it continues counting No more transitions on the output signals will be generated however Leaving Trap State After the trap trigger is removed input CTRAP has been sampled inactive trap state is not left immediately but in a synchronized way see Reference Point 2 in Figure 17 11 when timer T12 reaches the value 00004 This delay automatically resumes the generation of the programmed output signals after a trap event synchronized to the next timer period The generation of distorted truncated pulses is avoided Note In block commutation mode trap state is exited when timer T13 not T12 reaches 0004 Controlling Trap State The general trap state control signal provides the timing for the trap logic and is valid for all output signals see Trap Trigger in Figure 17 12 The trap enable logic determines the effect of the trap state on the individual CAPCOM6 outputs see Trap Enable in Figure 17 12 In the default case all outputs are switched to the level of the associated port output latch P1L x In this case the trap state level for each output can be predefined independent of the normal operation of the respective signal including its initial level For each timer separately the standard trap function fo
436. ogies Derivatives Real Time Clock Defining the RTC Time Base The reload timer T14 determines the input frequency of the RTC timer that is the RTC time base as well as the T14 interrupt cycle time Table 14 2 lists the interrupt period range and the T14 reload values for a time base of 1 s and 1 ms for several oscillator frequencies Table 14 2 RTC Interrupt Periods and Reload Values Oscillator RTC Interrupt Period Reload Value A Reload Value B Frequency Minimum Maximum T14REL Base T14REL Base 32 kHz Main 8000 us 524 29s FF83 11 000s 4 MHz Main 64 0 us 4 19 s C2F7 1 000s FFFO 1 024 ms 5 MHz Main 51 2 us 3 35 s B3B5 0 999s FFEC 1 024ms 8 MHz Main 32 0 us 2 10s 85EE 1 000s FFE1 0 992ms 10 MHz Main 25 6 us 1 68 s 676A 10 999s FFD9 0 998 ms 12 MHz Main 21 3 us 1 40 s 48E5y 1 000s FFD2 1 003ms 16 MHz Main 16 0 us 1 05 s OBDC 1 000s FFC2 0 992 ms Increased RTC Accuracy through Software Correction The accuracy of the C164CM s RTC is determined by the oscillator frequency and by the respective prescaling factor excluding or including T14 The accuracy limit generated by the prescaler is due to the quantization of a binary counter where the average is zero while the accuracy limit generated by the oscillator frequency is due to the difference between the ideal and real frequencies and therefore accumulates over time The tota
437. ogrammed to compare mode 0 see Double Register Compare Mode on Page 16 19 Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective Only capture compare channels 16 19 and 24 27 are connected to pins Compare Mode 2 Compare mode 2 is an interrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 110p When a match is detected in compare mode 2 for the first time within a timer period the interrupt request flag CCxIR is set to 1 The corresponding port pin is not affected and can be used for general purpose IO However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period User s Manual 16 16 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM2 In the example shown in Figure 16 8 the compare value in register C
438. ol Register 0000 ZEROS b FF1Cj 8E Constant Value 0 s Register read only 00004 1 The system configuration is selected during reset 2 The reset value depends on the indicated reset source User s Manual 23 10 V1 0 2002 02 _ Infineon technologies 23 4 C164CM C164SM Derivatives Register Set Registers Ordered by Address Table 23 4 lists all registers implemented in the C164CM ordered by their physical address The following markings assist in classifying the listed registers b in the Name column marks Bit addressable SFRs E in the Physical Address column marks E SFRs in the Extended SFR Space m in the Physical Address column marks SFRs without short 8 bit address X in the Physical Address column marks registers within on chip X Peripherals Table 23 4 C164CM Registers Ordered by Name Name Physical 8 Bit Description Reset Address Addr Value OPCTRL EDCO X OTP Progr Interface Control Register 00074 OPAD EDC2 X OTP Progr Interface Address Register 00004 OPDAT EDC4 X OTP Progr Interface Data Register 00004 C1CSR EFOO X CAN1 Control Status Register XX014 C1PCIR EFO2 X CAN 1 Port Control Interrupt Register XXXXy C1BTR EFO44 X CAN1 Bit Timing Register UUUU C1GMS EFO6 X CAN1 Global Mask Short UFUU C1UGML EFO8 X CAN Upper Global Mask Long UUUU
439. olarity Control Bit 0 Idle clock line is low leading clock edge is low to high transition T Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable Bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable Bit 0 Ignore receive errors 1 Check receive errors SSCPEN SSC Phase Error Enable Bit 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable Bit 0 Ignore baudrate errors 1 Check baudrate errors SSCAREN SSC Automatic Reset Enable Bit 0 No additional action upon a baudrate error 15 The SSC is automatically reset upon a baudrate error SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK n Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 0 Transmission and reception disabled Access to control bits User s Manual 12 3 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface SSCCON SSC Control Reg Op M SFR FFB2 D9 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC EN ms BSY BE PE RE TE 7 SCBC rw rw x rw rw rw rw rw p z xi s r Bit Function Operating Mode SSCEN 1 SSCBC SSC Bit Count Field Shift counter is updated with every shifted b
440. ome special occasions however require certain code sequences such as semaphore handling to be executed uninterruptedly to function properly This can be accomplished by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence The necessary overhead may be reduced by means of the ATOMIC instruction which allows locking 1 4 instructions to an inseparable code sequence during which the interrupt system standard interrupts and PEC requests and Class A Traps NMI stack overflow underflow are disabled Class B Traps illegal opcode illegal bus access etc however will interrupt the atomic sequence since it indicates a severe hardware problem The interrupt inhibit caused by an ATOMIC instruction gets active immediately no other instruction will enter the pipeline except the one following the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this case for example MUL is one instruction Any instruction type can be used within an inseparable code sequence ATOMIC 3 The next 3 instr are locked No NOP requ MOV RO 1234H Instr 1 no other instr enters pipeline MOV R1 5678H Instr 2 MUL RO R1 Instr 3 MUL regarded as one instruction MOV R2 MDL This instruction is out of the scope Pe Of the ATOMIC instruction sequence Note As long as a
441. ompare channels The input clock for the timers is programmable to several prescaled values of the internal CPU clock or may be derived from an overflow underflow of timer T3 in module GPT1 for CAPCOM2 timers This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition external inputs for the CAPCOM units allow event scheduling for the capture compare registers relative to external events The CAPCOM2 unit supports generation and control of timing sequences on up to 16 channels 12 I O pins with a maximum resolution of 8 CPU clock cycles The capture compare register array contains 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM2 timer T7 or T8 and programmed for capture or compare function Twelve registers have port pins associated with them they serve as input pins for triggering the capture function or as output pins to indicate the occurrence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal
442. omplement negation of a word or byte NEG NEGB Logical Instructions Bitwise ANDing of two words or bytes AND ANDB Bitwise ORing of two words or bytes OR ORB Bitwise XORing of two words or bytes XOR XORB Compare and Loop Control Instructions e Comparison of two words or bytes CMP CMPB Comparison of two words with post increment by either 1 or 2 CMPI1 CMPI2 e Comparison of two words with post decrement by either 1 or 2 CMPD1 CMPD2 User s Manual 24 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Instruction Set Summary Boolean Bit Manipulation Instructions e Manipulation of a maskable bit field in either the high or the low byte of a word BFLDH BFLDL e Setting a single bit to 1 BSET e Clearing a single bit to 0 BCLR Movement of a single bit BMOV e Movement of a negated bit BMOVN ANDing of two bits BAND e ORing of two bits BOR e XORing of two bits BXOR Comparison of two bits BCMP Shift and Rotate Instructions e Shifting right of a word SHR e Shifting left of a word SHL e Rotating right of a word ROR e Rotating left of a word ROL e Arithmetic shifting right of a word sign bit shifting ASHR Prioritize Instruction Determination of the number of shift cycles required to normalize a word operand floating point support PRIOR Data Movement Instructions e Standard data movement of a word or byte MOV MOVB e Data movement of
443. on chip XBUS peripherals of the C164CM can be accessed from outside via the external bus interface under certain circumstances In emulation mode the XBUS peripherals are controlled by the bondout chip User s Manual 9 25 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives General Purpose Timer Unit 10 General Purpose Timer Unit The General Purpose Timer Unit GPT1 has a very flexible multifunctional timer structure which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes Block GPT1 contains 3 timers counters with a maximum resolution of 16 TCL Each timer may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer GPT1 has alternate input output functions and specific interrupts associated with it 10 1 Timer Block GPT1 From a programmer s point of view the GPT1 block is composed of a set of Special Function Registers SFRs as summarized in Figure 10 1 Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T2 3 T4 T2CON T3CON T4CON T2IN P5 6 T2EUD
444. on is a transparent feature The Port Temperature Compensation Register PTCR provides access to the actual compensation value and even allows software control of this mechanism This is useful in two cases Device testing the function of the compensation mechanism can be verified during production testing or characterization User control during operation the device can be controlled via externally provided compensation values rather than via the internal mechanism Temperature compensation is initialized using register PTCR enable and prescaler for reference clock The reference clock is used to generate a temperature related count value which is compared to three thresholds temperature levels at which the four control values max high low min are switched User s Manual 7 7 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Parallel Ports oon eae Comp Reg ESFR FOAE 57 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCDIV TCS TCC TCE TCV rw rw rw rw rwh Bit Function TCV Temperature Compensation Value The value which is currently generated by the temperature compensation sensor This value is fed to the port logic while bit TCS 1 00 Maximum driver strength no reduction i e very high temperature 11 Minimum driver strength reduction for compensation i e very low temperature Note
445. onged by half a CPU clock so the data transfer within a bus cycle refers to the same CLKOUT edges as usual the data transfer is delayed by one CPU clock This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx are 0 after reset Normal Multiplexed ie Lengthened Multiplexed Bus Cycle Bus Cycle ALE N N lt 1 4 Setup Hold aseo Cs MC us XT as imp XC sus P Mes MCD02235M Figure 9 6 ALE Length Control User s Manual 9 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Programmable Memory Cycle Time The C164CM allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change Bus Cycle MCTC Wait States 1 15 MCT02063M Figure 9 7 Memory Cycle Time The external bus cycles of the C164CM can be extended for a memory or peripheral which cannot keep pace with the controllers maximum speed This is accomplished by introducing wait states during the access see Figure 9 7 During these memory c
446. ont d Name Physical 8 Bit Description Reset Address _ Addr Value CC31 FE7Ey 3F4 CAPCOM Register 31 00004 CC60 FE30 184 CAPCOM 6 Register 0 00004 CC61 FE32y 194 CAPCOM 6 Register 1 00004 CC62 FE34 1A4 CAPCOM 6 Register 2 00004 CC6EIC b F188 E C4 CAPCOM 6 Emergency Interrupt 00004 Control Register CC6CIC b F17E E BF CAPCOM 6 Interrupt Control Register 00004 CC6MCON b FF324 99 CAPCOM 6 Mode Control Register OOFFy CC6MIC ___ib FF36 9B CAPCOM 6 Mode Interrupt Ctrl Reg 00004 CC6MSEL F036 E 1By CAPCOM 6 Mode Select Register 00004 CC8IC b FF88 C4 External Interrupt O Control Register 0000 CC9IC b FF8A C5 External Interrupt 1 Control Register 0000 CCM4 b FF22 914 CAPCOM Mode Control Register 4 0000 CCM5 b FF24 924 CAPCOM Mode Control Register 5 00004 CCM6 b FF26 934 CAPCOM Mode Control Register 6 00004 CCM7 b FF28 944 CAPCOM Mode Control Register 7 00004 CMP13 FE36y 1B4 CAPCOM 6 Timer 13 Compare Reg 00004 CP FE104 084 CPU Context Pointer Register FCOO CSP FEO8 O44 CPU Code Segment Pointer Register 00004 8 bits not directly writeable CTCON b FF30 984 CAPCOM 6 Compare Timer Ctrl Reg 1010 DPOH b F102 Ej814 POH Direction Control Register 00H DPOL b F100 E 80 POL Direction Control Register 00H DP1H b F106 E 834 P1H Direction Control Register 004 D
447. or PEC data transfers the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The upper 256 Bytes of the Internal RAM 00 FD00 through 00 FDFF and the GPRs of the current bank are provided for single bit storage and thus they are bit addressable System Stack The system stack may be defined within the Internal RAM The size of the system stack is controlled by bitfield STKSZ in register SYSCON see Table 3 1 Table 3 1 System Stack Size Encoding lt STKSZ gt Stack Size words Internal RAM Addresses words 00 Og 256 OO FBFE 00 FAO0 Default after Reset 0 0 1g 128 OO FBFEj 00 FBOO 0 1 0p 64 OO FBFEj 00 FB80j 0 1 1g 32 OO FBFE OO FBCO 10 0g 512 00 FBFE 00 F800j 10 1g Reserved Do not use this combination 1 1 0g Reserved Do not use this combination 11 1g 1024 00 FDFE 00 F600 Note No circular stack For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word accesses are supported to the system stack A stack overflow STKOV register and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used both for protection against data destruction and
448. or interrupt request is due to a framing error Asynchronous mode only e lf the parity error detection enable bit SOPEN is set in the modes in which a parity bit is received and the parity check on the received data bits proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode only e Ifthe overrun error detection enable bit SOOEN is set and the last character received was not read out of the receive buffer by software or by PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that the error interrupt request is due to an overrun error Asynchronous and Synchronous modes User s Manual 11 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Asynchronous Synchronous Serial Interface 11 4 ASCO Baud Rate Generation The serial channel ASCO has its own dedicated 13 bit baud rate generator with 13 bit reload capability allowing baud rate generation independent of the GPT timers The baud rate generator is clocked with the CPU clock divided by 2 fcpy 2 The timer counts downwards and can be started or stopped through the Baud Rate Generator Run Bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13 bit reload register each time it underflows The resulting clock is again di
449. or the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations cannot cause a carry For shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of 0 is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bits V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers which are representable by either 16 bits for word operations 8000 to 7FFF or by 8 bits for byte operations 80 to 7F Otherwise the V flag is cleared Note that the result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division
450. ows from FFFFy to 0000 counting up or when it underflows from 0000 to FFFFy counting down its interrupt request flag T2IR T3IR or T4IR in register TxIC will be set This will cause an interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or will trigger a PEC service if the respective interrupt enable bit T2IE T3IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers nno 2 Intr Ctrl Reg SFR FF60 B0 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T2IR T2IE ILVL GLVL z mh rw rw rw T3IC Timer 3 Intr Ctrl Reg SFR FF62 B1 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T3IR T3IE ILVL GLVL mh rw rw rw T4IC Timer 4 Intr Ctrl Reg SFR FF64 B2 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAIR T4IE ILVL GLVL mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 10 20 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives Asynchronous Synchronous Serial Interface 11 Asynchronous Synchronous Serial Interface The Asynchronous Synchronous Serial Interface ASCO provides serial co
451. pace and lock sequence sequence step 1 1001B sequence step 2 0011B sequence step 3 0111B access to one locked register Next access to ESFR space PLLIE 1 21 25 i e PLL interrupt enabled V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming 22 System Programming A number of features have been incorporated into the instruction set of the C164CM to facilitate software development including constructs for modularity loops and context switching In many cases commonly used instruction sequences have been simplified while their flexibility has been enhanced The following programming features help to fully utilize this instruction set Instructions Provided as Subsets of Instructions In many cases instructions found in other microcontrollers are provided as subsets of more powerful instructions in the C164CM This allows the same functionality to be provided while decreasing the hardware required and decreasing decode complexity To assist with assembly programming these instructions which are familiar from other microcontrollers can be built in macros thus providing the same names Direct Substitution Instructions are instructions known from other microcontrollers which can be replaced by the following instructions of the C164CM Table 22 1 Substitution of Instructions Substituted Instruction C164CM Instruction Function CLR Hn A
452. pin for the compare function The capture function causes the current timer contents to be latched into the respective capture compare register triggered by an event transition on its associated port pin The compare function may cause an output signal transition on that port pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated upon each capture compare event or upon timer overflow Figure 16 2 shows the basic structure of the CAPCOM2 unit User s Manual 16 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 Reload Reg TXREL Jopu 2n 1 Tx Interrupt TxIN Input Request a Control TxIR GPT1 Timer T3 Over Underflow cczo p Mowe gsm Capture Inputs Capture Capture f Capture Compare Compare Outputs p Compare Interrupt Request Z Registers Z CCzIO p Interrupt Jopu 2n 1 Ty GPT1 Timer T3 Control Dl Over Underflow 7 16 19 24 31 MCAO05086 Figure 16 2 CAPCOM2 Unit Block Diagram xX y Z Table 16 1 CAPCOM2 Channel Port Connections Unit Channel Port Capture Compare CAPCOM2 CC161O CC19IO P8 3 P8 0 Input Output CC20IO CC23IO CC24l1O CC271O P1H 7 P1H 4 Input Output CC281O CC311O P1H 0 P1H 3 Input Output Es16 y 12
453. ps and the corresponding status flags in register TFR It also lists the priorities of trap service for those cases in which more than one trap condition might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program execution starts at the reset vector at location 00 0000 Reset conditions have priority over every other system activity and therefore have the highest priority trap priority III Software traps may be initiated to any vector location between 00 0000 and 00 01FC A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests Table 5 2 Hardware Trap Summary Exception Condition Trap Trap Vector Trap Trap Flag Vector Location Number Prio Reset Functions Hardware Reset RESET 00 00004 00 I Software Reset RESET 00 00004 00 I Watchdog Timer Overflow RESET 00 00004 1004 I Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 00084 024 I Stack Overflow STKOF STOTRAP 00 00104 044 I Stack Underflow STKUF STUTRAP 00 0018 064 I Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 00 00284 0A4 Protected Instruction Fault PRTFLT BTRAP
454. pt request flags T3CON TSOTL GPT1 timer output toggle latches T7IC T8IC T7IR T8IR CAPCOM timer interrupt request flags SOTIC SOTBIC SOTIR SOTBIR ASCO transmit buffer interrupt request flags SORIC SOEIC SORIR SOEIR ASCO receive error interrupt request flags SOCON SOREN ASCO receiver enable flag SSCTIC SSCRIC SSCTIR SSCRIR SSC transmit receive interrupt request flags SSCEIC SSCEIR SSC error interrupt request flag SSCCON SSCBSY SSC busy flag SSCCON SSCBE SSCPE SSC error flags SSCCON SSCRE SSCTE SSC error flags ADCIC ADEIC ADCIR ADEIR ADC end of conv overrun intr request flag ADCON ADST ADCRQ ADC start flag injection request flag CC311C CC16IC CC31IR CC16IR Fast external interrupt request flags TFR TFR 15 14 13 Class A trap flags TFR TFR 7 3 2 1 0 Class B trap flags P1H P1H 7 P1H 0 Those bits of PORT1 used for CAPCOM2 P8 P8 3 P8 0 All bits of Port 8 used for CAPCOM2 ISNC RTCIR Interrupt node sharing request flag XPOIC XP3IC XPOIR XP3IR CAN and PLL RTC interrupt request flags x 62 protected bits User s Manual 2 21 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Memory Organization 3 Memory Organization The memory space of the C164CM is configured in a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory areas including internal RO
455. pt service routine will not be entered until at least two instruction cycles have been executed of the interrupted program In most cases two instructions will be executed during this time Typically only one instruction will be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it reads an operand from internal code memory or if it is executed from the internal RAM Note A bus access in this context includes all delays which can occur during an external bus cycle User s Manual 5 21 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 6 PEC Response Times The PEC response time defines the time from the setting of an interrupt request flag of an enabled interrupt source to the start of the PEC data transfer The basic PEC response time for the C164CM is 2 instruction cycles Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 N 2 DECODE N 1 N PEC N 1 EXECUTE N 2 N 1 N PEC WRITEBACK N 3 N 2 N 1 N PEC Response Time IR Flag MCT04333 Figure 5 5 Pipeline Diagram for PEC Response Time In Figure 5 5 above the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of t
456. pt the same 4 KByte address range The size of the physical stack area within the internal RAM that is effectively used for standard stack operations is defined via bitfield STKSZ in register SYSCON see below Table 22 2 Circular Stack Address Transformation STKSZ Stack Size Internal RAM Addresses Words Significant Bits Words of Physical Stack of Stack Ptr SP 000g 256 00 FBFE 00 FAOO0 Default after Reset SP 8 SP 0 001g 128 00 FBFE O0 FBOO SP 7 SP 0 010g 164 00 FBFE 00 FB804 SP 6 SP O 011g 32 00 FBFE 00 FBCO SP 5 SP 0 100g 1512 00 FBFE 00 F800p not for 1 KByte IRAM SP 9 SP O 101g Reserved Do not use this combination 110g Reserved Do not use this combination 111g 512 OO FDFE j 00 FX00 Note No circular stack SP 11 SP 0 1024 00 FX00 represents the lower IRAM limit i e 1536 1 KB 00 FAO0 2 KB 00 F600 3 KB 00 F200 User s Manual 22 5 V1 0 2002 02 _ e e Infineon technologies C164CM C164SM Derivatives System Programming The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of the Stack Pointer register SP see Table 22 2 with the complementary most significant bits of the upper limit of the physical stack area OO FBFEj This transformation is done via hardware see Figure 22 1 The r
457. put signal may additionally be modulated by T12 or T13 For unmodulated active phases timer T12 must operate with 100 duty cycle that is its offset and compare registers must be cleared and T13 modulation must be off bits CMSELx3 must be cleared T12 modulation is effective when T12 s duty cycle is programmed below 100 T13 modulation is enabled via bits CMSELx3 see examples in Figure 17 10 Start Trigger De ede a CC60 COUT61 CC60 COUT60 COUT62 Unmodulated Modulated Modulated Active Phase by T12 by T13 The trigger that switches to the next phase may be a T12 overflow or a 1 being written to bit NMCS via software In block commutation mode the trigger is represented by a change in the input pattern on pins CC6POSx The shown waveforms are active high MCAO5114 Figure 17 10 Basic Five Phase Multi Channel Timing User s Manual 17 13 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Figure 17 10 shows the five phase output waveforms as an example For the other modes each passive phase is shortened or lengthened by one sequence phase respectively The compare output signals are enabled according to the intended multi phase mode Table 17 2 lists the required coding Table 17 2 Programming of Multi Channel PWM Outputs Multi Channel P
458. puts associated with timer T3 T3IN T3EUD are used to interface to an incremental encoder T3 is clocked by each transition on one or both of the external input pins to provide 2 fold or 4 fold resolution of the encoder input TSIN Edge To auxiliary Select Timers Tal Interrupt p Request T3IR Phase T3EUD Detect TSIN P5 3 TSEUD P5 2 MCB04000c Figure 10 6 Block Diagram of Core Timer T3 in Incremental Interface Mode Bitfield T3I in control register T3CON selects the triggering transitions see Table 10 6 In this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal T3 is modified automatically according to the speed and the direction of the incremental encoder and therefore its contents therefore always represent the encoder s current position Table 10 6 GPT1 Core Timer T3 Incremental Interface Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 stops 00 1 Any transition rising or falling edge on TSIN 010 Any transition rising or falling edge on T3EUD 011 Any transition rising or falling edge on any T3 input T3IN or T3EUD 1XX Reserved Do not use this combination User s Manual 10 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives General Purpose Timer Unit The incremental enc
459. qr S ese bc OR W ov sc tee es RE es 21 7 21 3 1 Output Pins Status During Power Reduction Modes 21 9 21 4 Slow Down Operation ax eee done acu eaa e Cn moe acit 21 11 21 5 Flexible Peripheral Management 2 000 ee eee eee 21 15 21 6 Programmable Frequency Output Signal suus 21 17 21 7 Security Mechanism uxicranace oo aden RR eine de x RR Ue ROT CR ROS 21 22 22 System Programming sllllle eese 22 1 22 1 Stack Operations sspe dees Rx DEOR REDE RE Chew ROC EE 22 4 22 2 Register Banking uu xem p rh xx REDE E RE RREEES Pe enews 22 9 22 3 Procedure Call Entry and Exit 0 0 0c cece eee eee 22 9 22 4 Table SOarcliriaese vse eienspevscedwe ted ESO RE FESSES Ee 22 12 22 5 Floating Point Support a 3 ward EUR hates Sele eR aD e Race 22 12 22 6 Peripheral Control and Interface liliis 22 13 22 7 Trap Interrupt Entry and Exit 0 000 eee 22 13 22 8 Inseparable Instruction Sequences 0000 0c eee eee 22 14 22 9 Overriding the DPP Addressing Mechanism 22 14 22 10 Handling the Internal Code Memory 0 0 00 eee eee 22 16 22 11 Pits Traps and Mines 0 ccc cee eee 22 18 23 HegISIer S t uei ne oh eo hes bend Rr ee yee eid we arn aH 23 1 23 1 Register Description Format 00 0c eee eee eee 23 1 User s Manual l 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives
460. quence Short Hardware Reset is indicated when the RSTIN input is sampled high inactive at the end of a hardware triggered internal reset sequence Software Reset is indicated after a reset triggered by the execution of instruction SRST Watchdog Timer Reset is indicated after a reset triggered by an overflow of the watchdog timer Note When bidirectional reset is enabled the RSTIN pin is pulled low for the duration of the internal reset sequence upon any sort of reset Therefore a long hardware reset LHWR will always be recognized in any case User s Manual 13 6 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Real Time Clock 14 Real Time Clock The Real Time Clock RTC module of the C164CM is basically an independent timer chain clocked directly with the oscillator clock It serves various purposes e System clock to determine the current time and date Cyclic time based interrupt e 48 bit timer for long term measurements Control Registers Data Registers Counter Registers Interrupt Control SYSCON2 E T14REL E ISNC E XP3IC E SYSCON2 Power Management Control Register RTCH Real Time Clock Register High Word T14REL Timer T14 Reload Register RTCL Real Time Clock Register Low Word T14 Timer T14 Count Register ISNC Interrupt Subnode Control Register XP3IC RTC Interrupt Control Register MCA04463 Figure 14 1 SFRs Associated with the RTC Module The RTC module consist
461. r MOV RO 0000H Move special control word MOV DPP3 OPDAT RO to data register MOV RO 0009H Select special OTP register MOV DPP3 OPCTRL RO for write access CALL MICROSEC 100 Keep the write signal low for 100 us MOV RO 000BH MOV DPP3 OPCTRL RO BCLR VPP ENABLE CALL MICROSEC 010 Trailing edge of write signal External progr voltage Off Let VPP settle for 10 us Read protection verify could be jw Gxecuted here MOV RO 0007H MOV DPP3 OPCTRL RO OTP module deselected User s Manual 3 19 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU 4 Central Processing Unit CPU Basic tasks of the Central Processing Unit CPU are to fetch and decode instructions to supply operands for the Arithmetic and Logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results As the CPU is the main engine of the C164CM microcontroller it is also affected by certain actions of the peripheral subsystem Because a four stage pipeline is implemented in the C164CM up to four instructions can be processed in parallel Most instructions of the C164CM are executed in one machine cycle 2 CPU clock periods due to this parallelism This chapter describes how the pipeline works for sequential and branch instructions in general and the hardware provisions which have been made to speed up execution of jump
462. r s Manual 15 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Bootstrap Loader Initial State in BSL Mode After entering BSL mode and the appropriate initialization the C164CM scans the RxDO line to receive a zero byte that is one start bit eight 0 data bits and one stop bit From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this baudrate an identification byte is returned to the host that provides the data to be loaded This identification byte identifies the device to be booted using the following codes 55 8xC 166 A5p Previous versions of the C167 obsolete B5 Previous versions of the C165 C54 C167 derivatives D5 4 All devices equipped with identification registers Note The identification byte D5 does not directly identify a specific derivative That information can be obtained from the identification registers When the C164CM has entered BSL mode the following configuration is automatically set values that deviate from the normal reset values are marked Watchdog Timer Disabled Register STKUN FCOO Context Pointer CP FAOO Register STKOV F600 Stack Pointer SP FA404 Register BUSCONO acc to startup config Register SOCON 80114 POH 3 TxDO T Register SOBG acc to 00 byte DPOH 3 T
463. r CMP13 Note For compare timer T13 only the output signal COUT63 in edge aligned mode is available Edge Aligned Mode Period value pv 1 Duty cycle of CC6x outputs 1 ae il x 100 Duty cycle of COUT6x outputs 1 e x 100 Center Aligned Mode Period value 2x pv Duty cycle of CC6x outputs Hee x 10096 Duty cycle of COUT6x outputs 1 pm x 100 User s Manual 17 9 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 4 Burst Mode In burst mode the output signal COUT63 of the 10 bit compare channel modulates the active phases of the output signals COUT6x of the three capture compare channels Burst mode is not possible on the CC6x outputs The modulating signal typically has a higher frequency than the modulated output channels Figure 17 8 shows an example for a waveform generated in burst mode Burst mode is enabled separately for each capture compare output by setting the respective bit CMSELx3 in register CC6MSEL Count Value Period Register T12 Compare Register T12 Start NE Time Active 0 l1 P Lo F Low CMSELx3 0 Burst Mode Active Disabled High AAAA AAAA AAAA AAAA AAAA AAAA Hs WVvVvVvvvvvvvvvvvvevvvvvevvv COUT63 HULU COUTXI 1 Sours LULL LULL COUTXI 0 Active Low MUUN LULL COUTXI 2 0 COUTE LLLI LLL COUTXI 1 Active High FULL LULL Figure 17 8 Operation in Burst Mode
464. r Special Function Registers 1024 Bytes of the address space are reserved The standard Special Function Register area SFR uses 512 bytes while the Extended Special Function Register area ESFR uses the other 512 bytes E SFRs are wordwide registers which are used for controlling and monitoring functions of the different on chip units Unused E SFR addresses are reserved for future members of the C166 microcontroller family with enhanced functionality Optional on chip OTP or ROM memory provides both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in only one machine cycle The ROM is mask programmed at the factory while the OTP memory can also be programmed within the application Program execution from on chip program memory is the fastest of all possible alternatives The type of the on chip program memory OTP ROM none depends on the chosen derivative User s Manual 2 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview External Bus Interface To meet the needs of designs where more memory is required than is provided on chip up to 64 KBytes of external RAM and or ROM can be connected to the C164CM microcontroller via its external bus interface The integrated External Bus Controller EBC allows very flexible access to external memory and or peripheral resources For up to fi
465. r its associated outputs can be disabled by setting bit TT12DIS or TT13DIS respectively For each individual T12 channel CC60 COUT62 the respective initial level can be driven during trap state by setting the associated bit s TRENx For the T13 output COUT63 no TREN bit is available so setting bit TT13DIS disables the trap function completely for this output Note When controlling inverters or electric motors the standard trap mode using P1L ensures safe operation all transistors off so in these cases bits TRENx and TTxDIS in register TRCON should be written with 0 only User s Manual 17 19 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM6 P1L i 5 me m 2 5 o Output Pin i 0 6 CC60 i COUT60 Init Value CC61 COUT61 cara p SS COUT63 T12 T13 TRENx x 0 Ru 5 Q Interrupt Request MCS04936 Figure 17 12 Trap Control Overview User s Manual 17 20 V1 0 2002 02 Infineon technologies 17 8 The CAPCOM6 register set provides a number of control data and status bits to control the operation of the two compare timers the generation of the output signals up to 7 and the combination of submodules for multi channel operation Note The register bits which are available in the full function module only not in the reduced version are marked This prov
466. r mode the PLL base frequency is divided by 2 fcpy 1 2 5 MHz If the oscillator clock fails while the PLL provides the basic clock the system will be supplied with the PLL base frequency anyway Using this PLL clock signal the CPU can either execute a controlled shutdown sequence bringing the system into a defined and safe idle state or it can provide an emergency operation of the system with reduced performance based on this normally slower emergency clock Note The CPU clock source is switched back to the oscillator clock only after a hardware reset The Oscillator Watchdog can be disabled by setting bit OWDDIS in register SYSCON In this case the PLL remains idle and provides no clock signal while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD Also no interrupt request will be generated in case of a missing oscillator clock Note At the end of an external reset bit OWDDIS reflects the inverted level of pin RD at that time Thus the Oscillator Watchdog may also be disabled via hardware by externally pulling the RD line low upon a reset in a manner similar to the standard reset configuration via PORTO The oscillator watchdog cannot provide full security while the CPU clock signal is generated by the SlowDown Divider because the OWD cannot switch to the PLL clock in this case see Figure 6 4 OWD interrupts are only recognizable if fosc is still available for instance the
467. r or not a multiplication or division must be continued after the end of an interrupt service The MULIP bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again afterwards User s Manual 4 18 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Note The MULIP flag is part of the task environment When the interrupting service routine does not return to the interrupted multiply divide instruction as in the case of a task scheduler which switches between independent tasks the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows interrupts to be globally enabled IEN 1 or disabled IEN 0 The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware on entry into an interrupt service routine but it can also be modified via software to prevent other interrupts from being acknowledged If an interrupt level 15 has been assigned to the CPU it has the highest possible priority thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details refer to Chapter 5
468. ransitions are required such as buses In Medium Driver Mode not all transistors are activated In this case the driver provides a reduced output current supporting applications with moderate requirements for current or speed while improving the EME behavior In Weak Driver Mode only a small transistor is activated In this case the driver may drive not time critical logic loads while switching noise is greatly reduced Edge Characteristic This defines the turn on speed of the main driver stage that is the shape of the respective output Soft edges reduce the peak currents drawn when changing the voltage level of an external capacitive load For a bus interface however sharp edges may still be required Edge characteristic affects the pre driver which controls the final output driver stage Note If Weak Driver Mode is selected additional edge shaping makes no sense and therefore is not supported User s Manual 7 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports The Port Output Control registers POCONXx provide the corresponding control bits For each group of four pins that is for each port nibble a 4 bit control field is provided Word ports consume four control nibbles each byte ports consume two control nibbles each where each control nibble controls 4 pins of the respective port The general register layout shown below is valid for all POCON registers Please note th
469. register BFLDH SYSCON2 03H 01H CLKCON 01B gt SDD frequency PLL on T 1 EXIT SLOWDOWN Currently running on SDD frequency MOV SYSCON2 ZEROS Clear bits 3 0 no EXTR required here EXTR 4H Switch to ESFR space and lock sequence BFLDL SYSCON2 0FH 09H Unlock sequence step 1 1001B MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to one locked register BFLDH SYSCON2 03H 00H CLKCON 00B basic frequency klx User s Manual 21 23 V1 0 2002 02 oe Infineon technologies C164CM C164SM Derivatives Examples where the PLL is disabled ENTER SLOWDOWN EXTR 1H BCLR ISNC 2 MOV SYSCON2 ZEROS EXTR 44H BFLDL SYSCON2 0FH 09H MOV SYSCON2 10003H BSET SYSCON2 2 BFLDH SYSCON2 03H 02H SDD EXIT AUTO MOV SYSCON2 ZEROS EXTR 4H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 00H EXTR 1H BSET ISNC 2 User s Manual d Power Management Currently running on basic clock frequ Next access to ESFR space PLLIE 0 i e PLL interrupt disabled Clear bits 3 0 no EXTR required here Switch Unlock Unlock Unlock Single f to ESFR space and lock sequence sequence step 1 1001B sequence step 2 0011B sequence step 3 0111B access to one locked register CLKCON 10B gt SDD frequency PLL ofr Currently running on SDD frequency Clear bits 3
470. requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled After the RETI Retum from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction If the interrupt request cannot be serviced because the priority is too low or the interrupt system is globally disabled the CPU immediately resumes normal program execution with the instruction following the IDLE instruction For a request programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode If the PEC request cannot be serviced because the priority is too low or the interrupt system is globally disabled the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction User s Manual 21 4 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Power Management Denied CPU Interrupt Request
471. ress Addr Value BUSCON4 b FF1A 8D Bus Configuration Register 4 0000 ZEROS b FF1Cj 8E Constant Value 0 s Register read only 00004 ONES b FF1Ej 8F Constant Value 1 s Register read only FFFF T78CON b FF204 90 CAPCOM Timer 7 and 8 Ctrl Reg 00004 CCM4 b FF22 914 CAPCOM Mode Control Register 4 0000 CCM5 b FF24 924 CAPCOM Mode Control Register 5 00004 CCM6 b FF26 934 CAPCOM Mode Control Register 6 00004 CCM7 b FF28 94 CAPCOM Mode Control Register 7 00004 CTCON b FF30 984 CAPCOM 6 Compare Timer Ctrl Reg 10104 CC6MCON b FF324 99 CAPCOM 6 Mode Control Register 00FF44 TRCON b FF34 9A CAPCOM 6 Trap Enable Ctrl Reg OOXXy CC6MIC b FF36 9B CAPCOM 6 Mode Interrupt Ctrl Reg 0000 T2CON b FF40 AO GPT1 Timer 2 Control Register 00004 T3CON b FF4244 Al GPT1 Timer 3 Control Register 0000 T4CON b FF444 A24 GPT1 Timer 4 Control Register 00004 T2IC b FF60 BO GPT1 Timer 2 Interrupt Control Register O000 T3IC b FF624 Bi GPT1 Timer 3 Interrupt Control Register 0000 T4IC b FF64 B2 GPT1 Timer 4 Interrupt Control Register 0000 SOTIC b FF6C4 B6 Serial Channel 0 Transmit Interrupt 0000 Control Register SORIC b FF6E B7 Serial Channel 0 Receive Interrupt 0000 Control Register SOEIC b FF70g B8 Serial Channel 0 Error Interrupt Ctrl 0000 Reg SSCTIC b FF72 B9 SSC Transmit Interrupt Control Register O000 SSCRIC b FF744 BA SSC Receive Interr
472. revent repeated interrupt requests A Receive Error Master or Slave mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is irretrievably lost A Phase Error Master or Slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes between one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 that is it either is more than double or less than half the expected baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the error interrupt request flag SSCEIR Using this error detection capability requires the slave s baud rate generator to be programmed to the same baud rate as the master device This feature detects false additional pulses or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit SSCAREN 1 an a
473. rnal ROM can be made by any instruction which is executed from any location outside the on chip mask ROM including IRAM XRAM and external memory A program cannot branch to a location within the protected ROM from outside This applies to JUMPs as well as to RETurns A called routine within RAM or external memory can never return to the protected ROM The fetched code will be replaced by the default value 009Bj for any access to any location This default value will be decoded as the instruction TRAP 00 which will restart program execution at location 00 0000 Note ROM protection may be used for applications where the complete software fits into the on chip ROM or where the on chip ROM holds initialization software which is then replaced by external application software for example In the latter case no data constants tables etc can be stored within the ROM The ROM itself should be mapped to segment 1 before branching outside so an interrupt vector table can be established in external memory User s Manual 3 11 V1 0 2002 02 _ e e Infineon technologies 3 6 C164CM C164SM Derivatives OTP Memory Programming Memory Organization During normal operation the One Time Programmable OTP memory appears like a standard ROM In the special OTP programming modes however the OTP memory can be programmed by writing to its special programming interface Programming is executed in units of 16 bit words and each
474. rnal code memory or when N is a call return trap or MOV Rn Rm data16 instruction the minimum PEC response time may additionally be extended by 2 state times during internal code memory program execution nthe case that instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 state times The worst case PEC response time during internal code memory program execution adds to 9 state times 18 TCL Any reference to external locations increases the PEC response time due to pipeline related access priorities The following conditions must be considered e Instruction fetch from an external location Operand read from an external location e Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N and N 1 are executed out of external memory instructions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the PEC response time is the time to perform 7 word bus accesses e When instructions N and N 1 are executed from external memory but all operands for instructions N
475. rnal memory or peripheral This means that the registers of the CAN module can be read and written using 16 bit or 8 bit direct or indirect MEM addressing modes Bit handling is not supported via the XBUS Since the XBUS to which the CAN module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream Accesses to the CAN module use demultiplexed addresses a 16 bit data bus byte accesses are possible two waitstates and no tristate waitstate The CAN address area starts at 00 EF00 and covers 256 Bytes This area is decoded internally so none of the programmable address windows must be sacrificed in order to access the on chip CAN module The advantage of locating the CAN address area in segment 0 is that the CAN module is accessible via data page 3 This is the system data page accessed usually through the system data page pointer DPP3 In this way internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data page and form a contiguous address space Power Down Mode If the C164CM enters Power Down mode the XCLK signal will be turned off This stops the operation of the CAN module thus any message transfer is interrupted To ensure that the CAN co
476. rol Port 5 pins may be used for either digital or analog input By setting the respective bit in register P5DIDIS the digital input stage of the respective Port 5 pin can be disconnected from the pin This is recommended when the pin is to be used as analog input as it reduces the current through the digital input stage and prevents it from toggling while the analog input level is between the digital low and high thresholds Thus the consumed power and the generated noise can be reduced After reset all digital input stages are enabled User s Manual 7 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports P5DIDIS P5 Dig Inp Disable Reg SFR FFA4 D2 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P5D P5D P5D P5D P5D P5D P5D P5D T4 6 5 4 3 2 1 0 7 rw rw rw rw rw rw rw rw Bit Function P5D y Port P5 Bit y Digital Input Control 0 Digital input stage connected to port line P5 y jh Digital input stage disconnected from port line P5 y When being read or used as alternate input this line appears as 1 Port 5 pins have a special port structure see Figure 7 10 for two reasons First because it is an input only port second because the analog input channels are connected directly to the pins rather than to the input latches Internal Bus lt z x
477. rt 4 This reduces the pin count ntroduction of Port 20 adds IO functionality to several formerly dedicated pins which can now also be used by single chip mode applications e On chip Program Memory OTP ROM supports development and volume production of single chip applications Cutting features only where required moving vital functions to the remaining pins adding new features such as configuration via software maintaining the basic architecture on chip PLL 16 bit CPU PEC interrupt controller memory concept keeping powerful industry standard peripheral modules such as CAPCOM6 and CAN resulted in a compact member of Infineon s C166 Family of 16 bit microcontrollers which fits to a board space of merely 1 44 cm 0 223 inch at a package body size of just 1 0 cm 0 155 inch User s Manual 2 2 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 2 Basic CPU Concepts and Optimizations The main core of the CPU consists of a four stage instruction pipeline a 16 bit Arithmetic and Logic Unit ALU and dedicated Special Function Registers SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter SYSCON Context Ptr BUSCON 0 BUSCON 1 BUSCON BUSCON BUSCON ADDRSEL 4 I i i Data Page Ptr 4 Code Seg Ptr SS I I I Internal l RAM KOV DL T Exec
478. ructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction This allows construction of locked sequences longer than 4 instructions Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked sequence User s Manual 22 15 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming 22 10 Handling the Internal Code Memory The Mask ROM OTP Flash versions of the C164CM provide on chip code memory that may store code as well as data The lower 32 KBytes of this code memory are referred to as the internal ROM area Access to this internal ROM area is controlled during the reset configuration and via software The ROM area may be mapped to segment O to segment 1 or the code memory may be disabled Note The internal ROM area always occupies an address area of 32 KBytes even if the implemented mask ROM OTP Flash memory is smaller than that such as 8 KBytes Of course the total implemented memory may exceed 32 KBytes Code Memory Configuration During Reset The control input pin EA External Access enables the user to define the address area from which the first instructions after reset are fetched When EA is low 0 during reset the internal code memory is disabled and the firs
479. s Enabling of XBUS Peripherals After reset all on chip XBUS peripherals are disabled In order to be usable an XBUS peripheral must be enabled via the global enable bit XPEN in register SYSCON Table 9 5 summarizes the XBUS peripherals and also the number of waitstates which are used when accessing the respective peripheral Table 9 5 XBUS Peripherals in the C164CM Associated XBUS Peripheral Waitstates CAN1 2 Visible Mode The C164CM can mirror on chip access cycles to its XBUS peripherals so these accesses can be observed or recorded by the external system This function is enabled via bit VISIBLE in register SYSCON Accesses to XBUS peripherals also use the EBC Due to timing constraints the address bus will change for all accesses using the EBC Note As XBUS peripherals use demultiplexed bus cycles the respective address is driven on PORT in visible mode even if the external system uses MUX buses only If visible mode is activated accesses to on chip XBUS peripherals including control signals RD WR are mirrored to the bus interface Accesses to internal resources program memory IRAM GPRs do not use the EBC and cannot be mirrored to outside If visible mode is deactivated however no control signals RD WR will be activated that is there will be no valid external bus cycles Note Visible mode can only work if the external bus is enabled at all 9 6 2 External Accesses to XBUS Peripherals The
480. s x 7 0 00 FCFE H 00 FCFE H 00 FCFCH 00 FCE0 H 00 FCDE 4 PEC Source and Destination Internal Pointers RAM 00 FCE2 H 00 F600 H 00 FCEO y 00 F5FE y MCD03903 Figure 3 4 Location of the PEC Pointers Whenever a PEC data transfer is performed the pair of source and destination pointers selected by the specified PEC channel number is accessed independently of the current DPP register contents The locations referred to by these pointers are accessed independently of the current DPP register contents as well If a PEC channel is not used the corresponding pointer locations are available and can be used for word or byte data storage For more details on the use of the source and destination pointers for PEC data transfers see Chapter 5 User s Manual 3 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Memory Organization Special Function Registers The functions of the CPU the bus interface the IO ports and the on chip peripherals of the C164CM are controlled via a number of Special Function Registers SFRs These SFRs are arranged within two areas of 512 Bytes each The first register block the SFR area is located in the 512 Bytes above the Internal RAM 00 FFFFy OO FE00 The second register block the Extended SFR ESFR area is located in the 512 Bytes below the Internal RAM 00 F1FFy 00 F000 Special Function Registers can be addr
481. s cycles access the same address window Only if the following cycle accesses a different window is a waitstate inserted between the last access to the previous window and the first access to the new window After reset no BUSCON switch waitstates are selected User s Manual 9 7 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface External Data Bus Width The EBC can operate on 8 bit or 16 bit wide external memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus uses only POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memory cost at the expense of transfer time The EBC can control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus read cycles Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses where the low byte is accessed first then the high byte The assembly of bytes into words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 bit data bus require that the upper and lower half of the memory can be accessed individually Because of the lack of the BHE signal the C164CM cannot select individual bytes on external resources When reading bytes from an external 16 bit device whole words may be read and the C164CM automatically selects the byte to be input and dis
482. s of a chain of 3 divider blocks a fixed 8 1 divider the reloadable 16 bit timer T14 and the 32 bit RTC timer accessible via registers RTCH and RTCL Both timers count upwards The clock signal for the RTC module is derived directly from the on chip oscillator frequency not from the CPU clock and is fed through a separate clock driver It is therefore independent from the selected clock generation mode of the C164CM and is controlled by the clock generation circuitry Table 14 1 RTC Register Location within ESFR Space Register Long Short Reset Notes Name Address Value T14 FOD2y 69 UUUU Prescaler timer generates input clock for RTC register and periodic interrupt T14REL FODO 684 UUUU Timer reload register RTCH FOD6 6B UUUU High word of RTC register RTCL FODAy 6Ay UUUU Low word of RTC register User s Manual 14 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Real Time Clock Note The RTC registers are not affected by a reset After a power on reset however they are undefined TI4REL Interrupt Request MCD04432 Figure 14 2 RTC Block Diagram System Clock Operation A real time system clock can be maintained that keeps on running also during idle mode and power down mode optionally and indicates the current time and date This is possible because the RTC module is not affected by a reset The maximum resolution
483. safe and robust operation of the sleep wakeup mechanism in an active environment 100 ns 10ns Signal Interrupt Request Rejected Recognized MCD04456 Figure 5 6 Input Noise Filter Operation User s Manual 5 30 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 9 Trap Functions Traps interrupt current execution in a manner similar to standard interrupts However trap functions offer the possibility to bypass the interrupt system s prioritization process for cases in which immediate system reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The C164CM provides two different kinds of trapping mechanisms Hardware Traps are triggered by events that occur during program execution such as illegal access or undefined opcode Software Traps are initiated via an instruction within the current execution flow Software Traps The TRAP instruction causes a software call to an interrupt service routine The trap number specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000 through 00 01FC will be branched to Executing a TRAP instruction causes an effect similar to the occurrence of an interrupt at the same vector PSW CSP in segmentation mode and IP are pushed on the internal sys
484. see Figure 20 3 This allows the complete configuration of the controller including its on chip peripheral units before releasing the reset signal for the external peripherals of the system Note RSTOUT remains active low when Port 20 is initially enabled The output level can be changed to high or the pin can be switched to input via the port control registers P20 and DP20 RSTOUT will float during emulation mode or adapt mode The Internal RAM after Reset The contents of the internal RAM are not affected by a system reset However after a power on reset the contents of the internal RAM are undefined This implies that the GPRs R15 RO and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM are also unchanged after a warm reset software reset or watchdog reset but are undefined after a power on reset Operation after Reset After the internal reset condition is removed the C164CM fetches the first instruction from the program memory location 00 0000 for a standard start As a rule this first location holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note If the Bootstrap Loader Mode was activated during a hardware reset the C164CM does not fetch instructions from the program memory The standard bootstrap loader expects data via serial interface ASCO User s Manual 20 8 V1 0 2002 02 _
485. set these bits to 1 so they are already in the correct state when switching between master and slave modes User s Manual 12 12 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface 12 5 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability This permits baud rate generation independent from the timers The baud rate generator is clocked with the CPU clock divided by 2 fcpu 2 The timer counts downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload register Reading SSCBR while the SSC is enabled returns the contents of the timer Reading SSCBR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value for a given baudrate fcpu fcpu Bssc gt SSCBR C Z oer Bx lt SSCBR gt 1 5 x Baudrategsc lt SSCBR gt represents the contents of the reload register taken as an unsigned 16 bit integer Table 12 2 lists some possible baud rates together with the required reload values and the resulting bit times for different CPU clock
486. sfer is done automatically if bit CTRES12 13 is set otherwise those latch values are not transferred Note If a new compare value is written to the shadow latches while T12 is counting up the new value must be smaller than the current period value Otherwise no more matches will be detected and the output signals will no longer change If a compare value is written while T12 is counting down any value may be used User s Manual 17 22 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 CTCON Compare Timer Control Reg SFR FF30 98 Reset Value 10104 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CT13 ECT STE CT13 CT13 STE CT12 CT12 P 130 13 RES R CT13CLK CTM ETRP 12 RES R CT12CLK wh rw wh mw rw rw w w wh w rw rw Bit Function CTnCLK Compare Timer Tn Input Clock Select Selects the input clock for timer T12 or T13 derived from the CPU clock frx fopy o CTnCLK 000 fr fcpu 111 Ti fcPU 128 CTnR Compare Timer Tn Run Bit CTnR starts and stops timer Tn T12 or T13 Together with bit CTnRES it controls Tn s operation 0 Timer Tn stops counting If bit CTnRES 1 timer Tn is cleared and the compare outputs are set to their defined idle state jh Timer Tn starts counting from its current value CTnRES Compare Timer Tn Reset Control 0 No effect on timer Tn when it is stopp
487. size see Table 9 3 For a given window size only those upper address bits of the start address are used marked R which are not implicitly used for addresses inside the window The lower bits of the start address marked x are disregarded Table 9 3 Address Window Definition Bit field RGSZ Resulting Window Size Relevant Bits R of Start Addr A12 0000 4 KByte RRRRRRRRRRRR 0001 8 KByte RRRRRRRRRRR OX 0010 16 KByte RRRRRRRRRR xX x 0011 32 KByte RRRRRRRR RX XX 0100 64 KByte RRRRRRRRX X X X 0101 128 KByte RR RRRRRX X X X X 0110 256 KByte RR RRRRX X X X X X 0111 512 KByte RR RRRxX X X X X X X 1000 1 MByte R RR RX X X X X X X X 1001 2 MByte RR RX X X X X X X X X 1010 4 MByte R RX X X X X X X X X X 1011 8 MByte HX X X X X X X X X X x 11xx Reserved User s Manual 9 20 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Address Window Arbitration The address windows which can be defined within the address space of the C164CM may partly overlap each other Thus for example small areas may be cut out of bigger windows in order to effectively utilize external resources especially within segment O For each access the EBC compares the current address with all address select registers programmable ADDRSELx and hardwired XADRSx This comparison is done in four priority levels Priority 1 Priority 2 Priority 3 Priority 4 The hardwir
488. sociated with the respective interrupt source This allows direct identification of the source which caused the request The only exceptions are the Class B hardware traps all of which share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the C164CM s address space segment 0 The jump table consists of the appropriate jump instructions which transfer control to the interrupt or trap service routines and which may be located anywhere within the address space The entries of the jump table are located at the lowest addresses in code segment 0 of the address space Each entry occupies two words except for the reset vector and the hardware trap vectors which occupy four or eight words Table 5 1 lists all sources capable of requesting interrupt or PEC service in the C164CM the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags The mnemonics consist of a part which specifies the respective source followed by a part which specifies its function IR Interrupt Request flag IE Interrupt Enable flag Note
489. ster SFR FF04 82 Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1L PAL PAL PiL Pil P1L PiL P1L d 6 5 4 3 2 1 0 x rw rw rw rw rw rw rw rw P1H PORT1 High Register SFR FF06 83 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1H P1H P1H P1H P1H P1H P1H P1H i 6 5 4 3 2 d 0 E z rwh rwh rwh rwh rwh rwh rwh rwh Bit Function P1X y Port data register P1H or P1L bit y User s Manual 7 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports DP1L P1L Direction Ctrl Register ESFR F104 824 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP L 7 L 6 L 5 L 4 L 3 L 2 L 1 L O rw rw rw rw rw rw rw rw DP1H P1H Direction Ctrl Register ESFR F106 83 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP1 H 7 H 6 H 5 H 4 H 3 H 2 H 1 H O zo 0 o omo om o o2 o IN IW IW IW IW IW Bit Function DP1X y Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y
490. store the allocated local space back to the system stack Note The system stack grows downward while the register bank grows upward User s Manual 22 10 V1 0 2002 02 eo Infineon technologies C164CM C164SM Derivatives System Programming Old Stack Area Newly Allocated Register Bank Old CPContents New Stack Area MCA04409 Figure 22 2 Local Registers The software to provide the local register bank for the example shown in Figure 22 2 is very compact After entering the subroutine SUB SP 10D Free 5 words in the current system stack SCXT CP SP Set the new register bank pointer Before exiting the subroutine POP CP Restore the old register bank ADD SP 10D Release the 5 words 0f the current system stack User s Manual 22 11 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives System Programming 22 4 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease th
491. t Pointer CSP cannot be accessed directly at all They can be changed only indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Note that any explicit write request via software to an SFR supersedes a simultaneous modification by hardware of the same register Note Any write operation to a single byte of an SFR clears the non addressed complementary byte within the specified SFR Non implemented reserved SFR bits cannot be modified and will always supply a read value of 0 User s Manual 4 12 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU System Configuration Register SYSCON This bit addressable register provides general system configuration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset see hardware effectable bits SYSCON System Control Register SFR FF12 89 Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD ROM SGT ROM CLK OWD VISI STKSZ 1 DIS EN EN pis RST XPEN BLE rw rw rw mh rw wh rw rw rw Bit Function VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally a XBUS peripheral accesses are made visible on the external
492. t Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ES NM MC CS CM CM CM SEL CMSEL2 SEL CMSEL1 SEL CMSELO 23 13 03 rw rw rw rw rw rw rw rw Bit Function CMSELn Capture Compare Mode Selection These bitfields select enable the operating mode and the output input pin configuration of the 16 bit capture compare channels Each channel can be programmed individually either for compare or capture operation 000 Compare outputs disabled CC6n COUT6n can be used for IO 001 Compare output on pin CC6n COUT6n can be used for IO 010 Compare output on pin COUT6n CC6n can be used for IO 011 Compare output on pins COUT6n and CC 6n 100 Capture mode not triggered by CC6n COUT6n is IO 101 Capture mode trigg d by a rising edge on CC6n COUTEn is IO 110 Capture mode trigg d by a falling edge on CC6n COUTEn is IO 111 Capture mode trigg d by any transition on CC6n COUTEn is IO CMSELn3 COUTEn Control by Timer T13 in Compare Mode This bit determines if the output COUT6n is modulated during its active phase defined via register CC6MCON by the output signal of the 10 bit compare channel typically a higher frequency signal 0 COUTEn drives its active level 1 COUTEn is modulated by the output signal of the 10 bit compare channel NMCS Next Multi Channel PWM State Valid when ESMC 1 0 Idle 1 Select the nex
493. t follower state in the 4 5 6 phase multi channel PWM modes NMCS is reset by hardware in the next clock cycle after it has been set ESMC Enable Software Controlled Multi Channel PWM Modes Defines the follower state selection in the 4 5 6 phase multi channel PWM modes 0 Follower state selection controlled by compare timer T12 1 Follower state selection controlled by bit NMCS software control User s Manual 17 29 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 CC6MIC CAPCOMSG Interrupt Ctrl Reg SFR FF36 9B Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FC CT12 CT12 CC2 CC2 CC1 CC1 CCO CCO EC EC CC2 CC2 CC1 CC1 CCO CCo FP FIR F R F R TP TC FEN REN FEN REN FEN REN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function CCnREN Capture Compare Rising Edge Interrupt Enable 0 Rising edge interrupt disabled 1 An interrupt from request flag CCnR is enabled CCnFEN Capture Compare Falling Edge Interrupt Enable 0 Falling edge interrupt disabled 1 An interrupt from request flag CCnF is enabled ECTC Enable Timer T12 Count Direction Change Interrupt 0 Count direction change interrupt disabled 1 An interrupt from request flag CT12FC is enabled Note No effect in edge aligned mode ECTP Enable Timer T12 Period Interrupt 0
494. t function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period To use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 3 this port pin must be configured as output the corresponding direction control bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 3 the port latch is set upon a compare event and cleared upon a timer overflow see Figure 16 9 However when compare value and reload value for a channel are equal the respective interrupt requests will be generated Only the output signal is not changed in this case set and clear would coincide Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In such a case the hardware triggered change will not become effective Only capture compare channels 16 19 and 24 31 are connected to pins capture compare channels 16 19 and
495. t instructions are fetched from external memory When EA is high 1 during reset the internal code memory is globally enabled and the first instructions are fetched from the internal memory Note Be sure not to select internal memory access after reset on ROMless devices Mapping the Internal ROM Area After reset the internal ROM area is mapped into segment 0 the system segment 00 0000 00 7FFF 4 as a default This is necessary to allow the first instructions to be fetched from locations 00 0000 ff The ROM area may be mapped to segment 1 01 0000 01 7FFFj by setting bit ROMS1 in register SYSCON The internal ROM area may now be accessed through the lower half of segment 1 while accesses to segment O will now be made to external memory This adds flexibility to the system software The interrupt trap vector table which uses locations 00 0000 through 00 01F Fy is now part of the external memory and may therefore be modified that is to say the system software may now change interrupt trap handlers according to the current condition of the system The internal code memory can still be used for fixed software routines such as IO drivers math libraries application specific invariant routines tables etc This combines the advantage of an integrated non volatile memory with the advantage of a flexible adaptable software system User s Manual 22 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Deri
496. t interrupt sources are controlled individually by their specific interrupt control registers IC Thus the acceptance of requests by the CPU is determined by both the individual interrupt control registers and by the PSW PEC services are controlled by the respective PECCx register and by the source and destination pointers which specify the task of the respective PEC service channel 5 1 1 Interrupt Control Registers All interrupt control registers are organized identically The lower 8 bits of an interrupt control register contain complete interrupt status information for the associated source which is required for one round of prioritization the upper 8 bits of the respective register are reserved All interrupt control registers are bit addressable and all bits can be read or written via software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control registers through instructions which operate on word data types their upper 8 bits 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each xxIC register where xx represents the mnemonic for the respective source User s Manual 5 5 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions mi Control Register E SFR yyyyu
497. t pins see description above User s Manual 12 9 V1 0 2002 02 o Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface 12 2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device and the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations As in full duplex mode there is an easy way to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver Because the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By these means any corruptions on the common data exchange line are detected if the received data is not equal to the transmitted data Master Device 1 Device 2 Slave Shift Register Common Transmit Receive Device 3 Slave Line MCS01965 Figure 12 5 SSC Half Duplex Configuration User s Manual 12 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies
498. t s 1 56 Mbit s 2 06 Mbit s 00074 800 kbit s 1 0 Mbit s 1 25 Mbit s 1 65 Mbit s 0009 100 kbit s 125 kbit s 156 kbit s 206 X kbit s 004F 80 kbit s 100 kbit s 125 kbit s 165 kbit s 0063 64 kbit s 80 kbit s 100 kbit s 132 kbit s 007C 48 5 kbit s 60 6 kbit s 75 8 kbit s 100 kbit s 00A44 1 0 kbit s 1 25 kbit s 1 56 kbit s 2 06 kbit s 1F3Fj 800 bit s 1 0 kbit s 1 25 kbit s 1 65 kbit s 270Fy 640 bit s 800 bit s 1 0 kbit s 1 32 kbit s 30D3y 122 1 bit s 152 6 bit s 190 7 bit s 251 7 bit s FFFF User s Manual 12 14 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface 12 6 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and Baudrate Error apply only to slave mode When an error is detected the respective error flag is set When the corresponding Error Enable Bit is set an error interrupt request will also be generated by setting SSCEIR see Figure 12 6 The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically like SSCEIR but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to p
499. t which is required for startup e g flash memory Bidirectional reset reflects internal reset sources software watchdog to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON and changes RSTIN from a pure input to an open drain IO line When an internal reset User s Manual 8 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Dedicated Pins is triggered by the SRST instruction or by a watchdog timer overflow or by application of a low level to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence It is released afterwards and is then controlled by the external circuitry alone The bidirectional reset function is useful for applications in which external devices require a defined reset signal but cannot be connected to the C164CM s RSTOUT signal e g an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT The following behavior differences must be observed when using the bidirectional reset feature in an application e Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset The reset indication flags always indicate a long hardware reset The PORTO configuration is treated like on a hardware reset In partic
500. tandard trap level for timer T13 controlled output P1L 12 Trap function for timer T13 controlled output is disabled TRENx Trap Enable for Output Pins 0 Trap function for the respective output is disabled 1 Trap level is initial value for the respective output if the standard trap level from P1L is disabled by bot TT12DIS 1 TRF Trap Flag TRF is set by hardware if the trap function is enabled TRPEN 1 and CTRAP becomes active low If enabled an interrupt is generated when TRF is set TRF must be cleared by software TRPEN External CTRAP Trap Function Enable Bit 0 External trap input CTRAP is disabled default after reset T External trap input CTRAP is enabled Note For applications driving inverters or electric motors the standard trap mode using P1L provides maximum safety It is therefore recommended to keep bits TRENx and TT12DIS cleared only write 0 to those bit locations User s Manual 17 25 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives CC6MCON Capture Compare Unit CAPCOM6 CAPCOMSG Mode Ctrl Reg SFR FF32 99 Reset Value O0FF 12 11 10 9 8 7 6 5 4 3 2 1 0 EB BC BC COUT COUTICOUT COUT COUT CE ERR EN BOM ar xt 21 CC2l ap CCT gp CCOI rw w w rw w rw rw rw rw rw rw rw Bit Function CCnl Compare Output CC6n Initial Value n 0 2 The compare output CC6n drives th
501. te bank pointer is used as the operand for the SCXT switch context instruction Upon exit from a task a simple POP instruction to the Context Pointer CP restores the previous task s register bank 22 3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines The CALL and RET instructions store and restore the value of the Instruction Pointer IP on the system stack before and after a subroutine is executed Procedures may be called conditionally with instructions CALLA or CALLI or may be called unconditionally using instructions CALLR or CALLS Note Any data pushed onto the system stack during execution of the subroutine must be popped before the RET instruction is executed Passing Parameters on the System Stack PUSH instructions may be used to pass parameters via the system stack before the subroutine is called POP instructions may be used during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine Indirect addressing provides a mechanism for accessing data referenced by data pointers which are passed to the subroutine Additionally two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead The PCALL push and call i
502. te cycle 4 Data drivers are disabled in a multiplexed normal write cycle Figure 9 9 Read Write Signal Duration Control User s Manual 9 14 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 4 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features such as segmentation and internal ROM mapping are controlled via register SYSCON Bus cycle properties such as length of ALE external bus mode read write delay and waitstates are controlled via registers BUSCON4 BUSCONO Four of these registers BUSCON4 BUSCON1 have an address select register ADDRSEL4 ADDRSEL1 associated with them This allows specifying up to four address areas and the individual bus characteristics within these areas All accesses not covered by these four areas are then controlled via BUSCONO This allows memory components or peripherals to be used with different interfaces within the same system while optimizing accesses to each of them SYSCON System Control Register SFR FF12 89 Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD ROM SGT ROM CLK OWD VISI STKSZ 1 DIS EN EN DIS RST XPEN BLE rw rw rw mh rw wh rw rw rw Bit Function VISIBLE v Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS perip
503. ted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest to the user The remaining portions of the MDC register are reserved for dedicated use by the hardware and should never be modified by the user in any way other than described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in Chapter 22 User s Manual 4 32 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware This register can be read only Register ZEROS can be used as a register addressable constant of all zeros i e for bit manipulation or mask generation It can be accessed via any instruction capable of addressing an SFR ZEROS Zeros Register SFR FF1C 8bE Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r Constant Ones Register ONES All bits of this bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register addressable constant of all ones for bit manipulatio
504. tem stack and a jump is taken to the specified vector location When segmentation is enabled and a trap is executed the CSP for the trap service routine is set to code segment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modified by the TRAP instruction so the service routine is executed on the same priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap Hardware Traps Hardware traps are issued by faults or specific system states which occur during runtime of a program not identified at assembly time A hardware trap may also be triggered intentionally for example to emulate additional instructions by generating an Illegal Opcode trap The C164CM distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either completed or cancelled i e it has no effect on the system state before the trap handling routine is entered Hardware traps are non maskable and always have prior
505. ternal Host Mode external host EHM 0110 Reserved Do not select this configuration 0101 Reserved Do not select this configuration 0100 Reserved Do not select this configuration 00 XxX Reserved Do not select this configuration The On Chip Bootstrap Loader allows the start code to be moved into the internal RAM of the C164CM via the serial interface ASCO The C164CM will remain in bootstrap loader mode until a hardware reset deselects BSL mode or until a software reset Default The C164CM starts fetching code from location 00 0000 the bootstrap loader is off User s Manual 20 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Reset External Bus Type Pins POL 7 and POL 6 BUSTYP select the external bus type during reset if an external start is selected via pin EA This allows configuration of the external bus interface of the C164CM even for the first code fetch after reset The two bits are copied into bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 controls the address output multiplexed or demultiplexed This bit field may be changed via software after reset if required Table 20 3 Configuration of External Bus Type POL 7 6 BTYP External Data Bus Width External Address Bus Mode Encoding 00 8 bit Data Demultiplexed Addresses 01 8 bit Data Multiplexed Addresses 10 16 bit Data Demultiplexed Addresses 11 16 bit D
506. terrupt Control annaa ccc eee eens 11 15 12 High Speed Synchronous Serial Interface 12 1 12 1 Full Duplex Operation 00000 cee ee eens 12 7 12 2 Half Duplex Operation 0 0 et eee 12 10 12 3 Continuous Transfers 0 6c cece ees 12 11 12 4 POM COMMON 22 2 seks aree mei bea cee eed ee ease de te haved ax 12 12 User s Manual 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Table of Contents Page 12 5 Baud Rate Generation 00 0 cee eee 12 13 12 6 Error Detection Mechanisms 00000 0c e eee eee 12 15 12 7 SSC Interrupt Control shcseks sie diete Ee needs bee 64 Rote esd 12 17 13 Watchdog Timer WDT 0 000 eee 13 1 13 1 Operation of the Watchdog Timer 0 00 eee eee eee 13 3 13 2 Reset Source Indication s c xoc dei sul re sre cad ES eek eee 13 6 14 Real Time Clock 0 c cee 14 1 15 Bootstrap Loader iios us e wy eae bake eee eS Ae Bae ER eR EHS 15 1 15 1 Entering the Bootstrap Loader 0 000 ee eee eee 15 2 15 2 Loading the Startup Code sc aer race x ra heres 15 5 15 3 Exiting Bootstrap Loader Mode 00 c eee eee 15 5 15 4 Choosing the Baudrate forthe BSL 0002 ce eee eee 15 6 16 Capture Compare Unit CAPCOM2 suus 16 1 16 1 CAPCOM2 Timers axes eaerr vates earn Fr Rea e o 1 card 16 4 16 2 CAPCOM2 Unit Timer Interrupts 0000 0 ee 16 9
507. terrupt system of the C164CM allows nesting of up to 15 interrupt service routines of different priority levels level O cannot be arbitrated Interrupt requests programmed to priority levels 15 or 14 i e ILVL 111Xg will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero In this case the request will be serviced by normal interrupt processing instead Interrupt requests programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000g is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never interrupt the CPU However an enabled interrupt request on level 0000g will terminate the C164CM s Idle mode and reactivate the CPU For interrupt requests which are to be serviced by the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see Figure 5 1 So programming a source to priority level 15 ILVL 1111p selects the PEC channel group 7 4 programming a source to priority level 14 ILVL 1110g selects the PEC channel group 3 O The actual PEC channel number is then determined by the group priority field GLVL Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 8 has highest priority Note All sources requesting PEC service must be programmed to different PEC chann
508. ters CC62 CMPx of timer T13 is disabled 1 The period and compare registers of timer T13 are loaded from their shadow latches when T13 reaches the respective period value Note STE13 is cleared by hardware after the shadow latch transfer ECT130 Enable compare timer T13 output 0 When ECT130 is cleared and timer T13 is running signal COUT63 outputs the corresponding port latch value ub When ECT130 is set and timer T13 is running timer T13 output COUTS63 is enabled and outputs the PWM signal of the 10 bit compare channel CT13P Timer T13 Period Flag The period flag CT13P is set whenever the contents of timer T13 match the contents of the timer T13 period register This also generates an interrupt request Bit CT13P must be cleared by software User s Manual 17 24 V1 0 2002 02 Infineon technologies C164CM C164SM Derivatives Capture Compare Unit CAPCOM6 TRCON Trap Enable Register SFR FF34 9A Reset Value 0000 15 14 13 12 11 10 9 8 7 6 3 2 1 0 TRP TRF TR TR TR TR TR TR ITT13 TT12 EN EN5 EN4 EN3 EN2 EN1 ENO DIS DIS w w rw rw rw rw w w W IW Bit Function TT12DIS Timer T12 Trap Disable Bit 0 Standard trap levels for timer T12 controlled outputs P1L jh Trap level is initial value for those timer T12 controlled outputs enabled by bits TRENx TT13DIS Timer T13 Trap Disable Bit 0 S
509. tes CLKCFG fcpu fosc x F Input Range 111 fosc x 4 2 5 to 6 25 MHz Default configuration 110 fosc x3 3 33 to 8 33 MHz 101 fosc x 2 5 to 12 5 MHz 100 fosc x 5 2 to 5 MHz 011 Josc x 1 1 to 25 MHz Direct drive 010 Josc x 1 5 6 66 to 16 6 MHz 0 0 1 fosc 2 2 to 50 MHz CPU clock via prescaler 000 fosc x 2 5 4 to 10 MHz L The external clock input range refers to a CPU clock range of 10 25 MHz m9 The maximum frequency depends on the duty cycle of the external clock signal In emulation mode pin P0 15 POH 7 is inverted i e the configuration 111 would select direct drive in emulation mode Default On chip PLL is active with a factor of 1 4 Watch the different requirements for frequency and duty cycle of the oscillator input clock for the possible selections Oscillator Watchdog Control The on chip oscillator watchdog OWD may be disabled via hardware by externally pulling the RD line low upon a reset similar to the standard reset configuration via PORTO At the end of an external reset bit OWDDIS in register SYSCON reflects the inverted level of pin RD at that time The software may again enable the oscillator watchdog by clearing bit OWDDIS before the execution of EINIT Note If direct drive or prescaler operation is selected as basic clock generation mode see above the PLL is switched off whenever bit OWDDIS is set via software or via hardware configuration User s
510. the Bit Timing According to the CAN protocol specification a bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 Each segment is a multiple of the time quantum t with Iq BRP 1 x 2 CPS x xcLK Note The CAN module is connected to the CPU clock signal therefore tyc x tcpy The Synchronization Segment Sync Seg is always 1 t long The Propagation Time Segment and the Phase Buffer Segment 1 combined to TSeg1 define the time before the sample point while Phase Buffer Segment 2 TSeg2 defines the time after the sample point The length of these segments is programmable except Sync Seg via the Bit Timing Register BTR Note For exact definition of these segments please refer to the CAN Protocol Specification 1 Bit Time Sync Sync Seg TSeg1 TSeg2 Seg A 1 time quantum Sample Point Transmit Point t MCT04393 Figure 19 4 Bit Timing Definition The bit time is determined by the XBUS clock period fyc x the Baud Rate Prescaler and the number of time quanta per bit bittime t t 19 1 Sync Seg t lTSeg1 t TSeg2 fSync Seg 1x TSegi TSEG1 1 Xt lTSeg2 TSEG2 1 x f 1 CPS ty BRP 1 x2 X tyorK 19 2 Note TSEG1 TSEG2 and BRP are the programmed numerical values from the respective fields of the Bit Timing Register User s Manual 19 11 V1 0 2002 02 _
511. the capacitances of the converter are loaded first via the respective analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted to a digital value in successive steps corresponding to the resolution of the ADC During these phases except for the sample time the internal capacitances are repeatedly charged and discharged via pins VAgge and VaAGwp The amount of current to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes because the capacitors must reach their final voltage level within the given time at least within a certain approximation The maximum current however that a source can deliver depends on its internal resistance The time required by the two sampling and converting phases during conversion can be programmed to be within a certain range in the C164CM relative to the CPU clock The absolute time consumed by the different conversion steps is therefore independent from the general speed of the controller This allows the A D converter of the C164CM to be adjusted to the properties of the system Fast Conversion can be achieved by programming the respective times to their absolute possible minimum This is preferred for scanning high frequency signals but the internal resistance of the analog source and analog supply must be sufficiently low High Internal Resistance ca
512. the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for use of the circular stack mechanism e Specify the size of the physical system stack area within the internal RAM bitfield STKSZ in register SYSCON e Define two pointers which specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data e Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After exiting from the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is emptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly User s Manual 22 7 V1 0 2002 02 _ Infineon C164CM C164SM technolo
513. the reset input these interrupt functions are alternate port functions User s Manual 5 1 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Interrupt and Trap Functions 5 1 Interrupt System Structure The C164CM provides 32 separate interrupt nodes assignable to 16 priority levels In order to support modular and consistent software design techniques most sources of an interrupt or PEC request are supplied with a separate interrupt control register and an interrupt vector The control register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is then activated by one specific event determined by the selected operating mode of the respective device For efficient resource usage multi source interrupt nodes are also incorporated These nodes can be activated by several source requests such as by different kinds of errors in the serial interfaces However specific status flags which identify the type of error are implemented in the serial channels control registers Additional sharing of interrupt nodes is supported via the interrupt subnode control register ISNC see Section 5 7 The C164CM provides a vectored interrupt system In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is as
514. the use of the EXTR instructions the ESFR area primarily holds registers which are mainly required for initialization and mode selection Registers which need to be accessed frequently are allocated to the standard SFR area wherever possible Note The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions User s Manual 3 8 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Memory Organization 3 3 External Memory Space The C164CM is capable of using an address space of up to 16 MBytes Only parts of this address space are occupied by internal memory areas All addresses which are not used for on chip memory ROM Flash OTP or RAM or for registers may reference external memory locations This external memory is accessed via the C164CM s external bus interface The C164CM supports four different bus types Multiplexed 16 bit Bus with address and data on PORTO Default after Reset Multiplexed 8 bit Bus with address and data on PORTO POL e Demultiplexed 16 bit Bus with address on PORT1 and data on PORTO e Demultiplexed 8 bit Bus with address on PORT1 and data on POL Due to the low pin count of the C164CM the external memory which can be directly addressed via the address bus is quite limited However the majority of applications is expected to work with on chip memories and use the bus i
515. ther a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled in a manner similar to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the vector location related to the corresponding source PEC services are very well suited for example to moving register contents to from a memory table The C164CM has eight PEC channels each of which offers such fast interrupt driven data transfer capabilities Memory Areas The memory space of the C164CM is configured in a Von Neumann architecture This means that code memory data memory registers and IO ports are organized within the same linear address space which covers up to 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have been made directly bit addressable as well 2 KBytes of 16 bit wide Internal R
516. tion of the connected sensor Table 10 7 summarizes the possible combinations Table 10 7 GPT1 Core Timer T3 Incremental Interface Mode Count Direction Level on respective T3IN Input T3EUD Input other input Rising Falling Rising Falling High Down Up Up Down Low Up Down Down Up User s Manual 10 10 V1 0 2002 02 ol Infineon technologies C164CM C164SM Derivatives General Purpose Timer Unit Figure 10 8 and Figure 10 9 give examples of T3 s operation visualizing count signal generation and direction control They also show how input jitter is compensated which might occur if the sensor rests near to one of its switching points Forward Jitter Backward Jitter Forward Contents of T3 Up Down Up Note This example shows the timer behaviour assuming that T3 counts upon any transition on input i e T3l 011 jy MCT04373 Figure 10 8 Evaluation of the Incremental Encoder Signals Forward Jitter Backward Jitter Forward Contents ors Up Down Up Note This example shows the timer behaviour assuming that T3 counts upon any transition on input TSIN i e T3l 001 MCT04374 Figure 10 9 Evaluation of the Incremental Encoder Signals Note Timer T3 operating in incremental interface mode automatically provides information about the sensor s curr
517. tion following the subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack to save the current system state twice PSW IP in segmented mode also CSP Otherwise a system reset should be generated Stack Underflow Trap Whenever the stack pointer is incremented to a value greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine Again which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction the pushed IP value represents the address of the instruction after the instruction following the add instruction Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid C164CM opcode the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented instructions The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP In order to resume processing the stacked IP valu
518. tion of four independent address windows while all external accesses outside these windows are controlled via register BUSCONO User s Manual 9 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 1 Single Chip Mode Single Chip Mode is entered when pin EA is high during reset In this case register BUSCONO is initialized with 00CO this also resets bit BUSACTO so no external bus is enabled In Single Chip Mode the C164CM operates using only internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface When running in Single Chip Mode however external access may be enabled by configuring an external bus under software control Single Chip Mode allows the C164CM to start execution from the internal program memory Mask ROM OTP or Flash memory Note Any attempt to access a location in the external memory space in Single Chip Mode results in the hardware trap ILLBUS if no external bus has been explicitly enabled by software 9 2 External Bus Modes When the external bus interface is enabled bit BUSACTx 1 and configured bitfield BTYP the C164CM uses a subset of its port lines to build the external bus Table 9 1 Summary of External Bus Modes BTYP External Data External Address External Address Encoding Bus Width Bus Width Bus Mode 00 8
519. tions or it can operate compatibly with the popular SPI interface Thus the SSC can be used to communicate with shift registers IO expansion peripherals EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR POH 6 Master Transmit Slave Receive and MRST POH 5 Master Receive Slave Transmit The clock signal is output or input on pin SCLK POH 7 These pins are alternate functions of PORTO pins Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions SSCCON POH SCLK POH 7 MTSR POH 6 MRST POH 5 DPOH Port 0 Direction Control Register POH Port 0 Data Register High SSCBR SSC Baud Rate Generator Reload Reg SSCCON SSC Control Register SSCTB SSC Transmit Buffer Register SSCRB SSC Receive Buffer Register SSCTIC SSC Transmit Interrupt Control Register SSCRIC SSC Receive Interrupt Control Register SSCEIC SSC Error Interrupt Control Register MCA05134 Figure 12 1 SFRs and Port Pins Associated with the SSC User s Manual 12 1 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface Slave Clock Master Clock 8 SCLK CPU Baud Rate Clock Generator Clock Control Shift Clock Receive Int Request Transmit Int Request SSC Control Block Error Int Request Status Control Pi
520. tives Central Processing Unit CPU Multiply Divide High Register MDH This register is part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bits of the 32 bit result For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit dividend before the division is started After any division register MDH represents the 16 bit remainder Mut IBS High Reg SFR FEOC 06 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mdh rwh Bit Function mdh Specifies the high order 16 bits of the 32 bit multiply and divide reg MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL and MDC to avoid erroneous results A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in Chapter 22 User s Manual 4 30 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Proc
521. to several port pins of the C164CM under software control This assignment is selected via bitfield IPC Interface Port Connection in register PCIR Table 19 3 Assignment of CAN Interface Lines to Port Pins IPC CAN_RxD CAN TxD Notes 000 Reserved Do not use this combination 001 Reserved Do not use this combination 010 P8 0 P8 1 011 P8 2 P8 3 100 Reserved Do not use this combination 101 Heserved Do not use this combination 110 Reserved Do not use this combination 111 Idle Disconnected No port assigned Default after Reset recessive The location of the CAN interface lines can now be selected via software according to the requirements of an application Port Assignment IPC 010g or 011g connects the CAN interface lines to Port 8 Two pairs of Port 8 pins can be selected No Assignment IPC 111g disconnects the CAN interface lines from the port logic This avoids undesired currents through the interface pin drivers while the C164CM is in a power saving state After reset the CAN interface lines are disconnected Note Assigning CAN interface signals to a port pin overrides the other alternate function of the respective pin CAPCOM lines on Port 8 User s Manual 19 37 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives System Reset 20 System Reset The internal system reset function provides
522. torr see Figure 17 6 Count Value T12 T120 A T12P 7 T120F 2 Time A 0 Tig 9 lor ee lope e amp lorc lt Duty Cycles CC6x o Active High 21 1 Ett 29 COUT6x Active High LU tt 313 T 5796 COUT6x Active Low i 57 CC6x 5 in this example MCT02603 Figure 17 6 Operation in Center Aligned Mode Note In order to generate correct dead times for PWM signals the offset value stored in T12OF must be lower than the value stored in the compare registers The offset value affects all COUT6x outputs Dead time generation is available only in the full function module User s Manual 17 7 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 17 3 1 Timing Relationships The resolution of the compare timers depends on the selected internal clock frequency The period range of the output signals in turn depends on the actual timer resolution minimum value and on the timer and period values maximum value Table 17 1 lists the respective values of both compare timers for the possible clock selections Due to internal operation the minimum possible output period is two internal clock cycles Edge Aligned Mode Count Value A CC6x 2 CC6x 2 T12P 23 T12P 25 T12 Start CC6x 1 T12P
523. tors which are connected to the CAPCOM6 s output lines Register TRCON enables and controls the trap function register CC6MCON or P1L provides the output levels during trap state Figure 17 11 shows examples for a trap state in edge aligned mode and in center aligned mode Trap Function In Edge Aligned Mode Notes Period P T124 T1A20F Value Reference Point 1 Input CTRAP is activated the outputs Compare k z Value immediately switch to their trap level Offset Reference Point 2 Input CTRAP is inactive CCx the outputs switch to their Abt cours synchronized to a new timer period Secure Trap State MCB04114 During trap state the Trap Function In Center Aligned Mode outputs CC6x and COUT6x which are selected for T13 Period T12 T120F Xv modulation are not Value modulated with T13 s ee eS MD output signal but rather Compare with its initial value Value Offset _ CTRAP MCT02606 Figure 17 11 Trap Function User s Manual 17 18 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM6 Entering Trap State Bit TRPEN generally enables the trigger function of input CTRAP When enabled a falling edge on input CTRAP activates the trap state immediately without any CPU activity see Reference Point 1 in Figure 17 11 This event sets the trap flag TRF in register TRCON to signal this event to the s
524. tr Ctrl Reg SFR FF98 CC Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC ADC IR IE ILVL GLVL mh rw rw rw ADEIC ADC Error Intr Ctrl Reg SFR FF9A CDy Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADE ADE mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 18 15 V1 0 2002 02 Oo Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface 19 On Chip CAN Interface The Controller Area Network CAN bus and its associated protocol allow highly efficient communication among a number of stations connected to this bus Efficiency in this context refers to Transfer speed Data rates of up to 1 Mbit s can be achieved Data integrity The CAN protocol provides several means of error checking Host processor unloading The controller handles most of the tasks autonomously e Flexible and powerful message passing The extended CAN protocol is supported The integrated CAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active Because of this the on chip CAN module can receive and transmit e Standard frames with 11 bit identifiers as well as e Extended frames with 29 bit identifiers Note The CAN module is an XBUS peripheral and therefore requires bit XP
525. trap Automatic system stack flushing allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack word locations are required to push IP PSW and CSP for both the interrupt service routine and the hardware trap service routine More details about the stack overflow trap service routine and virtual stack management are given in Chapter 24 User s Manual 4 28 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Central Processing Unit CPU Stack Underflow Pointer STKUN This non bit addressable register is compared against the SP register after each operation which pops data from the system stack e g POP and RET instructions and after each addition to the SP register If the content of the SP register is greater than the content of the STKUN register a stack underflow hardware trap will occur Because the least significant bit of register STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKUN register can contain values from F000 to FFFE only
526. tream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the Error Management Logic EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy Check Register This register generates the Cyclic Redundancy Check CRC code to be transmitted after the data bytes and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic EML is responsible for the fault confinement of the CAN device Its two counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the Bit Stream Processor According to the values of the error counters the CAN controller is set into one of three states error active error passive and busoff The CAN controller states occur as follows e Error active if both error counters are below the error passive limit of 128 e Error passive if at least one of the error counters equals or exceeds 128 e Busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in
527. trolled by its bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high byte of the timer selects the input clock prescaling factor and also provides flags to indicate the source of a reset After any reset except as noted the watchdog timer is enabled and starts counting up from 0000 with the default frequency fwpr cpy 2 The default input frequency may be changed to another frequency fwpr 7 fcpu 4 128 256 by programming the prescaler bits WDTPRE and WDTIN The watchdog timer can be disabled by executing the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT Note After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled The software reset which terminates the BSL mode will then enable the WDT When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even in Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFF the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication pin RSTOUT low The Watchdog Timer Reset Indication Flag WDTR in
528. troller PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations in segment 0 data pages O through 3 through one of eight programmable PEC Service Channels During a PEC transfer normal program execution of the CPU is halted for only one instruction cycle No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing PEC transfers share the two highest priority levels Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided to handle erroneous conditions and exceptions arising during instruction execution Hardware traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction that generates a software interrupt for a specified interrupt vector For all trap types current program status is saved on the system stack External Interrupt Processing Although the C164CM does not provide dedicated interrupt pins it allows connection of external interrupt sources and provides several mechanisms to react to external events including standard inputs non maskable interrupts and fast external interrupts Except for the non maskable interrupt and
529. ts TXRQ and RMTPND which are set In the last message object 15 which cannot start a transmission the identifier bits corresponding to the don t care bits of the Last Message Mask are copied from the received frame Bits corresponding to the don t care bits of the corresponding global mask are not copied bits masked out by the global and the last message mask cannot be retrieved from object 15 feces Arbitration Register XReg EFn2 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID17 13 ID28 21 nw nw LARn Lower Arbitration Register XReg EFn4 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDA 0 0 0 0 ID12 5 nw r r r nw Bit Function ID28 0 Identifier 29 bit Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers bits ID17 O are don t care User s Manual 19 21 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives On Chip CAN Interface Message Configuration The Message Configuration Register low byte of MCFGn holds a description of the message within this object Note There is no don t care option for bits XTD and DIR So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data
530. tten to their port output latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins used for bus control functions go into the state which represents the inactive state of the respective function e g WR or to a defined state which is based on the last bus access Port pins used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions e POH 2 0 outputs the high bits of the last address if a multiplexed bus mode with 8 bit data bus is used Otherwise POH 2 0 is floating POL is always floating in Idle mode e PORT1 outputs the lower 16 bits of the last address if a demultiplexed bus mode is used Otherwise the output pins of PORT1 represent the port latch data In Sleep mode the oscillator except for RTC operation and the clocks to the CPU and to the peripherals are turned off As in Idle mode all port pins configured as general purpose output pins will output the last data value written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off In Power Down mode the oscillator except for RTC operation and the clocks to the CPU and to the peripherals are turned off As in Id
531. ual 16 13 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 16 5 Compare Modes The compare modes allow triggering of events interrupts and or output signal transitions with minimum software overhead In all compare modes the 16 bit value stored in compare register CCx in the following also referred to as compare value is continuously compared with the contents of the allocated timer T7 or T8 If the current timer contents match the compare value an appropriate output signal based on the selected compare mode can be generated at the corresponding output pin CCxlO and the associated interrupt request flag CCxIR is set which can generate an interrupt request if enabled See Section 16 7 for a possible solution for channels 28 31 As for capture mode the compare registers are also processed sequentially in compare mode When any two compare registers are programmed to the same compare value their corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within eight CPU clock cycles after the allocated timer is incremented to the compare value Further compare events on the same compare value are disabled until the timer is incremented again or is written to by software After a reset compare events for register CCx will become enabled only if the allocated timer has been incremented or written to by software an
532. ual 6 4 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Clock Generation 6 2 Frequency Control The CPU clock is based on either the Basic Clock or the Slow Down Clock Both types of clock are generated from the oscillator clock and are software selectable The Basic Clock is the standard operating clock for the C164CM and is required to deliver the intended maximum performance The clock configuration in register RPOH bitfield CLKCFG RPOH 7 5 determines one of three possible basic clock generation modes Direct Drive the oscillator clock is directly fed to the controller hardware Prescaler the oscillator clock is divided by 2 to achieve a 50 duty cycle e PLL the oscillator clock is multiplied by a configurable factor of F 1 5 5 The Slow Down Clock is the oscillator clock divided by a programmable factor of 1 32 additional 2 1 divider in prescaler mode This alternate possibility runs the C164CM at a lower frequency determined by the programmed slow down factor and greatly reduces its power consumption cu et Configuration Oscillator Clock CPU Clock tose Joru MCD04458 Figure 6 4 Frequency Control Paths Note The configuration register RPOH is loaded with the logic levels present on the upper half of PORTO POH after a long hardware reset i e bitfield CLKCFG represents the logic levels on pins PO 15 13 POH 7 5 User s
533. ubnode Control Register 00004 RSTCON b F1EO m Reset Control Register OOXXy DPPO FEOO O0 CPU Data Page Pointer 0 Reg 10 bits 0000 DPP1 FEO2y Oi CPU Data Page Pointer 1 Reg 10 bits 0001 DPP2 FE044 02 CPU Data Page Pointer 2 Reg 10 bits 00024 DPP3 FEO6 034 CPU Data Page Pointer 3 Reg 10 bits 0003 CSP FEO8 044 CPU Code Segment Pointer Register 00004 8 bits not directly writeable User s Manual 23 13 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives Register Set Table 23 4 C164CM Registers Ordered by Name cont d Name Physical 8 Bit Description Reset Address Addr Value MDH FEOC 064 CPU Multiply Divide Reg High Word 00004 MDL FEOE 074 CPU Multiply Divide Reg Low Word 0000 CP FE10 084 CPU Context Pointer Register FCOO SP FE12 094 CPU System Stack Pointer Register FCOO STKOV FE14Q OA CPU Stack Overflow Pointer Register FAOOW STKUN FE16y OB CPU Stack Underflow Pointer Register FCOOy ADDRSEL1 FE18 OC Address Select Register 1 0000 ADDRSEL2 FE1Ay OD Address Select Register 2 0000 ADDRSEL3 FE1C OE Address Select Register 3 0000 ADDRSEL4 FE1E OF Address Select Register 4 0000 CC60 FE30y 184 CAPCOM 6 Register 0 00004 CC61 FES32 194 CAPCOM 6 Register 1 0000 CC62 FE34 1Ay CAPCOM 6 Regist
534. ue to the very compact package many alternate I O signals use PORTO and PORT1 so utilizing the full bus interface conflicts with a number of peripheral functions A very good compromise is 8 bit multiplexed mode where only 11 pins of PORTO are occupied by the bus interface This allows control of external peripherals while providing most I O functions at the same time User s Manual 2 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 4 On Chip Peripheral Blocks The C166 Family clearly separates peripherals from the core This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core Each functional block processes data independently and communicates information over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located within either the standard SFR area 00 FE0O OO FFFF or within the extended ESFR area 00 F000 OO F1FF These built in peripherals either allow the CPU to interface with the external world or provide functions on chip that otherwise would need to be added externally in the respective system The C164CM generic peripherals are e A General Purpose Timer Block GPT1 Two Serial Interfaces ASCO and SSC e A Watchdog Timer Two Capture Comp
535. ular the bootstrap loader may be activated when POL 4 is low Pin RSTIN may be connected only to external reset devices with an open drain output driver A short hardware reset is extended to the duration of the internal reset sequence The Reference Voltage pins for the Analog Digital Converter Varner and Vagnp provide a separate power supply reference voltage for the comparator circuitry of the on chip ADC This reduces the noise which is coupled to the analog input signals from the digital logic sections and so improves the stability of the conversion results when Varer and Vacnp are properly discoupled from Vpp and Vas The Power Supply pins Vpp and Vss provide the power supply for the digital logic of the C164CM The respective Vpp Vss pairs should be decoupled as close to the pins as possible For best results it is recommended to implement two level decoupling for example the widely used 100 nF in parallel with 30 40 pF capacitors which deliver the peak currents Note All Vpp pins and all Vss pins must be connected to the power supply and ground respectively The External Programming Voltage Vpp is applied to pin P20 5 EA Vpp This is required to program the on chip OTP program memory Note This feature is only available in OTP devices of course User s Manual 8 2 V1 0 2002 02 _ o Infineon C164CM C164SM technologies Derivatives External Bus Interface 9 External Bus Interface Although the
536. ulse width modulation PWM or measuring The C164CM supports generation and control of timing sequences on up to three 16 bit capture compare channels plus one 10 bit compare channel In compare mode the CAPCOMG unit provides two output signals per 16 bit channel which may have inverted polarity and non overlapping pulse transitions The 10 bit compare channel can generate a single PWM output signal and is further used to modulate the capture compare output signals The compare timers T12 16 bit and T13 10 bit are free running timers which are clocked by the prescaled CPU clock For motor control applications both subunits may generate versatile multi channel PWM signals which are basically either controlled by compare timer T12 or by a typical hall sensor pattern at the interrupt inputs This operating mode is called block commutation available only in devices with a full function CAPCOM6 In capture mode the contents of compare timer T12 are stored in the capture registers upon a programmable signal transition at pins CC6x From the programmer s point of view the term CAPCOM unit refers to a set of SFRs which are associated with this peripheral including the port pins which may be used for alternate input output functions and their direction control bits Ports amp Direction Control Alternate Functions Data Registers Control Registers Interrupt Control DP1H P1H T121C T12P E TI20F E T13P E li CTCON TRCON
537. ultiply divide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires the use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on bit instructions Multiplication or division is simply performed by specifying the correct signed or unsigned version of the multiply or divide instruction The result is then stored in register MD The overflow flag V is set if the result from a multiply or divide instruction is greater than 16 bits This flag can be used to determine whether both word halves must be transferred from register MD The high portion of register MD MDH must be moved into the register file or memory first to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only required for interrupted multiply divide instructions BSET SAVED Indicate the save operation PUSH MDH Save previous MD contents PUSH MDL P On System stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc NV COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MD
538. upt Control Register 0000 SSCEIC b FF764 BB SSC Error Interrupt Control Register 0000 CC8IC b FF88y C4 External Interrupt O Control Register 0000 CC9IC b FF8Ay C5 External Interrupt 1 Control Register 00004 CC10IC b FF8C4 C6 External Interrupt 2 Control Register 0000 User s Manual 23 16 V1 0 2002 02 _ Infineon technologies C164CM C164SM Derivatives Table 23 4 C164CM Registers Ordered by Name cont d Register Set Name Physical 8 Bit Description Reset Address Addr Value CC111IC b FF8E C7 External Interrupt 3 Control Register 00004 ADCIC b FF98 CC A D Converter End of Conversion 0000 Interrupt Control Register ADEIC b FF9A CD A D Converter Overrun Error Interrupt 0000 Control Register ADCON b FFAO DO A D Converter Control Register 0000 P5 b FFA2 Dip Port 5 Register read only XXXXy P5DIDIS b FFA4 D24 Port 5 Digital Input Disable Register 0000 FOCON b FFAA D5 Frequency Output Control Register 00004 TFR b FFAC D6 Trap Flag Register 0000 WDTCON FFAEW D74 Watchdog Timer Control Register 2 00xx SOCON b FFBO D8 Serial Channel 0 Control Register 00004 SSCCON b FFB2 D94 SSC Control Register 00004 P20 b FFB4 DA Port 20 Register 6 bits 00H DP20 b FFB6 DB Port 20 Direction Control Register 00 P8 b FFD4 EA Port 8 Register 4 bits 004 DP8 b FFD
539. ured basic mode uses the prescaler fcpy fosc 64 in this case After the reset sequence has been completed the RSTIN input is sampled again If the reset input signal is inactive at that time the internal reset condition is terminated indicated as short hardware reset SHWR If the reset input signal is still active at that time the internal reset condition is prolonged until RSTIN becomes inactive indicated as long hardware reset LHWR During a hardware reset the inputs for the reset configuration PORTO RD ALE need some time to settle on the required levels especially if the hardware reset aborts a read operation from an external peripheral During this settling time the configuration may intermittently be wrong For the duration of one internal reset sequence after a reset has been recognized the configuration latches are not transparent thus the new configuration becomes valid earliest after the completion of one reset sequence This usually covers the required settling time When the basic clock is generated by the PLL the internal reset condition is automatically extended until the on chip PLL has locked The input RSTIN provides an internal pull up device equalling a resistor of 50 kO to 250 kQ the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset see b in Figure 20 1 RSTIN may also be connected to the output o
540. ured for input or output A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Data Input Output Direction Control Diverse Control Registers Registers Registers SYSCON P5DIDIS DP20 MCAO05115 Figure 7 1 SFRs and Pins Associated with the Parallel Ports User s Manual 7 1 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the written value because the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin User s Manual 7 2 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Parallel Ports 7 1 Output Driver Control The output driver of a port pin is activated by switching the respective pin to output that is DPx y 1 The value driven to the pin is determined by the port output latch or by the associated alternate function e g address peripheral IO etc The user software can control the character
541. uses 21 10 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Power Management 21 4 Slow Down Operation A separate clock path can be selected for Slow Down operation bypassing the basic clock path used for standard operation The programmable Slow Down Divider SDD divides the oscillator frequency by a factor of 1 32 which is specified via bitfield CLKREL in register SYSCON2 factor lt CLKREL gt 1 When bitfield CLKREL is written during SDD operation the reload counter will output one more clock pulse with the old frequency in order to resynchronize internally before generating the new frequency If direct drive mode is configured clock signal fpp is directly fed to fcpy If prescaler mode is configured clock signal fpp is additionally divided by 2 1 to generate fcpy see examples below CLKREL Reload Counter pow T R do odo qox L Factor 3 Direct Drive Itt Itt Jean I I tl I tl fosc MCD04477 Figure 21 3 Slow Down Divider Operation Using a 5 MHz input clock for example the on chip logic may be run at a frequency down to 156 25 kHz or 78 kHz without an external hardware change An implemented PLL may be switched off in this case or may continue running depending on the requirements of the applic
542. ut RSTIN Reset Input Varer VaGnp _ Voltage Reference for Analog Digital Converter Vpp Digital Power Supply 4 pins Vss Digital Reference Ground 4 pins The Non Maskable Interrupt Input NMI allows triggering of a high priority trap via an external signal e g a power fail signal It also serves to validate the PWRDN instruction which switches the C164CM into Power Down mode The NMI pin is sampled with every CPU clock cycle to detect transitions The Oscillator Input XTAL1 and Output XTAL2 connect the internal Main Oscillator to the external crystal The oscillator provides an inverter and a feedback element The standard external oscillator circuitry see Chapter 6 consists of the crystal two low end capacitors and a series resistor to limit the current through the crystal The main oscillator is intended for the generation of the basic operating clock signal of the C164CM An external clock signal may be fed to the input XTAL1 leaving XTAL2 open or terminating it for higher input frequencies The Reset Input RSTIN allows the C164CM to be put into the well defined reset condition either at power up or on external events such as a hardware failure or manual reset The input voltage threshold of the RSTIN pin is raised compared to the standard pins to minimize the noise sensitivity of the reset input In bidirectional reset mode the C164CM s line RSTIN may be driven active by the chip logic in order to support external equipmen
543. utomatic reset of the SSC will be performed This is done to reinitialize the SSC if too few or too many clock pulses have been detected User s Manual 12 15 V1 0 2002 02 _ Oo Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Serial Interface A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when enabled via SSCTEN the error interrupt request flag SSCEIR If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer Note A slave with push pull output drivers which is not selected for transmission will normally have its output drivers switched However to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer Error Register SSCCON Register SSCEIC SSCTEN Transmit Error SSCTE SSCREN Receive SSCRE SSCEIE Error Error Interrupt ROGER SSCEINT SSCPEN Phase Error SSCPE Baudrate SSCBE MCA01968 Figure 12 6 SSC Error Interrupt Control User s Manual 12 16 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives High Speed Synchronous Seria
544. vatives System Programming Enabling and Disabling Internal Code Memory After Reset If the internal code memory does not contain an appropriate startup code the system may be booted from external memory while the internal memory is enabled afterwards to provide access to library routines tables etc If the internal code memory contains only the startup code and or test software the system may be booted from internal memory which may then be disabled after the software has switched to executing from external memory for example This may be done to free the address space occupied by the internal code memory which would no longer be necessary User s Manual 22 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives System Programming 22 11 Pits Traps and Mines Although handling the internal code memory provides a powerful means of enhancing the overall performance and flexibility of a system extreme care must be taken to avoid a system crash Instruction memory is the most crucial resource for the C164CM and it must be ensured that it never runs out The following precautions help to take advantage of the methods mentioned above without jeopardizing system security Internal code memory access after reset When the first instructions are to be fetched from internal memory EA 1 the device must contain code memory containing a valid reset vector and valid code at its destination Mapp
545. ve address areas the bus mode multiplexed demultiplexed the data bus width 8 bit 16 bit and even the length of a bus cycle waitstates signal delays can be selected independently This allows access to a variety of memory and peripheral components directly and with maximum efficiency If the device does not run in Single Chip Mode where no external memory is required the EBC can control external accesses in one of the following external access modes e 16 bit Addresses 16 bit Data Demultiplexed 16 bit Addresses 8 bit Data Demultiplexed e 16 bit Addresses 16 bit Data Multiplexed e 11 bit Addresses 8 bit Data Multiplexed The demultiplexed bus modes use PORT1 for addresses and PORTO for data input output The multiplexed bus modes use PORTO for both addresses and data input output Important timing characteristics of the external bus interface waitstates ALE length and Read Write Delay have been made programmable to allow the user select a wide range of different types of memories and or peripherals The on chip XBUS is an internal representation of the external bus It allows access to integrated application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripherals The on chip CAN Module is an example for these X Peripherals Even though the C164CM supports all the bus modes described above many applications will use it in Single Chip mode D
546. ve timer will be set This flag can be used to generate an interrupt or to trigger a PEC service request when enabled by the respective interrupt enable bit TxIE Each timer has its own bit addressable interrupt control register TxIC and its own interrupt vector TXINT The organization of the interrupt control registers TxIC is identical to the other interrupt control registers CR COM T7 Intr Ctrl Reg ESFR F17A BE Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T7IR T7IE ILVL GLVL mh rw rw rw T8IC CAPCOM T8 Intr Ctrl Reg ESFR F17C BFy Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T8IR T8IE ILVL GLVL mh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 16 9 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Capture Compare Unit CAPCOM2 16 3 Capture Compare Registers The 16 bit capture compare registers CC16 through CC31 are used as data registers for capture or compare operations with respect to timers T7 and T8 The capture compare registers are not bit addressable Each of the registers CCx may be individually programmed for capture mode or for one of four different compare modes Each register may be allocated individually to one of
547. vided according to the operating mode and controlled by the Baudrate Selection Bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3 of its frequency see formulas and table So the baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS and the operating mode asynchronous or synchronous Register SOBG is the dual function Baud Rate Generator Reload register Reading SOBG returns the content of the timer bits 15 13 return zero while writing to SOBG always updates the reload register bits 15 13 are insignificant Each time SOBG is written to an auto reload of the timer with the content of the reload register is performed However if SOR 0 at the time the write operation to SOBG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 Asynchronous Mode Baud Rates For asynchronous operation the baud rate generator provides a clock with 16 times the rate of the established baud rate Every received bit is sampled at the 7 8 and ot cycle of this clock The baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given baudrate can be determined by the following formulas B B fcPU ASynO A 76 QORBBUOICCGERBE Sa 16 x 2 SOBRS x lt SOBRL gt 1 SOBRL ____ ePU__ iy 16 x 2 lt SOBRS gt x Basync lt SOBRL gt represents the contents of the reload register take
548. vides a Capture Compare CAPCOM unit which provides 16 channels 12 IO pins which interact with 2 timers The CAPCOM2 unit can capture the contents of a timer on specific internal or external events or can compare a timer s contents with given values and modify output signals in case of a match This mechanism supports generation and control of timing sequences on up to 16 channels with a minimum of software intervention From the programmer s point of view the term CAPCOM unit refers to a set of Special Function Registers SFRs associated with this peripheral including the port pins which may be used for alternate input output functions including their direction control bits Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T78CON T1IC T8IC CC16 19 CC20 23 CC16lO P8 0 CC191O P8 3 EET CC24IO P1H 4 CC271O P1H 7 CC28IO P1H 0 CC311O P1H 3 CC16 19IC E CC24 271C E ODP8 Port 8 Open Drain Control Register T78CON CAPCOM2 Timers T7 and DPx Port x Direction Control Register T8 Control Register Px Port x Data Register TxIC CAPCOWM2 Timer x Interrupt Control Register TXREL CAPCOM2 Timer x Reload Register CC16 19IC CAPCOM2 Interrupt TX CAPCOM2 Timer x Register Control Register 16 19 CC16 19 CAPCOM2 Register 16 19 CC24 271IC CAPCOM2 Interrupt CC20 23 CAPCOM2 Register 20 23 Control Register 24 27 CC24 27 CAPCOM2 Register 24 27 CC2
549. w rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 12 17 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives Watchdog Timer WDT 13 Watchdog Timer WDT To allow recovery from software or hardware failure the C164CM provides a Watchdog Timer If the software fails to service this timer before an overflow occurs an internal reset sequence will be initiated This internal reset will also pull the RSTOUT pin low which in turn resets the peripheral hardware which might have caused the malfunction If the watchdog timer is enabled and the software has been designed to service it regularly before it overflows the watchdog timer will supervise the program execution so it will overflow only if the program does not progress properly The watchdog timer will also time out if a software error was caused by hardware related failures This prevents the controller from malfunctioning for a time longer than specified by the user Note When the bidirectional reset is enabled pin RSTIN will be pulled low for the duration of the internal reset sequence upon a software reset or a watchdog timer reset The watchdog timer provides two registers aread only timer register containing the current count and acontrol register for initialization and reset source detection Reset Indication Pins Data Registers Control Registers RST
550. w rw rw rw rw rw rw rw Bit Function DPOX y Port direction register DPOH or DPOL bit y DPOX y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 bit demultiplexed bus only uses POL while POH is free for IO provided that no other bus mode is enabled PORTO is also used to select the system startup configuration During reset PORTO is configured to input and each line is held high through an internal pull up device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pull down device A default configuration is selected when the respective PORTO lines are at a high level By pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pull up devices are designed such that external pull down resistors see Data Sheet specification can be used to apply a correct low level These external pull down resistors can remain connected to the PORTO pins also during normal operation however care must be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong On completion of reset the selected bus configuration will be written to the
551. which has a specific task 19 _ FETCH In this stage the instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal ROM internal RAM or external memory 2d _ DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instructions which implicitly access the system stack the SP register is either decremented or incremented as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken 3 d _ EXECUTE In this stage an operation is performed on the previously fetched operands in the ALU Additionally the condition flags in the PSW register are updated as specified by the instruction Also all explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction 4 _ WRITE BACK In this stage all external operands and the remaining operands within the internal RAM space are written back A special feature of the C164CM is the use of so called injected instructions Injected instructions are generated internally by the machine to provide the time needed to process instructions which cannot be processed within one machine cycle These instructions ar
552. which works in parallel with the CPU This section provides a very condensed summary of the execution times A detailed description of the execution times for the various instructions and the specific exceptions can be found in the C166 Family Instruction Set Manual Table 4 1 shows the minimum execution times required to process a C164CM instruction fetched from the internal code memory the internal RAM or from external memory These execution times apply to most of the C164CM instructions except for some of the branches the multiplication the division and a special move instruction In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations The numbers in the table are in units of CPU clock cycles and assume no waitstates Table 4 1 Minimum Execution Times Instruction Fetch Word Operand Access Memory Area Word Doubleword Read from Write to Instruction Instruction Internal code memory 2 2 2 Internal RAM 6 8 0 1 0 16 bit Demux Bus 2 4 2 2 16 bit Mux Bus 3 6 3 3 8 bit Demux Bus 4 8 4 4 8 bit Mux Bus 6 12 6 6 Execution from the internal RAM provides flexibility in terms of loadable and modifyable code on the account of execution time Execution from external memory is heavily dependent on the selected bus mode and the programming of the bus cycles waitstates User s Manual 4 11 V1 0 2002
553. with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 8 In wake up mode received frames are transferred to the receive buffer register only if the 9 pit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in a multi processor system When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9 bit is a 1 for an address byte and a 0 for a data byte so that no slave will be interrupted by a data byte An address byte will interrupt all slaves operating in 8 bit data wake up bit modes so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 bit data mode for example by clearing bit SOM 0 which enables it to also receive the data bytes that will be coming having the wake up bit cleared The slaves not being addressed remain in 8 bit data wake up bit modes ignoring the following data bytes 1st 2nd Stop Stop Bit Bit e Data Bit D8 e Parity e Wake up Bit MCT04378 Figure 11 4 Asynchronous 9 bit Data Frames User s Manual 11 6 V1 0 2002 02 _ Infineon
554. ws the operation control of entire groups of peripherals including the power required for generating and distributing their clock input signal Other peripherals may remain active for example in order to maintain communication channels The registers of separately disabled peripherals not within a disabled group can still be accessed Periodic Wakeup from Idle or Sleep Mode Periodic wakeup from Idle mode or from Sleep mode combines the drastically reduced power consumption in Idle Sleep mode in conjunction with the additional power management features with a high level of system availability External signals and events can be scanned at a lower rate by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time This greatly reduces the system s average power consumption Idle Sleep mode can also be terminated by external interrupt signals User s Manual 2 20 V1 0 2002 02 Infineon C164CM C164SM technologies Derivatives Architectural Overview 2 6 Protected Bits The C164CM provides a special mechanism to protect bits which can be modified by the on chip hardware from being changed unintentionally by software accesses to related bits see also Chapter 4 The following bits are protected Table 2 1 C164CM Protected Bits Register Bit Name Notes T2IC T3IC T4IC T2ZIR T3IR T4IR GPT1 timer interru
555. ycle time wait states the CPU is idle if this access is required for the execution of the current instruction The memory cycle time wait states can be programmed in increments of one CPU clock 2 TCL within a range from O to 15 default after reset via the MCTC fields of the BUSCON registers 15 lt MCTC gt waitstates will be inserted User s Manual 9 11 V1 0 2002 02 _ Infineon C164CM C164SM technologies Derivatives External Bus Interface Programmable Memory Tri State Time The C164CM allows the user to adjust the time between two subsequent external accesses to account for the tri state time of the external device The tri state time defines when the external device releases the bus after deactivation of the read command RD a Bus Cycle MTTC Wait State MCT02065M Figure 9 8 Memory Tri State Time The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers This is accomplished by introducing a wait state after the previous bus cycle see Figure 9 8 During this memory tri state time wait state the CPU is not idle so CPU operations will be slowed down only if a subsequent external instruction or data fetch operation is required during the next instruction cycle The memory tri state time waitstate requires one CPU clock 2 TCL and is controlled via the MTTOx bits of
556. zzyu Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxIR xxIE ILVL GLVL F A mwh srw rw rw Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests Fu Highest priority level Oy Lowest priority level xxlE Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt request is disabled T2 Interrupt Request is enabled xxIR Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from its respective source occurs It is cleared automatically upon entry into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COUNT field in register PECCx of the selected PEC channel decrements to zero This allows a normal CPU interrupt to respond to a completed PEC block transfer Note Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware The Interrupt Enable Control Bit determines whether the respective interrupt node takes part in the arbitration cycles enabled or not disabled The associated request flag will be set upon a source requ

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