HDL Synthesis Design with LeonardoSpectrum: ispXPGA Flow
Contents
1. O BS A D done 18 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 7 Route the Design The ispLEVER software routes the design in the device after placement The routing algorithm takes full advantage of the Lattice ispXPGA architecture to achieve maximum performance It uses congestion driven routing to achieve a fit with minimal congestion and it uses timing driven routing to achieve maximum performance To route the design 1 Double click the Route Design process The ispLEVER software successfully routes the design in the specified device and generates an 1d3 file When the process is through a green check mark appears next to the process E ispLE ER Project Navigator C ISPTOOLS5_0 EXAMPLES TUTORIAL TUTORS mux syn File Yiew Source Process Options Tools Window Help D S E nomal 7S K E co E amp l a af ag m GA e m e ds S a M wo l0l x Sources in Project Processes for current source E mux W O Build Database Gq Documents K Constraint Editor Ey LFX1200C 03FE680C 29 Pack amp Place Design B multiplexer4to1 multiple edF A E HTML PackjPlace Report mux html a Pack Place Report mux rpt Post Place Pinouts A Post Place Design Floorplan f IBIS Model mux ibs 2 9 Place Timing Checkpoint SL Place Timing Report mux trp oD Route Design A Route Report mux rlog Post Route Design Floorplan Timin2. f4 G4 Note Only a few files will be generated in this tutorial Because many generated files can be created in a real project it is a good practice to separate your design source files and batch scripts into a separate subdirectory For example the input source files could be kept in a subdirectory named src Then if your first synthesis run generates the fastest possible circuit you may want to do one or more optional runs to evaluate the tradeoffs between speed and area You can simply copy the src subdirectory into a new working directory named smallest for example and the new generated files for the next run will be placed there 7 Atthe bottom of the Quick Setup tab click Run Flow LeonardoSpectrum reads the opened input files and creates an in memory EDIF style database called the RTL database The design is composed of generic gates and non mapped black box modules such as operators counters and inferred RAMs Next the in memory design is mapped to the specified technology globally optimized and the results for each module are saved If a timing constraint is not met at this point additional critical path optimizations are run to try to meet the constraints The results are kept in a second in memory technology mapped design database The output EDIF netlist and support files are then automatically generated and written to the working directory The Critical Path Report now appears in the right pane
3. Note The Run Flow button is not active until you have selected your input files and target technology When the synthesis process is complete the information window on the right indicates that the run successfully ended 2005 Lattice Semiconductor 13 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Mentor Graphics LeonardoSpectrum for Lattice Information Read Only lel x S Fle Edt view Tools Window Help s ema S e memme ix 1404 5 MHz Quick Setup Run the entire flow from this one condensed page Specify your source file s technology and desired frequency then press Run Flow m Technology min Critical Path Report Critical path 1 unconstrained path NAHE GATE ARRIVAL ispLSI5000VE_old multiple v a ispLS18000 clock information not specified ispmach40008 delay thru clock network 0 00 ideal ispmach4000C J ispmach4000 Paias d 1 DFF 0 00 1 00 reg_data a a up Oe nx 2 0 LUT3 1 00 2 00 up mi ls ix 3 0 MUXLS 0 16 2 16 up 5 z_obuf 0 OBUF 1 08 3 24 up z z 0 00 3 24 up Device data arrival time 3 24 LFx12008 05FE680C z Speed Grade data required time not specified 05 Open files E J data required time not specified Package ipseca gt Working Directory ca m Constraints Clock Frequency Mhz m Optimize Effort Fa
4. a 5 Click OK to close the dialog box 6 Choose File gt Exit to exit the Performance Analyst without saving 7 Choose File gt Exit to exit the Project Navigator Do not save the design 24 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Summary You have completed the HDL Synthesis Design with LeonardoSpectrum tutorial In this tutorial you have learned how to do the following Use the Project Navigator to create a new EDIF project and target a device Launch LeonardoSpectrum from within the Project Navigator synthesize your Verilog design and generate an EDIF netlist file Import the EDIF file into the Project Navigator Implement the design using the pack place and route processes Set report viewing options and view the reports Run static timing analysis using the Performance Analyst and view the results 2005 Lattice Semiconductor 25 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Glossary Following are the the terms and concepts that you should understand to use this tutorial effectively EDIF EDIF Electronic Design Interchange Format is a format used to exchange design data between different electronic computer aided design systems It is designed to be written and read by computer programs that are constituent parts of EDA systems or tools Its syntax has been designed for easy machine parsing and is si
5. Lattice Release OEM Lat Run Started On Thu Mar 10 13 48 45 Pacific Daylight Time 2005 Working Directory tutorial tutor3 2005 Lattice Semiconductor Ln 17 Col 1 IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 4 Use Quick Setup to Synthesize the Design Quick Setup is a push button flow that you can use to achieve good first pass synthesis results You specify the target technology open your input design files optionally set the target clock frequency and verify the name of the output netlist When you click Run Flow the entire synthesis flow is executed from start to finish including synthesis applying global constraints optimization and writing the netlist The output is an EDIF netlist that can be read by ispLEVER Attributes that are placed on design objects by the HDL source code and LeonardoSpectrum are converted to properties in the EDIF netlist To synthesize the design 1 On the Quick Setup tab under Technology click the plus sign in front of Lattice to expand the tree view and select the ispXPGA device family m Technology ispLSIS000VE ispLSIS000VE_UPS ispLS18000 ispmach4000B ispmach4000C ispmach5000B ispmach5S000VG tat ee AS 2 In the Input field click the Open files icon to open the Set Input File s dialog box LeonardoSpectrum does not read pre compiled HDL designs from disk Instead the source files are r
6. Project Navigator C ISPTOOLS5_0 EXAMPLES TUTORIAL TUTORS mux syn File View Source Process Options Tools Window Help D S E norma S s e v cla e ala aa a ag M A e m e S M wo Sources in Project Processes for current source a mux gt Build Database Documents K Constraint Editor lt 3 LFX1200C 03FE680C 53 Pack amp Place Design B multiplexer4to1 multiple edF E HTML Pack Place Report mux html E Pack Place Report mux rpt Post Place Pinouts K Post Place Design Floorplan fe IBIS Model mux ibs gt Place Timing Checkpoint a Place Timing Report mux trp gt Route Design Route Report mux rlog Post Route Design Floorplan gt Timing Analysis 2 HTML Post Route Timing Report mux htm Post Route Timing Report mux trr Performance Analyst 9 Generate Timing Simulation Files mux nrp a Report File mux nrp Q Generate Bitstream Data Bitstream File mux svl x EDIF Compiler Version 13 0 Mar 8 2005 11 30 21 Generating design hierarchy only Reading multiple edf file Writing out design hierarchy output file EDIF Compiler finished successfully Done completed successfully 5 ofa Ready um 2 Note After you import an EDIF file into the ispLEVER project it is always linked to the Project Navigator Therefore if you make changes and recompile your HDL file to create a new EDIF file your project is automatically updated as w
7. click Finish Your Project Navigator should look like this Note Click on the part name to see the contents of the Processes for Current Source window 2005 Lattice Semiconductor ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow ispLEYER Project Navigator C gt ISPTOOLS5_0 EXAMPLES TUTORIAL TUTORS mux syn File View Source Process Options Tools Window Help D S GAY norma 7e vo co a l e e eee Oe les BM lie WO Sources in Project Processes for current source mux Q Build Database K Constraint Editor D gt Pack amp Place Design HTML Pack Place Report mux html B Documents 3 LFX1200C 03FE Pack Place Report mux rpt Post Place Pinouts K Post Place Design Floorplan f IBIS Model mux ibs 3 Place Timing Checkpoint B Place Timing Report mux trp 5 Route Design Route Report mux rlog Post Route Design Floorplan D gt Timing Analysis E HTML Post Route Timing Report mux htm E Post Route Timing Report mux trr Performance Analyst G Generate Timing Simulation Files mux nrp B Report File mux nrp gt Generate Bitstream Data f Bitstream File mux svl AIfispLEVER Aut o Make Log File 4 Starting C ispTOOLSS_O ispepld bin checkini exe err automake err C ispTOOLSS_O ispepld conf Done completed successfully a Tea wil Ready el 4 8 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with Le
8. to greater than and less than data comparators as shown in the following figure 2 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow COMPDAT cone lt DAT LT_O SEL CLK RST 6T_O gt COMP_EQ EQO This tutorial first directs you to create an EDIF project in the Project Navigator then select the target device in which the design will be implemented The tutorial assumes that functional simulation has already been performed Next you start LeonardoSpectrum and open a new LeonardoSpectrum project After you import the VHDL source files and set the implementation options the tool synthesizes the design into the target device and generates an EDIF netlist You then import the EDIF netlist into the Project Navigator project and fit the design Finally you perform a static timing analysis and examine the results About the Tutorial Data Flow The following figure illustrates the design flow that the tutorial takes You may find it helpful to refer to this diagram as you move through the tutorial tasks 2005 Lattice Semiconductor 3 isoLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Synthesize with multiple edf Leonardo Spectrum p Build database multiple id1 Pack and place design multiple ld2 Route design multiple ld3 Timing analysis Placement Performance Timing Analyst 4 2005 Lattic
9. HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Table of Contents HDL Synthesis Design with LeonardoSpectrum isOXPGA FIOW cceeeeeeeee 2 Task 1 Create a New Project an sicncssceiceoscsocdncnthenieredesdnctddeneannduescncbdiacdensdeentuecduoniis 5 Task 2 Target a DevViCE ata Sa icrns has nsres nadie atcn kasha aston aaita hetao ne TEn en TEn e ETE ETETE EA eSEE ENEE 7 Task 3 Start LeonardoSpectrum from isOLEVER cceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 9 Task 4 Use Quick Setup to Synthesize the DeSIQN cccceeeeeeeeeeeeeeeeeeeeeeees 11 Task 5 Import the EDIF File into Your Project cccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 15 Task 6 Pack and Place the Design eeeeeeeseeceeeeeeeeeeeeeeeeeaeeeeeeeeeeeeeeeeaaeees 17 Task 7 Route the Design sicsceteiccds cctheccmceticies iald cctanatealeeeticecienbltce eldenedanehatiienttncs 19 Task 8 Perform Static Timing Analysis cceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 22 SUMAYE aeda eae A E a E E ENS 25 Glossary ieri RanccentbcesmareatncbatieceiRaeen ce elaine dee eh ania a ciel A outicuds 26 Recommended Reference Materials ccccecesessecceeeeeeeeeeeeeseeeeeeeeeeeeeeeeeeee 27 2005 Lattice Semiconductor Tutor5 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow This tutorial shows you how to use LeonardoSpectrum from withi
10. cal notes and other information on ispXPGAs on the Lattice Web site at http www latticesemi com search literature cfm Click on FPGA gt ispXPGA 2005 Lattice Semiconductor 27
11. e Design Floorplan f IBIS Model mux ibs 3 Place Timing Checkpoint B Place Timing Report mux trp gt Route Design Route Report mux rlog Post Route Design Floorplan D gt Timing Analysis E HTML Post Route Timing Report mux htm Post Route Timing Report mux trr Performance Analyst Generate Timing Simulation Files mux nrp B Report File mux nrp Generate Bitstream Data f Bitstream File mux svl x Placement_Spread Off A But fer_Insertion_Fanout_Limit Off Packing_Datapath 1 Packing_Algorithm 1 Design_Type Normal Data Preparation completed Time 0 329 seconds Placement optimization Time 0 359seconds Total placement Time 0 704 seconds lt Note gt N00000 Placement has been completed successfully Done completed successfully fa KU om 2 Double click the HTML Pack Place Report process to open the report in your browser 2005 Lattice Semiconductor 17 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow This report gives details about the design s packing and placement before routing and includes such sections as summary reports signal lists fanin fanout removed and added logic and the compilation time 3 View the contents and then close the report c isptools5_0 examples tutorial tutor5 mux html Netscape a File Edit View Go Bookmarks Tools Window Help Q Q amp file C ISPTOOL55_0 EXAMPLES TUTORIAL TUTORS mux ht
12. e Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 1 Create a New Project To begin a new project you must create a project directory Then you must give the project file a name syn and declare the project type EDIF The ispLEVER software saves an initial design file with the syn file extension in the directory that you specify All project files are copied to or created in this directory The project type specifies that all design sources will be of this type To create a new project 1 2 2005 Lattice Semiconductor Start the ispLEVER system if it is not already running In the Project Navigator choose File gt New Project to open the Project Wizard dialog box In the dialog box do the following e Inthe Project Name box type mux e In the Location box change to the following directory lt install_path gt examples tutorial tutor5 Note If you want to preserve the original tutorial design files save the tutor5 directory to another location on your computer before proceeding e Inthe Design Entry Type box select EDIF e Inthe Synthesis Tools box select LeonardoSpectrum e Click Next to open the Project Wizard Select Device dialog box ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispoXPGA Flow Project Wizard xi C ISPTOOLS5_OMEXAMPLESSTUTORIALSTUTORS Schematic ABEL Schematic HDL yectrum VHDL Schematic erilo
13. ead directly into memory where LeonardoSpectrum builds an EDIF like in memory database 3 Make sure that you are in the tutorial tutor5 directory 4 Select multiple v Verilog file and click Open 2005 Lattice Semiconductor 11 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Look in a tutor5 e e E File name multiple v Files of type Input Files gt Y VERI H AVER VHD HE Cancel LeonardoSpectrum automatically points the output file to the project directory and places the file name in the Input box Input multiple v Open files icn Working Directory 5 Directly below the Open Files icon click the Working Directory icon to open the Set Working Directory dialog box The working directory is where LeonardoSpectrum places all generated output files These files include the output files from the synthesis process For ispLEVER projects you should make the working directory the same as your project directory 12 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow 6 Make sure the path is pointing to lt install_path gt examples tutorial tutor5 then click Set to close the dialog box x C ispTOOLSS_O examples T utorial tutor5 CI isptracy_tutor E tutori E tutor10 C tutor11 E tutor2 C tutor3 EI tutor4 armi C tutor6 CI tutor G tutor8 CI tutord Cancel DRR TEnA EAE
14. ell 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 6 Pack and Place the Design The ispLEVER software has a single user interface with all options preset to deliver the highest possible push button performance for most devices When you double click a process all the processes prior to that process run automatically Therefore all you have to do is double click the final process However here you will run one process at a time and view the results as you go After an initial internal database is generated the Pack amp Place Design process packs the design instances into programmable functional units PFUs and places them on the ispXPGA device To place and route the design and view the reports 1 With the target device selected in the Sources in Project window double click Pack amp Place Design in the Processes for Current Source window E ispLEYER Project Navigator C ISPTOOLS5_0 EXAMPLES TUTORIAL TUTORS mux syn File View Source Process Options Tools Window Help Da E Normal 7e Sl v cE R am a af a7 m GA e m e ds S a M vO Sources in Project Processes for current source B mux AD Build Database Gj Documents K Constraint Editor E LFx1200C 03FE680C e O Pack amp Place Design B multiplexer4to1 multiple edf A HTML Pack Place Report mux html 2E Pack Place Report mux rpt Post Place Pinouts K Post Plac
15. g Analysis E HTML Post Route Timing Report mux htm Post Route Timing Report mux trr Performance Analyst Generate Timing Simulation Files mux nrp B Report File mux nrp gt Generate Bitstream Data f Bitstream File mux svl Pass wire connectivity check Pass wire completeness check Pass wire replica check The solutions are valid with 0 errors FPGA router completed Done completed successfully EI Pe 2 Choose Options gt Environment to open the Environment Options dialog box Select the Log tab Make sure Using Report Viewer is selected This option enables you to open report files in the Report Viewer rather than in the Output Panel Click OK to close the dialog box 2005 Lattice Semiconductor 19 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispoXPGA Flow 3 20 Environment Options Double click the Route Report process to open the route report which shows how a design was routed in the target device and informs you of the success or failure of the route Note Your timing results may differ slightly 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow amp Report iewer mux rlog F oj x Eile Edit view Options Window Help laj x EspLEVER 5 0 00 32 10 05_CP_ALL FPGA Router Copyright C 1992 2005 Lattice Semiconductor Corporation All Rights Reserved Design mux Router O
16. g HDL Verilog HDL 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 2 Target a Device In the Project Navigator Sources in Project window the device icon 3 appears next to the target device for the project The Project Navigator enables you target a design to a specific Lattice device at any time during the design process The default device is the ispLSI5256VE 165LF256 For this project you will target a different device To view the list of available devices and to change the target device 1 In the Project Wizard Select Device dialog box do the following In the Family box select ispXPGA In the Device box select LFX1200C Accept the default settings for the rest of the boxes Click Next to open the Project Wizard Add Source dialog box Project Wizard Select Device r Select Device Family JispXPGA ispMACH SO00VG Speed grade _ Device LFX200CES 2x LFX125BES 2 LFX125CES 2 LF1 2008 Package type 3 E80feBGA 7 Operating conditions Commercial v Part Name LFx1 200C 03FE680C z Status Density Voltage LUT Block RAM Dist RAM SERDES Pairs 1 0 Cells 170 Pins r Device Information Production 1250K 1 8 15376 414K 246K 20 496 496 x cm ee 2 Inthe Project Wizard Add Source dialog box click Next then
17. milar to LISP The ispLEVER software supports EDIF Version 2 0 0 HDL An HDL is a hardware description language which describes the structure and function of integrated circuits static timing analysis Static timing analysis is the process of verifying circuit timing by totaling the propagation delays along paths between clocked or combinational elements in a circuit The analysis can determine and report timing data such as the critical path setup and hold time requirements and the maximum frequency synthesis Synthesis is the process of translating a high level design RTL description consisting of state machines truth tables and or Boolean equations into a process specific gate level logic implementation VHDL VHDL or VHSIC Very High Speed Integrated Circuits Hardware Description Language is a language for describing the structure and function of integrated circuits Verilog Verilog is a language for describing the structure and function of integrated circuits 26 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Recommended Reference Materials You can find additional information on the subjects covered by this tutorial from the following recommended sources e LeonardoSpectrum for Lattice User s Manual e LeonardoSpectrum for Lattice HDL Synthesis Manual e Lattice ispLEVER online help e How To guides e Process Flows gt ispXPGA Flows e Data sheets techni
18. ml iv SS A y a S Home My Netscape Qy Search S Instant Message S gt WebMail Radio S gt People S Yellow Pages S Download S Calendar channels Q Netscape Enter Search Terms A A Search hHiohlioht O ses che 2 FormFil Clear Browser History B news CA Email T Weather Table of Contents ispLEVER 5 0 00 32 10 05_CP_ALL Pack Place Report File co Copyright C 1999 2003 Lattice Semiconductor Corpora roject Summary User Defined Macros Summary Intellectual Property Summary All Rights Reserved Error Listing Warning Listing Note Listing e Pack and Place Options Project Summary Design Summary ot oe Device Resource Summary Project Name mux PLL Summary Project Type EDIF e HSI Receive Mode Summary Project Synthesis Version 2004b 39_ OEM Lattice HSI Transmit Mode Summary Synthesis Vendor LeonardoSpectrum for Lattice e HSI Loop Back Mode Summary Project Path c isptools5_O examples tutorial tuto EBR Summary Report Date Thu Mar 10 14 08 26 2005 Input Signal List Project constraint file mux let Output Signal List Pack and Placement Input File mux ldi Bi Directional Signal List Pack and Placement Output File g e Unreferenced IO List Device LFX1200c e Compilation Times Package 680feBGA Speed 3 Part Number LFX1200C O3FE680C Project mux Packed and Placed Successfully User Defined Macros Summary None Intellectual Property Summary
19. n ispLEVER to synthesize a Verilog design and generate an EDIF file for a Lattice ispXPGA device Note If you want to learn how to use LeonardoSpectrum in standalone mode or understand more about its advanced features please see the third party manuals online by choosing Help gt ispLEVER Documentation Library from the ispLEVER Project Navigator Learning Objectives When you have completed this tutorial you should be able to do the following e Create anew EDIF project in the ispLEVER system and target a device e Start LeonardoSpectrum from within the Project Navigator synthesize your Verilog design and generate an EDIF netlist file e Import the EDIF file into the Project Navigator and implement the design using the pack place and route processes e Set report viewing options and view the reports e Perform static timing analysis using the Performance Analyst and view the results Time to Complete This Tutorial The time to complete this tutorial is about 20 minutes System Requirements One of the following software configurations is required to complete the tutorial e IspLEVER Starter e ispLEVER Base e ispLEVER Advanced e ispLEVER Advanced System with active Mentor Graphics LeonardoSpectrum license Accessing Online Help You can find online help information on any tool included in the tutorial at any time by pressing the F1 key About the Tutorial Design The tutorial design consists of a simple set of equal
20. onardoSpectrum ispXPGA Flow Task 3 Start LeonardoSpectrum from ispLEVER For HDL designs the ispLEVER software provides two synthesis tools that are integrated into the Project Navigator environment LeonardoSpectrum and Synplify You can synthesize your Verilog or VHDL design as a standalone process by choosing the synthesis tool from the Lattice Semiconductor program group in your Start menu or you can synthesize automatically and seamlessly within the Project Navigator LeonardoSpectrum for Lattice is a logic synthesis tool that starts with a high level design written in the Verilog or VHDL hardware description language HDL Then it converts the HDL description into small high performance design netlists that are optimized for Lattice devices When you start LeonardoSpectrum for the first time the main window is maximized and displays the Tip of the Day and an information screen To start LeonardoSpectrum 1 In the Project Navigator choose Tools gt LeonardoSpectrum Synthesis to open the LeonardoSpectrum synthesis tool It may take a few moments to activate the tool 2 Click OK to close the Tip of the Day There are three ways to synthesize your design Quick Setup Advanced Flow Tabs and Synthesis Wizard In this tutorial you will use the Quick Setup method 3 Make sure the Quick Setup tab is selected on the toolbar Your screen should look similar to the following If not choose Tools gt Quick Setup 2005 La
21. ptions Effort Level HIGH TDR Effort Level HIGH Routing Option 4 Directory c isptoolsS_0 examples tutorial tutorS Initialize router Initialize router completed Time 0 9 seconds Starting iterative routing Routing active signals End of iteration 1 Enter TDR Ripup and Reroute fastCPU Mode 16 successful 100 0 unrouted 0 Total routing time 0 22 seconds Total routing REAL time 2 28 seconds Pass wire connectivity check Pass wire completeness check Pass wire replica check The solutions are valid with 0 errors FPGA router completed 4 gt Ln 1 Col 1 28 RO Rec Off No Wrap DOS INS NUM Document 1 of 1 4 Choose File gt Exit to exit the Report Viewer 2005 Lattice Semiconductor 21 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 8 Perform Static Timing Analysis Static timing analysis is the process of verifying circuit timing by totaling the propagation delays along paths between clocked or combinational elements in a circuit The analysis can determine and report timing data such as the critical path setup and hold time requirements and the maximum frequency The Performance Analyst traces each logical path in the design and calculates the path delays using the device s timing model and worst case AC specifications supplied in the device data sheet The timing analysis results are displayed in a graphical spreadsheet with sou
22. rce signals displayed on the vertical axis and destination signals displayed on the horizontal axis The worst case delay value is displayed in a spreadsheet cell if there is at least one delay path between the source and destination To more easily identify performance bottlenecks you can double click a cell to view the path delay details To perform timing analysis 1 In the Project Navigator Sources in Project window select the target device 2 In the Processes for Current Source window double click the Performance Analyst process to open the Performance Analyst is Performance Analyst Untitled mux File view Net Control Preferences Window Help isl Untitled mux LFX1200C 03FE680C Data Sheet Operating conditions Version 2 1 DELAY TABLE Commercial z SOURCE LI DESTINATI DELAY ns DELAY MH Delay Cons Speed grade r Analysis Max C co C tSUAH tOE C PD C COE C REV 6 tP2P a r Path Control of P Bans St m Display paths longer than P Number of 5 n n For Help press F1 fia 20 23 The Performance Analyst performs eight distinct analyses f MAX tSU tH tPD tRCV tCO tOE tCOE and tP2P The first type fMAX is an internal register to register delay analysis MAX measures the maximum clock operating frequency limited by worst case register to register delay The remaining seven types are 22 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design
23. stest 4 i a High Runtime Is Effort r Output Output File multiple edf m Place And Route J Run Integrated Place and Route data arrival time unconstrained path Design summary in file multiple sun AutoWrite args are multiple edf Writing file multiple edf CPU time taken for this run was 0 6 sec Run Successfully Ended On Thu Mar 10 13 53 05 Pacific Daylight T 0 Info Finished Synthesis run Help working Directory Tutorialtutor5 Ln 174 Col 1 8 Choose File gt Exit to exit LeonardoSpectrum Click Yes in the confirmation box 14 2005 Lattice Semiconductor IspLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Task 5 Import the EDIF File into Your Project You can import EDIF 2 0 0 netlists from third party synthesis tools such as Synplify or LeonardoSpectrum into ispLEVER To import an EDIF netlist into your project 1 In the ispLEVER Project Navigator choose Source gt Import to open the Import File dialog box 2 Select multiple edf and then click Open Look in S wto O oae File name mutiple edf Files of type f Sources txted Ipe The software adds the selected EDIF file multiple edf to the project sources 2005 Lattice Semiconductor 15 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow 16 ispLEYER
24. ttice Semiconductor 9 ispLEVER Tutorials 10 HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Mentor Graphics LeonardoSpectrum for Lattice Information Read Only LS Eile Edit view Tools Window Help js etsam suas re e Quick Setup Run the entire flow from this one condensed page Specify your source file s technology and desired frequency then press Run Flow Info License passed r Technology Lattice Copyright 1990 2004 Mentor Graphics All rights reserved Portions copyright 1991 2004 Compuware Corporation Welcome to LeonardoSpectrum for Lattice Run By xyz m Constraints Clock Frequency Mhz r Optimize Effort Fastest High Runtime _ _ _ Effort r Output Output File m Place And Route F Run Integrated Place and Route 4 4 TP TP active Review Help ix xd Info Attempting to checkout a license to run as LeonardoSpectrum foa Session history will be logged to file C ispTOOLSS_0 ispcpld examp Info Working Directory is now C ispTOOLS5S_0 ispepld examples tuto Info system variable EXEMPLAR set to C ISPTOOLSS_0 SPECTRUM Info Loading Exemplar Blocks file C ISPTOOLSS_0 SPECTRUM data xmp Messages will be logged to file C ispTOOLSS_0 ispcpld examples tut LeonardoSpectrum for Lattice 2004b 39_OEM
25. with LeonardoSpectrum ispXPGA Flow external pin to pin delay analyses Timing threshold filters source and destination filters and path filters can be used to independently fine tune each analysis 3 Under Analysis select tCO and then click Run The tCO path trace analysis reports clock to out delay starting from the primary input going through the clock of flip flops or gate of latches and ending at the primary output In this case it is 10 47 ns Note Your time may differ fellPerformance Analyst Untitled mux File View Net Control Preferences Window Help Peia DELAY TABLE Commercial 4 il nail ai reg_data C SUAH C tOE C IPD C COE CRAC tP2P Options Path Control fi por Set Display tco longer than Apply joo ns Number Delay path reg_data 3 CLK z 10 47 iez 5 4 Click the highlighted cell 10 47 in the spreadsheet window to open the Expanded Path dialog box This dialog box enables you to analyze the individual timing components used to calculate the timing path It shows a source pin From and a destination pin To It also shows the delay type the delay of that path value ns and the cumulative delay of all the signals 2005 Lattice Semiconductor 23 ispLEVER Tutorials HDL Synthesis Design with LeonardoSpectrum ispXPGA Flow Expanded Path a ee ee ee en eyen f D D 0 DO e Ca po a a E C E C Le O eo e Z m o po ee Tie 7 Equations 4 m
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