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S1C17 Family S1C17 Core Manual

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1. 7 17 cmc Jet aH ee 7 18 cmp FOU FOS m C 7 19 cmp c Vat VOUS EE 7 19 7 19 A 7 20 1 7 21 21 7 7 21 QUE 7 21 cmp a vaio Mr pde ER 7 22 cv ab SONS REESE 7 23 cv al yi C 7 24 Hra TS ar 7 25 cv la 7 26 cv Is yp MI M 7 27 di ei ext halt int intl jpa jpa d jpa jpa d jpr jpr d jpr jpr d jreq jreq d Dbpnp 7 38 jrge lLypm 7 39 jrge d CIL e PEE 7 39 jrgt Cp M Ma 7 40 jrgt d 7 40 jrle 7 41 jrle d 7 41 jrit Lippe 7 42 51 17 FAMILY 51 17 CORE MANUAL EPSON iii CONTENTS jrit d 7 42 jrne SI QUAL 7 43 jrne d MEER 7 43 np 7 44 jruge d 7 44 j
2. 000001100 sign7 jrgt 0 0 0 00 1 1 0 1 22 07 20 jrgt d IL IE C V 7 Signed PC relative jrgt Two cycles when not branched Three cycles when branched jrgt d Two cycles 1 Standard jrgt sign7 jrgt sign8 sign7 sign8 7 1 sign8 0 0 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met Z flag 0 and N flag V flag e g gt B has resulted by cmp A B The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jrgt sign7 jrgt sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext immi3 1 13 2 0 sign24 23 21 ext imm13 sign24 20 8 jrgt sign7 jrgt sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates 3 x 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrgt d sign
3. 7 61 Id a v2 cre 7 61 Id a 9erd 96tb tcc cn c e creer etree rere 7 61 Id a verd oS E 7 63 Id a 010 asp 7 63 eM por E 7 63 VIRI M 7 63 Fold 7 65 0 7 66 7 67 OSI ONS E 7 68 m 7 69 7 7 70 TIT I EI 7 70 9orD VOUS rrt mre 7 70 OK 7 70 EXDBINI Im P 7 72 sp 7 72 1965 Re 7 72 7 72 9095 4 107 7 74 7 75 Id b GON VOUS 7 76 Id b 9010 FOND mE 7 77 Id b 9010 FOr 7 77 Id b 9 27 7 77 Id b 2010 1261 reer Tee 7 77 Id b verd 6Sp s Imm eiii eri rere rv PU EE Avera 7 79 Id b em 7 80 Id b 96f8 rir rt D 7 81 iv EPSON 51 17 FAMILY S1C17 MANUAL CONTENTS Id b COPD 5 E e rti nett eere
4. 1 1 1 191 Mode Src Register direct 2rs ro to r7 Dst Register direct rd ro to r7 One cycle 1 Standard or rd rs rd amp rd rs The content of the rs register and that of the rd register are logically OR ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 Or rd rs rd rs imm13 The content of the rs register and the zero extended 13 bit immediate 13 are logically OR ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 2 0 imm16 15 13 ext immi3 immi6 12 0 Or rd rs rd rs 116 The content of the rs register and the zero extended 16 bit immediate imm 6 are logically OR ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution or c Executed as or when the C flag is 1 or executed as nop when the flag is 0 or nc Executed as or when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand
5. 6 2 6 2 1 Instruction Fetch and 6 2 6 2 2 Execution Cycles and 6 3 0 3 1 DES exec ERE 6 6 6 9 T Priority of Interr pts ioo iSo re teri Ne O NT 6 6 6 3 2 25 522255 25428 2552 58 2222422524252 22 2 2220 2 1 24 4412014 16 22 22 2 222 524 6 7 6 3 3 1 Handling ect Reit 6 7 6 7 6 3 5 Address Misaligned 6 8 NM 6 8 6 3 7 Maskable 6 8 6 3 8 Software 6 9 6 3 9 interruptMaskediPehiaod 6 9 6 4 oec ES 6 10 6 5 RR 6 11 6 5 1 Debugging FUNCTIONS Dante ctor ene p qe 6 11 6 5 2 Resource Requirements and Debugging 6 11 6 5 3 Registers for iieri rende ette terea tede im noie 6 12 7 Details of Instructions cceic cc cesi 7 1 adc Vat 7 2 adc c AOT Sisi
6. Remarks 1 One or two ext instruction can be placed prior to the instructions that can be extended Mnemonic Code Function Opcode Operand MSB ie c v 2 N bns 10 27 em SNOILONYLSNI 41916 40 151 XIGNAddV TWANVIN 3900 21915 MINV 21915 NOSd3 1 9 Shift and Swap Instructions S1C17 Core Instruction Set Mnemonic 2 Flags Opcode Operand 8 Code LSB Function Cycle jig 2 Sr Yrs 0101110 Logical shift to right rd 15 0 e rd 15 0 rs 15 0 rd 23 16 0 zero enters to MSB 51 imm7 1101111 Logical shift to right 15 0 lt 15 0 gt gt rd 23 16 lt 0 zero enters to MSB 51 2 O rs 0101110 Arithmetical shift to right rd 15 0 lt rd 15 0 gt gt rs 15 0 rd 23 16 lt 0 sign copied to MSB 51 imm7 1101111 Arithmetical shift to right rd 15 0 lt rd 15 0 gt gt imm7 23 16 0 sign copied to MSB 1 5210 8 rd Yrs 0101110 Logical shift to left rd 15 0 lt rd 15 0 lt lt rs 15 0 rd 23 16 lt 0 zero enters to LSB 51 1 imm7 1101111 Logical shift to left rd 15 0 lt rd 15 0 lt lt imm7 rd 23 16 lt 0 zero enters to LSB 1 2 O 9 Yrs 0101110 9 15 8 lt 7
7. 2 4 2 4 2 SP Operation at Subroutine Call Return pp 2 4 2 4 8 SP Operation when an Interrupt OCCUTS pp 2 5 2 4 4 Saving Restoring Register Data Using a Load Instruction 2 6 2 5 Register Notation and Register Numbers pe 2 7 2 5 1 General Purpose Registers pp 2 7 2 5 2 Special HeglSters 4 2 cde aeter ceo ere oun ated uota 2 7 3 Data Formats 3 1 3 1 Data Formats Handled in Operations Between Registers 3 1 3 1 1 Unsigned 8 Bit Transfer Register 3 1 3 1 2 Signed 8 Bit Transfer Register 3 1 3 1 3 16 Bit Transfer Register Register 3 2 3 1 4 24 Bit Transfer Register Register 3 2 3 2 Data Formats Handled in Operations Between Memory and a Register 3 2 3 2 1 Unsigned 8 Bit Transfer Memory Register 3 3 3 2 2 Signed 8 Bit Transfer Memory 3 3 3 2 3 8 Bit Transfer Register Memory 3 3 3 2 4 16 Bit Transfer Memory Register 3 3 3 2 5 16 Bit Transfer Register Memory pp 3 4 3 2 6 32 Bit Transfer Memory gt 0
8. Dst Register direct rd r0 to r7 One cycle 1 Standard add a rd imm7 rd rd imm7 The 7 bit immediate imm7 is added to the rd register after being zero extended 2 Extension 1 ext immi3 imm20 19 7 add a rd imm7 rd rd imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is added to the rd register after being zero extended 3 Extension 2 ext 1 13 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 add a rd imm7 rd 4 rd imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is added to the rd register 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 add a r0 0x7 rO Ox7f 2 ext Oxf ext Oxlfff add a r1 0x7f rl rl Oxffffff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 7 7 DETAILS OF INSTRUCTIONS add a sp ers ET 24 bit addition Standard 5 23 0 sp 23 0 rs 23 0 Extension 1 sp 23 0 lt rs 23 0 imm13 zero extended Extension 2 sp 23 0 lt rs 23 0 imm24 ETE 8 2765 4 2 1 001100000000 I rs LTEM 000 CV ZN Mode Src Register direct rs r0 to r7 Dst Register direct One cycle 1 Standard add a sp rs Sp Sp rs The content of the rs register is
9. 3 4 3 2 7 32 Bit Transfer Register Memory pp 3 4 4 Address Map MED 4 1 4 1 Address Space a de Hio dese eee 4 1 4 2 Processor Information in the Core I O Area RN 4 2 4 2 1 Trap Table Base Register TTBR 4 2 4 2 2 Processor ID Register IDIR OXffff84 sse 4 2 4 2 3 Debug RAM Base Register 4 2 5 SOU eee 5 1 5 1 5 InstrUctionis e E 5 1 5 2 Addressing Modes without ext extension pp 5 5 5 21 Immediate Addressing eniti apari 5 5 5 2 2 Register Direct 55 5 5 5 2 3 Register Indirect 5 6 5 2 4 Register Indirect Addressing with Post increment decrement or Pre decrement 5 6 5 2 5 Register Indirect Addressing with Displacement 5 7 5 2 6 Signed PC Relative Addressing pp 5 7 5 2 7 PC Absolute Addressing pp 5 7 51 17 FAMILY 51 17 CORE MANUAL EPSON i CONTENTS 5 3 Addressing Modes with 5 8 5 3 1 Extension of Immediate Addressing 5 8 5 3 2 Extension of Register Direct Addressing pp 5 9 5 3 3 Extension of Register Indirect Addressing pp 5 10 5 3 4 Extension of Register Indirect Address
10. 6 rb Yors 0101010 1 rs 1 0 0 0 rb 0 23 0 lt 0 23 0 1 B rb lt rs 7 0 2 6 sptimm7 Yrs 111 1100 rs imm7 B sp imm7 lt rs 7 0 2 5 imm7 Yrs 1110 10 0 rs imm7 B imm7 ers 7 0 1 1 1 1 1 1 134 0 19 06 9erd Yrs 01010 rd 0 0 0 1 rs rd 7 0 lt rs 7 0 9 15 8 lt 0 9 23 16 lt 0 14 1 1 1 1 1 1 19 9erd rb 0101110 10 0 0001 rb 7 0 0 9 15 8 lt 0 9 23 16 lt 0 1 27 1 O 9erd Yorb 01 000 rd 0 1 0 1 rb 7 0 61 9 15 8 lt 0 9 23 16 lt 0 rb 23 0 rb 23 0 1 2 6 9erd rb 01 000 rd 1 1 0 1 rb 7 0 0 9 15 8 lt 0 9 23 16 lt 0 23 0 lt 23 0 1 2 6 rb 0 0 1 0 0 0 rd 1101011 rb rb 23 0 lt rb 23 0 1 rd 7 0 B rb 15 8 lt 0 23 16 lt 0 2 6 rd Yesp imm7 1111001 rd imm7 rd 7 0 B sp imm7 15 8 0 23 16 lt 0 2 1 1 1 1 1 1 158510 imm7 1111000 1 rd imm7 rd 7 0 B imm7 9 15 8 lt 0 23 16 0 1 1 1 1 1 1 1534 O Id Yord Yrs 0 1 010 rd 0010 rs 9 15 0 15 0 23 16 lt 0 1 rd sign7 1100 1 10 sign7 rd 6 0 sign7 6 0 rd 15 7 sign7 6 rd 23 16 0 1 1 1 1 1 1 1542 0 rb 1 1 0 rb rd 15 0 W rb 23 16 lt 0 1 2 7 1 0 Yorb 0 0 110 0
11. oln olo 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit EIN nop Waits 2 cycles 7 96 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS not rs rd rs not nc rd rs Function 16 bit logical negation Standard rd 15 0 lt rs 15 0 rd 23 16 0 Extension 1 rd 15 0 lt imm13 zero extended rd 23 16 lt 0 Extension 2 rd 15 0 lt imm16 rd 23 16 0 coe 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 1 0 1 1 rd 1 0 1 1 TS not 0 0 1 0 1 1 0 0 1 1 TS not c 0 01 0 1 1 rd 0 1 1 1l LE not nc 1 1 10 Mode Src Register direct 515 r0 to r7 Dst Register direct r0 to r7 CLK One cycle 1 Standard not rd e rs The low order 16 bits of the rs register are reversed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 not rd lt immi3 All the bits of the zero extended 13 bit immediate 3 are reversed after zero extended into 16 bits and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Extension 2 ext i
12. 50000 1 rs eo e ee Mode Src Register direct 2rs Sr0 to r7 Dst Register direct rd r0 to r7 One cycle 1 Standard 7 DETAILS OF INSTRUCTIONS co_dout0 lt rd co doutl lt rs rd lt co din psr C V Z N lt cvzn Transfers data set in the rd and rs registers to the coprocessor and gets the operation results by the coprocessor The results are loaded to the rd register and the C V Z and N flags in the PSR 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit S1C17 FAMILY S1C17 CORE MANUAL EPSON 7 85 7 DETAILS OF INSTRUCTIONS 14 rd imm7 Function Transfer data to the coprocessor and get the results Standard co_dout0 lt rd co doutl lt imm7 rd lt co din psr C V Z N lt cvzn Extension 1 0 lt rd doutl 20 rd lt co din psr C Z lt co cvzn Extension 2 dout0 lt rd doutl lt 24 rd din psr C Z lt cvzn gt gt gt 8 7 6 5 4 3 2 0 1 1 1 1 1 7 444 Mode Src Immediate data unsigned Dst Register direct r0 to r7 One cycle 1 Standard ld ca 7 doutl data imm7 Transfers data set in rd regis
13. 819 10 sign24 0 0 The ext instruction extends the displacement into 24 bits using its 13 bit immediate imm13 The 24 bit displacement is added to the PC The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 3 Delayed branch d bit bit 10 1 call d signiO When 11 4 149110 is specified the d bit bit 10 in the instruction code is set and the following instruction becomes a delayed slot instruction The delayed slot instruction is executed before branching to the subroutine Therefore the address PC 4 of the instruction that follows the delayed slot instruction is stored into the stack as the return address When the call d instruction is executed interrupts cannot occur because traps are masked between the ca11 d and delayed slot instructions Oxlfff 0 0 2 address specified by pc 2 0 400 Calls the subroutine that starts from the When the call d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 7 14 EPSON 1C17 FAMILY 51 17 CORE MANUAL calla calla d Caution 7 DETAILS OF INSTRUCTIONS rb rb PC absolute subroutine call Standard sp lt sp 4 A sp lt pe 2 lt r
14. the displacement must W sp 0x82 lt 16 low order bits of specify a 16 bit boundary address least significant bit 0 Specifying an odd address causes an address misaligned interrupt Note however that the data transfer is performed by setting the least significant bit of the address to 0 7 56 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id imm7 rs Function Code Flag CLK Description 16 bit data transfer Standard Wiimm7 lt rs 15 0 Extension 1 W imm20 lt rs 15 0 Extension 2 W imm24 lt rs 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 I 1 0 rs IL IE V ZN Src Register direct 2rs r0 to r7 Dst Immediate data unsigned One cycle 1 Standard ld imm7 rs memory address imm7 The 16 low order bits of the rs register are transferred to the memory address specified with the 7 bit immediate imm7 2 Extension 1 ext immi3 imm20 19 7 ld imm7 rs memory address imm20 imm7 imm20 6 0 The ext instruction extends the memory address to a 20 bit quantity As a result the 16 low order bits of the rs register are transferred to the memory address specified with the 20 bit immediate imm20 3 Extension 2 ext imm13 imm24 23 20 ext imm13 imm24 19 7 14 7 3 6 memory address imm24 imm7 imm24 6 0 The two ext instructions extend the memory address to a 24 b
15. Tape amp reel BACK OC TCPBR 2 directions OD TCP 2 directions OE TCPBD 2directions OF Tape 8 reel FRONT OG TCPBT 4directions OH TCPBD 4 directions 0J TCP SL 2 directions OK TCPSR 2directions OL Tape amp reel LEFT OM TCP ST 2 directions ON TCP 2directions OP TCP ST 4 directions 0Q TCP SD 4 directions OR Tape amp reel RIGHT 99 Specs not fixed Specification Package D die form F QFP B BGA Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 17000 H2 1 00 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler package Sx Middleware package Corresponding model number 17 for 1C17xxx Tool classification C microcomputer use Product classification 185501 development tool for semiconductor products CONTENTS Contents Jede M 1 1 UII t E 1 1 2 ES 2 1 2 1 General Purpose Registers 7 2 1 2 2 Program Counter PO eoru ais eae en Beenie 2 1 2 3 Processor Status Register 2 2 2A Stack Pointer SP 2 4 2 4 1 About the Stack
16. lt rs imm24 Mnemonic Opcode Operand 8 Gods LSB Function Yrs 01011111110 1101010 Ts rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 lt 0 add c rd Yrs 110 rd 0101010 rs 15 0 lt 15 0 5 15 0 rd 23 16 lt 0 if C 1 nop if C 0 O add nc Yrs 0101111 1110 rd 0111010 Ts rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 lt 0 if C 0 nop if C 1 imm7 rd imm7 rd 15 0 lt rd 15 0 imm7 zero extended 9 23 16 lt 0 o add a 9erd Vrs 0101111 1010 1101010 rs rd 23 0 lt rd 23 0 rs 23 0 add a c 9ers 0 01 1 0 0 rd 0 rs 9 23 0 lt 23 0 23 0 if C 1 nop if C 0 O 9ers 0101111 1010 0111010 rs 9 23 0 lt 9 23 0 23 0 if C 0 nop if C 1 O add a 9 sp rs 0101111101010101010101011 rs sp 23 0 sp 23 0 rs 23 0 O rd imm7 01 111 0 0 0 imm7 rd 23 0 e rd 23 0 imm7 zero extended sp imm7 0 00 imm7 sp 23 0 lt sp 23 0 imm7 zero extended 9ers 01011111110 1101011 rS rd 15 0 lt rd 15 0 rs 15 0 C rd 23 16 0 adc c rd Yrs 010 1111110 rd 0 0 0 1 rs rd 15 0 lt rd 15 0 rs 15 0 C rd 23 16 lt 0 if C 1 nop if C 0 O adc nc Yrs 010 1111110 rd 0 1 0 1 rs rd 15 0 lt rd 15 0 rs 15 0 C rd 23 16 lt 0 if C 0 nop if C 1 O adc rd imm7 1101000 1 rd imm7 rd 15 0 lt rd 15 0 imm7 zero
17. sp Specification for register indirect addressing with post decrement Verb sp Specification for register indirect addressing with pre decrement EXT sptimmxX Specification for register indirect addressing with a displacement Indicates that the operand be extended see the Remarks on each page for the imm7 Specification for a memory address with an immediate data extended operand B XXX An address specified with XXX or the byte data stored in the address Indicates that the operand cannot be extended WIXXX A 16 bit address specified with XXX or the word data stored in the address A XXX A 32 bit address specified with XXX or the 24 bit or 32 bit data stored in the address D Cx Indicates that the instruction can be used as a delayed instruction Immediate Indicates that the instruction cannot be used as a delayed instruction immX A X bit unsigned immediate data signX A X bit signed immediate data Bit Field X Bit X of data X Y A bit field from bit X to bit Y X Y Indicates a bit data configuration Code rd rs rb Register number RO 0 R7 7 d Delayed bit 0 Standard branch instruction 1 Delayed branch instruction Functions lt Indicates that the right item is loaded or set to the left item 4 Addition Subtraction amp OR A XOR SNOILOonHLSNI 3409 21916 40 1511 XIaNaddv 21916 MINV 21915
18. 7 or be tween a general purpose register and an immediate Furthermore the add a and sub a instructions can perform operations between the SP and a general purpose register immediate Immediates in sizes smaller than the opera tion unit 16 bits or 24 bits except for the cmp instruction are zero extended when operation is performed The cmp instruction compares two operands and may alter a flag depending on the comparison result Basically it is used to set conditions for conditional jump instructions If an immediate smaller than operation unit in size is specified as the source it is sign extended when comparison is performed Conditional execution The arithmetic operation instructions for between registers op rs allow use of the switches to specify whether the instruction will be executed or not depending on the C flag status Unconditional execution instructions 3 rd rs op add add a adc sub sub a sbc cmp cmc The instruction without a switch will be always executed regardless how the C flag is set Example add rd rs Instructions executable under C condition rd rs op add add a adc sub sub a sbc cmp cmp a cmc The instruction with the c switch will be executed only when the C flag has been set to 1 Example sub c rd rs Instructions executable under NC condition op nc rd rs op add add a adc sub sub a sbc cmp cmp a cmc The instruction with the
19. 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 r0 r0 rO ro 2 ext 0x1 ext Oxlfff rl1 2r2 rl r2 Ox3fff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 99 7 DETAILS OF INSTRUCTIONS or rd sign7 LT 16 bit logical OR Standard rd 15 0 lt rd 15 0 sign7 sign extended rd 23 16 0 Extension 1 rd 15 0 rd 15 0 sign16 rd 23 16 lt 0 Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EU 0 1 TE PER IL IE C V Z 0 e e Src Immediate data signed Dst Register direct 4rd r0 to r7 One cycle 1 Standard or rd sign7 rd rd sign7 The content of the rd register and the sign extended 7 bit immediate sign7 are logically OR ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 1 13 8 0 19 16 15 7 or rd sign7 rd rd 819116 sign7 signl6 6 0 The content of the rd register and the 16 bit immediate 576176 are logically and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0
20. In this mode memory is accessed beginning with the address that is derived by adding a specified immediate dis placement to register content Unless ext instructions are used this addressing mode can only be used for load instructions that have sp imm7 as the operand Example 14 r0 sp 0x10 The byte data at the address derived by adding Ox10 to the content of the current SP is loaded into the RO register If ext instructions described in Section 5 3 are used ordinary register indirect addressing rb becomes a spe cial addressing mode in which the immediate specified by the ext instruction constitutes the displacement Example ext imm13 ld b rb The memory address to be accessed is rb imm13 5 2 6 Signed PC Relative Addressing This addressing mode is used for jpr jr and 1 1 instructions that have a signed 7 or 10 bit immediate sign7 sign10 or rb in their operand When these instructions are executed the program branches to the address derived by twice adding the sign7 sign10 value 16 bit boundary or the rb register value to the current PC Example PC 0 jrne 0x04 The program branches to the PC 8 address when the j xne branch i condition holds true 0 0x04 2 8 8 5 2 7 PC Absolute Addressing This addressing mode is used for jpa and calla instructions that have an unsigned 7 bit immediate imm7 or rb in their operand When these inst
21. ZN o le e e emp lt gt Mode Src Register direct 2rs Sr0 to r7 Dst Register direct rd ro to r7 One cycle 1 Standard cmp 15 rd rs Subtracts the contents of the rs register from the contents of the rd register and sets or resets the flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the contents of the rd register 2 Extension 1 ext immi3 cmp 15 rs immi3 Subtracts the 13 bit immediate imm13 from the contents of the rs register and sets or resets the flags C Z and according to the results The imm13 is zero extended into 16 bits prior to the operation The operation is performed in 16 bit size It does not change the contents of the rd and rs registers 3 Extension 2 ext imm13 imm13 2 0 imm16 15 13 ext immi3 immi6 12 0 cmp rd rs 11016 Subtracts the 16 bit immediate imm16 from the contents of the rs register and sets or resets flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the contents of the rd and rs registers 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution cmp c Executed as when the C flag is 1 or executed as nop when the flag is 0 cmp nc Executed as cmp when the C flag is 0 or executed as nop when the flag
22. jreq sign7 jreq sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext immi3 1 13 2 0 sign24 23 21 ext imm13 sign24 20 8 jreq sign7 jreq sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates 3 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jreq d sign7 For the req instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j req instruction and the next instruction so no interrupts occur cmp r0 rl jreq 0x2 Skips the next instruction if rl ro When the jreq d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 7 38 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS jrge sign
23. 0x000080 7 26 51 17 FAMILY 51 17 CORE MANUAL cv ls rd rs 7 DETAILS OF INSTRUCTIONS Function Data conversion from 16 bits to 32 bits Standard 23 16 lt 0 rd 15 0 lt rs 15 Extension 1 Unusable Extension 2 Unusable 10 9 8 7 6 4 15 14 13 12 11 0 0 1 0 5 3 1010 rs Mode Src Register direct 2rs r0to r7 Dst Register direct rd 5 0 to r7 One cycle 1 Standard Bit 15 sign bit of 16 bit data of the rs register is transferred to the 16 low order bits of the rd register The eight high order bits of the rd register are set to 0 23 16 15 0 rs S Word Y 23 16 15 0 00000000555555555555555 5 2 Delayed slot instruction This instruction be executed as delayed Slot instruction by writing directly after branch instruction with the bit When the R1 register contains 0x008000 cv ls r0 r1 20 OxOOffff S1C17 FAMILY S1C17 CORE MANUAL EPSON 7 27 7 DETAILS OF INSTRUCTIONS Function Disable interrupts Standard psrdE 0 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 00000000 01 00 0 0 0 0 CV ZN CRGA CLK One cycle 1 Standard Resets the IE bit in the PSR to disable external maskable interrupts The reset interrupt address misaligned interrupt and NMI will
24. 0x08 3 0x03 Maskable external interrupt 3 TTBR 0x0c 31 Ox1f Maskable external interrupt 31 TTBR Ox7c The vector address is one that contains a vector or the jump address for the user s interrupt handler routine that is provided for each interrupt and is executed when the relevant interrupt occurs Because an address value is stored each vector address is located at a 16 bit boundary The memory area in which these vectors are stored is referred to as the vector table The in the Vector Address column represents the base start address of the vector table For the TTBR value refer to the Technical Manual of each model The set value can be read from TTBR trap table base register located at address Oxffff80 6 3 3 Interrupt Handling When an interrupt occurs the processor starts interrupt handling This interrupt handling does not apply for reset and debug interrupts The interrupt handling performed by the processor is outlined below 1 Suspends the instructions currently being executed An interrupt is generated synchronously with the rising edge of the system clock at the end of the cycle of the currently executed instruction 2 Saves the contents of the PC and PSR to the stack SP in that order 3 Clears the IE interrupt enable bit in the PSR to disable maskable interrupts that would occur thereafter If the generated interrupt is a maskable interrupt the IL interrupt level in the PSR is r
25. 0x7c The TTBR is the trap table base address The reti instruction should be used for return from the handler routine int 2 Generates an NMI Cause of interrupt Reset interrupt Address misaligned interrupt NMI External maskable interrupt 0x03 External maskable interrupt Ox 1f 7 32 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS intl 5 imm3 Software interrupt with interrupt level setting Standard sp lt sp 4 A sp lt psr 2 pc lt vector vector No imm psr IL lt imm3 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 fo 1 1 1 0 I imm ZN 91 1 1 1 Immediate data unsigned Three cycles Generates the interrupt of the vector number specified with the imm5 The intl instruction saves the address of the next instruction and the contents of the PSR into the stack then reads the specified interrupt vector from the trap table and sets it to the PC By this processing the program flow branches to the specified interrupt handler routine In addition to this the imm3 value is set to the IL bits in the PSR interrupt level to disable interrupts of which the interrupt level is lower than imm3 while the interrupt handler routine is executed The altered IL bits are restored to the value before the intl instruction is executed when the interrupt handler routine is terminated by t
26. 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 xor r0 0x3e r0 Oxfffe 2 ext 1 xor r1 0x7f Oxffff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 121 7 DETAILS OF INSTRUCTIONS THIS PAGE 15 BLANK 7 122 EPSON 51 17 FAMILY S1C17 MANUAL TWANVIN 3900 21915 MINV 21915 NOSd3 Appendix List of 51 17 Core Instructions 51 17 Core Instruction Set Registers Register Data Flags rd rd A general purpose register RO R7 used as the destination register or its contents IL Interrupt level 9618 rs A general purpose register RO R7 used as the source register or its contents IE Interrupt enable flag 9010 rb A general purpose register 7 that has stored a base address to be accessed in C Carry flag the register indirect addressing mode or its contents V Overflow flag 9 sp 5 Stack pointer SP or its contents 2 Zero flag pc Program counter PC or its contents N Negative flag changed Memory Addresses Memory Data 2 Set 1 reset 0 or not changed rb sp Specification for register indirect addressing 1 Set 1 0 esp Specification for register indirect addressing with post increment 0 Reset 0 0
27. A rb 31 24 0 rb 23 0 lt rb 23 0 4 O rb Yrs 01011101011 5 1111111 rb A rb 23 0 rs 23 0 A rb 31 24 lt 0 rb 23 0 rb 23 0 4 rb Yrs 01011101011 5 1101111 23 0 lt 10 23 0 4 A rb 23 0 rs 23 0 A rb 31 24 0 sp imm7 ers 11 1111 rs imm7 A sp cimm7 23 0 rs 23 0 A sp imm7 31 24 0 imm7 rs 11110 111111 5 imm7 A imm7 23 0 lt rs 23 0 A imm7 31 24 0 5 01011111111 rd 0101010 00 rd 23 2 lt sp 23 2 rd 1 0 0 7 01011111111 0111010 0 0 23 0 lt 23 0 2 rd sp 00 1 1 1 1 rd 0101 110 0 0 rd 23 0 lt A sp 23 0 ignored A sp 31 24 5 01011111111 rd 0111111010 0 0 lt 23 0 ignored A sp 31 24 sp 23 0 lt sp 23 0 4 5 01011111111 rd 11111 11010 0 rd 23 0 A sp 23 0 lt 5 31 24 sp 23 0 lt sp 23 0 4 rd sp 01011111111 rd 1 10 11111010101sp 23 0 esp 23 0 4 23 0 5 23 0 ignoredA sp 31 24 sp ers 01011111111 5 001 111 0 0 5 23 0 5 23 0 31 24 lt 0 5 rs 01011111111 5 0111111111010 A sp 23 0 lt rs 23 0 A sp 31 24 lt 0 sp 23 0 lt sp 23 0 4 O sp rs 0011111 rs 11111111110 0 5 23 0 5 23 0 A sp 31 24 lt 0 23 0 lt 23 0 4 O sp rs 01011111111 rs 1 111 0 0 sp 23 0 lt sp 23 0 4 A sp 23 0 lt rs 23 0
28. Figure 2 4 2 2 SP and Stack 2 2 4 3 SP Operation when an Interrupt Occurs If an interrupt or a software interrupt resulting from the int int1 instruction occurs the processor enters an inter rupt handling process The processor saves the contents of the PC and PSR into the stack indicated by the SP before branching to the rel evant interrupt handler routine This is to save the contents of the two registers before they are altered by interrupt handling The PC and PSR data is saved into the stack as shown in the diagram below For returning from the handler routine the reti instruction is used to restore the contents of the PC and PSR from the stack In the reti instruction the PC and PSR are read out of the stack and the SP address is altered as shown in the diagram below SP operation when an interrupt occurred 1 SP SP 4 2 PC SP 3 PSR gt SP 3 Oxffffff Oxffffff 7 0 7 0 SP gt 0x00 23 16 PC 15 8 SP SP 4 7 0 0x000000 0 000000 Figure 2 4 3 1 SP and Stack 3 SP operation when the ret i instruction is executed 1 SP PC 2 SP 3 PSR 3 SP SP 4 Oxffftff Y 0 7 0 SP SP 4 PSR PSR PC 23 16 PC 23 16 PC 15 8 PC 15 8 SP 0 PC 7 0 Y 4 0x000000 0x000000 Figure 2 4 3 2 SP and Stack 4 S1C17 FAMILY S1C17 CORE MANUAL EPSON 2
29. instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 13 7 DETAILS OF INSTRUCTIONS 51900110 call d sign10 Function PC relative subroutine call sp lt sp 4 A sp pc 2 pc lt pc 2 sign10 x 2 Extension 1 sp lt sp 4 A sp lt pc 2 pc pc 2 sign24 CLK Standard Extension 2 Unusable H 5050 00 000009 8 276525252 1 0 Mode Signed PC relative 1 Standard EVI call 0 001 1 0 2 518110 mE call 0 0 0 1 1 1 signl0 2 11 4 IL IE C V ZN call Four cycles call d Three cycles call 191010 call signii 819 10 sign11 10 1 signi1 0 0 Stores the address of the following instruction into the stack then doubles the signed 10 bit immediate sign 0 and adds it to the PC PC 2 for calling the subroutine that starts from the address The sign O specifies a word address in 16 bit units When the ret instruction is executed in the subroutine the program flow returns to the instruction following 11 instruction The sign10 x2 allows branches within the range of PC 1 022 to PC 1 024 2 Extension 1 ext call 1 13 sign24 23 11 call sign24 sign24 10 1 signiO
30. jrge sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates imm13 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrge d sign7 For the instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j rge d instruction and the next instruction so no interrupts occur cmp 0 1 r0 and r1 contain signed data jrge 0x2 Skips the next instruction if r0 2 r1 When jrge d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 39 7 DETAILS OF INSTRUCTIONS jrgt sign7 jrgt d sign7 CLK Conditional PC relative jump for judgment of signed operation results Standard pe lt pe 2 sign7 x 21 7 amp is true Extension 1 pc lt 2 sign21 if 17 8 is true Extension 2 pc lt pc 2 sign24 if 17 8 is true 15 14 13 12 11 10 9 8 7 6 5 4 3 2
31. rO Oxffff80 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 23 7 DETAILS OF INSTRUCTIONS cv al 9615 Function Data conversion from 32 bits to 24 bits Standard 23 16 lt rs 7 0 rd 15 0 lt rd 15 0 Extension 1 Unusable Extension 2 Unusable H 7 6 4 1 0 0 1 0 10 1 1 1 1 rs LTEM 000 CV ZN Mode Src Register direct 15 r0 to r7 Dst Register direct r0 to r7 One cycle 1 Standard The eight low order bits of the rs register are transferred to the eight high order bits of the rd register 23 8 7 0 rs X 8 bits Y 23 16 15 0 rd 8 bits Unchanged 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit Example When R1 register contains and the RO register contains 0x0 cv al r0 r1 Oxff0000 7 24 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS cv as rd 9615 Function Data conversion from 16 bits to 24 bits Standard rd 23 16 lt rs 15 rd 15 0 lt rs 15 0 Extension 1 Unusable Extension 2 Unusable EINEN 0000000 8 7 6 1 5 0 0 1 0 1 0 rd 1 01 1 rs ENE ECV o Mode Src Register direct 2rs Sr0 to r7 Dst Register direct rd 5 0 to r7 One cycle 1 Standard The 16 low order b
32. rO 0x2 ext ld a ro lt 0x82 The imm7 must specify a 32 bit boundary address two least significant bits 0 Specifying other address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 7 66 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS ld a rd imm7 Function Code Flag CLK Description 24 bit data transfer Standard rd 6 0 lt imm7 rd 23 7 0 Extension 1 rd 19 0 lt imm20 rd 23 20 lt 0 Extension 2 rd 23 0 lt imm24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 9 3 1 1 1 rd 2 IL IE 7 Src Immediate data unsigned Dst Register direct rd 5 0 to r7 One cycle 1 Standard ld a rd imm7 rd 4 1007 zero extended The 7 bit immediate imm7 is loaded to the rd register after being zero extended 2 Extension 1 ext 1 13 619 20 19 7 ld a rd imm7 rd imm20 zero extended imm7 imm20 6 0 The immediate data is extended into a 20 bit quantity by the ext instruction and it is loaded to the rd register after being zero extended 3 Extension 2 ext immi3 imm24 23 20 ext 1 13 imm24 19 7 ld a rd imm7 rd lt imm24 imm7 imm24 6 0 The immediate data is extended into a 24 bit quantity by the ext instruction and it is loaded to the rd register 4 Delayed slot instructi
33. sp r2 Sp r2 Ox3fff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 117 7 DETAILS OF INSTRUCTIONS sub a sp imm7 24 bit subtraction Standard sp 23 0 sp 23 0 imm7 zero extended Extension 1 5 23 0 lt sp 23 0 imm20 zero extended Extension 2 sp 23 0 lt sp 23 0 imm24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 011011000 o dmm7 IL IE C V ZN Src Immediate data unsigned Dst Register direct One cycle 1 Standard sub a sp imm7 Sp lt sp imm7 The 7 bit immediate imm7 is subtracted from the stack pointer SP after being zero extended 2 Extension 1 ext immi3 imm20 19 7 sub a sp imm7 Sp sp imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is subtracted from the stack pointer SP after being zero extended 3 Extension 2 ext imm13 imm13 3 0 imm24 23 20 ext imm13 imm24 19 7 sub a sp imm7 Sp lt sp imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is subtracted from the stack pointer SP 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 sub a 0 7 sp Ox7f 2 ext Oxlfff sub a 0 7 Sp sp Oxfffff 7 118 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS swap rs
34. with pre decrement option Standard rb 23 0 lt rb 23 0 2 rd 15 0 lt W rb rd 23 16 0 Extension 1 rb 23 0 lt rb 23 0 imm13 rd 15 0 lt W rb imm13 rd 23 16 lt 0 Extension 2 rb 23 0 lt rb 23 0 imm24 rd 15 0 lt W rb imm24 4 23 16 lt 0 Code 00500000 000090 0765 552 00 1 0 0 0 rd 0 0 1 0 rb ld rd brb 0 0 1 0 0 0 0 1 1 0 rb ld rd 001 00 0 rd 1 1 1 0 tb ld brb 00 1 00 0 1 0 1 0 rb ld rd rb Mode Src Register indirect rb r0 to r7 Dst Register direct rd r0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard ld rd memory address rb The 16 bit data in the specified memory location is transferred to the rd register The rb register contains the memory address to be accessed The eight high order bits of the rd register are set to 0 2 Extension 1 ext immi3 ld rd rb memory address rb 13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the 16 bit data in which is transferred to the rd register The content of the rb register is not altered The eight high order bits of the rd register are set to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 49 7
35. 000 0 0 0 0 1 0 0 1 0 1 0 0 0 reti 0 1 1 0 1 0 1 0 0 0 reti a CLK reti Three cycles reti d Two cycles 1 Standard reti Restores the contents of the PC and PSR that were saved to the stack when an interrupt occurred to the respective registers and return from the trap handler routine The SP is incremented by an amount equivalent to 32 bits 2 Delayed branch d bit bit 7 1 reti d For the ret instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program returns from the trap handler routine Interrupts are masked in intervals between reti d instruction and the next instruction so no interrupts occur Example reti Return from a trap handler routine 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 103 7 DETAILS OF INSTRUCTIONS sa rs Arithmetic shift to the right Standard Shift the content of rd to right as many bits as specified by rs 0 3 4 or 8 bits MSB MSB sign bit Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 9 0 0 1 0 1 1 rd 1 10 I rs IE C V 7 e e e Src Register direct rs r0 to r7 Dst Register direct r0 to r7 One cycle 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the
36. 010101010101011 4 0101011 rb spe sp 4 lt 2 9 0 4 4 lt 1 pcerb 3 ret ret d 0 0 0 0 lt 5 23 0 spe sp 4 3 int imm5 011111110 11 101010 imm5 0 1 4 5 lt pc 2 pce vector TTBR imm5x4 intl imm5 imm3 0111110 1 imm3 imm5 111 4 2 pce vector TTBR imm5x4 psr IL e imm3 reti reti d 00 psr pc lt Al sp lt 5 4 brk 010 010 101010 11011 1 0 010 10 0 A DBRAM psr pc 2 AADBRAM 4 lt r0 pc lt Oxfffc00 retd 01010101010 101110 11 1 0 11 0 0 0 0 41 23 0 psr lt Remarks 1 With one EXT displacement sign21 imm13 sign7 0 With two EXT displacement sign24 1st imm13 2 0 2nd imm13 sign7 0 2 With one EXT absolute address sign20 imm13 imm7 With two EXT absolute address sign24 1st imm13 3 0 2nd imm13 imm7 3 These instructions become a delayed branch instruction when the d bit in the code is set to 1 by suffixing d to the opcode jrgt d call d etc 4 With one EXT displacement sign24 imm13 sign10 0j The conditional branch instructions other than delayed instructions without d are executed in two cycles when the program flow does not branch or three cycles when the program flow branches Immediate Extension Instruction 51 17 Core Instruction Set
37. 1 soc r0 r1 2 Subtraction of 32 bit data sbc rd rs rd amp rs The content of rs register and C carry flag are subtracted from rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 sbc rd lt rs immi3 The 13 bit immediate imm13 and C carry flag are subtracted from the rs register after being zero extended and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 2 0 imm16 15 13 ext immi3 imm16 12 0 sbe rd rs 11016 The 16 bit immediate and C carry flag are subtracted from the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution Sbc c Executed as sbc when the C flag is 1 or executed as nop when the flag is 0 Sbc nc Executed as sbc when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by wr
38. 1 cycle With EXT 2 cycles 3 4 5 6 7 TWANVIN 3900 21915 MINV 21915 NOSd3 e dy Data Transfer Instructions 2 51 17 Core Instruction Set Mnemonic 7 Opcode Operand MSB ram LSB sp imm7 rs 11111111110 rs imm7 5 7 lt 5 15 0 imm7 ers 1 01 110 Ts imm7 W imm7 ers 15 0 rs 0 0 1 0 1 0 rd 0101111 rs rd 23 0 rs 23 0 1001111 rd imm7 6 0 lt 7 6 0 rd 23 7 0 rb 010 110 1010 rd 0 0 1 1 rb 23 0 lt 0 23 0 ignored A rb 31 24 rb 0 0 1 0 0 0 rd 0111111 rb rd 23 0 A rb 23 0 ignored A rb 31 24 rb 23 0 e rb 23 0 4 rd rb 01011 0 1010 1111111 rb rd 23 0 A rb 23 0 ignored A rb 31 24 rb 23 0 e rb 23 0 4 rb 01011 101010 rd 1101111 rb rb 23 0 lt rb 23 0 4 rd 23 0 lt Al rb 23 0 ignored A rb 31 24 71 11 111 01111 rd imm7 9 23 0 lt 23 0 ignored A sp cimm7 31 24 rd imm7 1111001 1 rd imm7 rd 23 0 A imm7 23 0 ignored A imm7 31 24 Verb rs 01011101011 5 0101111 rb A rb 23 0 e rs 23 0 0 31 24 lt 0 rb rs 0 0 1 0 0 1 rs 0111111 rb A rb 23 0 rs 23 0
39. 3 Delayed slot instruction 1 2 This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed r0 0x3e r0 r0 Oxfffe ext Oxff or 1 0 7 1 oxvftf 7 100 EPSON 51 17 FAMILY S1C17 CORE MANUAL ret ret d Function Return from subroutine Standard 7 DETAILS OF INSTRUCTIONS pc lt A sp 23 0 sp lt sp 4 Extension 1 Unusable Extension 2 Unusable 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 0 1 0 0 1 0 0 0 0 0 ret 0 0100 0 ret a ret ret d 1 Standard ret Three cycles Two cycles Restores the PC value return address that was saved into the stack when the call calla instruction was executed for returning the program flow from the subroutine to the routine that called the subroutine The SP is incremented by 32 bits If the SP has been modified in the subroutine it is necessary to return the SP value before executing the ret instruction 2 Delayed branch d bit bit 7 1 ret d For the ret d instruction the next instruction becomes delayed slot instruction A delayed slot instruction is executed before the program returns from the subroutine Interrupts are masked in intervals between the ret d instruction and the next instruct
40. All the bits of the sign extended 7 bit immediate sign7 are reversed after sign extended into 16 bits and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 imm13 8 0 19 16 15 7 not 5 7 rd lt 18619016 81917 5 9 16 6 0 All the bits of the sign extended 16 bit immediate sign 6 are reversed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after branch instruction with the 4 bit instruction cannot be performed ETIAM 1 not r0 0x7f r0 2 ext 1 not r1 0x7 In this case extension of the immediate by ext OxOOffcO 0x000000 7 98 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Or Yrs rd rs or nc rs 16 bit logical OR Standard rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 lt 0 Extension 1 rd 15 0 lt rs 15 0 imm13 zero extended rd 23 16 lt 0 Extension 2 rd 15 0 lt rs 15 0 imm16 23 16 0 ETE 8 2765 552 1 1 9 0 1 0 1 1 1 0 0 1 rs 0 0 1 0 1 1 0 0 0 1 rs 00101 01 0 1
41. Swap Standard rd 15 8 lt rs 7 0 rd 7 0 lt rs 15 8 rd 23 16 0 Extension 1 Unusable Extension 2 Unusable ETE 8 265 1 1 9 0 1 0 1 1 1 1 2 1 rs IL IE V 7 Flag Scie Mode Src Register direct 2rs Sr0 to r7 Era Dst Register direct rd r0 to r7 CLK One cycle 1 Standard Swaps byte order of 16 low order bits of rs register high and low and loads results to the rd register 23 16 15 8 7 0 Byte 1 Byte 0 rdooooooooQ Byte 0 Byte 1 15 8 7 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after branch instruction with the bit BEST when rl 0x123456 swap r2 rl1 0x005634 r2 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 119 7 DETAILS OF INSTRUCTIONS xor Yrs xor c rd rs xor nc rd rs Function 16 bit exclusive OR Standard rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 0 Extension 1 rd 15 0 lt rs 15 0 imm13 zero extended rd 23 16 lt 0 Extension 2 rd 15 0 lt rs 15 0 imm16 rd 23 16 0 ETE 8 7 6 552 1 0 0 1 0 1 1 rd 1 0 1 0 TS xor 0 0 1 0 1 1 0 0 1 0 TS 0 0 1 0 I 1 rd 0 1 1 0 ws Fig L E C V ZN 0 Mode Src Register direct rs r0 to
42. When no ext is used as in 1 shown above 4 32 bit size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed The SP and the displacement must specify a 32 bit boundary address two least significant bits 0 Specifying other address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 73 7 DETAILS OF INSTRUCTIONS 14 Sp rs ETE 5 7 6 4 2 1 32 bit data transfer Standard imm7 23 0 lt rs 23 0 Alsp imm7 31 24 0 Extension 1 A sp imm20 23 0 lt rs 23 0 A sp imm20 31 24 lt 0 Extension 2 A sp imm24 23 0 lt rs 23 0 A sp imm24 31 24 lt 0 1 1 1 1 1 1 rs imm7 ME IL IE C V 7 Src Register direct rs r0 to r7 Dst Register indirect with displacement Two cycles 1 Standard 14 imm7 2rs memory address SP imm7 The content of the rs register is transferred to specified memory location The content of the current SP with the 7 bit immedi
43. a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed The rb register and the displacement must specify a 16 bit boundary address least significant bit 0 Specifying an odd address causes an address misaligned interrupt Note however that the data transfer is performed by setting the least significant bit of the address to 0 7 50 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id erd esp imm7 16 bit data transfer Standard rd 15 0 lt W sp imm7 rd 23 16 lt 0 Extension 1 rd 15 0 lt W sp 20 rd 23 16 lt 0 Extension 2 rd 15 0 lt W sp imm24 rd 23 16 lt 0 Function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 0 rd IL IE C ZN Mode Src Register indirect with displacement Dst Register direct rd r0 to r7 Two cycles 1 Standard ld 5 imm7 memory address sp imm7 The 16 bit data in the specified memory location is transferred to the rd register The content of the current SP with the 7 bit immediate imm7 added as displacement comprises the memory address to be accessed The eight high order bits of the rd register are set to 0 2 Extension 1 ext immi3 imm20 19 7 ld rd sp imm7 memory address sp imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quant
44. branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 7 78 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id b rd sp imm7 Signed byte data transfer Standard 7 0 lt B sp imm7 rd 15 8 lt B sp imm7 7 rd 23 16 lt 0 Extension 1 rd 7 0 lt B sp imm20 rd 15 8 lt B sp imm20 7 rd 23 16 lt 0 Extension 2 rd 7 0 lt B sp imm24 rd 15 8 lt B sp imm24 7 rd 23 16 lt 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 1 1 0 0 0 rd IL IE C V ZN EXER EAE Mode Src Register indirect with displacement Dst Register direct rd r0 to r7 Two cycles 1 Standard ld b rd sp imm7 memory address sp imm7 The byte data in the specified memory location is transferred to the rd register after being sign extended to 16 bits The content of the current SP with the 7 bit immediate imm7 added as displacement comprises the memory address to be accessed The eight high order bits of the rd register are set to 0 2 Extension 1 ext 1 13 imm20 19 7 ld b rd sp imm7 memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the SP with the 20 bit immediate imm20 added comprises the memory address the byte data in which is transferred to the rd regi
45. e adc rd imm7 1 ET e e e rd rs 1 lt e e sub c rd rs 1 e e es sub nc rd rs 1 e e sub rd imm7 1 es e e e sub a rd rs 1 sub a c rd rs 1 m sub a nc rd rs 1 sub a Ssp rs 1 E rd imm7 1 7 1 sbc rd rs 1 PES e e sbc c rd rs 1 e e ey rd rs 1 e e sbc rd imm7 1 ET lt e es rd rs 1 es e rd rs 1 e e cmp nc rd rs 1 e e cmp rd sign7 1 1 rd rs 1 m cmp a nc rd rs 1 E E cmp a imm7 1 E e cmc rd rs 1 es e e rd rs 1 gt ey cmc nc rd rs 1 e e cmc rd sign7 1 e e e e Logical operation and 1 0 e e and c rd rs 1 0 e and nc rd rs 1 0 e and grd sign7 1 0 e rd rs 1 0 e or c rd rs 1 0 e or nc rd rs 1 0 e or 1 0 e e xor rd rs 1 0 e rd rs 1 0 e xor nc rd rs 1 0 e xor grd sign7 1 0 es 1 0 e not c rd rs 1 0 e not nc rd rs 1 0 e not 1 0 e e EPSON 51 17 FAMILY S1C17 CORE MANUAL 6 FUNCTIO
46. it is necessary to modify the return address in that case 7 30 EPSON 51 17 FAMILY 51 17 CORE MANUAL halt 7 DETAILS OF INSTRUCTIONS HALT Standard Sets the processor to HALT mode Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 00000 0 eS olo oln Gajra olo IL IE C V Z N Six cycles Sets the processor to HALT mode for power saving Program execution is halted at the same time that the S1C17 Core executes the halt instruction and the processor enters HALT mode HALT mode commonly turns off only the S1C17 Core operation note however that modules to be turned off depend on the implementation of the clock control circuit outside the core Initial reset is one cause that can bring the processor out of HALT mode Other causes depend on the implementation of the clock control circuit outside the S1C17 Core Initial reset maskable external interrupts NMI and debug interrupts are commonly used for canceling HALT mode The interrupt enable disable status set in the processor does not affect the cancellation of HALT mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel HALT mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller depending on the implementation are set to disable interrupts When the processor is taken out of HALT mode using an interrupt that has
47. nc switch will be executed only when the C flag has been cleared to 0 Example srd brs 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 15 5 INSTRUCTION SET 5 7 Shift and Swap Instructions The S1C17 Core supports instructions to shift or swap the register data Sr Logical shift right sl Logical shift left Arithmetic shift left sa Arithmetic shift right swap Swap upper and lower bytes The shift operation is effective for bits 15 to O in the specified register and bits 23 to 16 are set to 0 The number of bits to be shifted can be specified to 0 3 bits 4 bits or 8 bits using the operand 5 or the rs reg ister rslimm7 0 3 Shift 0 to 3 bits 2rslimm7 4 7 Shift 4 bits fixed rslimm7 8 or more Shift 8 bits fixed Example sr rd 1 Bits 15 0 in 2rd logically shifted one bit to the right sl rd 7 Bits 15 0 in 2rd logically shifted four bits to left sa rd Oxf 15 0 in arithmetically shifted eight bits to the right 23 16 15 rd 0 sr Logical shift right 0000000904 gt gt C T 0 23 16 15 rd 0 sl Logical shift left 0 Y 23 16 15 0 sa Arithmetic shift right O 0 00000 0 Op Sign bit The swap instruction replaces the contents of general purpose registers with each other as shown below 23 16 15 8 7 0 rs X X X X X X XK X Byte 1 Byte 0 c PE rdi00000000 Byte 0 By
48. psr IE 1 1 1 111 1 1 1 1 10 0 0 0000 00 1 0000 0 0 lt 0 1 l lol Il I I SNOILONYLSNI 41916 40 1511 XIQN3ddV 8 dV NOSd3 3 00 21915 ATINVS 21915 Coprocessor Interface Instructions 51 17 Core Instruction Set Nhemonie Code Function Opcode Operand MSB LSB Id cw rd rs 0011101 0101140 rS co doutOcrd co doutic rs imm7 011111111 10 imm7 co doutOcrd co_dout1 lt imm7 ld ca rd rs 0011101 0011 rS co doutO rd dout1 rs rde co psr C V Z cvzn 9erd imm7 01111 111 1 imm7 lt din psr C V Z Id cf rd rs 0011101 0 0 0 1 rs co lt dout1 rs psr C Z N e co cvzn imm7 1110 1101 doutOc rd 1 lt psr C V Z lt cvzn Remarks 1 With one EXT dout1 output imm20 With two EXT dout1 output imm24 SNOILONYLSNI 41916 40 151 XIGNAddV EPSON International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA INC EPSON CHINA CO LTD HEADQUARTERS 23F Beijing Silver Tower 24 North RD DongSanHuan 2580 Orchard Parkway San Jose CA 95131 U S A Phone 1 800 22
49. r0 to r7 One cycle 1 Standard Example ld b ld b rd imm7 memory address imm7 The byte data in the memory address specified with the 7 bit immediate imm7 is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 2 Extension 1 ext immi3 imm20 19 7 ld b rd imm7 memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the byte data in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext immi3 imm24 31 19 ext 1 13 imm24 18 6 ld b rd imm7 memory address imm24 imm7 imm24 5 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the byte data in the memory address specified with the 24 bit immediate imm24 is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 0x1 0 0x1 ro 0x81 sign extended 7 80 EPSON 51 17 FAM
50. r7 Dst Register direct 2rd r0 to r7 One cycle 1 Standard rd srs rd rd rs The content of the rs register and that of the rd register are exclusively and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 rd rs rd rs immi3 The content of the rs register and the zero extended 13 bit immediate imm13 are exclusively and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 2 0 16 15 13 ext immi3 imm16 12 0 xor rd rs rd rs 16 The content of the rs register and the 16 bit immediate are exclusively and result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution xor c Executed as xor when the C flag is 1 or executed as nop when the flag is 0 xor nc Executed as xor when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instructi
51. 0 lt sp 23 0 imm24 Id a sp rs with post decrement option Standard A sp 23 0 lt rs 23 0 A sp 31 24 lt 0 sp 23 0 lt sp 23 0 4 Extension 1 A sp imm13 23 0 lt rs 23 0 A sp imm13 31 24 lt 0 sp 23 0 lt sp 23 0 imm13 Extension 2 A sp imm24 23 0 lt rs 23 0 A sp imm24 31 24 lt 0 sp 23 0 lt sp 23 0 imm24 Id a sp rs with pre decrement option Standard sp 23 0 lt sp 23 0 4 A sp 23 0 lt rs 23 0 A sp 3 1 24 lt 0 Extension 1 8 23 0 lt sp 23 0 imm13 A sp imm13 23 0 lt rs 23 0 A sp imm13 31 24 0 Extension 2 sp 23 0 lt sp 23 0 imm24 imm24 23 0 lt rs 23 0 A sp imm24 31 24 0 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 0 01 1 1 1 rs 0 0 1 1 1 0 0 14 4 ssp srs 0 9 1 1 1 1 rs 10 1 1 1 1 0 0 ide ssp srs 0 0 1 1 1 1 rs 1 1 1 1 1 0 0 ssp srs 0 0 1 1 1 1 rs 101 1 0 14 IS spl s rs Src Register direct 2rs r0 to r7 Dst Register indirect One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard ld a memory address sp The content of the rs register 24 bit data is transferred to the specified memory location The SP contains the memory address to be accessed This instruction writes 32 bit data with the eight high order bits set to 0 in the mem
52. 0 rd 23 16 lt 0 if C 0 nop if C 1 0 1 O xor sign7 1010110 rd Sign7 td 15 0 lt rd 15 0 4sign7 sign extended 23 16 0 2 O not rd Yrs 01011101111 rd 1 rs rd 15 0 lt rs 15 0 23 16 lt 0 0 3 not c Yrs 010 1101111 1 rs rd 15 0 e rs 15 0 rd 23 16 lt 0 if C 1 nop if C 0 0 3 O not nc 9erd Yrs 01011101111 1 rS td 15 0 lt rs 15 0 rd 23 16 lt 0 if C 0 nop if C 1 01 531 O 9610 81017 1010111 Sign7 td 15 0 lt sign7 sign extended 23 16 0 0o0o0 2 O Remarks 1 With one EXT rd rs imm13 With two EXT lt rs imm16 2 With one EXT data sign16 3 With one EXT rd imm13 With two EXT rd imm16 SNOILONYLSNI 41916 40 1511 XIaNaddv 9 dy NOSd3 21915 ATINVS 21915 Branch Instructions S1C17 Core Instruction Set Mnemonic Flags Opcode Operand MSB Code LSB Function Cycle tige 2 P jpr jpr d sign10 0 010 110 10 lt 2 9 11 sign11 sign10 0 3 9erb 1 1 2 3 jpa d imm7 010 010 101011 1 4 imm7 pcc 3 Arb 010 010 010 0 1 4 1 0 10 1 r
53. 0 rdl00000000ISSSSSSSSSSSSSSSS S1C17 FAMILY S1C17 CORE MANUAL EPSON 5 23 5 INSTRUCTION SET 5 11 Coprocessor Instructions The S1C17 Core incorporates coprocessor interface and provides dedicated coprocessor instructions listed be low ld cw Transfer data to the coprocessor 14 Transfer data and input the results and flag status to from the coprocessor ld cf flag status from the coprocessor The 1d cw and 1d ca instructions send two 24 bit data set in the rd data 0 and rs data 1 registers to the copro cessor Data 1 can also be specified in an immediate imm7 In this case the 7 bit immediate can be extended into imm20 or imm24 using the ext instruction The 1d ca instruction inputs the results from the coprocessor to the rd register The 1d ca and 1d cf instructions input the flag status from the coprocessor and set it to PSR C V 7 and flags The concrete commands and status of the coprocessor vary with each coprocessor connected to the chip Refer to the user s manual for the coprocessor used 5 24 EPSON 51 17 FAMILY S1C17 CORE MANUAL 6 FUNCTIONS 6 Functions This chapter describes the processing status of the 51 17 Core and outlines the operation 6 1 Transition of the Processor Status The diagram below shows the transition of the operating status in the S1C17 Core Reset state slp instruction Interrupt Interrupt handling SLE
54. 1 9 2 Changes the flags according to the results of Y2 Ox3fff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 21 7 DETAILS OF INSTRUCTIONS cmp a rd imm7 24 bit Standard rd 23 0 imm7 zero extended Extension 1 rd 23 0 imm20 zero extended Extension 2 rd 23 0 imm24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01 11 00 rd IL IE V ZN Src Immediate data unsigned Dst Register direct 4rd r0 to r7 One cycle 1 Standard cmp a 7 rd imm7 Subtracts the 7 bit immediate imm7 from the contents of the rd register and sets or resets the flags V Z according to the results The imm 7 is zero extended into 24 bits prior to the operation It does not change the contents of the rd register 2 Extension 1 ext immi3 imm20 19 7 cmp a 7 rd imm20 imm7 imm20 6 0 Subtracts the 20 bit immediate imm20 from the contents of the rd register and sets or resets the flags C Z and according to the results The imm20 is zero extended into 24 bits prior to the operation It does not change the contents of the rd register 3 Extension 2 ext 1 13 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 cmp a 7 rd imm24 imm7 imm24 6 0 Subtracts the 24 bit immediate imm24 from the contents of the rd register and sets or resets the flags C V Z and N
55. 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 2 0 imm16 15 13 ext immi3 imm16 12 0 adc rd rs rd rs 10016 C The 16 bit immediate imm 6 and C carry flag are added to the content of the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution adc c Executed as adc when the C flag is 1 or executed as nop when the flag is 0 adc nc Executed as adc when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed ETIAM 1 r0 r1 rO 10 114 0 2 Addition of 32 bit data data 1 12 r1 data 2 r4 r3 result 12 rl add r1 r3 Addition of the low order word adc r2 r4 Addition of the high order word 7 2 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS adc imm7 Code Flag CLK Description 16 bit addition with
56. 2 1 0 0 0 1 0 imm7 IL IE C V 7 Src Immediate data unsigned Dst Register direct r0 to r7 One cycle 1 Standard sub rd imm7 rd rd imm7 The 7 bit immediate imm7 is subtracted from the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 imm13 8 0 imm16 15 7 sub rd imm7 rd rd immi6 imm7 The 16 bit immediate imm16 is subtracted from the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 sub r0 0x3f r0 Ox3f 2 ext Oxlff sub r1 0x4f rl Oxffff 7 114 EPSON 51 17 FAMILY S1C17 CORE MANUAL immi6 6 0 7 DETAILS OF INSTRUCTIONS sub a Yrs sub a c erd rs sub a nc rd rs Function 24 bit subtraction Standard rd 23 0 lt rd 23 0 rs 23 0 Extension 1 rd 23 0 lt rs 23 0 imm13 zero extended Extension 2 rd 23 0 rs 23 0 imm24 00500500009 505655 2 1 0 001 100 rd 10 1 rs sub a 001 10 0 0 0 1 0
57. 24 bit immediate imm24 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ext 0 1 14 0x2 r0 0x82 lt ro The imm7 must specify a 32 bit boundary address two least significant bits 0 Specifying other address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 75 7 DETAILS OF INSTRUCTIONS ld b rd rs Function Signed byte data transfer Standard rd 7 0 lt rs 7 0 rd 15 8 lt rs 7 rd 23 16 0 Extension 1 Unusable Extension 2 Unusable EINEN gt gt 8 7 0 0 1 0 1 0 rs LTEM 07 ZN Mode Src Register direct 15 r0 to r7 Dst Register direct r0 to r7 One cycle 1 Standard The eight low order bits of the rs register are transferred to the rd register after being sign ola extended to 16 bits The eight high order bits of the rd register are set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit Example 14 r0 r1 r0 lt r1 7 0 si
58. 5 2 REGISTERS 2 4 4 Saving Restoring Register Data Using a Load Instruction The S1C17 Core provides load instructions to save and restore register data to from stack instead of push pop instructions Saving register data into the stack Example 1d a 1 SP SP 4 2 RO gt SP Oxffffff 7 0 7 0 SP gt 0x00 R0 23 16 15 8 SP SP 4 0 7 0 Y Y 0x000000 0x000000 Figure 2 4 4 1 SP and Stack 5 Restoring register data from the stack Example 1d a r0 5 1 SP gt RO 2 SP SP 4 Oxffffff 7 0 7 0 SP SP 4 gt 0 00 0 00 RO 23 16 RO 23 16 RO 15 8 RO 15 8 SP RO 7 0 RO 7 0 v 0x000000 0x000000 Figure 2 4 4 2 SP and Stack 6 In addition to the instructions shown above some other load instructions have been provided for operating the stack Refer to Chapter 7 Details of Instructions for more information on those instructions 2 6 EPSON 51 17 FAMILY S1C17 CORE MANUAL 2 REGISTERS 2 5 Register Notation and Register Numbers The following describes register notation and register numbers in the S1C17 Core instruction set 2 5 1 General Purpose Registers In the instruction code a general purpose register is specified using a 3 bit field with the register number entered in that field In the m
59. 7 add rd imm7 rd 4 rd immi6 imm7 immi6 6 0 The 16 bit immediate imm 6 is added to the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 add r0 0x3f ro rO Ox3f 2 ext 1 add r1 0x7f sow rl Oxffff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 5 7 DETAILS OF INSTRUCTIONS add a add a c Yrs add a nc rd rs 24 bit addition Standard rd 23 0 rd 23 0 rs 23 0 Extension 1 rd 23 0 lt rs 23 0 imm13 zero extended Extension 2 4 23 0 lt rs 23 0 imm24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 01 1 0 0 rd 1 0 0 0 00 1 100 rd 0 0 0 0 TS add a c 001100 rd 0 1 0 0 ws add a nc IL E C V 7 Src Register direct 2rs r0 to r7 Dst Register direct 2rd r0 to r7 One cycle 1 Standard add a rd rs rd rd rs The content of the rs register is added to the rd register 2 Extension 1 ext imm13 add a rd rs rd rs 11013 The 13 bit immediate imm13 is added to the content of the rs register after being zero extended and the result is loaded into the rd register The cont
60. DETAILS OF INSTRUCTIONS 3 Extension 2 ext immi3 imm13 10 0 imm24 23 13 ext immi3 imm24 12 0 14 srd rb memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the content of the rb register with the 24 bit immediate imm24 added comprises the memory address the 16 bit data in which is transferred to the rd register The content of the rb register is not altered The eight high order bits of the rd register are set to O 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer ld grd rb Load instruction with post increment option The memory address will be incremented after the data transfer has finished ld rd rb Load instruction with post decrement option The memory address will be decremented after the data transfer has finished ld rd rb Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 2 16 bit size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after
61. Data Transfer Instructions 1 S1C17 Core Instruction Set SNOILONYLSNI 41916 40 1511 XIQN3ddV Mnemonic Flags Opcode Operand MsB Gode LSB Cycle 2 PCT P 95 rs 010111011 0 rd rs rd 7 0 lt rs 7 0 9 15 8 lt 7 23 16 lt 0 1 rb 01 000 0000 rb rd 7 0 lt B rb rd 15 8 lt B rb 7 23 16 0 1 27 1 0 9erd Yorb 0 0 1 0 0 0 rd 0 1 0 0 rb rd 7 0 lt B rb rd 15 8 lt B rb 7 rd 23 16 lt 0 rb 23 0 lt rb 23 0 1 2 1 1 1 1 1 1 15346 O 9erd rb 0 101110 10 0 1 110 0 rb 9 7 0 lt 0 rd 15 8 lt B rb 7 23 16 lt 0 rb 23 0 lt rb 23 0 1 2 6 O 9erd rb 01 000 rd 1000 rb 0 23 0 lt 0 23 0 1 rd 7 0 B rb rd 15 8 B rb 7 23 16 lt 0 2 6 O rd 1110100 imm7 rd 7 0 B sp imm7 rd 15 8 B sp imm7 7 9 23 16 lt 0 2 5 0 imm7 1111000 0 rd 7 0 B imm7 9 15 8 lt 7 rd 23 16 0 1 l 4 O Verb Yrs 01011101011 rs rb B rb lt rs 7 0 1271 1 1 1 1 1 15 11 rb Yrs 0101010 1 rs 100 rb B rb lt rs 7 0 rb 23 0 lt rb 23 0 1 2 6 Verb Yrs 0101010 1 rs 111 010 rb B rb lt rs 7 0 rb 23 0 lt rb 23 0 1 2
62. Epson original 16 bit RISC type processor It features low power consumption high speed operation with a maximum 60 MHz to 90 MHz clock large address space up to 16M bytes addressable main instructions executable in one clock cycle and a small sized design The S1C17 Core is suitable for embedded applications that do not need a lot of data processing power like the S1C33 Cores the high end processors such as controllers and sequencers for which an eight bit CPU is commonly used The S1C17 Core incorporates a coprocessor interface allowing implementation of additional computing features Furthermore Seiko Epson provides a software development environment similar to the 51 33 Family that includes an IDE work bench a C compiler a serial ICE and a debugger for supporting the developer to develop application software 1 1 Features Processor type Seiko Epson original 16 bit RISC processor 0 35 0 15 um low power CMOS process technology Operating clock frequency 90 MHz maximum depending on the processor model and process technology Instruction set Code length 16 bit fixed length Number of instructions 111 basic instructions 184 including variations Execution cycle Main instructions executed in one cycles Extended immediate instructions Immediate extended up to 24 bits Compact and fast instruction set optimized for development in C language Register set Eight 24 bit general purpose registers Two 24 bit sp
63. Extension 1 Unusable Extension 2 Unusable Mode Register direct 2rb r0 to r7 CLK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 rb 11 0000000 1 1 0 0 0 0 rb 11 IL IE C V Z N call Four cycles call d Three cycles 1 Standard call rb Stores the address of the following instruction into the stack then adds the contents of the rb register to the PC PC 2 for calling the subroutine that starts from the address set to the PC The LSB of the rb register is invalid and is always handled as 0 When the ret instruction is executed in the subroutine the program flow returns to the instruction following the 11 instruction 2 Delayed branch d bit bit 7 1 call d rb When call d Z rb 15 specified the d bit bit 7 in the instruction code is set and the following instruction becomes a delayed slot instruction The delayed slot instruction is executed before branching to the subroutine Therefore the address PC 4 of the instruction that follows the delayed slot instruction is stored into the stack as the return address When the call d instruction is executed interrupts cannot occur because traps are masked between ca11 d and delayed slot instructions Example call amp 0 Calls the subroutine that starts from 2 ro When call d instruction delayed branch is used be careful to ensure that the next
64. N flags in the PSR are not altered 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit S1C17 FAMILY S1C17 CORE MANUAL EPSON 7 89 7 DETAILS OF INSTRUCTIONS Id cw rd Function Transfer data to the coprocessor H 8 265 5252 1 Standard doutO lt rd lt imm7 Extension 1 co 0 lt rd lt imm20 Extension 2 co 4010 lt rd lt imm24 0 1 1 1 1 0 rd imm7 IL IE V ZN Mode Src Immediate data unsigned Dst Register direct ro 0 r7 One cycle 1 Standard ld cw rd imm7 doutl data imm7 Transfers data set in the rd register and 7 bit immediate imm 7 to the coprocessor The rd register and the C V Z and N flags in the PSR are not altered 2 Extension 1 ext immi3 imm20 19 7 ld cw rd imm7 doutl data imm20 imm7 imm20 6 0 The ext instruction extends the immediate to a 20 bit quantity As a result data set in the rd register and 20 bit immediate irmm20 are transferred to coprocessor The rd register and the C V Z and N flags in the PSR are not altered 3 Extension 2 ext immi3 imm24 31 19 ext immi3 imm24 18 6 ld cw rd imm7 doutl data imm24 imm7 lt imm24 5 0 The two ext instructions extend the displ
65. Rad noch 7 81 Id b T0 C He 7 81 Id b 79101 TOES 7 81 Id b sp 4mm 7 96ES icc REY NER REX PR ER eS 7 83 Id b imm7 rs Id ca YOU YONG ld ca vid ie TT 2 e A E Id cf m IR AE HB Id cf rd imm7 Id cw Yrd 90 8 Id cw rd imm7 Id ub 1 Id ub 96 0 Yar E TT Id ub rb Id ub or 201 Id ub verd 9 6rb inire eerte setti hepar Id ub rd SP Suum 7 94 Id ub Perd DIE 7 95 nOD iubeo iade reisen ce eai cM cp 7 96 not E 7 97 not c 2052 E 7 97 not nc VAGA m 7 97 not 26 7 98 7 99 IO 7 99 or nc Vor YOM ETER HM 7 99 or sign7 7 100 ret retd He 7 101 MOTH 7 102 7 103 M ee 7 103 sa Hrd OK 7
66. S1C17 CORE MANUAL 5 INSTRUCTION SET 5 Instruction Set The S1C17 Core instruction codes are all fixed to 16 bits in length which combined with pipelined processing al lows most important instructions to be executed in one cycle For details refer to the description of each instruction in the latter sections of this manual 5 1 List of Instructions Table 5 1 1 S1C17 Instructions List Classification Data transfer Mnemonic Function ld b General purpose register byte general purpose register sign extended rb Memory byte general purpose register sign extended rb Memory address post increment post decrement and pre decrement functions 2rd rb can be used rb ssp imm7 Stack byte general purpose register sign extended imm7 Memory byte general purpose register sign extended rb rs General purpose register byte memory rb rs Memory address post increment post decrement and pre decrement functions 256 rs can be used rb rs sprimm7 rs General purpose register byte stack imm7 rs General purpose register byte memory ld ub General purpose register byte general purpose register zero extended rb Memory byte general purpose register zero extended rb Memory address post incre
67. S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS jpa d imm7 Unconditional absolute jump Standard lt Extension 1 pc lt imm20 Extension 2 pc lt imm24 15 14 13 12 11 10 9 8 7 0000 00110 7 0000 0 0 1 1 1 jpa d IL IE C V ZN PC absolute jpa Three cycles jpa d Two cycles 1 Standard jpa imm7 The 7 bit immediate imm 7 is loaded to the PC and the program branches to that address The LSB of the imm7 is ignored and is always handled as 0 2 Extension 1 ext immi3 imm20 19 7 jpa imm7 jpa imm20 imm7 imm20 6 0 The ext instruction extends the destination address into 20 bits using its 13 bit immediate imm13 The 20 bit destination address is set to the PC 3 Extension 2 ext immi3 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 jpa imm7 jpa imm24 imm7 imm24 6 0 The 24 bit destination address is set to the PC 4 Delayed branch d bit bit 7 1 jpa d imm7 For jpa d instruction the next instruction becomes delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between jpa d instruction and the next instruction so no interrupts occur ext 0x30 jpa 0x00 Jumps to the address 0x18000 When the jpa d instruction delayed branch is used be careful to ensure that the next instruction is l
68. Signed byte data transfer ld ub Unsigned byte data transfer 1 16 bit data transfer 14 24 32 bit data transfer In signed byte transfers to registers source data is sign extended to 16 bits In unsigned byte transfers source data is zero extended to 16 bits In transfers in which data is transferred from registers data of a specified size on the lower side of the register is the data to be transferred If the destination of transfer is a general purpose register the register content after a transfer is as follows Signed byte data transfer 23 16 15 8 7 0 00000000 55555555 5 Byte data Extended with the sign in bit 7 of the byte data Unsigned byte data transfer 23 16 15 8 7 0 rdj0 000000000000000 Byte data 16 bit data transfer 23 16 15 0 rdj0 0000000 16 bit data 24 32 bit data transfer 23 0 24 bit data Refer to Chapter 3 Data Formats for the data layout in memory 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 13 5 INSTRUCTION SET 5 5 Logical Operation Instructions Four discrete logical operation instructions are available for use with the S1C17 Core Al and Logical AND or Logical OR xor Exclusive OR not Logical NOT logical operations are performed in a specified general purpose register RO R7 The source is one of two ei ther 16 bit data in a specified general purpose register or immediate data 7 13 or 16 bits When
69. The imm13 specified by the first ext instruction is effective for only 3 bits from bit 2 to bit 0 with the 10 high order bits ignored so that sign24 is configured as follows sign24 imm13 2 0 imm15 sign7 0 23 2120 8 7 10 sign24 5 X 111013 51007 0 imm13 2 0 2 Current address 0 v PC Branch destination address 0 The range of addresses to which jumped is PC 8 388 606 to PC 8 388 608 The above range of addresses to which jumped is a theoretical value and is actually limited by the range of memory areas used 5 18 EPSON 51 17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET For jpr rb jpr rb A signed 24 bit relative value is specified for rb The jump address is configured as follows rb 23 1 0 23 1 rb 5 D 23 1 xX o 2 Current address 0 PC Branch destination address 0 The least significant in the rb register is always handled as 0 The range of addresses to which jumped is PC 8 388 606 to PC 8 388 608 The above range of addresses to which jumped is a theoretical value and is actually limited by the range of memory areas used Branch conditions The jpr instruction is an unconditional jump instruction that always cause the program to branch Instructions with names beginning with jr are conditional jump instructions for which the respective branch conditions are set by a combin
70. added to the stack pointer SP 2 Extension 1 ext 1 13 add a sp rs Sp rs immi3 The 13 bit immediate imm13 is added to the content of the rs register after being zero extended and the result is loaded into the stack pointer SP The content of the rs register is not altered 3 Extension 2 ext 1 13 imm13 10 0 imm24 23 13 ext immi3 imm24 12 0 add a Sp lt rs imm24 The 24 bit immediate imm24 is added to the content of the rs register and the result is loaded into the stack pointer SP The content of the rs register is not altered 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 add a sp r0 SP ro 2 ext 0 1 ext Oxlfff add a sp r2 Sp r2 Ox3fff 7 8 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS add a sp 7 Function Code Flag CLK Description 24 bit addition Standard sp 23 0 sp 23 0 imm7 zero extended Extension 1 sp 23 0 sp 23 0 imm20 zero extended Extension 2 sp 23 0 sp 23 0 imm24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 1 0 0 1 0 0 0 IL IE C V Z N Src Immediate data unsigned Dst Register direct sp One cycle 1 Standard a
71. been enabled by the interrupt controller and IE flag the corresponding interrupt handler routine is executed Therefore when the interrupt handler routine is terminated by the reti instruction the processor returns to the instruction next to halt When the interrupt has been disabled the processor restarts the program from the instruction next to halt after the processor is taken out of HALT mode Refer to the technical manual of each model for details of HALT mode halt Sets the processor in HALT mode 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 31 7 DETAILS OF INSTRUCTIONS int imm5 Function Software interrupt Standard Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 sp lt sp 4 A sp lt psr pc 2 lt vector vector No 0 1 1 1 9 8 7 0 1 0 0 0 ol IL IE C V ZN 0 Immediate data unsigned Three cycles Generates interrupt of vector number specified with the 5 The int instruction saves the address of the next instruction and the contents of the PSR into the stack then reads the specified interrupt vector from the trap table and sets it to the PC By this processing the program flow branches to the specified interrupt handler routine imm5 0x00 0x01 0x02 0x03 Ox1f Vector No Vector address 0 TTBR 0x00 1 0 04 2 0 08 3 TTBR 0x0c 31
72. bit quantity As a result the content of the SP with the 24 bit immediate imm24 added comprises the memory address the byte data in which is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed LIN ox ld ub r0 Ssp 0x1 lt sp 0x81 zero extended 7 94 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id ub rd imm7 Unsigned byte data transfer Standard rd 1 0 lt B imm7 rd 15 8 lt 0 rd 23 16 0 Extension 1 rd 7 0 lt B imm20 rd 15 8 lt 0 rd 23 16 lt 0 Extension 2 4 7 0 lt B imm24 rd 15 8 lt 0 rd 23 16 lt 0 15 14 13 12 11 10 9 8 7 6 S 4 3 2 0 1 0 0 0 1 IL IE C V ZN EXE EE Mode Src Immediate data unsigned Dst Register direct rd r0 to r7 One cycle 1 Standard ld ub rd imm7 memory address imm7 The byte data in the memory address specified with the 7 bit immediate imm7 is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 2 Extension 1 ext 1 13 imm20 19 7 ld ub rd imm7 m
73. carry Standard rd 15 0 lt rd 15 0 imm7 zero extended rd 23 16 lt 0 Extension 1 rd 15 0 lt rd 15 0 C rd 23 16 lt 0 Extension 2 Unusable 15 14 13 1 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 rd ILIE C V 7 Src Immediate data unsigned Dst Register direct rd r0 to r7 One cycle 1 Standard adc rd imm7 rd rd imm7 C The 7 bit immediate imm7 and C carry flag are added to rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 imm13 8 0 imm16 15 7 adc rd imm7 rd rd immi6 C 107 immi6 6 0 The 16 bit immediate imm16 and C carry flag are added to the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 r0 0x7f ro rO Ox7f C 2 ext Oxlff adc r1 0x7f sow rl Oxffff C 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 3 7 DETAILS OF INSTRUCTIONS rs add c erd rs add nc ET 16 bit addition Standard rd 15 0 lt rd 15 0 rs 15 0
74. ciis 7 2 adc nc Lom 7 2 adc IR BLE AE Ep EI E 7 8 add Vo T C 7 4 add c je D 7 4 add nc YOR CONS PN 7 4 add 7 5 7 6 ii EPSON 51 17 FAMILY 51 17 CORE MANUAL CONTENTS add a c 7 6 rd Corsi Es 7 6 add a 7 7 add a EIN m 7 8 add a oS Pj MONAT ni iiti atus E be DE e in Idus 7 9 and o M n 7 10 and c viae ONS E NEEUN 7 10 and nc Bar eee gee 7 10 GRIS nM 7 11 Bik A 7 12 701 7 13 call d 70112 2 2 2 22 2 22 02 12 22 2 212 22 22 2 14 221422 22 12 212 2121 12 22 22 5 25 7 13 M 7 14 call d EE 7 14 calla Vj X sei 7 15 calla d 1 7 15 7 16 calla d 7 16 vie MEE LIE 7 17 cmc c ot 9618 7 17 202
75. does not branch the instruction at the next address is executed as the one that follows the branch instruction The return address saved to the stack by the call d or calla d instruction becomes the address for the next instruction following the delayed slot instruction so that the delayed slot instruction is not executed when the program returns from the subroutine No interrupts occur in between a delayed branch instruction and a delayed slot instruction as they are masked out by hardware Application for leaf subroutines The following shows an example application of delayed branch instructions for achieving a fast leaf subroutine call Example jpr d SUB Jumps to a subroutine by a delayed branch instruction ld a r7 pc Loads the return address into a general purpose register by a delayed slot instruction add a r1 r2 Return address SUB jpr Sx7 Return Notes The 14 rd pc instruction must be executed as a delayed slot instruction If it does not follow a delayed branch instruction the PC value that is loaded into the rd register may not be the next instruction address to the 1 instruction e The delayed branch instruction listed below can only be used with the 1 de layed slot instruction jpr d 0 jr d 81917 jpa d rb imm7 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 21 5 INSTRUCTION SET 5 9 System Control Instructions The following five instructions a
76. execution 00000000 c 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit included 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 111 7 DETAILS OF INSTRUCTIONS sr rd 111017 Function Logical shift to the right Shift the content of rd to right as many bits as specified by imm7 0 3 4 or 8 bits MSB 0 H 8 2765 1 Mode Src Immediate unsigned Standard Extension 1 imm7 is extended to imm20 Extension 2 7 is extended to imm24 1 0 1 1 0 0 rd IL IE V ZN lel Dst Register direct 4rd r0 to r7 cycle 1 Standard The rd register is shifted as shown in diagram below The number of bits to be shifted is specified by the 7 bit immediate as follows imm7 0 3 imm7 4 7 0 3 bits 4 bits imm7 8 or more 8 bits Data 0 is placed in the bit 15 of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 23 16 rd register XX XXX XX X 15 after execution 00000000 c 2 Extension Using the ext instruction extends the 7 bit immediate imm7 to 20 bit immediate imm20 or 24 bit immediate imm24 However there is no differe
77. ext Ox7ff ext Oxlfff sub a r1 r2 s r2 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 115 7 DETAILS OF INSTRUCTIONS sub a erd 24 bit subtraction Standard rd 23 0 lt rd 23 0 imm7 zero extended Extension 1 4 23 0 rd 23 0 imm20 zero extended Extension 2 rd 23 0 rd 23 0 imm24 15 14 13 12 11 1 9 8 7 6 5 4 3 2 0 1 1 0 1 0 rd imm7 IL IE C V ZN Src Immediate data unsigned Dst Register direct 4rd r0 to r7 One cycle 1 Standard sub a rd imm7 rd rd imm7 The 7 bit immediate imm7 is subtracted from the rd register after being zero extended 2 Extension 1 ext immi3 imm20 19 7 sub a rd imm7 rd rd imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is subtracted from the rd register after being zero extended 3 Extension 2 ext imm13 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 sub a rd imm7 rd 4 rd imm24 imm7 imm24 6 0 The 24 bit immediate 24 is subtracted from the rs register 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 1 sub a r0 0x7 T0 0 7 2 ext Oxf ext Oxlfff sub a r1 0x7f rl Oxffffff 7 116 EPSON 51 17 FAMILY S1C17 CORE MA
78. halted at the same time the S1C17 Core executes 51 instruction and the processor enters SLEEP mode SLEEP mode commonly turns off the SICI7 Core and on chip peripheral circuit operations thereby it significantly reduces the current consumption in comparison to HALT mode However modules to be turned off depend on the implementation of the clock control circuit outside the core Refer to the technical manual of each model for details Canceling HALT or SLEEP mode Initial reset is one cause that can bring the processor out of HALT or SLEEP mode Other causes depend on the implementation of the clock control circuit outside the S1C17 Core Initial reset maskable external interrupts NMI and debug interrupts are commonly used for canceling HALT and SLEEP modes The interrupt enable disable status set in the processor does not affect the cancellation of HALT or SLEEP mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel HALT and SLEEP modes even if the IE flag in PSR or the interrupt enable bits in the interrupt controller depending on the implementation are set to disable interrupts When the processor is taken out of HALT or SLEEP mode using an interrupt that has been enabled by the interrupt controller and IE flag the corresponding interrupt handler routine is executed Therefore when the interrupt handler routine is terminated by the reti instruction the processor returns
79. name Debug control register Address FFFFAO B Bit D7 5 D4 Name DR Function Reserved Debug request flag Setting Occurred Not occurred Init R W Remarks 0 when being read Reset by writing 1 D3 IBE1 Instruction break 1 enable Enable Disable R W D2 IBE0 Instruction break 0 enable Disable RAW D1 SE Single step enable Enable Disable R W DO DM Debug mode 41 41 41 4 0 0 Enable 0 0 0 Debug mode 0 User mode 0 0 01 0 1 D 7 5 D4 Reserved DR Debug Request Flag Indicates whether an external debug request has occurred or not 1 R 0 R 1 0 W Occurred Not occurred default Flag is reset Has no effect D3 D2 D1 DO This flag is cleared reset to 0 by writing 1 The flag must be cleared before the debug handler routine has been terminated by executing the retd instruction IBE1 Instruction Break 1 Enable Bit Enables disables instruction break 1 R W Enable 0 R W Disable default When this bit is set to 1 instruction fetch addresses will be compared with the value set in the Instruction Break Address Register 1 Oxffffb4 and an instruction break will occur if they are matched Setting this bit to 0 disables the comparison IBEO Instruction Break 0 Enable Bit Enables disables instruction break 0 1 R W Enable 0 R W Disa
80. option is used 1 Standard ld b rb rs memory address rb The eight low order bits of the rs register are transferred to the specified memory location The rb register contains the memory address to be accessed 2 Extension 1 ext imm13 ld b rb rs memory address rb imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the eight low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 13 bit immediate imm 3 added The content of the rb register is not altered 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 81 7 DETAILS OF INSTRUCTIONS 3 Extension 2 ext immi3 imm24 23 13 ext immi3 imm24 12 0 ld b rb rs memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the eight low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 24 bit immediate imm24 added The content of the rb register is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer ld b rb rs Load instruction with post increment option The memory address will be incremented after the data transfer has finished ld b rb
81. rd 23 16 0 Extension 1 4 15 0 lt rs 15 0 imm13 zero extended rd 23 16 lt 0 Extension 2 rd 15 0 lt rs 15 0 imm16 rd 23 16 0 H 000 00055 8 7 6 5 4 3 2 1 0 add 0 0 1 1 10 1 0 0 0 0 0 1 1 1 0 0 0 0 rs 0 0 1 1 10 rd 0 1 0 0 rs add nc add gt lt add c add nc Mode Src Register direct 2rs ro to r7 Dst Register direct 4rd r0 to r7 One cycle 1 Standard add rd rs rd amp rd rs The content of the rs register is added to the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 add rd lt rs immi3 The 13 bit immediate imm13 is added to the content of the rs register after being zero extended and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 2 0 imm16 15 13 ext immi3 imm16 12 0 add rd rs rd rs 11016 The 16 bit immediate imm16 is added to the content of the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 4 Conditio
82. rs imm13 With two EXT lt rs imm24 3 With one EXT data imm16 sign16 4 With one EXT data imm20 With two EXT data imm24 S1C17 Core Instruction Set Mnemonic Flags Opcode Operand Code LSB Function cycle P rd Yrs 01011101111 010 rs 9 15 0 lt 9 15 0 8 6 15 0 rd 23 16 lt 0 5110 and c rd Yrs 01011101111 rd 0 0 5 rd 15 0 e rd 15 0 amp rs 15 0 rd 23 16 lt 0 if C 1 nop if 0 0o0o0 1 O and nc 9erd Yrs 01011101111 rd 0 0 5 9 15 0 lt 9 15 0 8 15 0 rd 23 16 lt 0 if C 0 nop if 1 1 O and rd sign7 1010100 rd Sign7 9 15 0 lt 9 15 0 8819 7 819 extended 23 16 0 2 O rs 01011101111 rd 011 rs rd 15 0 e rd 15 0 rs 15 0 9 23 16 lt 0 01 1 O rd Yrs 01011101111 rd 011 5 rd 15 0 e rd 15 0 rs 15 0 rd 23 16 lt 0 if 1 nop if C 0 0 5110 or nc 9erd Yrs 00 1 0 1 1 rd 011 rs rd 15 0 e rd 15 0 rs 15 0 rd 23 16 lt 0 if C 0 nop if C 1 0 5110 rd sign7 1101001 rd Sign7 rd 15 0 e rd 15 0 sign7 sign extended 9 23 16 lt 0 0o0o0 2 O0O xor 9erd Yrs 01011101111 0 rs rd 15 0 c rd 15 0 rs 15 0 rd 23 16 0 0o0o0 1 O xor c 9erd Yrs 01011101111 0 rs 9 15 0 lt 9 15 0 15 0 rd 23 16 lt 0 if C 1 nop if C 0 0olejej 1 O Yrs 01011101111 rd 0 rs 9 15 0 lt 9 15 0 15
83. rs 2 rb rs 2 rb 2rs 2 Ssp imm7 rs 2 imm7 rs 1 1 1 2rd 5 1 2 1 sp 2 sp 2 sp 2 Remark 1 1 cycle when ext is Used 2 cycles when ext is Used S1C17 FAMILY S1C17 CORE MANUAL EPSON 6 3 6 FUNCTIONS Fla Classification Mnemonic Cycle IL IE 5 7 N Remark Data transfer 14 ssp rs 1 2 1 1 cycle when ext is ssp rs 2 used ssp rs 2 2 cycles when ext is sp rs 2 sp rs 1 7 1 Integer arithmetic add rd rs 1 e operation add c rd rs 1 add nc rd rs 1 e e add rd imm7 1 es e e rd rs 1 E add a c rd rs 1 m add a nc rd rs 1 add a sp rs 1 imm7 1 7 1 ET adc rd rs 1 E es e e rd rs 1 lt gt rd rs 1 e
84. rs Load instruction with post decrement option The memory address will be decremented after the data transfer has finished 14 0 rb rs Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 1 byte size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 7 82 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id b imm7 rs Signed byte data transfer Standard B sp imm7 lt rs 7 0 Extension 1 B sp imm20 lt rs 7 0 Extension 2 B sp imm24 lt rs 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 1 1 1 0 0 TS IL IE V Z EXESERES Mode Src Register direct rs Sr0 to r7 Dst Register indirect with displacement Two cycles 1 Standard ld b sp imm7 rs memory address sp imm7 The eight low order bits of the rs register are transferred to the specified memory location The content of the current SP with the 7 bit immediate imm7 added as displacement comprises the memory
85. rs rd 15 0 rs 15 0 rs 0011111111 0 rs rd 15 0 rs 15 0 if C 1 nop if C 0 rs 01011111111 0111010 5 rd 15 0 rs 15 0 if C 0 nop if C 1 sign7 100 110 0 Sign7 4 15 0 7 extended O Remarks SNOILONYLSNI ZL LS 40 LSIT XIGNAddV TWANVIN 3900 21915 MINV 21915 NOSd3 Integer Arithmetic Operation Instructions 2 S1C17 Core Instruction Set Mnemonic Opcode Operand MSB Code Function M cmp a rs 01011111011 rd d 23 0 rs 23 0 cmp a c 9ers 0011110 1 rd 23 0 rs 23 0 if C 1 nop if C 0 O cmp a nc 9erd rs 0011110 1 d 23 0 rs 23 0 if C 0 nop if C 1 O cmp a imm7 01111 11 010 rd d 23 0 imm7 zero extended 9ers 01011111111 rd 15 0 rs 15 0 C rd Yrs 01011111111 rd rd 15 0 rs 15 0 C if 1 nop if 0 rd Yrs 01011111111 rd rd 15 0 rs 15 0 C if C 0 nop if C 1 sign7 1100110 1 rd 15 0 7 extended C Remarks 1 With one EXT rd rs op imm13 With two EXT rd rs op imm16 2 With one EXT rd lt
86. sign7 immediate in PC relative branch instructions is multiplied by 2 for conversion to a relative value for the jump address and the derived value is then added to PC to determine the jump address The ext instructions extend this relative jump address value Extending to a 21 bit immediate To extend the sign7 immediate to a 21 bit immediate enter one ext instruction directly before the target in struction Example ext imm13 jrgt sign7 jrgt sign21 23 21 20 8 7 1 0 Immediate S S 518 imm13 sign7 0 23 0 PC Current address 0 23 Y 0 PC New address 0 The most significant bit 75 in the immediate that has been extended by the ext instruction is the sign with which bits 23 21 are extended to become signed 21 bit data The most significant bit in sign7 is handled as the MSB data of 7 bit data and not as the sign 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 11 5 INSTRUCTION SET Extending to a 24 bit immediate To extend sign7 immediate to a 24 bit immediate enter two ext instructions directly before target in struction Example ext immi3 1 ext imm13 2 jrgt sign7 jrgt sign24 23 21 20 8 7 1 0 Immediate S 1 imm13 2 sign7 0 imm13 2 0 23 0 PC Current address 0 23 Y 0 PC New address 0 The most significant bit S in the immediate that has been extended by ext instructions is the sign Bits 12 3 in the first ext instruction are unuse
87. than that set in the IL bit field When an interrupt request is accepted the IL bit field is set to the priority level of that interrupt and all interrupt requests generated thereafter with the same or lower priority levels are masked unless the IL bit field is set to a different level or the interrupt handler routine is terminated by the reti instruction IE bit 4 Interrupt Enable This bit controls maskable external interrupts by accepting or disabling them When IE bit 1 the processor enables maskable external interrupts When IE bit 0 the processor disables maskable external interrupts When an interrupt is accepted the PSR is saved to the stack and this bit is cleared to 0 However the PSR is not saved to the stack for debug interrupts nor is this bit cleared to 0 C bit 3 Carry This bit indicates a carry or borrow More specifically this bit is set to 1 when in an add or subtract instruction in which the result of operation is handled as an unsigned 16 bit integer the execution of the instruction result ed in exceeding the range of values representable by an unsigned 16 bit integer or is reset to 0 when the result is within the range of said values The C flag is set under the following conditions 1 When an addition executed by an add instruction resulted in a value greater than the maximum value Oxffff representable by an unsigned 16 bit integer 2 When a subtraction executed by a subtract instruction resulted in a va
88. the PC value that is loaded into the rd register may not be the next instruction address to the 1d a instruction 7 58 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id a rs Function 24 bit data transfer Standard rd 23 0 lt rs 23 0 Extension 1 Unusable Extension 2 Unusable EIE 0000 000 8 7 1 6 5 0 0 1 0 1 0 rd 100 1 1 rs oo 1 1 151 Mode Src Register direct 2rs Sr0 to r7 Dst Register direct rd 5 0 to r7 One cycle 1 Standard The content of the rs register 24 bit data is transferred to the rd register 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit Example ld a 5 0 3 1 r0 r1 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 59 7 DETAILS OF INSTRUCTIONS Function 24 bit data transfer Standard 23 2 lt sp 23 2 rd 1 0 0 Extension 1 Unusable Extension 2 Unusable 00000 00095 7 6 3 2 1 0 0 0 1 1 1 1 rd 0 0 1 0 Q0 0 0 E CV ZN Mode Src Register direct Dst Register direct 4rd ro to r7 One cycle The content of the SP 24 bit data is transferred to the rd register Example ld a r0 sp r0 lt 7 60 EPSON 51 17 FAMILY S1C17 CORE MANUAL Id a Id a Id a
89. to an even address As with the PC relative jump instructions the specifiable displacement can be extended by the ext instruction For details on how to extend the displacement refer to the 1 PC relative jump instructions 4 Absolute call instructions The absolute call instruction calla causes the program to unconditionally call a subroutine starting from the location indicated by the content of a specified general purpose register rb or an immediate imm7 can be ex tended to imm20 or imm24 using the ext instruction as the absolute address When the content of the rb regis ter or the immediate is loaded into PC its least significant bit is always made 0 Refer to the 2 Absolute jump instructions 5 Software interrupts The software interrupts int and 1151 are the instructions that cause the software to generate an interrupt with the vector numbers specified by the operand imm5 by which a specified interrupt handler routine can be ex ecuted When a software interrupt occurs the processor saves the PSR and the instruction address next to int intl to the stack and reads the specified vector from the vector table in order to execute an interrupt handler routine Therefore to return from the interrupt handler routine the reti instruction must be used as it restores PSR as well as the PC from the stack For details on the software interrupt refer to Section 6 3 Interrupts 6 Return instructions The
90. to the instruction next to halt or slp When the interrupt has been disabled the processor restarts the program from the instruction next to halt or slp after the processor is taken out of HALT or SLEEP mode 6 10 EPSON 51 17 FAMILY S1C17 CORE MANUAL 6 FUNCTIONS 6 5 Debug The S1C17 Core has a debug circuit to assist in software development by user 6 5 1 Debugging Functions The debug circuit provides the following functions Instruction break A debug interrupt is generated before the set instruction address is executed An instruction break can be set at two addresses Single step A debug interrupt is generated every instruction executed Forcible break A debug interrupt is generated by an external input signal Software break A debug interrupt is generated when the brk instruction is executed When a debug interrupt occurs the processor performs the following processing 1 Suspends the instructions currently being executed 2 Saves the contents of the PC and PSR and RO in that order to the addresses specified below PC PSR DBRAM 0 0 RO DBRAM 0x4 DBRAM Start address of the work area for debugging in the user RAM 3 Loads address to PC and branches to the debug interrupt handler routine In the interrupt handler routine the instruction should be executed at the end of processing to return to the suspended instructions When returning from the interr
91. transferred data size before or after a data transfer In this way data can be read from or written to continuous addresses in memory only by setting the start address once at the beginning Increment decrement size without ext Byte transfer 1d b 1d ub rb rb 1 1 16 bit transfer 14 rb gt rb 2 rb gt rb 2 24 bit transfer 1d a rb rb 4 rb rb 4 Register indirect addressing with post increment When a data transfer finishes the base address is incremented This addressing mode is specified by enclosing the register name in brackets 1 which is then suffixed by The register name is actually written as 510 5 11 r7 or Register indirect addressing with post decrement When a data transfer finishes the base address is decremented This addressing mode is specified by enclosing the register name in brackets 1 which is then suffixed by The register name is actually written as r0 r1 r7 or Ssp Register indirect addressing with pre decrement The base address is decremented before a data transfer starts This addressing mode is specified by enclosing the register name in brackets 11 which is prefixed by The register name is actually written as r0 r1 r7 5 5 6 EPSON 1C17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET 5 2 5 Register Indirect Addressing with Displacement
92. which is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 The content of the rb register is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer ld ub rd rb Load instruction with post increment option The memory address will be incremented after the data transfer has finished ld ub rd rb Load instruction with post decrement option The memory address will be decremented after the data transfer has finished ld ub rd rb Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 1 byte size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 93 7 DETAILS OF INSTRUCTIONS Id ub esp imm7 Unsigned byte data transfer Standard 7 0 lt B sp imm7 rd 1
93. 0 ignored lt A sp 31 24 Extension 1 sp 23 0 lt sp 23 0 imm13 rd 23 0 lt A sp imm13 23 0 ignored lt A sp imm13 31 24 Extension 2 sp 23 0 lt sp 23 0 imm24 rd 23 0 lt A sp imm24 23 0 ignored lt A sp imm24 31 24 Code 50765 5252 1 1 1 I 10 0 1 1 0 0 0 1 srd ssp 0 0 1 1 1 1 rd Oo 1 110 0 0 ld a sp 0 011 1 1 1 1 11000 ld a sp 0 0 1 1 1 1 rd 1 0 1 100 0 14 8 Mode Src Register indirect 5 Dst Register direct 4rd 5 0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard 14 rd sp memory address sp The 32 bit data the eight high order bits are ignored in the specified memory location is transferred to the rd register The SP contains the memory address to be accessed 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 63 7 DETAILS OF INSTRUCTIONS 2 Extension 1 ext immi3 ld a rd l sp i The ext instruction changes memory address imm13 the addressing mode to register indirect addressing with displacement As a result the content of the SP with the 13 bit immediate imm 3 added comprises the memory address the 32 bit data the eight high order bits are ignored in which 15 transferred to the rd register The content of the SP is not altered 3 Extension 2 ext 1 13 ext
94. 0 lt B rb imm13 rd 15 8 lt B rb imm13 7 rd 24 16 lt 0 Extension 2 rb 23 0 lt rb 23 0 imm24 rd 7 0 lt B rb imm24 rd 15 8 lt B rb imm24 7 rd 24 16 lt 0 EINEN 0000000 8 7 6 5 4 3 2 0 0 1 0 0 01 rd 10 0 0 01 rb ld b 8 4 rb 00 1 0 0 0 rd 01 0 0 Fb ld b grd rb 0 11 1 0 01 rb ld b rd rb 0010 0 0 rd 10 0 0 rb ld b Mode Src Register indirect rb r0 to r7 Dst Register direct rd 5 0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard 14 rd rb memory address rb The byte data in the specified memory location is transferred to the rd register after being sign extended to 16 bits The rb register contains the memory address to be accessed The eight high order bits of the rd register are set to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 DETAILS OF INSTRUCTIONS 2 Extension 1 ext immi3 ld b srd rb memory address rb immi3 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the byte data in which is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 The content of the rb register is not altered 3 Extension 2 ext im
95. 0 rd 7 0 lt rs 15 8 rd 23 16 0 1 1 1 1 O Remarks 1 Number of bits to be shifted Zero to three bits when rs imm7 0 3 four bits when rs imm7 4 7 eight bits when rs imm7 gt 8 2 With one EXT immediate imm20 With two EXT immediate imm24 Conversion Instructions S1C17 Core Instruction Set Mnemonic Flags Opcode Operand MSB LSB Cycle 2 Yrs 01011101110 rd 0111111 Ts rd 23 8 rs 7 rd 7 0 lt rs 7 0 1 M rd Yrs 01011101110 rd 1101111 rS rd 23 16 lt rs 15 rd 15 0 lt rs 15 0 1 1 1 1 1 1 1 cv al 9erd Yrs 0 0 1 0 1 0 rd 1111111 rs 9 23 16 lt 7 0 rd 15 0 e rd 15 0 1 1 1 1 1 1 1 cv la 9erd Yrs 01011101110 0111110 rs 9 23 8 lt 0 rd 7 0 lt rs 23 16 1 1 1 1 1 cv ls 9erd Yrs 01011101110 11701110 rs rd 23 16 0 15 0 5 15 1 1 1 1 1 1 System Control Instructions S1C17 Core Instruction Set Mnemonic Flags Opcode Operand MSB code LSB Function cycle 2 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 operation 141 1 1 1 1 1 1 10 010 1010 10 0 0 10 0 0 01011 0 0 0 mode 8 ketas slp 0 10 0 101010101010101011101010101SLEEP mode 6 ei 0 0 0j0 0 0 0 0 0 0 1 0 0 0 0 0
96. 0 rd 01111 0 rb rd 15 0 W rb 23 16 lt 0 0 23 0 lt 0 23 0 2 2 6 rd rb 0 0 1 0 0 0 rd 1111110 rb rd 15 0 W rb rd 23 16 lt 0 rb 23 0 lt rb 23 0 2 2 J 0 Yrb 0 1000 rd 1 0 1 0 rb rb 23 0 lt rb 23 0 2 9 15 0 lt 0 23 16 0 2 6 O rd 1111010 rd imm7 rd 15 0 lt W sp imm7 9 23 16 lt 0 2 5 O imm7 1110010 rd 15 0 W imm7 rd 23 16 0 1 l s4 0O Verb Yrs 0401010 1 rs 0 0 1 0 W rb rs 15 0 1271 1 1 1 1 1 1511 0 Yrs 0010101 rs 0 1 1 0 W rb lt rs 15 0 rb 23 0 lt rb 23 0 2 2 1 1 1 1 1 o rb Yors 0101010 1 rs 111110 rb W rb ers 15 0 0 23 0 lt 0 23 0 2 2 6 0 verb Yors 0011010 1 rs 1101110 rb 0 23 0 lt 0 23 0 2 W rb rs 15 0 2 s 6 0 Remarks With one EXT base address rb imm13 With two EXT base address rb imm24 With one EXT data sign16 With one EXT data imm20 With two EXT data imm24 With one EXT base address imm20 With two EXT base address imm24 With one EXT base address sp imm20 With two EXT base address sp imm24 With one EXT base address rb imm13 address increment decrement rb sp rb sp imm13 With two EXT base address rb imm24 address increment decrement rb sp rb sp imm24 With no EXT
97. 1 13 14 sp 1 imm24 23 13 imm24 12 0 memory address sp 1024 The addressing mode changes to register indirect addressing with displacement so the content of the SP with 24 bit immediate imm24 added comprises memory address 32 bit data the eight high order bits are ignored in which is transferred to the rd register The content of the SP is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the SP This allows the program to simply perform continuous data transfer 14 rd sp Load instruction with post increment option The SP will be incremented after the data transfer has finished ld a rd Load instruction with post decrement option The SP will be decremented after the data transfer has finished 14 rd Load instruction with pre decrement option The SP will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 4 32 bit size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after branch instruction with the 4 bit In this case extension of the immediate by the ext instruct
98. 104 sa 80 7 105 sbc E M 7 106 sbc c 2 27 7 106 sbc nc Vor YOM 7 106 sbc yoODGNurdmmEPE E ESPEEREET 7 107 sl OW A EIE E AE E E E A 7 108 sl e 1021 a e E E E E 7 109 c AENEA Anaan SSKA 7 110 sr vd EA MEER IEEE TEE EE E 7 111 sr 7 112 Sub vilae PEA E T E A E E E E 7 113 sub c rd rs we 7 113 sub nc 96rs we 7 113 sub rd imm7 i 7 114 sub a YOU VOUS mM 7 115 sub a c 20 8 2 255 fa bdsa sa tundeeiteadaidesicaasaiasslandsddsbaaaisidonagadgaadsseseieaaeavachseidshiasaiesesctaenadebaseseaiaas 7 115 OC dii rd m a EE A Ra a 7 115 sub a Jo y pm 7 116 sub a oS Ps FOr S 7 117 sub a YSP Imm societa Robe ERIGI ID coisa 7 118 swap Vp E E 7 119 0 7 120 OO 7 120 VOUS eee 7 120 OO 7 121 S1C17 FAMILY 51 17 CORE MANUAL EPSON v CONTENTS Appendix List of S1C17 Core 5 5 Ap 1 vi EPSON 51 17 FAMILY S1C17 CORE MANUAL 1 SUMMARY 1 Summary The S1C17 Core is a Seiko
99. 15 0 lt W imm20 rd 23 16 0 Extension 2 rd 15 0 W imm24 rd 23 16 0 EINEN 0000 0005 8 7 6 5 4 3 2 1 1 0 0 1 0 7 LTEM CV ZN Mode Src Immediate data unsigned Dst Register direct ro 0 r7 One cycle 1 Standard ld rd imm7 memory address imm7 The 16 bit data in the memory address specified with the 7 bit immediate imm7 is transferred to the rd register The eight high order bits of the rd register are set to 0 2 Extension 1 ext immi3 imm20 19 7 ld rd imm7 memory address imm20 imm7 imm20 6 0 The ext instruction extends the memory address to a 20 bit quantity As a result the 16 bit data in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register The eight high order bits of the rd register are set to 0 3 Extension 2 ext immi3 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 ld rd imm7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the memory address to a 24 bit quantity As a result the 16 bit data in the memory address specified with the 24 bit immediate imm24 is transferred to rd register The eight high order bits of the rd register are set to 0 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after branch instruction with the 4 bit
100. 19 7 ld cf rd imm7 doutl data imm20 imm7 imm20 6 0 The ext instruction extends the immediate to a 20 bit quantity As a result data set in the rd register and 20 bit immediate imm20 are transferred to the coprocessor and the flag status is loaded to the C V Z and N flags in the PSR 3 Extension 2 ext immi3 imm24 31 19 ext immi3 imm24 18 6 ld cf rd imm7 doutl data imm24 imm7 lt imm24 5 0 The two ext instructions extend the displacement to a 24 bit quantity As a result data set in the rd register and 24 bit immediate imm24 are transferred to the coprocessor and the flag status is loaded to the C V Z and N flags in the PSR 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 7 88 EPSON 51 17 FAMILY S1C17 CORE MANUAL Id cw rd rs Transfer data to the coprocessor doutO lt rd co_doutl lt rs Standard Extension 1 Unusable Extension 2 Unusable 8 7 EIE 0000 000 1 2 001101 C 1 1 151 Mode Src Register direct 2rs Sr0 to r7 Dst Register direct rd 5 0 to r7 One cycle 1 Standard 7 DETAILS OF INSTRUCTIONS Transfers data set in the rd and rs registers to the coprocessor The rd register and the C V Z and
101. 24 23 0 ignored lt A rb imm24 31 24 15 14 13 12 11 109 8 7 6 5 4 3 2 0 0 1 0 0 0 0 0 1 1 rb ld a rb 001 000 rd 0 1 1 1 rb ld 2rd rb 00100 0 rd 1 1 1 1 rb ld a rb 00100 0 rd 10 L 3 rb ld a 2111 Src Register indirect rb r0 to r7 Dst Register direct 2rd r0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard ld a rd rb memory address rb The 32 bit data the eight high order bits are ignored in the specified memory location is transferred to the rd register The rb register contains the memory address to be accessed 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 61 7 DETAILS OF INSTRUCTIONS 2 Extension 1 ext immi3 14 rd brb memory address rb immi3 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register The content of the rb register is not altered 3 Extension 2 ext 1 13 1 24 23 13 ext immi3 imm24 12 0 14 rd brb memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the c
102. 4 System control 1 m ES halt 6 25 slp 6 ei 1 1 E di 1 E 0 m m Coprocessor control 1d cw rd rs 1 rd imm7 ld ca 1 e e e rd imm7 ld cf rd rs 1 o o e rd imm7 51 17 FAMILY S1C17 CORE MANUAL EPSON 6 5 6 FUNCTIONS 6 3 Interrupts When an interrupt occurs during program execution the processor enters an interrupt handling state The interrupt handling state is a process by which the processor branches to the corresponding user s service routine for the interrupt that occurred The processor returns after branching and starts executing the program from where it left off 6 3 1 Priority of Interrupts The interrupts supported by the 51 17 Core their vector addresses and the priority of these interrupts are listed in the table below Table 6 3 1 1 Vector Address and Priority of Interrupts Interrupt Vector address Hex Priority Reset TTBR 0x00 High Address misaligned interrupt TTBR 0x04 Debug interrupt OxfffcOO NMI TTBR 0x08 Software interrupt TTBR 0x00 to TTBR Ox7c Maskable external interrupt TTBR 0x00 to TTBR Ox7c Low When two or more interrupts occur simultaneously they are processed in order of priority beginning with the one that has the highest priority When an interrupt occurs the processor disables interrupts that would occur thereafter and performs interrupt
103. 4 23 21 ext 1 13 sign24 20 8 jrne sign7 jrne sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates imm13 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrne d sign7 For the j xne d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j rne instruction and the next instruction so no interrupts occur cmp r0 rl jrne 0x2 Skips the next instruction if r0 rl When the jrne d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 43 7 DETAILS OF INSTRUCTIONS jruge jruge d Function CLK sign7 sign7 Conditional PC relative jump for judgment of unsigned operation results Standard pe pe 2 sign7 x 2 if C is true Extension 1 pc lt pc 2 sign21 if C is true Extension 2 pc lt pc 2 sign24 if C is true 15 14 13 12 11 10 9 8 7 6 5 4 3 2 000010110 sign7 j
104. 5 8 lt 0 rd 23 16 lt 0 Extension 1 rd 7 0 lt B sp imm20 rd 15 8 lt 0 rd 23 16 lt 0 Extension 2 rd 7 0 lt B sp imm24 rd 15 8 lt 0 rd 23 16 lt 0 14 13 12 11 10 9 8 7 6 5 4 3 2 code 1 1 1 0 0 1 rd imm7 IE V 7 Mode 5 Register indirect with displacement Dst Register direct r0 to r7 Two cycles 1 Standard ld ub 5 imm7 memory address sp imm7 The byte data in the specified memory location is transferred to the rd register after being zero extended to 16 bits The content of the current SP with the 7 bit immediate imm7 added as displacement comprises the memory address to be accessed The eight high order bits of the rd register are set to 0 2 Extension 1 3 4 ext immi3 imm20 19 7 ld ub rd 5 imm7 memory address sp imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the SP with the 20 bit immediate imm20 added comprises the memory address the byte data in which is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 Extension 2 ext immi3 imm24 31 19 ext immi3 imm24 18 6 ld ub rd 5 imm7 memory address sp imm24 imm7 lt imm24 5 0 The two ext instructions extend the displacement to a 24
105. 6 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jrule sign7 jrule sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext 110013 imm13 2 0 sign24 23 21 ext imm13 sign24 20 8 jrule 81917 jrule sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates imm13 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrule d 8197 For the j rule instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j rule d instruction and the next instruction so no interrupts occur 510 5 1 r0 and rl contain unsigned data jrule 0 2 Skips the next instruction if r0 lt rl When the jrule d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminate
106. 7 EINEN 11 10 1 0 1 1 0 1 rd olo eo e ee Mode Src Register direct 2rs r0 to r7 Dst Register direct rd 5 0 to r7 One cycle 1 Standard 7 DETAILS OF INSTRUCTIONS Transfers data set in the rd and rs registers to the coprocessor and gets the flag status of the coprocessor to the C V Z and N flags in the PSR 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 DETAILS OF INSTRUCTIONS Id cf rd Function Transfer data to the coprocessor and the flag status Standard doutO lt rd co doutl lt imm7 psr C V Z lt cvzn Extension 1 0 lt rd doutl lt 20 psr C V Z lt co cvzn Extension 2 0 lt rd doutl lt 24 psr C V Z N lt co cvzn 00000005 8765 4 3 2 1 1 O 1 0 1 imm7 Mode Src Immediate data unsigned Dst Register direct r0 0 r7 One cycle 1 Standard ld cf rd imm7 doutl data imm7 Transfers data set in the rd register and 7 bit immediate imm7 to the coprocessor and gets flag status of the coprocessor to the C V 7 and N flags in the PSR 2 Extension 1 ext immi3 imm20
107. 7 For the jrgt d instruction the next instruction becomes delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j d instruction and the next instruction so no interrupts occur cmp 0 1 r0 and r1 contain signed data jrgt 0x2 Skips the next instruction if r0 gt rl When the jrgt d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 7 40 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS sign7 jrle d sign7 CLK Conditional relative jump for judgment of signed operation results Standard amp pc 2 sign7 x 2 if Z is true Extension 1 pc pc 2 sign21 if Z N V is true Extension 2 pc pc 2 sign24 if Z N V is true 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 1 0 0 1 O sign 0 0 0 0 1 0 0 I I sign jrle d IL IE C V ZN Signed PC relative jrle Two cycles when not branched Three cycles when branched jrle d Two cycles 1 Standard jrle sign7 jrle sign8 sign7 sign8 7 1 519 8 0 0 If the condition below h
108. 7 jrge d sign7 CLK Conditional PC relative jump for judgment of signed operation results Standard pe lt pe 2 sign7 x 2 if is true Extension 1 pc lt pc 2 510721 if is true Extension 2 pc pc 2 sign24 if is true 15 14 13 12 0 9 8 7 6 5 4 3 2 0 0 0 0 0 1 1 1 0 sign jrge 19 0 0 0 0 11 1 1 sign jrge d IL IE C V Z N Signed PC relative jrge Two cycles when not branched Three cycles when branched jrge d Two cycles 1 Standard jrge sign7 jrge sign8 sign7 sign8 7 1 sign8 0 0 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met N flag V flag e g gt B has resulted by The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext 1 13 sign21 20 8 jrge sign7 jrge sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext 1 13 1 13 2 0 sign24 23 21 ext 1 13 Sign24 20 8 jrge sign7
109. 7 36 EPSON 51 17 FAMILY S1C17 CORE MANUAL jpr 7 DETAILS OF INSTRUCTIONS sign10 jpr d sign10 Caution Unconditional PC relative jump Standard pe amp pc 2 signl0 x 2 Extension 1 pc pc 2 sign24 Extension 2 Unusable 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 SignIO 6 E IL IE C V ZN Signed PC relative jpr Three cycles jpr d Two cycles 1 Standard jpr signio jp signll sign7 519 11 8 1 5 11 0 0 Doubles the signed 10 bit immediate sign 0 and adds it to the PC PC 2 The program flow branches to the address The sign 0 specifies a word address in 16 bit units The sign10 x2 allows branches within the range of PC 1 022 to PC 1 024 2 Extension 1 ext jpr imm13 sign24 23 11 sign24 19 10 signl0 sign24 10 1 sign24 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into 24 bits using its 13 bit immediate imm13 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388608 3 Delayed branch d bit bit 10 1 jpr d 1 10 For the 3pr d instruction the next instruction becomes delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the jpr d instruction and the next instruction so no interrupts occur 0x20 0x00 Jumps to the
110. 8 3964 Fax 1 408 922 0238 SALES OFFICE Northeast 301 Edgewater Place Suite 210 Wakefield MA 01880 U S A Phone 1 800 922 7667 Fax 1 781 246 5443 EUROPE EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS Riesstrasse 15 80992 Munich GERMANY Phone 49 89 14005 0 Fax 49 89 14005 110 D SSELDORF BRANCH OFFICE Altstadtstrasse 176 51379 Leverkusen GERMANY Phone 49 2171 5045 0 Fax 49 2171 5045 10 FRENCH BRANCH OFFICE 1 Avenue de Atlantique LP 915 Les Conquerants Z A de Courtaboeuf 2 F 91976 Les Ulis Cedex FRANCE Phone 33 1 64862350 Fax 33 1 64862355 UK amp IRELAND BRANCH OFFICE 8 The Square Stockley Park Uxbridge Middx UB11 1FW UNITED KINGDOM Phone 44 1295 750 216 44 1342 824451 Fax 44 89 14005 446 447 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 Fax 44 1506 605041 ChaoYang District Beijing CHINA Phone 86 10 6410 6655 Fax 86 10 6410 7320 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5522 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Telex 65542 EPSCO HX Fax 86 21 5423 5512 Fax 852 2827 4346 EPSON Electronic Technology Development Shenzhen LTD 12 F Dawning Mansion Keji South 12th Road Hi Tech Park Shenzhen Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON TAIW
111. A imm24 23 0 ignored lt A imm24 31 24 0 EINEN 00000005 8 7 6 5 4 3 2 1 1 1 0 0 1 1 rd imm7 IL E C V ZN Src Immediate data unsigned Dst Register direct r0 to r7 One cycle 1 Standard ld a rd imm7 memory address Sp imm7 The 32 bit data the eight high order bits are ignored in the memory address specified with the 7 bit immediate imm 7 is transferred to the rd register 2 Extension 1 ext 1 13 imm20 19 7 ld a rd imm7 memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the 32 bit data the eight high order bits are ignored in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register 3 Extension 2 ext immi3 imm13 3 0 ext immi3 imm24 19 7 ld a rd imm7 memory address imm24 23 20 imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the 32 bit data the eight high order bits are ignored in the memory address specified with the 24 bit immediate 24 is transferred to rd register 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 0x1
112. A sp 31 24 0 9 rs 01011111111 1101100 0 0 sp 23 2 lt rs 23 2 sp imm7 1 011111111101010 imm7 sp 6 2 imm7 6 2 5 23 7 0 O Remarks 1 With one EXT base address ro imm13 With two EXT base address rb imm24 2 With one EXT data sign16 3 With one EXT data imm20 With two EXT data imm24 4 With one EXT base address imm20 With two EXT base address imm24 5 With one EXT base address sp imm20 With two EXT base address sp imm24 6 With one EXT base address ro imm13 address increment decrement rb sp lt rb sptimm13 With two EXT base address rb imm24 address increment decrement rb sp lt rb sptimm24 7 The ld a erd pc instruction should be used as a delayed slot instruction for the jr d jpr d or jpa d delayed branch instruction 8 With no EXT 1 cycle With EXT 2 cycles SNOILONYLSNI 41916 40 1511 XIGNAddV 21915 MINV 21915 Integer Arithmetic Operation Instructions 1 S1C17 Core Instruction Set 2 3 With one EXT data imm16 sign16 4 With one EXT data imm20 With two EXT data imm24 1 With one EXT rs imm13 With two EXT lt rs imm16 With one EXT lt rs imm13 With two EXT
113. AN TECHNOLOGY amp TRADING LTD 14F No 7 Song Ren Road Taipei 110 Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone 65 6586 5500 Fax 65 6271 3182 SEIKO EPSON CORPORATION KOREA OFFICE KLI 63 Bldg 60 Yoido dong Youngdeungpo Ku Seoul 150 763 KOREA Phone 82 2 784 6027 Fax 82 2 767 3677 GUMI OFFICE 2F Grand B D 457 4 Songjeong dong Gumi City KOREA Phone 82 54 454 6027 Fax 82 54 454 6093 SEIKO EPSON CORPORATION SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept IC International Sales Group 421 8 Hino Hino shi Tokyo 191 8501 JAPAN Phone 81 42 587 5814 Fax 81 42 587 5117 S1C17 Family S1C17 Core Manual SEIKO EPSON CORPORATION W EPSON Electronic Devices Website Document code 410905900 Issue April 2007 Printed in Japan DA
114. ANUAL 51 erd Logical shift to the left 7 DETAILS OF INSTRUCTIONS Standard Shift the content of rd to left as many bits as specified by imm7 0 3 4 or 8 bits LSB 0 Extension 1 imm7 is extended to imm20 Extension 2 imm7 is extended to imm24 ETE 8 7 6 5 5252 1 0 i 9 1 1 1 0 rd Mode Src Immediate unsigned Dst Register direct rd ro to r7 One cycle 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the 7 bit immediate imm7 as follows imm7 0 3 0 3 bits imm7 4 7 4 bits 8 more 8 bits Data 0 is placed in least significant bit of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 23 1615 rd register after execution 0 000000 0 gt 2 Extension Using the ext instruction extends the 7 bit immediate imm7 to 20 bit immediate 20 or 24 bit immediate imm24 However there is no difference in operation from the standard instruction without extension 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit included In this case extension of the immediate by the ext instructi
115. Bit 8 of the imm13 in the ext instruction is the sign with the immediate extended to become signed 16 bit data The most significant bit in sign7 is handled as the MSB data of 7 bit data and not as the sign 5 3 2 Extension of Register Direct Addressing Extending register to register operation instructions Register to register operation instructions are extended by one or two ext instructions Unlike data transfer instructions these instructions add or subtract the content of the rs register and the immediate specified by an ext instruction according to the arithmetic operation to be performed They then store the result in the rd reg ister The content of the rd register does not affect the arithmetic operation performed An example of how to extend for an add operation is shown below Extending to rs imm13 for 16 bit and 24 bit operation instructions To extend to rs imm13 enter one ext instruction directly before the target instruction Example ext imm13 add a rd rs If not extended rd rd rs When extended by one ext instruction rd rs 4 imm13 23 0 rs Data 23 13 12 0 Immediate 0000000000 0 imm13 23 Y 0 rd Data 4 imm13 Extending to rs imm16 for 16 bit operation instructions To extend to rs imm16 enter two ext instructions directly before the target instruction Example ext 1013 1 ext immi3 2 add rd rs If not extended rd rd rs When extended by two ext in
116. Dst Register indirect rb r0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard 1 rb rs memory address rb The 16 low order bits of the rs register are transferred to the specified memory location The rb register contains the memory address to be accessed 2 Extension 1 ext immi3 14 rb rs memory address rb immi3 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the 16 low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 13 bit immediate imm43 added The content of the rb register is not altered EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS 3 Extension 2 ext immi3 imm13 10 0 imm24 23 13 ext immi3 imm24 12 0 ld rb rs memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the 16 low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 24 bit immediate imm24 added The content of the rb register is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer ld 2 Load instruction with post incr
117. EM 000 CV ZN Mode Src Register direct 15 r0 to r7 Dst Register direct 4rd r0 to r7 One cycle 1 Standard The 16 low order bits of the rs register are transferred to the rd register The eight high order bits of the rd register are set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit r0 r1 15 0 7 48 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id rd rb Id rd rb Id rd rb Id rd rb Function 16 bit data transfer Id rd rb Standard rd 15 0 lt W rb rd 23 16 0 Extension 1 4 15 0 lt W rb imm13 rd 23 16 lt 0 Extension 2 rd 15 0 lt W rb imm24 rd 23 16 0 Id erd rb with post increment option Standard rd 15 0 W rb rd 23 16 lt 0 rb 23 0 lt rb 23 0 2 Extension 1 rd 15 0 lt W rb imm13 rd 23 16 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 rd 15 0 lt W rb imm24 rd 23 16 lt 0 rb 23 0 lt rb 23 0 imm24 Id rd rb with post decrement option Standard rd 15 0 W rb rd 23 16 lt 0 rb 23 0 lt rb 23 0 2 Extension 1 4 15 0 W rb 13 rd 23 16 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 rd 15 0 W rb imm24 rd 23 16 lt 0 rb 23 0 lt rb 23 0 imm24 Id rd rb
118. EP mode reti Interrupt instruction Program execution state halt instruction Debug interrupt Debug interrupt handling HALT mode retd instruction Interrupt Figure 6 1 1 Processor Status Transition Diagram 6 1 1 Reset State The processor is initialized when the reset signal is asserted and then starts processing from the reset vector when the reset signal is deasserted 6 1 2 Program Execution State This is a state in which the processor executes the user program sequentially The processor state transits to another when an interrupt occurs or the slp or halt instruction is executed 6 1 3 Interrupt Handling When a software or other interrupt occurs the processor enters an interrupt handling state The following are the possible causes of the need for interrupt handling 1 External interrupt 2 Software interrupt 3 Address misaligned interrupt 4 NMI 6 1 4 Debug Interrupt The S1C17 Core incorporates a debugging assistance facility to increase the efficiency of software development To use this facility a dedicated mode known as debug mode is provided The processor can be switched from user mode to this mode by the brk instruction or a debug interrupt The processor does not normally enter this mode 6 1 5 HALT and SLEEP Modes The processor is placed in HALT or SLEEP mode to reduce power consumption by executing the halt or slp instruction in t
119. EPSON EXCEED YOUR VISION CMOS 16 BIT SINGLE CHIP MICROCOMPUTER S1C17 Family 51 17 Core Manual SEIKO EPSON CORPORATION NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson Seiko Epson reserves the right to make changes to this material without notice Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and further there is no representation that this material is applicable to products requir ing high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this mate rial will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency SEIKO EPSON CORPORATION 2007 All rights reserved Configuration of product number Devices S1 C 17XXX F 00 1 00 Packing specifications 00 Besides tape amp reel TCP BL 2 directions
120. ETE 507655 2 1 0 0 1 1 1 1 11 9 0 TS cme 1 1 1 1 rd 00 0 1 rs 0 0 1 1 1 1 rd 0 1 0 1 ws cmc nc olo ele enc gt Mode Src Register direct 2rs Sr0 to r7 Dst Register direct 4rd ro to r7 CLK One cycle 1 Standard rd rs rd rs Subtracts the contents of the rs register and C carry flag from the contents of the rd register and sets or resets the flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the contents of the rd register 2 Extension 1 ext 1013 rd rs rs immi3 C Subtracts the contents of the 13 bit immediate imm13 and C carry flag from the contents of the rs register and sets or resets the flags C V Z and N according to the results The imm13 15 zero extended into 16 bits prior to the operation The operation is performed in 16 bit size It does not change the contents of the rd and rs registers 3 Extension 2 ext immi3 imm13 2 0 imm16 15 13 ext immi3 imml6 12 0 cmc 05 rs immi6 C Subtracts the contents of the 16 bit immediate imm16 and C carry flag from the contents of the rs register and sets or resets the flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the contents of the rd and rs registers 4 Conditional execution The
121. ILY S1C17 CORE MANUAL Id b erb rs Id b rb rs Id b rb rs Id b rb rs Signed byte data transfer Id b rb rs Standard B rb rs 7 0 Extension 1 B rb imm13 lt rs 7 0 Extension 2 B rb imm24 rs 7 0 Id b rb rs with post increment option B rb lt rs 7 0 rb 23 0 lt rb 23 0 1 Standard 7 DETAILS OF INSTRUCTIONS Extension 1 B rb imm13 lt rs 7 0 rb 23 0 lt rb 23 0 imm13 Extension 2 B rb imm24 lt rs 7 0 rb 23 0 lt rb 23 0 imm24 Id b rb rs with post decrement option B rb rs 7 0 rb 23 0 lt rb 23 0 1 Standard Extension 1 B rb imm13 lt rs 7 0 rb 23 0 lt rb 23 0 imm13 Extension 2 B rb imm24 lt rs 7 0 rb 23 0 lt rb 23 0 imm24 Id b erb rs with pre decrement option Standard rb 23 0 lt rb 23 0 1 B rb lt rs 7 0 Extension 1 rb 23 0 lt rb 23 0 imm13 B rb imm13 lt rs 7 0 Extension 2 rb 23 0 lt rb 23 0 imm24 B rb imm24 lt rs 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 rs 0 0 9 0 rb ld b rb rs 0 0 1 0 0 1 rs 0 1 0 0 Fb ld b rb rs 001 0 0 1 vs 1 1 0 0 rb ld b 8rb rs 0010 01 rs 1 0 0 0 To ld b rb rs Ec Src Register direct 2rs r0 to r7 Dst Register indirect rb r0 to r7 One cycle two cycles when the ext instruction or an increment decrement
122. Id a Function 7 DETAILS OF INSTRUCTIONS rd erb rb rd erb rb 32 bit data transfer Id a rd rb Standard rd 23 0 lt A rb 23 0 ignored lt A rb 31 24 Extension 1 rd 23 0 lt A rb imm13 23 0 ignored lt A rb imm13 31 24 Extension 2 rd 23 0 lt A rb imm24 23 0 ignored lt A rb imm24 31 24 Id a rd rb with post increment option Standard Extension 1 Extension 2 23 0 lt A rb 23 0 ignored lt A rb 31 24 rb 23 0 lt rb 23 0 4 23 0 lt A rb imm13 23 0 ignored lt A rb imm13 31 24 rb 23 0 lt rb 23 0 imm13 23 0 lt A rb imm24 23 0 ignored lt A rb imm24 31 24 rb 23 0 lt rb 23 0 imm24 Id a 96 erb with post decrement option Standard Extension 1 Extension 2 23 0 lt A rb 23 0 ignored lt A rb 31 24 rb 23 0 lt rb 23 0 4 23 0 lt A rb imm13 23 0 ignored lt A rb imm13 31 24 rb 23 0 rb 23 0 imm13 23 0 lt A rb imm24 23 0 ignored lt A rb imm24 31 24 rb 23 0 rb 23 0 imm24 Id a rb with pre decrement option Standard Extension 1 Extension 2 rb 23 0 lt rb 23 0 4 rd 23 0 lt A rb 23 0 ignored lt A rb 31 24 rb 23 0 lt rb 23 0 imm13 rd 23 0 lt A rb imm13 23 0 ignored lt A rb imm13 31 24 rb 23 0 lt rb 23 0 imm24 rd 23 0 lt A rb imm
123. In this case extension of the immediate by the ext instruction cannot be performed o ld 0x2 ro lt 0x82 The imm7 must specify a 16 bit boundary address least significant bit 0 Specifying an odd address causes an address misaligned interrupt Note however that the data transfer is performed by setting the least significant bit of the address to 0 7 52 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id sign7 16 bit data transfer Standard rd 6 0 lt sign7 6 0 rd 15 7 lt sign7 6 23 16 0 Extension 1 rd 15 0 lt sign16 15 0 rd 23 16 0 Extension 2 Unusable Function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 001 1 0 rd sign IL IE C V ZN l l l l l Mode Src Immediate data signed Dst Register direct 2rd r0 to r7 One cycle 1 Standard ld rd sign7 rd lt sign7 sign extended The 7 bit immediate sign7 is loaded to the rd register after being sign extended to a 16 bit quantity 2 Extension 1 ext imm13 signl6 15 7 ld rd sign7 rd lt 819116 sign7 519 16 6 0 The immediate data is extended into a 16 bit quantity by the ext instruction and it is loaded to the rd register 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate
124. Memory Register Bits 15 8 in the destination register are sign extended and bits 23 16 are set to 0 00 3 2 3 8 Bit Transfer Register Memory Example 1d b rb rs 23 16 15 8 7 0 rs X X Byte 7 0 rb Byte Figure 3 2 3 1 8 Bit Transfer Register Memory 3 2 4 16 Bit Transfer Memory Register Example 1d rd rb 7 0 Ob 1 Byte 1 rb 0 Byte 0 0 Y 23 1615 v 8 7 0 rd 0 00000090 Byte 1 Byte 0 Figure 3 2 4 1 16 Bit Transfer Memory Register Bits 23 16 in the destination register are set to 0 00 51 17 FAMILY 51 17 CORE MANUAL EPSON 3 3 3 DATA FORMATS 3 2 5 16 Bit Transfer Register Example 14 rb rs 23 16 15 87 9615 X Byte 1 Byte 0 7 0 ea Byte 1 6rb Ob Byte 0 Figure 3 2 5 1 16 Bit Transfer Register Memory 3 2 6 32 Bit Transfer Memory Register Example 1d a rd rb 7 0 Obese 1 Byte 3 Ignored after read Ober 10 Byte 2 Ob 01 Byte 1 196881 Ob 00 Byte 0 23 16 15 v 8 7 2 Byte 1 0 Figure 3 2 6 1 32 Bit Transfer Memory Register 3 2 7 32 Bit Transfer Register Memory Example 19 rb rs 23 16 15 8 7 9615 2 Byte 1 Byte 0 rS 7 0 1 0 00 0 Ob 10 Byte 2 4 Ob 01 Byt
125. N 3 1 3 DATA FORMATS 3 1 3 16 Bit Transfer Register Register Example 14 rd rs 23 16 15 0 ers X 16 bit data 0 v 23 16 15 0 rd 0 0000000 16 bit data Figure 3 1 3 1 16 Bit Transfer Register Register Bits 23 16 in the destination register are set to 0 00 3 1 4 24 Bit Transfer Register Register Example 14 rd 23 0 9615 24 bit data 23 0 24 bit data Figure 3 1 4 1 24 Bit Transfer Register Register 3 2 Data Formats Handled in Operations Between Memory and a Register The S1C17 Core can handle 8 16 and 32 bit data in memory operations In this manual data sizes are expressed as follows 8 bit data Byte or b 16 bit data Word W or w 32 bit data Address data A a Data sizes can be selected only in data transfer load instruction between memory and a general purpose register In an 8 bit data transfer with a general purpose register as the destination the data is sign or zero extended to 16 bits before being loaded into the register Whether the data will be sign or zero extended is determined by the load instruction used In a 16 bit or 8 bit data transfer using a general purpose register as the source the data to be transferred is stored in the low order 16 bits or the low order 8 bits of the source register Memory is accessed in little endian format one byte 16 bits or 32 bits at a time If memor
126. NS Flag Classification Mnemonic Cycle IL IE Z N Remark Shift and swap Sr rd rs 1 rd imm7 1 rd rs 1 rd imm7 1 o sl 2rd rs 1 e rd imm7 1 e Swap rd rs 1 m Immediate extension ext immi3 1 Conversion cv ab grd rs 1 m m cv as 2rd rs 1 2 E cv al 2rd rs 1 cv la 1 cv ls 2rd rs 1 E Branch 1 10 3 2 2 cycles when not jpr d rb 2 d jumped imm7 3 3 cycles when jumped ipa d rb 2 d jrgt sign7 2 3 jrgt d 2 d jrge sign7 2 3 z m m jrge d 2 d jelt sign7 2 32 jrit d 2 d jrle sign7 2 32 m jrle d 2 d jrugt sign7 2 3 jrugt 2 d jruge sign7 2 3 jruge 2 d jrult sign7 2 3 jrult 2 d jrule sign7 2 3 m jrule 2 d jreq sign7 2 3 jreq d 2 d jrne sign7 2 32 m jrne d 2 d call signiO0 4 call d rb 3 d calla imm7 4 calla d rb 3 d ret 3 25 ret d 2 d int 5 3 0 intl 5 imm3 3 0 reti 3 reti d 2 d brk 4 0 E retd
127. NUAL 7 DETAILS OF INSTRUCTIONS sub a sp ers Function Code Flag CLK Description 24 bit subtraction Standard sp 23 0 sp 23 0 rs 23 0 Extension 1 sp 23 0 lt rs 23 0 imm13 zero extended Extension 2 sp 23 0 rs 23 0 imm24 15 14 13 12 11 0 9 8 7 6 5 4 3 2 oo01100000001 1 rs IL IE V 7 N Src Register direct 2rs r0 to r7 Dst Register direct sp One cycle 1 Standard sub a Sp lt sp rs The content of the rs register is subtracted from the stack pointer SP 2 Extension 1 ext 1 13 sub a sp rs sp amp rs immi3 The 13 bit immediate 3 is subtracted from the content of the rs register after being zero extended and the result is loaded into the stack pointer SP The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 10 0 imm24 23 13 ext immi3 imm24 12 0 sub a sp rs Sp lt rs imm24 The 24 bit immediate imm24 is subtracted from the content of the rs register and the result is loaded into the stack pointer SP The content of the rs register is not altered 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 sub a sp rO sp sp ro 2 ext 0 1 ext Oxlfff sub a
128. O IBAR10 0 23 0 IBAR1 23 0 Instruction Break Address 1 This register is used to set instruction break address 1 Default 0x000000 OxFFFFCO Serial Status Register for Debugging SSR Register name Address Bit Name Function Setting Init R W Remarks Serial status FFFFCO 07 3 Reserved 0 when being read register for B 02 RXDEN Receive disable 1 Disable o Enable 1 RW debugging 01 Transmit data buffer empty flag 1 Empty o Not empty 1 R DO RDBF Receive data buffer full flag 1 Full 0 Not full 0 R D 7 3 Reserved D2 RXDEN Receive Disable Bit Enables disables receive operation in the serial interface for the on chip debug monitor 1 R W Disable default 0 R W Enable D1 TDBE Transmit Data Buffer Empty Flag Indicates transmit buffer status in the serial interface for the on chip debug monitor 1 R Empty default 0 R Not empty DO RDBF Receive Data Buffer Full Flag Indicates receive buffer status in the serial interface for the on chip debug monitor 1 0 Full Not full default OxFFFFC2 Serial Transmit Receive Data Register for Debugging SDR Register name Address Name Function Setting Init R W Remarks Serial transmit FFFFC2 07 TXRXD7 Transmit receive data 0 0 0 0 R W receive data B register for debugging DO TXRXDO D 7 0 TXRXD 7 0 Transmit Receive Data This is the
129. ZN Mode Src Register direct rs r0 to r7 Dst Register indirect with displacement Two cycles 1 Standard ld 5 imm7 rs memory address sp imm7 The 16 low order bits of the rs register are transferred to the specified memory location The content of the current SP with the 7 bit immediate imm7 added as displacement comprises the memory address to be accessed 2 Extension 1 ext immi3 14 55 imm7 rs imm20 19 7 memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the 16 low order bits of the rs register are transferred to the address indicated by the content of the SP with the 20 bit immediate imm20 added 3 Extension 2 ext immi3 ext immi3 14 55 imm7 rs imm24 23 20 imm24 19 7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the 16 low order bits of the rs register are transferred to the address indicated by the content of the SP with the 24 bit immediate imm24 added 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed o ld Ssp 0 21 5 0 The SP
130. a rd rs 24 bit addition between general purpose registers add a c Supports conditional execution c executed if C 1 nc executed if C 0 add a nc add a Ssp rs 24 bit addition of SP and general purpose register rd imm7 24 bit addition of general purpose register and immediate 5sp imm7 24 bit addition of SP and immediate adc rd rs 16 bit addition with carry between general purpose registers adc c Supports conditional execution c executed if C 1 nc executed if C 0 adc nc adc rd imm7 16 bit addition of general purpose register and immediate with carry sub rd rs 16 bit subtraction between general purpose registers sub c Supports conditional execution c executed if C 1 nc executed if C 0 sub nc sub rd imm7 16 bit subtraction of general purpose register and immediate sub a rd rs 24 bit subtraction between general purpose registers sub a c Supports conditional execution c executed if C 1 nc executed if C 0 sub a nc sub a Ssp rs 24 bit subtraction of SP and general purpose register rd imm7 24 bit subtraction of general purpose register and immediate 5sp imm7 24 bit subtraction of SP and immediate Sbc rd rs 16 bit subtraction with carry between general purpose registers Supports conditional execution c executed if C 1 nc executed if C 0 sbc nc Sbc rd imm7 16 bit subtraction of general purpose register and immediate with carry cmp rd rs 16 bit comparison between general purpos
131. a logical operation is performed the V flag bit 2 in the PSR is cleared Conditional execution The logical operation instructions for between registers op rs allow use of the switches to specify whether the instruction will be executed or not depending on the C flag status Unconditional execution instructions op 2 op and or xor not The instruction without a switch will be always executed regardless how the C flag is set Example and Instructions executable under C condition rd rs op and or xor not The instruction with the c switch will be executed only when the C flag has been set to 1 Example or c rd rs Instructions executable under NC condition op nc grd brs op and or xor not The instruction with the nc switch will be executed only when the C flag has been cleared to 0 Example xor nc rd rs 5 14 EPSON 51 17 FAMILY S1C17 CORE MANUAL 5 INSTRUCTION SET 5 6 Arithmetic Operation Instructions The instruction set of the S1C17 Core supports add subtract and compare instructions for arithmetic operations add 16 bit addition add a 24 bit addition adc 16 bit addition with carry sub 16 bit subtraction sub a 24 bit subtraction sbc 16 bit subtraction with borrow cmp 16 bit comparison cmp a 24 bit comparison cmc 16 bit comparison with borrow The above arithmetic operations are performed between one general purpose register and another
132. according to the results It does not change the contents of the rd register 4 Delayed slot instruction 1 2 This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed cmp a r0 0x7f Changes the flags according to the results of rO 0 7 ext Oxf ext Oxlfff cmp a r1 0x7f Changes the flags according to the results of s rl Oxfftfff 7 22 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS cv ab rd rs Data conversion from byte to 24 bits Standard rd 23 8 lt rs 7 rd 7 0 lt rs 7 0 Extension 1 Unusable Extension 2 Unusable ETE 0050 00 00 0009 2765 1 1 0 0 1 0 1 0 01 1 1 rs ENE ECV o Mode Src Register direct 2rs r0to r7 Dst Register direct rd 5 0 to r7 One cycle 1 Standard The eight low order bits of the rs register are transferred to the rd register after being sign extended to 24 bits 23 8 7 0 rs S Byte 4 3 23 8 7 0 4 5555555555555555 8 8 bits 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit When R1 register contains 0x80 cv ab r0 r1
133. acement to a 24 bit quantity As a result data set in the rd register and 24 bit immediate imm24 are transferred to coprocessor The rd register and the C V Z and N flags in the PSR are not altered 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 7 90 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id ub rd rs Unsigned byte data transfer Standard 7 0 lt rs 7 0 rd 15 8 lt 0 23 16 0 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 0 0 1 0 1 0 rd 22 IL IE C V 7 Src Register direct 2rs r0 to r7 Dst Register direct rd r0 to r7 One cycle 1 Standard The eight low order bits of the rs register are transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit ld ub r0 rl1 r0 r1 7 0 zero extended 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 91 7 DETAILS OF INSTRUCTIONS Id ub rd rb Id ub rd rb Id ub rd erb Id ub rd rb ET Unsigned byte
134. address specified by pc 2 0x10000 ext jpr When the jpr d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 1017 FAMILY 51 17 CORE MANUAL EPSON 7 DETAILS OF INSTRUCTIONS 5 7 jreq d sign7 CLK Conditional PC relative jump Standard pe pe 2 sign7 x 2 if Z is true Extension 1 pe lt pc 2 sign21 if Z is true Extension 2 pc pc 2 sign24 if Z is true 15 14 13 12 11 10 9 8 7 6 5 4 3 2 000011100 7 jreq 0 0 0 0 1 1 1 0 1 22 sga 000 jreq d IL IE C V 7 Signed PC relative jreq Two cycles when not branched Three cycles when branched jreq d Two cycles 1 Standard jreq sign7 jreq sign8 sign7 sign8 7 1 sign8 0 20 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met Z flag 1 e g B has resulted by cmp The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext immi3 sign21 20 8
135. address to be accessed 2 Extension 1 ext 1 13 imm20 19 7 ld b 5 imm7 rs memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the eight low order bits of the rs register are transferred to the address indicated by the content of the SP with the 20 bit immediate imm20 added 3 Extension 2 ext immi3 imm24 23 20 ext 1 13 imm24 19 7 ld b sp imm7 rs memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the eight low order bits of the rs register are transferred to the address indicated by the content of the SP with the 24 bit immediate imm24 added 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed LEVINE 0 ld b sp 0x1 r0 B sp 0x81 lt 8 low order bits of 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 83 7 DETAILS OF INSTRUCTIONS 1 5 imm7 rs Function Signed byte data transfer Standard B imm7 lt rs 7 0 Extension 1 B imm20 lt rs 7 0 Extension 2 B imm24 lt rs 7 0 H 8 265 1 1 1 0 rs IL IE C V 7 Mode Src Register dir
136. ain signed data jrle 0x2 Skips the next instruction if r0 lt r1 When the jrle d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 41 7 DETAILS OF INSTRUCTIONS jrit sign7 jrit d sign7 CLK Conditional PC relative jump for judgment of signed operation results Standard pe lt 2 sign7 x 2 if is true Extension 1 pc lt pe 2 sign21 if N V is true Extension 2 pc pc 2 sign24 if N V is true 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 we irit 00001000 sign7 jrlit d IL IE C V 7 Signed PC relative jrlt Two cycles when not branched Three cycles when branched jrlt d Two cycles 1 Standard jrlt sign7 jrlt sign8 sign7 sign8 7 1 sign8 0 0 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met N flag V flag e g lt B has resulted by cmp A B The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches withi
137. as been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met e Z flag or flag V flag e g lt B has resulted by cmp A B The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext immi3 sign21 20 8 jrle 819017 jrle sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext 1 13 1 13 2 0 sign24 23 21 ext 1 13 sign24 20 8 jrle sign7 jrle sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates imm413 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrle d sign7 For jrle d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j rle d instruction and the next instruction so no interrupts occur cmp 0 1 r0 and r1 cont
138. ast significant bits of the address to 0 7 74 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id a mm7 rs Function Code Flag CLK Description 32 bit data transfer Standard A imm7 23 0 lt rs 23 0 A imm7 31 24 0 Extension 1 A imm20 23 0 lt rs 23 0 A imm20 31 24 lt 0 Extension 2 A imm24 23 0 lt rs 23 0 A imm24 31 24 lt 0 15 14 13 12 11 0 9 8 7 6 5 4 3 2 11011 rs IL IE V Z N Src Register direct 2rs r0 to r7 Dst Immediate data unsigned One cycle 1 Standard ld a imm7 rs memory address imm7 The content of the rs register is transferred to the memory address specified with the 7 bit immediate imm7 This instruction writes 32 bit data with the eight high order bits set to O in the memory 2 Extension 1 ext 1 13 imm20 19 7 ld a imm7 rs memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the rs register is transferred to the memory address specified with the 20 bit immediate imm20 3 Extension 2 ext immi3 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 ld a imm7 rs memory address imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of the rs register is transferred to the memory address specified with the
139. ate imm7 added as displacement comprises the memory address to be accessed This instruction writes 32 bit data with the eight high order bits set to 0 in the memory 2 Extension 1 ext 1 13 imm7 rs imm20 19 7 memory address imm7 imm20 6 0 sp imm20 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the rs register is transferred to the address indicated by the content of the SP with the 20 bit immediate imm20 added 3 Extension 2 ext 1 13 ext immi3 i imm7 rs imm13 3 0 imm24 19 7 memory address imm7 imm24 6 0 imm24 23 20 sp imm24 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of the rs register is transferred to the address indicated by the content of the SP with the 24 bit immediate imm24 added 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ext 0x1 ld a sp 0x2 rO0 sp 0x82 lt ro The SP and displacement must specify 32 bit boundary address two least significant bits 0 Specifying other address causes an addre ss misaligned interrupt Note however that the data transfer is performed by setting the two le
140. ation Data transfer i Flag Mnemonic Cycle IL IE V ld b rs 1 grd rb 1 2 1 2 2 2 ssp imm7 2 imm7 1 1 2 1 rb rs 2 2 rb rs 2 Ssp imm7 rs 2 imm7 rs 1 ld ub rd 2rs 1 2rd rb 1 2 2 2 rd rb 2 ssp imm7 2 imm7 1 1 rd rs 1 rd sign7 1 2rd rb 1 2 rb 2 2 2 ssp imm7 2 imm7 1 1 2 rb rs 2 5 2 rb rs 2 Ssp imm7 rs 2 imm7 rs 1 1 1 1 7 1 2rd 2rb 1 2 8 183 1 2 2 rd rb 2 ssp imm7 2 imm7 1 1 2 1 rb
141. ation of flags so that only when the conditions are satisfied do they cause the program to branch to a specified address The program does not branch unless the conditions are satisfied The conditional jump instructions basically use the result of the comparison of two values by the cmp instruc tion to determine whether to branch For this reason the name of each instruction includes a character that rep resents relative magnitude The types of conditional jump instructions and branch conditions are listed in Table 5 8 1 1 Table 5 8 1 1 Conditional Jump Instructions and Branch Conditions Instruction Flag condition Comparison of A B Remark jrgt Than IZ amp N V A gt B Used to compare jrge or Equal A gt B signed data jrlt Less Than N V A B jrle Less or Equal Z N V A lt B jrugt Unsigned Greater Than IZ amp C A gt B Used to compare jruge Unsigned Greater or Equal IC gt unsigned jrult Unsigned Less Than C A B jrule Unsigned Less or Equal 2 lt jreq 2 jrne Not Equal 12 Comparison of A B made when 2 Absolute jump instructions The absolute jump instruction jpa causes the program to unconditionally branch to the location indicated by the content of a specified general purpose register rb or an immediate imm7 can be extended to imm20 or imm24 using the ext instruct
142. b Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 rb calla 0000 0 0 0 1 1 0 0 0 1 calla d IL IE C V ZN PC absolute 11 Four 5 calla d Three cycles 1 Standard calla rb Stores address of the following instruction into the stack then sets contents of rb register to the PC for calling the subroutine that starts from the address set to the PC The LSB of the rb register is invalid and is always handled as 0 When the ret instruction is executed in the subroutine the program flow returns to the instruction following calla instruction 2 Delayed branch d bit bit 7 1 calla d rb When calla d is specified the d bit bit 7 in the instruction code is set and the following instruction becomes a delayed slot instruction The delayed slot instruction is executed before branching to the subroutine Therefore the address PC 4 of the instruction that follows the delayed slot instruction is stored into the stack as the return address When the calla d instruction is executed interrupts cannot occur because traps are masked between the calla d and delayed slot instructions calla 5 0 Calls the subroutine that starts from the address stored in the r0 register When the calla d instruction delayed branch is used be careful to ensure that the next instruction i
143. b pcerb 3 jrgt jrgt d 51007 010 010 101111 014 2 519 8 if 28 is true sign8 sign7 0 3 jrge d Sign7 010 010 101111 1 4 sign7 2 519 8 if is true sign8 sign7 0 3 jrit d sign7 sign7 2 519 8 if NAV is true sign8 sign7 0 3 jrle d sign 0 0 0 0 1 0 0 1 d sign7 2 819 8 if Z is true sign8 sign7 0 3 jrugt jrugt d sign7 sign7 pc pc 2 sign8 if Z amp IC is true sign8 sign7 0 3 jruge jruge d sign7 sign7 2 519 8 if is true sign8 sign7 0 3 jrult jrult d sign7 11 sign7 2 519 8 if C is true sign8 sign7 0 3 jrule jrule d sign7 0 00 0 0 1 1 0 1 d sign7 2 819 8 if Z C is true sign8 sign7 0 3 jreq d sign 1 1 sign7 pcc pc 2 signe if Z is true sign8 sign7 0 3 sign7 010 010 111111 1 4 sign7 2 519 8 if 12 is true sign8 sign7 0 3 call call d sign10 010 011 1114 510110 4 lt 2 9 0 4 9 lt 1 lt 2 5 9 11 sign11 sign10 0 3 9erb 010 010 101010 1 rb sp lt sp 4 lt 2 9 0 4 9 1 2 3 calla calla d imm7 4 lt 2 9 0 4 9 lt 1 3
144. be accepted even if the IE bit is set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with bit ETIAM di Disables external maskable interrupts 7 28 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Enable interrupts Standard psr IE lt 1 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 000000 CV o SE EE ESI CLK One cycle 1 Standard Sets the IE bit in the PSR to enable external maskable interrupts olo eoe Gajra ole 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit 1 Enables external maskable interrupts 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 29 7 DETAILS OF INSTRUCTIONS ext imm13 Caution Immediate extension Standard Extends the immediate data operand of the following instruction Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 1 9 8 7 6 5 4 3 2 0 1 0 13 IL IE C V ZN Immediate data unsigned One cycle Extends the immediate data or operand of the following instruction When extending an immediate data the immediate data in the ext instruction will be p
145. ble default When this bit is set to 1 instruction fetch addresses will be compared with the value set in the Instruction Break Address Register 0 OxffffbO and an instruction break will occur if they are matched Setting this bit to 0 disables the comparison SE Single Step Enable Bit Enables disables single step execution R W Enable 0 R W Disable default DM Debug Mode Bit Indicates the current operation mode of the processor debug mode or user mode 1 0 Debug mode User mode default EPSON 51 17 FAMILY 51 17 CORE MANUAL OxFFFFBO Instruction Break Address Register 0 IBARO 6 FUNCTIONS Register name Address Bit Name Function Setting Init R W Remarks Instruction FFFFBO 031 24 Unused fixed at 0 0x0 R break address L D23 IBAR023 Instruction break address 0 0x0 0xFFFDE R W register 0 IBAROO is fixed at 0 DO IBAROO D 23 0 IBARO 23 0 Instruction Break Address 0 This register is used to set instruction break address Default 0x000000 OxFFFFBA Instruction Break Address Register 1 1 Register name Address Bit Name Function Setting Init R W Remarks Instruction FFFFB4 031 24 Unused fixed at 0 0 0 R break address L 023 IBAR123 Instruction break address 1 0x0 0xFFFDE 0x0 R W register 1 IBAR10 is fixed at 0 D
146. by the ext instruction cannot be performed Cang 000 r0 Oxffff OxOOffff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 53 7 DETAILS OF INSTRUCTIONS Id erb ers Id rb rs Id rb rs Id rb rs Function 16 bit data transfer Code 19 rb rs Standard Wi rb lt rs 15 0 Extension 1 W rb imm13 lt rs 15 0 Extension 2 W rb imm24 lt rs 15 0 Id rb rs with post increment option Standard Wi rb lt rs 15 0 rb 23 0 lt rb 23 0 2 Extension 1 W rb imm13 lt rs 15 0 rb 23 0 lt rb 23 0 imm13 Extension 2 W rb imm24 rs 15 0 rb 23 0 rb 23 0 imm24 Id rb rs with post decrement option Standard Wi rb lt rs 15 0 rb 23 0 lt rb 23 0 2 Extension 1 W rb imm13 rs 15 0 rb 23 0 rb 23 0 imm13 Extension 2 W rb imm24 lt rs 15 0 rb 23 0 lt rb 23 0 imm24 Id erb ers with pre decrement option Standard rb 23 0 rb 23 0 2 W rb rs 15 0 Extension 1 rb 23 0 lt rb 23 0 imm13 W rb imm13 lt rs 15 0 Extension 2 rb 23 0 lt rb 23 0 imm24 W rb imm24 lt rs 15 0 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 0 0 10 0 1 ws 0 0 1 0 rb 14 856 0 0 1 0 0 1 ws 0 1 1 0 rb 14 rb rs 0 0 1 0 0 1 LE 1 1 1 0 ld 001 00 Ts 1 0 1 0 rb ld rb rs Src Register direct 2rs r0 to r7
147. c or nc suffix on the opcode specifies conditional execution cmc c Executed as cmc when the C flag is 1 or executed as nop when the flag is 0 cmc nc Executed as cmc when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 cme r0 r1 Changes the flags according to the results of FO e rl C 2 ext 1 cmc 8 1 3 2 Changes the flags according to the results of r2 Oxlfff C 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 17 7 DETAILS OF INSTRUCTIONS cmc rd sign7 Function 16 bit comparison with carry Standard rd 15 0 sign7 sign extended C Extension 1 rd 15 0 sign16 C Extension 2 Unusable H 50050 00500 00009 8 27655252 1 1 00 1 9 I rd sign7 IL IE C Z leleleolo Mode Src Immediate data signed Dst Register direct r0 to 17 cycle 1 Standard mc rd sign7 rd sign7 C Subtracts the contents of the signed 7 bit immediate sign7 and C carry flag from the contents of the rd register and sets or resets the flags C V Z and N according to the results The sign7 i
148. ccepted by the processor and only interrupts with priority levels higher than that are accepted Interrupts with the same interrupt level as IL cannot be accepted The IE flag can be set in the software When an interrupt occurs the IE flag is cleared to 0 interrupts disabled after the PSR is saved to the stack and the maskable interrupts remain disabled until the IE flag is set in the handler routine or the handler routine is terminated by the reti instruction that restores the PSR from the stack The IL field is set to the priority level of the interrupt that occurred Multiple interrupts or the ability to accept another interrupt during interrupt handling if its priority is higher than that of the currently serviced interrupt can easily be realized by setting the IE flag in the interrupt handler routine When the processor is reset the PSR is initialized to 0 and the maskable interrupts are therefore disabled and the interrupt level is set to O interrupts with priority levels 1 7 enabled The following describes how the maskable interrupts are accepted and processed by the processor 1 Suspends the instructions currently being executed The interrupt is accepted synchronously with the rising edge of the system clock at the end of the cycle of the currently executed instruction 2 Saves the contents of the PC current value and PSR to the stack SP in that order 3 Clears the IE flag in the PSR and copy the priority level of the ac
149. cepted interrupt to the IL field 4 Reads the vector for the interrupt from the vector address in the vector table and sets it in the PC The processor then branches to the interrupt handler routine In the interrupt handler routine the reti instruction should be executed at the end of processing In the reti instruction the saved data is restored from the stack in order of the PC and PSR and the processing returns to the suspended instructions 6 8 EPSON 1C17 FAMILY 51 17 CORE MANUAL 6 FUNCTIONS 6 3 8 Software Interrupts The S1C17 Core provides the int imm5 and intl imm5 imm3 instructions allowing the software to generate any interrupts The operand imm5 specifies a vector number 0 31 in the vector table In addition to this the int1 instruction has the operand imm3 to specify an interrupt level 0 7 to be set to the IL field in the PSR The processor performs the same interrupt handling as that of a hardware interrupt 6 3 9 Interrupt Masked Period Address misaligned interrupts NMIs debug interrupts and external maskable interrupts are masked between the specific instructions listed below and cannot be generated during that period pending state When the processor exits the masked period the pending interrupt can be accepted 1 Between the ext instruction and the next instruction 2 Between a delayed branch instruction and the delayed slot instruction that follows 3 Between the retd instruction and t
150. contains the trap table base address The trap table also called a vector table contains the vectors to the interrupt handler routines handler routine start address that will be read by the S1C17 Core to execute the handler when an interrupt occurs The boot address from which the program starts running after a reset must be written to the top of the trap table 4 2 2 Processor ID Register IDIR Oxffff84 Register name Address Bit Name Function Setting Init R W Remarks Processor ID FFFF84 07 IDIR7 Processor ID 0x10 0x10 R register B 0x10 S1C17 Core DO IDIRO This is a read only register that contains the ID code to represent a processor model The S1C17 Core s ID code is 0x10 4 2 3 Debug RAM Base Register DBRAM 0xffff90 Register name Address Bit Name Function Setting Init R W Remarks Debug RAM FFFF90 031 24 Unused 0 0x0 R base register L D23 DBRAM23 Debug RAM base address 0 0 value is set in DBRAM 5 0 is fixed at 0x0 64 byte units the C17 RTL define DBRAMO DBRAM BASE This is a read only register that contains the start address of a work area 64 bytes for debugging n addition to the above registers the reserved core I O area contains some registers for debugging For the debug registers refer to Section 6 5 Debug Circuit 4 2 EPSON 51 17 FAMILY
151. contents of the rd register and sets resets the flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the contents of the rd register 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ETIAM 1 emp r0 0x3f Changes the flags according to the results of 7 X0 Ox3f 2 ext Oxlff cmp r1 0x7f Changes the flags according to the results of rl Oxffff 7 20 EPSON 51 17 FAMILY S1C17 CORE MANUAL cmp a cmp a c 7 DETAILS OF INSTRUCTIONS rs 9 Gmp aine rd rs 24 bit comparison Code Flag L Description Standard 23 0 rs 23 0 Extension 1 rs 23 0 imm13 zero extended Extension 2 rs 23 0 imm24 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 00110 1 10 0 0 0 9 T 1 0 1 0 0 0 0 rs 0 0 1 1 0 I rd 0 1 0 0 rs cmp a nc IL IE C V Z N el e cmp a e cmp a c cmp a nc Src Register direct 2rs r0 to r7 Dst Register direct rd r0 to r7 One cycle 1 Standard rd rs Subtracts the contents of the rs register from the contents of the rd register and sets or resets the fla
152. d Also 572110 operand in the jpr and call instructions can be extended to 24 bit quantity using one ext instruction Example ext 1 13 call 5819010 call sign24 23 11 10 10 Immediate S imm13 sign10 0 23 T 0 PC Current address 0 23 Y 0 PC New address 0 5 3 6 Extension of PC Absolute Addressing Extending the branch destination address The imm7 immediate is extended to a 20 or 24 bit immediate Extending to a 20 bit immediate To extend the immediate to 20 bit quantity enter one ext instruction directly before the target instruction Example ext calla Immediate PC imm13 imm7 calla 20 23 20 19 6 0 0 0 0 0 imm13 imm7 23 Y 0 New address Extending to a 24 bit immediate To extend the immediate to 24 bit quantity enter two ext instructions directly before the target instruction Example ext imm13 1 ext immi3 2 jpa imm7 jpa imm24 23 20 19 6 0 Immediate imm13 3 0 1 imm13 2 imm7 23 Y 0 PC New address EPSON 51 17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET 5 4 Data Transfer Instructions The transfer instructions in the 51 17 Core support data transfer between one register and another as well as be tween a register and memory A transfer data size and data extension format can be specified in the instruction code In mnemonics this specification is classified as follows ld b
153. d in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 4 ext immi3 imm13 2 0 imm16 15 13 ext immi3 imml6 12 0 sub srs rd amp rs 11016 The 16 bit immediate imm16 is subtracted from the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered Conditional execution The c or nc suffix on the opcode specifies conditional execution sub c Executed as sub when the C flag is 1 or executed as nop when the flag is 0 sub nc Executed as sub when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction 1 This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed sub r0 r0 10 10 ro 2 ext 0x1 ext Ox1fff sub r1 r2 rl r2 Ox3fff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 113 7 DETAILS OF INSTRUCTIONS sub rd 1117 16 bit subtraction Standard rd 15 0 lt rd 15 0 imm7 zero extended rd 23 16 lt 0 Extension 1 rd 15 0 lt rd 15 0 imm16 rd 23 16 0 Extension 2 Unusable 15 14 13 12 11 1 9 8 7 6 5 4 3
154. data transfer Code Id ub erd erb Standard rd 7 0 lt B rb rd 15 8 lt 0 rd 23 16 lt 0 Extension 1 rd 7 0 lt B rb imm13 rd 15 8 lt 0 rd 24 16 0 Extension 2 rd 7 0 lt B rb imm24 rd 15 8 lt 0 rd 24 16 0 Id ub rd rb with post increment option Standard 7 0 lt B rb rd 15 8 lt 0 rd 23 16 lt 0 rb 23 0 lt rb 23 0 1 Extension 1 rd 7 0 lt B rb imm13 rd 15 8 0 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 rd 7 0 lt B rb imm24 rd 15 8 0 rd 24 16 lt 0 rb 23 0 rb 23 0 imm24 Id ub rd rb with post decrement option Standard 7 0 lt B rb rd 15 8 lt 0 rd 23 16 lt 0 rb 23 0 lt rb 23 0 1 Extension 1 rd 7 0 lt B rb imm13 rd 15 8 lt 0 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 rd 7 0 lt B rb imm24 rd 15 8 lt 0 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm24 Id ub rd rb with pre decrement option Standard rb 23 0 lt rb 23 0 1 rd 7 0 lt B rb rd 15 8 lt 0 rd 23 16 lt 0 Extension 1 rb 23 0 lt rb 23 0 imm13 rd 7 0 lt B rb imm13 rd 15 8 lt 0 rd 24 16 0 Extension 2 rb 23 0 lt rb 23 0 imm24 rd 7 0 lt B rb imm24 rd 15 8 lt 0 rd 24 16 lt 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1000 rd 0 0 0 I rb ld ub rd rb ot 0 9 Ol l tub 4 ter 001 00 0 rd 1 1 0 1
155. dd a sp imm7 Sp lt sp imm7 The 7 bit immediate imm7 is added to the stack pointer SP after being zero extended 2 Extension 1 ext immi3 imm20 19 7 add a sp imm7 Sp lt sp imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is added to the stack pointer SP after being zero extended 3 Extension 2 ext immi3 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 add a sp imm7 Sp lt sp imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is added to the stack pointer SP 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 add a sp 0x7f Sp sp Ox7f 2 ext Oxlfff add a sp 0x7f Sp Sp Oxfffff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 9 7 DETAILS OF INSTRUCTIONS and erd rs and nc 16 bit logical AND Standard rd 15 0 lt rd 15 0 amp rs 15 0 rd 23 16 lt 0 Extension 1 rd 15 0 lt rs 15 0 amp imm13 zero extended rd 23 16 0 Extension 2 rd 15 0 lt rs 15 0 amp imm16 rd 23 16 lt 0 ETE 8 2765 552 1 0 0 1 0 1 1 rd 1 0 0 0 TS and 0 0 1 0 1 1 0 0 0 0 TS and c 0 0 1 0 I 1 rd 0 1 0 0 0 Mode Src Register direct rs r0 to r7 Ds
156. e and bits 23 16 of the rd register are set to 0 rd register after execution 2 Extension 23 16 15 XXXXXXXX rs Sign bit gt Y 00000000 5 5 Using the ext instruction extends 7 bit immediate imm7 to 20 bit immediate imm20 or 24 bit immediate imm24 However there is no difference in operation from the standard instruction without extension 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit included In this case extension of the immediate by the ext instruction cannot be performed 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 105 7 DETAILS OF INSTRUCTIONS sbc sbc c rs rd Yrs sbc nc rd rs ET 16 bit subtraction with borrow Standard Extension 1 rd 15 0 lt rs 15 0 imm13 zero extended rd 23 16 lt 0 Extension 2 rd 15 0 lt rs 15 0 imm16 C rd 23 16 lt 0 rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 0 ETE 8 265 2 1 0 0 0 1 1 1 0 rd 1 0 1 1 001110 0011 TS sbc c 001110 rd 0 1 1 1 ws sbc nc IL IE C V ZN e e e e sbe lt gt lt gt lt gt sbc c sbc nc Mode Src Register direct 2rs ro to r7 Dst Register direct rd r0 to r7 One cycle 1 Standard Example
157. e 1 196101 00 Byte 0 Figure 3 2 7 1 32 Bit Transfer Register gt Memory 3 4 EPSON 51 17 FAMILY S1C17 CORE MANUAL 4 ADDRESS MAP 4 Address Map 4 1 Address Space The S1C17 Core Supports 24 bit address allowing linear of address Space to 16M bytes Addresses Oxfffe00 to Oxffffff are reserved as an I O area for the core In addition to this area a 64 byte area located in user RAM is required for debugging Figure 4 1 1 shows the address space of the S1C17 Core Oxff ffff Oxff 0 Oxff fdff Reserved core I O area 0x00 0000 Figure 4 1 1 Address Space of the S1C17 Core The boot address and debug RAM address depend on the specifications of each the S1C17 Series models Refer to the Technical Manual of each model 51 17 FAMILY 51 17 CORE MANUAL EPSON 4 1 4 ADDRESS MAP 4 2 Processor Information in Core Area The reserved core I O area contains processor information described below 4 2 1 Trap Table Base Register TTBR Oxffff80 Register name Address Bit Name Function Setting Init R W Remarks Trap table FFFF80 031 24 Unused fixed at 0 0x0 0x0 R base register L D23 TTBR23 Trap table base address 0 0 Initial value is set by TTBRI 7 0 is fixed at 0x0 256 byte units the TTBR pins of the DO TTBRO C17 macro This is a read only register that
158. e base address is decremented by an amount equal to the access size before accessing the memory Also any desired value can be specified as the address increment decrement value using the ext instruc tion rb is also used as a symbol indicating the register that contains the jump address for the call or jump in structions In this case the brackets are unnecessary and the register is written as 510 r1 517 The field that specifies a register in the instruction code contains code corresponding to given register number The relationship between the general purpose registers and the register numbers is listed in the table below Table 2 5 1 1 General Purpose Registers General purpose register Register number Register notation RO 0 2 0 R1 1 rl R2 2 Sr2 R3 3 r3 R4 4 r4 R5 5 r5 R6 6 r6 R7 7 r7 2 5 2 Special Registers The special registers that can be directly specified in the S1C17 Core instructions are the SP Stack Pointer and PC Program Counter only The register is actually written as ssp 5 sp 5 1 Ssp imm7 or Spc 1017 FAMILY 51 17 CORE MANUAL EPSON 2 7 2 REGISTERS THIS PAGE IS BLANK 2 8 EPSON 51 17 FAMILY S1C17 CORE MANUAL 3 DATA FORMATS 3 Data Formats 3 1 Data Formats Handled in Operations Between Registers The S1C17 Core can handle 8 16 and 24 bit data in register operations In this man
159. e registers cmp c Supports conditional execution c executed if C 1 nc executed if C 0 cmp nc cmp rd sign7 16 bit comparison of general purpose register and immediate cmp a rd rs 24 bit comparison between general purpose registers cmp a c Supports conditional execution c executed if C 1 nc executed if C 0 cmp a nc cmp a rd imm7 24 bit comparison of general purpose register and immediate cmc rd rs 16 bit comparison with carry between general purpose registers cmc c Supports conditional execution c executed if C 1 nc executed if C 0 cmc nc cmc rd sign7 16 bit comparison of general purpose register and immediate with carry Logical operation and rd rs Logical AND between general purpose registers and c Supports conditional execution c executed if C 1 nc executed if C 0 and nc and rd sign7 Logical AND of general purpose register and immediate or rd rs Logical OR between general purpose registers or c Supports conditional execution c executed if C 1 nc executed if C 0 or nc rd sign7 Logical OR of general purpose register and immediate xor rd rs Exclusive OR between general purpose registers xor c Supports conditional execution c executed if C 1 nc executed if C 0 xor nc xor rd sign7 Exclusive OR of general purpose register and immediate not rd rs Logical inversion between general purpose registers 1 s complement not c Supports conditional execution c executed
160. ecial registers e One 8 bit special register Memory space and bus Up to 16M bytes of memory space 24 bit address Harvard architecture using separated instruction bus 16 bits and data bus 32 bits Interrupts Reset NMI and 32 external interrupts supported Address misaligned interrupt Debug interrupt Direct branching from vector table to interrupt handler routine Programmable software interrupts with a vector number specified all vector numbers specifiable Power saving HALT halt instruction SLEEP s1p instruction Coprocessor interface ALU instructions can be enhanced 51 17 FAMILY 51 17 CORE MANUAL EPSON 1 1 1 SUMMARY THIS PAGE IS BLANK 1 2 EPSON 51 17 FAMILY S1C17 CORE MANUAL 2 REGISTERS 2 Registers The S1C17 Core contains eight general purpose registers and three special registers Special registers General purpose registers bit 23 bit 0 bit 23 bit 0 PC 7 R7 SP 6 R6 PSR 5 R5 4 R4 7 6 5 4 2 1 90 3 R3 IL 2 0 2 2 R2 1 R1 0 RO Figure 2 1 Registers 2 1 General Purpose Registers RO R7 Symbol Register name Size R W Initial value RO R7 Register 24 bits R W 0x000000 or indeterminate The eight registers RO R7 r0 7 24 bit general purpose registers that can be used for data manipulation data transfer memory addressing or
161. ect 15 r0 to r7 Dst Immediate data unsigned One cycle 1 Standard ld b imm7 rs memory address Sp imm7 The eight low order bits of the rs register are transferred to the memory address specified with the 7 bit immediate imm7 2 Extension 1 ext 1 13 14 0 imm7 rs imm20 19 7 memory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the eight low order bits of the rs register are immediate imm20 3 Extension 2 ext immi3 ext 1 13 14 0 imm7 rs transferred to memory address specified with the 20 bit imm24 23 20 imm24 19 7 memory address imm7 imm24 6 0 imm24 The two ext instructions extend the displacement to a 24 bit quantity As a result the eight low order bits of the rs register are transferred to the memory address specified with the 24 bit immediate 24 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed EVI ld b 0x1 0x1 r0 i B 0x81 lt 8 low order bits of 7 84 EPSON 51 17 FAMILY S1C17 CORE MANUAL rd 9615 Transfer data to the coprocessor and get the results Standard Extension 1 Unusable Extension 2 Unusable 9 8 7
162. elayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 1 and r0 r0 rO ro ro 2 ext 0x1 ext Oxlfff and r1 r2 rl r2 amp Ox3fff 7 10 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS and sign7 16 bit logical AND Standard rd 15 0 lt rd 15 0 amp sign7 sign extended rd 23 16 lt 0 Extension 1 rd 15 0 lt rd 15 0 amp signl6 rd 23 16 0 Extension 2 Unusable ETE 8 2765 5252 1 0 1 1 0 1 0 0 0 sign IL IE C V 7 0 Mode Src Immediate data signed Dst Register direct rd r0 to r7 One cycle 1 Standard and rd sign7 rd 6 rd amp sign7 The content of the rd register and the sign extended 7 bit immediate sign7 are logically AND ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm13 1 13 8 0 19 16 15 7 and rd sign7 rd rd amp 810116 sign7 51 9 16 6 0 The content of the rd register and the 16 bit immediate 570176 are logically and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This instruction may be
163. ement option The memory address will be incremented after the data transfer has finished ld 2 Load instruction with post decrement option The memory address will be decremented after the data transfer has finished ld rb rs Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 2 16 bit size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed The rb register and the displacement must specify a 16 bit boundary address least significant bit 0 Specifying an odd address causes an address misaligned interrupt Note however that the data transfer is performed by setting the least significant bit of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 55 7 DETAILS OF INSTRUCTIONS Id sp imm7 rs Function 16 bit data transfer Standard W sp imm7 lt rs 15 0 Extension 1 W sp imm20 lt rs 15 0 Extension 2 W sp imm24 lt rs 15 0 ETE 8 7 6 5 4 2 1 0 1 1 1 1 1 0 rs imm7 000 CV
164. emory address imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the byte data in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext immi3 imm24 31 19 ext imm13 imm24 18 6 ld ub rd imm7 memory address imm24 imm7 imm24 5 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the byte data in the memory address specified with the 24 bit immediate imm24 is transferred to rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed LEVINE ox ld ub r0 0 1 lt 0x81 zero extended 1017 FAMILY 51 17 CORE MANUAL EPSON 7 95 7 DETAILS OF INSTRUCTIONS nop No operation Standard No operation Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 00 000000 LTEM 000 0 7o EXE Mode E CLK One cycle 1 Standard The nop instruction just takes one cycle and no operation results The PC is incremented 2 o ola
165. ent of the rs register is not altered 3 Extension 2 ext 1 13 imm13 10 0 imm24 23 13 ext immi3 imm24 12 0 add a rd rs rd lt rs imm24 The 24 bit immediate imm24 is added to the content of the rs register and the result is loaded into the rd register The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution add a c Executed as add a when the C flag is or executed as nop when the flag is 0 add a nc Executed as add a when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 add a r0 r0 r0 r0 ro 2 ext Ox7ff ext Oxlfff add a r1 r2 rl r2 Oxffffff 7 6 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS add a imm7 Function Code Flag CLK Description 24 bit addition Standard rd 23 0 lt rd 23 0 imm7 zero extended Extension 1 4 23 0 lt rd 23 0 imm20 zero extended Extension 2 4 23 0 lt rd 23 0 imm24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 rd IL IE V ZN Src Immediate data unsigned
166. er address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 7 62 EPSON 51 17 FAMILY 51 17 CORE MANUAL Id a Id a Id a Id a Function 7 DETAILS OF INSTRUCTIONS Vesp esp 5 rd 5 32 bit data transfer ld a rd Y sp Standard rd 23 0 lt A sp 23 0 ignored lt A sp 31 24 Extension 1 rd 23 0 lt A sp imm13 23 0 ignored lt A sp imm13 31 24 Extension 2 rd 23 0 lt A sp imm24 23 0 ignored lt A sp imm24 31 24 Id a rd sp with post increment option Standard 23 0 lt A sp 23 0 ignored lt A sp 31 24 sp 23 0 lt sp 23 0 4 Extension 1 rd 23 0 lt A sp imm13 23 0 ignored lt A sp imm13 31 24 5 23 0 sp 23 0 imm13 23 0 A sp imm24 23 0 ignored A sp imm24 31 24 8 23 0 lt sp 23 0 imm24 Extension 2 Id a rd 7esp with post decrement option Standard 23 0 lt A sp 23 0 ignored lt A sp 31 24 sp 23 0 lt sp 23 0 4 Extension 1 rd 23 0 lt A sp imm13 23 0 ignored lt A sp imm13 31 24 8 23 0 lt sp 23 0 imm13 Extension 2 rd 23 0 A sp imm24 23 0 ignored A sp imm24 31 24 8 23 0 lt sp 23 0 imm24 Id a sp with pre decrement option Standard sp 23 0 lt sp 23 0 4 rd 23 0 lt A sp 23
167. ewritten to that of the generated interrupt 4 Reads the vector for the generated interrupt from the vector table and sets it in the PC The processor thereby branches to the user s interrupt handler routine After branching to the user s interrupt handler routine when the reti instruction is executed at the end of interrupt handling the saved data is restored from the stack in order of the PC and PSR and the processing returns to the suspended instructions 6 3 4 Reset The processor is reset by applying a low level pulse to its rst n pin the registers are thereby cleared to 0 The processor starts operating at the rising edge of the reset pulse to perform a reset sequence In this reset sequence the reset vector is read out from the top of the vector table and set in the PC The processor thereby branches to the user s initialization routine in which it starts executing the program The reset sequence has priority over all other processing 51 17 FAMILY 51 17 CORE MANUAL EPSON 6 7 6 FUNCTIONS 6 3 5 Address Misaligned Interrupt The load instructions that access memory or I O areas are characteristic in that data size to be transferred is predetermined for each instruction used and that the accessed addresses must be aligned with the respective data size boundaries Instruction Transfer data size Address ld b ld ub Byte 8 bits Byte boundary applies to all addresses 16 bits 16 bit boundary least si
168. executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 r0 0x3e ro 2 ext Ox7ff and r1 0x3f sg ro Oxfffe rl 8 Oxlfff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 11 7 DETAILS OF INSTRUCTIONS brk Function Debugging interrupt Standard A DBRAM lt psr pc 2 A DBRAM 0x4 lt r0 pc lt Oxfffc00 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 4 3 2 1 0 0 0 0 0000 1 0 1100000 IL IE C V 7 CERA Four cycles Calls a debugging handler routine The brk instruction stores the address PC 2 that follows this instruction the contents of the PSR and the contents of the RO register into the work area for debugging then sets the mini monitor start address 00 to the PC Thus the program branches to the debug handler routine Furthermore the processor enters the debug mode The retd instruction must be used for return from the debug handler routine This instruction is provided for debug firmware Do not use it in the user program brk Executes the debug handler routine 7 12 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS call rb call d rb PC relative subroutine call Standard sp lt sp 4 A sp pc 2 pc pc 2 rb
169. extended C 23 16 0 rs 0 0 1 1 1 0 rd 1101110 rs rd 15 0 lt rd 15 0 rs 15 0 23 16 0 O sub c rd rs 110 rd 0101110 rs 9 15 0 lt 9 15 0 15 0 rd 23 16 lt 0 if C 1 nop if C 0 O sub nc rd Yrs 01011111110 rd 011 0 rs rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 lt 0 if C 0 nop if 1 e sub imm7 110 0101110 imm7 rd 15 0 lt rd 15 0 imm7 zero extended 23 16 0 Sub a rs 0101111 1010 rd 110 10 rs rd 23 0 e rd 23 0 rs 23 0 Sub a c 9ers 0101111 1010 0101110 rs rd 23 0 e rd 23 0 rs 23 0 if C 1 nop if C 0 O sub a nc 9ers 1110 0 0111110 rs rd 23 0 e rd 23 0 rs 23 0 if C 0 nop if C 1 O sub a 9 sp rs 0101111101010101010101111 rs sp 23 0 lt sp 23 0 rs 23 0 imm7 rd imm7 rd 23 0 e rd 23 0 imm7 zero extended o sp imm7 011111011 1 101010 imm7 sp 23 0 lt sp 23 0 imm7 zero extended sbc Yrs 0101111 1110 1101111 rs rd 15 0 lt rd 15 0 rs 15 0 C 23 16 0 Sbc c rs 110 0011 rs 9 15 0 lt 9 15 0 15 0 rd 23 16 lt 0 if 1 nop if 0 Sbc nc 9614 Yrs 0101111 1110 0111111 5 rd 15 0 lt rd 15 0 rs 15 0 C rd 23 16 lt 0 if C 0 nop if 1 Sbc imm7 1100011 rd imm7 rd 15 0 lt rd 15 0 imm7 zero extended C 23 16 0 rd Yrs 01011111111 rd 110 0 0
170. gister Example ext imm13 1 ext imm13 2 ld b rd rb imm24 23 0 rb Memory address pointer 23 13 12 0 Immediate imm13 10 0 1 imm13 2 5 10 EPSON S1C17 FAMILY S1C17 CORE MANUAL 5 INSTRUCTION SET 5 3 4 Extension of Register Indirect Addressing with Displacement Extending sp imm7 displacement The immediate imm7 in displacement added register indirect addressing instructions is extended The extended data and the SP are added to comprise the source or destination address of transfer Extending to a 20 bit immediate To extend the immediate to 20 bit quantity enter one ext instruction directly before the target instruction Example ext 1013 14 sp imm7 s ld ssp imm20 23 0 SP Stack pointer 23 20 19 7 6 0 Immediate 0 0 0 imm13 imm7 Extending to a 24 bit immediate To extend the immediate to 24 bit quantity enter two ext instructions directly before the target instruction Example ext imm13 1 ext imm13 2 ld ssp imm7 ld ssp imm24 23 0 SP Stack pointer 23 20 19 7 6 0 Immediate imm13 3 0 1 imm13 2 imm7 5 3 5 Extension of Signed PC Relative Addressing Extending the displacement of PC relative branch instructions The sign7 immediate in PC relative branch instructions is extended to a signed 21 bit or a signed 24 bit im mediate The
171. gn extended 7 76 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id b 26 0 rb Id b rd rb Id b rd erb Id b rd rb Signed byte data transfer rd rb Standard rd 7 0 lt B rb 4 15 8 lt B rb 7 rd 23 16 0 Extension 1 rd 7 0 lt B rb imm13 rd 15 8 lt B rb imm13 7 rd 24 16 0 Extension 2 rd 7 0 lt B rb imm24 rd 15 8 lt B rb imm24 7 rd 24 16 0 Id b rd rb with post increment option Standard 7 0 lt B rb rd 15 8 lt B rb 7 rd 23 16 lt 0 rb 23 0 lt rb 23 0 1 Extension 1 rd 7 0 lt B rb imm13 rd 15 8 lt B rb imm13 7 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 rd 7 0 lt B rb imm24 rd 15 8 lt B rb imm24 7 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm24 Id b rd rb with post decrement option Standard 7 0 lt B rb rd 15 8 lt B rb 7 rd 23 16 lt 0 rb 23 0 lt rb 23 0 1 Extension 1 rd 7 0 lt B rb imm13 rd 15 8 lt B rb imm13 7 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 rd 7 0 lt B rb imm24 rd 15 8 lt B rb imm24 7 rd 24 16 lt 0 rb 23 0 lt rb 23 0 imm24 Id b rd rb with pre decrement option Standard rb 23 0 lt rb 23 0 1 rd 7 0 lt B rb rd 15 8 lt B rb 7 rd 23 16 0 Extension 1 rb 23 0 lt rb 23 0 imm13 rd 7
172. gnificant address bit 0 ld a 32 bits 32 bit boundary two least significant address bits 00 If the specified address in a load instruction does not satisfy this condition the processor assumes an address misaligned interrupt and performs interrupt handling Even in this case the load instruction is executed as the least significant bit or the two low order bits of the address set to 0 The PC value saved to the stack in interrupt handling is the address of the load instruction that caused the interrupt This interrupt does not occur in the program branch instructions as the least significant bit of the PC is always fixed to 0 The same applies to the vector for interrupt handling 6 3 6 NMI An NMI is generated when the nmi input on the processor is asserted low When an NMI occurs the processor performs interrupt handling after it has finished executing the instruction currently underway 6 3 7 Maskable External Interrupts The S1C17 Core can accept up to 32 types of maskable external interrupts however the first three interrupt causes use the save vector address as the reset interrupt address misaligned interrupt and NMI It is only when the IE interrupt enable flag in the PSR is set that the processor accepts a maskable external interrupt Furthermore their acceptable interrupt levels are limited by the IL interrupt level field in the PSR The interrupt levels 0 7 in the IL field dictate the interrupt levels that can be a
173. gs C V Z and N according to the results It does not change the contents of the rd register 2 Extension 1 ext imm13 rd rs rs immi3 Subtracts the 13 bit immediate 13 from the contents of the rs register and sets or resets the flags C Z and according to the results The 3 is zero extended into 24 bits prior to the operation It does not change the contents of the rd and rs registers 3 Extension 2 ext immi3 imm13 10 0 imm24 23 13 ext immi3 imm24 12 0 rd rs imm24 Subtracts the 24 bit immediate imm24 from the contents of the rs register and sets or resets the flags C V Z and N according to the results It does not change the contents of the rd and rs registers 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution cmp a c Executed as cmp a when the C flag is 1 or executed as nop when flag is 0 cmp a nc Executed as cmp a when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 1 r0 rl Changes the flags according to the results of rO ri 2 ext 0 1 ext Oxlfff cmp a 8
174. handling To support multiple interrupts or another interrupt from within an interrupt set the IE flag in the PSR to 1 in the interrupt handler routine to enable interrupts during interrupt handling Basically even when multiple interrupts are enabled interrupts whose priorities are below the one set by the IL 2 0 bits in the PSR are not accepted The debug interrupt does not use the vector table and the stack The PC and PSR are saved in a specific area along with RO The table below shows the addresses that are referenced when a debug interrupt occurs Table 6 3 1 2 Debug Interrupt Handler Start Address and Register Save Area Address Content OxfffcOO Debug interrupt handler start address DBRAM set value 0x00 PC and PSR save area DBRAM set value 0x04 RO save area DBRAM See Section 4 2 3 During debug interrupt handling neither other interrupts nor multiple debug interrupts are accepted They are kept pending until the debug interrupt handling currently underway finishes 6 6 EPSON 51 17 FAMILY 51 17 CORE MANUAL 6 FUNCTIONS 6 3 2 Vector Table Vector table in the S1C17 Core The table below lists interrupts which vector table 15 referenced during interrupt handling Table 6 3 2 1 Vector List Tecta Na Interrupt Vector address Software interrupt No 0 0x00 Reset TTBR 0x00 1 0x01 Address misaligned interrupt TTBR 0x04 2 0x02 NMI TTBR
175. he next instruction located at the return address 4 Between the reti or reti d instruction and the next instruction located at the return address 5 Between the int ei di slp or halt instruction and the next instruction 2 6 Between a conditional jump j instruction and the next instruction when the condition has not been met 2 An interrupt that occurs when the ret i d instruction is being executed will be accepted after the delayed slot instruction that follows and the next instruction located at the return address are executed reti d Delayed slot instruction Interrupt masked state Instruction at return address Interrupt masked state still continues so the next instruction will be executed before interrupts can be generated Next instruction Interrupt mask is released 2 The debug interrupt may occur even in the conditions 4 to 6 51 17 FAMILY 51 17 CORE MANUAL EPSON 6 9 6 FUNCTIONS 6 4 Power Down Mode The S1C17 Core Supports two power down modes HALT and SLEEP modes HALT mode Program execution 15 halted at Same time that S1C17 Core executes halt instruction processor enters HALT mode HALT mode commonly turns off only S1C17 Core operation note however that modules to be turned off depend on the implementation of the clock control circuit outside the core Refer to the technical manual of each model for details SLEEP mode Program execution is
176. he reti instruction intl 0x3 0x2 Generates an external maskable interrupt 0x3 and set the IL bits to 0 2 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 33 7 DETAILS OF INSTRUCTIONS jpa rb jpa d rb Caution Unconditional PC absolute jump Standard pc lt rb Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O0 000 0 0 0 0 1 0 1 0 0 I rb jpa 0 0 00000 1 1 100 I TD jpa d IL IE C V 7 PC absolute jpa Three cycles jpa d Two cycles 1 Standard jpa rb The content of the rb register is loaded to the PC and the program branches to that address The LSB of the rb register is ignored and is always handled as 0 2 Delayed branch d bit bit 7 1 jpa d rb For the jpa d instruction the next instruction becomes delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between d instruction and the next instruction so no interrupts occur jpa rO0 Jumps to the address specified by the r0 register When the jpa d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 7 84 EPSON 51 17 FAMILY
177. he software see Section 6 4 Normally the processor can be taken out of HALT or SLEEP mode by NMI or an external interrupt as well as initial reset 51 17 FAMILY 51 17 CORE MANUAL EPSON 6 1 6 FUNCTIONS 6 2 Program Execution Following initial reset the processor loads reset vector address of reset handler routine into the PC and starts executing instructions beginning with the address As the instructions in the 51 17 Core are fixed to 16 bits in length the PC is incremented by 2 each time an instruction is fetched from the address indicated by the PC In this way instructions are executed successively When a branch instruction is executed the processor checks the PSR flags and whether the branch conditions have been satisfied and loads the jump address into the PC When an interrupt occurs the processor loads the address for the interrupt handler routine from the vector table into the PC The vector table contains interrupt vectors beginning with the reset vector and is located from the address set in the TTBR register Oxffff80 The start address can be set to the TTBR in the configuration 6 2 1 Instruction Fetch and Execution Internally in the S1C17 Core instructions are processed in three pipelined stages so that the basic instructions except for the branch instructions and data transfer instructions with the memory address increment decrement function can be executed in one clock cycle Pipelining speeds
178. if C 1 nc executed if C 0 not nc not rd sign7 Logical inversion of general purpose register and immediate 1 s complement 5 2 EPSON 1C17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET Classification Mnemonic Function Shift and swap sr rd rs Logical shift to the right with the number of bits specified by the register rd imm7 Logical shift to the right with the number of bits specified by immediate sa rd rs Arithmetic shift to the right with the number of bits specified by the register rd imm7 Arithmetic shift to the right with the number of bits specified by immediate 81 rd rs Logical shift to the left with the number of bits specified by the register rd imm7 Logical shift to the left with the number of bits specified by immediate swap rd rs Bytewise swap on byte boundary in 16 bits Immediate extension ext 1 13 Extend operand in following instruction Conversion rd rs Convert signed 8 bit data into 24 bits cv as rd rs Convert signed 16 bit data into 24 bits cv al rd rs Convert 32 bit data into 24 bits cv la rd rs Converts 24 bit data into 32 bits cv ls rd rs Converts 16 bit data into 32 bits Branch jpr sign10 PC relative jump jpr d rb Delayed branching possible jpa imm7 Absolute jump ipa d rb Delayed branching possible jrgt sign7 PC relative c
179. imited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 35 7 DETAILS OF INSTRUCTIONS rb jpr d rb Caution Unconditional PC relative jump Standard pc amp pc 2 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 00000 1 0 1 000 rb jpr 0000000 1 1 1000 jpr d IL IE C V 7 Signed PC relative jpr Three cycles jpr d Two cycles 1 Standard jpr rb The content of the rb register is added to the PC PC 2 and the program branches to that address 2 Delayed branch d bit bit 7 1 jpr d srb For the instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the jpr d instruction and the next instruction so no interrupts occur jpr 8 pe 2 When the jpr d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix
180. ing with Displacement 5 11 5 3 5 Extension of Signed PC Relative 5 11 5 3 6 Extension of PC Absolute Addressing ppp 5 12 5 4 Data Transfer Instructioris ta ettet ede e a e Ebenen Ye Rie 5 13 5 5 Logical Operation Instructions mnes 5 14 5 6 Arithmetic Operation INStrUCtIONS 5 15 5 7 Shift and Swap 5 16 5 8 Branch and Delayed Branch Instructions ee 5 17 5 8 1 Types of Branch 5 8 5 17 5 8 2 Delayed Branch 5 21 5 9 System Control Instructions pp 5 22 5 10 Conversion 5 23 5 11 Coprocessor Instructiofis 22 5 24 6 8 4 25 2 252 2 224 22 42 550225 6 1 6 1 Transition of the Processor 6 1 611 Reset Stala ERI 6 1 6 1 2 Program Execution State cie Eee 6 1 6 1 3 Interrupt intentare terere retia er tinere 6 1 6 1 4 Debug Intei pt aii E Gat tete Ec eie Eo tee ees 6 1 6 1 5 HALT and SLEEP Modes pp 6 1 62 Program EXecUtlOni
181. instruc tion will be executed as a nop instruction 5 3 1 Extension of Immediate Addressing Extension of imm7 The imm7 immediate is extended to a 16 20 or 24 bit immediate Extending to a 16 bit immediate To extend the immediate to 16 bit quantity enter one ext instruction directly before the target instruction Example ext imm13 add rd imm7 add rd immi6 Extended immediate 15 7 6 0 imm13 8 0 imm7 Extending to a 20 bit immediate To extend the immediate to 20 bit quantity enter one ext instruction directly before the target instruction Example ext imm13 add a rd imm7 add a rd imm20 Extended immediate 23 20 19 7 6 0 0 0 0 oJ imm13 imm7 Bits 23 20 are filled with 0 zero extension Extending to a 24 bit immediate To extend the immediate to 24 bit quantity enter two ext instructions directly before the target instruction Example ext imm13 1 ext immi3 2 14 imm7 20 18 imm24 Extended immediate 23 20 19 7 6 0 130 1 imm13 2 imm7 5 8 EPSON 51 17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET Extension of sign7 The sign7 immediate is extended to a 16 bit immediate Extending to a 16 bit immediate To extend the immediate to 16 bit quantity enter one ext instruction directly before the target instruction Example ext 1013 14 rd sign7 Extended immediate 15 7 6 0 S imm13 8 0 sign7
182. instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met Z flag 0 and C flag 0 e g A gt B has resulted by cmp A B The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jrugt sign7 jrugt sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext 3 1 13 2 0 sign24 23 21 ext immi3 sign24 20 8 jrugt sign7 jrugt sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates imm 3 x 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrugt d sign7 For the j d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j rugt d instruction and the next instruction so no interrupts occur Example 3 0 3 1 r0 and rl co
183. ion as the absolute address When the content of the rb register or the immediate is loaded into the PC its least significant bit is always made 0 jpa rb 23 10 rb D 23 1 X v PC Branch destination address 0 S1C17 FAMILY 51 17 CORE MANUAL EPSON 5 19 5 INSTRUCTION SET jpa imm7 23 20 19 7 6 0 imm7 withnoext 0 0000000000000000 imm7 X with one ext 0 0 0 0 imm13 imm7 X imm7 with two ext imm13 3 0 imm13 imm7 X v PC Branch destination address 0 3 PC relative call instructions The PC relative call instruction call signi10 rb is subroutine call instruction that is useful for relocat able programming as it causes the program to unconditionally branch to a subroutine starting from an address calculated as PC 2 the next address of the branch instruction signed displacement specified by the oper and During branching the program saves the address of the instruction next to ca11 instruction for de layed branching the address of the second instruction following ca11 to the stack as the return address When the ret instruction is executed at the end of the subroutine this address is loaded into the PC and the program returns to it from the subroutine Note that because the instruction length is fixed to 16 bits the least significant bit of the displacement is always handled as 0 sign 0 doubled rb is not doubled causing the program to branch
184. ion so no interrupts occur add ret d Sro ZEL Executed before return from the subroutine Caution When the ret d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 101 7 DETAILS OF INSTRUCTIONS retd Function Return from a debug interrupt handler routine Standard r0 lt A DBRAM 0x4 23 0 psr lt A DBRAM 0x0 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 2 1 0 0 0 0 0000 1 0 1101000 IL IE C 7 Four cycles Restore the contents of the RO PSR and PC that were saved to the work area for debugging DBRAM when an debug interrupt occurred to the respective registers and return from the debug interrupt handler routine This instruction is provided for debug firmware Do not use it in the user program retd Return from a debug interrupt handler routine 7 102 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS reti reti d Return from trap handler routine Standard psr lt A sp sp lt sp 4 Extension 1 Unusable Extension 2 Unusable ETE 50050 eunwoo 8 7 6 5 552 1
185. ion cannot be performed The displacement must specify a 32 bit boundary address two least significant bits 0 Specifying other address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 7 64 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id a erd esp imm7 32 bit data transfer Standard rd 23 0 lt A sp imm7 23 0 ignored lt A sp imm7 31 24 Extension 1 rd 23 0 lt A sp imm20 23 0 ignored lt A sp imm20 31 24 Extension 2 rd 23 0 lt A sp imm24 23 0 ignored lt A sp imm24 31 24 Function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 1 1 0 1 1 rd 20 IL IE V ZN Mode Src Register indirect with displacement Dst Register direct rd r0 to r7 Two cycles 1 Standard ld a rd sp imm7 memory address sp imm7 The 32 bit data the eight high order bits are ignored in the specified memory location is transferred to the rd register The content of the current SP with the 7 bit immediate imm7 added as displacement comprises the memory address to be accessed 2 Extension 1 ext immi3 imm20 19 7 ld a rd sp imm7 memory address sp imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the SP with the 20 bit immediate i
186. ion execution Indicates that the bit is set 1 or reset 0 by instruction execution Indicates that the bit is set 1 by instruction execution Indicates that the bit is reset 0 by instruction execution 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 1 7 DETAILS OF INSTRUCTIONS adc rs erd rs adc nc rd rs 16 bit addition with carry Standard rd 15 0 lt rd 15 0 rs 15 0 rd 23 16 0 Extension 1 rd 15 0 lt rs 15 0 imm13 zero extended rd 23 16 lt 0 Extension 2 rd 15 0 lt rs 15 0 imm16 rd 23 16 0 005000000009 505 655 2 1 0 0 1 1 1 0 rd 1 0 0 1 TS adc 0 0 1 1 1 0 rd 0 0 0 1 TS adc c 0 01 1 1 0 0 1 0 1 FS gt gt lt gt lt gt adc lt gt adc c adc nc Mode Src Register direct 15 r0 to r7 Dst Register direct 2rd 5 0 to r7 One cycle 1 Standard adc rd rs rd amp rd rs The content of the rs register and C carry flag are added to the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 adc rd rs rd rs immi3 C The 13 bit immediate imm13 and C carry flag are added to the content of the rs register after being zero extended and the result is loaded into the rd register The operation is performed in
187. ion that follows it has already been fetched when it is executed the execution cycles of the branch instruction can be reduced by one cycle by executing the prefetched in struction before the program branches This is referred to as a delayed branch function and the instruction executed before branching i e the instruction at the address next to the branch instruction is referred to as a delayed slot instruction The delayed branch function can be used in the instructions listed below which in mnemonics is identified by the extension added to the branch instruction name Delayed branch instructions jrgt d jrge d jrit d jrle d jrugt d jruge d jrult d jrule d jreq d jrne d call d calla d jpr d jpa d ret d reti d Delayed slot instructions All instructions other than those listed below can be used as a delayed slot instruction Instructions that cannot be used as a delayed slot instruction brk call calla ext halt int jpa jpr jr ret retd reti slp The ext instruction cannot be used to expand the operand of delayed slot instructions A delayed slot instruction is always executed regardless of whether the delayed branch instruction used is con ditional or unconditional and whether it branches In non delayed branch instructions those not followed by the extension the instruction at the address next to the branch instruction is not executed if the program branches however if it is a conditional jump and the program
188. is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 emp r0 r1 Changes the flags according to the results of rO rl 2 ext 0x1 ext Oxlfff Changes the flags according to the results of rl1 r2 r2 Ox3fff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 19 7 DETAILS OF INSTRUCTIONS cmp sign7 Function 16 bit comparison Standard rd 15 0 sign7 sign extended Extension 1 rd 15 0 sign16 Extension 2 Unusable 8 265552 1 10 0100 rd sign7 IL IE V ZN e elee Mode Src Immediate data signed Dst Register direct r0 to r7 One cycle 1 Standard cmp 8197 rd sign7 Subtracts the signed 7 bit immediate sign7 from the contents of the rd register and sets or resets the flags C V Z and N according to the results The sign7 is sign extended into 16 bits prior to the operation The operation is performed in 16 bit size It does not change the contents of the rd register 2 Extension 1 ext immi3 imm13 8 0 19 16 15 7 cmp rd sign7 rd signl6 81907 signi6 6 0 Subtracts the signed 16 bit immediate 7676 from the
189. it quantity As a result the 16 low order bits of the rs register are transferred to the memory address specified with the 24 bit immediate imm24 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ext 0 1 14 0x2 r0 0 82 16 low order bits of ro The imm7 must specify a 16 bit boundary address least significant bit 2 0 Specifying an odd address causes an address misaligned interrupt Note however that the data transfer is performed by setting the least significant bit of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 57 7 DETAILS OF INSTRUCTIONS Caution 24 bit data transfer Standard 23 0 lt pc 23 0 2 Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 1 9 8 7 6 5 4 3 2 1 9 0 0 1 1 1 1 0 1100 0 0 IL IE C V 7 Src Register direct pc Dst Register direct r0 to r7 One cycle The content of the PC PC 2 is transferred to the rd register 14 5 0 5 r0 lt 2 When this instruction is executed a value equal to PC of this instruction plus 2 is loaded into the register This instruction must be executed as a delayed slot instruction If it does not follow a delayed branch instruction
190. iting it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed 0 data 1 12 1 data2 r4 r3 result 12 rl sub r1 r3 Subtraction of the low order word sbc r2 r4 Subtraction of the high order word 7 106 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS sbc rd imm7 Function 16 bit subtraction with borrow Standard rd 15 0 lt rd 15 0 imm7 zero extended C rd 23 16 lt 0 Extension 1 rd 15 0 lt rd 15 0 imm16 C rd 23 16 lt 0 Extension 2 Unusable 8 2765 1 0 1 9 0 0 1 1 rd eo e ee Mode Src Immediate data unsigned Dst Register direct rd ro to r7 One cycle 1 Standard sbc rd imm7 rd amp rd imm7 The 7 bit immediate imm7 and C carry flag are subtracted from the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm13 imm13 8 0 imm16 15 7 sbc rd imm7 rd rd immi6 C 107 immi6 6 0 The 16 bit immediate imm16 and C carry flag are subtracted from the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by wr
191. iting it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed BERN 0 soc gt ro ox7f r0 0 7 C 2 ext 1 sbe r1 0x7 Yl rl Oxffff 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 107 7 DETAILS OF INSTRUCTIONS sl rd rs LT Logical shift to the left Standard Shift the content of rd to left as many bits as specified by rs 0 3 4 or 8 bits LSB 0 Extension 1 Unusable Extension 2 Unusable H 0050 0 0 000095 2765 2 1 0 3 0 0 1 0 1 1 rd 1 1 1 9 rs e e e Mode Src Register direct 15 r0 to r7 Dst Register direct r0 to r7 One cycle 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the rs register value as follows rs 0 3 0 3 bits rs 4 7 4 bits rs 8 more 8 bits Data 0 is placed in the least significant bit of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 23 1615 0 rd register XXXXXXXX 4 0 Y after execution 0 0 0 0 0 0 0 0 o 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit included 7 108 EPSON 51 17 FAMILY S1C17 CORE M
192. its of the rs register are transferred to the rd register after being sign extended to 24 bits 23 16 15 0 rs S Word 23 16 15 0 rd S SSSSSS S S 16 bits 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the bit When 1 register contains 0 8000 cv as r0 r1 Oxff8000 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 25 7 DETAILS OF INSTRUCTIONS cv la rs Function Data conversion from 24 bits to 32 bits Standard rd 23 8 lt 0 rd 7 0 lt rs 23 16 Extension 1 Unusable Extension 2 Unusable 000050 00095 265 3 0 0 1 0 1 0 rd 0 1 1 0 rs 000 CV ZN Mode Src Register direct rs r0 to r7 Dst Register direct 4rd r0 to r7 One cycle 1 Standard The eight high order bits of the rs register are transferred to the eight low order bits of the rd register The 16 high order bits of the rd register are set to 0 23 16 15 0 rs 8 bits X Y 23 8 7 0 rd 0 000000000000000 8 bits 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit Example When the R1 register contains 0x800000 cv la r0 r1
193. ity As a result the content of the SP with the 20 bit immediate imm20 added comprises the memory address the 16 bit data in which is transferred to the rd register The eight high order bits of the rd register are set to 0 3 Extension 2 ext immi3 imm13 3 0 imm24 23 20 ext immi3 imm24 19 7 ld 5 imm7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of the SP with the 24 bit immediate imm24 added comprises the memory address the 16 bit data in which is transferred to the rd register The eight high order bits of the rd register are set to 0 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 14 ssp 0x2 r0 amp 0x82 The SP and the displacement must specify a 16 bit boundary address least significant bit 0 Specifying an odd address causes an address misaligned interrupt Note however that the data transfer is performed by setting the least significant bit of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 51 7 DETAILS OF INSTRUCTIONS Id erd imm7 ET 16 bit data transfer Standard rd 15 0 W imm7 rd 23 16 lt 0 Extension 1 rd
194. izes are listed below When no ext is used as in 1 shown above 4 32 bit size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed The rb register and the displacement must specify a 32 bit boundary address two least significant bits 0 Specifying other address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 71 7 DETAILS OF INSTRUCTIONS Id a 9esp ers 14 5 rs Id a 9esp ers Id a Vesp rs DT 32 bit data transfer Code Id a sp rs Standard A sp 23 0 lt rs 23 0 A sp 3 1 24 lt 0 Extension 1 A sp imm13 23 0 lt rs 23 0 A sp imm13 31 24 lt 0 Extension 2 A sp imm24 23 0 lt rs 23 0 A sp imm24 31 24 lt 0 Id a sp rs with post increment option Standard A sp 23 0 lt rs 23 0 A sp 3 1 24 lt 0 sp 23 0 lt sp 23 0 4 Extension 1 A sp imm13 23 0 lt rs 23 0 A sp imm13 31 24 lt 0 sp 23 0 lt sp 23 0 imm13 Extension 2 A sp imm24 23 0 lt rs 23 0 A sp imm24 31 24 lt 0 sp 23
195. laced on the high order side and the immediate data in the target instruction to be extended is placed on the low order side Up to two ext imm3 instructions can be used sequentially In this case the immediate data in the first ext instruction is placed on the most upper part When three or more ext instructions have been described sequentially the last two are effective and others are ignored See descriptions of each instruction for the extension contents and the usage Interrupts for the ext instruction not including reset and debug break are masked in the hardware and interrupt handling is determined when the target instruction to be extended is executed In this case the return address from interrupt handling is the beginning of the ext instruction ext Ox7ff ext Oxlfff add a r1 r2 gt PI When a load instruction that transfers data between memory and a register follows the ext instruction an address misaligned interrupt may occur before executing the load instruction if the address that is specified with the immediate data in the ext instruction as the displacement is not a boundary address according to the transfer data size When an address misaligned interrupt occurs the trap handling saves the address of the load instruction into the stack as the return address If the trap handler routine is returned by simply executing the reti instruction the previous ext instruction is invalidated Therefore
196. lt rb 23 0 imm13 Extension 2 A rb imm24 23 0 lt rs 23 0 imm24 31 24 lt 0 rb 23 0 lt rb 23 0 imm24 Standard Id a rb rs with pre decrement option Standard A rb 23 0 lt rs 23 0 A rb 31 24 0 Extension 1 A rb imm13 23 0 lt rs 23 0 A rb imm13 31 24 0 Extension 2 A rb imm24 23 0 lt rs 23 0 A rb imm24 31 24 0 rb 23 0 lt rb 23 0 4 A rb 23 0 lt rs 23 0 A rb 31 24 lt 0 Extension 1 rb 23 0 lt rb 23 0 imm13 A rb imm13 23 0 lt rs 23 0 A rb imm13 31 24 lt 0 Extension 2 rb 23 0 lt rb 23 0 imm24 Arb imm24 23 0 lt rs 23 0 A rb imm24 31 24 lt 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 10 0 1 rs 0 0 1 1 rb 14 rb rs 0 0 1 0 0 1 rs 0 1 1 1 rb 1d rb rs 00 100 1 rs 1 1 1 1 tb rb rs 0 0 1 0 0 1 rs 1 0 1 1 rb 1d rb rs SEEMHE Src Register direct 2rs r0 to r7 Dst Register indirect rb r0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard ld a rb rs memory address rb The content of the rs register 24 bit data is transferred to the specified memory location The rb register contains the memory address to be accessed This instruction writes 32 bit data with the eight high order bits set to 0 in the memory 2 Extension 1 ext immi3 ld a rb rs memo
197. lue smaller than the minimum value 0x0000 representable by an unsigned 16 bit integer V bit 2 OVerflow This bit indicates that an overflow or underflow occurred in an arithmetic operation More specifically this bit is set to 1 when in an add or subtract instruction in which the result of operation is handled as a signed 16 bit integer the execution of the instruction resulted in an overflow or underflow or is reset to 0 when the result of the add or subtract operation is within the range of values representable by a signed 16 bit integer This flag is also reset to 0 by executing a logical operation instruction 2 2 EPSON 51 17 FAMILY 51 17 CORE MANUAL 2 REGISTERS The V flag is set under the following conditions 1 When negative integers are added together the operation produced a 0 positive in the sign bit most sig nificant bit of the result 2 When positive integers are added together the operation resulted in a 1 negative in the sign bit most sig nificant bit of the result 3 When a negative integer is subtracted from a positive integer the operation resulted in producing a 1 nega tive in the sign bit most significant bit of the result 4 When a positive integer is subtracted from a negative integer the operation resulted in producing a 0 positive in the sign bit most significant bit of the result Z bit 1 Zero This bit indicates that an operation resulted in 0 More specifically this bit is
198. ly For the usable instructions refer to the instruction list in the Appendix 7 46 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS jrult sign7 jrult d sign7 Conditional PC relative jump for judgment of unsigned operation results Standard pe pe 2 sign7 x 2 if C is true Extension 1 pc lt pc 2 sign21 if C is true Extension 2 pc pc 2 sign24 if C is true ETE 8 2765 1 00001100 0 sign7 jrult 0 0 0 0 1 1 0 0 1 sign jrult d Mode Signed PC relative CLK jrult Two cycles when not branched Three cycles when branched jrult d Two cycles 1 Standard jrult sign7 jrult sign8 sign7 sign8 7 1 sign8 0 0 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met C flag 1 e g A lt B has resulted by cmp The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jrult sign7 jrult sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574
199. m13 imm13 10 0 imm24 23 13 ext imm13 imm24 12 0 ld b memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the content of the rb register with the 24 bit immediate imm24 added comprises the memory address the byte data in which is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 The content of the rb register is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer ld b rd rb Load instruction with post increment option The memory address will be incremented after the data transfer has finished ld b rd rb Load instruction with post decrement option The memory address will be decremented after the data transfer has finished ld b rd rb Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 1 byte size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after
200. ment post decrement and pre decrement functions 2rd rb can be used rb ssp imm7 Stack byte general purpose register zero extended imm7 Memory byte general purpose register zero extended ld rd rs General purpose register 16 bits general purpose register rd sign7 Immediate general purpose register sign extended rb Memory 16 bits general purpose register rb Memory address post increment post decrement and pre decrement functions 2rd rb can be used rb ssp imm7 Stack 16 bits general purpose register imm7 Memory 16 bits general purpose register rb rs General purpose register 16 bits memory rb rs Memory address post increment post decrement and pre decrement functions rb rs can be used rb rs 5sp imm7 rs General purpose register 16 bits gt stack imm7 rs General purpose register 16 bits memory 14 General purpose register 24 bits general purpose register rd imm7 Immediate general purpose register zero extended Memory 32 bits general purpose register rb Memory address post increment post decrement and pre decrement functions 2rd rb can be used rb ssp imm7 Stack 32 bits general purpose register rd imm7 Memory 32 bits general purpose register rb r
201. mm20 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register 3 Extension 2 ext immi3 imm13 3 0 imm24 23 20 ext 1 13 imm24 19 7 14 rd sp imm7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of the SP with the 24 bit immediate imm24 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed LIN o 14 r0 sp 0x2 r0 amp sp 0x82 The SP and the displacement must specify a 32 bit boundary address two least significant bits 0 Specifying other address causes an address misaligned interrupt Note however that the data transfer is performed by setting the two least significant bits of the address to 0 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 65 7 DETAILS OF INSTRUCTIONS 14 erd imm7 Function 32 data transfer Standard 23 0 lt A imm7 23 0 ignored lt A imm7 31 24 Extension 1 rd 23 0 lt A imm20 23 0 ignored lt A imm20 31 24 Extension 2 rd 23 0 lt
202. mm24 23 20 ext imm13 imm24 19 7 call imm7 call imm24 imm7 imm24 6 0 The 24 bit destination address is set to the PC 4 Delayed branch d bit bit 7 1 calla d imm7 When calla d is specified the d bit bit 7 in the instruction code is set and the following instruction becomes a delayed slot instruction The delayed slot instruction is executed before branching to the subroutine Therefore the address PC 4 of the instruction that follows the delayed slot instruction is stored into the stack as the return address When the calla d instruction is executed interrupts cannot occur because traps are masked between the calla d and delayed slot instructions ext Oxlfff calla 0x0 Calls the subroutine that starts from address Oxfff80 When the calla d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 7 16 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS cmc nc rd rs 16 bit comparison with carry Standard rd 15 0 rs 15 0 Extension 1 rs 15 0 imm13 zero extended C Extension 2 rs 15 0 imm16
203. mmi3 imm13 2 0 imm16 15 13 ext immi3 1 16 12 0 not rd lt 11 16 All the bits of the 16 bit immediate imm16 are reversed and result is loaded into rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution not c Executed as not when the C flag is 1 or executed as nop when the flag is 0 not nc Executed as not when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed When rl 0 555555 not r0 r1 r0 Oxaaaaaa 1017 FAMILY 51 17 CORE MANUAL EPSON 7 97 7 DETAILS OF INSTRUCTIONS not sign7 Function 16 bit logical negation Standard rd 15 0 lt sign7 sign extended rd 23 16 lt 0 Extension 1 rd 15 0 lt sign16 rd 23 16 lt 0 Extension 2 Unusable 000 0005 8 7 6 5 4 3 2 1 0 1 0 1 0 1 1J 387 0 eo e Mode Src Immediate data signed Dst Register direct r0 0 r7 One cycle CD Standard not 1 7 rd lt sign7
204. n the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jrlt sign7 jrlt sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext 1 13 1 13 2 0 sign24 23 21 ext immi3 sign24 20 8 jrlt sign7 jrlt sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates 3 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrlt d sign7 For jr1t d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the jr1t d instruction and the next instruction so no interrupts occur cmp 0 1 r0 and r1 contain signed data jrlt 0 2 Skips the next instruction if r0 lt rl When the 3rlt d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instr
205. nal execution The c or nc suffix on the opcode specifies conditional execution add c Executed as add when the C flag is 1 or executed as nop when the flag is 0 add nc Executed as add when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 add r0 r0 r0 r0 2 ext 0x1 ext 1 add r1 r2 rl r2 Ox3fff 7 4 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS add rd Function Code Flag CLK Description 16 bit addition Standard rd 15 0 lt rd 15 0 imm7 zero extended rd 23 16 lt 0 Extension 1 rd 15 0 lt rd 15 0 imm16 4 23 16 lt 0 Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 rd 2 IL IE V 7 lelelolo Src Immediate data unsigned Dst Register direct rd r0 to r7 One cycle 1 Standard add rd imm7 rd 4 rd imm7 The 7 bit immediate imm7 is added to the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 imm13 8 0 imm16 15
206. nce in operation from the standard instruction without extension 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit included In this case extension of the immediate by the ext instruction cannot be performed 7 112 EPSON 51 17 FAMILY S1C17 CORE MANUAL Sub sub c sub nc 7 DETAILS OF INSTRUCTIONS Yrs Yrs Yrs 16 bit subtraction Standard rd 15 0 lt rd 15 0 rs 15 0 4 23 16 0 Extension 1 rd 15 0 lt rs 15 0 imm13 zero extended 23 16 lt 0 Extension 2 rd 15 0 lt rs 15 0 rd 23 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 00111 0 11 6 1 9 rs sub 0 0 1 1 1 0 rd 0 0 1 0 rs sub c 00111 0 1 0 rs sub nc IL E C V Z N e e e e sub sub c sub nc Src Register direct 2rs Sr0 to r7 Dst Register direct rd r0 to r7 One cycle 1 Standard sub srs rd amp rd rs The content of the rs register is subtracted from the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 sub srs rd rs immi3 The 13 bit immediate imm413 is subtracted from the rs register after being zero extended and the result is loaded into the rd register The operation is performe
207. nded imm7 imm20 6 0 The immediate data is extended into a 20 bit quantity by the ext instruction and it is loaded to the SP after being zero extended 3 Extension 2 ext immi3 imm24 23 20 ext 1 13 imm24 19 7 ld a 1 7 Sp imm24 imm7 imm24 6 0 The immediate data is extended into a 24 bit quantity by the ext instruction and it is loaded to the SP 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ext 0 8 14 5 0 0 Sp lt 0x400 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 69 7 DETAILS OF INSTRUCTIONS Id a erb rs Id a rb ers Id a erb ers Id a erb ers Code 32 bit data transfer Id a erb ers Standard Id a rb rs with post increment option A rb 23 0 lt rs 23 0 A rb 31 24 lt 0 rb 23 0 lt rb 23 0 4 Extension 1 A rb imm13 23 0 lt rs 23 0 imm13 31 24 lt 0 rb 23 0 lt rb 23 0 imm13 Extension 2 A rb imm24 23 0 lt rs 23 0 A rb imm24 31 24 lt 0 rb 23 0 lt rb 23 0 imm24 Standard Id a rb rs with post decrement option A rb 23 0 lt rs 23 0 A rb 31 24 lt 0 rb 23 0 lt rb 23 0 4 Extension 1 A rb imm13 23 0 lt rs 23 0 A rb imm13 31 24 lt 0 rb 23 0
208. ndicating bit length sign7 sign10 Signed immediate numerals indicating bit length 5 4 EPSON 51 17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET 5 2 Addressing Modes without ext extension The instruction set of the 51 17 Core has seven discrete addressing modes as described below The processor de termines the addressing mode according to the operand in each instruction before it accesses data 1 Immediate addressing 2 Register direct addressing 3 Register indirect addressing 4 Register indirect addressing with post increment post decrement pre decrement 5 Register indirect addressing with displacement 6 Signed PC relative addressing 7 PC absolute addressing 5 2 1 Immediate Addressing The immediate included in the instruction code that is indicated as immX unsigned immediate or signX signed immediate is used as the source data The immediate size specifiable in each instruction is indicated by a numeral in the symbol e g imm7 unsigned 7 bits sign7 signed 7 bits For signed immediates such as sign7 the most significant bit is the sign bit which is extended to 16 or 24 bits when the instruction is executed Example 1d r0 0x70 Load 16 bit data Before execution r0 After execution OxOOfffO The immediate sign7 can represent values in the range of 63 to 64 0b0111111 to 051000000 Except in the case of shift related instructions immediate data can be extended t
209. nemonic a register is specified by prefixing the register name with rs rsisa metasymbol indicating the general purpose register that holds the source data to be operated on or transferred The register is actually written as 5570 r1 or r7 rd rdis a metasymbol indicating the general purpose register that is the destination in which the result of op eration is to be stored or data is to be loaded The register is actually written as 0 r1 or r7 rb rbisa metasymbol indicating the general purpose register that holds the base address of memory to be ac cessed In this case the general purpose registers serve as an index register The register is actually written as r0 r1 or r7 with each register name enclosed in brackets 51 to denote register indi rect addressing In register indirect addressing the post increment decrement and pre decrement functions provided for continuous memory addresses can be used Post increment function Example 1 rb 1 1d srd brb 2 grb 2 The base address is incremented by an amount equal to the accessed size after the memory has been ac cessed Post decrement function Example 14 1 14 rd rb 2 rb rb 4 The base address is decremented by an amount equal to the accessed size after the memory has been ac cessed Pre decrement function Example 1d b rb rs 1 rb rb 1 2 1d b rb rs Th
210. ntain unsigned data jrugt 0 2 Skips the next instruction if r0 gt rl When the jrugt d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 45 7 DETAILS OF INSTRUCTIONS jrule sign7 jrule d sign7 CLK Conditional PC relative jump for judgment of unsigned operation results Standard pc pc 2 sign7 x 2 if Z C is true Extension 1 pc lt pc 2 sign21 if Z C is true Extension 2 pc lt pc 2 sign24 if Z is true 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 1 1 0 1 0 sign7 jrule 1 1 1 0 0 00 1 1 0 1 1 sign7 jrule d IL IE C V 7 Signed PC relative jrule Two cycles when not branched Three cycles when branched jrule d Two cycles 1 Standard jrule 81917 jrule sign8 sign7 sign8 7 1 sign8 0 20 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met Z flag or flag 1 e g lt B has resulted by cmp A B The sign7 specifies a word address in 1
211. o a maximum of 24 bits by a com bined use of the operand value and the ext instruction Example ext 1 13 1 ext 3 2 14 r0 imm7 Load 24 bit data 10 after execution 23 20 19 7 6 0 rO imm13 0 1 imm13 2 imm7 5 2 2 Register Direct Addressing The content of a specified register is used directly as the source data Furthermore if this addressing mode is speci fied as the destination for an instruction that loads the result in a register the result is loaded in this specified regis ter The instructions that have the following symbols as the operand are executed in this addressing mode rs rsisa metasymbol indicating the general purpose register that holds the source data to be operated on transferred The register is actually written as r0 r1 or r7 rd rdisa metasymbol indicating the general purpose register that is the destination for the result of operation The register is actually written as r0 r1 r7 Depending on the instruction it will also be used as the source data Special register names are written as follows Stack pointer Program counter Spc The register names are always prefixed by to discriminate them from symbol names label names and the like 1017 FAMILY 51 17 CORE MANUAL EPSON 5 5 5 INSTRUCTION SET 5 2 3 Register Indirect Addressing In this mode memory is accessed indirectly by specifying a general purpose regis
212. on This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ld a r0 0x3f rO 0x00003f 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 67 7 DETAILS OF INSTRUCTIONS 14 9esp rs Function 24 bit data transfer Standard 8 23 2 lt rs 23 2 Extension 1 Unusable Extension 2 Unusable 000000 00005 556 IL IE C V Z N 001111 rs 1 Mode Src Register direct rs r0 to r7 Dst Register direct One cycle The content of the rs register 24 bit data is transferred to the SP ENIM espero sp lt ro 7 68 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS Id a Sp imm7 Function Code Flag CLK Description 24 bit data transfer Standard sp 6 2 lt imm7 6 2 sp 23 7 lt 0 Extension 1 sp 19 2 lt imm20 19 2 sp 23 20 lt 0 Extension 2 sp 23 2 lt imm24 23 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IL IE C V Z N Src Immediate data unsigned Dst Register direct sp One cycle 1 Standard ld a 1 7 Sp lt imm7 zero extended The 7 bit immediate imm7 is loaded to the SP after being zero extended 2 Extension 1 ext immi3 619 20 19 7 ld a 1 7 Sp lt imm20 zero exte
213. on cannot be performed 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 109 7 DETAILS OF INSTRUCTIONS slp Function SLEEP Standard Place the processor in SLEEP mode Extension 1 Unusable Extension 2 Unusable 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 0 0 0 0 0 0 0100010000 IL IE 7 Six cycles Places the processor in SLEEP mode for power saving Program execution is halted at the same time that the S1C17 Core executes the s1p instruction and the processor enters SLEEP mode SLEEP mode commonly turns off the SICI7 Core and on chip peripheral circuit operations thereby it significantly reduces the current consumption in comparison to HALT mode Initial reset is one cause that can bring the processor out of SLEEP mode Other causes depend on the implementation of the clock control circuit outside the SIC17 Core Initial reset maskable external interrupts NMI and debug interrupts are commonly used for canceling SLEEP mode The interrupt enable disable status set in the processor does not affect the cancellation of SLEEP mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel SLEEP mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller depending on the implementation are set to disable interrupts When the processor is taken out of SLEEP mode using an interrupt that has been enabled by the inter
214. on may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 xor r0 r0 r o 2 ext 0x1 ext Oxlfff xor r1 r2 rl r2 Ox3fff 7 120 EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS xor rd sign7 16 bit exclusive OR Standard rd 15 0 lt rd 15 0 sign7 sign extended rd 23 16 lt 0 Extension 1 rd 15 0 lt rd 15 0 signl6 rd 23 16 lt 0 Extension 2 Unusable ETE 005000 2 00095 8 2765 4 2 1 1 1 0101 0 sign IL IE C V 7 0 Mode Src Immediate data signed Dst Register direct rd r0 to r7 One cycle 1 Standard xor rd sign7 rd lt rd sign7 The content of the rd register and the sign extended 7 bit immediate sign7 are exclusively ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 1 13 8 0 19 16 15 7 xor rd sign7 rd amp rd signl6 sign7 16 6 0 The content of the rd register and the 16 bit immediate sign 6 are exclusively and result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0
215. onditional jump Branch condition 12 amp V jrgt d Delayed branching possible jrge sign7 PC relative conditional jump Branch condition N V jrge d Delayed branching possible jrit 51917 PC relative conditional jump Branch condition N V jrlt d Delayed branching possible jrie sign7 PC relative conditional jump Branch condition Z N V jrle d Delayed branching possible jrugt sign7 PC relative conditional jump Branch condition Z amp C jrugt d Delayed branching possible jruge sign7 PC relative conditional jump Branch condition C jruge d Delayed branching possible jrult sign7 PC relative conditional jump Branch condition C jrult d Delayed branching possible jrule sign7 PC relative conditional jump Branch condition Z C jrule d Delayed branching possible jreq sign7 PC relative conditional jump Branch condition Z jreq d Delayed branching possible jrne sign7 PC relative conditional jump Branch condition Z jrne d Delayed branching possible call signiO PC relative subroutine call call d rb Delayed call possible calla imm7 Absolute subroutine call calla d rb Delayed call possible ret Return from subroutine ret d Delayed return possible int imm5 Software interrupt intl 5 imm3 Software interrupt with interrupt level setting reti Return from interrupt handling reti d Delayed call possible brk Debug interrupt retd Return from debug processing System control nop No operation halt HALT mode slp SLEEP mode ei Enable inte
216. ontent of the rb register with the 24 bit immediate imm24 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register The content of the rb register is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer 14 rd rb Load instruction with post increment option The memory address will be incremented after the data transfer has finished 14 rd rb Load instruction with post decrement option The memory address will be decremented after the data transfer has finished ld a rd rb Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement sizes are listed below When no ext is used as in 1 shown above 4 32 bit size When one ext is used as in 2 shown above imm13 When two ext are used as in 3 shown above imm24 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed The rb register and the displacement must specify a 32 bit boundary address two least significant bits 2 0 Specifying oth
217. ory 2 Extension 1 ext immi3 ld a sp rs memory address sp imm13 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rs register is transferred to the address indicated by the content of the SP with the 13 bit immediate imm 3 added The content of the SP is not altered EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS 3 Extension 2 ext 1 13 imm13 10 0 imm24 23 13 ext 1 13 imm24 12 0 ld a sp rs memory address imm24 The addressing mode changes to register indirect addressing with displacement so the content of the rs register is transferred to the address indicated by the content of the SP with the 24 bit immediate imm24 added The content of the SP is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the SP This allows the program to simply perform continuous data transfer 14 sp rs Load instruction with post increment option The SP will be incremented after the data transfer has finished oo rs Load instruction with post decrement option The SP will be decremented after the data transfer has finished ld a sp ld a sp rs Load instruction with pre decrement option The SP will be decremented before starting the data transfer The address increment decrement sizes are listed below
218. other general purposes The contents of all of these registers are handled as 24 bit data or addresses 8 or 16 bit data can be sign or zero extended to a 24 bit quantity when it is loaded into one of these registers using a load instruction or a conversion instruction When these registers are used for address refer ences 24 bit memory space can be accessed directly At initial reset the contents of the general purpose registers are set to 0 may be indeterminate without initialization depending on the configuration 2 2 Program Counter PC Symbol Register name Size R W Initial value PC Program Counter 24 bits R Reset vector The Program Counter hereinafter referred to as the is a 24 bit counter for holding the address of an instruc tion to be executed More specifically the PC value indicates the address of the next instruction to be executed As the instructions in the 51 17 Core are fixed at 16 bits in length the LSB bit 0 of the PC is always 0 Although the S1C17 Core allows PC to be referenced in a program the user cannot alter it Note however that the value actually loaded into the register when a 1d a 5 instruction can be executed as a delayed in struction is executed is the value for the 1d instruction 2 At an initial reset the reset vector address written at the top of vector table indicated by TTBR is loaded into the PC and the processor starts exec
219. re used to control the system nop Only increments the PC with no other operations performed halt Places the processor in HALT mode 1 Places processor in SLEEP mode 1 Enables interrupts di Disables interrupts For details on HALT and SLEEP modes refer to Section 6 4 Power Down Mode and the Technical Manual for each S1C17 model For details on the interrupt control refer to Section 6 3 Interrupts 5 22 EPSON 51 17 FAMILY S1C17 CORE MANUAL 5 INSTRUCTION SET 5 10 Conversion Instructions The 8 16 24 32 data conversion instructions listed below are provided for supporting C compiler cv ab rd rs Converts Byte data 8 bits into 24 bit data with sign extended 23 8 7 0 rs S Byte 23 8 7 0 8 bits cv as Converts 16 data into 24 bit data with sign extended 23 16 15 0 rs X Si Word 23 16 15 0 rdlSSSSSSSSIS 16 bits cv al rd rs Extracts the high order 8 bits to convert 32 bit data into 24 bit data 23 8 7 0 rs X 8 bits Y 23 16 15 0 rd 8 bits Unchanged cv la rd rs Extracts the high order 8 bits to convert 24 bit data into 32 bit data 23 16 15 0 rs 8 bits X l Y 23 8 7 0 rdj0000000000000000 8 bits cv ls rd rs Extends the sign to convert 16 bit data into 32 bit data 23 16 15 0 rs X S Word l Y 23 16 15
220. ret instruction which is a return instruction for the 11 and 1 instructions loads the saved return address from the stack into the PC as it terminates the subroutine Therefore the value of the SP when the ret instruction is executed must be the same as when the subroutine was executed 1 one that indicates the return address The reti instruction is a return instruction for the interrupt handler routine Since the PSR is saved to the stack along with the return address in interrupt handling the content of the PSR must be restored from the stack using the reti instruction In the reti instruction the PC and the PSR are read out of the stack in that order As in the case of the ret instruction the value of the SP when the reti instruction is executed must be the same as when the subroutine was executed 7 Debug interrupts The brk and retd instructions are used to call a debug interrupt handler routine and to return from that rou tine Since these instructions are basically provided for the debug firmware please do not use them in applica tion programs For details on the functionality of these instructions refer to Section 6 5 Debug Circuit 5 20 EPSON 1C17 FAMILY 51 17 CORE MANUAL 5 INSTRUCTION SET 5 8 2 Delayed Branch Instructions The S1C17 Core uses pipelined instruction processing in which instructions are executed while other instructions are being fetched In a branch instruction because the instruct
221. rrupts di Disable interrupts Coprocessor control 1d cw Transfer data to coprocessor rd imm7 14 rd rs Transfer data to coprocessor and get results and flag statuses rd imm7 ld cf rd rs Transfer data to coprocessor and get flag statuses rd imm7 The 1d a instruction accesses memories in 32 bit length During data transfer from a register to a memory the 32 bit data in which the eight high order bits are set to 0 is written to the memory During reading from a memo ry the eight high order bits of the read data are ignored 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 3 5 INSTRUCTION SET The symbols in the above table each have meanings specified below Table 5 1 2 Symbol Meanings Symbol Description General purpose register source General purpose register destination 5 grb Memory addressed by general purpose register srb Memory addressed by general purpose register with address post incremented srb Memory addressed by general purpose register with address post decremented rb Memory addressed by general purpose register with address pre decremented 5 Stack pointer ssp ssp imm7 Stack Stack with address post incremented sp Stack with address post decremented 158 1 Stack with address pre decremented imm3 imm5 imm7 imm13 Unsigned immediate numerals i
222. rs register value as follows rs 0 3 0 3 bits rs 4 7 4 bits rs 8 or more 8 bits The sign bit is copied to bit 15 of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 23 16 15 0 rd register 5 gt L Sign bit after execution 00000000 s s M c 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit included 7 104 EPSON 51 17 FAMILY S1C17 CORE MANUAL sa erd imm7 Arithmetic shift to the right Standard Shift the content of rd to right as many bits as specified by imm7 0 3 4 or 8 bits MSB lt MSB sign bit Extension 1 imm7 is Extension 2 imm7 is extended to imm20 extended to imm24 8 7 6 5 4 2 1 Mode Src Immediate unsigned Dst Register direct rd ro to r7 One cycle 1 Standard The rd register is shifted as shown in the diagram below 7 DETAILS OF INSTRUCTIONS The number of bits to be shifted is specified by the 7 bit immediate imm7 as follows imm7 0 3 imm7 4 7 0 3 bits 4 bits 8 more 8 bits The sign bit is copied to most significant of rd register The operation is performed in 16 bit siz
223. rs sub a c 0 0110 0 0 1 1 0 rs sub a nc Mode Src Register direct 2rs r0 to r7 Dst Register direct rd r0 to r7 One cycle CD Standard sub a rd brs rd amp rd rs The content of the rs register is subtracted from the rd register 2 Extension 1 ext imm13 sub a rd rs rd rs immi3 The 13 bit immediate imm43 is subtracted from the content of the rs register after being zero extended and the result is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 10 0 imm24 23 13 ext 1 13 imm24 12 0 sub a rs rd amp rs imm24 The 24 bit immediate imm24 is subtracted from the content of the rs register and the result is loaded into the rd register The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution sub a c Executed as sub a when the C flag is or executed as nop when the flag is 0 sub a nc Executed as sub a when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 sub a r0 r0 r0 r0 2
224. ructions are executed the program directly branches to the address speci fied with the imm7 or rb register value by loading the value to the PC Also this addressing mode is used for the int and 1151 instructions that execute interrupt handler routines Example int 0x03 Executes the interrupt handler of vector No 3 TTBR Oxc 1017 FAMILY 51 17 CORE MANUAL EPSON 5 7 5 INSTRUCTION SET 5 3 Addressing Modes with ext The immediate specifiable in 16 bit fixed length instruction code is specified in a bit field of a 7 or 10 bit length depending on the instruction used The ext instructions are used to extend the size of this immediate The ext instructions are used in combination with data transfer arithmetic logic or branch instructions and is placed directly before the instruction whose immediate needs to be extended The instruction is expressed in the form ext imm13 in which the immediate size extendable by one ext instruction is 13 bits and up to two ext instructions can be written in succession to extend the immediate further The ext instructions are effective only for the instructions for which the immediate extension written directly after ext is possible and have no effect for all other instructions When three or more ext instructions have been de scribed sequentially the last two are effective and others are ignored When an instruction which does not support the extension in the ext instruction follows an ext the ext
225. ruge 1 1 1 0 0 0 0 10 1 1 1 sign7 jruge d IL E C V 7 Signed PC relative jruge Two cycles when not branched Three cycles when branched jruge d Two cycles 1 Standard jruge sign7 jruge sign8 sign7 sign8 7 1 sign8 0 20 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met C flag 0 e g gt B has resulted by The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jruge sign7 jruge sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext 110013 imm13 2 0 sign24 23 21 ext imm13 sign24 20 8 jruge sign7 jruge sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates imm13 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jruge d sign7 For
226. rugt 7 45 jrugt d 1 7 45 jrule SIQh f adiit Rp bere ecce d cef ele fees ea dette e 7 46 jrule d 7 46 jrult Jj pe 7 47 jrult d 7 47 Id OF 7 48 Id POU 7 49 Id VOU m 7 49 Id 2010 256 7 49 Id 9010 ececsaisacasccascevbeoasnsssdsednesdescssianesacsadaseduneesdspeasesnasedsanenadapeahesass satsenseabascsaassanades 7 49 Id 9010 VoSP AMINA 7 51 Id TI 7 52 Id m A 7 53 Id ET M 7 54 Id E e ales 7 54 Id 68016 eas a 7 54 Id ODS 7 54 Id Dosp Imm rS anane E E N AE E E EEE 7 56 Id 7 57 Id a PoC ss 7 58 7 59 9010 VOSD s 7 60 o E SQUID ERI 7 61 Id a 2010 Por iii rt
227. rupt controller and IE flag the corresponding interrupt handler routine is executed Therefore when the interrupt handler routine is terminated by the reti instruction the processor returns to the instruction next to slp When the interrupt has been disabled the processor restarts the program from the instruction next to slp after the processor is taken out of SLEEP mode Refer to the technical manual of each model for details of SLEEP mode slp The processor is placed in SLEEP mode 7 110 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS sr rd rs Logical shift to the right Standard Shift the content of rd to right as many bits as specified by rs 0 3 4 or 8 bits MSB lt 0 Extension 1 Unusable Extension 2 Unusable 8 7 6 4 2 1 0 0 1 0 I I 1 1 0 0 rs 0 7 o ole Mode Src Register direct 2rs r0 to r7 Dst Register direct 2rd r0 to r7 One cycle 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the rs register value as follows rs 0 3 0 3 bits rs 4 7 4 bits rs 8 or more 8 bits Data 0 is placed in the bit 15 of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 23 16 15 0 rd register gt N gt Y after
228. ry address rb immi3 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rs register is transferred to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered EPSON 1C17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS 3 Extension 2 ext 1 13 imm13 10 0 imm24 23 13 ext 1 13 imm24 12 0 ld a rb rs memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the content of the rs register is transferred to the address indicated by the content of the rb register with the 24 bit immediate imm24 added The content of the rb register is not altered 4 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer 14 rb rs Load instruction with post increment option The memory address will be incremented after the data transfer has finished X ld a rb rs Load instruction with post decrement option The memory address will be decremented after the data transfer has finished ld a rb rs Load instruction with pre decrement option The memory address will be decremented before starting the data transfer The address increment decrement s
229. s 0 The range of addresses to which jumped is PC 126 to PC 128 jpr 19 10 Functionas jpr signll1 signll sign10 0 For j pr instruction that is used singly a signed 10 bit displacement sign 0 can be specified 10 sign10 0 PC Current address 0 v PC Branch destination address 0 The range of addresses to which jumped is 2 046 to PC 2 048 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 17 5 INSTRUCTION SET When extended by one ext instruction ext 1013 jr 810917 Functions as jr 61911217 sign21 imm13 sign7 0 The imm13 specified by the ext instruction is extended as the 13 high order bits sign21 23 2120 8 7 1 0 9 21 5 8 515 imm13 sign7 0 ENIMS _ 2 Current address 0 v PC Branch destination address 0 The range of addresses to which jumped is PC 1 048 574 to 1 048 576 ext 1013 signlO Functionsas jpr sign24 sign24 imm13 sign10 0 The imm13 specified by the ext instruction is extended as the 13 high order bits of sign24 23 11 10 1 0 sign24 5 1113 sign10 0 2 PC Current address 0 v PC Branch destination address 0 The range of addresses to which jumped is PC 8 388 606 to PC 8 388 608 When extended by two ext instructions ext 1013 ext 3 jr 810917 Functions as jr 819124
230. s General purpose register 32 bits zero extended memory rb rs Memory address post increment post decrement and pre decrement functions 256 rs can be used rb rs sp imm7 rs General purpose register 32 bits zero extended stack imm7 rs General purpose register 32 bits zero extended memory SP general purpose register general purpose register sp Stack 32 bits general purpose register Stack pointer post increment post decrement pre decrement functions sp be used 5 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 1 5 INSTRUCTION SET Classification Mnemonic Function Data transfer 1 spl rs General purpose register 32 bits zero extended stack Stack pointer post increment post decrement and pre decrement functions can 5sp rs be used spl rs ssp rs General purpose register 24 bits gt SP sp imm7 Immediate SP Integer arithmetic add rd rs 16 bit addition between general purpose registers operation add c Supports conditional execution c executed if C 1 nc executed if C 0 add nc add rd imm7 16 bit addition of general purpose register and immediate add
231. s limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 15 7 DETAILS OF INSTRUCTIONS calla imm7 calla d imm7 PC absolute subroutine Standard sp lt sp 4 A sp lt pc 2 pc imm7 Extension 1 sp lt sp 4 A sp lt 2 pe lt imm20 Extension 2 sp lt sp 4 A sp lt 2 lt imm24 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000010 1 0 imm7 calla 1 1 1 0 0 0 00 10 1 1 imm7 calla d E C V Z PC absolute calla Four cycles calla d Three cycles 1 Standard calla imm7 Stores the address of the following instruction into the stack then sets the 7 bit immediate imm7 to the PC for calling subroutine that starts from the address set to the PC The LSB of the imm7 is invalid and is always handled as 0 When the ret instruction is executed in the subroutine the program flow returns to the instruction following the calla instruction 2 Extension 1 ext 1 13 1 20 19 7 call imm7 i Call imm20 imm7 imm20 6 0 The ext instruction extends the destination address into 20 bits using its 13 bit immediate imm13 The 20 bit destination address is set to the PC 3 Extension 2 ext imm13 imm13 3 0 i
232. s sign extended into 16 bits prior to the operation The operation is performed in 16 bit size It does not change the contents of the rd register 2 Extension 1 ext immi3 1 13 8 0 19 16 15 7 cme rd sign7 rd 810016 C sign7 signl6 6 0 Subtracts the contents of the signed 16 bit immediate sign 6 and C carry flag from the contents of the rd register and sets or resets the flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the contents of the rd register 3 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after branch instruction with the 4 bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 cmc r0 0x7f Changes the flags according to the results of X0 OxTf C 2 ext Oxlff cmc r1 0x7f Changes the flags according to the results of rl Oxffff C 7 18 EPSON 51 17 FAMILY S1C17 CORE MANUAL cmp 7 DETAILS OF INSTRUCTIONS rs Yrs cmp nc rd rs 16 bit comparison Standard rd 15 0 rs 15 0 Extension 1 rs 15 0 imm13 zero extended Extension 2 rs 15 0 0050050000095 8 7 6 4 2 1 oo01111 1 0 0 0 rs cmp oo01111 0 0 0 0 rs 90 0 1 1 1 1 01 0 0 75 IL IE C
233. set to 1 when the execution of a logical operation arithmetic operation or shift instruction resulted in 0 or is otherwise reset to 0 N bit 0 Negative This bit indicates a sign More specifically the most significant bit bit 15 of the result of a logical operation arithmetic operation or shift instruction is copied to this N flag 51 17 FAMILY 51 17 CORE MANUAL EPSON 2 3 2 REGISTERS 2 4 Stack Pointer SP Symbol Register name Size R W Initial value SP Stack Pointer 24 bits R W 0x000000 The Stack Pointer hereinafter referred to as the SP is a 24 bit register for holding the start address of the stack The stack is an area locatable at any place in the system RAM the start address of which is set in the SP during the initialization process The 2 low order bits of the SP are fixed to 0 and cannot be accessed for writing Therefore the addresses specifiable by the SP are those that lie on 32 bit boundaries 23 2 1 0 32 bit boundary address 0 0 Fixed read only Figure 2 4 1 Stack Pointer SP 2 4 1 About the Stack Area The size of an area usable as stack is limited according to the RAM size available for system and size of the area occupied by ordinary RAM data Care must be taken to prevent the stack and data area from overlapping Furthermore as the SP becomes 0x000000 when it is initialized upon reset last stack address 4 with 2 low order bits 0 mu
234. st be written to the SP in the beginning part of the initialization routine A load instruction may be used to write this address If an interrupt occurs before the stack is set up it is possible that the PC or PSR will be saved to an indeterminate location and normal operation of a program cannot be guaranteed To prevent such a problem NMIs nonmaskable interrupts that cannot be controlled in software are masked out in hardware until the SP is initialized 2 4 2 SP Operation at Subroutine Call Return A subroutine call instruction call or calla uses four bytes of the stack The call calla instruction saves the contents of the PC return address onto the stack before branching to a subroutine The saved address is restored into the PC by the ret instruction and the program is returned to the address next to that of the 11 11 in struction SP operation by the ca11 calla instruction 1 SP SP 4 2 PC gt SP Oxtfffff Oxffffff 7 0 7 0 SP gt 0x00 PC 23 16 PC 15 8 SP SP 4 7 0 Y Y 0x000000 0x000000 Figure 2 4 2 1 SP and Stack 1 2 4 EPSON 51 17 FAMILY 51 17 CORE MANUAL 2 REGISTERS SP operation by the ret instruction 1 SP PC 2 SP SP 4 Oxfffftt 7 0 T 0 SP SP 4 gt 0x00 0x00 PC 23 16 2 PC 23 16 PC 15 8 PC 15 8 SP PC 7 0 Y Y 0x000000 0x000000
235. ster after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext immi3 imm24 31 19 ext immi3 imm24 18 6 ld b rd sp imm7 memory address sp imm24 imm7 lt imm24 5 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of the SP with 24 bit immediate imm24 added comprises the memory address the byte data in which is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed ld b 0 1 r0 sp 0x81 sign extended 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 79 7 DETAILS OF INSTRUCTIONS Id b erd imm7 Function Signed byte data transfer H 8 265552 1 Standard Extension 1 rd 7 0 lt B imm20 rd 15 8 lt B imm20 7 rd 23 16 0 Extension 2 rd 7 0 lt B imm24 rd 15 8 lt B imm24 7 rd 23 16 0 rd 7 0 lt B imm7 rd 15 8 lt B imm7 7 rd 23 16 lt 0 1 0000 der IL IE V ZN Mode Src Immediate data unsigned Dst Register direct 4rd
236. structions rd rs imm16 23 16 15 0 rs X XX XX X X X Data 15 1312 0 Immediate imm13 2 imm13 2 0 23 16 15 0 00000000 Data imm16 51 17 FAMILY 51 17 CORE MANUAL EPSON 5 9 5 INSTRUCTION SET Extending to rs imm24 24 bit operation instructions To extend to rs imm24 enter two ext instructions directly before the target instruction Example ext immi3 1 ext immi3 2 add a rd rs If not extended rd rd rs When extended by two ext instructions rd rs imm24 23 0 rs Data 23 13 12 0 Immediate imm13 10 0 1 imm13 2 23 Y 0 rd Data imm24 5 3 3 Extension of Register Indirect Addressing Adding displacement to 15 51 Memory is accessed at the address derived by adding the immediate specified by an ext instruction to the ad dress that is indirectly referenced by rb Adding a 13 bit immediate Memory is accessed at the address derived by adding the 13 bit immediate specified by imm13 to the address specified by the rb register During address calculation imm13 is zero extended to 24 bit quantity Example ext imm13 ld b rd rb ld b rd rb imm13 23 0 rb Memory address pointer 23 13 12 0 ImmediatejO 0000000000 imm13 Adding a 24 bit immediate Memory is accessed at the address derived by adding the 24 bit immediate specified by 24 to the address specified by the rb re
237. t Register direct 2rd r0 to r7 One cycle 1 Standard and rd rs rd amp rd amp rs The content of the rs register and that of the rd register are logically AND ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext immi3 and rd rs rd rs immi3 The content of the rs register and zero extended 13 bit immediate imm413 are logically and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext immi3 imm13 2 0 16 15 13 ext immi3 imm16 12 0 and rd rs rd rs 16 The content of the rs register and the 16 bit immediate are logically AND ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies conditional execution and c Executed as and when the C flag is 1 or executed as nop when the flag is 0 and nc Executed as and when the C flag is 0 or executed as nop when the flag is 1 In this case the ext instruction can be used to extend the operand 5 Delayed slot instruction This instruction may be executed as a d
238. tb ld ub rd brb 0 01 00 0 rd 1 0 0 1 rb ld ub rd rb IL IE C V ZN Src Register indirect 35 r0 to r7 Dst Register direct 4rd r0 to r7 One cycle two cycles when the ext instruction or an increment decrement option is used 1 Standard ld ub rd rb memory address rb The byte data in the specified memory location is transferred to the rd register after being zero extended to 16 bits The rb register contains the memory address to be accessed The eight high order bits of the rd register are set to 0 2 Extension 1 ext imm13 ld ub rd rb memory address rb immi3 The ext instruction changes the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the byte data in which is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 The content of the rb register is not altered EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS 3 Extension 2 ext immi3 imm13 10 0 imm24 23 13 ext 1 13 imm24 12 0 ld ub rb memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the content of the rb register with the 24 bit immediate imm24 added comprises the memory address the byte data in
239. te 1 15 8 7 0 5 16 EPSON 51 17 FAMILY S1C17 CORE MANUAL 5 INSTRUCTION SET 5 8 Branch and Delayed Branch Instructions 5 8 1 Types of Branch Instructions 1 PC relative jump instructions PC relative jump instructions include the following jr sign7 jpr 1 10 jer PC relative jump instructions are provided for relocatable programming so that the program branches to the ad dress calculated as PC 2 the next address of the branch instruction signed displacement specified by the operand The number of instruction steps to the jump address is specified for sign7 10 or rb However since the instruc tion length in the S1C17 Core is fixed to 16 bits the value of sign7 10 is doubled to become a word address in 16 bit units Therefore the displacement actually added to the PC is a signed 8 bit 11 bit quantity derived by doubling sign7 0 least significant bit always 0 When the rb register is used to specify the displacement the register contents are added to the PC without doubling The specifiable displacement can be extended by the ext instruction as shown below For branch instructions used singly jr sign7 Functions as jr 819187 sign sign7 0 For j x instructions that are used singly a signed 7 bit displacement sign7 can be specified 28 8 7 1 0 signBiSSSSSSSSSSSSSSS S S sign7 0 2 PC Current address 0 Branch destination addres
240. ter stack pointer that holds the address needed This addressing mode is used only for load instructions that have rb 5 as the op erand Actually this general purpose register is written as r0 r1 sr7 sp with the register name enclosed in brackets 5117 The processor refers to the content of a specified register as the base address and transfers data in the format that is determined by the type of load instruction Examples Memory Register ld b sr sri Load 8 bit data ld sro r1 Load 16 bit data 14 r0 r1 Load 24 bit data Register Memory ld b r1 rO0 Store 8 bit data ld r1 rO Store 16 bit data ld a r1 rO Store 24 bit data In this example the address indicated by r1 is the memory address from or to which data is to be trans ferred In 16 bit and 24 bit transfers the base address that is set in a register must be on a 16 bit boundary least significant address bit 0 or 32 bit boundary 2 low order address bits 0 respectively Otherwise an address misaligned interrupt will be generated 5 2 4 Register Indirect Addressing with Post increment decrement or Pre decrement As in register indirect addressing the memory location to be accessed is specified indirectly by a general purpose register or the stack pointer In this addressing mode the base address held in a specified register is incremented decremented by an amount equal to the
241. ter 7 bit immediate imm7 to coprocessor and gets operation results by the coprocessor The results are loaded to the rd register and the C V Z and N flags in the PSR 2 Extension 1 ext immi3 imm20 19 7 ld ca 7 doutl data imm20 imm7 imm20 6 0 The ext instruction extends the immediate to a 20 bit quantity As a result data set in the rd register and 20 bit immediate imm20 are transferred to the coprocessor and the results are loaded to the rd register and the C V Z and N flags in the PSR 3 Extension 2 ext imm13 imm24 31 19 ext imm13 imm24 18 6 ld ca 7 doutl data imm24 imm7 lt imm24 5 0 The two ext instructions extend the displacement to a 24 bit quantity As a result data set in the rd register and 24 bit immediate imm24 are transferred to the coprocessor and the results are loaded to the rd register and the C V Z and N flags in the PSR 4 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed 7 86 EPSON 51 17 FAMILY 51 17 CORE MANUAL Id cf rd rs Transfer data to the coprocessor and get the flag status co_dout0 lt rd co lt rs psr C V Z lt cvzn Standard Extension 1 Unusable Extension 2 Unusable 9 8
242. the j ruge d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the j ruge instruction and the next instruction so no interrupts occur 3 0 3 1 r0 and rl contain unsigned data jruge 0 2 Skips the next instruction if r0 2 r1 When the jruge d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 7 44 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS jrugt sign7 jrugt d sign7 Conditional PC relative jump for judgment of unsigned operation results Standard pe pe 2 sign7 x 2 if Z amp C is true Extension 1 pc pc 2 sign21 if Z amp C is true Extension 2 pc pc 2 sign24 if Z amp C is true ETE 8 2765 4 2 1 0 0 0 0 1 0 1 0 O sign 0 0 0 0 1 0 1 0 I sign jrugt d Mode Signed PC relative CLK jrugt Two cycles when not branched Three cycles when branched jrugt d Two cycles 1 Standard jrugt sign7 jrugt sign8 sign7 sign8 7 1 sign8 0 0 If the condition below has been met this
243. to PC 1 048 576 3 Extension 2 ext 3 1 13 2 0 sign24 23 21 ext immi3 sign24 20 8 jrult 81907 jrult sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displacement to be added to the PC PC 2 into signed 24 bits using their 13 bit immediates 77173 x 2 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 4 Delayed branch d bit bit 7 1 jrult d sign7 For the jrult instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the rult d instruction and the next instruction so no interrupts occur Example 3 0 3 1 r0 and rl contain unsigned data jrult 0x2 Skips the next instruction if r0 lt rl When jrult d instruction delayed branch is used be careful to ensure that the next instruction is limited to those that can be used as a delayed slot instruction If any other instruction is executed the program may operate indeterminately For the usable instructions refer to the instruction list in the Appendix 51 17 FAMILY 51 17 CORE MANUAL EPSON 7 47 7 DETAILS OF INSTRUCTIONS Id rd rs Function 16 bit data transfer Standard rd 15 0 lt rs 15 0 rd 23 16 lt 0 Extension 1 Unusable Extension 2 Unusable Code 5 6 5 3 001010 0010 LT
244. transmit receive data register of the serial interface for the on chip debug monitor used to set transmit data and to store received data Default 0x00 S1C17 FAMILY S1C17 CORE MANUAL EPSON 6 13 6 FUNCTIONS THIS PAGE IS BLANK 6 14 EPSON 51 17 FAMILY S1C17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS 7 Details of Instructions This section explains all the instructions in alphabetical order Symbols in the instruction reference rd SIS 5 grb rb SSp sp Spc pc General purpose registers 7 or their contents used as the destination General purpose registers 7 or their contents used as the source General purpose registers RO R7 or their contents that hold the base address to be accessed in register indirect addressing Stack pointer SP or its content Program counter PC or its content The register field rd rs in the code contains a general purpose register number RO 05000 0b001 R7 Ob111 immX signX zN oRBRERB Unsigned immediate X bits in length The X contains a number representing bit length of the immediate Signed immediate X bits in length The X contains a number representing the bit length of the immediate Furthermore the most significant bit is handled as the sign bit Interrupt level field Interrupt enable flag Carry flag Overflow flag Zero flag Negative flag Indicates that the bit is not changed by instruct
245. ual data sizes are expressed as follows 8 bit data Byte orb 16 bit data Word W or w 24 bit data Address data A a Data sizes can be selected only in data transfer load instruction between one general purpose register and another In an 8 bit data transfer with a general purpose register as the destination the data is sign or zero extended to 16 bits before being loaded into the register Whether the data will be sign or zero extended is determined by the load instruction used In a 16 bit or 8 bit data transfer using a general purpose register as the source the data to be transferred is stored in the low order 16 bits or the low order 8 bits of the source register The data transfer sizes and types are described below 3 1 1 Unsigned 8 Bit Transfer Register Register Example 1d ub rd rs 23 16 15 8 7 0 9615 Byte Y d 23 16 15 8 7 0 rd 0 000000000000000 Byte Figure 3 1 1 1 Unsigned 8 Bit Transfer Register Register Bits 23 8 in the destination register are set to 0x0000 3 1 2 Signed 8 Bit Transfer Register Register Example 1d b srd rs 23 16 15 8 7 0 rs X X 15 Byte 0 1 23 16 15 8 7 0 100000000 55555555 15 Byte Figure 3 1 2 1 Signed 8 Bit Transfer Register Register Bits 15 8 in the destination register are sign extended and bits 23 16 are set to 0 00 51 17 FAMILY 51 17 CORE MANUAL EPSO
246. uction list in the Appendix 7 42 EPSON 51 17 FAMILY 51 17 CORE MANUAL 7 DETAILS OF INSTRUCTIONS 5 7 jrne d sign7 CLK Conditional PC relative jump Standard pe pe 2 sign7 x 2 if Z is true Extension 1 pc lt pc 2 sign2 if Z is true Extension 2 pc pc 2 sign24 if Z is true 15 14 13 12 1 9 8 7 6 5 4 3 2 0 0 0 0 1 1 1 1 0 sign jrne 0 0 0 0 1 1 1 1 1 sign _ jrne d IL IE C V Z N Signed PC relative jrne Two cycles when not branched Three cycles when branched jrne d Two cycles 1 Standard jrne sign7 jrne sign8 sign7 sign8 7 1 519 8 0 0 If the condition below has been met this instruction doubles the signed 7 bit immediate sign7 and adds it to the PC PC 2 for branching the program flow to the address It does not branch if the condition has not been met Z flag 0 e g B has resulted by cmp A B The sign7 specifies a word address in 16 bit units The sign7 x2 allows branches within the range of PC 126 to PC 128 2 Extension 1 ext imm13 sign21 20 8 jrne sign7 jrne sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm13 1 13 2 0 sign2
247. up instruction processing by executing one instruction while fetching another In the 3 stage pipeline each instruction is processed in three stages with processing of instructions occurring in parallel for faster instruction execution Basic instruction stages Instruction fetch Instruction decode Instruction execution Memory access Register write Hereinafter each stage is represented by the following symbols F for Fetch Instruction fetch D for Decode Instruction decode E for Execute Instruction execution memory access register write Pipelined operation Clock PC F D E 2 F D 4 F D E Figure 6 2 1 1 Pipelined Operation Note The pipelined operation shown above uses the internal memory If external memory or low speed external devices are used one or more wait cycles may be inserted depending on the devices used with the E stage kept waiting 6 2 EPSON 1C17 FAMILY 51 17 CORE MANUAL 6 2 2 Execution Cycles Flags 6 FUNCTIONS The following shows the number of cycles required for executing each instruction in a 1 cycle accessible memory connected to Harvard bus and the flag change status Depending on the model clock cycles spent by the external bus arbiter and wait cycles inherent in the external devices may be added Table 6 2 2 1 Number of Instruction Execution Cycles and Flag Status Classific
248. upt by the retd instruction the processor restores the saved data in order of the RO and the PC and PSR Neither hardware interrupts nor NMI interrupts are accepted during a debug interrupt 6 5 2 Resource Requirements and Debugging Tools The on chip debug function requires a 64 byte work area For the work area for debugging refer to the Technical Manual of each model Debugging is performed by connecting a serial ICE to the debug pins of the SIC17 Core and entering debug commands from the debugger being run on a personal computer The tools listed below are required for debugging e SICI7 Family Serial ICE S5U1C17001H SICI7 Family C Compiler Package 51 17 FAMILY 51 17 CORE MANUAL EPSON 6 11 6 FUNCTIONS 6 5 3 Registers for Debugging The reserved core I O area contains debug registers described below OxFFFF90 Debug RAM Base Register DBRAM Register name Debug RAM base register Address Function Setting Init R W Remarks FFFF90 031 24 Unused fixed at 0 0 0 0x0 R L D23 DBRAM23 Debug RAM base address 0 0 Initial value is set in DBRAM 5 0 is fixed at 0x0 64 byte units the C17 RTL define DO DBRAMO DBRAM BASE D 23 0 DBRAN 23 0 Debug RAM Base Address Bits This is a read only register that contains the start address of a work area 64 bytes for debugging OxFFFFAO Debug Control Register DCR Register
249. uting a program from the address indicated by the PC 23 10 Effective address 0 Figure 2 2 1 Program Counter PC 51 17 FAMILY 51 17 CORE MANUAL EPSON 2 1 2 REGISTERS 2 3 Processor Status Register PSR Symbol Register name Size R W Initial value PSR Processor Status Register 8 bits R W 0x00 The Processor Status Register hereinafter referred to as the PSR is an 8 bit register for storing the internal status of the processor The PSR stores the internal status of the processor when the status has been changed by instruction execution It is referenced in arithmetic operations or branch instructions and therefore constitutes an important internal status in program composition The PSR does not allow the program to directly alter its contents except for the IE bit As the PSR affects program execution whenever an interrupt occurs the PSR is saved to the stack except for de bug interrupts to maintain value The IE flag bit 4 in it is cleared to 0 The reti instruction is used to return from interrupt handling and the PSR value is restored from the stack at the same time 7 6 5 4 3 2 1 0 PsR 120 i c v z w J Initialvalue 0 0 0 0 0 0 0 0 Figure 2 3 1 Processor Status Register PSR IL 2 0 bits 7 5 Interrupt Level These bits indicate the priority levels of the processor interrupts Maskable interrupt requests are accepted only when their priority levels are higher
250. y is to be accessed in 16 bit or 32 bit units the specified base address must be on a 16 bit boundary least significant address bit 0 or 32 bit boundary 2 low order address bits 00 respectively Unless this condition is satisfied an address misaligned interrupt is generated 31 24 23 16 15 8 7 0 8 bit data Byte 3 Byte 2 Byte 1 Byte 0 31 16 15 0 16 bit data Word 1 Word 0 31 24 23 0 32 bit data 0x00 Address data Figure 3 2 1 Data Format Little Endian Handling the eight high order bits during 32 bit accesses During writing the eight high order bits are written as 0 During reading from a memory the eight high order bits are ignored However the eight high order bits are effective as the PSR value only in the stack operation when an interrupt occurs The data transfer sizes and types are described below 3 2 EPSON 1C17 FAMILY 51 17 CORE MANUAL 3 DATA FORMATS 3 2 1 Unsigned 8 Bit Transfer Memory Register Example 1d ub rd rb 7 0 rb Byte 0 A oL 23 16 15 8 7 0 rdj00000000 00000000 Byte Figure 3 2 1 1 Unsigned 8 Bit Transfer Memory Register Bits 23 8 in the destination register are set to 0x0000 3 2 2 Signed 8 Bit Transfer Memory Register Example 14 56 rb 7 0 196181 S 0 E Y I 1 23 16 15 87 0 00000000 55555555 5 Byte Figure 3 2 2 1 Signed 8 Bit Transfer

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