Model PCL-724 24 Bit Digital I/O Card
Contents
1. out j to port B gotoxy 34 8 printf 2x j portB inportb base 1 read back gotoxy 63 8 printf 22x portB if portB j printf M7 beep gotoxy 30 13 textattr 0x09 cprintf Port B readback error getch exit 1 quit to dos outportb base 2 j out j to port C gotoxy 34 10 printf 2x j portC inportb base 2 read back gotoxy 63 10 printf 2x portC if portC j printf M7 beep gotoxy 30 13 textattr 0x09 cprintf Port C readback error getch exit 1 quit to dos Programming PCL 724 EXAMPLE 2 BRK RR KK KK KK kk RR RRA RRA RRA KR This demo program demonstrates how to use the PCL 724 s interrupt function trapping a rising edge HARDWARE SETTING les Base address set at 0X2C0 Jl set at IRQ 2 J2 set at EN or PGM J3 set at RISING trigger T BRIAN CR EI I II EO OE E eO III RR A Y mss include lt dos h gt include lt stdio h gt include lt conio h gt new INT OAH ISR void interrupt alarm void char Port61_Old_Status char Port61 New Status int DelayTime 0x300 int Count 0 int La get original port 61H status and save it Port61 New Status Port61 Old Status inportb 0x61 set port 61h bitl 0 Port61 New Status amp Oxfd 1111 1101 in binary for Count 0 Count lt 0x300 Count2. 4 1 Programming Notes The PCL 724 s signal direction can be INPUT or OUTPUT from a software program However after you turn on or hardware reset your PC all of the PCL 724 s ports will automatically be configured as INPUT When the PCL 724 is programmed as an output port for the first time it will not output until you execute the first output instruction This action safeguards your external device from being damaged before it is initialized OUTPUT Enable From Data Bus gt External To Data Bus RD Figure 4 1 Signal Direction of PCL 724 1 The output driver is disabled high impedance when the port is set to INPUT or after RESET 2 The output data written to the port is latched in the OUTPUT DATA LATCH no matter the port is set as INPUT or OUTPUT 3 When the port is set as OUTPUT the input circuit is used as output status read back 4 The data in the OUTPUT DATA LATCH is in a random status after power on It must be initialized before setting the port to output direction Programming PCL 724 4 2 Programming Examples The PCL 724 is easily programmed and the following section lists some program examples All the program examples below have been fully tested on PC XT AT or compatible computers Note The following programs should be run under Turbo C version 1 5 or 2 0 EXAMPLE 1 F K K K K RRA kk RK RRA This demo program demonstrates how to use the read back function of the PCL 724
3. 1 1 Introduction The PCL 724 24 bit DIO card is a generalized 24 line parallel digital I O capability and emulates mode 0 of an 8255 programmable peripheral interface chip With its 50 pin OPTO 22 compatible connector the PCL 724 is especially suitable for SSR I O module control Additionally one line of the PCL 724 can be used to generate a hardware interrupt to your PC ADDRESS BASEH gt PORT A BASE gt PORT B BASE 2 gt PORT C BASE 3 gt CFG REG OPTO 22 CONNECTOR Figure 1 1 PCL 724 BLOCK DIAGRAM General Information PCL 724 1 2 Features 24 TTL digital I O lines 6 connectors each with 24 I O lines Emulates mode O of 8255 PPI Programmable interrupt handling OPTO 22 compatible 50 pin connector 1 3 Applications Industrial AC DC I O module monitoring and control Relay and switch monitoring and control Parallel data transfer Sensing the signals of TTL DTL CMOS logic Driving indicator LED s 1 4 Electrical Specifications Input signal Input logic high voltage 2 0 V 5 25 V Input logic low voltage 0 0 V 0 80 V High level input current 20 0 uA Low level input current 0 2 mA Output signal output logic high voltage 2 4 V min output logic low voltage 0 4 V max High level output current 15 0 mA Low level output current 24 0 mA PCL 724 General Information Transfer rate Typical 300 K bytes sec Maximum 500 K bytes sec Power consumption Typical p
4. remove the PCL 724 I O board while the power is ON as this may damage the plug in board computer or both Always ensure that the power has been turned OFF before proceeding with installation or removal The following diagram shows PCL 724 s switch and jumpers location jo A 8765432 JI J2 IRQ2 MER oo oo oo oo oo 4 sle J3 7 oo f mmo 0000000000000000000000000 0000000000000000000000000 Installation PCL 724 2 2 Base Address Setting The PCL 724 requires four consecutive address locations within your PC s I O space Some I O address locations will be occupied by internal I O and peripherals devices In order to avoid conflicts with these devices the PCL 724 address can be set by a 8 position DIP switch and placed anywhere in the IBM PC decoded external UO space Address can range from 200 to 3FF in hexdecimal though you should check with the IBM Standard Technical Reference Manual for possible conflicts with commonly installed peripherals The required SWITCH settings for the BASE addresses are specified below I O PORT SWITCH POSITION SW1 ADDRESSES 1 2 3 4 5 6 jl 8 HEXADECIMAL A8 A7 A6 A5 A4 A3 A2 200 203 0 0 0 0 0 0 0 X 2C0 2C3 0 1 1 0 0 0 0 x 3FC 3FF 1 1 1 1 1 1 1 X NOTE 0 ON 1 OFF 1 2 X means don t care 3 1 8are switch positions 4 A2through A9 correspond to address lines of the PC bus 5 means factory setting PCL 724 Installation 2 4 Interrupt Sett
5. DelayTime Port61 New Status 0x02 On Off bitl outportb 0x61 Port61 New Status for i 0 i lt DelayTime i outportb 0x61 Port6l Old Status outportb 0x20 0x20 send EOI to 8259 void main int IMR void interrupt Int_A_Old_Vector Int_A_Old_Vector getvect 0x0a get old int Oah ISR setvet OxOa alarm set new int Oah ISR Programming PCL 724 IMR inportb 0x21 get 8259 interrupt mask register initialization outportb 0x2c3 0x80 set Port A Port B and Port C all as output ports outportb 0x2c0 OxO Port A outportb 0x2cl OxO Port B outportb 0x2c2 0x0 PC 4 0 gt interrupt enable PCO O clrscr printf Press any key to generate a rising edge interrupt getch outportb 0x21 0xfb amp IMR set IRQ2 nonmasked printf n nPort C x inportb 0x2c2 generate a rising edge signal at PCO outportb 0x2c2 0x1 printf n nPort C x inportb 0x2c2 printf n npress any key to quit getch restore old INT OAH ISR setvect OxOa Int A Old Vector outportb Ox21 IMR restore 8259 interrupt mask set as INPUT to release IRQ2 line outportb 0x2c3 0x9b
6. Model PCL 724 24 Bit Digital I O Card PCL 724 24 BIT DIGITAL I O CARD USER S MANUAL This documentation is copyrighted 1993 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use nor for any infringements of rights of third parties which may result from its use PC LabCard is a trademark of Advantech Co Ltd IBM PC PC XT and PC AT are trademarks of International Business Machines Corporation OPTO 22 is a trademark of OPTO 22 Corporation Part No 2003724010 Rev A2 Printed in Taiwan Aug 1993 TABLE OF CONTENTS CHAPTER 1 GENERAL INFORMATION 1 1 Introduction 2cEeat fes eternal ecc i ap aed 2 1 3 Applications ok Ree ere wu eee 2 1 4 Specifications eee 2 CHAPTER 2 INSTALLATION esee 5 2 1 Initial Inspection eee 5 2 2 Base Address Setting 6 2 3 Interrupt Settings LL 7 CHAPTER 3 OPERATION nen 9 3 1 Configuration eenen 9 3 2 Interrupt Handling CHAPTER 4 PROGRAMMING 4 1 Programming Notes ene 13 4 2 Programming Examples ene 14 CHAPTER 1 GENERAL INFORMATION
7. ble lists all possible configured commands to configure 8255 in mode 0 8255 Mode O Configuration Table m PBO PB7 PCO PC3 w PC4 PC7 output output output output 83H input output output output output output 88H output input output output input output 8BH output 90H input 91H input output 92H input output sam input input input input input input input 93H input output 98H input input io E input Operation PCL 724 3 2 Interrupt Handling The PCL 724 s I O line PCO can generate a hardware interrupt to your PC Interrupts are edge triggered Please refer to Chapter 2 for the appropriate jumper setting and description To use the interrupt capability via PCO you must determine the IRQ level to be used Do this by simply closing the appropriate pins on J1 to select the desired interrupt level IRQ 2 through 7 Then close J2 to select the desired interrupt enable mode EN or PGM Now determine whether or not you want to trap either a rising edge signal or falling edge signal change Note Since the PCL 724 s digital input data are not latched no first event trapping is provided to determine which input was active first Although interrupts are normally triggered by external signals the PCL 724 can send output data to emulate an interrupt singal See the example in the next chapter CHAPTER 4 PROGRAMMING
8. ings The PCL 724 provides one I O line PCO that generates a hardware interrupt to your PC The IRQ level is determined by setting jumper J1 J1 MO Ui UD 00000 00000 Default Setting The interrupt capability of PCO is controlled by setting jumper J2 If J2 is set to DIS then the interrupt capability is always disabled Alternatively if J2 is set to EN then the card s interrupt capability is always enabled In order to use the PCL 724 s programmable interrupt feature set J2 to PGM If J2 is set to PGM I O line PC4 will enable the interrupt if it goes TTL LOW If PC4 goes TTL HIGH then the interrupt will be disabled J2 J2 J2 DIS oo DIS oo DIS oo PGM PGM oo PGM o o EN o o EN EN Default Setting Installation PCL 724 Set J3 to select the interrupt s trigger edge rising or falling See the illustration below J3 J3 r 71 ca Ea EA le Rising Edge Falling Edge Default Setting If you set the PCL 724 to trap on a rising edge change then an interrupt will generate if PCO changes from TTL LOW to TTL HIGH Conversely if you set the card to trap on a falling edge change then it will generate an interrupt when PCO changes from TTL HIGH to LOW HIGH CHAPTER 3 OPERATION The PCL 724 card emulates MODE 0 of 8255 PPI and is pin compatible with most industrial solid state I O racks and modules such as those manufactured by OPTO 22 Potter Brumfield Gordos etc The PCL 724 uses a 50 pin male IDC connecto
9. ower 0 5 A 5V DC 5 Maximum power 0 8 A 5V DC 5 Connector One 50 pin connector CN1 OPTO 22 compatible CONNECTOR PIN ASSIGNMENT PC 7 GND PC 6 GND PC 5 GND PC 4 GND PC 3 GND PC 2 GND PC 1 GND PC 0 GND PB 7 GND PB 6 GND PB 5 GND PB 4 GND PB 3 GND PB 2 GND PB 1 GND PB 0 GND PA 7 GND PA 6 GND PA 5 GND PA 4 GND PA 3 GND PA 2 GND PA 1 GND PA 0 GND 5V GND General Information PCL 724 If you like you can also access the signals on CN1 by attaching connectors to the holes in the PCB at CN2 and CN3 by yourself The pin assignments are as follows PAO PAL PCO PA2 PA3 PC2 PA4 PAS PC4 PA6 PA7 PC6 PBO PB1 PB2 PB3 PB4 PB5 GND PB6 PB7 5V GND GND 5V 12V Operating environment Temperature Relative humidity Storage environment Temperature Relative humidity Dimensions Dimensions I O connector 1 1 0 Cto70 C 5 to 90 noncondensing 1 3 5 7 7 9 CN3 Ne 55 C to 150 C 5 to 90 noncondensing Omer BAAN 125 0 mm by 99 5 mm 50 pin male ribbon cable connector PC1 PC3 PC5 PC7 GND 12V CHAPPER 2 INSTALLATION 2 1 Initial Inspection Before installing the PCL 724 into your PC first check to make sure that the contents of this package include the following 1 PCL 724 24 bit Digital O Card 1 User s Manual If anything is damaged due to shipping or appears to be defective please contact your local dealer CAUTION Do not install or
10. rs to interface with OPTO 22 racks One of the PCL 724 s I O lines PC 0 can be used to generate a hardware interrupt Note The PCL 724 emulates MODE 0 of 8255 PPI it is in effect the same as an 8255 controller card and all packages or programs that support the 8255 in MODE 0 can be used on PCL 724 without reconfiguring software 3 1 Configuration Mode 0 of 8255 provides simple input output functions No handshaking is required since data is written directly to or read from a specified port see 8255 MODE 0 Function Definitions PCL 724 s read back function is another useful function that allows you to monitor each output port 8255 MODE 0 FUNCTION DEFINITIONS Two 8 bit ports Port A Port B m Two 4 bit ports Port C upper Port C lower Any port can be used for input or output Outputs are latched whereas inputs are not latched 16 different input output configurations are available in this mode Operation PCL 724 Address Function BASE ADDRESS 0 Read Write BASE ADDRESS Read Write Port C BASE ADDRESS 2 Read Write CFG REG EXAMPLE Base address set at 2A0 BASE ADDRESS 3 Fig 3 1 8255 address map D7 D6 DS D4 D3 D2 DI DO 1 input O output for Port C low nibble 1 input O output for Port B 1 input O output for Port C high nibble 1 input O output for Port A Fig 3 2 CFG register format mode 0 PCL 724 Operation The following ta
11. to monitor the output status HARDWARE SETTING A X 1 Base address set at 0x2CO 5 RR RRR AA RRA A ia ia ia ia ia Ck Sk kk oko ko ko ko ko ke ke kk kk kk ke ke eek A tinclude lt stdio h gt tinclude lt conio h gt include lt process h gt include lt dos h gt main int base 0x2c0 set base address at 2CO in hex int porta save read back value of port A int portB save read back value of port B int portC save read back value of port C int ivi screen handle x clrscr gotoxy 30 3 textattr 0x70 cputs PCL 724 DEMO PROGRAME gotoxy 11 6 printf Port A output value gt gotoxy 11 8 printf Port B output value gt gotoxy 11 10 printf Port C output value gt gotoxy 50 6 printf ReadBack gt gotoxy 50 8 printf ReadBack gt gotoxy 50 10 printf ReadBack PCL 724 Programming Initialization outportb 0x2c3 0x80 all as output S EKK K KK KARA main program KAKA ck ck ck ko ke ko ke ke ke ke e ek ke ke ke ee k for 3 0 3 lt 0x100 3 outportb base j out j to port A gotoxy 34 6 printf 22x 3 portA inportb base read back gotoxy 63 6 printf S2x portA if portA 3 printf M7 beep gotoxy 30 13 textattr 0x09 cprintf Port A readback error getch exit 1 quit to dos outportb basetl j
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