DNA-AI-202 Analog Current Input Layer User Manual
Contents
1. pos represents a position in the output buffer Upon power up every entry in the output buffer is filled with its relative position number As an initializing step you should read the buffer and discard the data before proceeding with normal data collection If you start receiving consecutive data from the layer such as 0 1 2 etc it means that the layer is either not initialized properly or is damaged Tel 508 921 4600 Vers 1 4 Date February 2009 File Al 202 Chap1 fm 8 Copyright 20099 United Electronic Industries Inc Chapter 1 Introduction To convert data into floating point format use the following formula Volts Raw 0x8000 30V 2 16 15V 32 bit data has different representation Bit Name Description Reset State 31 ISO EXT1 Current value of ISO EXT1 line 0 internal use 30 ISO EXTO Current value of ISO EXTO line 0 internal use 29 ISO INT1 Current value of ISO INT1 line 0 internal use 28 ISO INTO Current value of ISO INTO line 0 internal use 27 ADCBUSY Current value of ADC 1 BUSY 0 internal use 26 DIO2 Current value of DIO2 0 TRIG_IN pin 25 DIO1 Current value of DIO1 0 EXT CLK pin 24 DIOO Current value of DIOO 0 CLK OUT pin 23 18 RSVO Reserved read as 0 0 17 16 MSB18 Configured for 16 bit mode 0 15 0 ADCDATA 2 s complement conversion 0 results in 16 bit mode NOTE 16 bit mode 18BIT field 0 in conf2. llle 6 1 5 Layer capabilities csl RII mmn 7 1 6 Differential ciet BRET ae ebd rr SLE EN NEM E ERU SEA AFER 7 1 7 Data Representa tion i s atso wasipa i aletik p cee ee 8 Chapter 2 Programming with the High Level API 000 e eee eee eee eens 10 2 1 Creating a session neaei a i Ee ee eens 10 2 2 Configuring the channels 0 0 0 0 ccc 10 2 3 Configuring the timing saaa a a mh 10 2 4 Reading datas deu Read visse DOR Mere Ble ad mos Ree wee dis Tog 11 2 5 Cleaning up the session n 11 Chapter 3 Programming using the Low Level API lessen 12 3 1 Configuration settings lille en 12 3 2 Channel List Settings ecer 0 0 0c ren 14 3 3 Layer specific commands and parameters 02020 eee eee eee 15 3 3 1 Using layer in ACB MOJE ers redes pen iat ES nh 15 3 3 2 Using layer in DMap mode 0 0000 eae 18 Appendices eret sala ra ah Ste uuu Deca gaa taMan duet ce ME o v aedes is 19 IDs 20 Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202TOC fm List of Figures Chapter1 Introduction cerea a EA E ee 1 1 1 Al 202 BOaId l i a a diete itte nbl i tet a a es earn oe 3 1 2 Al 202 Architecture Block Diagram seen emen 4 1 3 Al 202 Connector Pinot e iiA e m dep ace ed 5 1 4 Recommended Ground Connections for Analog Inputs sse 6 1 5 Typical DNA AI 202 Input Wi
3. WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Table of Contents Chapter T Introduction e ren eree renne EE ee 1 1 1 Organization of this manual nauau aaau 1 1 1 1 IntroQdUctlon cos edet e dr Pe age eae te Rod A aed ed E 1 1 1 2 The Al 202 layer amp 23 tur ett vara apetece Cute ail ade Pipe ate Rap 1 1 1 3 Programming with the High Level API 0000 e eee eee 1 1 1 4 Programming using the Low Level API 00 ee eee eee 1 1 2 ithe AI202 Layer ee ci ae then eng au paved CIVEM CONI eae Bere Renae ead 3 1 3 Device architecture cse ba ege n ened pvc ddd ated eens 4 1 4 Layer connectors and wiring 0 0 0 eee 5 1 4 1 Analog Input Ground Connections
4. Chapter 1 7 Introduction 1 5 Layer An Al 202 layer is capable of acquiring analog input current signals in the ranges capabilities of x1 5 mA 15 mA 150 mA When working with 0 20 mA or 4 20 mA industrial sensors always use the 150 mA range A layer is capable of generating its own CL and CV clocks and trigger and deriving them either from local external lines through the DB 37 connector or from the SYNCx bus A layer does not have the hardware capability of analog triggering but will have a digital implementation after conversion data analysis in a future revision Table 1 2 Gain Selection Max Common Settling Mode time to Resolution Voltage 16 bit Noise noise Layer Gain Range Range _ resolution LSB limited AI 202 10 150mA 13V 23us 105 45V 100 15mA 15V 100us 1 58 40uV 1000 1 5mA 15V 1ms 4 32 30uV 1 6 Differential An Al 202 layer operates in differential mode and digitizes up to 12 channels Each channel uses two lines on the instrumentation amplifier you connect one lead from the signal source to the channel High input the positive input of the amplifier and connect the other signal lead to the channel Low input the negative input of the amplifier Each signal floats at its own level without reference to ground or other inputs When working with Al 202 layer Aln0 and AlnO form the High and Low inputs of differential input Ch 0 For differential
5. Layer This appendix outlines calibration procedures for the Al 202 series layer Calibration Index This is an alphabetical listing of the topics covered in this manual Copyright 20099 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap1 fm Chapter 1 2 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal e good ideas you might not discover on your own NOTE Notes alert you to important information Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Copyright 20099 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap1 fm 1 2 The Al 202 Layer Copyright 20099 United Electronic Industries Inc Chapter 1 Introduction The AI 202 is an analog input layer with specifications as listed in Table 1 1 Table 1 1 DNA AI 202 Technical Specifications Resolution 16 bits Number of Channels Differential 12 Maximum Sampling Rate 16 kS s aggr
6. United Electronic Industries The High Performance Alternative DNA AI 202 Analog Current Input Layer User Manual Sequential Sampling 16 bit 12 channel Analog Current Input layer for the PowerDNA Cube February 2009 Edition PN Man DNA AI 202 0209 Version 1 4 Copyright 1998 2009 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See UEI s website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Ave Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidaq com Web Site www ueidag com FTP Site ftp ftp ueidaq com Product Disclaimer
7. MODEFIFO 2L lt lt 16 continuous acquisition with FIFO define DQ LN MAPPED 1L lt lt 15 For WRRD DMAP devices define DQ LN STREAMING 1L lt lt 14 For RDFIFO devices stream the FIFO data automatically For WRFIFO do NOT send reply to WRFIFO unless needed define DQ LN IRQEN 1L 10 enable layer irqs define DQ LN PTRIGEDGE1 1L 9 stop trigger edge MSB define DQ LN PTRIGEDGEO 1L 8 stop trigger edge 00 software 01 rising 02 falling define DQ LN STRIGEDGE1 1L lt lt 7 start trigger edge MSB define DQ LN STRIGEDGEO 1L 6 start trigger edge 00 software 01 rising 02 falling define DQ LN CVCKSRC1 1L 5 CV clock source MSB define DQ LN CVCKSRCO 1L 4 CV clock source 01 SW 10 HW 11 EXT define DQ LN CLCKSRC1 1L 3 CL clock source MSB define DQ LN CLCKSRCO 1L 2 CL clock source 01 SW 10 HW 11 EXT define DQ LN ACTIVE 1L 1 STS LED status define DQ LN ENABLED 1L 0 enable operations DQ LN ENABLE For streaming operations with hardware clocking select the following flags DQ LN CLCKSRCO DQ LN STREAMING DQ LN IRQEN DQ LN ACTIVE ENABL E enables all operations with the layer DQ LN DQ LN CLCKS timebase Al 202 supports CL clock only where the time between consecutive channel readings is calculated by the rule of maximizing
8. a reader and link it to the session s stream CueiAnalogScaledReader reader session GetDataStream read one scan the buffer must be big enough to contain one value per channel double data 2 reader ReadSingleScan data 2 5 Cleaning up The session object will clean itself up when it goes out of scope or when it is the session destroyed However you can manually clean up the session as shown below to reuse the object with a different set of channels or parameters for example session CleanUp Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap2 fm Chapter 3 3 1 Configuration Chapter 3 12 Programming using the Low Level API Programming using the Low Level API This section describes how to program the PowerDNA cube using the low level API The low level API offers direct access to PowerDNA DAQBios protocol and also allows you to access device registers directly We recommend that you use the UeiDaq Framework see Chapter 2 which is easier to use than the low level API You should only need to use the low level API if you are using an operating system other than Windows Configuration setting are passed in DqgCmdSetCfg and DgAcbInitOps settings functions Not all configuration bits apply to Al 202 layer The following bits make sense define DQ FIFO
9. all NIS electronics An isolating DC DC converter produces 5V power for the IS components of the layer Two high frequency boosters generate 18V rails that are also available at the connector 15mA maximum each As shown in the diagram the Al 202 has shunt resistors on each differential input The current flowing through each resistor produces a voltage which in turn is input to the multiplexer The voltage signal is then fed to a programm able gain instrument amplifier and then to a 16 bit SAR A D converter with no pipeline delay After conversion the digital value is processed by the logic under software control Analog Input Connector External GND Control Logic 32 bit 66 MHz bus External Clocks and Triggers Optical Isolation Figure 1 2 Al 202 Architecture Block Diagram Copyright 20099 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap1 fm Chapter 1 5 Introduction 1 4 Layer As standard with other PowerDNA Layers the Al 202 uses a B size 37 pin connectors D sub connector with the pinout shown in Figure 1 3 and wiring DB 37 female 37 pin connector AINO 37 19 AINO AIN1 36 48 AINT AIN2 35 47 AIN2 AGND 34 16 AGND AIN3 33 45 AIN3 AINA 32 44 AIN4 AIN5 31 13 AINS AGND 30 12 AGND AIN6
10. between samples slow down the board by decreasing its digitization rate Next t is the minimal time between scans of the Channel List it depends on t4 and the number of entries in the Channel List The value of 1 t is the maximum scan rate in Hz The effective per channel sampling rate also depends on the number of channels in the Channel List In this case a layer acquires data across all channels sequentially at the selected speed which need not be the peak speed This rate is referred to as the aggregate rate When the Channel List contains two channels the per channel rate is one half the aggregate rate For multiple channels you can thus calculate the maximum per channel rate as Per channel rate Aggregate rate Number of channels Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap3 fm Chapter 3 14 Programming using the Low Level API 3 2 Channel List The AI 202 layer has a very simple channel list structure Settings Bit Name Purpose Macro 31 DQ LNCL NEXT Tells firmware that there is a next entry in the channel list 20 DQ LNCL TSRQ Request timestamp as a next data point 19 DQ LNCL SLOW Double the settling time for this channel 15 DQ LNCL DIFF Differential 11 8 Gain DQ LNCL GAIN 7 0 Channel number Gains are different for different options of the Al 202 layer Layer Type R
11. 1 fm 1 4 1 Ground Analog Input Chapter 1 Introduction To avoid errors caused by common mode voltages on analog inputs follow the recommended grounding guidelines in Figure 1 4 below Connections Input Configuration Type of Input Floating Grounded Typical Signal Sources Thermocouples DC Voltage Sources Instruments or sensors with isolated outputs DNA STP 37 DNA STP AI U Typical Signal Sources Instruments or sensors with non isolated outputs DNA STP AI U Differential i Add this connection to ensure that both Two resistors 10k lt R lt 100k provide grounds are at the same potential return paths to ground for bias currents NOT RECOMMENDED DNA STP AI U Single Ended Ground Referenced Copyright 20099 United Electronic Industries Inc Because all analog input channels in Al 201 202 207 208 224 layers are islated as a group you can connect the layer AGND to the ground of the signal source and eliminate resistors shown above for floating differential input signals Figure 1 4 Recommended Ground Connections for Analog Inputs Because all analog input channels in Al 201 202 207 208 225 layers are isolated as a group you can connect layer AGND to the ground of the signal source and eliminate the resistors shown in Figure 1 4 for floating differential input signals Tel 508 921 4600 Date February 2009 Vers 1 4 File Al 202 Chap1 fm 6
12. 29 41 AING AIN7 28 10 AIN7 AIN8 27 9 AIN8 COMP 26 8 COMP AIN9 25 7 AINO AIN10 24 6 AIN10 AINTI 23 5 AINTI CLK OUT 22 4 TRIG IN 18V 21 3 EXT CLK 18V 20 2 AGND 1 AGND 19 1 meea a ate aaa ae Ee 37 20 Figure 1 3 Al 202 Connector Pinout The following inputs or outputs are connected to the Al 202 through the DB 37 connector Aln0 to Aln11 input channels All inputs are differential current signals that flow through internal 10 ohm shunt resistors connected between terminals Alnx and Alnx where x is the channel number The Al 202 senses the voltage drop across the shunt resistor on each channel AGND layer analog ground isolated from system ground CLK OUT this line by default is an output which is used as an external channel list clock This line can also be used as a bidirectional general purpose DIO TRIG IN this is an external trigger input EXT CLK by default this channel is an input that provides an external CV or CL clock to the layer logic This line can also be used as a bidirectional general purpose DIO 18V 18V lines provide isolated voltage generated on the layer to power external sensors COMP and COMP These connections are reserved for future use Do not connect anything to them at this time Copyright 20099 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap
13. CleanUpDAQLib fendif Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap3 fm Chapter 3 Programming using the Low Level API 3 3 2 Using layer in DMap mode include PDNA h 1 Start DQE engine ifndef WIN32 DgInitDAQLib fendif Start engine DqStartDOEngine 1000 10 amp pDqe NULL open communication with IOM hd0 DqOpenIOM IOM IPADDRO DQ UDP DAQ PORT TIMEOUT DELAY amp DORdCfg Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg for i 0 i lt DO MAXDEVN i if DORdCfg devmod i printf Model x Option x n DQRdCfg gt devmod i DORdCfg option i l else break 2 Create and initialize host and IOM sides DqDmapCreate pDqe hd0 amp pBcb UPDATE PERIOD amp dmapin amp dmapout 3 Add channels into DMap for i 0 i lt CHANNELS i DqDmapSetEntry pBcb DEVN DQ SSOIN i DQ ACB DATA RAW 1 amp ioffset i DqDmapInitOps pBcb DqeSetEvent pBcb DQ eDataAvailable DQ ePacketLost DQ eBufferError DQ ePacketOOB 4 Start operation DqeEnable TRUE amp pBcb 1 FALSI GI x 5 Process data while keep looping Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap3 fm 18 Chapter 3 19 Programming usin
14. L pDQSETTRIG TrigMode amp fCLClk 0 float fCVClk amp CLSize n 0 uint32 ScanBlock amp acb printf Actual clock rate fMn fCLCIk Now set up events DqeSetl Event bcb eFrameDon 3 Start operation Start operations DqeEnable TRUE amp bcb 1 FALSE 4 Process data We will not use event notifica while keep looping DqeWaitForEvent amp bcb 1 FALSE EV if events amp DQ eFrameDone minrq acb framesize avail minrq while TRUE DgAcbGetScansCopy bcb data amp avail amp size for tion at first DQ_ePacketLost DQ eBufferError DQ ePacketOOB ENT TIMEOUT acb framesize samples size CHANNELS i 0 i lt size CHANNELS i fprintf fo Sf t float data i if i CHANNELS CHANNELS 1 just retrieve scans amp events acb framesize Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 Date February 2009 Vers 1 4 File Al 202 Chap3 fm Chapter 3 17 Programming using the Low Level API fprintf fo n printf eFD d scans received d samples min d avail d n size samples minrq avail if avail lt minrg break 5 Stop operation DqeEnable FALSE amp bcb 1 FALSI Ld 6 Clean up DgAcbDestroy bcb DqStopDQEngine pDqe DqCloseIOM hd0 ifndef WIN32 Dq
15. ampling call the same function with Oxffffffff as a channel number This is a pseudo code example that highlights the functions needed in sequence to use ACB on the 202 layer A complete example with error checking can be found in the directory SampleACB202 unit configuration word define CFG202 uint32 Config ifndef WIN32 DgInitDAQLib fendif DQ LN ENABLED V DQ LN ACTIVE DQ LN GETRAW DQ LN IRQEN DO LN CLCKSRCO DQ_ LN STREAMING DQ_AI202 MODEFIFO CFG202 1 Start DQE engine O Start engine DqStartDQEngine 1000 1 amp pDqe NULL Open communication with IOM hd0 DqOpenIOM IOM IPADDRO DQ UDP DAQ PORT TIMEOUT DELAY amp RdCfg Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 Vers 1 4 Date February 2009 File Al 202 Chap3 fm Set up channel lis n lt CHANNI for 0 n ss n CL n ELS n Chapter 3 16 Programming using the Low Level API 2 Create and initialize host and IOM sides Now we are going to test device DgAcbCreate pDqe hd0 DI EVN DQ SSOIN amp bcb Let s assume that we are dealing with AI 202 device dquser initialize acb structure Now call the function DgAcbInitoOps bcb 0 amp Config 0 TrigSize NUL
16. ange Gain Gain Number Al 202 1 5mA 1000 1 15 mA 100 2 150 mA 10 3 Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap3 fm 3 3 Layer specific commands and parameters 3 3 4 Using layer in ACB mode include PDNA h Chapter 3 Programming using the Low Level API Layer specific functions are described in DaqLibHL h file DqAdv202Read This function works using the underlying DqgReadAIChannel but converts data using internal knowledge of input range and gain of every channel It uses the DOCMD_IOCTL command with the DOIOCTL_CVTCHNL function When this function is called for the first time the firmware stops any ongoing operation on the device specified and reprograms it according to the channel list supplied This function uses the preprogrammed CL update frequency 10Hz You can reprogram the update frequency by calling the DqCmdSetClk command after the first call to DgaAdv202Read Thus you cannot call this function when the layer is involved in any streaming or data mapping operations If you specify a short timeout delay this function can time out when called for the first time because it is executed as a pending command and layer programming takes up to 10ms Once this function is called the layer continuously acquires data and every next call function returns the latest acquired data If you would like to cancel ongoing s
17. at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Ai0 2 3 4 The gain to apply on each channel is specified using low and high input limits For example the Al 202 100 available gains are 10 100 and 1000 and the maximum input range is 15V 15V To select the gain of 100 simply specify input limits of 0 15V 0 15V Configure channels 0 1 to use a gain of 100 in differential mode session CreateAIChannel pdna 192 168 100 2 Dev0 Ai0 1 0 15 0 15 UeiAIChannelInputModeDifferential You can configure the Al 202 to run in simple mode point by point or buffered mode ACB mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by the Al 202 on board clock The following example shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use the other timing modes Tel 508 921 4600 Vers 1 4 Date February 2009 File Al 202 Chap2 fm Chapter 2 11 Programming with the High Level API session ConfigureTimingForSimpleIlO 2 4 Reading data Reading data from the Al 202 is done by using a reader object There is a reader object to read raw data coming straight from the A D converter There is also a reader object to read data already scaled to volts The following sample code shows how to create a scaled reader object and read samples Create
18. egate Onboard FIFO Size 512 samples Input Ranges 1 5 mA 15 mA 150 mA use when measuring 0 20mA or 4 20mA sensors Shunt Resistance 10 2 0 196 Input Bias Current 15 nA Input Overvoltage 40V 2000V ESD powered or unpowered 20mA max current Isolation 1500Vrms A D Conversion Time 2 usec A D Settling Time 22 usec 150 mA scale 100 psec 15 mA scale 1 msec 41 5 mA scale Nonlinearity Noise Nonlinearity 1LSB System Noise 1 2 LSB Effective Number of Bits 14 8 Total Harmonic Distortion 91 dB Channel Crosstalk 85 dB 1kS s Power Consumption 1 8W Operating Temp tested 40 C to 85 C Operating Humidity 9096 non condensing The DNA AI 202 is similar in design to the DNA AI 201 100 except that it has shunt resistors on 12 differential inputs for sensing mA current inputs Gains of 10 100 and 1000 are also available on the Al 202 A photo of an Al 202 Layer s shown in Figure 1 1 Figure 1 1 Al 202 Board Tel 508 921 4600 Date February 2009 Vers 1 4 File Al 202 Chap1 fm 3 Chapter 1 4 Introduction 1 3 Device The Al 202 layer is physically divided into isolated IS and non isolated NIS architecture parts as illustrated in the block diagram of Figure 1 2 The non isolated part is powered from DC DC converters located on the CPU layer These converters provide 5V and 3 3 2 5V to power
19. f single ended mode Signals are measured relative to AGND Calibration procedure using a serial port terminal program Apply OV on channels 0 and 1 Type simod 1 Select the proper device from the device table to calibrate Select channel 0 as a signal source Select calibration DAC 2 to calibrate offset Adjust offset by pressing and keys current DAC values are dis played Use and Y keys to decrease or increase value of calibration DAC by 10 Select calibration DAC 1 to calibrate gain Apply 9 or 14V to the input and adjust DAC 2 to read proper value Press Esc and reply y if you want to save calibration values into E PROM Reset the PowerDNA cube to verify calibration NOTE The calibration program uses FIR and MAW filters to improve resolution Press c to clear the filter history We recommend that you calibrate offset by applying 0 volts from the signal source rather than by shorting inputs We recommend calibrating layer gain as close to the end of the scale as possible 14V calibration point is ideal for layer calibration Tel 508 921 4600 Vers 1 4 Date February 2009 File Al 202 Appx fm 21 You can verify calibration after resetting the PowerDNA cube using the same simod 1 routine but do not save results simod 2 shows raw acquired data without filtering For Al 202 layers we recommend annual factory recalibration at UEI C EEPROM The following structure represent
20. g the Low Level API DqeWaitForEvent amp pBcb 1 FALSE timeout amp eventsin if eventsin amp DQ eDataAvailable datarcv t t printf ndata for i 0 i lt CHANNELS i printf 04x uintl6 ioffset i 6 Stop operation DqeEnable FALSE amp pBcb 1 FALSI GI x 7 Clean up DqDmapDestroy pBcb DqStopDQOEngine pDqe DqCloseIOM hd0 ifndef WIN32 DqCleanUpDAOLib fendif Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap3 fm Appendices A Accessories B Layer Calibration Copyright 2009 United Electronic Industries Inc 20 The following cables and STP boards are available for the Al 202 layer DNA CBL 37 3ft 37 way flat ribbon cable connects DNA AI 202 to panels DNA CBL 37S 3ft 37 way round extender cable with thumbscrew connectors on both ends connects DNA AI 202 to screw termination panels and other devices DNA STP AI U Universal PowerDNA Analog Input Terminal Panel for the DNA AI 202 16 DNA STP 37 37 way screw terminal panel DNA 5B CONN 24 channel signal conditioning mating panel Please note that once you perform layer calibration yourself the factory calibration warranty is void Calibration should be performed with a microvolt resolution precision voltage source with low 1 ohm or less output impedance Calibration assumes the use o
21. iguration delivers data in two s complement format Tel 508 921 4600 Date February 2009 Vers 1 4 File Al 202 Chap1 fm 9 Chapter 2 2 4 Creating a session 2 2 Configuring the channels 2 3 Configuring the timing Copyright 2009 United Electronic Industries Inc Chapter 2 10 Programming with the High Level API Programming with the High Level API This section describes how to program the PowerDNA AI 202 using the UeiDaq Framework API As the UeiDaq Framework is object oriented its objects can be manipulated in the same manner in various development environments such as Visual C Visual Basic or LabVIEW Although the following section focuses on the C API the concept is the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual for more information about using other programming languages The Session object controls all operations on your PowerDNA device Therefore the first task is to create a session object as follows CUeiSession session Framework uses resource strings to select which device subsystem and channels to use within a session The resource string syntax is similar to a web URL as follows lt device class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA the device class is pdna For example the following resource string selects analog input channels 0 2 3 4 on device 1
22. input Ch 1 use Aln1 and Aln1 Follow this pattern for all twelve differential input pairs Two high impedance amplifiers monitor the voltage between the inputs and the analog ground A third amplifier measures the difference between the Positive and Negative inputs eliminating any voltage common to both wires common mode noise We recommend that you use twisted pair cable to bring signals to the data acquisition layer to ensure that any noise generated along the wiring path is the same for each line The amplifier subtracts this common mode noise The maximum common mode voltage range for each gain selection is listed in Table 1 2 Copyright 20099 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Chap1 fm Chapter 1 Introduction Figure 1 5 illustrates the wiring of a typical input to the DNA AI 202 Layer board A 1 7 Data Representa tion Copyright 20099 United Electronic Industries Inc lt luser AlnO Rioad V Vcommon mode V Figure 1 5 Typical DNA AI 202 Input Wiring The AI 202 layer is equipped with an 18 bit A D converter configured to return 16 bit 2 s complement data in 16 bit words 16 bit data is represented as follows Bit Name Description Reset State 15 SIGN Sign Signal levels below OV 0 correspond with negative values sign bit is set 14 0 ADCDATA Upper 15 bits of data 2 s pos complemented
23. itions int clperint number of channel lists per interrupt ignored if 1 or invalid DOOPMODEPRM 202 pDQOPMODEPRM 202 DQCNAMES 202 structure included contains channel names up to 20 characters long channel names typedef struct char cname DQ AI202 CHAN DQ AI202 NAMELEN Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Appx fm DQCNAMES 202 pDOCNAMES 202 User can set and store these parameters using DqCmdSetParameters See the API Reference Manual for details PowerDNA Explorer provides a graphical interface for program names and operation mode parameters Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202 Appx fm Index A Advanced Circular Buffer 15 C Cable s 20 Channel list Channels 13 Clock 12 13 Structure 14 F Features 3 G Ground Connections 6 L Layer Capabilities 7 Layout Connector 7 M Mode ACB 15 DMap 18 S Screw terminal panels 20 Settings ChannelList 14 Configuration 12 Copyright 2009 Tel 508 921 4600 United Electronic Industries Inc Date February 2009 Vers 1 4 File AI 202IX fm 23
24. ring ssseesenem mener 8 Chapter 2 Programming with the High Level API 000 e eee e eee eens 10 None Chapter 3 Programming using the Low Level API 00c cece ence een eeeee 12 3 1 Cleand GV Clock Tirrilrig o eee cer tr ea AN ene 13 Copyright 2009 Tel 508 921 4600 Vers 1 4 United Electronic Industries Inc Date February 2009 File Al 202LOF fm Chapter 1 1 Introduction Chapter 1 Introduction This document outlines the feature set and use of the PowerDNA DNA AI 202 layer This layer is an analog input module for the PowerDNA I O Cube designed for current input signals 1 4 Organization This DNA AI 202 User Manual is organized as follows of this manual 1 1 1 Introduction This section provides an overview of PowerDNA Analog Input Series board features the various models available and what you need to get started 1 1 2 The Al 202 This chapter provides an overview of the device architecture connectivity and layer logic of the Al 202 layer 1 1 3 Programming This chapter provides an overview of the how to create a session configure the with the High session for digital data acquisition output and format relevant output Level API 1 1 4 Programming This chapter describes the low level API commands for configuring and using using the Low the Al 202 layer Level API Appendices A Accessories This appendix provides a list of accessories available for the Al 202 layer B
25. s content of the layer EEPROM Structure combined structure to be allocated after DQEECMNDEVS typedef struct DQEECMNDEVS ee DOCALSET 202 calset DQOPMODEPRM 202 opmodeprm DOCNAMES 202 cname DEVEEPROM 202 pDEV Ld I EPROM 202 DQEECMNDEVS structure is a standard E PROM header described in 6 2 2 Calibration information includes calibration values for on board calibration potentiometers Current revision of the layer uses two potentiometers Two later values in the calibration array must duplicate the first two values specific device structure calibration values typedef struct uint8 cal AI202 CALDACS four calibration DAQs uintl6 precref AI202 VREFS exact binary code of the built in voltage ref CALSET 202 pCALSET_ 202 DQOPMODEPRM 202 structure contains data for operating mode This data is pre loaded into working array upon switching into configuration and mode can be overwritten before going into operating mode channel list for this device operation mode is stored here only this device driver knows about this data nobody else should typedef struct uint32 chlst DO AI202 CHAN 2 channel list full uint32 conf control word layer API flags uint32 cvclk CV clock uint32 clclk CL clock uint32 trig trigger cond
26. setup time per channel If you d like to select the CL clock from an external clock source such as the SYNCx line set DO LN CLCKSRC1 as well RCO selects the internal channel list clock CL source as a Copyright 2009 United Electronic Industries Inc Tel 508 921 4600 Vers 1 4 Date February 2009 File Al 202 Chap3 fm Chapter 3 13 Programming using the Low Level API DQ LN CVCKSRCO selects the internal conversion clock CV source as a timebase Setting CV clock allows having an equal time period between conversions of different channels It is mostly used when the user is interested in a phase shift between different channels DO LN ACTIVE is needed to switch on STS LED on the CPU layer You can select either the CL clock or the CV clock as a timebase If you select both clocks the CL clock is taken as a timebase and the CV clock determines the delay between converting channels i e settling time In the following figure CL refers to the CL Clock also known as the Channel List clock or the Scan Clock CV refers to the CV Clock also known as the Conversion Clock m2 Moment of Digitization Signal level at the moment of digitization Figure 3 1 CL and CV Clock Timing Note that t4 shows the time between individual samples on the A D the time between CV clock cycles is limited by the board s maximum digitization rate and settling time If you need to increase the settling time
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