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PMP10580 DE0-Nano User Manual (Terasic

1. Message Processing Extra Info Info A Warning A Critical Warning A Error A Suppressed Flag J Message Location Zi Locate 096 00 00 00 Figure 7 8 A New Complete Project 5 Select Tools SOPC Builder to open SOPC Builder the Altera system generation tool as shown in Figure 7 9 Tools Window Help Run Simulation Tool Run Timing Analysis Tool Launch EDA Simulation Library Compiler Launch Design Space Explorer TimeQuest Timing Analyzer Advisers Chip Flanner Floorplan and Chip Editor Design Fartition Planner Hetlist Viewersz SignalTap II Logic Analyrer In System Memory Content Editor Logic Analyzer Interface Editor Sources and Probes Editor SigmalFrobe Fins Programmer JTAS Chain Debugger Transceiver Toolkit External Memory Interface Toolkit Mezalirard Fluz In Manager SOFC Builder zyz Tel Seripts Customize Options License Setup Figure 7 9 SOPC Builder Menu 87 Terasic DEO Nano User Manual www terasic com www terasic com Create New System Altera SOPC Builder unnamed sope 0 niosiiXunnamed File Edit Module System View Tools Help System Contents System Generation Target Device Family Verification Suite and Adapters i 4Interface Protocols
2. User Manual World Leading FPGA Based Products Design Services 010101010001010101010101010101001010101 1 10101001010100100101010101010010101010101010101010 1001011010101101 T000 101111010011010 1010101010001010101010101010101001010101110101001010100100T0TOTOTOTOTOOTOTOTOTOTOTOTOTOTOTOTOOTOTTOTOTOTTO T1000 TOTTTTOTOO TOTO 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010101010100101 1010101010001010101010101010101001010101110101001010100100101010101010010101010101C 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010101010100101 1010101101 1000101111010011010 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010101010100101 10101011011000101111010011010 1010101010001010101010101010101001010101 1 101010010101001001010101010100101010101010101010101001 01 1010101101100010111101001 1010 ter ERT www terasic com Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved CONTENTS prx US CHAPTER 1 INTRODUCTION 5 INIT EE m mm 5 L Pere mdi dU 7 PH 7 CHAPTER 2 DEU NANO PEE Eva 8 21 Layo t and m 8 2 2 Block D
3. gli Auto Detect Delete Add File Change File it Save File up Down Figure 9 7 Erasing setting in Quartus Il programmer window 5 Click Start to erase the serial configuration device 153 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA 9 2 EPCS Programming via nios 2 flash programmer Before programming the EPCS via nios 2 flash programmer users must add an EPCS patch file nios flash override txt into the Nios H EDS folder The patch file is available in the folder Demonstation EPCS_Patch of DEO Nano System CD Please copy this file to the folder QuartusInstalledFolder nios2eds bin e g C altera 11 1 nios2eds bin If the patch file is not included into the Nios II EDS folder an error will occur as shown in Figure 9 8 Using cable USB Blaster USB 1 device 1 instance ipar And eres Tiri Baga e a EPCS layout data looking For section 18216 1 Unable Co aeuice Leaving target processor paused Figure 9 8 EPCS Message 9 3 Revision History Version Change Log V1 0 Initial Version Preliminary V1 3 Add Table 3 1 3 2 and 3 3 V1 4 Modified Digital Accelerometer Description on page 31 V1 5 Modified ADC description on page 32 V1 6 Corrected Digital Accelerometer Schematic on page 23 V1 7 Modified Altera EPCS16 to be Spansion EPCS64 V1 8 Add SDRAM test section
4. o Standard 3 39V 3 3V 3 3V www terasic com JA DTE RIA GPIO 02 GPIO 03 GPIO 04 GPIO 05 GPIO 06 GPIO 07 GPIO 08 GPIO 09 GPIO_010 _011 _012 _013 GPIO 014 GPIO 015 GPIO 016 GPIO 017 GPIO 018 GPIO 019 GPIO 020 GPIO 021 GPIO 022 GPIO 023 GPIO 024 GPIO 025 GPIO 026 GPIO 027 GPIO 028 GPIO 029 GPIO 030 GPIO 031 GPIO 032 GPIO 033 Signal Name GPIO 1 INO GPIO 10 GPIO 1 1 1 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 Terasic DEO Nano User Manual www terasic com PIN A2 PIN A3 PIN B3 PIN B4 PIN A4 PIN B5 PIN A5 PIN D5 PIN B6 PIN A6 PIN B7 PIN D6 PIN A7 PIN C6 PIN C8 PIN E6 PIN E7 PIN D8 PIN E8 PIN F8 PIN F9 PIN PIN C9 PIN D9 PIN E11 PIN E10 PIN C11 PIN B11 PIN A12 PIN D11 PIN D12 PIN B12 GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection
5. PINCi6 GPIO Connection DATA 3 3 GPIO 244 5 Connection DATA 4 3 3V 25 PIN 016 GPIO Connection DATA 5 3 3 GPIO 260 Di5 GPIO Connection DATA 6 3 GPIO 27 Di4 GPIO Connection DATA 7 3 3V GPIO 281 PINFI15 GPIO Connection 330 16 14 GPIO Connection DATA 9 3 3V GPIO 210 IGPIO Connection DATA 10 3 3V 2 11 PIN 616 GPIO Connection DATA 11 3 3V 3 3V GPIO_2_IN 0 15 GPIO Input 8 GPO 2 NH PINE6 GPIO Input GPO 2 NZ PNMI Table 3 9 Pin Assignments for ADC Name FPGA Pin No Description VO Standard ADC_CS_N PIN_A10 Chip select 3 3V 3V ADC_SADDR PIN B10 Digital data input ADC_SDAT 9 Digital data output ADC SCLK PIN B14 Digital clock input 22 Terasic 0 User Manual www terasic com www terasic com JA DTE RYA 3 7 Digital Accelerometer The ADXL345 is a small thin ultralow power 3 axis accelerometer with high resolution measurement This digital accelerometer can be accessed through a SPI 3 wire digital interface or DC 2 wire digital interface Main applications include medical instrumentation industrial instrumentation personal electronic aid and hard disk drive protection etc Some of the key features of this device are listed below For more detailed information please refer to its datasheet which
6. Computer File soPc Network Places Files af type SOPC Builder System Files sopc Figure 7 37 Generate SOPC 108 TagasiC Terasic DEO Nano User Manual www terasic com www terasic com Altera 5OPC Builder SOPC sopc D myfirst_ niosiDED _ ODE File Edit Module System View Tools Mios II Help System Generation Options System module logic will be created in Verilog Simulation Create project simulator files Run Simulator 1 Tools Mios 1 Software Build Tools for Eclipse 2011 02 24 13 23 09 Generating Quartus symbol for top level DEO SOPC 2011 02 24 13 23 08 Generating Symbol Duimytirst_niosivDEO bet 2011 02 24 13 23 08 Creating command line system qeneration script Dr Anyfirst_niosivDEO MANO SOPC generation script 2011 02 24 13 23 09 Running setup for HOL simulator madelzim 2011 02 24 13 23 10 Completed generation for system DEO WANG SOPC 2011 02 24 13 23 10 THE FOLLOWING SYSTEM ITEMS HAYE BEEN GENERATED SOPC Builder database Drmvyfirst niasii DED SOPIC ptf System ADL Model D imfirst SOPC v System Generation Script Oo dmwyfirst generation script 2011 02 24 13 23 10 SUCCESS SY STEM GENERATION COMPLETED Warning epu Custom Instruction components can be edited through the Compo
7. Construct using registers instead of memory blocks Simulated input character stream interactive windows INTERACTIVE ASCI OUTPUT Figure 7 20 JTAG UART s add wizard 12 We are going to use the default settings for this component so click Finish to close the wizard and return to the window as shown in Figure 7 21 95 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN Altera SOPC Builder File Edit Module System View Tools Niosl Help system Contents System Generation Ta rget Project Device Family Cyclone WE Name Source Fines i New component External Library Verification Suite Bridges and Adapters E3 Interface Protocols 8 ASI Ethernet High Speed instruction master Avalon Memory Mapped Master Interlaken data master Avalon Memory Mapped Master gr Pol een jag debug module E SO a fag uart 0 E Serial avalon jtag slave Avalon Memory Mapped Slave Avalon ST JT AG Avalon ST Serial gt SPI 3Wire Serial UART RS 232 Se Legacy Components I GJ To Do cpu reset vector has been specified for this CPU Please parameterize the CPU to resolve this sue Do exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue A Warning cpu Reset vector and Exception vector cannot be set until memory devices
8. Controller oqe 5 JAG Timer Figure 8 6 SOPC Block Diagram A 50 MHz Clock is required for the SOPC System A NIOS II processor is included in the system for flow control The PLL is used to generate clocks including 100 MHz 10 MHz and 2MHz The NIOS II Processor and SDRAM are running at 100 MHZ The SDRAM is used to store the NIOS Program The ADC SPI Controller is running at 2 MHz The other peripheral controllers are running at 10 MHz The ADC SPI Controller and the Accelerometer SPI Controller are custom SOPC component The source code for these two controllers is located in the ip folder under this Quartus project The other components are standard SOPC Builder components 136 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN B KEY The KEY button is driven by Controller with interrupt enabled It 15 design to generate an interrupt event when users click KEYO or KEYI The interrupt event is used to terminate accelerometer and analog to digital conversion process in this demo For default the interrupt 1s disabled in the PIO Controller Users can enable it with the parameter setting as shown in below Figure 7 PIO Parallel key WE Parallel 1 0 E Magetore allera avalon pio Width 1 32 bits 2 Direction Bidir Input CO Inout Q Output Output Port Re
9. SDRAM System Intercoment Fabric Figure 8 15 Block diagram of the SDRAM Basic Demonstration The system flow 1 controlled by a Nios II program First the Nios II program writes test patterns into the SDRAM Then it calls Nios II system function alt dcache flush all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result 1 displayed the JTAG Terminal B Design Tools e Quartus II 13 0 SPI e Nios II Eclipse 13 0 SPI B Demonstration Source Code e Quartus Project directory DEO SDRAM Nios Test Nios Eclipse DEO SDRAM Nios Test Software B Nios II Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse 144 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA B Demonstration Batch File Demo Batch File Folder DEO NANO SDRAM _ Nios Test Memo batch The demo batch file includes following files e Batch File for USB Blaster DEO NANO SDRAM Test bat DEO SDRAM Test sh FPGA Configure File DEO SDRAM Test sof Nios Program DEO SDRAM Nios Test elf B Dem
10. cives eo euo pii cu tieg 3l SNP Qu J 32 4 7 Overall Structure of DEO Nano Control Panel eese 33 CHAPTER 5 DEU NANO SYSTEM BUILDER DA 34 E EE 34 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA FA DE E E E ER 34 5 3 Using DEO Nano System 36 6 TUTORIAL CREATING AN FPGA 40 OMM BT Eus T O a 40 YOU De 4 E b COTRA ER BS DOR T E T TEES 45 Thee IU 45 49 C ASS CS 71 6 7 Create a Default Time Quest SDC File 73 Genre BIST NET 74 OP re ari al 76 a SINCERE E E E 79 CHAPTER 7 TUTORIAL CREATING NIOS II PROJECT ccccsssssssscssccscssccsscsscssccscssssssccses 92 WRC ONC 62 Ted Creation Hardware m 62 To Download Hardware 117 7 4 Create a hello world Example nenne
11. pin b F bidir H A storage Name input Repeat insert mode Insert symbol as block Launch MegaWizard Plug In MegaWizard Plug In Manager Cancel Figure 6 28 Input pin symbol 62 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 4 Place the new pin onto the BDF so that it is touching the input to the pll symbol 5 Use the mouse to click and drag the new input pin to the left notice that the ports remain connected as shown in Figure 6 29 frequency 50 000 MHz CLOCK 5 counter out 31 0 Operation Mode Normal Ratio Ph dg DC 3 Len 110 0 00 50 00 Figure 6 29 Connecting the PLL symbol and Input port 6 Change the pin name by double clicking pin name and typing CLOCK 50 see Figure 6 30 This name correlates to the oscillator clock that is connected to the FPGA B Adding an Output bus to the Schematic The following steps describe how to add an output bus to the schematic 1 Using the Orthogonal Bus tool draw a bus line connected on one side to the simple counter output port and leave the other end unconnected at about 4 to 8 grid spaces to the right of the simple counter 63 Terasic DEO Nano User Manual www terasic com www terasic com ra Properties To create multiple pins enter a name in AHDL bus notation For example name 3 0 or enter comma seperated list of names an vanes fat va Figure 6 3
12. zenerated gdb generated sh m 0 HI generated x I E ond O n s L generated_all mk H O Goo er L O pm mig mp m m p p pm p pr pr MM M pu p bt pp Le generated app mk 0 o alteraniozzl libhello world D lg d i Makefile s gt ket TE eee Properties system stf Creating generated Build completed in Figure 7 59 The system h file If you look in the system h file for the Nios II project example used in this tutorial you will notice the pio_led function This function controls the LEDs The Nios processor controls the PIO ports and thereby the LEDs by reading and writing to the register map For the PIO there are four registers data direction interruptmask and edgecapture To turn the LED on and off the application writes to the PIO s data register The PIO core has an associated software file altera_avalon_pio_regs h This file defines the core s register map providing symbolic constants to access the low level hardware The altera_avalon_pio_regs h file is located in the directory altera 10 1 ip sopc_builder_ip altera_avalon_pio When you include the altera_avalon_pio_regs h file several useful functions that man
13. 7 Click Change File 8 Browse to the myfirst_niosii project directory 9 Select the programming file myfirst_niosi1 sof 10 Click OK 11 Click Hardware Setup in the top left comer of the Quartus II programmer window The Hardware Setup dialog box appears 12 Select USB Blaster from the currently selected hardware drop down list box as shown in Figure 7 53 Note If the appropriate download cable does not appear in the list you must first install drivers for the cable Refer to Quartus II Help for information on how to install the driver lt gt Hardware Setup Hardware Settings Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware USB Blaster USB 0 p 206 No Hardware Available hardware items UISB Blaster USB 0 Hardware LISB Blaster Remove Hardware Figure 7 53 Hardware Setup Window 13 Click Close 14 Make sure the Program Configure option for the programming file see Figure 7 54 for an example 15 Click Start 118 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA Quartus II Programmer Chainl cdfls File Edit View Processing Tools Help Hardware Setup USB Blaster USB 0 TAG Enable real time ISP to allow background programming for MAX II and MAX V devices File D
14. Programmer E Ny design my first fpga my first my first fpga my E mfx Edit View Processing Tools Window i USE Blaster 58 0 JTAG Progress Do d Enable real time ISP to allow background programming for MAX II and MAX V devices I ls ii EL m Lh m ET T Checksum Usercode Program Verify Blank pel start Configure Check my first fnga sof EP4CE22F17 00138880 Stop Auto Detect X Delete fa Add File lr Change File Save File 6 Add Device rd samudu H T ERA I Down Figure 6 46 Programmer Window 2 Click Hardware Setup 3 fit is not already turned on turn on the USB Blaster USB 0 option under currently selected hardware as shown in Figure 6 47 77 TilasiC Terasic DEO Nano User Manual www terasic com UO Hardware Set up Hardware Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies onl to the current programmer window Currently selected hardware USB Blaster USB 0 Hardware Available hardware items USB Blaster USB 0 Remove Hardware Figure 6 47 Hardware Setting Click Close If the file name in the Programmer does not show my first fpga sof click Add File Select the my first fpga sof file from the project directory see Figure 6 48
15. Qo Mapped Slave i 9 JAwalon ST Dual Clock FIFO onchip_memory2 Avalon ST Multi Channel Shared Memory FIFO Avalon ST Round Robin Scheduler 5 Single Clock FIFO On Chip FIFO Memory On Chip Memory or ROM Target Clock Settings Device Family Cyclone Module Error cpu instruction master onchip memory2 s1 cannot be at 0 2000 0 0 0x10000 are acceptable Error cpu data master onchip memory2 s1 cannot be at 0x2000 0x0 010000 are acceptable CJ To Do cpu No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue GJ To Do cpu No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Figure 7 27 Rename On Chip memory 18 Right click on the cpu component table and select Edit from the list Update the Reset Vector and Exception Vector as shown in Figure 7 28 Then click Finish to return to the window as shown Figure 7 29 101 Terasic DEO Nano User Manual www terasic com ON Nios II Processor cpu Parameter 2 Caches and Memory Interfaces Core Nios Il E Advanced Features gt MMU and MPU Settings gt Debug Module Custom Instructions Select a Il core ONios ONios 1 5 RISC Nios ll api Selector Guide Family Cyclone T stem 50 0 MHz cpuid 0
16. The DEO Nano System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 5 6 Users can save the current board configuration information into a cfg file and load it to the DEO Nano System Builder 38 DEO Nano User Manual www terasic com www terasic com Terasic DEO Nano System Builder V1 0 0 System Configuration UNTVEWSBITY www terasic com EPOR ini PROGRAM DEO NANO DEO Nano FPGA Board clock LEDx8 sd Button x 2 Dip Switch x 4 M SDRAM 32MB H E EEPROM 2Kb EPCS Accelerometer 2x13 Pin Header or amma ITT G PIO 0 Header oM Piy el Camera sa HB Prefix Name ARARRRARARAAARA L4 GPIO 1 Header Load Setting None Prefix Name Save Setting Figure 5 6 Project Settings B Project Generation When users press the Generate button DEO Nano System Builder will generate the corresponding Quartus II files and documents as listed in the Table 5 1 Table 5 1 The files generated by DEO0 Nano System Builder No Filename Projectname v name gt v Top level Verilog HDL file for Quartus level Verilog HDL file for Quartus I lt Project name gt qpf Il Project File Project name gt qsf Quartus ll Setting File Project name gt sdc Synopsys Design Constraints fi
17. hello world application stf readme txt E ES hello world 0 syslib 2 115 SOPC include lt stdio n gt include system n include altera avalon int main bl int while 1 Problems Console 52 Properties lal B hello world 0 Hios II HW configuration Hios II Hardware Hios II Terminal Window 10 65 18 F4F8 38 nios2 terminal connected hardware target using JTAG UART on cable nios2 terminal USB Blaster U DIM V 1 instance O E 4 4 ITT THE Tasg 4 3 T nios2 terminal Use the IDE co o Ct C to terminate Writable Figure 7 60 Set Breakpoint 2 To debug your application right click the application hello_world_0 and select Debug as gt Nios Hardware 3 If the Confirm Perspective Switch message box appears click Yes After a moment the main function appears in the editor A blue arrow next to the first line of code indicates that execution stopped at that line 127 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 5 Select Run gt Resume to resume execution When debugging a project in the Nios IDE you can pause stop or single step the program set breakpoints examine variables and perform many other common debugging tasks Note To return to the Nios II C C project perspective from the debug perspective click the two arrows gt gt in the top right corner of the GUI 7 9 Configure System Libr
18. Factory default enhanced EP4CE22 0017775C FFFFFFFF lili Stop output file jic EPCS64 7 940117 gli Auto Detect Delete Change File a Save File Add Device EPCSe4 E 4b up TUSSUUSUUS Ji Doin Figure 9 6 Quartus II programmer window with one JIC file 3 Click Start to program serial configuration device B Erase Serial Configuration Device To erase the existed file in the serial configuration device follow the steps listed below 1 Select Tools gt Programmer The Chainl cdf window displays 2 Click Add File From the Select Programming File page browse to a JIC file 3 Click Open 4 Erase the serial configuration device by checking the corresponding Erase box a Factory 152 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA default SFL image will be load See Figure 9 7 Programmer 0 vl 0 9 CDROR DEU Nano v1 0 9 CDROR Demonstration DEU default E Edit View Processing Tools Window Pad Hardware Setup USB Blaster 058 0 Mode Progress Enable real time ISP to allow background programming for MAX II devices File Device Checksum Usercode Program Verify Blank Examine Security Erase start Configure Check Bit a Factory default enhanced 22 0017776C FFFFFFFF Wii Stop NE 7C920117
19. Performance at 50 0 MHz Up to 8 DMIPS Logic Usage 600 700 LEs Hardware Multiply Embedded Multipliers Reset Vector Memory onchip_memory Offset 0 00002000 Exception Vector Memory v Offset 0 00002020 Fast TLB Miss Exception Vector Memory Offset include MPU Figure 7 28 Update CPU settings 102 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA Altera 50PC Builder File Edit Module System View Tools System Contents System Generation Target Avalon Verification Suite Device Family Cyclone Bridges and Adapters Es 3 Interface Protocols Legacy Components Memories and Memory Controllers DDR2 SDRAM Controller with UniPHY New a 00 SORAM Controler with UniPHY Mew ao QDRI and QDR 1 SRAM Controller with UniPH L amp RLDRAM 1 Controller with UniPHY x amp Traffic Generator and BIST Engine New Flash On Chip 9 Avalon ST Dual Clock FIFO Avalon ST Multi Channel Shared Memory FIFO Avalon ST Round Robin Scheduler Avalon ST Single Clock FIFO On Chip FIFO Memory EXE On chip Memory RAM or ROM Mios 1 Processor instruction_master Avalon Memory Mapped Master data_master Avalon Memory Mapped Master debug module Avalon Memory Mapped Slave E jtag uart JTAG UART avalon slave Avalon Memory Mapped Slave onchip memory On Chip Memory RAM or ROM 51 Avalon Memory Mapped
20. Programming file type JTAG Indirect Configuration File jic d Options Configuration device EPCS64 vi Mode Active Serial File name l output file jic ty SOF File Properties Input files to convert File Data area i Flash Loader Iz SOF Data Page 0 DEO NANG sof EPS CE22F 17 Figure 9 5 Compression the sof file B Write JIC File into Serial Configuration Device To program the serial configuration device with the JIC file that you just created add the file to the Quartus Programmer window and follow the steps 1 When the SOF to JIC file conversion is complete add the JIC file to the Quartus Programmer window i Select Tools gt Programmer The Chainl cdf window displays Click Add File From the Select Programming File page browse to the file 11 Click Open 151 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA 2 Program the serial configuration device by checking the corresponding Program Configure box a Factory default SFL image will be load See Figure 9 6 lt gt Programmer D CD DE_Nano DEO_Nano_v1 0 9_CDRON DEO_Nano_v1 0 9 CDROMN Demonstra DX Edit View Processing Tools Window rae Hardware Setup USE Blaster 058 0 Made AG s Progress Enable real time ISP to allow background programming for MAX II devices File Device Checksum Usercode Program Verify Blank Ben pil start Configure Check
21. RLDRAM I Controler with UniPH Traffic Generator and BIST Engir GE DMA Flash E On Chip SDRAM 1 SRAM Merlin Componenta E epu Nios Il Processor instruction_master Avalon Memory Mapped Master data master Avalon Memory Mapped Master jag debug module Avalon Memory Mapped Slave uart JTAG UART avalon jag zlave Memory Mapped Slave onchip memory2 On Chip Memory RAM or ROM 1 Awalon Memory Mapped Slave pio led PIO Parallel lO 31 Avalon Memory Mapped Slave E Waring cpu Custom Instruction components can be edited through the Component Editor ss Warning cpu Disabling the assign CPUID control register value manually will no longer auto assigns unique control register value This option will always be turned on with default i gt Figure 7 35 No errors or warnings 107 Terasic 0 User Manual www terasic com www terasic com JA DTE RYA 23 Click the Generate button which will pop up a window as shown in Figure 7 36 Click Save which bring up the window in Figure 7 37 Input the name DEO NANO SOPC and click the save button The compilation will automatically start If there are no errors the generation the window will show a message of success as shown in Figure 7 38 Save changez 22 Save changes to unnamed Figure 7 36 Generate SOPC Epmvtrst nosi bestia builder D E Recent Documents Documents
22. X Extra Extra Info fo X Warning _ Warning Error X Suppressed X Flag Message Location Locate Ec 00 00 00 Figure 7 42 A blank verilog file 34 Type the following Verilog into the blank file as shown in Figure 7 43 The module DEO NANO SOPC is the system created by SOPC Builder and its Verilog can be found in the DEO NANO SOPC v file as shown in 111 TagasiC Terasic DEO Nano User Manual www terasic com www terasic com S RYA pen File Look In E E EX E sope builder jag uart v 17 db myfirst niosii v Recent C3DED SOPC sim onchip memory2 v Documents cpu v led cpu jtag debug madule svaclk cpu jtag debug module Eck cpu debug module wrapper cpu cell cpu nci bench cpu best bench DEO SOPC ptf DEO SOPC sopc DEO SOPC sopcinfo NANG SOPC v NANO vy Desktop My Documents Computer My Network File name SUPE v Places Files of type Design Files td vid vhdl venlog oF Add file to current project Open as Auto Figure 7 44 and Figure 7 45 module myfirst niosii 50 LED input 50 output 7 0 DEO SOPC DEO inst 50 CLOC
23. right click the hello world 0 project select Run As gt NIOS II Hardware The IDE will download the program to the target FPGA development board and begin execution When the target hardware begins executing the program the message from Nios will appear in the NIOS II IDE Console tab as shown in Figure 7 58 for an example Nios II C C hello world c Nios II IDE File Edit Refactor Navigate Search Project Tools Run Window Help 4 m 9n 8 d 5 09 0 49 ite 1 ES WE ios c c Nios II Projects EH 8 hello world c 38 zr 8 altera components LS world 0 lt Binaries E e Includes Debug hello_world application stf E readme txt E ES hello world 0 syslib 115 SOPG include lt stdio h gt int main printf Hello from Nios 4 return 9 Problems Console 22 Properties X gt BE hello world 0 Nios II HW configuration Nios II Hardware Nios II Terminal Window 10 6 17 4 11 48 nios2 terminal connected to hardware target using JIAG UART on cabie nios2 terminal USB Blaster USB 0 device i instance 0 nios2 terminal Use the IDE stop button or Ctri C to terminate lio from Nios II fhello world 0 Figure 7 58 Hello World 0 Program Output Now you have created compiled and run your first software program based on NIOS II And you can perform additional operations such as con
24. under the batch file folder DEO Default batch This will load the demo into the FPGA 131 DEO Nano User Manual www terasic com www terasic com S RYAN 8 3 ADC Reading This demonstration illustrates steps which can be used to evaluate the performance of the 8 channel 12 bit A D Converter The DC 3 3V on the 2x13 header is used to drive the analog signals and by using a trimmer potentiometer the voltage can be adjusted within the range of 0 3 3V The 12 bit voltage measurements are indicated on the 8 LEDs Since there are only 8 LEDs only bit 4 through bit 11 from the ADC are represented on the LEDs B Design Concept This section describes the design concepts for this demo Figure 8 3 shows the block diagram FPGA B mare P 4 ND Convener 2X13 Header Output Control DEO Nano Board Figure 8 3 ADC Reading Block Diagram The ADC Controller reads the voltage from the A D converter through a serial interface and displays its measurement on the LEDs The on board dip switch determines which channel to read from Table 8 1 lists the Switch settings and its corresponding ADC channel 132 Terasic DEO Nano User Manual www terasic com www terasic com Table 8 1 DIP Switch Settings DIP Switch SW1 Setting ADC Channel 0000 Analog InO 0001 Analog In1 0010 Analog In2 0011 Analog In3 0100 Analog
25. 1s available on manufacturer s website or under the datasheet folder of the system CD Up to 13 bit resolution at 16g SPI 3 wire or 2 wire digital interface e Flexible interrupts modes Figure 3 13 shows the connections between the ADXL345 and the Cyclone IV E device VESPO ADXL345 I2C SCLK SCL SCLK 2 SDAT SDA SDI SDIO G SENSOR CS N CS n ENSOR INT Se INT1 INT2 Figure 3 13 Wiring between the ADXL345 and the Cyclone IV E device Table 3 10 Pin Assignments for Digital Accelerometer Signal Name FPGA Pin No Description Standard I2C SCLK PIN F2 EEPROM clock 13 3V I2C SDAT PIN F1 EEPROM data 3 3V G SENSOR INT PIN M2 G Sensor Interrupt 3 _ G SENSOR CS N PIN G5 G Sensor chip select 3 3V 3 8 Clock Circuitry The DEO Nano board includes 50 MHz oscillator The oscillator is connected directly to a dedicated clock input pin of the Cyclone IV E FPGA The 50MHz clock input can be used as a source clock to drive the phase lock loops PLL circuit The clock distribution on the DEO Nano board is shown in Figure 3 14 23 Terasic DEO Nano User Manual www terasic com www terasic com CLOCK 50 Figure 3 14 Block diagram of the clock distribution 3 9 Power Supply The DEO Nano board s power is provided through the USB 5V power the 5V VCC pins on the two 40 pin headers or the 2 pin power header The DC voltage is then stepped d
26. 66 231 100 00 05 23 Figure 6 43 Default SDC Naming the SDC with the same name as the top level file causes the Quartus II software to use this timing analysis file automatically by default If you used another name you would need to add the SDC to the Quartus II assignments file 6 8 Compile Your Design After creating your design you must compile it Compilation converts the design into a bitstream that can be downloaded into the FPGA The most important output of compilation is an SRAM Object File sof which you use to program the device Also the software generates report files that provide information about your circuit as it compiles Now that you have created a complete Quartus II project and entered all assignments you can compile the design In the Processing menu select Start Compilation or click the Play button on the toolbar If you are asked to save changes to your BDF click Yes While compiling your design the Quartus II software provides useful information about the compilation as shown in Figure 6 44 74 Terasic DEO Nano User Manual www terasic com www terasic com S Quartus II E Ny design my first fprga my first fpga my first E Edit View v Project Assignments Processing Tools Window Help Jx rdv ProjectNavigator frst fpga bdf O first_foga bdf E ee simple counter v RE of Contents 1 Flow Summary meti Flow Summar
27. Click the Start button 78 Terasic DEO Nano User Manual www terasic com www terasic com Edit View Processing Tools Window Mode v Progress Enable real time ISP to allow background programming For MAX II and MAX V devices Device Checksum Usercode Program verify Bla p Start Configure Che mv First Fpga sof EPACEZ2ZFl17 O00137CD6 FFFFFFFF Stop p Auto Detect 3X Delete Add File is Change File Save File 22 Add Device t Up Down Figure 6 48 Downloading Complete Congratulations you have created compiled and programmed your first FPGA design The compiled SRAM Object File sof is loaded onto the FPGA on the development board and the design should be running 6 10 Verify The Hardware When you verify the design in hardware you observe the runtime behavior of the FPGA hardware design and ensure that it is functioning appropriately Verify the design by performing the following steps 1 Observe that the four development board LEDs appear to be advancing slowly a binary count pattern which 15 driven by the simple counter bits 26 23 The LEDs are active low therefore when counting begins all LEDs are turned on the 0000 state 2 Press and hold KEY 0 on the development board and observe that the LEDs advance more quickly Pressing this KEY causes the design to multiplex using the faster advancing part of the counter bits 24 21 3 LEDs emi
28. E Legacy Components Memories and Memory Contro T 7 Persi Peripherals E PLL Target HDL Verilog Processor Additions Processors SLS 5 University Program Video and Image Processing 2 E B Create New System Figure 7 10 Create New SOPC System 0 6 Rename System Name as shown in Figure 7 10 and Figure 7 11 Click OK and your will see a window as shown in Figure 7 12 Create New System System Mame DEO MANO Target HDL Verilog VHDL BS Figure 7 11 Create New System 1 88 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA Altera 50 Builder Fie Edt Modue System View Tool Help System Contents System Generation Component Library Target Project Device Family Cyclone VE Nam Source M Pe ug Mew component Library Remove Verification Suite m B ridges and Adapters Interface Protocols 3 l Legacy Components 3 and Memory Contra Merlin Components 8 Additions 3 EU niversity Program and Imaae iL i i Figure 7 12 Create New System 2 7 Click the 0 name in the Clock Settings table to rename clk 0 to 50 Press Enter to complete the update as shown in Figure 7 13 Altera SOPC Builder lt Edit Module System View Tools Heb System Contents
29. IV E FPGA which be programmed using JTAG programming This allows users to configure the FPGA with a specified design using Quartus II software The programmed design will remain functional the FPGA as long as the board 1 powered on or until the device 15 reprogrammed The configuration information will be lost when the power 1 turned off To download a configuration bit stream file using JTAG Programming into the Cyclone IV FPGA perform the following steps 1 Connect a USB Mini B cable between a host computer and the DEO Nano 2 The FPGA can now be programmed through the Quartus II Programmer by selecting a configuration bit stream file with the sof filename extension B Configuring Spansion EPCS64 device The DEO Nano board contains a Spansion EPCS64 serial configuration device This device provides non volatile storage of the configuration bit stream so that the information 15 retained even when the power supply to the DEO Nano board is turned off When the board s power 1 turned on the configuration data in the EPCS64 device is automatically loaded into the Cyclone IV E FPGA The Cyclone IV E device supports in system programming of a serial configuration device using the JTAG interface via the serial flash loader design The serial flash loader is a bridge design for the Cyclone IV E device that uses its JTAG interface to access the EPCS file and then uses AS interface to program the EPCS device Fi
30. Ny design my first fpga my first fpga my first fpga Ele Edit View Processing Tools Window 1 Top Vas Vina unns mica ME EACE HETES i ec A e ArH gt gt amed weed i Location I O Bank VREF Group I O Standard Reserved m m E Jm RETE RT I ET 1 B3 NO 5 3 Ey AE 5 10 00 00 00 at Figure 6 42 Completed Pin Planning Example Now you are finished creating your Quartus design 6 7 Create a Default TimeQuest SDC File Timing settings are critically important for a successful design For this tutorial you will create a basic Synopsys Design Constraints File sdc that the Quartus TimeQuest Timing Analyzer uses during design compilation For more complex designs you will need to consider the timing requirements more carefully To create an SDC perform the following steps 1 Open the TimeQuest Timing Analyzer by choosing Tools gt TimeQuest Timing Analyzer 2 Select File gt New SDC file The SDC editor opens 3 the following code into the editor create clock period 20 000 name CLOCK_50 derive pll clocks derive clock uncertainty 4 Save this file as my first fpga sdc see Figure 6 43 73 Terasic DEO Nano User Manual www terasic com www terasic com Seles PT osse first Psy 2 ries d Design Units
31. System Generation Component Library Target Project Device Family z New component Library Remove Avalon Verification Suite and Adapters 4 Interface Protocols Legacy Components Use Module Description Clock Base End and Memory Contra Merlin Components t Peripherals H P Figure 7 13 Rename Clock Name 8 In the left hand side Component Library tree select Library gt Processors gt Nios Processor and click the Add button to open the Nios II component wizard as shown in Figure 7 14 and Figure 7 15 89 Terasic DE0 Nano User Manual www terasic com www 8 Altera SOPC Builder Fie Edit Module System View Took t 8 I Processor University Program H Video and Image Processing Figure 7 14 Add NIOS Il Processor 90 Terasic DEO Nano User Manual www terasic com www terasic com Wios II Processor cpu 0 Nios II Processor Parameter Settings l Advanced Features gt MML and MPL Settings gt JTAG Debug Module gt stom Instructions gt Core Nios II Select a Nios core ONios O Nios ll s E _ RISC IRISC Nios ll 32 bit 32 bit Selector Guide Instruction Cache Family Cyclone Branch Prediction Hardware Multiply l yaten 50 0 MHz Hardware Divide cpuid 0 Performance at 50 0 MHz Up to 8 DMIPS Up to 32 DMIPS Logic Us
32. User Manual www terasic com www terasic com Libraries tI simple counter i EE 9 10 1 quartus ibraries C megafunctions EJ others i gt primitives E3 buffer G logic it E other tl bidir EF output Ed storage Mame output Repeat insert mode Insert symbol as block Launch MegaWizard Plug In MegaWizard Plug In Manager Figure 6 38 Choose output pin 18 Click OK 19 Place this output pin so that it connects to the counter bus mux s result 3 0 bus output line 20 Rename the output pin as LED 3 0 see Figure 6 39 oa xiu E 2 LED 3 U datalx 3 0 i us W JS G6 xe cxlo od M sel Figure 6 39 Rename the output 2 Attach an input pin to the multiplexer select line using an input pin a Right click in the blank area of the BDF and select Insert gt Symbol b Under Libraries double click quartus libraries gt primitives gt pin gt input c Click OK 22 Place this input pin below counter bus mux 23 Connect the input pin to the counter bus mux sel pin 24 Rename the input pin as KEY 0 see Figure 6 40 70 Terasic DEO Nano User Manual www terasic com www terasic com fe 8 3120 inclkO frequency 50 000 MHz CLOCK 5 counter out 31 0 s Operation M
33. a project successfully in the Quartus II software your design om ALTMEMPHY files must be in the project directory in a library specified in the Libraries page of the Options dialog box Tools menu ar a library specified in the Libraries page of the Settings dialog box Assignments menu ALTPLL_RECONFIG Your current user library directories are ALTREMOTE LIPDATE ALTTEMP SENSE Altera PLL v10 1 MAX V oscillator Lp Ob dei ep Figure 6 20 MegaWizard Plug In Manager page 2a Selections 5 In the MegaWizard Plug In Manager page 3 of 14 window make the following selections see Figure 6 21 a Confirm that the currently selected device family option is set to Cyclone IV E b For device speed grade choose 6 for DEO Nano c Set the frequency of the inclockO input 50 MHz 56 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN d Click Next 1 Manager page 3 of 14 E ALTPLL Clock switchover Currently selected device family IV E Match project default Able to implement the requested PLL frequency 52 000 MHz Operation Mote Norma General Which device speed grade will you be using Lise military temperature range devices only What is the frequency of t
34. board including block diagram and components 2 1 Layout and Components The picture of the DEO Nano board is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components FPGA Serial Configuration Device EPCS 32 MB 8 Green LEDs SDRAM 40 Header USB Type mini AB Port IM A E TIBET 2Kb I2C EN EEPROM w EN 4 Dip Switches a Hg c 2 pin External Digital Power Header Accelerometer 1 SOMH2z ER t p f Y le gt gt 50MHz Clock Oscillator 99919999 9 9 2 Push buttons Altera Cyclone IV EP4CE22F17C6N FPGA 26 pin Header A D Converter 40 pin GPIO Header Figure 2 1 The DEO Nano Board PCB and component diagram top view Terasic 0 User Manual www terasic com www terasic com 32MB SDRAM I M M OM ut R42 R40 1 M 8120894 94 0 1 HL9 VO NSM 1 5 1952 T 2 E ql ISR 2X13 Pin PE Header H i Figure 2 2 The DEO Nano Board PCB and component diagram bottom view 2 2 Block Diagram of the DEO Nano Board Figure 2 3 shows the block diagram of the DEO Nano board To provide maximum flexibility for the user all connections are made through the Cyclone IV FPGA device Thus the user can configure the FPGA to imple
35. page displays ly Convert Programming File D CD DE v1 0 9 E f Ele Window Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Conversion Setup Output programming file Programming file type m AG Indirect Configuration File Options Configuration device 564 Made Active Serial File name output file jic m Advanced Remote Local update difference file Memory Map File Input files to convert File Data area Properties Start Address Add Hex Data Flash Loader E SOF Data Add Sof Page Add File Remove Figure 9 1 Convert Programming Files Dialog Box 147 Terasic DEO Nano User Manual www terasic com ON Convert Programming File D CD DE v1 0 9 CDRO E f Elle Window Specify the input files to convert and the type of programming file to generate You can also import input information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type JTAG Indirect Configuration File jic Opt
36. pushbuttons o 4 position DIP switch e G Sensor o ADI ADXL345 3 axis accelerometer with high resolution 13 bit e A D Converter o NS ADCI288022 8 Channel 12 bit A D Converter o 50 to 200 Ksps e Clock system o On board 50MHz clock oscillator e Power Supply o USB Type mini AB port 5V o DC 5V pin for each GPIO header 2 DC SV pins o 2 pin external power header 3 6 5 7V Terasic DEO Nano User Manual www terasic com www terasic com S RYA 1 2 About the KIT The kit comes with the following contents e DEO Nano board e System CD ROM e USB Cable The system CD contains technical documents for the DEO Nano board which includes component datasheets demonstrations schematic and user manual Figure 1 2 shows the photograph of the DEO Nano kit contents Gies DEO Nano ga ue St Altera DEO Nano Board Cope Eom tare USB Mini B Cable DEO Nano System CD O Altera Complete Design Suite Free Package DEO Nano Quick Start Guide Figure 1 2 DEO Nano kit package contents 1 3 Getting Help Here is information of how to get help if you encounter any problem e Terasic Technologies e 886 3 575 0880 e Email support terasic com e Altera Corporation e Email university altera com Terasic DEO Nano User Manual www terasic com www terasic com Chapter 2 DEO Nano Board Architecture This chapter describes the architecture of the DEO Nano
37. terasic com OO Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family Show in Available devices list Family Cyclone IVE v Package Any hl Devices Pin count Any NE Speed grade Auto device selected by the Fitter Show advanced devices 5 Specific device selected in Available devices list HardCopy compatible only Other n a Available devices Fame Core Voltage User I Os Bemory Bits Embedded multiplier 93 bit elements EPACEP EP IBL 1 0V 122320 80 608256 d32 EPACEZ F1TAT 1 2 22320 154 808256 132 EPACEPZFITEB 1 27 122320 154 132 1 I1 154 608256 4 22 17 8 1 21 154 608256 EPACEP FiTCBL 1 0 154 808256 EPACEP F1TCOL 1 01 154 808256 EPACES2F 1717 Em 154 808256 2 itt Companion device HardCopy 1 LimitDSP amp RAM to HardCopy device resources Figure 7 5 New Project Wizard Family amp Device Settings page 3 of 5 4 Click Next and will see a window as shown in Figure 7 7 Figure 7 7 is a summary about the new project Click Finish to complete the New Project Wizard Figure 7 8 show the new project 85 Terasic DEO Nano User Manual www terasic com www terasic com X Project Wizard EDA Tool Settings page 4 of 5 Specify the other EDA tools used with the Quartus II software to develop your
38. the Folder that contains drivers Far your hardware 10 1 E3 installer niosZeds 3 quartus bin bin amp 4 common cusp drivers i386 sentinel usb blaster x32 dep builder ia eda view any subfolders click a plus sign above Figure 6 5 Browse to find the location Hardware Installation The software you are installing for this hardware Altera USB Blaster has not passed Windows Logo testing to verify its compatibility with Windows Tell me why this testing important Continuing your installation of this software may impair or destabilize the correct operation of your system either immediately or in the future Microsoft strongly recommends that you stop this installation now and contact the hardware vendor software that haz passed Windows Logo testing Continue Anyway STOP Installation Figure 6 6 There is no need to test the driver 44 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA The driver will now be installed as indicated in Figure 6 7 Click Finish and you can start using the DEO Nano board Found Mew Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software Far Altera USB Blaster Click Finish to clase the wizard Back Cancel Figure 6 7 The driver is installed 6 3 What You Will Learn In this tutorial
39. you will build and run the program To build the program right click the hello world 0 project in the Nios C C Projects tab and select Build Project The Build Project dialog box appears and the IDE begins compiling the project When compilation completes a message Build complete will appear in the Console tab as shown in Figure 7 57 Il C C 110 Nios II IDE File Edit Refactor Havigate Search Project Tools Eun Window Help Tm ae dm 839 7 lef Or Qe Ti NE vies C C lt lt II Projects 77 O helloworld 2 E E TEE iltera Ie hello werld n ffl gt Binaries a Includes 6 5 Debug Ex hello world i application stf i readme txt E hello world 0 syslib DE 5 Ep a Uu j Figure 7 57 Nios Il IDE hello world 0 Build Completed Note If there appears in the console tab an error region onchip_memory2 is full hello world 0 elf section text Region needs to be XXX bytes larger please right click hello world 0 select System Library Properties menu then pop a window In the System Library Properties window select Small C Library then click OK to close the window Rebuild the project 123 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA After a successful compilation
40. 0 00014 3 3V 0 2 Regulator LP385005D ADJ 12 0 654 1 5A output 5V power pins On two 40 pin GPIO Headers USB PHY FT245BL VCCA EPACE22 EPCS16 amp 24LCO2B VCCIO EPACE22 VDD amp VDDQ SDRAM VCCINT amp VCCIO MAX Il EPM240 ADXL345 amp VDDIO 3 3V power pins of two 40 pin GPIO headers VCCINT EP4CE22 Figure 3 16 0 Power Distribution System 29 Terasic 0 User Manual www terasic com www terasic com Chapter 4 DEO Nano Control Panel The DEO Nano board comes with a Control Panel facility that allows users to access various components on the board from a host computer The host computer communicates with the board through a USB connection The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 4 1 Control Panel Setup The Control Panel Software Utility is located in the directory tools DEO ControlPanel in the DEO Nano System CD It s free of installation just copy the whole folder to your host computer and launch the control panel by executing the DEO NANO ControlPanel exe When Control Panel starts 1 will attempt to download a configurat
41. 0 Change the input port name 2 Right click the new output bus line and select Properties 3 counter 31 0 as the bus name see Figure 6 31 The notation X Y is the Quartus II method for specifying the bus width in BDF schematics where X 1 the most significant bit MSB and Y 1s the least significant bit LSB 4 Click OK Figure 6 32 shows the BDF 64 Terasic DEO Nano User Manual www terasic com www terasic com Hide name in block design file Cet Cree EE T T Lo Ccounter 11 0 oe incik frequency 50 000 MHz CLOCKS counter out 31 0 m Operation Mode Normal i co 1 10 0 00 50 00 Figure 6 32 Circuit schematic BDF B Adding a Multiplexer to the Schematic This design uses a multiplexer to route the simple counter output to the LED pins on the DEO Nano development board You will use the MegaWizard Plug In Manager to add the multiplexer The design multiplexes two portions of the counter bus to four LEDs on the DEO Nano board The following steps describe how to add a multiplexer to the schematic 65 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA 1 Right click in the blank area of the BDF and select Insert gt Symbol 2 Click Megawizard Plug in Manager 3 Click Next 4 Select Installed Plug Ins gt Gates gt LPM 5 Select the Cyclone IV E device family Verilog
42. 18 GPIO 19 GPIO 010 GPIO 011 GPIO 110 bie GPIO 111 GPIO 012 s GPIO 013 GPIO 112 GPIO 113 GPIO 014 _015 _114 bios GPIO 115 GPIO 016 20 GPIO 017 GPIO 116 pi GPIO 117 GPIO 018 2 019 GPIO 118 n s GPIO 119 GPIO 020 bx GPIO 021 GPIO 120 pa GPIO 121 GPIO 022 Ps GPIO 023 GPIO 122 GPIO 123 21 k GPIO 024 nri GPIO 025 GPIO 124 e GPIO 125 GPIO 026 2 GPIO 027 GPIO 126 GPIO 127 GPIO 028 nim GPIO 029 GPIO 128 GPIO 129 GPIO 030 GPIO 031 GPIO 130 GPIO 131 GPIO 032 GPIO 033 GPIO 132 GPIO 133 Figure 3 8 Pin arrangement of the GPIO expansion headers The pictures below indicate the pin 1 location of the expansion headers Signal Name GPIO 0 INO GPIO 00 GPIO 0 IN1 GPIO 01 Tasic Terasic www 4 P012860013 eles 941 0 DE HLS VO snan 1240 e 1 rm 5 c gt 1 in 1 TT PHNH gt 1 O 3 Figure 3 9 Pin1 locations of the GPIO expansion headers Table 3 6 GPIO 0 Pin Assignments FPGA Pin No Description PIN A8 GPIO Connection DATA PIN D GPIO Connection DATA PIN B8 GPIO Connection DATA PIN C3 GPIO Connection DATA DEO Nano User Manual 18 i Pin 1 3 M MN MM R42 R40 o
43. 3V DRAM CS N PIN P6 SDRAM Chip Select 3 3V 3 4 12 Serial EEPROM The DEO Nano contains a 2Kbit Electrically Erasable PROM EEPROM The EEPROM is configured through a 2 wire I2C serial interface The device is organized as one block of 256 x 8 bit memory The I2C write and read address are Ox AO and OxA1 respectively Figure 3 7 illustrates its connections with the Cyclone IV FPGA 16 Terasic DEO Nano User Manual www terasic com www terasic com VCC3P3 I2C SCLK I2C SDAT Figure 3 7 Connections between FPGA and EEPROM Table 3 5 Pin Assignments for I2C Serial EEPROM Signal Name FPGA Pin No VO Standard 2C SCLK PINF2 EEPROM clock I2C_SDAT PIN_F1 EEPROM data 3 5 Expansion Headers The DEO Nano board provides two 40 pin expansion headers Each header connects directly to 36 pins of the Cyclone IV E FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Figure 3 8 shows the I O distribution of the GPIO connectors Terasic DEO Nano User Manual www terasic com www terasic com GPIO 0 GPIO 1 JP1 JP2 GPIO 0 INO a alk GPIO 00 GPIO 1 INO e a lE GPIO_10 GPIO 0 IN1 MEA GPO9O1 GPIO 1 IN1 GPO GPIO 02 MEG GPIO 03 GPIO 12 MEM GC GPO 13 GPIO 04 MENS GPIO_05 GPIO 14 MEM S GPO 5 GPIO 06 10 07 GPIO 16 10 17 12 12 SYS U SPIO 08 3 hs 09 CCS YS O SbIO
44. 50PC Builder System Contents System Generation Avalon Verification Suite Bridges and Adapters Interface Protocols Legacy Components i Memories and Memory Controllers Components gt j Peripherals i Debug and Performance Display Peripherals Microcontroller Peripherals g Interval Timer Parallel O 8 Multiprocessor Coordination i Processor Additions Target Clock settings Device Family Cyclone instruction master data master itag uart awvalon slawe E onchip memory 1 pio 0 1 Source Avalon Memory Mapped Slave JTAG UART Avalon Memory Mapped Slave On Chip Memory RAM or ROM Avalon Memory Mapped Slave FIC Parallel vO Avalon Memory Mapped Slave i C Error cpu instruction master onchip_memory2 s1 cannot be at 0x 2000 or Ox 10000 are acceptable Error cpu data master onchip memory2 s1 cannot be at 0x2000 0x0 or 0x10000 acceptable TEN Figure 7 32 PIO 21 Rename pio 0 to pio led as shown in Figure 7 33 Altera SOPC Builder File Edit Module System View Tools system Contents System Generation Project Mew component Library amp j Avalon Verification Suite Bridges and Adapters interface Protocol i Legacy Components i Memories and Memory Controllers i Merlin Components Peripherals E Debug and Performance i Display Peripherals zi Microcontrolle
45. 9 4 Copyright Statement Copyright 2012 Terasic Technologies All rights reserved Always visit the DEO Nano webpage for new applications We will continue providing interesting examples and labs on our DEO Nano webpage Please visit www altera com or DEO Nano terasic com for more information 154 Terasic DEO Nano User Manual www terasic com www terasic com IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated TI reference designs are solely intended to assist designers Buyers who are developing systems that incorporate semiconductor products also referred to herein as components Buyer understands and agrees that Buyer remains responsible for using its independent analysis evaluation and judgment in designing Buyer s systems and products TI reference designs have been created using standard laboratory conditions and engineering practices has not conducted any testing other than that specifically described in the published documentation for a particular reference design may make corrections enhancements improvements and other changes to its reference designs Buyers are authorized to use reference designs with the component s identified in each particular reference design and to modify the reference design in the development of their end products HOWEVER NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENS
46. CPU Please parameterize the CPU to resolve this issue E Warning cpu 0 Reset vector and Exception vector cannot be set until memory devices are connected to the Nios ll processor Figure 7 16 Add Nios Il CPU completely 10 Select the cpu 0 component and right click then select rename after this you can update cpu 0 to cpu as shown in Figure 7 17 and Figure 7 18 92 Terasic DEO Nano User Manual www terasic com www terasic com Altera SOPC Builder System Contents System Generation Avalon Verification Suite Bridges and Adapters Interface Protocol Legacy Component Memories and Memory Controller Merlin Components Peripherals PLL Processor Additions Processors SLS Universiby Program Widen and Image Processing Fie Edt Module System View Tools Connections Li Mapped Master Print Show Connected Default All Clocks Awalon ST Edit CtrltE Remove Details Show Arbitration To Do cpu 0 reset vector has been specified for this CPU Plea CJ To De epu 0 No exception vector has been specified for this CPU E Warning cpu 0 Reset vector and Exception vector cannot be set ur Altera SOPC B Builder system Contents System Generation FE Avalon Verification Suite i Bridges and Adapters H Interface Protocols i Legacy Components H Memories and Memory Controle Components Peripherals i PLL i Processor Additio
47. DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA Table 3 7 GPIO 1 Pin Assignments FPGA Pin No PIN T9 PIN F13 PIN R9 PIN T15 PIN T14 PIN T13 PIN R13 PIN T12 Description GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA GPIO Connection DATA 19 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com JA DTE RIA GPIO_16 PIN_R12 GPIO Connection DATA 3 3V GPIO_17 PIN_T11 GPIO Connection DATA 3 3V GPIO_18 PIN_T10 GPIO Connection DATA 3 3V GPIO_19 PIN_R11 GPIO Connection DATA 3 3V GPIO_110 PIN_P11 GPIO Connection DATA 3 3V GPIO_111 PIN_R10 GPIO Connection DATA 3 3V GPIO_112 PIN_N12 GPIO Connection DATA 3 3V GPIO_113 PIN_P9 GPIO Connection DATA 3 3V GPIO_114 PIN N9 GPIO Connection DATA 3 3V GPIO_115 PIN_N11 GPIO Connection DATA 3 3V GPIO_116 PIN_L16 GPIO Connection DATA 3 3V GPIO_117 PIN K16 GPIO Connection DATA 3 3V GPIO_118 PIN_R16 GPIO Connection DATA 3 3V GPIO_119 PIN_L15 GPIO Connection DATA 3 3V GPIO_120 PIN_P15 GPIO Connection DATA 3 3V GPIO_121 PIN_ P16 GPIO Connection DATA 3 3V GPIO_122 PIN_R14 GPIO Connection DATA 3 3V GPIO_123 PIN_N16 GPIO Connection DATA 3 3V GPIO_124 PIN_N15 GPI
48. DE NANO SOPC for hierarchy DE SOPC DE SOPC inst d Info Elaborating entity cpu jtag debug module arbitrator for hierarchy DE SOPC DE SOPC in 3 d Info Elaborating entity cpu data Master ar rbitrator ior hierarchy DE SOPC DE SOPC inst cpu d Info Elaborating entity cpu instruction master arbitrator for hierarchy DE NANO SOPC DE NANO SOPC i v lUl gt Critical Warning 5 Suppressed 10 System 268 Extra Info Info 245 Warning 18 Locate i Messaae 0 of 957 Location 100 00 01 45 Figure 7 49 Compile project completely 38 Now we will assign the inputs and outputs of the circuit to specific pins Select Assignments gt Pin Planner from the menubar as shown in Figure 7 50 The pin planner is shown in Figure 7 51 myfirst niosii myfirst niosii myfir Device Settings Sh TimeQuest Timing Analyzer Wizard Ctrl 5hift A Ctrl Shift N Assignment Editor amp Pin Planner Remove Assignments Back Annotate Assignments 5 Import Assignments Export Assignments LogicLock Regions Window Design Partitions Window ul Figure 7 50 Pins menu 116 Terasic DEO Nano User Manual www terasic com www terasic com P Node Name Direction Location I OBank VREFGroup J OStandard Reserved i CLOCK 50 Input 2 5 V default EP LED 7 Output 2 5 V d
49. DE NANO SOPC _ X Lacate 11 3 00 00 29 Figure 7 48 Execute Compile 115 Terasic DEO Nano User Manual www terasic com OO S RYAN 37 A dialog box will appear upon successful completion of the compile as shown in Figure 7 49 Quartus II D myfirst niosii myfirst niosii myfirst niosii 1 Edi Project Processing Tools Window Help TII gd amp Ca XY 2qu Project Navigator gnments Orr s Oo Bal myfirst_niosii v deh Compilation Report DON Summary Entity Successful Thu Jan 13 18 01 03 Cyclone IV E EP4CE22F 17C6 E pbs myfrst E g DE SOPC DE SOPC in 5 Flow Settings us Flow Non Default Global Settings Flow Elapsed Time Quartus II Version Revision Name Topdevel Entity Name 10 1 Build 153 11 29 2010 53 Full myfirst niosii myfirst Cydone IV BBS sid hub auto hub Final 2 759 22 320 12 2 479 22 320 11 1 665 22 320 7 e Flow OS Summary T Quartus 11 Tota combinational functions Dedicated logic registers 1665 Files WP Design Units 1154 6 Module is Compilation P Analysis amp Synthesis Fitter Assembler 271 360 608 256 45 4 132 3 0 4 0 96 76 Progress gt Type Message d Info Elaborating entity
50. E TO ANY THIRD PARTY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI TI REFERENCE DESIGNS ARE PROVIDED AS IS TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THE REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS EXPRESS IMPLIED OR STATUTORY INCLUDING ACCURACY OR COMPLETENESS TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE QUIET ENJOYMENT QUIET POSSESSION AND NON INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES HOWEVER CA
51. ED 2 PIN B13 LED Green 2 3 3V LED 3 PIN A11 LED Green 3 3 3V LED 4 PIN D1 LED Green 4 3 3V LED 5 PIN F3 LED Green 5 3 3V LED 6 PIN B1 LED Green 6 3 3V LED 7 PIN_L3 LED Green 7 3 3V Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA Table 3 3 Pin Assignments for DIP Switches Signal Name FPGA Pin No DIP Switch 0 PIN_M1 DIP Switch 1 PIN_T8 DIP Switch 2 PIN_B9 DIP Switch 3 PIN M15 3 3 SDRAM Memory Description Standard DIP Switch 0 3 3V DIP Switch 1 3 3V DIP Switch 2 3 3V DIP Switch 3 3 3V The board features a Synchronous Dynamic Random Access Memory SDRAM device providing 32MB with a 16 bit data lines connected to the FPGA The chip uses 3 32V LVCMOS signaling standard signals are registered on the positive edge of the clock signal DRAM_CLK Connections between the FPGA and SDRAM chips are shown in Figure 3 6 ANU S n VAN IV DQ 15 0 DRAM ADDR 12 0 DRAM 01 DRAM CLK DRAM CKE DRAM WE N DRAM CAS N DRAM RAS N DRAM CS N DRAM BAO DRAM SDRAM 16MX16 Figure 3 6 Connections between FPGA and SDRAM Table 3 4 SDRAM Pin Assignments Signal Name FPGA Pin No DRAM ADDR O PIN P2 DRAM ADDR 1 PIN N5 DRAM ADDR 2 PIN N6 DRAM ADDR 3 PIN 8 DRAM_ADDR 4 PIN_P8 DRAM_ADDR 5 PIN T7 DRAM ADDR 6 PIN N8 DRAM ADDR 7 PIN T6 DRAM ADDR S PIN R1 DRAM ADDR 9 PIN P1 DRAM ADDR 10 PIN N2 DRAM ADDR 11 PIN N1
52. EY O 0 Input Group LED 3 0 Output Group lt lt new group gt mI GL 2D uw MN x Named Edit Fitter Pins all Direction Location 1 0 Bank VREF Group I O Standard CLOCK 50 Input 2 5 V default KEY O Input 2 5 V default 4 LED 3 Output 2 5 V default LED Z Output 2 5 V default LED 1 Output 2 5 V default LED O Output 2 5 V default z new node Reserved 0 00 00 00 Figure 6 41 Pin Planner Example 2 In the Location column next to each of the six node names add the coordinates pin numbers as shown in Table 6 1 for the actual values to use with your DEO Nano board Table 6 1 Pin Information Setting Double click the Location column for any of the six pins to open a drop down list and type the location shown in the table Alternatively you can select the pin from a drop down list For example if you type F1 and press the Enter key the Quartus II software fills in the full PIN location name for you The software also keeps track of corresponding FPGA data such as the I O bank and VREF Group Each bank has a distinct color which corresponds to the top view wire bond drawing in the upper right window as shown in Figure 6 42 72 Terasic DEO Nano User Manual www terasic com OO OO eee sae Pin Planner E
53. File New Verilog HDL File and click OK as shown in Figure 7 40 and Figure 7 41 Quartus II D myfirst niosii my Project Assignments Processing Ctrl N Col shitt s Recent Files Recent Projects Exit Figure 7 40 New Verilog file Mew Quartus II Project SOPC Builder System E Design Files z Block Diagram Schematic File Be Osys System File State Machine File SystemVerilog HDL File Script File fe verilodg HOL File Files Hexadecimal Intel Format File i Memory Initialization File z Verification Debugging Files In System Sources and Probes File H Logic Analyzer Interface File i SignalTap II Logic Analyzer File B Other Files gt AHDL Include File H Block Symbol File Chain Description File H Synopsys Design Constraints File Text File Figure 7 41 New Verilog File 110 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 33 Figure 7 42 show a blank Verilog file Quartus II D myfirst niozsii myFirzt niosii1 myFirst ninzii Mij d Bile Edit View Project Processing Tools Window D cm a c nas ff niosii w xe ee 7 GR SF db e MA Pets 25 Eb UT Iw Project Navigator Emu v d Cyclone IV EPACE22F 17C6 myfirst niosii Hierarchy Files B Design Units Status x Module 7 Progress C9 Time ssage System Processing
54. Finish again 59 Terasic DEO Nano User Manual www terasic com www terasic com NegzaWizard Plug In Manager page 12 of 12 _about_ Documentation 5 Summary Turn on the files you wish to generate gray checkmark indicates file that is automatically generated and green checkmark indicates an optional Click Finish to generate the selected files The state of each checkbox is maintained in subsequent MegaWizard Plug In Manager sessions The MegaWizard Plug In Manager creates the selected files in the following directory designimy first fpga File Description nil Variation file pll ppf PinPlanner parts PPF file pil inc AHDL Include file pil cmp VHDL component dedaration file pll bsf Quartus II symbol file inst v Instantiation template file pll bb v Verilog HDL black box file Figure 6 24 Wizard Created Files The Symbol window opens showing the newly created PLL megafunction a s shown in Figure 6 25 60 Terasic DEO Nano User Manual www terasic com www terasic com Libraries E Project tl counter bus mux EJ simple counter ES FiuguarkusiD 1 fquartus libraries inclk frequency 50 000 Operation lade Cik Ratio Ph dg DC 3 50 00 1 10 Repeat insert mode Insert symbol as block Launch Megawizard Plug In MegaWizard Plug In Manager Figure 6 25 PLL Symbol 11 Click O
55. HDL as the output file type and name the output file counter bus mux v as shown in Figure 6 33 6 Click Next X NezaWizard Plug In page 2 Which megafunction would you like to customize wich device Wil you Cydone Select megafunction from the list below Which type of output file do you want to create Altera SOPC Builder Arithmetic VHDL T3 Communications LL pse E What name do you want for the output file EN cone E My desian my first fpga counter bus mux v A LPM DECODE Verilog HDL Return to this page for another create operation L1 10 Interfaces Note To compile a project successfully in the Quartus II software your design JTAG accessible Extensions files must be in the project directory in a library specified in the Libraries page of the Options dialog box Tools menu ar a library specified in the Libraries page of the Settings dialog box Assignments menu E Memory Compiler kt Your current user library directories are Cancel Figure 6 33 Selecting 7 Under How many data inputs do you want select 2 inputs default 8 Under How wide should the data input and the result output buses be select 4 as shown in Figure 6 34 66 Terasic DEO Nano User Manual www terasic com www t
56. IRA DE a WERTE EET Wir WU WI WO VERI CRT o Ry ERR EAT ET ER ET SR RT Cyclone IV E EPACE27F 17C6 gt my frst dil amp Hierarchy Compilat Compilation _ Compile Design Analysis amp Synthesis Fitter Place amp Route D gt Assembler Generate pi TimeQuest Timing Analy B d Y P EDA Netlist Writer _ 15 B Message System Processing Extra Info JX Info Warning X Critical Warning Error X Suppressed Flag 2 Message amp Locate 633 218 0 00 00 00 Messages Figure 6 13 Bank BDF B Adding a Verilog HDL to the Schematic 1 Add HDL code to the blank block diagram by choosing File gt New gt Verilog HDL File 2 Select Verilog HDL File in the tree and Click OK 3 Save the newly created file by selecting File gt Save As and entering the following information see Figure 6 14 e File name simple counter v e Save as type Verilog HDL File v vlg verilog 51 Terasic DEO Nano User Manual www terasic com www terasic com Save As Save In mw first fpga db greybox _tmp My Recent yincremental db counter bus cou
57. In4 0101 Analog In5 0110 Analog In6 0111 Analog In7 Figure 8 4 depicts the pin arrangement of the 2X13 header Connect the trimmer to the ADC channel which is selected by the DIP Switches Analog InO Analog In7 133 Terasic DEO Nano User Manual www terasic com www terasic com JP3 2 HDR26 INO 4 HDR26 IN2 6 HDR26 01 g HDR26 03 O HDR26 IN1 HDR26 DO HDR26 D2 HDR26 D4 9 40 HDR26 D5 HDR26 D6 411 12 HDR26 D7 HDR26 D8 13 44 HDR26 D9 HDR26 D10 15 HDR26 D12 1 1 116 HDR26 D11 18 Analog In5 20 Analog In 22 Analog In2 Analog 1 0 126 zi ae E 2X13 HEADER Analog Analog_In3 23 25 Analog 1 4 E REM A3 M M M M MN M MN E Analog In1 Figure 8 4 2X13 Header B System Requirements The following items are required for the ADC Reading demonstration e DEO Nano board x1 e Trimmer Potentiometer x1 e Wire Strip x3 B Hardware Setup e ligure 8 5 shows the hardware setup for the ADC Reading demonstration 134 Terasic DEO Nano User Manual www terasic com www terasic com JG EN umm RRO 5 Os So 95 9 rl IU aec rH 1 1T T 727 224222454062421241 JE MEOS M MEM HM OMM Figure 8 5 ADC Reading hardware setup Note the setup shown above 1 connected ADC channel 1 Demonstration Source Code e P
58. K 50 out port from the pio led LED Ieset n 1 b1 endmodule 112 Terasic DEO Nano User Manual www terasic com Cancel EA www terasic com Zo Quartus II D myfirst niosii myfirst niosii myfirst niosii File Edit View Project Assignments Processing Tools Window 5 5 O44 0 SS 98 5 Xj abe myfirst_niosii v 9 ES dy Cyclone IV E EP4CE22F 17C6 259 myfirst Major Functions myfirst niosii fi Ejmoduie myfirst niosii Bt CLOCK 50 LED input CLOCK 50 output 7 0 LED DEO NANO SOPC DEO NANO SOPC inst Out port from the pio led LED reset n 1 b1 endmodule Hierarchy Files e Design Units File Look In E mufirst amp j E Documents Desktop My Documents E Network Places fF Author Mod Date V1 0 Yaqun chang 02 16 2011 clk 50 CLOCK 50 BART 4 05 DB B Changes Made Initial Revis Figure 7 43 Input verilog Text I builder Ede myfirst_niosii v DEO SOPC sim memoarwvz v cpu v led cpu jtag debug madule svaclk w E cpu jtag debug madule Eck cpu debug module wrapper c
59. K and place pll symbol onto the BDF to the left of the simple counter symbol You can drag and drop the symbols if you need to rearrange them See Figure 6 26 inclk frequency 50 000 MHz counter out 31 0 Operation Made Normal cO 110 0 00 50 00 Figure 6 26 Place the PLL Symbol 12 Move the mouse so that the cursor also called the selection tool is over the pll symbol s cO output pin The orthogonal node tool cross hair icon appears 13 Click and drag a bus line from the c0 output to the simple counter clock input This action ties the pll output to the simple counter input see Figure 6 27 61 1 Terasic DEO Nano User Manual www terasic com www terasic com frequency 50 000 MHz counter out 31 0 Operation Mode Normal co 110 0 00 50 00 Figure 6 27 Draw a Bus Line connect pll c0 port to simple counter CLOCK 5 port B Adding an Input pin to the Schematic The following steps describe how to add an input pin to the schematic 1 Right click in the blank area of the BDF and select Insert gt Symbol 2 Under Libraries select quartus libraries gt primitives gt pin gt input See Figure 6 28 3 Click OK If you need more room to place symbols you can use the vertical and horizontal scroll bars at the edges of the BDF window to view more drawing space megafunctions others EF primitives buffer H 3 logic other i
60. O Connection DATA 3 3V GPIO_125 PIN P14 GPIO Connection DATA 3 3V GPIO_126 PIN L14 GPIO Connection DATA 3 3V GPIO_127 PIN_N14 GPIO Connection DATA 3 3V GPIO_128 PIN_M10 GPIO Connection DATA 3 3V GPIO_129 PIN_L13 GPIO Connection DATA 3 3V GPIO_130 PIN_J16 GPIO Connection DATA 3 3V GPIO_131 PIN_K15 GPIO Connection DATA 3 3V GPIO_132 PIN_J13 GPIO Connection DATA 3 3V GPIO_133 PIN_J14 GPIO Connection DATA 3 3V 3 6 A D Converter and 2x13 Header The DEO Nano contains an ADC128S022 lower power eight channel CMOS _ 12 bit analog to digital converter This A to D provides conversion throughput rates of 50 ksps to 200 ksps It can be configured to accept up to eight input signals at inputs INO through IN7 This eight input signals are connected to the 2x13 header as shown in Figure 3 10 The remaining I Os of the 2x13 header are a DC 3 3V VCC33 a GND and 13 pins which are connect directly to the Cyclone IV E device For more detailed information on the A D converter chip please refer to its datasheet which 1s available on manufacturer s website or under the datasheet folder of the system CD 20 Terasic DEO Nano User Manual www terasic com www terasic com JP3 2 GPIO 2 INO 4 GPIO 2 IN2 VCC3P3 Q GPIO 2 IN1 GPIO 20 6 GPIO 21 GPIO 22 8 GPIO 23 GPIO 24 10 GPIO 25 GPIO 26 GPIO 28 GPIO 210 GPIO 212 Analog In6 12 GPIO 27 14 GPIO 29 16 GPIO 211 18 Analog In5 120 Analog In7 22 Analog In2 24 An
61. O Nano Control Panel is illustrated in Figure 4 2 The Control Circuit that performs the control functions is implemented in FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to 1ssue commands to the control circuit It handles all requests and performs data transfers between the computer and the DEO Nano board Accelerometer l lt lt Button Switch Om USB Blaster Figure 4 2 The DEO Nano Control Panel concept 27 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA The DEO Nano Control Panel can be used to light up LEDs change the buttons switches status read write to SDRAM Memory read ADC channels and display the Accelerometer information 4 2 Controlling the LEDs A simple function of the Control Panel is to allow setting the values displayed on LEDs Choosing the LED tab displays the window in Figure 4 3 Here you can directly turn the LEDs on or off individually or by clicking Light or Unlight Switches Memory 5 Accelerometer Figure 4 3 Controlling LEDs 4 3 Switches and Pushbuttons Choosing the Switches tab displays the window in Figure 4 4 The function is designed to monitor the status of slide switches and pushbuttons in real time and show the status in a graphical user interface It
62. Quartus II software The computer will recognize the new hardware connected to its USB port but it will be unable to proceed if it does not have the required driver already installed If the USB Blaster driver 15 not already installed the New Hardware Wizard in Figure 6 2 will appear 4 Terasic DEO Nano User Manual www terasic com www terasic com Welcome the Found New Hardware Wizard windows will search for current and updated software looking on your computer on the hardware installation CD ar on the Windows Update Web site with your permission Read our privacy policy Can Windows connect to Windows Update to search for software C2 Yes this time only Yes now and every time connect device No this time Click Hest to continue Figure 6 2 Found New Hardware Wizard The desired driver is not available on the Windows Update Web site therefore select No not this time and click Next This leads to the window in Figure 6 3 Hardware Update Wizard Welcome to the Hardware Update Wizard This wizard helps you install software For LIS B Blaster If your hardware came with an installation CD ar floppy disk insert it now What do you want the wizard to do CO Install the software automatically Recommended Install from list or specific location Advanced Click Next to continue Figure 6 3 The driver is found in a specific location 42 Terasic DEO N
63. SPI Timing Diagram B EEPROM Control EEPROM 1 accessed through the I2C interface In this demo I2C signal 1 toggle by NIOS II through the PIO controller The I2C clock signal is driver by an OUTPUT PIO Controller and the 2 data signal is driver by a BIDIRECTION PIO Controller The I2C C code is located in DEO SOPC DEMOYNsoftwareNDEO libM2C c B EPCS Control EPCS64 1 accessed through the EPCS interface In Quartus 10 0 or later the EPCS pin assignment is required and should be connected the pins to EPCS Controller as shown below Figure 8 12 the epcs datal to the epcsiEPCS dclk from the epes EPCS DCLEK from the epcsi EPCS NCSO sdo from the epes EPCs ASDOj Figure 8 12 EPCS interface connection For the EPCS access functions users can refer to DEO SOPC DEMOYNsoftwareNDEO NANO terasic_lib Flash c 139 Terasic 0 User Manual www terasic com www terasic com JA DTE RA Demonstration Source Code e Project directory DEO SOPC DEMO e Bit stream used DEO NANO sof e NIOS II elf file DEO NANO elf Demonstration Batch File e Demo Batch File Folder DEO SOPC DEMOdemo batch The demo batch file includes the file e Batch File test bat and test bashrc e FPGA Configure File DEO NANO sof e Nios Program DEO NANO elf Demonstration Setup Make sure Quartus II and Nios II are installed on your PC e C
64. Slave a Fs et Error cepu instruction master onchip memoryz s1 cannot be at 0x2000 0 0 010000 are acceptable Error cpu data master onchip memory2 51 cannot be at 0x2000 00 or 010000 are acceptable Figure 7 29 Updated CPU settings 19 Add the Library gt Peripherals gt Microcontroller Peripherals gt PIO Parallel component to the system as shown in Figure 7 30 and Figure 7 31 103 Terasic DEO Nano User Manual www terasic com www terasic com 8 Altera SOPC Builder File Edi Module System View Tool Help Verification Suite and Adapters i Interface Protocols Legacy Components m Memories and Memory Controlers Figure 7 30 Add PIO 104 Terasic 0 User Manual www terasic com www terasic com Parallel 1 0 pio 0 PIO Parallel I O Megotore altera avalon pia 7 Block Diagram clock reset reset avalon Ms conduit external connection Width 1 32 bits I Input Output Port Reset Value 0x0000000000000000 7 Output Register Synchrunausiy capture Edge Type RISING Enable tit clearing Tor edge capture register Figure 7 31 Add PIO 20 Click Finish to use the default settings for this component This closes the PIO wizard and returns to the window shown in Figure 7 32 105 www terasic com 1 Terasic DE0 Nano User Manual www terasic com Altera
65. Software Select Target Hardware SOFC Builder System PIF File D myfirst niosiiVDE 50 ptf CPU cpu Select Project Template Blank Project Description Board Diagnostics Prints Hello from Hios Lount Binary Hello Freeztanding Details Hello 05 Hello World Hello World prints Hello from Nios II to STDOUT Hello World Small i Memory Test This example runs with or without the MicroC Z II RTOS Memory Test Small and requires an STDOUT device in your system hardware simple Socket Server Simple Socket Server ROMII Rn Wap ossis For details click Finish to create the project and refer Web Server to the readme txt file in the project directory Figure 7 55 Nios Il IDE New Project Wizard 5 Click Finish The NIOS II IDE creates the hello world 0 project and returns to the NIOS II C C project perspective as shown in Figure 7 56 121 Terasic DEO Nano User Manual www terasic com www terasic com NHios C C hello world c Nios II IDE File Edit Refactor Navigate Search Project Tools Run Window Help rji i 8 HO Q i 4 iter i B Fle Eno gt Projects 2 H altera components 5 hello world 0 ut hello world 0 syszlib DE SOPC include lt stdio h gt int main printf Hello from Nio return 9 i Problems 25 Console Properties 0 errors 0 warnings 0 infos Des
66. TE RYA 15 Add input buses and output pins to the counter bus mux symbol as follows a Using the Orthogonal Bus tool draw bus lines from datalx 3 0 and dataOx 3 0 input ports to about 8 to 12 grid spaces to the left of counter bus mux b Draw a bus line from the result 3 0 output port to about 6 to 8 grid spaces to the right of counter bus mux c Right click the bus line connected to datalx 3 0 and select Properties d Name the bus counter 26 23 which selects only those counter output bits to connect to the four bits of the datalx input Because the input busses to counter bus mux have the same names as the output bus from simple counter counter x y the Quartus II software knows to connect these busses e Click OK f Right click the bus line connected to data0x 3 0 and select Properties Name the bus counter 24 21 which selects only those counter output bits to connect to the four bits of the datalx input h Click OK Figure 6 37 shows the renamed buses heme dto peus ts counter bus mux 24 21 TT ocounteq26 22 data1x 3 0 Figure 6 37 Renamed counter bus mux Bus Lines If you have not done so already you may want to save your project file before continuing 16 Right click in the blank area of the BDF and select Insert Symbol 17 Under Libraries select quartus libraries gt primitives gt pin gt output as shown in Figure 6 38 69 Terasic DEO Nano
67. Terasic DEO Nano User Manual www terasic com Description I O Standard Address 0 3 3V SDRAM Address 1 3 3V SDRAM Address 2 3 3V SDRAM Address 3 3 3V SDRAM Address 4 3 3V SDRAM Address 5 3 3V SDRAM Address 6 3 3V SDRAM Address 7 3 3V SDRAM 8 3 3V SDRAM Address 9 3 3V SDRAM Address 10 3 3V SDRAM Address 11 3 3V 15 www terasic com JA DTE RIA _ 12 PIN L4 SDRAM Address 12 3 3V DRAM 0010 PIN G2 SDRAM Data 0 3 3V DRAM_DOQ 1 PIN G1 SDRAM Data 1 3 3V DRAM DQ 2 PIN L8 SDRAM Data 2 3 3V DRAM DQ 3 PIN K5 SDRAM Data 3 3 3V DRAM DOQ 4 PIN K2 SDRAM Data 4 3 3V DRAM DQ 5 PIN J2 SDRAM Data 5 3 3V DRAM DQ 6 PIN SDRAM Data 6 3 3V DQ 7 PIN R7 SDRAM Data 7 3 3V DRAM DQ 6 PIN T4 SDRAM Data 8 3 3V DRAM 0019 PIN T2 SDRAM Data 9 3 3V DRAM DQ 10 PIN T3 SDRAM Data 10 3 3V 0011 PIN R3 SDRAM Data 11 3 3V DRAM DQ 12 PIN R5 SDRAM Data 12 3 3V DRAM DQ 13 PIN P3 SDRAM Data 13 3 3V DRAM_DQ 14 PIN N3 SDRAM Data 14 3 3V DRAM DQ 15 PIN K1 SDRAM Data 15 3 3V DRAM 0 PIN M7 SDRAM Bank Address 0 3 3V DRAM 1 PIN M6 SDRAM Bank Address 1 3 3V DRAM PIN R6 SDRAM byte Data Mask 0 3 3V DRAM PIN T5 SDRAM byte Data Mask 1 3 3V DRAM RAS N PIN L2 SDRAM Row Address Strobe 3 3V DRAM CAS N PIN L1 SDRAM Column Address Strobe 3 3V DRAM CKE PIN L7 SDRAM Clock Enable 3 3V DRAM CLK PIN R4 SDRAM Clock 3 3V DRAM WE N PIN C2 SDRAM Write Enable 3
68. USED ON ANY THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING IN ANY WAY OUT OF TI REFERENCE DESIGNS OR BUYER S USE OF TI REFERENCE DESIGNS TI reserves the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques for Tl components are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using Tl components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards Reproduction of significant portions of in
69. ace a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the EEPROM and EPCS Please note that users need to erase the EPCS before writing data to it 4 5 Digital Accelerometer The Control Panel can be used to display the status of the Digital Accelerometer where it measures the output of its 3 axis X Y Z The measurement range and resolution is set to default value 2g acceleration of gravity and 10bit twos complement respectively Figure 4 6 shows the current digital accelerometer status of the DEO Nano when Accelerometer tab is clicked The units that are displayed are the raw register values converted to decimal The value in parentheses is the gravitational acceleration values mg calculated from the register values according the formula Table 4 1 shows the rule Table 4 1 acceleration values convert rule Register Value Formula Result mg 0 0 511 2 0 1 1 511 2 3 9 2 2 511 2 6 8 17 17 511 2 66 4 511 511 511 2 2000 31 Terasic DE0 Nano User Manual www terasic com www terasic Figure 4 6 Digital Accelerometer status 4 6 ADC From the Control Panel users are able to view the eight channel 12 bit analog to digital converter reading The values shown are the ADC register outputs fro
70. age 600 700 LEs 1200 1400 LEs Hardware Multiply Embedded Multipliers Hardware Divide Reset Vector Memory v Offset 1050 Exception Vector Memory Offset 10 20 include MMU Only include the MMU when using an operating system that explicitly supports an MMU Fast TLB Miss Exception Vector Memory Offset E _ include MPU Warning Reset vector and Exception vector cannot be set until memory devices are connected to the Nios Il processor Figure 7 15 Nios Il Processor 9 Click Finish to return to main window as shown in Figure 7 16 9 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN Altera SOPC Builder File Edit Module System View Tools Niosl Help System Contents System Generation Target Project Device Family Cyclone n New component Library Verification Suite i Bridges and Adapters Interface Protocols Legacy Components Description Memories and Memory Controlle Nios 1 Processor Merlin Components Avalon Memory Mapped Master Peripherals Avalon Memory Mapped Master PLL Avalon Memory Mapped Slave Processor Additions Processors E 51 H University Program Wideo and Image Processing 2 To Do cpu 0 No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue 5J To 00 cpu 0 No exception vector has been specified for this
71. al www terasic com www terasic com JA DTE RIA 14 Press the Esc key or click an empty place on the schematic grid to cancel placing further instances of this symbol 15 Save your project regularly B Adding a Megafunction to the Schematic Megafunctions such as the ones available in the LPM are pre designed modules that you can use in FPGA designs These Altera provided megafunctions are optimized for speed area and device family You can increase efficiency by using a megafunction instead of writing the function yourself Altera also provides more complex functions called MegaCore functions which you can evaluate for free but require a license file for use in production designs This tutorial design uses a PLL clock source to drive a simple counter PLL uses on board oscillator DEO Nano Board is 50 MHz to create a constant clock frequency as the input to the counter To create the clock source you will add a pre built LPM megafunction named ALTPLL 1 Right click in the blank space in the BDF and select Insert gt Symbol or click the Add Symbol icon on the toolbar 2 Click the Megawizard Plug in Manager button The MegaWizard Plug In Manager appears as shown in Figure 6 19 4 NegaWizard Plug In Manager page 1 The MegaWizard Plug In Manager helps you create modify design files that contain custom variations of megafunctions Which action do you want to perform Edit an existing custom megafun
72. alog InO 26 Analog In3 Analog 1 4 Analog In1 LLLLLLLLLLLLA 2X13 HEADER Figure 3 10 Pin distribution of the 2x13 Header Figure 3 11 shows the connections on the 2x13 header A D converter and Cyclone IV device GPIO 2 12 0 GPIO 2 IN 2 0 2 13 ADC CS N ADC SADDR ADC SDAT Analog In 7 0O ADC SCLK ADC128S022CIMTX Figure 3 11 Wiring for 2x13 header and A D converter The pictures below indicate the pin 1 location of the 2x13 header 21 Terasic DEO Nano User Manual www terasic com www terasic com 1 Pin 1 LIN ei Pin 1 012060013 RN1 94V 0 ey gt in 1 ams US Excess ES tlli ul 6 4210 2 6 RE mono bal m 9 a NSIO B zm mme I xe 2 4 CSB E H 3 H LD BI ale 4 me a p gt po p gt Figure 3 12 Pin1 locations of the 2x13 header Table 3 8 Pin Assignments for 2x13 Header Signal Name FPGA Pin No I O Standard GPIO Connection DATA 0 3 3V PIN B16 IGPIO Connection DATA 1 3 3V 2 GPIO 21 GPIO 22 Ci4 GPIO Connection DATA 2 3 3 GPIO 23
73. ano User Manual www terasic com www terasic com JA DTE RIA The driver is available within the Quartus software Hence select Install from a list or specific location and click Next to get to Figure 6 4 Found Mew Hardware Wizard Please choose your search and installation options Search for the best driver in these locations Use the check bores below to limit or expand the default search which includes local paths and removable media The best driver found will be installed Search removable media floppy lnclude this location in the search Caltera 0 7 quartusdrivers usb blaster Don t search will choose the driver to install Choose this option to select the device driver from list Windows does not guarantee that the driver vau choose will be the best match vour hardware Figure 6 4 Specify the location of the driver Now select Search for the best driver in these locations and click Browse to get to the pop up dialog box in Figure 6 5 Find the desired driver which is at location C altera 10 1 quartus drivers usb blaster Click OK and then upon returning to Figure 6 4 click Next At this point the installation will commence but a dialog box in Figure 6 6 will appear indicating that the driver has not passed the Windows Logo testing Click Continue Anyway 43 Terasic DEO Nano User Manual www terasic com www terasic com Browse For Folder Select
74. apters amp i Interface Protocols 91 4 Components Module Description and Memory Controllers Components z Peripherals EB Debug and Performance Display 4 FPGA Peripherals f Microcontroller Peripheral Clock Settings epu Il Processor instruction master Avalon Memory Mapped Master data master Avalon Memory happed Master jag debug module Avalon Memory Mapped Slave E avalon slave Avalon Memory Mapped Slave onchip mermory2Z On Chip Memory RAM or ROM Interval Timer 1 Avalon Memory Mapped Slave PIO Parallel VO Multiprocessor Coordination Avalon Memory Mapped Slave Processor Additions Processors ry jill gt JE Error cpu instruction master onchip rmermoryz s1 cannot be at 0x2000 0x0 0010000 are acceptable Error cpur data master onchip mermory2 51 cannot be at Ox2000 0x0 10000 are acceptable Figure 7 34 Auto Assign Base Addresses Altera SOPC Builder File Edit Module System View Tools Nios il Help System Contents System Generation Target Project Device Family Cyclone Bren Mew component i Library Remove Avalon Verification Suite E B ridges and Adapters Interface Protocole Legacy Components Description Memories and Memory Controllers esl Pod DDR2 SDRAM Controller with Un DDR3 SDRAM Controller with Un QDR QDR 1 SRAM Contra
75. are connected ta the Mios I processor Figure 7 21 JTAG UART 13 Select jtag uart 0 component and rename it to jtag_uart as shown in Figure 7 22 96 Terasic 0 User Manual www terasic com www terasic com S RYAN Altera SOPC Builder File Edit Module System View Tools Help system Contents System Generation Target Project Device Family Cyclone m ug New component Library Avalon Verification Suite E B ridges and Adapters E3 Interface Protocols ASI Ethernet ie High speed Avalon Memory Mapped Master Interlaken Avalon Memory Mapped Master EPCI i Avalon Memory Mapped Slave ESO JTAG UART E Serial avalon jtag slave Avalon Memory Mapped Slave Avalon ST Avalon ST Serial SPI 3Wire Serial UART 85 232 Legacy Components GJ To Do cpu reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue Do cpu exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue A Warning Reset vector and Exception vector cannot be set until memory devices are connected ta the Mios I processor Figure 7 22 Rename JTAG UART 15 Add the Library Memories and Memory Controllers On Chip On Chip Memory RAM or ROM component to system as shown in Figure 7 23 and Figure 7 24 97 TagasiC Terasic DEO Nano User Manual www terasic c
76. ary In this section you will learn how to configure some advanced options in the Nios IDE By performing the following steps you can change all the available settings 1 In the Nios II IDE right click hello world 0 and select System Library Properties The Properties for hello world 0 syslib dialog box opens 2 Click System Library in the tree on the left side The System Library page contains settings related to how the program interacts with the underlying hardware The settings have names that correspond to the targeted NIOS II hardware 3 In the Linker Script box observe which memory has been assigned for Program memory text Read only data memory rodata Read write data memory rwdata Heap memory and Stack memory see Figure 7 61 These settings determine which memory is used to store the compiled executable program You can also specify which interface you want to use for stdio stdin and stderr You can also add and configure an RTOS for your application and configure build options to support reduced device drivers etc 4 Select onchip memory2 for all the memory options in the Linker Script box as shown in Figure 7 61 128 Terasic DEO Nano User Manual www terasic com www terasic com Properties for hello world 0 syslib Builders C C Build Documentation File Types Include Paths Indexer Make Project C Ctt Project Paths Project References Refactoring Hist
77. can be used to verify the functionality of the slide switches and pushbuttons 28 Terasic DEO Nano User Manual www terasic com www terasic com Teer Accelerometer Figure 4 4 Monitoring switches and buttons The ability to check the status of pushbutton and slider switches 1s not needed in typical design activities However it provides a simple mechanism for verifying if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 4 4 Memory Controller The Control Panel can be used to write read data to from the SDRAM EEPROM EPCS on the DEO Nano board As an example we will describe how the SDRAM may be accessed the same approach is used to access the EEPROM and EPCS Click on the Memory tab and select SDRAM to reach the window in Figure 4 5 29 Terasic DEO Nano User Manual www terasic com www terasic com LED Switches 100000200 00000000 Length Bid 2222252 Accelerometer Addre Addre Addre 100000000 Length D Entire Memory DISCONNECT i Figure 4 5 Accessing the SDRAM A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 4 5 depicts the result of writing the hexadecimal valu
78. cription Resource Path Location fritable Smart Insert Figure 7 56 Nios Il IDE C Project Perspective for hello_world_0 When you create a new project the NIOS II IDE creates two new projects in the NIOS C C Projects tab m hello world 0 is your application project This project contains the source and header files for your application m hello world 0 syslib is a system library that encapsulates the details of the Nios II system hardware Note When you build the system library for the first time the NIOS II IDE automatically generates files useful for software development including e Installed IP device drivers including SOPC component device drivers for the NIOS II hardware system e Newlib C library a richly featured C library for the NIOS II processor e NIOS II software packages which includes NIOS II hardware abstraction layer Nichestack TCP IP Network stack NIOS II host file system NIOS II read only zip file system and Micrium s realtime operating system RTOS e system h a header file that encapsulates your hardware system 122 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA e alt sys init c an initialization file that initializes the devices in the system e Hello world 0 elf an executable and linked format file for the application located in hello world 0 folder under the Debug directory 7 5 Build and Run the Program In this section
79. ction variation existing custom megafunction variation Copyright C 1991 2010 Altera Corporation lt Back Next gt Finish Figure 6 19 Mega Wizard Plug In Manager 55 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA 3 Click Next 4 In MegaWizard Plug In Manager page 2a specify the following selections see Figure 6 20 a Select gt ALTPLL b Under Which device family will you be using select the Cyclone IV E for DEO Nano development board c Under Which type of output file do you want to create select Verilog HDL d Under What name do you want for the output file type pll at the end of the already created directory name e Click Next Plug In page 2 Which megafunction would you like to customize Which device family will you be using Cydone WE Select a ini aad from the list below _ Which type of output file do you want to create 2a lt ALTDDIO IN CO AHDL WX ALTDDIO OUT VHDL ame ALTDOS S ALTDQ DOS What name do you want for the output file Jf A rs design my first _first_fpaaipll P ALTGX RECONFIG Verilog HDL ET ALTIOBUF nw rr Return to this page for another create operation E ALTLVDS TX Note compile
80. e 06CA into offset address 200 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789 defines eight 8 bit values 01 23 45 67 89 AB CD These values will be loaded consecutively into the memory The Sequential Read function 15 used to read the contents of the SDRAM and fill them into a as follows 30 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM are to be copied which involves all 32 Mbytes then pl
81. ead of six bytes X Y Z register from 0x32 to 0x37 1s performed to prevent a change in data between reads of sequential register Note the output data 1s twos complement with DATAxO as the least significant byte and as the most significant byte where x represent X Y Z Register 0x30 INT SOURCE Read Only 2 05 D4 DATA READY 2 SINGLE DOUBLE Activity 2 D D1 DO Inactivity FREE FALL Watermark Overrun Figure 8 9 Register 0x30 The SPI timing scheme follows clock polarity CPOL 1 and clock phase CPHA 1 CPOL 1 means the clock is high in idle CPHA 1 means data is captured on clock s rising edge and data is propagated on a falling edge The timing diagram of 3 wire SPI is shown below Figure 8 10 tout Hi e 500 ADDRESS BITS BITS Figure 8 10 3 wire SPI Timing Diagram B ADC Control The Analog to Digital Conversion 1s controller through a 4 wire SPI interface with the timing dialog given below Figure 8 11 Note the DIN signal is used to specify the channel INO IN7 for the next data conversion The DOUT signal 1s used to read the data conversion result whose channel 1 specified in previous transaction The first conversion result after power up will be on INO The output format of conversion result is straight binary 138 Terasic DEO Nano User Manual www terasic com www terasic com L OUT Figure 8 11 4 wire
82. eate Symbol Files for Current File to convert the simple counter v file to a Symbol File sym You will use this Symbol File to add the HDL code to your schematic The Quartus II software creates a Symbol File and displays a message see Figure 6 16 W Quartus II 1 Create 5ymbol File was successful Figure 6 16 Create Symbol File was Successful 7 Click OK 8 add simple counter v symbol to the top level design click the first fpga bdf tab 53 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 9 Right click in the blank area of the BDF file and select Insert gt Symbol 10 Double click the Project directory to expand it 11 Select the newly created simple_counter symbol by clicking its icon Libraries Project E3 d faltera 10 1 quartus libraries counter out 31 0 Mame Repeat insert mode Insert symbol as block Launch MegaWizard Plug In Mega Wizard Plug In Manager Figure 6 17 Adding the Symbol to the BDF 12 Click OK 13 Move the cursor to the BDF grid the symbol image moves with the cursor Click to place the simple_counter symbol onto the BDF You can move the block after placing it by simply clicking and dragging it to where you want it and releasing the mouse button to place it See Figure 6 18 simple counter CLOCK 5 counter out 31 0 Figure 6 18 Placing the simple counter symbol 54 Terasic DEO Nano User Manu
83. ecific FPGA device to the design Select the EP4CE22F17C6 device as it is the FPGA on the DEO Nano as shown in Figure 6 10 47 Terasic DEO Nano User Manual www terasic com www terasic com X Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family Show in Available devices list Devices Al eunt O FJ Target device speed grade CO Auto device selected by the Fitter Show advanced devices Specific device selected in Available devices list HardCopy compatible only Other n a Available devices Name User 1 05 Hemory Bits Embedded multiplier 9 bit elements EPACE22E2217 2 22320 80 _ 608256 _ 138 EP4CE22F17A7 22320 154 608256 E Companion device HardCopy Limit DSP amp RAM to device resources Figure 6 10 Specify the Device Example f Click Finish 4 When prompted select Yes to create the my first fpga project directory You just created your Quartus II FPGA project Your project is now open in Quartus II as shown in Figure 6 11 48 Terasic DEO Nano User Manual www terasic com www terasic com Q amp Hierarchy Files if Design P Q View Quartus Il information Documentation 00 00 00 o Figure 6 11 my first fpga project 6 5 Creating an FPGA design This section describes
84. efault EP 1 0 6 Output 2 5 V default lt P LED 5 Output 2 5 V default EP LED 4 Output 2 5 V default LED 3 Output 2 5 V default LED 7 Output 2 5 V default i LED 1 Output 2 5 V default LED 0 Output 2 5 V default lt new node gt gt Figure 7 51 Blank Pins 39 Input Location values as shown in Figure 7 52 Node Name Direction Location 1 I OBank VWREFGroup I OStandard Reserved CLOCK 50 Input PIN R8 3 B3 2 5 V default LED 7 Output PIN L3 2 B2 2 5 V default X LED 6 Output PIN B1 1 B1 2 5 V default LED 5 Output PIN_F3 1 B1 NO 2 5 V default EP LED 4 Output PIN 01 1 B1 NO 12 5 V default Figure 7 52 Set Pins 40 Close the pin planner and recompile the project 7 3 Download the Hardware Design This section describes how to download the configuration file to the board Download the FPGA configuration file 1 e the SRAM Object File sof that contains the NIOS II based system to the board by performing the following steps 1 Connect the board to the host computer via the USB download cable 2 Start the NIOS II IDE 3 After the welcome page appears click Workbench 4 Select Tools Quartus II Programmer 5 Click Auto Detect The device on your development board should be detected automatically 6 Click the top row to highlight it 117 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA
85. emory size setting to 26000 as shown in Figure 7 25 Click Finish to return to the window as in Figure 7 26 99 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYAN On Chip Memory RAM or ROM altera_avalon_onchip_memory2 Block Diagram clack avalon reset Size Minamize memory block usage may impact fmax 7 Read latency Slave 1 Latency Tow Slave 52 Latency e E Figure 7 25 Update Total memory size 100 www terasic com 1 Terasic DE0 Nano User Manual www terasic com Altera SOPC Builder File Edit Module System View Tools Nios ll System Contents System Generation Component Library Target Avalon Verification Suite Device Family Cyclone IV E v Name MHz Bridges and Adapters External 50 Interface Protocols Remove H Legacy Components z Memories and Memory Controllers i P DDR2 SDRAM Controller with UniPHY New DDR3 SDRAM Controller with UniPHY New Module Description I QDR SRAM Controller with UniPHY pri E cpu Nios IP G PADO we instruction master Memory Mapped Master Traffic Generator and BIST Engine New data master Avalon td M Master jag debug module Avalon Memory Mapped Slave fag uart JT AG UART a On Chip avalon jtag slave Avalon Memory Mapped Slave 5 Dua
86. erasic com PR 3 7 Currently selected device family lesione IE counter bus mux D0us _ Match project default How many data inputs do you want 2 How wide should the data inputand ll the result output buses be 4 bits vou want to pipeline the multiplexer Yes I wantan output latency of _ clock cycles Create an asynchronous Clear input Create Clock Enable input Figure 6 34 settings 9 Click Next 10 Click Next 11 Select the counter bus mux bsf option 12 Click Finish The Symbol window appears see Figure 6 35 for an example 67 Terasic DEO Nano User Manual www terasic com www terasic com ai d faltera 10 1 quartus libraries data x 3 0 data1x 3 0 Repeat insert mode Insert symbol as block Launch MegaWizard Plug In MegaWizard Plug In Manager Figure 6 35 Symbol 13 Click OK 14 Place the counter bus symbol below the existing symbols on the BDF as shown in Figure 6 36 Quibus uc ominie i QLOCK 50 inclk frequency 50 000 MHz CLOCK 5 counter out 31 0 E M ins Cyclone IV E CU ITI OD counter bus mux data1x 3 0 Figure 6 36 Place the symbol 68 Terasic DEO Nano User Manual www terasic com OC JA D
87. essages Figure 7 45 DEO NANO SOPC module 35 Save the newly created Verilog file as myfirst niosii v as shown in Figure 7 46 Save As Save in I3 myfirst_niogii sopce huilder is cb My Recent DEU SOPC sim Documents EB Im cpu jag debug module svsclk v cpu debug madule Eck cpu debug module wrapper cpu mul call cpu test bench cpu test bench DEO SOPC v DEO SOPC inst y jtag_uart s fl anchip memoaorvz v pio led E Desktop Documents Network Places File Save as type Verilog Files lg verlag Cancel Add file to current project Ex Figure 7 46 Save the Verilog file 114 Terasic DEO Nano User Manual www terasic com www terasic com JN OTS RYAN 36 Compile the project by selecting Processing gt Start Compilation as shown in Figure 7 47 Figure 7 48 shows the compilation process rst niosii myfirst niosii myfirst 1110511 ments ete Tool Window Help Start Compilation E Analyze Current File start Update Memory Initialization File db Compilation Report X PowerPlay Power Analyzer Tool SSN Analyzer Tool 6 input CLOCK 50 7 output 7 0 LED gt 8 DE DE NANO _ 3 H Design Units 10 clk 50 see we m 11 Out port from the e x 12 reset n Ot
88. evice Checksum Usercode pel start all D myfirst niosiifmyfirst EP4CE115F29 0081D85C FFFFFFFF Stop Delete 3 Add File ul Change File us I Down TDI Save File iz Message P i Inro Configuring device index 1 P 1 Info Device 1 contains JTAG ID code 0x020FT7TO0DD i Into Configuration succeeded 1 device s configured ie 1 Info Successfully performed operation s Ended Programmer operation at Fri Jan i4 09 45 13 Seles Progress Program Verify Blank Configure Check essaqes Message D of 6 Location Processing Extra Info Info Warnina Critical Warning JV Error Suppressed X Figure 7 54 Quartus ll Programmer The Progress meter sweeps to 100 after the configuration finished When configuration is complete the FPGA 15 configured with the Nios II system but it does not yet have a C program in memory to execute The Nios II IDE build flow 1 an easy to use graphical user interface GUI that automates build and makefile management The Nios II IDE integrates a text editor debugger the Nios II flash programmer the Quartus II Programmer and the Nios II C to Hardware C2H compiler GUI The included example software application templates make it easy for new software programmers to get started quickly In this section y
89. evice family and device EDA tool settings You can change the settings for an existing project and specify additional project wide settings with the Settings command Assignments menu You can use the various pages of the Settings dialog box to add functionality to the project lt Back Finish Help Figure 6 8 New Project Wizard introduction 2 Click Next 3 Enter the following information about your project Note File names project names and directories in the Quartus II software cannot contain spaces a What is the working directory for this project Enter a directory in which you will store your Quartus II project files for this design For example E My_design my_first_fpga b What is the name of this project Type my_first_fpga c What is the name of the top level design entity for this project Type my_first_fpga See Figure 6 9 46 Terasic DEO Nano User Manual www terasic com www terasic com New Project Wizard Directory Name Top Level Entity page 1 of 5 What is the working directory Far this project designimy First m What is the name of this project 7 What is Ehe name of the top level design entity For this project This name is case sensitive and must exactly match the entity name in Ehe design File First Use Existing Project Settings Figure 6 9 Project information d Click Next e In the next dialog box you will assign a sp
90. figuring the system properties editing and re building the application and debugging the source code 7 6 Edit and Re Run the Program You can modify the hello world c program file in the IDE build it and re run the program to Observe your changes as it executes on the target board In this section you will add code that will make the green LEDs on the DEO Nano board blink Perform the following steps to modify and re run the program 1 In the hello world c file add text shown in blue in the example below include lt stdio h gt 124 Terasic DEO Nano User Manual www terasic com OO S RYAN include system h include altera avalon pio regs h int main from Nios int count 0 int delay while 1 IOWR ALTERA AVALON PIO DATA PIO LED BASE count amp 0x01 delay 0 while delay 2000000 delay count return 0 j 2 Save the project 3 Recompile the project by right clicking hello world 0 in the NIOS II Projects tab and choosing Run Run As Nios II Hardware Note You do not need to build the project manually the Nios II IDE automatically re builds the program before downloading it to the FPGA 4 Orient your development board so that you can observe LEDs blinking 125 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 7 7 Why the LED Blinks The Nios syste
91. formation in TI data books data sheets or reference designs is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Tl is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards that anticipate dangerous failures monitor failures and their consequences lessen the likelihood of dangerous failures and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any Tl components in Buyer s safety critical applications In some cases components may be promoted specifically to facilitate safety related applications With such components Tl s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No Tl components are authorized for use in FDA Class or similar life crit
92. gure 3 1 illustrates the programming method when adopting a serial flash loader solution Chapter 9 of this document describes how to load a circuit to the serial configuration device 11 Terasic DEO Nano User Manual www terasic com www terasic com amp E mu QUARTUS Iv Figure 3 1 Programming a serial configuration device with serial flash loader solution B JTAG Chain on DEO Nano Board The JTAG Chain on the DEO Nano board is connected to a host computer using an on board USB blaster The USB blaster consists of a USB Mini B connector a FTDI USB 2 0 Controller and an Altera MAX II CPLD Figure 3 2 illustrates the JTAG configuration setup USB Connector LAAT gt gt 1 7 Figure 3 2 JTAG Chain 3 2 General User Input Output B Pushbuttons The DEO Nano board contains two pushbuttons shown in Figure 3 3 Each pushbutton is debounced using a Schmitt Trigger circuit as indicated in Figure 3 4 The two outputs called KEYO and KEY1 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA Each pushbutton provides a high logic level when it 1s not pressed and provides a low logic level when pressed Since the pushbuttons are debounced they are appropriate for using as clock or reset inputs 12 Terasic DEO Nano User Manual www terasic com www terasic com VCC2P5 KEY1 Am KEYO Am Figure 3 3 Connection
93. he desired functionality Timing or post place and route simulation verifies that the design meets timing and functions appropriately in the device Simulation tutorials can be found on the Altera University Program website at http university altera com 40 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 6 2 Before You Begin This tutorial assumes the following prerequisites You have a general understanding of FPGAs This tutorial does not explain the basic concepts of programmable logic You are somewhat familiar with digital circuit design and electronic design automation EDA tools You have installed the Altera Quartus II 10 1 software on your computer If you do not have the Quartus II software you can download it from the Altera web site at www altera com download You have DEO Nano Development Board on which you will test your project Using development board helps you to verify whether your design 1s really working You have gone through the quick start guide and or the getting started user guide for your development kit These documents ensure that you have e nstalled the required software e Determined that the development board functions properly and 15 connected to your computer Next step is to install the USB Blaster driver if not already done To install the driver connect a USB cable between the DEO Nano board and a USB port on a computer that 1 running the
94. he inclkO input 50 000 Setup in LVDS made Data rate Not Available Which PLL type will you be using FastPLL Enhanced PLL Select the PLL type automatically Operation Mode How will the PLL outputs be generated Use the feedback path inside the PLL In source synchronous compensation Mode In zero delay buffer mode Connect the fhmimic port bidirectional C3 With no compensation Create an input for an external feedback Externa Which output dock will be compensated for Figure 6 21 MegaWizard Plug In Manager page 3 of 14 Selections 6 Unselect all options on MegaWizard page 4 As you turn them off pins disappear from PLL block s graphical preview See Figure 6 22 for an example 57 Terasic DEO Nano User Manual www terasic com www terasic com Plug In Manager page 4 of 14 EE aut i 55 Clock switchover Able to implement the requested PLL Optional Inputs inched frequency 52 200 MHz _ Create pllena input to selectively enable the PLL Operation Mote Normal Create an pfdena input to selectively enable the phase frequency detector Lock Output Create locked output Enable self reset on loss lock Advanced Parameters Using these parameters is recommended for advanced users only Create output file s using the Advanced PLL parameters Configuratio
95. how to create an FPGA design This includes creating the top level design adding components in Verilog HDL and using the megafunctions adding pins and interconnecting all the components and pins First create a top level module In this tutorial you will use schematic entry via a Block Design File bdf Alternatively you could use Verilog HDL or VHDL for the top level module The following steps describe how to create the top level schematic 1 Select File gt New gt Block Diagram Schematic File see Figure 6 12 to create a new file Block1 bdf which you will save as the top level design 49 Terasic DEO Nano User Manual www terasic com www terasic com Intel Format File Memor Initialization File Verification Debugging Files SignalTap II Logic Analyzer File Other Files Text hile L x ce J ve jJ Figure 6 12 New BDF 2 Click OK 3 Select File Save As and enter the following information e File name my first fpga e Save as type Block Diagram Schematic File bdf 4 Click Save The new design file appears in the Block Editor see Figure 6 13 50 Terasic DEO Nano User Manual www terasic com www terasic com 4 Quartus II E NEy design my first fpga my first fpga my first fpga Edit View Project Assignments Processing Tools Window i Deka X Bgm LIII X NEN Project Navigator X my first fnga bdf Entity H
96. iagram of DEO Nano 9 9 2 9 Power upthe DBO Nano suci Dean sae ek Cupio 10 CHAPTER 3 USING THE DEU NANO BOARD 11 3 1 C nfi r nne the Cyclone IV E A EAT 11 3 2 General User Input Output a n 12 eR SID AM 15 SAPE ciis diis T 16 S LX Pansion Oade eee cuan qub mq Ua MM MIN i NEM MEUM LUE 17 2 6 A D Converter and 2x I5 erret eR Ora EA e a 20 3T MTS Walle ACCC ICE isi que toss musa EEE REE PIMM diDPSUUNE SUI NE DID quu ROH OPEP DUE 23 RR T T Tt 23 24 CHAPTER 4 DEU NANOCONTROL PA NEU 26 d I Control Patel SEM i s10eccssosascunnsaenscosasasdussancheaviaseusamsdentaterenosduboansheasiasnidemnaeabetugunoudebsanstaxstemuasmedeobeborueieess 26 A2 Bro diuo EE Tie RR 28 A 5witches dnd PusBbUEtODS 28 AA Memory Controller LUUD bU Sero Dr PUR 29
97. ical medical equipment unless authorized officers of the parties have executed an agreement specifically governing such use Only those components that has specifically designated as military grade or enhanced plastic are designed and intended for use military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of Tl components that have not been so designated is solely at Buyer s risk and Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products will not be responsible for any failure to meet ISO TS16949 Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2015 Texas Instruments Incorporated
98. installed The tutorial was written for version 10 1 of those software packages If you are using a different version there may be some difference in the flow Also this tutorial requires the DEO Nano board 7 2 Creation of Hardware Design This section describes the flow of how to create a hardware system including a Nios II processor 1 Launch Quartus II then select File gt New Project Wizard start to create a new project See Figure 7 land Figure 7 2 82 Terasic DEO Nano User Manual www terasic com www terasic com Quartus II File Edit View Project Fro Hew CtrltH Ctrlt Close CtrltFE4 3 ie Hew Project Wizard Open Project Ctrl I Save Project Close Project LE Ctrlts cave S seve All Ctrl ShifttS Eile Properties Create Update k Export Convert Programming Files Fage Setup Print Frewiew Print Ctrl F hoB Recent Files Recent Projects j Exit 4 Figure 7 1 Start to Create a New Project Hew Project Wizard Directory Name Top Level Entity page 1 of 5 Whatis the working directory for this project D HomeWser pesktoo What is the name of this project What is the name of the topJevel design entity for this project This name is case sensitive and must exactly match the entity name in the design file Figure 7 2 New Project Wizard 2 Select a working directory for this pr
99. ion file onto the DEO Nano board The configuration file contains a design that communicates with the peripheral devices on the board that are attached to the FPGA device Perform the following steps to ensure that the control panel starts up successfully 1 Make sure Quartus II 10 0 or later version is installed successfully on your 2 Connect a USB A to Mini B cable to a USB Type A host port and to the board 3 Start the executable DEO NANO ControlPanel exe on the host computer The Control Panel user interface shown in Figure 4 1 will appear 5 The DEO NANO ControlPanel sof bit stream 15 loaded automatically as soon as the DEO NANO ControlPanel exe 1s launched 6 In case the connection is disconnected click on CONNECT where sof will be re loaded onto the board Note the Control Panel will occupy the USB port until you choose to close the program or disconnect it from the board by clicking the Disconnect button While the Control Panel is connected to the board you will be unable to use Quartus II to download a configuration file into the FPGA 26 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN 8 The Control Panel is now ready for use experience it by setting the ON OFF status for some LEDs and observing the result on the DEO Nano board Switches Memory Accelerometer ADC _ CN DISCONNECT Figure 4 1 The DEO Nano Control Panel The concept of the DE
100. ions Configuration device 564 vi Mode lactive Serial File name output file jic Remote Local update difference fie NONE o Memory Map File Input files to convert File Data area Properties Start Address Add Hex Data In EE Add Sof Page SOF Data 0 lt gt Add Device DEO NANO sof EPACE22F 17 Remove Up Down Properties Figure 9 2 Highlight Flash Loader 11 Select the targeted FPGA Cyclone IV E EPACE22 as shown in Figure 9 3 12 Click OK The Convert Programming Files page displays should look like Figure 9 4 13 Select the sof file and Click the Properties Select Compression click OK as shown in Figure 9 5 14 Click Generate 148 Terasic DEO Nano User Manual www terasic com www terasic com W gt Select Devices Device family Device name APEX20K 4 1 New Arria Gx 4 1 15 Arria 15 Import Arria GZ EP4CE22 Export cydone 55 15 IV E 75 IV Gx C MAx II C Max v stratix 1 stratix Gx stratix stratix I1 GX stratix Stratix Iv Edit Remove Figure 9 3 Select Devices Page 149 Terasic 0 User Manual www terasic com w
101. ipulate the PIO core registers are available to your program In particular the macro IOWR ALTERA AVALON PIO DATA base data 126 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA can write to the PIO data register turning the LED on and off The PIO is just one of many SOPC peripherals that you can use in a system To learn about the PIO core and other embedded peripheral cores refer to Quartus II Version 10 1 Handbook Volume 5 Embedded Peripherals When developing your own designs you can use the software functions and resources that are provided with the Nios HAL Refer to the Nios Software Developer s Handbook for extensive documentation on developing your own Nios processor based software applications 7 8 Debugging the Application Before you can debug a project in the NIOS II IDE you need to create a debug configuration that specifies how to run the software To set up a debug configuration perform the following steps 1 In the hello_world c double click the front of the line where you would like to set breakpoint as shown in Figure 7 60 Nios II C C hello world c Nios II IDE 4 File Edit Refactor Navigate Search Project Tools Run Window Help ri 6 9 O Q im iG Fe M Nios Tr cron Projects 01 kello world Tim ES altera components 5 hello world 0 Qo Binaries e Includes 2 Debug 4
102. is section provides the detailed procedures on how the to use the DEO Nano System Builder B Install and launch the DEO Nano System Builder The DEO Nano System Builder is located in the directory Tools DEO_NANO_SystemBuilder on the DEO Nano System CD Users can copy the whole folder to a host computer without installing the utility Launch the DEO Nano System Builder by executing the DEO SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 5 2 Terasic 0 System Builder V1 0 0 System Configuration Project Name DEO NANO CLOCK Button x 2 SDRAM 32MB EEPROM 2Kb Accelerometer ter T EJ E LH 3 HTI GPIO 0 Header LED x8 Dip Switch x 4 ADC EPCS 2x13 Pin Header Prefix Name GPIO 1 Header None Prefix Name Figure 5 2 The DEO Nano System Builder window B Input Project Name Input project name as show in Figure 5 3 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity 36 Terasic DEO Nano User Manual www terasic com www terasic com Terasic DEU Nano System Builder Y 1 0 0 INDERA System Configuration A UNIVERSITY Project PROGRAM www terasic com DEO Nano FPGA Board CLOCK LED x8 Butt
103. l Clock FIFO al onchip memory2 0 On Chip Memory RAM or ROM Ayalon ST Mult Channel Shared Memory FIFO 51 Avalon M M Slave Avalon ST Round Robin Scheduler Ayalon ST Single Clock FIFO FIFO Memory On Chip Memory RAM or ROM lt i gt Lx Jia JL v Fiter Defaut e Error cpu instruction master onchip memory2 0 s1 cannot be at 0x2000 0x0 or 0x10000 are acceptable e Error cpu data master onchip memory2 0 s1 cannot be at 0x2000 0x0 or 0x10000 are acceptable CJ To Do cpu No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue To Do cpu No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue Figure 7 26 Add On Chip memory 17 Rename onchip memory2 0 to onchip memory2 as shown in Figure 7 27 Altera SOPC Builder File Edit Module System View Tools Niosll Help System Contents System Generation Component Library Avalon Verification Suite Bridges and Adapters Interface Protocols i Legacy Components Memories and Memory Controllers 0082 SDRAM Controller with UniPHY New 0083 SDRAM Controller with UniPHY New QDR Il and QDR 1 SRAM Controller with UniPHY El cpu RLDRAM Controller with UniPHY instruction master Fe Traffic Generator and BIST Engine New data master T nur debug module Avalon Memory Mapped Slave zi On Chip
104. le for Quartus Il LN Project name gt htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof 39 Terasic DEO Nano User Manual www terasic com www terasic com Chapter 6 Tutorial Creating an FPGA Project This tutorial provides comprehensive information for understanding how to create a FPGA design and run it on the DEO Nano development and education board The following sections provide a quick overview of the design flow explaining what is needed to get started and describe what is taught in this tutorial 6 1 Design Flow Figure 6 lshows a block diagram of the FPGA design flow The first step in the FPGA design flow starts is design entry The standard design entry methods are using schematics or a hardware description language HDL such as Verilog HDL or VHDL The design entry step is where the designer creates the digital circuit to be implemented inside the FPGA The flow then proceeds through compilation simulation programming and verification in the FPGA hardware Figure 6 1 Design Flow This tutorial describes all of the steps except for simulation Although it 1s not covered in this document simulation 15 very important to learn There are two types of simulation Functional and Timing Functional simulation allows you to verify that your hardware 1s performing t
105. m all of the eight separate channels The voltage shown is the voltage reading from the separate pins on the extension header Figure 4 7 shows the ADC readings when the ADC tab is chosen EN DISCONNECT Figure 4 7 ADC Readings 32 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN 4 7 Overall Structure of the DEO Nano Control Panel The DEO Nano Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV E FPGA with software running on on chip memory The software part is implemented in C code the hardware part is implemented in Verilog HDL code with SOPC builder The source code is not available on the DEO Nano System CD To run the Control Panel users should make the configuration according to Section 4 1 Figure 4 8 depicts the structure of the Control Panel Each input output device is controlled by the Nios II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The Nios II interprets the commands sent from the PC and performs the corresponding actions FPGA SOPC JTAG Blaster Hardware 5 Figure 4 8 The block diagram of the DEO Nano Control Panel 33 Terasic DEO Nano User Manual www terasic com www terasic com Chapter 5 DEO Nano System Builder This chapter describes how users can create a custom design project on the DEO Nano board b
106. m description header file system h contains the software definitions name locations base addresses and settings for all of the components in the Nios hardware system The system h file is located in the in the hello_world_0_syslib Debug system_description directory and is shown in Figure 7 59 7 II C C4 zystem h Hios II IDE EES EET E Hios II c ce File Edit Refactor Havigate Search Project Tools Kun Window Help ef Q Qu i E Ew MEG IT 52 E 6 helle world system h 5 sicak hello world 0 E gt Binaries EE Includes tae altera components r3 T Izd 5 ipi Es 1 H Debug zl Le hello world application stf i readme tit ae hello world syslib DE fl lt gt Archives E m Includes Debug obj f derfine fdefine Fdefine Ffoertine fodefine fderine Rderftine Li d on x D m pp Op NT 2 0 Om Pp D 1 H m Cj m tou EN ay rem oh D D lt 1 in ipi Ter Pio B i Sy system description les Ln system xi alt zyz 1114 define foertine 1 1 Rdefine fdefine fderfine 1 IJ
107. me 13 14 T 4 D Len 1 e Quartus II D ayfirst niosii myfirst niosii myfirst 110511 Edt Project Assionmenis Processing Tool Window S deem VHSB doo Project Navigator ib myfirst_niosii v d Compilation Report f Cont Flow Summary is leva 5 In progress Thu Jan 13 17 59 27 2011 IV E EPACE22F 17C6 R L Si 10 1Build 153 11 29 2010 53 Full Version 9 myfirst nios Flow Settings R myfirst_niosii m i Flow Non Default Global Settings p ewe itr Name miyfirst Flow Elapsed Time Famil i IV E EB Flow OS Summary Flow Log Analysis amp Synthesis Files d Design Units TEETH Madule Progress Full Compilation H Analysis amp Synthesis Assembler TimeQuest Timing Analyzer i 00 Typ Bi ii m Inte Orating entity r hierarchy inst Elab DE NANO SOPC DE NANO SOPC DE NANO SOPC _ Info grating entity cpu jtag debug module arbitrator or hierarchy 1 i in Elab debug module arb m DE NANO SOPC DE NANO 5 _ 6 Info Elaborating entity cpu data master arbitrator or hierarchy 5 Te inst cpu Elab M du DE NANO SOPC DE NANO SOPC _ Li Info Ela Oreting entity cpu instruction master arbitrator hierarchy z i1 Elah 2 arb NM da DE NANO SOPC
108. ment any system design pio Dip EEPROM 2Kbit Switch X2 X2 X2 X4 40 pin X39 X72 lt gt 40 pin GPIO S RYAN Cyclone P 64Mb X16 2X13 lt lt 6 lt 50 MHz Figure 2 3 Block diagram of DEO Nano Board Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 2 3 Power up the DEO Nano Board The DEO Nano board comes with a preloaded configuration bit stream to demonstrate some features of the board This allows users to see quickly if the board 1 working properly To power up the board two options are available which are described below 1 Connect a USB Mini B cable between USB Type A host port and the board For communication between the host and the DEO Nano board it 15 necessary to install the Altera USB Blaster driver software 2 Alternatively users can power up the DEO Nano board by supplying 5V to the two DC 5 VCC5 pins of GPIO headers or supplying 3 6 5 7V to the 2 pin header At this point you should observe flashing LEDs on the board Terasic DEO Nano User Manual www terasic com www terasic com Chapter 3 Using the DEO Nano Board This chapter gives instructions for using the DEO Nano board and describes in detail its components and connectors along with the required pin assignments 3 1 Configuring the Cyclone IV FPGA The DEO Nano board contains a Cyclone
109. meter Value Press or to terminal the monitor process 20 mg Y 4 mg 2 872 mg 32 mg Y 8 mg A7976 mg 2 mg Y 8 mg A7956 mg dum A mg 4 mg A7986 mg m 12 mg mg 2 1 4 m 36 mg Y 8 my Z 9 72 32 mg Y 8 mg 2 968 28 mg Y 8 A7986 e Input 1 to start Analog to Digital Conversion demo The demo repeatedly displays the voltage on eight channels To terminate the process press KEYO or KEY on the DEO Nano board Upon exiting the demo the selection menu will be displayed Select Demo ADC onitor ADG Value Press KEYG or 1 to terminal the monitor process u u U U U u e Input 2 to start EEPROM Content Dump demo The demo displays the values in the first 16 bytes of the EEPROM The demo automatically exists and returns to the selection menu Select Demo EEPROM ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh e Input 3 to start EPCS demo The demo displays the memory size of EPCS The demo automatically exists and returns to the selection menu Selection function 1AGCELEROMET ER 1 1n DC 2 TEEPROH 3 JEPCS EPCS EPCS Size 8388688 Bytes lt 8 141 NWW terasic com 1 self E i j ey b m 7 27 P 4 5 p 14 4 SEG amp racif I E Alia m gt gt WAW Tarare
110. my first fpga Configuration Programming Files Specify device wide options for reserving all unused pins on the device To reserve Unused Pins individual dual purpose configuration pins go to the Dual Purpose Pins tab To reserve Dual Purpose Pins other pins individually use the Assignment Editor Capacitive Loading 205 a Reserve all unused pins lls Voltage Pin Placement Error Detection CRC CvPCIe Settings Description Reserves all unused pins the target device in one of 5 states as inputs that are tri stated as outputs that drive ground as outputs that drive an unspecified signal as input tri stated with bus hold or as input tri stated with weak pull up Figure 6 50 Setting unused pins Click twice OK 4 In the Processing menu choose Start Compilation After the compile select Tools Programmer Select the my first fpga sof file from the project directory Click Start At this time you could find the other LEDs are off 81 Terasic DEO Nano User Manual www terasic com ON Chapter 7 Tutorial Creating a Nios ll Project This tutorial provides comprehensive information that will help you understand how to create microprocessor system on your FPGA development board and run software on it This system will be based on the Altera Nios II processor 7 1 Required Features This tutorial requires the Quartus II and Nios II EDS software to be
111. n nennen nennen nnn nnn nnn 120 Tm 123 7 5 Edit and RE RU 124 ead VV Wey ie LEDE Em 126 7 8 Debugging the 127 T COMI 128 CHAPTER 8 DEO NANO DEMONSTRATIONS 130 VES SC TN IR ae E E 130 130 cr RETE 132 o 136 TT 142 eSI Test 143 CHAPTER 9 APPENDIX dies 146 9 1 Programming the Serial Configuration Device nennen enne nennen 146 9 2 EPCS Programming via nios 2 flash programmetr essen enne nennen nennen nnne nnn 154 3 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN 9 3 Revision History DC ODUEIP BE 154 DEO Nano User Manual www terasic com www terasic com Chapter 1 Introduction The DEO Nano board introduces compact sized FPGA development platform suited for to a wide range of portable design projects such as robots and mobile projects The DEO Nano is ideal for use with embedded
112. nent Editar E Warning epar Disabling the assign CPUID control register value manually langer auta assigns unique control register value This option will always be turned on with deta lt Figure 7 38 SOPC Builder generation successful 24 Click Exit to exit the SOPC Builder and return to the window as shown in Figure 7 39 Quartus II D myfirst ninsii myfirst niosii myfirst ninsii Edit Project Assignments Processing Tools Window ug oc wwms RIV OSV OGY Project Navigator Bx Entity amp Cydone IV E EPACE22F 17C6 3 myfirst niasii 4 Hierarchy Files 47 Design Units Status Progress Documentation 4 Processing Extra Extra Info JX Info Warning X Critical Warning X Error X Suppressed Flag Message Location Locate _ 10 00 00 00 Messages Figure 7 39 Return to Quartus ll after exiting SOPC Builder 109 Terasic DEO Nano User Manual www terasic com UC s s Mn S RYA 25 Create a new Verilog HDL file by selecting
113. ns 3 Processors 81 515 nei niersity Program Widen and Image Processing Figure 7 17 Rename the CPU 1 Mics ll Processor Avalon Memory Mapped Master Avalon Memory Mapped Master Avalon Memory Mapped Slave _ To Da cpu No reset vector has been specified for this CPU Please parameterize the CPU to resolve this issue 4 To Da cpu No exception vector has been specified for this CPU Please parameterize the CPU to resolve this issue E Warning cpu Reset vector and Exception vector cannot be set until memory devices are connected to the Nios Ill processor Figure 7 18 Rename the CPU 2 93 Terasic 0 User Manual www terasic com www terasic com S RYAN 11 Add a second component by selecting Library Interface Protocols Serial JTAG UART and clicking the Add button as shown in Figure 7 19 and Figure 7 20 Altera SOPC Builder Fie Edt Module System View system Contents System Generation Verification Suite Bridges and Adapters Interface Protocols Ethernet High Speed 9 50 E Serial 8 Avalon ST JTAG STAG VART Figure 7 19 Add the JTAG UART component 94 Terasic DEO Nano User Manual www terasic com www terasic com jtag uart 0 JTAG UART Mequtore altera avalon Block Diagram clock Interrupi reset avalon Read FIFO Data from JTAG to Avalon Buffer depth bytes
114. ns with output dock s that use cascade counters are not supported Figure 6 22 MegaWizard Plug In Manager page 4 of 14 Selections 7 Click Next four times to get to page 8 8 Setthe Clock division factor to 10 as shown in Figure 6 23 58 Terasic DEO Nano User Manual www terasic com www terasic com S RYA Plug In Manager page 6 of 12 2 ALTPLL About i fi Output Clocks LEX 24 mi dkco gt gt dka c0 Core External Output Clock Able to implement the requested PLL inched frequency 50 000 MH Operation Mode Normal Use this clock Clock Tap Settings Requested Settings Actual Settings Enter output dock frequency 160 00000000 d zi MHz 5 000000 Clock multiplication factor Clock division factor Clock phase shift Clock duty 96 Description Primary clock VCO frequency MHz Note The displayed internal Modulus for M counter settings of the PLL is recommended Maric foe for use advanced users only initial VCO ase cydes for M counter VCO phase tap for M counter Per Clock Feasibility Indicators co Figure 6 23 MegaWizard Plug In Manager page 8 of 14 Selections 9 Click Next and then click Finish 10 The wizard displays a summary of the files it creates see Figure 6 24 Select the pll bsf option and click
115. nsorMemo batch The demo batch file includes the following files e FPGA Configure File DEO Sensor sof Demonstration Setup e Make sure Quartus II 1s installed on your PC e Connect USB cable to the DEO Nano board and install the USB Blaster driver if necessary e Execute the demo batch file test bat under the batch file folder DEO GsSensorMemo batch This will load the demo into FPGA Tilt the DEO Nano board from side to side and observe the result on the LEDs 8 6 SDRAM Test by Nios II Many applications use SDRAM to provide temporary storage In this demonstration hardware and software designs are provided to illustrate how to perform memory access in QS YS We describe how the Altera s SDRAM Controller IP 1 used to access a SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The SDRAM controller handles the complex aspects of using SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals B System Block Diagram Figure 15 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The SDRAM controller is configured as a 32MB controller The working frequency of SDRAM controller is 100MHZ and the Nios II program 15 running in the SDRAM 143 Terasic DEO Nano User Manual www terasic com www terasic com FPGA 095 50 2
116. nter bus mux bb v pll Desktop all bise simple counter Documents Computer My Network File name Isimple counter v Flaces Save as type Verlag HEL Files vlg verilog Cancel Add file to current project Figure 6 14 Saving the Verilog HDL file The resulting empty file is ready for you to enter the Verilog HDL code 4 the following Verilog HDL code into the blank simple counter v file as shown in Figure 6 15 It has a single clock input and a 32 bit output port module simple counter CLOCK 5 counter out input CLOCK 5 output 31 0 counter out reg 31 0 counter out 22 Terasic DEO Nano User Manual www terasic com www terasic com always posedge CLOCK 5 on positive clock edge begin counter out lt counter out 1 increment counter end endmodule end of module counter 1 It has a single clock input and a 32 bit output port 2 module simple counter 3 CLOCK 5 4 counter out 5 6 input CLOCK 5 1 output 31 0 counter out 8 req 31 0 counter out g 10 always 8 posedge CLOCK 5 on positive clock edge 11 begin 12 counter out lt counter out 1 increment counter 13 end 14 endmodule end of module counter 15 Figure 6 15 The Verilog File of simple counter v 5 Save the file by choosing File gt Save pressing Ctrl S or by clicking the floppy disk icon 6 Select File Create Update Cr
117. ode Normal 110 0 00 50 00 RU RE ww um ats sb ec ND NM v p Figure 6 40 Adding the KEY 0 Input Pin You have finished adding all required components of the circuit to your design You can add notes or information to the project as text using the Text tool on the toolbar indicated with the A symbol For example you can add the label OFF SLOW ON FAST to the KEY 0 input pin and add a project description such as DEO Nano Tutorial Project 6 6 Assign the Pins In this section you will make pin assignments Before making pin assignments perform the following steps 1 Select Processing gt Start gt Start Analysis amp Elaboration in preparation for assigning pin locations 2 Click OK in the message window that appears after analysis and elaboration completes To make pin assignments to the KEY 0 and 50 input pins and to the LED 3 0 output pins perform the following steps 1 Select Assignments gt Pin Planner which opens the Pin Planner a spreadsheet like table of specific pin assignments The Pin Planner shows the design s six pins See Figure 6 41 71 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA lt Pin Planner design my first fpga my first fpga my first fpga Skt File Edit View Processing Tools Window Groups Namedi m Node Mame Direction K
118. oject type project name and top level entity name as shown in Figure 7 3 Then click Next you will see a window as shown in Figure 7 4 83 Terasic DEO Nano User Manual www terasic com ON Project Wizard Directory Name Top Level Entity page 1 of 5 What is the working directory for this project What is the name of the design entity for this project This name is case sensitive and must exactly match the entity name in the design file mryfirst niosii Lise Existing Project Settings Figure 7 3 Input the working directory the name of project top level design entity Ji uu Hew Project Wizard Add Files page 2 of 5 Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project Mote you can always add design files to the project later File name File Library Design Entry Synthesis Tool Verzion Down Properties Specify the path names af any non default libraries Figure 7 4 New Project Wizard Add Files page 2 of 5 3 Click Next to skip in Add Files window In the Family amp Device Settings window we will choose device family and device settings appropriate for the DEO Nano board You should choose settings the same as shown in Figure 7 5 Then click Next to get to the window as shown in Figure 7 6 84 TagasiC Terasic DEO Nano User Manual www
119. om UC S pa Altera SOPC Builder File Edi Module System View Took 1 Help system Contents System Generation Avalon Verification Suite amp j Bridges and Adapters Interface Protocols 9 1 Components Ei Memories and Memory Controllers amp DDR3 SDRAM Controller with UniPHY New QDR QDR I SRAM Controller with UniPHY amp RLDRAM II Controller with UniPHY Figure 7 23 Add On Chip Memory 98 Terasic 0 User Manual www terasic com www terasic com JA DTE RYA On Chip or onchip memory2 0 Memory RAM or ROM Megatore altera_avalon_onchip_memory2 211 Block Diagram clock avalon Memory Type RAM Writable Dua port access Read During Write Mode DONT CARE Block type Auto v Size Data width 32 Total memory size 4095 bytes Minimize memory block usage may impact fmax Read latency Slave s1 Latency 1 a Slave 52 Latency aret Memory initialization Figure 7 24 On Chip Memory Box 16 Modify Total m
120. on x 2 Dip Switch x 4 V SDRAM 32MB VADC EEPROM 2Kb EPCS Accelerometer 2x13 Pin Header Cyclonet Ii GPIO 0 Header None 6868668680 86 6 6 of 9009009090000 0 Prefix Name GPIO 1 Header Prefix Name Save Setting Figure 5 3 The DEO Nano Board Type and Project Name B System Configuration Under System Configuration users are given the flexibility of enabling their choice of included components on the DEO Nano as shown in Figure 5 4 Each component of the DEO Nano is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled the DEO Nano System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard Terasic DEO Nano System Builder 1 0 0 System Configuration SVAN www terasic com Project Name 95 IDEO NANO DEO Nano FPGA Board CLOCK LEDx8 Button x 2 Dip Switch x 4 v SDRAM 32MB v ADC v EEPROM 2Kb EPCS Accelerometer 2x13 Pin Header mh CATA leno SRE SS ot GPIO 0 Header None 2 L L gt 5 LI Prefix Name G PIO 1 Header Prefix Name Save Setting Figure 5 4 System Configuration Group B GPIO Expansion 37 Terasic DEO Nano User Manual ww
121. onnect a USB cable to the DEO Nano board and install USB Blaster driver if necessary e Execute the demo batch file test bat under the batch file folder DEO NANO SOPC DEMOdemo batch This will load the demo into the FPGA After executing the batch file a selection menu appears as follows Nios EDS 10 1 3 Example designs can he found in fcyugdrive c altera i A niosZzeds examples You may add a startup script c altera 10 6 niosZeds user bashre gt Using cable USB Blaster USB 1 device 1 instance AxA Resetting and pausing target processor OK Initializing CPU cache Cif present Downloaded 84KB 1 45 68 KE s gt Merified OK Starting processor at address BHxH2HHBiC8 nioz2 terminal connected to hardware target using JIAG UART on cable mios2 terminal USB Blaster USB HI device 1 instance nioz2 terminal Use the IDE stop button or Ctrl C to terminate Demo Selection function B IR GCELEROMET ER C1 JADC 2 IEEPROH 5 e Input 0 to start accelerometer demo The demo starts by displaying the accelerometer s chip ID and then continues by displaying the X Y Z values every 1 0 second To terminate the demo press KEYO or KEY on the DEO Nano board Upon exiting demo the selection menu will be displayed 140 Terasic DEO Nano User Manual www terasic com www terasic com Select Demo ACCELEROMETER id ESh onitor Accero
122. onstration Setup e Make sure Quartus and Nios are installed on your Connect a USB cable to the DEO Nano board and install USB Blaster driver if necessary Execute demo batch file DEO NANO SDRAM wmNlos Test ba t under the batch file folder DEO SDRAM wNlios Test Nemo batch e After Nios program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Press KEYI KEYO of the DEO Nano board to start SDRAM verify process Press KEYO for continued test e The program will display progressing and result information as shown in Figure 8 16 29 Altera Nios II EDS 13 0sp1 gcc4 oE Pausing target processor Initializing CPU cache if present OK Downloaded 61KB in 09 83 76 2 Verified OK Starting processor at address 0x000001B4 nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB 0 device 1 instance 0 nios2 terminal Use the IDE stop button or Ctrl C to terminate SDRAM Test Size 32MB CPU Clock 100000000 Press any KEV to start test KEVO for continued test gt SDRAM Testing Iteration 1 write 104 204 304 504 604 TOA 804 904 100 read verify 104 204 304 504 604 TOA 804 904 100 SDRAM test Pass 12 seconds gt SDRAM Testing Iteration 2 Write 104 20 304 404 50 604 TOA 80 904 1004 read verify 20 30 Figure 8 16 Display Progress and Result Inf
123. ormation for the SDRAM Demonstration 145 Terasic DEO Nano User Manual www terasic com www terasic com Chapter 9 Appendix 9 1 Programming the Serial Configuration Device This section describes how to program the serial configuration device with Serial Flash Loader SFL function via the JTAG interface User can program serial configuration devices with a JTAG indirect configuration jic file To generate JIC programming files with the Quartus II software users need to generate a user specified SRAM object file sof of the circuit they wish to put in the serial configuration device Next users need to convert the SOF to a JIC file To convert a SOF to a JIC file in Quartus II software follow these steps B Convert SOF to JIC 1 Select File gt Convert Programming Files 2 Inthe Convert Programming Files dialog box set the Programming file type field to JTAG Indirect Configuration File jic 3 Inthe Configuration device field specify the targeted serial configuration device EPCS64 4 Inthe File name field browse to the target directory and specify an output file name 5 Highlight the SOF Data row in the table as shown in Figure 9 1 6 Click Add File 7 Select the SOF that you want to convert to a JIC file 8 Click Open 146 Terasic DEO Nano User Manual www terasic com www terasic com 9 Highlight the Flash Loader and click Add Device as shown in Figure 9 2 10 Click OK The Select Devices
124. ory System Library Target Hardware SOPC Builder System D nyfirst nicsii DE CPU epu System Library Contents singl e threade d RTOS Options stdout jtag uart stderr jtag uart stdin jtag System clock timer none Timestamp timer Max file descriptors Program never exits v Clean exit flush buffers v Support C Reduced device drivers Lightweight device driver v Small C library Link with profiling library ModelSim only no hardware support Unimplemented instruction handler Run time stack checking Software Components Linker Script O Custom linker script none SUse auto generated linker script Program memory text onchip memory2 Read only data memory rodata onrhip memory2 v Read write data memory rwdata onchip memory2 Heap memory onchip memory2 Stack memory onchip memory2 separate exception stack Exception stack memory Maximum exception stack size bytes Restore Defaults Apply Figure 7 61 Configuring System Library Properties 5 Click OK to close the Properties for hello world 0 syslib dialog box and return to the IDE workbench Note If you make changes to the system properties you must rebuild your project To rebuild right click the hello_wo
125. ou will use the Nios II IDE to compile a simple C language example software program to run on the Nios II system on your development board You will create a new software project build it and run it on the target hardware You will also edit the project re build it and set up a debug session 119 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYA 7 4 Create a hello world Example Project In this section you will create a new NIOS II application project based on an installed example To begin perform the following steps in the NIOS II IDE Return to the NIOS II IDE Note you can close the Quartus Programmer or leave it open in the background if you want to reload the processor system onto your development board quickly 2 Select File gt New gt NIOS II Application to open the New Project Wizard 3 the New Project wizard make sure the following things a Select the Hello World project template b Give the project a name hello world 0 is default name c Select the target hardware system s PTF file that 1s located in the previously created hardware project directory as shown in Figure 7 55 120 Terasic DEO Nano User Manual www terasic com www terasic com Project Nios Application Click Finish to create application with a default system library as D myfirzt niozii Softwarekhello world 0 Specify Location Location D myfirst niosiiW
126. own to various required voltages For portable project applications connect a battery power supply 3 6 5 7V to the 2 pin external power header shown in Figure 3 15 Tey MIL WIE MID 29 w E 39 3 caen un oo 73 04 9705 5 Designed amp Manufactured Terasic 3 chet Luis pem en Tai c 2 2 Oro rr SIS E rn Ni MH BATTERY CHARGER o U9 702070 2070 aj NUNU Qn Cn uNe Od L3 9609 3 EP Yr TIRA Xi 2122998 292999292 4 T ee GO CR B36 i uz R57 C83 C73 NCAAA31007 27 amt 3N1GAOROC WY Ed m C18 aay 25 m fis ues pira ES Ji T7 Je Figure 3 15 Portable Battery Connection 24 Terasic DEO Nano User Manual www terasic com www terasic com B Power Distribution System Figure 3 16 shows the power distribution system on the DEO Nano board 5V USB 5V Power 02 Max 500mA output 5V VCC pins on two 40 pin headers 2 pin power header 5V 0 025 Regulator LP5900TL 2 5 Max 0 15A output 2 5V 0 035 3 3V 0 02 Regulator LP385005D ADJ Max 1 5A output 3 3V 0 019 3 3V 0 292 3 3 01A 3 3V
127. project EDA tools Ec ation gt Run gatetevel simulation automatically after compilation Analysis None gt ET ine gt CENSUI Run this tool automatically after compilation Formal Yerificat Haar bevel Timing lt gt ma sNone Signal Integrity None 3 Boundary Scan None Hew Project Wizard Figure 7 6 New Project Wizard EDA Tool Settings page 4 of 5 Summary page 5 of 5 When you cick Finish the project wil be created with the following settings Project directory fmyfirst_niosii Project name myfirst niasii Top devel design entity myfirst niasii Number of files added 0 Number of user libraries added Device assignment Family name Cyclone E Device EPACEZ2F17Cb5 EDA tools Design entry synthesis lt None gt lt gt Simulation lt gt lt gt Timing analysis lt gt Mone gt Operating conditions VCCIMT voltage Junction temperature range Figure 7 7 New Project Wizard Summary page 5 of 5 86 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN Quartus II D myfirst niosii myfirst niosii myfirst ni sil File Edit View Project Assignments Processing Tools Window Help Be omyfirst 110511 QUARTUS I n Hierarchy Files Design Units Oo
128. pu cell nci bench test bench DEO SOPC ptf DEO SOPC sopc SOPC sopcinfo SOPC v DEO SOPC_inst v File name SUPE v Files of type Design Files Add current project Open az Auto Figure 7 44 Open DEO NANO SOPC v 113 Terasic DEO Nano User Manual www terasic com 0 00 00 00 Cancel www terasic com Quartus II D myfirst niosii myfirst niosii myfirst niosii File Edit View Project Assignments Processing Tools Window Help 5 X 6b OO B84 Project Navigator 8 myfrstiniosi v 3 soc 3 Entity dA n 47 7900 0 Sw Cyclone IV E EPACE22F 17C6 gt myfrst niosi DEO NANO SOPC 1 global signals clk 50 reset n the pio ied out port from the pio Y out port from the pio led input clk 50 input reset n wire clk 50 reset n Hierarchy B Files d Design Units Type Message e EJ System Processing Extra Info Info Warning X Critical Warning Error Suppressed Flaa Message Locate 0 00 00 00 M
129. r Peripherals Do i 9 Interval Timer i Multiprocessor Coordination amp PLL Processor Additions Target Clock Settings Device Famay ysoneVE V El cpu instruction master data master jag debug module jtag uart avalon jtag slave onchip memory2 a1 e Error cpu instruction master onchip mermory2 51 cannot be at 0x2000 0x0 or 010000 are acceptable Error cpu data master onchip memory2 51 cannot be at 0x2000 0x0 0x10000 are acceptable Terasic 0 User Manual www terasic com 106 Desc ription Nios Processor Avalon Memory Mapped Master Avalon Memory Mapped Master Avalon Memory Mapped Slave JTAG UART Avalon Memory Mapped Slave On Chip Memory RAM or ROM Avalon Memory Mapped Slave PIO Parallel Avalon Memory happed Slave Figure 7 33 Rename PIO www terasic com Det Remove JA DTE RYA 22 Select System gt Auto Assign Base Addresses as shown in Figure 7 34 Then select File gt Refresh System After that you will find that there is no error in the message window as shown in Figure 7 35 Altera 50 Builder Fie Edit Module 72728 View Tool Help System Contents E Base Addresses Auto Assign R s Insert Avalon ST Adapters Project Show Transformed System Famiy Cycne VE wj Mew comporem Library Ge Avalon Verification Suite amp i Bridges and Ad
130. rld_0 project in the Nios C C Projects tab and select Build Project 129 Terasic DEO Nano User Manual www terasic com www terasic com Chapter 8 DEO Nano Demonstrations 8 1 System Requirements Make sure Quartus II and NIOS II are installed on your PC 8 2 Breathing LEDs This demonstration shows how to use the FPGA to control the luminance of the LEDs by means of pulse width modulation scheme The LEDs are divided into two groups while one group dims the other group brightens vice versa Users can change the PWM wave s duty ratio and frequency to control the LED luminance and repetition rate Figure 8 1 Shows a diagram of PWM signals to drive LED 130 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RYAN 90 Brightness 50 Brightness 10 Brightness Pulse Width Modulation Figure 8 2 Pulse Width Modulation Figure 8 2 shows the relationship between duty cycle and LED luminance Demonstration Source Code e Project directory DEO Default e Bit stream used DEO NANO sof Demonstration Batch File Demo Batch File Folder DEO Defaultdemo batch The demo batch file includes the following files e FPGA Configure File DEO NANO sof Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Connect USB cable to the DEO Nano board and install the USB Blaster driver if necessary e Execute the demo batch file DEO NANO bat
131. roject directory DEO e Bit stream used DEO NANO sof Demonstration Batch File Demo Batch File Folder DEO _ADC demo_ batch The demo batch file includes the following files e FPGA Configure File DEO NANO sof Demonstration Setup e Make sure Quartus II 1 installed on your e Connect the trimmer to corresponding ADC channel to read from as well as the 3 3V and GND signals e Adjust the DIP switch according to the ADC channel connected e Connect USB cable to the DEO Nano board and install the USB Blaster driver if necessary e Execute the demo batch file DEO ADC bat under the batch file folder DEO ADCWeemo batch This will load the demo into FPGA e Adjust the voltage using the trimmer and observe the measurements on the LEDs Note a fully lit LED bar indicates the voltage 1 3 3V and similarly no LED lit indicates OV 135 Terasic 0 User Manual www terasic com www terasic com JA DTE RYA 8 4 SOPC Demo This demostration illustrates how to use the SOPC Builder to create a system with the following functions e Control accelerometer through 3 wire SPI interface e Control analog to digital conversion through 4 wire SPI interface Access EEPROM memory through I2C interface Access EPCS memory B System Block Diagram This section describes the SOPC System Block Diagram of this demo as shown in Figure 8 6 FPGA 80MHz SOPC P S a
132. s between the push buttons and Cyclone IV FPGA J45 IV oem depressed oe released Before ow EBENEN Schmitt Trigger Debounced lt gt Figure 3 4 Pushbuttons debouncing B LEDs There are 8 green user controllable LEDs on the DEO Nano board The eight LEDs which are presented in Figure 3 4 allow users to display status and debugging information Each LED is driven directly by the Cyclone IV E FPGA Each LED is driven directly by a pin on the Cyclone IV E FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off 13 Terasic DEO Nano User Manual www terasic com www terasic co LEDO zz LEDG 45 LED1 LEDG B13 LED2 LEDG A11 LED3 LEDG ADER Cyclone IV LED4 v LEDG D1 LED5 LEDG F3 B1 LED6 LEDG L3 LED7 ve LEDG Figure 3 5 Connections between the LEDs and Cyclone IV FPGA B DIPSwitch The DEO Nano board contains a 4 dip switches A DIP switch provides to the FPGA a high logic level when it 15 the DOWN position and a low logic level when in the UPPER position Table 3 1 Pin Assignments for Push buttons Signal Name FPGA Pin No Description Standard KEY 0 PIN J15 Push button 0 3 3V KEY 1 PIN E1 Push button 1 3 3V Table 3 2 Pin Assignments for LEDs Signal Name FPGA Pin No Description Standard LED 0 PIN A15 LED Green 0 3 3V LED 1 PIN A13 LED Green 1 3 3V L
133. set value Output Register Edge capture register Synchronously capture Edge FALLING Enable bit clearing for edge capture register Generate IRG Level Interrupt CPU when any unmasked pin is logic true Edge Interrupt CPU when any unmasked bit in the edge capture register is logic true Available when synchronous capture is enabled Figure 8 7 PIO Controller B Accelerometer Control The accelerometer controller is a custom SOPC component developed by Terasic The source code is available under the folder DEO_NANO_SOPC_DEMO p TARASIC_SPI_3WIRE In this demo the accelerometer 15 controlled through 3 wire SPI Before reading any data from the accelerometer master should set 1 on the SPI bit in the Register 0x31 DATA FORMAT register as shown in below Figure 8 8 to set the device to 3 wire SPI mode 07 D D5 oo sELF TEST 5 1 INVERT FULL RES Range Figure 8 8 DATA_FORMAT Register 137 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN The data format is configured as 10 bits right justify 2g mode The output data rate is configured as 400 HZ The X Y Z value 1 read using polling mode Before reading X Y Z the master needs to make sure data 1s ready by reading the register 0x30 INT SOURCE as shown below Figure 8 9 and checking the DATA READY bit In the demo multiple byte r
134. soft processors it features a powerful Altera Cyclone IV with 22 320 logic elements 32 MB of SDRAM 2 Kb EEPROM and a 64 Mb serial configuration memory device For connecting to real world sensors the DEO Nano includes a National Semiconductor 8 channel 12 bit A D converter and it also features an Analog Devices 13 bit 3 axis accelerometer device The DEO Nano board includes a built in USB Blaster for FPGA programming and the board can be powered either from this USB port or by an external power source The board includes expansion headers that can be used to attach various Terasic daughter cards or other devices such as motors and actuators Inputs and outputs include 2 pushbuttons 8 user LEDs and a set of 4 dip switches 1 1 Features Figure 1 1 shows a photograph of the DEO Nano Board P f ER ELT Figure 1 1 The DEO Nano Board 5 Terasic DEO Nano User Manual www terasic com www terasic com The key features of the board are listed below e Featured device o Altera Cyclone IV EP4CE22F17C6N FPGA o 153 maximum FPGA I O pins e Configuration status and set up elements o USB Blaster circuit for programming o Spansion EPCS64 e Expansion header o Two 40 pin Headers GPIOs provide 72 I O pins 5V power pins two 3 3V power pins and four ground pins e Memory devices o 32MB SDRAM o 2KbI2C EEPROM e General user input output o green LEDs o 2 debounced
135. t The software provides the compilation results in the Compilation Report tab as shown in Figure 6 45 75 TagasiC Terasic DEO Nano User Manual www terasic com OO JA DTE RYAN Flow Summary Successful Fri Jan 14 17 42 39 2011 10 1 Build 153 11 29 2010 5J Full Version my_first_fpga my_first_fpga IV E EPACE22F 17C6 Final 31 22 320 lt 1 Dedicated logic registers 27 22 320 1 Total registers 27 Total pins Total virtual pins Total memory bits 0 608 256 0 Embedded Multiplier 9 bit elements 0 132 0 96 1 4 25 amp Figure 6 45 Compilation Report Example 6 9 Program the FPGA Device After compiling and verifying your design you are ready to program the FPGA on the development board You download the SOF you just created into the FPGA using the USB Blaster circuitry on the board Set up your hardware for programming using the following steps First connect the USB cable which was included in your development kit between the DEO Nano and the host computer Refer to the getting started user guide for detailed instructions on how to connect the cables Refer to the getting started user guide for detailed instructions on how to connect the cables Program the FPGA using the following steps 1 Select Tools gt Programmer The Programmer window opens as shown in Figure 6 46 76 DEO Nano User Manual www terasic com www terasic com
136. t faintness light select Assignments gt Device Click Device and Options See Figure 6 49 79 Terasic DEO Nano User Manual www terasic com www terasic com Select the family and device you want to target for compilation Device family Show in Available devices list Family Cyclone IVE Package Devices al Pin count Any Target device Speed grade Any Auto device selected by the Fitter Show advanced devices ardCooy compatible Specific device selected in Available devices list ont Other n a zi Device and Pin Options Available devices Name Hemory Bits Embedded multiplier 9 bit elements EPACE22E22C9L 608255 132 608256 132 EPACE22E22T8L 608256 132 EPACE22F 17 Lv 508256 132 4 2 17 6 12 5 608256 132 EP4CE22F17C7 at 508255 EP4CE22F 1708 aT i 608256 608256 IEPACE22F 17C8L 608256 EFdCE27F 1717 608256 EPACE22F 17I8L 608256 IFDACE22I 417 Migration compatibility Companion device Migration Devices Hardcopy 0 migration devices selected Limit DSP to HardCopy device resources Figure 6 49 Device and Options Select unused pins Reserve all unused pins select the As input tri stated option See Figure 6 50 80 Terasic DEO Nano User Manual www terasic com www terasic com 4 Device and Pin Options
137. the system 34 Terasic DEO Nano User Manual www terasic com www terasic com S RYAN The generated system 1 described using several files In particular there 1s the project file qpf the top level Verilog wrapper file v that describes the I O pins you will use in your design and the Quartus II settings file qsf that specifies which pin on the FPGA each I O in your design should connect to A Synopsys Design Constraints sdc file with timing constraints and an HTML file with pin descriptions will be generated as well To proceed with your design open the Quartus II CAD software and open your newly created project You will now be able to implement the logic of your design by describing your design in a hardware description language and connecting it to I Os in the top level wrapper file Once your design 1s complete compile the design using Quartus II and then use the Quartus II Programmer tool to configure the FPGA on the DEO Nano board using the JTAG programming mode Launch DEO Nano System Builder Create New DEO Nano System Builder Project Generate Quartus II Project and Document QPF HTM QSF SDC Launch Quartus II and Open Project Add User Design Logic Compile to generate SOF Configure FPGA Figure 5 1 The general design flow of building a design Terasic DEO Nano User Manual www terasic com www terasic com S RYA 5 3 Using DEO Nano System Builder Th
138. trom liget DrEU Nano U ser Manual WWW terasic com JA DTE RYAN 8 5 G Sensor This demonstration illustrates how to use the digital accelerometer on the DEO Nano board to measure the static acceleration of gravity in tilt sensing applications As the board is tilted from left to right and right to left the digital accelerometer detects the tilting movement and displays it on the LEDs a pie ee J5 4 SREG3 R37 ze MN ar uy 973 ESRI c5 Figure 8 13 DEO Nano on level surface B Design Concept This section describes the design concepts for this demo Figure 8 14 shows the block diagram DEO Nano Board FPGA LED Driver 3 wire SPI Controller Figure 8 14 G Sensor block diagram 142 www terasic com Terasic DEO Nano User Manual www terasic com JA DTE RIA In this demo the accelerometer is controlled through a 3 wire SPI Before reading any data from the accelerometer the controller sets the SPI bit in the Register 0x31 DATA FORMAT register The 3 wire SPI Controller block reads the digital accelerometer X axis value to determine the tilt of the board The LEDs are lit up as if they were a bubble floating to the top of the board Demonstration Source Code e Project directory DEO GsSensor e Bit stream used DEO Sensor sof Demonstration Batch File Demo Batch File Folder DEO GSe
139. w terasic com www terasic com S RYAN Users can connect GPIO expansion card onto GPIO header located on the DEO Nano board as shown in Figure 5 5 Select the appropriate daughter card you wish to include in your design from the drop down menu The system builder will automatically generate the associated pin assignments including the pin name pin location pin direction and IO standard If a customized daughter board 1s used users can select Default followed by changing the pin name and pin direction according to the specification of the customized daughter board Terasic 0 System Builder V1 0 0 ATERA PRT sie UNIVERSITY PROGRAM WwW Cerasic com System Configuration Project Name DEO_NANO DEO Nano FPGA Board CLOCK LEDx8 Button x 2 Dip Switch x 4 32MB M ADC MV EEPROM 2Kb M EPCS Accelerometer 2x13 Pin Header Lg 3 Si on el 1 wus GPIO 0 Header 5 PixelCamera Slee 19 9 Br Name GPIO 1 Header Load Setting Generate None Prefix Name Figure 5 5 GPIO Expansion Group The Name 15 an optional feature which denotes the prefix pin name of the daughter card assigned in your design Users may leave this field empty B Project Setting Management
140. ww terasic com File Window Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file B Programming file type JTAG Indirect Configuration File jic Options Configuration device EPCS64 vi Mode active Serial 3 file jic Remote Local update difference file NONE File name Memory Map File Input files to convert File Data area Properties Start Address Add Hex Data Flash Loader EPACE22 Add Sof Page SOF Data Page 0 DEO sof EP4CEZ7F 17 Ada Device Remove Up Down Properties Figure 9 4 Convert Programming Files Page 150 Terasic DEO Nano User Manual www terasic com www terasic com iy Convert Programming File D CD DE Nano v1 0 9 CDRO X Specify the input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file s
141. y using DEO Nano Tool DEO Nano System Builder 5 1 Introduction The DEO Nano System Builder is a Windows based software utility designed to assist users in creating a Quartus II project for the DEO Nano board within minutes The generated Quartus project files include e Quartus II Project File qpf Quartus II Setting File qsf e Top Level Design File v e Synopsys Design Constraints file sdc e Pin Assignment Document htm By providing the above files DEO Nano System Builder helps to prevents occurrence of situations that are prone to errors when users manually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damaged for wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degeneration because of improper pin assignments 5 2 General Design Flow This section will introduce the general design flow to build a project for the DEO Nano board via the DEO Nano System Builder The general design flow 15 illustrated in Figure 5 1 To create a new system using the DEO Nano System Builder begin by launching the DEO Nano System Builder software The software will then prompt you to specify the name of the project you wish to create as well as the components on the DEO Nano board you wish to you Once your specification 15 complete you can generate
142. y Flow Status In progress Fri Jan 14 17 42 11 2011 as Cyclone EPACE22F17C6 Quartus II Version 10 1Build 153 11 29 2010 3 Full Versior _ How Settings Revision Mame my first fpga a first pll inst2 Flow Elapsed Time Family Cyclone IV E Lm ism EB Flow OS Summary a counter_bus 1 mux inst3 Bonton Analysis amp Synthesis Hierarchy Files df Design Units Tasks B x Flow Compilation Customize i Info 5 registers lost all their fanouts during netitst optimizations The first 5 are displayed below H i Info Generating hard block partition hard Bblock aute generated inst EC ij Info Implemented 38 device resources after synthesis the final resource count might be dirferent ij Info Quartus II Analysis amp Synthesis was successful 0 errors 0 warnings JA Pr 27 Extra Info Info 27 Warning Critical Warning X Error X Suppressed dp D of 107 ee Locate _ 66 231 24 00 00 13 Messages Figure 6 44 Compilation Message for project When compilation is complete the Quartus II software displays a message Click OK to close the message box The Quartus II Messages window displays many messages during compilation It should not display any critical warnings it may display a few warnings that indicate that the device timing information is preliminary or that some parameters on the I O pins used for the LEDs were not se
143. you will perform the following tasks Create a design that causes LEDs on the development board to blink at two distinct rates This design is easy to create and gives you visual feedback that the design works Of course you can use your DEO Nano board to run other designs as well For the LED design you will write Verilog HDL code for a simple 32 bit counter add a phase locked loop PLL megafunction as the clock source and add a 2 input multiplexer megafunction When the design is running on the board you can press an input switch to multiplex the counter bits that drive the output LEDs 6 4 Assign The Device Begin this tutorial by creating a new Quartus II project A project is a set of files that maintain information about your FPGA design The Quartus II Settings File qsf and Quartus II Project File qpf files are the primary files in a Quartus II project To compile a design or make pin assignments you must first create a project The steps used to create a project are 45 Terasic DEO Nano User Manual www terasic com www terasic com JA DTE RIA 1 In the Quartus II software select File gt New Project Wizard The Introduction page opens as shown in Figure 6 8 X Project Wizard Introduction The New Project Wizard helps you create a new project and preliminary project settings induding the following Project name and directory of the top evel design entity Project files and libraries Target d

PMP10580 DE0-Nano User Manual (Terasic

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