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Mentor Graphics VHDL Reference Manual

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1. CONFIGURATION cntr cfgl OF counter IS FOR gen counter Architecture FOR gl Outer generate FOR g2 Nested generate FOR ff7 jkff USE ENTITY work 3kff bhv PORT MAP clk gt clk j gt j gt k q gt q gb gt qb END FOR END FOR FOR g3 FOR ffx jkff USE ENTITY work 3kff bhv PORT MAP clk gt clk j gt j k gt k q gt q qb gt qb END FOR FOR andx and2 USE ENTITY work and2 bhv PORT MAP a gt a b gt b y gt y END FOR END FOR FOR g4 FOR ff0 jkff USE ENTITY work 3kff bhv PORT MAP clk gt clk j gt j k gt k q gt q qb gt qb 7 END FOR END FOR END FOR END FOR END cntr cfgl 8 42 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations component configuration A component configuration specifies the component bindings within a block of an architecture body Construct Placement block configuration Syntax component configuration for component specification use binding indication block configuration end for Description A component configuration serves the same purpose within a configuration declaration that a configuration specification serves within an entity dec
2. this must mux design entity Mee The configuration declaration in this example lines 58 through 74 binds the inverter OR gate and AND gate components of the multiplexer to particular Mentor Graphics VHDL Reference Manual July 1994 8 37 Design Entities and Configurations entities and architectures The first line of the declaration names the configuration ver1 and names the entity declaration mux to which the configuration applies If you use a name at the end of the declaration it must match the identifier given in the first line as in line 74 The use clause USE WORK ALL makes the work library visible to the configuration You can add any number of use clauses at this point to make additional library information visible or to add user defined attributes Beginning on line 61 and ending on line 73 is a block configuration This configuration makes the top level components of architecture st ruct visible for binding Within the block configuration are three component configurations The first component configuration beginning on line 62 and ending on line 66 binds the component labeled U1 This component which is an instance of inverter 1s bound to the entity declaration inv and architecture body inv_basic that reside in my parts lib The component configuration for U1 also includes a generic map which sets the val
3. TYPE ref array IS ARRAY natural RANGE lt gt OF integer VARIABLE x ref array 0 TO 899 Size is 900 VARIABLE z ref array 0 TO 99 Size is 100 VARIABLE comp arry ref array 0 TO 999 Size is 1000 BEGIN comp arry z concatenate the arrays size is 1000 END PROCESS You concatenate the one dimensional arrays using the concatenation operator amp You can also concatenate an array with a single element value of the same type For a discussion on concatenation refer to page 2 23 You can also select a contiguous subset of a one dimensional array by using a slice name A slice name designates a portion of a one dimensional array as the following example shows PROCESS sens sig TYPE ref array IS ARRAY natural RANGE lt gt OF integer VARIABLE main bus ref array 0 TO 255 Declare arrays VARIABLE addr data ref array 0 TO 127 BEGIN addr main bus 0 TO 127 data main bus 128 TO 255 END PROCESS For more information on slice names and slicing arrays refer to page 3 9 5 28 Mentor Graphics VHDL Reference Manual July 1994 Types record type definition A record is a composite type whose elements can be of various types The record type definition specifies a particular record type Construct Placement composite type definition t
4. ARCHITECTURE FUNCTION x RETURN integer BEGIN PROCESS PROCEDURE x gt VARIABLE x boolean C BEGIN B ja SA da C END o BEGIN END PROCESS END Figure 3 7 No Homograph Instance In Figure 3 7 function x is declared in scope C and procedure x is declared in scope A In this case function x and procedure x are not homographs of each other because the system can determine a difference between the two x values by the context Therefore overloading is allowed for both of the values If you replace the function with a procedure the two procedures are homographs of each other if the procedures have the same parameter type because the system cannot determine a difference between the two identifiers Mentor Graphics VHDL Reference Manual July 1994 3 21 Naming Scope and Visibility use clause The use clause allows you to make directly visible a declaration in a package or library that is visible by selection Construct Placement block declarative item context item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax use clause use selected name selected name Description You can specify one or more selected names to identify declarations that you want to become directly visible For more information on selected names refer to page 3 4 You
5. Mentor Graphics VHDL Reference Manual July 1994 7 9 Subprograms subprogram body A subprogram body defines how of a procedure or function behaves using a sequence of sequential statements in the subprogram statement part of the body Construct Placement block declarative item entity declarative item package body declarative item process declarative item subprogram declarative item Syntax subprogram body subprogram specification is subprogram declarative part begin subprogram statement part end designator subprogram declarative part subprogram declarative item subprogram declarative item subprogram declaration subprogram body type declaration subtype declaration constant declaration variable declaration file declaration alias declaration attribute declaration attribute specification use clause subprogram statement part sequential statement 7 10 Mentor Graphics VHDL Reference Manual July 1994 Subprograms Description If you use a designator at the end of the subprogram body it must be the same as the name you use in the subprogram specification The subprogram specification appears in the subprogram body and in the subprogram declaration The reason for this duplication is that the declaration of a subprogram is not required When you do not declare a procedure or function the subprog
6. 241101 0000 base 2 representation of decimal 80 16150 base 16 representation of decimal 80 16 A0 base 16 representation of decimal 160 2431010 00004 base 2 representation of decimal 160 The following are examples of valid real literals using different bases 2 1 0 e3 base 2 representation of decimal 1000 0 1644 2 base 16 representation of decimal 4 125 Character Literals A character literal is a single graphic character from the 95 printable ASCII characters You must enclose a character literal with single quote marks as the following syntax shows character literal graphic character The following examples show some possible character literals ror F 7 ur FA F Z 7 S A character literal is case sensitive Therefore an X is not equal to an x and Z is not equal to z 1 18 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements String Literals A string literal consists of zero or more graphic characters String literals must be enclosed between double quote marks The following diagram shows the syntax for a string literal string literal graphic character When you use the double quote character within a string literal another double quote mark must precede it For example to include the string message within the string literal The string will
7. test lt GUARDED data AFTER test lt GUARDED cntrl AFTER 2 ns WHEN enl 1 2 ns WHEN en2 1 ELSE ELSE test AFTER 3 ns test AFTER 3 ns Signal test gt m gt eni en2 data cntrl 11 6 Mentor Graphics VHDL Reference Manual July 1994 Signals This second example shows the declaration of a signal called test of type bit and signal kind register It also shows the use of this signal in a simple circuit The partial code that describes the circuit is the same code as in the previous example except for the signal kind SIGNAL test wired or bit REGISTER signal declaration partial code descriptions of circuit with signal test D cntrl AFTER D data AFTER test lt GUARD test GUARDE E 2 ns WHEN enl 1 2 ns WHEN en2 1 ELSE ELSE test AFTER 3 ns test AFTER 3 ns 4 Signal gt lt p guards gt Signal test Value en2 data cntrl Mentor Graphics VHDL Reference Manual July 1994 Signals disconnection specification You use the disconnection specification to specify the time delay for turning off a driver of a guarded signal when the guard is false Construct Placement block declarative item entity declarative item package declarative it
8. operator symbol selected name 1ndexed name slice name attribute name S 3 3 lt next statement next oop label when y condition gt gt 6 38 null_statement gt null gt H 6 39 numeric literal abstract literal gt physical literal gt 1 15 A 46 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary object declaration constant declaration variable declaration Signal declaration g T 4 10 operator symbol string literal E 7 6 options guarded transport 6 23 Mentor Graphics VHDL Reference Manual July 1994 A 47 Syntax Summary package body package body gt package _simple_name Le is package body declarative _____ end hr package simple name L 5j gt V E 9 15 package body declarative item Subprogram declaration y subprogram body type declaration subtype declaration gt constan
9. attribute declaration component declaration entity declaration configuration declaration y subprogram declaration package declaration N M 4 3 A 26 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary design file 7 design unit g gt 9 3 design unit context clause library unit 9 3 designator x identifier operator symbol 7 6 digit x x x x ov fe Y Pa Y ov Y Y fo Y fe Y Y x Y Y Y OJ LL 12 X9 we 9 CIF 85 9 i oe di X Ny iM NS Em iS N NL NS gt 1 5 direction gt to i downto P 5 5 Mentor Graphics VHDL Reference Manual July 1994 A 27 Syntax Summary disconnection_specification al a o A guarded signal specification after time expression gt 11 8 discrete range discrete subtype indication element association ychoices gt expression 2 8 element declaration identifier list 28 p element subtype definition gt gt 5 29
10. The qsim 12state values and strengths map one for one with QuickSim II This has an implicit resolution function that matches QuickSim II The qsim 12state and the qsim 12state vector types are provided for accessing all state information and for interfacing to other Mentor Graphics primitives Only conversion functions to and from are provided I TYPE dqdsim i state IS SXR SXZ SXS SXI SOR 80275 9095 SOI SIR SIG SiS SII ys Now a vector for gsim_12state TYPE qsim 12state vector IS ARRAY natural RANGE OF qsim 12state Mentor Graphics VHDL Reference Manual July 1994 9 37 Design Units and Packages Resol RI ution function and resolved subtype for qsim 12state UNCTION qsim 12state wired input qsim 12state vector ETURN qsim 12state This resolution function implements QuickSim s resolution function as follows SXR SXZ SXS SXI SOR 502 SOS SOI SIR 512 515 SII SXR SXR
11. Declaration Occurring Within Formal parameter Subprogram declaration Declaration Package declaration Local generic Component declaration Local port Component declaration Formal generic Entity declaration Formal port Entity declaration This extension is also valid if a separate subprogram declaration is missing and the subprogram body is used as the declaration The declaration must occur immediately within the package declaration The library unit scope and logical library name scope in a design library extend beyond the immediate scope Visibility Visibility refers to an item that has a unique name thereby making it an item you can refer to in a code description An item may be hidden from other portions of code by the nesting of language constructs and by the use of homographs Figure 3 5 shows the variable declared within the procedure is visible only to the highlighted area or its scope An item declared in the entity declaration such as signall in Figure 3 4 can be visible to the entire scope identified by region C unless it is hidden as described later 3 16 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility ARCHITECTURE SIGNAL BEGIN VARIABLE PROCEDURE VARIABLE BEGIN END BEGIN END PROCESS END Figure 3 5 Visibility Visibility Rules The visibil
12. 3 In the following string literals double quotes have been replaced by the percent sign lights will turn green 9 SlightsSswillS turn green Mentor Graphics VHDL Reference Manual July 1994 1 7 Lexical Elements Identifiers An identifier is a name that you assign to a design item The syntax for an identifier 1s as follows identifier letter _ letter digit Identifiers must conform to the following rules S e The first character of an identifier must be a letter e Identifiers are case insensitive For example identl IDENT1 and Ident1 are all the same identifier in VHDL No spaces are allowed in identifiers because the space character is a separator You cannot use the as a leading or trailing character and it cannot be used two or more times in succession without being separated by a letter or digit Here are some valid identifiers d FF my Test circuit R169 ExampleOut Here are some invalid identifiers 2test design first character must be a letter EBD leading underscore not allowed R14 trailing underscore not allowed Example Out no space allowed 1 8 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements Reserved Words S Reserved words have specific meaning to VHDL therefore you cannot use a reserved word as an identifier For example you are not allowed to declare a variable name a
13. In this example L is the parameter for the left operand and R is the parameter for the right operand The function designator for operator overloading functions is an operator symbol which is a string literal Therefore the operator you wish to overload must be enclosed in double quotes For more information about predefined operators refer to page 2 16 Rules for Operator Overloading The following rules apply to operator overloading e The subprogram specification of a unary operator abs not and must have only one parameter The subprogram specification of a binary operator must have two parameters the first for the left operand the second for the right operand e Overloading is legal for and as both unary and binary operators n_n e Overloading the operator has no effect on choices in the case statement or the selected signal assignment statement You can make a function call by using the function call notation or by using the operator notation only For example OR a b OR function call with parameters a and p a OR b operator notation only 7 18 Mentor Graphics VHDL Reference Manual July 1994 Subprograms Complete Subprogram Example The following example shows the code description for the memory programmer and tester The elements of this code are explained individually in the preceding subsections The contents of the packa
14. 2 3 In the previous array the star represents the array contents Since the predefined attributes for array objects relate to the array bounds the examples do not require actual array element values When specifying a parameter n you are either referencing an index row from above the dashed line or an index column to the left of the solid line For example matrix high 1 parameter n 1 The parameter 1 is referencing the boxed column shown in the following diagram 10 8 Mentor Graphics VHDL Reference Manual July 1994 Attributes 1 N 1 2 3 If you specify a parameter of 2 as follows matrix high 2 parameter N 2 the parameter 2 is referencing the boxed row shown in the following matrix 1 2 3 You cannot use parameter values that exceed the dimension of the array For example if you specify n 3 using the example array an error occurs because the example array is two dimensional not three dimensional When you are examining arrays the ascending and descending range refers to the direction of the index The boxed regions of Figure 10 2 illustrate this concept Mentor Graphics VHDL Reference Manual July 1994 10 9 Attributes left high right low Descending gt INDEX 9 8 7 6 left low TE eer 2 5 Ascending 2 i E right high 3
15. Convert Type To Type Integer Floating point Floating point Integer Integer Different integer Floating point Different floating point The following diagram shows the syntax for type conversion type conversion type mark expression The following example shows a type conversion VARIABLE x real 256 55 variable declarations VARIABLE y z integer 5 z t integer x y Converts two different types and assigns the value to z In the preceding example if the variables x and y are at their default value the value of z is 262 When a floating point type is converted to an integer type the floating point value converts to the nearest integer Floating point values that are halfway between two integers are rounded up A type conversion converts the expression to the base type of the type mark The type mark designates a type or subtype If the type mark is a subtype the range is checked to determine if the result of the conversion is valid for the subtype You can always convert an expression of any type to its same type 2 12 Mentor Graphics VHDL Reference Manual July 1994 Expressions Type conversions are allowed for all expressions except aggregates string literals allocators and those involving the literal null You can use an expression enclosed by parentheses only when the expression itself is not an aggregate or string lite
16. 2 The following example shows an architecture statement part within a partial code description for a traffic light controller ARCHITECTURE mixed OF tlc IS SIGNAL count bit vector 1 TO 3 B 000 BEGIN architecture statement main green part from this point on BLOCK main color green PORT SIGNAL c 1 m IN rf bit SIGNAL cnt IN bit vector 1 TO 3 SIGNAL mc INOUT color The PORT MAP establishes the corresponding mapping of the internal and external signals PORT MAP c gt cross 1 gt left m gt main cnt gt count mc gt main color Signal control is used to determine the correct color transition based upon the counter and the three sensors SIGNAL control bit vector 1 TO 6 BEGIN Assign the values of cnt c l and m to control if main color is green control lt GUARDED cnt c 1 amp m 1st concurrent statement WITH control SELECT 2nd concurrent statement mc lt GUARDED yellow WHEN B 011010 yellow WHEN B 011110 yellow WHEN B 011100 yellow WHEN B 111011 yellow WHEN B 111111 yellow WHEN B 111101 green WHEN OTHERS END BLOCK main green
17. subprogram declaration N subprogram body N gt type_declaration Po subtype declaration N gt constant declaration variable declaration file declaration alias declaration attribute declaration attribute specification use clause 6 41 y process_declarative_part _ process_declarative_item 6 41 Mentor Graphics VHDL Reference Manual July 1994 A 53 Syntax Summary P E ae process_statement process _label gt fer process a Y sensitivity_list gt _ process_declarative_part begin process statement part lt p end process process label E gt l 6 41 process_statement_part BE 2 sequential statement gt 6 41 qualified expression type mark i j Y expression gt type mark Y aggregate ___ _ 2 10 A 54 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary range range attribute name P simple expression direction simple expr
18. In the previous example the array vacation is a one dimensional array type that is constrained by a range of the enumerated type month The elements of the array are specified to be of the type nours which are floating point numbers If constrained arrays were the only arrays allowed in VHDL you could never specify two arrays that have the same type but different range bounds This is why the unconstrained array exists An unconstrained array is an array in which you specify the type of the indices but do not specify the range In place of specifying the range you use the box symbol In this way you can declare the array type without declaring its range and then you can declare as many arrays of the same type with the desired range This allows you to pass arrays of arbitrary size as parameters Figure 5 3 shows this concept of unconstrained arrays The following example shows you the declaration of an unconstrained array and the declaration of two arrays of the same type as the unconstrained array which could possibly appear elsewhere in your code description TYPE data array IS ARRAY integer RANGE lt gt OF integer With the unconst array declared the following code can be used in a hardware description VARIABLE address data array 0 TO 255 VARIABLE hex code data array 255 TO 1023 5 26 Mentor Graphics VHDL Reference Manual July 1994 Types Co
19. guard expression SIGNAL z bit plock declarative item BEGIN 2 lt GUARDED a z gets a if test 71 END BLOCK sig assign e lt D sig test Mentor Graphics VHDL Reference Manual July 1994 11 9 Signals Multiple Drivers and Resolution Functions Every signal you define that is the target of a signal assignment has a driver If the signal has more than one driver is a target for more than one signal assignment statement you need to define a resolution function The resolution function is a subprogram that defines what single value the signal should have when there are multiple drivers for that signal The input parameter to the resolution function is an array that contains all the driver values for the signal The resolution function is called every time the signal is active For information on subprograms functions and procedures refer to page 7 1 For example you create the signal test that has three drivers The system creates an array that contains the value of the drivers as the input to a resolution function Assume that signal test is of the following my qsim state type TYPE my qsim state IS X 0 1 727 You then write a resolution function that represents a wired OR function based on a driver resolution table for the states 1 X 0 and Z The resolution function returns a resolved value for the
20. process statement concurrent procedure call concurrent assertion statement concurrent signal assignment statement component instantiation statement generate statement gt 6 7 A 22 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary condition boolean expression 6 49 condition gt condition clause until 6 49 conditional signal assignment target gfe lg options J conditional waveforms gt 6 25 conditional_waveforms gt waveform when condition else p waveform Mentor Graphics VHDL Reference Manual July 1994 A 23 Syntax Summary 6 25 configuration declaration configuration E N configuration simple name of entity name is configuration declarative part block configuration end configuration simple name gt D b ae E 8 35 configuration declarative item use clause attribute specification 8 35 configuration declarative part configura
21. Overloaded and Operators FUNCTION 1 Y std ulogic RETURN std ulogic FUNCTION 1 Y std ulogic RETURN std ulogic gt Vectorized Overloaded Arithmetic Operators FUNCTION 1 r std ulogic vector RETURN std ulogic vector FUNCTION l r std ulogic vector RETURN std ulogic vector FUNCTION l r std ulogic vector RETURN std ulogic vector FUNCTION l r std ulogic vector RETURN std ulogic vector FUNCTION MOD 1 r std ulogic vector RETURN std ulogic vector FUNCTION REM 1 r std ulogic vector RETURN std ulogic vector FUNCTION l r std ulogic vector RETURN std ulogic vector Conversion Functions FUNCTION Convert to Bit val std ulogic vector RETURN bit_vector FUNCTION Convert_to_Integer val std_ulogic_vector x integer 0 RETURN integer FUNCTION Convert_to_Std_ulogic val integer size integer RETURN std ulogic vector FUNCTION Convert to Std ulogic val bit vector RETURN std ulogic vector FUNCTION Convert to Std ulogic val bit RETURN std ulogic END std logic 1164 extensions Mentor Graphics VHDL Reference Manual July 1994 9 29 Design Units and Packages Package Textio P
22. lt D mixed Mentor Graphics VHDL Reference Manual July 1994 8 19 Design Entities and Configurations Components Components are the basic units of structural design descriptions Components allow you to declare a device and instantiate it within an architecture without having to specify the actual architecture of the instantiated device You then use a configuration specification or configuration declaration to bind the component instantiation to the entity architecture that describes the component If you want an explicit binding this specification must appear before the instantiation of a component Otherwise the default binding is used Figure 8 2 illustrates the component concept 8 20 P d Architecture ET Architecture Body Entity Declaration Body Architecture B Component e9y Declaration Component Instantiation Configuration Specification eS Architecture Body Figure 8 2 Components Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Component Declarations A component declaration defines a design entity interface that is used in a component instantiation statement The component declaration is also described on page 4 36 The following examples show some possible component declarations COMPONENT and 2 GENERIC prop delay time PORT a b IN bit
23. TYPE mem address IS RANGE O TO 1023 SUBTYPE mem data IS mem address RANGE 0 TO 63 VARIABLE offset mem address CONSTANT decade mem data 10 5 10 Mentor Graphics VHDL Reference Manual July 1994 Types Predefined Integer Types There is one predefined integer type integer Integer is specified in package standard as follows TYPE integer IS RANGE 2147483648 TO 2147483647 This assumes a 32 bit machine There are two predefined subtypes specified in package standard SUBTYPE natural IS integer RANGE 0 TO integer high SUBTYPE positive IS integer RANGE 1 TO integer high CAUTION Do not use predefined type or subtype names for your own definitions While it is possible to do so it can become very confusing for you to keep track of when the system is using its definition of a predefined type or is being overwritten to use your definition Mentor Graphics VHDL Reference Manual July 1994 5 11 Types floating type definition A floating point type provides real number approximations Construct Placeme scalar type definition type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax floating type definition range constraint Def
24. The following subsections discuss each predefined type attribute in detail Mentor Graphics VHDL Reference Manual July 1994 10 41 Attributes base Kind Type Prefix Any type or subtype Evaluation Result The result is the base type of the type you specify in the prefix Example The following code defines a type and a subtype TYPE env parms IS cap volt temp min max type decl SUBTYPE el par IS env parms RANGE cap TO temp subtype decl The following code examines the right bound of env parms The attribute value is the right bound of the base type of the subtype which is the value max el par base right Returns right bound of the base type of the subtype el par which is max el par right Returns right bound of el par which is temp Restrictions gt This attribute must be used in conjunction with another attribute where base is then considered the prefix as the preceding example shows 10 42 Mentor Graphics VHDL Reference Manual July 1994 Attributes high Kind Value Prefix Any scalar type or subtype Result Type The same type as the prefix type Evaluation Result The result is the upper bound of the specified prefix type Example The following code defines address range TYPE address range IS RANGE 0 TO 16 The following code returns the value 16 which is the upper bound of address range addr
25. element subtype definition subtype indication gt 5 29 A 28 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary entity aspect entity entity name lt a architecture identifier gt PEEN confi guration gt configuration identifier Na gt 00 en 2 8 31 Mentor Graphics VHDL Reference Manual July 1994 A 29 Syntax Summary entity class A 30 gt entity Mp procedure y Y type gt e libel architecture funcion subtype variable configuration package constant gt component gt 10 55 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary entity declaration entity entity simple name is entity_header y jentity declarative part begin entity statement part gt end entity _simple_name N 8 4 entity declarative item subprogram declaration subprogram body type declaration N subtype declaration constant declaration No 5 signal declaration file declaration attribute specification disconnecti
26. Attributes Components Types Signals Statements Subprograms Declarations Expressions _ Lexical Elements Naming Scope and Visibility Lexical Elements Y Y Y Y Y Identifier Comment Literal Delimiter Y Numeric Character String Figure 1 1 Lexical Elements 1 2 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements Definition of Lexical Elements Lexical elements are the items used to form the VHDL language A lexical element is one of the following e An identifier or a reserved word A comment A literal O Numeric O Character O String A delimiter VHDL has a character set that contains 95 printable characters From this character set lexical elements are formed Lexical elements in turn form the language constructs that are the building blocks of VHDL For a complete summary of all the language constructs see the syntax summary appendix starting on page A 1 You combine the language constructs to create design units which are a group of specific language constructs that can be compiled independently and placed in a design library For information on design units refer to page 9 1 Finally you put the design units together to form the VHDL code description of your design Figure 1 2 shows how lexical elements fit into the coding process Mentor Graphics VHDL Reference Manual July 1994 1 3 Lexical Eleme
27. Using the preceding example the following example shows the equivalent process the system creates for the conditional signal assignment PROCESS data a data b enl en2 sens list created BEGIN from all signals IF enl 1 THEN test lt TRANSPORT data a AFTER 2 ns ELSIF en2 1 THEN test lt TRANSPORT data b AFTER 2 ns ELSE test lt TRANSPORT 1 AFTER 2 ns END IF ND PROCESS tz 6 26 Mentor Graphics VHDL Reference Manual July 1994 Statements selected signal assignment The selected signal assignment form of the concurrent signal assignment statement results in an equivalent process statement generated by the system that assigns values to signals using a case statement format Construct Placement concurrent signal assignment statement concurrent statement architecture statement part block statement part Syntax selected signal assignment with expression select target lt options selected waveforms selected waveforms waveform when choices waveform when choices Example The following example shows a possible use of the selected signal assignment ARCHITECTURE data flow OF tester IS SIGNAL test data a data b my qsim state SIGNAL enl bit BEGIN WITH enl SELECT test lt data a WHEN 0 data b WHEN 1 END data
28. defined that contains the following definitions TYPE my qsim state IS X 0 1 727 FUNCTION L R my qsim state RETURN my qsim state FUNCTION and L R my qsim state RETURN my qsim state FUNCTION L R my qsim state RETURN boolean Ambiguity occurs when you call this package in a portion of code and also use an expression such as the following a b AND c d a b c and d are type my qsim state In this expression you do not know which overloaded operator is used To resolve this ambiguity you could use the following qualified expression boolean a b AND boolean c d This qualified expression specifies that the boolean operator is to be used Here are some guidelines for the use of qualified expressions The operand value determines the qualified expression value The expression or aggregate operand must have the same base type as the type mark At the location the qualified expression is evaluated the expression operand must belong in the subtype specified by the type mark Mentor Graphics VHDL Reference Manual July 1994 2 11 Expressions Type Conversions S A type conversion provides you with a method for converting from one type to another closely related type For more information on types refer to Section 5 Table 2 1 lists the valid type conversions that VHDL can perform Table 2 1 Type Conversions
29. pn Qo J USE prim lib gates and2 AND from gates in prim lib USE gen lib or2 gen lib exor OR and XOR gates from gen lib The selected indexed slice and attribute names require a prefix As the following BNF description shows the prefix can be either a name or a function call prefix name function call When a name prefix is a function call the suffix designates an attribute element or slice of the function call result For information on function calls refer to page 7 15 When a name is evaluated the item designated by the name is determined If the name has a prefix the name or function call designated by the prefix is evaluated Throughout this manual there are several rules that involve a concept called the longest static prefix The longest static prefix is equivalent to the static signal name you use If you do not use a static signal name the longest static prefix is Mentor Graphics VHDL Reference Manual July 1994 3 5 Naming Scope and Visibility the static part of the name you use For example sname 5 7 E Static Name Longest Static Prefix In the preceding example the signal name contains the static expressions 5 7 which designate the name as a static signal name Therefore the entire signal name is the longest static prefix Another example follows Non Static Expression m sname 5 3 EE gt sname 5 Static Na
30. y range constraint gt base unit declaration X secondary unit declaration gt end gt units l gt 5 15 port clause port p Oo port_list gt gt gt 8 8 port list interface signal declara ion 8 8 A 50 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary port map aspect prefix primary gt port l map dd LO 3 name literal aggregate function call qualified expression type conversion allocator gt expression port association list gt gt 8 32 name function call 3 5 gt gt 2 6 A 51 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary primary unit entity declaration 3 configuration declaration package declaration p 9 3 procedure call statement gt procedure name actual parameter part gt gt gt 6 40 A 52 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary process declarative item
31. ia SS of E index specification gt A 18 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary 8 39 block statement block label La Took 7 lt Y v guard expression WP block header block declarative part begin js gt block statement part end rl block pblock_label ide 6 12 block statement part concurrent statement gt 6 13 case statement J case expression LM is NN E gt case statement alternative ___ end case x N J 6 15 Mentor Graphics VHDL Reference Manual July 1994 A 19 Syntax Summary case statement alternative when choices gt gt sequence of statements 6 15 character literal graphic character gt 1 18 choice simple expression _ discrete range element simple name gt others gt 2 8 choices choice ls 2 8 component configuration for component specification 7 use binding indication bl
32. B secondary unit declaration The secondary unit declaration is also used to define a unit name The secondary unit declarations are defined in multiples of the root or multiples of a previously defined secondary unit Mentor Graphics VHDL Reference Manual July 1994 5 15 Types Description gt The range you specify as the range constraint must be between 2147483648 and 12147483647 inclusive on a 32 bit machine The range constraint bounds you specify in the physical type definition must be an expression that can be evaluated during the current design unit analysis a locally static expression and must be an integer type The range constraint bounds can have different sign values For example TYPE phy_type IS RANGE 2147483647 TO 2147483647 Different signs The following example shows an illegal range constraint bound TYPE test int IS RANGE 0 TO 10 5 In the preceding example the right or high range constraint bound is 10 5 which is of a floating point type Since the bound is not of an integer type it is nota legal bound The following example shows another illegal condition TYPE my int IS RANGE 0 TO mem value illegal range bound In the preceding example the right or high range constraint bound is the variable mem value Which has been previously declared in the same design unit Therefore mem value is not a locally static expression and is not legal as a
33. Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax null statement null Description You can use this statement in your code as a placeholder for readability or to specify that no action is to be taken when a condition is true The most common use of the null statement is within the case statement Since an action for all the possible values for a case statement expression is required you can use the null statement as a choice for situations that require no action For more information on the case statement refer to page 6 15 Example The following example uses a null statement within a case statement CASE opcode IS WHEN 00 gt instruction add WHEN O1 gt instruction sub WHEN 10 gt instruction jmp WHEN OTHERS gt NULL gt specify no action END CASE This example assigns the variable instruction a value depending on the opcode value Values other than 00 01 or 10 require no action Mentor Graphics VHDL Reference Manual July 1994 6 39 Statements procedure call statement The procedure call statement causes the execution of a procedure body Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax procedure call statement procedure name actual parameter par
34. signal declaration A signal declaration declares an object that has a current value a history and a projected value Construct Placement block declarative item entity declarative item object declaration package declarative item Syntax signal declaration signal identifier list subtype indication signal kind expression signal kind register bus Definitions B identifier list Lists one or more signal names Multiple names must be separated by commas B subtype indication Indicates the subtype of the signal s and any resolution function or constraints that apply The subtype must not be a file type or access type B signal kind Valid entries are bus or register B expression Defines the initial value of the signal Description lt 0 0 A signal declaration specifies the simple names type kind and default value of an object that has a current value a history and a projected value Using previous signal concepts as a foundation you can now explore the details of signals One of these details is the signal declaration Throughout this section you have seen examples of signal declarations The following list shows what a signal declaration accomplishes 11 14 Mentor Graphics VHDL Reference Manual July 1994 Signals Assigns names to the signals identifier list e Defines the resolution function the type of the signal and any index or range constraints subtype indi
35. Construct Placement concurrent statement architecture statement part block statement part generate statement Syntax generate statement generate label generation scheme generate concurrent statement end generate generate label generation scheme for generate parameter specification if condition parameter specification identifier in discrete range Definitions B generate label Identifies the generate statement If a label appears at the end of the generate statement it must repeat the generate label B generation scheme A for generation scheme specifies how many times a block of concurrent statements is to be replicated An if generation scheme causes one replication if the condition expression evaluates to TRUE otherwise it generates no repetitions B parameter specification In a for generation scheme defines the generate parameter The generate parameter takes on each value in the specified discrete range as the 6 30 Mentor Graphics VHDL Reference Manual July 1994 Statements concurrent statement block is replicated generated once for each value in the specified discrete range The generate parameter acts as a constant whose value may be read it has meaning only within the generate statement it applies to Description You can describe repetitive structures in a structural design by individually instantiating all the required subcomponents or you can use generate stateme
36. Declarations Section 4 Declarations This section discusses the subject of declarations and how to use them A declaration defines a design item and relates an identifier to that design item For the system to manipulate design items you must declare them explicitly or they must be declared implicitly The following ordered list shows the topics and related constructs discussed in this section type declaration 44 subtype declaration 47 object declaration 4 10 constant_declaration 1 1 4 13 variable declaration J J 4 15 Signal Declaration Summary gt J 4 17 file declaration o 448 Interface Declarations 4 interface_list___ 0 0 0 0 0 0 0 0 0 4 interface constant declaration o 1 1 4 24 interface_signal_declaration AAA 4 26 interface_variable_declaration gt gt gt gt 1 1 1 429 association list o 1 1 1 Aal alias declaration o o 1 1 4 35 component declaration 4 36 Type Conversion Functions 437 You must declare design items before you can operate assign values or otherwise manipulate them Every declaration has a defined text region called the declaration scope For information on scope and visibility refer to page Mentor Graphics VHDL Reference Manual July 1994 4 1 Declarations 3 12 The declared items are visible only
37. Each choice in the case statement alternative must be the same type as the expression you use All the possible values of the expression must appear in the choices for the case statement and must be of the same type as the expression and locally static You can use each choice only once You use the choice of others to represent any values of the expression that you do not list in the case statement alternative This choice must be the last alternative The reserved word others must be the only choice in this situation The following example shows an illegal use of others Mentor Graphics VHDL Reference Manual July 1994 6 15 Statements CASE slt IS WHEN 1 gt sctl lt false WHEN 0 OTHERS gt sctl lt true Illegal More than one END CASE choice when using OTHERS Example The following example shows a use of the case statement CASE traffic sensor IS traffic sensor is expression WHEN 00 gt color lt red Case statement WHEN 01 gt color lt yellow alternatives WHEN 10 gt color lt green WHEN OTHERS gt color lt flashing gt END CASE The preceding example states the following assign the signal color a value depending on the value of the expression traffic_sensor 6 16 Mentor Graphics VHDL Reference Manual
38. Deferred constants in packages 9 14 Delay concepts for modeling 11 19 Delimiters 1 22 Delta delay 11 20 Design entity 8 2 Design file 9 3 Design libraries 9 8 Design library complete example 9 10 Design unit definition of 9 1 Designator 5 31 Direct visibility 3 18 Disconnection specification 11 8 Discrete array type 2 30 Driver 6 46 11 4 Driver definition of 11 3 11 4 Drivers 11 4 Index 2 Drivers multiple 11 10 Element association named 2 9 Element association positional 2 9 Entity aspect 8 31 Entity declaration 8 4 Entity declarative part 8 10 Entity header 8 6 Entity statement part 8 12 Enumeration types 5 19 Equality operator 2 29 Exit statement 6 28 Expanded name 3 7 Exponentiation 2 18 Expression 2 3 Expression general rules for 2 4 Extended digit 1 18 File declarations 4 18 File logical name 4 19 File mode 4 19 File types 5 34 Files implicit subprograms created 5 34 Floating point arithmetic important note to read 2 17 Floating point types 5 12 Formal ports 8 23 Formals 4 31 Function 7 3 Function call as a primary 2 10 Function calls 7 15 Function calls rules for using 7 15 Functions type conversion 4 37 Generate statement 6 30 Generic map aspect 8 32 Generics 8 7 Globally static array subtype 2 36 Globally static discrete range 2 35 Globally static expressions 2 32 Globally static index constraint 2
39. G OUT Dit ND COMPONENT tz COMPONENT inv PORT in line IN bit out line OUT bit ND COMPONENT tz COMPONENT my design GENERIC x integer 5 z real 0 5 PORT enab IN bit output OUT bit D COMPONENT e lt Mentor Graphics VHDL Reference Manual July 1994 8 21 Design Entities and Configurations Component Instantiations S Once you declare a component you can instantiate it multiple times The component instantiation statement creates a component instance and is described on page 6 17 The component instantiation statement associates any generic values with the component and identifies the signals that are connected to the component ports The following example shows component instantiations IS al ENT PORT TY mux a0 sel y IN bit OUT bit N D mux ARCHITECTURE COMPONENT and2 PORT a b Z D COMPONENT IN bit OUT bit tz N COMPONENT or2 PORT a b Z COMPONENT IN bit OUT bit tz D N inverter PORT i IN bit 2 OUT bit MPONENT ab COMPONENT tz ND CO IGNAL aa GIN Us 3 U2 and2 PORT MAP U3 and2 PORT MAP al U4 or2 PORT MAP aa ND structure descript nsel but Ed nverter PORT MAP a0 sel nsel sel ab y
40. LIBRARY basic parts ENT ARCH COMPONENT mult 8 IY project IS I ECT URE try 1 my lib project lib OF project library clause In the preceding example the contents of the libraries basic parts my lib and project lib are available for the design unit to use This example shows only a skeleton of a design unit Mentor Graphics VHDL Reference Manual July 1994 9 9 Design Units and Packages Example of a Design Library The following example shows a design library containing one design unit This design unit is a four input buffer with three control lines as Figure 9 3 shows 741800 NLS c2 DO ay vo 741502 A I3 M N20 c3 E J P one e p em 7 i pm qo a0 1D 201 gt ql a 2D 2 QD I2 74LS75 T E 5 944 gt 335 E agp 753 Figure 9 3 Input Buffer Schematic The following code description shows a possible structural representation of the input buffer in a design unit LIBRARY 1s lib my lib context item USE ls lib ALL context item USE my lib my qsim base ALL context item ENTITY alu loader IS primary unit PORT C1 C2 C3 A0 A1 A2 A3 IN my qsim 12state 03 02 01 00 OUT my qsim
41. New Operand 1 E NR pases ta Li222 24 Figure 2 2 Expression Concept A large number of the VHDL constructs make use of expressions in various forms Complete examples of their use can be found throughout this manual The following source code excerpts contain examples of expressions CASE a gt b IS Ma co as ASSERT x AND y AND z OR r RI Both x AND y AND 2 OR r expressions DISCONNECT sig a bit AFTER 2 VARIABLE test integer 25 an expression race condition is is a ane an expression EPORT race condition and 5 US e U25 18 6 gt 256 Mentor Graphics VHDL Reference Manual July 1994 n expression 2 3 Expressions There are several related language constructs that govern the syntax of an expression as the following syntax descriptions show expression relation and relation relation or relation relation xor relation relation nand relation relation nor relation relation simple expression relational operator simple expression simple expression sign term adding operator term term factor multiplying operator factor factor primary primary abs primary not primary General Expression Rules The related expression language constructs on page 2 4 show that the associative logical operators and or a
42. The default delay in the preceding example is 0 ns The preceding example can be rewritten as follows pure delay lt a b AFTER O ns However nothing in the simulation environment happens in absolutely zero time The simulation iteration takes a delta amount of time To understand this concept better the following list presents a fundamental overview of the simulation iteration cycle Atthe beginning of the iteration any pending events for the given time mature When the event maturity triggers a process that is sensitive to the signal change the process is evaluated When a signal assignment that has a 0 ns delay is found the iteration increments and the preceding steps repeat The iterations continue until all the 0 ns delay assignments are scheduled The simulation then advances by one simulator time step Given the preceding overview signal assignment values that you define to occur all at one given time are actually scheduled by the simulator a delta delay apart The value the simulator assigns does take effect in the future However since the delta delay is so very small the scheduled signal assignments with O ns delay all take effect before any signal assignment that has an actual delay value greater than 0 There can be any number of delta delays for a given time step and the sum of these delays will never equal the next time step The remainder of this discussion shows you through examples th
43. VARIABLE op code Op code array CONSTANT seed real 0 1 seed for random number BEGIN address integer erand48 seed 63 0 4 random address test add start address FOR a IN O TO address 3 LOOP read ram cntnts op code a Read file for desired data IF a gt address THEN ram data a address op code a Extract the data END IF END LOOP ND ram read D memory read iral Z TO 3 ram_data ram_data_conc OUT bit_vector ram_data The concatenation PACKAGE concat IS TYPE ram_data_array IS ARRAY 0 PROCEDURE concat_data VARIABLE VARIABLE END concat PACKAGE BODY concat IS PROCEDURE concat data VARIABLE VARIABLE ram data conc BEGIN ram data conc ram data 0 amp ram data 3 END concat data END concat Parity checker PACKAGE FUNCTION chk_pty RETURN boolean D parity check lt 7 20 parity check function IS ram data conc op code conc OF bit vector ram data 1 concatenate the data For parity check procedure 0 TO 7 IN ram data array 0 TO 31 IN ram data array OUT bit vector 0 TO 31 IS amp ram data 2 amp C_VEC tor 0 TO 23 lt gt Vec tor
44. exponent gt E EN E REN integer gt ER 1 16 Mentor Graphics VHDL Reference Manual July 1994 A 33 Syntax Summary expression relation and relation M A extended_digit or relation xor relation M gt nand p relation nor relation gt Y a E 09 gt pU aJ Pb Ce do ep Uf Tr tT T M S S N A 34 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary factor primary 2 ee primary gt abs mprimary not primary gt 2 4 file declaration gt file gt identifier gt subtype indication p is mode file logical name 5 4 18 file logical name gt string expression gt 4 18 file type definition file type mark ss 5 34 floating type definition range constraint 5 12 Mentor Graphics VHDL Reference Manual July 1994 A 35 Syntax Summary formal designator generic name Pp port name parameter name gt 4 31
45. instantiation label others all Description The following rules govern the use of the configuration specification You supply a list of instantiation labels The labels associate one or more instantiated components with a given component name The labels must be declared in the immediately enclosing declarative region The component name associated with the labels must be declared in a component declaration statement When you use the reserved word others the configuration specification applies to those instances of a component not bound by a previous configuration specification A configuration specification that uses others must be the last configuration specification for the given component name When you use the reserved word all the configuration specification applies to all instances of of a given component A configuration specification that uses all must be the only configuration specification for the given component name Mentor Graphics VHDL Reference Manual July 1994 8 25 Design Entities and Configurations Example In the following example a design entity for an inverter lines 1 through 11 two versions of an AND gate lines 14 through 34 and an OR gate lines 37 through 45 are defined Then an entity declaration and architecture body for a multiplexer is defined lines 48 through 79 that bind the inverter the OR gate and the AND gate component to the multiplexer using configuration specifi
46. subtype declaration constant declaration signal declaration file declaration m attribute specification m attribute declaration alias declaration use clause disconnection specification component declaration subprogram declaration E type declaration subtype declaration constant declaration file declaration use clause alias declaration subprogram declaration subprogram body A subpro gram_body E A architecture statement part os contains concurrent statements type declaration subtype declaration constant declaration signal declaration file declaration attribute specification use clause m attribute declaration alias declaration subprogram declaration component declaration block H XT C process D sjonujsuo abenbue7 Buneoo r d v66L Aine enuen soususjoy TAHA solydesy 101ue A subprogram_body component_declaration A B subprogram_statement_part m contains sequential statements I type declaration subtype declaration generic clause port clause constant declaration subprogram declaration variable declaration 1 alias declaration attribute declaration attribute specification use clause
47. x letter letter gt digit special characters gt 1 5 guarded signal list al type mark gt 11 8 J a gt letter 7 p 2 gt digit 1 8 identifier gt identifier_list A 38 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary if statement if condition gt then gt sequence_of_statements elsif condition gt then p sequence_of_statements sequence_of_statements end gt 6 34 incomplete type declaration type identifier gt 4 4 index_constraint gt discrete range gt gt 5 23 index specification discrete range tatic expression 8 39 index subtype definition type mark gt range gt gt gt 5 23 Mentor Graphics VHDL Reference Manual July 1994 A 39 Syntax Summary indexed name prefix Lf e expression E gt gt 3 8 instantiation list instantiation label J others al 8 25 integer digit A EE lt 1 16 integer type definitio
48. 5 1 Enumeration 5 19 Enumeration predefined 5 21 File 5 34 Floating point 5 12 Floating point predefined 5 14 Integer 5 9 Integer predefined 5 11 Overview 5 1 Physical 5 15 Physical predefined 5 18 Record 5 29 Scalar type definition 5 4 Subtype 5 2 Jnary operator 2 22 nconnected signal 11 15 nconstrained array 5 26 nit name 5 16 nit delay 11 23 niversal expressions 2 36 niversal_integer 1 16 iversal_real 1 16 se clauses 3 22 9 5 User defined attributes 10 53 4 cacacacc c CE Variable assignment statement 6 48 Variable declarations 4 15 Variables default initial value 4 16 Variables initial value 4 15 Visibility 3 16 Visibility by selection 3 18 Visibility rules 3 17 Visibility direct 3 18 vscan script B 1 Wait statement 6 49 While iteration scheme 6 36 Index 7 Index INDEX continued Working library 9 8 XOR 2 31 Index 8 Mentor Graphics VHDL Reference Manual July 1994
49. Author Mod Date Changes Made v1 00 kk 05 26 91 functions types used as extensions to support synthesis LIBRARY IEEE PACKAGI US std logic 1164 extensions IS ieee std logic 1164 ALL LH FUNCTIONS AND TYPES DECLARED FOR SYNTHESIS Resolution function and resolved subtype for STD ULOGIC FUNCTION std ulogic wired x input std ulogic vector 9 26 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages RETURN std ulogic a wired X operation is performed on the inputs to gt determine the resolved value FUNCTION std ulogic wired or input std ulogic vector RETURN std ulogic a wired OR operation is performed on the inputs to determine the resolved value FUNCTION std ulogic wired and input std ulogic vector RETURN std ulogic a wired AND operation is performed on the inputs to determine the resolved value SUBTYPE std ulogic resolved x IS std ulogic wired x std ulogic TYPE std ulogic resolved x vector IS ARRAY NATURAL RANGE lt gt OF std ulogic resolved x SUBTYPE std ulogic resolved or IS std ulogic wired or std ulogic TYPE std ulogic resolved or vect
50. ENTITY shifter IS GENERIC prop delay time 25 ns PORT sin IN bit vector 0 TO 3 sout OUT bit vector 0 TO 3 sctl IN bit vector 0 TO 1 END shifter ARCHITECTURE behav OF shifter IS TYPE temp IS ARRAY 1 TO 3 OF integer BEGIN shf desc PROCESS sin sout sctl VARIABLE shifted bit vector 0 TO 3 proc decl part BEGIN CASE sctl IS sequential statements WHEN 00 gt shifted sin WHEN 01 gt shifted sin 1 TO 3 amp 0 WHEN 10 gt shifted 0 sin 0 TO 2 WHEN 11 gt shifted sin 0 amp sin 0 TO 2 END CASE sout lt shifted AFTER prop delay END PROCESS shf desc Label must match label at END behav beginning of the process Mentor Graphics VHDL Reference Manual July 1994 6 43 Statements return statement The return statement terminates execution of a subprogram A subprogram is a procedure or a function For more information on subprograms refer to Section 7 Construct Placement sequential_statement subprogram_statement_part Syntax return_statement return expression Description The return statement is allowed only within a subprogram When it executes it applies to the innermost enclosing subprogram in the nested calling structure The expression value defines the result that the function returns to the calling code This expression is required when the return statement appears in a function body Th
51. FUNCTION The operators of SSR The overload functions for qsim state vector assume the standard Mentor o 1 rs qsim state RI 0 Tt X X 0 0 1 X X a 0 0 0 0 X O X X X 7 O X X X em CL r qsim state BAD OO XS X eZ 0 O X X 1 1 1 X X X X 7 X X X HSE cU r qsim state r l 0 X 2 0 1 1 1 0 X xX X X X X Z X xX X 4 1l r qsim_state r l 0 1 X YZ 0 0 1 X X 1 1 0 X X X X X X X Z X X X X o 1l r qsim_state rXl 0 X 2 0 0 xX X 1 I Oo X X X X X X X Z X X X X amp unary unary abs are not defined ETURN ETURN ETURN ETURN E y for qsim state ETURN qsim state qsim state qsim state qsim state qsim state mod rem Graphics notation of the most significant bit msb being the left most element All functions unless otherwise stated work with arrays of unequal length The Mentor Graphics VHDL Reference Manual July 1994 9 43 Design Units and Packages shorter arrays will be prepended with 0 to make them the same length This is true for the relational operators to prevent expressions like 011 lt 10 TRUE Functions returning vector types have a result that has a length of the longest operand and the result has a left and direction equal to the left and direction of the left operand unless otherwise noted The relational operators and logical operators work as 1f the qsim_stat
52. Figure 10 2 Array Direction In the preceding array the vertical index is ascending 1 To 3 Therefore left or low corresponds to vertical index 1 and right or high corresponds to vertical index 3 The horizontal index is descending 9 DOWNTO 6 Therefore left or high corresponds to horizontal index 9 and right or low corresponds to horizontal index 6 The direction relationships between the range indices are determined by using this table Range Ascending Range Descending Constraint Range Bound Left most Lowest value Highest value Right most Highest value Lowest value Lowest Left most value Right most value Highest Right most value Left most value The following subsections describe each predefined array object attribute in detail 10 10 Mentor Graphics VHDL Reference Manual July 1994 Attributes high n Kind Function Prefix KK Any valid array object prefix or a prefix that designates a constrained array subtype Parameter h B 1 An expression of type universal integer that can be evaluated during the current design unit analysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the default value is one 1 Result Type 1 1 1 1 1 1 1 1 0 0 0 0 The result type corresponds to the type indicated by
53. Interface Object E E ww n A Generics in design entities Ports in design entities Generics in components Ports in components Parameters in subprograms Parameters in subprograms Parameters in subprograms Figure 4 2 Interface Object Concept Mentor Graphics VHDL Reference Manual July 1994 4 21 Declarations interface list An interface list declares one or more interface objects These objects can be generics for a design entity component or block constant parameters for a subprogram ports for a design entity component or block signal parameters for a subprogram or variable parameters for a subprogram Construct Placement See Figure 4 2 Syntax interface list interface declaration interface declaration interface declaration interface constant declaration interface signal declaration linterface variable declaration Description The interface list contains one or more interface declarations separated by semicolons The following rules are common to all three kinds of interface declaration For each interface declaration you can specify a mode The mode specifies which direction information flows through the communication channel that the interface object provides The following BNF description lists the available modes mode in out inout buffer linkage Mode in The interface object may only be read Mode out The interface
54. July 1994 Design Entities and Configurations Description An entity declaration can be used by many architectures This feature gives you the ability to declare one design entity with one interface and then write different architecture abstractions for that design entity The following subsections describe the language constructs that compose the entity declaration Example An example of an entity declaration follows ENTITY shifter IS entity simple name is shifter GENERIC prop delay time These 4 lines until PORT sin IN bit vector 0 TO 3 the TYPE are the sout OUT bit vector 0 TO 3 entity header sct IN bit vector 0 TO 1 TYPE temp IS ARRAY 1 TO 3 OF integer entity decl part BEGIN ASSERT sin delayed stable AND sctl active entity stmnt prt REPORT Timing violation END shifter If you use entity name here it must match the entity simple name used on the first line Mentor Graphics VHDL Reference Manual July 1994 8 5 Design Entities and Configurations entity header The entity header declares the interface for the entity to communicate with other items in the design environment This interface consists of ports and generics Construct Placement entity declaration Syntax entity header formal generic clause formal port
55. July 1994 4 29 Declarations identifiers of mode in Also based on a recommendation in the JEEE std 1076 INT 1991 document the optional default expression in a variable interface declaration is not allowed for identifiers of mode out or inout This IEEE document helps clarify ambiguities in the IEEE Std 1076 1987 IEEE Standard VHDL Language Reference Manual Example 4M The following example shows the interface variable declaration within a portion of code subprogram declaration PROC EDURE check VAI VAI R R VAI R A BLE A BLE A BLE subprogram declaration PROC 4 30 EDURE chec2 VAI VAI VA R VA DW DW A BLE BLE BLE A A A BLE KNX x Ze y ok OUT bit IS IN bit_vector 0 TO 7 OUT integer INOUT bit IS IN integer 0 Legal default IN bit 707 expressions INOUT bit 0 ERROR Mentor Graphics VHDL Reference Manual July 1994 Declarations association list Association lists provide the mapping between formal or local generics ports or subprogram parameter names and local or actual names or expressions Figure 4 3 shows this concept Construct Placement actual parameter part function call procedure call statement generic map aspect port map aspect
56. Section 5 defined in package standard refer to page 9 18 Evaluation Result If while in a simulation cycle the signal becomes active the result of this attribute is a signal that is the inverse of its previous value Example For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 Mentor Graphics VHDL Reference Manual July 1994 10 37 Attributes Signal Attribute Example The following code shows a simple process that is sensitive on the signal clk and makes assignments to the signal sig these signals are of type Boolean and are declared elsewhere signal att example PROCESS clk process is sensitive to the signal clk VARIABLE x bit 0 BEGIN IF clk 1 THEN x NOT x END IF sig lt x AFTER 0 ns signal assignment END PROCESS signal att example The previous example shows that sig gets the value of x at every edge of the signal clk This means that sig is active at every edge of c1k even if the value of sig does not change Figure 10 4 shows the attribute signals in relation to the preceding example The signal attributes that have the option to specify a time parameter are denoted with a value of t The indicates an attribute value of TRUE The following relationships between the signal attributes exist e The attribute stable tracks the attribute event e The attribu
57. TY a ent Z PORT b G D a ent EN I tz N RCH PORT 2 a D a com TECTURE TY a com I IN bit vector IN integer formal port clause OUT integer OUT bit vector struct OF s SI SI GNAL GNAL d COMPONENT a ent b PORT iral N COMP ON PORT ND N tz 4 38 N ul u2 D struct D COMPONI COMPONI S Y E Z a a ent POI a com POI truct entity IS t vector 0 TO 31 teger bi in component declaration IN integer OUT integer ENT ENT a com IN bit vector OUT bit vector ENT RT MAP b gt to integer s gt d assoc C RT MAP a gt s z gt to_bit y lists Mentor Graphics VHDL Reference Manual July 1994 Types Section 5 Types This section discusses data types and the different classes into which they are categorized A type is like a template that defines the set of values that an object can take on and the kinds of operations that apply to that object For example the predefined type boolean has a value set of TRUE or FALSE so objects declared to be of that type can have either of those two values and no others The following ordered list contains the topics explained in this section scalar type definition 1 1 1 54 range_constraint OS
58. bmux muxl6 USE CONFIGURATION work muxil6 cfg END FOR END FOR END verl As shown in this example you can nest a block configuration inside a component configuration to open up the scope of a lower level architecture within that component configuration The following rules apply to block configurations within component configurations The corresponding components must be fully bound The block specification must name an architecture body The named architecture body must be the same as that to which the corresponding components are bound Block configurations nested within another block configuration open up either block statements or generate statements for configuration These block configurations must contain either block statement or generate statement labels in their block specifications and corresponding statements must appear immediately within the containing block of the architecture If you do not explicitly supply a block configuration for a given block statement within an architecture an implicit block configuration is assumed for that block Implicit blocks are assumed to appear after all explicit block configurations 8 40 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Block configurations for generate statements contain implicit block configurations corresponding to all the generated blocks A block configuration for a gen
59. clause generic clause generic generic list port clause port port list Description All object types used in the entity header must be declared either in package standard or in a user defined package Example The following examples show entity headers for separate entities ENTITY idea check IS An entity decl with no header END idea check declarative or statement part is legal ENTITY shifter IS GENERIC prop delay time Entity header with a generic PORT sin IN bit vector 0 TO 3 and port decl sout OUT bit vector 0 TO 3 sctl IN bit vector 0 TO 1 END shifter ENTITY proto IS PORT input IN bit vector 0 TO 7 Entity header with output OUT bit vector 0 TO 7 port decl only busl INOUT bit vector 0 TO 7 END proto In the previous examples types time and bit vector are declared in package standard 8 6 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations generic clause Generics provide a method for passing data or fixed design parameters into internal and external blocks Internal blocks are defined within an architecture by using the block statement and external blocks are defined by other design entities For more information on block statements refer to page 6 12 Construct Placement formal generic clau
60. enumeration type definition An enumeration type consists of a list of values that can be character literals or identifiers Using the enumeration type definition you can define enumeration types other than those predefined in VHDL Construct Placement scalar type definition type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax enumeration type definition enumeration literal enumeration literal enumeration literal identifier character literal Definitions B enumeration literal A list of character literals or identifiers specified by you Description To define an enumeration type or subtype you use the enumeration type definition which consists of a list of enumeration literals separated by commas The enumeration literals each have a distinct enumeration value The first enumeration literal listed has the predefined position of zero The enumeration literals that follow the first enumeration literal are arranged in ascending positions For example TYPE light IS active off flashing Position 0 1 2 In the preceding example act ive off and flashing are identifiers for enumeration literals each having a distinct enumeration value Notice that the position of the enumeration literals is predefined starting at O f
61. formal parameter list gt parameter interface list 7 8 formal part formal designator gt function name formal designator 4 31 full type declaration gt type y identifier gt is type definition 4 4 function call function name actual parameter part Y X 7 15 A 36 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary generate statement generate label gt gt generation scheme M generate concurrent statement ps end generate generate label gt gt 6 30 generation scheme gt for generate parameter specification EE condition gt 6 30 generic clause generic generic list O 8 7 generic_list gt interface constant declaration x us 8 7 generic map aspect generic map gt O generic _association_list gt 8 32 Mentor Graphics VHDL Reference Manual July 1994 A 37 Syntax Summary graphic character guarded signal specification identifier
62. gt Any valid array object prefix or a prefix that designates a constrained array subtype Parameter OA An expression of type universal_integer which can be evaluated during the current design unit analysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the default value is one 1 Result Type 1 lt 0 The result type corresponds to the type indicated by the specified parameter n Evaluation Result The result returns the lower bound of the index range that the parameter n specifies The index range is all the possible index values in a specified range Mentor Graphics VHDL Reference Manual July 1994 10 17 Attributes Example The following example shows an attribute portion of a code description TYPE arr 1 IS ARRAY integer RANGE lt gt OF integer VARIABLE matrix arr 1 1 TO 3 9 DOWNTO 6 array var decl matrix low 2 parameter n is 2 lt Returned value is 6 matrix low 1 parameter n is 1 lt Returned value is 1 When the parameter n is 2 the boxed column is examined 1 2 3 The value returned is 6 which is the value of the right bound that the parameter 2 specifies When the parameter n is 1 the vertical column is examined In this example the returned value is 1 10 18 Mentor Graphics
63. integer type definition 5 9 floating type defintion 5 12 physical type definition ISS enumeration type definition 5 19 composite type definition A 522 array type definition 0 5 22 record_type_definition 1 1 1 1 5 29 access type definition J 531 Incomplete Types 5 32 file type definition A 2 534 An analogy can be made between VHDL and the English language In the English language sentences contain objects which are the targets of actions In VHDL objects are the targets of actions that taken together make up the desired design behavior The kinds of actions that can be taken on an object and the values that the object can take on are determined by its type The following example shows this concept Mentor Graphics VHDL Reference Manual July 1994 5 1 Types PROCESS TYPE result IS RANGE 1 TO 255 type declaration VARIABLE a b result 8 Declare var type result BEGIN b a 25 Perform operation with a and assign to p WAIT FOR 10 ns END PROCESS VHDL is a strongly typed language which means that all objects must possess a specific type Operations on the typed object are limited to the operations specified for that type Therefore if you make a mistake by trying to illegally operate on an object of a given type an error condition is identified wh
64. lt x fo Y Y Y Y Va Y 7 Y ADO 00 3 o LA vyo oy yow x a 6 gt gt gt x y Z O f x 1 5 library clause library logical name list gt 9 8 library_unit primary unit secondary unit 3 gt 9 3 A 42 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary literal numeric literal y enumeration literal string literal p bit string literal null 1 15 logical name identifier gt 9 8 y logical_name_list logical_name s gt e a NTA logical_operator and Mentor Graphics VHDL Reference Manual July 1994 A 43 Syntax Summary loop statement loop label Lol 2 iteration scheme gt loop gt end loop gt gt sequence of statements loop label mode gt in A 44 C gt out gt 5 e buffer gt linkage gt 4 22 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary multiplying operator vo vy jf f a rem mod 2 20 Mentor Graphics VHDL Reference Manual July 1994 A 45 Syntax Summary name y simple name
65. signal declaration subtype declaration to if statement direction options signal assignment statement type declaration physical type definition condition clause configuration specification use clause walt statement conditional waveforms exit statement next statement selected waveforms iteration scheme selected signal assignment expression logical operator 1 14 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements Comments You can include comments to document your VHDL code Comments consist of two adjacent hyphens followed by the text of the comment Comments terminate at the end of the line For example This is the beginning of the code counter PROCESS clk Counter executes when clk changes A comment can appear anywhere in a description without affecting how the code is processed or simulated Any of the 95 ASCII graphic characters can be used in a comment Literals Literals are lexical elements such as numbers characters and strings that represent themselves VHDL has five types of literals as shown in the following BNF syntax description literal numeric literal enumeration literal string literal bit string literal null The following pages discuss numeric string and bit string literals For information about the enumeration literal refer to page 5 19 The null literal represents the null access value for an access type it is an a
66. signal name is the prefix Example Ah lt 4 For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 10 30 Mentor Graphics VHDL Reference Manual July 1994 Attributes event Kind Function Prefix KK KE Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Result Type Boolean Evaluation Result If an event on the signal specified by the prefix has just occurred while in the current simulation cycle the return result for a scalar signal is a value of TRUE If an event on any scalar subelement that the prefix specifies has just occurred while in the current simulation cycle the return result for a composite signal is a value of TRUE If the preceding conditions are not met the return value is FALSE Example h 5 For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 Mentor Graphics VHDL Reference Manual July 1994 10 31 Attributes last active Kind Function Prefix KK KE Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Result Type lt The result type is type time which is a predefined physical type refer to Section 5 from package standard refer to page 9 18 Evaluation Result L1 1 1 The result is th
67. std ulogic RETURN UXO1 FUNCTION xor 1 std ulogic r std ulogic RETURN UXO1 function xnor 1 std ulogic r std ulogic return ux01 FUNCTION not 1 std ulogic RETURN UXO1 vectorized overloaded logical operators FUNCTION and 1 r std logic vector RETURN std logic vector FUNCTION and 1 r std ulogic vector RETURN std ulogic vector FUNCTION nand 1 r std logic vector RETURN std logic vector FUNCTION nand 1 r std ulogic vector RETURN std ulogic vector FUNCTION or 1 r std logic vector RETURN std logic vector FUNCTION or 1 r std ulogic vector RETURN std ulogic vector FUNCTION nor l r std logic vector RETURN std logic vector FUNCTION nor l r std ulogic vector RETURN std ulogic vector FUNCTION xor 1 r std logic vector RETURN std logic vector FUNCTION xor 1 r std ulogic vector RETURN std ulogic vector Note The declaration and implementation of the xnor function is specifically commented until at which time the VHDL language has been officially adopted as containing such a function At such a point the following comments may be removed along with this notice without further official ballotting of this std logic 1164 package It is the intent of this effort to provide such a function once it becomes available
68. 0 TO 23 Mentor Graphics VHDL Reference Manual July 1994 Subprograms PACKAGE BODY parity check IS FUNCTION chk pty CONSTANT ram data conc IN bit vector 0 TO 31 CONSTANT op code conc IN bit vector 0 TO 31 RETURN boolean IS VARIABLE suml sum2 boolean false BEGIN FOR i IN O TO 31 LOOP IF ram data conc i 71 THEN suml NOT suml compute parity for ram data END IF IF op code conc i 1 THEN sum2 NOT sum2 compute parity for op code data END IF END LOOP RETURN suml sum2 Return true if suml sum2 END chk pty false if not equal END parity check Mentor Graphics VHDL Reference Manual July 1994 7 21 Design Entities and Configurations Section 8 Design Entities and Configurations This section describes the major hardware abstraction in VHDL the design entity It also discusses components which are the basic units of structural designs and configurations which can assemble external design entities into a higher level design The following list summarizes the topics contained in this section Design Entities entity declaration entity header generic clause port clause entity declarative part entity statement part architecture body architecture declarative part architecture statement part
69. 23 Sequential Signal Assignments The sequential signal assignment schedules a waveform element to be assigned to a signal s driver after a time you specify If you do not specify a time a value of zero nanoseconds is used as the delay A target in a signal assignment that uses a zero nanosecond delay does not get updated within the current simulator iteration it is updated at the beginning of the next simulator iteration If you have several assignments the signal assignments are evaluated sequentially Each evaluation schedules an event a minimum of one iteration later it does not update the signal immediately in the current simulator iteration For example data out lt t AND d Current value a 0 new value a 1 result lt data out AND carry bit 11 16 Mentor Graphics VHDL Reference Manual July 1994 Signals In the preceding example the value for data out evaluates first and then schedules an event to update the signal In this example the current value for data out is a 0 and the current evaluation has scheduleddat a_out to be updated to a 1 The next sequential signal assignment statement then executes and schedules an event for signal result The evaluation of the result signal uses the value for data out within the current iteration which in this example is a 0 Based on the evaluation in the current iteration a new value is scheduled for signal result The evaluation of the wavefor
70. 35 Globally static operand 2 32 Globally static range 2 35 Mentor Graphics VHDL Reference Manual July 1994 Index INDEX continued Globally static range constraint 2 35 Globally static scalar subtype 2 35 Guarded signals 6 23 11 5 Hidden declaration 3 18 Homograph 3 18 Identifier list 4 11 Identifiers 1 8 If statement 6 34 Immediate scope 3 15 Incomplete Types 5 32 Index constraint 4 8 5 27 Indexed names 3 8 Inequality operators 2 29 Inertial delay 6 47 11 19 Integer literal 1 16 Integer types 5 9 Integer type declaration 9 19 Interface constant declaration 4 24 Interface declarations 4 21 Interface lists 4 22 Interface objects 4 21 Interface signal declaration 4 26 Interface variable declaration 4 29 Iteration scheme 6 36 Iterative statements 6 6 Labels 6 3 Language construct tree B 1 Language constructs 1 3 Language constructs locating B 1 Leading digit 1 21 Lexical element definition 1 3 Library clause 9 8 Library logical name 9 8 Library resource 9 8 Library working 9 8 Literals 1 15 Local ports 8 23 Locally static array subtype 2 34 Locally static discrete range 2 34 Locally static expression 2 32 5 9 5 12 Mentor Graphics VHDL Reference Manual July 1994 5 16 Locally static index constraint 2 34 Locally static operand 2 32 Locally static range 2 34 Locally static range constant 2 34 Locally static scalar subtype 2 34 Lo
71. 4 matrix range 1 This is equivalent to the following x ARRAY 1 TO 4 1 TO 3 4 by 3 two dimen array An example using range in a loop statement follows FOR test IN matrix range 1 LOOP This is equivalent to the following FOR test IN 1 TO 3 LOOP 10 20 Mentor Graphics VHDL Reference Manual July 1994 Attributes reverse range n Kind Range Prefix gt gt Any valid array object prefix or a prefix that designates a constrained array subtype Parameter OA An expression of type universal_integer which can be evaluated during the current design unit analysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the default value is one 1 Result Type 1 1 1 0 0 0 The result type corresponds to the type indicated by the specified parameter n Evaluation Result The result is the conversion of ascending range to a descending range or the conversion of a descending to an ascending range using the specified parameter Mentor Graphics VHDL Reference Manual July 1994 10 21 Attributes Example The following example shows an attribute portion of a code description matrix reverse_range 1 Since the parameter n is 1 the boxed column is examined INDEX 9 8 7 6 A 1 DOWNTO 2 3 The value of the attribute is 3 downto 1 w
72. 7 10 Subprogram Calls 7 13 function call J h34 4 JJ 7 15 The Procedure Call 7 17 Subprograms and Overloading _ 7 17 Overloading Operators 1 1 1 7 1 Complete Subprogram Example 7 19 Mentor Graphics VHDL Reference Manual July 1994 7 1 Subprograms Figure 7 1 shows where subprograms belong in the overall language and the items that comprise them Design Units Design Entities Configurations Packages Attributes Components Types Signals Statements Subprograms _ Declarations b Expressions Lexical Elements a Naming Scope and Visibility Subprograms Y Y Y Subprogram Declaration Subprogram Body Subprogram Specification Subprogram Specification Procedure Procedure Function Function Subprogram Declarative Part Subprogram Statement Part Figure 7 1 Subprograms 7 2 Mentor Graphics VHDL Reference Manual July 1994 Subprograms Definition of a Subprogram A subprogram consists of algorithms for calculating values or it consists of behavior descriptions Subprograms give you the ability to define an algorithm once and then call it many times or to write a description that calls an algorithm that has not be defined yet but which must be defined before simulation A subprogram is a function
73. AFTER 7 ns 30 END or2 basic 31 8 36 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations 32 33 34 35 36 37 38 39 I o cO J004s C0 PO ES The design entity for the mux placed in work Component declarations ENTITY mux IS PORT a0 al sel IN bit y OUT bit END mux ARCHITECTURE struct OF mux IS COMPONENT and2 PORT a b IN bit y OUT bit END COMPONENT COMPONENT or2 PORT a b IN bit y QUT bat END COMPONENT COMPONENT inverter PORT a IN bit not a OUT bit END COMPONENT SIGNAL aa ab nsel bit BEGIN Component instantiations for the mux Ul inverter PORT MAP sel nsel U2 and2 PORT MAP a0 nsel aa U3 and2 PORT MAP al sel ab U4 or2 PORT MAP a gt aa b gt ab y gt y END struct ere is the configuration for the mux reside in the same library as the LIBRARY my_parts_lib work CONFIGURATION verl OF mux IS USE WORK ALL FOR struct FOR Ul inverter USE ENTITY my_parts_lib inv inv_basic GENERIC MAP Del gt 1 5 ns PORT MAP i gt a i bar gt not a END FOR FOR ALL and2 USE ENTITY my parts lib angd2 and2 basic END FOR FOR U4 or2 USE ENTITY my parts lib or2 or2 basic END FOR END FOR END verl
74. FUNCTION FUNCTION FUNCTION gt FUNCTION lt qsim state vector qsim state vector qsim state vector RETURN qsim state qsim state vector ETURN qsim state ETURN qsim state ETURN qsim state ETURN qsim state ETURN qsim state qsim state vector qsim state vector R BKR B Kh Kh KBK EEE 9 44 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages Addition and subtraction of qsim state vectors use the table defined for qsim state and operators The result vector is the size of the larger operand The range of the result array will have a left and direction equal to the left and direction of the left operand The result will be as optimistic as possible when X s are present For example 01X0 0100 10X0 2 AM OUXO E TOIIQUy o 4xXx0 FUNCTION 1 r qsim state vector RETURN qsim state vector FUNCTION 1 r qsim state vector RETURN qsim state vector For these multiplying operators the result is the size of the larger operand with a left and direction of the left operand The operators mod rem and xx will do the following convert the entry to a natural universal integer perform the operation and truncate the result to the size of the result array The size of the result is the same as for a
75. Figure A 1 illustrates all the possible elements of a syntax diagram example construct 7 gt construct one M construct two construct three preserved_word Uoo Figure A 1 Example Syntax Diagram The syntax diagram is read from left to right by following the arrow directions The following list describes each element of the syntax diagram Each individual syntax diagram is called a language construct The name of the construct is the left most item In Figure A 1 the language construct is named example construct e example construct is composed of three different items By following the arrows you can take three different paths as shown in Figure A 2 by Path A or Path B or Path C e In taking Path A the boxed item construct one is encountered All boxed items indicate another language construct which is defined by another individual syntax diagram Mentor Graphics VHDL Reference Manual July 1994 A 9 Syntax Summary PathA example construct lt 7 construct one gt Path B p construct two L construct three Path V reserved word gt EUN Figure A 2 Multiple Syntax Diagram Paths The loop back in Path A indicates you can use one or more of the language construct construct one separated by a comma Al
76. INOUT line value OUT character good OUT boolean 9 30 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages ROC ROC ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI ROCEI Mentor Graphics VHDL Reference Manual July 1994 DURE read 1 INOUT line value OUT character DURE read 1 INOUT line value OUT integer good OUT boolean DURE read 1 INOUT line value OUT integer DURE read 1 INOUT line value OUT real good OUT boolean DURE read 1 INOUT line value OUT real DURE read 1 INOUT line value OUT string good OUT boolean DURE read 1 INOUT line value OUT string DURE read 1 INOUT line value OUT time good OUT boolean DURE read 1 INOUT line value OUT time tput Routines for Standard Types DURE writeline f OUT text 1 NOUT line DU
77. Instantiation of the U2 and2 PORT MAP a0 nsel aa components using component U3 and2 PORT MAP al sel ab instantiation U4 or2 PORT MAP aa ab y statements END structure descript 6 18 Mentor Graphics VHDL Reference Manual July 1994 Statements concurrent assertion statement The concurrent assertion statement is an equivalent process statement generated by the system that contains a sequential assertion statement and a wait statement at the end This equivalent process is a passive process because it has no signal assignment statements For more information on the sequential assertion statement refer to page 6 10 Construct Placement entity statement Cconcurr ent statement architectur e_statement_par t block_statement_part Syntax concurrent_assertion_statement label assertion statement Description AAPP Except for the optional label the syntax for this statement is the same as for the sequential assertion statement The system knows when to create a concurrent assertion by the location in which the assertion statement appears because concurrent statements are allowed only in architectures or blocks If you specify an operand that is a signal in the expression of the assertion statement the signal s longest static prefix name appears in the sensitivity list of the implied wait statement If you specify an operand in the expression that is not a signal no sensitivity clause condi
78. July 1994 Declarations Description The full type declaration establishes a name identifier for the type and defines the classification for the type The incomplete type declaration names the type but defers the definition of the type The subject of types is discussed in detail in Section 5 The use of incomplete type declarations is treated in that section as well under Incomplete Types on page 5 32 As the preceding syntax descriptions indicate you can use one of four type definitions the scalar type which includes enumeration integer floating and physical types the composite type which is an array type that can be constrained specific range or unconstrained the access type the values of which designate or point to objects created by allocators and the file type which designates external files The following examples show some possible type declarations TYPE add sz IS RANGE 0 TO 255 integer type decl scalar TYPE color IS red yellow green flashing enum type decl scalar TYPE mem info IS ARRAY 0 TO 1024 OF bit const array type decl composite TYPE tfd 4 IS ARRAY integer RANGE lt gt OF integer unconst array type decl composite Type declarations define separate types for each identifier you specify This is the case even if the type definitions are textually equivalent except for the identifier The following exam
79. Mentor Graphics VHDL Reference Manual July 1994 Signals Check the temporary values templ temp0 and tempz IF templ AND temp0 THEN If there are drivers of 1 RETURN X and 0 return an X ELSIF templ THEN otherwise if 1 driver RETURN 17 return a 1 ELSIF temp0 THEN otherwise if 0 driver RETURN 0 return a O ELSE otherwise return Z RETURN Z END IF END wired or END tester The following list shows the rules that govern the use of the resolution function e Every signal of signal kind bus or register must have a resolution function to handle the disconnection specification e If the signal kind is bus the resolution function must provide a return value for the case when all the drivers are disconnected The previous example checks for this using the following code IF driv array length 0 THEN check if all drivers RETURN Z are disconnected END IF There can be only one input parameter to the function You can use any legal name you wish for this parameter In the previous example the name driv array is used as the following code shows FUNCTION wired or driv array my qsim state vector RETURN my qsim state IS Mentor Graphics VHDL Reference Manual July 1994 11 13 Signals
80. Reference Manual not a particular Mentor Graphics implementation of this language S System 1076 readers should watch for paragraphs or sentences in this manual that are preceded by an S like the one preceding this paragraph System 1076 users who see an S beside a topic should consult Appendix C of the System 1076 Design and Model Development Manual Readers who use the Bold Browser can click on the S character to bring up the appropriate page in that manual Hardcopy readers can find information in that manual by using the table of contents Appendix C in the System 1076 Design and Model Development Manual which is organized with the same section and subsection names as this manual contains important additional information on the marked topic E When a paragraph is preceded by an E Explorer VHDLsim readers should xvi Mentor Graphics VHDL Reference Manual July 1994 About This Manual consult the Explorer VHDLsim User s Manual Appendix A for further information on the marked topic For quick access to information you should look up a topic in the index of this manual If you are interested in a certain language construct consult Appendix A This appendix contains every language construct in alphabetical order Each construct shows a page reference for more information on this subject The basic structure of this manual is to present an overview of a concept followed by the related BNF description and an example of the topic Fi
81. Types Signals Statements Subprograms Declarations AN Expressions la Lexical Elements Naming Scope and Visibility Signals Y Signal Concepts Drivers Guarded Signals Disconnection Specification Multiple Drivers amp Resolution Functions Y Y Y Signal Declaration Signal Assignment Sequential Concurrent Figure 11 1 Signals After declaring a signal you assign values to it using a sequential or concurrent signal assignment statement For example the following code shows a signal 11 2 Mentor Graphics VHDL Reference Manual July 1994 Signals assignment that can be sequential or concurrent depending on where in your code it appears enable lt 0 1 AFTER 5 ns 0 AFTER 10 717 AFTER 30 ns In the preceding example the items to the right of the lt are waveform elements Each of the waveform elements is held in a container called a driver These values are the projected output waveform for the signal The signal is the item on the left of the lt delimiter and the simulator creates a driver for this signal which is a source for the value of a signal Each time the signal assignment statement executes the value of the waveform element is appended to the driver when the time you designate arrives The driver is the item that is read by the system to determine the new value for the signal A signal
82. VHDL Reference Manual July 1994 Attributes range n Kind 0000000 0 Range Prefix gt Any valid array object prefix or a prefix that designates a constrained array subtype Parameter gt An expression of type universal integer which can be evaluated during the current design unit analysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the default value is one 1 Result Type 1 lt The result type corresponds to the type indicated by the specified parameter n Evaluation Result 3 The result is the range of the array you specify in the prefix using the reserved word to if ascending and downto if descending The result is not a visible string but a value you can use as a range constraint or in a for statement Mentor Graphics VHDL Reference Manual July 1994 10 19 Attributes Example The following example shows an attribute portion of a code description matrix range 1 Since the parameter n is 1 the boxed column is examined The value of the attribute is 1 to 3 which is the value of the ascending range of the specified parameter 1 This returned value can be used only when specifying a range e The following example shows the specification of a range of another array by using the preceding example x ARRAY 1 TO
83. VHDL do text string comparisons The standard defines comparisons of arrays to proceed from left to right However bit vectors normally represent numbers and in this case comparisons should proceed from right to left To illustrate the implications of this take the bit string literals B 011 and B 10 The first bit string literal represents the number 3 the second 2 Going by the standard B 011 B 10 is true i e 3 lt 2 is true To fix this the comparison operators are overloaded for bit vectors to perform a numeric comparison Mentor Graphics VHDL Reference Manual July 1994 9 49 Design Units and Packages FUNCTION 153b bit vector RETURN bit FUNCTION 35 0 bit vector RETURN bit FUNCTION l r bit vector RETURN bit FUNCTION l T bit_vector RETURN bit FUNCTION gt ly E bit_vector RETURN bit FUNCTION lt 1 xv bit vector RETURN bit FUNCTION Ls E bit_vector RETURN boolean FUNCTION gt IE bit vector RETURN boolean FUNCTION Ql bit vector RETURN boolean FUNCTION A5 e bit vector RETURN boolean FUNCTION gt E bit_vector RETURN boolean FUNCTION lt 1 xv bit vector RETURN boolean tz ND qsim relations 9 50 Mentor Graphics VHDL Reference Manual July 1994 Attributes Section 10 Attributes This section includes informa
84. a given time step to evaluate and assign new values to the targets of concurrent statements Mentor Graphics VHDL Reference Manual July 1994 11 17 Signals The concurrent signal assignment can take two forms e Conditional signal assignment Selected signal assignment The conditional signal assignment form of the concurrent signal assignment statement is an equivalent process statement that the system generates that assigns values to signals using an if statement format You do not actually see this format It is created internally when you use the syntax the following example shows bus test BLOCK SIGNAL test data a data b wired or my qsim state vector 0 TO 7 SIGNAL enl en2 bit BEGIN the following code shows cond signal assignments test lt data a AFTER 2 ns WHEN enl 1 ELSE data b AFTER 2 ns END BLOCK bus test The selected signal assignment form of the concurrent signal assignment statement is an equivalent process statement generated by the system The concurrent signal assignment statement assigns values to signals using a case statement format You do not actually see this format It is created internally when you use the format the following example shows 11 18 Mentor Graphics VHDL Reference Manual July 1994 Signals bus drive BLOCK SIGNAL test data a data b my qsim state vector 0 TO 7 SIGNAL enl bit BE
85. a signal declaration with no default expression specified and the implicit default the system assumes TYPE my qsim state IS X 0 1 Z Type decl Mentor Graphics VHDL Reference Manual July 1994 11 15 Signals SIGNAL enable my qsim state declaration with no default my qsim state left system assumes the defaul In the previous example the default value of the signal enable is the left most value of the signal type which 15 X The default expression for signals differs from the default expression for ports in terms of its interpretation in association lists For a discussion on this topic refer to page 4 31 Signal Assignments After you declare a signal you assign values to it using a sequential or concurrent signal assignment The following example shows the form that signal assignment statements take test signal lt 1 AFTER 25 ns 707 AFTER 30 ns The value to the left of the lt delimiter is the signal which is the target of the assignment The values to the right of the lt are the waveform elements The following subsections give you an overview of the sequential and concurrent signal assignments in relation to the previous discussion on signal concepts For more detailed information on the sequential signal assignment statement refer to page 6 46 For more detailed information on the concurrent signal assignment statement refer to page 6
86. always referenced from zero and increases left to right From the previous example Value red yellow green flash Position 0 1 2 3 Mentor Graphics VHDL Reference Manual July 1994 10 47 Attributes pred x Kind Function Prefix Any enumeration integer physical type or subtype Parameter The value for the parameter x must be of the same base as the specified prefix Result Type The result type corresponds to the base type of the specified prefix Evaluation Result The result returns the value that is located one position less than the specified parameter x Example The following code shows the definition of num TYPE num IS RANGE 3 TO 17 The following code returns the value 9 which is the value at one position less than the position specified by the parameter 10 num pred 10 Restrictions 1 0 0 0 You cannot specify a parameter that is equal to the lower bound of the base type Using the previous example an error occurs if you specify the following code num pred 3 The previous example shows an error condition since there is no value in the position one lower than 3 10 48 Mentor Graphics VHDL Reference Manual July 1994 Attributes right Kind Value Prefix Any scalar type or subtype Result Type 1 lt The same type as the prefix type Evaluation Result The result is the right bound of the specified prefix type Exampl
87. be printed you must use the following format The string message will be printed Since a string literal is a lexical element the end of the line format effector is considered a separator Therefore if you wish to use a string literal that exceeds the length of the line you can concatenate the graphic characters You concatenate by using the ampersand amp character For example Tf your string literal is too long then amp use the concatenation character You can also concatenate graphic characters with nongraphic characters There are several nongraphical characters in package standard in the predefined type character For example if you want to concatenate the nongraphical character BEL with two string literals the format is as follows Concatenating string literals amp bel amp with nongraphical characters A string literal is case sensitive because strings are arrays of character literals which are case sensitive Therefore the following strings are not equivalent This string this string NOT EQUAL Mentor Graphics VHDL Reference Manual July 1994 1 19 Lexical Elements Character and String Literal Differences In some situations it might appear to you that there is no difference between a character literal and a string literal For example the character literal x x the string literal x The difference between a character literal a
88. capability for compiled library or design units that can be used in other hardware design descriptions The library clause specifies the logical names of libraries that the design unit can reference The library clause is part of the context clause Construct Placement context item context clause design unit Syntax library clause library logical name list logical name list logical name logical name logical name identifier Description S The mapping of the logical name list in the library clause to the actual file names occurs in the VHDL environment VHDL provides two classifications for design libraries e Working libraries Resource libraries The working library is the library in which the compiled design unit is placed The analogy to the working library is your working directory When you compile the design unit it exists in the working directory in which you performed the compilation There is only one working library during the compilation of a design unit The resource library is a library that contains the library units that the design unit being compiled references There can be any number of resource libraries for a given design unit The working library itself can be a resource library Example 9 8 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages The following example shows the possible use of the library clause within the design unit construct
89. clause refer to page 3 22 Example The following example shows the context clause in a partial design file LIBRARY c USE c ALL context clause ENTITY tester IS PORT pinl pin2 pin3 IN bit pin4 OUT bit A VHDL implementation generates an implicit context clause for every design unit This context clause consists of a library clause and a use clause as the following example shows LIBRARY std work USE std standard ALL The previous example shows that std is the library logical name for the design library in which package standard is located The use clause makes all the declarations in package standard directly visible For more information on the working library work refer to page 9 9 9 6 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages Design Files USE x ALL PACKAGE x IS NC Physical Libraries LIBRARY a b Pe SN lA Logical to Physical Mappin LI PPS Y 4 Library b ZA oL A Library b y g c LIBRARY c TUN ogical to USE C ALL e Physical lt q Library c a Mapping Figure 9 2 Context Clause Concept Mentor Graphics VHDL Reference Manual July 1994 9 7 Design Units and Packages library clause A design library provides storage
90. d A 1 17 binding indication entity aspect generic_map_aspect port map aspect 8 29 bit string literal base specifier EX value el E E 1 20 bit_value extended digit lt A 16 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary 1 20 block configuration for block specification N ha pluse_clause ____ configuration item 8 39 block declarative item subprogram declaration subprogram body type declaration subtype declaration M constant declaration signal declaration file declaration component declaration BS configuration specification attribute specification disconnection specification use clause end for gt gt Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary 8 17 block declarative part block declarative item gt 6 12 block header generic clause generic map aspect o port clause port map aspect _ gt 6 12 architecture name block specification block statement label generate statement label
91. default binding indication is composed of a default entity aspect and default generic and port map aspects which are optional The default entity aspect is determined by the following methods When you instantiate a component that has a simple name that is not the same as a visible entity declaration no default is determined and an error occurs When you instantiate a component that has a simple name that is the same as a visible entity declaration and that design entity has no architecture to use the entity aspect is the simple name of the instantiated component e In all other cases the default entity aspect is the entity name of the instantiated component and the architecture which is identified by the architecture body associated with the entity declaration that was most recently analyzed by the compiler When the design entity implied by the entity aspect has formal generics or ports the default binding indication uses a default generic map aspect or port map aspect The default generic map aspect associates every local generic named in Mentor Graphics VHDL Reference Manual July 1994 8 33 Design Entities and Configurations the component instantiation with a formal generic of the same name in the entity declaration The default port map aspect associates every local port named in the component instantiation with a formal port of the same name in the entity declaration The following conditions create an error e Th
92. documentation of the call may be unclear when using the default parameter method for calls you can safely use the default method when the subprogram values do not change in the majority of calls For more examples and the rules for association refer to page 4 33 7 14 Mentor Graphics VHDL Reference Manual July 1994 Subprograms function call A function call causes the execution of a function body Construct Placement primary prefix Syntax function call function name actual parameter part actual parameter part parameter association list Description lt 0 0 A function call must have an associated parameter for each formal parameter of the called function If you do not specify an actual parameter in the association list a default expression is used For more information on association lists refer to page 4 31 Before the function call executes all the actual parameter expressions you specify are evaluated For formal parameters that do not have matching actual parameters the corresponding default expressions evaluate The result of the expression must match the formal parameter type If the formal parameter is an unconstrained array the actual parameter must have the same base type as the formal parameter The formal parameter takes the actual parameter subtype When the function body executes a value is returned This value type is the result type of the function declaration For mo
93. e Signals Subprograms e Variables Packages e Components e Types e Labels All members that you designate in the entity name list inherit the attribute provided that the classes of those members are the same as the specified entity class it is an error if the classes do not match Here are some examples of attribute specifications ATTR B U TE ATTR B TE technology OF rd_wrt_cont5 CONFIGURATION IS ec part_count OF rd_wrt_cont5 CONFIGURATION IS 35 ATTR B TE ATTR B U TE output cap OF strobel SIGNAL IS 5 0E 12 component_location OF U210 LABEL is 110 450 A given attribute must not be associated more than once with a particular entity class member Likewise two different attributes with the same simple 10 56 Mentor Graphics VHDL Reference Manual July 1994 Attributes name must not be associated with the same entity class member If you use others in the entity name list the specification applies within the immediately enclosing declarative region to members of the specified entity class whose names have not appeared in the name list of a previous attribute specification If you use all in the entity name list the specification applies to all members of the specified entity class within the immediately enclosing declarative region An attribute specifi
94. entity class within a VHDL description It also defines the value of that attribute for those members Attribute specifications are not allowed for predefined attributes Construct Placement configuration declarative part entity declarative item package declarative item process declarative item subprogram declarative item Syntax attribute specification attribute attribute designator of entity specification is expression attribute designator attribute simple name entity specification entity name list entity class entity name list entity designator entity_designator others all entity class entity architecture configuration procedure function package type subtype constant signal variable component label entity designator simple name loperator symbol Mentor Graphics VHDL Reference Manual July 1994 10 55 Attributes Definitions attribute designator This denotes a previously declared attribute entity specification This specifies the items that the attribute specification applies to and identifies the entity class of those items W entity name list This identifies the items that will inherit the attribute Description An attribute specification associates a previously declared user defined attribute with particular members of one of the following entity classes e Entities Subtypes e Architectures e Constants e Configurations
95. examples show the declaration of file types TYPE rom data IS FILE OF integer TYPE error file IS FILE OF string TYPE input data IS FILE OF bit vector When you declare a file type with a type mark that is scalar or a constrained array subtype read and write procedures and an endfile function are implicitly defined immediately following the file type declaration For more information on file declarations refer to page 4 18 The following example shows the declaration of 5 34 Mentor Graphics VHDL Reference Manual July 1994 Types a file type a file declaration and the implicit subprogram definitions that are declared by the system pe TYPE stat IS FILE OF integer le type decl FILE my stats stat IS stat file file decl implicit definitions PROCEDURE read VARIABLE my stats INOUT stat value OUT integer PROCEDURE write my stats INOUT stat value IN integer FUNCTION endfile VARIABLE my stats IN stat RETURN boolean The read procedure returns a value from the file you specify allowing you to do a file read The write procedure appends a value to the file you specify allowing you to do a file write The endfile function returns a Boolean value of TRUE when a read operation cannot return another value from the file otherwi
96. exists page 9 13 e Subprogram declaration combined with a subprogram body page 7 6 3 12 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility e Block statement page 6 12 Loop statement page 6 36 Process statement page 6 41 Each declarative region in the preceding list is associated with a corresponding declaration or statement The declaration is immediately within a declarative region if the corresponding region is the innermost region enclosing the declaration This innermost region does not include the declarative region if it exists of the declaration The following example shows a skeleton of a block statement and the declarative region test_block BLOCK declarative region TYPE test IS 1 TO 10 BEGIN concurrent statements END BLOCK test_block Scope Scope is the region of code over which a declared item has effect For example 1f you declare objects inside a block statement the scope of the objects extends from the point where you first name the objects to the end of the block statement Figure 3 3 shows an architecture body that contains a procedure within a process Region A shows the scope of the subprogram specification procedure region B shows the scope of the process statement and region C shows the scope of the architecture body Mentor Graphics VHDL Reference Manual July 1994 3 13 Naming Scope a
97. file object that can have data written into it or read from it Construct Placement block declarative item entity declarative item declaration package body declarative item package declarative item process declarative item subprogram declarative item Syntax file declaration file identifier subtype indication is mode file logical name file logical name string expression Definitions B identifier A name that you provide for the file object being defined B subtype indication Indicates the subtype must be a file type and any related restrictions that apply to the object being declared mode Specifies the direction of information flow m file logical name Maps the name of your file to a system physical file name Description lt 0 A file declaration specifies a file object name a file data type optional mode and a logical filename that maps to a filesystem A file object is actually a member of the variable class of objects however an assignment to a file object is not allowed as shown in the following examples 4 18 Mentor Graphics VHDL Reference Manual July 1994 Declarations VARIABLE x real variable declaration x 0 707 output assignment to a variable is legal FILE z int file IS OUT test file file declaration z 8 assignment to a file object is not legal The following examples show some possib
98. from least to most severe NOTE use for general information messages WARNING use for a possible undesirable condition e ERROR use for a task completed with the wrong results e FAILURE use for a task that is not completed 6 10 Mentor Graphics VHDL Reference Manual July 1994 Statements Example The following example shows how to use assertion statements to report setup time and pulse width violations on a synchronous device ASSERT NOT clock event AND clock 1 AND preset 1 AND NOT preset stable 20 ns REPORT Setup time violation SEVERITY warning This statement asserts that when the clock changes to a high and the delayed preset signal is a one and remains stable for 20 ns the setup time is not in violation However if the assertion fails a Setup time violation warning is generated ASSERT preset delayed 1 AND preset 0 AND preset delayed last_event gt 25 ns REPORT Pulse width violation SEVERITY warning The preceding example asserts that when preset changes from a high to a low and the preset signal stays in the same state for at least 25 ns the pulse width is not in violation If the assertion fails a Pulse width violation warning is generated The items that follow the tic mark are predefined signal attributes For more information on signal attributes refer page 10 28 Mentor Graphics VHDL Ref
99. generics of design entity gates are positionally associated with local generics in a component declaration beginning with the line COMPONENT and2 Here the association list of the generic declaration maps the local generic prop_delay to the formal generic x The local generics are in turn positionally associated with actuals in the generic map of the configuration specification thus prop_delay 1s mapped to 25 ns The formal ports of design entity gates are positionally associated with the local ports in the component declaration for and2 However the association of the locals with the actuals is a named association the association is done in the port map of the configuration declaration The preceding example associates formal ports and generics with locals and locals with actuals For a discussion of association as 1t applies to subprogram parameters refer to page 7 13 For further discussion on the association of component generics and ports refer to page 8 23 The following list shows information and rules for association lists When the mode of the formal is in or inout and the actual is not open the type of the actual must match the type of the formal Mentor Graphics VHDL Reference Manual July 1994 4 33 Declarations 4 34 When the mode of the formal is out or inout and the actual is not open the type of the formal must match the type of the corresponding actual A formal port associated with the reserved wo
100. info ALL END team info If you use simple name here it must match identifier used after the word PACKAGE The preceding example shows some of the possible package declarative items that you can use in the package declarative part Declarations are discussed in detail in Section 4 An example of a package declaration requiring no package body follows PACKAGE information IS TYPE memory IS ARRAY 0 TO 23 OF integer TYPE submemory IS ARRAY 0 TO 7 OF memory CONSTANT gravity real 9 8 SIGNAL start calculation bit END information WE 9 14 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages package body The package body specifies the values of deferred constants and defines the subprogram bodies declared in the package declaration Construct Placement gt J secondary unit Syntax package body package body package simple name is package body declarative part end package simple name package body declarative part package body declarative item package body declarative item subprogram declaration subprogram body type declaration subtype declaration constant declaration file declaration alias declaration use clause Definitions B package simple name This must be the same identifier that you provided in the corresponding package declaration B
101. is a named element association is to look for the delimiter gt A positional element association is an element association in which each expression implicitly specifies the element of the array by location For example the first expression specifies the first element and the second expression specifies the second element For record aggregates you can use both named and positional association in the same aggregate However all positional elements must appear first followed by the named associations No association can appear after the reserved word others If you have an aggregate with only one element association you must use a named association For a complete discussion on association methods refer to page 4 31 The reserved word others indicates that other unspecified elements of the array take on the value specified after the gt delimiter You can use a string or bit string literal in multidimensional aggregates where you would use a one dimensional array that is of type character Mentor Graphics VHDL Reference Manual July 1994 2 9 Expressions Function Calls A function call is an expression that causes the execution of a function body The following example shows a function call PROCESS TYPE state IS x z VARIABLE s state FUNCTION funcl st state RETURN state IS The function BEGIN is declare
102. listed in Table 2 8 2 32 Mentor Graphics VHDL Reference Manual July 1994 Expressions Table 2 7 Local Static Operands Locally Static Rules For the Locally Static Operand Operand Constant No deferred constants are allowed Constant must be declared with a locally static subtype and initialized using a locally static expression Predefined Must be an attribute of a locally static subtype that is a attribute value or a function with actual parameters that are locally static Function call The function name must designate a predefined operator Actual parameters must be locally static Literal Any scalar literal type Qualified The type mark must designate a locally static subtype expression The operand must be a locally static expression Locally static expression May be enclosed by parentheses Mentor Graphics VHDL Reference Manual July 1994 2 33 Expressions In this manual several items are defined as locally static Locally static range a range with bounds that are locally static expressions Locally static range constraint a range constraint with a range that is locally static Locally static scalar subtype a scalar type or subtype or base type that is formed by restricting a locally static subtype by imposing a locally static range Locally static discrete range a locally static subtype or locally static range Locally static index constraint an index c
103. ns 717 AFTER 3 ns Mentor Graphics VHDL Reference Manual July 1994 6 47 Statements variable assignment statement The variable assignment statement replaces a current variable value specified by the target with a new value specified by an expression The target and the expression must be of the same base type Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax variable assignment statement target expression Description You usually use a variable for temporary storage when performing calculations Unlike signals variables have no history and their value cannot be scheduled to occur in the future The value of a variable is updated immediately within a process The valid targets of variable assignment are variable names array variable names and aggregates The variable assignment statement cannot assign a new value to a file type variable When you use an array variable name as the target of the variable assignment the new value of the target is specified by the matching element in the corresponding array value expression result Example The following examples show possible variable assignments PROCESS TYPE b array IS ARRAY positive RANGE lt gt OF integer VARIABLE z b array 1 TO 1023 Variable declarations VARIABLE a b c sqrd integ
104. of this expanded name must designate the language construct For more information on expanded names refer to page 3 6 A declaration is directly visible in a specific area of the immediate scope This area encompasses the area between the declaration and the end of the immediate scope except for areas where the declaration is hidden You can make a declaration that occurs immediately within the visible part of a package directly visible outside the package by using the use clause For more information on the use clause refer to page 3 22 Two declarations are homographs of each other if they both use a common identifier and if overloading is allowed for at most one of the two declarations There are two homograph cases one declaration can be overloaded and the other cannot or both declarations can be overloaded and they have the same parameter and result type profile Only enumeration literals or subprogram declarations can be overloaded Homographs declared within the same declarative region create an error With homographs declared in different regions the inner declaration hides the corresponding outer declaration within the inner scope region In this case the homograph declared in the outer region is not visible within the inner region Two formal parameter lists have the parameter type profile if they have the same number of parameters in the list and if the parameters at each position in the list have the same base type Two subprogr
105. package body declarative part Declares items that are used within the package body Description A package body can contain declarative items for a subprogram body In the parity check package body example the variables answer sum1 and sum2 are defined in the subprogram body for function chk_pty These variables are not visible outside of the package parity check Mentor Graphics VHDL Reference Manual July 1994 9 15 Design Units and Packages When you use deferred constants in your package declaration the corresponding package must contain a constant declaration with a value for that deferred constant For more information on deferred constants refer to page 4 13 The value you assign to the deferred constant must be of the same type as defined in the package declaration In the parity check package body example check is a deferred constant whose value is resolved in the package body You can only use the name of the deferred constant in the default expression for a local generic or port or a formal parameter if this name is used before the constant value is defined The VHDL standard predefines two packages for use in your designs Those packages are package standard which provides an assortment of common predefined functions types and subtypes and package textio which allows you to read from and write to formatted ASCII text files Information on these packages is given in the in the following subsection starting on page
106. page 4 5 The following example shows the code you can use to declare an array Mentor Graphics VHDL Reference Manual July 1994 5 23 Types TYPE array frame IS ARRAY VAR ABLE mem array array integer RANGE 1 TO 3 9 DOWNTO 6 OF positive is an array frame mem array The preceding code creates a 3 by 4 two dimensional array The following figure is a representation of this array In the preceding array the stars represent the value of each array element When the array is initialized each element value is equal to positive left which returns an integer value 1 The left value of the range of subtype positive is 1 You can define the contents of this FOR i IN 1 TO 3 LOOP FOR j IN 9 DOWNTO 6 LOOP mem array i j j END LOOP END LOOP array with the following code T3 Another way to define the values for each of the array elements is shown as follows mem_array 2 2 2 2 3 3 3 3 4 4 4 4 ys Both preceding code examples fill the array mem_array with values as the following figure shows 5 24 Mentor Graphics VHDL Reference Manual July 1994 Types 1 Bom ua 2 2 3 3 3 3 3 4 4 4 4 The preceding array example shows you an example of a constrained array and some of the syntax for declaring and manipulating a constrained array An array can be either constrained or uncons
107. range constraint bound The base unit declaration and the secondary unit declaration are used to define a unit name The base unit declaration can be considered the root measure The secondary unit declarations are defined in multiples of the root or in multiples of a previously defined secondary unit For example 5 16 Mentor Graphics VHDL Reference Manual July 1994 Types PROCESS TYPE weight IS RANGE 0 TO 1E6 range constraint UNITS g base unit declaration gram dg 10 g secondary unit declaration decagram hg 10 dg secondary unit declaration hectogram kg 1000 g secondary unit declaration kilogram END UNITS VARIABLE w z weight Declare variables of type weight BEGIN w 100 dg 1 kg 10g Use the phy types in equations z 16 kg dg gt WAIT FOR 10 ns END PROCESS The following examples show some typical uses of physical types from within VHDL code GENERIC prop_delay time o CONSTANT drift freq time is physical type frequency 25 Hz frequency is physical type SUBTYPE p weight IS weight RANGE 1 g TO 10 dg weight is physical type I All physical types can be used with the appropriate predefined arithmetic operators For information on operators refer to page 2 16 If an arithmetic oper
108. statement AHO y 6 34 incomplete_type_declaratin________A40______44 index constraint lt A 4400 5 23 index specification 1 1 1 A 4400 J 38 39 index subtype definion A 2400 523 indexed name A41 38 instantiation_listzz_________AJ4l_______ 8 25 1100 A 4 1 16 integer_type_definition_________A41l____ 539 interface_constant_declaration______A 42______ 424 interface_declaration__________A492_________ 422 interface list gt A 42 422 interface signal declaration A 42 4 26 interface variable declaration A 43 429 iteration_scheme__ 11 A 2433 6 36 label AL 6 3 A 43 1 5 library_clause______________ AM 9 8 library unit 1 AM 9 3 literal 0 AM 1 15 logical name___ A 44 9 8 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary Table A 1 VHDL Construct Listing continued logical name list logical operator loop statement miscellaneous operator mode multiplying operator name next statement null statement numeric literal object declaration operator symbol options package body package body declarative item package body declarative part package declaration package declarative item package declarative part parameter specification physical literal physical type definition port clause port list port map aspect prefix primary primary unit procedure call statement pr
109. the attribute kind The attribute kind tells you what the attribute actually is and the rules for using the attribute value The attribute kinds are as follows O Function O Range O Signal Type O Value For example the attribute low of the array object kind is an attribute of the function kind This means that when you use the attribute it actually calls a function that returns a value Also all the rules for functions apply to the attribute Another example is the attribute quiet that has an object kind of signal and is an attribute of signal kind Therefore if you state test delayed 10 ns there actually exists a signal called test delayed which is test delayed by 10 ns with all the rules that apply to signals You can use this signal just as you would the signal test Mentor Graphics VHDL Reference Manual July 1994 10 5 Attributes Table 10 1 Attributes Attribute Object Page Kind ACTIVE cad Signal 10 29 DASE Type 10 42 behavior Block 10 25 delayed t Signal 10 30 Nica Signal 10 31 ta Type 10 43 high n Array 10 11 ast active Signal 10 32 last event Signal 10 33 ast value Signal 10 34 i E iE Type 10 44 TO rd Array 10 13 TEO ia Type 10 45 length n Array 10 15 OM esie d A Type 10 46 low n Array 10 17 DOS airis Type 10 47 gt
110. the guard is TRUE the signal assignment is made You specify the delay time for the driver to turn off by using a disconnection specification For information on the disconnection specification refer to page 11 8 The methods for guarding signals is to specify register or bus as the signal kind in a signal declaration Refer also to the discussion of concurrent signal assignments on page 6 23 Here is an example of a signal declaration that uses bus as the signal kind SIGNAL data bus wired or bit vector 0 TO 7 BUS Registers and buses are automatically guarded signals You specify the guard expression in a block statement Signals of the kind register retain the last output value when all drivers are disconnected Signals of the kind bus re evaluate the output value when all drivers are disconnected The following example shows the difference between the register and bus signal kinds This first example shows the declaration of a signal called cest of type bit and signal kind bus Notice that the signal cest has two drivers so a resolution function called wired or is necessary The partial code that describes a simple Mentor Graphics VHDL Reference Manual July 1994 11 5 Signals circuit and the illustration of what the circuit could look like follows SIGNAL test wired or bit BUS signal declaration partial code descriptions of circuit with signal test
111. to certain defined regions of your description Figure 4 1 shows where declarations belong in the overall language and the various declarations that this section discusses Design Units Design Entities Configurations Packages Attributes Components Types Signals Statements Subprograms 77 Declarations Expressions Lexical Elements Naming Scope and Visibility Declarations Y Constant Type Variable Subtype Signal Component File Interface Figure 4 1 Declarations The items in this section that the declaration defines are discussed in various sections of this manual This section concentrates mainly on the declaration of a design item not a complete discussion on what the design item is and the rules for using it For the actual pages where these topics are discussed refer to the index page references and the table of contents Appendix B contains a major language construct tree that shows you where you can use all the declarations in 4 2 Mentor Graphics VHDL Reference Manual July 1994 Declarations VHDL You can make several declarations as shown in the following diagram declaration type declaration subtype declaration object declaration file declaration interface declaration alias declaration attribute declaration component declaration lentity declaration subprogram declaration package declaration The following subsecti
112. type with no bounds that represents real numbers with infinite precision Real literals are members of this type Anonymous types have no name so you cannot refer to them Therefore throughout this manual universal integer and universal real appear in italic font to designate that you cannot actually use these types A decimal literal is expressed in base 10 the conventional decimal notation The BNF descriptions for the decimal literal and related constructs are as follows decimal literal integer integer exponent integer digit digit exponent E integer e integer E integer e integer An integer literal cannot contain a decimal point but it can have an exponent The character E represents an exponent and can be either uppercase or 1 16 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements lowercase The is optional after the E A space between the E and the integer is not allowed An integer literal can have a leading zero or a zero exponent but not a negative exponent Spaces are not allowed Here are some examples of valid and invalid integer literals 01468 leading zero is legal 17E0 zero exponent is legal 769 1 space NOT LEGAL The special character in the syntax for integer has no effect on the value of the literal This character provides a method for grouping fields For example 100 000 000 separates fields f
113. type operand operand Subtraction Any numeric Same as left Same as left type operand operand amp Concatenation Any Same as left Same as left single dim operand array operand array array type type type Any Same as Same as left single dim element type operand array array type of left type operand Same as Any Same as element type single dim right operand of right array type array type operand Any element The same as An array of type left operand element type element type Mentor Graphics VHDL Reference Manual July 1994 2 23 Expressions For concatenation the following three cases apply 1 Both operands are one dimensional arrays 2 Only one operand is a one dimensional array 3 Both operands are of the array element type These cases are described in the following paragraphs 1 Following is an example of concatenation in which the operands are both one dimensional arrays PROCESS sens sigl TYPE ref array IS ARRAY positive RANGE OF integer VARIABLE vector ref array 5 TO 9 size is 5 VARIABLE null array ref array 5 TO 1 typing error TO VARIABLE one d ref array 6 DOWNTO 3 size is 4 VARIABLE new array ref array 9 DOWNTO 1 size is 9 BEGIN new array vector amp one d Concatenate arrays size is 9 END PROCESS The conca
114. tz structure descript OF mux nsel aa ab instantiation statements Generic and port maps are discussed on page 8 32 8 22 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Component Binding Component binding is the method you use to connect your declared and instantiated components to the design entities that actually supply the functionality for the components Binding may be compared to plugging an IC into a socket on a circuit board The component declaration and instantiation provide the socket binding plugs an external design entity into the socket The connection is made through three kinds of ports Formal ports which are the inputs and outputs of an entity declaration Local ports which are ports declared in a component declaration Actual ports which are declared in the port map of a component instantiation statement The following three examples show formal local and actual ports The figure at the right shows formal ports declared in the following a code e 2 ENTITY test IS PORT a c dir en b IN bit dir test zz OUT bit en o END test a c dir en b gt z CT E 3 b Z are orma ports L Mentor Graphics VHDL Reference Manual July 1994 8 23 Design Entities and Configurations The figure at the right illustrates the local ports in th
115. vector RETURN boolean FUNCTION 1 r qsim state vector RETURN boolean Only the relational operators for qsim strength are defined All other operations on qsim strength are undefined FUNCTION l r qsim strength RETURN boolean R S I gt Z il F E F mE R F T F F ES S F F T F F F E F FUNCTION 1 r qsim strength RETURN boolean z p R S I A ya F T I F R aes eee e E S Je Oe EU GE xi F F F F 9 48 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages FUNCTION E qsim strength lt 7 R S I Z FE Eo E OE R T F E E S Te E VE CE E O BE E E FUNCTION gt 1 r qsim strength AM EL XA Re aS 1 E I T E R F F T F S F E FEF F E aBa O FUNCTION lt 1 r qsim strength lt r l Z R S I 1 Pe SE E R T T F E cip S qu beu cr I I O IS FUNCTION gt 1 r qsim strength gt Z R S I x Z ee WES GB uem R E E GE F S F F T F x B GE I F FUNCTION same l r qsim_strength True equivalence R R R R R ETURN boolean ETURN boolean ETURN boolean ETURN boolean ETURN boolean The following definitions redefine the basic comparison operators on bit vectors because those operators defined in
116. wired X operation is performed on the inputs to determine the resolved value as follows X 0 L X rx P FX TERK PM 0 rx A EQ 1 T 4 7 EXE M 4 cL VA TXI EQ M dee 9 36 Z x 70 prt FG Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages FUNCTION qsim wired or input qsim state vector RETURN qsim state A wired OR operation is performed on the inputs to determine the resolved value as follows X 0 1 Z o XD CATENAS C LX Lr ut aot uri pe tee EO HX oes ut N HP 6 FUNCTION qsim wired and input qsim state vector RETURN qsim state A wired AND operation is performed on the inputs to determine the resolved value as follows X 0 1 Z X XE des yeh S 0 tiet OE tr tr 1 Z FOSS FE FPE gt qe Xu pue rhe Hem ESPERO EA ES TF QU Vo ee SUBTYPE qsim state resolved x IS qsim wired x qsim state TYPE qsim state resolved x vector IS ARRAY natural RANGE OF qsim state resolved x SUBTYPE qsim state resolved or IS qsim wired or qsim state TYPE qsim state resolved or vector IS ARRAY natural RANGE lt gt OF qsim state resolved or SUBTYPE qsim state resolved and IS qsim wired and qsim state TYPE qsim state resolved and vector IS ARRAY natural RANGE lt gt OF qsim state resolved ang
117. 0 0 Type 10 48 quietltD sais Signal 10 35 range n Array 10 19 reverse range n Array 10 21 Mtra Type 10 49 right m Array 10 23 Hghtof X enne Type 10 50 stable t Signal 10 36 structure cerdas Block 10 26 SUCER Type 10 51 transaction Signal 10 37 ACA Type 10 52 10 6 Mentor Graphics VHDL Reference Manual July 1994 Attributes Detailed Predefined Attribute Description The predefined attributes are divided into four categories according to their object kind If you are not sure which object kind the attribute relates to refer to Table 10 1 on page 10 6 A discussion on each object kind precedes a detailed description of each predefined attribute for that object kind The descriptions for the attributes appear in the following format Kind This subsection designates which kind the attribute is attribute kind An attribute can be a function range signal type or value The attribute kind is not the object kind Table 10 1 on page 10 6 lists the object kind for each attribute Prefix This subsection defines the valid prefix for the attribute The prefix is the object name or function call of the item to which to apply the attribute Parameter This subsection defines the parameter if applicable for the attribute You provide the parameter which is a value that specifies an exact location or time In the descripti
118. 12state BEGIN END alu loader ARCHITECTURE struct OF alu loader IS secondary unit COMPONENT nand2 PORT 10 1 IN my qsim 12state OUT1 OUT my qsim 12state END COMPONENT COMPONENT nor2 PORT I0 1 IN my qsim 12state OUT1 OUT my qsim 12state END COMPONENT COMPONENT latch PORT EN D1 D2 IN my qsim 12state 9 10 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages 01 0_1 02 0_2 OUT my qsim 12state END COMPONENT FOR I1 latch USE ENTITY 1s75 FOR I2 latch USE ENTITY 1s75 FOR I3 nand2 USE ENTITY 1s00 FOR 14 nor2 USE ENTITY 1s02 SIGNAL N15 my qgsim 12state SIGNAL N20 my qgsim 12state BEGIN I1 latch PORT MAP EN gt N20 D1 gt AO D2 gt Al Ql gt Q0 0 l gt OPEN Q2 gt Ol Q 2 gt OPEN I2 latch PORT MAP EN gt N20 D1 gt A2 D2 gt A3 Ol gt Q2 Q_1 gt OPEN Q2 gt Q3 Q 2 gt OPEN I3 nand2 PORT MAP IO gt C2 11 gt C3 OUT1 gt N15 I4 nor2 PORT MAP 10 gt N15 11 gt Cl OUT1 gt N20 END struct Mentor Graphics VHDL Reference Manual July 1994 9 11 Design Units and Packages Packages Packages provide you with a location for collecting various commonly used declarations and subprograms The items in a package
119. 2 Adding operators 2 23 Aggregate 2 8 Allocators 2 13 5 31 AND 2 31 Anonymous types 1 16 4 6 5 9 Architecture bodies 8 14 8 35 Architecture declarative part 8 17 8 39 8 43 Architecture statement part 8 18 Array concatenation 5 28 Array direction 10 10 Array object attributes see Predefined attributes Array type rules 5 27 Array types 5 22 Array definition 5 22 Array operations on 5 28 Arrays slicing 5 28 Assertion statement 6 10 Assignment statements 6 5 Association list 4 31 Attribute declaration 10 54 Attribute kind 10 5 Attribute name 10 3 Attribute names 3 10 Attribute specification 10 55 Attributes predefined 10 5 Base specifiers 1 21 Base type 5 2 Based literal 1 17 Behavioral description 8 15 Binding indication 8 29 Bit string literals 1 20 Bit type declaration 9 18 Bit_vector type declaration 9 20 Block attributes see Predefined attributes Block statement 6 12 Mentor Graphics VHDL Reference Manual July 1994 BNF syntax description how to read xix Boolean type declaration 9 18 Box lt gt 5 26 Buses 11 5 Case statement 6 15 Character and string literal difference 1 20 Character literal 1 18 Character set 1 5 Digits 1 5 Format effectors 1 6 Letters 1 5 Special characters 1 5 Character type declaration 9 19 Comments 1 15 Compatibility range 5 8 Compatible range constraints 5 8 Complete context 3 24 Compo
120. 34 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations configuration declaration A configuration declaration defines a configuration which binds separate design entities to individual components within another design entity A configuration is a primary unit and therefore can be analyzed separately from other primary units Construct Placement declarations primary unit Syntax configuration declaration configuration identifier of entity name is configuration declarative part block configuration end configuration simple name configuration declarative part configuration declarative item configuration declarative item use clause attribute specification Definitions B configuration simple name Same as the identifier you supply for the configuration B entity name Specifies the entity declaration to which the configuration applies B configuration declarative item Optional use clauses make library contents visible optional attribute specifications associate user defined attributes with the configuration B block configuration A block configuration defines the bindings of internal components of an architecture block or generate statement Description Mentor Graphics VHDL Reference Manual July 1994 8 35 Design Entities and Configurations The following example shows how a configuration can be used It is similar to an example given earlier under confi
121. 6 manual vscan SSCSDIR ind bin vscan The script responds with the following prompt Enter phrase to use in search cr to stop You can then enter a phrase to search for For example Enter phrase to use in search cr to stop entity header The preceding command executes the vscan script and returns any occurrence of the language construct entity header To exit the script you enter a carriage return If you require help you can use the h option as shown in the following examples MGC HOME shared pkgs sys 1076 manual vscan h S SCSDIR ind bin vscan h B 2 Mentor Graphics VHDL Reference Manual July 1994 v66L Aine enuey soussejoy TAHA solydesy 101 g design file configuration declaration attribute spec block configuration I component configuration ification library_clause entity package_declaration use_clause entity_statement_part m contains concurrent statements generic clause port clause type declaration subtype declaration constant declaration m signal declaration file declaration attribute specification attribute declaration m use clause disconnection specification alias declaration m subprogram declaration subprogram body E A package_body architecture type declaration I
122. 7 A 64 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary suffix simple name y character literal p operator symbol gt 3 5 target name 9 aggregate gt 6 46 term factor multiplying operator factor 2 4 timeout clause gt for time expression 6 49 type conversion type mark expression 2 12 Mentor Graphics VHDL Reference Manual July 1994 A 65 Syntax Summary type declaration full type declaration p incomplete type declaration S gt 4 4 type definition scalar type definition gt composite type definition access type definition p file type definition N gt 4 4 type_mark fype name subtype name gt 4 7 unconstrained_array_definition ae array of index subtype definition LL of element subtype indication gt 5 23 A 66 Mentor Graphics VHDL Reference Ma
123. 9 18 9 16 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages Example An example of a package declaration with a package body follows Package declaration PACKAGE parity check IS FUNCTION chk pty ram data conc IN bit vector 0 TO 23 orig data conc IN bit vector 0 TO 23 RETURN boolean CONSTANT check integer A deferred constant END parity check Package body PACKAGE BODY parity check IS CONSTANT check integer 0 Deferred constant FUNCTION chk pty ram data conc IN bit vector 0 TO 23 orig data conc IN bit vector 0 TO 23 RETURN boolean IS subprogram body until RETURN VARIABLE answer integer answer is not visible outside of this package VARIABLE suml sum2 boolean false suml and sum2 BEGIN not visible outside this pack FOR i IN O TO 17 LOOP F ram data conc i 17 THEN suml NOT suml compute parity for ram data END IF IF orig data conc i 1 THEN sum2 NOT sum2 compute parity for opcode data END IF END LOOP answer check 1 RETURN suml sum2 return true if suml sum2 END chk pty END parity check If you use package simple name it must match name used after PACKAGE BODY Mento
124. ABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Portions of this manual are based on IEEE Std 1076 1987 IEEE Standard VHDL Language Reference Manual copyright 1988 by the Institute of Electrical and Electronics Engineers Inc The IEEE does not in whole or in part endorse the contents of this manual For information on purchasing the IEEE Standard call 1 800 678 IEEE RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the Government is subject to restrictions as set forth in subdivision c 1 ii of the Rights in Technical Data and Computer Software clause at DFARS 252 227 7013 A complete list of trademark names appears in a separate Trademark Information document Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 Copyright Mentor Graphics Corporation 1993 All rights reserved An unpublished work of Mentor Graphics Corporation Table of Contents TABLE OF CONTENTS About This Manual Section 1 Lexical Elements Definition of Lexical Elements Character Set Replacement Characters Identifiers Reserved Words Comments Literals Numeric Literals Character Literals String Literals Character and String Literal Differences Bit String Litera
125. AP din1 1 din2 I dsel dout I END GENERATE END gen8 Mentor Graphics VHDL Reference Manual July 1994 6 31 Statements Notice that no component binding is specified in the architecture of the preceding example For components that are instantiated by a generate statement component binding must take place in a configuration declaration For an example of such a configuration declaration refer to block configuration beginning on page 8 39 of this manual The following example is an 8 bit synchronous counter consisting of j k flip flops and some AND gates that generate a ripple carry This example shows how if generate statements can be used to cope with irregularities in an otherwise regular structure In this case the counter stages at the ends of the chain are connected differently than those in the middle Conditional generate statements are used to instantiate the counter stages according to their positions in the chain 6 32 Mentor Graphics VHDL Reference Manual July 1994 Statements ENTITY counte
126. CTION 1 Y std_ulogic RETURN std ulogic FUNCTION 1 r std_ulogic RETURN std_ulogic FUNCTION lt rg e std_ulogic RETURN std_ulogic FUNCTION gt dus 8 std_ulogic RETURN std_ulogic FUNCTION lt 1 r std_ulogic RETURN std_ulogic FUNCTION gt 1 r std_ulogic RETURN std_ulogic FUNCTION 1 Y std_ulogic RETURN boolean FUNCTION 1 Y std_ulogic RETURN boolean FUNCTION lt Ty i std ulogic RETURN boolean FUNCTION Lp std ulogic RETURN boolean FUNCTION r std ulogic RETURN boolean FUNCTION r std ulogic RETURN boolean Vectorized Overloaded Relational Operators FUNCTION 1 r std ulogic vector RETURN std ulogic FUNCTION z L E std ulogic vector RETURN std ulogic FUNCTION lt 1 Y std_ulogic_vector RETURN std_ulogic FUNCTION gt Cody std ulogic vector RETURN std ulogic FUNCTION r std ulogic vector RETURN std ulogic FUNCTION gt 1 r std ulogic vector RETURN std ulogic FUNCTION C Lf std ulogic vector RETURN boolean FUNCTION 1 Y std_ulogic_vector RETURN boolean FUNCTION lt Lue zE std ulogic vector RETURN boolean FUNCTION G6 dy E std ulogic vector RETURN boolean FUNCTION r std ulogic vector RETURN boolean FUNCTION r std ulogic vector RETURN boolean 9 28 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages
127. Components Component Declarations Component Instantiations Component Binding configuration specification binding indication entity aspect Generic and Port Map Aspects Default Binding Indication Configurations configuration declaration block configuration component configuration Mentor Graphics VHDL Reference Manual July 1994 8 2 8 4 8 6 8 7 8 8 8 10 8 12 8 14 8 17 8 18 8 20 8 21 8 22 8 23 8 34 8 35 8 39 8 43 Design Entities and Configurations Design Entities The design entity is the basic unit of design description You can create a design entity that describes any level of a design from a complex system to a single logic gate A given design entity can be reused as many times in a design as you wish and you can substitute different design descriptions through different architecture bodies into a design entity to compare implementation results The design entity is composed of two parts The entity declaration The architecture body Figure 8 1 shows where design entities belong in the overall language and it lists the items they contain 8 2 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Design Units Design Entities Configurations Packages Aj Attributes Components p Types Signals Statements Subprograms Declarations Expressions Lexical Elements Naming Scope and Visibility Design Entities Y Y Y Enti
128. Declare a variable Slices of the constant signal and variable result 25 TO 50 Slice of the array result traffic lights 5 TO 4 Null slice because wrong direction test 5 DOWNTO 1 Slice of the array test result 0 DOWNTO 100 Null slice because range of slice is opposite of the range declared for the array result Also a range of 0 downto 100 is null by itself Attribute Names An attribute name consists of a prefix and an attribute designator For predefined attributes the prefix denotes an array block signal or type The prefix for a user defined attribute may denote an entity declaration an architecture body a configuration a procedure a function a package a type a subtype a constant a signal a variable a component or a label The attribute designator is the simple name for the predefined attribute The attribute returns certain information about the item named in the prefix such as length of an array or whether a signal is active The complete discussion of attributes is covered in Section 10 The following diagram shows the related 3 10 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility syntax for an attribute name attribute name prefix attribute designator expression attribute designator attribute sim
129. GIN the following code shows selected sig assign WITH enl SELECT test lt data a WHEN O data b WHEN 1 END BLOCK bus drive For more information on concurrent signal assignments refer to page 6 23 Delay Concepts In each of the three forms of signal assignments you can specify two models to represent delay e Transport delay e Inertial delay You use the reserved word transport to specify that the delay associated with the first waveform element is a transport delay Transport delay indicates that any pulse is transmitted to the signal name you specify with no regard to how short the pulse width or duration This pulse waveform exhibits a frequency response that is nearly infinite which is characteristic of items such as wires and metal paths You typically use transport delay to model pure delay without any consideration of the real physical behavior at high levels of abstraction All input changes pass to the output after the delay time you specify If you do not use the reserved word transport the default is inertial delay Inertial delay applied to a waveform indicates that pulses with a width shorter than the delay time you specify in the waveform element are not transmitted to the signal name you specify This type of delay is characteristic of switching circuits because of the effect of filtering out pulses that are not require
130. HDL Construct Listing continued Location of Syntax For More Language Construct Diagram Information composite type definition A22 5 22 concurrent assertion statement 1 1 A 22 6 19 concurrent procedure call 1 1 A23 6 21 concurrent signal assignment statement A 23 6 23 concurrent statement 1 1 1 A23 67 conditon A24 6 49 condition clause A24 6 49 conditional signal assignment ss A 24 6 25 conditional waveforms A24 6 25 configuration declaration A25 835 configuration _declarative_item_______A25______ 8 35 configuration _declarative_patzz______A25______ 8 35 configuration item _____________A 25___ 8 39 configuration specification 1 A25 8 25 constant_declaration 1 1 A 2606 4 13 constrained array definition A26 523 constraint 1 1 A 2600 4 7 context_clause______________A 6_____ 9 5 context A 2260 9 55 decimal_literal_______________A27_______ 1 16 declaration 1 1 1 A27 43 design file A 28 9 3 design_unit A 28 9 3 designator_ A HB 76 digit CAB 1 5 direction A 28 5 5 disconnection specification 1 A 29 11 8 discrete_range_ A229 5 23 element_association_______________ A 29 2 8 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary Table A 1 VHDL Construct Listing continued element declaration element subtype d
131. I subprogram declaration subprogram body 1 file declaration Bo procedure function block process GE D block statement part contains concurrent statements type declaration subtype declaration constant declaration signal declaration file declaration alias declaration attribute specification attribute declaration use clause generic clause port clause configuration specification subprogram declaration En subprogram_body disconnection_specification process component declaration block text A box indicates the construct is non terminal text An oval indicates objects of this type can be declared within the object itself text Indicates the construct is terminal meaning no declarations can occur within it process statement part m contains sequential statements type declaration r subtype declaration constant declaration variable declaration m file declaration alias declaration attribute specification attribute declaration use clause subprogram declaration subprogram body sjonujsuo oBenDue7 Hueso Index INDEX ABS 2 18 Abstract literal 1 16 Access type definition 5 31 Access types 5 31 Actual ports 8 23 Actuals 4 3
132. July 1994 Statements component instantiation statement The component instantiation statement creates an instance of a subcomponent within a design entity connects signals to that subcomponent and associates generics in the design entity with generics in the subcomponent Construct Placement concurrent statement architecture statement part block statement part Syntax component instantiation statement instantiation label component name generic map aspect port map aspect Definitions E instantiation label A unique identifier that you supply to identify the component instance B component name The name of the component from the component declaration that is being instantiated Description Using component instantiation statements along with component declarations and signals allows you to decompose a structural design into subcomponents The instantiated subcomponents must be bound to external design entities that determine the behavior of the subcomponents You can alter the characteristics of a design at any point in the design process by binding different design entities to the subcomponents The topic of components and their use is discussed beginning on page 8 20 The following list shows the rules and information for using the component instantiation statement e The component name you use must be the name of a component you declare in the component declaration Mentor Graphics VHDL Referen
133. Mentor Graphics VHDL Reference Manual July 1994 GMishice Copyright 1991 1994 Mentor Graphics Corporation All rights reserved Confidential May be photocopied by licensed customers of Mentor Graphics for internal business purposes only The software programs described in this document are confidential and proprietary products of Mentor Graphics Corporation Mentor Graphics or its licensors No part of this document may be photocopied reproduced or translated or transferred disclosed or otherwise provided to third parties without the prior written consent of Mentor Graphics The document is for informational and instructional purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in the written contracts between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LI
134. Mentor Graphics VHDL Reference Manual July 1994 Declarations constant declaration A constant declaration declares an object in which the object value is set and cannot be changed Construct Placement block declarative item entity declarative item object declaration package body declarative item package declarative item process declarative item subprogram declarative item Syntax constant declaration constant identifier list subtype indication expression Definitions B identifier list An identifier list is one or more names that you provide for each declared object B subtype indication Indicates the type and any related restrictions that apply to the object s being declared B expression Defines the value of the constant Description 2 A constant declaration specifies a list of simple names a type and an optional value for objects that cannot change value These objects are constants If you use an expression after the delimiter this expression defines the value of the constant This expression must be of the same type as the constant and the expression subtype must be convertible to the subtype indication The type of the constant cannot be a file type The following examples show some possible constant declarations that use the constant value expression CONSTANT offset real 0 5 CONSTANT vcc high voltage logic 1 integer 5 CONSTANT bit mask st
135. Mentor Graphics VHDL Reference Manual July 1994 Declarations variable declaration A variable declaration declares an object in which the object value has a single current value that can be changed Construct Placement object declaration process declarative item subprogram declarative item Syntax variable declaration variable identifier list subtype indication expression Definitions B identifier list An identifier list is one or more names that you provide for each declared object B subtype indication A subtype indication specifies the type and any related restrictions that apply to the object s being declared B expression An expression defines the initial value of the variable Description A variable declaration specifies simple names a type and an optional initial value for objects that have a single current value that can be changed If you use an expression after the delimiter this expression defines the initial value of the variable This expression must be of the same type as the variable and the expression subtype must be convertible to the subtype indication The type of the variable cannot be a file type The following examples show some possible variable declarations that use the initial variable value expression VARIABLE calc result integer 0 VARIABLE x y z real 0 707 VARIABLE data integer RANGE 0 TO 1024 256 Mentor Graphic
136. Mentor Graphics VHDL Reference Manual July 1994 4 11 Declarations CONSTANT round off term offset real 0 5 The preceding constant declaration is equivalent to CONSTANT round off real 0 5 single object decl CONSTANT term real 0 5 single object decl CONSTANT offset real 0 5 single object decl Table 4 1 Objects Object Example Item declared by an object CONSTANT gnd integer 0 declaration gnd is an object Element or slice of another object VARIABLE x bit vector 1 TO 20 x 10 TO 15 slice File declared by a file declaration FILE stats integer IS OUT tfd stats is an object A loop parameter FOR i IN 1 TO 20 LOOP i is the loop parameter Formal parameter in a subprogram FUNCTION z m IN bit RETURN bit m is a formal parameter Formal port in design entity ENTITY check IS PORT sin IN bit sin is a formal port A local port COMPONENT and3 PORT in 1 IN bit in 1 is a local port A formal generic ENTITY adder IS GENERIC dly time A local generic dly is a formal generic COMPONE GENERIC ldly time ldly is a local generic The following subsections show you the specific details for declaring each of the VHDL objects
137. Notice that without an incomplete type declaration you would be unable to include the pointer as part of the structure that it refers to You must first use an incomplete type declaration to make the name of the access type available to the record type declaration Once the record type has been declared you complete the declaration of the access type which can now refer to the record type For additional information on access types refer to the preceding subsection access type definition For a formal syntax description of both full and incomplete type declarations refer to type declaration on page 4 4 Mentor Graphics VHDL Reference Manual July 1994 5 33 Types file type definition The file type definition defines data types for use in file declarations Construct Placement type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax file_type_definition file of type_mark Definitions o gt B type mark Defines the type of the values contained in the file Description lt 0 0 0 0 0 0 Files may be read only or write only but not both Some uses of file types are the following e Logging and tracing error conditions e Collecting data for statistics e Loading the contents of memory with data e Loading test vectors for your model The following
138. OOP array b array a 6 TO 9 slice of array a END PROCESS Figure 3 2 illustrates the preceding example array a 11 12 18 14 15 E16 17 18 19 20 21 22 array b 16 17 18 1119 Figure 3 2 Slice Name Concept Mentor Graphics VHDL Reference Manual July 1994 3 9 Naming Scope and Visibility The prefix you use must be valid for one dimensional array types For information on array types refer to page 5 22 You specify the array bounds of the slice by using a discrete range The discrete range you specify must be of the same type as the index of the array you are slicing If you specify a null discrete range or a range direction opposite to the object designated by the slice name prefix the slice is a null slice When a slice name is evaluated an error occurs if you specify a discrete range with bounds that do not belong to the index range specified in the prefix array No error occurs if a null slice is specified because the null slice bounds do not have to be a subtype of the index range specified by the prefix array Some slice name examples follow Begin by declaring a constant signal and variable TYPE this array IS ARRAY natural RANGE lt gt OF integer CONSTANT result this array 0 TO 100 OTHERS gt 0 SIGNAL traffic lights bit vector 0 TO 7 Declare a signal VARIABLE test this array 10 DOWNTO 1
139. OOP i 256 16 cannot use loop parameter as target of assignment e lt D LOOP Mentor Graphics VHDL Reference Manual July 1994 6 37 Statements next statement The next statement is used to complete the execution of one of the iterations of an enclosing loop statement Completion depends on a condition you specify The condition must be a Boolean expression Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax next statement next oop label when condition Description If you use a loop label it must be within an enclosing loop with the same label If you do not use a loop label the next statement applies only to the nearest enclosing loop in which it appears Example The following example shows the next statement in an enclosing loop outer Outer loop label WHILE a 10 LOOP Sequence of statements inner Inner loop label FOR i IN O TO 10 LOOP Sequence of statements NEXT outer WHEN i a END LOOP inner Sequence of statements END LOOP outer 6 38 Mentor Graphics VHDL Reference Manual July 1994 Statements null statement The null statement allows you to explicitly state that no action occurs This statement has no effect on your description other than causing execution to pass on to the next construct
140. OUT bit END COMPONENT COMPONENT inverter A PORT 1 IN bit z OUT bit END COMPONENT BEGIN 4 36 Mentor Graphics VHDL Reference Manual July 1994 Declarations Type Conversion Functions As the syntax description for association lists on page 4 31 shows the formal and actual part in an element association can be a function call The function in this case is a user defined type conversion function This function allows you to map formals of one type to actuals of another type This is especially important for the mapping of signals because you want to return a converted signal with all the corresponding signal attributes included For information about writing functions refer to Section 7 There are several common type conversion functions provided in the package my qsim base The example following this paragraph shows a typical situation for the mapping of signals and the use of a conversion function from my qsim base to integer In this example there are two design items that are connected together that have different signal types The following code shows a call to the type conversion function for connecting port a with port b using signal s The entity declaration struct entity does not appear in this example Mentor Graphics VHDL Reference Manual July 1994 4 37 Declarations EN I
141. RE write NOUT line value IN bit justified IN side right field IN width DURE write NOUT line value IN bit vector justified IN side right field IN width DURE write NOUT line value IN boolean justified IN side right field IN width DURE write NOUT line value IN character justified IN side right field IN width DURE write NOUT line value IN integer justified IN side right field IN width DURE write NOUT line value IN real justified IN side right field IN width digits IN natural 0 DURE write INOUT line value IN string justified IN side right field IN width DURE write INOUT line value IN time justified IN side right field IN width unit IN time ns 9 31 Design Units and Packages File Position Predicates FUNCTION endfile f IN text RETURN boolean Eri ND textio The following example writes two characters H and I on separate lines to a file named txtio tmp USE std textio ALL ENTITY textio ex IS EGIN ND textio ex E UJ ARCHITECTURE behav OF textio ex IS FILE outl text IS OUT txtio tmp BEGIN PROCESS VARIABLE linel line VARIABLE charl character BEGIN charl H write linel charl RIGHT 0 charl a s RES en
142. SXR SXS SXI SXR SXR SOS SXI SXR SXR S1S SXI SXZ SXR SXZ SXS SXI SOR SXZ SOS SXI SIR SXZ S1S SXI SXS SXS SXS SXS SXS SXS SXS SXS SXS SXS SXS SXS SXS SXI SXI SXI SXS SXI SXI SXI SXS SXI SXI SXI SXS SXI SOR SXR SOR SXS SXI SOR SOR SOS SOI SXR SOR S1S SXI SOZ SXR SXZ SXS SXI SOR 507 SOS SOI SIR SXZ S1S SXI 505 SOS SOS SXS SXS SOS SOS SOS SOS SOS SOS SXS SXS gt SOI SXI SXI SXS SXI SOI SOI SOS SOI SXI SXI SXS SXI gt SIR SXR SIR SXS SXI SXR SIR SOS SXI SIR SIR S1S SII 12 SXR SXZ SXS SXI SOR SXZ SOS SXI SIR S12 S1S SII SS S1S S1S SXS SXS S1S SIS SXS SXS 515 S1S SIS 515 S21 SXI SXI SXS SXI SXI SXI SXS SXI SII 511 S1S SII SUBTYPE qsim 12state resolved IS qsim wired qsim 12state TYPE qsim 12state resolved vector IS ARRAY natural RANGE lt gt OF qsim 12state resolveg Other miscellaneous types related to qsim 12state SUBTYPE qsim value IS qsim state RANGE X TO 1 TYPE qsim value vector IS ARRAY natural RANGE OF qsim value TYPE qsim strength IS I tA NR a TYPE qsim strength vector IS ARRAY natural RANGE lt gt OF qsim strength Other miscellaneous types Resolution function and type for bit types FUNCTION bit wired or input bit vector RETURN bit SUBTYPE bit resolved or IS bit wired or bit TYPE bit resolved or vector IS ARRAY natural RANGE OF bit resolved or FUNCTION bit wired and input bit vector RETURN bit SUBTYPE bit resolved and IS bit wired and bit T
143. Syntax association list association element association element association element formal part gt actual part formal part formal designator function name formal designator formal designator generic name port name parameter name actual part actual designator function name actual designator actual designator expression signal name variable name open Definitions m A formal is a generic or port of a design entity or a parameter of a subprogram Mentor Graphics VHDL Reference Manual July 1994 4 31 Declarations An actual is a port signal variable or expression that is associated with a corresponding formal B A local is a special name for a generic or port in a component declaration Description FORMAL or LOCAL LOCAL or ACTUAL E GI Generic Name Generic Name lt SH b Port Name Port Name Subprogram Parameter Name e ai Parameter Name xpression Figure 4 3 Association List Concept Every association element in an association list relates an actual designator with a corresponding interface declaration The interface declaration is in the interface list of a component entity or subprogram declaration This relation can be made by the following methods e Named e Positional You make a named association when you use the gt delimiter to state explicitly which formal is associated with whi
144. T 1991 document recommends that within subprograms the optional default expression is not allowed This IEEE document helps clarify ambiguities in the IEEE Std 1076 1987 IEEE Standard VHDL Language Reference Manual The following notes document how each Mentor Graphics VHDL implementation handles this situation S In an interface signal declaration within subprograms the System 1076 compiler flags the default expression as an error E Inan interface signal declaration within subprograms the Explorer VHDLSim compiler allows use of a default expression Mentor Graphics VHDL Reference Manual July 1994 4 27 Declarations Example The following examples show the interface signal declaration within portions of code component declaration COMPONENT nand2 GENERIC PORT SIGNAL a b IN bit interface signal decl z 4 QUI bit entity declaration ENTITY controller IS GENERIC PORT a0 al sel IN bit interface signal decl y OUT bit subprogram declaration PROCEDURE check SIGNAL test IN bit IS interface signal declaration gt subprogram declaration PROCEDURE check SIGNAL test IN bit 0 IS System 1076 ERROR Default expression not allowed here in all VHDL implementations This c
145. TECTURE or2 behav OF or2 input IS 43 BEGIN 44 f lt d OR e AFTER 10 ns 45 END or2 behav 46 47 48 ENTITY mux IS The design entity for a mux is defined 49 PORT a0 al sel IN bit y OUT bit 50 END mux 51 52 53 ARCHITECTURE structure_descript OF mux IS 54 COMPONENT and2 Component declarations 55 PORT a b IN bit 2 OUT bit 56 END COMPONENT 57 COMPONENT or2 58 PORT a b IN bit z OUT bit 59 END COMPONENT 60 COMPONENT inverter 61 PORT i IN bit z OUT bit 62 END COMPONENT 63 64 SIGNAL aa ab nsel bit 65 66 The configuration specifications 67 FOR Ul inverter USE ENTITY WORK inv not_a 68 GENERIC MAP 7 ns 69 PORT MAP i z 70 FOR U2 and2 USE ENTITY WORK and2 input basic and2 71 FOR OTHERS and2 USE ENTITY WORK and2 s behav and2 72 13 BEGIN 74 Component instantiation statements 75 Ul inverter PORT MAP sel nsel 76 U2 and2 PORT MAP a0 nsel aa 73 U3 and2 PORT MAP al sel ab positional assoc 78 U4 or2 PORT MAP a gt aa b gt ab z gt y named assoc 79 END structure descript Mentor Graphics VHDL Reference Manual July 1994 8 27 Design Entities and Configurations The previous example shows three configuration specifications lines 66 through 70 one with the reserved word others line 70 and two specifying an explicit label name lines 66 and 69 The following example is a section of code showing the use of th
146. TIONS atan2 x y real RETURN real pseudo random numbers should be used as follows VARIABLE rn real rn gt wl459 rn rand rn rn is the random number Generate random number from seed cyeturns a number between 10 0 1 0 based on the seed The results from this function is not guaranteed to be portable FUNCTION rand seed real RETURN real END math Mentor Graphics VHDL Reference Manual July 1994 9 35 Design Units and Packages mgc portable qsim logic S PACKAGE qsim logic IS This predefined Mentor Graphics package provides enumerated types that allow the designer to interface from a VHDL model to a Mentor Graphics model or allow a VHDL model to be used in a non VHDL design The qsim state type provides signal values that are typically found in most simulators with minimum worry about signal strengths The signal is mapped as to STATE follows Mentor maps OS Or gt 0 mc TS lr gt 1 XS Xr Xi gt X Qu is i X 07 Xz 17 gt Z Sa STATE map s to Mentor N XRO ll V TYPE qsim state IS TYPE qsim state vec OF qsim state X tor OS 15 XS XZ EQ LA Fars IS ARRAY natural RANGE lt gt Resolution function and resolved subtype for qsim state FUNCTION qsim wired x RETURN qsim state input qsim state vector A
147. TURN qsim strength vector Mentor Graphics VHDL Reference Manual July 1994 9 39 Design Units and Packages FUNCTION qsim state from val qsim 1 RETURN qsim state vector Define the to qsim state function FUNCTION to qsim 12state val qsim s str qsim s RETURN qsim 12state FUNCTION to qsim 12state val qsim str qsim s RETURN qsim 12state vector FUNCTION to qsim 12state val qsim s RETURN qsim 12state vector 2state vector tate trength rst value vector trength vector tate vector The following are miscellaneous conversion functions from bit to qsim state bit vector to integer qsim state vector to integer integer to bit and integer to qsim state vector For integer conversion the left is msb and right 15 Isb For those functions taking a vector argument and returning a vector the range of the result is taken from the input vector For those functions having a scalar argument and returning a vector the range of the result has a left value of 0 a direction of to and a length value equal to the input argument size FUNCTION to qsim state val de faul initial F F tra FUNCTI FUNCTI gt FUNCT R UNCTI to_qsim state prod ON to_qsim_state val integer parameters not yet supported bi RI t ET ION RN to_qsim_state qsim
148. YPE bit resolved and vector IS ARRAY natural RANGE OF bit resolved and 9 38 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages An array of TYPE time vector Timi TYPE timing_type IS Conversions to and from qsim state time values IS ARRAY natural RANGE lt gt OF time ng mode selection min typ max qsim strength and qsim value FUNCTION qsim value from val qsim 12state RETURN qsim value XE Conversion is State Result SOS SOR S02 SOI 0 515 SIR S12 SII T SXS SXR SXZ SXI X FUNCTION qsim strength from val qsim 12state RETURN qsim strength conversion is m state result 502 512 SXZ Z aS SOR SIR SXR R SOS S1S SXS S SOI 511 SXI I FUNCTION qsim state from val qsim 12state RETURN qsim state m Conversion is m State Result m S0S SOR 0 Er S1S SIR 1 SXS SXR SXI SOI S1 X pu SXZ 502 812 Z Conversion for arrays is the same as for scalars the result is the same size as the argument and the conversion is applied to each element For those functions taking a vector argument and returning a vector the range of the result is taken from the input vector FUNCTION qsim value from val qsim 12state vector RETURN qsim value vector FUNCTION qsim strength from val qsim 12state vector RE
149. _________A60_______ 6 5 Sign 1 1 JJ co A 0600 222 signal assignment statement 1 A 6061 lt 6 46 signal _declaration_____________A61_______ 11 14 signal kind A 6601 11 14 signal list_zz___________A61______ 1I 8s simple_expression _________A62___ 24 simple_name AL 34 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary Table A 1 VHDL Construct Listing continued slice name special characters string literal subprogram body subprogram declaration subprogram declarative item subprogram declarative part subprogram specification subprogram statement part subtype declaration subtype indication suffix target term timeout clause type conversion type declaration type definition type mark unconstrained array definition use clause variable assignment statement variable declaration wait statement waveform waveform element Location of Syntax For More Diagram Information A 62 3 9 A 62 1 5 A 63 1 19 A 63 7 10 A 63 7 6 A 64 7 10 A 64 7 10 A 65 7 6 A 65 7 10 A 65 4 7 A 65 4 7 A 66 3 5 A 66 6 46 A 66 2 4 A 66 6 49 A 66 2 12 A 67 4 4 A 67 4 4 A 67 4 7 A 67 5 23 A 68 3 22 A 68 6 48 A 68 4 15 A 68 6 49 A 69 6 46 A 69 6 46 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary How to Read a Syntax Diagram The syntax diagram is a visual representation of the rules for constructing and arranging your code The example in
150. _state_vec val tor ION to_qsim_state RN qsim_state_vec val tor these conversions r nslated to the bit value bit_vect integer the qsim state value X 0 ON to bi val qsim s ta RE 7 E te ON to bi val qsim s ION to bit val ETURN bit vector De Fault initial 9 40 ta integer size te vector Size integer 32 URN qsim state Or size integer uces a 2 s complement representation and Z is TURN bit RETURN bit vector integer 32 parameters not yet supported Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages FUNCTION to bit val integer size integer RETURN bit vector to bit produces a 2 s complement representation FUNCTION to integer val bit vector RETURN integer to integer assumes a 2 s complement representation In this conversion function the qsim state value X and Z are translated to the integer value of the second parameter x By default the value is zero 0 FUNCTION to integer val qsim state vector x integer 0 default initial parameters not yet supported FUNCTION to integer val qsim state vector x integer RETURN in
151. able t transaction Signal Attribute Example Type Attributes base Mentor Graphics VHDL Reference Manual July 1994 9 47 10 8 10 11 10 13 10 15 Table of Contents TABLE OF CONTENTS continued Section 10 Attributes continued high left Jeftof x low pos x pred x right rightof x succ x val x User Defined Attributes o gt S attribute declaration attribute specification 00 0000000000000 0000 0 0 Section 11 Signals Signal Concepts Drivers Guarded Signals disconnection specification Multiple Drivers and Resolution Functions signal declaration Default Expression Signal Assignments Sequential Signal Assignments Concurrent Signal Assignments Delay Concepts Delta Delay 10 54 10 55 11 4 11 4 Mentor Graphics VHDL Reference Manual July 1994 Table of Contents TABLE OF CONTENTS continued Appendix A Syntax Summary How to Read a Syntax Diagram Appendix B Locating Language Constructs Index Mentor Graphics VHDL Reference Manual July 1994 A 1 A 9 B 1 xi Table of Contents LIST OF FIGURES Lexical Elements Lexical Element Use Special Characters Syntax Expressions Expression Concept Naming Scope and Visibility Slice Name Concept Scope Scope of Entity Plus Architecture Visibility Declaration Hiding and Homographs No Homograph Instance Multiple Use Clauses Declarations Interfac
152. ackage textio contains declarations of types and subprograms that allow you to read from and write to formatted ASCII text files Some examples showing the use of the textio package follow the listing of the package PACKAGE textio IS Type Definitions for Text I O TYPE line IS ACCESS string a line is a pointer to a string value TYPE text IS FILE OF string a file of variable length ASC records TYPE side IS right left for justifying output data within fields SUBTYPE width IS natural for specifying widths of output fields Standard Text Files FILE input text IS IN STD INPUT FILE output text IS OUT STD OUTPUT Input Routines for Standard Types PROCEDURE readline VARIABLE f IN text 1 INOUT line PROCEDURE read 1 INOUT line value OUT bit good OUT boolean PROCEDURE read 1 INOUT line value OUT bit PROCEDURE read l INOUT line value OUT bit vector good OUT boolean PROCEDURE read 1 INOUT line value OUT bit vector PROCEDURE read 1 INOUT line value OUT boolean good OUT boolean PROCEDURE read 1 INOUT line value OUT boolean PROCEDURE read 1
153. adding operator gt amp fe es J S 2 23 aggregate gt element association gt is 2 8 alias declaration alias identifier gt subtype indication gt is name gt gt 4 35 allocator gt new subtype indication __ qualified expression gt 2 4 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary architecture simple name architecture body gt architecture gt b js N CS j gt of entity name gt is gt architecture declarative part El begin B architecture statement part i V end architecture simple name gt 8 14 architecture declarative part block declarative item gt 8 17 architecture statement part concurrent statement gt 8 18 array type definition unconstrained array definition constrained array definition gt 5 23 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary assertion statement assert condition report gt expression i TIN p Severity expression 5 gt 6 10 y AES associatio
154. additional operand and result types for the multiplication and division predefined operators 2 36 Table 2 9 Universal Expression Operators Operator Operation Left Right Result Type Operand Operand Type Type x Multiplication universal universal universal real integer real universal universal universal integer real real Division universal universal universal real integer real Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility Section 3 Naming Scope and Visibility S This section discusses two topics the concept of names and the concept of scope and visibility You must identify every design item you declare with some form of name The system requires a design item to be named before the system can manipulate the design item Each design you create may have hundreds of names within it This collection of names forms a name space There can only be one declaration of a given name per name space and the collection of name spaces forms the complete name space To make the task of managing the complete name space controllable VHDL provides scope and visibility rules The scope of a design item is the region of text in which the declaration of the item has effect Visibility rules define where the name from a declaration can be seen The following ordered list shows the topics described in this section Naming 3 3 Simple Names 3 4 Selected Names 3 4 Indexed Na
155. ains a signal assignment statement The value is FALSE for any other case If the result is TRUE it informs you that the code contains a structured description 10 26 Mentor Graphics VHDL Reference Manual July 1994 Attributes Example The following example shows a block within an architecture ARCHITECTURE sig test OF test IS SIGNAL tester wired or bit vector BUS signal decl SIGNAL a b c bit BEGIN sig assign block label BLOCK tester 1 guard expression SIGNAL z bit vector block declarative item DISCONNECT tester bit vector AFTER 10 ns BEGIN z lt GUARDED a z gets a if test 1 sig assign END BLOCK sig assign ND sig test tz The following example shows the use of the predefined attribute structure in relation to the preceding example Sig assign structure The value that returns from the preceding code is FALSE because the block sig assign contains a signal assignment statement Mentor Graphics VHDL Reference Manual July 1994 10 27 Attributes Signal Attributes You use signal attributes to determine if certain signal conditions are true to return information about signals or to add delay time to signals An important concept to keep in mind is that the delayed signal attribute is actually a signal of the same base type as the prefix Figure 10 3 shows an example of
156. al and the delimiter for signal assignment lt are the same can be confusing in some situations For an example of when this can produce valid code that gives completely different results than you might expect refer to page 6 25 Miscellaneous Operators Miscellaneous operators have the highest precedence of the predefined operators and have the following syntax miscellaneous operator abs not Table 2 3 lists the miscellaneous operators their operation and valid types for the operands and result For more information on types refer to Section 5 Table 2 3 Miscellaneous Operators Predefined Operation Left Right Result Type Operator Operand Operand Type Type Exponentiation Any integer Predefined Same as left S type type integer operand Any floating Predefined Same as left point type type integer operand abs Absolute value None Any numeric Same as right type operand The predefined operator not is a logical operator that has the precedence of a miscellaneous operator Therefore not is discussed with the other logical operators on page 2 31 An example using the miscellaneous operators and abs follows 2 18 Mentor Graphics VHDL Reference Manual July 1994 Expressions PROCESS VARIABLE a b c e result answer integer 2 CONSTANT d integer 2 BEGIN a lt 0 6 result e 8 ABS d
157. al contains information about the commands functions userware and related reference material specific to the Mentor Graphics digital analysis applications Mentor Graphics VHDL Reference Manual July 1994 xxi About This Manual e Getting Started with Design Architect Training Workbook is for new users of Design Architect who have some knowledge about schematic drawing and electronic design and are familiar with the UNIX or Aegis environment This training workbook provides basic instructions on using Design Architect to create schematics and symbols e Getting Started with Falcon Framework Training Workbook is for new users of the Mentor Graphics Falcon Framework This workbook introduces you to the components of the Falcon Framework and provides information about and practice using the Common User Interface Design Manager INFORM Notepad and Decision Support System applications e Getting Started with QuickSimllI Training Workbook is for Electrical Engineers who have not previously used QuickSimlII This training workbook provides basic instructions on using QuickSimll to simulate digital designs e Simview Common Simulation User s Manual contains information about the features common to the Mentor Graphics analog and digital analysis applications e Simview Common Simulation Reference Manual contains reference information about the commands functions userware and features common to the Mentor Graphics analog and digital analy
158. amine data shifter data contents 25 ns shifter corresponds to my part data contents to read data and 25 ns to prop delay If the type of the parameter in the call does not match the type of the parameter in the subprogram an error occurs You can also use named parameter association as a method for calling a subprogram In this method you explicitly relate the parameter in the call to the parameter in the subprogram This method allows you to use a different parameter order in the call than the order in which the parameters appear in the subprogram Mentor Graphics VHDL Reference Manual July 1994 7 13 Subprograms Named parameter association is also a good way to document exactly what is taking place in the call Using the example specification for examine data the following example shows a parameter association call examine data my part gt shifter prop_delay gt 25 ns read_data gt data_contents shifter corresponds to my part data contents to read data and 25 ns to prop delay You can also use default parameters as a method for calling a subprogram Using this method you omit parameters in the call that have default values assigned thereby using the default value The following example shows a default parameter call for examine data examine data shifter data contents the default value for prop delay is 1 ns Although the
159. ams have the same parameter and result type profile if they both have the same parameter profile and if they are functions the functions return a result with the same base type In the case of enumeration literals no homograph exists if the base types are different For information on overloading refer to page 3 24 3 18 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility Table 3 2 Visibility by Selection Design Item Selected By Primary unit in library Suffix in selected name prefix designates the library Declaration in package declaration Suffix in selected name prefix designates the package Predefined attribute that applies to a given range of definition Attribute designator after in attribute name Formal parameter decl of specified subprogram declaration Formal designator before gt in parameter association list Local generic decl of specified component declaration Formal designator before 2 in a named generic association list of a corresponding component instantiation statement or actual designator after gt in generic association list of a corresponding binding indication Local port decl of specified component declaration Formal designator before gt in a named port association list of a corresponding component instantiation statement or actual designator after gt in port association list of a corresponding
160. arded Signals __ 5S disconnection specification 8 Multiple Drivers and Resolution Functions 11 10 signal_declaration o 14 Default Expression 1 15 Signal Assignments l 16 Sequential Signal Assignments 1 1 1 1 11 16 Concurrent Signal Assignments 11 17 Delay Concepts 1 1 19 Delta Delay LL 11 20 Figure 11 1 shows where signals belong in the overall language and shows the topics that this section discusses Signals are the fundamental design object in VHDL Signals are the only means for interfacing two or more entities as they provide the channels of communication You can make the analogy that signals are the equivalent of nets and pins on a schematic sheet Since a signal is an object it must be declared before you can use it A signal declaration takes two forms as the following list shows e Explicitly declare the signal using a signal declaration You can use the signal declaration in an entity declaration architecture declaration block statement or a package declaration Mentor Graphics VHDL Reference Manual July 1994 11 1 Signals Declare the signal as a port You can declare a port in the entity header of an entity declaration in a parameter in a subprogram specification or in a component declaration For information on ports refer to page 8 8 Design Units Design Entities Configurations Packages Attributes Components
161. are visible anywhere the name of the package is visible or where a use clause makes them visible The use clause is discussed in detail on page 3 22 Packages consist of two parts a declaration and a body This has the same benefits as having separate declarations and bodies for entities and subprograms O One interface the declaration can have several different bodies You can rewrite the bodies without having to recompile the declaration These features are all necessary for dividing up a project between teams Figure 9 4 shows the package concept Package NENS 2 and Subprograms 72 PE Description b Code Pee Sharing One Package Figure 9 4 Package Concept 9 12 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages package declaration The package declaration defines a name for the package and an interface to other design items by specifying the visible contents of the package Visibility is discussed in detail on page 3 12 Construct Placement declaration primary unit Syntax package_declaration package package_simple_name is package_declarative_part end package simple name package declarative part package declarative item package declarative item subprogram declaration type declaration subtype declaration constant declaration signal declaration file declaration alias declaration component declaration attribute declara
162. ase does compile in Explorer VHDLSim 4 28 Mentor Graphics VHDL Reference Manual July 1994 Declarations interface variable declaration An interface variable declaration declares one or more variable objects that serve as variable parameters in subprograms Construct Placement interface declaration subprogram specification Syntax interface variable declaration variable identifier list mode subtype indication static expression Definitions B identifier list Lists one or more variable names Multiple names must be separated by commas B subtype indication Indicates the type and any constraints that apply B expression Defines the initial value of the variable Description The following list shows information and the rules for using the interface variable declaration You have the option to use the reserved word variable at the beginning of the interface variable declaration There are defaults for subprograms when you omit this reserved word This issue is discussed in detail on page 7 8 You have the option to specify a mode for the variable parameter If omitted the mode defaults to in The subprogram parameter can be a file type when the interface object is a variable Based on the recommendation in the JEEE std 1076 INT 1991 document the optional default expression in a variable interface declaration is allowed for Mentor Graphics VHDL Reference Manual
163. assignment statement variable assignment statement procedure call statement if statement case statement loop statement next statement exit statement return statement null statement Description You can use sequential statements only inside a process statement or within a subprogram procedure or function Each statement executes in the order in which it is encountered The preceding BNF description listed the sequential statements available in VHDL Sequential statements are divided into categories based on their operation The following list shows the categories for the sequential statements Assignment statements These statements provide you with a method for changing the value of variables and signals The statements include the following O Variable assignment statement O Signal assignment statement Mentor Graphics VHDL Reference Manual July 1994 6 5 Statements Conditional statements These statements provide you with a method of controlling the execution of other sequential statements This control depends on the resulting value of an expression The statements include the following O Case statement O If statement O Wait statement e Iterative statements These statements provide you with a method of executing a sequence of statements repeatedly The statements include the following O Loop statement O Next statement Also controls loop iteration O Exit statement Also controls l
164. at position 2 specified by the parameter 2 color val 2 The position number for an enumerated type is always referenced from zero and increases left to right From the previous example Value red yellow green flash Position 0 1 2 3 10 52 Mentor Graphics VHDL Reference Manual July 1994 Attributes User Defined Attributes User defined attributes allow you to add to design descriptions incidental or supplemental information that cannot be described using other VHDL constructs For example you might want to back annotate such physical characteristics as component placement signal to pin assignments or output and input capacitances to a design You employ user defined attributes through the following VHDL constructs e Attribute declaration names and sets the type of a user defined attribute Attribute specification which associates a user defined attribute with one or more members of a particular entity class such as an entity declaration procedure signal or component The specification also defines the value of an attribute Attribute name gives you access to a user defined attribute in the same way as for predefined attributes The attribute declaration and attribute specification constructs are described on pages 10 54 and 10 55 respectively the attribute name construct is described on page 10 3 Mentor Graphics VHDL Reference Manual July 1994 10 53 Attributes attribute declaration An
165. atement label index specification configuration item block configuration component configuration index specification discrete range static expression Description To make the internal structure of an architecture body visible for component binding any number of block configurations may appear within a configuration declaration Block configurations can be nested within other block configurations and within component configurations The top level block configuration immediately within the configuration declaration must apply to the architecture body of the design entity named by the configuration In other words a top level block configuration is required to open up the top level architecture body and it must name that architecture body in its block specification Within the top level block other block configurations and component configurations can be nested as shown in the following example Mentor Graphics VHDL Reference Manual July 1994 8 39 Design Entities and Configurations CONFIGURATION verl OF processor IS FOR struct The architecture FOR alu A block within the architecture FOR ALL adder USE A component configuration ENTITY work fal6 struct FOR struct This block config opens struct FOR ALL ha USE ENTITY work hal bhv END FOR END FOR This component configuration nests another config FOR amux
166. ation result is not a physical type in the range specified an error occurs For example PROCESS sens sig TYPE sys unit IS RANGE 0 TO 1000 UNITS Ls base unit declaration tv 10 tu secondary unit declaration tz 20 tv secondary unit declaration END UNITS VARIABLE s sys unit Declare variable of type sys unit BEGIN 5 1000 tu 2000 tv Using physical type sys unit do an arithmetic operation END PROCESS In the previous example the arithmetic operation s 1000 tu 2000 tv results in a value that is not in the specified range for sys unit The result of any expression that uses a physical type is truncated to the nearest base unit Mentor Graphics VHDL Reference Manual July 1994 Types Predefined Physical Types S There is one predefined physical type time You must specify all delays with the type time The type time is specified in package standard as follows TYPE time IS RANGI UNITS fs ps 1000 fs ns 1000 ps us 1000 ns ms 1000 us sec 1000 ms min 60 sec hr 60 min END UNITS 5 18 E a number TO a_number a number is machine dependent femtoseconds picoseconds nanoseconds microseconds milliseconds seconds minutes hours Mentor Graphics VHDL Reference Manual July 1994 Types
167. atrix 3 The element in the position of the array my matrix designated by the index value 3 d matrix 2 3 The element in the position of the two dimensional array 2d matrix designated by the index 2 3 zi ll WAIT FOR 10 ns ND PROCESS tz You must use a corresponding number of expressions for the dimension of the array In the preceding example if you designate an element of matrix you need two expressions for example 2 3 If you use one expression for example 3 an error occurs because another dimension is needed to locate the array element 3 8 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility Slice Names A slice name designates a one dimensional array that is created from a consecutive portion of another one dimensional array A slice of a design item equates to a new design item of the same type The following diagram shows the syntax for a slice name slice name prefix discrete range The following example shows the concept of using a slice name PROCESS sens signal TYPE ref array IS ARRAY positive RANGE OF integer VARIABLE array a ref array 1 TO 12 declare array a VARIABLE array b ref array 1 TO 4 declare array b BEGIN FOR i IN 1 TO 12 LOOP Load array with values array a i i 10 7 11 through 22 END L
168. attribute declaration defines a user defined attribute Attribute declarations are not allowed for predefined attributes Construct Placement declaration package declarative item process declarative item subprogram declarative item Syntax attribute declaration attribute identifier type mark Definitions B identifier This is the simple name of the attribute B type mark Denotes a subtype that is neither an access type nor a file type The subtype does not need to be constrained Description lt 0 0 Before a user defined attribute can be used in a VHDL description it has to be declared The declaration establishes the name of the attribute and the type of the attribute Once declared the attribute can be used through an attribute specification anywhere within the scope of the region in which it was declared Examples ATTRIBUTE technology STRING ATTRIBUTE part count NTEGER TYPE capacitance IS RANGE 0 0 TO 1 0E 6 ATTRIBUTE output cap capacitance TYPE coordinates IS RECORD Xvalue Yvalue integer type declaration END RECORD ATTRIBUTE component location coordinates attribute decl 10 54 Mentor Graphics VHDL Reference Manual July 1994 Attributes attribute specification An attribute specification associates a user defined attribute with one or more members of an
169. attribute value is FALSE If the result is TRUE the code contains a behavioral description Example The following example shows a block within an architecture ARCHITECTURE sig test OF test IS SIGNAL tester wired or bit vector BUS signal decl SIGNAL a b c bit BEGIN sig assign block label BLOCK tester 1 guard expression SIGNAL z bit vector block declarative item DISCONNECT tester bit vector AFTER 10 ns BEGIN 2 lt GUARDED a z gets a if test 71 END BLOCK sig assign END sig test The following example shows the use of the predefined attribute behavior in relation to the preceding example sig assign behavior The value that returns from the preceding code is TRUE because the block sig assign does not contain a component instantiation statement Mentor Graphics VHDL Reference Manual July 1994 10 25 Attributes structure Kind Value Prefix Any block designated by the corresponding block label or design entity designated by the corresponding architecture name Result Type Boolean Evaluation Result The result of evaluating the attribute is TRUE if the specified block specified by the block statement or design entity does not contain a signal assignment statement or concurrent statement that cont
170. ave a specified type or the same type as another expression or name O Rules requiring the type of expressions or names to be of a specified type class O Rules requiring a specified type to be one of the following B Boolean B Character B Discrete Integer B Physical m Real B Universal 3 24 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility O Rules requiring an appropriate prefix for a specified type O Rules requiring the type of an aggregate to be determined from context only O Rules requiring the type of the attribute prefix of the expression in a case statement or of the operand of a type conversion being determined independent of context O Rules for resolution of subprogram calls that are overloaded or for implicit universal expression conversion O Rules for interpreting discrete ranges that have universal type bounds O Rules for interpreting an expanded name that has a prefix designating a subprogram The preceding rules are discussed in the appropriate sections of this manual To find the exact page location for the subject you wish to explore in detail refer to the index or table of contents The rules for each of these subjects are discussed in the context of the complete discussion about the item For information about overloading enumeration literals refer to page 5 19 about overloading subprograms refer to page 7 17 Mentor Graphics VHDL Reference Manual July 1994 3 25
171. binding indication Formal generic decl of specified entity decl Formal designator before gt in generic assoc list of a corresponding binding indication Formal port decl of specified entity decl Formal designator before gt in port assoc list of a corresponding binding indication Element of a record Suffix in selected name prefix denotes record Mentor Graphics VHDL Reference Manual July 1994 Figure 3 6 shows an example of hidden declarations and homographs 3 19 Naming Scope and Visibility ARCHITECTURE SIGNAL BEGIN VARIABLE x boolean PROCESS PROCEDURE b d aa VARIABLE x boolean E N BEGIN B gt C e A END A BEGIN END PROCESS E rn D END Figure 3 6 Declaration Hiding and Homographs In Figure 3 6 variable x is declared within the procedure in scope A and within the process in scope B The variable x declared in the process is hidden within scope A by the variable x declared in the procedure The variable in scope A is a homograph of the variable in scope B because the variables have the same identifier Figure 3 7 shows an example of hidden declarations and overloading that results in no homograph 3 20 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility
172. bject pointed to by the pointer TYPE buff elem type IS O TO 255 2 TYPE my buffer IS ARRAY 0 TO 3 OF buff elem type 3 TYPE buff ptr IS ACCESS my buffer 4 VARIABLE ptrl puff per NEW my b ffer 1 2 3 4 3 5 VARIABLE ptr2 buff ptr NEW my buffer 6 VARIABLE ptr3 buff ptr ptrl 7 VARIABLE vl buff elem type 2 14 Mentor Graphics VHDL Reference Manual July 1994 Expressions 8 ptr2 ALL pte AU 9 vl ptr1l ALL 0 10 deallocate ptrl The preceding example does the following e Line 1 declares a type buff elem type for elements of an array object that will be pointed to by an access type e Line 2 declares the type my buffer which is defined as a four element array with elements of type buff elem type e Line 3 declares an access type buff ptr of type my buffer This access type is now available for variables that will be used as designators of pointers to objects of type my buffer e Line 4 declares a variable ptr of access type buff ptr and uses an allocator expression the reserved word NEw followed by my buffer which does three things O Allocates enough memory to store an object of type my buffer O Creates and assigns a value to an unnamed array object of type my buffer In
173. blocks are defined within an architecture by using the block statement and external blocks are defined by other design entities For more information on block statements refer to page 6 12 The port modes are in read the signal out update the signal inout read and update the signal buffer read but update by at most one source and linkage read but update only by appearing as an actual of an interface object of mode linkage The interface declarations and the modes are discussed in detail beginning on page 4 21 If you associate a formal port with an actual port or signal the port is connected If you associate the formal port with the reserved word open the port is unconnected For more information about association refer to page 4 31 An input port mode is in cannot be left unconnected if there is no default expression to handle such a situation The default expression is discussed in detail on page 11 15 A port that has any other mode can be left unconnected if its type is not an unconstrained array 8 8 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Example The following examples show port declarations from separate entity headers PORT in pin IN bit vector 0 TO 3 out pin OUT bit vector 0 TO 3 PORT a line IN bit bus lines OUT bit vector 0 TO 7 chk bit INOUT bit Mentor Graphics VHDL Reference Manual July 1994 8 9 Desi
174. briefly describes the three kinds of description methods that you can use in an architecture e Structural Description describes a design as an arrangement of interconnected components e Behavioral Description describes a design s functional behavior using algorithms without describing the design structure e Data flow Description describes design in terms of the flow of information from one input to another input or output This method of description is similar to a register transfer language Using any combination of the three description methods you can describe a design in a complete or incomplete manner For detailed information on the three methods of design description refer to the Mentor Graphics Introduction to VHDL The architecture simple name defines the identifier for the architecture body This identifier allows you to distinguish between different architecture bodies written for a single entity declaration In the architecture body example the architecture name is data flow The entity name specifies the entity declaration to use with the architecture body The entity declaration you specify must be in the same library as the associated architecture body In the architecture body example the entity name is shifter If the design contains more than one architecture body the architecture bodies can have the same architecture simple name provided they are associated with different entity declarations This is tr
175. cal file which can have multiple file objects mapped to it However because it is impossible to predict the order in which concurrent processes will be executed during simulation you should be aware that Mentor Graphics VHDL Reference Manual July 1994 4 19 Declarations concurrent file operations could lead to unexpected results For example the following architecture body contains two concurrent processes that read the same file object In this case you never know the order in which the processes read from the file and because each read operation moves the pointer to the file data you cannot predict what data will be read by either of processes ARCHITECTURE behave OF controller IS FILE test rom d IS IN t BEGIN pro 1 PROCESS a b c BEGIN read test datal pro 2 PROCESS a b c BEGIN read test data2 A given file can be sequentially written to and read from in any combination with predictable results this facilitates modeling such devices as RAMs 4 20 Mentor Graphics VHDL Reference Manual July 1994 Declarations Interface Declarations An interface declaration declares an object that provides a channel for passing information between a portion of a design and its environment The interface objects can be constants variables or signals depending on their intended use as Figure 4 2 shows
176. cals 4 32 Locating language constructs B 1 Logical library name 9 8 Logical operators 2 31 Longest static prefix 3 5 Loop parameter 4 11 6 36 Loop statement 6 36 Major language construct tree B 1 Miscellaneous operators 2 18 Mode 4 22 File 4 19 Parameters 7 8 Ports 8 8 Side effect 7 3 Multiple object declaration 4 11 Multiplying operators 2 20 Name space 3 1 Name logical library 9 8 Named notation 7 13 Names Attribute names 3 10 Indexed names 3 8 Prefix 3 5 Selected names 3 4 Simple names 3 4 Slice names 3 9 Naming 3 3 NAND 2 31 Natural type declaration 5 11 9 20 Next statement 6 38 NOR 2 31 NOT 2 31 Null range 5 4 Null slice 3 10 Null statement 6 39 Index 3 Index INDEX continued Numeric literal 1 15 Objects Declaration of 4 10 Definition of 4 10 What an object is 4 11 Operands primaries 2 6 Operations on arrays 5 28 Operator and signal assignment similarity 6 25 Operator precedence 2 16 Operators 2 16 Operators important note to read 2 17 Operators overloading 7 18 OR 2 31 Ordering operators 2 30 Overload interpretation rules 3 24 Overloading Enumeration types 5 20 Operators 7 18 Rules for operator overloading 7 18 Subprograms 7 17 Package body 9 15 Package declaration 9 13 Package standard 9 18 Package std logic 1164 9 21 Package std logic 1164 ext 9 26 Package textio 9 30 Packages 9 12 Parameter type profi
177. can also specify the use of all of the declarations by using the reserved word all For example USE package 1l test funcl package l test func2 line 1 USE package 2 ALL line 2 Line 1 makes the functions test_func1 and test func2 from package 1 directly visible Line 2 makes all the top level declarations of package 2 visible For examples of use clauses in relation to libraries refer to page 9 5 There are two cases in which a declaration is not made directly visible by the use clause The use clause designates a place within the immediate scope of a homograph of a declaration Two declarations you wish to make visible have the same designator and are not a subprogram declaration or an enumeration literal specification Any declaration you make directly visible by a use clause does not hide a previous directly visible declaration in any situation This is assured by the rules of the use clause There is a situation you must be aware of when utilizing the use clause If you have a use clause in one model Model A for reference that references a package 3 22 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility that also contains a use clause the items that are made visible to the package are not made directly visible to the original model Model A For more information see the following example and Figure 3 8 Example Figure 3 8 shows an example of multiple use claus
178. cation e Optionally defines the signal to be a bus or register signal kind e Optionally defines a default expression for the signal The following examples show some possible signal declarations SIGNAL data in data out bit With identifier list and type mark SIGNAL add line wired or bit vector 1 TO 3 BUS With resolution function type mark and signal kind SIGNAL enable bit 0 With default expression The following list shows the rules that govern the signal declaration e You cannot declare a signal that is a file type When you specify the signal as being guarded by using the reserved words bus or register you must include a resolution function e If the signal has multiple sources it also must have a resolution function Default Expression The expression construct at the end of the signal declaration is the default value for the signal driver at initialization of the simulation and for the times when the signal is left unconnected The expression type you use for the default must be the same type as the signal For example SIGNAL enable my qsim state X Defaults to X state If you do not use a default statement the system assumes a default for the signal This implicit default is the left most value of the signal type determined by the value of the predefined signal attribute left The following example shows a signal type declaration
179. cation that uses either others or all for a given entity class must be not used again for that entity class within a given declarative region To supply a particular value that you want to associate with the designated entity class members you use the expression portion of the attribute specification User defined attributes must be constants The type of the expression must be the same as or must implicitly convert to the type specified in the corresponding attribute declaration The information supplied through a user defined attribute is local only and cannot be passed from one element of a description to another If you apply an attribute specification to a design unit entity declaration architecture body configuration package declaration or package body it must appear immediately within the declarative part of the design unit For other entity class members procedures types subtypes objects components and labels the attribute specification must appear within the declarative part where the individual members are declared Mentor Graphics VHDL Reference Manual July 1994 10 57 Signals Section 11 Signals This section discusses the subject of signals and how to use them A signal is an object that you can assign projected future values to and has a history and a time dimension The following ordered list shows the constructs and topics this section discusses Signal Concepts lt 11 4 Drivers 4 Gu
180. cations lines 66 through 70 follow 1 The design entity for an inverter is defined 2 ENTITY inv IS 3 GENERIC del time 4 PORT a IN bit na OUT bit 5 END inv 6 7 8 ARCHITECTURE not_a OF inv IS 9 BEGIN 10 na lt NOT a AFTER del 1 END not_a 12 13 Design entities for two versions of an AND gate 14 ENTITY and2 s IS 15 GENERIC del time 4 5ns 16 PORT a b IN bit c OUT bit 17 END and2_s 18 19 20 ARCHITECTURE behav_and2 OF and2_s IS 21 BEGIN 22 c lt a AND b AFTER del 23 END behav_and2 24 25 26 ENTITY and2 input IS 27 PORT d e IN bit OUT bit 28 END and2 input 29 30 31 ARCHITECTURE basic and2 OF and2 input IS 32 BEGIN 33 f lt d AND e AFTER 10 ns 34 END basic_and2 35 36 8 26 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations 37 ENTITY or2 input IS 38 PORT d e IN bit OUT bit 39 END or2 input 40 41 42 ARCHI
181. ccess value that points to nothing For information on access types refer to page 5 31 Numeric Literals A numeric literal represents an exact integer or real value Examples of numeric literals start on page 1 17 Here is the BNF description for a numeric literal numeric literal abstract literal physical literal Mentor Graphics VHDL Reference Manual July 1994 1 15 Lexical Elements A physical literal is used in a secondary unit declaration as part of a physical type definition For more information on physical type definitions refer to the subsection called physical type definition in Section 5 Here is the BNF description for a physical literal physical literal abstract literal unit name Abstract literals are either integer literals or real literals You specify integer literals and real literals either in decimal notation decimal literal or using another base based literal A real literal includes a decimal point and is of the type universal real An integer literal does not include a decimal point and is of the type universal integer For information about types refer to Section 5 The BNF description for an abstract literal is as follows abstract literal decimal literal based literal You can think of type universal integer as an anonymous type with no bounds representing all the integers in the universe Integer literals are members of this type Type universal real is also an anonymous
182. ce Manual July 1994 6 17 Statements The optional generic map aspect associates a single actual with each local generic in the component declaration Each of these local generics must be associated exactly once e The optional port map aspect associates a single actual with each local port in the component declaration Each of these local ports must be associated exactly once For information on the generic and port map aspect refer to page 8 32 Example The following example shows the declaration of three components and the instantiation of these components using component instantiation statements IN bit Y ENTITY mux IS PORT a0 al sel END mux ARCHITECTURE OUT bit structure descript OF mux IS COMPONENT and2 component declaration for and2 PORT a b IN bit z OUT bit local port clause END COMPONENT COMPONENT or2 component declaration for or2 PORT a b IN bit z OUT bit END COMPONENT COMPONENT inv component declaration for inv PORT i IN bit OUT bit END COMPONENT SIGNAL aa ab nsel bit signal declaration FOR U1 inv USE ENTITY WORK invrt behav configuration FOR U2 U3 and2 USE ENTITY WORK and gt dflw specif FOR U4 or2 USE ENTITY WORK or gt archl BEGIN Ul inv PORT MAP sel nsel
183. ch actual This association can be made in any order You make a positional association when you omit the gt delimiter The association between the formal and the actual is made by the position of the designators For example the first formal in the list is associated with the first actual in the list and so on The following example shows how to associate formal generics and ports to local and actual generics and ports The formals for this example are declared in the following entity declaration ENTITY gates IS GENERIC x time formal generic clause 4 32 Mentor Graphics VHDL Reference Manual July 1994 Declarations y real z real 5 0 PORT inl in2 IN bit formal port clause out3 OUT bit END gates Here is the declarative part of an architecture body named struct that uses design entity gates as a component ARCHITECTURE struct OF struct entity IS COMPONENT and2 component declaration GENERIC prop delay time temp real vcc real 5 0 PORT il i2 IN bit outl OUT bit END COMPONENT FOR ALL and2 USE ENTITY gates gates arch config spec GENERIC MAP 25 ns 27 0 4 7 association list PORT MAP inl gt il out3 gt outl in2 gt i2 assoc BEGIN list In this architecture body the formal
184. ciates 45 ns with the generic declared in the entity declaration decoder The port map aspect associates the signals a b c d and output with the signals specified in the entity declaration for decoder This entity declaration does not appear in the preceding example The following rules apply to generic and port map aspects Each local generic or port in the applicable configuration specification must be associated with at least one formal in an entity declaration e No formal can be associated with more than one actual An actual associated with a formal port in the port map aspect must be a signal and an actual associated with a formal generic in a generic map aspect must be an expression There are more specific rules for associating formal ports with actual ports in relation to which formal ports with a given mode can be associated with actual 8 32 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations ports of a given mode Table 8 1 shows the appropriate modes for associating formal ports with actual ports Table 8 1 Port Association Rules Formal Port Mode Actual Port Mode in in inout or buffer out out inout inout inout buffer buffer linkage any mode Default Binding Indication S There are certain cases in which a default binding indication is applied when you do not use an explicit binding indication in the configuration specification The
185. cifies is active while in the current simulation cycle the return result for a scalar signal is a value of TRUE If any scalar subelement specified by the prefix is active the return result for a composite signal is a value of TRUE If the preceding conditions are not met the return value is FALSE Example lt For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 Mentor Graphics VHDL Reference Manual July 1994 10 29 Attributes delayed t Kind Signal Prefix gt Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Parameter 1 1 1 11 A static expression of type time Type time is a predefined physical type refer to Section 5 from package standard refer to page 9 18 The static expression cannot be negative If you do not specify the parameter t it defaults to O ns Result Type The result type corresponds to the base type of the specified prefix Evaluation Result h 5 5h The result is a new signal that is the prefix signal delayed by the period of time specified by the parameter t If the default value of 0 ns is specified as the parameter the following expression is not the same for one simulation cycle only if the signal has just changed If the signal has not just changed then signal name delayed 0 ns signal name where
186. ckage declaration Secondary units 9 2 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages O Architecture body O Package body A library unit that contains a context clause is called a design unit One or more design units make up a design file The design units in a design file are analyzed in the order in which they appear in the file The following BNF descriptions show the syntax for the design unit and related constructs design file design unit design unit design unit context clause library unit library unit primary unit secondary unit primary unit secondary unit entity declaration architecture body configuration declaration package body package declaration The following example shows one design unit within a partial design file LIBRARY my lib context clause ENTITY and2 IS library unit primary unit GENERIC prop delay time PORT inl in2 IN bit outl OUT bit BEGIN END and2 ARCHITECTURE alt arc OF and2 IS lib unit secondary unit alt arc tz UO Mentor Graphics VHDL Reference Manual July 1994 9 3 Design Units and Packages The following items apply to the design unit The primary unit name is the identifier that follows the reserved word entity package or configuration in an entity package or config
187. ction in VHDL the design entity and it describes how components are bound together to make a complete design VHDL stands for VHSIC Very High Speed Integrated Circuit Hardware Description Language Mentor Graphics VHDL Reference Manual July 1994 XV About This Manual e Section 9 Design Units and Packages describes stand alone descriptions that you can place into a library and storage facilities for collecting commonly used declarations and subprograms Section 10 Attributes describes the items you use to create your own attributes and describes the predefined attributes e Section 11 Signals describes the items you use to communicate between design entities Appendix A Syntax Summary shows every language construct in the form of syntax diagrams arranged in alphabetical order Each diagram has a reference to the appropriate page in this manual to refer to for more information Appendix B Locating Language Constructs shows how to quickly locate where you can use particular VHDL language constructs Using This Manual This manual presents the VHDL language in a reference format Each major topic of VHDL is contained in its own section allowing you look up the topics at random Throughout the manual there are references to other locations where you can find more detailed information on a particular topic This manual documents the language defined in IEEE Std 1076 1987 IEEE Standard VHDL Language
188. ctor FUNCTION XOR l r bit vector RETURN bit vector Define addition and subtraction for bit vectors left is the most significant bit and right is the least significant bit The result is the size of the larger operand Bit vectors are treated as unsigned integers FUNCTION l r bit vector RETURN bit vector FUNCTION l r bit vector RETURN bit vector mod rem and are defined to be convert the entry to a natural universal integer perform the operation and truncate it to the size of the resultant array FUNCTION x l r bit vector RETURN bit vector FUNCTION l r bit vector RETURN bit vector FUNCTION MOD 1 r bit vector RETURN bit vector NOTE Since the operands are treated as unsigned integers m REM returns the same result as MOD FUNCTION REM 1 r bit vector RETURN bit vector FUNCTION xx l r bit vector RETURN bit vector Al E The operators unary unary and abs are not defined tz ND qsim logic 9 46 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages mgc portable qsim relations S In this package the lt gt etc operators are defined for type qsim state to deal effectively an reasonably with unknown sta
189. ctor IS ARRAY 1 TO 10 1 TO 15 OF integer color val 2 Returns the value of element in position 2 of the type color which is blue positions start at zero vector right 1 returns right bound of the specified index 1 in the array vector which is 10 10 4 Mentor Graphics VHDL Reference Manual July 1994 Attributes Predefined Attributes Predefined attributes are a means of determining types ranges and values that relate to design items For example you can examine array bounds or determine whether a certain condition is true or false You can use some attributes as subprogram parameters For information on this topic refer to page 7 8 Each predefined attribute relates to only one valid object kind This object kind corresponds to the prefix you use before the attribute designator Each predefined attribute falls into one of the four object kind categories array objects blocks signals scalar or composite and types scalar composite or file For example if you want information about a signal you use a signal attribute or if you want information about an array you use an array object attribute It would not be logical for instance to determine if an integer scalar type was stable at a certain time because only signals can be stable Table 10 1 lists each predefined attribute name and the related object kind The object kind should not be confused with
190. d You typically use inertial delay to model real physical behavior where a rise or fall time of the output is equivalent to the delay time The output begins to react to the input change However the new value is not recognized until after the delay time Mentor Graphics VHDL Reference Manual July 1994 11 19 Signals The following example shows two signal assignments one with transport delay the other with the default inertial delay Figure 11 4 shows the difference between the two waveforms a tran lt TRANSPORT wave AFTER 10 ns a iner wave AFTER 10 ns wave 0 5 10 15 20 25 30 35 40 45 50 time ns Figure 11 4 Inertial and Transport Delay In the preceding example the 5 ns pulse circled area on wave is assigned to the signal tran which has transport delay The 5 ns pulse on wave is not assigned to a iner because this signal has inertial delay which means any pulse width smaller than 10 ns is not assigned to a_iner Delta Delay Another delay concept that is important to understand is the concept of delta delay Delta delay is an infinitesimal value of time that is greater than zero You can think of delta delay as one simulation iteration The concept of delta delay is necessary when you make a signal assignment with no delay expression For example pure delay lt a b 11 20 Mentor Graphics VHDL Reference Manual July 1994 Signals
191. d RETURN st END funcl BEGIN The function is called and s is S funcl z assigned the result of function call WAIT FOR 10 ns in this case 2 END PROCESS The function name specifies the name of the function you wish to execute In the preceding example the function name is funcl The optional actual parameter part specifies the actual parameters that are associated with the formal parameters of the function In the preceding example the z in the function call s funci z is the actual parameter part and st is the formal part in the function declaration FUNCTION funcl st state For the details and rules pertaining to function calls functions and parameter passing refer to Section 7 Qualified Expressions A qualified expression is an expression you use to explicitly describe the type or subtype using the type mark of an operand that is an aggregate or an expression The following diagram shows the syntax for a qualified expression qualified expression type mark 7 expression type mark 7 aggregate Qualified expressions do not perform type conversions For more information on type conversions refer to page 2 12 Qualified expressions give you the ability to eliminate the ambiguity that occurs when you overload operators functions and operands For example assume that a package my qsim base is 2 10 Mentor Graphics VHDL Reference Manual July 1994 Expressions
192. d NEW followed by buff which does three things Allocates enough memory to store an object of type buff O Creates and assigns a value to an unnamed object of type buff In this case an initial value of 511 is assigned to the object Assigns an access value address to ptr1 which can then be used to reference the object You can also initialize a pointer variable to a value of null without using an allocator expression as shown in the following example In this case the pointer points to no object VARIABLE ptrl buff ptr NULL The use of allocators is discussed in more detail in Section 2 of this manual under Allocators beginning on page 2 13 The following subsection discusses incomplete type declarations and their use with access types in creating self referencing structures such as linked lists Incomplete Types An incomplete type declaration names a type without specifying anything else about the type You can use this kind of type declaration with access types to create interdependent self referencing structures such as linked lists The following restrictions apply to incomplete type declarations Each incomplete type declaration must have a corresponding full type declaration with the same identifier e The corresponding full type declaration must occur within the same declarative part as the incomplete type declaration Between the incomplete type declaratio
193. ddition and subtraction the size of the larger operand The size of the result for is the sum of the lengths of the two operands If any X s or Z s are present in either operand the complete result is all X s FUNCTION l r qsim state vector RETURN qsim state vector FUNCTION 1 r qsim state vector RETURN qsim state vector FUNCTION MOD 1 r qsim state vector RETURN qsim state vector NOTE Since the operands are treated as unsigned integers REM returns the same result as MOD UNCTION REM 1 r qsim state vector RETURN qsim state vector FUNCTION 1 r qsim state vector RETURN qsim state vector The operators unary and abs are not defined amp has the normal meaning Mentor Graphics VHDL Reference Manual July 1994 9 45 Design Units and Packages Define logic operators on bit vectors These differ from the standard in that they accept vectors of different lengths FUNCTION AND dc E bit vector RETURN bit vector FUNCTION OR CL bit vector RETURN bit vector FUNCTION NAND 1 r bit vector RETURN bit vector FUNCTION NOR IL cx bit vector RETURN bit ve
194. dering Operators As Table 2 6 shows the ordering operators are predefined for any scalar or discrete array type A discrete array type is a one dimensional array that contains elements that are of enumeration or integer types Each ordering operator returns a value of TRUE if the specified relation is satisfied Otherwise a value of FALSE is returned Scalar type ordering operations are defined by the left and right operand relative values For discrete array types the relational operator less than means that the left operand is less than the right operand if the following conditions are satisfied e The left operand is a null array and the right operand is not a null array e The left and right operands are not null arrays If they are not null arrays one of the following conditions must be met O The left most element of the left operand is less than the left most element of the right operand O The left most element of the left operand is equal to the left most element of the right operand and the tail of the left operand is less than the tail of the right operand The tail of an operand is the remaining elements to the right of the left most element The tail can be null The relational operator less than or equal to lt for discrete array types is true if either or is true for the left and right operands you specify 2 30 Mentor Graphics VHDL Reference Manual July 1994 Expressions Using the def
195. e gt 5 0 0 49 o0 The following example shows the definition of address range TYPE address range IS RANGE 1 TO 32 The following code returns the value 32 which is the right bound of address range address range right Mentor Graphics VHDL Reference Manual July 1994 10 49 Attributes rightof x Kind Function Prefix Any enumeration integer physical type or subtype Parameter The value for the parameter x must be of the same base as the specified prefix Result Type The result type corresponds to the base type of the specified prefix Evaluation Result 0 5 The evaluation result is the value that is to the right of the specified parameter Example The following code defines color TYPE color IS red yellow green flash The following code returns the value flash which is the value at the position to the right of the position specified by the parameter green color rightof green Restrictions 1 1 1 0 0 0 0 0 0 The specified parameter x cannot be equal to the right bound of the base type An error occurs if you try to examine an item to the right of the right most item 10 50 Mentor Graphics VHDL Reference Manual July 1994 Attributes succ x Kind Function Prefix Any enumeration integer physical type or subtype Parameter The va
196. e Left most value Using a range constraint allows you to specify the range of a certain type only once in your code description and then use this range elsewhere in your code without explicitly specifying it The following example shows a type and subtype declaration with range constraints followed by a variable and a type declaration that could exist later in a description TYPE my array IS ARRAY positive RANGE lt gt OF integer unconst array decl SUBTYPE ar ran IS positive RANGE 1 TO 255 Type decl with range const VARIABLE hold my array ar ran Use ar ran as the range constraint TYPE x IS ARRAY ar ran OF integer Use ar ran as the 5 6 Mentor Graphics VHDL Reference Manual July 1994 Types range constraint The preceding example illustrates a fundamental coding practice you should try to follow avoid hard coding values that you use many times in a description Having to change just one value is much more desirable than having to change several hard coded values in a description For more information on coding guidelines refer to the Mentor Graphics Introduction to VHDL If you use a range constraint in a subtype indication the simple expression type in the language construct range must match the type you specify in the subtype indication For more information on subtype indications refer to page 4 7 Figure 5 2 illustra
197. e information on signals and drivers refer to Section 11 The target is the signal to which you wish to assign the value of the expression that follows the lt delimiter The lt delimiter differentiates a signal assignment from a variable assignment and can be thought of as the word gets Therefore the signal assignment statement reads as follows The signal gets a value of the waveform specified by a waveform element Do not confuse the lt with the relational operator lt meaning less than or equal to You can specify a comma separated series of waveform elements If you do so the sequence of the elements must be in be in ascending time order 6 46 Mentor Graphics VHDL Reference Manual July 1994 Statements You can use the reserved word transport to specify that the delay associated with the first waveform element is a transport delay Transport delay causes any pulse to be transmitted to the signal name you specify no matter how short the duration In other words transport delay exhibits a frequency response that is characteristic of transmission lines thus it can be used to model interconnect or wire delays If you do not use the reserved word transport the default for the first waveform element is inertial delay All subsequent elements are considered to have transport delay Inertial delay applied to a waveform element prevents pulses with a width shorter than the delay time you specify from being tra
198. e left operand In the sens sig2 process the left bound of the index subtype of the left operand vector is 5 The elements of the resulting array consist of the elements of the left operand followed by the elements of the right operand Had the concatenation in the sens sig2 process placed the single element as the left operand as shown below the same rules would apply next array 3 amp vector Concatenate 3 with vector The single element 3 is viewed as an implied one dimensional array with one element The resultant array created by the concatenation of an array element with a one dimensional array has the range and direction of the index subtype of the left operand In this case the resultant array from the concatenation starts with an index of 1 and has a range of 1 to 6 The following paragraphs include a description of how a single element is treated as an implied array 3 Following is an example of concatenation in which both operands are of the same type as an array element type PROCESS sens sig3 TYPE ref array IS ARRAY positive RANGE OF integer VARIABLE x z integer VARIABLE element array ref array 6 TO 7 BEGIN x 3 Z ups element array END PROCESS x z Concatenate to form 2 elem array The concatenation operation and the value of e1ement array from the preceding sens sig3 process is equivalent to the
199. e CAD C8 alias_declaration__z________A 12______ 4 35 allocator AA 214 architecture_body_____________A 13______ 8 14 architecture declarative A 13______ 8 17 architecture statement part A 13 J J 8 18 array type definition 1 A 13 J 523 Mentor Graphics VHDL Reference Manual July 1994 A 1 Syntax Summary Table A 1 VHDL Construct Listing continued assertion statement association element association list attribute declaration attribute designator attribute name attribute specification base base specifier base unit declaration based integer based literal binding indication bit string literal bit value block configuration block declarative item block declarative part block header block specification block statement block statement part case statement case statement alternative choice choices component configuration component declaration component instantiation statement component specification Location of Syntax For More Diagram Information A 14 6 10 A 14 4 31 A 14 4 31 A 14 10 54 A 14 10 3 A 15 10 3 A 15 10 55 A 15 1 17 A 15 1 20 A 16 5 15 A 16 1 17 A 16 1 17 A 16 8 20 A 16 1 20 A 17 1 20 A 17 8 39 A 18 8 17 A 19 6 12 A 19 6 12 A 19 8 39 A 20 6 12 A 20 6 13 A 20 6 15 A 21 6 15 A 21 2 8 A 21 2 8 A 21 8 43 A 22 4 36 A 22 6 17 A 22 8 25 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary Table A 1 V
200. e Manual this manual contains reference information for the language and related packages e Mentor Graphics Introduction to VHDL contains fundamental VHDL concepts The following manuals pertain to Explorer VHDLsim users e Explorer VHDLsim Quick Reference Booklet provides reference information for Explorer VHDLsim in a quick lookp format e Explorer VHDLsim User s and Reference Manual contains task oriented operating instructions for Explorer VHDLsim covering such topics as compiling and simulating VHDL models in the Explorer VHDLsim environment Explorer Lsim User s Manual describes and explains how to use the Explorer Lsim Mixed Signal Multi Level Simulator Since VHDLsim is an integral part of the Lsim simulation environment you will need to refer to this manual while using Explorer VHDLsim Explorer Lsim Reference Manual describes Explorer Lsim Simulator commands menus and programs e M Language User s Guide describes how to use the M hardware description language The following manuals pertain to System 1076 users e Getting Started with System 1076 contains information about creating modeling and debugging hardware designs with Mentor Graphics Xx Mentor Graphics VHDL Reference Manual July 1994 About This Manual System 1076 System 1076 allows system and component designers to create language models of their systems or chips System 1076 is based on IEEE Std 1076 1987 IEEE Standard VHDL Language Refere
201. e Object Concept Association List Concept Types Range Constraints in Subtype Indications Unconstrained Arrays Statements Subprograms Memory Programmer and Tester Block Diagram Design Entities Components Design Units and Packages Context Clause Concept Input Buffer Schematic Package Concept 10 1 Array Direction Signal Attribute Concept Example of All The Signal Attributes Signals Composition of a Signal Resolution Function Concept Inertial and Transport Delay Zero Delay Gates Comparing Traces Unit delay Modeling Attributes NN 10 2 10 10 10 28 10 39 11 2 11 3 11 11 11 20 11 22 11 22 11 23 Mentor Graphics VHDL Reference Manual July 1994 Table of Contents LIST OF FIGURES continued A 1 Example Syntax Diagram A AS A 2 Multiple Syntax Diagram Paths A 10 Mentor Graphics VHDL Reference Manual July 1994 xiii Table of Contents C9 P2 P2 02 PEE LIST OF TABLES Replacement Characters VHDL Reserved Words Type Conversions Operators by Precedence Miscellaneous Operators Multiplying Operators Adding Operators VHDL Relational Operators Local Static Operands Global Static Operands Universal Expression Operators Immediate Scope Exceptions Visibility by Selection Objects System 1076 Statements Comparison of Functions and Procedures Subpro
202. e concept of delta delay Figure 11 5 shows three AND gates cascaded together The AND gates are modeled with O ns delay The input signal in 1 goes high at the simulation timestep of 25 ns Input signals in 2 in 3 and in 4 are all high and have been since the last timestep Mentor Graphics VHDL Reference Manual July 1994 11 21 Signals eem ied cec gt N a gt Mn F a mi A b lt lt INS N in4 Figure 11 5 Zero Delay Gates When you trace the signal in the simulator you see the output signals a b and c all change to a high state at 25 ns However if you could trace what the simulator actually sees you would see each of the output signals scheduled one delta delay or iteration apart Figure 11 6 shows the trace you see at the left and it shows the trace the simulator sees at the right 25 ns 1 iteration 25 ns 2 iterations 1 31 7 25ns 3 iterations a b C 55g tp eese p i LT pr tr Y 25 7 time ns Figure 11 6 Comparing Traces The delta delay model allows you to model event sequences without taking into consideration when the events occur This concept is called unit delay modeling Each delta delay is an equivalent amount of time However you should keep in mind that when you model with signal assignments using the O ns default there 11 22 Mentor Graph
203. e construct discussion in the Mentor Graphics Introduction to VHDL The majority of the language constructs in this tree are declarations NOTE BA The diagrams on pages B 3 and B 4 consolidate the Construct Placement information that appears on the Mentor Graphics VHDL Summary poster Ifyou are reading this document online you should print out pages B 3 and B 4 to make the diagrams easier to view When you are interested in language constructs that do not appear in the major language construct tree you can use the vscan script This script allows you to perform an on line search of the VHDL syntax for any language construct or reserved word For System 1076 users the vscan script can be called from within the Design Architect VHDL Editor with the Help gt On VHDL gt Syntax menu choice or it can be found in the following directory MGC HOME shared pkgs sys 1076 manual For more information on the VHDL Syntax Viewer in the VHDL Editor refer to Finding VHDL Syntax Information Within the Editor in the System 1076 Design and Model Development Manual Mentor Graphics VHDL Reference Manual July 1994 B 1 Locating Language Constructs For Explorer VHDLsim users the vscan script resides in the following directory SCSDIR ind bin SSCSDIR is set to the location where the Explorer tools are installed The following examples show how to use the vscan script MGC HOME shared pkgs sys 107
204. e elapsed time value since the signal specified by the prefix was active For composite signals the value that returns is the last time any element in the composite was active Example 3L lt 0 For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 10 32 Mentor Graphics VHDL Reference Manual July 1994 Attributes last event Kind Function Prefix KK KE Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Result Type lt The result type is type time which is a predefined physical type refer to Section 5 from package standard refer to page 9 18 Evaluation Result D 0 3 Because an event occurred on the signal specified by the prefix the result is the elapsed time value For composite signals the value that returns is the last time any element in the composite had an event Example h Dh 2 5 0 0 0 2 For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 Mentor Graphics VHDL Reference Manual July 1994 10 33 Attributes last value Kind Function Prefix KK KE Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Result Type The result type corresponds to the base ty
205. e expression is not allowed in a procedure body The expression type must be the same as the base type specified in the type mark after the word return in the function specification When a return statement is encountered in a subprogram execution returns to the calling code that is it exits the subprogram To avoid an error condition you should do the following Supply a return statement for every function Make sure the expression value type is the same as the base type given by the type mark after the reserved word return in the corresponding function specification 6 44 Mentor Graphics VHDL Reference Manual July 1994 Statements Example The following examples show the return statement in a function and in a procedure example of a return statement FUNCTION chk pty CONSTANT op code conc RETURN boolean IS VARIABLE suml sum2 boolean false FOR i IN 0 TO 23 LOOP in a function CONSTANT ram_data_conc IN bit_vector 0 TO 23 IN bit_vector 0 TO 23 IF ram_data_conc i 17 THEN suml NOT suml Compute parity for ram data END IF IF op_code_conc i 1 THEN sum2 NOT sum2 Compute parity for op code data END IF END LOOP RETURN suml sum2 Return true if suml sum2 END chk_pty false if not example o
206. e following code COMPONENT inv PORT inp IN bit err otp OUT bit TAB iyo otp END COMPONENT i 1 inp em N COMPONENT and2 and2 otp PORT inp inp 2 IN bit inp 2 Y otp OUT bit END COMPONENT inp inp 2 otp are local ports The figure at the right illustrates the actual ports of the following code a SIGNAL ne bit Ul inv PORT MAP en ne l m U2 and2 PORT MAP ne b z CREE unes K ne en ne b z are actual ports an ul o PR je u2 b The local ports in a component declaration are connected to actual ports by using a port map in a component instantiation statement The connection between local ports and the formal ports in an external design entity is made in a configuration specification or configuration declaration The configuration specification and related topics are discussed in the following subsections 8 24 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations configuration specification S The configuration specification binds one or more component instances to the desired entity declaration by using a binding indication Construct Placement block declarative item Syntax configuration specification for component specification use binding indication component specification instantiation list component name instantiation list instantiation label
207. e formal generic or port in the entity declaration does not exist The mode and type of the formal generic or port are not legal for the association for the local generic or port For more information on the concept of association refer to page 4 31 Configurations The preceding section discusses the concept of binding components to design entities using configuration specifications It is often more useful to gather all the component bindings for a design entity into a single library unit The design configuration provides the means to do this Using design configurations different implementations of a design using entirely different component bindings may be evaluated without having to modify and reanalyze the design itself The most important constructs that make up a design configuration are the following e Configuration declaration defines and encloses the configuration e Block configurations develop structure within the configuration Any number of block configurations may be used e Component configurations in addition to developing structure supply component bindings within the configuration Together these constructs open up the hierarchy of a design make the internal components of the design visible and bind the components instantiated in the design to other design entities The configuration declaration block configuration and component configuration are discussed in detail in the following three subsections 8
208. e in the driver for a signal You can think of a driver as a container for the projected output waveform that the system creates The value of a signal is related to the current values of its drivers The following example shows a signal assignment statement and is followed by an illustration showing how the driver determines the value of the signal enable lt 0 1 AFTER 5 ns 0 AFTER 10ns 1 AFTER 20 ns A Driver for enable signal value p 0 5 10 15 20 time ns A driver contains the projected output waveform for the signal The projected output waveform contains at least one transaction A transaction is a signal value 11 4 Mentor Graphics VHDL Reference Manual July 1994 Signals and time for the transaction to occur The transactions from the previous example consist of the following pairs of items Value Time 0 Ons on 5 ns 0 10 ns 1 20 ns A signal can have multiple drivers or sources In this case a resolution function is required to resolve the effective value of the signal that has two or more drivers contributing to the signal For more information about resolution functions refer to page 11 10 Guarded Signals A signal guard allows you to control the assigning of signal values The guard is a Boolean expression that assigns the drivers of the guarded signal a null transaction which turns the driver off when the value of the expression is FALSE If the value of
209. e lights passive process statement PROCESS sensor VARIABLE sensor check character BEGIN IF sensor 0 THEN sensor check f END IF END PROCESS update lights END controller Mentor Graphics VHDL Reference Manual July 1994 8 13 Design Entities and Configurations architecture body An architecture body describes how the inputs and outputs of a design entity relate to one another In other words the architecture body specifies what the design entity does You can express an architecture in terms of structural behavioral or data flow descriptions Construct Placement secondary unit Syntax architecture body architecture architecture simple name of entity name is architecture declarative part begin architecture statement part end architecture simple name Definitions B architecture simple name Defines the identifier for the architecture body B entity name Specifies the entity declaration to use with the architecture body B architecture declarative part Contains declarations of items that are used in a block that is defined by a design entity architecture statement part Contains concurrent statements that describe the operation and the relationship between the inputs and outputs in the block defined by the design entity 8 14 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Description The following list
210. e operator were applied individually to each operand pair The relational operator rules for arrays apply for qsim_state_vectors qsim_state_vectors are treated as unsigned integers in all arithmetic operations If either operand contains X or Z an attempt is made to compute an answer as optimistically as possible In some cases a partial result will be produced Otherwise the result will be X or an array of X s bitwise operations FUNCTION AND 1 r qsim state vector RETURN qsim state vector FUNCTION OR 1 r qsim state vector RETURN qsim state vector FUNCTION NAND l r qsim state vector RETURN qsim state vector FUNCTION NOR 1 r qsim state vector RETURN qsim state vector FUNCTION XOR 1 r qsim state vector RETURN qsim state vector FUNCTION NOT 1 qsim state vector RETURN qsim state vector For these relational operators an algorithm is employed to provide the most optimistic answer possible in the case where X s are present For example the result of 011 gt 0X1 is 1 In effect a comparison is done with the X replaced with a 0 and then repeated with the X replaced with a 1 If the results of both comparisons are the same then that result is returned If the results don t match an X is returned FUNCTION lt FUNCTION gt
211. e or more actions to take place in a hardware description These actions can take place one after another sequentially or at the same time concurrently The following list shows the topics and constructs explained in this section Statement Classes 62 sequential statement 1 1 1 6 5 concurrent_statement____ 7 Statement Quick Reference 68 assertion statement J 6 10 block statement 1 6 12 case statement 1 1 1 6 5 component instantiation statement 6 17 concurrenf assertion statement 6 19 concurrent procedure call 6021 concurrent signal assignment stmnt 6 23 conditional signal assignment 1 1 1 6 25 selected signal assignment 8 27 exit statement 1 1 1 6 28 generate statement 6 230 if statement 1 1 1 6 34 loop statement 636 Mentor Graphics VHDL Reference Manual July 1994 6 1 Statements next statement 1 1 1 1 638 nul statement 6 39 procedure call statement 6 40 process statement 64l return statement 1 1 6 44 signal assignment statement lt lt 6 46 variable assignment statement 6 48 wait statement 649 Statemen
212. e reserved word all FOR ALL or2 USE ENTITY or2 input or2_behav In this example all the component instances named or2 are bound to the design entity or2 input and the architecture or2 behav 8 28 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations binding indication The binding indication associates binds one or more component instances to an external entity declaration and it optionally maps the ports and generics of those instances to ports and generics of the entity declaration Construct Placement configuration specification Syntax binding indication entity aspect generic map aspect port map aspect Definitions entity aspect Binds a component instance to the entity declaration and entity architecture you specify B generic map aspect Associates a value with the formal generic declared in the entity declaration port map aspect Associates signals with the formal ports declared in the entity declaration Description lt 0 0 0 For more information on the association of local ports and generics in component declarations with formal ports and generics in entity declarations refer to page 4 31 If you do not specify a generic or port map aspect a default binding indication is used For more information on the default binding indication refer to page 8 33 Mentor Graphics VHDL Reference Manual July 1994 8 29 Design Entitie
213. eclaration signal declaration file declaration alias declaration component declaration attribute declaration configuration specification attribute specification disconnection specification use clause Example The following example shows a possible architecture declarative part ARCHITECTURE declare part OF declared entity IS USE parity ALL use clause TYPE code IS ARRAY integer RAN SUBTYPE bcode IS code 0 TO 1 CONSTANT even check string CONSTANT odd check string SIGNAL x y bit BEGIN END declare part Mentor Graphics VHDL Reference Manual July 1994 subtype gt 10000010 00000001 GE lt gt OF integer Type decl declaration constant declarations signal decl Design Entities and Configurations architecture statement part The architecture statement part contains concurrent statements that describe the operation and the relationship between the inputs and outputs in the block defined by the design entity Construct Placement architecture body Syntax architecture statement part concurrent statement Description Concurrent statements execute asynchronously with respect to one another For more information on concurrent statements refer to page 6 7 8 18 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Example
214. eclarations that are used within the block Block declarative items can also be declared in the architecture declarative part and are discussed in that subsection on page 8 17 The block statement part contains zero or more concurrent statements Example The following example shows the possible use of a block statement ARCHITECTURE data flow OF test IS SIGNAL clk a b c bit BEGIN sig assign block label BLOCK clk 1 guard expression SIGNAL z bit bplock declarative item BEGIN z lt GUARDED a z gets a if clk END BLOCK sig assign END data flow 6 14 Mentor Graphics VHDL Reference Manual July 1994 Statements case statement The case statement selects one or more sets of sequential statements for execution depending on on the result of an expression Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax case statement case expression is case statement alternative case statement alternative end case case statement alternative when choices gt sequence of statements sequence of statements sequential statement Description The following list shows the rules for using the case statement The expression must be an integer enumeration or one dimensional character array type
215. eclarative item subprogram declaration gt subprogram_body type declaration gt subtype declaration J constant declaration variable declaration file declaration alias declaration gt attribute declaration attribute specification TERES use clause gt 7 10 subprogram declarative part y subprogram declarative item Luc 7 10 Mentor Graphics VHDL Reference Manual July 1994 A 63 Syntax Summary subprogram specification procedure identifier ATN eid formal parameter list NOU No cf lt y gt function designator formal parameter list gt n 6 return gt type mark gt 7 6 l subprogram statement part sequential statement A x 7 10 subtype declaration subtype identifier 15 Rm d NA gt subtype indication gt gt 4 7 l subtype indication resolution function name type_mark n gt constraint 7 4
216. eclarative part process declarative item process declarative item subprogram declaration subprogram body type declaration subtype declaration constant declaration variable declaration file declaration alias declaration configuration declaration attribute specification use clause process statement part sequential statement Mentor Graphics VHDL Reference Manual July 1994 6 41 Statements Definitions B process declarative part Contains declarations that are local to the process Signal declarations are not allowed in this part process statement part Contains one or more sequential statements B sensitivity list Defines a list of signals that cause the process to execute when they change Description The sensitivity list defines a list of signals that cause the process to execute when they change The sensitivity list for the process statement is optional However if you use one an implied wait statement is included at the end of the process This implied wait statement has a sensitivity list that is the same as the sensitivity list in the process statement You can use only static signal names in the sensitivity list of the process statement and the signals must be readable For simulation a process without a sensitivity list must contain a wait statement If you use the sensitivity list in the process statement you cannot use a wait statement with a sen
217. ed name construct as shown in the following examples VARIABLE time of day clock time time of day minute 35 start hour time of loads 35 into element minute fF day hour assigns value of element hour to start hour When assigning values to or reading from record elements the types of the record elements must match the types of the variables You can also access a record as an aggregate in which case all the elements are assigned at once as shown in the following example VARIABLE time of time of day 12 05 23 5 30 VARIABLE start hour day clock time integer RANGE 1 TO 12 am Mentor Graphics VHDL Reference Manual July 1994 Types access type definition Access types are types whose values point to other objects they allow access to objects such as FIFOs and linked lists that contain unnamed elements for which storage is dynamically allocated Construct Placement type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax access type definition access subtype indication Definitions B subtype indication Defines the type of the objects pointed to by the access type This subtype is called the designated subtype and the base type is called the designa
218. efault value is one 1 Result Type lt The result type corresponds to the left bound type indicated by the specified parameter n Evaluation Result h 3 5 5 5 The result returns the left bound of the index range specified by the parameter n The index range is all the possible index values in a specified range Mentor Graphics VHDL Reference Manual July 1994 10 13 Attributes Example The following example shows an attribute portion of a code description TYPE arr 1 IS ARRAY integer RANGE lt gt OF integer VARIABLE matrix arr 1 1 TO 3 9 DOWNTO 6 array var decl matrix left 2 parameter N is 2 Returned value is 9 matrix left 1 parameter N is 1 Returned value is 1 When the parameter n is 2 the boxed column is examined 1 2 3 The value that returns is 9 which 1s the value of the left bound that the parameter 2 specifies When the parameter n is 1 the vertical column is examined In this example a 1 is returned 10 14 Mentor Graphics VHDL Reference Manual July 1994 Attributes length n Kind 2220 Value Prefix gt gt Any valid array object prefix or a prefix that designates a constrained array subtype Parameter OA An expression of type universal_integer which can be evaluated during the current design unit a
219. efer to page 10 38 Mentor Graphics VHDL Reference Manual July 1994 10 35 Attributes stable t Kind Signal Prefix gt Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Parameter A static expression of type time which must not be negative Type time is a predefined physical type refer to Section 5 from package standard refer to page 9 18 If you do not specify the parameter t it defaults to O ns Result Type Boolean Evaluation Result ee If an event has not occurred on the signal for the period of time specified by the parameter t the result is a signal with a value of TRUE If the preceding condition is not met the value of the signal is FALSE If the parameter is omitted it defaults to O ns In this case the value of the signal is FALSE for one simulation cycle only if the signal has just changed In other words signal stable Q signal delayed 0 signal wheresignal is the name of the signal Example For a comparison of this attribute with other signal attributes refer to page 10 38 10 36 Mentor Graphics VHDL Reference Manual July 1994 Attributes transaction Kind Signal Prefix gt Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Result Type The result type is type bit which is a predefined enumeration type refer to
220. efinition subtype indication entity aspect entity class entity declaration entity declarative item entity declarative part entity designator entity header entity name list entity specification entity statement entity statement part enumeration literal enumeration type definition exit statement exponent expression extended digit factor file declaration file logical name file type definition floating type definition formal designator formal parameter list formal part full type declaration function call Location of Syntax For More Diagram Information A 29 5 29 A 29 5 29 A 65 4 7 A 30 8 31 A 31 10 55 A 32 8 4 A 32 8 10 A 33 8 10 A 33 10 55 A 33 8 6 A 33 10 55 A 33 10 55 A 34 8 12 A 34 8 12 A 34 5 19 A 34 5 19 A 34 6 28 A 34 1 16 A 35 2 4 A 35 1 17 A 36 2 4 A 36 418 A 36 4 18 A 36 5 34 A 36 5 12 A 37 _ C4 A 37 7 8 A 37 4 3 A 37 44 A 37 7 15 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary Table A 1 VHDL Construct Listing continued Location of Syntax For More Language Construct Diagram Information generate statement 1 1 A38 6 30 generation scheme A338 6 30 generic clause 1 1 1 1 A338 87 generic_list_zz_____________A38_______ 8 7 generic map aspect 1 1 A 38 88 32 graphic character 3 1 5 guarded signal specification A 39 141 8 identifier ARH identifier list gt 1 1 11 A339 9 4l if
221. em Syntax disconnection specification disconnect guarded signal specification after fime expression guarded signal specification guarded signal list type mark signal list signal name signal name others all Description The following list shows the rules for using the disconnection specification When you specify a signal list each signal name in the list must be a locally static name that refers to a guarded signal The time expression must be static and evaluate to a positive value e The disconnection specification can apply only to the drivers of one signal If two or more disconnection specifications apply to the drivers of the same signal an error occurs There is a disconnection specification for every guarded signal whether you explicitly define one or you elect to use the implicit default The default disconnection specification is generated by the system internally and takes the following form DISCONNECT guarded sig name guarded sig type AFTER 0 ns 11 8 Mentor Graphics VHDL Reference Manual July 1994 Signals Example The following example shows a possible use of the disconnection specification ARCHITECTURE sig test OF test IS SIGNAL tester wired or bit BUS SIGNAL a bit DISCONNECT tester bit AFTER 10 ns BEGIN Sig assign block label BLOCK tester 1 signal declarations discon spec
222. ements for which storage is dynamically allocated Mentor Graphics VHDL Reference Manual July 1994 2 13 Expressions The BNF description for the allocator construct is as follows allocator new subtype_indication new qualified expression The following list describes the characteristics of an allocator An allocator creates an object of the type given in the type mark of the subtype indication or qualified expression e The initial value of the object created by an allocator is determined as follows O With a subtype indication the initial value is the same as the default initial value of any explicitly declared variable of the designated subtype O With a qualified expression the initial value is determined by the expression e Only an index constraint is allowed in the subtype indication of an allocator If the created object is an array type the subtype indication must denote a constrained subtype or include an explicit index constraint A subtype indication in an allocator must not include a resolution function Declaring an access type is a preliminary step to setting up a pointer Once an access type has been declared you can create a pointer by declaring a variable of that type and then assigning an access value to that variable using an allocator expression The following example illustrates the process of creating an access type assigning an access value to a pointer and assigning a value to the o
223. en type checking is performed For example if you try to assign a value of type floating point to a variable of type integer an error occurs For more information about type declarations refer to page 4 4 There are occasions when you want to use a subset of values of a given type In this case you can define a subtype When you use a subtype it saves you from having to declare another type if you are dealing with a large set of enumeration literals The following example shows a subtype declaration that has three elements from the type environment TYPE environment IS op temp stor temp capac dissipat load SUBTYPE basic sim IS environment RANGE op temp TO capac When you define a subtype you are not defining a new type you are defining a name for a subset of the type with a specific range or index constraint These constraints are discussed later in this section beginning on page 5 8 Every subtype has an associated type called a base type In the previous example the base type of basic simis environment For consistency every type has itself as a base type In the previous example the base type of environment 15 environment For more information on subtypes other benefits of using them and their declarations refer to page 4 7 You can convert a value of one type to another value of a closely related type by using the type conversion construct For example you can convert a floating point type object t
224. ent with a loop label is valid only within a loop that has a corresponding label You can use an exit statement in a loop that does not have a loop label In this case the statement applies only to the innermost enclosing loop If the condition you use evaluates to FALSE the exit statement has no effect 6 28 Mentor Graphics VHDL Reference Manual July 1994 Statements Example The following example shows the exit statement in a nested loop structure sum data Loop label for outer loop WHILE count 10 LOOP sequence of sequential statements eval data Loop label for inner loop FOR i IN 0 TO 10 LOOP sequence of sequential statements EXIT sum data WHEN i a Exit outer loop on the condition sequence of sequential statements tz ND LOOP eval data ND LOOP sum data iral In the preceding example if you change the exit statement to the following the inner loop exits on the condition and remains in the loop sum data EXIT eval data WHEN i a Mentor Graphics VHDL Reference Manual July 1994 6 29 Statements generate statement Generate statements efficiently model regular structures such as registers and multiplexers in structural design descriptions A generate statement can replicate a block of concurrent statements a specified number of times or can conditionally create a block of concurrent statements
225. entional definitions Table 2 4 lists the multiplying operators their operation and the operand and result type multiplying operator mod rem The rem remainder operator is defined in terms of integer division by the following identity A A B B A rem B The operation A rem B result has the sign of A and has an absolute value less than the absolute value of B Integer division satisfies the following identity which states that if A B is negative the result truncates towards zero A B A B AK B The mod modulus operator satisfies the following relation A B integer value A mod B The operation A mod B result has the sign of B and has an absolute value less than the absolute value of B The right operand for the mod and rem operators cannot be a value of zero An example of mod and rem follows PROCESS sens_list CONSTANT a integer 7 CONSTANT b integer 3 VARIABLE x y integer BEGIN X a MOD b x 2 y a REM b y 1 END PROCESS 2 20 Mentor Graphics VHDL Reference Manual July 1994 Expressions Table 2 4 Multiplying Operators Predefined Operation Left Right Result type Operator Operand Operand Type Type Multiplication Any integer Same as left Same as left type operand operand Any floating Same as left Same as left point ty
226. entor Graphics VHDL Reference Manual July 1994 Types integer type definition An integer type represents any member of the set of positive and negative whole numbers including zero depending on the range you specify In 32 bit two s complement hardware this range is usually between 2 147 483 648 and 2 147 483 647 inclusive 32 bit integer Construct Placement scalar type definition type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax integer type definition range constraint Definitions B range constraint Specifies subset of values for integer type definition Description To define an integer type or subtype you use the integer type definition An integer type definition defines both a subtype and an anonymous type Integer types are subtypes of an anonymous type Anonymous types cannot be referenced directly because they do not have a name Each range constraint bound you specify in the integer type definition must be an expression that can be evaluated during the current design unit analysis a locally static expression and must be of an integer type The two range constraint bounds can have different sign values For example TYPE group integer IS RANGE 1025 TO 1025 Different signs The following example shows an illegal range con
227. eplacement Characters You may wish to port to a system that does not use the following special characters e Vertical bar e Number sign e Double quote In this situation there are replacement characters available that do not alter a description Table 1 1 lists the replacement information Following Table 1 1 are replacement examples 1 6 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements Table 1 1 Replacement Characters Character Replacement Restrictions Replacement is allowed only if the is to be used as a delimiter The of based literals is replaced by only if you replace both characters The used on both ends of string literals can be replaced by only if each embedded is replaced with using the same rules for embedded Replacement is allowed for bit string literals also Here are some replacement examples 1 The following example shows how the vertical bar choice delimiters in a case statement can be replaced by exclamation points CASE test IS WHEN store save keep gt acc 1 WHEN OTHERS gt illop true END CASE CASE test IS WHEN store save keep gt acc 1 WHEN OTHERS gt illop true END CASE 2 The following example shows how the number sign can be replaced by the colon in a based literal 16 1f l6zlfi
228. er 1 BEGIN a 25 Variable name targets b 50 esgid y a ATL D RR 2 SS FOR i IN 1 TO 1023 LOOP z i 1 c_sqrd Array variable name as a target END LOOP WAIT FOR 10 ns END PROCESS 6 48 Mentor Graphics VHDL Reference Manual July 1994 Statements wait statement The wait statement suspends a process statement or a process called by a procedure Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax walt statement wait sensitivity clause condition clause timeout clause sensitivity clause condition clause timeout clause on sensitivity list until condition for time expression condition boolean expression Definitions sensitivity clause Defines the set of signals to which the wait statement responds B condition clause Uses a Boolean expression to specify a condition to be met before the wait terminates and the process resumes B timeout clause Specifies the maximum time that the wait statement suspends a process Description L You can control the suspension of a process with the wait statement by using the sensitivity clause condition clause or the timeout clause For simulation purposes a process that has no sensitivity list must include a wait statement or the wait statement must be included in a subprogram that is called from the process The sens
229. erate statement may contain an index specification in which case the following rules apply The block configuration applies to all the corresponding implicit block statements that are generated for each value of the index specification The block configuration applies to each static expression in the generate statement that corresponds to a value in the index specification of the block configuration e If no index specification is supplied then the block configuration applies to all implicit blocks generated by the corresponding generate statement Example The following example shows a block configuration for a design unit containing a generate statement This particular configuration applies to an example given in Section 6 of this manual under generate statement on page 6 30 CONFIGURATION mux8 cfg OF mux8 IS USE work ALL FOR gen8 This is the architecture body FOR gl 0 TO7 Block configuration with index FOR ALL mux2 USE ENTITY work mux2 bhv END FOR END FOR END mux8 cfg The following example shows a block configuration for a design unit that contains nested generate statements Like the previous example this configuration applies to an example given under generate statement For more information refer to page 6 30 Mentor Graphics VHDL Reference Manual July 1994 8 41 Design Entities and Configurations
230. erence Manual July 1994 6 11 Statements block statement The block statement groups together other concurrent statements forming an internal block that represents a section of a design description You can nest internal blocks hierarchically to organize your design Construct Placement concurrent statement architecture statement part block statement part Syntax block statement block label block guard expression block header block declarative part begin block statement part end block block label block header generic clause generic map aspect port clause port map aspect block declarative part block declarative item 6 12 Mentor Graphics VHDL Reference Manual July 1994 Statements block declarative item subprogram declaration subprogram body type declaration subtype declaration constant declaration signal declaration file declaration alias declaration component declaration attribute declaration configuration specification attribute specification disconnection specification use clause block statement part concurrent statement Definitions B ouard expression An expression of type boolean that you can use to control the execution of the concurrent signal assignment statements within a block Description A AA Y ou use a hierarchy of blocks to describe a design entity which in turn describ
231. error to reference that object Pointers that depend on the deallocated pointer such as ptr3 in the example can no longer be used For additional information on the use of allocators refer to access type definition on page 5 31 VHDL Predefined Operators S Predefined operators act upon operands and are grouped into six classes based on their precedence Table 2 2 lists all the predefined operators by operator class The operator classes are listed in the order of precedence from highest to lowest All the predefined operators in a given operator class have the same precedence In an expression the predefined operator with the highest precedence is applied to the operands first following the rules of mathematics However you can use parentheses to control the order of evaluation in an expression and non associative operators such as NAND require parentheses to determine the order of evaluation You cannot change the precedence of a predefined operator For examples refer to page 2 22 2 16 Mentor Graphics VHDL Reference Manual July 1994 Expressions Table 2 2 Operators by Precedence Operator Class Operators Miscellaneous operator abs not Multiplying operator mod rem Sign T Adding operator amp Relational operator j lt lt gt gt Logical operator and or nand nor xor The predefined operator not is a logical operator that has the precedence of a miscellaneous o
232. es a portion of a complete design The highest level block in this hierarchy is the design entity itself which is an external block residing in a library You can use this external block as an element in other designs The block statement however describes the internal blocks of your design Y ou use the block label to help you keep track of the different internal blocks of your design The block label at the end of the block statement is optional However if you use a block label here it must match the block label at the beginning of the block statement You can specify a guard expression of type boolean to control the execution of the concurrent signal assignment statements within a block When you use this Mentor Graphics VHDL Reference Manual July 1994 6 13 Statements expression the system automatically declares a signal with a simple name of guard of type boolean The signal guard can be passed as an actual signal in a component instantiation statement The topic of guarded signals is discussed in detail on page 11 5 In the block header you can define ports and generics for a block This definition allows you to map signals and generics external to the block to those contained within the block For additional information refer to the port clause port map aspect generic clause and generic map aspect discussions in Section You can specify zero or more block declarative items in a block statement These items are d
233. es About Operators 1 2 17 Miscellaneous Operators 1 1 2 18 Multiplying Operators IIA 22 22 Adding Operators 223 Relational Operators 1 1 1 1 1 228 Logical Operators 3 Static Expressions 3 Universal Expressions J 2 36 Figure 2 1 shows the where expressions fit in the overall language and the items that comprise the expressions Mentor Graphics VHDL Reference Manual July 1994 2 1 Expressions Design Units Design Entities Configurations Packages Attributes Components Types Signals Statements Subprograms Declarations Expressions Lexical Elements Naming Scope and Visibility Expressions Y Y Y Primaries Predefined Operators Names Miscellaneous Literals Multiplying Aggregates Sign Function Calls Adding Qualified Expressions Relational Type Conversions Logical Expressions VHDL Operators Figure 2 1 Expressions 2 2 Mentor Graphics VHDL Reference Manual July 1994 Expressions Definition of Expressions An expression is a formula that you use to compute a new value or a single term that defines a value As Figure 2 2 shows a binary expression takes a left operand and a right operand and operates on them with an operator to form a new operand Operands left right 1 2 Operation Operator
234. es in packages The figure shows Model A that contains a use clause that makes all the declarations in pkg b directly visible Within pkg_b is a use clause that makes the function x in pkg a Visible Function x is not directly visible to the Model A code but function z in pkg b is directly visible ackage pkg a Y Package pkg b y FUNCTION x RETURN bit CTION z RETURN bit a ay Y y USE pkg a x Model A USE pkg b all d Figure 3 8 Multiple Use Clauses Mentor Graphics VHDL Reference Manual July 1994 3 23 Naming Scope and Visibility Overload Resolution When the rules for visibility determine there is more than one acceptable meaning for an enumeration literal or subprogram name overload resolution determines the actual meaning Overload resolution also determines the actual meaning of an operator occurrence All visible declarations are examined to determine overloading legality The overloading is legal only if there is one interpretation of the innermost declaration specification or statement complete context The actual interpretation of the overloaded complete context is governed by the following rules e Scope rules e Syntax rules e Visibility rules e Miscellaneous rules which include the following O Rules requiring expressions or names to h
235. ess range high The following code defines down address range TYPE down address range IS RANGE 10 DOWNTO 1 The following code returns the value 10 which is the upper bound of down address rang down address range high Mentor Graphics VHDL Reference Manual July 1994 10 43 Attributes left Kind Value Prefix Any scalar type or subtype Result Type The same type as the prefix type Evaluation Result The result is the left bound of the specified prefix type Example The following code defines address range TYPE address range IS RANGI EO TO 31 The following code returns the value 0 which is the left bound of address range address range left 10 44 Mentor Graphics VHDL Reference Manual July 1994 Attributes leftof x Kind Function Prefix Any enumeration integer physical type or subtype Parameter The value for the parameter x must be of the same base as the specified prefix Result Type The result type corresponds to the base type of the specified prefix Evaluation Result The evaluation result is the value that is to the left of the specified parameter Example The following code defines the enumerated type color TYPE color IS red yellow green flash The following code returns the value yellow which is the value at the position to the left of the position specified by the parameter green c
236. ession Ne 5 5 range range constraint range gt 5 5 record type definition record element declaration 5 29 relation simple expression relational operator simple expression 2 4 Mentor Graphics VHDL Reference Manual July 1994 gt end record A 55 Syntax Summary relational operator lt gt same jJ 2 28 return statement return expression gt gt 6 44 scalar type definition _ enumeration type definition integer type definition floating type definition y physical_type_definition Sa 5 4 A 56 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary secondary unit architecture body package body gt 9 3 secondary unit declaration identifier gt physical_literal gt gt 5 15 selected name prefix gt gt suffix 3 5 selected signal assignment gt with gt expression select l x target k options selected waveforms gt E A 6 27 selec
237. essions Mentor Graphics VHDL Reference Manual July 1994 2 31 Expressions Static Expressions Static expressions fall into two categories e Locally static e Globally static A locally static expression is an expression that can be completely evaluated when the design unit in which it appears is evaluated The values for locally static expressions depend only on those declarations that are local to the design unit or on any packages used by the design unit A locally static expression must use operators that are predefined and all the operands and results of the expression must be scalar types Therefore if you use an overloaded operator in an expression it is not a locally static expression Every operand in the expression must be a locally static operand A locally static operand is one of the items listed in Table 2 7 A globally static expression is an expression that can be evaluated when the design hierarchy where the expression appears is elaborated The values for globally static expressions may depend upon declarations that appear in other design units The values for globally static expressions are determined when the design unit is elaborated A globally static expression must use operators that are predefined Therefore if you use an overloaded operator in an expression it is not a globally static expression Every operand in the expression must be a globally static operand A globally static operand is one of the items
238. est lt data b AFTER 2 ns WHEN en2 1 ELSE test 1 AFTER 2 ns END data flow However the following example shows what the preceding example actually does This example evaluates certain relational expressions test less than or Mentor Graphics VHDL Reference Manual July 1994 6 25 Statements equal to data b and so on and then assigns the boolean result of the expression to the signal test NTITY tester IS ND tester E pH ARCHITECTURE data flow OF tester IS SIGNAL test data a data b qsim state SIGNAL enl en2 bit BEGIN test data a AFTER 2 ns WHEN enl 71 ELSE test lt data b AFTER 2 ns WHEN en2 1 ELSE test lt 1 AFTER 2 ns tz ND data flow The following example although similar to the first example shows a valid use of a conditional signal assignment ARCHITECTURE data flow OF tester IS SIGNAL test data a data b my qsim state SIGNAL enl en2 bit BEGIN bus test BLOCK BEGIN The following code shows cond sig assignments test lt TRANSPORT data a AFTER 2 ns WHEN enl 71 ELSE data b AFTER 2 ns WHEN en2 1 ELSE 1 AFTER 2 ns END BLOCK bus test ND data flow tz
239. f a return statement PROCEDURE ve CONSTANT VARIABLE ram exam VA A VARIA J in a procedure BLE ram con IN bit vector 0 TO 17 count const integer incr count integer BEGIN IF address 255 THEN BLE address IN integer VARIABLE new add OUT integer IS 3 RETURN When encountered returns to calling code ELSE new add address 3 END IF incr count incr count count const tz ND ram exam Mentor Graphics VHDL Reference Manual July 1994 6 45 Statements signal assignment statement The signal assignment statement changes the values of the projected output waveforms that are in the driver for one or more signals Signals are not updated until a process suspends Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax signal assignment statement target lt transport waveform target name aggregate waveform waveform element waveform element waveform element value expression after time expression null after time expression Description gt gt 00 You can think of a signal driver as a container for the projected output waveform The value of a signal is related to the current values of its drivers For mor
240. ffix must not be the reserved word all The simple name character literal or operator symbol declaration you use as the suffix must be declared immediately within the construct designated in the prefix An expanded name used to designate an item declared immediately within a named construct is allowed only within the construct named in the prefix The suffix is the item in a design library or package that you wish to select This selection can be a single item several items or all the items that the design library or package contains To select all the items you use the reserved word all Mentor Graphics VHDL Reference Manual July 1994 3 7 Naming Scope and Visibility Indexed Names You use an indexed name to designate an element of an array The following BNF description shows the syntax for an indexed name indexed name prefix expression expression The prefix you use must be valid for array types For information on array types refer to page 5 22 You use one or more expressions to designate the index value for an array element For example PROCESS TYPE one array IS ARRAY positive RANGE lt gt OF integer TYPE two array IS ARRAY positive RANGE lt gt positive RANGE lt gt OF integer VARIABLE my_matrix one_array 1 TO 5 VARIABLE d_matrix two_array 1 TO 10 1 TO 10 VARIABLE y w integer BEGIN y my m
241. ficient for modeling switched ransistors since such a requirement is out of he scope of this effort Furthermore athematics primitives timing standards etc re considered orthogonal issues as 1t relates to his package and are therefore beyond the scope f this effort declarations or definitions shall be included or excluded from this package The package laration defines the types subtypes and larations of std_logic_1164 The td logic 1164 package body shall be considered the formal definition of the semantics of this package Tool developers may choose to implement the package body in the most efficient manner gt available to them Limitation O H Note J 0 Q nAaarBAoctoa sada O Q modification history version mod date e v4 200 01 02 92 Mentor Graphics VHDL Reference Manual July 1994 9 21 Design Units and Packages PACKAGE std logic 1164 IS logic state system unresolved TYPE std ulogic IS U Uninitialized X Forcing Unknown Q Forcing 0 Clita Foreing 4 2 High Impedance W Weak Unknown L Weak 0 HT Weak 1 Don t care gt unconstrained array of resolution function s
242. flow Using the previous example the following example shows the equivalent form the system creates for the selected signal assignment PROCESS test data a data b enl sens list created BEGIN from all signals CASE enl IS WHEN 0 gt tes WHEN 1 gt tes END CASE END PROCESS t lt data a t lt data b Mentor Graphics VHDL Reference Manual July 1994 6 27 Statements exit statement The exit statement relates to the loop statement in that you use this statement to leave an enclosing loop After execution of the exit statement control goes to the point immediately following the exited loop Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax exit statement exit 000 label when condition Description As the BNF description shows the exit statement can take several forms For example EXIT Leave the nearest enclosing loop EXIT sum data Leave loop named by loop label sum data EXIT WHEN data 1024 Leave enclosing loop if condition data 1024 is true EXIT fill memory WHEN enable 1 Leave named loop if the condition enable 1 is true An exit statem
243. following 2 26 Mentor Graphics VHDL Reference Manual July 1994 Expressions I TO I 1101 3 Es amp 1 2 3 SM resultant array from concatenation TL M me element_array When you concatenate two non array objects each non array object is treated as a one dimensional array containing one element It is important that at least one array type declaration is visible in the current scope and that this visible array type declaration contain an element type that matches the type of the elements you are concatenating In the case of the sens_sig3 process variables x and z are both of type integer which is the same as the elements in arrays of type ref_array In the sens_sig3 process there is only one visible array type declaration that has an element type that matches the type of the variables being concatenated This means that the left bound and range of each of the implied one element arrays are determined by the ref_array type declaration Each element of the implied array has a left bound of 1 the left bound of the positive lt gt value set and an ascending range as determined by the range of the positive subtype declaration SUBTYPE positive IS integer RANGE 1 TO integer high The range of the implied arrays for x and z are 1 to 1 Had the following type declaration also been included in the sens_sig3 process overloading rules would determine which array type declaratio
244. for an if statement you must use a boolean expression If the expression evaluates to TRUE the sequence of statements is executed if the expression evaluates to FALSE the sequence of statements is not executed There are three basic forms of the if statement e The if then form selects a statement or sequence of statements for execution if a single condition is true as shown in the following example The if then statement format IF sum 256 THEN sum sum 1 END IF 6 34 Mentor Graphics VHDL Reference Manual July 1994 Statements e The if then else form selects one of two sequences of statement if a condition is true as shown in the following example if then else statement format IF preset 1 AND clear 0 AND clock 1 THEN output 1 ELSE output 0 END IF e The if then elsif else form selects from alternative sequences of statements based on a set of conditions Here is an example Selecting alternative sequences with the ELSIF IF main 1 AND cross 1 AND left 1 THEN main color green sensor count false ELSIF main 0 AND cross 1 AND left 1 THEN main color lt red sensor count true ELSE main color yellow sensor count true END IF Men
245. ge new math and the file ram cntnts do not appear in this example The ram write procedure IS ARRAY O0 TO 255 op code op code PACKAGE memory write IS TYPE op code array PROCEDURE ram load VARIABLE END memory write PACKAGE BODY memory write IS PROCEDURE ram load VARIABLE USE ram ALL ram to load BEGIN ram code op code END ram load END memory write OF bit vector 0 TO 7 IN op code array IN op code array The ram read procedure PACKAGE memory read IS TYPE op code array IS ARRAY 0 TO 255 OF bit vector 0 TO 7 TYPE ram file IS FILE OF op code array FILE ram cntnts ram file IS IN user sys 1076 lib raml1l file PROCEDURE ram read VARIABLE ram data OUT ram data array VARIABLE test add start OUT integer lt D memory read Mentor Graphics VHDL Reference Manual July 1994 7 19 Subprograms PACKAGE BODY memory read IS PROCEDURE ram read VARIABLE ram data OUT ram data array VARIABLE test add start OUT integer IS USE new math ALL Random number generator in this package VARIABLE address integer
246. gle line There must be one or more separators between an identifier or an abstract literal and an adjacent identifier or abstract literal Delimiters A delimiter is one or more special characters that establish the boundaries of one or more lexical elements A compound delimiter consists of two delimiters together The delimiters and compound delimiters you can use are as follows e Delimiters amp 2 2 1 e Compound delimiters gt gt lt lt gt The delimiter characters are not delimiters when you use them in comments abstract literals character literals or string literals The following are examples of delimiter use SIGNAL yellow green red bit Uses and z lt TRANSPORT t AFTER q Uses the compound delimiter lt the and the space 1 22 Mentor Graphics VHDL Reference Manual July 1994 Expressions Section 2 Expressions An expression is an equation or a primary that indicates a value This section defines the items that comprise an expression and discusses the rules for using expressions The following list shows the topics covered this section Definition of Expressions 2 3 General Expression Rules__ 2 4 Operands Primaries Names 2 Literal 7 Aggregates 8 Function Calls 10 Qualified Expressions _ _ 2 10 Type Conversions ___ 21 Allocators 213 VHDL Predefined Operators 1 2 16 Important Not
247. gn Entities and Configurations entity declarative part The entity declarative part contains declarations of items that are shared with other architectures having the same interface Construct Placement entity declaration Syntax entity declarative part entity declarative item entity declarative item subprogram declaration subprogram body type declaration subtype declaration constant declaration signal declaration file declaration alias declaration attribute declaration attribute specification disconnection specification use clause Description When you declare items in the entity declarative part the names you use are visible to all the architectures that correspond to the design entity For more information on visibility refer to page 3 12 8 10 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Example The following example shows some possible entity declarative items ENTITY bus monitor IS GENERIC prop delay time PORT data bus IN bit vector 0 TO 7 prty IN bit error e QUT bit dig USE parity ALL use clause TYPE code IS ARRAY integer RANGE lt gt OF integer type decl SUBTYPE bcode IS code 0 TO 1 subtype declaration CONSTANT even check string 10000010 constant CONSTANT odd check string 00000001 decl s
248. gram Parameters Port Association Rules 10 1 Attributes 11 1 Driver Resolution Table A 1 VHDL Construct Listing xiv 8 33 A 1 Mentor Graphics VHDL Reference Manual July 1994 About This Manual About This Manual This manual contains reference material for the VHDL language defined in IEEE Std 1076 1987 IEEE Standard VHDL Language Reference Manual Mentor Graphics has several product offerings based on VHDL that allow system and component designers to create and analyze language models of their systems and integrated circuits Manual Organization Section 1 Lexical Elements describes the most basic items that you use to form the VHDL language e Section 2 Expressions describes the items you use to create formulas for computing values and the operators you use in these formulas e Section 3 Naming Scope and Visibility describes how to identify items and the region of code in which the item has effect Section 4 Declarations describes how to define a design item e Section 5 Types describes how to specify the kind of a defined design item Section 6 Statements describes all the concurrent and sequential statements you can use to specify different actions e Section 7 Subprograms describes the procedure and the function which allow you to partition descriptions into stand alone modules e Section 8 Design Entities and Configurations discusses the major hardware abstra
249. guration specification on page 8 25 except that this time a configuration declaration is used to bind the components of the design instead of using a configuration specification In this example assume that the entity declarations and architecture bodies for the inverter AND gate and OR gate are stored individually in a parts library named my parts lib Furthermore assume that the entity declaration and architecture body for the multiplexer have been placed in the work library 1 Design entity for an inverter in my parts lib 2 ENTITY inv IS 3 GENERIC Del time 2ns 4 PORT i IN bit i bar OUT bit 5 END inv 6 7 ARCHITECTURE inv basic OF inv IS 8 BEGIN 9 i bar lt NOT i AFTER Del 10 END inv basic 11 12 Design entity for an and gate in my parts lib 13 ENTITY and2 IS defined 14 GENERIC Del time 4 5ns 15 PORT ay big OLN baby QUE bit 16 END and2 s 17 ARCHITECTURE and2 basic OF and2 s IS 18 BEGIN 19 y lt a AND b AFTER Del 20 END and2 basic 21 22 Design entity for the OR gate in my parts lib 23 ENTITY or2 IS 24 PORT a b IN bit y OUT bit 25 END or2 26 27 ARCHITECTURE or2 basic OF or2 input IS 28 BEGIN 29 y lt a OR b
250. he shift operators perform bit shifting and rotation on operands This release of System 1076 fully supports the six shift operators defined in the IEEE Std 1076 1993 IEEE Standard VHDL Hardware Description Language Manual The following BNF description shows the shift operators relational operator sll srl sla sra rol ror Relational Operators The relational operators check for equality inequality and the ordering of operands The following BNF description shows the relational operators relational_operator l lt lt I gt gt Table 2 6 shows the standard VHDL relational operators their operations and their operand and result types When you are using the standard VHDL operators not using an overloaded version of one of these operators the operands you use must be of the same type and the result type is always boolean 2 28 Mentor Graphics VHDL Reference Manual July 1994 Expressions Table 2 6 VHDL Relational Operators Operator Operation Operand Type Result Type Equality Any type except file types Boolean Inequality Any type except file types Boolean lt Ordering Any scalar or discrete Boolean array type lt Ordering Any scalar or discrete Boolean array type gt Ordering Any scalar or discrete Boolean array type gt Ordering Any scalar or discrete Boolean array type Predefined Equality and Inequality Operators As Table 2 6 s
251. hich is the value of the descending range converted from ascending range of the specified parameter 1 This returned value can be used only when specifying a range The following example shows the specification of a range of another array by using the preceding example x ARRAY 1 TO 4 matrix reverse range 1 This is equivalent to the following x ARRAY 1 TO 4 3 DOWNTO 1 4 by 3 two dimen array Anexample using range in a loop statement follows FOR test IN matrix reverse range 1 LOOP This is equivalent to the following FOR test IN 3 DOWNTO 1 LOOP 10 22 Mentor Graphics VHDL Reference Manual July 1994 Attributes right n Kind gt gt Function Prefix gt gt Any valid array object prefix or a prefix that designates a constrained array subtype Parameter OA An expression of type universal_integer which can be evaluated during the current design unit analysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the default value is one 1 Result Type 1 lt 0 The result type corresponds to the type indicated by the specified parameter n Evaluation Result The result returns the right bound of the index range that the parameter n specifies The index range is all the possible index values in a specified range Mentor Graphics VHDL Reference Manual J
252. his attribute creates and accesses a signal that has the same value as clock except it is delayed 50 ns The prefix indicates the object that the attribute relates to The prefix for a predefined attribute denotes a particular array block signal or type On the other hand the prefix for a user defined attribute may denote an entity declaration an architecture body a configuration a procedure a function a package a type a subtype a constant a signal a variable a component or a Mentor Graphics VHDL Reference Manual July 1994 10 3 Attributes label In the preceding example the prefix clock is of type signal therefore the attribute relates to the signal called clock The attribute designator is the name of the attribute that you wish to use In the preceding example delayed is the attribute designator The optional expression is an expression that designates a specific parameter for the attribute In the preceding example the expression is 50 ns Not all the predefined attributes allow parameters The expression in the attribute name may be required or may be optional depending on the particular attribute definition The following examples show the declaration of two types and the use of attribute names to determine information about those types These code fragments have been taken out of context from a description Type declarations TYPE color IS red white blue orange purple TYPE ve
253. hows the equality and inequality operators are predefined for all types except file types The equality operator returns a value of TRUE if the left and right operands are equal Otherwise a value of FALSE is returned The inequality operator returns a value of FALSE if the left and right operands are equal Otherwise a value of TRUE is returned When you use two scalar values of the same type as operands they are equal only if their values are the same When you use two composite values of the same type as operands they are equal only if the following conditions exist Each element of the left operand has a matching element in the right operand The left operand is no larger than the right operand Each element of the right operand has a matching element in the left operand The right operand is no larger than the left operand e The matching elements in the left and right operands are equal Mentor Graphics VHDL Reference Manual July 1994 2 29 Expressions Using the preceding conditions two null arrays of the same type are always considered equal When two one dimensional arrays are compared matching elements are determined by matching index values Index values match if the left bound element values of the index ranges match If the left bound element values match the next element values to the right are compared This process continues until the right bound of one of the arrays is reached Predefined Or
254. ics VHDL Reference Manual July 1994 Signals actually is a unit delay Figure 11 7 illustrates this concept by using the three AND gates with zero delay as one input to a device and by using a straight signal as the other input Notice that the path to dO an edge triggered input takes three delta delays while the path to d1 takes one delta delay This is a potential race condition in a real hardware circuit 1 Unit delay l i aay 3 Units of ee 1 Unit delay total lt ___ ye N delay gt yl Loo N do gt q mM di Figure 11 7 Unit delay Modeling Mentor Graphics VHDL Reference Manual July 1994 11 23 Syntax Summary Appendix A Syntax Summary This appendix includes the following information e Table A 1 lists the VHDL constructs in alphabetical order and provides a page number for the syntax drawing and a page number where information for each construct can be found in this manual A subsection shows how to use the syntax diagrams All the syntax diagrams for VHDL are listed in alphabetical order Table A 1 VHDL Construct Listing Location of Syntax For More Language Construct Diagram Information abstract literal _______________A 11________ 1 16 access type definition 1 1 A 1ll1 5 31 actual designator 1 1 1 1 A l1l 431 actual parameter part 1 1 lt A 11 7 15 actual part AH Ls 431 adding operator AHI 2 223 aggregat
255. ier freq in freq out x integer TYPE info IS ARRAY integer RANGE lt gt OF integer VARIABLE z info 1 TO 10 BEGIN expression for output frequency using names for operands freq out multiplier freq in decade Right bound of array x z right 10 WAIT FOR 1 ns ND PROCESS tz Literal mon is 10 se Expression using an attribute name that returns a value Therefore 20 A literal consists of one or more characters that represent themselves There are three general categories of literals e Numeric e Character e String Literals are discussed in detail on page 1 15 Examples of literals used in expressions follow VARIABLE result integer 1024 8 Variable declaration with expression containing numeric literals 1024 and 8 VARIABLE answer character x Expression assigning character literal x to variable answer CONSTANT string 1 string 011 amp true Initialize string 1 using an expression to concatenate string literals O11 and true Mentor Graphics VHDL Reference Manual July 1994 2 7 Expressions Aggregates An aggregate is the combination of one or more values into a composite value of an array type The following BNF description shows the syntax related to aggregates aggregate element association element association elemen
256. in a design library visible to a design unit use clause A use clause makes visible certain declarations within library units contained in a design library The use clause is a shorthand method that relieves you from having to use a full selected name for declarations if they exist in a design library Mentor Graphics VHDL Reference Manual July 1994 9 5 Design Units and Packages Description S Figure 9 2 shows the context clause concept The following list describes the three situations A B and C shown in the figure A In this situation the design file contains a use clause to make the contents of package x directly visible This package is already visible by selection to the design file environment B In this situation the design file contains a library clause to make library a and b visible The library names within the design file are mapped to the outside libraries with an implementation dependent method The physical libraries then become visible to the current design file C In this situation the design file contains a library clause to make library c visible A use clause is also in the context clause which enables you to use the shorthand method of making the items of library c directly visible The library names within the design file are mapped to the outside libraries with an implementation dependent method Visibility is discussed in detail on page 3 12 For detailed information about the use
257. in the VHDL standard Mentor Graphics VHDL Reference Manual July 1994 9 23 Design Units and Packages function xnor 1 r std logic vector return std_logic_vector function xnor 1 r std_ulogic_vector E return std ulogic vector FUNCTION not 1 std logic vector RETURN std logic vector FUNCTION not 1 std ulogic vector RETURN std ulogic vector conversion functions FUNCTION To bit s std ulogic xmap BIT 0 RETURN BIT FUNCTION To bitvector s std logic vector xmap BIT 707 RETURN BIT VECTOR FUNCTION To bitvector s std ulogic vector xmap BIT 0 RETURN BIT VECTOR FUNCTION To StdULogic b BIT RETURN std ulogic FUNCTION To StdLogicVector b BIT VECTOR RETURN std logic vector FUNCTION To StdLogicVector s std ulogic vector RETURN std logic vector FUNCTION To StdULogicVector b BIT VECTOR RETURN std ulogic vector FUNCTION To StdULogicVector s std logic vector RETURN std ulogic vector strength strippers and type convertors FUNCTION To X01 s std logic vector RETURN std logic vector FUNCTION To X01 s s
258. ing an assertion statement severity Concurrent None Represents a process containing the Procedure Con corresponding sequential procedure call Call Concurrent guarded Represents an equivalent process Signal transport Con statement that assigns values to a signal Assignment 6 8 Mentor Graphics VHDL Reference Manual July 1994 Statements Table 6 1 System 1076 Statements continued Reserved Statement Words Class Description Assertion assert Seq Checks if specified condition is true and report if so reports a message and a severity severity level Exit exit Seq Exits from an enclosing loop statement when Generate generate Con Generates a regular structure such as a end register within a structural description If if Selects 0 or 1 of the enclosed sequential then Seq statements for execution elsif end Loop loop Seq Iteractively executes a sequence of end statements Next next Seq Completes the execution of one of the when iterations of an enclosing loop statement Null null Seq Specifies no action is to be performed passes execution to the next statement Procedure None Seq Executes a particular procedure body Call process Defines an independent sequential Process begin Con process representing the behavior of a end portion of a design Return return Seq Completes execution of the innermost enclosing function or procedure Signal None Modifies projected
259. inition of equality and less than the remaining relational operators can be defined as follows Less than is the complement to greater than or equal to Greater than is the complement to less than or equal to Logical Operators The logical operators are predefined for the types bit and boolean and one dimensional arrays of type bit or boolean The logical operators have their conventional definitions 0 is false and 1 is true The following syntax description shows the logical operators logical operator and or nand nor xor xnor If the operands are arrays and the logical operator is a logical operator other than not then the following information applies to the expression The operands must be the same length The operation is accomplished by computing the result of applying the operator to matching elements of the the arrays The result is an array of the same subtype as the left operand with the same index range If the operand is an array and the logical operator is not the not operation is performed on each array element and the result is an array of the same subtype as the operand with the same index range There are other expressions that are special cases that do not fall into the expression categories in the previous discussion about expressions These expressions are identified as follows and are further described in the following subsections Static expressions Universal expr
260. initions B range constraint Specifies a subset of values for a floating type definition Description An example of a floating point number is the ratio 5 3 which results in the decimal number 1 66666 where the numeral six repeats indefinitely Since hardware can provide only a finite number of bits a real number approximation is required To define a floating point type or subtype you use the floating type definition A floating type definition defines both a subtype and an anonymous type Floating point types are a subtype of an anonymous type Anonymous types cannot be referenced directly because they do not have a name The range constraint bounds you specify in the floating type definition must be an expression that can be evaluated during the current design unit analysis locally static expression and must be of a floating point type The two range constraint bounds can have different sign values For example TYPE fpt result IS RANGE 1 0 TO 1000 0 Different signs The following example shows an illegal range constraint bound TYPE tst fpt IS RANGE 100 75 DOWNTO 5 Ill low range bound 5 12 Mentor Graphics VHDL Reference Manual July 1994 Types In the preceding example the right or low range constraint bound is 5 which is of an integer type Since the bound is not of a floating point type it is not a legal bound The following example shows another illegal c
261. inued null 1 13 of 1 13 on 1 13 open 1 13 or 1 13 others 1 13 out 1 13 package 1 13 port 1 13 procedure 1 13 process 1 13 range 1 13 record 1 13 register 1 13 rem 1 13 report 1 13 return 1 13 select 1 14 severity 1 14 signal 1 14 subtype 1 14 then 1 14 to 1 14 transport 1 14 type 1 14 units 1 14 until 1 14 use 1 14 variable 1 14 wait 1 14 when 1 14 while 1 14 with 1 14 xor 1 14 Resolution functions 4 9 11 10 Resource library 9 8 Result type profile 3 18 Return statement 6 44 Scalar types 5 4 Scope 3 13 Scope rules 3 15 Index 6 Selected names 3 4 Selected signal assignment 6 27 Sensitivity list process 6 42 Sensitivity list wait statement 6 49 Separators 1 21 Sequential statements 6 5 Assertion 6 10 Case 6 15 Exit 6 28 Generate 6 30 If 6 34 Loop 6 36 Next 6 38 Null 6 39 Procedure call 6 40 Return 6 44 Signal assignment 6 46 Variable assignment 6 48 Wait 6 49 Sequential difference between concurrent 6 2 Severity level type declaration 9 19 Shift operators 2 28 Short circuit operation 2 17 Side effect for functions 7 3 Sign 2 22 Signal assignment and operator similarity 6 25 Signal assignment statement 6 46 Signal assignments overview Concurrent 11 17 Sequential 11 16 Signal attributes see Predefined attributes Signal declarations summary 4 17 Signal definition of 11 1 Signal in
262. iral ND bus monitor Mentor Graphics VHDL Reference Manual July 1994 8 11 Design Entities and Configurations entity statement part The entity statement part contains passive concurrent statements that are shared with other architectures having the same interface Construct Placement entity declaration Syntax entity statement part entity statement entity statement concurrent assertion statement passive concurrent procedure call passive process statement Description Passive concurrent statements are process statements and concurrent procedure calls that do not make signal assignments or do not execute file operations The concurrent assertion statement is inherently passive You can use these statements to monitor your design during simulation For more information on concurrent statements refer to page 6 7 8 12 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations Example The following example shows some possible entity statement parts Define the design entity ENTITY controller IS PORT sensor IN bit count IN bit output OUT bit Entity statement part until BEGIN BEGIN ASSERT count 1 REPORT The state is changing con SEVERITY note assert updat
263. it value The type bit from package standard is limited to the values of zero and one Therefore the O and X specified literal converts to the equivalent B specified bit string literal This conversion does not discard leading zeros a leading digit is the left most array entry The size of the bit string literal is the number of digits in its binary representation The following examples show some possible bit string literals X 333 equivalent to B 001100110011 O 333 equivalent to B 011011011 X OF7 equivalent to B 000011110111 oum equivalent to B 111010 Separators and Delimiters Separators and delimiters are characters that divide and establish the boundaries of lexical elements Separators When you put lexical elements together there are situations in which you must use a separator between the elements Otherwise the adjacent lexical elements could be construed as being a single element There are three lexical separators Space character except when the space is in a comment string literal or character literal Mentor Graphics VHDL Reference Manual July 1994 1 21 Lexical Elements Format effector except when the format effector is in a comment or a string literal e End of line consists of the line feed character Since the end of the line is always considered a separator all lexical elements must appear on a sin
264. itial value 11 15 Signal unconnected 11 15 Signals default values 11 15 Signals guarded 11 5 Simple names 3 4 Simulation iteration cycle 11 21 Single object declaration 4 11 Slice names 3 9 Mentor Graphics VHDL Reference Manual July 1994 Index INDEX continued Slicing arrays 3 9 5 28 Statements Assignment 6 5 Classes of 6 2 Concurrent 6 7 Concurrent vs sequential 6 2 Conditional 6 6 Iterative 6 6 Procedure control 6 6 Quick reference table 6 8 Sequential 6 5 Static expressions 2 32 3 11 Static name 3 11 Static signal name 3 11 String literal 1 19 String type declaration 9 20 Strongly typed language 5 2 Structural description 8 15 Subprogram bodies 7 10 Subprogram calls Default parameters 7 14 Named parameter association notation 7 13 Positional parameter notation 7 13 Subprogram declarations 7 6 Valid modes 7 8 Valid object types 7 8 Subprogram overloading 7 17 Subprogram complete example 7 19 Subtype 5 2 Subtype declarations 4 7 Suffix names 3 7 Syntax diagrams how to read A 9 Syntax summary A 1 Tail operand 2 30 Terminal A 10 textio 9 30 Transaction 11 4 Transport delay 6 24 6 47 11 19 Type Attributes see Predefined attributes Type conversion 2 12 Type conversion functions 4 37 Type declaration 4 4 Mentor Graphics VHDL Reference Manual July 1994 Type mark 2 12 4 9 Types Access 5 31 Array 5 22 Composite 5 22 Definition of
265. itivity clause allows you to define the set of signals to which the wait statement responds The signal names used in this clause must be static signal names and each name must designate a readable signal If you omit the Mentor Graphics VHDL Reference Manual July 1994 6 49 Statements sensitivity clause the wait statement sensitivity defaults to the longest static prefix of the signal names in the condition clause if any If you use a signal name in the sensitivity clause which defines a signal of a composite type every element of the composite appears in the sensitivity list For more information about signals refer to Section 11 The condition clause allows you to use a Boolean expression to specify a condition to be met before the wait terminates and the process resumes If you do not use the condition clause the default is a condition value of TRUE allowing the sensitivity and timeout clause to control the wait statement Note the condition construct is part of several other VHDL statements For page references to the statements that contain a condition construct refer to the index entry Condition The timeout clause allows you to specify the maximum time that the wait statement suspends a process The time expression you use cannot evaluate to a negative number If you do not use the timeout clause the maximum wait defaults to an infinite value The process resumes at the latest after the timeout value expires if no o
266. ity rules establish the meaning of an identifier The possible meanings of the occurrence of this identifier are determined during evaluation The following list shows the two possible results of this determination One possible meaning the visibility rules alone find the declaration that defines the identifier meaning If this declaration does not exist the visibility rules alone determine that the identifier is not legal e Multiple meanings the visibility rules find multiple meanings for the identifier In other words it is overloaded Within the related context one visible declaration is used if the overloading rules have been met For information on overloading rules refer to page 3 24 An identifier can be made visible by two different means as the following list shows Mentor Graphics VHDL Reference Manual July 1994 3 17 Naming Scope and Visibility e Selection if the item is hidden it becomes visible only when you use a selected name Selected names designate an item declared within another item For more information on selected names refer to page 3 4 Directly visible if the item is not hidden it is directly visible A directly visible declaration is also visible by selection Table 3 2 shows the places where a declaration is visible by selection Any declaration that occurs immediately within a declarative region of a language construct is visible by selection at the suffix of an expanded name The prefix
267. kages standard 9 18 std logic 1164 9 21 std logic 1164 ext 9 26 textio 9 30 Prefix attribute 10 3 Prefix names 3 5 Primary 2 6 Procedure 7 3 Procedure call statement 6 40 Procedure calls 7 17 Procedure control statements 6 6 Process statement 6 41 Projected output waveform 11 3 11 4 Qsim values character literal issues 1 18 Qualified expression 2 10 Range constraint 4 8 5 5 5 27 10 19 Range of integer types maximum 5 9 Range of physical types maximum 5 16 Range scalar types 5 4 Ranges important concepts 5 5 Real literal 1 16 Real type declaration 9 19 Record types 5 29 Record definition 5 29 Registers 11 5 Relational operators 2 28 Replacement characters 1 6 Reserved words 1 9 to 1 14 abs 1 9 access 1 9 after 1 9 Mentor Graphics VHDL Reference Manual July 1994 alias 1 10 all 1 10 and 1 10 architecture 1 10 array 1 10 assert 1 10 attribute 1 10 begin 1 10 block 1 10 body 1 10 buffer 1 10 bus 1 10 case 1 11 component 1 11 configuration 1 11 constant 1 11 disconnect 1 11 downto 1 11 else 1 11 elsif 1 11 end 1 11 entity 1 11 exit 1 11 file 1 12 for 1 12 generate 1 12 generic 1 12 guarded 1 12 if 1 12 in 1 12 inout 1 12 is 1 12 label 1 12 library 1 12 linkage 1 12 loop 1 12 map 1 12 mod 1 12 nand 1 12 new 1 12 next 1 12 nor 1 12 not 1 13 Index 5 Index INDEX continued Reserved words cont
268. l logarithm base 10 FUNCTION logl10 x natural real RETURN real square root FUNCTION sqrt x natural real RETURN real E X 2 n FUNCTION ldexp x real n integer RETURN real gt OX if x is negative then y must be a whole number FUNCTION pow X Y real RETURN real remainder of x y 9 34 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages returns the value x i y for some integer i such that if y is nonzero the result has the same sign as x and magnitude less than the magnitude of y Y should not be zero FUNCTION fmod x y real RETURN real largest integer returns the largest integer not greater than x FUNCTION floor x real RETURN real smallest integer returns the smallest integer not less than x FUNCTION ceil x real RETURN real hyperbolic functions FUNCTION sinh x real RETURN real FUNCTION cosh x real RETURN real FUNCTION tanh x real RETURN real trigonometric functions FUNCTIONS sin x real RETURN real FUNCTIONS cos x real RETURN real FUNCTIONS tan x real RETURN real FUNCTIONS asin x real RETURN real FUNCTIONS acos x real RETURN real FUNCTIONS atan x real RETURN real FUNC
269. l July 1994 4 9 Declarations object declaration An object is an item that has a value and a type Each object can be operated upon and manipulated Construct Placement declaration Syntax object declaration constant declaration signal declaration variable declaration Definitions B constant declaration Declares an object in which the object value is set and cannot be changed B variable declaration Declares an object in which the object value has a single current value that can be changed W signal declaration Declares an object in which the object value has a history and has current and projected values Description An object belongs to one of three classes constant variable or signal You specify the class of an object when you explicitly declare it by using the reserved word that corresponds to the classification of the object The details of how to declare these objects are discussed in the following constant declaration variable declaration and signal declaration subsections 4 10 Mentor Graphics VHDL Reference Manual July 1994 Declarations The following examples show some possible object declarations CONSTANT vcc integer 5 vcc is object of const class VARIABLE limit real imit is object of var class SIGNAL enable my qgsim state enable is obj of sig class The classification of implicitly declared objects depends on their u
270. l items in a circle or ellipse indicate a terminal A terminal is what you actually use in the code a reserved word or character e In taking Path B you must use construct two but construct three can be either used or omitted e The italic words give you additional information and do not represent an actual language construct The words that follow the italics represent an actual language construct e In taking Path C a reserved word terminal must be used The complete syntax for VHDL follows The number under each language construct shows you where to look in this manual for more information A 10 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary abstract literal decimal literal based literal gt 1 16 access type definition p access subtype indication gt 5 31 actual designator expression gt signal name gt variable name open S gt 4 3 actual_parameter_part gt parameter association list gt 7 15 actual part actual designator function name actual designator 4 31 Mentor Graphics VHDL Reference Manual July 1994 A 11 Syntax Summary
271. l value of the signal Description The interface signal declaration specifies the following interface objects e Signals that are ports that appear in entity or component declarations e Signals that are parameters in subprograms The following rules apply to the interface signal declaration You have the option to use the reserved word signal at the beginning of the interface signal declaration A port is a signal Therefore using the reserved word signal is purely for documentation and understandability If you want a signal in a subprogram parameter you must use signal Subprogram parameters are discussed on page 7 8 4 26 Mentor Graphics VHDL Reference Manual July 1994 Declarations You have the option to specify the mode for the signal If you do not specify the mode the signal defaults to mode in The subtype indication must not be a file type If you use the reserved word bus this signal declaration indicates a signal that is guarded and has a signal kind of bus This topic is discussed on page 11 5 For each interface signal you can specify a default value using the optional default expression followed by a static expression The default expression sets the initial value of the driver for the signal unless the signal is a port For additional information on default port values refer to page 4 34 For additional information on signals and related topics refer to Section 11 O The ZEEE std 1076 IN
272. laration entity name list instantiation list suffix expression logical operator architecture body constrained array definition unconstrained array definition assertion statement attribute declaration attribute specification 4 35 10 55 8 25 3 5 2 4 2 3 block body buffer bus architecture body block statement entity declaration process statement subprogram body block statement package body mode interface signal declaration signal kind 1 10 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements VHDL Reserved Words continued case component configuration constant case statement component declaration configuration declaration entity aspect entity class constant declaration interface constant declaration disconnect downto disconnection specification direction conditional waveforms if statement if statement architecture body block statement case statement component declaration entity declaration if statement loop statement package body package declaration physical type definition process statement subprogram body entity aspect entity declaration exit statement Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements VHDL Reserved Words continued file declaration file type definition configuration specification iteration scheme timeout clause subprogram specification generate generic guarded generate
273. laration to bind instantiated components to the design entities that describe their functionality The difference is that component configurations can be nested so that they can be used hierarchically to open up the structure of an architecture The component specification identifies the instances to which a given component configuration applies All the component instances named in the component specification must lie at the same level of the hierarchy immediately within the block that encloses the component configuration A given component configuration may or may not have a binding indication i If a binding indication appears it has the same effect as a component specification for the specified components It is however an error to have both an explicit configuration specification and explicit component configuration for the same instantiated component If no binding indication is given for a component either in a configuration specification or in a component configuration a default binding indication is applied as described earlier in this section For more information refer to Default Binding Indication on page 8 33 Mentor Graphics VHDL Reference Manual July 1994 8 43 Design Units and Packages Section 9 Design Units and Packages This section includes information on the design unit and the package A design unit is composed of certain language constructs that you can store and analyze independently You can place a design u
274. le 3 18 Parameter attribute 10 7 Parameters subprogram 7 8 Passive process 6 42 Physical file name 4 19 Physical types 5 15 Pointer see Access types Port map aspect 8 32 Ports 8 8 Ports default expression 4 34 Ports unconnected 4 34 8 8 Positional notation 7 13 Positive type declaration 5 11 9 20 Index 4 Precedence operator 2 16 Predefined Array types Bit vector 9 20 String 9 20 Predefined attributes 10 5 active 10 29 base 10 42 behavior 10 25 delayed t 10 30 event 10 31 high 10 43 high N 10 11 last_active 10 32 LAST_EVENT 10 33 last_value 10 34 left 10 44 leftof x 10 45 left N 10 13 length N 10 15 low 10 46 low m 10 17 pos x 10 47 pred x 10 48 quiet t 10 35 range n 10 19 reverse range n 10 21 right 10 49 rightof x 10 50 right n 10 23 stable t 10 36 structure 10 26 succ x 10 51 transaction 10 37 val x 10 52 Predefined Enumeration types Bit 5 21 9 18 Boolean 5 21 9 18 Character 5 21 9 19 Severity level 5 21 9 19 Predefined floating point types Real 5 14 Predefined integer types Integer 5 11 Mentor Graphics VHDL Reference Manual July 1994 Index INDEX continued Predefined Numeric subtypes Natural 5 11 9 20 Positive 5 11 9 20 Predefined Numeric types Integer 9 19 Real 9 19 Predefined Operators 2 16 Predefined Physical types Time 5 18 Predefined VHDL pac
275. le file type and file object declarations TYPE rom d IS FILE OF integer TYPE stat file IS FILE OF real TYPE vectors IS FILE OF bit vector 0 TO 15 FILE stats stat file IS out data FILE rom data rom d IS IN rom contents FILE test vectors vectors IS IN vectors The following rules apply to the file declaration The subtype indication can be only a subtype of a file type For information on file types refer to page 5 34 e The optional mode can be only in or out e The file logical name must be an expression of type string defined in package standard The mode indicates whether the file object is read only or write only When the mode is in the external file contents are read but not updated during the simulation of your design When the mode is out the external file contents are written but cannot be read during the simulation of your design If you do not specify a mode the default is mode in The file logical name maps to a physical file name within the file system Thus during simulation information is read from or written into a file that is external to your design Multiple concurrent processes can read from a file object of mode IN and write to a file object of mode OUT Moreover any combination of reading and writing allowed by the operating system can occur concurrently on a given logi
276. ll as the following example does because all is a reserved word VARIABLE all integer all is an illegal identifier Even if you use All with a capital A you still get an error the case of the letters does not differentiate a name you declare from a reserved word if it is the same word There are two exceptions to the rules involving reserved words First the reserved word range is also the identifier for the predefined attribute range N For more information on this predefined attribute refer to page 10 19 Second you can use reserved words in comments and string literals where they are not considered reserved words For example the use of the word all as part of the comment in the preceding example is perfectly legal Table 1 2 lists the VHDL reserved words The heading descriptions for Table 1 2 are as follows e Name the name of the reserved word e Language Constructs the language constructs that use the reserved word Page the page in this manual where the reserved word is used in the context of the listed language construct Table 1 2 VHDL Reserved Words Name Language Constructs Page abs miscellaneous operator 2 18 factor 2 4 access access type definition 5 31 after disconnection specification 11 8 waveform element 6 46 Mentor Graphics VHDL Reference Manual July 1994 1 9 Lexical Elements alias all and architecture array assert attribute alias dec
277. locate one driver value along the bottom row and the other driver value along the left hand column The cross point indicates the resolution value To find the resolution of the third driver you compare your first result to the third driver value Table 11 1 Driver Resolution Table i 1 X X 1 X X X X X F 0 X X 0 0 Driver Z 1 X 0 Z 1 X 0 Z Value For example if en1 en2 and en3 are 1 and if data a is X data bis 1 and data c is 0 the resolution value for signal test is X because X dominates any other driver value 3 Using Table 11 1 you can write a resolution function similar to the following ENTITY tester IS FUNCTION wired or driv array my qsim state vector RETURN my qsim state IS VARIABLE templ temp0 tempz boolean BEGIN IF driv array length 0 THEN Check if all drivers RETURN 2 are disconnected END IF Loop to check each FOR i IN driv array range LOOP driver array value IF driv array i X THEN Check for X RETURN X ELSIF driv array i 1 THEN Check for E templ true Set templ true ELSIF driv array i 0 THEN Check for 0 temp0 true Set temp0 true ELSE tempz true Must be Z END IF END LOOP 11 12
278. ls Separators and Delimiters Separators Delimiters Section 2 Expressions Definition of Expressions General Expression Rules Operands Primaries Names Literal Aggregates Function Calls Qualified Expressions Type Conversions Mentor Graphics VHDL Reference Manual July 1994 XV m I m NYFF O0O0NNO 0 YU U ULA 00 QQ UI YW ph o m om do do E do do m 2 1 2 3 2 4 2 6 2 6 2 7 2 8 2 10 2 10 2 12 Table of Contents TABLE OF CONTENTS continued Section 2 Expressions continued Allocators VHDL Predefined Operators Important Notes About Operators Miscellaneous Operators Multiplying Operators Sign Adding Operators Shift Operators Relational Operators Predefined Equality and Inequality Operators Predefined Ordering Operators Logical Operators Static Expressions Universal Expressions Section 3 Naming Scope and Visibility Naming Simple Names Selected Names Indexed Names Slice Names Attribute Names Scope and Visibility Declarative Region Scope Scope Rules Visibility Visibility Rules use clause Overload Resolution 2 13 2 16 2 17 2 18 2 20 2 22 2 23 2 28 2 28 2 29 2 30 2 31 2 32 2 36 0 7 2 iv Mentor Graphics VHDL Reference Manual July 1994 Table of Contents TABLE OF CONTENTS continued Section 4 Declarations lt type_declaration AAA subtype_declaration 0 4 object_declaration 4 constant_declarati
279. lt lt 6 19 concument procedure cal 621 concurrent signal assignment stmnt 1 6 23 conditional signal assignment D5 selected signal assignment 0 27 exit statement J 6 28 generate statement 2 6 30 if statement 6 94 loop statement 6 36 next statement 035 nul statement 1 6 39 procedure call statement AA 6 40 process statement 6 4 return statement _ 8 44 Mentor Graphics VHDL Reference Manual July 1994 Table of Contents TABLE OF CONTENTS continued Section 6 Statements continued signal assignment statement variable assignment statement wait statement Section 7 Subprograms Definition of a Subprogram subprogram declaration formal parameter list subprogram body Subprogram Calls function call The Procedure Call Subprograms and Overloading Overloading Operators Rules for Operator Overloading Complete Subprogram Example Section 8 Design Entities and Configurations Design Entities entity declaration entity header generic clause port clause entity declarative part entity statement part architecture body architecture declarative part Mentor Graphics VHDL Reference Manual July 1994 7 1 7 6 7 8 7 10 7 13 7 15 7 17 7 17 7 18 7 18 7 19 4 r0 000 10 Rr 90 Oo OO a a lt Table of Contents TABLE OF CONTENTS continued Section 8 Design Entities and Co
280. lue for the parameter x must be of the same base as the specified prefix Result Type The result type corresponds to the base type of the specified prefix Evaluation Result 5A The result returns the value that is located one position greater than the specified parameter x Example The following code defines num TYPE num IS RANGE 3 TO 25 The following code returns the value which is the value at one position greater than the position specified by the parameter 2 num succ 2 Restrictions 1 1 1 1 0 0 0 0 0 0 0 You cannot specify a parameter that is equal to the upper bound of the base type Using the previous example an error occurs if you specify the following code num pred 25 The previous example shows an error condition since there is no value in the position one greater than 25 Mentor Graphics VHDL Reference Manual July 1994 10 51 Attributes val x Kind Function Prefix Any enumeration integer physical type or subtype Parameter Any integer type expression Result Type The result type corresponds to the base type of the specified prefix Evaluation Result The result returns the value of the position number specified by parameter x Example The following code defines the enumeration type color TYPE color IS red yellow green flash The following code returns the value green which is the value
281. ly when you use the corresponding predefined attributes left right low and high which are described in Section 10 When using a range of items you can specify two directions Ascending using the reserved word to Descending using the reserved word downto The following examples show the use of the range O TYPE test integer IS RANGE 5 TO 4 In this example test integer is any of the integers Mentor Graphics VHDL Reference Manual July 1994 5 5 Types 5 4 3 2 101234 ascending where the left most integer 5 is equal to the low range constraint bound and the right most integer 4 is equal to the high range constraint bound O TYPE next integer IS RANGE 4 DOWNTO 5 In this example next integer is any of the integers 43210 1 2 3 4 5 descending A A where the left most integer 4 in this case is equal to the high range constraint bound and the right most integer 5 is equal to the low range constraint bound The same principle of direction applies to composite types arrays For an example of array direction refer to the discussion starting on page 5 22 The following table summarizes the relationship between the range and direction Range Ascending Range Descending Constraint Range Bound Left most Lowest value Highest value Right most Highest value Lowest value Lowest Left most value Right most value Highest Right most valu
282. m elements determines the future behavior of the drivers for the target you specify During the evaluation of a waveform element the following action occurs Assign the target a specific value at a specified time e Specify that the target is turned off after a specified time If you specify time expressions in the waveform element these delay times must use the time units from package standard If you do not specify a time expression the default is zero nanoseconds The following examples show possible sequential signal assignments from within portions of code clk lt 1 AFTER 100 ns clk gets 1 after time specified result lt a OR b OR c result gets expression in 0 ns wire lt TRANSPORT 5 AFTER 25 ns Trans delay after time line lt TRANSPORT 100 Transport delay at 0 ns Concurrent Signal Assignments The concurrent signal assignment statement is an equivalent process statement that the system generates to assign values to signals If you have several assignments the signal assignments are made all at the same time step concurrently For example data out lt t AND d result lt data out AND carry bit In the preceding example the value for data out evaluates during the same time step as the value for result evaluates Therefore the evaluation for result uses the new value of data out determined by the t AND devaluation More than one iteration is required within
283. may have more than one driver which means the drivers collectively determine the value of the signal If this is the case you must specify what happens to the signal by specifying a resolution You accomplish this by using a resolution function The signal also contains attribute information You use signal attributes to determine information about a signal such as when the last time an event took place or what the last value of the signal was Some signal attributes are actually another signal while others return a value For detailed information on all the predefined signal attributes refer to page 10 28 Figure 11 2 shows the concept of what comprises a signal This figure shows a signal with two drivers Signal E Current Value Driver Driver Attributes Figure 11 2 Composition of a Signal The following subsections elaborate on the preceding topics as well as introduce you to other signal concepts Mentor Graphics VHDL Reference Manual July 1994 11 3 Signals Signal Concepts This subsection discusses the various concepts that apply to signals and their use The following list shows you the topics that are covered e Drivers O Guarded signals registers and buses Disconnection specification Multiple drivers and resolution functions Drivers You use the signal assignment statement to change the value of the projected output waveforms that ar
284. me Longest Static Prefix In the preceding example j is a variable Therefore the expression j is non static The longest static prefix is the static part sname 5 Another example follows Non Static Expression Static Name Longest Static Prefix In the preceding example j and x are variables Therefore the expression x 3 is non static The longest static prefix is the static part sname 3 6 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility Another form of the selected name is the expanded name The expanded name designates one of the following O Primary unit in a design library In this case the prefix designates the library and the suffix is a primary unit simple name which you declare within the library designated by the prefix For example USE design lib and gate e Item declared in a package In this case the prefix designates the package and the suffix is not the reserved word all The simple name character literal or operator symbol declaration you use as the suffix must be declared immediately within the package designated in the prefix All items declared in a package In this case the prefix designates the package and the suffix 1s all e Item declared immediately within a named construct In this case the prefix designates one of the following O Entity O Architecture O Subprogram O Block statement O Process statement O Loop statement The su
285. mes 3 8 Slice Names 3 9 Attribute Names 3 10 Scope and Visibility 3 12 Declarative Region 3 12 Scope 3 13 Visibility 3 16 Overload Resolution 3 24 Mentor Graphics VHDL Reference Manual July 1994 3 1 Naming Scope and Visibility Design Units Design Entities Configurations Packages Attributes Components Types Signals Statements Subprograms Declarations Expressions Lexical Elements Naming Scope and Visibility Naming Scope amp Visibility y Simple Names Selected Names Indexed Names Slice Names Attribute Names Operator Symbols Figure 3 1 Naming Scope and Visibility Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility Naming Your VHDL code must be able to refer to a declared item to act upon it Therefore each declared item must have a name Names formally designate one of the following e Explicitly or implicitly declared items e Subelements of composite objects e Attributes e Objects denoted by access values Here are some examples that show the use of names VARIABLE vcc integer 5 vcc is a simple name test base left test base left is an attribute name To refer to a design item you use the name assigned to that design item Declared items such as design entities packages and procedures are named using the simple name construct In some cases you may want to refe
286. meters of mode in out or inout can be variables Procedure parameters of mode in can be file variables 4 16 Mentor Graphics VHDL Reference Manual July 1994 Declarations Signal Declaration Summary A signal declaration declares an object whose value has a current value a history and a projected value Signal declarations are discussed in detail under signal declaration beginning on page 11 14 Construct Placement block declarative item entity declarative item object declaration package declarative item Syntax signal declaration signal identifier list subtype indication signal kind 2 expression Definitions B identifier list An identifier list is one or more signal names that you provide for each declared object Multiple names must be separated by commas B subtype indication A subtype indication specifies the subtype of the signal s and any resolution function or constraints that apply The subtype must not be a file type or access type B signal kind Valid entries for a signal kind are bus or register B expression An expression defines the initial value of the signal Description A signal declaration specifies the simple names type kind and default value of a signal which is an object that has a current value a history and a projected value Mentor Graphics VHDL Reference Manual July 1994 4 17 Declarations file declaration A file declaration creates a
287. ms of the concurrent signal assignment statement You cannot use a null waveform element on the right hand side of the concurrent signal assignment An error occurs if this is the case e If you use a concurrent signal assignment that has a static target and static waveforms the equivalent process that the system creates includes a wait statement with no sensitivity list This means the equivalent process executes one time during the start of the simulation and suspends action permanently You can use the reserved word guarded or transport or both as options in the concurrent signal assignment statements you use The option guarded controls the execution of the signal assignment through one of the following Mentor Graphics VHDL Reference Manual July 1994 6 23 Statements O An implied guard signal declared through a guard expression on a block O An explicitly declared signal of type boolean that you supply The signal assignment is made when the guard value changes from FALSE to TRUE or when the guard is at a TRUE value and an event occurs on a guard signal input The topic of guarded signals is discussed in detail on page 11 5 When you use the option transport you specify that the signal assignment has transport delay Transport delay means that any pulse is transmitted to the signal with no regard to how short the pulse width or duration The topic of transport delay is discussed in detail on page 11 19 The following
288. must match the type of the interface constant Example The following examples show the interface constant declaration within a portion of code component declaration COMPONI EN GENER T nand2 C prop delay time zs grd integer entity declaration ENTITY c GENER ontroller IS C CONSTANT capac real delay subprogram declaration PROCEDUR interface constant decl E check CONSTANT of Mentor Graphics VHDL Reference Manual July 1994 IN real interface constant decl IN time Fset IN bit 47 IS interface constant declaration 4 25 Declarations interface signal declaration An interface signal declaration declares one or more objects that can serve as ports in design entities ports in component declarations or signal parameters in subprograms Construct Placement port list interface declaration subprogram specification Syntax interface signal declaration signal iden fier list mode subtype indication bus static expression Definitions B identifier list Lists one or more signal names Multiple names must be separated by commas B subtype indication Indicates the subtype of the signal s and any resolution function or constraints that apply The subtype must not be a file type or access type B expression Defines the initia
289. n gt range constraint gt 5 9 interface constant declaration constant identifier list TN KN EN a gt in subtype indication static_expression gt V E E NL n A 40 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary 4 24 interface declaration yinterface constant declaration p interface signal declaration interface variable declaration 4 22 interface list I interface declaration E gt 4 22 interface signal declaration signal identifier list _ mode subtype indication bus static _expression gt 4 26 y AS interface variable declaration variable identifier list gt static_expression gt mode subtype indication 4 29 Mentor Graphics VHDL Reference Manual July 1994 A 41 Syntax Summary condition iteration scheme amp while loop parameter specification gt foro gt 6 36 label identifier P 6 3 letter
290. n and the end of the corresponding full type declaration you can use the name of the incomplete type only as a type mark in the subtype indication of an access type definition No constraints are allowed in the subtype indication 5 32 Mentor Graphics VHDL Reference Manual July 1994 Types The following example shows how an incomplete type declaration is used TYPE dl data IS RANGE 0 TO 255 TYPE dl block IS ARRAY 0 TO 7 OF dl data TYPE dl pntr Incomplete type declaration TYPE dl record IS RECORD data block dl block next rec dl pntr The incomplete type is used here END RECORD The following declaration completes the declaration of dl pntr as an access type to objects of type dl record TYPE dl pntr IS ACCESS dl record Complete type declaration This example declares a record type to hold data in a linked list structure At same time it sets up a pointer that will be used to gain access to the elements of the linked list Notice that the record type for the list elements beginning TYPE dl record IS RECORD consists of two parts an array of integers data block that holds the data and a pointer next rec to the next element of the list The pointer needs to be an access type which can be assigned an access value that points to the location of the next list element
291. n element formal_part gt actual part gt N DA 4 31 association list association element 4 31 attribute declaration attribute identifier gt type mark af 10 54 attribute designator attribute simple name gt 10 3 A 14 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary attribute name attribute specification gt attribute attribute designator static expression 10 3 attribute designator y of gt entity_specification ads expression gt A 10 55 ee M base integer gt 1 17 base specifier KB G XJ Ko WX x gt 1 20 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary base unit declaration identifier gt gt 5 15 based integer extended digit gt 4 1 17 based literal base gt based integer e based integer gt exponent E A
292. n to use to determine the left bound and range of the implied arrays for x and z TYPE ref array2 IS ARRAY natural lt gt OF integer unconst Now that we have determined what the implied arrays for x and z look like we can determine the left bound and range of the array that results from the concatenation of the two implied arrays for x and z The resultant array from the concatenation of the two implied arrays has the range and direction of the index subtype of the implied array of the left operand In the sens 5193 process the left bound of the index subtype of the implied array is 1 and the range is Mentor Graphics VHDL Reference Manual July 1994 2 27 Expressions ascending The elements of the resulting array consist of the left operand elements followed by the right operand elements You can also concatenate items to form a bus The following example shows the initialization of a four bit type called my qsim state vector VARIABLE a bus my qsim state vector 0 TO 3 variable decl 0 amp 1 Z X Assign initial values NOVAK or do it this way a bus a bus In the preceding example the four bits are concatenated to form a bus There is a natural inclination to assign a bus without using the amp operator or by using single quotes creating an illegal condition as follows a bus Ol1ZX illegal condition Shift Operators S T
293. nally all the rules and further information about the topic are discussed This manual is designed to be the companion to the Mentor Graphics Introduction to VHDL The introduction manual covers the major topics of VHDL in an overview method without going into all the rules on a given construct Therefore there is an overlap of information between these two manuals To tie all the sections of this manual into the language as a whole a pyramid such as the one shown in the following illustration appears at the beginning of each section This illustration shows you where in the language the topic of a given section belongs and gives some details about the section topic Mentor Graphics VHDL Reference Manual July 1994 xvii About This Manual Notational Conventions This subsection describes the conventions used throughout this manual for language syntax and the graphical syntax diagrams For information about general documentation conventions refer to Mentor Graphics Documentation Conventions item item A syntax diagram item shown in boldface text is a reserved word For example entity and is in the following BNF description are reserved words Also see the subsection titled BNF Syntax Description Method on page xix entity entity simple name is entity header entity declarative part begin entity statement part end entity simple name A lowercase monospaced item in a pr
294. nalysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the default value is one 1 Result Type 1 1 1 1 1 1 1 1 1 0L 0 universal integer Evaluation Result The result is the number of values within the index range specified by the parameter The following is the algebraic expression for length n length n high n low n 1 If you specify a prefix that designates a null array the evaluation result is zero Mentor Graphics VHDL Reference Manual July 1994 10 15 Attributes Example The following example shows an attribute portion of a code description TYPE arr 1 IS ARRAY integer RANGE lt gt OF integer VARIABLE matrix arr 1 1 TO 3 9 DOWNTO 6 array var decl matrix length 1 parameter n is 1 Returned value is 3 Since the parameter n is 1 the boxed column is examined T INDEX 9 8 7 6 Caec pc RU 1 2 gt 3 The value that returns is 3 which is the number of values within the specified parameter 1 The return value is determined by substituting values in the algebraic expression as the following example shows length 1 high 1 low 1 1 length 1 2 3 141 length 1 3 10 16 Mentor Graphics VHDL Reference Manual July 1994 Attributes low n Kind 0 0 Function Prefix gt
295. nc i 1 THEN suml NOT suml Compute parity for ram data END IF IF op code conc i 1 THEN sum2 NOT sum2 Compute parity for op code data END IF END LOOP RETURN suml sum2 Return true if parity matches false END chk pty if parity does not match 7 12 Mentor Graphics VHDL Reference Manual July 1994 Subprograms Subprogram Calls A subprogram call causes the execution of a procedure or function and specifies the parameter passing conventions if parameters exist The function call is an expression while the procedure call can be a sequential or concurrent statement To call a subprogram use one of the following methods Positional parameter notation Named parameter association notation e Default parameters You also use these methods for generic and port association For more information on this topic refer to page 4 31 To illustrate the three subprogram calling methods the following discussion refers to the following specification PROCEDURE examine data my part IN string read data OUT bit vector 0 TO 23 prop delay IN time 1 ns Positional parameter notation is the most common method for calling a subprogram In this method the parameters you specify in the call must match the order of the parameters in the subprogram Using the example specification for examine data the following example shows a positional parameter call ex
296. nce Manual e System 1076 Design and Model Development Manual provides concepts procedures and techniques for using VHDL within the System 1076 environment e System 1076 Error Message Manual contains information about the error and warning messages generated when compiling and simulating System 1076 models e AutoLogic VHDL Reference Manual defines the syntax of VHDL constructs used for logic synthesis and describes their resultant implementations after synthesis by AutoLogic VHDL e AutoLogic VHDL Synthesis Guide describes using VHDL within the synthesis environment the coding guidelines for writing VHDL code that can be synthesized and the operating procedures for running AutoLogic VHDL e BOLD Browser User s Manual describes the BOLD Browser and covers basic operations such as locating and viewing online information Design Architect Reference Manual contains information about the functions used to create and modify schematic and cabling designs logic symbols and VHDL source files e Design Architect User s Manual provides a basic overview of Design Architect key concepts for using the Schematic Editor Symbol Editor and VHDL Editor and design creation procedures Digital Modeling Guide contains basic information for designers and modelers using the Mentor Graphics digital analysis environment This manual can help you make some rudimentary decisions in model or design development e Digital Simulators Reference Manu
297. nd Visibility n ARCHITECTURE SIGNAL BEGIN PROCESS VARIABLE PROCEDURE BEGIN END BEGIN END PROCESS END Figure 3 3 Scope Figure 3 4 shows that even though the architecture body can be stored and evaluated in a file separate from the entity declaration an item declared in the entity declaration such as signa11 is visible throughout region C An item declared in a package header is visible to the package header and the package body Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility SIGNAL1 END enl ENTITY enl IS In File entity1 hdl ARCHITECTURE SIGNAL2 BEGIN al OF enl IS In File arch1 hdl PROCESS ds VARIABLE PROCEDURE BEGIN END BEGIN END PROCESS UN a END a1 Figure 3 4 Scope of Entity Plus Architecture Scope Rules The scope rules discussed in this subsection are valid for all declaration forms implicit or explicit Immediate scope is the scope of a declaration that is directly within a declarative region Table 3 1 lists the cases in which a declaration extends beyond its immediate scope Mentor Graphics VHDL Reference Manual July 1994 3 15 Naming Scope and Visibility Table 3 1 Immediate Scope Exceptions
298. nd a string literal with only one item is their type A character literal is of the type character and a string literal is type string Therefore you cannot mix the types when you perform operations on the literals For example VARIABLE x character Declare x of subtype character x a Assign x the string literal a The types are not the same therefore this code is not legal Bit String Literals Bit string literals are strings of extended digits enclosed by double quotes with a prefix of a base specifier Bit string literals represent binary octal or hexadecimal numbers The following diagram shows the related syntax of the bit string literal bit string literal base specifier bit value base specifier BIOIXIblolIx bit value extended digit extended digit 1 20 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements There are three valid base specifiers for bit string literals e B specifies that the extended digits are restricted to the binary number system 1 and 0 O specifies that the extended digits are restricted to the octal number system 0 1 2 3 4 5 6 7 e X specifies that the extended digits are restricted to the hexadecimal number system 0 1 2 3 4 5 6 7 8 9 a b c d e f The base specifiers B O and X can be uppercase or lowercase You cannot place a space between the base specifier and the b
299. nd xor can be in a sequence For example IF a AND b AND c d AND e AND f THEN You cannot write an expression using the logical operators nand and nor in a sequence because these operators are not associative For example IF a NAND b NAND c d NAND e NAND f THEN Illegal sequence Mentor Graphics VHDL Reference Manual July 1994 Expressions To mix the associative logical operators you must use parentheses For example IF a AND b OR c d AND e OR f THEN Mix logical operators Logical operators are discussed in detail on page 2 31 The operand types and the operator determine the expression type The following example shows this concept VARIABLE test real 5 0 variable declarations VARIABLE check real 5 5 The following expression appears later in a description answer test check In the preceding example the expression test check is of type real because the operand types are real When you use an overloaded operand the operand type is determined by the context in which it appears When you use an overloaded operator the operator identification is also determined by the context For more information on overload resolution refer to page 3 24 If you enclose an expression in parentheses you can use it as an operand Operands are described in the following subsecti
300. nent Binding 8 23 Component declarations 4 35 4 36 Component declarations overview 8 21 Component Instantiation 8 22 Component instantiation statement 6 17 Components 8 20 Composite types 5 22 Compound delimiter 1 22 Concatenation operator 2 23 Concatenation of arrays 5 28 Concatenation of string literals 1 19 Concatenation to form a bus 2 28 Concurrency difference between sequential 6 2 Concurrent Assertion Statement 6 19 Concurrent procedure call statement 6 21 Concurrent signal assignment statement 6 23 Concurrent statements 6 7 Block 6 12 Component instantiation 6 17 Concurrent assertion 6 19 Concurrent procedure call 6 21 Concurrent signal assignment 6 23 Process 6 41 Index 1 Index INDEX continued Condition In a next statement 6 38 In a wait statement 6 50 In an assertion statement 6 10 In an exit statement 6 28 In an if statement 6 34 Conditional signal assignment 6 25 Conditional statements 6 6 Configuration specification 8 25 Constant declarations 4 13 Constants deferred 4 14 Constrained array 5 25 Constraint Index 4 8 Range 4 8 5 5 Context clauses 9 5 Context of overload resolution 3 24 Conversion functions type 4 37 Data flow description 8 15 Decimal literal 1 16 Declaration definition of 4 1 Declarative region 3 12 Default binding indication 8 33 Default expression for signals 11 15 Deferred constants in constant declarations 4 14
301. nfigurations continued architecture statement part Components Component Declarations Component Instantiations Component Binding configuration specification binding indication entity aspect Generic and Port Map Aspects Default Binding Indication Configurations configuration declaration block configuration component configuration Section 9 Design Units and Packages Design Unit Overview context clause library clause Example of a Design Library Packages package declaration package body Predefined Packages Package Standard std logic 1164 std logic 1164 ext Package Textio Mentor Graphics Predefined Packages std math mgc portable qsim logic UM NO CA 4 0 b2 NO UA OU O 00 Qo 00 QO OO OO QO CO OO QO CO QO CO 90 OO BRWWWWWWNNNNNN 9 9 2 9 9 8 9 10 9 12 9 13 9 15 9 18 9 18 9 2 9 26 9 30 9 33 9 34 9 36 viii Mentor Graphics VHDL Reference Manual July 1994 Table of Contents TABLE OF CONTENTS continued Section 9 Design Units and Packages continued mgc portable qsim relations Section 10 Attributes Attribute Overview attribute name Predefined Attributes Detailed Predefined Attribute Description Array Object Attributes high n Jeft n length n low n range n reverse_rangel n right n Block Attributes behavior structure Signal Attributes active delayed t event last active last event last value quiet t st
302. nit into a library You can think of a package as a container for collecting various commonly used declarations and subprograms The following ordered list shows the topics and constructs described in this section Design Unit Overview 1 92 context clause os library clause 9 8 Example of a Design Library 1 910 Packages 1 Oa package_declaration___ AAA 9 13 package body S 0 5 Predefined Packages OIB Package Standard 1 1 9 18 Figure 9 1 shows where design units and predefined packages belong in the overall language and shows which items are described in this section Mentor Graphics VHDL Reference Manual July 1994 9 1 Design Units and Packages __ Design Units gt Design Entities Configurations Packages lt Attributes Components Types Signals Statements Subprograms Declarations Expressions Lexical Elements Naming Scope and Visibility Design Units Y Context Clause Design Libraries Packages Y Package Declaration Package Body Predefined Packages Figure 9 1 Design Units and Packages Design Unit Overview Certain VHDL language constructs can be independently stored and analyzed These constructs are called library units Library units fall into two categories O Primary units O Entity declaration O Configuration declaration O Pa
303. nsmitted to the signal name you specify This type of delay is characteristic of switching circuits For more detailed information on transport and inertial delay refer to page 11 19 The evaluation of the waveform elements determines the future behavior of the drivers for the target you specify The waveform element takes two forms Assign the target a specific value at a specified time e Specify that the target is turned off after a specified time If you specify time expressions in the waveform element these delay times must use the time units from package standard If you do not specify a time expression the default is zero nanoseconds A time expression must not evaluate to negative number It is an error if the target of the signal assignment is not a guarded signal and you assign the target a null waveform turn off the signal For more information on guarded signals refer to page 11 5 Example The following examples show possible signal assignments clk lt 1 AFTER 100 ns clk gets 1 after time specified clock lt GUARDED NULL AFTER 100 ns Clock turned off after time specified clock must be a guarded signal result lt a OR b OR c result gets expression value in 0 ns wire lt TRANSPORT 5 AFTER 25 ns Transport delay after time This assignment includes a series of waveform elements clk lt 1 AFTER 1 ns 07 AFTER 2
304. nstrained Array Of The Same Type S nmm Unconstrained Array i Constrained Array Of The Same Type Figure 5 3 Unconstrained Arrays Summary of Array Type Rules The following list is a summary of the rules that govern the use of arrays All the elements in an array must be of the same type The element types in an array can be only scalar other array types or record types no file types are allowed If you use a subtype indication as a discrete range the subtype indication must not contain a resolution function For information on resolution functions refer to page 11 10 You use index constraints for arrays and you use range constraints for subtypes Mentor Graphics VHDL Reference Manual July 1994 5 27 Types Array Operations There are several operations you can perform using arrays through the use of expressions and specific array operations You can extract a single array element by specifying an index value in an expression You specify an index by using an indexed name For more information on indexed names refer to page 3 8 You can compare two arrays of the same type with relational operators For more information on expressions and operators refer to Section 2 You can concatenate one dimensional arrays to form larger one dimensional arrays as the following example shows PROCESS sens sig
305. nt physical and enumeration types Composite array types and records e File files Each type attribute has a prefix that corresponds to one of three type classes As is the case with array type attributes type attributes deal with direction It is important to understand the relationship between left right low and high between attributes When using a range of items you can specify two directions Ascending using the reserved word to Descending using the reserved word downto 10 40 Mentor Graphics VHDL Reference Manual July 1994 Attributes In the following example TYPE test integer IS RANGE 5 TO 4 type test integer is any of the following integers 5 4 3 2 10 1234 ascending where the left most integer 5 is equal to low and the right most integer 4 is equal to high In the following example TYPE next integer IS RANGE 4 DOWNTO 5 type next integer is any of the following integers 43210 1 2 3 4 5 descending where the left most integer 4 in this case is equal to high and the right most integer 5 is equal to low The following table summarizes type attribute direction relationships Range Ascending Range Descending Constraint Range Bound Left most Lowest value Highest value Right most Highest value Lowest value Lowest Left most value Right most value Highest Right most value Left most value
306. nts ys ils Character Set J 0 PA Ss i K A fj gp Ll SL Lexical Elements Language Constructs SS A v Design Units EL fus N Code po En SA ya Figure 1 2 Lexical Element Use Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements Character Set Before you can use the lexical elements you must know the character set allowed in VHDL There are 95 printable ASCII graphic characters and 5 format effectors that you can use in VHDL The graphic characters consist of the following e letter uppercase ABCDEFGHIJKLMNOPQRSTUVWXYZ lowercase abcdefghijklmnopqrstuvwxyz O digit 0123456789 special characters Figure 1 3 shows the special characters special characters Y N K Y i y Y N Y Y No 4 Y x Y N y w eH RECO SP cer Ie umo erm T S 1 PA N de NES N p P A Y YN Y Y Y Y pa NY Y z Y N y Oi PE oS N T P S 7 A S we PA in SS 7 P Y v v v Y vy v Y JA3053 L CI G5 GN US Figure 1 3 Special Characters Syntax Mentor Graphics VHDL Reference Manual July 1994 1 5 Lexical Elements There are five format effectors used in VHDL A format effector is a non printable control character you use to format the ASCII text in your source file The following list shows the VHDL format effectors e Tab e Vertical tab O Carriage return e Line feed e Form feed R
307. nts to build the structure automatically by replication Beside being more efficient for large structures the latter approach is more flexible since you can make the structure entirely configurable by using generics to specify its size The following example generates a 16 line to 8 line data selector by repeating a basic 2 line to 1 line multiplexer eight times The generate statement labeled G1 not only repeats subsections of the multiplexer but maps all the inputs and ouputs automatically The generate parameter I takes on each value in the discrete range 0 to 7 and the port mapping uses that parameter to map individual input and output bits to individual sections of the multiplexer The single select input dse1 is connected in parallel to the se1 ports of all the individual multiplexers Design entity for a 16 line to 8 line data selector ENTITY muxl6to8s IS PORT dsel IN bit dinl IN bit vector 0 to 7 din2 IN bit vector 0 to 7 dout OUT bit vector 0 to 7 END mux16to8 Architecture for muxl6to8 ARCHITECTURE gen8 OF muxl6to8 IS COMPONENT mux2 Basic 2 input mux PORT a b sel IN bit y OUT bit END COMPONENT BEGIN Instantiate 8 copies of the basic mux Gl for I in 0 to 7 GENERATE Mx mux2 PORT M
308. nts that apply B expression Defines the initial value of the constant Description The interface constant declaration specifies the following interface objects Constants that appear as generics in entity or component declarations e Constants that are parameters in subprograms The following list summarizes the rules for using the interface constant declaration You can optionally use the reserved word constant at the beginning of the interface constant declaration A generic is a constant therefore using the reserved word constant is purely for documentation and understandability If the constant is a subprogram parameter you may or may not want to use constant This issue is discussed in detail on page 7 8 4 24 Mentor Graphics VHDL Reference Manual July 1994 Declarations You can optionally use the reserved word in to indicate the mode for the constant Again this is purely for documentation if the constant is a generic If the constant is a subprogram parameter you may or may not want to use in This issue is discussed in detail on page 7 8 The subtype indication must not be a file type or access type For each interface constant you can specify a default value using the optional default expression followed by a static expression This expression assigns the constant a value when it is not otherwise given value within a design such as by association through a generic map The type of the expression
309. nual July 1994 Syntax Summary use clause puse selected name ZEN OS gt variable assignment statement target gt expression gt ae 6 48 ES variable declaration variable gt identifier list gt subtype indication Nou E p expression gt gt wait statement wait sensitivity clause condition clause timeout clause 27 gt 6 49 Mentor Graphics VHDL Reference Manual July 1994 A 67 Syntax Summary waveform gt gt waveform element x X A 6 46 J gt aL waveform element yalue expression after gt ime expression null after time expression gt 6 46 A 68 Mentor Graphics VHDL Reference Manual July 1994 Locating Language Constructs Appendix B Locating Language Constructs This appendix describes two methods for assisting you in the location of the VHDL language constructs The following list shows these methods e The major language construct tree e The vscan VHDL scan script The major language construct tree starting on page B 3 shows you where you can use the language constructs that you use often and that form the basic foundation of VHDL This tree corresponds to the major languag
310. o an integer type object Detailed information on type conversion begins on page 2 12 5 2 Mentor Graphics VHDL Reference Manual July 1994 Types VHDL has a mechanism for you to determine information about the characteristics attributes of a type such as the upper or lower bound or the value at a position This mechanism is the predefined attribute AII the predefined attributes are described beginning on page 10 5 Figure 5 1 shows where types belong in the overall language and the categories of types that are discussed in this section 7 dd E Design Units Design Entities Configurations Packages Attributes bec Types Statements Components Signals Subprograms Declarations Expressions Lexical Elements Naming Scope and Visibility TYPES Y i Y y FILE SCALAR COMPOSITE ACCESS Array Record Yr oy yy Integer Floating Point Physical Enumeration Figure 5 1 Types Mentor Graphics VHDL Reference Manual July 1994 Types scalar type definition A scalar type definition creates a template for an object that can take on scalar values A scalar value is one that cannot be subdivided and that can be ordered along a single scale Construct Placement type definition type declaration block declarative item entity declarative item package bod
311. object value may be updated but not read Mode inout The interface object may be read and updated Mode buffer The interface object may be read but updated by at most one source Any associated actual may have at most one source 4 22 Mentor Graphics VHDL Reference Manual July 1994 Declarations Mode linkage The interface object may be read and updated but only by appearing as an actual corresponding to an object of mode linkage If you do not specify a mode in is the default mode that the system uses The interface constant declaration can be only of mode in For each interface object you can specify a default value using an optional default expression This expression consisting of the symbol followed by a static expression assigns the expression value to an interface object if that object is not otherwise given a value within a design The type of the expression must match the type of the interface object The default expression cannot be used with an interface object that is a file type or cannot be used when the mode of the object is linkage e Interface objects are associated with other objects in the design environment through an association list The association list establishes actual communication paths between separate portions of a design For more information on this topic refer to page 4 31 The following subsections describe each kind of interface declaration in detail Example lt The foll
312. ocess declarative item Location of Syntax For More Diagram Information A 44 9 8 A 45 2 31 A 45 6 36 A 45 2 18 A 46 4 22 A 46 2 20 A 47 3 3 A 47 6 38 A 47 6 39 A 47 1 15 A 48 4 10 A 48 7 6 A 48 6 23 A 49 9 15 A 49 9 15 A 49 9 15 A 50 9 13 A 50 9 13 A 51 9 13 A 51 6 36 A 51 1 16 A 51 5 15 A 51 8 8 A 51 8 8 A 52 8 32 A 52 3 5 A 52 2 6 A 53 9 3 A 53 6 40 A 54 6 41 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary Table A 1 VHDL Construct Listing continued Location of Syntax For More Language Construct Diagram Information process declarative pat A 54 64l process statement 1 1 1 1 1 1 A 55 644 process statement part 1 A55 64l qualified_expression A 55 2 10 range 56 range constraint A 56 record type definition A 9560 5 29 rela ion 1 1 1 A 5956 24 relational_operator_____________A37_______ 228 return statement 1 1 1 1 1 A 57 6 44 scalar type definition 1 1 1 1 A 57 544 secondary unit A 58 93 secondary_unit_declaration_________A 38______ 5 15 selected name 1 1 1 1 A 8 3 5 selected signal assignment A 58 6 27 selected waveforms A 8 6 27 sensitivity clause A 8 6 49 sensitivity_list_z___________A39______ C4 sequence of statements 1 A 59 6 15 sequential statement ____
313. ock configuration _ rend for gt 8 43 A 20 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary component declaration component identifier gt local generic clause local port clause gt end component k gt 3 4 36 component instantiation statement gt instantiation label component name generic map aspect T port map aspect gt Nc 6 17 component specification instantiation list gt A component name gt 8 25 composite_type_definition array type definition record type definition 5 22 PAS concurrent assertion statement label assertion_statement gt 6 19 Mentor Graphics VHDL Reference Manual July 1994 A 21 Syntax Summary concurrent procedure call label gt y procedure call statement 6 21 concurrent signal assignment statement LR gt label gt conditional signal assignment RU S selected signal assignment S gt 6 23 concurrent statement block statement
314. ogic vector RETURN BOOLEAN FUNCTION IS X s std logic vector RETURN BOOLEAN FUNCTION IS X s std ulogic RETURN BOOLEAN e lt D std logic 1164 Mentor Graphics VHDL Reference Manual July 1994 9 25 Design Units and Packages std logic 1164 ext S The IEEE 1164 extensions package contains declarations of types and subprograms that support a standard nine state logic system This package is located in the ieee library File name std logic 1164 ext header pkg vhdl Title STD LOGIC 1164 EXTENSIONS package multivalue logic system Library Author s MENTOR GRAPHICS CORPORATION Purpose This packages defines a standard for digital designers to use in describing the interconnection data types used in modeling common ttl cmos GaAs nmos pmos and ecl digital devices Notes The logic system defined in this package may be insufficient for modeling switched cc transistors since that requirement is out of gt the scope of this effort gt No other declarations or definitions shall be included in this package Any additional declarations shall be placed in other orthogonal packages ie timing etc Modification History Version No
315. ogram example is a user specified item See the following code example This font is also used in text when referring to specific items from a program example such as the name counter circuit in the following code example An uppercase monospaced code item in a program example is a reserved word In the following example ENTITY and rs are reserved words ENTITY counter circuit IS PORT a IN bit vector 0 TO 3 c OUT bit vector 0 TO 1 END counter circuit prefix item The italic prefix preceding an item provides supplemental xviii information on the construct item prefix item is not considered a language construct For example time expression indicates a construct called expression that is used for expressing time Mentor Graphics VHDL Reference Manual July 1994 About This Manual BNF Syntax Description Method BNF Backus Naur Format is another method used in this manual to describe the syntax of the VHDL language The following example shows a BNF method of showing the syntax of a given construct example construct construct one construct one construct two construct three reserved word Certain characters represent specific meaning when reading the BNF syntax description The combination of characters on the first line of the BNF description separates the subject such as example construct from the description O regular text Tex
316. ollowing is an example of concatenation in which only one operand is a one dimensional array PROCESS sens sig2 TYPE ref array IS ARRAY positive RANGE OF integer VARIABLE vector ref array 5 TO 9 size is 5 VARIABLE next array ref array 6 DOWNTO 1 size is 6 BEGIN next array vector amp 3 Concatenate vector with 3 END PROCESS The concatenation operation and the value of next array from the preceding sens sig2 process is equivalent to the following 5 6 7 8 9 3 vector amp 3 5 6 7 8 A 10 3 resultant array from concatenation 6 5 4 3 2 1 next_array One way to encounter a null array like null_array is if the range is reversed in this case typing TO instead of DOWNTO in the array variable declaration in the sens sig1 process Mentor Graphics VHDL Reference Manual July 1994 2 25 Expressions The resultant array created by the concatenation of a one dimensional array with an array element has the range and direction of the index subtype of the left operand In the sens sig2 process the resulting array uses an ascending direction as specified in the left operand vector declaration VARIABLE vector ref array 5 TO 9 The left bound of the resulting array is the left bound of the index subtype of th
317. olor leftof green Restrictions 0 0 0 0 0 The specified parameter x cannot be equal to the left bound of the base type An error occurs if you try to examine an item to the left of the left most item Mentor Graphics VHDL Reference Manual July 1994 10 45 Attributes low Kind Value Prefix Any scalar type or subtype Result Type The same type as the prefix type Evaluation Result The result is the lower bound of the specified prefix type Example The following code defines address_range TYPE address_range IS RANGE 2 L3 16 DOWNTO 0 The following code returns the value 0 which is the lower bound of address range address range low 10 46 Mentor Graphics VHDL Reference Manual July 1994 Attributes pos x Kind Function Prefix 0 0 0 00 0 00 0000000000 Any enumeration integer physical type or subtype Parameter The value for the parameter x must be of the same base as the specified prefix Result Type universal integer Evaluation Result The result is the position number of the item specified by the parameter x Example The following code defines the enumerated type color TYPE color IS red yellow green flash The following returns the integer 2 which is the value of the position of green color pos green The position number for an enumerated type is
318. on Mentor Graphics VHDL Reference Manual July 1994 2 5 Expressions Operands Primaries An operand or primary has a value and a type it is a quantity on which an operator performs an operation The following BNF description lists all the valid primaries primary name literal aggregate function call qualified expression type conversion allocator expression Following subsections discuss all of these items in their roles as primaries These items are also discussed in other sections of this manual in relation to their other functions within the language Please consult the index or text references for the locations of these discussions Names When you use a name as an operand in an expression it must be one of the following items The name of an attribute that returns a value O A name that identifies an object or value The value of a operand is the value of the object For more information on objects refer to page 4 10 Names are discussed in detail beginning on page 3 3 The following example shows the use of names in expressions 2 6 Mentor Graphics VHDL Reference Manual July 1994 Expressions decade multiplier freq in freq out x and z are names that identify objects info identifies a type PROCESS CONSTANT decade integer 10 VARIABLE multipl
319. on O 4 3 variable_declaration AA 45 Signal Declaration Summary 417 file_declaration 48 Interface Declarations 4 2 interface list _ 4D interface_constant_declaration lt 4 24 interface signal declaration 4 26 interface variable declaration 1 1 1 1 4 29 association 115 4 3 alias declaation 485 component declaration 1 4 36 Type Conversion Functions AAA 4 37 Section 5 A scalar type definition AAA Y 54 range constraint 5 5 integer type definition 5 9 Predefined Integer Types 5 11 floating type definition 5 12 Predefined Floating Point Types 5 14 physical_type_definition 5 15 Predefined Physical Types 5 18 enumeration_type_definition 5 19 Predefined Enumeration Types 5 21 composite_type_definition 5 22 Mentor Graphics VHDL Reference Manual July 1994 V Table of Contents TABLE OF CONTENTS continued Section 5 Types continued array type definition 5 22 Summary of Array Type Rules 5 27 Array Operations AA 5 28 record_type_definition 5 29 access_type_definition 5 31 Incomplete Types 5 32 file_type_definition 5 34 Section 6 Statements 0 0 0 0 0 0 6l Statement Classes AA 062 sequential statement 8 5 concurrent statement 8 7 Statement Quick Reference __ CB assertion_statement 1 1 lt 6 10 block 5 6 12 case_statement 6 15 component instantiation statement 1 6 17 concurrent assertion statement 1 1 1
320. on of two different subtypes the declaration of two variables and an example of an intermediate calculation using the different subtypes This calculation is legal because the 4 8 Mentor Graphics VHDL Reference Manual July 1994 Declarations operations are performed on items that have the same base type which is integer When you make the assignment a range check is made to determine if the calculation result is in the range of the subtype of the target Here are some rules and additional information about the subtype declaration The subtype indication designates what restrictions are placed on the subtype you declare When you use the optional resolution function name every declared signal of the specified subtype is resolved by this function The resolution function name is only for signal objects with no effect on other item declarations A subtype indication designating a file type or access type must not use a resolution function For more information on resolution functions refer to page 11 10 When you use a constraint in the subtype indication it must be compatible with any constraint implied by the type mark Range constraints are discussed on page 5 5 Index constraints are discussed starting on page 5 23 The type mark designates a type or subtype In the following subtype declaration the type mark is integer SUBTYPE result IS integer RANGE 1 TO 20 Mentor Graphics VHDL Reference Manua
321. on specification o use clause 8 10 Mentor Graphics VHDL Reference Manual July 1994 A 31 Syntax Summary entity declarative part entity declarative item gt 8 10 entity designator gt simple_name Operator symbol S gt 10 55 ES N entity header formal generic clause formal _port_clause gt 8 6 entity name list gt entity_designator pOthers gt 10 55 fe ES entity_specification gt entity_name_list gt entity class 2 eS 10 55 A 32 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary entity statement concurrent assertion statement passive concurrent procedure call gt passive process statement 8 12 entity statement part entity statement gt 8 12 enumeration_literal identifier character literal 5 19 enumeration type definition gt Q 4 enumeration literal A ya 5 19 exit_statement exit loop label Vana when ha condition EA i 6 28
322. ondition TYPE my result IS RANGE 0 5 TO result Bound not loc static In the preceding example the right or high range constraint bound is the variable result Which has been declared previously in the same design unit Therefore result is not a locally static expression and is not legal as a range constraint bound You can use all floating point types with the appropriate predefined arithmetic operators For information on operators refer to page 2 16 If an arithmetic operation result is not a floating point type in the range specified an error occurs For example PROCESS VARIABLE f z real RANGE 1 0 TO 100 0 BEGIN f 10 0 z f 1988 0 error condition WAIT FOR 10 ns END PROCESS In the preceding example the arithmetic operation z f 1988 0 results in a value which is not in the specified range for z Therefore a run time error condition exists when the assignment to z occurs during simulation The following examples show some typical uses of floating point types from within VHDL code TYPE result IS RANGE 0 0 TO 11063 5 SUBTYPE p_result IS result RANGE 2765 88 TO 8297 63 VARIABLE a b c result CONSTANT offset p result 3000 5 Mentor Graphics VHDL Reference Manual July 1994 5 13 Types Predefined Floating Point Types Type real is
323. ons the parameter is indicated by a letter set off in parentheses which are required and in some cases brackets which are not used in the code If you do not provide a value for a parameter it assumes a default value Result Type This subsection discusses the resulting type after evaluating the attribute Evaluation Result This subsection discusses the results of the attribute evaluation Example 3 5 5 A3 0 c o This subsection contains an example for using the attribute and the results after evaluation Restrictions This subsection discusses any restrictions that apply to the attribute Mentor Graphics VHDL Reference Manual July 1994 10 7 Attributes Array Object Attributes You use array object attributes for passing array parameter information to other arrays such as unconstrained arrays Aan important concept to keep in mind when using array object attributes is that the evaluation results are the bounds of the array not the contents of the array For more information on array types refer to page 5 22 For this subsection one array is used for the examples This array is called matrix as the following code shows TYPE arr 1 IS ARRAY integer RANGE lt gt OF integer VARIABLE matrix arr 1 1 TO 3 9 DOWNTO 6 array var decl The preceding line of code creates a 3 by 4 two dimensional array The following is a representation of this array 1
324. ons show you how to declare types subtypes objects files interfaces aliases and components The following list shows the pages were you can find information on the remaining declarations e Entity declaration page 8 4 Subprogram declaration page 7 6 Package declaration page 9 13 Attribute declaration page 10 54 To determine where you can make a particular declaration refer to Appendix B This appendix contains a diagram showing all the declarations in relation to the major language constructs Mentor Graphics VHDL Reference Manual July 1994 4 3 Declarations type declaration A type declaration specifies a template or skeleton for objects that includes a set of values and a set of operations Construct Placement declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax type declaration full type declaration incomplete type declaration full type declaration type identifier is type definition incomplete type declaration type identifier type definition scalar type definition composite type definition access type definition file type definition Definitions B identifier A name that you provide for the type B type definition Specifies one of four classifications which are described in Section 5 4 4 Mentor Graphics VHDL Reference Manual
325. onstraint in which each index subtype of the corresponding array type is locally static Each discrete range is locally static Locally static array subtype a constrained array subtype that is formed by restricting an unconstrained array type using a locally static index constraint Ranges are discussed on page 5 5 scalar types are discussed on page 5 4 and arrays are discussed on page 5 22 2 34 Mentor Graphics VHDL Reference Manual July 1994 Expressions Table 2 8 Global Static Operands Globally Static Rules For the Globally Static Operand Operand Locally static Any locally static operand is considered a globally operand static operand Constant Deferred and generic constants are allowed Constants must be declared with globally static subtype Predefined Must be an attribute of a globally static subtype that is attribute a value range or a function with actual parameters that are globally static Function call The function name must designate a predefined operator Actual parameters must be globally static Qualified The type mark must designate a globally static subtype expression The operand must be a globally static expression Globally static May be enclosed by parentheses expression Aggregate Must have a globally static subtype and its element associations can contain only globally static expressions In this manual several items are defined as being globall
326. oop iteration Procedure control statements These statements provide you with a method of controlling subprogram execution The statements include the following O Procedure call statement O Return statement e Miscellaneous statements These statements include O Assertion statement O Null statement 6 6 Mentor Graphics VHDL Reference Manual July 1994 Statements concurrent statement Concurrent statements define blocks and processes that are connected together to describe the general behavior or structure of a design You can think of concurrent statements as processes that exist in parallel waiting for a specified condition to be satisfied before executing Construct Placement architecture statement part block statement part Syntax concurrent statement block statement process statement concurrent procedure call concurrent assertion statement concurrent signal assignment stmnt component instantiation statement generate statement Description lt 0 0 You use the block statement to group together other concurrent statements The main concurrent statement is the process statement which defines a sequential operation representing a part of the design The remaining concurrent statements except for the component instantiation statement provide you with a shorthand method for specifying processes that commonly occur These statements use an implied process that is automatically created b
327. or IS ARRAY NATURAL RANGE lt gt OF std ulogic resolved or SUBTYPE std ulogic resolved and IS std ulogic wired and std ulogic TYPE std ulogic resolved and vector IS ARRAY NATURAL RANGE lt gt OF std ulogic resolved and Overloaded Logical Operators FUNCTION and 1 std ulogic RETURN std ulogic FUNCTION nand 1 r std_ulogic RETURN std_ulogic ao FUNCTION or 1 Y std ulogic RETURN std ulogic FUNCTION nor 1 r std ulogic RETURN std ulogic FUNCTION xor 1 r std ulogic RETURN std ulogic FUNCTION not 1 std ulogic RETURN std ulogic Mentor Graphics VHDL Reference Manual July 1994 9 27 Design Units and Packages gt Vectorized Overloaded Logical Operators FUNCTION and 1 r std ulogic vector RETURN std_ulogic_vector FUNCTION nand 1 r std_ulogic_vector RETURN std_ulogic_vector FUNCTION or l r std ulogic vector RETURN std_ulogic_vector FUNCTION nor 1 r std_ulogic_vector ne RETURN std ulogic vector FUNCTION xor l r std ulogic vector zz RETURN std ulogic vector FUNCTION not 1 std ulogic vector gt RETURN std_ulogic_vector Overloaded Relational Operators FUN
328. or a procedure As a guideline you use a function to calculate and return one value and you use a procedure to define an algorithm that describes a behavior Table 7 1 shows the comparison between functions and procedures to assist you in determining which subprogram to use Table 7 1 Comparison of Functions and Procedures Functions Procedures One value is always returned Multiple values returned as parameters or no value is returned Formal parameter mode must be in Parameter mode can be in out or The parameter object class can bea inout The parameter object class constant or a signal can be a constant signal or variable Called within an expression Called by a sequential or concurrent statement Must use the reserved word return The reserved word return is not and provide an expression to return required No side effects allowed Side effects are possible A side effect refers to the execution of a subprogram that produces a change in an object value outside of the subprogram Mentor Graphics VHDL Reference Manual July 1994 7 3 Subprograms The following example is also discussed in the Mentor Graphics Introduction to VHDL Itis used in this manual to explain in detail the items that compose a subprogram The example is a high level description of a memory programming and testing device without regard to implementation details such as control lines The following list con
329. or easier reading The following examples show valid integer literal values 0 14e3 27E2 2e2 34e 7 91 432_198 The following examples show valid real literal values 17 0 23 65e 10 87 1E3 7 616 11 0 0 0 1426 Based literals are abstract literals in which you can specify the numeric base The base you specify must be in the range of base 2 to base 16 inclusive The following diagrams shows the related syntax for a based literal based literal base based integer based integer exponent base integer based integer extended digit extended digit extended digit digtl AI BICIDIEIFlalblclidlelf The character must enclose the based integer The optional underline character in the based integer has no effect on the value of the literal This character is used to group digits for readability The exponent is always base 10 Mentor Graphics VHDL Reference Manual July 1994 1 17 Lexical Elements An extended digit is a hexadecimal digit The letters A through F in the extended digit represent the digits 10 through 15 These letters can be uppercase or lowercase Within a based integer the extended digits must be a value less than the base For example 2 1101_A1B1 is not allowed because the base is 2 Therefore the extended digits A and B are illegal The following are examples of valid integer literals using different bases
330. or the first literal active and ascending to position 2 for flashing Position is important when Mentor Graphics VHDL Reference Manual July 1994 5 19 Types using the predefined attributes For more information on attributes refer to page 10 5 The following examples show the use of enumeration types TYPE legte vole TS 70r AA AA a a ye SUBTYPE ideal v IS logic volt RANGE 0 TO 757 TYPE shift IS shr shl shrc skle If you use an identifier or character literal that has been specified in the same section of code same scope or outer scope and give it a different value you have overloaded the literal For example if previously in a process you wrote E EG TYPE traffic IS car cab truck van then you write the following code later in the same process TYPE vehicle IS cab car truck motorcycle van Overloaded the enumeration literals car cab truck and van are overloaded by being used in another enumerated type vehicle Overloading provides you with a method for using the same identifier name for different enumerated types within the same process For more information on overloading refer to page 3 24 For more information on scope refer to page 3 12 5 20 Mentor Graphics VHDL Reference Manual July 1994 Types Predefined Enumeration Types The following enumeration types have been predefined in package
331. output waveform in Assignment Seq the driver of a signal Variable None Seq Replaces current variable value with a Assignment new value Wait wait Seq Suspends a process or procedure on Mentor Graphics VHDL Reference Manual July 1994 6 9 Statements assertion statement The assertion statement checks a condition you specify to determine if it is true and can report a message with a specified severity if the condition is not true There is also a concurrent assertion statement which is defined on page 6 19 Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax assertion statement assert condition report expression severity expression Description When you use a report expression it must include an expression of the predefined type string that specifies a message to be reported If you do not specify a report expression a default value of assertion violation is used for this string When you use a severity expression it must specify an expression of the predefined type severity level that specifies to what degree the severity of the assertion condition exists If you do not specify a severity expression a default value of ERROR is used for the severity level The types string and severity level are predefined in package standard which is discussed on page 9 18 The following list shows the predefined severity levels
332. owing examples show the use of the interface list in portions of code component declaration COMPONENT xor2 GENERIC prop delay time interface constant decl temp real PORT SIGNAL a b IN bit interface signal decl 2 OUT bit END COMPONENT entity declaration ENTITY mux IS GENERIC CONSTANT capac real interface constant decl real delay time PORT a0 al sel IN bit interface signal decl ys QUIE Bik 5 END mux subprogram specification PROCEDURE check VARIABLE x IN bit vector 0 TO 7 intfc CONSTANT z IN bit decl SIGNAL tester IN bit IS gt Mentor Graphics VHDL Reference Manual July 1994 4 23 Declarations interface constant declaration An interface constant declaration declares one or more objects that can serve as generics in design entities generics in component declarations or constant parameters in subprograms Construct Placement generic list interface declaration subprogram specification Syntax interface constant declaration constant identifier list in subtype indication static expression Definitions B identifier list Lists one or more constant names Multiple names must be separated by commas B subtype indication Indicates the subtype and any constrai
333. pe of the specified prefix Evaluation Result M The result is the value of the signal specified by the prefix immediately before the signal changed value For composite signals the value that returns is the last time any element in the composite changed value Example h J LOS For an example of this attribute in contrast to all the other signal attributes refer to page 10 38 10 34 Mentor Graphics VHDL Reference Manual July 1994 Attributes quiet t Kind Signal Prefix gt gt Any signal designated by the signal name All the expressions in the signal name can depend only on constants or generics Parameter A static expression of type time which must not be negative Type time is a predefined physical type refer to Section 5 from package standard refer to page 9 18 If you do not specify the parameter t it defaults to O ns Result Type Boolean Evaluation Result 0 0 0 3 If the signal has not been active quiet for the period of time specified by the parameter t the result is a signal with a value of TRUE If the default value of 0 ns is specified as the parameter the result is TRUE only if the signal is quiet for the current simulation cycle If the preceding conditions are not met the value of the signal is FALSE Example For an example of this attribute in contrast to all the other signal attributes r
334. pe operand operand Any physical Predefined Same as left type type integer operand Any physical Predefined Same as left type type real operand Predefined Any physical Same as right type integer type operand Predefined Any physical Same as right type real type operand Division Any integer Same as left Same as left type operand operand Any floating Same as left Same as left point type operand operand Any physical Predefined Same as left type type integer operand Any physical Predefined Same as left type type real operand cont Division Any physical Same as left Universal cont type operand integer mod Modulus Any integer Same as left Same as left type operand operand rem Remainder Any integer Same as left Same as left type operand operand Mentor Graphics VHDL Reference Manual July 1994 2 21 Expressions Sign The predefined sign operators and have their conventional definition The positive represents the identity function and the negative represents the negation function For the predefined sign operators the operand and result have the same type The predefined sign operators are also called unary operators as are abs and not The formal syntax is shown as follows sign The precedence of the predefined sign operators places restrictions on where you can use them A signed operand cannot follow these operators e A mul
335. perator Therefore it does not appear with the other logical operators In most cases both the left and right operands are evaluated before the predefined operator is applied The exception is the logical operators defined for the types bit and Boolean In this case the right operand is evaluated only if the left operand does not possess adequate information to determine the operation result These operations are called short circuit operations The following subsections discuss in detail each operator class that Table 2 2 lists Important Notes About Operators The operands used with an operator or any expression must be readable they must be of mode in or inout e Floating point arithmetic in VHDL is not always exact The accuracy of the results depends on machine specific factors such as size of storage for floating point numbers size of registers and library routines for exponentiation and logarithms For this reason you should never use the operator to compare two floating point numbers or even a floating point number with a literal For example instead of writing as a condition IF x 0 125 THEN Mentor Graphics VHDL Reference Manual July 1994 2 17 Expressions a better way to check for this condition is IF abs x lt 0 125 lt tolerance THEN where tolerance is some suitable value that you have selected e The fact that the symbol for the relational operator lt less than or equ
336. pes may differ to the extent of any range or index constraint applied to the alias subtype The type of an alias must not be a multidimensional array type BH name The name of the aliased object Example The following example shows two alias declarations SIGNAL sbus data bit vector 15 DOWNTO 0 ALIAS sdata h bit vector 7 DOWNTO O IS sbus data 15 DOWNTO 8 ALIAS sdata l bit vector 7 DOWNTO O IS sbus data 7 DOWNTO 0 Mentor Graphics VHDL Reference Manual July 1994 4 35 Declarations component declaration A component declaration is the local interface to a component whose architecture may be described in another design entity The component declaration specifies the name of this local component as well as the local ports and generics The topic of components is also discussed on page 8 208 Construct Placement declaration block declarative item package declarative item Syntax component declaration component identifier local generic clause local port clause end component Example The following example shows component declarations within an architecture declarative part ARCHITECTURE struct descrip OF mux IS COMPONENT and2 GENERIC prop delay time 10 ns local generic clause PORT a b IN bit z OUT bit local port clause END COMPONENT COMPONENT or2 GENERIC prop delay time 14 ns PORT a b IN bit z
337. picoseconds nanoseconds microseconds milliseconds seconds minutes hours function that returns the current simulator time FUNCTION now RETURN time predefined numeric subtypes SUBTYPE natural IS integer RANGE 0 TO integer high SU predefined array types BTYPE positive IS integer RANGE 1 TO integer high TYPE string IS ARRAY positive RANGE lt gt OF character TYPE bit vector IS ARRAY iral 9 20 NI D standard natural RANGE lt gt OF bit Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages std logic 1164 S Package std logic 1164 and the related extensions package contains declarations of types and subprograms that support a standard nine state logic system These packages are located in the ieee library The std logic 1164 package has been developed by the IEEE Design Automation Standards Subcommittee Modeling group Title std logic 1164 multi value logic system Library This package shall be compiled into a library symbolically named IEEE Developers IEEE model standards group par 1164 Purpose This packages defines a standard for designers x to use in describing the interconnection data types used in vhdl modeling he logic system defined in this package may e insuf
338. ple name The expression in the attribute name may be required or may be optional depending on the particular attribute definition The following examples show the declaration of two types and the use of attribute names to determine information on these types These are source code fragments taken out of context TYPE color IS red white blue orange purple type decl TYPE vector IS ARRAY 1 TO 10 1 TO 15 OF integer color val 2 Returns the value of element in position 2 of the type color which is blue positions start at zero returns right bound of the specified index 1 in the array vector which is 10 vector right 1 There are several terms used to describe to a certain subclass of names as the following list shows O Static name Static expression e Static signal name Indexed names have an expression as part of the language construct If you use a static expression the name is a static name A static expression is one whose value is determined either at compile time or at elaboration time For example when you use a signal that is declared in a previous design unit the signal value is not known in the current design unit Therefore using this signal name in an expression makes it a non static For more information on static expressions refer to page 2 32 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Vi
339. ple shows the declaration of two types that look similar in definition followed by the declaration of two variables of these types TYPE add size IS RANGE 0 TO 255 add size and sub size TYPE sub size IS RANGE 0 TO 255 3 are two distinct types VARIABLE check add size variable declarations VARIABLE next check sub size In the previous example the variable check and the variable next check are of different types even though the they have the same definition This allows you to be confident that when you declare a type with your own unique identifier that type and not a type with a similar definition is used Mentor Graphics VHDL Reference Manual July 1994 4 5 Declarations You can use a simple name to declare both a base type and subtype of the base type In this case the base type is an anonymous unnamed type and the simple name refers to the subtype This situation occurs with numeric types integer floating point and physical and array types The following example shows both an array type declaration and the implicit declarations the system makes TYPE data ar IS ARRAY positive RANGE 1 TO 1024 OF integer Following declarations are implicitly made by the system SUBTYPE index sbtp IS positive RANGE 1 TO 1024 index type TYPE array type IS ARRAY index subtype RANGE lt gt OF integer SUBTYPE data ar IS ar
340. r Graphics VHDL Reference Manual July 1994 9 17 Design Units and Packages Predefined Packages Package Standard This subsection contains an annotated listing of VHDL package standard Package standard which is a required part of all VHDL implementations contains a number of useful predefined types subtypes and functions You do not have to include explicit context clauses in your library units to make use of items declared in package standard You cannot modify package standard CAUTION Do not use predefined type names for your own definitions While it is possible to do so it may become very confusing for you to keep track of when the system is using its definition of a predefined type or is being overwritten to use your definition The following are the equivalent VHDL headers for package standard PACKAGE standard IS predefined enumeration types TYPE bit IS 0 1 TYPE boolean IS false true 9 18 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages TYPE character IS nul soh stx etx eot enq ack bel bs ht lf vt Ef er so si dle dcl dc2 dc3 dc4 nak syn etb can em sub esc fsp gsp rsp usp d ra ELLA E LS A net IE Pet I EE ud E ET 7 el Chae B5 nan us up PAY rot Puts gt foot Put bts w pm m Lt 1 ror pnr ra
341. r IS 2 PORT clock IN bit 3 qout BUFFER bit vector 7 DOWNTO 0 4 END counter 1 ARCHITECTURE gen_counter OF counter IS 2 3 COMPONENT jkff 4 PORT clk j k bit aq ab BUFFER bit 5 END COMPONENT 6 7 COMPONENT and2 8 PORT a b bit y OUT bit 9 END COMPONENT 10 11 SIGNAL rc bit vector 7 DOWNTO 0 12 SIGNAL high bit 717 T3 14 BEGIN 15 gl FOR N 7 DOWNTO 0 GENERATE 16 g2 IF I 7 GENERATE 17 567 jkff PORT MAP 18 clock rc I 1 rc I 1 qout I OP 19 END GENERATE 20 21 g3 IF 7 AND 0 GENERATE 22 andx and2 PORT MAP qout I rc I 1 rc I 23 ffx jkff PORT MAP 24 clock rc I 1 rc I 1 qout I OPEN 25 END GENERATE 26 27 g4 F 0 GENERATE 28 Ff0 jkff PORT MAP clock high high qout 1 29 rc I lt qout 1 30 END GENERATE 31 END GENERATE 32 33 END gen counter Mentor Graphics VHDL Reference Manual July 1994 OP 6 33 Statements If statement The if statement selects one or more groups of sequential statements for execution or selects no statements based on conditions you specify using a boolean expression Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax if statement if condition then sequence of statements elsif condition then sequence of statements else sequence of statements end if Description To set up a condition
342. r rar rar rar A B e D E F G gr LT roe yx T M FN ror H r J K L M N o U Tp Lot FRE LSE nts X Y Z N PAT d a diio ret d et BU Lat h ua Pe Let Lots m Ln o ps rat ar re b gly AS w rx a ae not P5 EE ops DEL The ASCII mnemonics for file separator fs group separator gs record separator rs and unit separator us are represented by sp gsp rsp and usp respectively in type character in order to avoid conflict with the units of type time TYPE severity level IS note warning error failure predefined numeric types I TYPE integer IS RANGE 2147483648 TO 2147483047 TYPE real IS RANGE 1 79769E308 TO 1 79769E308 The ranges for types integer and real are machine dependent The values shown in the previous type definitions assume a 32 bit two s complement machine that follows IEEE double precision standard Mentor Graphics VHDL Reference Manual July 1994 9 19 Design Units and Packages predefined type time I TYPE time IS RANGE a number TO a number UNITS Fs ps 1000 fs ns 1000 ps us 1000 ns ms 1000 us mE sec 1000 ms min 60 sec gt hr 60 min EE END UNITS a number is machine dependent femtoseconds
343. r value inside the loop for example as an array index and this value cannot be modified within the loop An example of modification is when you use the loop parameter as the target of an assignment statement The loop 6 36 Mentor Graphics VHDL Reference Manual July 1994 Statements parameter is an implicitly declared object that is declared by the loop statement Example The following examples show possible uses of the loop statement Example of an infinite loop LOOP sample data sample time amp result Declaration not shown ND LOOP tz Example of a possible infinite loop with an exit statement get data Loop label LOOP sample data sample time amp result Either exits EXIT get data WHEN sample data 900256 first time or in END LOOP get data infinite loop because sample time and result can never change Example using the while iteration scheme answer loop label WHILE b 50 LOOP while loop b 1024 8 END LOOP answer Label must match corresponding loop label example using the for iteration scheme and no loop label FOR i IN 1 TO 100 LOOP for loop a i i 2 Use loop parameter as an array index END LOOP The following example shows the illegal use of the loop parameter in the for loop FOR i IN 1 TO 20 L
344. ral If the conversion result fails to satisfy the type mark you specify the conversion fails creating an error Type conversions also allow you to convert integer types to other integer types and to convert floating point types to other floating point types The following example shows you how to use type conversion on an expression to add values of two different integer types PROCESS TYPE apples IS RANGE 1 TO 10 Declare two different TYPE oranges IS RANGE 1 TO 5 integer types apples and oranges VARIABLE vl ans apples Declare vl and ans as apples VARIABLE v2 oranges Declare v2 as type oranges BEGIN ans vl v2 Illegal vi and v2 are different types WAIT FOR 10 ns END PROCESS To make this expression valid you can use the following type conversion ans vl apples v2 convert v2 to type apples Allocators An allocator is an expression that when evaluated creates an anonymous object and yields an access value that designates that object The access value can be thought of as the address of the object The access value may be assigned to an access type variable which then becomes a designator of hereafter called a pointer to the unnamed object Such pointers allow access to structures like FIFOs first in first out registers and linked lists that contain unnamed el
345. ram specification in the subprogram body is used as the declaration The following rules apply When you declare a subprogram it must have a corresponding subprogram body e The subprogram declaration and corresponding subprogram body must be in the same declarative region When you declare a subprogram and define a subprogram body the two subprogram specifications must match Because of the visibility rules you must use a subprogram declaration if you wish to call a subprogram whose body occurs textually after the call This declaration must occur before the call in your description code For more information on visibility rules refer to page 3 17 Example The following subprogram body is from the code for the memory programmer and tester described in the introduction to this section in the check parity function RAM Data Conc Check Op Code Conc Parity Boolean Function Value Mentor Graphics VHDL Reference Manual July 1994 7 11 Subprograms subprogram specification FUNCTION chk pty CONSTANT ram data conc IN bit vector 0 TO 31 CONSTANT op code conc IN bit vector 0 TO 31 RETURN boolean IS subprogram declarative part VARIABLE suml sum2 boolean false BEGIN subprogram statement part FOR i IN 0 TO 31 LOOP IF ram data co
346. ray type index subtype In the previous example the base type of data ar is not defined explicitly but is defined by the subtype of data ar Notice that the range constraint on the array has its own type 4 6 Mentor Graphics VHDL Reference Manual July 1994 Declarations subtype declaration A subtype declaration declares a subset of values of a specified type or subtype Construct Placement declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax subtype declaration subtype identifier is subtype indication subtype indication resolution function name type mark constraint type mark type name subtype name constraint range constraint index constraint Definitions B identifier A name that you provide for the subtype B subtype indication Indicates restrictions placed on the subtype Mentor Graphics VHDL Reference Manual July 1994 4 7 Declarations Description When you define a subtype you are not defining a new type you are defining a name for a subset of the type with a specific range or index constraint There are two major advantages of using subtypes 1 You save time because you don t need to declare a new type when a subset of a larger type definition will do 2 You can perform calculations on primaries of different subt
347. rd open means the formal is unconnected For more information on unconnected ports refer to page 8 8 For an example of using open refer to page 9 10 If you mix named and positional associations in the same association list all positional associations must be listed first and the remainder of the list can use only named association If you omit an association element in the association list all the associations after that point must be named The default expression in an interface signal declaration for a port determines the value of the port during simulation when the port is left unconnected Unlike signals that are not ports the default expression for a port is not the value of the implicit association element for the port This is because ports must be associated with signals not values Mentor Graphics VHDL Reference Manual July 1994 Declarations alias declaration An alias declaration defines an alternate name for a signal variable or constant Construct Placement block declarative item entity declarative item package declarative item package body declarative item process declarative item subprogram declarative item Syntax alias declaration alias identifier subtype indication is name Definitions B identifier The alias B subtype indication The name of a type or subtype with an optional range or index constraint The base type must be the same as that of the aliased object but the subty
348. re information on function call expressions refer to page 2 10 Mentor Graphics VHDL Reference Manual July 1994 7 15 Subprograms Example An example of a function call from the memory programmer and tester follows subprogram specification for chk pty function FUNCTION chk pty ram data conc IN bit vector 0 TO 23 op code conc IN bit vector 0 TO 23 RETURN boolean ASSERT chk pty ram data conc gt a op code conc gt b REPORT Parity Failed function call expres to chk pty Mentor Graphics VHDL Reference Manual July 1994 Subprograms The Procedure Call The procedure call causes the execution of the procedure body Procedure calls can be sequential or concurrent The sequential procedure call is shown on page 6 40 and the concurrent procedure call is shown on page 6 21 The following example shows the sequential procedure calls for the memory programmer and tester PROCEDURE ram read VARIABLE ram data OUT bit vector 0 TO 7 VARIABLE test add start OUT integer 0 TO 255 PROCEDURE ram load VARIABLE op code IN bit vector 0 TO 7 PROCEDURE concat data VARIABLE test add start IN integer 0 TO 255 VARIABLE ram data IN bit vector 0 TO 7 VA BLE op code IN bit vector 0 TO 7 VARIABLE ram data conc op code concat OUT bit
349. re statements belong in the language hierarchy and it lists the available concurrent and sequential statements Several of the statements and other constructs use the label construct Rules for using the label with each construct are discussed in the appropriate subsection The following BNF description shows that a label is an identifier label identifier Mentor Graphics VHDL Reference Manual July 1994 6 3 Statements Design Units Design Entities Configurations Packages Attributes Components Types Signals __ Statements Subprograms d Declarations Expressions Lexical Elements Naming Scope and Visibility Statements Y Y Y Concurrent Statements Sequential Statements Block Wait Process Assertion Concurrent Procedure Call Signal Assignment Concurrent Assertion Procedure Call Concurrent Signal Assignment If Exit Component Instantiation Case Return Generate VERE Null Figure 6 1 Statements 6 4 Mentor Graphics VHDL Reference Manual July 1994 Statements sequential statement Sequential statements represent hardware algorithms that define the behavior of a design Construct Placement process statement part subprogram statement part sequence of statements if statement loop statement case statement alternative case statement Syntax sequential statement wait statement assertion statement signal
350. rence a certain portion of an item such as element of an array or record In those cases you might use an indexed name or selected name In all there are six forms of names you can use as the following BNF description illustrates name simple_name operator_symbol selected_name indexed_name slice_name attribute_name The following subsections show you how to use simple names selected names indexed names slice names and attribute names The operator symbol is a name for an operator that you can overload and use to manipulate objects This topic is discussed in the subprogram declaration description on page 7 6 Mentor Graphics VHDL Reference Manual July 1994 3 3 Naming Scope and Visibility Simple Names When you declare an item using an identifier you use a simple name When the simple name is evaluated the item to which it refers is determined Every item you explicitly declare has a simple name and some items declared implicitly have a simple name such as labels and loop indexes The following BNF syntax description shows the related syntax for a simple name simple name identifier identifier letter _ letter digit All declarations require simple names The following are some valid simple name examples within a line of code ARCHITECTURE behave OF shifter IS behave is the simple name identifier in the first line of the architecture body const
351. result equals 128 answer 8 ABS qd answer equals 64 answer ABS d ABS d answer equals 4 WAIT FOR 10 ns END PROCESS Exponentiation using an integer exponent right operand is equivalent to multiplying the left operand by itself for the number of times specified by the absolute value of the right operand It is an error to use a negative integer exponent When you use a negative exponent the operation result is the reciprocal of the value returned using the absolute value of the exponent You can use only negative exponents with left operands that are floating point types NOTE Floating point arithmetic in VHDL is not always exact The accuracy of a result depends on machine specific factors such as size of storage for floating point numbers size of registers and library routines for exponentiation and logarithms Therefore an operation such as 2 0 3 may not always produce a result of exactly 0 125 When you use an exponent that has a value of zero the operation result is a value of one When you use predefined operator abs the right operand value is always converted to a non negative value Mentor Graphics VHDL Reference Manual July 1994 2 19 Expressions Multiplying Operators S The following BNF syntax description shows the multiplying operators The multiplication operator and the division operator have their conv
352. ring 1001 Mentor Graphics VHDL Reference Manual July 1994 4 13 Declarations If you omit the expression and the delimiter the constant declaration specifies a deferred constant A deferred constant allows you to declare a constant but not to specify the value of the constant at that point Deferred constant declarations can appear only in package declarations The full constant declaration with the value expression must appear in the corresponding package body This full declaration must match the deferred declaration exactly except for the value expression The following example shows a deferred constant declaration and the corresponding full constant declaration PACKAGE common info IS CONSTANT xtal value real deferred constant END common info PACKAGE BODY common info IS CONSTANT xtal value real 1 556E6 full constant decl For more information on packages refer to page 9 12 The following list shows the objects that are constants in VHDL Any object you explicitly declare as a constant using the constant declaration is a constant A slice or subelement of a constant is always a constant Formal subprogram parameters that are mode in can be constants Formal and local generics are constants automatically A loop parameter in a loop statement is a constant but its value does change from iteration to iteration 4 14
353. rom Mentor Graphics Mentor Graphics VHDL Reference Manual July 1994 9 33 Design Units and Packages std math These functions and procedures provide access to system supplied math functions As such they are not guaranteed portable or even available between different hosts In other words different host platforms may produce different results under the same circumstances Mentor Graphics is not responsible for the availability or performance of these functions For a description of how these functions work please refer to the ANSI C Language Reference Manual PACKAGE math IS SUBTYPE natural real IS real RANGE 0 0 TO real high NOTE The precision of these constants is specified greater than the host implementation is capable of representing REAL s are only accurate to gt approximately 16 decimal digits CONSTANT e real 2 718281828459045235 CONSTANT log2e real 1 4426950408889634074 CONSTANT logl0e real 0 43429448190325182765 CONSTANT 1n2 real 0 69314718055994530942 CONSTANT 1n10 real 2 30258509299404568402 CONSTANT pi real 3 14159265358979323846 e x FUNCTION exp x real RETURN real natural logarithm FUNCTION log x natural real RETURN rea
354. ruct ENTITY counter IS counter is the simple name identifier in the first line of the entity declaration construct FUNCTION chk parity chk parity is the simple name identifier in the first line of the subprogram specification construct Selected Names Selected names designate elements of record types objects pointed to by access values and items declared within another item design library or package You use selected names in use clauses which are discussed on page 3 22 You can use a selected name to designate all the items declared in a library or package by using the reserved word all You can also use selected names to resolve overloading conflicts The use of selected names to access individual elements of records is discussed under record type definition beginning on page 5 29 The use of selected names for objects pointed to by access values is discussed under Allocators beginning on page 2 13 3 4 Mentor Graphics VHDL Reference Manual July 1994 Naming Scope and Visibility The following BNF descriptions show the syntax for a selected name selected name prefix suffix suffix simple name character literal operator symbol all The following examples show the use of selected names USE USE standard time The item time in package standard tandard ALL All the items in package standard
355. s VHDL Reference Manual July 1994 4 15 Declarations If you do not use the initial value expression the system determines the default initial value for the variable This default is the left most value of the variable type This value is determined by using the predefined attribute left The following example shows a type declaration a variable declaration without the initial expression and the equivalent default value the system determines TYPE mem addr IS RANGE 0 TO 1024 type declaration VARIABLE up bit mem addr variable decl with no initial variable value expression VARIABLE up bit mem addr mem addr left default assumes left most value as the default In the previous example the initial default for the variable up bit is the left most value of the type mem_addr which is 0 You change the current value of variable by using the variable assignment statement The variable assignment statement is discussed in detail on page 6 48 The following examples show some possible variable assignments calc result a b C out a AND out b AND out Cc next add cur add 4 Here are some additional rules relating to variable declarations e Variable assignments take immediate effect e Variables you declare in a subprogram exist until the subprogram completes and until control returns to the description that called the subprogram e Procedure para
356. s a collection of elements of the same type that are organized in one or more dimensions Elements of type file are not permitted Construct Placement composite type definition type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax 5 22 Mentor Graphics VHDL Reference Manual July 1994 Types array type definition unconstrained array definition constrained array definition unconstrained array definition array index subtype definition index subtype definition of element subtype indication constrained array definition array index constraint of element subtype indication index subtype definition type mark range lt gt index constraint discrete range discrete range discrete range discrete subtype indication range Definitions unconstrained array definition Defines an unconstrained array in which you specify the type of the indices but do not specify the range B constrained array definition Defines a constrained array which has a specific subset of values for the range of the array indices Description VHDL does not limit the number of dimensions you can have in an array The values in an array are referenced by indices that also have a specified type For more information on this topic refer to
357. s and Configurations Example The following examples show a portion of code from within an architecture This code shows the use of the binding indication as part of the configuration specification FOR Ul inverter USE ENTITY inv not a entity aspect starting at ENTITY ending at GENERIC GENERIC MAP 7 ns generic map aspect PORT MAP sel nsel port map aspect FOR U2 and2 USE ENTITY WORK and2 input basic and2 FOR OTHERS and2 USE ENTITY WORK and2 s FOR ALL or2 USE ENTITY WORK or 2input or struct 8 30 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations entity aspect The entity aspect binds a component instance to the entity declaration and architecture body you specify Construct Placement binding indication Syntax entity aspect entity entity name architecture identifier configuration configuration name open Description S As the BNF description shows the architecture identifier is optional If you do not use an architecture identifier the most recently analyzed architecture body associated with the named entity is chosen It is an error if no such architecture exists Refer also to Default Binding Indication on page 8 33 Example ss Ss A The following examples show the use of the entity aspec
358. se entity header local generic clause component declaration Syntax generic clause generic generic list generic list interface constant declaration 5 interface constant declaration Description lt 0 Generics allow you to reuse a single design entity by passing in information that is unique to that design entity such as delays temperature and capacitance They also provide a method for documenting your design The interface declarations are discussed in detail beginning on page 4 21 Example 5 9 D 3 The following examples show generic declarations from separate entity headers GENERIC propagation delay time 15 ns Default to 15 ns GENERIC temperature real No default value GENERIC capacitance real resistance integer multiple declarations Mentor Graphics VHDL Reference Manual July 1994 8 7 Design Entities and Configurations port clause A port clause declares one or more ports A port is a signal that serves as a communication channel between a block of a description and its external environment Construct Placement formal port clause entity header local port clause component declaration Syntax port clause port port list port list interface signal declaration interface signal declaration Description sap mu P Q Internal
359. se In this case the reserved words constant variable and signal do not appear in the declaration These objects are the objects in Table 4 1 except for the first entry The first entry is the explicit declaration of objects as the preceding example shows Table 4 1 shows what a VHDL object is and gives a partial code example for that object The items in this table are discussed in detail in various sections in this manual Refer to the index for exact page locations Keeping in mind the objects that Table 4 1 shows the following list shows where you can use these objects e You can use explicitly declared objects anywhere they are visible You can use the loop parameter only within the corresponding loop statement The remaining objects that Table 4 1 shows are declared by interface declarations These objects provide channels of communication between independent portions of your design For information on interface objects refer to page 4 21 Each of the three object declaration classes have an identifier list language construct The syntax for an identifier list is shown in the following diagram identifier list identifier identifier An object declaration is a single object declaration if the identifier list has one identifier If you use two or more identifiers the declaration is a multiple object declaration The multiple object declaration is equivalent to a series of single object declarations For example
360. se the function returns a value of FALSE An error condition exists 1f a read 1s made on a file that has an endfile value of TRUE The content of value is the value of the item in the file This value must be the same type as the file In the preceding example value in the read and write procedures must be of type integer In the following example value in the read procedure must be an array of type real The following example shows a file type that has an unconstrained array type as a type mark and the implicit read procedure that follows The write and endfile operations are the same as the previous example TYPE rom array IS ARRAY integer RANGE lt gt OF real uncons TYPE data values IS FILE OF rom array file type decl FILE rval data values IS my file file declaration PROCEDURE read VARIABLE rval INOUT data values value OUT rom array length OUT natural implicit read def The read procedure from the preceding example returns a value from the file and a parameter called 1engtn that specifies the actual length of the array value read For information on file objects and their declaration refer to page 4 18 Mentor Graphics VHDL Reference Manual July 1994 5 35 Statements Section 6 Statements This section discusses the statements that you can use in VHDL A statement is a construct you use to specify on
361. sibility expression For detailed information about the design unit refer to Section 9 If you use a static name to designate a signal the name is considered a static signal name Scope and Visibility S Scope and visibility are concepts that are closely related The scope is the region of code text over which an item exists declarative region Within the scope visibility refers to an item that has a unique name that you can reference If an item is hidden it is not visible without using a selected name This topic is discussed on page 3 17 Using the concepts of scope and visibility and by using the rules of overloading you can control the name space That is you can control where names have effect without worrying about the global effects of manipulating a named item This becomes a very important factor when your design contains hundreds of names The following subsections describe in detail the following items The declarative region The concept of scope and the scope rules The concept of visibility and the visibility rules e Overloading concepts Declarative Region Scope and visibility are defined in terms of declarative regions The declarative region is a part of the text of a description The declarative region is formed by the text of the following items e Component declaration page 8 21 e Entity declaration combined with an architecture body page 8 4 e Package declaration combined with a package body if it
362. signal Figure 11 3 illustrates this concept 11 10 Mentor Graphics VHDL Reference Manual July 1994 Signals Signal test 9 enl 7 en2 7j en3 Jj Code describing a signal NN with three drivers represented at the right data a data b data c drivers created Array of the three data a data b data c Array of the three drivers is the input parameter to the resolution function Y Resolution Function Signal value is resolved m Figure 11 3 Resolution Function Concept The following steps show you how to write the description and the resolution function for the example in Figure 11 3 1 The following architecture body shows the description for the signal test with three drivers ARCHITECTURE data flow OF tester SIGNAL test wired or my qgsim IS state SIGNAL data a data b data SIGNAL enl en2 en3 bit BEGIN test lt data a AFTER 2 ns W test lt data b AFTER 2 ns W test lt data c AFTER 2 ns WHE END data flow Mentor Graphics VHDL Reference Manual July 1994 e my qsim state EN enl 1 ELSE 2Z EN en2 717 ELSE Z EN en3 1 ELSE Z 11 11 Signals 2 Table 11 1 shows the driver resolution value for two drivers To determine the resolution value you
363. sis applications e Notepad User s and Reference Manual describes how to edit files and documents in Notepad a text editor This manual provides examples explanations and an alphabetical listing of AMPLE functions that are available for customizing Notepad e QuickSim II User s Manualdescribes how to use the QuickSim II logic simulator This manual provides background information a hands on tutorial intended for new users various simulation procedures and a comprehensive list of related procedures xxii Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements Section 1 Lexical Elements The lexical element is the most basic item in VHDL When combined these items form the language Figure 1 1 shows where lexical elements belong in the overall language and the items that comprise the lexical elements The following list identifies the topics described in this section Definition of Lexical Elements 1 3 Character Set 1 1 1 1 Z 5 Replacement Characters dG Identifiers 1 S 8 Reserved Words 1 _ 19 Comments SS Literals 1 15 Numeric Literals _ 1S Character Literals _ 18 String Literals 0 0 0 11 Character and String Literal Differences 1 20 Bit String Literals 1 20 Separators and Delimiters J 1 21 Separators S Oal Delimiters 22 Mentor Graphics VHDL Reference Manual July 1994 1 1 Lexical Elements Design Units Design Entities Configurations Packages
364. sitivity list in the process statement part You also cannot use a wait statement within a procedure if the procedure is called by a process that uses a sensitivity list When the process statement executes the sequence of sequential statements execute When the last sequential statement executes the first sequential statement in the sequence then executes This is analogous to a looping action The process declarative part contains declarations that are local to the process The declarations allowed are listed in the previous syntax When you use a signal assignment statement in the process this statement defines a driver for the destination signal All drivers for a signal in the process are combined into one source For a discussion on signals and drivers refer to Section 11 If no signal assignment statement appears in the process or in a procedure called by the process the process is called a passive process Only a passive process can appear in the entity statement part of an entity declaration For more 6 42 Mentor Graphics VHDL Reference Manual July 1994 Statements information on this subject refer to page 8 12 Example The following example shows the possible use of a process statement
365. ssion AS 4 N A R P 11 14 signal kind register bus 11 14 signal list y signal_name SON Lor e 7 gt others gt all do 11 8 A 60 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary simple_expression sign L p term gt adding operator term 2 4 identifier simple name gt 3 4 slice name y prefix gt discrete range 3 9 special_characters 2 B X OX o X 4 6 3 C30 4 5G amp NDS ES E N NO DES A NC T P SN DA Mentor Graphics VHDL Reference Manual July 1994 A 61 Syntax Summary string literal Ny m ONG gt graphic character gt 1 19 subprogram_body Subprogram_specification pf is ee subprogram declarative part gt begin subprogram_statement_part subprogram declaration A 62 gt designator 7 10 subprogram specification gt gt 7 6 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary subprogram d
366. standard Character e Bit e Boolean O severity level The equivalent code for package standard is discussed on page 9 18 Refer to that discussion for detailed information on the predefined enumeration types CAUTION Do not use predefined type names for your own definitions While it is possible to do so it may become very confusing for you to keep track of when the system is using its definition of a predefined type or is being overwritten to use your definition Mentor Graphics VHDL Reference Manual July 1994 5 21 Types composite type definition A composite type specifies groups of values under a single identifier Construct Placement type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax composite type definition array type definition record type definition Definitions array type definition Declares an array which is a collection of elements of the same type that are organized in one or more dimensions Elements of type file are not permitted B record type definition Declares a record which is a collection of named elements Description lt 0 The composite type allows you to group items that are naturally bundled together or represented as tables array type definition An array i
367. statement generic clause generic map aspect options if statement interface constant declaration mode parameter specification mode type declaration package declaration subtype declaration library loop entity class library clause mode loop statement generic map aspect port map aspect multiplying operator 1 12 expression logical operator allocator next statement expression logical operator 2 31 Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements VHDL Reserved Words continued factor miscellaneous operator literal null statement waveform element on open or others package port procedure process architecture body constrained array definition file type definition unconstrained array definition sensitivity clause actual designator entity aspect expression logical operator choice entity name list instantiation list mode package body package declaration port clause port map aspect subprogram specification process statement range record register rem report return range constraint record type definition signal kind multiplying operator assertion statement return statement subprogram specification Mentor Graphics VHDL Reference Manual July 1994 Lexical Elements VHDL Reserved Words continued select severity signal subtype selected signal assignment assertion statement interface signal declaration
368. straint TYPE test int IS RANGE 0 TO 255 5 Illegal high range bound In the preceding example the right or high range constraint bound is 225 5 which is of a floating point type Since the bound is not of an integer type it is not a legal bound The following example shows another illegal condition Mentor Graphics VHDL Reference Manual July 1994 5 9 Types TYPE my int IS RANGE 0 TO nonlocst High bound not loc stc In the preceding example the right or high range constraint bound is the variable nonlocst Which has been declared previously in the same design unit Therefore nonlocst is not a locally static expression and is not legal as a range constraint bound You can use all integer types with the appropriate predefined arithmetic operators For information on operators refer to page 2 16 If an arithmetic operation result is not an integer type in the range you specify an error occurs For example PROCESS VARIABLE x integer RANGE 0 TO 7 VARIABLE j integer BEGIN Jed X j 1 error condition WAIT FOR 10 ns END PROCESS I In this example the arithmetic operation j 1 results in a value which is not in the specified range for x Therefore a run time error condition exists when the assignment to x occurs during simulation The following examples show some typical uses of integer types from within VHDL code
369. subsections discuss the two forms of the concurrent signal assignment statements 6 24 Mentor Graphics VHDL Reference Manual July 1994 Statements conditional signal assignment The conditional signal assignment form of the concurrent signal assignment statement results in an equivalent process statement generated by the system that assigns values to signals using an if statement format Construct Placement concurrent signal assignment statement concurrent statement architecture statement part block statement part Syntax conditional signal assignment target lt options conditional waveforms conditional waveforms waveform when condition else waveform Description lt 0 0 Because of the similarity in appearance of the assignment operator and the less than or equal operator both of which are written lt you should be careful that your code does not produce unexpected results For example the intent of the signal assignment statement in the following code was this If enl is 1 assign data ato test If en2 is 1 assign data b to test If neither of the above is true assign 1 to test ENTITY tester IS END tester ARCHITECTURE data flow OF tester IS SIGNAL test data a data b qsim state SIGNAL enl en2 bit BEGIN test lt data a AFTER 2 ns WHEN enl 1 ELSE t
370. t Description lt 0 0 The procedure name is the name of the procedure body that you want to execute You use the optional actual parameter part to specify the association of actual with formal parameters of the procedure For more information on parameters refer to page 7 8 and page 7 13 The concurrent procedure call is also discussed on page 6 21 Example The following example shows a procedure specification and a call to the procedure procedure specification PROCEDURE examine data my part IN string read data OUT bit vector 0 TO 23 prop delay IN time procedure call later in a code description examine data shifter data contents t ns In the preceding example the parameter shifter corresponds to my part data contents to read data and t ns to prop delay 6 40 Mentor Graphics VHDL Reference Manual July 1994 Statements process statement The process statement is a concurrent statement that contains within it a series of sequentially executed statements that define the behavior of a portion of a design Construct Placement entity statement Cconcurr ent statement architectur e_statement_par t block_statement_part Syntax process_statement process label process sensitivity list process declarative part begin process statement part end process process label sensitivity list signal name signal name process d
371. t class Mentor Graphics VHDL Reference Manual July 1994 Subprograms e For functions O constant is the default O If no mode is given in is the default The mode of the formal parameter determines how it is accessed within the subprogram The three modes are defined as follows in The subprogram reads the parameter but does not modify the value e out The subprogram defines a parameter value to be used by the calling code but the subprogram is not read O inout The subprogram reads and defines a parameter value Example 46e 4 The following example shows the subprogram declaration from the code of the memory programmer and tester PROCEDURE ram read VARIABLE ram data OUT ram data array VARIABLE test add start OUT integer 0 TO 255 The default object class for a procedure with the mode out is variable Therefore the preceding example can be written as the following PROCEDURE ram read ram data OUT ram data array test add start OUT integer 0 TO 255 The following examples show illegal parameter modes and object classes FUNCTION tester chk data OUT result RETURN integer Mode OUT not allowed FUNCTION today date INOUT 13s RETURN integer Mode INOUT not allowed FUNCTION tfd_4 VARIABLE b IN day RETURN integer VARIABLE not allowed
372. t Classes There are two classes of statements you can use in your VHDL descriptions e Sequential statements Concurrent statements The following example illustrates the difference between sequential and concurrent statement execution pl PROCESS a b c bl BLOCK BEGIN sequential area BEGIN concurrent area a lt b AND c a lt b AND c d lt a AND c d lt a AND Cc END PROCESS pl END BLOCK b1 In this example the code in the left hand column contains two sequential signal assignments within a process labeled pl In the right hand column of the example two concurrent signal assignments within block b1 perform the same functions as the statements in pl Statements within a process must be sequential statements they are evaluated in the order in which they appear in the code In contrast statements within the statement part of a block must be concurrent statements During simulation 6 2 Mentor Graphics VHDL Reference Manual July 1994 Statements concurrent statements are evaluated as if they occur simultaneously Thus the signal assignments in pl occur one after the other while the signal assignments in b1 occur simultaneously For more information on how sequential and concurrent statements are evaluated refer to the Mentor Graphics Introduction to VHDL the Contrasting Concurrent and Sequential Modeling subsection Figure 6 1 shows whe
373. t as part of the binding indication FOR device 1 mux USE ENTITY WORK test mux mux architecture FOR U9 counter USE ENTITY my lib 4bit count FOR exor exor gate USE ENTITY my lib gates xor gate FOR dsp2 display cont USE CONFIGURATION work cfgl dsp Mentor Graphics VHDL Reference Manual July 1994 8 31 Design Entities and Configurations Generic and Port Map Aspects A generic map aspect associates a value with the formal generic declared in the entity declaration A port map aspect associates signals with the formal ports declared in the entity declaration The following diagram shows the syntax for generic and port map aspects For more information on association lists refer to page 4 31 generic map aspect generic map generic association list port map aspect port map port association list The following example is a code fragment from an architecture body that shows the use of the generic and port map aspects as part of a binding indication FOR U7 dec USE ENTITY decoder decode behav GENERIC MAP 45 ns decoder type generic map aspect PORT MAP a b c d output port map aspect In the preceding example the configuration specification for v7 specifies that the design entity decoder and the architecture body decode behav are to be used for the component dec The generic map aspect asso
374. t association choices gt expression choices choice choice choice simple_expression discrete_range element_simple_name others An example array aggregate follows PROCESS CONSTANT offset integer 5 CONSTANT start integer 0 TYPE dump_memory IS ARRAY 0 to 5 OF integer VARIABLE mem_d dump_memory BEGIN mem d start offset gt 1 OTHERS gt 0 array WAIT FOR 10 ns aggregate END PROCESS The result of the preceding example is a one dimensional array mem d with the following value mem d 1 0 0 0 0 1 2 8 Mentor Graphics VHDL Reference Manual July 1994 Expressions From the previous example the following code represents the array aggregate mem d start offset gt 1 OTHERS gt 0 The element association in the preceding example relates a choice of start or offset that have a value of 1 to elements 0 and 5 of the array mem a All other elements of the array are assigned a value of 0 Each choice value must specify index values for the one dimensional array Each element association that you use relates an expression to one or more elements of an array A named element association is an element association if you specify the array elements by using the construct choices as the previous example shows An easy way to determine if there
375. t declaration file declaration alias declaration Uuse clause o j 9 15 package_body_declarative_part package body declarative item gt 9 15 A 48 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary package declaration package gt package simple name La is e gt package declarative part gt end package simple name N 9 13 package declarative item subprogram declaration type declaration subtype declaration m constant declaration gt signal_declaration N file declaration alias declaration component declaration attribute_declaration attribute_specification disconnection_specification use clause Mentor Graphics VHDL Reference Manual July 9 13 1994 A 49 Syntax Summary package declarative part _ package declarative item 9 13 parameter specification identifier in _ discrete range gt 6 36 physical literal gt abstract literal unit_name 1 16 physical type definition
376. t that is not set off with brackets or braces indicates that the item is required e construct three Text surrounded by square brackets denotes an optional area that can be used only once In this example construct three is not required in the example construct syntax If construct three is used along with construct two it can be used only once construct one Text surrounded by braces denotes an optional area that can be used one or more times O construct one Italic text within a construct name indicates additional information and does not represent an actual language construct The words that follow the italics represent an actual language construct e boldface text This convention sets off reserved words and characters that must be typed literally as presented O A vertical bar indicates an or situation Thus linel line2 line3 indicates that either linel or line2 or line3 can be used to describe the syntax Mentor Graphics VHDL Reference Manual July 1994 xix About This Manual Related Publications The following Mentor Graphics manuals contain important information on related topics The list is divided into three parts one for all Mentor Graphics VHDL users one specifically for Explorer VHDLsim users and one specifically for System 1076 users In addition to this manual the following manual relates to all Mentor Graphics VHDL solutions e Mentor Graphics VHDL Referenc
377. tains a brief statement about the subprograms necessary to describe the example device Memory write procedure that writes opcodes to the memory device This procedure demonstrates that you can write a procedure with only one parameter that makes changes to an external file without side effects Memory read procedure that reads a random three address line section of the memory device to check that the write operation performs correctly This procedure demonstrates the return of multiple values to the calling code without an input parameter e Concatenation procedure that joins the memory device data to check the parity This procedure demonstrates the passing of an input parameter and the return of an output parameter to the calling code Check parity function that returns a TRUE or FALSE value after checking the parity between the written data and the read data This function demonstrates the use of a function Figure 7 2 shows the block diagram for the memory programmer and tester The arrows show the necessary parameters that need to pass between the subprogram calls and the subprograms Parameters are discussed in detail on page 7 8 The small figure at the bottom right shows the hierarchical structure of this block diagram The following subsections discuss the items that make up a subprogram and the rules for using these items using the memory programmer and tester as an example 7 4 Mentor Graphics VHDL Reference Man
378. td ulogic vector TYPI std ulogic IS ARRAY NATURAL RANGE for use with the lt gt OF std ulogic resolution function FUNCTION resolved s std ul logic vector RETURN std ulogic industry standard SUBTYPE std logic logic type IS resolved std ulogic unconstrained array of std logic for use in declaring signal arrays TYPE std logic vector IS ARRAY NATURAL RANGE lt gt OF std logic common subtypes SUBTYPE X01 IS resolved std ulogic RANGE X TO 1 LL EX AO rotary SUBTYPE X01 S resolved std ulogic RANGE X TO Z e CXV IH V PESE SUBTYPE UXO IS resolved std ulogic RANGE U TO 1 zl CIF ASES OO ESOS SUBTYPE UX01Z IS resolved std ulogic RANGE U TO Z E QUAS XE PELEAS 9 22 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages overloaded logical operators FUNCTION and 1 std ulogic r std ulogic RETURN UXO1 FUNCTION nand 1 std ulogic r std ulogic RETURN UX01 FUNCTION or 1 std ulogic r std ulogic RETURN UX01 FUNCTION nor 1 std ulogic r
379. td ulogic vector RETURN std ulogic vector FUNCTION To X01 s std ulogic RETURN X01 FUNCTION To 01 b BIT VECTOR RETURN std logic vector FUNCTION To X01 b BIT VECTOR RETURN std ulogic vector FUNCTION To 01 b BIT RETURN X01 FUNCTION To X012 s std logic vector RETURN std logic vector FUNCTION To X012 s std ulogic vector RETURN std ulogic vector FUNCTION To X012 s std ulogic RETURN X017 FUNCTION To_X01Z b BIT VECTOR RETURN std logic vector FUNCTION To 017 b BIT VECTOR RETURN std ulogic vector FUNCTION To X01Z2 b BIT RETURN X017 FUNCTION To UXO1 s std logic vector RETURN std logic vector 9 24 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages FUNCTION To UXO1 s std ulogic vector RETURN std ulogic vector FUNCTION To UXO1 s std ulogic RETURN UX01 FUNCTION To UXO1 b BIT VECTOR RETURN std logic vector FUNCTION To UXO1 b BIT VECTOR RETURN std ulogic vector FUNCTION To UXO1 b BIT RETURN UXO1 gt edge detection FUNCTION rising edge SIGNAL s std ulogic RETURN BOOLEAN FUNCTION falling edge SIGNAL s std ulogic RETURN BOOLEAN object contains an unknown FUNCTION IS X s std ul
380. te transaction tracks the attribute active e The attribute quiet tracks the attribute active e The attribute last event tracks the attribute event e The attribute last active tracks the attribute active 10 38 Mentor Graphics VHDL Reference Manual July 1994 Attributes clk gt gt sig sig active true 7 X boolean sig delayed t sig event true boolean sig quiet t boolean E sig stable t boolean sig transaction A A bit 1T 2T 3T 4T 5T 6T 7T 8T Figure 10 4 Example of All The Signal Attributes Mentor Graphics VHDL Reference Manual July 1994 10 39 Attributes The following table shows the values of the attributes that Figure 10 4 does not show at times 4T through 6T These examples assume 3T 30 ns 4T 2 40ns 5T 2 50nms Signal Attribute Value at AT Value at 5T Value at 6T sig last active 4T AT Ons ST 5T 0 ns 6T 6T 0 ns sig last event AT 3T 10 ns ST 5T 0 ns 6T 5T 10 ns sig last value UL 0 Type Attributes You use the type attributes for determining bounds position or actual values of the various types Types are discussed in Section 5 The following list shows the three classes of types in VHDL e Scalar integer floating poi
381. ted type The designated type must not be a file type The only kind of constraint allowed in the subtype indication is an index constraint Description Declaring an access type is a preliminary step to setting up an object called a designator such an object can be assigned access values that designate or point to other unnamed objects containing values of the designated subtype Once an access type has been declared you can create a designator hereafter called a pointer by declaring a variable of that type and then assigning an access value to that variable using an allocator expression Only variables can be declared access types and only variables may be pointed to by access values The following example illustrates the process of creating an access type access value and pointer TYPE buff IS RANGE 0 TO 1023 TYPE buff ptr IS ACCESS buff VARIABLE ptrl buff ptr NEW buff 511 Mentor Graphics VHDL Reference Manual July 1994 5 31 Types This example accomplishes three things First it declares the type buff that is the type of object that will be pointed to Second it declares an access type buff ptr of type buff This access type is now available for variables that will be used as pointers to objects of type buff Third it declares a variable ptr of access type buff ptr and uses an allocator expression the reserved wor
382. ted waveforms waveform when choices gt N 3 6 27 sensitivity clause gt on sensitivity list gt 6 49 Mentor Graphics VHDL Reference Manual July 1994 A 57 Syntax Summary sensitivity list sienal name gt 6 41 sequence of statements v sequential statement c 6 15 A 58 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary sequential statement wait statement assertion statement signal assignment statement variable assignment statement procedure call statement 1f statement p case_statement loop_statement next_statement e exit statement gt N return statement null statement gt po 6 5 e 2 22 Mentor Graphics VHDL Reference Manual July 1994 A 59 Syntax Summary signal assignment statement target lt transport waveform E 2 6 46 signal declaration signal identifier list subtype indication K signal kind o expre
383. teger to integer assumes a 2 s complement representation Overloaded math and logic operations FUNCTION AND 1 r qsim state RETURN qsim state cc AND rXlQ I X 2 0 0 0 0 0 1 0 1 X X X 0 X X X Z 0 X X X FUNCTION OR l r qgsim state RETURN qsim state OR r l 0 X 2 0 0 X X 1 il im X X X X Z X X X FUNCTION NAND 1 r qsim state RETURN qsim state NAND r l 0 X 2 0 1 1 1 0 X X a X X X X Z X X X Mentor Graphics VHDL Reference Manual July 1994 9 41 Design Units and Packages 9 42 LON N XRO ON Tr re NOR 1 rNl 0 1 0 1 0 ill 0 0 X X 0 Z X 0 XOR 1 xi ood 0 Qr lt 1 1 0 X X X Z X X NOT 1 NOT 1 0 X X r r l 0 0 1 0 1 Q 1 X X X Z X X 1 r r l 0 1 0 0 1 1 0 X X X Z X X lt l E r l 0 1 0 0 0 1 1 0 X X 0 Z X 0 qsim state R X 2 X X 0 0 X X X X qsim state R X 2 X X X X X X X X R qsim state RI qsim_state x gt PX PX X x gt xX XN qsim state PX PX lt lt PX xx x XN qsim state xx lt OM x x x ON ETURN qsim state RI RI ETURN qsim_state ETURN qsim state ETURN qsim state ETURN qsim state ETURN qsim state Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages
384. tenation operation and the value of new array from the preceding sens sigl process example is equivalent to the following 5 6 7 8 9 6 5 4 3 vector amp one_d 5 6 d 8 9 10 11 12 13 resultant array from concatenation 9 8 T 6 S 4 3 2 1 new array The array created by the concatenation of two one dimensional arrays has the range and direction of the left operand In the sens sig1 process the left operand vector has an ascending range 5 TO 9 Therefore the resultant array also has an ascending range The target variable new array has the range 2 24 Mentor Graphics VHDL Reference Manual July 1994 Expressions and direction specified in its own declaration not that of the array created from the concatenation of the other two variables The left bound of the resulting array is the left bound of the left operand If the left operand is a null array the resulting concatenated array uses the range and direction of the right operand In the previous sens sig1 process the resulting concatenated array has the left bound of 5 as determined by the left bound of the left operand vector The size of the resulting array matches the total size of the combined right and left operand array sizes The elements of the resulting array consist of the elements of the left operand followed by the elements of the right operand 2 F
385. tes X LIBRARY mentor USE mentor qsim logic ALL PACKAGE qsim relations IS FUNCTION 1 r qsim state RETURN boolean Ix ROK TAA oO AAPA AR on nn on xX HAN H FUNCTION 1 qsim state RETURN boolean um w a ape Hj c nj nj AAR HR gx HAAN qsim state RETURN boolean Fy 1G lt Q H Z E Ez op 1 nj nj nj np trj rr fz Hj pq n Hj tr nj N Hy GA lt Q H O z v m qsim state RETURN boolean 440 noz o on XK rz rz N Mentor Graphics VHDL Reference Manual July 1994 9 47 Design Units and Packages FUNCTION lt l r qsim state RETURN boolean lt r l 0 1 X ES 0 p BO E gt 1 JF AMES CE l e X E E CE GE 2 T F F E FUNCTION gt 1 r qsim state RETURN boolean gt dno XZ zA 0 qp lw gt Ee mE 1 F T F E mE X Ro WESIGBS GE F I F E FUNCTION same 1 r qsim state RETURN boolean True equivalence FUNCTION lt E qsim state vector RETURN boolean FUNCTION l Y qsim state vector RETURN boolean FUNCTION LT qsim state vector RETURN boolean FUNCTION 1l r qsim state vector RETURN boolean FUNCTION 1 r qsim state
386. tes this concept The following code shows the concept that Figure 5 2 illustrates TYPE test IS RANGI SUBTYPE my test E d TOTO Range expr is type integer IS test RANGE 1 TO 5 Type mark test also integer type range range attribute name simple expression direction simple expression Ae Must have the same base type E subtype indication resolution function name type_mark constraint Figure 5 2 Range Constraints in Subtype Indications Mentor Graphics VHDL Reference Manual July 1994 Types If each element in a range constraint bound is a member of the range subtype and the range bounds are not exceeded then the range constraint is compatible with the subtype range If they have different base types or range bounds then the range constraint is not compatible with the subtype range For example TYPE t1 fa SUBTYPE IS RANGI IS ti fd RANGI E 1 TO 10 The two ranges are not jrd E 11 TO 25 compatible because range bounds exceeded If the range constraint is a null range then any applicable subtype range bound type can be specified Each of the scalar types use the preceding range concepts The following subsections discuss each of the scalar types in detail M
387. tester bit CONSTANT offsets real 0 5 PROCEDURE test vectors SIGNAL clk IN bit proced SIGNAL test INOUT bit decl CONSTANT offset IN real 0 5 PROCEDURE test vectors SIGNAL clk IN bit proced SIGNAL test INOUT bit body CONSTANT offset IN real 0 5 IS BEGIN NULL ummy body for example END BEGIN test vectors clock tester offsets con proced call PROCESS equivalent process BEGIN test vectors clock tester offsets WAIT ON clock tester sens list formed by in and END PROCESS inout signals END test 6 22 Mentor Graphics VHDL Reference Manual July 1994 Statements concurrent signal assignment stmnt The concurrent signal assignment statement is an equivalent process statement generated by the system that assigns values to signals Construct Placement concurrent statement architecture statement part block statement part Syntax concurrent signal assignment statement label conditional signal assignment label selected signal assignment options guarded transport Description The concurrent signal assignment can take two forms e Conditional signal assignment Selected signal assignment The following rules apply to both for
388. tester follow PROCEDURE ram load CONSTANT op code IN op code array PROCEDURE concat data CONSTANT ram data IN ram data array VARIABLE ram data conc OUT bit vector 0 TO 31 FUNCTION chk pty CONSTANT ram data conc IN bit vector 0 TO 31 CONSTANT op code conc IN bit vector 0 TO 31 RETURN boolean Mentor Graphics VHDL Reference Manual July 1994 7 7 Subprograms formal parameter list Subprogram parameters are the items that designate which object type and in which mode the values in subprograms are passed These parameters are specified in a formal parameter list For information on interface lists and modes refer to page 4 22 Construct Placement subprogram specification Syntax formal parameter list parameter interface list Description Table 7 2 shows the valid object type and mode for a function and a procedure Table 7 2 Subprogram Parameters Procedures Functions Object constant constant Classes signal signal variable Modes in in out inout When you do not specify an object class in the subprogram declaration there is a default These defaults are defined by the following list e For procedures O If the mode is in constant is the default O If the mode is out or inout variable is the default O If no mode is given in is the default mode and constant is the defaul
389. the only predefined floating point type Real is specified in package standard as TYPE real IS RANGE 1 79769E308 TO 1 79769E308 This assumes a machine that follows EE double precision standard CAUTION Do not use predefined type names for your own definitions While it is possible to do so it can become very confusing for you to keep track of when the system is using its definition of a predefined type or is being overwritten to use your definition 5 14 Mentor Graphics VHDL Reference Manual July 1994 Types physical type definition Physical types describe measurements of a tangible quantity in a multiple of the base unit of measurement within the range you specify Construct Placement scalar type definition type definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax physical type definition range constraint units base unit declaration secondary unit declaration end units base unit declaration identifier secondary unit declaration identifier 2 physical literal physical literal abstract literal unit name Definitions B base unit declaration The base unit declaration is used to define a unit name The base unit declaration can be considered the root measure
390. the specified parameter n Evaluation Result D0O 1 1 The result returns the upper bound of the index range specified by the parameter n The index range is all the possible index values in a specified range Mentor Graphics VHDL Reference Manual July 1994 10 11 Attributes Example The following example shows an attribute portion of a code description TYPE arr 1 IS ARRAY integer RANGE lt gt OF integer VARIABLE matrix arr 1 1 TO 3 9 DOWNTO 6 array var decl matrix high 1 parameter n is 1 lt Returned value is 3 matrix high 2 parameter n is 2 lt Returned value is 9 When the parameter n is 1 the boxed column is examined The value that returns is 3 which is the value of the upper bound of the array index that the parameter 1 specifies When the parameter n is 2 the horizontal row is examined In this example a 9 is returned 10 12 Mentor Graphics VHDL Reference Manual July 1994 Attributes left n Kind Function Prefix gt gt Any valid array object prefix or a prefix that designates a constrained array subtype Parameter OA An expression of type universal_integer which can be evaluated during the current design unit analysis locally static expression The value of this expression cannot be larger than the array object dimension If you do not include this expression the d
391. ther clauses cause the process to resume The following are illegal uses of the wait statement that generate errors You use the wait statement in a function e You use the wait statement in a procedure that is called from a function You use the wait statement in process statement that has a sensitivity list You use the wait statement in a procedure that is called by a process with a sensitivity list Example 3 Jh 42 The following examples show some of the various forms the wait statement can take WAI WAI WAI WAI WAI ON sync pulse No condition or timeout clause UNTIL counter 7 Using condition clause ON interrupt FOR 25 ns Using timeout clause ON clk sensor UNTIL counter 3 FOR 25 ns Using all FOR 1 ns Using only the timeout clause HHHHHAH 6 50 Mentor Graphics VHDL Reference Manual July 1994 Subprograms Section 7 Subprograms This section describes subprograms which can be either procedures or functions Subprograms allow you to place computational sequences or behavior descriptions into stand alone modules that can be invoked repeatedly from other locations in your design description The following list contains the topics and constructs explained in this section Definition of a Subprogram 73 subprogram declaration 76 formal_parameter_list 0 0 7 8 subprogram_body OO
392. this case an initial value of 1 2 3 4 is assigned to the object You set this up by inserting a tick mark after the type or subtype name followed by a value in parentheses as follows type name initial value O Assigns an access value address to ptr1 which can then be used to reference the object Line 5 creates a new pointer ptr2 and a new object but in this case the object assumes a default value The default value for each element of this object is the default value for the type buff elem type which is 0 buff elem type LEFT e Line 6 assigns the access value of ptr1 to ptr3 these pointers now point to the same object e Line 8 assigns the value of the object pointed to by ptr1 to the object pointed to by ptr2 The suffix ALL dereferences the pointers causing the values of Mentor Graphics VHDL Reference Manual July 1994 2 15 Expressions the objects to which they point to be assigned instead of the addresses of the objects e Line 9 assigns the value of element 0 of the object pointed to by ptr1 to the variable v1 that was declared in line 8 The ALL is not actually necessary in this case but it does document that the value of the element rather than its address is being assigned e Line 10 deallocates the storage space reserved for the object pointed to by ptr1 The implicit procedure deallocate exists for each access type you create Once storage for an object has been deallocated it is an
393. this concept Code Portion Signal Waveforms ASSERT NOT preset delayed 5 ns 1 preset AND preset 0 bit REPORT Check Failed SEVERITY warning preset delayed bit 15 20 25 30 35 time ns Figure 10 3 Signal Attribute Concept The previous example shows the signal attribute delayed combined with the signal preset the prefix to create another signal preset delayed This signal is preset delayed by 5 ns You can use the signal attribute signal in several ways as the following list shows e Sensitivity lists of process and wait statements O Guard expressions e Read the signal You cannot make assignments to the attribute signal The remaining signal attributes are functions that return values about a signal For more information on signals refer to Section 11 The following subsections discuss each predefined signal attribute in detail Examples of the signal attributes are more informative if they are shown together Therefore there is one example on page 10 38 that shows the use and effects of all the signal attributes 10 28 Mentor Graphics VHDL Reference Manual July 1994 Attributes active Kind Function Prefix KE Any signal designated by the signal name All the expressions in the signal name can only depend on constants or generics Result Type lt Boolean Evaluation Result If the signal that the prefix spe
394. tion attribute specification disconnection specification use clause Definitions gt 0 0 0 o B package simple name An identifier that you provide to give the package a unique name which is referenced by other primary or secondary units B package declarative part Contains declarations of items that can be made visible to design files outside the package Mentor Graphics VHDL Reference Manual July 1994 9 13 Design Units and Packages Description When you define a package declaration that does not declare deferred constants discussed on page 4 13 or subprograms the package does not require a package body The following team info package example requires a package body because it contains subprogram declarations convert chk and data check and a deferred constant Ge erred const Example The following example shows a possible package declaration PACKAGE team info IS package declarative part FUNCTION convert chk result array IN bit vector 0 TO 7 RETURN boolean PROCEDURE data check VARIABLE add start IN bit vector 0 TO 7 VARIABLE chk answer OUT boolean TYPE storage IS ARRAY 0 TO 23 OF integer TYPE opcode IS ARRAY 0 TO 7 OF storage CONSTANT default volt integer 5 CONSTANT deferred const integer SIGNAL enable 5 ba USE global
395. tion As the BNF description shows the subprogram declaration consists of a subprogram specification which defines the name of the subprogram and the parameters if any to be passed The subprogram specification determines the parameter types If the subprogram is a function the subprogram specification defines the result type returned The following list shows the rules that govern subprogram declarations A procedure designator can only be an identifier The subprogram specification must match the subprogram specification in the subprogram body A function designator can be an identifier or an operator symbol for operator overloading 7 6 Mentor Graphics VHDL Reference Manual July 1994 Subprograms The operator symbol must be one of the predefined operators discussed on page 2 16 Procedures and functions can be called recursively Example The following subprogram declaration is from the code for the memory programmer and tester described in the introduction to this section It is the RAM read procedure Address RAM eso Read RAM Lodh Procedure PROCEDURE ram read VARIABLE ram data OUT ram data array VARIABLE test add start OUT integer 0 TO 255 ram data is read from RAM starting at location specified by test add start The subprogram declarations for the remaining subprograms in the memory programmer and
396. tion clause or timeout clause appears in the implied wait statement For more information on the wait statement refer to page 6 49 A guarded signal has no effect on the assertion evaluation unless the guarded signal appears in the assertion condition Mentor Graphics VHDL Reference Manual July 1994 6 19 Statements Example The following example shows a concurrent assertion statement and the equivalent process statement that the system creates ARCHITECTURE test OF parts IS B EGIN sig check Label ASSERT preset 1 AND clk 1 Concurrent assertion stmnt REPORT Output Change Allowed SEVERITY note END test equivalent process PROCESS BEGIN ASSERT preset 1 AND clk 1 REPORT Output Change Allowed SEVERITY note WAIT ON preset clk Sensitivity list formed by signals END PROCESS in the assertion condition expres 6 20 Mentor Graphics VHDL Reference Manual July 1994 Statements concurrent procedure call The concurrent procedure call statement is an equivalent process statement generated by the system that contains a sequential procedure call and a wait statement at the end For more information on the sequential procedure call statement refer to page 6 40 Construct Placement entity statement concurrent statement architecture statement part block statement part S
397. tion declarative item 8 35 configuration item block configuration component configuration gt 8 39 configuration specification for component specification N M lt gt use binding indication gt gt 8 25 A 24 Mentor Graphics VHDL Reference Manual July 1994 Syntax Summary constant declaration constant identifier list m subtype indication pS expression 4 13 constrained array definition array index constraint of element subtype indication 5 23 constraint gt gt range constraint y index constraint S gt 4 7 context clause y context item Ld gt 9 5 context item gt library clause use clause gt gt 9 5 Mentor Graphics VHDL Reference Manual July 1994 A 25 Syntax Summary a h decimal_literal integer m gt integer LL exponent LA 1 16 declaration type_declaration y subtype declaration object declaration file declaration p interface declaration gt alias declaration
398. tion on attributes both user defined and predefined Attributes allow you to associate information with an item The following ordered list shows the constructs and topics this section discusses Attribute Overview A J 101 atribute name 1 1 1 S 0 3 Predefined Attributes 1 10 5 Detailed Predefined Attribute Descripton 10 7 Array Object 10 8 Block Attributes 24 Signal Attributes 1 1 10 28 Type Attributes __ A A 10 40 User Defined Attributes J J Aw 10 53 attribute_declaration 1 1 10 54 attribute specification 10 55 Attribute Overview An attribute is a named characteristic that is associated with one or more items in a VHDL description There are two varieties of attributes Predefined attributes are part of the predefined language environment Predefined attributes are useful for examining the characteristics of arrays types and blocks or for querying and manipulating the values of signals User defined attributes allows you to add additional information that cannot be described using other VHDL constructs For example you might want to back annotate physical characteristics such as output and input capacitances to a design Mentor Graphics VHDL Reference Manual July 1994 10 1 Attributes Design Units Design Entities Configurations Packages Attributes Componen
399. tiplying operator For information on multiplying operators refer to page 2 20 A miscellaneous operator For information on miscellaneous operators refer to page 2 18 An adding operator For additional information refer to Adding Operators For example A B Illegal exp sign follows multiplying operator B C Illegal exp sign follows multiplying operator Z B Illegal exp sign follows miscellaneous operator A B Illegal exp sign follows an adding operator If you use parentheses the previous examples can be written as legal expressions For example Ao UB legal expression B C legal expression Zo kN UB legal expression A B legal expression 2 22 Mentor Graphics VHDL Reference Manual July 1994 Expressions Adding Operators The adding operators are as follows adding operator Il amp l 4 The predefined adding operators and have their conventional definition The concatenation operator amp defines the connection of one dimensional arrays and elements Table 2 5 lists the adding operators their operations and their operand and result types Table 2 5 Adding Operators Predefined Operation Left Right Result Type Operator Operand Operand Type Type Addition Any numeric Same as left Same as left
400. tor Graphics VHDL Reference Manual July 1994 6 35 Statements loop statement The loop statement allows you to have a sequence of sequential statements execute zero or more times depending on an iteration scheme you specify Construct Placement sequential statement process statement part subprogram statement part sequence of statements Syntax loop statement loop label iteration scheme loop sequence of statements end loop oop label iteration scheme while condition for loop parameter specification parameter specification identifier in discrete range Description An iteration scheme consists of a while or for structure which controls the execution of the loop If you do not specify an iteration scheme the loop will cycle indefinitely unless the sequence of statements contains an exit or return statement In this case if the condition or expression is satisfied the statement executes and the loop sequence stops The while iteration scheme controls the loop using a condition you specify This condition is a Boolean expression If the expression evaluates to TRUE the sequence of statements in the loop executes If the return value is FALSE the loop exits and the sequence of statements is not executed The for iteration scheme controls the number of times the loop executes using a discrete range you specify in the loop parameter You can use only the loop paramete
401. trained as the following pages describe The diagrams on page 5 23 show some of the related syntax for defining a constrained or unconstrained array As indicated by the BNF descriptions on page 5 23 arrays have the following characteristics An array can be constrained or unconstrained The range bounds can be of types other than integer types e You can specify the range bound type of a constrained array A constrained array is an array that has a specific subset of values for the range of the array indices You saw an example of a constrained array on page 5 24 If you specify a range using universal integers or integer literals the system assumes these indices are a subset of the type integer from package standard For example the first line in the following code is equivalent to the second line of code TYPE int array IS ARRAY 1 TO 25 OF integer This is equiv TYPE int array IS ARRAY integer RANGE 1 TO 25 to this OF integer The most common array ranges are integer types The range type for arrays does not have to be of type integer However the left and right bounds must be of the same type The range bounds can be any discrete type For example Mentor Graphics VHDL Reference Manual July 1994 5 25 Types TYPE month IS jan feb mar apr may jun jly aug sep oct nov dec TYPE hours IS RANGE 0 0 TO 23 0 TYPE vacation IS ARRAY month RANGE jun TO sep OF hours
402. ts Types Signals Statements Subprograms Declarations Expressions Lexical Elements Naming Scope and Visibility Attributes i Predefined Attributes User Defined Attributes Array Object Block Signal Type Figure 10 1 Attributes 10 2 Mentor Graphics VHDL Reference Manual July 1994 Attributes attribute name An attribute name denotes a particular characteristic associated with a type subprogram object design unit component or label Construct Placement name Syntax attribute name prefix attribute designator expression attribute designator attribute simple name Definitions attribute designator The attribute designator names the attribute that you wish to use Description gt gt 0 0 0 0 When referenced by its name an attribute returns certain information about the item named in the prefix such as length of an array or whether a signal is active The apostrophe character designates that the identifier immediately following itis an attribute The apostrophe character is also used to designate qualified expressions and to enclose character literals The following code example shows the use of a predefined attribute clock delayed 50 ns clock is the prefix signal name delayed is the attribute designator simple name 50 ns is the optional static expression T
403. ty Declaration Architecture Body Y Y Entity Header Architecture Declarative Part Generics Architecture Statement Part Ports Entity Declarative Part Entity Statement Part Figure 8 1 Design Entities Mentor Graphics VHDL Reference Manual July 1994 8 3 Design Entities and Configurations entity declaration The entity declaration establishes a name for a design entity and it defines an interface for communication with the design entity Construct Placement declaration primary unit Syntax entity declaration entity entity simple name is entity header entity declarative part begin entity statement part end entity simple name Definitions B entity simple name An identifier that you provide to give the design entity a unique name that is referenced by other primary units If you use the optional name after the reserved word end it must match the name that you used between the reserved words entity and is B entity header Declares the interface for the design entity to communicate with other items in the design environment entity declarative part Contains declarations of items that are shared with other architectures having the same interface entity statement part Contains passive concurrent statements that are shared with other architectures having the same interface 8 4 Mentor Graphics VHDL Reference Manual
404. ual July 1994 Subprograms Subprogram Design Description Code Code Op Code 256 RAM Op Code 256 Procedure Cal Load gt a RAM RAM c dime Procedure File lt gt Sn Unit Procedure Call lt Bootes RAM E addu Read RAM Code 4 Procedure Pe Design Description Code Procedure Call p AM Data 4 RSS m gt Concat La S mE RAM Data Subprogram Code RAM_Data_Conc P Procedure RAM Data Conc Function Call gt p Op Code Conc E arity ada Function Value AAN AE Figure 7 2 Memory Programmer and Tester Block Diagram Mentor Graphics VHDL Reference Manual July 1994 7 5 Subprograms subprogram declaration A subprogram declaration defines a convention for calling a subprogram This convention is an interface between the subprogram and external descriptions Construct Placement block declarative item declaration entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax subprogram declaration subprogram specification subprogram specification procedure identifier formal parameter list function designator formal parameter list return type mark designator identifier operator_symbol operator_symbol string_literal Descrip
405. ue even if the architecture bodies are in the same library For more information on libraries refer to page 9 8 Mentor Graphics VHDL Reference Manual July 1994 8 15 Design Entities and Configurations Example An example of an architecture body follows ARCHITECTURE data flow OF shifter IS TYPE temp IS ARRAY 1 TO 3 OF integer arch decl part BEGIN sout lt sin 1 TO 3 0 AFTER prop delay From this point WHEN sctl 01 until the END ELSE is the arch 0 amp sin 0 TO 2 AFTER prop delay statement part WHEN sctl 10 ELSE sin 0 amp sin 0 TO 2 AFTER prop_delay WHEN sctl 11 ELSE sin 0 TO 3 AFTER prop_delay END data flow If you use architecture name here it must match architecture name used on the ARCHITECTURE line 8 16 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations architecture declarative part The architecture declarative part contains declarations of items that are used in a block that is defined by a design entity Construct Placement architecture body Syntax architecture declarative part block declarative item block declarative item subprogram declaration subprogram body type declaration subtype declaration constant d
406. ue of the generic Del to 1 5 ns The port map is necessary because the port names specified in the component declarations within mux do not match the port names given in the entity declaration inv The reserved word all is used in line 67 to bind all instances of ana to the entity declaration and2 and the architecture body and2_basic The preceding example was relatively simple having only one level of hierarchy below the top level design entity You can however specify a configuration having no internal block configurations or component configurations at all as in the following example CONFIGURATION Verl OF mux IS FOR struct END FOR END Verl This is called a default configuration In this case a set of default rules will be applied to bind components that may appear within the hierarchy of the design These rules and others are discussed in more detail in the following two subsections 8 38 Mentor Graphics VHDL Reference Manual July 1994 Design Entities and Configurations block configuration A block configuration makes the internal components of an architecture block or generate statement visible for binding Construct Placement configuration declaration block configuration component configuration Syntax block_configuration for block_specification use_clause configuration_item end for block_specification architecture_name block statement label generate st
407. uly 1994 10 23 Attributes Example The following example shows an attribute portion of a code description TYPE arr 1 IS ARRAY integer RANGE lt gt OF integer VARIABLE matrix arr 1 1 TO 3 9 DOWNTO 6 array var decl matrix right 2 parameter n is 2 lt Returns value of 6 matrix right 1 parameter n is 1 lt Returns value of 3 When the parameter n is 2 the boxed column is examined 1 2 3 The value that returns is 6 which is the value of the right bound that the parameter 2 specifies When the parameter n is 1 the vertical column is examined In this example the returned value is 3 Block Attributes Block attributes provide you with a means for checking whether certain conditions exist within a block or for returning certain information about the block 10 24 Mentor Graphics VHDL Reference Manual July 1994 Attributes behavior Kind Value Prefix Any block designated by the corresponding block label or design entity designated by the corresponding architecture name Result Type Boolean Evaluation Result The result of evaluating the attribute is TRUE if the specified block specified by the block statement or design entity does not contain a component instantiation statement If a component instantiation statement is present the
408. uration declaration Each primary unit in a given library must have a name that is different from any other primary name in that library The secondary unit name for the architecture body is the identifier following the reserved word architecture The package body has no name Every architecture in a secondary unit in the same library must have a name that is different from any other architecture that is associated with an entity declaration A secondary unit that has a corresponding primary unit can be placed only in a design library that contains that primary unit This section defines design units and related topics For more information on the following related topics refer to the indicated reference e Designentities Section 8 e Packages in this section page 9 12 The following subsections provide details on the topics discussed in this design unit overview 9 4 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages context clause Context clauses make design libraries and their contents visible to a design unit Design libraries contain compiled library units that are available for use by design units A design unit is analyzed within the environment specified by its context clauses Construct Placement design unit Syntax context clause context item context item library clause use clause Definitions B library clause A library clause makes library units with
409. vector 0 TO 23 d D sequential procedure calls ram read ram data gt mem data test add start gt address ram load codes concat data test add start ram data op code ram data conc op code concat Subprograms and Overloading There are two common uses of overloading related to subprograms e Overloading subprogram names where multiple subprograms declarations having different parameter and or result type profiles use the same name e Overloading operators where an operator such as or OR is given an additional meaning by declaring a function that uses the operator symbol as its name For a detailed example and discussion about overloading subprogram names refer to the Mentor Graphics Introduction to VHDL Mentor Graphics VHDL Reference Manual July 1994 7 17 Subprograms Overloading Operators You use a function to define a new operation for a predefined operator overloading Assume that a package called my qsim base performs overloading of predefined operators to use values from the my qsim package Here are some examples that show overloading of operators with functions from my qsim base TYPE my qsim state IS x 07 1 727 FUNCTION or L R my qsim state RETURN my qsim state FUNCTION L R my qsim state RETURN boolean FUNCTION L R my qsim state RETURN my qsim state
410. write linel charl RIGHT 0 writeline outl linel WAIT Se END PROCESS e lt D behav 9 32 Mentor Graphics VHDL Reference Manual July 1994 Design Units and Packages Mentor Graphics Predefined Packages Mentor Graphics has created packages that define various types and subprograms that make it possible to write and simulate a VHDL model within the Mentor Graphics environment These packages are written in standard VHDL and can be compiled on any system that supports the language E Of the packages that Mentor Graphics supplies one package called math is located in the std library along with the standard and textio packages The math package contains the set of ANSI C math functions and constants Other Mentor Graphics supplied packages are located in a library called mgc portable These packages are as follows e qsim logic The package qsim logic contains basic 4 state and 12 state types along with supporting resolution conversion and operator functions e qsim relations The package qsim relations defines all relational operators for qsim state that return boolean to deal with unknown states X reasonably Also defined are relational operators for bit vector that do numerical comparisons by zero extending shorter operands The headers for the Mentor Graphics predefined packages have been provided in the following subsections The package bodies are available f
411. y declarative item package declarative item process declarative item subprogram declarative item Syntax scalar type definition enumeration type definition integer type definition floating type definition physical type definition Description There are four scalar types as Figure 5 1 shows The scalar type definition defines a range of values that the object can assume For example a 10 ns Physical type 10 ns completely specifies a b 4 7 Floating point type 4 7 specifies bp Subsets of values for scalar types are specified by a range If the subset is empty the range is defined as a null range The following subsection shows the related syntax for a range 5 4 Mentor Graphics VHDL Reference Manual July 1994 Types range constraint Subsets of values for scalar types are specified by a range constraint Construct Placement constraint floating point type definition integer type definition physical type definition Syntax range constraint range range range range_attribute_name simple expression direction simple expression direction to downto Definitions BW simple expression You define the upper and lower range bounds with a simple expression B direction You define a range direction as either ascending or descending Description The relationship between range constraint bounds left right low and high is important to understand especial
412. y static e Globally static range a range with bounds that are globally static expressions e Globally static range constraint a range constraint with a range that is globally static e Globally static scalar subtype a scalar type or subtype or base type that is formed by restricting a globally static subtype by imposing a globally static range e Globally static discrete range a globally static subtype or globally static range Globally static index constraint an index constraint in which each index subtype of the corresponding array type is globally static Each discrete range is globally static Mentor Graphics VHDL Reference Manual July 1994 2 35 Expressions e Globally static array subtype a constrained array subtype that is formed by restricting an unconstrained array type using a globally static index constraint Ranges are discussed on page 5 5 scalar types are discussed on page 5 4 and arrays are discussed on page 5 22 Universal Expressions A universal expression is an expression that has a result type of universal integer or universal real For a discussion about universal integer and universal real refer to pages 5 9 and 5 12 respectively For any integer type predefined operation there is an equivalent universal integer predefined operation Likewise for any floating point type predefined operation there is an equivalent universal real predefined operation Table 2 9 lists the
413. y the system The preceding BNF description shows the concurrent statements that are available in VHDL The ability to express concurrent action is especially important when you model logic circuits The reason for this is that logic circuits often work in parallel where a change in one signal can propagate through several devices at the same time Mentor Graphics VHDL Reference Manual July 1994 6 7 Statements Statement Quick Reference Table 6 1 is a quick reference table that lists all the VHDL statements The table heading descriptions for this table follow e Statement the name of the statement e Reserved Words the reserved words used in the statement if any e Class Con indicates a concurrent statement classification Seq indicates a sequential statement classification e Description a brief description of the statement Table 6 1 System 1076 Statements Reserved Statement Words Class Description Assertion assert Seq Checks if specified condition is true and report if so reports a message and a severity severity level Block block Defines an internal block and groups begin Con concurrent statements together end Case case Selects one of a number of statement is Seq sequences for execution end Component None Instantiates a subcomponent within a Instantiation Con design entity Concurrent assert Represents a process statement Assertion report Con contain
414. yntax concurrent procedure call label procedure call statement Description The syntax for this statement is the same as for the sequential procedure call statement except for the optional label The system knows when to create a concurrent procedure call by the location of the procedure call statement because concurrent statements are allowed only in internal and external blocks The concurrent procedure call is a shorthand way to declare procedures that represent commonly used processes by calling the procedure as a concurrent statement the equivalent process is automatically created by the system The implied wait statement gets its sensitivity list from signals of mode in or inout from the actual part of any association element in the concurrent procedure call Any other condition produces no sensitivity clause For more information on the wait statement refer to page 6 49 A guarded signal has no effect on the concurrent procedure call statement evaluation unless the guarded signal appears in association list of the actual parameter part construct A concurrent procedure call appearing in an entity statement part must be passive Mentor Graphics VHDL Reference Manual July 1994 6 21 Statements Example The following example shows a procedure declaration a concurrent procedure call a small procedure body and the equivalent process that the system creates ARCHITECTURE test OF parts IS SIGNAL clock
415. ype definition type declaration block declarative item entity declarative item package body declarative item package declarative item process declarative item subprogram declarative item Syntax record type definition record element declaration element declaration end record element declaration identifier list element subtype definition element subtype definition subtype indication Definitions B clement declaration Declares the subtypes of one or more record elements named in the identifier list Description A record type groups objects of different types so they can be operated on as a single object The record type definition contains of a series of element declarations each of which contains one or more element identifiers and a subtype indication for those elements All the element identifiers must be unique The following example shows two record type definitions Mentor Graphics VHDL Reference Manual July 1994 5 29 Types TYPE coordinates xvalue yvalue END RECORD TYPE half day IS TYPE clock time S RECORD integer am pm S RECORD minute second ampm half day END RECORD hour integer RANGE 1 TO 12 integer RANGE 1 TO 600 You can read from and assign data to individual elements of a record To access an individual record element you use the select
416. ypes that have the same base type This is not legal for different types Here is an example of taking a subtype of a larger type TYPE color IS red yellow green orange blue violet purple pink brown olive gray black white copper silver SUBTYPE traffic color IS color RANGE red TO green The following examples compare calculations involving different types to calculations involving different subtypes TYPE result IS ZSUBTYPE result IS integer HL s ace EL Z RANGE 1 TO 20 i Te ZSUBTYPE ans IS integer VARIABLE a result Z ER VARIABLE b z ans RANGE 10 TO 50 any operation with the ZVAR ABLE a result preceding variables ZVARIABLE b z ans Rllegal Z Intermediate operations with v f Z the preceding variables is a b gt 1 ega y ua Z legal z a b illega f Za b legal Zz a b Range check done to Z determine if legal or illegal In the preceding example the left column shows the declaration of two different types the declaration of two variables and an example of an intermediate calculation using the different types This calculation is not legal because operations must be performed on items that have the same base type In the preceding example the right column shows the declarati

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