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mohamad amin bin noordin 19 february 1989 remote video

1. This is the design of the remote video surveillance system for this project in block diagram The Nios II processor is central or core of this system It will be connected to the flash memory and also the DM9000A Ethernet controller chip This three components will be built using SOPC builder in FPGA The FPGA DE2 board will be connected to the computer and the data transfer will be done through the Davicom DM9000A chip Physically the communication will be done using and Ethernet cable and the connection is through the RJ45 port on both the FPGA DE2 and also the computer A router in an optional in this project since the establishment of connection and sending data from DE2 board to computer is the main target of the project This project design emphasize the client server relationship Where the computer is the client and the FPGA DE2 is the server The client will make request to access the image file in the flash memory through a web browser and the server will respond by executing the request Nios Il Processor Davicom DM9000A Ethernet Controller ee Figure 3 1 Block Design of System 28 3 5 Operation Flow Figure 3 2 below shows the operational flow of the overall project which is from the storing of image file until the display of image file on browser through the computer Image stored into flash memory User will use computer connected to network to access image User will open browser and enter the IP a
2. int use_dhcp int ret_code 0 int sw struct netif netif lwip_dev gt netif sw IORD SWITCH_PIO BASE 0 if sw a 1 17 char buf 32 char buf1 32 u char ip3 ip4 u char ptr use dhcp 0 ip3 sw gt gt 12 Ox0F ip4 sw gt gt 8 OxOF 128 sprintf buf 192 168 d d ip3 ip4 LCD Show Text buf LCD_Line2 sprintf bufi MAC 009000AE00 2X netif gt hwaddr S LCD Show Text buf1 VERB Use static IP configuration IP ts n buf ptr u_char ipaddr ptr 192 ptr 168 ptr ip3 ptr ip4 ptr u char netmask ptr Oxff ptr Oxff ptr OxXff ptr 0 ptr u char gw ptr 192 ptr 168 ptr ip3 ptri 1 return 1 of use static if strcmp lwip dev name dev LWIP DEFAULT IF if LWIP_DHCP 1 use_dhcp 1 adapter lwip dev netif else IP4 ADDR ipaddr IPADDRO IPADDR1 IPADDR2 IPADDR3 IP4 ADDR gw GWADDRO GWADDR1 GWADDR2 GWADDR3 IP4 ADDR netmask MSKADDRO MSKADDR1 MSKADDR2 MSKADDR3 use dhcp 0 endif LWIP DECP ret_code 1 return ret_code 55 if LWIP DHCP 1 void dhcp timeout task int have_address 0 timeout_dhcp 0 struct ip addr ipaddr netmask gw INTEU return_code OS NO ERR OSSemPend attained_ip address sem 0 amp return code while 1 4
3. Signature Name of Supervisor ASSOC PROF DR MUHAMMAD NASIR BIN IBRAHIM Date 24 June 2013 REMOTE VIDEO SURVEILLANCE USING FPGA MOHAMAD AMIN BIN NOORDIN A thesis awarded in fulfilment of the requirement for the award of Bachelor Degree in Electronics Engineering Faculty of Electrical Engineering Universiti Teknologi Malaysia June 2013 T hereby declare that this thesis entitled Remote Video Surveillance Using FPGA is the result of my own research except as cited in the references The thesis has not been accepted for any degree and is not concurrently submitted in candidature of any other degree Signature Name MOHAMAD AMIN BIN NOORDIN Date 24 June 2013 Dedicated to my beloved mother brother and sister and in the memories of my father ACKNOWLEDGEMENT First and foremost I would like to express my greatest gratitude to my supervisor Assoc Prof Dr Muhammad Nasir bin Ibrahim for the guidance enthusiasm and motivation given throughout the progress of this project Without his continuous support and interest this project would not be accomplished as presented here My sincere appreciation also goes to my mother brother and sister who has been supportive and has given me encouragement either morally or financially which enabled me to pursue on finishing the project I would also like to thank my friends who has directly or indirectly helped me in giving opinions ideas and other use
4. Type of cable used for Ethernet port connection is cat5 cable with RJ45 connector 12 F J S Figure 2 5 Block Diagram for DM9000A Inc 2006 Altera FPGA DE2 board has 10 100 Ethernet Controller with a connector The DE2 board uses Davicom DM9000a as the Ethernet controller which has a general processor interface It is a cost effective and low pin count single chip Fast Ethernet Controller It has integrated MAC and PHY and supports 100base T and 10 base T applications Moreover it is also fully in accordance with the standards IEEE 802 3u specifications It also supports IP TCP UDP checksum generation and checking DM9000a supports 8 bit and 16 bit data interfaces to internal memory accesses 13 N vocu Q VCC Am APA NGND 4 wu jou OW zan Ta c7 BC BCS 6 6m qH Ri 2 RA L BEAD 45 49R9 N VOC FR T A os oy oe ce CT O j NVOCIIO A T Ly a YOL il veca 7 T Vi N VECJO R Ru CHSGNO aaro aoro CHSGND J w NOND ON VOU Figure 2 6 Fast Ethernet interface schematic inside FPGA Corporation 2006 2 5 Universal Serial Bus USB USB that was developed in the mid 1990s is an industry standard that defines cables connectors and communications protocols that are used in bus for the purpose of data transfer device communication and power supply to connected devices Nowadays all computers have a USB connectors Wit
5. q p remains amp amp q q q gt next dm9k_meminw pdev q gt payload q gt len remains q gt len of fill loop finally read out the 4 byte CRC dm3k datinw pdev dm3k datinw pdev if LINK STATS lwip stats link recv i endif LINK STATS dm3k idxout pdev saveidx return p 67
6. 2 It is a small real time kernel mainly written in C language which is intended for use in embedded systems In this project this component is required to run the web server type system MicroC OS II or uCOS II is part of Real Time Operating System RTOS RTOS is an operating system intended to serve real time application request This problem related to software problem so Altera was contacted regarding this problem through e mail Altera engineers gave their insight regarding this problem that uCOS II component is missing due to Nios II software not installed properly and the current software might be broken So the software was re downloaded at Altera ftp site and Nios II software was reinstalled However this did not solve the problem Altera was contacted again but this time the engineers suspects the IP core might have some problem and not the software Since the IP core was provided by TERASIC the problem was re directed to TERASIC for troubleshooting TERASIC engineer suggested a method to solve the problem The project was recreated under the web server template which is available during the project creation in Nios II The coding in c language and the image file in zip format was copied into the new project The project was built but the problem still persists TERASIC was contacted again and the engineers suggested that Altera should be consulted regarding this problem as this problem was due to software error Alte
7. 7 LIST OF FIGURES TITLE The DE2 Board Block Diagram of DE2 Board Nios II Processor Cat5 Cable with RJ45 Connector Block Diagram for DM9000A Fast Ethernet interface schematic inside FPGA Type A Type B USB ISP1362 Host and Device Schematic ISP1362 Architectural Diagram Hardware Principe Diagram The connection of DM9000A with Nios II CPU Proposed FPGA Based Data Communication for Smart Grid Entity Communication Channels Block Design of System Operation Flow index html not_found html DE2 Control Panel Flash Memory Erasing Write to Flash Memory SOPC Hardware Design Nios II Processor Type PAGE 11 12 13 14 14 15 16 17 18 19 21 27 28 30 30 31 31 32 33 34 Xi 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 Nios II Processor Instruction and Data Bus Setting Nios II JTAG Setting Flash Memory Data and Address Width Flash Memory Timing Red LED Setting Green LED Setting Button Setting Switch Setting DM9000A Custom Component Creation Wireshark Protocol Analysis Wireshark Protocol Hierarchy Statistics DE2 Switches LCD Display of MAC and IP Address Image Display on Browser MicroC OS II Missing Component System Library Properties 34 35 35 36 36 36 37 37 38 39 40 42 43 44 45 45 Xii FPGA PCB IP TCP UDP HDL LE GPIO RTOS MMU EDS ACK SMTP FTP HTTP LAN CSMA D MAC PHY USB OTG SOPC CMOS ICMP ARP
8. BASE Text i usleep 2000 void LCD Line2 lcd write cmd LCD 16207 0 BASE OxC0 usleep 2000 void LCD Test ki char Texti 16 lt NIOS II on DE2 gt char Text2 16 Nice to See You Initial LCD LCD Init Show Text to LCD LCD Show Text Text1 Change Line2 LCD_Line2 Show Text to LCD LCD Show Text Text2 dm9000 c define USE ARP SEMAPHORE include dm9000 h ifdef ALT DEBUG define VERB msg printf msg else define VERB msg do while 0 endif inline void dm9k idxout alt avalon dm9k if pdev u_char val IOWR pdev gt base_addr pdev gt index_offset val inline u_char dm3k idxin alt avalon dm3k if pdev return u_char IORD pdev gt base_addr pdev gt index_offset amp Oxff inline void dm3k datout alt avalon dm3k if pdev u_char val IOWR pdev gt base_addr pdev gt data_offset val inline u_char dm9k datin alt avalon dm3k if pdev return u_char IORD pdev gt base_addr pdev gt data_offset amp Oxff inline void dm3k datoutw alt_avalon_dm9k if pdev u short val IOWR pdev gt base_addr pdev gt data_offset val aaa u short dm9k datinw alt avalon dm9k if pdev l return u short TORD pdev base addr pdev gt data_offset Oxffff inline void dm9k datoutl alt avalon dm3k if pdev u long val IOWR pdev gt base_addr pdev gt data_offset val inline u long dm9k datinl alt ava
9. Interrupt The interrupt mode will be chosen by devices like mouse or keyboard which only send very little data 2 Bulk Bulk transfer mode a used by devices like printers which receives data in one big packet Data is sent to the printer in 64 bit chunks and will be verified later to make sure its validity 3 Isochronous 15 Isochronous mode is used by streaming device such as speakers where data streams between the devices in real time and does not involve any error correction Figure 2 9 USB ISP1362 Host and Device Schematic Corporation 2006 In FPGA DE2 board It provides USB Host Slave controller with USB type A and type B connectors It complies with USB 2 0 where it supports data transfer at full and low speed and also supports both USB host and device This USB host and device interfaces are provided using the Philips ISP1362 single chip USB controller 16 12 MHz CLKOUT xi x2 co POWER ON p internal HC BUFFER RESET reset MEMORY PLL H_SUSPEND FLWARFUP i to system dock ADVANCED HOST Is CONTROLLER potencies DO to DIS a z o ON THE GO BUS CONTROLLER Ai INTERFACE Dror OTG DEVICE TRANCEIVER WT CONTROLLER Wr DC BUFFER MEMORY GOODLINK D SUSPEND a OIGMoObLE ID CP CAP CP CAPI DLWAKEUP Figure 2 10 ISP1362 Architectural Diagram Semiconductor 2002 The ISP 1362 includes the OTG controller where a
10. Switches LCD display DM9000A Ethernet controller chip and Jtag UART The interconnection between this components are made through Avalon bus For the part of bus width matching bus arbitration and clock domain crossing it will all be handled by the SOPC builder Apart from using the SOPC builder to create the soft hardware components Verilog language will be used to create the top level module 25 3 2 2 Software Design The software design of this project is done using the Nios II IDE software which is part of the Altera software package that comes with the Quartus II software The software part is actually a coding which are done using C language There are several coding need to be done in order to create a complete system These includes the creation of Internet protocol IP for transport layer which is either TCP or UDP the creation of c file for retrieving the image from the flash memory creating c files for the initialization and setting of IP address and MAC address creating c file for LCD display and the creation of c file for the protocol and communication of the DM9000A Ethernet controller chip 3 2 3 Image File Creation and Storing The image file will be created in a format so that it can be stored inside the flash memory of FPGA DE2 In order for the image to be viewed through the browser it will be stored in an html format where the image will be embedded in it 3 3 TCP vs UDP TCP stands for transmissio
11. TITLE gt lt HEAD gt lt title gt LWIP on Nios II lt title gt lt BODY gt lt hi gt HTTP Error 404 lt hi gt lt center gt lt h2 gt Nios II Web Server Demonstration lt h2 gt Can t find the requested file file Have you programmed the flash filing system into flash lt html gt he static const alt 8 hello http_response HITP 1 0 200 r n Content Type text html r n Content Length 203 r n r n lt HTML gt lt HEAD gt lt TITLE gt Nios II Web Server Demonstration lt TITLE gt lt HEAD gt lt title gt LWIP on Nios II lt title gt lt BODY gt lt br gt lt br gt lt center gt lt hi gt Nios II Web Server Demonstration lt h1 gt lt br gt lt h2 gt Hello World lt h2 gt lt br gt lt center gt lt html gt he typedef struct funcs alt u8 name void func post_funcs void print printf HITP POST received n post funcs mapping PRINI print Me void http_reset_connection http_conn conn int http_instance memset conn 0 sizeof http_conn conn gt fd 1 conn gt state READY conn gt keep alive count HTTP KEEP ALIVE COUNT conn gt rx_buffer alt u8 amp http rx buffer http_instance 0 conn gt tx_buffer alt u8 amp http_tx_buffer http_instance 0 conn gt rx_wr_pos alt u8 amp http rx buffer http_instance 0 conn gt rx_rd pos alt u8 amp http rx buffer http_instance 9 59 void http manage conne
12. addr int ret_code 0 Find the Carriage return which marks the end of the header 1f addr strchr conn rx rd pos n if If addr NULL ki ret code 1 else if 1f_addr gt conn gt rx_buffer s 1f_addr 1 Ar ki 1f_addr 1 0 1 addr 0 conn gt rx_rd_pos 1f addr i return ret_code int http process headers http conn conn alt_u8 option alt u8 orig read pos conn gt rx_rd_pos alt u8 temp if temp strstr conn rx rd pos conn gt rx_rd_pos temp 1 else return 1 option strtok orig read pos if stricmp option Connection 0 alt u8 temp option 17 option 17 0 if stricmp option 12 close 0 conn gt close 1 option 17 temp else if stricmp option Content Length 0 conn gt content_length atoi option 16 return 0 int http process request http conn conn alt_u uri 0 alt_u amp version 0 alt_u temp 0 if temp strstr conn rx rd pos GET conn gt action GET conn gt rx_rd_pos temp else if temp strstr conn gt rx_rd_pos POST conn gt action POST conn gt rx_rd_pos temp else fprintf stderr Unsupported for now request n conn gt action UNKNOWN return 1 61 while 1 FD ZERO readfds FD ZERO writefds FD SET fd listen readfd
13. bus interface connects a host controller and a peripheral controller to the external CPU Both the host controller and peripheral controller includes built in memory to buffer USB traffic The USB OTG controller also provides control switching functions and monitoring necessary for the OTG operations 17 2 6 Related Works 2 6 1 The Design of Remote Image Monitoring System Based on DM9000A There are some previous projects done involving the DM9000a Ethernet Controller Chip For example is The Design of Remote Image Monitoring System Based on DM9000A Ping Xue 2011 et al adopts the technology of SOPC hardware and software co design by taking advantage of the high speed parallel computing ability of the hardware circuit and also the flexibility in control of the software The network card controller and the image acquisition controller uses the IP core for the system design The control of the exposure time and the switching of the image acquisition controller are done using the Nios II software core Instead of TCP IP UDP protocol is used in this project to transmit data The system IP core can be designed usig SOPC and realized by using hardware description language HDL The board used in this project is DE2 board with Cyclone II EP2C35 The Terasic TRDB i f H DSM i Figure 2 11 Hardware Principe Diagram Ping Xue 2011 TRDB_D5M digital camera development module is used as the image sensor In the
14. dm9k init pdev ERR OK pdev arp semaphore sys sem new 1 pdev gt tx_semaphore sys sem new pdev dm3k tx space free netif state return ERR IF of dm9k initialization etharp init return ERR OK void alt avalon dm3k rx alt lwip dev paltdev ki alt avalon dm3k if pdev alt avalon dm3k if paltdev netif state save current index register volatile u_char idxold dm9k idxin pdev for dm9k input paltdev gt netif resotre old idx register dm3k idxout pdev idxold 1 power on internal PHY dm3k regout pdev Ox1f Ox00 usleep 5000 2 software reset dm3k regout pdev 0x00 0x03 usleep 5000 3 clear Network Stautus Register NSR by reading out dm3k regin pdev Ox01 4 set MAC address for i 0 i 6 i dm3k regout pdev Ox10 i pdev gt hwaddr i 4 1 set hash table for i 0 i 6 i dm9k regout pdev Ox16 i Oxff 5 clear Interrupt Status Register NSR dm3k regout pdev Oxfe 0x00 err t dm9k link output struct netif netif struct pbuf p alt_avalon_dm9k_if pdev alt_avalon_dm9k_if netif gt state wait tx resource availability sys sem wait pdev gt tx_semaphore fill packet to MAC dm3k memoutw pdev u short p payload p tot len specify the length dm3k regout pdev Oxfc u_char p tot len amp Oxff dm3k regout pdev Oxfd u_char p tot len Oxff00 gt g
15. is jitter free It is also an ideal real time processor to be used with the DSP builder based Hardware accelerator to provide real time high performance results It is also supported by industry leading Real Time Operating Systems RTOS One of its features is also custom instructions which means the ability to use FPGA for function acceleration Nios II f fast The Nios II fast processor core can use a memory management unit MMU to run embedded Linux with just a simple configuration option Both the open source and also the commercially supported versions of Linux for Nios II processors are available The Avalon switch fabric is used by the Nios II processor as the interface to its embedded peripherals The Avalon switch fabric uses a slave die arbitration scheme which lets multiple masters operate simultaneously The traditional bus on the other hand only lets one bus master access the bus at a time The development of Nios II can be subdivided into two parts which are hardware generation and software creation The hardware generation part in done using the Quartus II software through SOPC builder The Quartus II will perform the synthesis and place and route operation for the implementation of the entire system inside FPGA For the software creation part the Embedded Design Suite EDS will manage the software development The EDS includes C C compiler debugger and also an instruction set simulator Figure 2 3
16. prominent The network video surveillance system is also becoming more important and having better quality With this trend the network video surveillance is going to replace analogue surveillance industry The advances in this surveillance technology are tightly coupled with the advances in image sensing technologies and in signal processing capabilities On the other hand video surveillance using FPGA can be said as the next generation of video surveillance The field programmable gate array FPGA is actually a semiconductor device that can be programmed after manufacturing Instead of being restricted to any predetermined hardware feature FPGA allows for reconfiguration of hardware even after the products has been installed in the field By using FPGA high performance of video processing can be achieved Moreover the data captured by the FPGA can also be sent through the Ethernet port and viewed by any computer on the same network The low cost FPGAs are now making it possible to implement high performance processing systems on a cost effective and low powered FPGA Furthermore this low cost FPGA enables high performance signal processing It has abundant multipliers large amounts of on chip memory and with fast fabric performance This is what makes the FPGA an ideal platform for the rapidly expanding field of video surveillance system 1 2 Problem Statement Currently CCTV camera is used mostly in video surveillance with the n
17. system Nios II processor controls the CMOS controller to get the video image For the data buffer SDRAM is used and to compress the image JPEG encoder is used UDP protocol is used by the DM9000A to send the image data The hardware circuit for this circuit is constructed in SOPC builder where the Nios II softcore is connected 18 with TIMER SRAM JTAG CMOS controller and DM9000A controller to form a chip programmable system DM9000A SD 15 0 Ethernet controller Avalon Bus AEN H Slave port CMD IOR 10W IRQ DM9000A Figure 2 12 The Connection of DM9000A with Nios II CPU Ping Xue 2011 2 6 2 A Reconfigurable Hardware Networking Platform for Smart Grid The purpose of this project is to achieve high performance and secure network communication system based on the implementation of two type of protocol stack which are the NicheStack TCP IP and also Open TCP IP Hard Core Rami Amiri 2012 For the NicheStack TCP IP in order to achieve a secure communication system the ECC Elliptic Curve Cryptography C code is integrated into the web server source code HTTP client is used to access the web server from the internet The Open TCP IP hard core was designed using VHDL The purpose of this is to enhance the Smart Grid infrastructure The TCP IP core is divided into several distinctive modules Each of the module is represented as a set of Finite State Machine transitio
18. the camera module and also the network module For the camera module the purpose is to store image captured using camera into the DE2 board flash memory In order to use a USB camera the ISP1362 chip need to be utilized and protocols for this communication must be created For the network module the image stored inside the FPGA DE2 board must be able to be accessed when a computer request to view it The scope reflects the aim of this research Therefore one of this project aims is to use TCP UDP protocol to communicate between the FPGA DE2 and computer through a specific IP address set for the FPGA DE2 board Other than that the scope of this project is to use C language and Verilog to code for the interface of DM9000A chip and its protocol programmed through Quartus II and Nios II EDS suite The computer also must be able to access the FPGA DE2 flash memory and view the image stored in from the computer CHAPTER 2 LITERATURE REVIEW 2 1 FPGA Field Programmable Gate Array abbreviated as FPGA is an integrated circuit that is designed in a way that it can be configured by the user after manufacturing FPGA has the capability to perform any logical function The flexibility and reconfigurable ability of FPGA makes it a unique and preferred platform for project development The configurability or the programming of the FPGA is usually done using hardware description language HDL such as VHDL or Verilog An FPGA contains programmable l
19. the flash memory where the server will fetch the file and send it to the client that is requesting the file It also includes socket creation network_utilities c contains MAC address IP address and DHCP routines to manage the addressing These are implementation specific and used by LWIP during initialization dm9000a c defines the communication for DM9000A Ethernet controller chip The Icd c file is a sub function which defines LCD initialization and how to write text string on LCD display LWIP stands for Light Weight Internet Protocol It is a small independent implementation of TCP IP protocol The focus of the LWIP TCP IP implementation is to reduce the RAM usage while still having a full scale TCP There are also other protocol stack which is Interniche stack LWIP is specific for TCP IP protocol only Interniche supports other protocols but it requires more RAM and ROM usage compared to LWIP 4 3 2 1 IP Address and MAC Address Setting The IP Address and MAC address can be set The coding for setting the IP and MAC address is done in network_utilities c There are two possibilities of assigning the IP and MAC address either using the switches or let DHCP assign the IP address lalala EEL PRSSSERRRR HRS EG SSD IM dede ob Figure 4 19 DE2 Switches 43 There are 18 switches in DE2 board SWO until SW17 SW17 used to control how the IP address is set There are 4 segments in an IP address The first two is s
20. 15 Switch Setting There are some components which are not included in the library These components are DM9000A and ISP1362 The DM9000A is an Ethernet controller chip while the ISP1362 is a single chip USB controller The ISP1362 will not be used in this project but it is included in the hardware interconnection for future project improvisations In order to create these components a custom component must be created and the Verilog source file which defines the interconnection of pins the inputs and outputs must be added into the new custom component creation menu After that the signal and interfaces must be set but usually and in this case the settings are done in default 38 Component Editor untitled Fie Templates Introduction HDL Files Signals Interfaces SW Files Component Wizard p About HDL Files File Name Bi DMSOODA y Add Synthesis File Yo MOU Files v Figure 4 16 DM9000A Custom Component Creation 4 3 Software The software has been coded and created which consists of several main parts 4 3 1 Transport Layer Internet Protocol IP A network protocol analysis has being done on a pre made IP core which are provided by TERASIC in order to get more understanding on the protocols involving network connections This analysis is being done using Wireshark which is a network analyser packet sniffer software 39 ky Capturing from Atheros L1C PCI E Ethernet Controller Device NPF_ AC39
21. 2 Weeks Activities Creating image file and store in flash memory Developing protocol for data packets transfer Accessing image file stored in DE2 board flash from pc Testing and trouble shooting Meeting with supervisor Preparation for Seminar FYP 2 Presentation of Seminar FYP 2 Preparation for FYP 2 Report FYP 2 Report Submission APPENDIX C Nios II Coding web_server c include lt stdio h gt include lt errno h gt include lt ctype h gt include includes h include alt_lwip_dev h include lwip sys h include user h include dm9000 h include lcd h ALTERA_AVALON_DM9K_INSTANCE DM9000A dm3k void user_task void pvoid static u_long val 0 simply doing sanity check for val 1 lt lt 17 IOWR LED_RED BASE 0 val usleep 500000 of forever loop ifndef LWIP error is Web Server requires the Lightweight IP Software C onent endif ifndef _ ucosii error Ihis Web Server requires the UCOS II IP Software Component endif ifndef RO ZIPFS error This Web Server reguires the Altera Read only Zip filing system endif A MicroC OS II message box will be used to communicate between telnet and board LED control tasks A OS EVENT attained ip address sem s t
22. 25E7 4CA0 4919 8898 0203307980D6 Wireshark 1 8 5 SVN Rev 47350 from trunk File Edit View Go Capture Analyze Statistics Telephony Tools Internals Help SMASH SBEXSS QeoaFzs ES QQQH FHRBKE Filter Expression Clear Apply Save Protocol Length Info No Time Source Destination Frame 1266 175 bytes on wire 1400 bits 175 bytes captured 1400 bits on interface 0 Ethernet II Src Inventec 19 78 3b 00 26 6c 19 78 3b Dst IPv4mcast 7f ff fa 01 00 5e 7f ff fa Internet Protocol Version 4 Src 169 254 217 51 169 254 217 51 Dst 239 255 255 250 239 255 255 250 User Datagram Protocol Src Port 58050 58050 Dst Port ssdp 1900 Figure 4 17 Wireshark Protocol Analysis After the IP core is being run in Nios II Wireshark was used to capture the interfaces after the connection has been made between the DE2 and computer through Ethernet The above figure shows the protocol involved during the initialization of the protocol SSDP stands for Simple Service Discovery Protocol It is a network protocol based on Internet Protocol Suite that is used for discovery of network services It accomplishes this without the assistance of DHCP and DNS A client which in this case is the computer that wishes to discover available services on a network will use the M SEARCH method DHCP is an acronym for Dynamic Host Configuration Protocol It is a network protocol that is used to configure devices that are connected to the netwo
23. 3 1 Work Flow This project is divided into several steps to accomplish in order to accomplish the objectives of this project The following flowchart shows the step by step approach to reach the objectives which starts from the research of the similar projects the needs of this project and the required tools until the accomplishment of the overall project objectives Research on previous similar projects done on the same platform Altera FPGA DE2 Literature reviews on ieee journals Studying the DE2 board specifications and port connections Understanding the control of Davicom DM9000A Create image file and store inside DE2 flash memory Create a TCP UDP Internet Protocol Module for data trancfer Access image stored in flash memory through network from a computer Test and trouble shooting 23 24 3 2 Project Design 3 2 1 This project design consists of three parts which are hardware design software design and image file creation and storing Hardware Design The hardware design of this project is done using Altera Quartus II Software which incorporates the use of SOPC builder SOPC builder is a software developed by Altera which is integrated in the Quartus II software Using this SOPC components the soft hardware components will be created and interconnected There are library of pre made components The main components that are going to be inserted using this is Nios II processor RAM Flash memory
24. Nios II IDE software The hardware part was only creating the interfaces between the components used The software part involves the protocol creation which is TCP IP and MAC address setting communication for DM9000A and http implementation for requesting file from server to send to client requesting it The image creation part is to create an html file with image embedded in it and store it in flash memory The image file used in this project was created in an html formal and stored in flash memory using the DE2 control panel The hardware creation coding software part and image storing in flash memory was a success but the code cannot be built because of software problem of not having the MicroC OS II component to run this web server type system vi ABSTRAK Perkembangan teknologi di dalam pemprosesan imej dan video telah merevolusikan industri pemantauan video Perubahan daripada pemantauan video analog camera CCTV kepada video jaringan yang menekankan penggunaan Ethernet menjadi semakin penting Camera CCTV memerlukan komputer untuk menyimpan data dan tidak mempunyai penyimpanan data tersendiri dan tidak boleh memproses imej yang berkualiti tinggi Camera IP memerlukan jalurlebar yang besar justeru mengurangkan kebolehan untuk pengaliran videonya Mikropengawal adalah lebih murah daripada FPGA tetapi ia tidak boleh mengalahkan FPGA daripada segi kelajuan proses and prestasi Ia juga tidak fleksibel kerana sebarang perubahan di dalam r
25. Nios II Processor Corporation 2012 In this Remote Video Surveillance Project Nios II processor will be used for the purpose of Ethernet connectivity between FPGA and router The code or TCP IP core protocols will be written in Verilog in Quartus I and in C in the EDS 2 3 TCP IP Protocol TCP stands for Transmission Control Protocol and IP stands for Internet Protocol TCP IP is actually a set of interconnected communication protocols called the TCP IP core protocols The internet protocol or IP is a connectionless and also unreliable protocol which has the task of addressing and packets routing between hosts What does it mean by connectionless is that there are no session established before data exchange It is unreliable because deliveries of packets are not guaranteed due to the probability of being lost delivered out of sequence delayed or duplicated This IP will not make any attempt to recover any of these errors TCP on the other hand is reliable and provides delivery service of data though established connection The data will be transmitted in segments where each segment transmitted is assigned a specific number to achieve reliability An acknowledgement ACK signal must be returned by the receiving hosts for each segment sent within a specific period of bytes received by the host The data will be retransmitted if ACK if nor received when there is no acknowledgement TCP IP actually provides connectivity and also specifies ho
26. OSTimeD1lyHMSM 0 0 0 100 if timeout_dhcp lt DHCP TIMEOUT amp amp have address 0 timeout dhcp if ip addr isany sadapter ip addr have_address 1 VERB Assigned IP Address is d d d d n n ip4 addri sadapter ip addr ip4_addr2 sadapter ip addr ip4 addr3 sadapter ip addr ip4 addr sadapter ip addr VERB Assigned GW Address is td td sa ta n n ip4 addri sadapter gw ip4 addr2 sadapter gw ip4 addr3 sadapter gw ip4 addr sadapter gw ki char buf 32 sprintf buf ta sa ta sa ip4 addri sadapter ip addr ip4 addr2 sadapter ip addr ip4 addr3 sadapter ip addr ip4 addr sadapter ip addr de LCD_Show_Text buf LCD Line2 sprintf buf MAC 009000AE00 2x adapter gt hwaddr 5 de LCD Show Text buf if timeout_dhcp DHCP_TIMEOUT dhcp_stop adapter IP4 ADDR amp ipaddr IPADDRO IPADDR1 IPADDR2 IPADDR3 IP4 ADDR 6gw GWADDRO GWADDR1 GWADDR2 GWADDR3 IP4 ADDR amp netmask MSKADDRO MSKADDR1 MSKADDR2 MSKADDR3 netif_set_addr adapter amp ipaddr netmask gw netif_set_up adapter have_address 1 if have address 1 OSSemPost attained ip address sem OSTaskDel OS PRIO SELF endif LWIP_DHCP http c include lt stdio h gt include lt stdlib h gt include lt string h gt include lt ctype h gt include lt sys param h gt include sys fcnti h include lwip netif n
27. UNIVERSITI TEKNOLOGI MALAYSIA DO Pe Yo DECLARATION OF THESIS UNDERGRADUATE PROJECT PAPER AND COPYRIGHT Author s full name MOHAMAD AMIN BIN NOORDIN Date of birth n 19 FEBRUARY 1989 Title REMOTE VIDEO SURVEILLANCE USING FPGA Academic Session 2012 2013 declare that this thesis is classified as CONFIDENTIAL Contains confidential information under the Official Secret Act 1972 RESTRICTED Contains restricted information as specified by the organization where research was done OPEN ACCESS lagree that my thesis to be published as online open access full text acknowledged that Universiti Teknologi Malaysia reserves the right as follows The thesis is the property of Universiti Teknologi Malaysia The Library of Universiti Teknologi Malaysia has the right to make copies for the purpose of research only The Library has the right to make copies of the thesis for academic exchange Certified by SIGNATURE SIGNATURE OF SUPERVISOR 890214 07 5567 ASSOC PROF DR MUHAMMAD NASIR BIN IBRAHIM NEW IC NO PASSPORT NO NAME OF SUPERVISOR Date NOTES If the thesis is CONFIDENTAL or RESTRICTED please attach with the letter from the organization with period and reasons for confidentiality or restriction T hereby declare that I have read this thesis and in my opinion this thesis is sufficient in terms of scope and quality for the award of the degree of Bachelor of Electronics Engineering
28. cpip init done This function is called once the LWIP stack is alive as specified in our lwip stack init call in main below We tell it about each of our network devices and start the application amp timer threads as appropriate e tatic void tcpip init done void arg ALTERA AVALON DM3K INIT dm9k At this point LWIP has been initialized but the Ethernet interface has not the initialise_lwip_devices call does so adding in MicroC OS II threads for low level Ethernet MAC interface and TCP protocol timer ef if lwip devices init ETHER PRIO die with error tcpip init done Fatal Can t add ethernet interface attained ip address sem OSSemCreate 21 53 if LWIP_DHCP 1 if TORD SWITCH PIO BASE 0 amp 1 17 sys thread new dhcp timeout task endif LWIP DHCP a Add any application task s that rely on LWIP http task Creates HITP listening sockets manages incoming W connection requests and handles all web server duties WA if sys thread new http task NULL HTTP PRIO die with error tcpip init done Fatal Can t add HTTP task int main LCD Init printf Nn nWeb Server starting up n n Our very first call in an LWIP example design is to start up the LWIP stack We specify a MicroC OS II thread priority for the tcp ip thread as well as a call back routine tcpip init done which is called once
29. ction http conn conn int http_instance alt_u32 current_time 0 if conn gt state READY conn gt state PROCESS conn gt state DATA current time alt nticks if current time conn gt activity_time gt HTTP KEEP ALIVE TIME conn gt state RESET if conn gt state COMPLETE if conn gt file_handle NULL hyclose conn file handle conn keep alive count conn data sent 0 if conn keep alive count 0 conn gt close 1 conn gt state conn gt close CLOSE READY if conn gt state RESET if conn gt file_handle NULL hyclose conn file handle memset conn gt rx_buffer 0 HTTP RX BUF SIZE conn state CLOSE Close the TCP connection if conn gt state CLOSE close conn fd http reset connection conn http instance int http handle accept int listen socket http_conn conn int ret_code 0 i socket len struct sockaddr_in rem len sizeof rem for i 0 i HTTP NUM CONNECTIONS i if conn i gt fd 1 if i HTTP NUM CONNECTIONS return 1 if socket accept listen socket struct sockaddr srem slen lt 0 fprintf stderr http handle accept accept failed d n socket return socket conn i gt fd socket conn i activity time alt_nticks return ret_code 60 int http_read_line http_conn conn alt_u 1f
30. ction oriented category This layer deals with the connections opening and maintaining between internet hosts 4 Application Layer This is the highest layer where applications creates user data in order to communicate this data to other processes or applications on the same or another host This is the layer where the protocols such as SMTP FTP HTTP operates The application layer actually uses the lower layers to provide a stable network connection across which to communicate 11 2 4 Ethernet Ethernet is basically a technology for local area networking LAN It is used to connect devices in close area For example connecting all computers in a building would require an Ethernet port in all the computers For human to communicate with each other we need a language The same concept applies to computers that want to communicate with each other through Ethernet port This is where TCP IP protocol comes in as a medium of communication or the language Ethernet was developed in 1970 s by Xerox before becoming popular when Digital Equipment Corporation and Figure 2 4 Cat5 Cable with RJ45 Connector Staff 2012 Intel joining Xerox in developing the Ethernet standard In 1985 it was officially accepted as IEE standard 802 3 Ethernet uses CSMA D during packets transmitting CSMA D stands for Carrier Sense Multiple Access with Collision Detection and it is an algorithm for packets transmission and receiving over a common network
31. ddress specified on the LCD display of FPGA DE2 Image will be displayed on the browser Figure 3 2 Operation Flow CHAPTER 4 RESULTS AND DISCUSSIONS 4 1 Image File The image file is created in the format so that a computer client can access the image stored inside FPGA DE2 flash memory The image file is stored in a zip format 4 1 1 Image File Creation The image file created and stored in a zip format B ro_zipfs zip The contents of this zip file are dJi images index html not_found html 30 The folder images contain the image to be viewed The index html and not found html contents are as follows Remote Video Surveillanc x amp CM file G Users AMIN AppData Local Temp Rar EXa0 034 index html Ha FM Football Manager 20 Facebook chat code Anno 2070 RELOAD eus CMD Design Automatic Pill Dispe MI Automatic Monthly fB Reduce Medication Simple Socket Serve Figure 4 1 index html The index html file contains the image to be viewed when the computer access the flash memory to view this image this file will be shown amp gt C file G Users AMIN AppData Local Temp Rar EXa0 273 not found htmi Ww FM Football Manager 20 W Facebook chat code B Anno 2070 RELOAD EZ Zeus CMD Design FS Automatic Pill Dispe J Automatic Monthly EH Reduce Medication Simple Socket Serve File not found Sorry The page you req
32. dress Resolution Protocol a 12 0 27 504 0 000 12 504 0 000 Help Close Figure 4 18 Wireshark Protocol Hierarchy Statistics The figure above shows the protocol hierarchy analysis using Wireshark This IP core uses UDP protocol under the UDP protocol layer there are a lot of protocols involved which are Hypertext Transfer Protocol HTTP Bootstrap protocol NetBIOS Datagram Service Server Message Block SMB protocol and SMB MailSlot Protocol Microsoft Windows Browser Protocol NetBIOS Name Service Domain Name Service DNS and Internet Group Management Protocol IGMP Each protocol has its own function HTTP is an application layer network protocol HTTP functions as a request response protocol in the client server computing model A web browser for example may be the client and an application running on a computer hosting a web site may be the server The client submits an HTTP request message to the server The server which provides resources such as HTML files and other content or performs other functions on behalf of the client returns a response message to the client In computer networking the Bootstrap Protocol or BOOTP is a network protocol used by a network client to obtain an IP address from a configuration server In NetBIOS Datagram Service the application is responsible for error detection and 41 recovery NetBIOS Name Service is a service providing name lookup and registration It serves the same purpose a
33. ekaan akan menyebabkan fabrikasi semula PCB kerana ia adalah rekaan berwayar Ia juga 50 ke 100 kali ganda lebih perlahan daripada FPGA dari segi prestasi watt Untuk menyelesaikannya satu jaringan pemantauan video telah direka dengan menggunakan FPGA DE2 Rekaan dibahagikan kepada dua iaitu bahagian perkakasan perisian dan penciptaan dan penyimpanan imej Bahagian perkakasan direka dengan menggunakan SOPC Builder dan bahagian perisian direka dengan menggunakan Nios II IDE Bahagian perkakasan hanya mereka bentuk pengantaramuka diantara komponen yang digunakan Bahagian perisian computer melibatkan reka bentuk protocol iaitu TCP penetapan alamat IP dan MAC kominikasai untuk DM9000A dan pelaksanaan http Fail dicipta dalam bentuk hmtl dan imej disimpan dalamnya sebelum menyimpannya di dalam memori flash Fail imej yang digunakan dalam projek ini direka dalam bentuk html dan disimpan di dalam memori flash dengan menggunakan panel kawalan DE2 Reka bentuk perkakasan elektronik kod dan penyimpanan imej ke dalam memori flash telah Berjaya dilaksanakan tetapi kod tersebut tidak dapat di bina kerana terdapat masalah dengan perisian komputer di mana ia tidak mempunyai komponen MicroC OC II untuk menjalankan system server web ini vii TABLE OF CONTENTS CHAPTER TITLE PAGE DECLARATION ACKNOWLEDGEMENT ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS CHAPTER 1 INTRODUCTION 1 1 Background of study 1 1 2 Pr
34. et to default value and the 3 and 4 segment is set based on switch If the SW17 is 1 the IP address are as follows 192 168 SW 15 12 SW 11 8 128 If SW17 is 0 it will get the IP address from DHCP server There are 5 segments for MAC address setting where the first 4 segments are set to default value The 5 segment value are set based on switches The MAC address setting is as follows 00 09 00 AE SW 7 0 4 4 Expected Result The expected result of this project is a creation of a web server where the FPGA DE2 is the server and the computer is the client The client will open a browser and type the IP address displayed on LCD to request access to the image from the server Figure 4 20 LCD Display of MAC and IP Address 44 The server will process the request and fetch the image file from the flash memory for the client to view D Remote Video Surveillanc x amp gt C D htto 192 168 1 131 Ri Index of downloads Facebook chat code ild DS1302 16F628 Woes PJ DS1302 Demo Code W Servo control Wiki 9 www microdigitaled MJ uC OS Il Overview mikroElektronika V 9 58 PM 20 5 2013 a PEN Figure 4 21 Image Display on Browser This will be the result when the image access is a success 4 5 Problem and Troubleshooting The result cannot be displayed as the project stumbled on an error during the building of project in Nios II IDE The erro
35. etwork video surveillance slowly growing in importance For the CCTV camera it has a sensor which captures images The resolution of the camera is limited to 720x575 pixels For the CCTV camera data cannot be directly accessed or taken from the camera It needs a computer medium for storage of data FPGA on the other hand can act as a stand alone network video surveillance system IP cameras which are now gaining in attention from people are a type of networked video surveillance It requires more bandwidth than analog CCTV cameras so this may limit its capability for streaming or recording FPGA on the other hand has greater bandwidth capability and will not have any limitations due to bandwidth Moreover many IP cameras are underpowered For example in dark conditions the image processor spends more time trying to compensate for low light images and cannot output the same higher frame rate from normal lighting condition FPGA enables high performance signal or video processing due to the availability of abundant multipliers and large amount of on chip memory Some people may question the use of FPGA instead of microcontroller in video surveillance Microcontroller is cheaper than FPGA but it cannot beat FPGA in terms of processing speed and performance FPGA has a lot of advantages over microcontroller One of its biggest advantage is flexibility and reconfigurable FPGA can always be reprogrammed by simply changing the Verilog code and reprogram t
36. for Smart Grid 1 4 Semiconductor P 2002 Philips ISP1362 Koninklijke Philips Electronics 50 Staff T S G 2012 EC unveils plan to allow wireless technologies including broadband to share radio spectrum Business Economy EU News from http sofiaglobe com 2012 09 03 ec unveils plan to allow wireless technologies including broadband share radio spectrum Wikipedia Internet protocol suite from http en wikipedia org wiki Internet_protocol_suite Corporation A 2011 Using the NicheStack TCP IP Stack Nios II Edition 1 36 Pidgeon N How Ethernet Works from http computer howstuffworks com ethernet4 htm Technologies T NIOS II Web Server Demo 1 6 Microsoft TCP IP Core Protocols from http technet microsoft com en us library cc958827 aspx Nios IL from http en wikipedia org wiki Nios II APPENDIX A FYP 1 Gantt Chart Weeks Activities FYP Briefing Methodology Briefing FYP Title searching Searching materials related to FYP and literature review Write project proposal and submit Progress report FYP 1 2 Progress report FYP 1 3 Preparation for Seminar FYP 1 Presentation of Seminar FYP 1 Preparation for FYP 1 Report FYP 1 Report Submission APPENDIX B FYP 2 Gantt Chart 5
37. ful information throughout this project Nevertheless my appreciation also goes to Mr Jeevan Srikunan who willing to spend some of his time to help me with his technical skills and knowledge ABSTRACT Technological innovations in imaging and video processing have revolutionized the video surveillance industry The transition from analogue CCTV camera surveillance to network video surveillance which emphasizes the use of Ethernet is becoming more and more prominent The network video surveillance system is also becoming more important Currently CCTV camera is used mostly in video surveillance with the network video surveillance slowly growing in importance CCTV cameras need pc s to store data and it doesn t have its own storage and unable to process high image quality IP camera requires a lot bandwidth so it limits its capability to stream Microcontroller is cheaper than FPGA but it cannot beat FPGA in terms of processing speed and performance It is also not flexible because any changes in the design will result in fabrication of new PCB since it is hard wired It is also 50 to 100 times slower in performance watt compared to FPGA To solve this problem a network video surveillance using FPGA DE has been developed The main design was created in terms of block design before divided into hardware software part and image creation and storing part The hardware part was created using SOPC builder and the software part was created using
38. h the USB connectors many devices can be connected to the computer such as mouse keyboard printers and even handphones In 1996 USB 1 0 was introduced which has data transfer rates of 1 5Mbits s at Low Speed and 12Mbits s at Full Speed USB 1 1 was released in 1998 and this was the connector that was widely used in that time In April 2000 USB 2 0 was released It has a higher data transfer rate with 480Mbits s which is 40 times 14 better than that of USB 1 1 USB 2 0 is backward compatible with its predecessor USB 1 1 Even though USB 1 1 is the older version it is forward compatible with USB 2 0 In 2008 USB 3 0 was introduced It has a data transfer rate of 5 Gbit s and it is backward compatible with USB 2 0 Compared to USB 2 0 the USB 3 0 has an increased bandwidth where it uses two unidirectional data paths for data transmitting and data receiving instead of a one way communications There are two USB standard connectors which are A and B A connectors connects towards computers head upstream while B connectors connect to individual devices head downstream Figure 2 7 Type A Figure 2 8 Type B Brain The USB process is basically starts when the power up of the host occurs The host will query all the devices connected to the bus and will assign an address to each one This process is called enumeration With the connection established the host will find what kind of data transfers to perform which are 1
39. he board The hard wired printed circuit board PCB is very hard to reconfigure once the PCB already done Any changes in the design will result in the fabrication of a new PCB Furthermore microcontroller will not have enough processing power in video processing and telecommunications applications especially the data path Microcontroller is also not good in image processing where it will process image at a very slow time and at very low quality In those sorts of applications a direct hard wired logic is needed to process the packet FPGA has larger memory on chip than microcontroller which means a greater bandwidth FPGA also has a built in Ethernet module for network ip communication Moreover FPGA has a faster processing speed compare to any microcontroller and it also enables image compression and storage FPGA can provide approximately 50 to 100 times the performance watt of power consumed than that of a microprocessor This makes it a better choice in terms of power compared to microprocessors 1 3 Objective This project has three main objectives First is to create an image file and convert it in format so that it can be stored into the FPGA DE2 flash memory The next objective is to create an Internet Protocol IP module for data and packets sending The final objective is to view the image stored inside DE2 flash memory from a computer through the network 1 4 Scope A complete remote video surveillance system requires both
40. he project requirement The cpu setting is as follows components are pre made components which are taken from the library Even though the components are pre made there are settings need to be done to match 34 IM Altera Nios I cpu 0 3 j Caches amp Tightly Coupled Memories Advanced Features JTAG Debug Module Custom Instructions ONios IIe ONios II s jo Nios II f RISC RISC RISC Nios II 52w 52 bit 32 bit Selector Guide Instruction Cache Instruction Cache Fa C ne II Branch Prediction Branch Prediction re Hardware Multiply Hardware Multiply F system 100 MHz Hardware Divide Hardware Divide Barrel Shifter Data Cache Dynamic Branch Prediction Performance at 100 MHz Up to 9 DMIPS Up to 50 DMIPS Up to 101 DMIPS Logic Usage 600 700 LEs 1200 1400 LEs 1400 1800 LEs Memory Usage Two M4KS Two M4Ks cache Three M4KS cache Select a Nios li core Hardware Multiply Embedded Multipliers C Hardware Divide Figure 4 7 Nios II Processor Type Nios II f is selected where the f stands for fast The other two types are Nios II e for economic and Nios II s for standard IM Altera Nios Il cpu_O Instruction Bus Data Bus Instruction Cache 4 Kbytes Mi Data Cache 2 Kbytes v Data Cache Line Size 4Bytes w C Include tightly coupled instruction master port s C Include tightly coupled data master port s Figure 4 8 Nios II Processor Instruction and Data Bus Setting This window of setting shows the
41. include lwip sockets h include arch sys_arch h include sys alt alarm n include alt types h include http h include user h if 0 struct sFILE unsigned char _p current position in some buffer int r read space left for getc int w write space left for putc short flags flags below this FILE is free if 0 short file fileno if Unix descriptor else 1 struct sbuf bf the buffer at least 1 byte if NULL int lbfsize 0 or bf size for inline putc operations _PTR _cookie cookie passed to io functions _READ WRITE RETURN TYPE EXFUN read PIR cookie char buf int _n _READ WRITE RETURN TYPE EXFUN write PTR cookie const char buf int n _fpos_t _EXFUN _seek _PTR cookie fpos t offset int whence int EXFUN close PTR cookie separate buffer for long sequences of ungetc struct sbuf ub ungetc buffer unsigned char up saved p when p is doing ungetc data int _ur saved r when r is counting ungetc data tricks to meet minimum requirements even when malloc fails unsigned char ubuf 3 guarantee an ungetc buffer unsigned char nbuf 1 guarantee a getc buffer separate buffer for fgetline when line crosses buffer boundary struct sbuf lb buffer for fgetline Unix stdio files get aligned to block boundaries on hyseek int blksize stat st_blk
42. instruction cache for instruction bus and data cache for data bus t Altera Nios Il cpu 0 Nios II Core Caches amp Tightly Coupled Memories Advanced Featur Select a debugging levet O No Debugger fDtevel1 T QLevel2 Otevel 3 Olevel4 JTAG Target Connection JTAG Target Connection JTAG Target Connection JTAG Target Connection Download Software Download Software Download Software Download Software Software Breakpoints Software Breakpoints Software Breakpoints Software Breakpoints 2 Hardware Breakpoints 2 Hardware Breakpoints 4 Hardware Breakpoints 2 Data Triggers 2 Data Triggers 4 Data Triggers Instruction Trace Instruction Trace Data Trace On Chip Trace On Chip Trace Off Chip Trace No LEs 300 400 LES 800 900 LEs 2400 2700 LES 3100 3700 LEs No M4Ks Two M4Ks Two M4Ks Four M4Ks Four M4Ks Advanced debug licenses can be purchased from F52 hittp Awww fs2 corn Figure 4 9 Nios II JTAG Setting This is set as default Address Width 22 bits Data Width 8 vY bits Board Info Create an interface to any industry standard CFI Common Flash Interface compliant flash memory device Select from a list ot tested flash memories or provide interface amp timing information for a CFI memory which does not appear on the list JT Flash memory capacity 4 MBytes 4194304 bytes Figure 4 10 Flash Memory Data and Address Width The flash memory address width and data width settings are as foll
43. itches 4 Debounced Pushbutton Switches 50 MHz Oscillator 8 MB SDRAM 512 KBSRAM 4 MB Flash Memory Figure 2 1 The DE2 board Corporation 2006 50 Mhz 27Mhz Extin USB 2 0 Host Device 16 bit Audio CODEC 10 100 Ethernet P hy MAC VGA 10 bit Video DAC TV Decoder Cyclone II FPGA 2C35 IrDA Transceiver User Green LEDs 8 User Red LEDs 18 SDRAM 8 Mbytes 16x 2 LCD Module SRAM 512 Kbytes PS2 amp RS 232 Ports 7 Segment Display 8 Toggle Switches 18 Expansion Headers 2 Pushbutton Switches 4 EPCS16 Config Device USB Blaster Figure 2 2 Block Diagram of DE2 Board Corporation 2006 2 2 Nios II Processor According to Gartner Research Corporation 2012 Altera Nios II processor is said to be the world most versatile processor and the most widely used softcore processor in the history of FPGA It is a 32 bit embedded processor architecture which is specifically designed for the Altera FPGA family It is really flexible and ASIC optimized The soft core nature of the Nios II enables the users designers to use and generate their own custom Nios II core based on their specifications There are 3 different categories of Nios II processors which uses Harvard architecture 1 Nios II e economy It has low number of logic elements which is 600 It is an ideal processor for microcontroller applications Nios II s standard The unique feature about this processor is its real time performance
44. lon dm9k if pdev return u long IORD pdev gt base_addr pdev gt data_offset inline u_char dm9k regin alt_avalon_dm9k_if pdev u_char regidx dm3k idxout pdev regidx return dm3k datin pdev inline void dm3k regout alt avalon dm3k if pdev u_char regidx u_char val ki dm3k idxout pdev regidx dm3k datout pdev val inline void dm9k_meminw alt_avalon_dm9k if pdev u_short pbuffer int len dm9k_idxout pdev Oxf2 for len len 1 2 len pbuffer dm9k_datinw pdev 64 int dm9k identify alt avalon dm3k if pdev ki vid 29 28 0A 46 if dm9k regin pdev 0x28 0x46 dm9k_regin pdev 0x29 0x0a return 1 pid 2B 2A 90 00 if dm3k regin pdev Ox2A 0x00 dm3k regin pdev 0x2B 0x90 return 1 return 0 err t alt avalon dm3k init struct netif netif int i alt_avalon_dm9k_if pdev alt avalon dm3k if netif state pdev lwip dev list dev netif netif check private data s availability if pdev return ERR IF identify our device if dm3k identify pdev 1 return ERR IF specify callback routines netif name 0 d netif name 1 m netif gt output dm3k output netif linkoutput dm9k link output set physical address 4I pdev gt hwaddr 5 IORD SWITCH PIO BASE 0 amp OxFF for i 0 i lt netif hwaddr len 6 i netif gt hwaddr i pdev gt hwaddr i dm9k initialization if
45. missing component the build of the project does not show any error on the code So the coding was a success and the project aim of creating a web server type system is a success In this project the computer should be able to access the image stored inside the FPGA DE2 flash memory by requesting through a browser using a specific IP address The server responds and process the request to complete the overall flow of the project 48 5 2 Recommendations This project is Remote Video Surveillance using FPGA The scope of this project was limited to the creation of the protocol and method of communications between FPGA and computer so that the computer can access the image The scope also involves the storing of image file into the flash memory This project can be further improvised by adding the camera module Creating the camera module was not included in the scope of this project as the creation need to include the utilization of Phillips ISP1362 USB controller chip inside FPGA DE2 A protocol for USB communication using this chip must be created and it will take a long time to develop Creating this protocol for USB communications and storing the image taken into the flash memory will create a complete standalone video surveillance system However in order to create a real and more powerful video surveillance system live video feed can be used to replace the image This kind of design implementation should allow any user connected to the net
46. n control protocol and UDP stands for user datagram protocol TCP is a connection based protocol which means it is reliable and ordered When a message data packet is sent if there are no connection fails it will get delivered If loss of connection happens the lost 26 part will be requested by the server So there can be no corruption while message transferring occurs Unlike TCP UDP protocol is connectionless Whenever a message is sent there will be no guarantee that the message is received by the receiver The sent message could also been corrupted during sending So this UDP is unreliable Furthermore TCP is ordered The data sent and the received data are in the same order For UDP the received data may not be the same order as the sent data Moreover TCP is less susceptible to attack When packets data sent from sender to receiver there will be acknowledgment sent from the sender to receiver and also acknowledgement from receiver to sender to confirm data has arrived So it is hard for attackers hackers to modify or delete any data For UDP there is no acknowledgement from both side of sender and receiver which means it has no built in mechanism to guarantee delivery of data and also retransmit of lost data So it is easy for attackers hackers to insert delete or modify the data packets sent Due to important of reliable and secure data in video surveillance TCP protocol has been chosen 27 3 4 Block Diagram of Design
47. ng over TCP IP and one hardware IP core for the purpose of encrypting and decrypting the communication on one hand and for authentication of entities and the data on the other hand There are two standalone options for using TCP IP currently exists in embedded systems which are micro IP uIP and light weight IP LWIP It requires a lot of work to port uIP to MicroBlaze even though it is the smallest one LWIP already exist for Xilinx FPGA but the size is large The C implementations of the TCP IP protocol are as follows 1 A synchronization package is sent by the client to the server SYN 2 The server accepts the SYN signal and replies with an acknowledge SYN ACK 3 Data transfer are initiated after the client acknowledges it too with ACK 4 A push command is sent PSH after the last transmitted byte With this the sender accentuates that all bytes are sent and the receiver can subsequently empty its receiver buffer PSH The communication will be terminated mainly due to the triggering by FIN and acknowledged by reply FIN ACK 21 Embedded Syo End User Figure 2 14 Entity Communication Channels An Braeken 2011 CHAPTER 3 RESEARCH METHODOLOGY The contents covered in this chapter discuss the technique approach and the method used to fulfil the projects objectives and also discusses the flow of the project A systematic and well planned approach is necessary in order to complete this project
48. ns The modules that define the TCP IP hard core are UDP TCP IP ICMP and ARP For the TCP module its purpose is to communicate with the application layer The TCP module interprets applications instructions and controls other modules Buffers and tables such as socket table are defined by the TCP module to store information 19 about TCP connections The main components of the TCP are the Send and Receive module a g Smart meter a g Corporate gateway Smart meter rc Network Management 2 operator s Data Concentrator g Smart meter a Z el Figure 2 13 Proposed FPGA Based Data Communication for Smart Grid Rami Amiri 2012 The NicheStack TCP IP was written in C and the Open TCP IP hard core was written in VHDL The two modules were compared in terms of speed FPGA utilization and SDRAM code size The results are as follow Table 2 1 C Code vs VHDL Implementation Implementation FPGA Utilization SDRAM code Speed Latency size C Code 16 822KB SOMHz VHDL 1290 N A 1000MHz 20 2 6 3 Secure Remote Reconfiguration of an FPGA based Embedded System This project An Braeken 2011 is about the implementation of the protocol architecture and implementation details of an FPGA based embedded that is able to remotely and securely reconfigure FPGA by using TCP IP protocol There are mainly two blocks at the embedded system ES side which are one communication component for communicati
49. oblem Statement 2 1 3 Objective 3 1 4 Scope 3 CHAPTER 2 LITERATURE REVIEW 2 1 FPGA 5 2 2 Nios II Processor 7 2 3 TCP IP Protocol 9 2 4 Ethernet 11 2 5 Universal Serial Bus USB 13 2 6 Related Works 17 CHAPTER 3 CHAPTER 4 2 6 1 The Design of Remote Image Monitoring System Based on DM9000A 2 6 2 A Reconfigurable Hardware Networking Platform for Smart Grid 2 6 3 Secure Remote Reconfiguration of an FPGA based Embedded System RESEARCH METHODOLOGY 3 1 3 2 3 3 3 4 3 5 Work Flow Project Design 3 2 1 Hardware Design 3 2 2 Software Design 3 2 3 Image File Creation and Storing TCP vs UDP Block Diagram of Design Operation Flow RESULTS AND DISCUSSIONS 4 1 4 2 4 3 4 4 4 5 Image File 4 1 1 Image File Creation 4 1 2 Image File Storing Hardware Software 4 3 1 The Transport Layer Internet Protocol IP 4 3 2 The Nios II Coding 4 3 2 1 IP Address and MAC Address Setting Expected Result Problem and Troubleshooting 18 20 22 23 23 24 24 24 26 27 29 29 31 33 38 38 41 42 43 44 viii CHAPTER 5 REFERENCES APPENDIX A APPENDIX B AAPENDIX C CONCLUSIONS AND RECOMMENDATIONS 5 1 Conclusions 5 2 Recommendations 47 48 49 51 52 53 LIST OF TABLES TABLE NO TITLE PAGE 2 1 C Code vs VHDL Implementation 19 4 1 TCP vs UDP 41 FIGURE NO 2 1 2 2 25 2 4 2 5 2 6 27 2 8 2 9 2 10 2 11 2 12 2 13 2 14 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4
50. ogic components which are called logic elements LEs and a hierarchy of interconnects which are reconfigurable that allow the LEs to be connected physically The FPGA can be reconfigured to perform complex combinational logic functions flip flops and complete memory blocks or just simple AND and OR logics There are several companies producing their own FPGAs The top two companies are Altera and Xilinx FPGA not only allow for digital programming but it also has many features which allows user to implement a wide range of design Take Altera FPGA DE2 as an example The DE2 also has a lot of ports such as VGA Ethernet RS 232 USB 2 0 PS 2 two GPIO ports and also IrDA transceiver This is what makes FPGA to be implemented on a wide range of design scope USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGAVideo 10 100M Port Port Pot in in Out In Port RS 232 Port 9V DC Power amt tf tt 27 MHz Oscillator P 24 bit Audio Codec van gt PS 2 Keyboard Mouse Port VGA 10 bit DAC k N Ethernet 10 100M Controller wii Expansion Header 2 JP2 Power ON OFF Switch USB Host Slave Controller TV Decoder NTSC PAL Altera USB Blaster Controller Chipset Altera EPCS16 Configuration Device i ka Expansion Header 1 JP1 Altera Cyclone Il FPGA RUN PROG Switch for JTAG AS Modes 16x2 LCD Module SD Card Slot 7 Segment Displays 8 Green LEDs 18 Red LEDs NE IrDA Transceiver SMA External Clock 18 Toggle Sw
51. ows 36 Attributes Setup 40 Wait 160 Hold 40 Units ns System Clock 100 MHz Timing granularity is System Clock cycles Read Waveforms data aar XX select readn 40ns 170ns Write Waveforms data addr XK select writen 40ns l 170ns 40ns L4 Flash memory capacity 4 MBytes 4194304 bytes a Cope Da Figure 4 11 Flash Memory Timing The timing settings which includes setup time wait time and hold time are as shown above Other settings of LEDs buttons and switches are as follows Um Ayalon PIO led red UT Avalon PIO led green 18 bits 9 bits PIO width must be between 1 and 32 bts PIO width must be between 1 and 32 bits Direction Direction Bidirectional tri state ports Bidirectional tri state ports O Input ports only Input ports only O Both input and output ports Both input and output ports Output ports only Output ports only Figure 4 12 Red LED Setting Figure 4 13 Green LED Setting 37 L Avalon PIO button_pio KB Avalon PIO switch pio 4 bits 18 bits PIO width must be between 1 and 32 bits PIO width must be between 1 and 32 bits Direction Direction Bidrectional tri state ports Bidirectional tri state ports Input ports only Input ports only Both input and output ports Both input and output ports Output ports only Output ports only Cree Cre Figure 4 14 Button Setting Figure 4
52. r is as follows 45 AA A build error occurred Reason Makefile generation failed No component folder found for MicroC OS II oc a Makefile generation failed No component folder found for MicroC OS lI Figure 4 22 MicroC OS II Missing Component Properties for web server 0 syslib 6 5 Info Builders You must specify an RTOS C C Bukd Target Hardware CjC Documentation SOPC Bulder System Cle ina Waaa I I U CiC Fie Types C C Indexer PU l Project References System Ubrary System Library Contents Linker Script RTOS TI stdout stderr kag yan 0 z Program memory text sdram 0 X stdin rega SAN X System dock timer timer _0 z Readjwrite data memory rwdata sdram 0 z Timestamp timer timer 1 vi Heap memory sdram 0 X Max file descriptors 32 Stack memory sdram 0 v I Clean ext flush buffers I Reduced device drivers a r I Small C trary Unk with profiting trary Exception stack memory Ss I ModeiSim only no hardware support Emulate multiply and divide instructions oye Maximum exception stack size bytes Figure 4 23 System Library Properties When the project is built the makefile generation failed as the component required to run the program is missing and unavailable The system library properties also flags the same error stating that the MicroC OS II component is missing and invalid MicroC OS II is an abbreviation of Micro Controller Operating System 46 version
53. ra was contacted several times regarding this issue but no response from the engineers regarding this matter This problem was then being discussed in the Altera Forum There are some suggestions given and tried out which are regenerate the SOPC system file and recompile the project Unfortunately the method did not work out The uCOS II currently provided by Micrium So the uCOS II was searched at the website but there are no uCOS II component or the current board used for the project which are cyclone II type board The available component is for cyclone III board Nevertheless the component was downloaded but the integration failed CHAPTER 5 CONCLUSIONS AND RECOMMENDATIONS 5 1 Conclusions This project purpose of creating the network module for remote video surveillance can be considered a success as all the necessary soft hardware creations image file format creations and software coding creations was completed This project has achieved the objective of creating an image file and embedded it in an html file where the html files and the images are stored in a zip format before successfully being stored in the flash memory The protocol creation the IP core was created and integrated successfully in the code However the objective of viewing the image stored inside the flash memory was unsuccessful due to Nios II software problem of not having the required uCOS II component to run the web server type project Even though there are
54. rk so the devices can communicate with each other using internet protocol IP It involves client and server In this case FPGA is the server and computer is the client 40 Wireshark Protocol Hierarchy Statistics a Display filter none Protocol Packets Packets Bytes Bytes Mbit s End Packets End Bytes End Mbit s E Frame 1257 TT 28157 000 noon 5 Ethernet knn 1157 000 o o ooo E Internet Protocol Version 4 981 151610 0 000 0 0 0000 El User Datagram Protocol 48 TES 149204 0 000 0 0 0000 Hypertext Transfer Protocol NN 28764 SG 65275 0 000 373 65275 0 000 Bootstrap Protocol E ax ER 280 D 0 000 112 38304 0 000 EI NetBIOS Datagram Service 30 44M 506 9318 0 000 0 0 000 EI SMB Server Message Block Protocol 32x mf 506 D 0 0 000 E SMB MailSlot Protocol S oon of 506 9318 0 000 0 0 0000 Microsoft Windows Browser Protocol f3 Waf 5064 918 ooo 4 as 0 000 NetBIOS Name Service MM kn n ss o a oo 308 29344 0 000 Domain Name Service H 7x o o aa 7563 0 000 115 7568 0 000 Internet Group Management Protocol es 83633 0 98 36 1806 0 000 33 1806 0 000 E Internet Protocol Version 6 MM 284 ws 21 a 0 000 0 0 00 E User Datagram Protocol ki 4x ST 447 26645 0 000 0 0 0000 DHCPv6 E vox au 772 14210 0 000 98 14210 0 000 Domain Name Service MM wt Mu 654 on 12435 0 00 145 12435 0 000 Internet Control Message Protocol v6 HO 4ax ssf 24 5050 0 000 55 5050 0 000 Link Layer Discovery Protocol JI a 6 0 19 36 348 0 000 6 348 0 000 Ad
55. s max socket fd listen 1 for i 0 i lt HTTP_NUM_CONNECTIONS i if conn i fd 1 We re interested in reading any of our active sockets FD SET conn i fd readfds fa We re interested in writing to any of our active sockets in the DATA state kid if conn i state DATA FD_SET conn i fd amp writefds if max socket lt conn i fd max socket conn i fd 1 select_timeout tv_sec 0 select_timeout tv_usec 500000 select max socket readfds writefds NULL amp select_timeout if FD_ISSET fd_listen sreadfds http handle accept fd listen conn for i 0 i lt HTTP_NUM_CONNECTIONS i if conn i fd 1 ki if FD ISSET conn i fd readfds http handle receive sconn i i if FD ISSET conn i fd writefds http handle transmit amp conn i i http manage connection conn i i while 1 62 Icd c include lt unistd h gt include lt string h gt include lt io h gt include system h include LCD h lcd write cmd LCD 16207 0 BASE 0x38 usleep 2000 lcd write cmd LCD 16207 0 BASE 0x0C usleep 2000 lcd write cmd LCD 16207 0 BASE 0x01 usleep 2000 lcd write cma LCD 16207 0 BASE 0x06 usleep 2000 lcd write cmd LCD 16207 0 BASE 0x80 usleep 2000 void LCD Show Text char Text int i for i 0 i lt strilen Text itt lcd write data LCD 16207 0
56. s DNS which is to translate human readable names to IP address It is encapsulated by UDP DNS translates domain names to numerical IP addresses needed for the purpose of locating computer services and devices worldwide The Internet Group Management Protocol IGMP is a communications protocol which are used by hosts and adjacent routers on IP networks so that multicast group memberships can be established IGMP is an integral part of IP multicast Table 4 1 TCP vs UDP PROTOCOL TCP UDP Connection oriented reliable and data Connectionless protocol unreliable not lost and data will be loss Ordered Not ordered Less susceptible to hack attack More susceptible to hack attack The table above is the comparison between UDP and TCP protocol Since this project is on video surveillance so TCP will be chosen as it is a safer and more reliable protocol 4 3 2 The Nios II Coding The coding of this project has been divided into 5 main parts which are web_server c http c network_utilities c dm9000a c and Icd c web_server c file contains the main function and the LWIP callback function The LWIP callback installs task once LWIP has been properly initialized http c file is the implementation of an HTTP server which includes all the necessary sockets calls to 42 handle a multiple connections and parsing basic HTTP commands to handle GET and POST requests HTTP GET request the image file stored inside
57. s programmed into the flash memory 4 2 Hardware fs S SESS SSS PS PS CS SSS PSS ES SSS SSCS cS 33 The design of the soft hardware part which is done using SOPC builder is as follows Description INos li Processor Altera Corporation Master port Master port Slave port Avalon Tristate Bridge Flash Memory Common Flash Interface ISORAM Controller EPCS Serial Flash Controter JTAG UART UART RS 232 serial port Interval timer Interval timer Character LCD 16x2 Optrex 16207 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 SEG LUT 8 SRAM 168 5124 DMS0004 15P1362 Binary VGA Controler AUDIO DAC FFO PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 Input Cl 2 8 RIRRRRRRZERZREZ SRLS Figure 4 6 SOPC Hardware Design Base End ROO RAJ 0x00680000 0x006807FF 0x00000 Ox003FFFFF 0x00800000 0x0OFFFFFF 0x00680800 0x00630FFF 0x006810F0 0x006810F7 0x00681000 0x0068101F 0x00681020 0x0068103F 0x00681040 0x0068105F 0x00681060 0x0066106F 0x00681070 0x0068107F 0x00681080 0x0068108F 0x00681090 0x0068109F 0x006810A0 0x006810AF 0x00681100 0x00681103 0x00600000 0x0067FFFF 0x006810F8 0x006810FF l 0x00400000 0x005FFFFF 0x00681104 0x00681107 0x006810C0 0x006810CF 0x00681000 0x0068100F 0x006810E0 0x006810EF A ed The hardware design and interconnections are as follows Most of the t
58. size may be bf size int offset current lseek offset ifndef SINGLE THREAD _flock_t lock for thread safety locking endif do endif define MAX CONCURRENT HYPER 64 define HYPER FID START 0x7000 FILE _gFiles MAX_CONCURRENT_HYPER int ghy initd 0 define HY_CHK_FP fp fp 66 fp file gt HYPER FID START FILE hy allocate fp void ki int i for 1 0 1i MAX CONCURRENT HYPER i 1 if gFiles i flags 0 continue _GFiles i _flags Oxbeef return amp gFiles i of for i return NULL void hy release fp FILE fp fp gt _flags 0 57 FILE hyopen const char pfname const char pmode bypass if ordinary file if strncmp pfname strlen ALTERA_RO_ZIPFS_NAME file 5 return fopen pfname pmode initialization if _ghy_initd int i _ghy initd 1 for i 0 1 lt MAX_CONCURRENT_HYPER i _GFiles i file HYPER FID START i gFiles i flags 0 of for i of not init d FILE fp if fp hy allocate fp return NULL int flen 0 char ptr seek for size if ptr strstr pfiname size flen atoi ptr 5 seek for unit for ptr 5 ptr ptr if ptr lt 0 ptr gt 9 break switch ptr ki case k 1000 flen 1000 break case K 1024 flen 1024 break case m 1 000 000 flen 1000000 break case M 1024 1024 flen 1024 1024 break defa
59. t 8 kick start dm3k regout pdev 0x02 0x01 return ERR OK int dm9k input struct netif netif struct eth_hdr ethhdr struct pbuf p alt avalon dm9k if pdev alt_avalon_dm9k_if netif gt state move received packet into a new pbuf if p dm9k link input pdev return 0 ethhdr struct eth hdr p gt payload switch htons ethhdr gt type IP packet case ETHTYPE_IP w update ARP table A WAIT ARP SEMAPHORE pdev etharp ip input netif p SIGNAL ARP SEMAPHORE pdev skip Ethernet header pbuf header p s1i6 t sizeof struct eth_hdr pass to network layer netif input p netif break case ETHTYPE ARP ja pass p to ARP module ki WAIT ARP SEMAPHORE pdev etharp arp input netif struct eth addr amp netif gt hwaddr p SIGNAL ARP SEMAPHORE pdev break default pbuf free p p NULL break of packet type switch return 1 of alt_avalon_dm9k_rx struct pbuf dm9k link input alt_avalon_dm9k if pdev u_char saveidx struct pbuf p a volatile u short pklen status u short remains Saveidx dm3k idxin pdev check RX availability first dummy read dm3k idxout pdev Oxf0 status dm9k datinw pdev re read again status dm9k datinw pdev if Status amp Oxff 0x01 ki dm3k idxout pdev saveidx return NULL 66 fill packet per chunk for remains pklen
60. the stack is alive and well lwip stack init TCPIP PRIO tcpip init done 9 As with all MicroC OS II designs once the initial thread s and associated RTOS resources are declared we start the RTOS That s it me sys thread new user task NULL SANITY_PRIO OSStart return 0 network utilities c include lt stdio h gt include lt ctype h gt include lt string h gt include alt lwip dev h include alt types h include sys alt flash h include includes h include io h include user h include lcd h ifdef LWIP_DEFAULT_IF undef LWIP_DEFAULT_IF define LWIP DEFAULT IF DM9000A endif ifdef ALT DEBUG define VERB msg printf msg else define VERB msg do while 0 endif The adapter storage here is declared so that when LWIP calls the get ip addr routine the adapter struct will be populated with the NULL DHCP_TMR_PRIO network device Ethernet MAC that LWIP is currently trying to setup an IP address for This is later used in the dhcp timeout task routine to determine if DHCP was successful for the particular adapter struct netif adapter 54 extern OS_EVENT attained ip address sem void die with error char err msg DIE WITH ERROR BUFFER printf nts n err msg OSTaskDel OS PRIO SELF while 1 int get ip addr alt lwip dev lwip dev struct ip addr ipaddr struct ip_addr netmask struct ip addr gw
61. uested cannot be found 8 20PM 1 6 2013 i i ao Figure 4 2 not_found html If the image failed to be accessed this will be displayed 31 4 1 2 Image File Storing After the image file is created it is stored inside the FPGA DE2 flash memory using the DE2 Control Panel DE DE2 Control Panel a Open Help About PS2 amp 7 SEG LED amp LCD TOOLS FLASH SDRAM sram veaa FLASH Random Access Address fo wDATA foo DATA oo Chip Erase 40 Sec Write Read Sequential Write Address fo Length or 4951 M File Length Write a File to FLASH Sequential Read Address o Length n I Entire Flash Load FLASH Contentto a File Figure 4 3 DE2 Control Panel DE DE2 Control Panel lt Open Help About PS2 amp 7 SEG LED amp LCD TOOLS FLASH spram SRAM vs FLASH rRandom Access Address fo wDATA oo DATA foo Processing 7 Yo Sequential Read Address fo Length fo I Entire Flash Figure 4 4 Flash Memory Erasing Before the zip file is stored the contents of the flash must be erased first 32 Open Help About PS2 amp 7 SEG LED amp LCD SDRAM SRAM FLASH Random Access 7 Address fo wDATA oo IDATA oo Processing Sequential Read Address Length p I Entire Flash fo Load FLASH Content to a File Figure 4 5 Write to Flash Memory After the contents has been erased the zip file i
62. ult break of switch fp cookie flen void flen void 10241024 return fp int hygetpos FILE fp fpos t offset if HY_CHK_FP fp return fgetpos fp offset offset int fp gt _offset return 0 int hyseek FILE fp long offset int origin if HY_CHK_FP fp return fseek fp offset origin switch origin case SEEK SET fp gt _offset offset break case SEEK CUR is it right fp gt _offset offset break case SEEK_END fp gt _offset int fp gt _cookie offset break default return 1 of switch origin return 0 int hyclose FILE fp if HY_CHK_FP fp return fclose fp hy release fp fp return 0 int hyread void pbuffer size t size size t count FILE fp if HY CHK FP fp return fread pbuffer size count fp int total remains remains int fp cookie fp offset total remains gt size count size count remains fp gt _offset total return total ifdef DEBUG1 include alt_debug h else define ALT DEBUG ASSERT a endif DEBUG alt u8 http_rx_buffer HTTP_NUM_CONNECTIONS HTTP_RX BUF SIZE alt u8 http tx buffer HITP NUM CONNECTIONS HITP TX BUF SIZE static const alt 8 canned http response HTTP 1 0 404 Not Found r n Content Type text html r n Content Length 272 r n r n lt HTML gt lt HEAD gt lt TITLE gt Nios II Web Server Demonstration lt
63. w data should be addressed formatted transmitted routed and received at the destination There are four abstraction layers each having their own protocols 1 Link Layer It is the lowest layer which is commonly known as Ethernet It contains communication technologies for a local network The function of the link layer is to move packets between the Internet Layer interfaces of two different hosts that are on the same link 10 2 Internet Layer IP It establishes internetworking by connecting local networks It is also responsible in sending packets across multiple networks What it means by internetworking is sending data from a source network to a destination network This is what called as routing The IP performs two basic functions which are host addressing and identification and also packet routing This layer only provides host to host unreliable datagram transmission facility on different IP networks by forwarding the transport layer datagrams to the next router for relaying it further to its destination 3 Transport Layer TCP t establishes and handles host to host connectivity It is responsible for end to end message transfer disregarding the underlying network This message transfer includes error control flow control congestion control application addressing and segmentation This layer can be categorized in two different category which are connection oriented and connectionless The TCP falls into the conne
64. work to access and view the video streamed by the camera To add more security to the system a password can be created when user tries to access using the browser Only if the password is correct then the video stream can be accessed The support provided by Altera was not efficient and fast The response from the Altera and their engineers can be improved as the project can achieve success and further improvisations if the software problem has been solved REFERENCE An Braeken J G Serge Kubera Nele Mentensyz Abdellah Touhafi Ingrid Verbauwhedez Yannick Verbelen Jo Vliegenyz Karel Woutersz 2011 Secure Remote Reconfiguration of an FPGA based Embedded System 1 6 Brain M How USB Ports Work from http computer howstuffworks com usb1 htm Corporation A 2006 DE2 Development and Education Board User Manual 7 Corporation A 2006 DE2 Development and Education Board User Manual 9 Corporation A 2006 DE2 Development and Education Board User Manual 46 Corporation A 2012 Nios II Processor The World s Most Versatile Embedded Processor from http www altera com my devices processor nios2 ni2 index html Inc D S 2006 DM9000A Ethernet Controller with General Processor Interface Ping Xue J H Haichao Wang and Jianwei Ma 2011 The Design of Remote Image Monitoring System Based on DM9000A 885 889 Rami Amiri O E 2012 A Reconfigurable Hardware Networking Platform
65. xiii LIST OF ABBREVIATIONS Field Programmable Gate Array Printed Circuit Board Internet Protocol Transfer Control Protocol User Datagram Protocol Hardware Description Language Logic Element General Input Output Port Real Time Operating System Memory Management Unit Embedded Design Suite Acknowledgement Simple Mail Transfer Protocol File Transfer Protocol Hypertext Transfer Protocol Local Area Network Carrier Sense Multiple Access with Collision Detection Media Access Control Physical Layer of OSI Model Universal Serial Bus On The Go System On Programmable Chip Complementary Metal Oxide Semiconductor Internet Control Message Protocol Address Resolution Protocol ES uIP LWIP SSDP DHCP SMB IGMP DNS BOOTP xiv Embedded System Micro IP Light Weight IP Simple Service Discovery Protocol Dynamic Host Control Protocol Server Message Block Internet Group Management Protocol Domain Name Service Bootstrap Protocol XV LIST OF APPENDICES APPENDIX TITLE PAGE APPENDIX A FYP 1 Gantt Chart 51 APPENDIX B FYP 2 Gantt Chart 52 APPENDIX C Nios II Coding 53 CHAPTER 1 INTRODUCTION 1 1 Background of Study The video surveillance trend is changing Technological innovations in imaging and video processing have revolutionized the video surveillance industry The transition from analogue CCTV camera surveillance to network video surveillance which emphasizes the use of Ethernet is becoming more and more

mohamad amin bin noordin 19 february 1989 remote video

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