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sim system integration module reference manual

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1. Characteristic Symbol Min Max Unit F1 Frequency of Operation 32 768 kHz or 4 194 MHZz crystal 1 Be 2 s ER ECLK Period SS oe 46 18 External Glock input Period 598 ns 2 28 728 38 External Clock Input Time beu 8 ns 45 ClockRise andFalTime 5 XA EA Rss and Fal Time AT Gulls xcept ROUT 48 58 ExemalCockHiseandFalTime 5 ns 87 Cock High to Address FC SIZE RMC Valid f tv 0 29 ns Clock High to Address Data FC SIZE High Impedance O 59 ns 111227 9 OockLowioAS DS CSAssered o ias 2 25 ns Reed 5 Address FC SIZE Vaid tAVSA 15 ns to AS CS Asserted 12 Clock Low to AS DS CS Negated 2 29 ns 13 AS DS CS Negated to tsnal 15 ns Address FC SIZE Invalid Address Hold 14 AS CS Width Asserted tswa 100 ns 14A DS CS Width Asserted Write tswaw 45 ns 14B AS CS Width Asserted Fast Write Cycle tswow 40 ns 155 5 DS CS Width Negated isn 40 ns 16 Clock High to AS DS R W High Impedance 2 59 ns 17 AS DS CS Negated to R W High tsNRN 15 ns 18 Clock High to R W High tcHRH 0 29 ns 20 Clock High
2. Mnemonic Pin State Pin State After RESET Released While Default Function Alternate Function RESET Pin State Pin Function Pin State Pin Function Asserted CS10 ADDR23 1 CS10 1 ADDR23 Unknown CS 9 6 ADDR 22 19 1 CS 9 6 1 ADDR 22 19 Unknown PC 6 3 ADDR 18 0 High Z Output ADDR 18 0 Unknown ADDR 18 0 Unknown AS PE5 See Note 1 AS Output 5 Input AVEC PE2 Inactive Input AVEC Input PE2 Input BERR Inactive Input BERR Input BERR Input CS1 BG 1 CS1 1 BG 1 CS2 BGACK 1 CS2 1 BGACK Input CSO BR 1 cso 1 BR Input CLKOUT Output CLKOUT Output CLKOUT Output CSBOOT 1 CSBOOT 0 CSBOOT 0 DATA 15 0 Mode Select DATA 15 0 Input DATA 15 0 Input DS PE4 See Note 1 DS Output PE4 Input DSACKO PEO Inactive Input DSACKO Input PEO Input DSACK1 PE1 Inactive Input Input PE1 Input CS B 3 FC 2 0 1 CS 5 3 1 FC 2 0 Unknown PC 2 0 HALT Inactive Input HALT Input HALT Input 1 7 1 7 1 Inactive Input IRQ 7 1 Input PF 7 1 Input MODCLK PF0 Mode Select MODCLK Input PF0 Input RW High Z Output R W Output R W Output RESET Asserted RESET Input RESET Input RMC PE3 See Note 1 RMC Output PE3 Input SIZ 1 0 PE 7 6 See Note 1 SIZ 1 0 Unknown PE 7 6 Input TSTME TSC Mode Select TSC Input TSC Input NOTES 1 The state of these bus control port E pins during reset depends on the state of DATAS If DATA8 is high during reset the default these pins are driven high d
3. 47 Input Setup Time tAIST 5 ns BR BGACK DSACK BERR AVEC HALT 47B Input Hold Time 15 ns 4819 DSACK Asserted to BERR HALT Asserted 30 ns 53 Data Out Hold from Clock High tpocH 0 ns 54 Clock High to Data Out High Impedance lcHDH d 28 ns 55 R W Asserted to Data Bus Impedance Change 40 ns 56 RESET Pulse Width Reset Instruction tuRPW 512 57 Negated to HALT Negated Rerun BNHN 0 ns 70 Clock Low to Data Bus Driven Show tscLDD 0 29 ns 71 Data Setup Time to Clock Low Show tscLDS 15 ns 72 Data Hold from Clock Low Show tscLDH 10 ns 73 BKPT Input Setup Time BKST 15 ns 74 BKPT Input Hold Time 10 ns 75 Mode Select Setup Time tss 20 76 Mode Select Hold Time 0 ns 77 RESET Assertion Time RSTA 4 lave 78 RESET Rise Time RSTR 10 live NOTES 1 2 3 6 7 8 9 10 In All AC timing is shown with respect to 20 Vpp and 7096 Vpp levels unless otherwise noted Minimum system clock frequency is four times the crystal frequency subject to specified limits Minimum external clock high and low times are based on a 50 duty cycle The minimum allowable txcyc period will be reduced when the duty cycle of the external clock signal varies The relationship between external clock input du
4. 5 43 5 9 4 aaa 5 45 5 10 Arbitration MES 5 47 5 10 1 Bus ROQUGSE a is ce ed 5 48 5 10 2 Bis Call ma n a une A M A M M A M 5 48 5 10 3 Bus Grant Acknowledge 5 49 5 10 4 Bus Arbitration 5 49 5 10 5 BUS Arbittatiohi COMMON 5 50 5 10 6 Factory Test Slave Mode Arbitration 5 52 5 11 Show Cycle Me 5 52 SECTION 6 INTERRUPTS 6 1 Sources of Interrupt 6 1 6 2 Interrupt Level and Recognition 6 1 6 3 lnterrupt Arbitrator Dm 6 2 6 4 Interrupt Acknowledge Bus Cycles 2222 1 6 3 6 4 1 Bus Cycle Terminated by DSACK Signals 6 5 6 4 2 Bus Cycle Terminated by AVEC Signal 6 6 6 4 3 Spurious Interrupt Cycle r 6 8 SIM MOTOROLA REFERENCE MANUAL TABLE OF CONTENTS Continued Paragraph Title Page 6 5 Interrupt Processing Summary 6 8 SECTION 7 CHIP SELECTS 7 1 Chip Select Options x nat 7 2 7 2 Chip Select Base Addresses 22 2 4
5. 5 51 6 1 Interrupt Acknowledge Read Cycles 6 3 6 2 Interrupt Acknowledge Cycle Flowchart 2 6 4 6 3 Interrupt Acknowledge Cycle Timing seen 6 5 6 4 External Connections for Interrupt Processing 6 6 6 5 Autovector Timing deban Doe Loto aeneus 6 7 7 1 Chip Select Circuit Block Diagram 7 2 7 2 Flow Diagram for Chip Select Sheet 1 of 7 7 7 2 Flow Diagram for Chip Select Sheet 2 of 7 8 7 2 Flow Diagram for Chip Select Sheet 3 of 7 9 7 3 Fast Termination Timing 7 12 7 4 CPU Space Encoding for Interrupt Acknowledge Cycles 7 14 7 5 System Configuration with Chip Selects 7 22 8 1 Reset Block Diagram n 8 2 8 2 Hoser Control 8 5 8 3 Power On Reset Timing io Pec e too Dre re reta 8 7 8 4 Data Bus Signal Conditioning ss uie P Uu 8 10 A 1 CLKOUT Output Timing Diagram
6. gt DATA 15 0 68300 RST MODE SEL TIM Figure A 7 Reset and Mode Select Timing Diagram Table A 9 Key to Figure A 7 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Max Units 75 Mode Select Setup Time tuss 20 76 Mode Select Hold Time 0 ns 77 RESET Assertion Time RSTA 4 78 RESET Rise Time RSTR 10 NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 11 After external RESET negation is detected a short transition period approximately 2 elapses then the SIM drives low for 512 toyc 12 External logic must pull RESET high during this period in order for normal MCU operation to begin MOTOROLA 14 ELECTRICAL CHARACTERISTICS SIM REFERENCE MANUAL 50 51 52 53 54 55 598 5 5 2 68300 BUS ARB TIM Figure A 8 Bus Arbitration Timing Diagram Active Bus Case SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 15 Table A 10 Key to Figure 8 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Max Units 7 Clock High to Address Data FC SIZE RMC High 2 0 59 ns Impedance 16 Clock High to AS DS R W High Impedance tcusz 59 ns 33 Clock Low to BG Asserted Negated tcLBA
7. 7 19 7 10 3 Chip Select Option Registers 2 222222111 7 19 7 10 4 Port C Data Register PORTO 7 21 7 11 Interfacing Example with Chip Selects 7 21 7 11 1 Configuring the RAM Chip Selects 7 22 7 11 1 1 Pin Connections oou vn eiui ae EU EE 7 22 7 11 1 2 Base Address Registers 1 7 22 7 11 1 3 Option RegISt TS ico hie 7 23 7 11 2 Configuring the Boot ROM Chip Select 7 23 7 11 2 1 PUM COMMS CONG TP PE 7 23 7 11 2 2 Base Address Register 222 2 1 7 23 7 11 2 3 Option Registers 7 23 SECTION 8 RESET AND SYSTEM INITIALIZATION 8 1 Reset Operation ENE EKE EADAE EEA 8 1 8 2 Sources of Reset 00 0000 0 tre rise reser s rns risas 8 2 8 2 1 External Reset a tnnt tren sna 8 3 MOTOROLA SIM vi REFERENCE MANUAL TABLE OF CONTENTS Continued Paragraph Title Page 8 2 2 Power On Besel s n EU Unete ER 8 3 8 2 3 Software Watchdog 8 3 8 2 4 Double Bus Fault ibt ete bebes 8 3 8 2 5 Loss of Clock Reset
8. 5 25 Timing of Long Word Read or Write 16 Bit Port 5 26 Long Word Operand to 16 Bit Port Misaligned 5 27 Connecting an 8 Bit Memory Device 5 29 Connecting a 16 Bit Memory Device 5 30 Connecting Two 8 bit Memory Devices 5 31 CPU Space Address Encoding 5 32 CPU32 Breakpoint Operation Flow 5 34 CPU16 Breakpoint Operation Flow 5 35 Breakpoint Acknowledge Cycle Timing Opcode Returned CPUS2 Only 5 36 Breakpoint Acknowledge Cycle Timing Exception Signaled 5 37 LPSTOP Interrupt Mask Level 5 38 Bus Error Without DSACK a ce ALD ue e 5 41 Late Bus Error with DSACK a a 5 42 Retry Sequence PC 5 44 MOTOROLA REFERENCE MANUAL ix LIST OF ILLUSTRATIONS Continued Figure Title Page 5 34 Late Retry Sequence b ERE ins 5 45 5 35 OAL TUERI DO uen cotes uuu Ca SUR 5 46 5 36 Arbitration Flow Chart for Single Request 5 48 5 37 Bus Arbitration State Diagram
9. 16 Bit 8 Bit Alternate Discrete Output or Chip Select Chip Select Function ECLK CSBOOT CSBOOT CSBOOT 50 50 BR CS1 CS1 BG CS2 CS2 BGACK CS3 53 FC0 PC0 CS4 CS4 FC1 PC1 CS5 CS5 FC2 PC2 CS6 CS6 ADDR19 CS7 CS7 ADDR20 PC4 CS8 CS8 ADDR21 PC5 CS9 CS9 ADDR22 PC6 CS10 CS10 ADDR23 ECLK Table 7 4 shows pin assignment field encoding Pins that have no discrete output or ECLK function do not use the 00 encoding Table 7 4 Pin Assignment Field Encoding Bit Field Description 00 Discrete Output or ECLK 01 Alternate Function 10 Chip Select 8 Bit Port 11 Chip Select 16 Bit Port Port size is involved in dynamic bus sizing and determines which DSACK signal the chip select circuit asserts during a bus cycle Refer to 7 6 Chip Selects and Dynamic Bus Sizing for more information A pin programmed as a discrete output drives an external signal to the value specified in the port C data register No discrete output function is available on pins CSBOOT BR BG or BGACK ADDR23 provides ECLK output rather than a discrete output sig nal When a pin is programmed for discrete output or alternate function internal chip select logic still functions and can be used to generate DSACK or AVEC internally on an ad dress and control signal match Refer to 7 8 Using Chip Selects in Interrupt Ac knowledge Cycles for additional information Refer to 7 9 Chip Select Rese
10. RMC PEPA2 PE2 AVEC PEPA1 PE1 DSACK1 PEPA0 PE0 DSACK0 On CPU16 based MCUs when is set the PE3 pin if connected goes to logic level one The CPU16 does not sup port the RMC function for this pin PORTFO PORTF1 Port F Data Register 1HHHI8 SHHHHIA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 7 PF6 4 PF2 PFO RESET U U U U U U U U DDRF Port F Data Direction Register SIHHHHC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDFO RESET 0 0 0 0 0 0 0 0 PFPAR Port F Pin Assignment Register IHHHHE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0 RESET DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 MOTOROLA MEMORY MAP AND REGISTERS SIM B 6 REFERENCE MANUAL Any bit cleared to zero defines the corresponding pin to be an pin Any bit set to one defines the corresponding pin to be an interrupt request signal or MODCLK Table B 3 Port F Pin Assignments PFPAR Field Port F Signal Alternate Signal PFPA7 PF7 IRQ7 IRQ6 PFPA5 PF5 IRQ5 PFPA4 PF4 IRQ4 PFPA3 PF3 IRQ3 PFPA2 PF2 IRQ2 PFPA1 PF1 IRQ1 PFPAO P
11. r 5 5 Read Cycle Flowchart r 5 9 Read Cycle Timing Diagram ab eno 5 10 Write Cycle Flow Chart Mp 5 11 Write Cycle Timing Diagram 5 13 Read Modify Write Timing 004 0 5 14 Operand Byte 5 15 Byte Operand to 8 Bit Port 5 16 Byte Operand to 16 Bit Port Even ADDRO 0 5 17 Byte Operand to 16 Bit Port Odd ADDRO 1 5 17 Word Operand to 8 Bit Port Aligned 5 18 Word Operand to 8 Bit Port Misaligned 5 19 Word Operand to 16 Bit Port Aligned 5 19 Word Operand to 16 Bit Port Misaligned 5 20 Long Word Operand to 8 Bit Port Aligned 5 21 Timing of a Long Word Read of an 8 Bit Port 5 22 Timing of a Long Word Write to an 8 Bit Port 5 23 Long Word Operand to 8 Bit Port Misaligned 5 24 Long Word Operand to 16 Bit Port Aligned
12. When a system asserts DSACK for the required window around the falling edge of state 2 see 5 4 1 Read Cycles and 5 4 2 Write Cycles and obeys the bus protocol by maintaining DSACK until and throughout the clock edge that negates AS no wait states are inserted The bus cycle runs at the maximum speed of three clocks per cy cle 5 3 Dynamic Bus Sizing Dynamic bus sizing allows the MCU to move byte word or long word data to either an 8 bit or 16 bit memory or peripheral system The MCU and target device use the SIZ 1 0 DSACK 1 0 and ADDRO signals to in dicate the operand and port size and operand alignment even or odd address Based on this information the MCU places the data on or reads the data from the appropriate byte or bytes of the data bus 5 3 1 Size Signal Encoding When the MCU starts to perform an access to an external device it uses the SIZ 1 0 pins to inform the external device of the size of the intended data transfer Table 5 1 shows the encodings for the size signals Table 5 1 Size Signal Encoding SIZ1 SIZO Transfer Size 0 1 Byte 1 0 Word 1 1 3 Byte 0 0 Long Word If a transfer operation requires more than one bus cycle the MCU automatically up dates the SIZ 1 0 pins at the start of each cycle to reflect the number of remaining bytes to be transferred For example a word write to an 8 bit port requires two bus cles During the first cycle the MCU drives 1 and 0 on t
13. it tbt A 14 A 10 Key ru u eens A 16 A 11 Key LON IONS eM A 17 A 12 Keyto Figure ione Diatr itte cote A 19 A 13 Keyto Figure A 11 21 Keyto Figure A 12 fU bcp 23 A15 Key to Figure eT datae iare hend qo prc A 25 B 1 SIM Address EM E B 1 B 2 Port EXPIDsASSIODITIGDES 2 chi ay gales ua eot tees B 6 B 3 Port F Pin Assignments cs Lo ee B 7 B 4 CSPARO0 Pin Asslgnmoehls uade ee Eo be rete B 9 B 5 CSPARA Pin Assignments undae reno eet ilte e B 9 B 6 Pin Assignment EFIGOOIDtjs s necis esie o b eet ash eR cni RR RUE B 10 MOTOROLA SIM xii REFERENCE MANUAL SIM PREFACE This manual describes the capabilities operation and functions of the system integra tion module SIM an integral module of Motorola s family of modular microcontrollers Documentation for the Modular Microcontroller Family follows the modular construc tion of the devices in the product line Each device has a comprehensive user s man ual which provides sufficient information for normal operation of the device The user s manual is supplemented by module reference manuals including the SIM reference manual that provide detai
14. 8 3 8 2 6 System Reset 8 4 8 2 7 Fest Module FOSQLD q i u ttc Pact dime ta xs 8 4 8 2 8 Reset Status Register Orge Pero 8 4 8 3 Res t Control 8 5 8 3 1 RESET Assertion by an External Device 8 6 8 3 2 Internal Reset 00 8 6 8 4 Power On Besel betonte eit e Dope 8 6 8 4 1 SIM Operation During Power On Reset 8 6 8 4 2 Other Modules During Power On Reset 8 7 8 5 Use of the Three State Control Pin 8 7 8 6 Operating Configuration out of Reset 8 8 8 6 1 Data Bus Mode Selection eer ch ede ean aks 8 8 8 6 2 Holding Data Bus Pins Low at Reset 8 9 8 6 3 Glock Mode Selection ORE e u elevatus 8 10 8 6 4 Breakpoint Mode Selection 8 10 8 7 Pin State During 8 11 8 8 SIM Registers Out of 8 13 8 9 System Initialization er 8 14 SECTION 9GENERAL PURPOSE 9 1 Pin Assignment Registers toe de PLE eaae 9 1 9 2 Data Direction Registers Lau usu a t e Rr Rene re ie ERU 9 2 9 3 Registers einni
15. 10 2 Address Select Pins Up to three address bus chip select pins ADDR 22 20 CS 9 7 PC 6 4 are optionally not included on MCUs with a reduced pin count SIM On MCUs that lack these pins ADDR 22 20 follow the logic level of ADDR19 and the chip select and discrete output functions for these pins are unavailable 10 3 Data Size and Acknowledge Pins On MCUs with both DSACK 1 0 pins an external device asserts the appropriate DSACK signal to indicate port size and the availability of data On some MCUS with a reduced pin count SIM no DSACKO pin is provided With these MCUS an external de vice indicates the availability of data by asserting DSACK1 regardless of port size All accesses thus appear to be word accesses When connecting an 8 bit device with an 8 bit port to an MCU with no DSACKO pin connect the peripheral to DATA 15 8 as usual The peripheral asserts DSACK1 rath er than DSACKO to indicate completion of the cycle and the read or write operation terminates after the first bus cycle SIM REDUCED PIN COUNT SIM MOTOROLA REFERENCE MANUAL 10 1 Connecting 8 bit device with 16 bit port e g a 16 bit timer to an MCU with no DSACKO0 pin requires one of the following work arounds For CPU16 based products connect the peripheral to DATA 15 8 Use long word load and store instructions LDED and STED and arrange the upper bytes of ac cumulators E and D into a word For CPU32 based pr
16. SIM SYSTEM CONFIGURATION AND PROTECTION MOTOROLA REFERENCE MANUAL 3 5 3 5 Software Watchdog The software watchdog is controlled by the software watchdog enable SWE bit in the SYPCR When enabled the watchdog requires that a service sequence be written to the software service register SWSR on a periodic basis If servicing does not take place the watchdog times out and asserts the reset signal Perform a software watchdog service sequence as follows Write 55 to the SWSR Write AA to the SWSR Both writes must occur in the order listed prior to time out but any number of instruc tions can be executed between the two writes Watchdog clock rate is affected by the software watchdog prescale SWP and soft ware watchdog timing SWT fields in the SYPCR SWP determines system clock prescaling for the watchdog timer Either no prescaling or prescaling by a factor of 512 can be selected During reset the state of the MOD CLK pin determines the value of SWP as shown in Table 3 2 System software can change the value of SWP Table 3 2 MODCLK Pin and SWP Bit During Reset MODCLK SWP Watchdog Prescaling 0 External Clock 1 512 1 Internal Clock 0 1 The SWT field in conjunction with the SWT bit selects the divide ratio used to estab lish software watchdog time out period Time out period is given by the following equa tions Time out Period 1 EXTAL Frequency Divide Ratio or Time
17. ns E8 ECLK Low to Data High Impedance tepHz 115 ns E9 CS Negated to Data Hold Read tECDH 0 ns E10 5 Negated to Data High Impedance tecpz 1 E11 ECLK Low to Data Valid Write teppw 2 12 ECLK Low to Data Hold Write tEDHW 5 ns E13 5 Negated to Data Hold Write tEcuw 0 ns E145 Address Access Time Read 386 ns E15 Chip Select Access Time Read tEACS 326 ns E16 Setup Time teas 1 2 1 All AC timing is shown with respect to 20 Vpp 70 Vpp levels unless otherwise noted 2 When the previous bus cycle is not an ECLK cycle the address may be valid before ECLK goes low Address access time teap tepsr 4 Chip select access time tecsp tEpsR ELECTRICAL CHARACTERISTICS SIM REFERENCE MANUAL CLKOUT 5 gt NOTE Timing shown with respect to 20 and 70 Vpp 68300 CLKOUT TIM Figure A 1 CLKOUT Output Timing Diagram EXTAL NOTE Timing shown with respect to 20 and 70 Vpp Pulse width shown with respect to 50 Vpp 68300 EXT CLK INPUT TIM Figure A 2 External Clock Input Timing Diagram ECLK NOTE Timing shown with respect to 20 and 70 Vpp 68300 ECLK OUTPUT TIM Figure A 3 ECLK Output Timing Diagram SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL 7 Table A 5 Key to Figures A 1 A 2 A 3 Abstracted
18. o Dove ta fe ede 9 3 SECTION 10 REDUCED PIN COUNT SIM 10 1 Optional RPSIM 2 02224 000 010000 10 1 10 2 Address Bus Chip Select Pins 10 1 10 3 Data Size and Acknowledge Pins 10 1 104 IRMG PIN 10 2 APPENDIX ELECTRICAL CHARACTERISTICS APPENDIX BMEMORY MAP AND REGISTERS B 1 SIM Memory r 1 SIM MOTOROLA REFERENCE MANUAL vii TABLE OF CONTENTS Continued Paragraph Title Page B 2 SIM amp ittm Ut B 3 MOTOROLA SIM viii REFERENCE MANUAL SIM LIST OF ILLUSTRATIONS Title Page System Integration Module Block Diagram 1 2 SIM Input and Output Signals 1 3 System Configuration and Protection 3 1 Periodic Interrupt Timer and Software Watchdog Timer 3 7 System Clock with 32 768 kHz Reference Crystal 4 2 System Clock with 4 194 MHz Reference Crystal 4 3 Crystal Layout Example o ect ee wey ted 4 4 Conditioning the XFC and Vppsyy PINS 4 6 Input Sample Window
19. 22 7 3 7 3 Pin Assignments and Discrete Output 7 4 7 4 GhipeSelect ODOrallolT LU 7 5 7 5 Chip Select Timing 7 9 7 5 1 Synchronization with AS or 05 2 7 9 7 5 2 Synchronization with 7 10 7 6 Chip Selects and Dynamic Bus Sizing 7 10 7 7 Fast Termination Cycles ep aa bu Uu ud 7 11 7 7 1 Fast Termination Read Cycle 7 12 7 7 2 Fast Termination Write Cycle 7 13 7 8 Using Chip Selects in Interrupt Acknowledge Cycles 7 13 7 8 1 Using a Chip Select Pin as an Interrupt Acknowledge Signal 7 14 7 8 2 Generating an Autovector Signal with a Chip Select Circuit 7 15 7 9 Chip Select Reset Operation 7 15 7 9 1 ek ime 7 16 7 9 2 CS 10 0 Base and Option Registers 7 16 7 9 3 CSBOOT Base Address and Option Registers 7 17 7 10 Chip Select Register 111 7 17 7 10 1 Chip Select Pin Assignment Registers 7 17 7 10 2 Chip Select Base Address Registers
20. 29 ns 35 IBR Asserted to BG Asserted Not Asserted tBRAGA 1 37 Asserted to BG Negated GAGN 1 2 39A Width Asserted tea 1 47 Input Setup Time 5 ns BR BGACK DSACK BERR AVEC HALT NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 9 To ensure coherency during every operand transfer BG will not be asserted in response to BR until after all cy cles of the current operand transfer are complete and RMC is negated 14 RMC signal is not supported CPU16 based MCUs MOTOROLA A 16 ELECTRICAL CHARACTERISTICS SIM REFERENCE MANUAL A0 A5 A5 A2 A0 ye e NC SENA AS UE Xe uA NS 68300 BUS ARB TIM IDLE Figure A 9 Bus Arbitration Timing Diagram Idle Bus Case Table A 11 Key to Figure A 9 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Max Units 33 Clock Low to BG Asserted Negated tcLBA 29 ns 359 Asserted to BG Asserted RMC Not Asserted tBRAGA 1 37 Asserted to Negated 1 2 47A Input Setup Time tAIST 5 ns BR BGACK DSACK BERR AVEC HALT NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted
21. 4 DSACK1 B Y N 1 DSACK01 B Y N PEO EXTAL3 Special FC 2 0 CS 5 3 A Y N 2 0 HALT Bo Y N IRQ 7 6 B Y Y 7 6 RABA B Y Y 5 1 MODCLK2 B Y N PFO R W A Y N RESET Bo Y Y RMC B Y N SIZ 1 0 B Y N PE 7 6 TSTME TSC Y Y XFC3 E XTAL3 NOTES 1 These pins may not be implemented on certain MCUs 2 DATA 15 0 are synchronized during reset only MODCLK is synchronized only when used as an input port pin 3 CLKOUT EXTAL XFC and XTAL are clock reference connections MOTOROLA 2 2 SIGNAL AND PIN DESCRIPTIONS SIM REFERENCE MANUAL 2 2 Signal Descriptions The following tables are a quick reference to SIM signals Table 2 3 shows signal name type and active state Table 2 4 describes signal functions Both tables are sorted alphabetically by mnemonic Since MCU pins often have multiple functions more than one description may apply to a pin Table 2 3 SIM Signal Characteristics Signal Signal Active Name Type State ADDR 23 0 Bus AS Output 0 AVEC Input 0 BERR Input 0 BG Output 0 BGACK Input 0 BR Input 0 CLKOUT Output CS 10 0 Output 0 CSBOOT Output 0 DATA 15 0 Bus DS Output 0 DSACK T 0 Input 0 EXTAL Input FC 2 0 Output FREEZE Output 1 HALT Input Output 0 IRQ 7 1 Input 0
22. F highest priority to 1 lowest priority if lower priority interrupts are to be arbitrated Refer to SECTION 6 INTERRUPTS for additional information 3 1 5 Factory Test Mode The internal IMB can be slaved to an external master for direct module testing This mode is reserved for factory testing Factory test mode is enabled by holding DATA1 1 low during reset The factory test slave mode enabled SLVEN bit is a read only bit that shows the reset state of DATA11 3 1 6 SIM Configuration Register The SIM configuration register SIMCRS controls system configuration It can be read or written at any time Refer to the discussion of the MM bit however for certain re strictions SIMCR Module Configuration Register 00 15 14 13 12 11 10 9 8 7 6 5 4 3 0 EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB RESET 0 0 0 0 DATA 0 0 0 1 1 0 0 1 1 1 1 11 EXOFF External Clock Off 0 The CLKOUT pin is driven from an internal clock source 1 The CLKOUT pin is placed a high impedance state FRZSW Freeze Software Enable 0 When FREEZE is asserted the software watchdog and periodic interrupt timer counters continue to run 1 When FREEZE is asserted the software watchdog and periodic interrupt timer counters are disabled preventing interrupts during software debugging SIM SYSTEM CONFIGURATION AND PROTECTION MOTOROLA REFERENCE MANUAL 3 3 FRZBM Freeze Bus Mo
23. serts DSACKO to indicate that the first byte has been transferred The MCU then dec rements the transfer size counter increments the address and transfers OP1 to bits 15 8 of the data bus for the second cycle of the transfer a byte write to an 8 bit port For both reads and writes refer to 5 5 1 Byte Operand to 8 Bit Port for details on the second cycle of the data transfer 5 5 5 Word Operand to 8 Bit Port Misaligned To initiate a transfer the MCU places the desired address on the address bus and drives the size pins to indicate a word operand The MCU also drives the function code and R W pins to appropriate values MOTOROLA EXTERNAL BUS INTERFACE SIM 5 18 REFERENCE MANUAL The CPU32 does not support misaligned operand transfers 15 8 7 0 Operand OPO OP1 Data Bus 15 8 7 0 SIZ1 5120 ADDRO DSACK1 DSACKO Cycle 1 OPO 1 0 1 1 0 Cycle 2 OP1 OP1 0 1 0 1 0 Figure 5 12 Word Operand to 8 Bit Port Misaligned For a read operation the 8 bit peripheral responds by placing OPO on DATA 15 8 and asserting DSACKO The MCU reads the upper operand byte from DATA 15 8 and ig nores DATA 7 0 The MCU then decrements the transfer size counter increments the address and waits for the peripheral to place OP1 on the upper byte of the data bus for the second cycle of the transfer a byte read of an 8 bit port For write operation the MCU drives on DATA 15 8 and OP1 on DATA 7 0
24. 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 14 RMC signal is not supported on CPU32 based MCUs SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 21 CLKOUT ECLK ADDR 23 0 DATA 15 0 DATA 15 0 68300 E CYCLE TIM Figure 12 Timing Diagram MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 22 REFERENCE MANUAL Table A 14 Key to Figure A 12 Abstracted from Tables A 3 and A 4 see tables for complete notes Nm Characteristce Symbol Min Max Units 1A Period tEcyc 476 ns 2A ECLK Pulse Width tecw 236 ns 4 5 Rise and Fall Time All Outputs except CLKOUT tert 8 ns E17 Low to Address and R W Valid TEAD 60 ns E2 ECLK Low to Address R W Hold tEAH 10 ns ECLKLowtoCS Valid CS delay tess 120 ms 4 Low to CS Hold tEcsH 15 ns E5 5 Negated Width tECSN 100 ns E6 Read Data Setup Time tEpsR 30 ns E7 Read Data Hold Time tEDHR 15 ns E8 ECLK Low to Data High Impedance tEpuz 115 ns E9 CSNegatedto Data Hold Rea 0 ms E10 5 Negated to Data High Impedance tEcpz 1 11 ECLK Low to Data Valid Write tEDDW 2 12 ECLK Low to Data Hold Write tEpHW 5 ns E13 5 Negated to Data Hold Wr
25. 30 TEST MODULE MASTER SHIFT A TSTMSRA S THHHE32 TEST MODULE MASTER SHIFT B TSTMSRB S THHHESA TEST MODULE SHIFT COUNT TSTSC S THHHE36 TEST MODULE REPETITION COUNTER TSTRC S THHHE38 TEST MODULE CONTROL CREG S U THHHEGA TEST MODULE DISTRIBUTED DREG S THHHESC UNUSED UNUSED S THHHEGE UNUSED UNUSED S U THHHIAO UNUSED PORT C DATA PORTC S U THHHIA2 UNUSED UNUSED S THHHIAA CHIP SELECT PIN ASSIGNMENT REGISTER CSPARO S THHHIAG CHIP SELECT PIN ASSIGNMENT REGISTER CSPAR1 S THHHIAB CHIP SELECT BASE ADDRESS REGISTER BOOT CSBARBT S THHHIAA CHIP SELECT OPTION REGISTER BOOT CSORBT S THHHIAC CHIP SELECT BASE ADDRESS REGISTER 0 CSBARO MEMORY MAP AND REGISTERS MOTOROLA B 1 Table B 1 SIM Address Map Continued Access Address 15 817 0 5 THHHIAE CHIP SELECT OPTION REGISTER 0 CSORO S THHHEDO CHIP SELECT BASE ADDRESS REGISTER 1 CSBAR1 S THHHED2 CHIP SELECT OPTION REGISTER 1 CSOR1 S 54 CHIP SELECT BASE ADDRESS REGISTER 2 CSBAR2 S THHHEDG CHIP SELECT OPTION REGISTER 2 CSOR2 S 58 CHIP SELECT BASE ADDRESS REGISTER 3 CSBAR3 S CHIP SELECT OPTION REGISTER 3 CSOR3 S THHHIBC CHIP SELECT BASE ADDRESS REGISTER 4 CSBAR4 S 5E CHIP SELECT OPTION REGISTER 4 CSOR4 S THHHEGO CHIP SELECT BASE ADDRESS REGISTER 5 CSBAR5 S THHHEG2 CHIP SELECT OPTION REGISTER 5 CSOR5 S 64 CHIP SELECT BASE ADDRESS REGISTER 6
26. 4 4 1 Frequency Control with a Reference Frequency of 25 50 kHz 4 6 4 4 2 Frequency Control with a Reference Frequency of 3 2 6 4 MHz 4 7 4 4 3 Avoiding Frequency Overshoot 4 7 4 4 4 Frequency Control Fables i eR RERUM 4 7 4 5 External Bu s und 4 11 4 6 Low Power Stop Operation 4 11 4 7 Loss of Reference Signal 4 12 4 8 Clock Synthesizer Control Register SYNCR 4 13 SECTION 5 EXTERNAL BUS INTERFACE 5 1 Bus Signal DescripllOlis s uoce 5 1 5 1 1 u reete A o M LL LM des 5 2 5 1 2 Address Strobe 5 2 5 1 3 Data d eid LET ae 5 2 5 1 4 PALA em 5 2 5 1 5 Read Write Signal proeul nage piece tes d ect 5 2 5 1 6 uito eL a a E asus 5 2 5 1 7 Function CodeS 5 2 5 1 8 Data and Size Acknowledge Signals 5 3 5 1 9 Bus Error Signal drin ecc uus 5 3 5 1 10 MEI cS 5 3 5 1 11 uot eases cnet lagen oet tae c oi credo 5 3 5 2 External Bus Cycle Overview r 5 4 5 2 1 Bus Cycle
27. 542 No change The bus controller remains in S42 until the internal read cycle is complete State 43 843 DS is negated to indicate that show data is valid on the next falling edge of CLKOUT External data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus State 0 50 ADDR 23 0 FC 2 0 and SIZ 1 0 pins change state to begin the next cycle Data from the preceding cycle is valid through SO MOTOROLA EXTERNAL BUS INTERFACE SIM 5 52 REFERENCE MANUAL SECTION 6 INTERRUPTS Interrupt recognition and servicing involve complex interaction between the system in tegration module the central processing unit and a device or module requesting in terrupt service This discussion provides an overview of the entire interrupt process Chip select logic can also be used to respond to interrupt requests from external de vices Refer to SECTION 7 CHIP SELECTS for more information The CPU handles interrupts as a type of asynchronous exception An exception is an event that preempts normal processing Each exception has an assigned vector that points to an associated handler routine During exception processing the CPU fetches the vector assigned to the exception and executes the exception routine to which the vector points Refer to the appropriate CPU manual for additional information on ex ception processing 6 1 Sources of Interrupt External devices or m
28. Refer to 7 9 Chip Select Reset Operation for ad ditional information on pin assignments at reset CSPARO Chip Select Pin Assignment Register 0 IHHHIAA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 CSPAO 6 CSPAO 5 5 4 CSPA0 3 CSPA0 2 CSPAQ 1 CSBOOT RESET 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATAO CSPARO contains seven two bit fields that determine the functions of corresponding chip select pins CSPARO 15 14 are not used These bits always read zero writes have no effect CSPARO bit 1 always reads one writes to CSPARO bit 1 have no ef fect Table 7 9 CSPARO Pin Assignments CSPARO Field Chip Select Signal Alternate Signal Discrete Output CSPAO 6 CS5 FC2 PC2 CSPAO 5 54 1 1 53 PCO CSPAO 3 CS2 BGACK CSPA0 2 CS1 BG CSPAQ 1 50 CSBOOT CSBOOT CSPAR1 Chip Select Pin Assignment Register 1 1HHHIAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CSPA1 4 CSPA1 8 CSPA1 2 CSPA1 1 CSPA1 0 RESET 0 0 0 0 0 0 DATA7 1 DATA6 1 DATAS 1 DATA4 1 DATA3 1 CSPAR1contains five two bit fields that determine the functions of corresponding chip select pins CSPAR1 15 10 are not used These bits always read zero writes have no effect Table 7 10 CSPAR1 Pin Assignments CSPARO Field Chip Select Signal Alternate Signal D
29. These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on synchronous reads The user is free to use either hold time 14 RMC signal is not supported on CPU16 based MCUs SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 19 50 51 54 55 50 lt 68300 FAST WR CYC TIM Figure A 11 Fast Termination Write Cycle Timing Diagram MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 20 REFERENCE MANUAL Table A 13 Key to Figure A 11 Abstracted from Table A 3 see table for complete notes Nm Characteristic Symbol Min Max Units 614 Clock High to Address FC SIZE RMC Valid lcHAV 0 29 ns 874 Clock High to Address FC SIZE RMC Invalid tcHazn 0 ns 9 Clock Low to AS DS CS Asserted ici SA 2 25 ns 12 Clock Low to AS DS CS Negated 2 29 14B 5 CS Width Asserted tswow 40 ns 18 Clock High to R W High CHRH 0 29 ns 20 Clock High to RW Low 0 29 ns 23 Clock High to Data Out Valid tcHDo 29 ns 24 Data Out Valid to Negating Edge of AS CS 15 ns 25 105 CS Negated to Data Out Invalid Data Out Hold teNDOI 15 ns 46A R W Width Asserted trwas 90 ns 73 BKPTInputSetupTime 15 ms 74 BKPT Input Hold Time tBKHT 10 ns NOTES
30. Vss All input output and output pins 2 5 2 5 CMOS Output High Voltage 3 Vou Vpp 02 V 710 0 pA Group 1 2 input output and all output pins CMOS Output Low Voltage VoL 0 2 V logi 10 0 Group 1 2 input output and all output pins Output High Voltage Vou Vpp 0 8 V 0 8 mA Group 1 2 input output and all output pins Output Low Voltage VoL V loi 1 6 mA Group 1 I O Pins FREEZE QUOT 0 4 lol 5 3 mA Group 2 I O Pins CSBOOT BG CS 0 4 12 mA Group 3 0 4 Three State Control Input High Voltage Vintsc 1 6 Vpp 9 1 V Data Bus Mode Select Pull up Current Vin Vi DATA 15 0 120 Vin Vin DATA 15 0 15 Vpp Supply Current RUN 4 124 mA LPSTOP 32 768 kHz or 4 194 MHz crystal VCO Off STSIM 0 Sipp 350 LPSTOP External clock input frequency maximum Sipp 5 Clock Synthesizer Operating Voltage lt 4 5 5 5 V Vppsyn Supply Current 32 768 kHz or 4 194 MHz crystal VCO on maximum fsys IppsvN E 1 mA External Clock maximum fey IppsvN 5 mA LPSTOP 32 768 kHz or 4 194 MHz crystal VCO off STSIM 0 SIDDSYN 150 uA 32 768 kHz or 4 194 MHz crystal Vpp powered down IppsvN 100 uA Power Dissipation Pp 690 mW Input Capacitance 8 Cin 10 pF All input only pins 20 All input output pins Load Capacitance Group 1 I O Pins and CLKOUT FREEZE QUOT CL 90 pF Group 2 I O Pins and CSB
31. base address and options registers to assign pin function initialize chip selects and assign base addresses and options Initialize the port E and port F data registers Then program the port E and port F data direction and pin assignment registers if necessary to change the reset values Initializing the data registers first guarantees that the desired logic level is output on the pins that are configured as outputs MOTOROLA RESET AND SYSTEM INITIALIZATION SIM 8 14 REFERENCE MANUAL SECTION 9GENERAL PURPOSE Sixteen of the SIM pins can be configured for general purpose discrete input and out put Although these pins are organized into two ports port E and port F function as signment is by individual pin Pin assignment registers data direction registers and data registers are used to implement discrete In addition to the sixteen pins in ports E and F the seven pins in port C can be config ured as discrete outputs Port C is discussed in SECTION 7 CHIP SELECTS The fol lowing paragraphs describe ports E and F NOTE On MCUS with a reduced pin count SIM some of the pins that com prise ports E and F may not be available Refer to the user s manual for the particular MCU for a list of the pins on the chip 9 1 Pin Assignment Registers Bits in the port E and port F pin assignment registers PEPAR and PFPAR control the functions of the pins in each port Any bit cleared to zero defines the corresponding pi
32. 0 Periodic Interrupt Vector The bits of this field contain the periodic interrupt vector number supplied by the SIM when the CPU acknowledges an interrupt request PITR Periodic Interrupt Timer Register 1HHHI24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PTP PITM RESET 0 0 0 0 0 0 0 MODCLK 0 0 0 0 0 0 0 0 PTP Periodic Timer Prescaler Control 1 Periodic timer clock prescaled by a value of 512 0 Periodic timer clock not prescaled PITM 7 0 Periodic Interrupt Timing Modulus This is the 8 bit timing modulus used to determine periodic interrupt rate Use the fol lowing expression to calculate timer period PIT Period Modulus Prescaler value 4 EXTAL Frequency SWSR Software Service Register 1HHHEI26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 0 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 MOTOROLA MEMORY MAP AND REGISTERS SIM B 8 REFERENCE MANUAL PORTC Port C Data Register 40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 0 PC6 PC5 4 2 1 PC0 RESET 1 1 1 1 1 1 1 1 CSPAR0 Chip Select Pin Assignment Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 CSPAO 6 CSPAO 5 5 4 CSPA0 3 CSPA0 2 CSPAQ 1 CSBOOT RESET 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATAO 5
33. 1 4 3 2 3 4 MODCLK 3 6 3 7 4 1 4 4 8 10 MODE 7 2 7 9 7 10 7 20 Mode selection with DATA pins 1 6 1 7 8 8 Module mapping MM 1 4 3 2 3 4 Operands alignment 5 7 byte order 5 15 misaligned 5 8 5 18 5 20 5 23 5 26 transfer cases 5 15 Option registers chip select 7 19 Output driver types 2 1 Output discrete 7 4 7 21 SIM REFERENCE MANUAL 9 1 PEPAR 9 1 Periodic interrupt control register PICR 3 8 3 10 request level PIRQL 3 8 3 10 vector PIV 3 8 3 10 PFPA 9 2 PFPAR 9 1 9 2 Phase locked loop PLL 4 1 PICR 3 8 3 10 Pin assignment chip selects at reset 7 16 registers chip select 7 4 7 17 ports E and F 9 1 Pins SIM 2 1 characteristics 2 1 2 2 output driver types 2 1 state during reset 8 11 PIRQL 3 8 3 10 PIT 3 7 3 8 6 1 modulus counter PITM 3 8 3 11 prescaler PTP 3 7 3 10 priority 3 9 vector 3 9 PITCLK PIT clock 3 8 PITM PIT modulus 3 8 3 11 PITR PIT register 3 7 3 10 PIV 3 8 3 10 PLL 4 1 4 7 Port C data register PORTC 7 21 Ports E and F 9 1 data direction registers 9 2 data register 9 3 pin assignment register 9 1 9 2 POW power on reset flag 8 3 8 4 Power on reset 8 3 8 6 Privilege levels 1 4 3 2 protection system 3 1 registers 3 9 PTP 3 7 3 10 R R W 5 2 and interrupts 6 3 bit 7 2 7 20 Read cycles 5 8 and RPSIM 10 2 fast termination 7 12 modify write RMC 5 13 5 43 5 47 timing diagram A 9 Reduced pin count SIM RP
34. 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 6 PFO RESET U U U U U U U U SIM GENERAL PURPOSE 1 0 MOTOROLA REFERENCE MANUAL 9 3 MOTOROLA GENERAL PURPOSE SIM 9 4 REFERENCE MANUAL SECTION 10 REDUCED PIN COUNT SIM Some Motorola MCUS contain a version of the SIM with a reduced pin count MCUs with a reduced pin count SIM RPSIM always contain the SIM pins that are most basic to MCU operation some SIM pins however are not included on these chips The set of pins that are not connected depends on the MCU but it is always a subset of the pins listed in this section This section lists the pins that may be omitted from RPSIM based MCUs and discusses how the omission of these pins affects SIM operation 10 1 Optional RPSIM Pins Table 10 1 lists the pins that are optionally not included on MCUS with a reduced pin count SIM RPSIM based MCUs may still have some of these pins available depend ing on the requirements of the particular microcontroller Refer to the user s manual for the specific MCU for a list of the pins on a given chip Table 10 1 Optional RPSIM Pins Pin Description Port Mnemonic Designation ADDR 22 20 CS 9 7 Address Bus Chip Selects PC 6 4 AVEC Autovector PE2 CSBOOT Boot Chip Select DSACKO Data and Size Acknowledge PEO HALT Halt IRQ 5 1 Interrupt Request Level PF 5 1 RMC Read Modify Write Cycle
35. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDEO RESET 0 0 0 0 0 0 0 0 DDRF Port F Data Direction Register SIHHHHC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDFO RESET 0 0 0 0 0 0 0 0 9 3 Data Registers A write to the port E and port F data registers PORTE and is stored an internal data latch and if any pin in the corresponding port is configured as an output the value stored for that bit is driven out on the pin A read of a data register returns the value atthe pin only if the pin is configured as a discrete input Otherwise the value read is the value stored in the register Both data registers can be accessed in two lo cations They can be read or written at any time PORTE and PORTF are unaffected by reset PORTEO PORTE1 Port E Data Register SHHHHIO S 12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 RESET U U U U U U U U NOTE On CPU16 based MCUs the RMC signal is not implemented and may not be connected to a pin CPU16 based MCUs the value read from depends on the particular MCU Refer to the ap propriate MCU user s manual Writes to have no effect when the RMC PES pin is not available PORTFO PORTF1 Port F Data Register 8 SHHHHIA 15 14 13 12
36. 2 Clock Synthesizer Operation When MODCLK is held high during reset a voltage controlled oscillator VCO in the phase locked loop generates the system clock signal A portion of the clock signal is fed back to a divider counter The divider controls the frequency of one input to a phase comparator The other phase comparator input is the reference signal The comparator generates a control signal proportional to the difference in phase between its two inputs The signal is low pass filtered and used to correct VCO output frequen cy The synthesizer locks when VCO frequency is equal to reference frequency or refer ence frequency divided by 128 if the reference frequency is a 4 194 MHz crystal Lock time is affected by the filter time constant and by the amount of difference be tween the two comparator inputs Whenever a comparator input changes the synthe sizer must relock Lock status is shown by the SLOCK bit in the SYNCR The MCU does not come out of the reset state until the synthesizer locks 4 3 External Circuit Design The following paragraphs discuss design issues relating to the oscillator circuit and ex ternal filter circuit 4 3 1 Conditioning the XTAL and EXTAL Pins As in all crystal oscillator designs all leads should be kept as short as possible It is also good practice to route Vss paths as shown in Figure 4 3 These paths isolate the oscillator input from the output and the oscillator from adjacent circuitry onl
37. A 7 A 2 External Clock Input Timing Diagram A 7 A 3 Output Timing Diagrami e HO E ci A 7 A 4 Read Cycle Timing Diagram a A 9 A 5 Write Cycle Timing Diagram ete etin ccs A 11 A 6 Show Cycle Timing Diagram A 13 A 7 Reset and Mode Select Timing A 14 A 8 Bus Arbitration Timing Diagram Active Bus Case A 15 A 9 Bus Arbitration Timing Diagram Idle Bus Case A 17 A 10 Fast Termination Read Cycle Timing Diagram A 18 A 11 Fast Termination Write Cycle Timing Diagram A 20 Timing Diagram cea A 22 A 13 Chip Select Timing 2000000 0 A 24 MOTOROLA SIM x REFERENCE MANUAL Table 7 10 SIM LIST OF TABLES Title Page MIM Address suara u ua a 1 5 SIM Reset Mode Selection 1 7 CPU Differences Affecting SIM Operation 1 8 SIM Output Driver EIOS secre o rr ar acc ein 2 1 SIM Pin Characteristics 5 teeth Mette
38. A write operation consists of one or more write cycles If the instruction spec ifies a long word or word operation the MCU attempts to write two bytes per cycle For a byte operation the MCU writes one byte The portion of the data bus to which each byte is written depends on operand size peripheral address and peripheral port size Refer to 5 3 Dynamic Bus Sizing for more information Figure 5 4 is a flow chart of a write cycle for a word transfer MCU PERIPHERAL ADDRESS DEVICE 50 SET R W TO WRITE DRIVE ADDRESS ON ADDR 23 0 1 2 3 DRIVE FUNCTION CODE ON FC 2 0 4 DRIVE SIZ 1 0 FOR OPERAND SIZE ASSERT AS 1 PLACE DATA ON DATA 15 0 S2 ASSERT DS AND WAIT FOR DSACK S3 ACCEPT DATA S2 S3 1 DECODE ADDRESS 2 LATCH DATA FROM DATA BUS 3 ASSERT DSACK SIGNALS TERMINATE OUTPUT TRANSFER S5 1 NEGATE AS AND DS 2 REMOVE DATA FROM DATA BUS TERMINATE CYCLE START NEXT CYCLE 1 NEGATE DSACK WR CYC FLOW Figure 5 4 Write Cycle Flow Chart State 0 0 The MCU places an address on ADDR 23 0 and function codes on FC 2 0 On CPU16 based MCUs ADDR 23 20 always follow the state of ADDR19 and FC2 is always equal to one The MCU drives R W low for a write cycle SIZ 1 0 become valid indicating the number of bytes to be written SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 11 State 1 S1 The MCU asserts AS indicating that the address on the address b
39. ADDR20 ADDR19 x x x x x oj gt x gt x X x 1 1 1 1 1 0 7 9 2 CS 10 0 Base and Option Registers Base address and option registers for CS 10 0 have reset values of all zeros This means that the chip selects are disabled out of reset Assigning a nonzero value in the BYTE field of the option register enables the associated chip select MOTOROLA CHIP SELECTS SIM 7 16 REFERENCE MANUAL 7 9 3 CSBOOT Base Address Option Registers The CSBOOT assignment field in CSPARO is configured differently from the other pin assignment fields The MSB bit 1 of the CSBOOT assignment field in CSPARO has a reset value of one This enables the CSBOOT signal to select a boot ROM contain ing initialization firmware The LSB value determined by the logic level of DATAO dur ing reset selects boot ROM port size When DATAO is held low port size is 8 bits When DATAO is held high either by the weak internal pull up driver or by an external pull up device port size is 16 bits After reset the MCU fetches initialization vectors beginning at word address 000000 To support bootstrap operation from reset the base address field in chip select base address register boot CSBARBT has a reset value of all zeros A ROM device con taining a reset vector beginning at its base address can be enabled by CSBOOT after a reset Table 7 8 shows the reset values in the base and option registers for CS
40. Alternate Function 10 Chip Select 8 Bit Port 11 Chip Select 16 Bit Port CSBARBT Chip Select Base Address Register Boot ROM 1HHHIA8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 CSBAR 10 0 Chip Select Base Address Registers SIHHHIAC SIHHHIETA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 15 3 Base Address Field This field sets the starting address of a particular address space BLKSZ Block Size Field This field determines the size of the block above the base address that is enabled by the chip select CSORBT Chip Select Option Register Boot ROM SIHHHIAA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE BYTE RW STRB DSACK SPACE IPL RESET 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 CSOR 10 0 Chip Select Option Registers SHHHHOE S HH 76 15 14 13 12 11 10 9 8 TA 6 5 4 3 2 1 0 MODE BYTE RW STRB DSACK SPACE IPL RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE Timing Mode The MODE bit determines whether chip select operation emulates asynchronous bus operation or is synchronized to the M6800 type bus clock signal ECLK available on A
41. BERR assertion is not detected until an instruction is complete The BERR latch is cleared by the first instruction of the BERR exception handler Double bus faults may occur under the following conditions depending on the CPU Bus error exception processing begins and a second is detected before the first instruction of the first exception handler is executed One or more bus errors occur before the first instruction after a reset exception is executed A bus error occurs while the CPU is loading information from a bus error stack frame during a return from exception RTE instruction CPU32 based MCUs only Multiple bus errors within a single instruction which can generate multiple bus cycles cause a single bus error exception after the instruction has executed MOTOROLA EXTERNAL BUS INTERFACE SIM 5 42 REFERENCE MANUAL Immediately after assertion of a second BERR signal the MCU halts and drives the HALT line low Only a reset can restart a halted MCU However bus arbitration can still occur Refer to 5 10 Bus Arbitration A bus error or address error that occurs after exception processing has completed during the execution of the exception han dler routine or later does not cause a double bus fault A bus cycle that is retried does not constitute a bus error or cause a double bus fault The MCU continues to retry the same bus cycle as long as the external hardware requests it 5 9 3 Retry Operation SIM W
42. BUS CONTROL NOTE All figures are shown in positive logic active high regardless of their active state BUS ARB STATE Figure 5 37 Bus Arbitration State Diagram State changes occur on the next rising edge of CLKOUT after the internal signal is val id The BG signal transitions on the falling edge of the clock after a state is reached during which G changes The bus control signals controlled by T are driven by the MCU immediately following a state change when bus mastership is returned to the MCU State 0 in which G and T are both negated is the state of the bus arbiter while the MCU is bus master Request R and acknowledge A keep the arbiter in state 0 as long as they are both negated SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 51 5 10 6 Factory Test Slave Mode Arbitration This mode is used for factory production testing of internal modules It is not supported for customer use due to abnormal operating conditions that result Factory test mode is enabled by holding DATA11 low during reset In this mode when BG is asserted the MCU is slaved to an external tester that has full access to all internal registers 5 11 Show Cycles The MCU normally performs internal data transfers without affecting the external bus but it is possible to show these transfers during debugging AS is not asserted exter nally during show cycles Show cycles are controlled by the SHEN field in the SIMCR Refer to 3 1 6 SIM Con fig
43. CPU space write to address 3FFFE This write puts a copy of the interrupt mask value in the clock control logic The mask is encoded on the data bus as shown in Figure 5 30 The CPU space cycle is shown externally if the bus is available as an indication to external devices that the MCU is going into low power stop mode The SIM provides an internally gen erated DSACK response to this cycle The timing of this bus cycle is the same as for a fast write cycle 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IP MASK Figure 5 30 LPSTOP Interrupt Mask Level The SIM brings the MCU out of low power mode when either an interrupt of higher pri ority than the stored mask or a reset occurs Refer to the appropriate CPU reference manual for more information 5 9 Bus Error Processing An external device or a chip select circuit must assert at least one of the DSACK 1 0 signals or the AVEC signal to terminate a bus cycle normally Bus error processing oc curs when bus cycles are not terminated in the expected manner The internal bus monitor can be used to generate BERR internally causing a bus error exception to be taken Bus cycles can also be terminated by assertion of the external BERR or HALT signal or by assertion of the two signals simultaneously Acceptable bus cycle termination sequences are summarized as follows The case numbers refer to Table 3 5 which in
44. CSBAR6 S THHHEOG CHIP SELECT OPTION REGISTER 6 CSOR6 S 1THHHEG8 CHIP SELECT BASE ADDRESS REGISTER 7 CSBAR7 S THHHEGA CHIP SELECT OPTION REGISTER 7 CSOR7 S THHHEGC CHIP SELECT BASE ADDRESS REGISTER 8 CSBAR8 S CHIP SELECT OPTION REGISTER 8 CSOR8 S THHHETO CHIP SELECT BASE ADDRESS REGISTER 9 CSBAR9 S THHHET2 CHIP SELECT OPTION REGISTER 9 CSOR9 S THHHETA CHIP SELECT BASE ADDRESS REGISTER 10 CSBAR10 S THHHETG CHIP SELECT OPTION REGISTER 10 CSOR10 THHHETB UNUSED UNUSED THHHETA UNUSED UNUSED THHHETC UNUSED UNUSED THHHETE UNUSED UNUSED MOTOROLA MEMORY MAP AND REGISTERS SIM B 2 REFERENCE MANUAL B 2 SIM Registers SIMCR Module Configuration Register 00 15 14 13 12 11 10 9 8 7 6 5 4 3 0 EXOFF FRZSW FRZBM 0 SLVEN 0 SHEN SUPV MM 0 0 IARB RESET 0 0 0 0 DATA 0 0 0 1 1 0 0 1 1 1 1 11 EXOFF External Clock Off 0 The CLKOUT pin is driven from an internal clock source 1 The CLKOUT pin is placed in a high impedance state FRZSW Freeze Software Enable 0 When FREEZE is asserted the software watchdog and periodic interrupt timer counters continue to run 1 When FREEZE is asserted the software watchdog and periodic interrupt timer counters are disabled preventing interrupts during software debugging FRZBM Freeze Bus Monitor Enable 0 When FREEZE is asserted the bus monitor continues to operate 1 When FREEZE is asserted the bus
45. CSORBT contains parameters that support bootstrap operations from periph eral memory devices Bit and field definitions for and CSOR 10 0 are the same but their reset settings differ CSORBT Chip Select Option Register Boot ROM SIHHHIAA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE BYTE RW STRB DSACK SPACE IPL AVEC RESET 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 CSOR 10 0 Chip Select Option Registers SIHHHIAE SIHHHETG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE BYTE RW STRB DSACK SPACE IPL AVEC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 19 MODE Timing Mode The MODE bit determines whether chip select operation emulates asynchronous bus operation or is synchronized to the M6800 type bus clock signal ECLK available on ADDR23 Refer to 7 5 Chip Select Timing for additional information 0 Emulate asynchronous bus operation 1 Synchronize chip select assertion to ECLK BYTE Upper Lower Byte Option This field enables or disables the chip select circuit and for 16 bit ports determines which combinations of size and ADDRO pins will cause the chip select to be asserted Refer to 7 6 Chip Selects and Dynamic Bus Sizing for more information 00 Disable 01 Lower byte 10 Upper byte 11 Both Bytes R W Read Write This field causes a chip select to be asserted only for a read only for a write or for
46. MCU also drives the function code and R W pins to appro priate values MOTOROLA EXTERNAL BUS INTERFACE SIM 5 20 REFERENCE MANUAL SIM Operand OP0 OP1 OP1 OP3 Data Bus 15 8 7 0 SIZ1 5120 ADDRO DSACK1 DSACKO Cycle 1 OPO OP1 0 0 0 1 0 Cycle 2 OP1 OP1 1 1 1 1 0 Cycle 3 OP2 OP2 1 0 0 1 0 Cycle 4 0 1 1 1 0 Figure 5 15 Long Word Operand to 8 Bit Port Aligned For a read operation the peripheral places OPO on DATA 15 8 and asserts DSACKO to indicate an 8 bit port The MCU reads from DATA 15 8 and ignores DA TA 7 0 The MCU then decrements the transfer size counter increments the address and waits for the peripheral to place OP1 on the upper byte of the data bus for the sec ond cycle of the transfer a three byte read of an 8 bit port The process is repeated for OP2 in the third cycle aligned word to 8 bit port transfer and OP3 in the fourth cy cle byte to 8 bit port transfer For write operation the MCU drives on DATA 15 8 and OP1 on DATA 7 0 The peripheral device then reads only OPO from DATA 15 8 and asserts DSACKO to indicate an 8 bit port The MCU then decrements the transfer size counter increments the address and writes OP1 to DATA 15 8 during the second cycle a three byte to 8 bit port transfer The process is repeated for OP2 in the third cycle aligned word to 8 bit port transfer and in the fourth cycle byte to 8 bit port
47. MCU cannot service interrupt requests while halted CLKOUT ADDR 23 0 FC 2 0 R W DATA 15 0 HALT MOTOROLA 5 46 S0 lt 52 54 50 52 54 S E Rumi s s X I x X I WM So READ gt lt gt ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED Figure 5 35 HALT Timing EXTERNAL BUS INTERFACE S0 HALT TIM SIM REFERENCE MANUAL 5 10 Bus Arbitration SIM MCU bus design provides for a single bus master at any one time Either the MCU or an external device can be master Bus arbitration protocols determine when an exter nal device can become bus master Bus arbitration requests are recognized during normal processing during HALT assertion and when the CPU has halted due to a double bus fault The bus controller in the MCU manages bus arbitration signals so that the MCU has the lowest priority Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices so that when two or more external devices attempt to become bus master at the same time the one having the highest priority becomes bus master first External devices that need to obtain the bus must assert bus arbitration signals in the following sequence An external device asserts the bus request signal The MCU asserts the bus grant si
48. MODCLK Input 6 0 Output Port PE 7 0 Input Output Port PF 7 0 Input Output Port R W Output 1 0 RESET Input Output 0 RMC Input Output 0 SIZ 1 0 Output TSC Input TSTME Input 0 XFC Input XTAL Output SIM REFERENCE MANUAL SIGNAL AND PIN DESCRIPTIONS MOTOROLA 2 3 Table 2 4 SIM Signal Function Signal Name Mnemonic Function Address Bus ADDR 23 0 24 bit address bus Address Strobe AS Indicates that a valid address is on the address bus Autovector AVEC Requests an automatic vector during interrupt acknowledge Bus Error BERR Indicates that a bus error has occurred Bus Grant BG Indicates that the MCU has relinquished the bus Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership Breakpoint BKPT Signals a hardware breakpoint to the CPU Bus Request BR Indicates that an external device requires bus mastership Chip Selects CS 10 0 Select external devices at programmed addresses Boot Chip Select CSBOOT Chip select for external boot start up ROM System Clockout CLKOUT System clock output Data Bus DATA 15 0 16 bit data bus Data Strobe DS During a read cycle indicates that an external device should place valid data on the data bus During a write cycle indicates that valid data is on the data bus Halt HALT Suspend external bus activity Interrupt Request Level IR
49. Operation 5 4 5 2 2 synchronization to CLKOU T acca aka wal ae 5 5 5 3 Dynamic BUS SIZING 5 6 5 3 1 Size Signal ERGOdinIg 5 6 5 8 2 Data and Size Acknowledge Signal Encoding 5 6 5 3 3 Operand Alignment LAE 5 7 5 3 4 Misaligned Operands 5 8 5 4 Data Transfer Operations a 5 8 5 4 1 Read CY CIOS 5 8 5 4 2 Write CV CIOS ae nd C ER 5 11 5 4 3 Indivisible Read Modify Write Sequence 5 13 5 5 Operand Transfer 5 15 5 5 1 Byte Operand to 8 Bit Port 5 16 5 5 2 Byte Operand to 16 Bit Port Even ADDRO 0 5 17 MOTOROLA SIM iv REFERENCE MANUAL TABLE OF CONTENTS Continued Paragraph Title Page 5 5 3 Byte Operand to 16 Port Odd ADDRO 1 5 17 5 5 4 Word to 8 Bit Port Aligned 5 18 5 5 5 Word Operand to 8 Bit Port Misaligned 5 18 5 5 6 Word Operand to 16 Bit Port Aligned 5 19 5 5 7 Word Operand t
50. Out Valid to DS CS Asserted Write Late BERR HALT Asserted to Clock Low Setup Time AS DS Negated to DSACK BERR HALT AVEC Negated R W Width Asserted Write or Read Asynchronous Input Setup Time tAIST BR BGACK DSACK BERR AVEC HALT DSACK Asserted to BERR HALT Asserted tDABA Data Out Hold from Clock High tpocH Clock High to Data Out High Impedance tcHDH BKPT Input Setup Time tekst BKPT Input Hold Time tBkHT NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 5 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles 10 In the absence of DSACK BERR is an asynchronous input using the asynchronous setup time specification 47A 14 RMC signal is not supported on CPU16 based MCUs MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 12 REFERENCE MANUAL 50 541 542 543 50 51 52 DE ADDR 23 0 Gi START OF amp SHOW CYCLE gt lt RNALCYCLE gt
51. The 8 bit peripheral transfers OPO to the specified address then asserts DSACKO to indicate that the first byte of word data has been received The MCU then decrements the transfer size counter increments the address and transfers OP1 to the upper byte of the data bus for the second cycle of the transfer a byte write to an 8 bit port For both reads and writes refer to 5 5 1 Byte Operand to 8 Bit Port for details on the second cycle of the data transfer 5 5 6 Word Operand to 16 Bit Port Aligned To initiate a transfer the MCU places the desired address on the address bus and drives the size pins to indicate a word operand The MCU also drives the function code and R W pins to appropriate values 15 8 7 0 Operand 1 Data Bus 15 8 7 0 121 120 ADDRO DSACK1 DSACKO Cycle 1 OPO OP1 1 0 0 0 1 Figure 5 13 Word Operand to 16 Bit Port Aligned For a read operation the peripheral responds by placing OPO on DATA 15 8 and OP1 on DATA 7 0 then asserts 1 to indicate a 16 bit port When DSACK1 is as serted the MCU reads DATA 15 0 and terminates the cycle SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 19 For a write operation the MCU drives the word operand on DATA 15 0 The periph eral device then reads the entire operand from DATA 15 0 and asserts DSACK1 to terminate the bus cycle 5 5 7 Word Operand to 16 Bit Port Misaligned To initiate a transfer the MCU places the desired ad
52. additional information SLOCK Synthesizer Lock 0 VCO is enabled but has not locked 1 VCO has locked on the desired frequency or system clock is external RSTEN Reset Enable 0 Loss of clock causes the MCU to operate in limp mode 1 Loss of clock causes system reset Refer to 4 7 Loss of Reference Signal for additional information STSIM Stop Mode SIM Clock 0 SIM clock driven by the external reference signal and the VCO is turned off dur ing low power stop 1 SIM clock driven by VCO during low power stop This bit has an effect only if the PLL is configured to supply the clock signal MODCLK held high during reset 4 6 Low Power Stop Operation has additional information SIM SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 13 STEXT Stop Mode External Clock 0 held low during low power stop 1 CLKOUT driven from SIM clock during low power stop Refer to 4 6 Low Power Stop Operation for additional information MOTOROLA SYSTEM CLOCK SIM 4 14 REFERENCE MANUAL SECTION 5 EXTERNAL BUS INTERFACE The external bus interface EBI transfers information between the internal MCU bus and external devices The external bus has 24 address lines and 16 data lines NOTE On 16 bit MCUs 19 0 are normal address outputs and AD DR 23 20 follow the output state of ADDR19 A three line handshaking interface performs external bus arbitration The interface supports byte word and long word transfe
53. be terminated by a data and size acknowledge DSACK signal or by an autovector AVEC signal The value of the DSACK field in the associated chip select option register determines whether DSACK is generated internally If it is the DSACK field determines the num ber of wait states inserted before internal DSACK assertion SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 9 A wait state has a duration of one clock cycle The wait states are inserted beginning with S3 of the external bus cycle An encoding of zero wait states corresponds to a three clock cycle bus Fast termination encoding corresponds to a two clock cycle bus access MCU mod ules typically respond at this rate the fast termination encoding is used to access fast external devices With fast termination encoding the bus cycle can be terminated at S3 Refer to 7 7 Fast Termination Cycles Cycles are terminated by the first DSACK signal that occurs If an external DSACK sig nal occurs during internal wait state generation the bus cycle terminates immediately If the externally generated acknowledge option is selected the MCU waits indefinitely for external DSACK assertion If multiple chip selects are to be used to provide control signals to a single device and match conditions can occur simultaneously all of the associated DSACK fields should be programmed for the same number of wait states Alternately all but one of the as sociated DSACK fields can be p
54. bus arbitration protocol supports operand coherency When an operand transfer requires multiple bus cycles the MCU does not release the bus until the entire transfer is complete The assertion of bus grant is subject to the following constraints The minimum time for BG assertion after BR assertion depends on internal syn chronization as specified in APPENDIX A ELECTRICAL CHARACTERISTICS During an external transfer the MCU does not assert BG until after the last cycle of the transfer determined by SIZ 1 0 and DSACK 1 0 signals MOTOROLA EXTERNAL BUS INTERFACE SIM 5 48 REFERENCE MANUAL During an external transfer the MCU does not assert BG as long as is as serted When SHEN bits are both set and the CPU is making internal accesses the MCU does not assert BG until the CPU finishes the internal transfers When a device is granted the bus and asserts BGACK it must also negate BR If BR remains asserted after assertion of BGACK the MCU assumes that another device is requesting the bus and prepares to assert BG again Externally the BG signal can be routed through a daisy chained network or a priority encoded network The MCU is not affected by the method of arbitration as long as the protocol is obeyed 5 10 3 Bus Grant Acknowledge When bus protocols are obeyed a device becomes the active bus master when it as serts BGACK An external device cannot request and be granted the bus while another device is
55. connected to CS0 as the upper byte and the bank connected to CS1 as the lower byte R W 9611 This configures the memory for both reads and writes STRB 0 This causes the chip select to be asserted with AS DSACK 960000 This causes DSACK signals to be generated internally by the SIM chip select circuitry with zero wait states inserted SPACE 11 This selects the memory for both supervisor and user access IPL AVEC 950000 Since the chip selects not being used during interrupt ac knowledge cycles the interrupt fields are set to zeros 7 11 2 Configuring the Boot ROM Chip Select The following paragraphs describe the configuration of the boot ROM chip select in Figure 7 5 7 11 2 1 Pin Connections The boot ROM chip is connected to CSBOOT ADDR 16 1 are connected to AD DR 15 0 of the ROM chip ADDRO of the MCU is not connected to the ROM in this example As with the RAM chips no DSACK lines are connected since the chip selects are con figured to generate DSACK signals internally No function code lines are connected in this example chip select logic is used to specify supervisor user space 7 11 2 2 Base Address Register CSBARBT comes out of reset with a base address of 000000 and a block size of 1 Mbyte The register is reassigned this value CSBARBT 0003 This selects a block size of 128 Kbytes starting at address 000000 7 11 2 3 Option Registers The option register CSORBT is reprogr
56. contains seven two bit fields that determine the functions of corresponding chip select pins CSPARO 15 14 are not used These bits always read zero writes have no effect CSPARO bit 1 always reads one writes to CSPARO bit 1 have no ef fect Table B 4 CSPARO Pin Assignments CSPARO Field Chip Select Signal Alternate Signal Discrete Output CSPAO 6 CS5 FC2 PC2 CSPAO 5 54 1 1 CSPA0 4 CS3 FC0 PC0 52 CSPAQ 2 CS1 BG CSPAQ 1 50 BR CSBOOT CSBOOT CSPAR1 Chip Select Pin Assignment Register 1 1HHHIAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CSPA1 4 CSPA1 3 CSPA1 2 CSPA1 1 CSPA1 0 RESET 0 0 0 0 0 0 1 DATA6 1 DATA5 1 DATA4 1 DATA3 1 CSPARI1 contains five two bit fields that determine the functions of corresponding chip select pins CSPAR1 15 10 are not used These bits always read zero writes have no effect Table B 5 CSPAR1 Pin Assignments CSPARO0 Field Chip Select Signal Alternate Signal Discrete Output CSPA1 4 CS10 ADDR23 ECLK CSPA1 3 CS9 ADDR22 PC6 CSPA1 2 CS8 ADDR21 PC5 CSPA1 1 CS7 ADDR20 PC4 CSPA1 0 CS6 ADDR19 PC3 SIM MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 9 Table B 6 Pin Assignment Encodings Bit Field Description 00 Discrete Output 01
57. dip in current will occur This dip is not sharp as in many LC circuits but is rather very broad As the shape of this curve suggests the exact value of is not critical Finally verify that the maximum operating supply voltage does not overdrive the crys tal Observe the output frequency as a function of Vppsyn at the buffered CLKOUT output with the device powered up in reset Under proper operating conditions the fre quency should increase a few parts per million as supply voltage increases If the crys tal is overdriven an increase in supply voltage will cause a decrease in frequency or the frequency will become unstable If frequency problems arise supply voltage must be decreased or the values of Rs and the two capacitors should be increased to re duce the crystal drive 4 3 3 Conditioning the Vppsyn and Vssi Pins SIM The VppsvN and Vssi input lines should be made as free of noise as possible Noise on these lines will cause frequency shifts in CLKOUT Guard ring the XFC line with VppsyN and guard ring Vppsyn with wherever possible The XFC filter capacitor and the Vppsyn bypass capacitors should be kept as close to the XFC and VDDSYN pins as possible with no digital logic coupling to either XFC or VppsvN The ground for the VppsvN bypass capacitors should be tied directly to the Vss ground plane If possible route Vppsyn and Vssi as separate supply runs or planes VDDSYN may require an inductive or
58. for a single device EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 47 MCU GRANT BUS ARBITRATION REQUESTING DEVICE REQUEST THE BUS 1 ASSERT BUS GRANT BG 1 ASSERT BUS REQUEST BR ACKNOWLEDGE BUS MASTERSHIP 1 EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2 NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3 NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER TERMINATE ARBITRATION 4 BUS MASTER NEGATES BR 1 NEGATE BG AND WAIT FOR BGACK TO BE NEGATED OPERATE AS BUS MASTER 1 PERFORM DATA TRANSFERS READ AND WRITE CYCLES ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP RE ARBITRATE OR RESUME PROCESSOR OPERATION 1 NEGATE BGACK Figure 5 36 Bus Arbitration Flow Chart for Single Request BUS ARB FLOW 5 10 1 Bus Request External devices capable of becoming bus masters request the bus by asserting the BR signal In a system with a number of devices capable of bus mastership a wired OR connection can connect the bus request line from each device to the MCU After it has completed the current operand transfer the MCU asserts BG then releases the bus when is asserted If no acknowledge signal is received the MCU remains bus master This prevents in terference with ordinary processing if the arbitration circuitry responds to noise or if an external device negates a request after mastership has been granted 5 10 2 Bus Grant The
59. function code and address lines and supply the interrupt acknowledge signal Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles MCU INTERRUPT ACKNOWLEDGED ACKNOWLEDGE e INTERRUPTING DEVICE AND GLUE LOGIC VECTOR NUMBER BUS TIME OUT CIRCUITRY Figure 6 4 External Connections for Interrupt Processing IACK CONN 6 4 2 Bus Cycle Terminated by AVEC Signal An external interrupting device requests an automatically generated vector autovec tor by asserting the AVEC signal to terminate an interrupt acknowledge cycle DSACK signals must not be asserted during an interrupt acknowledge cycle terminated by AVEC If the AVEC pin is permanently wired low asserted the CPU generates an au tovector whenever an interrupt of any priority from any external source is acknowl edged When AVEC is asserted the CPU ignores the state of the data bus and generates a vector number Refer to the appropriate CPU manual for information on determining the vector number and vector address Seven autovectors are available one for each of the seven interrupt request signals Figure 6 5 shows the timing for an autovector operation MOTOROLA INTERRUPTS SIM 6 6 REFERENCE MANUAL Chip select logic can be programmed to decode this bus cycle and generate inter nal AVEC response when an external interrupt request is made The interrupting de v
60. option data strobe is asserted only in a read cycle and not in a write cycle The STRB field in the chip select option register used must be programmed to address strobe in order to assert the chip select during a fast termina tion write cycle Figure 7 3 shows the DSACK timing for a read cycle with two wait states followed by a fast termination read cycle and a fast termination write cycle SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 11 S0 51 S2 S3 SW SW SW SW S4 S5 SO 51 54 S5 SO S1 54 S5 SO CLKOUT r TWO WAIT STATES IN READ FAST gt lt _ FAST gt TERMINATION TERMINATION READ WRITE DSACK only internally asserted for fast termination FAST TERM TIM Figure 7 3 Fast Termination Timing 7 7 1 Fast Termination Read Cycle A fast termination read cycle takes place in much the same way as a regular read cy cle except that the clock states for external handshaking are omitted State 0 50 The read cycle starts The CPU places an address on ADDR 23 0 and function codes on FC 2 0 The CPU drives R W high for a read cycle Size signals SIZ 1 0 become valid indicating the number of bytes to be read State 1 S1 The CPU asserts AS indicating that the address on the address bus is valid The CPU also asserts DS indicating to external devices that data can be placed on the data bus SIM chip select logic decodes the appropriate address lines FC 1 0 RAN
61. reference frequency is divided by 128 before it is passed to the PLL system The system clock frequency is determined by SYNCR bit settings as follows F meg 1 x The internal VCO frequency is twice the system clock frequency if X 1 or four times the system clock frequency if X 0 The reset state of SYNCR 3F00 produces a modulus 64 count 4 4 3 Avoiding Frequency Overshoot When the W and Y fields in the SYNCR are changed to increase the operating fre quency a frequency overshoot of up to 30 can occur This overshoot can be avoided by following these procedures 1 Determine the values for the W and Y fields which will result in the desired fre quency when the X bit is set 2 With the X bit cleared write these values for the W and Y fields to the SYNCR 3 After the VCO locks set the X bit in the SYNCR This changes the clock fre quency to the desired frequency For example follow these procedures to change the clock frequency from 8 to 13 MHz after reset using a 32 768 kHz crystal 1 Determine the values for the W and Y fields W 960 Y 2 96110100 2 Clear the X bit 3 Write the values to the SYNCR W 960 Y 96110100 4 When the VCO locks set the X bit 4 4 4 Frequency Control Tables Table 4 1 shows how to compute system clock frequency for various combinations of SYNCR bits Table 4 2 shows actual clock frequencies for the same combinations of SYNCR bits The frequencies i
62. resistive filter to control supply noise Figure 4 4 shows the external circuit for the XFC and Vppsyn pins SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 5 VDDSYN 0 1uF 0 1uF 01 MCU PINS VDDSYN VSSI Must be low leakage capacitor insulation resistance 30 000 or greater XFC VDDSYN CONN Figure 4 4 Conditioning the and Vppsyn Pins A Vppsyn resistive filter would consist of a 100 to 500 ohm resistor from Vpp to VDDSYN and a 0 1 uF bypass capacitor from Vppsyn to Vss The proper values for the resistor and capacitor can be determined by examining the frequency of the VDDSYN noise The RC time constant needs to be large enough to filter the supply noise An inductive filter would replace the resistor with an inductor The low pass filter requires an external low leakage capacitor 0 polypropylene typically 0 1 with an insulation resistance specification of 30 000 or greater connected between the XFC and Vppsyn pins 4 4 System Clock Frequency Control When the clock synthesizer is used bits 15 8 of the synthesizer control register SYNCR determine the operating frequency The W bit controls a prescaler tap in the synthesizer feedback loop The Y field determines the modulus for a modulo down counter Y contains a value from 0 to 63 input to the modulo counter is divided by a value of Y 1 Both W and Y affect the value of the feedback divider input to the VCO Conse
63. responds by placing on DATA 7 0 and as serting DSACK1 to indicate a 16 bit port When DSACK1 is asserted the MCU reads from DATA 7 0 decrements the transfer size counter increments the address and waits for the peripheral to place OP1 on the upper byte of the data bus during the second cycle of the transfer a byte read of an 8 bit port When the second cycle is finished one misaligned word has been read The MCU then reads a second mis aligned word OP2 and OP3 from the 16 bit port during the third and fourth cycles of the transfer For a write operation the MCU first drives OPO on DATA 7 0 and duplicates it on DA TA 15 8 The peripheral device reads from DATA 7 0 and asserts DSACK1 The MCU decrements the transfer size counter increments the address and places OP1 on both bytes of the data bus during the second cycle of the transfer When the second cycle is finished one misaligned word has been written The MCU then writes a sec ond misaligned word OP2 and OP3 to the 16 bit port during the third and fourth cy cles of the transfer 5 6 Function Codes and Memory Usage The CPU generates function code output signals FC 2 0 to indicate the type of activity occurring on the data or address bus These signals can be considered address ex tensions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle Address space 7 is designated CPU space CPU sp
64. so that the address comparator checks address lines ADDR 19 16 against the corresponding bits in the base address register The CPU places the CPU space type on AD DR 19 16 3 Program the chip select options register as follows Program MODE to zero to emulate asynchronous bus cycles e Set the RAN field to read write Program the BYTE field to both bytes Program STRB to synchronize with AS Program the DSACK field to any value When the AVEC bit is set fast termi nation is automatically selected Program IPL to respond to the desired interrupt request level or to 95000 to respond to all request levels Program the AVEC bit to 1 to enable autovector generation 7 9 Chip Select Reset Operation Chip select pin assignment at reset and the reset values in the base and option regis ters are discussed in the following paragraphs SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 15 7 9 1 Pin Assignment Out of reset chip select pin functions are determined by the logic levels on pins DA TA 7 0 Data pins have weak internal pull up drivers but external devices can hold the pins low Refer to SECTION 8 RESET AND SYSTEM INITIALIZATION for sug gestions for holding pins low during reset and to APPENDIX A ELECTRICAL CHAR ACTERISTICS for drive requirements The least significant bit of each of the 2 bit CS 10 0 pin assignment fields in CSPARO and CSPAR1 has a reset value of one The reset value of the most signif
65. some MCUs ADDR 23 20 follow the state of ADDR19 and DATA 7 4 have limited use Refer to 7 9 Chip Select Reset Operation for more information DATAS determines the function of the DSACKO DSACK1 AVEC DS AS and SIZ 1 0 pins If DATAS is held low during reset these pins are used for discrete port E determines the function of interrupt request pins IRQ 7 0 and the clock mode select pin MODCLK When DATAS is held low during reset these pins are used for discrete port F DATA11 determines whether the SIM operates in test mode out of reset This capabil ity is used for factory testing of the MCU 2 Holding Data Bus Pins Low at Reset To avoid conflicts on the data bus during reset use an active device to hold data bus lines low The data bus configuration logic must be released prior to the first bus cycle after reset in order to prevent conflict with external memory devices The first bus cycle occurs 14 CLKOUT cycles after RESET is released If external mode selection logic causes a conflict with external memory devices an isolation resistor on the driven lines may be required Figure 8 4 shows a recommended method for conditioning data bus pins that are held low at reset RESET AND SYSTEM INITIALIZATION MOTOROLA REFERENCE MANUAL 8 9 lt DATA15 o gt MODE SELECT LINES lt UN DATAO M VDD VDD RESE
66. space for the chip select circuit to respond to interrupt acknowledge cycles Table 7 1 is a summary of option register functions Table 7 1 Option Register Function Summary MODE BYTE R W STRB DSACK SPACE IPL AVEC 0 Async 00 Disable 00 Rsvd 0 AS 0000 0 wait states 00 CPU 000 All 0 Off 1 Sync 01 Lower 01 Read 1 DS 0001 1 wait state 01 User 001 Level 1 1 10 Upper 10 Write 0010 2 wait states 10 Supv 010 Level 2 11 Both 11 Both 0011 3 wait states 11 S U 011 Level 0100 4 wait states 100 Level 4 0101 5 wait states 101 2 Level 5 0110 6 wait states 110 2 Level 6 0111 7 wait states 111 2 Level 7 1000 8 wait states 1001 9 wait states 1010 10 wait states 1011 2 11 wait states 1100 12 wait states 1101 13 wait states 1110 Fast terminate 1111 External Use this value when function is not required for chip select operation For additional information on the MODE and STRB fields refer to 7 5 Chip Select Timing For more information on the BYTE field refer to 7 6 Chip Selects and Dy namic Bus Sizing For information on the DSACK field see 7 5 Chip Select Timing and 7 7 Fast Termination Cycles For details on the IPL AVEC and SPACE fields refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles Diagrams of the chip select option registers are provided in 7 10 Chip Select Register Dia
67. to 8 Bit Port For an eight bit port consecutive bytes of data can be read from and written to con secutive byte addresses in the memory system To initiate a transfer the MCU places the desired address on the address bus and drives the size pins to indicate a single byte operand Since bytes of data can be written to either odd or even addresses ADDRO can be either zero or one The MCU also drives the function code and R W pins to appropriate values 7 0 Operand OP0 Data Bus 15 8 7 0 SIZ1 5120 ADDRO DSACK1 DSACKO Cycle 1 OPO 0 1 X 1 0 Figure 5 8 Byte Operand to 8 Bit Port MOTOROLA EXTERNAL BUS INTERFACE SIM 5 16 REFERENCE MANUAL For a read operation the 8 bit peripheral responds by placing on DATA 15 8 and asserting DSACKO The MCU reads from DATA 15 8 and ignores DATA 7 0 For a write operation the MCU drives OPO on both bytes of the data bus The periph eral determines the operand size and transfers the data from the upper byte of the data bus to the specified address then asserts DSACKO to terminate the bus cycle 5 5 2 Byte Operand to 16 Bit Port Even ADDRO 0 To initiate a transfer the MCU places the desired address on the address bus and drives the size pins to indicate a single byte operand The MCU also drives the func tion code and R W pins to appropriate values 7 0 Operand Data Bus 15 8 7 0 5121 5120 ADDRO DSACK1 DSACKO Cycle 1 OPO 0 1
68. to R W Low lcHRL 0 29 ns 21 R W High to AS CS Asserted tRAAA 15 ns 22 R W Low to DS CS Asserted Write 70 ns 23 Clock High to Data Out Valid tcHDo 29 ns 24 Data Out Valid to Negating Edge of AS CS DVASN 15 ns 25 DS CS Negated to Data Out Invalid Data Out Hold lsNDOI 15 ns 26 Data Out Valid to DS CS Asserted Write tpvsa 15 ns 27 Data In Valid to Clock Low Data Setup tpicL 5 ns 27A Late BERR HALT Asserted to Clock Low Setup Time tBELCL 20 ns 28 AS DS Negated to DSACK BERR HALT AVEC Negated tsnNDN 0 80 ns 29 05 CS Negated to Data In Invalid Data In Hold teNDI 0 ns 2946 7 05 CS Negated to Data In High Impedance 55 ns 306 CLKOUT Low to Data In Invalid Fast Cycle Hold tci DI 15 ns 30A5 CLKOUT Low to Data In High Impedance 90 ns 318 DSACK Asserted to Data In Valid 50 ns 33 Clock Low to BG Asserted Negated CLBAN 29 ns 35 14 BR Asserted to BG Asserted Not Asserted BRAGA 1 37 Asserted to Negated GAGN 1 2 39 Width Negated tau 2 39A BG Width Asserted tea 1 46 R W Width Asserted Write Read 150 m ns 46A R W Width Asserted Fast Write or Read Cycle tRwAS 90 ns MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 4 REFERENCE MANUAL Table A 3 AC Timing Vpp and VDDSYN 5 0 Vdc 10 Vss 0 Vdo
69. 0 0 1 Figure 5 9 Byte Operand to 16 Bit Port Even ADDRO 0 For a read operation the 16 bit peripheral responds by placing OPO on DATA 15 8 and asserting DSACK1 The MCU reads the data from DATA 15 8 and ignores DA 7 0 For a write operation the drives onto both bytes of the data bus The pe ripheral determines operand size and transfers the data from the upper byte of the data bus to the specified address then asserts DSACK1 to terminate the bus cycle In order to read or write to individual bytes of a 16 bit memory the memory must con sist of 8 bit banks with individual chip selects Refer to 5 7 System Interfacing Exam ples for a description of such a configuration 5 5 3 Byte Operand to 16 Bit Port Odd ADDRO 1 To initiate a transfer the MCU places the desired address on the address bus and drives the size pins to indicate a single byte operand The MCU also drives the func tion code and R W pins to appropriate values 7 0 Operand Data Bus 15 8 7 0 121 120 ADDRO DSACK1 DSACKO Cycle 1 OPO 0 1 1 0 1 Figure 5 10 Byte Operand to 16 Bit Port Odd ADDRO 1 SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 17 For a read operation the 16 bit peripheral responds to the address and size signals by placing OP0 on DATA 7 0 and asserting DSACK1 The MCU then reads the data from DATA 7 0 and ignores DATA 15 8 For a write operation the M
70. 00 5374 10748 21496 42992 101001 5505 11010 22020 44040 101010 5636 11272 22544 45089 MOTOROLA SYSTEM CLOCK SIM 4 10 REFERENCE MANUAL Table 4 2 System Frequencies from Typical 32 768 kHz or 4 194 MHz Reference Continued To obtain the clock frequency find the counter modulus in the leftmost column then look in the appropriate prescaler cell Values are in kilohertz Shaded cells represent values that exceed maximum system frequency specification Modulus Prescaler Y W X 00 W X 01 W X 10 W X 11 101011 5767 11534 23069 46137 101100 5898 11796 23593 47186 101101 6029 12059 24117 48234 101110 6160 12321 24642 49283 101111 6291 12583 25166 50332 110000 6423 12845 25690 51380 110001 6554 13107 26214 52428 110010 6685 13369 26739 53477 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 110101 7078 14156 28312 56623 110110 7209 14418 28836 57672 110111 7340 14680 29360 58720 111000 7471 14942 2988 59769 111001 7602 15204 30409 60817 111010 7733 15466 30933 61866 111011 7864 15729 31457 62915 111100 7995 15991 31982 63963 111101 8126 16253 32506 65011 111110 8258 16515 33030 66060 111111 8389 16777 33554 67109 4 5 External Bus Clock The state of the external clock division bit EDIV in the SYNCR determines the clock rate for the external bus clock signal ECLK available on pin ADDR23 ECLK is a bus clock for MC6800 devices an
71. 00 to respond to all request levels Program the AVEC bit to 0 to disable autovector generation Generating an autovector signal with chip selects is described in the following subsection 7 8 2 Generating an Autovector Signal with a Chip Select Circuit If the AVEC bit in the chip select option register is set to one chip select circuitry gen erates an internal automatic vector signal in response to an interrupt acknowledge cy cle initiated by an IRQ pin provided the match conditions in the base address and option registers are met The AVEC signal causes the CPU to use a predetermined set of vectors to service the interrupt If the AVEC bit is set to zero the device requesting interrupt service must either assert the AVEC pin or supply the vector and terminate the cycle by asserting DSACK The AVEC bit must not be set when the MODE bit is set chip select assertion syn chronized to ECLK since autovector response timing can vary due to ECLK synchro nization To generate an autovector signal with a chip select circuit follow these steps 1 For most applications program the appropriate chip select pin assignment reg ister to configure the pin for either discrete output or its alternate function This prevents the pin from being asserted during interrupt acknowledge cycles 2 In the base address register program the base address field bits 15 3 to all ones Program the block size to no more than 64 Kbytes
72. 148 296 592 1184 100101 152 304 608 1216 100110 156 312 624 1248 100111 160 320 640 1280 101000 164 328 656 1312 101001 168 336 672 1344 101010 172 344 688 1376 101011 176 352 704 1408 MOTOROLA SYSTEM CLOCK SIM 4 8 REFERENCE MANUAL Table 4 1 Clock Control Multipliers Continued To obtain the clock frequency find the counter modulus in the leftmost column then multiply the reference frequency by the value in the appropriate prescaler cell For 4 194 MHz reference crystals first divide by 128 Shaded cells contain values that exceed specifications Modulus Prescalers Y W X 00 W X 01 W X 10 W X 11 101100 180 360 720 1440 101101 184 368 736 1472 101110 188 376 752 1504 101111 192 384 768 1536 110000 196 392 784 1568 110001 200 400 800 1600 110010 204 408 816 1632 110011 208 416 832 1664 110100 212 424 848 1696 110101 216 432 864 1728 110110 220 440 880 1760 110111 224 448 896 1792 111000 228 456 912 1824 111001 232 464 928 1856 111010 236 472 944 1888 111011 240 480 960 1920 111100 244 488 976 1952 111101 248 496 992 1984 111110 252 504 1008 2016 111111 256 512 1024 2048 SIM SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 9 Table 4 2 System Frequencies from Typical 32 768 kHz or 4 194 MHz Reference To obtain the clock frequency find the counter modulus in the leftmost column then look in the appropriate prescaler cell Valu
73. 2 2 SIM Signal CH aracterIStIes uuu usu u una ulna p A RES 2 3 SIM Signal Function ett Dc 2 4 B s Montor Period 3 5 MODCLK Pin and SWP Bit During Reset 3 6 Software Watchdog 3 6 MODCLK Pin and Bit During 22 2 221 1 3 7 Periodic Interrupt Priority aec sc ue 3 9 Glock Control Multpliers dio roS Ee ertet Laus 4 8 System Frequencies from Typical 32 768 kHz or 4 194 MHz Reference 4 10 OCI OO cas des ku SE A ACE 4 12 Size Signal Encoding ss eb unie bee ratito bea bela 5 6 DSACK Signal Encodings e ERI 5 7 Operand Transler Gases ex A veneer sista RES E tated 5 16 Address Space EMCOdling secu s suu o Eee e fece itus 5 28 DSACK BERR and HALT Assertion Results 5 39 Bus Arbitration Pin State 5 50 Option Register Function Summary 7 3 Block Size Encoding Munere pibe st en REP 7 4 Chip Select Pin Functions 7 5 Pin Assig
74. 2 CS9 ADDR21 CS8 ADDR20 CS7 ADDR19 CS6 FC2 CS5 FC1 CS4 FC0 CS3 BGACK CS2 gt BG CS1 BR CS0 PORT C ADDR 18 0 5121 5170 AS CONTROL PORTE z gt gt lt a gt 9 yn gt OJ gt e SIM CONTROL MODCLK MODCLK CLKOUT gt XTAL EXTAL CLOCK TSTME TSC TSTME TSC TEST QUOT CONTROL Y m m m N m 9 FREEZE FROM CPU SS SSS mpm femen S fme immi reir emu Eu cer SS SS Em m me SS SSS SS SSS SSS ELEM kus SS ia SS SS Ei Ee Re SIM PINOUT Figure 1 2 SIM Input and Output Signals SIM INTRODUCTION MOTOROLA REFERENCE MANUAL 1 3 1 1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping MM bit in the SIM module configuration reg ister SIMCR determines where the control register block is located in the system memory map When MM is equal to zero register addresses range from 7FF000 to 7FFFFF When 1 register addresses range from FFF000 to FFFFFF CAUTION On CPU16 based MCUs ADDR 23 20 follow the logic state of ADDR 19 unless externally driven If MM is cleared on these MCUs the SIM maps IMB modules into an address space which is inacces sible to the CPU Modules remain inaccessible until reset occurs The reset stat
75. 4 and breakpoints 5 33 BG 5 48 5 51 5 52 BGACK 5 47 5 49 BKPT 5 33 8 10 BLKSZ 7 19 Block diagram reset 8 2 SIM 1 2 system configuration and protection 3 1 Block size BLKSZ 7 19 BME 3 5 3 11 BMT 3 5 3 12 BR 5 47 5 48 5 49 Breakpoints acknowledge cycle 5 32 hardware 5 33 mode selection 8 10 signal BKPT 5 33 8 10 software 5 33 Bus arbitration 5 48 5 50 control 5 50 timing diagrams A 15 A 17 cycles CPU space 5 31 external 5 4 SIM REFERENCE MANUAL INDEX interrupt acknowledge 6 3 read 5 8 write 5 11 error double bus fault 5 42 exceptions 5 40 processing 5 38 grant BG 5 48 5 51 5 52 acknowledge BGACK 5 47 5 49 intermodule 1 1 master 5 48 5 49 monitor 3 5 external enable BME 3 5 3 11 timing BMT 3 5 3 12 request BR 5 47 5 48 5 49 BYTE field 7 2 7 6 7 10 7 20 Byte transfer 16 bit port 5 17 5 18 8 bit port 5 16 Chip selects 7 1 asynchronous emulation 7 9 base address 7 3 registers 7 17 7 19 boot CSBOOT 7 17 dynamic bus sizing 7 10 interfacing example 7 22 enabling 7 6 fast termination 7 11 interrupt acknowledge cycles 7 13 operation 7 6 option registers 7 2 7 16 7 19 CSOR 10 0 7 19 CSORBT 7 19 pin assignment registers 7 16 7 17 CSPARO 7 18 CSPAR 1 7 18 register diagrams 7 17 reset operation 7 15 timing 7 9 diagram A 24 wait states 7 10 CLKOUT 3 3 and resets 7 5 output timing diagram A 7 synchronization to 5 5 Clock system 4 1 control mul
76. 5 3 Dynamic Bus Sizing The remaining address lines are decoded to select the peripheral and address within the peripheral When AS DS and R W are valid a peripheral device either places data on the bus during a read cycle or latches data from the bus during a write cycle then asserts the appropriate DSACK signal to indicate port size DSACK signals can be asserted before the data from a peripheral device is valid on a read cycle To ensure that valid data is latched into the MCU a maximum period be tween DSACK assertion and DS assertion is specified Refer to Table A 3 in APPEN DIX A ELECTRICAL CHARACTERISTICS MOTOROLA EXTERNAL BUS INTERFACE SIM 5 4 REFERENCE MANUAL There is no specified maximum for the period between AS assertion and DSACK as sertion Although the MCU can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK the MCU inserts wait cycles in clock period incre ments until either DSACK signal goes low NOTE The SIM bus monitor asserts BERR when response time exceeds a predetermined limit Bus monitor period is determined by the BMT field in the system protection control register SYPCR The bus mon itor cannot be disabled maximum monitor period is 64 system clock cycles If no peripheral responds to an access or if an access is invalid external logic should assert the BERR signal to abort the bus cycle If BERR or bus termination signals are not asserted within th
77. 6 1 Prescaler Modulus 3 6 2 Interrupt Priority and Vectoring 4444 2442222 3 7 Low Power Stop Operation Re Ee 3 8 System Protection Registers 2 22 3 8 1 Software Service Register SWSR 3 8 2 Periodic Interrupt Control Register PICR 3 8 3 Periodic Interrupt Timer Register 3 8 4 System Protection Register SYPCR SECTION 4 SYSTEM CLOCK 4 1 eT 4 1 1 Internal Phase Locked Loop 4 1 2 External Clock Signal 4 2 Glock Synthesizer ODOFGlIQP 4 3 External Circuit Design cee des cea ORA NIE SIM REFERENCE MANUAL MOTOROLA iii TABLE OF CONTENTS Continued Paragraph Title Page 4 3 1 Conditioning the XTAL and EXTAL Pins 4 4 4 3 2 Crystal Tune up Procedure 4 5 4 3 3 Conditioning the XFC and Vssi Pins 4 5 4 4 System Clock Frequency Control 4 6
78. 68300 SHW CYC TIM Figure A 6 Show Cycle Timing Diagram Table A 8 Key to Figure A 6 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Max Units 674 Clock High to Address FC SIZE RMC Valid tcHAV 0 29 ns 874 Clock High to Address FC SIZE RMC Invalid tcHazn 0 ns 9 Clock Low to AS DS CS Asserted ici SA 2 25 ns 12 ClockLowto AS DS CS 2 29 ms 155 5 DS CS Width Negated isn 40 ns 18 Clock High to R W High tcHRH 0 29 ns 20 High to RW Low tcunL 0 29 ns 70 Low to Data Bus Driven Show tecLDD 0 29 ns 71 Data Setup Time to Clock Low Show teci ps 15 ns 72 Data Hold from Clock Low Show taw 10 ms 73 BKPT Input Setup Time tBksT 15 ns 74 BKPT Input Hold Time 10 ns NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 5 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles 14 RMC signal is not supported on CPU16 based MCUs SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 13
79. 8 This minimizes the number of bus cycles needed to transfer data and ensures that the MCU transfers val id data SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 7 5 3 The largest amount of data that be transferred by a single bus cycle is an aligned word If the MCU transfers a long word operand via a 16 bit port the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle 4 Misaligned Operands For external bus cycles the basic operand size of both the CPU16 and CPUS2 pro cessors is 16 bits An operand is misaligned when it overlaps a word boundary When ADDRO 0 indicating an even address the address is on a word and byte boundary When ADDRO 1 indicating an odd address the address is a byte boundary only A byte operand is aligned at any address a word or long word operand is misaligned at an odd address NOTE The CPU16 can perform misaligned word transfers This capability makes it compatible with the M68HC11 CPU The CPU16 treats mis aligned long word transfers as two misaligned word transfers The CPU32 however does not support misaligned word transfers Refer to the user s manual for the specific MCU or CPU for additional infor mation 5 4 Data Transfer Operations The following paragraphs provide detailed descriptions of read and write bus cycles Following these descriptions is a discussion of the CPU32 indivisib
80. 9 To ensure coherency during every operand transfer BG will not be asserted in response to BR until after all cy cles of the current operand transfer are complete and RMC is negated SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 17 50 51 54 55 50 He 68300 FAST RD Figure 10 Fast Termination Read Cycle Timing Diagram MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 18 REFERENCE MANUAL Table A 12 Key to Figure A 10 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Max Units 674 Clock High to Address FC SIZE RMC Valid tcHav 0 29 ns 874 Clock High to Address FC SIZE RMC Invalid tcHazn 0 ns 9 Clock Low to AS DS CS Asserted tci SA 2 25 ns 12 Clock Low to AS DS CS Negated teLsn 2 29 ns 14B 5 CS Width Asserted tswow 40 ns 18 Clock High to R W High CHRH 0 29 ns 20 Clock High to RW Low 0 29 ns 27 Data In Valid to Clock Low Data Setup tpicL 5 ns 306 CLKOUT Low to Data In Invalid tci pI 15 ns 30A5 CLKOUT Low to Data In High Impedance tci pH 90 ns 46A R W Width Asserted trwas 90 m ns 73 BKPTInputSetupTime 15 74 BKPT Input Hold Time tBkuT 10 ns NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 6
81. AL RESET EXTERNAL RESET NOT DRIVEN 12 CLOCK COUNTDOWN EXTERNAL EXTERNAL RESET NOT DRIVEN RESET ASSERTED EXTERNAL RESET ASSERTED YES FETCH RESET VECTOR AND RUN CODE UNTIL RESET IS ASSERTED FROM ANY SOURCE EXTERNAL RESET NOT DRIVEN CONTINUE RUNNING CODE UNTIL RESET IS ASSERTED FROM ANY SOURCE EXTERNAL RESET NOT DRIVEN SIM RESET FLOW Figure 8 2 Reset Control Flow SIM RESET AND SYSTEM INITIALIZATION MOTOROLA REFERENCE MANUAL 8 5 8 3 1 RESET Assertion by an External Device When an external device requests reset by asserting RESET for at least four CLKOUT Cycles reset control logic clocks the signal into an internal latch The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven to guarantee this length of reset to the entire system After 512 cycles have elapsed allowing the weak pull up devices on the data bus con figuration pins to pull the pins up to logic level one the RESET pin goes to a disabled high impedance state for 10 cycles At the end of this 10 cycle period the data bus pin configuration is latched and the state of the RESET pin is tested If the pin state is logic level one negated reset exception processing begins If however the pin state is logic level zero asserted the reset control logic drives the pin low for another 512 cycles on the assu
82. ATION MOTOROLA REFERENCE MANUAL 8 3 8 2 6 System Reset When the SYS bit in the RSR is set the most recent reset was caused by the CPU32 RESET instruction The CPU16 does not support this instruction This type of reset does not load a reset vector or affect CPU registers or SIM configuration registers but does assert the RESET line thus resetting external devices and internal modules oth er than the CPU Not all internal modules respond to system reset Refer to the refer ence manuals for the individual modules to determine how they respond to this instruction System reset thus allows software to reset the system to a known state and then continue processing with the next instruction Since the CPU32 is in control during a RESET instruction it is not normally necessary to read the RSR to determine the source of reset The SYS bit is provided however for the sake of completeness 8 2 7 Test Module Reset When the TST bit in the RSR is set the most recent reset was caused by the test sub module This condition occurs during system testing only 8 2 8 Reset Status Register The reset status register RSR contains a bit for each reset source in the MCU When a reset occurs a bit corresponding to the reset type is set When multiple causes of reset occur at the same time more than one bit in RSR may be set The reset status register is updated by the reset control logic when the RESET signal is released This register can be r
83. Asserted tAVSA 15 ns 12 Clock Low to AS DS CS Negated 2 29 ns 13 5 DS CS Negated to Address FC SIZE Invalid tsnal 15 ns Address Hold 14 5 CS Width Asserted tswa 100 ns 14 05 CS Width Asserted Write tswaw 45 ns 155 JAS DS CS Width Negated isn 40 ns 18 Clock High to R W High icHRH 0 29 ns 20 High to RW Low tcunL 0 29 ns 23 Clock High to Data Out Valid tcHDo 29 ns 25 05 CS Negated to Data Out Invalid Data Out Hold teNDOI 15 ns 29 DS CS Negated to Data In Invalid Data In Hold tsi 9 ns 29A 7 5 CS Negated to Data In High Impedance tsHDI 55 ns 46 R W Width Asserted Write or Read tRWA 150 ns 53 Data Out Hold from Clock High tpocH 0 ns 54 Clock High to Data Out High Impedance tcHDH 28 ns 55 R W Asserted to Data Bus Impedance Change tRapc 40 ns NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 5 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles N 14 RMC signal is not supported on CPU16 based MCUs SIM ELECTRICAL CHARACTERISTICS REFERENCE MANUAL These hold times are specifi
84. BOOT Table 7 8 CSBOOT Base and Option Register Reset Values Field Reset Value Base Address 000000 Block Size 1 Mbyte Timing Mode Emulates Asynchronous Bus Cycles Upper Lower Byte Both Bytes Read Write Read Write Strobe AS DS AS DSACK 13 Wait States Address Space Supervisor User Space IPL Any Level Autovector Interrupt Vector Externally Default block size is effectively 512 Kbyte on CPU16 based MCUs since values of ADDR 23 20 follow ADDR19 7 10 Chip Select Register Diagrams Chip select registers include two pin assignment registers two base address regis ters twelve option registers and a discrete output data register 7 10 1 Chip Select Pin Assignment Registers The pin assignment registers contain 12 two bit fields CS 10 0 and CSBOOT that determine the functions of the chip select pins Each pin has two or three possible functions as shown below Pins that have no discrete output function do not use the 9600 encoding Bit Field Description 00 Discrete Output 01 Alternate Function 10 Chip Select 8 Bit Port 11 Chip Select 16 Bit Port SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 17 On MCUs with a reduced pin count SIM some chip select pins may not be available Refer to the user s manual for the particular MCU for details Pin assignments at reset are determined by the states of the data bus pins indicated in the following register diagrams
85. CPU enters background debugging mode it suspends instruction execution and asserts the internal FREEZE signal The CPU enters background debugging mode if a breakpoint occurs while background mode is enabled Refer to the appropri ate CPU manual for a discussion of background debugging mode Two bits in the SIMCR determine how the SIM responds to FREEZE assertion Setting the freeze bus monitor FRZBM bit in the SIMCR disables the bus monitor when MOTOROLA SYSTEM CONFIGURATION AND PROTECTION SIM 3 2 REFERENCE MANUAL FREEZE is asserted Setting the freeze software watchdog FRZSW bit disables the software watchdog and the periodic interrupt timer when FREEZE is asserted If these bits are cleared when FREEZE is asserted the bus monitor software watchdog and periodic interrupt timer continue to operate normally FREEZE assertion has no affect on the halt monitor or spurious interrupt monitor they continue to operate normally 3 1 4 Interrupt Arbitration Priority Each module that can generate interrupts including the SIM has an IARB interrupt arbitration number field in its module configuration register Each IARB field has a dif ferent value During an interrupt acknowledge cycle IARB permits arbitration among simultaneous interrupts of the same priority level The reset value of IARB in the SIMCR is F This prevents SIM interrupts from being discarded Initialization software must set the IARB field to a lower value in the range
86. CU drives OPO on both bytes of the data bus The periph eral determines operand size and transfers OPO from the lower byte of the data bus to the specified address then asserts DSACK1 to terminate the bus cycle In order to read or write to individual bytes of a 16 bit memory the memory must be divided into 8 bit banks with individual chip selects Refer to 5 7 System Interfacing Examples for a description of such a configuration 5 5 4 Word Operand to 8 Bit Port Aligned To initiate a transfer the MCU places the desired address on the address bus and drives the size pins to indicate a word operand The MCU also drives the function code and R W pins to appropriate values 15 8 7 0 Operand OP0 OP1 Data Bus 15 8 7 0 121 120 ADDRO DSACK1 DSACKO Cycle 1 OPO OP1 1 0 0 1 0 Cycle 2 OP1 OP1 0 1 1 1 0 Figure 5 11 Word Operand to 8 Bit Port Aligned For a read operation the 8 bit peripheral responds to the address and size signals by placing on DATA 15 8 and asserting DSACKO The MCU reads from DA TA 15 8 and ignores DATA 7 0 then decrements the transfer size counter incre ments the address and waits for the peripheral to place OP1 on the upper byte of the data bus for the second cycle of the transfer a byte read of an 8 bit port For a write operation the MCU drives OPO on DATA 15 8 and OP1 on DATA 7 0 The 8 bit peripheral transfers OPO from DATA 15 8 to the specified address then as
87. DDR23 Refer to 7 5 Chip Select Timing for additional information 0 Emulate asynchronous bus operation 1 Synchronize chip select assertion to ECLK MOTOROLA MEMORY MAP AND REGISTERS SIM B 10 REFERENCE MANUAL Upper Lower Byte Option This field enables or disables the chip select circuit and for 16 bit ports determines which combinations of size and ADDRO pins will cause the chip select to be asserted Refer to 7 6 Chip Selects and Dynamic Bus Sizing for more information 00 Disable 01 Lower byte 10 Upper byte 11 Both Bytes R W Read Write This field causes a chip select to be asserted only for a read only for a write or for both read and write 00 Reserved 01 Read only 10 Write only 11 Read Write STRB Address Strobe Data Strobe The STRB bit controls the timing of a chip select assertion in asynchronous mode This bit has no effect in synchronous mode 0 Synchronize chip select assertion with address strobe 1 Synchronize chip select assertion with data strobe DSACK Data and Size Acknowledge This field specifies the source of DSACK when chip select cycles emulate asynchro nous bus cycles and controls wait state insertion Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles for details SPACE Address Space Select The SPACE field determines the address space in which a chip select is asserted An access must have the space type represented by SPACE encoding in ord
88. DS CS Negated to Data In High Impedance tsHDI 55 ns 318 DSACK Asserted to Data In Valid tDADI 50 ns 46 R W Width Asserted Write or Read 150 ns 47A Asynchronous Input Setup Time tAIST 5 ns BR BGACK DSACK BERR AVEC HALT 47B Input Hold Time 15 ES ns 4870 DSACK Asserted to BERR HALT Asserted 30 ns 73 BKPT Input Setup Time tekst 15 ns 74 BKPT Input Hold Time 10 ns NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 4 This is the worst case skew between AS and DS or CS The amount of skew depends on the relative loading of these signals When loads are kept within specified limits skew will not cause AS and DS to fall outside the limits shown in specification 9 5 If multiple chip selects are used CS width negated 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects used for ECLK cycles 6 These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on synchronous reads The user is free to use either hold time 7 Maximum value is equal to 2 25 ns 8 If the asynchronous setup time 47A requirements are satisfied the DSACK low to data setup time 31 and DSACK low
89. DSACK signal is recognized as asserted by the start of S3 the MCU inserts wait states instead of proceeding to S4 and S5 While wait states are added the MCU continues to sample the DSACK signals on falling edges of the clock until a change in one or more is recognized In effect S3 and S4 repeat until a change in the DSACK signals is detected State 4 S4 If a change in the DSACK signals is detected by the beginning of S3 the MCU latches data on the falling edge at the end of S4 If not S3 and S4 repeat until a change in the DSACK signals is detected State 5 S5 The MCU negates AS and DS but holds the address valid to provide address hold time for memory systems R W SIZ 1 0 and FC 2 0 also remain valid throughout S5 The external device must maintain data and assert the DSACK signals until it detects the negation of either AS or DS The external device must remove the data and negate DSACK within approximately one clock period after sensing the ne gation of AS or DS Signals that remain asserted beyond this limit can be prematurely detected during the next bus cycle Figure 5 3 is a timing diagram of a read cycle S0 52 54 50 lt READ gt RD MOD WR RD TIM Figure 5 3 Read Cycle Timing Diagram MOTOROLA EXTERNAL BUS INTERFACE SIM 5 10 REFERENCE MANUAL 5 4 2 Write Cycles During a write operation the MCU transfers data to an external memory or peripheral device
90. EASE 2 NEGATE AS AND DS 1 NEGATE DSACK START NEXT CYCLE IACK FLOW Figure 6 2 Interrupt Acknowledge Cycle Flowchart MOTOROLA INTERRUPTS SIM 6 4 REFERENCE MANUAL 6 4 1 Bus Cycle Terminated by DSACK Signals If an external device with a vector number register wins arbitration the device places the vector number on the data bus and asserts the appropriate DSACK signal to ter minate the interrupt acknowledge cycle The device must place its vector number on the least significant byte of its data port A device with an 8 bit port must drive the vec tor number on DATA 15 8 a device with a 16 bit port must drive the vector number on DATA 7 0 Figure 6 3 shows the timing for an interrupt acknowledge cycle terminated with DSACK S0 52 54 50 521 522 523 824 51 52 54 50 52 CLKOUT ADDR 23 4 X ADDR 8 1 X X INTERRUPT LEVEL X ADDR0 N FC 2 0 X N 5170 X N DSACK N N N VECTOR FROM 16 BIT PORT VECTOR FROM 8 BIT PORT lt READ gt lt INTERNAL gt lt WRITE CYCLE ARBITRATION STACK r INTERRUPT ACKNOWLEDGE CYCLE gt Figure 6 3 Interrupt Acknowledge Cycle Timing SIM INTERRUPTS MOTOROLA REFERENCE MANUAL 6 5 Figure 6 4 indicates possible pin connections and external logic connecting the SIM and an interrupting external device that provides a vector number The design shown in Figure 6 4 can be simplified by using SIM chip selects to decode the
91. ESET AND SYSTEM INITIALIZATION for more infor mation on reset procedures MOTOROLA SYSTEM CLOCK SIM 4 12 REFERENCE MANUAL 4 8 Clock Synthesizer Control Register SYNCR The SYNCR determines system clock operating frequency and mode of operation Bits with reset states labeled U are unaffected by reset SYNCR Clock Synthesizer Control Register 1HHHIOA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W X Y EDIV 0 0 SLIMP SLOCK RSTEN STSIM STEXT RESET 0 0 1 1 1 1 1 1 0 0 0 U U 0 0 0 W Frequency Control VCO 0 Base VCO frequency 1 VCO frequency multiplied by four Refer to 4 4 System Clock Frequency Control for additional information X Frequency Control Bit Prescale 0 Base system clock frequency 1 System clock frequency multiplied by two Refer to 4 4 System Clock Frequency Control for additional information Y 5 0 Frequency Control Counter The Y field is the initial value for the modulus 64 down counter in the synthesizer feed back loop Values range from 0 to 63 Refer to 4 4 System Clock Frequency Control for additional information EDIV ECLK Divide Rate 0 ECLK is system clock divided by 8 1 ECLK is system clock divided by 16 Refer to 4 5 External Bus Clock for additional information SLIMP Limp Mode Status 0 MCU is operating normally 1 Loss of reference signal MCU operating in limp mode Refer to 4 7 Loss of Reference Signal for
92. External resets are synchronous NOTE Since this pin is bidirectional a conflict exists when the CPU32 exe cutes a RESET instruction and an external device asserts the RE SET line On CPU32 based MCUS to guarantee that an external reset is recognized by the EBI RESET must be held for at least 520 cycles so that it overlaps the 512 cycles of the CPU32 RESET in struction 8 2 2 Power On Reset When the POW bit in the RSR is set the most recent reset state was caused by the power on reset circuit in the reset controller A power on reset is asynchronous Refer to 8 4 Power On Reset for more information 8 2 3 Software Watchdog Reset When the SW bit the RSR is set the most recent reset was caused by the software watchdog circuit in the system protection module A software watchdog reset indicates that the CPU is no longer executing the desired code A software watchdog reset is asynchronous 8 2 4 Double Bus Fault Reset When the bit in the RSR is set the most recent reset was caused by a double bus fault detected by the system protection module This type of reset is asynchro nous 8 2 5 Loss of Clock Reset When the LOC bit in the RSR is set the most recent reset was caused by a loss of clock reference signal This reset condition can exist only if the RSTEN bit in the syn thesizer control register SYNCR is set and the VCO is being used This type of reset is synchronous SIM RESET AND SYSTEM INITIALIZ
93. FO MODCLK SYPCR System Protection Control Register 1HHHI20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED SWE SWP SWT HME BME BMT RESET 1 0 0 0 0 0 0 SWE Software Watchdog Enable 0 Software watchdog disabled 1 Software watchdog enabled SWP Software Watchdog Prescale 0 Software watchdog clock not prescaled 1 Software watchdog clock prescaled by 512 SWTT 1 0 Software Watchdog Timing This field selects software watchdog time out period Software Watchdog Ratio SWP SWT Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 HME Halt Monitor Enable 0 Disable halt monitor function 1 Enable halt monitor function SIM MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 7 Bus Monitor External Enable 0 Disable bus monitor function for an internal to external bus cycle 1 Enable bus monitor function for an internal to external bus cycle 1 0 Bus Monitor Timing This field selects bus monitor time out period Bus Monitor Period BMT Bus Monitor Time out Period 00 64 System Clocks 01 32 System Clocks 10 16 System Clocks 11 8 System Clocks PICR Periodic Interrupt Control Register 22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 PIRQL PIV RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PIRQL 2 0 Periodic Interrupt Request Level This field determines the priority of periodic interrupt requests PIV 7
94. IZE TO WORD 7 ASSERT AS AND DS IF BKPT PIN ASSERTED 1 SET RAW TO READ 2 SET FUNCTION CODE TO CPU SPACE PLACE CPU SPACE 0 ON ADDR 19 16 IF BKPT INSTRUCTION EXECUTED PLACE ALLONES ON ADDIS 1 PLACE REPLACEMENT OPCODE ON DATA BUS SET SIZE TO WORD OR ASSERT AS AND DS 1 ASSERT BERR TO INITIATE EXCEPTION PROCESSING 3 4 5 6 7 IF BKPT ASSERTED IF BREAKPOINT INSTRUCTION EXECUTED AND 1 ASSERT DSACK DSACK IS ASSERTED OR 1 LATCHDATA _ 1 ASSERT BERR TO INITIATE EXCEPTION PROCESSING 2 NEGATE AS AND DS 3 GO TO A IF BKPT PIN ASSERTED AND DSACK IS ASSERTED 1 NEGATE AS AND DS 2 GO TO A IF BERR ASSERTED 1 NEGATE AS AND DS 2 GO TO B A IF BKPT INSTRUCTION EXECUTED 1 NEGATE DSACK OR BERR 1 PLACE LATCHED DATA IN INSTRUCTION PIPELINE 2 CONTINUE PROCESSING IF BKPT PIN ASSERTED 1 CONTINUE PROCESSING IF BKPT INSTRUCTION EXECUTED 1 INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED 1 INITIATE HARDWARE BREAKPOINT PROCESSING 1110A Figure 5 26 CPU32 Breakpoint Operation Flow MOTOROLA EXTERNAL BUS INTERFACE SIM 5 34 REFERENCE MANUAL CPU16 PERIPHERAL ACKNOWLEDGE BREAKPOINT 1 SET RW TO READ 2 SET FUNCTION CODE TO CPU SPACE 3 PLACE CPU SPACE TYPE 0 ON ADDR 19 16 4 PLACE ALL ONES ON ADDR 422 5 6 7 SET ADDR1 TO ONE SET SIZE TO WORD ASSERT AS AND DS ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING NEGATE AS AND DS NEGATE D
95. K Exceptions are taken in both cases Refer to the appropriate CPU ref erence manual for details of bus error exception processing When BERR is asserted after DSACK BERR must be asserted within the time spec ified referto APPENDIX A ELECTRICAL CHARACTERISTICS for purely asynchro nous operation or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACK is recognized WARNING If BERR is not stable at the specified time the MCU may exhibit er ratic behavior When BERR is asserted after DSACK data may be present on the bus but not be val id This sequence may be used by systems that have memory error detection and cor rection logic and by external cache memories so 5 sw sw s so s 54 CLKOUT l li 4 lt READ CYCLE WITH BUS 91 INTERNAL gt lt STACK gt PROCESSING WRITE BERR W O DSACK TIM Figure 5 31 Bus Error Without DSACK EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 41 aw XXX lt WRITE gt lt INTERNAL gt lt STACK gt CYCLE PROCESSING WRITE WI DSACK Figure 5 32 Late Bus Error with DSACK 5 9 2 Double Bus Faults Exception processing for bus error exceptions follows the standard exception process ing sequence However a special case of bus error called double bus fault can abort exception processing
96. Kbytes on CPU16 based MCUS in which ADDR 23 20 ADDR19 The address compare logic uses only the most significant bits to match an address within a block The value of the base address must be a multiple of block size Base address register diagrams show how base register bits correspond to address lines See 7 10 Chip Select Register Diagrams After reset the MCU fetches initialization vectors from word addresses beginning at memory location 000000 To support bootstrap operation from reset the base ad dress field in chip select base address register boot CSBARBT has a reset value of all zeros A memory device containing initialization can be automatically enabled by CSBOOT after a reset The block size field in CSBARBT has a reset value of 512 Kbytes Refer to 7 9 Chip Select Reset Operation for more information When programming a chip select circuit to respond to interrupt acknowledge cycles program the base address field bits 15 3 in the base address register to all ones Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles for more infor mation 7 3 Pin Assignments and Discrete Output The chip select pin assignment registers CSPAR1 0 contain 12 two bit fields CS 10 0 and CSBOOT that determine the functions of the chip select pins Each pin has two or three possible functions as shown in Table 7 3 MOTOROLA CHIP SELECTS SIM 7 4 REFERENCE MANUAL Table 7 3 Chip Select Pin Functions
97. LK OCCURS AFTER AS RSSERTED ASSERTS CS SYNCHRONIZED ASSERTS CS DURING THE WITH AS OR DS ECLK CYCLE 1 ENABLED YES AVEC ENABLED NO NO NO ASSERTS AVEC CS IACK FLOW 2 Figure 7 2 Flow Diagram for Chip Select Sheet 2 of 3 MOTOROLA CHIP SELECTS SIM 7 8 REFERENCE MANUAL MODE 1 DSACK GENERATOR EXTERNAL INTERNAL OR EXTERNAL INTERNAL GENERATES DSACK INTERNALLY WITH WAIT STATES OR FAST TERMINATE TERMINATES THE BUS CYCLE AT THE END OF ECLK CYCLE NEGATES CS AFTER AS OR DS CS IACK FLOW Figure 7 2 Flow Diagram for Chip Select Sheet 3 of 3 7 5 Chip Select Timing The MODE bit in the chip select option register determines whether chip select oper ation emulates asynchronous bus operation or is synchronized to the M6800 type bus clock signal ECLK available on ADDR23 Refer to SECTION 4 SYSTEM CLOCK for more information on ECLK When the MODE bit is programmed to emulate asyn chronous bus operation the DSACK and STRB fields further define chip select timing 7 5 1 Synchronization with AS or DS When MODE 0 in the associated chip select option register chip select operation emulates asynchronous external bus operation The chip select signal is asserted at the same time as AS or DS depending on the value in the STRB field in the option register As in an asynchronous bus cycle the chip select cycle must
98. M TEST REGISTER E SIMTRE S 0A UNUSED UNUSED S 0C UNUSED UNUSED S 0E UNUSED UNUSED S U 10 UNUSED PORT E DATA PORTEO S U 12 UNUSED PORT E DATA PORTE1 S U 4HHHHA UNUSED PORT E DATA DIRECTION DDRE S 16 UNUSED PORT E PINASSIGNMENT PEPAR S U 18 UNUSED PORT F DATA PORTF0 S U 1A UNUSED PORT F DATA PORTF1 S U 1C UNUSED PORT F DATA DIRECTION DDRF S 1E UNUSED PORT F PIN ASSIGNMENT PFPAR S 20 UNUSED SYSTEM PROTECTION CONTROL SYPCR S 22 PERIODIC INTERRUPT CONTROL REGISTER PICR S SHHHHO4 PERIODIC INTERRUPT TIMING REGISTER PITR S 26 UNUSED SOFTWARE SERVICE SWSR S 28 UNUSED UNUSED S SHHHHOA UNUSED UNUSED S 2G UNUSED UNUSED S 2E UNUSED UNUSED S 30 TEST MODULE MASTER SHIFT A TSTMSRA S 4HHHE32 TEST MODULE MASTER SHIFT B TSTMSRB S 4HHHE3A TEST MODULE SHIFT COUNT TSTSC S 36 TEST MODULE REPETITION COUNTER TSTRC S 8 TEST MODULE CONTROL CREG S U 3A TEST MODULE DISTRIBUTED DREG S 3C UNUSED UNUSED S SIHHHEGE UNUSED UNUSED S U 40 UNUSED PORT C DATA PORTC S U 42 UNUSED UNUSED S 44 CHIP SELECT PIN ASSIGNMENT REGISTER CSPAR0 S 46 CHIP SELECT PIN ASSIGNMENT REGISTER CSPAR1 S 48 CHIP SELECT BASE ADDRESS REGISTER BOOT CSBARBT S CHIP SELECT REGISTER CSORBT s 4C CHIP SELECT BASE ADDRESS REGISTER 0 CSBAR0 S SHHHH4E CHIP SELECT OPTION REGI
99. OOT BG CS 100 Group 3 I O pins 130 MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 2 REFERENCE MANUAL NOTES 1 Applies to Port D 7 0 Port E 7 3 Port F 7 0 TSTME TSC BKPT RESET 2 Input Only Pins TSTME TSC BKPT Output Only Pins CSBOOT BG CS CLKOUT FREEZE QUOT Input Output Pins Group 1 DATA 15 0 Group 2 Port C ADDR23 ECLK ADDR 22 19 CS 9 6 FC 2 0 CS 5 S3 Port E DSACK 1 0 AVEC DS AS SIZ 1 0 Port F IRQ 7 1 MODCLK ADDR 18 0 R W BERR BR CSO BGACK CS2 Group 3 HALT RESET 3 Does not apply to HALT and RESET because they are open drain pins 4 Current measured at system clock frequency of 16 78 MHz 5 Use of an active pulldown device is recommended 6 Total operating current is the sum of the appropriate Vpp supply and Vppsyn supply current 7 Power dissipation measured with system clock frequency of 16 78 MHz Power dissipation is calculated using the following expression Pp Maximum Vpp IppsvN t Ipp 8 Input capacitance is periodically sampled rather than 100 tested SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 3 Table A 3 AC Timing Vpp and VDDSYN 5 0 Vdc 10 Vss 0 Vdc
100. Q 7 1 Provides an interrupt priority level to the CPU Data and Size Acknowledge DSACK 1 0 Provide asynchronous data transfers and dynamic bus sizing Reset RESET System reset Test Mode Enable TSTME Hardware enable for SIM test mode Crystal Oscillator EXTAL XTAL Connections for clock synthesizer circuit reference a crystal or an external oscillator can be used Function Codes FC 2 0 Identify processor state and current address space Clock Mode Select MODCLK Selects the source and type of system clock Port C PC 6 0 SIM digital output port signals Port E PE 7 0 SIM digital I O port signals Port F PF 7 0 SIM digital I O port signals Read Modify Write RMC Indicates indivisible read modify write cycle CPU32 test and set instruction Read Write R W Indicates the direction of data transfer on the bus Size SIZ 1 0 Indicates the number of bytes to be transferred during a bus cycle Three State Control TSC Places all output drivers in a high impedance state External Filter Capacitor XFC Connection for external phase locked loop filter capacitor MOTOROLA SIGNAL AND PIN DESCRIPTIONS SIM 2 4 REFERENCE MANUAL SECTION 3 SYSTEM CONFIGURATION AND PROTECTION The system configuration and protection submodule controls MCU configuration and testing monitors internal activity monitors reset status and provides periodic interrupt generation Providing these functions on chip reduces the number of external compo nents in a complete control
101. SACK OR BERR INITIATE HARDWARE BREAKPOINT PROCESSING CPU16 BKPT FLOW Figure 5 27 CPU16 Breakpoint Operation Flow SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 35 0 51 52 53 84 55 S 52 53 54 55 580 51 52 53 54 55 ad e e ADDR 19 16 BREAKPOINT ENCODING 0000 ADDR 5 5 ADDRO Y gt BERR A HALT BKPT FETCHED INSTRUCTION BREAKPOINT EXECUTION BREAKPOINT READ lt ACKNOWLEDGE gt OCCURS INSTRUCTION WORD FETCHED BKPT OP RET TIM Figure 5 28 Breakpoint Acknowledge Cycle Timing Opcode Returned CPU32 Only MOTOROLA EXTERNAL BUS INTERFACE SIM 5 36 REFERENCE MANUAL 50 51 52 53 54 55 50 51 52 53 54 SS 50 51 52 53 54 V nue ADDR 320 Ta 19 16 BREAKPOINT ENCODING 0000 BREAKPOINT NUMBER T BIT ADDR 15 5 ADDRO Y Y CPU SPACE szo xw e aay RO eee X EU BREAKPOINT EXCEPTION ACKNOWLEDGE STACKING BREAKPOINT READ lt BERR ASSERTED CPU32 OCCURS OR DSACK OR BERR ASSERTED CPU16 CPU16 32 TIM Figure 5 29 Breakpoint Acknowledge Cycle Timing Exception Signaled SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 37 5 8 2 LPSTOP Broadcast Cycle When the CPU executes the LPSTOP instruction an LPSTOP broadcast cycle is gen erated During an LPSTOP broadcast cycle the CPU performs a
102. SIM 10 1 Registers address map 1 5 diagrams B 1 reset state 8 13 MOTOROLA l 3 RESET instruction 8 4 Resets 8 1 and chip selects 7 15 and mode select timing diagram A 14 block diagram 8 2 double bus fault 8 3 enable RSTEN 4 12 4 13 external 8 3 loss of clock 8 3 mode selection 1 6 operating configuration 8 8 pin state 8 11 power on 8 3 8 6 SIM registers 8 13 software watchdog 8 3 sources 8 2 status register RSR 8 3 8 4 system 8 4 timing 8 4 Retry sequence 5 44 termination 5 38 Return from exception RTE 5 42 RMC 5 13 5 43 5 47 and RPSIM 10 2 RPSIM 10 1 RSR 8 3 8 4 RSTEN 4 12 4 13 5 42 SHEN 3 4 5 52 Show cycles 5 52 enable SHEN 3 4 5 52 timing diagram A 13 Signals SIM 2 1 2 3 characteristics 2 3 function 2 4 SIM address map 1 5 block diagram 1 2 clock SIMCLK 4 12 configuration register SIMCR 3 2 3 3 reduced pin count 10 1 signals and pins 2 1 SIMCLK 4 12 SIMCR 3 2 3 3 SIZ 1 0 5 2 5 6 5 52 and interrupts 6 3 Slave factory test mode 3 3 enable SLVEN 3 3 3 4 SLIMP 4 13 SLOCK 4 13 SLVEN 3 3 3 4 Software breakpoints 5 32 watchdog 3 6 3 7 enable SWE 3 6 3 11 prescaler SWP 3 6 3 11 MOTOROLA 4 ratio 3 6 reset flag SW 8 3 8 4 service register SWSR 3 6 3 10 timing SWT 3 6 3 11 SPACE 7 2 7 3 7 20 Spurious interrupt monitor 3 5 STEXT stop mode external clock 4 12 4 14 Stop low power 3 9 STRB strobe 7 2 7 11 7 20 STSIM stop mode SIM clo
103. SIM SYSTEM INTEGRATION MODULE REFERENCE MANUAL MOTOROLA PART NUMBER 2 MANUAL TYPE TABLE CONTENTS Paragraph Title SECTION 1INTRODUCTION 1 1 Module MAPPING 2 to Peer etna E e 1 2 Reset Mode Selection 1 0 004 4 4 1 3 CPU Specific Differences Affecting SIM Operation SECTION 2 SIGNAL AND PIN DESCRIPTIONS 2 1 Pin Characteristics eee ap ed Cope ues etit dedos 2 2 Signal Desenplloris u uu nu u ben ec en eti SECTION 3 SYSTEM CONFIGURATION AND PROTECTION 3 1 Module Configuration and Testing 3 1 1 Module Mapping 3 1 2 Privilege Levels 3 1 3 Response to FREEZE Assertion 3 1 4 Interrupt Arbitration Priority r 3 1 5 Factory Test Modei un Rd edis 3 1 6 SIM Configuration Register 3 1 7 SIM Test Registers eoo pa du tx ex n 3 2 Internal Bus Monitor 3 3 Halt MORON sq u p 3 4 Spurious Interrupt Monitor oido t e ette t ee SR Pea s 3 5 Software Watchdog tet Goodies 3 6 Periodic Interrupt 3
104. ST is asserted for at least four clock cycles these modules are reset Vpp ramp time and VCO frequency ramp time determine how long these four cycles take Worst case is approximately 15 millisec onds During this period input output and output only port pins on modules other than the SIM may be in an indeterminate state Input output pins on these modules may be in output mode for a short time which may create a conflict with external input drive logic If a known state on input output or output only pins is required before this 15 ms peri od external reset control logic must condition these lines Active drivers require high impedance buffers or isolation resistors to prevent conflict Input only pins can be placed in a known state by means of external pull up resistors 8 5 Use of the Three State Control Pin Asserting the three state control TSC input causes the MCU to put all output drivers in a disabled high impedance state The signal must remain asserted for approxi mately 10 clock cycles in order for drivers to change state When the internal clock synthesizer is used MODCLK held high during reset synthe sizer ramp up time affects how long the 10 cycles take Worst case is approximately 20 milliseconds from TSC assertion SIM RESET AND SYSTEM INITIALIZATION MOTOROLA REFERENCE MANUAL 8 7 When an external clock signal is applied MODCLK held low during reset pins go to high impedance state as soon after TSC assertion
105. STER 0 CSORO S 50 CHIP SELECT BASE ADDRESS REGISTER 1 CSBAR1 S 52 CHIP SELECT OPTION REGISTER 1 CSOR1 S 54 CHIP SELECT BASE ADDRESS REGISTER 2 CSBAR2 S 56 CHIP SELECT OPTION REGISTER 2 CSOR2 S 58 CHIP SELECT BASE ADDRESS REGISTER 3 CSBAR3 S 5A CHIP SELECT OPTION REGISTER 3 CSOR3 INTRODUCTION MOTOROLA 1 5 Table 1 1 SIM Address Access Address 15 87 0 S 5 CHIP SELECT BASE ADDRESS REGISTER 4 CSBAR4 s 5E CHIP SELECT OPTION REGISTER 4 CSOR4 S 60 CHIP SELECT BASE ADDRESS REGISTER 5 CSBAR5 S 62 CHIP SELECT OPTION REGISTER 5 CSOR5 s 64 CHIP SELECT BASE ADDRESS REGISTER 6 CSBAR6 s 66 CHIP SELECT OPTION REGISTER 6 CSOR6 s SHHHHES CHIP SELECT BASE ADDRESS REGISTER 7 CSBAR7 S S4HHHIGA CHIP SELECT OPTION REGISTER 7 CSOR7 S SHHHHEC CHIP SELECT BASE ADDRESS REGISTER 8 CSBAR8 s 6E CHIP SELECT OPTION REGISTER 8 CSOR8 s 70 CHIP SELECT BASE ADDRESS REGISTER 9 CSBAR9 s 72 CHIP SELECT OPTION REGISTER 9 CSOR9 S 74 CHIP SELECT BASE ADDRESS REGISTER 10 CSBAR10 s 76 CHIP SELECT OPTION REGISTER 10 CSOR10 78 UNUSED UNUSED 7A UNUSED UNUSED 7C UNUSED UNUSED 7E UNUSED UNUSED 1 2 Reset Mode Selection The following information is a concise reference to one aspect of system reset System resetis a complex operation T
106. SYNCHRONOUS INPUTS SIM RD CYC TIM Figure A 4 Read Cycle Timing Diagram SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 9 Table 6 Key to Figure 4 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Max Units 614 Clock High to Address FC SIZE RMC Valid tcHAV 0 29 ns 8 Clock High to Address FC SIZE Invalid tcHazn 0 ns 9 Clock Low to AS DS CS Asserted ici SA 2 25 ns 9A AS to DS or CS Asserted Read tsTsa 15 15 ns 11 AppR FC SIZ RMC Valid tavsa 15 ns to AS CS Asserted 12 Clock Low to AS DS CS Negated 2 29 ns 13 5 DS CS Negated to Address FC SIZE Invalid 15 ns Address Hold 14 5 CS Width Asserted tswa 100 ns 155 JAS DS CS Width Negated isn 40 ns 18 Clock High to R W High CHRH 0 29 ns 20 Clock High to RW Low 0 29 ns 21 RAW High to AS CS Asserted tRAAA 15 ns 27 Data In Valid to Clock Low Data Setup tpicL 5 ns 27A Late BERR HALT Asserted to Clock Low Setup Time tBELCL 20 ns 28 AS DS Negated to DSACK BERR HALT AVEC Negated 0 80 ns 295 05 CS Negated to Data In Invalid Data In Hold teNDI 0 ns 29A 7
107. T p 08 ee MS RW Optional to prevent conflict on RESET negation DATA BUS MODE DECODE Figure 8 4 Data Bus Signal Conditioning If conflicts on the data bus during reset are not a concern a diode in series with a 1 kQ resistor can be used in place of an active device to hold a data bus pin low 8 6 3 Clock Mode Selection The state of the clock mode MODCLK pin during reset determines which clock source the MCU uses When MODCLK is held high during reset the clock signal is generated from a reference frequency When MODCLK is held low during reset the clock synthesizer is disabled and an external system clock signal must be applied Refer to SECTION 4 SYSTEM CLOCK for more information NOTE If the MODCLK pin is also used as a parallel port pin make certain that bus loading does not overcome the weak internal pull up driver during reset and cause inadvertent clock mode selection 8 6 4 Breakpoint Mode Selection The MCU uses internal and external breakpoint BKPT signals During reset excep tion processing at the release of the RESET signal the CPU samples these signals to determine how to handle breakpoints If either BKPT signal is at logic level zero when sampled an internal BDM flag is set and the CPU enters background debugging mode whenever either BKPT input is sub sequently asserted If both BKPT inputs are at logic level one when sampled breakpoint exception pro cessing begins wheneve
108. TOROLA REFERENCE MANUAL 5 15 Table 5 3 Operand Transfer Cases Num Transfer Case SIZ 1 0 ADDRO DSACK 1 0 Read Cycles Write Cycles Next DATA DATA DATA DATA Cycle 15 8 7 0 15 8 7 0 1 Byte to 8 bit Port 01 X 10 OPO OPO OPO 2 16 bit Port Even 01 0 01 OPO OPO OPO 3 Byte to 16 bit Port Odd 01 1 01 4 Word to 8 bit Port 10 0 10 OPO OPO OP1 1 Aligned 5 Word to 8 bit Port 10 1 10 OPO 1 Misaligned 1 6 Word to 16 bit Port 10 0 01 OPO OP1 OPO OP1 Aligned 7 Word to 16 bit Port 10 1 01 2 Misaligned 1 8 Long Word to 8 bit Port 00 0 10 OPO 1 13 Aligned 9 Long Word to 8 bit Port 10 1 10 OP0 OP0 12 Misaligned 1 3 10 Long Word to 16 bit Port 00 0 01 OPO OP1 OPO OP1 6 Aligned 11 Long Word to 16 bit Port 10 1 01 2 Misaligned 1 3 12 Byte to 8 bit Port 11 0 10 OPO OPO OP1 5 Aligned 2 13 Byte to 8 bit Port 11 1 10 OPO 4 Misaligned 2 NOTES 1 The CPU32 does not support misaligned transfers 2 Three byte transfer cases occur only as a result of a long word to byte transfer 3 The CPU16 treats misaligned long word transfers as two misaligned word transfers 5 5 1 Byte Operand
109. The system integration module SIM is a module on many Motorola 16 and 32 bit modular microcontroller units MCUs SIM based MCUs contain a SIM a CPU and some combination of communication timing and memory modules The different modules perform the following tasks The SIM supplies a clock signal to the rest of the microcontroller provides system protection features and manages the external bus In addition the SIM provides on chip chip select signals and if the pins are not being used for their alternate functions ports The CPU contains the microcode to process the instructions in its instruction set The CPU also works with the SIM to support exception processing including pro cessing of interrupts and reset requests system initialization special CPU bus cycles including breakpoint acknowledge cycles input output and separate su pervisor and user privilege levels To understand the SIM it is necessary to be familiar with the microcontroller s CPU Use this reference manual in conjunction with the appropriate CPU refer ence manual The CPU16 and CPU32 are the CPUs currently used with the SIM 1 3 CPU Specific Differences Affecting SIM Operation summarizes the differ ences between the CPU32 based SIM and the CPU16 based SIM Communication and timing modules include an analog to digital converter ADC time processing unit TPU general purpose timer GPT queued serial module QSM and multichannel communica
110. XTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 23 1 2 Data Bus 15 8 7 0 121 120 ADDRO DSACK1 DSACKO Cycle 1 OPO 1 0 1 1 0 Cycle 2 OP1 OP1 0 1 0 1 0 Cycle 3 OP2 OP2 1 0 1 1 0 Cycle 4 0 1 0 1 0 Figure 5 18 Long Word Operand to 8 Bit Port Misaligned For a read operation the 8 bit peripheral responds by placing OPO on DATA 15 8 and asserting DSACKO The MCU reads from DATA 15 8 and ignores DATA 7 0 The MCU then decrements the transfer size counter increments the address and waits for the peripheral to place OP1 on the upper byte of the data bus during the sec ond cycle a byte read of an 8 bit port When the second cycle is finished one mis aligned word has been read The MCU then reads a second misaligned word OP2 and OP3 from the 8 bit port during the third and fourth cycles For a write operation the MCU drives OPO on DATA 15 8 and OP1 on DATA 7 0 The 8 bit peripheral transfers OPO to the specified address then asserts DSACKO to indicate that the first byte of word data has been received The MCU then decrements the transfer size counter increments the address and places OP1 on the upper half of the data bus for the second cycle of the transfer a byte write to an 8 bit port After this second cycle one misaligned word has been written The MCU then writes a sec ond misaligned word OP2 and OP3 to the 8 bit
111. YTE ENABLE ROM ENABLE MIN SYS BLOCK Figure 7 5 System Configuration with Chip Selects 7 11 1 Configuring the RAM Chip Selects The following paragraphs describe the configuration of the RAM chip selects in the ex ample configuration Figure 7 5 7 11 1 1 Pin Connections The upper and lower memory banks are connected to CSO and CS1 respectively AD DR 13 1 are connected to ADDR 12 0 of each memory bank ADDRO of the MCU is not connected to the memory chips instead the chip select logic in each circuit uses the value of ADDRO on the internal address bus and the value of the BYTE field in the associated chip select option register to determine whether a match occurs No DSACK lines are connected since the chip selects are configured to generate DSACK signals internally No function code lines are connected in this example chip select logic is used to specify supervisor user space 7 11 1 2 Base Address Registers The base address registers are programmed as follows CSBARO 1001 CSBAR1 1001 This selects a block size of 16 Kbytes starting at address 100000 SIM MOTOROLA CHIP SELECTS REFERENCE MANUAL 7 22 7 11 1 3 Option Registers The option registers CSOR0 and CSOR1 are programmed as follows MODE 960 This causes chip select operation to emulate asynchronous bus op eration Bus cycles are terminated with DSACK BYTE 2910 CSORO and BYTE 9601 in CSOR1 This assigns the memory bank
112. ace is used for control information not normally associated with read or write bus cycles Function codes are valid while AS is asserted Table 5 4 shows address space encoding SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 27 Table 5 4 Address Space Encoding FC2 FC1 FC0 Address Space 0 0 0 Reserved 0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space The supervisor bit in the status register determines whether the CPU is operating in supervisor or user mode Addressing mode and the instruction being executed deter mine whether a memory access is to program or data space NOTE Because the CPU16 always operates in supervisor mode FC2 1 it does not use address spaces 0 to 3 The SIM chip select circuits can be programmed to respond to the type of memory ac cess CPU space user space supervisor space or user supervisor space Refer to SECTION 7 CHIP SELECTS for more information 5 7 System Interfacing Examples This section provides examples of interfacing the MCU to 8 and 16 bit memory devic es For purposes of illustration the examples that follow decode EBI signals external ly In practice it is more efficient to use SIM chip selects for most applications For configurations using SIM chip selects refer to 7 11 Interfacing Example with Chip Selects 5 7 1 Connectin
113. ads the content of the vector address into the PC and jumps to the exception handler routine at that address 5 8 1 2 Hardware Breakpoints A hardware breakpoint is initiated by assertion of the BKPT input The CPU responds by initiating a breakpoint acknowledge read cycle in CPU space It places 00001E on the address bus The breakpoint acknowledge code of 960000 is placed in AD DR 19 16 the breakpoint number value of 96111 is placed ADDR 4 2 and ADDR1 is set to one indicating a hardware breakpoint With CPU16 based MCUS the external breakpoint circuitry decodes the function code and address lines places an instruction word on the data bus and asserts either BERR or DSACK The CPU16 then performs hardware breakpoint exception process ing it acquires the number of the hardware breakpoint exception vector computes the vector address from this number loads the content of the vector address into the PC and jumps to the exception handler routine at that address With CPU32 based MCUs the external breakpoint circuitry decodes the function code and address lines places an instruction word on the data bus and asserts BERH The CPU32 then performs hardware breakpoint exception processing it acquires the num ber of the hardware breakpoint exception vector computes the vector address from this number loads the content of the vector address into the PC and jumps to the ex ception handler routine at that address If the exte
114. ammed as follows MODE 960 This causes chip select operation to emulate asynchronous bus op eration Bus cycles are terminated with DSACK BYTE 11 This assigns the ROM to be a 16 bit port SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 23 R W 9601 This configures the memory as read only STRB 960 This causes the chip select to be asserted with AS DSACK 960010 This causes DSACK signals to be generated internally by the SIM chip select circuitry with two wait states inserted SPACE 11 This selects the memory for both supervisor and user access IPL AVEC 960000 For read write cycles the interrupt fields are set to zeros MOTOROLA CHIP SELECTS SIM 7 24 REFERENCE MANUAL SECTION 8 RESET AND SYSTEM INITIALIZATION Reset procedures handle system initialization and recovery from catastrophic failure The MCU performs resets with a combination of hardware and software The SIM de termines whether a reset is valid synchronizes the reset if necessary to the completion of the current bus cycle asserts the appropriate internal signals performs basic sys tem configuration and boot ROM selection based on hardware mode select inputs and then passes control to the CPU The CPU handles a reset as the highest priority exception Each exception has an as signed vector that points to an associated handler routine During exception process ing the CPU fetches the vector assigned to the exception and executes th
115. and SIZ 1 0 One or both of DATA 15 8 and DATA 7 0 are selected and the responding device places data on that portion of the bus State 4 54 Appropriate internal DSACK signals are generated and the CPU latch es data on the falling edge of S4 State 5 55 The CPU negates AS and DS but holds the address valid to provide address hold time for memory systems R W SIZ 1 0 and FC 2 0 also remain valid throughout S5 The external device must maintain data until either AS or DS is negat ed It must remove the data within approximately one clock period after sensing the negation of AS or DS Signals that remain asserted beyond this limit can be prema turely detected during the next bus cycle MOTOROLA CHIP SELECTS SIM 7 12 REFERENCE MANUAL 7 7 7 8 SIM 2 Fast Termination Write Cycle A fast termination write cycle takes place in much the same way as a regular write cy cle except that the clock states for external handshaking are omitted State 0 0 The CPU places an address on ADDH 23 0 and function codes FC 2 0 The CPU drives R W low for a write cycle Size signals SIZ 1 0 become valid indicating the number of bytes to be written State 1 81 The CPU asserts AS indicating that the address on the address bus is valid SIM chip select logic decodes the appropriate address lines FC 1 0 R W SIZ 1 0 and AS State 4 84 Data driven onto DATA 15 0 becomes valid and the selected periph
116. arbitration is complete the module or device that wins contention places an interrupt vector number on the data bus and terminates the bus cycle with the appropriate DSACK signal When arbitration is complete an external device that wins contention asserts the autovector AVEC signal If no device or module enters interrupt arbitration or if the device winning arbitra tion does not respond in time the EBI bus monitor if enabled asserts the bus er ror signal and a spurious interrupt exception is taken Chip select logic can be programmed to decode the interrupt acknowledge bus cycle generate an interrupt acknowledge signal to the external device and generate a DSACK response Alternately the chip select circuit can be programmed to generate an AVEC response Refer to SECTION 7 CHIP SELECTS for more information Figure 6 2 is a flow chart of the interrupt acknowledge cycle INTERRUPTING DEVICE CPU REQUEST INTERRUPT GRANT INTERRUPT 1 SYNCHRONIZE 2 COMPARE IRQ 7 1 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE 3 PLACE INTERRUPT LEVEL ON ADDR 3 1 TYPE FIELD ADDR 19 16 F SET RW TO READ SET FC 2 0 TO 111 DRIVE SIZ 1 0 TO INDICATE SIZE OF TRANSFER ASSERT AS AND DS 4 5 6 7 PROVIDE VECTOR NUMBER 1 PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA BUS 2 ASSERT DSACK OR AVEC IF NO VECTOR NUMBER ACQUIRE VECTOR NUMBER 1 LATCH VECTOR NUMBER REL
117. as approximately 10 clock pulses have been applied to the EXTAL pin NOTE When TSC assertion takes effect internal signals are forced to val ues that can cause inadvertent mode selection Once the output driv ers change state the MCU must be powered down and restarted before normal operation can resume 8 6 Operating Configuration out of Reset The logic states of certain data bus pins during reset determine SIM operating config uration In addition the state of the MODCLK pin determines the system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint assertions Table 8 2 is a summary of reset mode selection options Subsequent para graphs explain these options in detail Table 8 2 Reset Mode Selection Mode Select Pin Default Function Alternate Function Pin Left High Pin Pulled Low DATAO CSBOOT 16 Bit CSBOOT 8 Bit DATA1 50 BR 51 BG S2 BGACK DATA2 S3 FC0 S4 FC1 S5 FC2 DATAS S6 ADDR19 DATA4 CS 7 6 ADDR 20 19 DATA5 CS 8 6 ADDR 21 19 DATA6 CS 9 6 ADDR 22 19 DATA7 CS 10 6 ADDR 23 19 DATA8 DSACKO DSACK1 PORTE AVEC DS AS SIZE DATA9 IRQ 7 1 PORTF MODCLK DATA11 Test Mode Disabled Test Mode Enabled MODCLK VCO System Clock EXTAL System Clock BKPT Background Mode Disabled Background Mode Enabled 8 6 1 Data Bus Mode Selection All data lines have weak internal pull up drivers during reset When pins a
118. bit memory device to the MCU SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 29 16 BIT MEMORY DEVICE DSACK GENERATOR ADDR x 1 ADDRI x 1 0 ADDR0 DATA 15 0 DATA 15 0 16 BIT MEM CONN Figure 5 23 Connecting a 16 Bit Memory Device 5 7 3 Connecting Two 8 bit Memory Devices to the MCU A 16 bit memory can be implemented using two 8 bit banks This configuration allows both byte and word memory accesses To implement this method individual chip se lects must be used for each bank of memory The upper bank of memory is selected when ADDRO 1 and the lower bank is selected when ADDRO 0 ADDRO is thus connected to the chip selects rather than to the address lines of the memory Figure 5 24 illustrates this configuration MOTOROLA EXTERNAL BUS INTERFACE SIM 5 30 REFERENCE MANUAL 5 8 SIM 8 BIT MEMORY DEVICE 5 ADDR x 1 0 DATA 15 8 8 BIT MEMORY DEVICE cs ADDR x 1 ADDR x 1 0 DATA 15 8 DATA 7 0 DATA 7 0 8 8 BIT MEM CONN Figure 5 24 Connecting Two 8 bit Memory Devices The SIM chip select circuitry can be programmed to individually select upper and low er bytes of a 16 bit memory system using two 8 bit banks Refer to 7 11 Interfacing Example with Chip Selects for an example of such a configuration CPU Space Cycles Function code signals FC 2 0 designate which of eight external address spaces is ac cessed during a bus cycle Address space 7 is designated CPU space CPU s
119. both read and write 00 Reserved 01 Read only 10 Write only 11 Read Write STRB Address Strobe Data Strobe The STRB bit controls the timing of a chip select assertion in asynchronous mode This bit has no effect in synchronous mode 0 Synchronize chip select assertion with address strobe 1 Synchronize chip select assertion with data strobe DSACK Data and Size Acknowledge This field specifies the source of DSACK when chip select cycles emulate asynchro nous bus cycles and controls wait state insertion Refer to 7 6 Chip Selects and Dy namic Bus Sizing for details SPACE Address Space Select The SPACE field determines the address space in which a chip select is asserted An access must have the space type represented by SPACE encoding in order for a chip select signal to be asserted Refer to 7 8 Using Chip Selects in Interrupt Acknowl edge Cycles for additional information 00 CPU space 01 User space 10 Supervisor space 11 Supervisor or user space MOTOROLA CHIP SELECTS SIM 7 20 REFERENCE MANUAL IPL Interrupt Priority Level This field selects the interrupt level when a chip select is used for interrupt acknowl edge Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles for addi tional information 000 Any Level 001 Level 1 010 Level 2 011 Level 3 100 Level 4 101 Level 5 110 Level 6 111 Level 7 AVEC Autovector Enable This field specifies whether to gen
120. chip selects Refer to 7 3 Pin Assignments and Dis crete Output for pin assignment field encoding Port size assignment determines which signal the chip select logic asserts DSACK1 or DSACKO after the specified number of wait states elapse during a chip select access Chip select logic also decodes the internal SIZ 1 0 signals to determine which byte or bytes of the data bus to use during a data transfer In addition for 16 bit ports the BYTE field in the chip select option register determines whether the chip select is as serted for upper byte accesses lower byte accesses or both Table 7 5 shows BYTE field encoding MOTOROLA CHIP SELECTS SIM 7 10 REFERENCE MANUAL Table 7 5 BYTE Field Encoding BYTE 1 0 Meaning 00 Disable 01 Assert when ADDR 0 lower byte 10 Assert when ADDR 1 upper byte 11 Assert when ADDR 0 or 1 either byte BYTE field encoding options are used to generate chip select signals for word and sin gle byte transfers to 16 bit ports For example two chip select lines can be used to se lect 8 bit banks in a 16 bit memory To do this program two chip select base address registers with the same base address then set up the individual lines for byte access Program both option registers identically except for the BYTE fields use the upper byte option for one line and the lower byte option for the other Refer to 7 11 Interfacing Example with Chip Selects for an illustration of dynam
121. ck 3 9 4 12 4 13 Supervisor privilege level 1 1 1 4 1 8 3 2 SUPV 3 4 SW 8 3 8 4 SWE 3 6 3 11 SWP 3 6 3 11 SWSR 3 6 3 10 SWT 3 6 3 11 Synchronous resets 8 2 SYNCR 4 1 4 6 4 12 4 13 Synthesizer lock SLOCK 4 13 SYPCR 3 6 3 11 SYS 8 4 System configuration 3 1 initialization 8 1 8 14 protection 3 1 control register SYPCR 3 5 3 11 reset flag SYS 8 4 e TAS test and set 5 13 Test mode 3 3 registers 3 4 reset flag TST 8 4 TSC three state control 8 7 TST 8 4 U User privilege level 1 1 1 4 1 8 3 2 V st subscript DDSYN 4 5 V st subscript SSI 4 5 VCO 4 4 Vector interrupt 6 4 W W bit 4 6 4 7 4 13 Wait states 5 6 and chip selects 7 10 Word transfer 16 bit port 5 20 SIM REFERENCE MANUAL 8 bit port 5 18 Write cycles 5 11 fast termination 7 13 timing diagram A 11 X bit 4 6 4 7 4 13 XFC 4 5 XTAL 4 1 4 3 4 4 Y Y field 4 6 4 7 4 13 SIM REFERENCE MANUAL MOTOROLA l 5 SIM 1 6 REFERENCE MANUAL
122. cle opera tion Additionally on certain MCUs and HALT can be asserted simultaneously to indicate a retry termination 5 9 Bus Error Processing provides additional informa tion on the HALT signal 5 1 11 Autovector Signal The autovector signal AVEC can be used to terminate external interrupt acknowl edge cycles resulting from interrupts from external IRQ pins Assertion of AVEC caus es the CPU to generate vector numbers to locate an interrupt handler routine Refer to SECTION 6 INTERRUPTS for more information for external interrupt requests can also be supplied internally by chip select logic Refer to SECTION 7 CHIP SELECTS for more information SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 3 5 2 External Bus Cycle Overview Data transfer operations with external devices consist of one or more external bus cy cles This subsection describes individual bus cycles during each of these transfer op erations 5 3 Dynamic Bus Sizing explains the use of the DSACK 1 0 and SIZ 1 0 signals and the placement of operands on the data bus 5 5 Operand Transfer Cases provides additional details of bus cycle operation for each combination of operand size and port width External bus cycles are normally asynchronous using handshaking between the MCU and external peripherals to indicate transfer size and the availability of data These ac cesses typically require a minimum of three system clock cycles Two clock accesse
123. complete The CPU does not latch the priority of a pending interrupt request If an interrupt source of higher priority makes a service request while a lower priority request is pend ing the higher priority request is serviced If an interrupt request with a priority equal to or lower than the current IP mask value is made the CPU does not recognize the occurrence of the request 6 3 Interrupt Arbitration When the CPU detects one or more interrupt requests of a priority higher than the in terrupt priority mask value it places the interrupt request level on the address bus and initiates a CPU space read cycle The request level serves two purposes it is decoded by modules that have requested interrupt service to determine whether the current in terrupt acknowledge cycle pertains to them and it is latched into the interrupt priority mask field in the CPU status register on CPU32 based MCUs or condition code reg ister on CPU16 based MCUS in order to mask lower priority interrupts during excep tion processing Modules that have requested interrupt service decode the interrupt priority mask value placed on the address bus at the beginning of the interrupt acknowledge cycle If a module s request is at the specified priority mask level it enters interrupt arbitration Arbitration between simultaneous requests of the same level is performed by means of serial contention between module interrupt arbitration IARBI field bit values Each m
124. cycle the MCU asserts data strobe DS to signal an external device to place data on the bus DS is asserted at the same time as AS during a read cycle For a write cycle DS signals an external device that data on the bus is valid The MCU asserts DS one full clock cycle after the assertion of AS during a write cycle 5 1 5 Read Write Signal The read write R W signal determines the direction of the transfer during a bus cycle This signal changes state when required at the beginning of a bus cycle and is valid while AS is asserted R W changes state only when a write cycle is preceded by a read cycle or vice versa The signal may remain low for two consecutive write cycles 5 1 6 Size Signals The size signals SIZ 1 0 indicate the number of bytes remaining to be transferred during an operand cycle They are valid while the address strobe AS is asserted Re fer to 5 3 Dynamic Bus Sizing for information on SIZ1 and SIZO encoding and on us ing the SIZO and SIZ1 pins in dynamic bus allocation 5 1 7 Function Codes The CPU generates function code signals FC 2 0 The function codes can be consid ered address extensions that designate which of eight external address spaces is ac cessed during a bus cycle Refer to 5 6 Function Codes and Memory Usage for information on function code signal encoding and usage MOTOROLA EXTERNAL BUS INTERFACE SIM 5 2 REFERENCE MANUAL 5 1 8 Data and Size Acknowledge Signals During normal asynchronou
125. d peripherals ECLK frequency can be set to the system clock frequency divided by eight or system clock frequency divided by sixteen The clock is enabled by the CS10 field in chip select pin assignment register 1 CSPAR1 The operation of the external bus clock during low power stop is described below Re fer to SECTION 7 CHIP SELECTS for more information on the external bus clock 4 6 Low Power Stop Operation To reduce overall microcontroller power consumption to a minimum the CPU can ex ecute the LPSTOP instruction which causes the SIM to turn off the system clock to most of the MCU When the CPU executes LPSTOP a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic The SIM brings the MCU out of low power operation when either an interrupt of higher priority than the stored mask or a reset occurs Refer to 5 8 2 LPSTOP Broadcast Cycle for more information SIM SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 11 During low power stop SIM clock control logic and the SIM clock signal SIMCLK continue to operate The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK The SIM can also continue to generate the CLKOUT signal while in low power mode The STSIM stop mode SIM clock and STEXT stop mode external clock bits in the SYNCR determine clock operation during low power stop Table 4 3 summarizes the sources of SIMCLK and CLKOUT for different comb
126. dicates the results of each type of bus cycle ter mination Normal Termination DSACK is asserted BERR and HALT remain negated case 1 Halt Termination HALT is asserted at the same time or before DSACK and BERR remains negated case 2 Bus Error Termination BERR is asserted in lieu of at the same time as or before DSACK case 3 or after DSACK case 4 and HALT remains negated is negated at the same time or after DSACK Retry Termination HALT and BERR are asserted in lieu of at the same time as or before DSACK case 5 or after DSACK case 6 BERR is negated at the same time or after DSACK HALT may be negated at the same time or after BERR MOTOROLA EXTERNAL BUS INTERFACE SIM 5 38 REFERENCE MANUAL On CPU16 based MCUs assertion of BERR results in bus error exception regardless of the state ofthe HALT signal These CPUs do not support the retry termination sequence Refer to the appropriate CPU manual or to the user manual for the specific device for details Table 5 5 shows various combinations of control signal sequences and the resulting bus cycle terminations Table 5 5 DSACK BERR and HALT Assertion Results Case Control Signal Asserted on Result Number Rising Edge of State N 2 1 DSACK A s Normal termination BERR NA NA HALT NA x 2 DSACK A s Halt termination normal cycle termi
127. dress on the address bus and drives the size pins to indicate a word operand The MCU also drives the function code and R W pins to appropriate values NOTE The CPU32 does not support transfers of misaligned operands 15 8 7 0 Operand OPO OP1 Data Bus 15 8 7 0 5121 5120 ADDRO DSACK1 DSACKO Cycle 1 1 0 1 0 1 Cycle 2 OP1 OP1 0 1 0 0 1 Figure 5 14 Word Operand to 16 Bit Port Misaligned For a read operation the peripheral responds by placing OP0 on DATA 7 0 and as serting DSACK1 to indicate a 16 bit port When DSACK1 is asserted the MCU reads from 7 0 decrements the transfer size counter increments the address and waits for the peripheral to place OP1 on the upper byte of the data bus for the sec ond cycle of the transfer a byte read of a 16 bit port For a write operation the MCU drives OP0 on both bytes of the data bus The periph eral device reads from DATA 7 0 and asserts DSACK1 The MCU decrements the transfer size counter increments the address and places OP1 on both bytes of the data bus for the second cycle of the transfer a byte write to a 16 bit port For both reads and writes refer to 5 5 2 Byte Operand to 16 Bit Port Even ADDRO z 0 for details on the second cycle of the data transfer 5 5 8 Long Word Operand to 8 Bit Port Aligned The MCU arives the address bus with the desired address and the size pins to indicate a long word operand The
128. e clock synthesizer is bypassed SYNCR frequency control bits have no effect in this case CAUTION When using the MODCLK pin for I O PFO be sure the external cir cuitry is designed so that during reset MODCLK is held at the logic level that selects the desired clock mode After reset the PFO bit in the port F data register can be assigned the desired value for I O 4 1 1 Internal Phase Locked Loop To generate a clock signal with the phase locked loop PLL connect a clock refer ence to the EXTAL pin and hold MODCLK high during reset The clock reference can be created by connecting a crystal circuit across the EXTAL and XTAL pins or by con necting an external reference to the EXTAL pin In the latter case the XTAL pin must be left floating The frequency of the external reference depends on the MCU Refer to the user s manual for the particular MCU for the range of reference frequencies that can be used with the part Possible frequency ranges include 25 to 50 kHz and 3 2 to 6 4 MHz For frequencies in the latter range the reference frequency is divided internally by 128 be fore it is supplied to the PLL Refer to 4 2 Clock Synthesizer Operation With a 4 194 MHz reference frequency a signal of 32 768 kHz is provided to the PLL Clock synthesizer specifications in Table A 1 of APPENDIX A ELECTRICAL CHARAC TERISTICS are based upon a 32 768 kHz or 4 194 MHz reference frequency SIM SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 1 Fi
129. e different sources of reset and the reset lines that the reset control logic asserts for each type of reset request SIM RESET AND SYSTEM INITIALIZATION MOTOROLA REFERENCE MANUAL 8 1 RESET REQUEST RESET LINE SYSTEM SOFTWARE WATCHDOG DOUBLE BUS FAULT LOSS OF CLOCK TEST MSTRST CLKRST EXTRST SYSRST POWER ON RESET RESET LOGIC BLOCK Figure 8 1 Reset Block Diagram All resets are gated by CLKOUT Resets are classified as synchronous or asynchro nous An asynchronous reset can occur on any CLKOUT edge Reset sources that cause an asynchronous reset usually indicate a catastrophic failure thus the reset control logic responds by asserting reset to the system immediately A system reset however caused by the CPU32 RESET instruction is asynchronous but does not in dicate any type of catastrophic failure see 8 2 Sources of Reset for more informa tion A synchronous reset occurs at the end of a bus cycle For synchronous resets only single byte or aligned word writes on the IMB are guaranteed to be completed without data corruption Long word writes misaligned operand writes and read cycles are not guaranteed to be completed External writes are also guaranteed to be completed provided the external configuration logic on the data bus is conditioned by R W as shown in Figure 8 4 later in this section The internal bus monitor is automatically enabled whenever the reset control logic must synchronize reset to the end
130. e exception routine to which the vector points Exception vectors are stored in a vector table Out of reset the table is located begin ning at address 000000 The reset vector occupies the first four words of the vector table The CSBOOT chip select signal which responds to memory accesses starting at 000000 coming out of reset can be used to select the boot ROM chip with the sys tem initialization routine The size of the vector table the size of each exception vector and whether the table can be relocated depend on the CPU Refer to the appropriate CPU reference manual for additional information on exception vectors and exception processing 8 1 Reset Operation Sources of reset include external reset power on reset software watchdog double bus fault loss of crystal and system the CPU32 RESET instruction The reset status register RSR contains a status bit for every reset source in the SIM Reset control logic determines the cause of reset synchronizes reset assertion if nec essary to the completion of the current bus cycle and asserts the appropriate reset lines Reset control logic can drive four different internal signals EXTRST external reset drives the external reset pin CLKRST clock reset resets the clock module MSTRST master reset goes to all other internal circuits e SYSRST system reset indicates to internal circuits that the CPU has executed a RESET instruction Figure 8 1 indicates th
131. e must be written to the SWSR within a specific interval When read the SWSR returns all zeros The register is shown with the read value SWSR Software Service Register 1HHHEI26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 0 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 3 8 2 Periodic Interrupt Control Register PICR The PICR contains the interrupt request level and vector number for the periodic inter rupt timer PICR 10 0 can be read or written at any time PICR 15 11 are unimple mented and always return zero PICR Periodic Interrupt Control Register SHHHH22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 PIRQP PIB RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PIRQL 2 0 Periodic Interrupt Request Level This field determines the priority of periodic interrupt requests PIV 7 0 Periodic Interrupt Vector The bits of this field contain the periodic interrupt vector number supplied by the SIM when the CPU acknowledges an interrupt request 3 8 3 Periodic Interrupt Timer Register PITR The PITR contains the count value for the periodic timer This register can be read or written at any time PITR Periodic Interrupt Timer Register 1HHHI24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PTP PITM RESET 0 0 0 0 0 0 0 MODCLK 0 0 0 0 0 0 0 0 PTP Periodic Timer Prescaler Control 0 Periodic timer clock not
132. e of MM is one but the bit can be written once Initial ization software should make certain it remains set by writing a one to it Table 1 1 is the SIM register map The column labeled Access indicates the privilege level at which the CPU must be operating to access the register A designation of S indicates that supervisor access is required a designation of S U indicates that the register can be programmed to the desired privilege level Refer to 3 1 Module Con figuration and Testing for information on assigning privilege levels NOTE CPU16 based MCUs do not support separate supervisor and user privilege levels The CPU16 always operates at the supervisor privi lege level Table 1 1 provides SIM register addresses relative to the SIM base address In this table the four high order nibbles of each address are listed as Refer to the us er s manual for the specific MCU for the exact location of these registers Remember that the MSB is determined by the MM bit MOTOROLA INTRODUCTION SIM 1 4 REFERENCE MANUAL Table 1 1 SIM Address SIM REFERENCE MANUAL Access Address 15 8 7 0 S 00 SIM CONFIGURATION REGISTER SIMCR S 02 SIM TEST REGISTER SIMTR S 4HHHEOA SYNTHESIZER CONTROL REGISTER SYNCR S 4HHHEOG UNUSED RESET STATUS REGISTER RSR S 08 SYSTE
133. e specified bus monitor time out period the bus monitor if en abled for internal to external bus cycles terminates the cycle 5 2 2 Synchronization to CLKOUT All external asynchronous input signals must be synchronized to the MCU clock before being acted upon The CLKOUT system clock output signal enables external devices to synchronize DSACK and other signals with the MCU system clock For all inputs the MCU latches the level of the input during a sample window around the falling edge of CLKOUT Refer to Figure 5 1 To ensure that an input signal is recognized on a specific falling edge of the clock that input must be stable during the sample window If an input makes a transition during the window time period the level recognized by the MCU is not predictable however the MCU always resolves the latched level to a logic high or low before using it CLKOUT XXXI SAMPLE WINDOW INPUT SAMPLE TIM Figure 5 1 Input Sample Window SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 5 When the specifications for asynchronous setup and hold time are met the MCU is guaranteed to recognize the appropriate signal on a specific edge of the CLKOUT sig nal For a read cycle when assertion of DSACK is recognized on a particular falling edge of the clock valid data is latched into the MCU on the next falling clock edge provided that the data meets the data setup time
134. ead at any time A write has no effect RSR Reset Status Register 4HHHIEOG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED EXT POW SW DBF 0 LOC SYS TST EXT External Reset Reset was caused by an external signal POW Power On Reset Reset was caused by the power on reset circuit SW Software Watchdog Reset Reset was caused by the software watchdog circuit DBF Double Bus Fault Reset Reset was caused by a double bus fault LOC Loss of Clock Reset Reset was caused by loss of clock reference signal SYS System Reset Reset was caused by the CPU32 RESET instruction The CPU16 does not support this instruction TST Test Submodule Reset Reset was caused by the test submodule This bit is set during system test only MOTOROLA RESET AND SYSTEM INITIALIZATION SIM 8 4 REFERENCE MANUAL 8 3 Reset Control Flow The following paragraphs describe reset control flow after the SIM receives a reset re quest Refer to 8 4 Power On Reset for additional details of reset timing during power on reset Figure 8 2 is a reset control flow diagram POWER ON RESET ASSERT EXTERNAL RESET EXTERNAL RESET ASSERTED NO 512 CLOCK COUNTDOWN ASSERT EXTERNAL RESET SOFTWARE LATCH DATA BUS CONFIGURATION RESET AND RECONFIGURE ASSERT EXTERNAL RESET 512 CLOCK COUNTDOWN 12 CLOCK COUNTDOWN ASSERT EXTERN
135. ed in the clock control logic and internal clocks are disabled according to the state of the STSIM bit in the SYNCR The bus monitor halt monitor and spurious interrupt monitor are all inactive during low power stop During low power stop the clock input to the software watchdog timer is disabled and the timer stops The software watchdog begins to run again on the first rising clock edge after low power stop ends The watchdog is not reset by low power stop a ser vice sequence must be performed to reset the timer The periodic interrupt timer does not respond to the LPSTOP instruction It continues to run at the same frequency as EXTAL during LPSTOP A periodic timer interrupt can bring the MCU out of low power stop if it has a higher priority than the interrupt mask value stored in the clock control logic when low power stop is initiated To stop the pe riodic interrupt timer the PITR must be loaded with a zero value before the LPSTOP instruction is executed 3 8 System Protection Registers The following registers are involved in system protection the SIMCR the SWSR the PICR the PITR and the SYPCR A register diagram of the SIMCR is provided in 3 1 Module Configuration and Testing Register diagrams of the other registers are pro vided in the following paragraphs SIM SYSTEM CONFIGURATION AND PROTECTION MOTOROLA REFERENCE MANUAL 3 9 3 8 1 Software Service Register SWSR When the software watchdog is enabled a service sequenc
136. ed with respect to DS or CS on asynchronous reads and with respect to CLKOUT on synchronous reads The user is free to use either hold time Maximum value is equal to 2 25 ns MOTOROLA A 25 MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 26 REFERENCE MANUAL APPENDIX BMEMORY MAP AND REGISTERS B 1 SIM Memory Map Table B 1 SIM Address Map SIM REFERENCE MANUAL Access Address 15 817 0 5 3HHHEOO SIM CONFIGURATION REGISTER SIMCR S THHHEO2 SIM TEST REGISTER SIMTR S 3HHHEOA SYNTHESIZER CONTROL REGISTER SYNCR S THHHEOG UNUSED RESET STATUS REGISTER RSR S 08 SYSTEM TEST REGISTER E SIMTRE S THHHEOA UNUSED UNUSED S THHHEOC UNUSED UNUSED S THHHEOE UNUSED UNUSED S U THHHHO UNUSED PORT E DATA PORTEO S U THHHH 2 UNUSED PORT E DATA PORTE1 S U THHHH A UNUSED PORT E DATA DIRECTION DDRE S THHHH 6 UNUSED PORT E PIN ASSIGNMENT PEPAR S U THHHH8 UNUSED PORT F DATA PORTFO S U HHHHIA UNUSED PORT F DATA PORTF1 S U THHHHC UNUSED PORT F DATA DIRECTION DDRF S UNUSED PORT F PIN ASSIGNMENT PFPAR S THHHE20 UNUSED SYSTEM PROTECTION CONTROL SYPCR S THHHE22 PERIODIC INTERRUPT CONTROL REGISTER PICR S THHHE2A PERIODIC INTERRUPT TIMING REGISTER PITR S THHHE26 UNUSED SOFTWARE SERVICE SWSR S THHHE28 UNUSED UNUSED S THHHEZA UNUSED UNUSED S 2 UNUSED UNUSED S THHHEZE UNUSED UNUSED S
137. eing used for their chip select function or alternate function as address or function code lines Two data ports port E and port F are available for general purpose input and out put if not required for their alternate function A port data register data direction register and pin assignment register are associated with each port The system test block incorporates hardware necessary for testing the MCU Its use in normal applications is not supported NOTE Some SIM based MCUs have a reduced pin set due to pin limita tions Some of the chip select and data port pins described in this manual may not be present on these MCUs Refer to the user s man ual for the particular MCU for a list of the available pins on that de vice Refer to SECTION 10 REDUCED PIN COUNT SIM for additional information Figure 1 1 is a block diagram of the SIM SYSTEM CONFIGURATION AND PROTECTION CLKOUT CLOCK SYNTHESIZER EXTAL MODCLK EXTERNAL BUS UPPER ADDRESS CHIP SELECTS p CHIP SELECTS EXTERNAL BUS INTERFACE RESET TSTME FACTORY TEST FREEZE QUOT SIM BLOCK Figure 1 1 System Integration Module Block Diagram MOTOROLA INTRODUCTION SIM 1 2 REFERENCE MANUAL Figure 1 2 shows the input and output signals associated with each functional block of the SIM These signals are described more fully in SECTION 2 SIGNAL AND PIN DESCRIPTIONS and in subsequent sections of the manual CHIP SELECTS ADDR23 CS10 ADDR2
138. eparately RMC remains asserted during the entire retry sequence The MCU will not relinquish the bus while RMC is asserted Any device that requires the MCU to give up the bus and retry a bus cycle during a read modify write cycle must assert BERR and BR only HALT must remain negated The bus error handler software should examine the read modify write bit in the special status word and take the appropriate action to resolve this type of fault when it occurs Refer to the CPU32 reference manual for de tails on the special status word The CPU16 does not use this word EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 43 CLKOUT ADDR 23 0 FC 2 0 MOTOROLA 5 44 F READ CYCLE WITH gt 5 lt lt 22 7 RETRY Figure 5 33 Retry Sequence EXTERNAL BUS INTERFACE BERR RETRY TIM SIM REFERENCE MANUAL wwa D X wen C CC X lt WRITE gt lt HALT gt lt WRITE gt CYCLE RERUN BERR LATE RETRY TIM Figure 5 34 Late Retry Sequence 5 9 4 Halt Operation When HALT is asserted and BERR is not asserted on MCUs that support the retry sequence the MCU halts external bus activity after negation of DSACK The MCU may complete the current word transfer in progress For a long word to byte transfer this could be after S2 or S4 For a word to byte transfer activit
139. er P er T CLKOUT gt SYSTEM CLOCK pur 1 Must be low leakage capacitor insulation resistance 30 000 or greater 2 Resistance and capacitance based on a test circuit constructed with a KDS041 18 4 194 MHz crystal Specific components must be based on crystal type Contact crystal vendor for exact circuit 3 4 MHz divided to 32 kHz 16 SYS CLOCK BLOCK 4MHZ Figure 4 2 System Clock with 4 194 MHz Reference Crystal 4 1 2 External Clock Signal To use an external clock source with the MCU apply the clock signal to the EXTAL pin and leave the XTAL pin floating Hold the MODCLK pin low during reset signaling the MCU to bypass the frequency synthesizer and VCO SYNCR frequency control bits have no effect in this case When an external system clock signal is applied the duty cycle of the input is critical especially at operating frequencies close to the maximum The relationship between the duty cycle of an external clock signal and the clock signal period is expressed as follows Minimum external clock period minimum external clock high low time 5096 percentage variation of external clock input duty cycle Refer to Table A 3 in APPENDIX A ELECTRICAL CHARACTERISTICS for the min imum external clock high low time The external system clock signal frequency must be less than or equal to the maximum specified system clock frequency SIM SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 3 4
140. er for a chip select signal to be asserted Refer to 7 8 Using Chip Selects in Interrupt Acknowl edge Cycles for additional information 00 CPU space 01 User space 10 Supervisor space 11 Supervisor or user space IPL Interrupt Priority Level This field selects the interrupt level when a chip select is used for interrupt acknowl edge Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles for addi tional information 000 Any Level 001 Level 1 010 Level 2 011 Level 3 100 Level 4 101 Level 5 110 Level 6 111 Level 7 SIM MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 11 AVEC Autovector Enable This field specifies whether to generate an internal AVEC signal during an interrupt ac knowledge cycle initiated by assertion of an IRQ pin when match conditions are met Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles for additional in formation 0 Disable AVEC generation 1 Enable AVEC generation MOTOROLA MEMORY MAP AND REGISTERS SIM B 12 REFERENCE MANUAL timing 4 Access levels 1 4 3 2 ADDR 23 0 5 2 7 19 and interrupts 6 3 and RPSIM 10 1 Address map SIM 1 5 strobe AS 5 2 Alignment operand 5 7 AS 5 2 Asynchronous resets 7 9 AVEC autovector 5 3 6 6 bit 7 3 7 15 7 21 Background debugging mode BDM 3 2 Base address registers chip select 7 19 CSBAR 10 0 7 19 CSBARBT 7 4 7 17 7 19 BDM 3 2 BERR 3 5 5 3 5 38 5 40 6
141. eral latches the data Appropriate internal DSACK signals are generated State 5 S5 The MCU negates AS but holds the address and data valid to provide address hold time for memory systems R W SIZ 1 0 and FC 2 0 also remain valid throughout S5 Using Chip Selects in Interrupt Acknowledge Cycles Chip select circuits can be programmed to respond during interrupt acknowledge cy cles initiated by assertion of an external IRQ pin Any chip select circuit can be pro grammed so that the chip select pin is asserted during an interrupt acknowledge cycle when match conditions are met Alternately the chip select circuit can be programmed to generate autovector AVEC signals internally To configure a chip select to respond during an interrupt acknowledge cycle bits 15 3 of the base register must be set to all ones to match ADDR 23 11 since the address is compared to an address generated by the CPU See Figure 7 4 In the chip select option register set the SPACE field to 9600 for CPU space and set the R W field to read only During an interrupt acknowledge cycle the interrupt priority on ADDR 3 1 is com pared to the value of IPL in the chip select option register If the values are the same and other option register constraints are satisfied a chip select signal is asserted Encoding 96000 causes a chip select signal to be asserted regardless of the interrupt level on ADDR 3 1 provided all other constraints are met F
142. erate an internal AVEC signal during an interrupt ac knowledge cycle initiated by assertion of an IRQ pin when match conditions are met Refer to 7 8 Using Chip Selects in Interrupt Acknowledge Cycles for additional in formation 0 Disable AVEC generation 1 Enable AVEC generation 7 10 4 Port C Data Register PORTC The port C data register latches data for pins programmed as discrete outputs When a pin is assigned as a discrete output the value in this register appears at the output PC 6 0 correspond to CS 9 3 This is a read write register Bit 7 is not used Writing to this bit has no effect and a read returns zero Refer to 7 3 Pin Assignments and Discrete Output for more information on this register PORTC Port C Data Register 1HHHIAO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 0 PC6 PC5 4 2 1 PC0 7 11 Interfacing Example with Chip Selects Figure 7 5 shows a system configuration in which SIM chip select pins are connected to a boot ROM module and a 16 bit memory consisting of two banks of 8 bit memory The following paragraphs discuss connecting the pins and programming the base and option registers for the connected chip selects SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 21 MCU 15 0 DATA 15 0 DATA 15 0 ADDR 15 0 55 2 a a DATA ADDR DATA ADDR DATA ADDR ROM 64K X 16 UPPER BYTE ENABLE LOWER B
143. es are in kilohertz Shaded cells represent values that exceed maximum system frequency specification Modulus Prescaler Y W X 00 W X 01 W X 10 W X 11 000000 131 kHz 262 kHz 524 kHz 1049 kHz 000001 262 524 1049 2097 000010 393 786 1573 3146 000011 524 1049 2097 4194 000100 655 1311 2621 5243 000101 786 1573 3146 6291 000110 918 1835 3670 7340 000111 1049 2097 4194 8389 001000 1180 2359 4719 9437 001001 1311 2621 5243 10486 001010 1442 2884 5767 11534 001011 1573 3146 6291 12583 001100 1704 3408 6816 13631 001101 1835 3670 7340 14680 001110 1966 3932 7864 15729 001111 2097 4194 8389 16777 010000 2228 4456 8913 17826 010001 2359 4719 9437 18874 010010 2490 4981 9961 19923 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 010101 2884 5767 11534 23069 010110 3015 6029 12059 24117 010111 3146 6291 12583 25166 011000 3277 6554 13107 26214 011001 3408 6816 13631 27263 011010 3539 7078 14156 28312 011011 3670 7340 14680 29360 011100 3801 7602 15204 30409 011101 3932 7864 15729 31457 011110 4063 8126 16253 32506 011111 4194 8389 16777 33554 100000 4325 kHz 8651 kHz 17302 kHz 34603 kHz 100001 4456 8913 17826 35652 100010 4588 9175 18350 36700 100011 4719 9437 18874 37749 100100 4850 9699 19399 38797 100101 4981 9961 19923 39846 100110 5112 10224 20447 40894 100111 5243 10486 20972 41943 1010
144. ference Signal for additional information SLOCK Synthesizer Lock 0 VCO is enabled but has not locked 1 VCO has locked on the desired frequency or system clock is external RSTEN Reset Enable 0 Loss of clock causes the MCU to operate in limp mode 1 Loss of clock causes system reset Refer to 4 7 Loss of Reference Signal for additional information MOTOROLA MEMORY MAP AND REGISTERS SIM B 4 REFERENCE MANUAL STSIM Stop Mode SIM Clock 0 SIM clock driven by the external reference signal and the VCO is turned off dur ing low power stop 1 SIM clock driven by VCO during low power stop This bit has an effect only if the PLL is configured to supply the clock signal MODCLK held high during reset Refer to 4 6 Low Power Stop Operation for additional infor mation STEXT Stop Mode External Clock 0 CLKOUT held low during low power stop 1 CLKOUT driven from SIM clock during low power stop Refer to 4 6 Low Power Stop Operation for additional information RSR Reset Status Register t 06 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED EXT POW SW DBF 0 LOC SYS TST EXT External Reset Reset was caused by an external signal POW Power On Reset Reset was caused by the power on reset circuit SW Software Watchdog Reset Reset was caused by the software watchdog circuit DBF Double Bus Fault Reset Reset was caused by a double bus fault LOC Loss
145. field in the option register ADDRO or SIZ bits to the BYTE field in the option register 16 bit ports only Priority of the interrupt being acknowledged ADDR 3 1 to the IPL field in the option register when the access is an interrupt acknowledge cycle When a match occurs the chip select signal is asserted The signal is asserted at the same time as or DS assertion if MODE 0 in the chip select option register chip se lect assertion is synchronized with ECLK if MODE 1 Chip select signals are active low gt P So S If a chip select function is given the same address as an internal microcontroller mod ule or an internal memory array access to the internal module or array has priority The chip select signal is not asserted and no external bus cycle occurs Figure 7 2 is a flow diagram for the assertion of chip select MOTOROLA CHIP SELECTS SIM 7 6 REFERENCE MANUAL BEGIN ADDRESS SPACE FC 2 0 2 NO MATCH BASE ADDR BITS 3 15 NO MATCH DEPENDING ON BLOCK SIZE INTERRUPT ACKNOWLEDGE CYCLE YES MATCH OR NO CHECK INTERRUPT PRIORITY LEVEL NO MATCH NO MATCH READ WRITE 16 BIT 8 BIT NO MATCH UPPER LOWER MATCH lt Figure 7 2 Flow Diagram for Chip Select Sheet 1 of 3 END CS IACK FLOW 1 SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 7 MODE 1 MODE 0 FALLING EDGE OF EC
146. from Table A 3 see table for complete notes 7 Characteristic Symbol Min Max Units 1 Clock Period 59 6 ns 1 Period tEcyc 476 ns 1B3 External Clock Input Period txcyc 59 6 ns 2 3 Clock Pulse Width tow 24 ns 2A 3A ECLK Pulse Width tecw 236 ns 2B 3B3 External Clock Input High Low Time 298 ms 4 5 Clock Rise and Fall Time tort 5 ns 4 5 ECLK Rise and Fall Time ter 8 ns 4B 5B External Clock Rise and Fall Time txcrt 5 ns NOTES 1 3 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted Minimum external clock high and low times are based on a 50 duty cycle The minimum allowable period will be reduced when the duty cycle of the external clock signal varies The relationship between external clock input duty cycle and minimum tycyc is expressed Minimum txcyc period minimum 50 external clock input duty cycle tolerance To achieve maximum operating frequency fsys while using an external clock input adjust clock input duty cycle to obtain a 5096 duty cycle on CLKOUT MOTOROLA ELECTRICAL CHARACTERISTICS SIM A 8 REFERENCE MANUAL 50 51 52 53 54 55 lt O gt lt 4 gt lt gt lt lt 13 AS 73 lt lt 74 BKP e A
147. g an 8 Bit Device to the MCU When connecting an 8 bit memory device or peripheral to the MCU connect the upper eight bits of the data bus DATA 15 8 to the eight data lines of the external device Connect high order address lines to the external chip select and lower order address lines to the corresponding address lines of the memory or peripheral Figure 5 22 shows the basic configuration MOTOROLA EXTERNAL BUS INTERFACE SIM 5 28 REFERENCE MANUAL 8 BIT MEMORY DEVICE GENERATOR ADDR x 0 DATA 15 8 DATA 7 0 8 BIT MEM CONN Figure 5 22 Connecting an 8 Bit Memory Device 5 7 2 Connecting a 16 Bit Memory Device to the MCU When connecting a 16 bit memory system to the MCU connect DATA 15 0 of the MCU to the sixteen data lines of the memory Since the memory is arranged in words 16 bits rather than bytes the address bus is incremented by two bytes with each suc cessive access To accommodate this connect ADDR1 of the MCU to ADDRO of the memory ADDR2 of the MCU to ADDR1 of the memory and so on Do not connect ADDRO of the MCU to the address bus of the memory system This method precludes writes to individual bytes all memory accesses are 16 bits wide To be able to write to individual bytes of the memory construct the memory sys tem as outlined in 5 7 3 Connecting Two 8 bit Memory Devices to the MCU or use chip selects as explained in 7 11 Interfacing Example with Chip Selects Figure 5 23 illustrates connecting a 16
148. gnal BG to indicate that the bus is available An external device asserts the bus grant acknowledge BGACK signal to indicate that it has assumed bus mastership BR may be issued any time during a bus cycle or between cycles BG is asserted in response to BR To guarantee operand coherency BG is only asserted at the end of operand transfer Additionally BG is not asserted until the end of an indivisible read modify write operation when RMC is negated on CPU32 based MCUs CPU16 based MCUs do not provide an RMC signal If more than one external device can be bus master required external arbitration must begin when a requesting device receives BG An external device must assert BGACK when it assumes mastership and must maintain BGACK assertion as long as it is bus master Two conditions must be met for an external device to assume bus mastership The de vice must receive BG through the arbitration process and BGACK must be inactive indicating that no other bus master is active This technique allows processing of bus requests during data transfer cycles BG is negated a few clock cycles after an external device asserts BGACK However if bus requests are still pending after BG is negated the MCU asserts BG again within a few clock cycles This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus Figure 5 36 is a flow chart of bus arbitration
149. grams 7 2 Chip Select Base Addresses Each chip select has an associated base address register The base address register specifies the base address and block size of the memory or peripheral enabled by the chip select A base address is the lowest address in the block of addresses enabled by a chip select Block size is the extent of the address block above the base address Block sizes of 2 Kbytes to 1 Mbyte can be selected Address blocks for separate chip select functions can overlap SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 3 On CPU16 based MCUs because the logic states of ADDR 23 20 follow that of ADDR19 a 1 Mbyte block size encoding is not support ed In addition on these MCUs be sure that the ADDR 23 20 bits in the base address register have the same value as ADDR19 to con form with the logic states of the corresponding address bus pins The BLKSZ field determines which bits in the base address field are compared to cor responding bits on the address bus during an access Provided other constraints de termined by option register fields are also satisfied when a match occurs the associated chip select signal is asserted Table 7 2 shows BLKSZ encoding Table 7 2 Block Size Encoding BLKSZ 2 0 Block Size Address Lines Compared ADDR 23 11 ADDR 23 13 ADDR 23 14 ADDR 23 16 ADDR 23 17 ADDR 23 18 110 512K ADDR 23 19 111 1M ADDR 23 20 Maximum block size 512
150. gure 4 1 is block diagram of the clock submodule and external circuitry with Daishinku DMX 38 32 768 kHz crystal providing the reference signal Figure 4 2 shows the clock submodule with a Daishinku KDS041 4 194 MHz crystal Resistor and capacitor values depend on the crystal type Refer to vendor documentation for recommended values In addition refer to 4 3 2 Crystal Tune up Procedure VDDSYN 22 2 330 22 pF2 da 0 1uF dl 10M VSSI VSSI 0 1uF 01uF VDDSYN Mo EXTAL XTAL XFC PIN o CRYSTAL PHASE LOW PASS OSCILLATOR COMPARATOR FILTER vco FEEDBACK DIVIDER CLKOUT gt SYSTEM CLOCK 1 Must be low leakage capacitor insulation resistance 30 000 or greater 2 Resistance and capacitance based on a test circuit constructed with a DAISHINKU DMX 38 32 768 kHz crystal Specific components must be based on crystal type Contact crystal vendor for exact circuit SYS CLOCK BLOCK 32KHZ Figure 4 1 System Clock with 32 768 kHz Reference Crystal MOTOROLA SYSTEM CLOCK SIM 4 2 REFERENCE MANUAL 4 194 MHz VDDSYN 22 pF2 15k 22pF2 i 0 1uF Vssi VSSI ow 01uF VSSI _ EXTAL p PIN VDDSYN I FEEDBACK DIVIDER e
151. he SIZ1 and SIZO pins respec tively During the second cycle the MCU drives 0 and 1 on these pins 5 3 2 Data and Size Acknowledge Signal Encoding The external device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK inputs If the processor attempts to write a word to an 8 bit port for example the DSACK pins inform the processor that the port is only 8 bits wide and the processor initiates a second bus cycle to write the remain ing byte Table 5 2 shows DSACK encodings MOTOROLA EXTERNAL BUS INTERFACE SIM 5 6 REFERENCE MANUAL Table 5 2 DSACK Signal Encodings DSACK1 DSACK0 Result 1 1 Insert Wait States in Current Bus Cycle 1 0 Complete Cycle Data Bus Port Size is 8 Bits 0 1 Complete Cycle Data Bus Port Size is 16 Bits 0 0 Reserved Defaults to 16 bit Port NOTE Some MCUs with reduced pin count SIMs do not contain DSACKO pin Refer to SECTION 10 REDUCED PIN COUNT SIM for details on handshaking with these MCUs Chip select logic can generate data and size acknowledge signals for an external de vice Refer to SECTION 7 CHIP SELECTS for details on generating DSACK signals with chip selects 5 3 3 Operand Alignment Operand alignment on the data bus is determined by the ADDRO SIZ 1 0 and 0 signals To understand operand alignment more fully refer to the individ ual cases described in 5 5 Operand Transfer Cases T
152. he following paragraphs sum marize the procedure the EBI follows for aligning operands The EBI dynamically determines the port size of the target device during each bus cy cle The EBI begins each bus cycle by assuming a 16 bit port and then determines the actual state of affairs based on the DSACK signals returned by the target device During a write cycle the EBI routes the bytes of the operand to the bytes of the data bus so that both 8 and 16 bit devices can retrieve the data The EBI signals the loca tion of the data to the target device through the SIZ 1 0 and ADDRO pins This scheme implies that in some cases both bytes of the data bus are copies of the same byte of the operand and that in some cases one of the bytes of the data bus will be unused by the target device During a read cycle the EBI uses the encoding of the DSACK 1 0 pins to determine the location of the valid data on the data bus This method implies that in some cases the EBI must reroute a byte of data internally to the operand latch and that sometimes a byte of data is ignored Table 5 3 indicates the location of valid data for each combination of operand size port size and even or odd address for read and write cycles Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed A 16 bit port must be connected to data bus bits 15 0 and an 8 bit port must be connected to data bus bits 15
153. hen an external device asserts BERR and HALT during a bus cycle the MCU enters the retry sequence shown in Figure 5 33 NOTE On CPU16 based MCUS assertion of BERR and HALT results in a bus error exception rather than a retry sequence The retry se quence is not available with these CPUs Refer to the appropriate CPU manual or to the user s manual for the specific device for de tails A delayed retry Figure 5 34 similar to the delayed bus error signal described previ ously can also occur The MCU terminates the bus cycle places the AS and DS sig nals in their inactive state and does not begin another bus cycle until the BERR and HALT signals are negated by external logic After a synchronization delay the MCU retries the previous cycle using the same address function codes data for a write and control signals The signal should be negated before S2 of the read cycle to ensure correct operation of the retried cycle If BR BERR and HALT are all asserted on the same cycle the EBI will enter the rerun sequence but first relinquishes the bus to an external master Once the external mas ter returns the bus and negates BERR and HALT the EBI runs the previous bus cycle This feature allows an external device to correct the problem that caused the bus error e g swap in a new page of memory and then try the bus cycle again The MCU retries any read or write cycle of an indivisible read modify write operation s
154. ic bus sizing using chip selects 7 7 Fast Termination Cycles With an external device that has a fast access time the chip select circuit fast termi nation option can provide a two cycle external bus transfer Select this option by as signing a value of 1110 to the field in the appropriate chip select option register Fast termination cycles are only available in conjunction with chip selects If multiple chip selects are to be used to select the same device that can support fast termination and match conditions can occur simultaneously select the fast termina tion option in the DSACK field of each associated chip select option register Alter nately select fast termination in one of the DSACK fields for external termination Fasttermination cycles use internal handshaking signals generated by the chip select logic To initiate a transfer the CPU asserts an address and the SIZ 1 0 signals When AS DS and R W are valid a peripheral device places data on the bus during a read cycle or latches data from the bus during a write cycle At the appropriate time chip select logic asserts data and size acknowledge signals Two clock states 52 and S3 that are normally required for external handshaking are eliminated during fast termi nation cycles To use the fast termination option an external device should be fast enough to have data ready within the specified setup time by the falling edge of S4 When using the fast termination
155. icant bit of each field is determined by the states of DATA 7 1 during reset An encoding of 11 configures the pin as a chip select for 16 bit port An encoding of 01 selects the alternate function for the pin DATA 2 0 determine the reset setting of CSPARO which controls pins CS 5 0 and CSBOOT See Table 7 6 Table 7 6 Reset Pin Function of CS 5 0 CSBOOT Mode Select Pin Default Function Alternate Function Pin Left High Pin Pulled Low DATAO CSBOOT 16 Bit CSBOOT 8 Bit DATA1 CSO BR TST BG CS2 BGACK DATA2 CS3 FC0 CS4 1 55 2 DATA 7 3 determine the reset setting of CSPAR1 which controls pins CS 10 6 If an external device pulls one of these data pins low the associated chip select pin and lower numbered pins controlled by CSPAR1 are configured as address pins coming out of reset For example if DATA6 is pulled low during reset pins CS 9 6 AD DR 22 19 are configured as address lines Table 7 7 summarizes the reset operation of pins controlled by CSPAR1 Table 7 7 Reset Pin Function of CS 10 6 Data Bus Pins at Reset Chip Select Address Bus Pin Function DATA DATA6 DATA5 DATA4 DATA3 CS10 59 58 57 56 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 CS10 CS9 CS8 CS7 CS6 CS10 CS9 CS8 CS7 ADDR19 CS10 CS9 CS8 ADDR20 ADDR19 CS10 CS9 ADDR21 ADDR20 ADDR19 510 ADDR22 ADDR21 ADDR20 ADDR19 ADDR23 ADDR22 ADDR21
156. ice does not have to respond in this case Chip select logic is typically used to generate an internal autovector signal when the corresponding chip select pin is used for an alternate function or for general purpose output Refer to 7 8 Using Chip Se lects in Interrupt Acknowledge Cycles for more information S0 52 54 50 521 522 S28 824 51 52 54 50 52 CLKOUT ADDR 23 4 X N ADDR 3 1 X X INTERRUPT LEVEL X va X 171 X N j AVEC E mum r READ gt lt INTERNAL lt WRITE CYCLE ARBITRATION STACK lt INTERRUPT ACKNOWLEDGE CYCLE AVEC IACK TIM Figure 6 5 Autovector Timing SIM INTERRUPTS MOTOROLA REFERENCE MANUAL 6 7 6 4 3 Spurious Interrupt Cycle When an interrupt request is made but no IARB field value is asserted in response to the interrupt acknowledge cycle the spurious interrupt monitor asserts the BERR sig nal internally to prevent vector acquisition When a responding device does not termi nate an interrupt acknowledge cycle with AVEC or DSACK the bus monitor asserts BERR internally The CPU automatically generates the spurious interrupt vector num ber F in both cases 6 5 Interrupt Processing Summary A summary of the entire interrupt processing sequence follows When the sequence begins a valid interrupt service request has been detected and
157. icrocontroller modules can assert interrupt request signals The SIM includes two sources of interrupt requests the periodic interrupt timer and the ex ternal bus interface The external bus interface routes external interrupt requests i e requests received from the interrupt request pins IRQ 7 1 to the CPU During inter rupt arbitration see 6 3 Interrupt Arbitration the CPU treats external interrupt re quests as though they come from the SIM NOTE MCUS with a reduced pin count SIM may not have all the interrupt request pins mentioned above Refer to the user s manual for the specific MCU for details When the CPU receives simultaneous interrupt requests of the same level see 6 2 In terrupt Level and Recognition from an interrupt request pin and the PIT the PIT is given priority The interrupt from the interrupt request pin remains pending until the next allowable interrupt time 6 2 Interrupt Level and Recognition Each of the interrupt request signals IRQ 7 1 corresponds to an interrupt priority level IRQ1 has the lowest priority and IRQ7 the highest For periodic timer interrupts the PIRQ field in the periodic interrupt control register PICR determines the priority level A priority level of 0 in the PICR means that PIT interrupts are inactive Interrupt recognition is based on the interrupt priority level and the interrupt priority mask value The interrupt priority mask consists of three bits in the CPU status regis
158. ied is affected by specific crystal parameters and by oscillator circuit de sign 8 4 1 SIM Operation During Power On Reset During power on reset an internal circuit in the SIM drives the IMB internal MSTRST and external EXTRST reset lines The power on reset circuit releases the internal re set line as Vpp ramps up to the minimum operating voltage refer to Table A 4 in AP PENDIX A ELECTRICAL CHARACTERISTICS and SIM pins are initialized to the values shown in Table 8 3 When Vpp reaches the minimum operating voltage the clock synthesizer VCO begins operation Clock frequency ramps up to the specified limp mode frequency Fi IMP The external RESET signal remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse MOTOROLA RESET AND SYSTEM INITIALIZATION SIM 8 6 REFERENCE MANUAL Figure 8 3 is a timing diagram of power on reset It shows the relationships between RESET Vpp and bus signals CLKOUT LOCK Vpp lt 512 CLOCKS 1 10 CLOCKS gt BUS CYCLES ADDRESS AND CONTROL SIGNALS THREE STATED BUS STATE UNKNOWN NOTES 1 Internal start up time 2 First instruction fetched CPU32 3 First instruction fetched CPU16 POR TIM Figure 8 3 Power On Reset Timing 8 4 2 Other Modules During Power On Reset The clock synthesizer in the SIM provides clock signals to other MCU modules After the clock is running and the internal reset signal MSTR
159. igure 7 4 shows CPU space encoding for an interrupt acknowledge cycle FC 2 0 are set to 96111 designating CPU space access ADDR 3 1 indicate interrupt priority and the space type field ADDR 19 16 is set to 961111 the interrupt acknowledge code The rest of the address lines are set to one CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 13 FUNCTION ADDRESS BUS CODE INTERRUPT ETE _ Gem enoe 1131113111113113121113 1 LVEL 1 NIA LU CPU SPACE TYPE FIELD CPU SPACE IACK TIM Figure 7 4 CPU Space Encoding for Interrupt Acknowledge Cycles When the chip select base and option registers are programmed to respond during an interrupt acknowledge cycle they must not be programmed to select an external de vice for reading or writing Normal data accesses occur in supervisor or user data space but interrupt acknowledge cycles occur in CPU space To select the device for reading or writing a separate chip select is needed from the one programmed to re spond during interrupt acknowledge cycles If a chip select circuit is used for AVEC support however the associated pin can still be used for discrete output or its alter nate function NOTE If chip select base and option registers are programmed to generate an AVEC or DSACK signal internally in response to a given interrupt level and an internal module generates an interrupt request of that level the internal module will supply an internal DSACK signal to ter minate the in
160. ilable as a programming option on ADDR23 Chip select registers include two global pin assignment registers a base address reg ister and option register for each chip select circuit and a data register The pin as signment registers assign pins individually for chip select operation discrete output or alternate functions The pin data register controls the state of pins programmed as discrete outputs The base address registers define the base address and block size to which the chip select responds The option registers determine timing of and condi tions for assertion of chip select signals 7 11 Interfacing Example with Chip Selects provides a diagram of a basic system that uses chip selects Figure 7 1 is a functional diagram of a single chip select circuit CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 1 10F 12 INTERNAL SIGNALS BASE ADDRESS REGISTER ADDRESS ADDRESS COMPARATOR Sn AND PIN BUS CONTROL OPTION COMPARE CONTROL OPTION REGISTER TuS PIN PIN AVEC DSACK AVEC GENERATOR GENERATOR s s DSACK lt Figure 7 1 Chip Select Circuit Block Diagram CHIP SEL BLOCK 7 1 Chip Select Options Chip select option registers determine timing of and conditions for assertion of chip select signals Constraints set by fields in the option register and in the base address register must all be satisfied in order to assert a chip select signal and to provide DSACK or autovector support The follow
161. in and that the crystal oscillator is stable Lock time is measured from power up to RESET release This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register SYNCR while the PLL is running and to the period required for the clock to lock after LPSTOP 3 Determined by the internal reference voltage applied to the on chip VCO The X bit in SYNCR controls a divide by two prescaler on the system clock output 4 Short term CLKOUT stability is the average deviation from programmed frequency measured over a 2 us interval at maximum fsys Long term CLKOUT stability is the average deviation from programmed frequency measured over a 1 ms interval at maximum fsys Stability is measured with a stable external clock input applied variation in crystal oscillator frequency is additive to this figure 5 This parameter is periodically sampled rather than 100 tested SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 1 Table 2 DC Characteristics Vpp and VDDSYN 5 0 10 Vss 0 Vdc Characteristic Symbol Min Max Unit Input High Voltage ViH 0 7 Vpp Vpp 0 3 V Input Low Voltage Vu Vss 0 3 0 2 Vpp V Input Hysteresis Vuys 0 5 V Input Leakage Current lin 2 5 2 5 uA Vin Vpp or Vss Input only pins High Impedance Off State Leakage Current loz Vin Vpp
162. in aspects of SIM operation however vary according to which CPU is present Whenever a feature being discussed is CPU dependent this manual refers the reader to the appropriate CPU reference manual or to the user s manual for a specific MCU The major differences between the CPU16 and CPUS2 that affect SIM operation are summarized in Table 1 3 SIM REFERENCE MANUAL INTRODUCTION MOTOROLA 1 7 Table 1 3 CPU Differences Affecting SIM Operation Feature CPU16 Operation CPU32 Operation Address Bus ADDR 23 20 follow state of ADDR19 All 24 lines are operational Module Mapping MM bit in SIMCR must equal 1 MM bit in SIMCR can equal 0 or 1 Each vector except reset vector is one Exception Vector Table word vector table is 512 bytes and is not relocatable there is no vector base register Each vector except reset vector is two words vector table is 1024 bytes and is relocatable base address is stored in vector base register Privilege Levels CPU always operates at supervisor privilege level FC2 always 1 CPU supports supervisor and user privilege levels FC2 is active according to privilege level Memory Partitions Memory partitioned into 16 banks of 64 Kbytes register extension fields sup port bank switching separate 1 Mbyte program and data spaces available Memory is fully accessible as 16 Mbyte program and data spaces RMC pin port E Pin may or may not be c
163. inations of clock mode STSIM and STEXT during low power stop and normal operation MODCLK value is the logic level on the MODCLK pin during the last reset prior to LPSTOP execution Any clock in the off state is held low Table 4 3 Clock Control Mode Pins SYNCR Bits Clock Source LPSTOP MODCLK EXTAL STSIM STEXT SIMCLK CLKOUT No 0 External X X External External Clock Clock Clock Yes 0 External 0 0 External Off Clock Clock Yes 0 External 0 1 External External Clock Clock Clock Yes 0 External 1 0 External Off Clock Clock Yes 0 External 1 1 External External Clock Clock Clock No 1 Crystal X X VCO VCO Reference Yes 1 Crystal 0 0 Crystal Off Reference Reference Yes 1 Crystal 0 1 Crystal Crystal Reference Reference Reference Yes 1 Crystal 1 0 VCO Off Reference Yes 1 Crystal 1 1 VCO VCO Reference 4 7 Loss of Reference Signal The state of the reset enable RSTEN bit in the SYNCR determines what happens when clock logic detects a reference failure When RSTEN is cleared the default state out of reset the clock synthesizer is forced into an operating condition referred to as limp mode Limp mode frequency varies from device to device but maximum limp frequency does not exceed one half maximum system when X 0 or maximum system clock frequency when X 1 When RSTEN is set the SIM generates a reset when clock logic detects a reference failure Refer to SECTION 8 R
164. ing fields in the option registers specify the conditions for assertion of the chip select signal These conditions must all be satisfied before chip select logic will respond The BYTE field determines whether to assert the chip select for an upper byte ac cess lower byte access both or neither disabled The R W field specifies whether to assert the chip select during a read cycle write cycle or both The SPACE field specifies whether to assert the chip select during a user space access supervisor space access user or supervisor access or CPU space ac cess The following fields specify chip select assertion timing DSACK specifies the number of wait states to insert before the chip select circuit asserts DSACK or specifies that the external device must provide the DSACK signal STRB specifies whether chip select assertion is synchronous with AS or DS This bit applies only when MODE 0 MODE determines whether the chip select cycle is synchronous with ECLK or emulates an asynchronous external bus cycle MOTOROLA CHIP SELECTS SIM 7 2 REFERENCE MANUAL The following fields determine chip select operation during interrupt acknowledge cles e AVEC determines whether to generate AVEC internally when match conditions specified in SPACE and IPL fields and base address register are satisfied IPL specifies the interrupt priority level to which the chip select responds e SPACE must be set to 00 CPU
165. ion on exception processing and background debugging mode On CPU32 based MCUs both hardware and software can initiate breakpoints CPU16 based MCUS support hardware initiated breakpoints only Refer to the appro priate CPU reference manual for details The following paragraphs discuss both types of breakpoints 5 8 1 1 Software Breakpoints The CPU32 BKPT instruction allows the user to insert breakpoints through software The CPU responds to this instruction by initiating a breakpoint acknowledge read cy cle in CPU space It places the breakpoint acknowledge 960000 code in AD DR 19 16 the breakpoint number bits 2 0 of the BKPT opcode in ADDR 4 2 and 950 indicating a software breakpoint in ADDR1 NOTE The CPU16 does not support the BKPT instruction The external breakpoint circuitry decodes the function code and address lines and re sponds by either asserting BERR or placing an instruction word on the data bus and asserting DSACK If the bus cycle is terminated by DSACK the CPU32 reads the instruction on the data bus and inserts the instruction into the pipeline For eight bit ports this instruction fetch may require two read cycles MOTOROLA EXTERNAL BUS INTERFACE SIM 5 32 REFERENCE MANUAL If the bus cycle is terminated by BERR the CPU32 then performs illegal instruction exception processing it acquires the number of the illegal instruction exception vector computes the vector address from this number lo
166. is pending A B The CPU finishes higher priority exception processing or reaches an instruction boundary The processor state is stacked On CPU16 based MCUs the PK extension field in the condition code register is cleared On CPU32 based MCUs the S bit in the status register is set establishing supervisor access level and bits T1 and TO are cleared disabling tracing The interrupt acknowledge cycle begins 1 FC 2 0 are driven to 96111 CPU space encoding 2 The address bus is driven as follows ADDR 23 20 951111 ADDR 19 16 961111 which indicates that the cycle is an interrupt acknowledge CPU space cycle ADDR 15 4 111111111111 ADDR S 1 the priority of the interrupt request being acknowledged and ADDRO 1 3 The request level is latched from the address bus into the interrupt priority mask field in the status or condition code register Modules or external peripherals that have requested interrupt service decode the priority value in ADDR 3 1 Each module or device with a request level equal to the value in ADDR 3 1 enters interrupt arbitration When there is no arbitration the spurious interrupt monitor asserts BERH and a spurious inter rupt exception is processed After arbitration the interrupt acknowledge cycle is completed in one of three ways 1 The interrupt source that wins arbitration supplies a vector number and DSACK signals appropriate to the access The CPU acquires the
167. iscrete Output CSPA1 4 CS10 ADDR23 ECLK CSPA1 3 CS9 ADDR22 PC6 CSPA1 2 CS8 ADDR21 PC5 CSPA1 1 CS7 ADDR20 PC4 CSPA1 0 CS6 ADDR19 PC3 MOTOROLA CHIP SELECTS SIM 7 18 REFERENCE MANUAL 7 10 2 Chip Select Base Address Registers CSBARBT contains the base address for selection of a bootstrap peripheral memory device Bit and field definition for CSBARBT and CSBAR 10 0 are the same but reset block sizes differ Refer to 7 2 Chip Select Base Addresses for more information CSBARBT Chip Select Base Address Register Boot ROM 1HHHIA8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 CSBAR 10 0 Chip Select Base Address Registers SIHHHIAC SIHHHIETA 15 14 13 12 11 10 9 8 f 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR BLKSZ 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 15 3 Base Address Field This field sets the starting address of a particular address space BLKSZ Block Size Field This field determines the size of the block above the base address that is enabled by the chip select 7 10 3 Chip Select Option Registers Option register fields determine timing of and conditions for assertion of chip select signals
168. ite tEcuw 0 ns E14 Address Access Time Read lEACC 386 ns E15 ChipSelect Access Time Read 326 ms E16 Address Setup Time teas 1 2 NOTES 1 All AC timing is shown with respect to 20 Vpp and 70 Vpp levels unless otherwise noted 2 When the previous bus cycle is not a synchronous ECLK bus cycle the address may be valid before ECLK goes low Address access time tEcyc tEAD tEpsR 4 Chip select access time 1 tecsp tEDSR 14 RMC signal is not supported on CPU16 based MCUs SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 23 50 51 52 53 54 55 50 51 52 53 54 aoc F N N N Z N 7 N N 7 SN 6 lt s lt gt lt gt 55 DATA 15 0 Son Le MOTOROLA A 24 Figure A 13 Chip Select Timing Diagram ELECTRICAL CHARACTERISTICS 68300 CHIP SEL TIM SIM REFERENCE MANUAL Table A 15 Key to Figure A 13 Abstracted from Table A 3 see table for complete notes Num Characteristic Symbol Min Units 61 Clock High to Address FC SIZE RMC Valid lcHAV 0 29 ns 874 Clock High to Address FC SIZE RMC Invalid tcHazn 0 ns 9 Clock Low to AS DS CS Asserted tcLsa 2 25 ns 111 Address FC SIZE Valid to AS CS
169. le bus monitor function for an internal to external bus cycle 1 Enable bus monitor function for an internal to external bus cycle SIM SYSTEM CONFIGURATION AND PROTECTION MOTOROLA REFERENCE MANUAL 3 11 1 0 Bus Monitor Timing This field selects bus monitor time out period Bus Monitor Period BMT Bus Monitor Time Out Period 00 64 System Clocks 01 32 System Clocks 10 16 System Clocks 11 8 System Clocks SIM SYSTEM CONFIGURATION AND PROTECTION REFERENCE MANUAL MOTOROLA 3 12 SECTION 4 SYSTEM CLOCK The system clock provides timing signals for the IMB modules and for an external pe ripheral bus Because the MCU is a fully static design register and memory contents are not affected when the clock rate changes An internal phase locked loop can syn thesize the clock from a reference frequency or the clock signal can be input from an external source 4 1 Clock Sources The state of the clock mode MODCLK pin during reset determines the source of the system clock When MODCLK is held high during reset the clock synthesizer gener ates a clock signal from the reference frequency The reference signal is the EXTAL input to the phase locked loop Refer to 4 2 Clock Synthesizer Operation Fre quency control bits in the clock synthesizer control register SYNCR determine the operating frequency When MODCLK is held low during reset and an external clock signal is applied to the EXTAL pin th
170. le read modify write operation which consists of one or more read cycles followed by one or more write cycles 5 4 1 Read Cycles During a read operation the MCU transfers data from an external memory or periph eral device A read operation consists of one or more read cycles If the instruction specifies a long word or word operation the MCU attempts to read two bytes per cy cle For a byte operation the MCU reads one byte The portion of the data bus from which each byte is read depends on operand size peripheral address and peripheral port size Refer to 5 3 Dynamic Bus Sizing for more information Figure 5 2 is a flow chart of a word read cycle MOTOROLA EXTERNAL BUS INTERFACE SIM 5 8 REFERENCE MANUAL MCU PERIPHERAL ADDRESS DEVICE S0 SET R W TO READ DRIVE ADDRESS ON ADDR 23 0 DRIVE FUNCTION CODE ON FC 2 0 DRIVE SIZ 1 0 FOR OPERAND SIZE ASSERT AS AND DS S1 PRESENT DATA S2 1 DECODE ADDR R W SIZ 1 0 DS 2 PLACE DATA ON DATA 15 0 OR DECODE DSACK 83 DATA 15 8 IF 8 BIT DATA 3 DRIVE DSACK SIGNALS LATCH DATA 54 NEGATE AS AND DS 55 TERMINATE CYCLE S5 1 REMOVE DATA FROM DATA BUS 2 NEGATE DSACK START NEXT CYCLE 50 RD CYC FLOW Figure 5 2 Read Cycle Flowchart A read cycle consists of the following states The designation state refers to the logic level of the clock signal and does not correspond to any implemented machine state A clock cycle con
171. led information about module operation and applications Refer to Motorola publication Advanced Microcontroller Unit AMCU Literature BR1116 D for a complete listing of documentation The following conventions are used throughout the manual Logic level one is the voltage that corresponds to Boolean true 1 state Logic level zero is the voltage that corresponds to Boolean false 0 state To set a bit or bits means to establish logic level one on the bit or bits To clear a bit or bits means to establish logic level zero on the bit or bits A signal that is asserted is in its active logic state An active low signal changes from logic level one to logic level zero when asserted and an active high signal changes from logic level zero to logic level one A signal that is negated is in its inactive logic state An active low signal changes from logic level zero to logic level one when negated and an active high signal changes from logic level one to logic level zero LSB means least significant bit or bits MSB means most significant bit or bits Ref erences to low and high bytes are spelled out A specific bit or signal within a range is referred to by mnemonic and number For example ADDR15 is bit 15 of the address bus A range of bits or signals is referred to by mnemonic and the numbers that define the range For example DATA 7 0 form the low byte of the data bus PREFACE MOTOROLA REFERENCE MANUAL SECTION 1INTRODUCTION
172. logic level one The CPU16 does not sup port the RMC function for this pin PFPAR Port F Pin Assignment Register IHHHH E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PFPA7 PFPA6 PFPA5 4 PFPA2 1 PFPA0 DATA9 DATA9 DATA9 9 9 DATA9 DATA9 DATA9 Any bit cleared to zero defines the corresponding pin to be an pin Any bit set to one defines the corresponding pin to be an interrupt request signal or MODCLK Table 9 2 Port F Pin Assignments PFPAR Field Port F Signal Alternate Signal PFPA7 PF7 IRQ7 PFPA6 PF6 IRQ6 5 5 IRQ5 PFPA4 PF4 IRQ4 PFPA3 PF3 IRQ3 PFPA2 PF2 IRQ2 PFPA1 PF1 IRQ1 PFPA0 PF0 MODCLK 9 2 Data Direction Registers Bits in the port E and port F data direction registers DDRE and control the di rection of the pin drivers when the pins are configured for I O Any bit in a register set to one configures the corresponding pin as an output Any bit in a register cleared to zero configures the corresponding pin as an input These registers can be read or writ ten at any time In MCUs in which the RMC pin is not implemented DDE3 always re turns one when read and writes have no effect MOTOROLA GENERAL PURPOSE SIM 9 2 REFERENCE MANUAL DDRE Port E Data Direction Register 4 15 14
173. monitor is disabled SLVEN Factory Test Slave Mode Enabled 0 IMB is not available to an external tester 1 An external tester has direct access to the IMB SHEN 1 0 Show Cycle Enable This field determines what the external bus interface does with the external bus during internal transfer operations Refer to 5 11 Show Cycles for more information SHEN Action 00 Show cycles disabled external arbitration enabled 01 Show cycles enabled external arbitration disabled 10 Show cycles enabled external arbitration enabled 11 Show cycles enabled external arbitration enabled internal activity is halted by a bus grant SUPV Supervisor Unrestricted Data Space 0 Registers with access controlled by this bit are unrestricted 1 Registers with access controlled by this bit are restricted to supervisor access only MM Module Mapping 0 Internal modules are addressed from 7FF000 7FFFFF 1 Internal modules are addressed from FFF000 This bit can be written only once Subsequent attempts to change this bit are ignored Address space 7FF000 7FFFFF is inaccessible to the CPU16 On CPU16 based microcontrollers MM must always be set Initialization software for these MCUs should make certain MM remains set its reset state by writing a one to it SIM MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 3 IARB 3 0 Interrupt Arbitration Field IARB determines SIM inter
174. mple when a 32 768 kHz crystal reference frequency is being used to gener ate the system clock and the PIT prescaler is disabled PTP 0 PIT period is deter mined as follows PIT Period PIT Modulus 1 4 32768 PIT Modulus 8192 This results in a PIT period ranging from 122 us when PITM 01 to 31 128 ms when PITM FF With the same 32 768 kHz reference crystal and the prescaler enabled 1 PIT Period PIT Modulus 512 4 32768 PIT Modulus 16 This results in a PIT period ranging from 62 5 ms when PITM 01 to 15 94 s when PITM FF For fast calculation of periodic timer period using a 32 768 kHz crystal reference fre quency the following equations can be used With prescaler disabled PIT Period PIT Modulus 122 us With prescaler enabled PIT Period PIT Modulus 62 5 ms To use the periodic interrupt timer as a real time clock interrupt rearrange the periodic timer period equation to solve for the desired count value For a timer period of one second for example with the prescaler enabled PIT Modulus PIT Period EXTAL Prescaler 4 1 32768 512 4 16 Therefore the PITR should be loaded with a value of 10 16 decimal with the pres caler enabled to generate interrupts at a 1 s rate 3 6 2 Interrupt Priority and Vectoring Interrupt priority and vectoring are determined by the values of the periodic interrupt request level PIRQL and periodic interrupt vector PIV fields i
175. mption that an external device is driving the pin low At the end of this period the pin again goes to a high impedance state for 10 cycles and then is tested again The process repeats until RESET goes high Refer to parameters 77 and 78 in Table A 3 in APPENDIX A ELECTRICAL CHAR ACTERISTICS for additional timing details regarding RESET assertion and negation 8 3 2 Internal Reset Request When reset is requested by any source other than an external device driving the RE SET pin low the reset control logic asserts RESET for a minimum of 512 cycles al lowing the weak pull up devices on the data bus configuration pins to pull the pins up to logic level one If the reset signal is still asserted at the end of 512 cycles the control logic continues to assert RESET until the internal reset signal is negated 8 4 Power On Reset When the SIM clock synthesizer is used to generate the system clock power on reset involves special circumstances related to the application of system and clock synthe sizer power Regardless of clock source voltage must be applied to clock synthesizer power input pin Vppsyn in order for the MCU to operate The following discussion as sumes that VppsvN is applied before and during reset minimizing crystal start up time When this is not the case start up time includes crystal cold start up time in ad dition to the delays listed in the following paragraphs Crystal start up time without VDDSYN appl
176. n to be an pin Any bit set to one configures the corresponding pin for its alternate function NOTE On CPU16 based MCUs the RMC signal is not implemented and the RMC PE3 pin may be left unconnected When the pin is left un connected always returns one when read and writes have no effect The states of the DATA8 and DATA9 pins control the reset state of PEPAR and PF PAR respectively When DATAS is high during reset PEPAR is set to FF defining all port E pins to be bus control signals When DATAS is low during reset PEPAR is set to 00 defining all port E pins to be I O pins In a similar fashion DATA9 deter mines the reset state of PFPAR PEPAR Port E Pin Assignment Register 1HHHI6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PEPA7 PEPA6 5 4 2 PEPA1 PEPAO RESET DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 Any bit cleared to zero defines the corresponding pin to be an I O pin Any bit set to one defines the corresponding pin to be a bus control signal SIM GENERAL PURPOSE MOTOROLA REFERENCE MANUAL 9 1 Table 9 1 Port E Pin Assignments PEPAR Bit Port E Signal Bus Control Signal PEPA7 PE7 171 SIZO PEPA5 PE5 AS PEPA4 PE4 DS RMC PEPA2 PE2 AVEC PEPA1 PE1 DSACK1 PEPA0 PE0 DSACK0 On CPU16 based MCUs when PEPA3 is set the PE3 pin if connected goes to
177. n Table 4 2 are valid for typical values of 32 768 kHz and 4 194 MHz crystal references SIM SYSTEM CLOCK MOTOROLA REFERENCE MANUAL 4 7 values that exceed specifications Table 4 1 Clock Control Multipliers To obtain the clock frequency find the counter modulus in the leftmost column then multiply the reference frequency by the value in the appropriate prescaler cell For 4 194 MHz reference crystals first divide by 128 Shaded cells contain Modulus Prescalers Y W X 00 W X 01 W X 10 W X 11 000000 4 8 16 32 000001 8 16 32 64 000010 12 24 48 96 000011 16 32 64 128 000100 20 40 80 160 000101 24 48 96 192 000110 28 56 112 224 000111 32 64 128 256 001000 36 72 144 288 001001 40 80 160 320 001010 44 88 176 352 001011 48 96 192 384 001100 52 104 208 416 001101 56 112 224 448 001110 60 120 240 480 001111 64 128 256 512 010000 68 136 272 544 010001 72 144 288 576 010010 76 152 304 608 010011 80 160 320 640 010100 84 168 336 672 010101 88 176 352 704 010110 92 184 368 736 010111 96 192 384 768 011000 100 200 400 800 011001 104 208 416 832 011010 108 216 432 864 011011 112 224 448 896 011100 116 232 464 928 011101 120 240 480 960 011110 124 248 496 992 011111 128 256 512 1024 100000 132 264 528 1056 100001 136 272 544 1088 100010 140 280 560 1120 100011 144 288 576 1152 100100
178. n external frequency source is used The value of the periodic timer prescaler PTP bit in the periodic interrupt timer register PITR determines system clock prescaling for the watchdog timer Either no prescal ing or prescaling by a factor of 512 can be selected During reset the state of the MODCLK pin which also determines the source of the system clock determines the value of PTP as shown in Table 3 4 System software can change the PTP value Table 3 4 MODCLK Pin and PTP Bit During Reset MODCLK PTP Watchdog Prescaling 0 External Clock 1 512 1 Internal Clock 0 1 Either clock signal EXTAL EXTAL 512 is divided by four before driving the mod ulus counter PITCLK The modulus counter is initialized by writing a value to the pe riodic timer modulus PITM field in the PITR A zero value turns off the periodic timer SIM SYSTEM CONFIGURATION AND PROTECTION MOTOROLA REFERENCE MANUAL 3 7 When the modulus counter value reaches zero interrupt is generated The modu lus counter is then reloaded with the value in PITM and counting repeats If a new val ue is written to the PITM field it is loaded into the modulus counter when the current count is completed Use the following equation to calculate timer period with a 32 768 kHz reference fre quency with a 4 194 MHz reference first divide the EXTAL frequency by 128 PIT Period PIT Modulus Prescaler value 4 EXTAL Frequency For exa
179. n instruction is terminated by assertion of BERR The number of bus cycles in the instruction during which BERR is asserted The number of bus cycles in the instruction following the instruction in which BERR is asserted Whether is asserted during a program space access or a data space cess Because of these factors it is impossible to predict precisely how long after occur rence of a bus error the bus error exception will be processed CAUTION The external bus interface does not latch data when an external bus cycle is terminated by a bus error When this occurs during an in struction prefetch the IMB precharge state bus pulled high or FF is latched into the CPU instruction register with indeterminate re sults The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them If a bus error occurs on an instruction fetch the CPU does not take the exception until it attempts to use that instruction word Should an in MOTOROLA EXTERNAL BUS INTERFACE SIM 5 40 REFERENCE MANUAL tervening instruction cause a branch or should a task switch occur the bus error ex ception does not occur When the MCU recognizes a bus error condition it terminates the current bus cycle in the normal way Figure 5 31 shows the timing of a bus error for the case in which DSACK is not asserted Figure 5 32 shows the timing for a bus error that is asserted after DSAC
180. n involving a 16 bit port SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 25 50 52 54 50 S2 54 50 52 54 80 S2 54 50 52 54 0 52 54 wV TT TTTFTFTMNMLELLLILLELLEg AS N N N N N N SUN SHE I Susa sama 4BYTES 2 BYTES 2 BYTES 4 BYTES 2 BYTES 2 BYTES sa o s DATA 7 0 1 OP3 1 OP3 1 WORD READ WORD amp LONG WORDREAD gt FROM gt lt LONG WORD WRITE TO gt WRITETO FROM 16 BIT BUS 16 BIT BUS 16 BIT BUS 16 BIT BUS LONG WORD R W TIM Figure 5 20 Timing of Long Word Read or Write 16 Bit Port 5 5 11 Long Word Operand to 16 Bit Port Misaligned The CPU16 treats misaligned long word transfers as two misaligned word transfers The MCU drives the address bus with the desired address and drives the size pins to indicate a word operand The MCU also drives the function code and R W pins to ap propriate values NOTE The CPU32 does not support transfers of misaligned operands MOTOROLA EXTERNAL BUS INTERFACE SIM 5 26 REFERENCE MANUAL 1 2 Data Bus 15 8 7 0 121 120 ADDRO DSACK1 DSACKO Cycle 1 1 0 1 0 1 Cycle 2 1 1 0 1 0 0 1 Cycle 3 OP2 OP2 1 0 1 0 1 Cycle 4 OP3 OP3 0 1 0 0 1 Figure 5 21 Long Word Operand to 16 Bit Port Misaligned For a read operation the peripheral
181. n the periodic interrupt control register PICR MOTOROLA SYSTEM CONFIGURATION AND PROTECTION SIM 3 8 REFERENCE MANUAL The content of PIRQL is compared to the CPU interrupt priority mask to determine whether the interrupt is recognized Table 3 5 shows the priority of PIRQL values Due to SIM hardware prioritization a PIT interrupt is serviced before an external interrupt request of the same priority The periodic timer continues to run when the interrupt is disabled Table 3 5 Periodic Interrupt Priority PIRQL Priority Level 000 Periodic Interrupt Disabled 001 Interrupt Priority Level 1 010 Interrupt Priority Level 2 011 Interrupt Priority Level 3 100 Interrupt Priority Level 4 101 Interrupt Priority Level 5 110 Interrupt Priority Level 6 111 Interrupt Priority Level 7 The PIV field contains the periodic interrupt vector The vector is placed on the IMB when an interrupt request is made The method for calculating the vector address from the vector number depends on the CPU Refer to the appropriate CPU reference man ual or to the user manual for the particular MCU for this information Refer to SECTION 6 INTERRUPTS of this manual for additional details concerning interrupt exception processing Reset value of the PIV field is 0F which generates the uninitialized interrupt vector 3 7 Low Power Stop Operation When the CPU executes the LPSTOP instruction the current interrupt priority mask is stor
182. nate and halt BERR NA NA Continue when HALT is negated HALT A S S 3 DSACK NA A X Bus error termination terminate and take bus error BERR A S exception possibly deferred HALT NA X 4 DSACK A X Bus error termination terminate and take bus error 5 exception possibly deferred HALT NA NA 5 DSACK NA A X Retry termination terminate and retry when HALT is BERR A S negated The result is a bus error termination rather HALT A S S than retry termination on CPU16 based MCUs 6 DSACK A X Retry termination terminate and retry when HALT is BERR NA A negated The result is a bus error termination rather HALT NA A than retry termination on CPU16 based MCUs NOTES N The number of current even bus state S2 S4 etc Signal is asserted in this bus state NA Signal is not asserted in this state Don t care S Signal was asserted in previous state and remains asserted in this state To properly control termination of a bus cycle for a retry or a bus error condition DSACK BERR and HALT must be asserted and negated with the rising edge of the MCU clock This ensures that when two signals are asserted simultaneously the re quired setup time and hold time for both of them are met for the same falling edge of the MCU clock Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for timing requirements External circuitry that provides these signals must be designed with these constraints in mind or else the internal bu
183. nd terminate the bus cycle by asserting DSACK ternately an external device that wins arbitration can assert the autovector AVEC signal to request that the CPU supply a vector number The process is described in 6 4 Interrupt Acknowledge Bus Cycles 6 4 Interrupt Acknowledge Bus Cycles The MCU acknowledges an interrupt request by performing a read cycle in CPU space to obtain the interrupt vector number The interrupt acknowledge cycle differs from the read cycle described in 5 4 1 Read Cycles in the following ways e FC 2 0 are set to 95111 the CPU space encoding ADDR 19 16 the CPU space type field are set to 1111 the interrupt acknowl edge encoding e ADDR 3 1 are set to the interrupt request level All remaining address bits are set SIZ 1 0 and R W are driven to indicate a single byte read cycle Figure 6 1 shows the encoding of the address and function code lines for an interrupt acknowledge read cycle FUNCTION ADDRESS BUS CODE INTERRUPT ZUR Eee eee Loe ee a cee 11 CPU SPACE TYPE FIELD CPU SPACE IACK TIM Figure 6 1 Interrupt Acknowledge Read Cycles SIM INTERRUPTS MOTOROLA REFERENCE MANUAL 6 3 Interrupting devices must decode ADDR 3 1 to determine which device or devices ter interrupt arbitration The responding devices must also decode SIZ 1 0 for dynam ic bus allocation An interrupt acknowledge cycle is completed in one of three ways When
184. nitor Enable 0 When FREEZE is asserted the bus monitor continues to operate 1 When FREEZE is asserted the bus monitor is disabled SLVEN Factory Test Slave Mode Enabled 0 IMB is not available to an external tester 1 An external tester has direct access to the IMB SHEN 1 0 Show Cycle Enable This field determines what the external bus interface does with the external bus during internal transfer operations Refer to 5 11 Show Cycles for more information SHEN Action 00 Show cycles disabled external arbitration enabled 01 Show cycles enabled external arbitration disabled 10 Show cycles enabled external arbitration enabled 11 Show cycles enabled external arbitration enabled internal activity is halted by a bus grant SUPV Supervisor Unrestricted Data Space 0 Registers with access controlled by this bit are unrestricted 1 Registers with access controlled by this bit are restricted to supervisor access only MM Module Mapping 0 Internal modules are addressed from 7FF000 7FFFFF 1 Internal modules are addressed from FFF000 FFFFFF This bit can be written only once Subsequent attempts to change this bit are ignored Address space 7FF000 7FFFFF is inaccessible to the CPU16 On CPU16 based microcontrollers MM must always be set Initialization software for these MCUs should make certain MM remains set its reset state by writing a one to it IARB 3 0 Interrup
185. nment Field EDCOGIDO seio oic vans etes 7 5 BY TE Field Ericodlg uu u 7 11 Reset Pin Function of CS 5 0 CSBOOT 7 16 Reset Pin Function of CS 0 6 ces 7 16 CSBOOT Base and Option Register Reset 7 17 CSPARO Pin ASSIGMINGING uu uu edd Ear REI E M HU UE 7 18 CSPAR1 Pin Assignments ele eue Fee ben eee 7 18 SOURCES Mie Q 8 3 Reset Mode Selection 8 8 SIM Pin Reset States 2 8 12 SIM Registers Out of Reset nasa vance A ee aaa aA 8 13 Port E a dese EET Ma era ec tee eu 9 2 Port u editio eL ro eb e t dd pL 9 2 Optional RP SIM PIS oco o peor tet p nep patr Erde 10 1 Clock Control Timing a te MD 1 DC Characteristics UN A 2 LEUTE RE A 4 MOTOROLA REFERENCE MANUAL xi LIST OF TABLES Continued Table Title Page A 4 BUS tices u u aaa A 6 A 5 Key to Figures gt AE A tee co oda A 8 A 6 Key to Figure A 4 dcm A 10 A 7 Key to me OAS i o A 12 A 8 Key to Figure A O a E kee A 13 A 9 Key TO Figure AFT eiua e
186. not check DSACK response on the external bus unless the CPU ini tiates a bus cycle The BME bit in the SYPCR enables the internal bus monitor for in ternal to external bus cycles If a system contains external bus masters an external bus monitor must be implemented and the internalto external bus monitor option must be disabled Refer to 3 8 System Protection Registers for a register diagram of the SYPCR 3 3 Halt Monitor The halt monitor responds to an assertion of HALT on the internal bus Refer to 5 9 Bus Error Processing for more information Halt monitor reset can be inhibited by the halt monitor enable HME bit in the SYPCR Refer to 3 8 System Protection Regis ters for a register diagram of the SYPCR 3 4 Spurious Interrupt Monitor During interrupt exception processing the CPU normally acknowledges an interrupt request arbitrates among various sources of interrupt recognizes the highest priority source and then acquires a vector or responds to a request for autovectoring The spurious interrupt monitor asserts the internal bus error signal BERR if no interrupt arbitration occurs during interrupt exception processing The assertion of BERR caus es the CPU to load the spurious interrupt exception vector into the program counter The spurious interrupt monitor cannot be disabled Refer to SECTION 6 INTER RUPTS for a comprehensive discussion of interrupts and to 5 9 Bus Error Process ing for a discussion of bus error exceptions
187. o 16 Bit Port Misaligned 5 20 5 5 8 Long Word Operand to 8 Bit Port Aligned 5 20 5 5 9 Long Word Operand 8 Bit Port Misaligned 5 23 5 5 10 Long Word Operand to 16 Bit Port Aligned 5 24 5 5 11 Long Word Operand to 16 Bit Port Misaligned 5 26 5 6 Function Codes and Memory Usage 5 27 5 7 System Interfacing Examples 5 28 5 7 1 Connecting 8 Bit Device to the MCU 5 28 5 7 2 Connecting a 16 Bit Memory Device to the 5 29 5 7 3 Connecting Two 8 bit Memory Devices to the MCU 5 30 5 8 CPU Space Cycles TL 5 31 5 8 1 Breakpoint Acknowledge Cycle 5 32 5 8 1 1 Software Breakpoints 5 32 5 8 1 2 Hardware Breakpoints 5 33 5 8 2 LPSTOP Broadcast Cycle 5 38 5 9 Bus Error Processing i An EE 5 38 5 9 1 Bus Error Exceptions 5 40 5 9 2 Double Bus Faults 2 5 42 5 9 3 Retry
188. o understand SIM operation during and after reset refer to SECTION 8 RESET AND SYSTEM INITIALIZATION The logic states of certain data bus pins during reset determine the function of SIM pins that can be assigned to more than one function In addition the state of the DATA11 pin determines whether test mode is enabled the state of the MODCLK pin determines the source of the system clock and the state of the BKPT pin determines what happens during subsequent breakpoint assertions Table 1 2 is a summary of re set mode selection options MOTOROLA 1 6 INTRODUCTION SIM REFERENCE MANUAL Table 1 2 SIM Reset Mode Selection Mode Select Pin Default Function Alternate Function Pin Left High Pin Pulled Low DATA0 CSBOOT 16 Bit CSBOOT 8 Bit DATA1 CS0 BR CS1 BG CS2 BGACK DATA2 53 54 1 55 2 DATA3 CS6 ADDR19 DATA4 5 7 6 ADDR 20 19 DATA5 CS 8 6 ADDR 21 19 DATA6 CS 9 6 ADDR 22 19 CS 10 6 ADDR 23 19 DATA8 DSACKO DSACK1 PORTE AVEC DS AS SIZE DATA9 IRQ 7 1 PORTF MODCLK DATA11 Test Mode Disabled Test Mode Enabled MODCLK VCO System Clock EXTAL System Clock BKPT Background Mode Disabled Background Mode Enabled 1 3 CPU Specific Differences Affecting SIM Operation This reference manual can be used with Motorola modular MCUs that contain a sys tem integration module regardless of whether the chip contains CPU16 or CPU32 Certa
189. oducts use the MOVEP move peripheral data instruction to move data to and from even addresses Refer to the CPU32 reference manual for details 10 4 RMC Pin The CPU32 asserts the RMC signal to indicate that the current bus cycle is part of an indivisible read modify write instruction The CPU16 does not support this signal On CPU16 based MCUs the pin may or may not be available for discrete If the pin is not available a read of PE3 will always return either zero or one depending on the particular MCU Refer to the user s manual for the particular CPU16 based MCU to determine how PE3 is implemented MOTOROLA REDUCED PIN COUNT SIM SIM 10 2 REFERENCE MANUAL APPENDIX AELECTRICAL CHARACTERISTICS Table A 1 Clock Control Timing Vpp and VpDSYN 5 0 10 Vss 0 32 768 kHz or 4 194 MHz reference Characteristic Symbol Min Max Unit PLL Reference Frequency Range fret 25 50 kHz System Frequency dc 16 78 On Chip PLL System Frequency fsys 0 131 16 78 MHz External Clock Operation dc 16 78 PLL Lock Time tipi 20 ms Limp Mode Clock Frequency SYNCR X bit 0 flimp fsys max 2 MHz SYNCR X bit 1 max CLKOUT Stability gt Short term Cstab 1 0 1 0 Long term 0 5 0 5 NOTES 1 All internal registers retain data at 0 Hz 2 Assumes that stable VppsvN is applied that an external filter capacitor with a value of 0 1 uF is attached to the XFC p
190. odule that can make an interrupt service request including the SIM has an IARB field in its configuration register An IARB field can be assigned a value from 950001 lowest priority to 961111 highest priority A value of 960000 an IARB field causes the CPU to process a spurious interrupt exception when an interrupt from that module is recognized MOTOROLA INTERRUPTS SIM 6 2 REFERENCE MANUAL Because the EBI manages external interrupt requests the SIM IARB value is used for arbitration between internal and external interrupt requests The reset value of IARB for the SIM is 1111 and the reset IARB value for all other modules is 0000 Initial ization software must assign different IARB values in order to implement an arbitration scheme WARNING Do not assign the same level and arbitration priority to more than one module When two or more IARB fields have the same nonzero val ue the CPU interprets multiple vector numbers simultaneously with unpredictable consequences Arbitration must always take place even when a single source is requesting service This point is important for two reasons the EBI does not transfer the CPU interrupt ac knowledge cycle to the external bus unless the SIM wins contention and failure to con tend causes the interrupt acknowledge bus cycle to be terminated early by a bus error When arbitration is complete the module that wins contention must place an interrupt vector number on the data bus a
191. of Clock Reset Reset was caused by loss of clock reference signal SYS System Reset Reset was caused by the CPU32 RESET instruction The CPU16 does not support this instruction TST Test Submodule Reset Reset was caused by the test submodule This bit is set during system test only SIMTRE System Integration Test Register ECLK HH 08 The SIMTRE is used for factory test only PORTE0 PORTE1 Port E Data Register SHHHH10 SHHH112 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 U U U U U U U U SIM MEMORY MAP AND REGISTERS MOTOROLA REFERENCE MANUAL B 5 DDRE Port E Data Direction Register IHHHHA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDEO RESET 0 0 0 0 0 0 0 0 PEPAR Port E Pin Assignment Register 1HHHI6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PEPA7 PEPA6 5 4 PEPA2 PEPA1 PEPAO RESET DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 Any bit cleared to zero defines the corresponding to be an I O pin Any bit set to one defines the corresponding pin to be a bus control signal Table B 2 Port E Pin Assignments PEPAR Bit Port E Signal Bus Control Signal PEPA7 PE7 171 120 5 5 AS PEPA4 PE4 DS
192. of crystal causes limp mode not reset 1 STSIM 0 If LPSTOP disable system clock 0 STEXT 0 If LPSTOP disable external clock PICR 10 8 PIRQL 000 Periodic interrupt disabled 7 0 PIV 00001111 Vector number F uninitialized interrupt vector PITR 8 PTP MODCLK If MODCLK is low 1 PIT prescaled by 512 If MODCLK is high PTP 0 PIT not prescaled 7 0 PITM 00000000 Periodic timer disabled PORTE 7 0 PE Unchanged Port E data register is unaffected by reset DDRE 7 0 DDE 00000000 PortE pins are configured for input PEPAR 7 0 DATA8 If DATAB 0 pins configured for G P If DATA8 1 pins configured for bus control PORTF 7 0 Unchanged Port F data register is unaffected by reset DDRF 7 0 DDF 00000000 F pins are configured for input PFPAR 7 0 PFPA DATAS DATA 0 pins configured for If 1 pins configured for interrupt request MODCLK for PFO PORTC 6 0 PC 1111111 Port C data register bits 6 0 set to 1 CSPAR1 9 0 See Table 7 7 CSPARO 13 0 See Table 7 6 CSBARBT 15 3 AD 0 Base address 0 DR 23 11 2 0 BLKSZ 111 Block size 1 Mbyte CSBAR 10 0 15 3 AD 0 Base address 0 DR 23 1 1 2 0 BLKSZ 000 Block size 2 Kbytes REFERENCE MANUAL RESET AND SYSTEM INITIALIZATION MOTOROLA 8 13 Table 8 4 SIM Registers Out of Reset Continued Register Bits Name Value Meaning CSORBT 15 MODE 0 Asynchronous mode 14 13 BYTE 11 Both bytes 12 11 RW 11 Assert chip selec
193. of the bus cycle When a bus cycle does not termi nate normally the bus monitor terminates it based on the length of time programmed in the BMT field of the system protection control register Refer to 3 2 Internal Bus Monitor for additional information 8 2 Sources of Reset Sources of reset include external reset requests the power on reset circuit the soft ware watchdog monitor the double bus fault monitor the loss of crystal circuitry and the CPU32 RESET instruction system reset The reset status register RSR con tains a status bit for every reset source in the EBI NOTE The RESET instruction is a CPUS2 instruction the CPU16 does not support it Table 8 1 is a summary of reset sources MOTOROLA RESET AND SYSTEM INITIALIZATION SIM 8 2 REFERENCE MANUAL Table 8 1 Reset Sources Type Source Timing Cause Lines Asserted by Reset Controller External External Synch External Signal MSTRST CLKRST EXTRST Power Up EBI Asynch VDD MSTRST CLKRST EXTRST Software Watchdog SW Monitor Asynch Time Out MSTRST CLKRST EXTRST Double Bus Fault DBF Monitor Asynch Double Bus Fault MSTRST CLKRST EXTRST Loss of Clock Clock Synch Loss of Reference MSTRST CLKRST EXTRST Test Test Synch Test Mode MSTRST EXTRST System CPU32 Asynch RESET Instruction EXTRST 8 2 1 External Reset When the EXT bitin the RSR is set the most recent was caused by an external device asserting RESET
194. old time for memory systems R W SIZ 1 0 and FC 2 0 also re main valid throughout S5 The external device must assert the DSACK signals until it detects the negation of either AS or DS It must negate DSACK within approximately one clock period after sensing the negation of AS or DS Signals that remain asserted beyond this limit can be prematurely detected during the next bus cycle Figure 5 5 is a timing diagram of a write cycle MOTOROLA EXTERNAL BUS INTERFACE SIM 5 12 REFERENCE MANUAL 50 52 54 50 lt lt WRITE gt RD MOD WR WR TIM Figure 5 5 Write Cycle Timing Diagram 5 4 3 Indivisible Read Modify Write Sequence The indivisible read modify write sequence provides semaphore capabilities for multi processor systems This sequence performs a read conditionally modifies the data in the arithmetic logic unit and may write the data out to memory During the entire read modify write sequence the MCU asserts the RMC signal to indicate that an indivisible operation is occurring The MCU does not issue a bus grant BG signal in response to a bus request BR signal during this operation The 2 test and set TAS instruction is the only instruction that generates an in divisible read modify write memory cycle Refer to the CPU32 Reference Manual CPU32RM AD for information on this instruction NOTE The CPU16 does not support the RMC signal or the TAS instruction Figure 5 6 is an example of a f
195. onnected for I O RMC function not supported for indivisible read modify write operations Pin connected port E fully operational RMC asserted during indivisible read modify write operations Misaligned Transfers Misaligned transfers are allowed Misaligned transfers are not supported Retry Operation Retry operation not supported Assertion of BERR and HALT results in retry sequence MOTOROLA 1 8 INTRODUCTION SIM REFERENCE MANUAL SECTION 2 SIGNAL AND PIN DESCRIPTIONS The tables in this section summarize functional characteristics of SIM pins For a more detailed discussion of a particular signal refer to the section of this manual that dis cusses the SIM function or submodule involved Refer to SECTION 8 RESET AND SYSTEMIINITIALIZATION for details on pin state during and after system reset NOTE On MCUs with a reduced pin count SIM some of the pins described in this section may not be available Refer to SECTION 10 RE DUCED PIN COUNT SIM for additional information Refer to the us er s manual for the particular MCU for a list of the pins on the chip 2 1 Pin Characteristics Table 2 1 shows types of output drivers Table 2 1 SIM Output Driver Types Type Description A Output only signals that are always driven no external pull up required Aw Type A output with weak P channel pull up during reset B Output that includes circuitry to pull up output bef
196. ore high impedance state is established to ensure rapid rise time An external holding resistor is required to maintain logic level while the pin is in the high impedance state Assertion of TSC always places these pins in a high impedance state in addition many bus control outputs are placed in a high impedance state when bus is granted to an external master Refer to 5 10 Bus Arbitration for details Bo Type B output that can be operated in an open drain mode Table 2 2 shows all inputs and outputs Digital inputs and outputs use CMOS logic lev els An entry in the Discrete column indicates that a pin can also be used for gen eral purpose input output or both I O port designation is given when it applies For details on the states of bus control signals when the bus is granted to an external mas ter refer to 5 10 Bus Arbitration SIM SIGNAL AND PIN DESCRIPTIONS MOTOROLA REFERENCE MANUAL 2 1 Table 2 2 SIM Pin Characteristics Pin Output Input Input Discrete Port Mnemonic Driver Synchronized Hysteresis Designation ADDR23 CS10 ECLK A Y N ADDR 22 20 CS 9 7 1 A 6 4 ADDR19 CS6 A Y N O PC3 ADDR 18 0 A Y N AS B Y N VO PE5 AVEC B Y N y o PE2 BERR B Y N BG CS1 B BGACK CS2 B M N BR CSO B Y N CLKOUT3 A ES CSBOOT B DATA 15 0 2 Aw Y N DS B Y N
197. out Period Divide Ratio EXTAL Frequency Table 3 3 gives the ratio for each combination of SWP and SWT bits When SWT 1 0 are modified a watchdog service sequence must be performed before the new time out period can take effect Table 3 3 Software Watchdog Ratio SWP SWT Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 MOTOROLA SYSTEM CONFIGURATION AND PROTECTION SIM 3 6 REFERENCE MANUAL Figure 3 2 is a block diagram of the watchdog timer and the clock control for the pe riodic interrupt timer SWP PTP FREEZE PIT INTERRUPT 8 BIT MODULUS COUNTER PRECLK CLOCK DISABLE EXTAL PRESCALER 29 LPSTOP SWT1 SWTO SWE 15 STAGE DIVIDER CHAIN 215 290 211 213 215 PIT BLOCK Figure 3 2 Periodic Interrupt Timer and Software Watchdog Timer 3 6 Periodic Interrupt Timer The periodic interrupt timer allows a user to generate interrupts of specific priority at predetermined intervals This capability is often used to schedule control system tasks that must be performed within time constraints The timer consists of a prescaler a modulus counter and registers that determine interrupt timing and priority and vector assignment 3 6 1 Prescaler and Modulus Counter The periodic interrupt modulus counter is clocked by a signal derived from the buffered crystal oscillator EXTAL input pin unless a
198. ow setup time specification 27A for the following clock cycle To ensure coherency during every operand transfer BG will not be asserted in response to BR until after all cy cles of the current operand transfer are complete and RMC is negated the absence of DSACK BERR is an asynchronous input using the asynchronous setup time specification 47A 11 After external RESET negation is detected a short transition period approximately 2 elapses then the SIM drives low for 512 toc 12 External logic must pull RESET high during this period in order for normal MCU operation to begin 13 Address access time 2 5 WS teye lcHAV Chip select access time 2 WS tcLSA tpicL Where WS number of wait states When fast termination is used 2 clock bus WS 1 14 RMC signal is not supported on CPU16 based MCUs SIM REFE ELECTRICAL CHARACTERISTICS MOTOROLA RENCE MANUAL A 5 MOTOROLA A 6 Table A 4 ECLK Bus Timing Vpp 5 0 Vdc 10 Vss 0 Vdc Num Characteristic Symbol Min Max Unit E17 Low to Address Valid TEAD 60 ns 2 ECLK Low to Address Hold tEAH 10 ns E3 ECLK Low to CS Valid CS delay tEcsp 120 ns E4 ECLK Low to CS Hold tECSH 15 ns E5 CS Negated Width lECSN 100 ns E6 Read Data Setup Time tEDSR 30 ns E7 Read Data Hold Time tepuR 15
199. pace is used for control information not normally associated with read or write bus cycles Re fer to 5 6 Function Codes and Memory Usage for more information on function codes During a CPU space access ADDR 19 16 are encoded to reflect the type of access being made The three encodings are shown in Figure 5 25 These encodings repre sent breakpoint acknowledge type 0 cycles low power stop broadcast Type 3 cy cles and interrupt acknowledge type F cycles Type 0 and type 3 cycles are discussed in the following paragraphs Refer to SECTION 6 INTERRUPTS for a com prehensive discussion of interrupt acknowledge bus cycles EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 81 CPU SPACE CYCLES FUNCTION ADDRESS BUS CODE 2 0 23 19 16 4 210 KNOWLEDGE 0000000000000000000 acknowtepae 111 0000000000000000000 2 2 19 1 0 LOW POWER 00 006031 1 AGE OLIO C9 INTERRUPT I tr Ati Alat ii a LEVEL CPU SPACE TYPE FIELD CPU SPACE CYC TIM Figure 5 25 CPU Space Address Encoding 5 8 1 Breakpoint Acknowledge Cycle Breakpoints are used to stop program execution at a predefined point during system development Breakpoints can be used alone or in conjunction with the background debugging mode The following paragraphs discuss breakpoint processing when background debugging mode is not enabled Refer to the appropriate CPU reference manual for informat
200. port during the third and fourth cycles of the transfer 5 5 10 Long Word Operand to 16 Bit Port Aligned The MCU drives the address bus with the desired address and drives the size pins to indicate a long word operand The MCU also drives the function code and R W pins to appropriate values MOTOROLA EXTERNAL BUS INTERFACE SIM 5 24 REFERENCE MANUAL 1 2 Data Bus 15 8 7 0 SIZ1 5120 ADDRO DSACK1 DSACKO Cycle 1 OPO 0 0 0 0 1 Cycle 2 OP1 OP1 1 0 0 0 1 Figure 5 19 Long Word Operand to 16 Bit Port Aligned For a read operation the 16 bit peripheral responds by placing OPO on DATA 15 8 and OP1 on DATA 7 0 then asserts DSACK1 to indicate a 16 bit port The MCU reads OPO and OP1 from DATA 15 0 The MCU increments the address bus by two drives SIZ1 to 1 and SIZO to 0 and waits for the peripheral to place OP2 and OP3 on the data bus during the second cycle of the transfer an aligned word read of a 16 bit port For a write operation the MCU drives OPO on DATA 15 8 and OP1 on DATA 7 0 The peripheral device reads and OP1 DATA 15 0 and asserts DSACK1 to indicate a 16 bit port The MCU increments the address bus by two drives SIZ1 to 1 and SIZO to 0 and places OP2 and OP3 on the data bus during the second cycle of the transfer an aligned word write to a 16 bit port Figure 5 20 is a timing diagram for a long word read or write operatio
201. prescaled 1 Periodic timer clock prescaled by a value of 512 MOTOROLA SYSTEM CONFIGURATION AND PROTECTION SIM 3 10 REFERENCE MANUAL PITM 7 0 Periodic Interrupt Timing Modulus This is the 8 bit timing modulus used to determine periodic interrupt rate Use the fol lowing expression to calculate timer period PIT Period Modulus Prescaler value 4 EXTAL Frequency 3 8 4 System Protection Register SYPCR The system protection control register controls system monitor functions software watchdog clock prescaling and bus monitor timing This register can be written only once following power on or external reset but can be read at any time SYPCR System Protection Control Register 1HHHI20 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED SWE SWP SWT HME BME BMT RESET 1 0 0 0 0 0 0 SWE Software Watchdog Enable 0 Software watchdog disabled 1 Software watchdog enabled SWP Software Watchdog Prescale 0 Software watchdog clock not prescaled 1 Software watchdog clock prescaled by 512 SWT 1 0 Software Watchdog Timing This field selects software watchdog time out period Software Watchdog Ratio SWP SWT Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 HME Halt Monitor Enable 0 Disable halt monitor function 1 Enable halt monitor function BME Bus Monitor External Enable 0 Disab
202. quently changing either of these values results in a time delay before the VCO locks in to the new frequency The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feed back loop Setting X doubles the clock speed without changing the VCO speed Con sequently there is no VCO relock delay In order for the device to perform correctly the clock frequency selected by the W X and Y bits must be within the limits specified in Table A 1 of APPENDIX A ELECTRI CAL CHARACTERISTICS As Table 4 1 and Table 4 2 indicate with either a 32 768 kHz or a 4 194 MHz reference frequency W and X must not both be set when the count modulus is greater than Y 96001111 4 4 1 Frequency Control with a Reference Frequency of 25 50 kHz With a reference frequency between 25 and 50 kHz such as a 32 768 kHz crystal clock frequency is determined by SYNCR bit settings as follows MOTOROLA SYSTEM CLOCK SIM 4 6 REFERENCE MANUAL 2W X amp 1 2 The internal VCO frequency is twice the system clock frequency if X 1 or four times the system clock frequency if X 0 The reset state of SYNCR 3F00 produces a modulus 64 count The W and X bits are both zero so that system frequency is 256 times the reference frequency 4 4 2 Frequency Control with a Reference Frequency 3 2 6 4 MHz With a reference frequency between 3 2 and 6 4 MHz such as a 4 194 MHzZz crystal the
203. r either BKPT signal is subsequently asserted MOTOROLA RESET AND SYSTEM INITIALIZATION SIM 8 10 REFERENCE MANUAL 8 7 SIM Refer to the appropriate CPU manual for more information on background debugging mode and exceptions Refer to 5 8 CPU Space Cycles for information concerning breakpoint acknowledge bus cycles Pin State During Reset While the MCU is held in reset the data bus pins are configured as inputs Function code pins are driven high Bus control pins AS DS SIZ 1 0 and RMC are driven high if configured for their bus control function see Table 8 3 Any bus control pins con figured for I O ports E and F are configured as inputs when the SIM comes out of reset NOTE Pins that are not used should either be configured as outputs or if configured as inputs pulled to the appropriate inactive state This de creases additional Ipp caused by digital inputs floating near mid sup ply level After RESET is released mode selection occurs and reset exception processing be gins Pins configured as inputs during reset become active high impedance loads after RESET is released Inputs must be driven to the desired active state pull up or pull down circuitry may be necessary Pins configured as outputs begin to function after RESET is released Table 8 3 is a summary of SIM pin states during reset RESET AND SYSTEM INITIALIZATION MOTOROLA REFERENCE MANUAL 8 11 Table 8 3 SIM Pin Reset States
204. re held high by the internal drivers the MCU uses a default operating configuration However spe cific lines can be held low externally to achieve an alternate configuration NOTE External bus loading can overcome the weak internal pull up drivers on data bus lines and hold pins low during reset MOTOROLA 8 8 RESET AND SYSTEM INITIALIZATION REFERENCE MANUAL 8 6 SIM DATAO determines the function of the boot ROM chip select signal CSBOOT Unlike other chip select signals CSBOOT is active at the release of reset During reset ex ception processing the MCU fetches initialization vectors beginning at address 000000 in supervisor program space After a reset an external memory device con taining the reset vector can be enabled by CSBOOT which is assigned at reset to a memory block beginning at 000000 The logic level of DATAO during reset selects boot ROM port size When DATAO is held low port size is 8 bits when DATAO is held high either by the weak internal pull up driver or by an external pull up port size is 16 bits Refer to 7 9 Chip Select Reset Operation for more information DATA1 and DATA determine the functions of CS 2 0 and CS 5 3 respectively DA TA 7 3 determine the functions of an associated chip select and all lower numbered chip selects down through CS6 For example if DATAS is pulled low during reset CS 8 6 are assigned alternate function as ADDR 21 19 and CS 10 9 remain chip selects On
205. rnal device asserts DSACK rather than BERR the CPUS2 ignores the breakpoint and continues processing Refer to the appropriate CPU reference manual for additional details When BKPT assertion is synchronized with an instruction prefetch processing of the breakpoint exception occurs at the end of that instruction The prefetched instruction is tagged with the breakpoint when it enters the instruction pipeline and the break point exception occurs after the instruction executes If the pipeline is flushed before the tagged instruction is executed no breakpoint occurs When BKPT assertion is syn chronized with an operand fetch exception processing occurs at the end of the instruc tion during which BKPT is latched Breakpoint operation flow for CPU32 based MCUs is shown in Figure 5 26 Figure 5 27 shows breakpoint flow for CPU16 based MCUs Figure 5 28 is the timing diagram for the breakpoint acknowledge cycle for the CPU32 BKPT instruction Figure 5 29 shows the timing for both CPU16 and CPU32 based MCUs for breakpoint acknowl edge cycles initiated by a low signal on the BKPT pin SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 33 BREAKPOINT OPERATION FLOW CPU32 PERIPHERAL ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED 1 SET RAW TO READ 2 SET FUNCTION CODE TO CPU SPACE 3 PLACE CPU SPACE 0 ON ADDR 19 16 4 PLACE BREAKPOINT NUMBER ON ADDR 4 2 5 SET T BIT ADDR1 TO ZERO 6 SET S
206. rnal devices Strobe signals one for the address bus and another for the data bus indicate the validity of an ad dress and provide timing information for data SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 1 Control signals indicate the availability of an address on the bus AS validity of data on the bus DS the address space where the bus cycle is to occur FC 2 0 the size of the transfer SIZ 1 0 and the type of cycle RAN External devices decode these signals and respond by transferring data and terminating the bus cycle 5 1 1 Address Bus Bus signals ADDR 23 0 define the address of the most significant byte to be trans ferred during a bus cycle The MCU places the address on the bus at the beginning of a bus cycle The address is valid while AS is asserted 5 1 2 Address Strobe Address strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals It is asserted one half clock after the begin ning of a bus cycle 5 1 3 Data Bus Bus signals DATA 15 0 comprise a bidirectional nonmultiplexed parallel bus that transfers data to or from the MCU A read or write operation can transfer 8 or 16 bits of data in one bus cycle During a read cycle the MCU latches the data on the last falling clock edge of the bus cycle During a write cycle the MCU places the data on the data bus one half clock cycle after AS is asserted 5 1 4 Data Strobe For a read
207. rogrammed for external DSACK generation and the remaining DSACK field to the desired number of wait states This prevents a conflict on the internal bus when the wait states are loaded into the DSACK counter shared by all chip selects 7 5 2 Synchronization with ECLK When MODE 1 in the associated chip select option register chip select assertion is synchronized to the MCU ECLK output When a match condition occurs the chip se lect circuit signals the EBI that an ECLK cycle is pending When the EBI determines that bus timing constraints are satisfied the chip select signal is asserted Transfers of word and long word data to an 8 bit port are performed consecutively without inser tion of additional ECLK cycles The bus monitor time out period must be longer than the number of clock cycles required for two ECLK cycles Refer to SECTION 3 SYS TEM CONFIGURATION AND PROTECTION for more information Because chip se lect cycles synchronized to ECLK are not terminated by data and size acknowledge signals the DSACK field has no effect in this mode The AVEC bit must not be used since autovector response timing can vary due to ECLK synchronization with the in ternal system clock 7 6 Chip Selects and Dynamic Bus Sizing Chip select logic works with the external bus interface to perform dynamic bus sizing Pin assignment fields in the pin assignment registers assign port sizes of 8 or 16 bits to the devices assigned to the
208. rs The EBI performs dynamic sizing for data accesses The maximum number of bits transferred during an access is referred to as port width Widths of eight and sixteen bits can be accessed by means of asynchronous bus cy cles controlled by the size SIZO and SIZ1 and the data and size acknowledge DSACKO and 1 signals Multiple bus cycles may be required for a dynamical ly sized transfer Refer to 5 3 Dynamic Bus Sizing for more information on data align ment and port width 5 7 System Interfacing Examples provides example system configurations for different port widths NOTE Some MCUs with reduced pin count SIMs do not include a DSACKO pin Refer to SECTION 10 REDUCED PIN COUNT SIM for details on handshaking with these MCUs The SIM contains 12 chip select circuits that can simplify the interface to memory and peripherals These chip selects are described in SECTION 7 CHIP SELECTS The discussion of the EBI in this section is useful both as a background for understanding chip select operation and as a guide to interfacing to external devices without the use of SIM chip selects NOTE MCUS with reduced pin count SIMs may contain fewer than 12 chip select pins Refer to SECTION 10 REDUCED PIN COUNT SIM and to the user s manual for the particular MCU for details 5 1 Bus Signal Descriptions The address bus provides addressing information to external devices The data bus transfers 8 bit and 16 bit data between the MCU and exte
209. rupt arbitration priority The reset value is F highest prior ity to prevent SIM interrupts from being discarded during initialization Refer to 3 1 4 Interrupt Arbitration Priority and SECTION 6 INTERRUPTS for additional informa tion SIMTR System Integration Test Register 4HHHIO2 SIMTR is used for factory test only SYNCR Clock Synthesizer Control Register SHHHHO4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W X Y EDIV 0 0 SLIMP SLOCK RSTEN STSIM STEXT RESET 0 0 1 1 1 1 1 1 0 0 0 U U 0 0 0 W Frequency Control VCO 0 Base VCO frequency 1 VCO frequency multiplied by four Refer to 4 4 System Clock Frequency Control for additional information X Frequency Control Bit Prescale 0 Base system clock frequency 1 System clock frequency multiplied by two Refer to 4 4 System Clock Frequency Control for additional information Y 5 0 Frequency Control Counter The Y field is the initial value for the modulus 64 down counter in the synthesizer feed back loop Values range from 0 to 63 Refer to 4 4 System Clock Frequency Control for additional information EDIV ECLK Divide Rate 0 ECLK is system clock divided by 8 1 ECLK is system clock divided by 16 Refer to 4 5 External Bus Clock for additional information SLIMP Limp Mode Status 0 MCU is operating normally 1 Loss of reference signal MCU operating in limp mode Refer to 4 7 Loss of Re
210. s are possible with the chip select fast termination option Internal microcontroller mod ules in contrast are typically accessed in two system clock cycles The SIM contains 12 chip select circuits These on chip circuits decode EBI address lines and control signals RAN SIZ 1 0 AS DS and FC 2 0 reducing the need for external glue logic Chip select circuits can also generate the following types of exter nal bus cycles Bus cycles with internally generated DSACK signals e Fast termination two clock cycles Bus cycles that are synchronous to the ECLK signal rather than asynchronous Asynchronous cycles are always terminated with DSACK signals These features are discussed in SECTION 7 CHIP SELECTS The paragraphs that follow describe asynchronous external bus cycles that require a minimum of three clock cycles decode address and control signals externally and use externally gen erated DSACK signals Bus cycles normally occur in user or supervisor space Bus cycles that occur in CPU space which follow most of the protocol of regular external bus cycles are described in 5 8 CPU Space Cycles The interrupt acknowledge cycle a type of CPU space cy cle is described in SECTION 6 INTERRUPTS 5 2 1 Bus Cycle Operation To initiate a transfer the MCU asserts the appropriate address and SIZ 1 0 signals The SIZ 1 0 signals and ADDRO are externally decoded to select the active portion of the data bus Refer to
211. s bus transfers external devices assert one of the data and size acknowledge signals DSACK1 and DSACKO to indicate port width to the MCU During a read cycle these signals also tell the MCU to terminate the bus cycle and to latch data During a write cycle they indicate that an external device has suc cessfully stored data and that the cycle may terminate Refer to 5 3 Dynamic Bus Siz ing for information on DSACK encoding and dynamic bus sizing DSACK1 and DSACKO can also be supplied internally by chip select logic Refer to SECTION 7 CHIP SELECTS for more information on internally generated DSACKT 1 0 signals The designation DSACK is used in this manual as a generic reference to one or both of these signals NOTE Some MCUs with reduced pin count SIMs do not include a DSACKO pin Refer to SECTION 10 REDUCED PIN COUNT SIM for details on handshaking with these MCUs 5 1 9 Bus Error Signal The bus error BERR signal is asserted in the absence of DSACK assertion to indi cate a bus error condition It can also be asserted in conjunction with DSACK to indi cate a bus error condition provided it meets the appropriate timing requirements Refer to 5 9 Bus Error Processing for more information An external bus master must provide its own BERR generation and drive the BERR pin Refer to 5 10 Bus Arbitration for more information 5 1 10 Halt Signal An external device can assert the halt signal HALT to cause single bus cy
212. s monitor must be used DSACK BERR and HALT may be negated after AS is negated SIM EXTERNAL BUS INTERFACE REFERENCE MANUAL MOTOROLA 5 39 WARNING If DSACK or BERR remain asserted into S2 of the next bus cycle that cycle may be terminated prematurely 5 9 1 Bus Error Exceptions The CPU treats bus errors as a type of exception Bus error exception processing be gins when the CPU detects assertion of the IMB BERR signal by the internal bus mon itor or an external source while the HALT signal remains negated NOTE On CPU16 based MCUs assertion of BERR results in a bus error exception regardless of the state of the HALT signal takes precedence over DSACK provided it meets the timing constraints de scribed in APPENDIX A ELECTRICAL CHARACTERISTICS WARNING If BERR does not meet these constraints it may cause unpredictable operation of the MCU If BERR remains asserted into the next bus cycle it may cause incorrect operation of that cycle assertions do not force immediate exception processing The signal is synchro nized with normal bus cycles and is latched into the CPU at the end of the bus cycle in which it was asserted Since bus cycles can overlap instruction boundaries bus er ror exception processing may not occur at the end of the instruction in which the bus cycle begins Timing of BERR detection and acknowledgment depends on several fac tors Which bus cycle of a
213. sists of two successive states State 0 SO The read cycle starts The MCU places an address on ADDR 23 0 and function codes on FC 2 0 On CPU16 based MCUs ADDR 23 20 always follow the state of ADDR19 and FC2 is always equal to one The MCU drives R W high for a read cycle SIZ 1 0 become valid indicating the number of bytes to be read State 1 51 The MCU asserts AS indicating that the address on the address bus is valid The MCU also asserts DS signaling the peripheral to place data on the bus State 2 52 External logic decodes ADDR 23 0 FC 1 0 R W SIZ 1 0 and DS One or both of DATA 15 8 and DATA 7 0 are selected and the responding device places data on that portion of the bus Concurrently the device asserts the appropriate DSACK signals For the MCU to be guaranteed to latch the data in minimum cycle time at least one DSACK signal must be recognized as asserted by the end of S2 That is it must meet the input setup time requirement preceding the falling edge of S2 For wait states to be guaranteed to be inserted both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times at the end of S2 SIM EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 9 State 3 83 When a change in one or both of the DSACK signals has been recog nized the MCU latches data from the bus the next falling edge of the clock 54 and the cycle terminates S5 If neither
214. synchronous inputs to the MCU are internally synchronized in a maximum of two CLKOUT cycles Figure 5 37 is the bus arbitration state diagram Input signals labeled R and are internal versions of the bus request and bus grant acknowledge signals that are internally synchronized to the system clock The bus grant output is labeled G and the internal high impedance control signal is labeled T If T is true the address data and control buses are placed in the high impedance state after the next rising edge following the negation of AS and RMC MOTOROLA 5 50 Pin Mnemonic Bus Control Signal Pin Direction Pin State when Bus Granted Away ADDR23 CS10 ECLK ADDR23 Output High Impedance ADDR 22 19 CS 9 6 PC 6 3 ADDR 22 19 Output High Impedance ADDR 18 0 ADDR 18 0 Output High Impedance AS PE5 AS Output High Impedance AVEC PE2 AVEC Input Inactive BERR BERR Input Inactive BG CS1 BG Output Active BGACK CS2 BGACK Input Active BR CSO BR Input Active DATA 15 0 DATA 15 0 Depends on R W High Impedance DS PE4 DS Output High Impedance DSACK 1 0 PE 1 0 DSACK 1 0 Input Inactive FC 2 0 CS 5 S PC 2 0 FC 2 0 Output High Impedance R W R W Output High Impedance RMC PE3 RMC Output High Impedance SIZ 1 0 PE 7 6 SIZ 1 0 Output High Impedance EXTERNAL BUS INTERFACE SIM REFERENCE MANUAL R BUS REQUEST G BUS GRANT A BUS GRANT ACKNOWLEDGE T THREE STATE SIGNAL TO BUS CONTROL B BUS CYCLE IN PROGRESS V BUS AVAILABLE TO
215. system For a discussion of the reset status register refer to SECTION 8 RESET AND SYS TEM INITIALIZATION Other aspects of system configuration and protection are dis cussed in the following paragraphs Figure 3 1 is a block diagram of the submodule MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR EL CLOCK SOFTWARE WATCHDOG TIMER RESET REQUEST 29 PRESCALER PERIODIC INTERRUPT TIMER IRQ 7 1 SYS PROTECT BLOCK Figure 3 1 System Configuration and Protection SIM SYSTEM CONFIGURATION AND PROTECTION MOTOROLA REFERENCE MANUAL 3 1 3 1 Module Configuration and Testing The SIM configuration register SIMCR governs the operation of the system protec tion block and other aspects of system operation System protection is discussed in detail later in this section The following paragraphs describe the other aspects of sys tem configuration controlled by the SIMCR 3 1 1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping MM bit in the SIM module configuration reg ister SIMCR determines where the control register block is located in the system memory map When is equal to zero register addresses range from 7FF000 to 7FFFFF When MM 1 register addresses range from FFFO000 to FFFFFF CAUTION On CPU16 based MCUs ADDR 23 20 follo
216. t Arbitration Field IARB determines SIM interrupt arbitration priority The reset value is F highest prior ity to prevent SIM interrupts from being discarded during initialization Refer to 3 1 4 Interrupt Arbitration Priority and SECTION 6 INTERRUPTS for additional informa tion 3 1 7 SIM Test Registers SIMTRE System Integration Test Register ECLK 08 The SIMTRE is used for factory test only SIMTR System Integration Test Register 1HHHEO2 SIMTR is used for factory test only MOTOROLA SYSTEM CONFIGURATION AND PROTECTION SIM 3 4 REFERENCE MANUAL 3 2 Internal Bus Monitor The internal bus monitor checks for excessively long response times during normal bus cycles those terminated by DSACK or AVEC during autovector cycles The monitor asserts internal BERR when response time is excessive Refer to SECTION 5 EXTERNAL BUS INTERFACE for a discussion of external bus cycles and DSACK signals Refer to SECTION 6 INTERRUPTS for a discussion of AVEC signals during interrupt acknowledge cycles DSACK and AVEC response times are measured in clock cycles Maximum allowable response time can be selected by setting the bus monitor timing BMT field in the sys tem protection control register SYPCR Table 3 1 shows possible periods Table 3 1 Bus Monitor Period BMT Bus Monitor Time out Period 00 64 System Clocks 01 32 System Clocks 10 16 System Clocks 11 8 System Clocks The monitor does
217. t Operation for information on pin assignments at re set 7 4 Chip Select Operation Pins come out of reset assigned to their chip select function Before a chip select oth er than CSBOOT can respond to a memory access however its option register and base address register must be programmed The BYTE fields in the option registers for CS 10 0 are cleared during reset These fields must be set to nonzero values to SIM CHIP SELECTS MOTOROLA REFERENCE MANUAL 7 5 enable the associated chip selects However CSBOOT is made active out of reset so that it can be used as a chip select for the initialization memory See 7 9 Chip Select Reset Operation for information on the initial states of the CSBOOT base address and option registers Disabling the chip selects prevents chip select signal assertion even when all other constraints are satisfied The associated pin is driven high and internal chip select logic cannot assert associated signals such as DSACK or AVEC internally Alternate functions for chip select pins are enabled if appropriate data bus pins are held low at the release of the reset signal Refer to 7 9 Chip Select Reset Operation for more information When the MCU makes a memory access each enabled chip select circuit compares the following items Appropriate ADDR bits to the base address field in the base address register Function code signals to the SPACE field in the option register Read write status to R W
218. t for both reads and writes 10 STRB 0 Chip select synchronized with AS 9 6 DSACK 1101 13 wait states 5 4 SPACE 11 Supervisor user space 3 1 IPL 000 Assert chip select on any level interrupt 0 AVEC 0 Autovector disabled CSOR 10 0 Disabled BYTE field 0 8 9 System Initialization During system initialization a hardware initialization sequence occurs Following hard ware initialization the MCU performs the initialization routine fetched from the excep tion vector table This initialization routine normally defines constants addresses and other data values needed by the program The following steps summarize procedures for initializing the SIM Initialize the SIM before initializing other MCU modules 1 Program the SIMCR to set the SIM arbitration level base address of the module registers and privilege level of assignable SIM registers and to enable or dis able the external clock the software watchdog and bus monitor and show cy cles Program the SYNCR to set the system clock frequency ECLK divide rate to enable or disable loss of crystal reset and to assign STOP mode clock opera tion Program the SYPCR to enable or disable the software watchdog halt monitor and bus monitor and to assign the timing for the software watchdog and bus monitor Program the PICR and PITR to set the periodic interrupt request level and es tablish the timing for the periodic timer Program the chip select pin assignment
219. ter CPU32 based MCUs or condition code register on CPU16 based MCUs Binary values 96000 to 96111 provide eight priority masks Masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed SIM INTERRUPTS MOTOROLA REFERENCE MANUAL 6 1 IRQ7 however is always recognized even if the mask value is 111 If simultaneous interrupt requests of different levels are made the CPU recognizes the higher level re quest IRQ 7 1 are active low level sensitive inputs The level on the pin must remain assert ed until an interrupt acknowledge cycle corresponding to that level is detected IRQ7 is transition sensitive as well as level sensitive a level 7 interrupt is not detected unless a falling edge transition is detected on the IRQ7 line This prevents redundant servicing and stack overflow A nonmaskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask changes from 111 to a lower number while IRQ7 is asserted Interrupt requests are sampled on consecutive falling edges of the system clock In terrupt request input circuitry has hysteresis to be valid a request signal must be as serted for at least two consecutive clock periods Valid requests do not cause immediate exception processing but are left pending Pending requests are pro cessed at instruction boundaries or when exception processing of higher priority ex ceptions is
220. terrupt acknowledge cycle The chip select circuit gen erates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins 7 8 1 Using a Chip Select Pin as an Interrupt Acknowledge Signal Follow these steps to use a chip select pin as an interrupt acknowledge signal 1 Configure the pin as a chip select to an 8 or 16 bit port in the appropriate chip select pin assignment register 2 In the base address register program the base address field bits 15 3 to all ones Program the block size to no more than 64 Kbytes so that the address comparator checks address lines ADDR 19 16 against the corresponding bits in the base address register The CPU places the CPU space type on AD DR 19 16 3 Program the chip select options register as follows Program MODE to zero to emulate asynchronous bus cycles Set the R W field to read only An interrupt acknowledge cycle is performed as a read cycle Program the BYTE field to lower byte when using a 16 bit port since the ex ternal vector for a 16 bit port is fetched from the lower byte Program the BYTE field to upper byte when using an 8 bit port MOTOROLA CHIP SELECTS SIM 7 14 REFERENCE MANUAL Program STRB to synchronize with AS Program the DSACK field to the desired number of wait states Select the 961111 option if the external device will generate DSACK signals e Program IPL to respond to the desired interrupt request level or to 950
221. the active bus master A device remains the bus master until it negates BGACK BGACK must not be negated until all required bus cycles are completed NOTE On MCUs with a reduced pin count SIM the BGACK may not be supported Refer to SECTION 10 REDUCED PIN COUNT SIM and to the user s manual for the particular MCU for additional information When a device receives the bus and asserts BGACK it must also negate BR If BR remains asserted after BGACK assertion the MCU assumes that another device is re questing the bus and prepares to issue another BG Since external devices have priority the MCU cannot regain control of the external bus until all pending external bus requests have been satisfied 5 10 4 Bus Arbitration Pin State SIM Table 5 6 indicates the states of bus control pins when an external master has control of the bus For pins with multiple functions Table 5 6 applies if the pin is configured for its bus control function shown in the second column Output bus control signals not used when an external master has control of the bus are placed in a disabled high impedance state and inactive signals are placed in an inactive state EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 49 Table 5 6 Bus Arbitration Pin State 5 10 5 Bus Arbitration Control The bus arbitration control unit in the MCU is implemented with a finite state machine All a
222. tions interface MCCI These modules are present in different combinations on different MCUs Memory modules include standby RAM ROM EEPROM Flash EEPROM and standby RAM with TPU emulation capabilities TPURAM These modules are present in different combinations on different MCUs The different modules on an MCU communicate with one another and with external components via the intermodule bus IMB a standardized bus developed to facilitate design of modular microcontrollers The IMB supports 24 address and 16 data lines NOTE On CPU16 based MCUs external address lines ADDR 23 20 follow the state of ADDR19 The SIM consists of the following functional blocks The system configuration and protection block controls configuration parameters and provides bus and software watchdog monitors In addition it provides a peri odic interrupt generator to support execution of time critical control routines system clock generates clock signals used by the SIM other IMB modules and external devices The external bus interface handles the transfer of information between IMB mod ules and external address space SIM INTRODUCTION MOTOROLA REFERENCE MANUAL 1 1 The chip select block provides 12 chip select signals Each chip select signal has an associated base register and option register that contain the programmable characteristics of that chip select A data port port C is available for discrete out put on pins not b
223. tipliers 4 8 MOTOROLA 1 1 timing 1 external 4 3 circuit 4 4 frequency control 4 6 loss of 4 12 mode selection 8 10 sources 4 1 synthesizer 4 1 4 4 Configuration system 3 1 CPU and SIM interaction 1 7 space cycles 5 31 CPU16 1 7 CPU32 1 7 Crystal oscillator 4 5 tune up 4 5 CSBAR 10 0 7 19 CSBARBT 74 7 17 7 19 CSBOOT 7 17 CSOR 10 0 7 19 CSORBT 7 19 CSPAO 7 18 CSPA1 7 18 CSPARO 7 18 CSPAR1 7 18 D Data and size acknowledge DSACK 5 3 5 6 6 5 bus DATA 15 0 5 2 mode selection with 1 6 1 7 8 8 signal conditioning 8 10 direction registers DDRE DDRF 9 2 strobe DS 5 2 5 52 DBF 8 3 8 4 DC characteristics A 2 DDRE 9 3 DDRF 9 3 Debugging and HALT 5 45 show cycles 5 52 Discrete 9 1 output 7 21 Double bus fault 5 42 reset flag DBF 8 3 8 4 DS 5 2 5 52 DSACK 5 3 5 6 6 5 and RPSIM 10 1 field 7 2 7 9 7 20 Dynamic bus sizing 5 6 and chip selects 7 10 E EBI 5 1 ECLK 4 11 7 1 7 10 divide rate EDIV 4 11 4 13 MOTOROLA 1 2 timing diagrams 7 timing diagrams A 3 A 22 EDIV 4 11 4 13 Exceptions bus error 5 42 EXOFF 3 3 EXT 8 3 8 4 EXTAL 3 7 3 8 4 1 4 8 4 4 External bus arbitration 5 47 bus clock ECLK 4 11 7 1 7 10 bus cycles 5 4 synchronization to CLKOUT 5 5 bus interface EBI 5 1 clock 4 3 input timing diagram A 7 off EXOFF 3 3 devices interfacing to 5 28 filter capacitor XFC 4 5 reset flag EXT 8 3 8 4 m Factory test slave mode 3 3 arbi
224. to BERR low setup time 48 can be ignored The data must only satisfy the data in to clock low setup time 27 for the following clock cycle BERR must satisfy only the late BERR low to clock low setup time 27A for the following clock cycle 10 In the absence of DSACK BERR is an asynchronous input using the asynchronous setup time 47 14 RMC signal is not supported on CPU16 based MCUs MOTOROLA A 10 ELECTRICAL CHARACTERISTICS SIM REFERENCE MANUAL 50 51 52 53 54 55 meg D es 7 E SIM WR CYC TIM Figure A 5 Write Cycle Timing Diagram SIM ELECTRICAL CHARACTERISTICS MOTOROLA REFERENCE MANUAL A 11 Table 7 Key to Figure 5 Abstracted from Table A 3 see table for complete notes Characteristic Symbol Clock High to Address FC SIZE RMC Valid Clock High to Address FC SIZE Invalid lCHAZn Clock Low to AS DS CS Asserted tcLsa Address FC SIZE RMC Valid tavsa to AS CS Asserted Clock Low to AS DS CS Negated tcLsn AS DS CS Negated to Address FC SIZE Invalid tsnal Address Hold AS CS Width Asserted tswa DS CS Width Asserted Write tswaw AS DS CS Width Negated tsN AS DS CS Negated to R W High tsNRN Clock High to R W Low R W Low to DS CS Asserted Write Clock High to Data Valid tcHDO DS CS Negated to Data Out Invalid Data Out Hold lsNDOI Data
225. transfer Figure 5 16 and Figure 5 17 are timing diagrams for long word read and write oper ations respectively to an eight bit port EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 21 50 52 54 50 52 54 50 52 54 50 52 54 CLKOUT 4 BYTES 3 BYTES 2 BYTES 1 BYTE DATA 15 8 DATA 7 0 BYTE gt lt gt lt gt lt READ READ READ READ LONG WORD OPERAND READ FROM 8 BIT BUS gt LONG WORD RD TIM Figure 5 16 Timing of a Long Word Read of an 8 Bit Port MOTOROLA EXTERNAL BUS INTERFACE SIM 5 22 REFERENCE MANUAL CLKOUT ADDR 23 0 S0 52 54 50 52 54 50 52 54 50 2 54 5170 4 BYTES 3 BYTES 2 BYTES 1BYTE 5171 DSACKO N N N N DSACKi DATA 7 0 OP1 OP1 OP3 OP3 lt WRITE gt lt WRITE 3 WRITE gt lt WRITE gt lt LONG WORD OPERAND WRITE TO 8 BIT BUS LONG WORD WR TIM Figure 5 17 Timing of a Long Word Write to an 8 Bit Port 5 5 9 Long Word Operand to 8 Bit Port Misaligned The CPU16 treats misaligned long words as two misaligned words The MCU drives the address bus with the desired address and the size pins to indicate a word operand The MCU also drives the function code and R W pins to appropriate values NOTE The CPU32 does not support transfers of misaligned operands SIM E
226. tration 5 52 Fast termination cycles 7 11 read 7 12 timing diagram A 18 write 7 13 timing diagram A 20 FC 2 0 5 2 5 27 and interrupts 6 3 FREEZE 3 2 Freeze bus monitor FRZBM 3 2 3 4 software watchdog FRZSW 3 3 Frequency control system clock 4 6 avoiding overshoot 4 7 tables 4 7 FRZBM 3 2 3 4 FRZSW 3 3 Function codes FC 2 0 5 2 5 27 and interrupts 6 3 G General purpose 9 1 H HALT 3 5 5 3 5 38 5 45 5 46 5 47 timing 5 46 Halt monitor 3 5 enable HME 3 5 3 11 operation 5 47 Hardware breakpoints 5 33 HME 3 5 3 11 SIM REFERENCE MANUAL 1 3 3 3 4 6 3 IMB 1 1 Initialization system 8 14 Input sample window 5 5 Input output discrete 9 1 Interfacing system examples 5 28 with chip selects 7 22 Intermodule bus IMB 1 1 Internal bus monitor 3 5 Interrupts 6 1 acknowledge cycles 6 3 6 5 and chip selects 7 13 arbitration 3 3 6 2 number IARB 3 3 3 4 6 3 level and recognition 6 1 6 2 PIT 3 9 priority level chip selects IPL 7 3 7 21 7 23 priority mask 6 2 recognition 6 1 request signals IRQ 7 1 6 1 7 13 sources 6 1 vectors 6 4 IPL 7 3 7 23 IRQ 7 1 6 1 7 13 ese Late retry sequence 5 45 Limp mode 4 13 status flag SLIMP 4 13 LOC loss of clock reset flag 8 3 8 4 Loss of reference signal 4 12 LPSTOP low power stop 3 9 4 11 broadcast cycle 5 38 Mask value interrupt 6 2 MCU 1 1 Memory map SIM 1 5 Misaligned operands 5 8 5 18 5 23 5 26 MM
227. ty cycle and minimum is expressed Minimum txcyc period minimum 50 external clock input duty cycle tolerance To achieve maximum operating frequency fsys while using an external clock input adjust clock input duty cycle to obtain a 5096 duty cycle on CLKOUT Specification 9A is the worst case skew between AS and DS or CS The amount of skew depends on the relative loading of these signals When loads are kept within specified limits skew will not cause AS and DS to fall outside the limits shown in specification 9 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification be tween multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads The user is free to use either hold time Maximum value is equal to 2 25 ns If the asynchronous setup time specification 47A requirements are satisfied the DSACK low to data setup time specification 31 and DSACK low to BERR low setup time specification 48 can be ignored The data must only satisfy the data in to clock low setup time specification 27 for the following clock cycle BERR must satisfy only the late BERR low to clock l
228. unctional timing diagram of a read modify write instruc tion specified in terms of clock periods EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 13 50 52 54 50 52 54 50 lt READ gt lt WRITE gt lt INDIVISIBLE gt CYCLE RD MOD WR TIM Figure 5 6 Read Modify Write Timing The read modify write sequence consists of one or more read cycles followed by idle states followed by one or more write cycles The read and write cycles are similar to those previously described The differences are summarized as follows Read Cycles If more than one read cycle is required to read the operand S0 S5 are repeated for each read cycle In S0 the MCU asserts RMC to identify a read modify write cycle When finished reading in S5 the MCU holds the address R W and FC 2 0 valid in preparation for the write portion of the cycle Idle States The MCU does not assert any new control signals during the idle states between the read and write cycles but it may internally begin the modify portion of the cycle at this time If a write cycle is required the R W signal continues to signal a read operation until state O of the write cycle to prevent bus conflicts with the preceding read portion of the cycle Write Cycle The write cycle is omitted if it is not required If more than one write cycle is required 50 55 are repeated for each write cycle During SO the MCU drives RAW low for a
229. uration Register This field is cleared by reset When show cycles are disabled the address bus function codes size and read write signals reflect internal bus activ ity but AS and DS are not asserted externally and external data bus pins are in high impedance state during internal accesses When show cycles are enabled DS is asserted externally during internal cycles and internal data is driven out on the external data bus during writes Since internal cycles normally continue to run when the external bus is granted away one SHEN encoding halts internal bus activity while there is an external master SIZ 1 0 signals reflect bus allocation during show cycles Only the appropriate portion of the data bus is valid during the cycle During a byte write to an internal address the portion of the bus that represents the byte that is not written reflects internal bus con ditions and is indeterminate During a byte write to an external address the data mul tiplexer in the SIM causes the value of the byte that is written to be driven out on both bytes of the data bus State 0 50 Address and function codes become valid R W is driven to indicate show read or write cycle and the size pins indicate the number of bytes to transfer During a read the addressed peripheral drives the data bus and the user must take care to avoid bus conflicts State 41 S41 DS is asserted to indicate that address information is valid State 42
230. uring reset and come out of reset as bus control outputs If DATA8 is held low during reset these pins are inactive high impedance inputs during reset and come out of reset as port E inputs MOTOROLA 8 12 RESET AND SYSTEM INITIALIZATION SIM REFERENCE MANUAL 8 8 SIM Registers Out of Reset Table 8 4 summarizes the reset values of bits and fields in the SIM registers Bits not included in the table are unimplemented and have reset values of zero Table 8 4 SIM Registers Out of Reset Register Bits Name Value Meaning SIMCR 15 EXOFF 0 CLKOUT enabled 14 FRZSW 1 Disable watchdog and PIT when FREEZE asserted 13 FRZBM 1 Disable bus monitor when FREEZE asserted 11 SLVEN DATA11 Slave mode enabled if DATA11 low 9 8 SHEN 00 Show cycles disabled 7 SUPV 1 Supervisor access only 6 MM 1 Module registers begin at FFF000 3 0 IARB 1111 SIM interrupts have highest priority SYPCR 7 SWE 1 Software watchdog enabled 6 SWP MODCLK Software watchdog prescaled by 512 if MODCLK low 5 4 SWT 00 Software watchdog time out set to minimum 3 HME 0 Disable halt monitor 2 BME 0 Disable internal to external bus monitor 1 0 BMT 00 Bus monitor time out 64 system clocks SYNCR 15 8 W X Y 00111111 System clock frequency Source frequency 256 7 EDIV 0 ECLK System clock gt 8 4 SLIMP Unchanged Limp mode flag unaffected by reset 3 SLOCK Unchanged Synthesizer lock flag unaffected by reset 2 RSTEN 0 Loss
231. us is valid State 2 82 The MCU places the data on DATA 15 0 then begins to sample the DSACK signals External logic decodes the address lines FC 1 0 R W SIZ 1 0 and AS One or both of DATA 15 8 and DATA 7 0 are selected and appropriate DSACK signals are asserted For the MCU to be guaranteed to latch the data in minimum cycle time the MCU must recognize a change in at least one DSACK signal by the end of S2 that is the DSACK signal must meet the input setup and hold time requirements For wait states to be guaranteed to be inserted both DSACK1 and DSACKO must re main negated throughout the asynchronous input setup and hold times at the end of 52 State 3 S3 MCU asserts DS to indicate that data is stable on the data bus and the selected peripheral latches the data When a change in one or both of the DSACK signals has already been recognized S4 elapses and the cycle terminates during S5 If neither DSACK signal changes state by the start of S3 the MCU inserts wait states instead of proceeding to S4 and S5 While wait states are added the MCU continues to sample the DSACK signals on falling edges of the clock until a change in one or more is recognized In effect S3 repeats until a change in the DSACK signals is detected State 4 84 The MCU issues no new control signals during S4 State 5 85 The MCU negates AS and DS but holds the address and data valid to provide address h
232. vector number 2 The AVEC signal is asserted the external interrupt source can assert the signal or the pin can be tied low and the CPU generates an autovector number corresponding to the interrupt priority level 3 The bus monitor or external device asserts BERR and the CPU generates the spurious interrupt vector number The vector number is converted to a vector address The content of the vector address is loaded into the PC and the processor transfers control to the exception handler routine MOTOROLA INTERRUPTS SIM 6 8 REFERENCE MANUAL SIM SECTION 7 CHIP SELECTS Typical microcontrollers require additional hardware to provide external chip select and address decode signals The SIM includes 12 programmable chip select circuits that can provide 2 clock cycle fast termination to 16 clock cycle 13 wait state ac cess to external memory and peripherals Address block sizes of 2 Kbytes to 1 Mbyte on CPU32 based MCUS or 2 Kbytes to 512 Kbytes on CPU16 based MCUSs be selected NOTE MCUS with reduced pin count SIMs may not have all 12 chip select pins available Consult the user s manual for the particular MCU for details Chip select assertion can be synchronized with bus control signals to provide output enable read write strobe or interrupt acknowledge signals Chip select logic can gen erate DSACK and AVEC signals internally Each signal can also be synchronized with the ECLK signal ava
233. w the logic state of ADDR19 On these MCUs if MM is cleared the SIM maps MCU modules into an address space that is inaccessible to the CPU Mod ules remain inaccessible until reset occurs The reset state of MM is one but the bit can be written once Initialization software for these MCUs should make certain MM remains set by writing a one to it 3 1 2 Privilege Levels To protect system resources the processor in CPU32 based MCUS can operate at ei ther the user or supervisor privilege level On CPU32 based MCUs access to most SIM registers is permitted only when the CPU is operating at the supervisor privilege level The remaining SIM registers are programmable to permit supervisor access only or to permit access when the CPU is operating at either the supervisor or user privilege level If the SUPV bit in the SIMCR is set access to SIM registers is permitted only when the CPU is operating at the supervisor level If SUPV is cleared then access to certain SIM registers is permitted when the CPU is operating at either the supervisor or user privilege level The SIM address map Table 1 1 indicates which registers are pro grammable to allow access from either privilege level CPU16 based MCUs which do not support the user privilege level always operate at the supervisor level so that SIM and all MCU registers are always accessible The state of the SUPV bit has no meaning on these MCUs 3 1 3 Response to FREEZE Assertion When the
234. write cycle Depending on the write operation to be performed the address MOTOROLA EXTERNAL BUS INTERFACE SIM 5 14 REFERENCE MANUAL lines may change during S0 Function code and size signals do not change 5 5 Operand Transfer Cases Table 5 3 summarizes operand alignment for various types of transfers Subsequent subsections discuss each allowable transfer case in detail In Table 5 3 operand bytes are designated as shown in Figure 5 7 OP0 OP3 rep resent the order of access For instance OP0 is the most significant byte of a long word operand and is accessed first while OP3 the least significant byte is accessed last The two bytes of a word length operand are OP0 most significant and OP1 The single byte of a byte length operand is OP0 Operand Byte Order 31 24 23 16 15 8 7 0 Long Word OP0 OP1 OP2 OP3 Three Byte OP0 OP1 OP2 Word OP0 OP1 Byte OP0 Figure 5 7 Operand Byte Order In Table 5 3 an X in a column means that the state of the signal has no effect Blank entries in the data bus columns represent bytes of the data bus that the CPU ignores during read cycles Operands in parentheses are placed on the data bus but ignored by the peripheral during write cycles The Next Cycle column indicates the number ofthe transfer case for the next bus cycle of the transfer operation A blank in the Next Cycle column indicates that the transfer is complete SIM EXTERNAL BUS INTERFACE MO
235. y add ing capacitance in parallel capacitors C1 and C2 CRYSTAL Tl MCU PINS HE XTAL EXTAL SMT XTAL LAYOUT Figure 4 3 Crystal Layout Example MOTOROLA SYSTEM CLOCK SIM 4 4 REFERENCE MANUAL 4 3 2 Crystal Tune up Procedure The following tune up procedure applies to crystals with frequencies below 1 MHz At higher crystal frequencies because Rs the resistance between the external oscillator and the XTAL pin is normally 0 this procedure is not needed For more specific tun ing instructions contact the crystal manufacturer The value of Rs can be determined experimentally by using the final PCB and an MCU of the exact type that will be used in the final application The MCU need not have the final software in place Because of the number of variables involved use components with the exact properties of those that will be used in production For example do not use a ceramic packaged MCU prototype for the experiment when a plastic packaged MCU will be used in production An emulator version of the part will also have slightly different electrical properties from the masked ROM version of the same part To determine the optimum value for Rs observe the operating current IppsvN of the MCU as a function of Rs The MCU should have only Vppsyn powered throughout this procedure because operating current variations when the MCU is running are much greater than the current variations due to varying Rs Normally a
236. y ceases after S2 refer to Figure 5 35 Negating and reasserting HALT in accordance with timing requirements provides sin gle step bus cycle to bus cycle operation The HALT signal affects external bus cy cles only so that a program which does not use the external bus can continue executing During dynamically sized 8 bit transfers external bus activity may not stop at the next cycle boundary Occurrence of a bus error while HALT is asserted causes the CPU to either process a bus error exception on CPU16 based MCUs or initiate a retry sequence on CPU32 based MCUs In the latter case retry cycles must be anticipated while debugging in single cycle mode In dynamically sized 8 bit transfers external bus activity may not stop at the next cycle boundary EXTERNAL BUS INTERFACE MOTOROLA REFERENCE MANUAL 5 45 When the MCU completes a bus cycle while the HAL signal is asserted the data bus goes to high impedance state and the AS and DS signals are driven to their inactive states Address function code size and read write signals remain in the same state The halt operation has no effect on bus arbitration Refer to 5 10 Bus Arbitration However when external bus arbitration occurs while the MCU is halted address and control signals go to a high impedance state If HALT is still asserted when the MCU regains control of the bus address function code size and read write signals revert to the previous driven states The

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