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MICROCOMPUTER MN103002A LSI User`s Manual

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1. Vss 0V 20 C to 70 C CL 50 pF Allowable values Item Symbol Conditions i T Min Max Unit DRAM mode data transfer signal output timing Refer to Fig 13 4 6 1 Read dat le signal fall delay ti ps2 Reac ata enable signal fall delay time A a s RE 4 4 7 1 53 Read data enable signal rise delay time necs is 2 B RE 4 1 54 Write data enable signal fall delay time A xs x ns 0 8 2 I 1 55 Write data enable signal rise delay time b WE 2 E ns WE3 0 4 te E Ese Write data delay time ben EE Nr ns D31 0 2 Write data hold ti 57 3 id a MEE 0 E58 Read data setup time tae 15 3 iii D31 0 59 Read data hold time _ 0 s D31 0 Note ty is SYSCLK cycle time 354 Characteristics Chapter 13 Electrical Characteristics la trow toot 2 1 0 Row Address Column Address RASA 1 lt traspr Es 4 lcasor tcasor RD WT ke QN read gt toreoR 031 0 in 32 bit bus mode D31 16 poene in 16 bit bus mode toros write gt 0 toweor D31 0 32 bit bus mode D31 16 in 16 bit bus mode pwop Fig 13 4 6 M
2. 55 0 TA 20 C to 70 C CL 50 pF Allowable values Item Symbol Conditions Unit Min Max Asynchronous mode data transfer signal output timing Refer to Fig 13 4 5 E36 Chip select signal fall delay time ERA _ 9 0 ni CS7 0 4 7 Chip select signal rise delay time 5 4 45 CS7 0 E38 Read data enable signal fall delay time MM 2 ig RE 4 E39 Read data enable signal rise delay time A 5 i 4 is RE E40 Write data enable signal fall delay time kuh k 5 2 X WE3 0 B mE E41 Write data enable signal rise delay time A 3 4 is WE3 0 EN 642 Write data delay time o 5 D31 0 Write data hold delay time UM 85 D31 0 4 p44 Read data setup time Bins 18 ae D31 0 E45 Read data hold time 0 _ a D31 0 AC Characteristics 35 Chapter 13 Electrical Characteristics CS7 0 t tcspra CSDF read RE tREDFA 031 0 32 bit bus mode J in 16 bit bus mode gt lt trosa lt write gt WES 1 p tweora D31 0 in 32 bit bus mode D31 16 in 16 bit bus mode ica Fig 13 4 5 Asynchronous Mode Data Trasnsfer Signal Timing Notes m in 1 changes depending on the setting contents of
3. Folloing annotation is added under the table i Varies according to the state of the instruction buffer The Ist line of main text The MN10300 Series The Ist line of main text The MN1030 Series Programming Cautions is added for PUTX Programming Cautions is added for PUTCX Following sentences are added to Programming Cautions of GETX When udf15 Dm Dn is operated Dm is ignored The operations of ud 15 imm8 Dn udf15 imm16 Dn and udf15 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases Following sentences are added to Programming Cautions of GETCHX When udf12 Dm Dn is operated Dm is ignored The operations of ud 12 imm8 Dn udf12 imm16 Dn udf12 imm32 Dn not assured In addition system error interrupt does not occur in these cases vii Following sentences are added to Programming Cautions of GETCLX When udf 13 Dm Dn is operated Dm is ignored The operations of 14513 imm8 Dn udf13 imm16 Dn and udf13 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases Operation of The range of significant values for the multiplier that is sto
4. lt 1 TM6IOB detect Edge detect lt 1 Make the output signal and input output setting in the I O port control register Fig 9 3 1 16 bit Timer Connection Diagram 226 System Configuration Chapter 9 16 bit Timers 9 4 Block Diagram Timer 4 Timer 5 TMnINO TMnINI TMnIN2 TMnIN3 TMnIN4 TMnIN5 TMnIN6 TMnIN7 p gt TMnCLK Clock output TMnBR Base register TMnCI Cascaded signal from Counting operation enable higher order timer gt TMnCO Cascaded signal p TMnIRQ Binary counter Underflow interrupt TMnMD p gt TMnOUT Mode register Timer output Reset Fig 9 4 1 16 bit Timer Block Diagram Timer 4 5 Timer 6 TM6INO TM6DREQ TM6IN1 DMA request TM6IN2 TM6BC TM IR TM6IN4 1 TMGINS TM6IN6 TM6IN7 TM6AIRQ B Compare capturc interrupt A TM6INA y 5 TM6CA S TM60UTA Compare capture register g gt gt 3 8 S B L TM60UTB TM6BIRQ Compare capture interrupt TM6CB Compare capture register B Fig 9 4 2 16 bit Timer Block Diagram Timer 6 Block Diagram 227 Chapter 9 16 bit Timers Timer 6 compare capture registers TM6CA TM6CB TM6BC Binary counter Capture timing Capture enabl
5. IYI st JOU 1 VY ue 8 jou sr uone1ed peyqrqojd 1 jou yey seor 81559595 930N LZ nuo 0 X4L00t87 X 921 Anus 0 X3 00 82 X 1 Knuo 0 XTOOOE8Z X 0 Anuo 0 0000682 C 4 10082 10082 XI0T028 X 0070 82 4 00082 00282 1000282 0000282 LTI Anus X4LTOT8C X 901 Anus XHLIOISZ X NEINENE GEH 1 Anua XIOIOISC X 0 Knuo 0070 80 I SsoJppy 0 List of Register Maps 373 sr jou st jeu vare ue JI poojuerens jou sr 40 si jou jeu seasg Surssoooy 293051 ALOWVAA ILNOJHH 0 EGG RTT ERE o nuoo OWLOWAN TALOWAN onuoo snq WLOSOI 000026 TALOWIN VHLONWSHW SALOWTN 9ALOWIW LYLOWAWN 1000026 20000 o LTI nuo 1 Ae 9c Anua 1 Anua 0 Anuo LTI nuo 0 9z Anus Q 1 Anua 0 Ke 0 0 LTI 901 nuo 1 key Anus IYI 0 Knuo
6. 186 7 4 2 16 Group 18 Interrupt Control Register 187 7 4 2 17 Group 19 Interrupt Control Register sess 188 7 4 2 18 Group 20 Interrupt Control Register sse 189 7 4 2 19 Group 21 Interrupt Control Register 190 7 4 2 20 Group 23 Interrupt Control Register 191 7 4 2 21 Group 24 Interrupt Control Register 192 7 4 2 22 Group 25 Interrupt Control Register 193 7 4 2 23 Group 26 Interrupt Control Register 194 7 4 2 24 Group 27 Interrupt Control Register 195 7 4 2 25 Group 28 Interrupt Control Register 196 7 4 2 26 Group 29 Interrupt Control Register 197 7 4 2 27 Group 30 Interrupt Control Register 198 7 4 2 28 Interrupt Acceptance Group Register 199 7 5 Chapter 8 8 1 8 2 8 3 8 4 8 5 8 6 8 7 Chapter 9 9 1 9 2 9 3 9 4 9 5 9 6 7 4 2 29 External Interrupt Condition Specification Register 200 Description of Operation
7. 259 Fig 9 7 19 Operation of Interval Timer on Timer 6 When Using 1 259 Fig 9 7 20 Event Counting Operation When Select the Rising Edge 261 Fig 9 7 21 Additional Bit Style PWM Output 1 ceci terio tio repertus 264 Fig 9 7 22 Additional Bit Style PWM Output 2 1 tette tette tete 264 Chapter10 Watchdog Timer Fag 10 3 T Block E battu Diosa td Meee aes 267 Fig 10 5 1 Operation Diagram 1 When Reset Is Released 272 Fig 10 5 2 Operation Diagram 2 When Recovering from Stop 273 Fig 10 5 3 Operation Diagram 3 Watchdog Operation 274 Chapter 11 Serial Interfaces Lig tI Structural Diag ran 278 Fig 11 3 1 Serial Interface 0 Serial Interface 1 Block Diagram seee 281 Fig 11 3 2 Serial Interface 2 Block Diagram 0020444 220 tette tette trt trente 282 Tag 11 5 1 Connections 295 Fig 11 5 2 Connections 295 11 553 3 eit ioci ete ecco 296 Pig Died Timing AR ed bite tcu td e UNDE 299 Ing 11 5 5 Timing Chart 2 5 eret t
8. Crystal Oscillator C2 Use and C2 that will result in the optimal circuit characteristics Fig 13 3 1 Recommended Self excited Oscillation Circuit DC Characteristics 343 Chapter 13 Electrical Characteristics 13 4 AC Characteristics Tables 13 4 1 through 13 4 12 show the AC characteristics 13 4 1 Reset Signal Timing Table 13 4 1 AC Characteristics 1 VDD 3 3 V 0 165 Vss 0V 20 C to 70 C CL 50 pF Allowable values Item Symbol Conditions Unit Min Typ Max Reset input timing Refer to Figs 13 4 1 and 13 4 2 e Reset signal pulse width 17 Pin 5 5 ns RST testw FRQS 24 teye high Power on oscillation stabilization time _ 1 aii E2 VDD RSTN Input clock frequency switching signal setup time PN _ 4 FRQS Mode setting signal setup time E4 5 x ms MMODE trstmms 0 5 ES Bus mode switching signal setup time 3 0 5 bis BMODE Characteristics Chapter 13 Electrical Characteristics t RSTW Fig 13 4 1 Reset Timing 1 VDD 2 916 V gt tastn RST FRQS MMODE g BMODE 1 5 5 Fig 13 4 2 Reset Timing 2 AC Characteristics 345 Chapter 13 Electrical Characteristi
9. CD Output data from device with Output data from device with Output data from device with acknowledge function acknowledge function DMA cycle m sc O DMR sampling Fig 6 4 5 One Bus Cycle Transfer Burst Transfer DMR Edge Detection Synchronous Mode Fig 6 4 5 shows the timing chart for a burst transfer in synchronous mode from an external device that supports the acknowledge function to external memory initiated by edge detection of a DMA request signal DMR from an external source Once the edge is detected detection does not occur again until the burst transfer is completed 156 Description of Operation Chapter 6 Controller bus cycle transfer single word transfer DMR edge detection asynchronous mode Transfer devices External memory External device with acknowledge function Transfer method One bus cycle single word transfer DMR edge detection Bus mode 32 bit bus asynchronous mode one wait state nnnnnnnnnnmnnnnnnnnnnnnnnnnnn A31 0 CPU DMA X X DMA y CPU D31 0 DMR DMK DNE I DIR DMA cycle DMA cycle O DMR sampling Fig 6 4 6 One Bus Cycle Transfer Single word Transfer DMR Edge Detection Asynchronous Mode Description of Operation 157 Chapter 6 Controller MOERS FESSES SETTE TP eal ca eee IDE al oe A31 0 CPU Y
10. erouduog LUXA esoyduag ja 81 IJANU 9107 snq gp snq 55 1 snq og 5 snq 5 haa iid 815 Fig 5 4 1 shows the block diagram for the bus controller The bus controller consists of controller CPU interface an on chip interface an external device interface and a controller 5 4 Block Diagram 85 Block Diagram Bus Controller Block Diagram Fig 5 4 1 Chapter 5 Bus Controller 5 5 Pin Functions 1 2 Note to 1 and CAS3 to 1 are shared pins and CS7 and A31 and CS6 to 4 and A28 to 26 are shared pins 86 Table 5 5 1 External Pin Functions Relating to the Bus Controller Input output Pin name Function OSCI Input Oscillator input pin 13 0 MHz to 33 3 MHz OSCO Output Oscillator output pin 13 0 MHz to 33 3 MHz FRQS Input Input frequency setting 1 13 0 MHz to 16 6 MHz 0 26 0 MHz to 33 3 MHz SYSCLK Output System clock output same frequency as the input clock A31 0 Output Memory address output Row column address multiplexed output when DRAM is connected Input output Memory data input output D31 to 16 for a 16 bit bus Output DRAM RA
11. 202 8 bit Timers M 206 Inn eem E 206 System Configuration three teret 207 Block Diagram 207 List of Functions 209 Description of Registers ona n rne 210 8 6 1 Timer n Mode Register n 0 1 2 3 sss 211 8 6 2 Timer n Base Register n 0 1 2 3 212 8 6 3 Timer n Binary Counter n 0 1 2 9 213 8 6 4 Prescaler Control Register 213 Description Of Operation sinisa et i 214 8 7 1 Interval Timer Timer Output 2 44 2 1 000 04400 6060 00 6 8 0 04291 214 8 7 2 Event Counting Operation essent ennt 217 8 7 3 Cascaded Connection nito deed T M e 218 8 7 4 Example of Prescaler Timer and Cascaded 220 16 bit Timers E 224 etit te tet 224 System Configuratio o ensani outer 226 Block Diagram nene deeun 227 Lastof Func ons ae eee eret ttd 229 Description of i Bee 230 9 6 1 Timer Mode
12. 36 2 7 2 2 Interrupt Control Registers 1 37 2 1 2 3 Interrupt Accept Group Register 1 39 2 1 24 Interrupt Vector Registers 39 2 7 3 Interr pt Types ege o e ence eti 40 2592 Reset S 40 2 7 3 2 Nonmaskable 40 2 7 3 3 Level Interrupts esssesessseeeeerttee 41 2 7 4 Interrupt Operation essere 42 2 7 4 1 Interrupt Sequence sess 42 2 7 4 2 Nested Interrupts 2220 2 02200444100000 ettet retten ra 46 2 7 4 3 Interrupt Acceptance Timing sese 46 27 44 Stack Frame he eere tette tete le eu 46 2 8 Operating Modes dta Prades ted 47 2 8 1 pP 47 2 8 2 Reset 48 2 8 3 Low Power Consumption 49 Chapter 3 Generator 3 1 OVEIVIGW e GN A eee HO ae a tore RU EON 52 3 2 c 52 3 3 Block Diagram eere tee aia a En e 53 3 4 Description of 1 1 70 2 400 2 22 2 44 54 3 4 1 Input Frequency Setting
13. A31 0 Row Colum Column Te Hii del precharge precharge CAS3 0 2 EET WE3 0 D31 0 UT 2s cess SIZE1 0 eo A Read cycle r Write cycle gt Fig 5 8 18 32 bit DRAM Read Write Timing When FRQ 1 120 Description of Operation 5 A31 0 RowX Column X_ X RowX Column MEN Column X Column RASn precharge T precharge precharge CAS3 2 HEL E WE3 2 D31 16 HOT 2272 RD WT um 81261 0 Lower half Upper half Lower half Upper half word read cycle word read cycle word write cycle word write cycle Fig 5 8 19 16 bit DRAM Read Write Timing When FRQ 1 5 8 5 3 Page Mode DRAM page mode when FRQ 0 If the PAGE bit in the DRAM control register is set page mode access is enabled making high speed access in page mode possible for consecutive accesses to DRAM The byte specification by WE3 through 0 is set by clearing the BnCAS bit in memory control registers 1 through 3 The RAS signal and in the case of a write the WE signal are negated as soon as the consecutive accesses to DRAM are completed The byte specification by CAS3 through 0 is set by setting the BnCAS bit in mem
14. D31 is LO TE RD WT 51781 0 7 ty tH a a N 2waitok p 4 2 wait ok p 4 2waitok P Lower half Upper half word Lower half word Upper half word word read cycle read cycle write cycle write cycle Fig 5 8 8 Timing for Access in 16 bit Bus Synchronous Mode with Fixed Wait State Insertion Two Wait OK Fig 5 8 9 is a timing chart for an access with a 16 bit bus and handshaking specified When handshaking is specified the data acknowledge signal DK is sampled at the rising edge of SYSCLK and if it is asserted the bus access ends at the next cycle Note that when the DK signal is found to have been asserted it is not sampled in the next cycle Bus access termination by handshaking is valid only in synchronous mode YSCLK A31 0 AI CU SIZE1 0 Ge QUEM INS Ga NNNM Lower half Upper half word Lower half word Upper half word word read cycle read cycle write cycle write cycle Fig 5 8 9 Timing for Bus Access by 16 bit Bus Handshaking 112 Description of Operation Chapter 5 Bus Controller 5 8 4 2 Asynchronous Modes 32 bit bus asynchronous mode when FRQ 0 Asynchronous mode is used for accessing external memory at high speed the address signals CS signals etc are output asynchronously with the external clock but synchronously with the internal MCLK In asynchronous mode accesses
15. uw lt as 9 o 50 o e 0207020 0 70 020 I l ooooooooooo 200000000000 lt 0 855 10 00 11 00 2015 426 Package Outline and Dimensions 123 5 5678 9 10111213 BOTTOM VIEW TOP VIEW Epoxy resin Sealing resin Ceramic Body material Au plating Lead finish method Fig F 2 Package Outline and Dimensions of MN103002AYB The correction table The Revised Edition of MN103002A LSI User s Manual From 3rd Edition 1st Printing to 5th Edition i MN103002AYB CSP has been added to the products described in this LSI User s Manual since 5th edition Accordingly the product name is changed partly in writing In the 7th line of 1 1 Overview 3 3 V 5 In the 7th line of 1 1 Overview 3 3 V 0 165 V The following sentence is added at the end of 1 1 Overview MN103002AYB is a product with 103002 package changed to CSP and includes the same function and performance as MN103002A Supports high speed p
16. 365 Fig 13 4 17 Serial Interface Signal Timing 1 during synchronous serial reception 366 Fig 13 4 18 Serial Interface Signal Timing 2 during synchronous serial transmission 367 Fig 13 4 19 AC Timing Test Voltage Levels s ccsssssssssesssesssssssssssssssesssssssecsecvessscnsssucsasssssacesecsseceness 367 xvii xviii Appendices Fig E 1 Fig E 2 Fig E 3 Fig E 4 Fig E 5 Fig E 6 Fig E 7 Fig F 1 Fig F 2 Block Diagram of the Extension Function 383 Extension Function Unit Register Set c ccccscsssscsssssssssssseccscssessesessesesecsesecseseaescsrsaseavees 385 Pipeline Diagram Illustrating This Note 0 2 0 00020440 419 Pipeline Diagram Illustrating This Note 2 420 Pipeline Diagram Illustrating This Note 3 222 02200000212 421 Pipeline Diagram Illustrating This Note 4 422 Pipeline Diagram Illustrating This Note 5 0 020204110000 423 Package Outline and Dimensions of 103002 s 425 Package Outline and Dimensions of MN103002AYB eere 426 List of Tables Chapter 1 General Table 1 4 1 103002 Pin Assignments 4400 4 11010110100 tette tentent tentent ret btts 7 Table 1 4 2 MN103002AYB Pin Assignments essere trt 9 Table 1 4 3 List of MN103002A MN103002A YB Pin Functions tee 10 Chapter 2 CPU Ta
17. 54 3 4 2 Internal Clock Supply 0 0 0 ce csssescsesssssssesssesescsesescesscscsssssscscsssescassessecavarecacaens 54 Chapter 4 4 1 OVERVIEW adiens reli idt 58 4 2 Features inne neret teen de ERR bee piedi eee dete ORE 58 4 3 Confipur tion z eet a cederet 59 4 3 1 Instruction Cache ee i sg ER et pe ee DLE 59 4 3 2 D ta Cache 60 4 4 Description of Registers sess 62 4 41 Cache Control Register 2 0200000 0101 tette ens 62 4 5 Description of 64 4 5 1 Instruction Cachesida 64 64 4 5 1 2 Read Operation 2 1 1 1 1 2 0202 0 000000000101010 005000000000 65 iii lt gt 4 6 Chapter 5 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 4 5 2 Data Cache a SERIE ATI as oret 68 4 5 2 4 idc ADR IRR 68 4 5 22 Read 69 4 5 23 Write Operation 0 eeecesssssssssssssesececsssscesssesessssevscscesssevsssescensaens 72 4 5 2 4 Consistency between the Cache and the External Memory TI 4 5 3 Way Operatio
18. control register 2 Register symbol DM2CTR Address x 32000400 Purpose Sets the transfer parameters for DMA channel 2 Bit name EO CUN PRUE RT RT RT RI Bi name Bit position Bit name Description 0 DM2BGO DMA channel 2 initiation source LSB DM2BGI DMA channel 2 initiation source 2 DM2BG2 DMA channel 2 initiation source 3 DM2BG3 DMA channel 2 initiation source 4 DM2BG4 DMA channel 2 initiation source MSB 00000 Software source 00001 Setting prohibited 00010 Serial 0 transmission end source 00011 Serial 0 reception end source 00100 Serial 1 transmission end source 00101 Serial 1 reception end source 00110 Serial 2 transmission end source 00111 Serial 2 reception end source 01000 Timer 2 underflow source 01001 Timer 3 underflow source 01010 Timer 6A compare capture source 01011 Setting prohibited 01100 IRQO input source 01101 IRQI input source 01110 External request 2 source 01111 External request 3 source 10000 to 11111 Setting prohibited Continued Description of DMA Registers 143 Chapter 6 Controller Continued Bit position 5 10 11 12 24 Bit name DM2ST DM2SAMO DM2SAMI DM2DAMO DM2DAMI DM2DIR DM2TMO DM2TMI DM2UTO DM2UTI DM2RQM DM2TEN DM2RQF Description DMA channel 2 transfer type 0 Two bus cycle transfer 1 One bus cycle transfer Transfer between external memory and an external device that
19. Fig 9 7 22 Additional Bit Style PWM Output 2 264 Description of Operation Chapter 10 Watchdog Timer Chapter 10 Watchdog Timer 10 1 Overview This microcontroller has a 25 bit binary counter built in that can be used as a 16 to 25 bit watchdog timer nonmaskable interrupt and the watchdog timer overflow output can be generated in response to a watchdog timer overflow The watchdog timer is also used as an oscillation stabilization wait timer 10 2 Features The number of bits in the binary counter is selectable When the FRQS pin input is High oscillating frequency 13 0 MHz to 16 6 MHz 16 18 20 22 or 24 bits When the FRQS pin input is Low oscillating frequency 26 0 MHz to 33 3 MHz 17 19 21 23 or 25 bits Overflow cycle 3 972 ms to 1016 801 ms when the FRQS pin input is High and the oscillating frequency is 16 5 MHz 3 972 ms to 1016 801 ms when the FRQS pin input is Low and the oscillating frequency is 33 MHz nonmaskable interrupt is generated when a watchdog timer overflow occurs Watchdog timer overflow output When an overflow occurs the watchdog timer overflow output is output to the WDOVF pin The watch dog timer overflow output can be selected as either pulse output or level output Oscillation stabilization wait time when the FRQS pin input is high and the oscillating frequency is 16 5 MHz When reset is released 15 888 ms When recovering from STOP
20. oria v cip E 19 24 Data Formats aste boa ha eot 22 2 5 Instructions terrere i ne eeu e 23 2 5 1 Instruction Format c ccccsessesessesesessesesseeseseccssssnsscsesscsssscsessesucansesaneatsacevens 23 2 5 2 Addressing Modes 24 2 5 3 8 ste eat opere iet 26 2 5 5 1 Transfer Instructions 4244 0 27 2 5 3 2 Arithmetic Operation Instructions 2 000 28 2 5 3 3 Compare Instruction seen 28 2 5 3 4 Logical Operation Instructions 29 2 5 3 5 Manipulation Instructions 29 2 5 3 6 Shift Instructions essere 30 2 5 3 7 Branch Instructions cesesescssesescsssseseseessscssessessnvsesesessrsrssestenescaees 30 2 5 3 8 Instruction 22 4 1 1 0 2 22202 12 1011 00 010101000 31 2 5 3 9 Extension Instructions 31 2 6 Memory Map tren hl te 32 2 7 Interrupt Functions sess tette ttt tiet 34 2 71 HE 34 22 Interrupt related Registers ssec 36 2 7 2 1 Processor Status Word Register PSW
21. 123 32 bit DRAM Page Mode Read Timing When 1 124 32 bit DRAM Page Mode Write Timing When 1 sees 125 16 bit DRAM Page Mode Read Timing When 1 125 16 bit DRAM Page Mode Write Timing When 1 126 DRAM Refresh Operation essere terere tenerte 127 Setting the DRAM Refresh Timing 20 retain 128 DRAM Refresh Timing When all blocks that are set in blocks 1 through 4 of DRAM are set for WE byte specification and 0 128 DRAM Refresh Timing When CAS byte specification is set and 1 129 Memory Connection Example When DRAM Byte Specification Is By WE 130 Memory Connection Example When DRAM Byte Specification Is 131 Bus Arbitration Timing 1 Bus Authority Release Bus Authority 0 132 Bus Arbitration Timing 2 Refresh Request Generated While Bus Authority Has Been Released and 0 essere terree ttes 133 Chapter 6 Controller Example of Transfer in Single word Transfer Mode sse 149 Example of Transfer in Burst Transfer 150 Example of Transfer in Intermittent Transfer Mode seeeeee 15
22. 4 VT A Wi RE WE3 0 LT LE D31 0 SIZE1 0 cat i A Write Write Write 9 Write gt cycle cycle cycle cycle Fig 5 8 25 32 bit DRAM Page Mode Write Timing When FRQ 1 1 0 Row ColumnX ColumnX ColumnX ColumnX ColumnX ColumnX ColumnX ColumnX RASn E SIZE1 0 CREME Gen Gren QNMD gt lt gt Ld N gt Read Read Read Read Read Read Read Read cycle cycle cycle cycle cycle cycle cycle Fig 5 8 26 16 bit DRAM Page Mode Read Timing When FRQ 1 Description of Operation 125 Chapter 5 Bus Controller A31 0 Row ColumnX ColumnX ColumnX ColumnX ColumnX ColumnX ColumnX Column RASn 3 2 WE3 2 D31 16 RD WT SIZE1 0 gt lt Write Write Write Write Write Write Write Write cycle cycle cycle cycle cycle cycle cycle cycle Fig 5 8 27 16 bit DRAM Page Mode Write Timing When FRQ 1 126 Description of Operation
23. Fig 5 8 4 Timing for Access in 32 bit Bus Synchronous Mode with Fixed Wait State Insertion One Wait OK SSS 1 0 i WE3 0 D31 0 RD WT SIZE1 0 4 2 wait ok ae ie 2waitok Read cycle Write cycle Fig 5 8 5 Timing for Access in 32 bit Bus Synchronous Mode with Fixed Wait State Insertion Two Wait OK Description of Operation 109 Chapter 5 Bus Controller Fig 5 8 6 is a timing chart for an access with a 32 bit bus and handshaking specified When handshaking is specified the data acknowledge signal DK is sampled at the rising edge of SYSCLK and if it is asserted the bus access ends at the next cycle Note that when the DK signal is found to have been asserted it is not sampled in the next cycle Bus access termination by handshaking is valid only in synchronous mode L LJ eS S E RD WT es EE ue ga 51281 0 Write cycle Fig 5 8 6 Timing for Bus Access by 32 bit Bus Handshaking 11 0 Description of Operation Chapter 5 Bus Controller 16 bit bus synchronous mode 16 bit bus mode can be entered by inputting 0 to the BMODE pin for block 0 or by setting 0 in the
24. SCnOEF flag D D SCnPEFflg 2 o MEE SE SCnFEF flag Interrupt N DMA request 1 1 1 1 1 Fig 11 5 14 Timing Chart 11 Description of Operation 307 Chapter 11 Serial Interfaces Transfer in clock synchronous mode with 8 bit data length and parity on SBlpin ir T ep2 wi we 55 6 7 e SCnRXF SCnRBF flag SCnOEF flag E 1 1 1 1 D i t 1 SCHPEF fig Interrupt request Fig 11 5 15 Timing Chart 12 A DMA request is generated at the moment that reception ends regardless of whether or not an error occurred When reception end is set as the reception interrupt source an interrupt request is generated when reception ends regardless of whether or not an error occurred When reception end with error is set as the reception interrupt source an interrupt request is generated when reception ends with an error having occurred The interrupt request is not generated at the moment that the error occurred 308 Description of Operation Chapter 11 Serial Interfaces 11 5 2 Serial Interface 2 11 5 2 1 Connection Start stop synchronous mode Two different connection methods are possible one is unidirectional transfer and the other is bidirectional transfer The SBO2 pin i
25. i Lc exa External interrupt 4 cow Z E TOV External interrupt 5 28 x 34000170 External interrupt 6 cu 1 a E DAS See External interrupt 7 Jif o ver x Fig 7 3 5 Block Diagram 4 11 1 Configuration 167 Chapter 7 Interrupt Controller 7 4 Description of Registers This interrupt controller includes interrupt control registers an interrupt acceptance group register and an external interrupt condition specification register Register list Address The registers are described the pages that follow Table 7 4 1 Register List Register name Symbol Number of bits Initial value Access size x 34000100 Non maskable interrupt control register GOICR NMICR 16 x 0000 8 16 x 34000108 Group 2 interrupt control register G2ICR 16 x 0000 8 16 x 3400010C Group 3 interrupt control register G3ICR 16 x 0000 8 16 x 34000110 Group 4 interrupt control register G4ICR 16 x 0000 L 8 16 x 34000114 i Group 5 interrupt control register GSICR 16 x 0000 8 16 x 34000118 Group 6 interrupt control register G6ICR 16 x 0000 8 16 3400011 Group 7 interrupt control register G7ICR 16 x 0000 8 16 x 34000120 Group 8 interrupt control register
26. 0 EE BE 4 710 821 XHLTOY8C X 5 1 1 1 L 1 1 i 0 1 1 1 1 i 1 1 1 D T i D 1 T D D 1 1 D 1 1 1 1 D D i D z t 1 1 i 1 1 i i T 1 1 1 1 i 1 1010780 0070 82 aes 4 00782 1 D X3L00v87 X L 5 1000782 0000 82 XALTOE8T 1X XHLIOESC X 5 XTOTOE8T X 8 X Y D 1 D 1 1 1 1 D i 1 T 1 j 1 T D 1 T 1 D D 1 1 1 1 T 1 1 T 4 i D 1 1 1 T 5 D T 1 1 i 1 1 1 1 1 1 j 1 1 1 21 374 List of Register Maps Appendices possoooe st pojunoui jou 1 Jey Bare ue jr 8 zou sr uone1ed poiqrgoid st jou IEY 58918 Suissoooy NON IWAJU 412055 ds 08000 o 82000 CQWLXd X02000vt X
27. 9 7 2 3 Setting of Pin Output Any type of output wave is available for TM6IOA TM6IOB pin using timer 6 1 Setting for the initial output level Initializing timer 6 with the setting TM6LDE flag of TM6MD 1 cause TM6IOA pin output level to be the value in TM6AEG flag of TM6MDA register Similarly TM6IOB pin output level is value in TM6BEG flag of TM6MD register Once switched to the normal operating mode set 0 for TM6LDE flag of TM6MD register the pin output level never changes even the TM6AEG TM6BEG flag is changed 2 Setting for output wave during count operation TM6IOA pin has wave set into 6 00 1 2 as output wave when count operation of timer 6 is permitted by setting TM6CNE flag of TM6MD to 1 Similarly TM6IOB pin output wave equal to the wave set in 6 0 1 2 flag of TM6MDB register TM6AEG flag setting is used only to change the output level Le Output level stays until the next output is changes after the setting is replaced Example of TM6IOA pin output wave is shown below They are exactly same for TM6BIO Fig 9 7 8 shows the TM6IOA pin output wave in the case Simultaneously set and reset for TM6BC and TM6CA Reset has higher priority than set if the set and reset are generated simultaneously Match TM6BC with TM6CA 4 gi A Match TM6BC with TM6CB 4 7 F T TMGIOA pin output When TM6AEG 0 TMGIOA pin output When TM6AEG 1 TUUS du dE Fig
28. 339 DC Characteristics eee och lee tet op etd 340 13 4 AG Characteristis a 344 1341 Reset Signal Timing sse tette rtnentntntr ene 344 13 4 2 Clock Timing nee o eer rer 346 13 4 3 Address Data Transfer Signal Timing sese 348 13 4 4 Arbitration Signal 359 13 45 DMA Signal Timing e brodo dett 361 13 4 6 Interrupt Signal Timing essent trennen 362 13 4 7 Timer Signal Timing sss tntnt nente tras 363 13 4 8 Watchdog Timer Signal Timing esssseeseeeeeeeeeee 365 13 4 9 Serial Interface Signal Timing eeeeeeeerrees 366 13 4 10 Characteristics Test Conditions 367 Appendices Appendix A Treatment of Pins seesesssseseee eene 370 Appendix B External Pin Statuses essent 371 Appendix List of Register Maps 372 Appendix D Instruction S t asocian ii teret tete teer 377 Appendix E Extension Instruction Specifications RO 383 Appendix F Package Outline and Dimensions 2 2 425 xi xii List of Figures and Tables List of Figures Chapter 1 General Fig 1 3 1 MN103002A MNI103002A YB Block Diagram 2222
29. D31 0 in 32 bit bus mode D31 16 in 16 bit bus mode Fig 13 4 7 DRAM Page Mode Data Transfer Signal Timing AC Characteristics 357 Chapter 13 Electrical Characteristics Table 13 4 9 AC Characteristics 9 VDD 3 3 0 165 V Vss 0V 20 C to 70 C CL 50 pF Allowable values Symbol Conditions Unit Min Max DRAM refresh signal timing Refer to Fig 13 4 8 tc E66 Row address strobe signal fall delay time 2 _ RASA 1 2 tc 3 E67 Row address strobe signal rise delay time 2 fics x Nb ns RASA 1 2 E68 Column address strobe signal rise delay time 2 TER E CAS3 0 4 P Notes 1 1 is the SYSCLK cycle time 2 n change according to the DRAMCTR and MEMCTRO setting The correspondence is shown below 64 ia RERP nr When 0 n 2 and when 1 n 4 RASA 1 traspr2 ra gt traspre CAS3 0 N nn gt tcasore Fig 13 4 8 DRAM Refresh Signal Timing 358 AC Characteristics Chapter 13 Electrical Characteristics 13 4 4 Bus Arbitration Signal Timing Table 13 4 10 AC Characteristics 10 VDD 3 3 0 165 V Vss 0V 20 C to 70 C CL 50 pF P Allowable values
30. GROUP ba The interrupt level can be set independently for each group However GROUPO and GROUPI are non maskable x 3400011C Fig 7 3 2 Block Diagram 1 164 Configuration Chapter 7 Interrupt Controller Timer 6 underflow GROUP Timer 6A GROUP Timer 6B GROUP Reserved for system GROUP DMAO transfer end GROUP DMAI transfer end GROUP 13 DMA2 transfer end GROUP 14 DMA3 transfer end GROUP 15 Interrupt control register address x 34000120 x 34000124 x 34000128 x 34000130 x 34000134 x 34000138 x 3400013C Fig 7 3 3 Block Diagram 2 Configuration 165 Chapter 7 Interrupt Controller GROUP 16 GROUP 17 GROUP 18 GROUP GROUP GROUP GROUP N N N EZ Serial 0 receive Serial 0 send Serial 1 receive Serial 1 send Serial 2 receive Serial 2 send Reserved for system Interrupt control register address x 34000140 x 34000144 x 34000148 x 3400014C x 34000150 x 34000154 166 Configuration Fig 7 3 4 Block Diagram 3 Chapter 7 interrupt Controller Interrupt control register address o External interrupt 0 croup 5 Wile External interrupt 1 GROUP ted JEN e ll External interrupt 2 GROUP EU NECEM x 34000164 deer lj CESE o External interrupt 3 wow ae Cd
31. 140 5 Fig 1 4 1 MN103002A Pin Assignment Diagram 22 2 0 00 6 Fig 1 4 2 MN103002AYB Pin Assignment Diagram 8 Chapter 2 CPU Fig Fig Fig Fig Fig 2 6 1 Fig Fig Fig Fig Fig Fig Fig Fig Fig 2 2 1 2 3 1 2 3 2 2 4 1 2 5 1 2 7 1 2 7 2 2 7 3 2 7 4 2 7 5 2 7 6 2 7 7 2 8 1 CPU Core Block 15 Register Set sis te t E e e 16 Processor Status d ti dtp AER 17 Little Endian Format s seno eet lp ote ditata ht dan ncs 22 Instruction Format Types esset ttt rtett 23 MN103002A MN103002A YB Memory 33 Overview of the Interrupt System 35 Interrupt Control Register GnICR 37 Interrupt Accept Group Register s hau dept cue 39 Interrupt Vector Register 39 Flow of Interrupt Sequencers ERR E ANDR ri d 44 Flow of Interrupt Sequence base iti et b e eue 45 Stack Frame Configuration eiue Enn ER ies hans tics i oett eu n 46 Operating Mode Transition Diagram 47 Chapter 3 Clock Generator Fig 3 3 1 Clocke Generation amt faeta RR Rena tere dic n A d 53
32. 425 41 P40S 4 to 7 334 4 Bit name Description P40S 415 425 435 Pin output content selection 0 Address output A31 1 Chip select signal CS7 Pin output content selection 0 Address output A28 1 Chip select signal CS6 Pin output content selection 0 Address output A27 1 Chip select signal CS5 Pin output content selection 0 Address output A26 1 Chip select signal CS4 Always returns 0 Chapter 12 Ports 12 6 2 Pin Configuration Table 12 6 1 shows the pin configuration for port 4 Table 12 6 1 Port 4 Configuration Port P4n Port 4 P40 P41 P42 P43 P4nM 1 P4nM 0 1 Address output A28 Address output A27 Address output A26 Address output After a reset Port 4 335 Chapter 12 Ports 336 Pot4 Chapter 13 Electrical Characteristics Chapter 13 Electrical Characteristics This LSI manual describes the standard specifications When using this LSI contact our sales department for the product standards 13 1 Absolute Maximum Ratings Table 13 1 1 shows the absolute maximum ratings Table 13 1 1 Absolute Maximum Ratings Vss PVss 0 0 V Item Symbol Ratings Unit Al Supply voltage Vpp 03 to 46 V A2 PLL supply pin PVDD voltage 0 3 to 46
33. MD BR WTMD INV INV BUSY BUSY Bit No Bit name Description 0 IGEN Instruction cache enable This bit indicates whether or not the instruction cache is to be used 0 Instruction cache disabled 1 Instruction cache enabled 1 DCEN Data cache enable This bit indicates whether or not the data cache is to be used 0 Data cache disabled 1 Data cache enabled 2 ICBUSY Instruction cache busy This bit indicates whether the instruction cache is busy or not This bit must be checked when accessing the contents of data memory or tag memory directly 0 Instruction cache not busy 1 Instruction cache busy Continued Description of Registers 1 0 4 Continued Bit No Bit name Description 3 DCBUSY Data cache busy This bit indicates whether the data cache is busy or not This bit must be checked when accessing the contents of data memory or tag memory directly 0 Data cache not busy 1 Data cache busy 4 ICINV Instruction cache invalidate Writing a 1 to this bit invalidates all of the instruction cache ways and entries This operation is performed by clearing the valid bits V for all of the entries in tag memory This bit always returns a 0 when it is read 5 DCINV Data cache invalidate Writing a 1 to this bit invalidates all of the data cache ways and en tries This operation is performed by clearing the valid bits V for all of the entries in tag memory T
34. OO 090 OO 00 Overview 315 Chapter 12 Ports 12 2 Port 0 12 2 1 Block Diagram Fig 12 2 1 shows the block diagram for port 0 Internal data bus POOUT W 27 0 Data bus output enable PODIR W PODIR R POMD W D7 0 Port 0 pin 07 00 Fig 12 2 1 Port 0 Block Diagram 07 to 00 316 Porto Chapter 12 Ports 12 2 2 Description of Registers Port 0 is a general purpose input output port that also can be used as the data bus signals D 7 0 Each register for port 0 is described below 12 2 2 1 Port 0 Output Register Register symbol POOUT Address x 36008000 Purpose Sets the data that is to be output on port 0 mw TT T T5 T4 T5 gt P070 P060 P050 P030 P020 P000 name o 9 9 9 9 12 2 2 2 Port 0 Output Mode Register Register symbol POMD Address x 36008020 Purpose This register selects the port O pin output content Bit No Bit name Description 0 P00M Port 0 pin output content selection 0 Data input output D7 to DO 1 General purpose I O port P07 to P00 17 Always returns 0 Poto 317 Chapter 12 Ports 12 2 2 3 Port 0 Input Output Control Register Register symbol PODIR Address x 36008060 Purpose This register sets the input output direction of the port 0 pins 0 input pin 1 output pin
35. b Just before rti instructions return from interrupt handler execute dummy accesses shown below mov 0x0 b SP 40 mov Ox4 b SP 40 mov a0 40 Make sure that address a0 is within the uncachable space c It is necessary that the instruction that reads from the uncachable space is placed at the return address of the subroutine call instruction call 2 If either of two ways is need to be lockd lock the way 1 74 Description of Operation Chapter 4 Caches Cache Hit Operation If data is written to a cacheable space x 00000000 to x 1FFFFFFF or x 40000000 to x 7FFFFFFF while the data cache is enabled the data cache tag array is accessed using the tag entry address field bits 10 to 4 of the data address as the address If the value in the tag address field TADD of the accessed entry matches the value in the tag field of the data address and the valid bit V of that entry has been set to 1 then a hit is said to have occurred during the write access to the data cache If a hit occurs in the write access to the data cache the data is sent from the CPU to the corresponding entry line in the data memory section At the same time data is written to the corresponding address in external memory Because the data is written simultaneously to the data cache and to the external memory consistency between the data in the data cache and the data in the external memory is maintained Oper
36. 278 Instruction Set Appendices Instruction Source Destination Code Length Number of registers with regs specification 4 Number of registers with regs specification 7 Number of registers with regs specification 8_ Number of registers with regs specification 9 Number of registers with regs specification 10 Number of registers with regs specification 11 Dn is a value that can be expressed by 1 byte Dn is a value that can be expressed by 2 byte Dn is a value that can be expressed by 3 byte Dn is a value that can be expressed by 4 byte Dnz0 Dn is a value that be expressed by byte Dn is a value that can be expressed by 2 byte _ Dn is a value that can be expressed by 3 byte Dn is a value that can be expressed by 4 byte MMDRDn 0 ____ Dn is a value that can be expressed by 1 byte MDR Dn is a value that can be expressed by 2 byte MDR Dn is a value that can be expressed by 3 byte MDR Dn is a value that can be expressed by 4 bytes or more MDR Dn 0 MDR Dn is a value that can be expressed by 1 byte Instruction Set 379 Appendices Instruction Code Length Number of Cycles abs32 Dm An imm8 d8 An imm8 abs32 Dm _ imms dA D2 i D5 imm8 5 0 D2 D5 Varies according to the state of the instruction buffer 380 Instruction Set 221 2 amp Joa 4 1 5 2
37. Chapter 5 Bus Controller 5 8 5 4 Refresh If the REFE bit in the DRAM control register is set CAS before RAS refresh is performed at the interval set by the refresh count register Fig 5 8 28 illustrates the refresh operation concept The refresh interval is the product of the value of the REFC bits in the refresh count register and the SYSCLK frequency If the REFE bit in the DRAM control register is set the refresh count register operates as a down counter that counts down from the REFC value to 0 The refresh operation is executed once in an idle external bus cycle during the period while the refresh count value is counted down from REFC to 0 If due to a DMA access or other such operation there is no idle external bus cycle before the refresh count value reaches 0 then a refresh cycle is inserted right after the bus cycle that is being executed at the moment the refresh count value reaches 0 is completed If a DMA burst transfer is in progress the burst transfer is interrupted Regarding the output timing of the RAS CAS signals during the refresh operation the RAS assertion period can be set through the RERP bit in the DRAM control register as shown in Fi 5 5 8 29 The number of cycles is given in terms of the number of MCLK cycles In 32 bit bus mode when all of the blocks that are set in blocks 1 through 4 of DRAM are set for WE byte specification CAS3 is asserted if CAS byte specification is set CAS3 through 0 are asserted
38. In the mathematical expression 15 888 ms T The 1st line of 4 2 Features The features of the MN103002A s built in caches T The Ist line of 4 2 Features _ The features of the built in caches of the MN103002A MN103002A YB are In Fig 4 2 Fig 4 1 In Fig 4 3 2 Fig 4 3 1 Re I 23 bits un Fig 4 2 Purpose of Cache Control Register Fig 4 3 2 Purpose of Cache Control Register This register sets operaton of caches Fig 4 3 Fig 4 5 1 Fig 4 4 Fig 4 5 2 Fig 4 5 Fig 4 6 Fig 4 5 3 Fig 4 5 4 l Fig 4 7 Fig 4 5 5 Following description in the figure CHCTR 9 8 Following description in the figure CHCTR 13 12 Fig 4 8 Fig 4 5 6 Fig 4 9 Fig 4 5 7 Fig 4 7 Fig 4 5 5 Fig 4 10 Fig 4 5 8 Fig 4 11 Fig 4 5 9 ig 4 12 l Fig 4 5 10 ig 4 13 Fig 4 5 11 ig 4 14 11 4 6 1 Fig 4 15 4 6 2 Support for high speed page mode Supports high speed page mode Supports the page mode mix cycle DRAM Description of Bit No 12 to 8 The relationship between the value of BOWC4 to 0 and the number of i wait states is shown below CPU clock frequency MCLK MHz Synchronous mode 0 number of wait st
39. Sequence of Stopping Operation 1 Stop timer counting Stop timer counting when set vale 0 to TMnCNE field of TMnMD register 2 Initialize timer if it is necessary If set value 1 to TMnLED field of TMnMD register the value of TMnBR register is loaded into TMnBC as initial value then output is reset After timer is stopped if never set the value 1 to TMnLDE the value output from pin and binary counter are maintained If set the value 1 to TMnCNE again restart counting from the last stopping condition TMnBC value TMnCNE Interrupt request Timer output Fig 8 7 1 Interval Timer Operation Description of Operation 215 Chapter 8 8 bit Timers or Reese Interrupt request TMnIRQ Timer output TMnOUT TMnBR value 1 XIOCLK Fig 8 7 2 Interval Timer Operation When Clock Source IOCLK Counting clock Value in TMnBC x01 x 00 TMnBR value TMnBR value 1 TMnBR value 2 Interrupt request TMnIRQ Timet output TMnOUT Fig 8 7 3 Interval Timer Operation When Use Prescaler 216 Description of Operation Chapter 8 8 bit Timers 8 7 2 Event Counting Operation While 8 bit timer is used as event counting set as follows If timers are cascaded and operate as 16 24 32 bit timer refer to the chapter 8 7 3 Cascaded Connection Sequence of
40. eo When reset Bit DMI DMI DM1 DM1 DM1 DM1 TMO DIR Dies 6 Bitposition Bit name Description 0 DM1BG0 DMA channel 1 initiation source LSB 1 DMIBGI DMA channel 1 initiation source 2 DMIBG2 DMA channel 1 initiation source 3 DMIBG3 DMA channel 1 initiation source 4 DMIBG4 DMA channel 1 initiation source MSB 00000 Software source 00001 Setting prohibited 00010 Serial O transmission end source 00011 Serial 0 reception end source 00100 Serial 1 transmission end source 00101 Serial 1 reception end source 00110 Serial 2 transmission end source 00111 Serial 2 reception end source 01000 Timer 2 underflow source 01001 Timer 3 underflow source 01010 Timer 6A compare capture source 01011 Setting prohibited 01100 IRQO input source 01101 IRQI input source 01110 External request 0 source 01111 External request 1 source 10000 to 11111 Setting prohibited Continued Description of DMA Registers 141 Chapter 6 Controller Continued Bit position 5 11 12 13 14 15 24 Bit name DMIST DMI1SAMO DMISAMI DMIDAMO DMIDAMI DMIDIR DMITMO DMITMI DMIUTO DMIUTI DMIRQM DMITEN DMIRQF Description DMA channel 1 transfer type 0 Two bus cycle transfer 1 One bus cycle transfer Transfer between external memory and an external device that sup ports the acknowle
41. interrupts 8 Watchdog timer overflow System error Purpose of Non maskable Interrupt Control Register Governs the generation of NMIs Purpose of Non maskable Interrupt Control Register Governs the generation of a non maskable interrupt Bit name Description NMIF External NMI request flag Bit Description NMIF External non maskable interrupt request flag From Ist line of main text When an non maskable interrupt request is generated the corresponding flag is set After the non maskable interrupt is accepted the corresponding The relationship between the flag status the write data and the value of the flag after the write is indicated in the table below The table of flag status is here flag is cleared by software the non maskable interrupt handler When flag is set to 1 the flag is cleared by writing a 1 to it NMIs cannot be generated by software The 2nd line right after the itemizations p itis a non maskable interrupt NMI or a level interrupt From Ist line of main text The method of clearing flag differs according to the interrupt request flags 1 External non maskable interrupt request flag NMIF and Watchdog timer overflow interrupt request flag WDIF After a non maskable interrupt is accepted these flags can be cleared by writing to the non maskable interrupt control register
42. tain to set the FRQS to the prescribed value during the reset 54 Description of Operation Chapter 3 Clock Generator The relationship between the input frequency fosci and the SYSCLK MCLK and IOCLK multiples and frequen cies is shown in Table 3 4 2 Table 3 4 2 Relationship between the Input Frequency and the SYSCLK MCLK and IOCLK Frequencies mou frequency SYSCLK frequency MCLK frequency fc MHz IOCLK frequency fio MHz fosci MHz fsys MHz 2x 4x Ix 13 0 fio 16 6 1 2 26 0 fosci 33 3 26 05 fsys 33 3 52 05 fc 66 6 13 0 lt 16 6 52 051 lt 66 6 13 05 fio 16 6 13 0 fosci 16 6 Description of Operation S5 Chapter 3 Clock Generator 56 Description of Operation Chapter 4 4 4 1 Overview The MN103002A MN103002A YB has a 4 Kbytes instruction cache and 4 Kbytes data cache on chip Caches are used to overcome the speed difference between external memory and the CPU increasing the apparent memory access speed The instruction cache stores line 16 byte units of instructions requested by the CPU while the data cache stores line 16 byte units of data requested by the CPU If the caches are enabled instruction fetches in cacheable spaces and data accesses by means of load store instructions all become eligible for caching 4 2 Features The features
43. 9 6 1 Timer n Mode Register n 4 5 Register symbol TMnMD Address x 34001080 4 x 34001082 5 Purpose This register sets the operation control conditions for timer n Bit No Bit name When reset Access Bit No Bit name Description 0 Clock source selection LSB 1 Clock source selection 2 TMnCK2 Clock source selection MSB Refer to table 9 6 2 about clock source setting 3to5 Always returns 0 6 TMnLDE Timer n initialization flag Initializes timer n 0 Normal operation 1 Initialize Loads the value in TMnBR into TMnBC and resets timer output n 7 TMnCNE Timer n operation enable flag Enables disables the timer n counting operation 0 Operation stopped 1 Operation enabled To set TMnCK 1 2 TMnCNE has to be set 0 To set TMnLDE equal to 0 TMnCNE has to be set 1 To set TMnCNE equal to 0 TMnLDE has to be set 1 Operation is not guaranteed when both TMnCNE and TMnLDE are become 1 Description of Registers 231 Chapter 9 16 bit Timers Table 9 6 2 16 bit Timer Clock Source TMnCK 2 0 Setting 000 IOCLK IOCLK IOCLK Timer 4 Timer 5 Timer 6 001 1 8 IOCLK 1 8 IOCLK 1 8 IOCLK 010 1 32 IOCLK 1 32 IOCLK 1 32 IOCLK 011 Setting prohibited Cascaded with timer 4 Setting prohibited 100 Timer 0 underflow Timer 0 underflow Timer 0 underflow 101 Timer 1 underflow Timer 1 underflow Timer 1
44. Fast response and optimal program allocation are also made possible by placing interrupt processing programs interrupt handlers at varying addresses for each interrupt level The MN103002A MN103002A YB has the interrupts shown below When of these interrupts is generated control shifts to the appropriate interrupt handler depending on the source of the interrupt Reset interrupt Highest priority ranking Non maskable interrupts Level interrupt n n 0 to 6 Lowest priority ranking Fig 2 7 1 shows an overview of the interrupt system The MN103002A MN103002A YB has 28 interrupt group control blocks external to the CPU and controls the interrupts of each group separately Each interrupt group control block can accept up to three interrupt requests the controller as a whole can handle up to 30 interrupt Sources Except for reset interrupts interrupts from the timer and other peripheral circuits and external pin interrupts are registered in all of the interrupt group control blocks Those interrupt requests that pass the interrupt mask level a level from O to 6 that is set in the interrupt group control blocks are output to the CPU Group 0 is allocated for nonmaskable interrupts only 34 Interrupt Functions Chapter 2 CPU 32 bit CPU Nonmaskable interrupts Three sources are allocated to this group External pin nonmaskable interrupts watchdog timer overflow interrupts and Interrupt system error interrupts T
45. G28ICR 16 x 0000 x 34000174 Group 29 interrupt control register G29ICR 16 x 0000 x 34000178 Group 30 interrupt control register G30ICR 16 x 0000 x 34000200 Interrupt acceptance group register IAGR 16 x 0000 x 34000280 External interrupt condition specification register 168 Description of Registers EXTMD 16 x 0000 Chapter 7 Interrupt Controller 7 4 1 Non maskable Interrupt Control Register Register symbol GOICR NMICR Address x 34000100 Purpose Governs the generation of a non maskable interrupt When reset Access Bit No Bit name Description 0 NMIF External non maskable interrupt request flag 0 Off 1 On 1 WDIF Watchdog timer overflow interrupt request flag 0 Off 1 On 2 SYSEF System error interrupt request flag 0 Off 1 On The method of clearing flag differs according to the interrupt request flags 1 External non maskable interrupt request flag NMIF and Watchdog timer overflow interrupt request flag WDIF After a non maskable interrupt is accepted these flags be cleared by writing to the non maskable interrupt control register NMICR When flag is set to 1 write a 1 to the flag to clear it The relationship between the flag status the data written to the flag and the new flag status after the data is written is shown in the table below 0 No change 0 1 1 2 System error int
46. In 16 bit bus mode when all of the blocks that are set in blocks 1 through 4 of DRAM are set for WE byte specification CAS3 is asserted just as in 32 bit bus mode however if CAS byte specification is set only CAS3 and CAS2 are asserted Figs 5 8 30 and 5 8 31 show the timing of a CAS before RAS refresh operation when the RERP bit in DRAMCTR is 0 Refresh count RERC 0 REFC 0 REFC value Count interval Count interval Refresh is executed Refresh is executed during idle cycle with the highest priority REFE bit is set Fig 5 8 28 DRAM Refresh Operation Description of Operation 127 Chapter 5 Bus Controller MCLK A31 0 RASn CAS RE WE 3 0 D31 0 RD WT SIZE1 0 Fig 5 8 29 Setting the DRAM Refresh Timing MCLK A31 0 RASn precharge CAS 3 WE 3 0 D31 0 RD WT ee oin Hei SIZE1 0 Fig 5 8 30 DRAM Refresh Timing When all blocks that are set in blocks 1 through 4 of DRAM are set for WE byte specification and FRQ 0 128 Description of Operation Chapter 5 Bus Controller A31 0 RASn 4 precharge 3 0 RE WE3 D31 0 RD WT SIZE1 0 Fig 5 8 31 DRAM Refresh Timing When CAS byte specification is set and FRQ 1 5 8 5 5 Connection Examples Fig 5 8 32 shows an example of external memory
47. In asynchronous mode wait states can be controlled for individual CPU cycles External memory space is managed by partitioning it into eight blocks Chip select signal output for each block The bus width for each block can be set to 16 32 bits Blocks 0 to 5 can be switched between synchronous mode and asynchronous mode Blocks 2 through 7 can be switched between fixed wait state insertion and handshaking Blocks 1 to 4 can be used as DRAM space Built in DRAM direct link interface Supports address multiplexing function 8 to 11 bit shift for the low address can be selected Supports two types of byte specification methods CAS or WE Supports high speed page mode Supports the page mode mix cycle DRAM Supports CAS before RAS refresh The refresh cycle is programmable Avoids time penalty when performing a store operation in the store buffer one step Supports store operations in internal peripheral circuitry and external devices When the store buffer is empty the store operation is completed with no wait states and the CPU can then continue with subsequent processing 5 V input interface Supports 5 V TTL level input interface excluding the oscillator pins Features 3 Chapter 1 General 4 Wide variety of on chip peripheral functions Interrupts 30 sources External interrupts 9 sources n 7 to 0 x 8 and NMIRQ x 1 Internal interrupts 21 sources timers 9 SIO 6 DM
48. Sets a level from 6 to 0 15 Always returns 0 Description of Registers 195 Chapter 7 Interrupt Controller 7 4 2 25 Group 28 Interrupt Control Register Register symbol G28ICR Address x 34000170 Purpose This register is used to enable group 28 interrupts and to confirm interrupt requests and detection When reset Bit No Bit name Description 0 IQSID External interrupt 5 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1 03 Always returns 0 4 IQSIR External interrupt 5 interrupt request flag 0 No interrupt requested 1 Interrupt requested 507 Always returns 0 8 IQSIE External interrupt 5 interrupt enable flag 0 Disabled 1 Enabled 910 11 Always returns 0 12 G28LVO Group 28 interrupt priority level register LSB 13 G28LV1 Group 28 interrupt priority level register 14 G28LV2 Group 28 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 196 Description of Registers Chapter 7 Interrupt Controller 7 4 2 26 Group 29 Interrupt Control Register Register symbol G29ICR Address x 34000174 Purpose This register is used to enable group 29 interrupts and to confirm interrupt requests and detection Bit No Bit name 0 IQ6ID 1 to3 4 IQ6IR 5 07 8 IQ6IE 9 to 11 12 G29LVO 13 G29LV1 14 G29LV2 15 Description External interrupt 6 interrupt detection flag 0 No i
49. set as compare resister Interrupts occur whenever TM6BC matches with TM6CB 2 If set as compare register of double buffer The value written to TM6CB is stored into buffer once This may cause reading of previous value when reading happens after writing to TM6CB Under following condition the value is loaded from buffer to compare register Then TM6BC is set to x 0000 1 At the initialization of timer 6 2 When overflow occurs in the case TM6CAE 0 3 TM6BC matches with TM6CA in the case TM6CA is compare register setting and TM6CAE 1 4 When TM6CA is captured in the case TM6CA is capture register setting and TM6CAE 1 3 If set as capture register If TM6IOB pin gets edge selected in TM6BEG flag value of TM6BC is captured into TM6CB and then an interrupt occurs Under both edge capture setting capturing happens at either of rising or falling edge and interrupt occurs Description of Registers 239 Chapter 9 16 bit Timers 9 6 9 Register symbol Address Purpose Bit No Prescaler Control Register TMPSCNT x 34001071 Controls prescaler operations Bit name When reset Access Bit No 0 to 6 7 Description Always returns 0 TMPSCNE Prescaler operation enable flag Enable disables 1 8 IOCLK amd 1 32 IOCLK prescaler operation Bit name 0 Prescaler operation disable 1 Prescaler operation enabled This prescaler also serves as the 1 8 IOCLK or 1 3
50. 12 2 2 4 Port 0 Pin Register Register symbol POIN Address x 36008080 Purpose This register is used to read the value of the port 0 pins 318 Porto Chapter 12 Ports 12 2 3 Pin Configuration Table 12 2 1 shows the pin configuration of port 0 Table 12 2 1 Port 0 Configuration P00M 1 POnD 1 POnD 0 General purpose output porti General purpose input port General purpose output port General purpose input port E General purpose output port General purpose input port General purpose output porti General purpose input port General purpose output port General purpose input port General purpose output port General purpose input port General purpose output port General purpose input port After a reset PortO 319 Chapter 12 Ports 12 3 Port 1 12 3 1 Block Diagram Fig 12 3 1 shows the block diagram for port 1 Internal data bus P1OUT W P10UT Port 1 pin P1OUT R iz 4 lt D P17 10 D15 8 Data bus output enable P1DIR W MPX P1DIR gt P1MDIR D15 8 P1IN R qt Fig 12 3 1 Port 1 Block Diagram 320 Port 1 Chapter 12 Ports 12 3 2 Description of Registers Port 1 is a general purpose input output port that also can be used as the data bus signals D 15 8 Each register for port 1 is described below 12 3 2 1 Port 1
51. 3491800 SEE 4591650 42059 4100076 onuoo XOTOOOPE X ee d JASENA lsacwa INOEWG X080002 X OUSTNG ISacwa X0P0002 X DAD ASTINA LNOING XOZOO0ZE X ALONA DASONA LSaowa INOOING NE X010002 X SsoJppy List of Register Maps 375 Appendices uod 119 91 I Iaun 119 8 POSSI st PUNOU 100 st Bare ue jt 8 jou 1 sr jou seorg Surssaooy ION NIOd m X808009E x 1 080096 X908009 X 1 1 D XSO8009E x 7080095 i 08009 208009 LNO0d L1OTd LNOEd DJAM alo 15 82901 VO9SWL VAW OWL INL X108009t X X008009E 1 00 2007 X XO0100vt X XAOTOOPE X OSTVIAL OSSIALL OS9IAL HSPALL XVOTO0TE X X60100vE X X80100vYE X 2010076 XTOTOOVE X 2 WL WL X00100TvE X TAL CNL ENL TAL CNL ENL 6 v ssaippV 376 List of Register Maps Appendices App
52. 5 20000018 6 Purpose These registers set the lower 16 bits of the start address of the interrupt handler for each mE level Bit No 15 12 11 6 Bit name IVRNn Rs WE RNn o Bk s IVRNn IVRNn IVRNn IVRNn s is s is 15 14 13 6 Afterreset x X X X X ans RW carers EN The interrupt vector registers ARO to IVAR6 store the lower 16 bits of the start address of the interrupt handler for each interrupt level that is accepted by the CPU IVARO corresponds to level 0 interrupts and IVARI through IVAR6 correspond to level 1 through 6 interrupts respectively Note that the upper 16 bits of the start addresses of the interrupt handlers for each level fixed at either x 4000 or x 5000 For details how to select the value of the upper 16 bits of the start address refer to section 4 4 1 Cache Control Register 20 Programming Model Chapter 2 CPU CPU Mode Register Register symbol Address x 20000040 Purpose This register sets the clock operation mode for the CPU core and peripheral blocks BitNo 15 14 13 12 n 10 9 6 Bit Afterreset 0 0 0 0 0 0 0 Access R R R R R R R R R Bit No Bit name Description 0 OSCO Always returns 0 when read Always write 0 OSCI Always retu
53. 7 4 2 28 Interrupt Acceptance Group Register Register symbol IAGR Address x 34000200 Purpose This register is used to read the number of a generated interrupt request Bit No Bit name Description 0 to 1 Always returns 0 2 to 6 GNO to Group number register The group number that was accepted is stored in GN 4 0 7 to 15 Always returns 0 The Interrupt Accept Group Register IAGR stores the current lowest interrupt group number among the group numbers of the interrupts with the same interrupt level indicated by IM2 to IMO in the PSW Because the interrupt level is set to IM2 to IMO when an interrupt is accepted by the CPU IAGR indicates the current lowest interrupt group number among the group numbers of the interrupts that have been accepted by the CPU with the same interrupt level If IM2 to IMO is changed or Group Interrupt Control Register is updated or a new interrupt request occured IAGR may change while the interupt handler is working The interrupt acceptance group register IAGR is a read only register it cannot be written Description of Registers 199 Chapter 7 Interrupt Controller 7 4 2 29 External Interrupt Condition Specification Register Register symbol EXTMD Address x 34000280 Purpose This register specifies the external interrupt generation conditions Set the desired level or edge for each pin Bit No Bit name Description 0 IROTGO IRQO pin trigger con
54. CLK DAT 15 P17 14 P16 MODE EIE o O Aaf Af al Nal al al al z o o aEIBIEIBIBIBE al a al al gt al a 5 l 51 olola Q e e oO e e O j oj uj uj uj j u Of uf Of o oj Oj I ri 5 gt gt x 5 x 2 2 elio 9 h al o olalov a 1815155151555 Tl aol oll 2118 Z u amp amp a Af ej oN M or o sl Tm cis TiN eji NENT NENT NJ N 2 1 LL UP D WT DOVF VREF5V A26 C84 RAS4 A28 CS6 A29 A27 CS5 A31 CS7 2 sr 212 Y E 2 2 gt lt gt 5 6 Ol ant e RIS o 9 c Oj lt is lt Those pins for which two or more names defined are dual purpose pins D Connect a pull up resistor 9 Pin Descriptions Chapter 1 General 1 4 2 Pin Functions Table 1 4 3 List of MN103002A MN103002AYB Pin Functions Category Pinname Number of pins Pin function Power ground pins VDD 14 Digital system power supply VSS I 14 Digital system GND VREFSV I 1 5 V reference voltage input
55. Chapter 5 Bus Controller 5 8 6 Bus Arbitration In the MN103002A MN103002A YB bus arbitration is implemented through the bus request signal BR and the bus grant signal BG If an external device asserts the BR signal then once the current bus access being executed is completed the BG signal is asserted and the bus authority is released to the external device Once the BR signal is negated this LSI negates the BG signal in order to re acquire the bus authority However if a refresh request is generated by the DRAM control circuit within this LSI while the bus authority has been released to an external device this LSI negates the BG signal and requests the bus authority back from the external device The external device then negates the BR signal in response and the refresh is executed Note that bus arbitration is performed in synchronization with SYSCLK Fig 5 8 34 shows the timing for releasing the bus authority to an external device and Fig 5 8 35 shows the timing when a refresh request is generated while the bus authority has been released 1 to 0 CSn WE3 to 0 RAS and CAS3 to 0 are always output when the MN103002A MN103002A YB has the bus authority BG 1 and go to high impedance when the bus authority is released BG 0 SYSCLK A31 0 CAS D31 0 RD WT SIZE1 0 CPU Read Standby cycle i Hiiz Hi Hiz Hiz Hiz Hi
56. During single word transfer After the single word transfer is completed the DMA with the high priority is executed When the DMA with high priority is executed the transfer that was interrupted is resumed after the high priority DMA transfer is completed During burst transfer The high priority DMA is executed after the transfer is completed During intermittent transfer After the specified number of intermittent transfer cycles are completed the DMA with the high priority is executed When the DMA with the high priority is executed the transfer that was interrupted is resumed after the high priority DMA transfer is completed If a DRAM refresh request or an external bus request is generated while a burst transfer or an intermittent transfer is in progress the transfer is interrupted and the bus is released The transfer is then resumed after the bus is no longer needed for the DRAM refresh or external device In addition if the CPU requests the use of a non conflict ing bus while a burst transfer is in progress for example if the CPU attempted to access the external bus while O was being accessed during a DMA transfer between I O and the external bus then the CPU access cycle may be inserted 6 4 44 Transfer Start End Interrupt Transfer start A transfer starts if a startup source set in the DMnBG4 to 0 bits of the control register is generated and the DMnTEN bit is 1 Transfer end If a transfer is performed according
57. Output voltage high level SYSCLK Vo Output voltage low level Vit3 MAX Vita MAX 0 7 Voo x 0 3 Input signal 227 4 Vr Input voltage transition level Output signal Vr Output voltage transition level Vpp x 0 5 Fig 13 4 19 AC Timing Test Voltage Levels AC Characteristics 367 Chapter 13 Electrical Characteristics 368 AC Characteristics Appendix Appendix Treatment of Pins Treat pins as following Table A 1 Table A 1 Treatment of Pins Treatment A31 CS7 A30 A29 26 56 A2 1ICSS A26 CS4 RAS4 A25 A24 A23 A22 A21 A20 A19 18 A17 A16 15 A14 13 RAS3 CS3 R S2 When not connected with 3 Connect to Vpp through resister signal line When external devices OZ 3 RE and CPU have might to Connect to through resister RASI CSI 850 Sep TA W p CASO RD WT SIZEI SIZEO D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 216 When only CPU has might to use buses Set as port input connect to Vpp through When not connected with resister or set as port output leave as signal line floating pin When external devices and CPU h
58. SV supply 5 voltage 0 3 to 57 V A4 Input pin voltage 1 M 03 to Vpp 0 3 V 5 Input pin voltage 2 Vis 03 to 60 A6 Output pin voltage Vo 03 to 4 03 V A7 Input output pin voltage Vio 0 3 to Vpp 0 3 V 8 Operating ambient temperature 20 to 70 9 Storage temperature 55 to 125 10 Allowable power dissipation Pb 0 9 W All Averaged output current IO 12 Notes 1 The absolute maximum ratings are the allowable values which if applied to the chip will not cause dam age to the chip they are not the values at which operation is guaranteed 2 Connect all VDD and PVDD pins directly to an external power supply 3 Connect all VSS and PVSS pins directly to an external ground 4 Insert at least one bypass capacitor of at least 0 33 between the power supply pins and ground The rising edge and falling edge sequences must observe the criteria described below VDD VREFS and tkersy must be at least 0 Transitions in VDD and VREF5 must be smooth trersit 338 Absolute Maximum Ratings 13 2 Operating Conditions Table 13 2 1 shows the operating conditions Chapter 13 Electrical Characteristics Table 13 2 1 Operating Conditions Vss PVSs 0 0 V TA 20 to 70 Tieni E 2 Allowable values Unit Symbol Conditions Min Typ
59. interrupt acknowledge consists of reading the Interrupt Accept Group Register IAGR to obtain the group number of the interrupt group with the highest priority among the specified interrupt levels Step 2 2 The starting address of the interrupt handler for the individual level is generated Step 2 3 Control is transferred to the interrupt handler for the individual level Step3 there are multiple sources within a single group the individual sources are specified by reading the Interrupt Control Register GnICR In the case of non maskable interrupts the source is specified by accessing the GOICR NMICR directly without accessing the IAGR Step 4 Control is transferred to the interrupt handler for the individual interrupt source Note that because this microcontroller uses a store buffer when writing data via the bus controller when releasing the interrupt source it is necessary to read the appropriate register immedi ately after clearing the interrupt source in order to wait for the source in the GnICR to be cleared completely Example of post processing by the interrupt handler Step5 contents of the registers are restored The registers that are restored are those that were saved in the preprocessing Step 6 RTI instruction is executed and control returns to the program before the interrupt Interrupt Functions 42 Chapter 2 CPU 44 Fig 2 7 5 shows the flow of the interrupt sequence when nested
60. 1 changes depending on the setting contents of MEMCTRO n 1 m Description of signals in table 13 4 6 Asynchronous mode data transfer signal output timing Refer to Fis 13 4 5 FRQ 0 n represents the number of wait states Description of signals in table 13 4 6 DRAM mode data transfer signal output timing Refer to Fig 13 4 6 2 and change according to the DRAMCTR setting The correspondence is shown below Nr 2 2RTC a ee 4 nir WC Furthermore when FRQS L level Nf 2 and when FRQS level Nf 4 2 Mr and change according to the DRAMCTR and MEMCTRO setting The correspondence is shown below 2 2 4 4 a When 0 Nf 2 and when 1 4 Min of E59 Read data hold time 5 Min of E59 Read data hold time 0 2 change according to the DRAMCTR setting The correspondence is shown below no 6 8 nr Furthermore when FRQS L level Nf 2 and when FRQS level Nf 4 2 change according to the DRAMCTR and MEMCTRO setting The correspondence is shown below 8 Np 6 pr When 0 Nf 2 and when 1 Nf 4 Note 1 is the SYSCLK cycle time When FRQS L level Nf 2 and when level 4 Note is the SYSCLK cycle time change according to the MEMCTRO setting When 0
61. 2 0 16 2400 0 00 625 125 4 0 00 1200 0 00 1250 125 8 0 00 Table 11 5 3 Baud Rates 3 when IOCLK 10 MHz When cascaded When using prescalers Baud rate bps Timer division ratio Transfer rate error Timer division ratio Transfer rate error 19 200 0 16 0 16 9 600 0 16 0 16 4 800 0 16 260 130x2 0 16 2 400 0 03 520 130 x4 0 16 1200 0 03 1040 130 8 0 16 It is not necessary to use cascaded connection or prescaler When using 1 8 of an external clock as the clock source the widths of the high and low pulses of the input clock must be at least two IOCLK cycles 298 Description of Operation Chapter 11 Serial interfaces 11 5 1 3 Clock Synchronous Mode Timing Transmission One byte transfer with 8 bit data length and parity on SBO pin 5 v6 Data write SCnTXF flag lt r SCnTBF flag Interrupt request when set to transmission end RA Interrupt DMA request 4 when set to transmission buffer empty Fig 11 5 4 Timing Chart 1 Two byte transfer with 8 bit data length and parity off SBO pin fi ees eoe feos e e vs ees eer Data write A flag SCnTBF flag 1 Interrupt request when set to transmission end T XD
62. 3 bytes 110132 is a value which can be expressed with 2 bytes to 1 byte or imm32 0 imm32 is a value which can be expressed with 4 bytes to 3 bytes Dm is a value which can be expressed with 2 bytes to 1 byte or Dm 0 Dm is a value which can be expressed with 4 bytes to 3 bytes 1110132 is a value which can be expressed with 2 bytes to 1 byte or imm32 0 1111132 is a value which can be expressed with 4 bytes to 3 bytes MN103002A LSI User s Manual March 2002 5th Edition Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Panasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 N Randall Road Elgin Illinois 60123 7847 U S A 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 Fax 1
63. Additional Bit Style PWM Mode 262 Watchdog Timer OVE VIEW iacere bue ip dad ER e lee d 266 c T 266 Block 267 Description of Registers 268 10 4 1 Watchdog Binary Counter 0 cccccccssseesssesesessescsesscsesessscssseesacessreneaearanes 268 10 4 2 Watchdog Timer Control Register esee 269 10 4 3 Reset Control Register eese tenter tennis 271 Description of Operation sese eee 272 10 5 1 Oscillation Stabilization Wait Operation sss 272 10 5 2 Watchdog Operation sse ret 274 10 5 3 Self reset Operation sese tnter 275 Serial Interfaces OVETVIG onte icit ect a e e Rp 278 279 11 2 1 Serial Interface 0 and 1 4 279 11 22 Serial Interface Zrin a e e 280 Block Diagram d t E HORN 281 11 3 1 Serial Interface 0 and 1 sette ttnttetetentntecnt 281 11 3 2 Serial Interface 2 oo eee trente iia 282 11 4 Description of Registers p ERU eere p ein Ede di 283 11 4 1 Serial n Control Register n 0 1 284 11 5 2 Serial n Interrupt Mode
64. Chapter 13 Electrical Characteristics IRQ7 0 NMIRQ tiraw nmiraw Fig 13 4 13 Interrupt Signal Timing 13 4 7 Timer Signal Timing Table 13 4 13 AC Characteristics 13 VDD 3 3 V 0 165 V Vss 0V 20 C to 70 C CL 50 pF Allowable values Item Symbol Conditions Unit Min Max Timer counter signal input output timing Refer to Figs 13 4 14 and 13 4 15 Timer input signal setup time E82 t ns 5 TM6IOA TM6IOB 13 Timer input signal pulse width EROS pir 3 5 tec 2 E83 TMOIO TMSIO TM6IOA TM6IOB trciw ns FRQS pin H level 1 5 tcvc E84 Timer counter output signal delay time iz 5 m TMOIO TMSIO TM6IOA TM6IOB Note ty is the SYSCLK cycle time AC Characteristics 363 Chapter 13 Electrical Characteristics SYSCLK TMOIO 5 TM6IOA TM6IOB trcis trciw Fig 13 4 14 Timer Counter Input Timing SYSCLK TMOIO TMBIO TM6IOA TM6IOB treo Fig 13 4 15 Timer Counter Output Timing 364 AC Characteristics Chapter 13 Electrical Characteristics 13 4 8 Watchdog Timer Signal Timing Table 13 4 14 AC Characteristics 14 VDD 3 3 0 165 55 0 20 to 70 CL 50 pF Allowable values Item S 1 Conditi Unit ymbol Condition Min Mik Watchdog
65. G8ICR 16 x 0000 L x 34000124 Group 9 interrupt control register G9ICR 16 x 0000 x 34000128 Group 10 interrupt control register GIOICR 16 x 0000 x 34000130 Group 12 interrupt control register G12ICR 16 0000 x 34000134 Group 13 interrupt control register 16 x 0000 x 34000138 Group 14 interrupt control register G14ICR 16 x 0000 x 3400013C Group 15 interrupt control register GISICR 16 x 0000 x 34000140 Group 16 interrupt control register GI6ICR 16 x 0000 x 34000144 Group 17 interrupt control register G17ICR 16 x 0000 x 34000148 Group 18 interrupt control register G18ICR 16 x 0000 x 3400014C Group 19 interrupt control register G19ICR 16 x 0000 x 34000150 Group 20 interrupt control register G20ICR 16 x 0000 x 34000154 Group 21 interrupt control register G21ICR 16 x 0000 x 3400015C Group 23 interrupt control register G23ICR 16 x 0000 x 34000160 Group 24 interrupt control register G24ICR 16 x 0000 34000164 Group 25 interrupt control register G25ICR 16 x 0000 x 34000168 Group 26 interrupt control register G26ICR 16 x 0000 x 3400016C Group 27 interrupt control register G27ICR 16 x 0000 x 34000170 Group 28 interrupt control register
66. MEMCTR3 Address x 32000026 Purpose Sets the bus mode and the number of wait states to be inserted for external memory space block 3 Bit No Bit name Description 0 B3DRAM Block 3 DRAM space setting 0 Do not use this block as a DRAM space 1 Use this block as a DRAM space 1 B3WM Block 3 wait mode 0 Fixed wait state insertion 1 Handshaking 2 B3BM Block 3 bus mode 0 Synchronous mode synchronized with SYSCLK 1 Asynchronous mode synchronized with MCLK 5 B3BW Block 3 bus width 0 16 bits 1 32 bits 6 B3CAS Block 3 DRAM byte specification 0 Specified by WE3 to 0 1 Specified by CAS3 to 0 8 B3WCO Number of block 3 wait state insertions LSB 9 B3WCI Number of block 3 wait state insertions 10 B3WC2 Number of block 3 wait state insertions 11 B3WC3 Number of block 3 wait state insertions 12 B3WC4 Number of block 3 wait state insertions MSB After reset mode is released block 3 is set to synchronous mode with 15 wait states and the bus width is 32 bits When using block 3 as a DRAM space the number of wait states is as indicated by the setting of the WC bit in the DRAM control register However even when using block 3 as a DRAM space be sure not to set a prohibited value B3WC4 to 0 1 The number of wait states that are inserted is the same as set in bits BOWC4 100 Refer to the description of memory control register 0 MEMCTRO O4 Description of Registers Chapter 5 Bus Controller 9 6
67. NMICR When a flag is set to 1 write a 1 to the flag to clear it The relationship between the flag status the data written to the flag and the new flag status after the data is written is shown in the table below The table of flag status is here 2 System error interrupt request flag SYSEF This flag cannot be cleared by writing to the non maskable interrupt control register NMICR This flag can be cleared by generating a reset interrupt by setting the RST pin to L level or by the self reset which is generated by writing to the reset control register RSTCTR of the watchdog timer Y Non maskable interrupts cannot be generated by software The 2nd line right after the itemizations pt it is a non maskable interrupt or a level interrupt The 2nd line from the bottom The 2nd line from the bottom non maskable interrupt request is sent to the CPU an NMI interrupt request is sent to the CPU Fig 8 3 1 Timer Configuration Diagram Fig 8 3 1 Timer Connection Diagram The 1st line of main text Prescaler control register TMPSCNT is used at 8 bit controller The Ist line of main text Prescaler control register TMPSCNT is also used at 8 bit timer 9 7 1 1 Register Settings 19 711 1 Interval Timer Timer Output In 6 Oscillation stabilization wait time When recovering from STOP mode 3 972 ms to 1016 801 ms In 6 Oscillation
68. PVDD I 1 PLL circuit power supply PVSS I 1 PLL circuit ground Clock OSCI I 1 Oscillator input OSCO 1 Oscillator output SYSCLK 1 System clock output FRQS I 1 Input clock frequency switching Reset RST I 1 Reset input System control MMODE I 1 Mode setting signal DSCLK VO 1 Debugging serial clock I O DSDAT VO 1 Debugging serial data Address bus AO A31 32 Address lines 0 to 31 A26 through A28 and A31 EN are dual use pins with CS4 through 6 and CS7 Data lines 0 to 31 DO through D15 are dual use pins with POO through P07 and P10 through P17 Bus control BMODE rae Block 0 bus mode switching signal RASI RAS4 3 Row address strobe signals RASA only is dual use pin with A26 WE0 WE3 4 Write enable signals RE 1 Read pulse signal RD WT O 1 Read write status signal SIZE0 SIZEI 2 Access size information notification signals CS0 CS7 1 Chip select signals CS1 through 7 dual use pins with other signals DK I 1 Data acknowledge signal BG 1 Bus grant signal BR I 1 Bus request signal Serial interfaces SBIO SBD I 3 Serial interface 0 to 2 data inputs SBO0 SBOI 2 Serial interface 0 to 1 data inputs outputs dual use SBO2 1 Serial interface 2 output 5 0 8 0 Serial interface 0 to 2 transfer clock input output dual use SBT2 I 1 Serial interface 2 transfer clock input CTS I
69. Port 3 P3 The pins of this port also serve as serial interface input outputs SBOO and SBOI Port 4 P4 The pins of this port also serve as address outputs A 31 and A 28 26 and as chip select signals CS7 to 4 Although these pins do not constitute an I O port they are referred to as Port 4 for the sake of conve nience in this manual 314 Overview Chapter 12 Ports Table 12 1 1 lists the I O port registers Table 12 1 1 List of Registers Address Name Number bits Initial value Access size x 36008000 Port output register i 8 16 x 36008001 Port 1 output register x 36008004 Port 2 output register x 36008005 Port 3 output register x 36008020 Port 0 output mode register x 36008021 Port 1 output mode register x 36008024 Port 2 output mode register x 36008025 Port 3 output mode register x 36008044 Port 2 dedicated output control register x 36008048 Port 4 dedicated output control register x 36008060 Port 0 I O control register x 36008061 Port 1 I O control register x 36008064 Port 2 UO control register x 36008065 x Port 3 I O control register x 36008080 Port 0 pin register x 36008081 Port 1 pin register 36008084 Port 2 register x 36008085 Port 3 pin register 5 OO 100 0 OO
70. the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of ud 07 imm8 Dn udf07 imm16 Dn and udf07 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases Extension Instruction Specifications 41 5 Appendices SWAP Data swapping instruction that swaps bytes high order to low order and vice versa in four byte data Instruction Format Macro Name SWAP Dm Dn Assembler Mnemonic udf08 Dm Dn Operation This instruction swaps the positions of the high order and low order 8 bit bytes within the respective high and low order 16 bit half words within the 32 bit data stored in Dm and then swaps the positions of the high order and low order 16 bit half words and then stores the result in Dn Asa result bits 31 through 24 of Dm are stored in bits 7 through 0 in Dn bits 23 through 16 of Dm are stored in bits 15 through 8 in Dn bits 15 through 8 of Dm are stored in bits 23 through 16 in Dn and bits 7 through 0 of Dm are stored in bits 31 through 24 in Dn Dm before execution Bit 31 Bit 0 E Dm 31 24 Dm 23 16 Dm 15 8 Dm 7 0 MSB LSB Dn after execution Bit 31 Bit 0 Dm 7 0 Dm 15 8 Dm 23 16 Dm 31 24 jsp Spe MSB LSB Execution examp
71. the interrupt priority level can be set independently for each interrupt group It is also possible to set the same interrupt priority level for different interrupt groups If interrupts of the same priority level are generated simultaneously the interrupts are accepted in the order set by the hardware the interrupt group with the lowest interrupt group number is given priority When a maskable interrupt is accepted control branches to the 32 bit address of which the upper 16 bits are either 4000 or x 5000 and the lower 16 bits the value stored in the IVARn register that corresponds to the level of the interrupt that was generated The interrupt handler accesses IAGR to analyze the interrupt group accesses GnICR n 2 to 10 12 to 21 or 23 to 30 analyzes the interrupt source performs the interrupt processing cancels the interrupt source and then returns to the normal program using the RTI instruction Interrupt Functions 41 Chapter 2 CPU 2 7 4 Interrupt Operation When the MN103002A MN103002A YB accepts an interrupt first the sequence that is processed by the hardware automatically is executed Control then shifts to the software interrupt handler and the interrupt handler is started up The interrupt processing sequence is described below 2 7 4 1 Interrupt Sequence Hardware interrupt processing sequence Step 1 Step 2 Step 3 Step 4 Step 5 The contents of the PSW are saved to the st
72. 0 Inhibit capturing operation TMAEG optional TM6AM1 0 00 Compare register single buffer or 01 Compare register double buffer Must use double buffer setting if the value in compare capture register A is changed during count operation 2 Set the value to terminate timer Give the comparison value into TM6CA Timer is terminated after value in TM6CA register 1 counts 3 Setting of operation mode Set TM6MD register as follows TM6CK2 1 0 optional select clock source TM6CAE 1 Clear TM6BC if TM6CA equal to TM6BC TM60NE 1 Permission for one shot operation TM6TGE 0 Inhibit starting up of timer by external trigger TM6PM1 0 optional This setting never to be used TM6PME 0 Select normal wave TM6LDE 0 Normal operation TM6CNE 0 Terminate count operation Prescaler operation must be permitted setting 1 to TMPSCNE of TMPSCNT register before the count operation of timer 6 is allowed when 1 8 IOCLK or 1 32 IOCLK is used as clock source 4 Initialization of timer Initialize timer 6 by set 1 into TM6LDE of TM6MD register Clear the TM6BC Reset pin output When compare capture register has double buffer compare setting load the value from buffer into compare register Switch to the normal mode set 0 into TM6LDE must be done after the initialization 5 Set the I O port when using pin output Set the I O port to timer output pin In the I O port register select timer output for the output signal and then set
73. 10 interrupts and to confirm interrupt re quests and detection Bit No Bit name Description 0 T6BID Timer 6B interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 TGBIR Timer 6B interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 Timer 6B interrupt enable flag 0 Disabled 1 Enabled 9to 11 Always returns 0 12 GI10LVO Group 10 interrupt priority level register LSB 13 GIOLVI Group 10 interrupt priority level register 14 GIOLV2 Group 10 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 1 80 Description of Registers Chapter 7 Interrupt Controller 7 4 2 10 Group 12 Interrupt Control Register Register symbol GI2ICR Address x 34000130 Purpose This register is used to enable group 12 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 DMOID transfer end interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 DMOIR transfer end interrupt request flag 0 No interrupt requested 1 Interrupt requested 57 Always returns 0 8 DMOIE DMAO transfer end interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G12LV0 Group 12 interrupt priority level register LSB 13 G12LV1 Group 12 interr
74. 2 Output Register 2 2 326 12 4 2 2 Port 2 Output Mode Register sse 326 12 4 2 3 Port 2 Dedicated Output Control 1 327 12 4 2 4 Port 2 Input Output Control Register 328 12 4 2 5 Port 2 Pin 00 328 1243 Configuration sssi eere p Seer RR tet italia o Mnt 329 330 12 5 1 aiin 330 12 5 2 Description of Registers ci unco eus Pax Nah e RISE D LR UE 331 12 5 2 1 Port 3 Output Register sess 331 12 5 2 2 Port 3 Output Mode 20 331 12 5 2 3 Port Input Output Control Register 332 12 5 2 4 Port 3 Pin 0 0 20000000010000 trenes 332 12 5 3 Pin Configuration sieden Oe e 333 894 12 6 1 Description of Registers 4000 00 014200 334 12 61 11 4 Dedicated Output Control 334 12 6 2 Pin Configuration tret tritani 335 Electrical Characteristics Absolute Maximum Ratings 0 cccccccccscssssesssesesscssssscssesesssasstsvsssaescsececasavacsucasavavseesens 338 Operating Conditions esses tette tette
75. 3 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 IQ3IR External interrupt 3 interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 IQ3IE External interrupt 3 interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G26LVO Group 26 interrupt priority level register LSB 13 G26LVI Group 26 interrupt priority level register 14 G26LV2 Group 26 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 194 Description of Registers Chapter 7 Interrupt Controller 7 4 2 24 Group 27 Interrupt Control Register Register symbol G27ICR Address x 3400016C Purpose This register is used to enable group 27 interrupts and to confirm interrupt Bi name requests and detection Bit No Bit name Description 0 10410 External interrupt 4 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1to3 Always returns 0 4 IO4IR External interrupt 4 interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 IO4IE External interrupt 4 interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G27LVO Group 27 interrupt priority level register LSB 13 G27LV Group 27 interrupt priority level register 14 G27LV2 Group 27 interrupt priority level register MSB
76. 3 p s GN WE30 i aUe mE D31 0 4 80 Startup Internal Memory I O read write Fig 6 4 9 Two Bus Cycle Transfer Single word Transfer Serial Reception End Interrupt Fig 6 4 9 shows the timing chart for a two bus cycle transfer from the serial reception buffer to external memory initiated by a serial reception end interrupt The DMA transfer begins within a minimum of four CPU cycles after the serial reception end interrupt is input to the DMA After the contents of the serial reception data register are read into the DMA data buffer via bus access then the external bus cycle starts within a minimum of two CPU cycles and the data is written to external memory Note that the number of bus cycles and the bus mode for external memory access are determined by the values set in the memory control register just as in the case of external accesses performed by the CPU 160 Description of Operation Chapter 7 Interrupt Controller Chapter 7 Interrupt Controller 71 Overview The interrupt controller processes non maskable interrupts and level interrupts internal interrupts and external interrupts The microcontroller has eight external interrupt pins and one non maskable interrupt pin External level interrupts are processed when an external pin interrupt signal is maintained for two or more I O clock cycles 7 2 Features Up to four interrupt requests can be accepted by e
77. 5 1 Block Diagram Fig 12 5 1 shows the block diagram for port 3 Internal data bus P3OUT W P3OUT o Port 3 pin PSOUTIR D lt P31 30 gt SBOI SBOO Data bus output enable P3DIR W 4 P3MD W SBOI SBOO Fig 12 5 1 Port 3 Block Diagram P31 30 330 Port3 Chapter 12 Ports 12 5 2 Description of Registers Port 3 is a general purpose input output port that also can be used as the serial data input outputs SBOO and SBOI Each register for port 3 is described below 12 5 2 1 Port 3 Output Register Register symbol P3OUT Address x 36008005 Purpose Sets the data that is to be output on port 3 Bit Epp ICON COR REEL I pepis l P310 P300 Aces 12 5 2 2 Port 3 Output Mode Register Register symbol P3MD Address x 36008025 Purpose This register selects the port 3 pin output content Bi name Bit No Bit name Description 0 P30M Port 3 pin output content selection 0 Serial data input output SBOO 1 General purpose I O port P30 1 Port 3 pin output content selection 0 Serial data input output SBO1 1 General purpose I O port P31 2 to 7 Always returns 0 Port 3 331 Chapter 12 O Ports 12 5 2 3 Port 3 Input Output Control Register Register symbol P3DIR Add
78. 5 are down counters having TMnBR value as the initial value They generate interrupt when they make underflow caused on TMnBR value 1 times count Timer 6 is up counter start from the initial value x 0000 It generates interrupt whenever overflow occurs Under additional bit style PWM mode it operates as binary counter and generates interrupt when over flow occurs Description of Registers 235 Chapter 9 16 bit Timers 9 6 5 Timer 6 Compare Capture A Mode Register Register symbol TM6MDA Address x 340010B4 Purpose This register sets the operation control conditions for the compare capture register A for timer 6 This register also sets the waveform that is output to the TM6IOA pin me 7 6 5 4 3 Bit name TM6 TM6 TM6 TM6 AMI 0 AEG ACE Wiens 9151519 Bit No Bit name Description 0 TM6AO0 Timer 6A output waveform selection flag LSB 1 6 1 Timer 6A output waveform selection flag 2 6 2 Timer 6A output waveform selection MSB These bits select the waveform that is output to the TM6IOA pin 000 Set when TM6BC matchs TM6CA reset when TM6BC matchs TM6CB 001 Set when TM6BC matchs TM6CA reset when TM6BC overflows 010 Set when TM6BC matchs TM6CA Reset only when the timer is initialized 011 Reset when TM6BC matchs TM6CA 100 Toggled output Output is inverted when TMnBC matches TMnCA 101 110 111 Setting prohibited 3 Always returns 0
79. 6 Controller control register 3 Register symbol DM3CTR Address x 32000800 Purpose Sets the transfer parameters for DMA channel 3 Bitposition Bit name Description 0 DM2BGO DMA channel 3 initiation source LSB DM2BGI DMA channel 3 initiation source 1 2 DM2BG2 DMA channel 3 initiation source 3 DM2BG3 DMA channel 3 initiation source 4 DM2BG4 DMA channel 3 initiation source MSB 00000 Software source 00001 Setting prohibited 00010 Serial O transmission end source 00011 Serial 0 reception end source 00100 Serial 1 transmission end source 00101 Serial 1 reception end source 00110 Serial 2 transmission end source 00111 Serial 2 reception end source 01000 Timer 2 underflow source 01001 Timer 3 underflow source 01010 Timer 6A compare capture source 01011 Setting prohibited 01100 IRQO input source 01101 IRQI input source 01110 External request 2 source 01111 External request 3 source 10000 to 11111 Setting prohibited Continued Description of DMA Registers 145 Chapter 6 Controller Continued Bit position 5 11 12 13 24 Bit name DM3ST DM3SAMO DM3SAMI DM3DAMO DM3DAMI DM3DIR DM3TMO DM3TMI DM3UTO DM3UT1 DM3RQM DM3TEN DM3RQF Description DMA channel 3 transfer type 0 Two bus cycle transfer 1 One bus cycle transfer Transfer between external memory and an external device that sup ports the acknowledge function DMA cha
80. 8 16 x34001013 Timer 3 base register TM3BR 8 34001020 Timer 0 bainary counter TMOBC 8 16 32 34001021 Timer 1 bainary counter 8 x34001022 Timer 2 bainary counter TM2BC 8 16 x34001023 Timer 3 bainary counter TM3BC 8 x 34001071 Prescaler control register TMPSCNT 8 00 OO Prescaler timer is also used in 16 bit timer When writing to or reading from an 8 bit timer register set the bus mode to synchronous mode Operation is not guaranteed if the read write is performed in asynchronous mode 210 Description of Registers 8 6 1 Chapter 8 8 bit Timers Timer n Mode Register n 0 1 2 3 Register symbol Address Purpose 3105 Bit name TMnCKO TMnCK1I TMnCK2 TMnLDE TMnCNE TMnMD x 34001000 0 34001001 n 1 x 34001002 2 34001003 3 Control of the operation of timet n Description Clock source selection LSB Clock source selection Clock source selection MSB Refer to table 8 6 2 about clock source setting Always returns 0 Timer n initialization flag Initializes timer n 0 Normal operation 1 Initialize Loads the value of TMnBR in TMnBC Resets timer output n to L level Timer n output enable flag Enables disables the timer n count operation 0 Operation disabled 1 Operation enabled To set TMnCK
81. 9 7 8 Pin Output Waveform 1 Description of Operation 240 Chapter 9 16 bit Timers Fig 9 7 9 shows TM6IOA pin output wave in the case Simultaneously set for TM6BC and TM6CA and reset when overflow of TM6BC occurs Reset has higher priority than set when both reset and set are generated simultaneously TM6CNE overflow 4 2 A Match TM6BC with TM6CA 2 i 4 pin output When TM6AEG 0 TMGIOA pin output NEN m When TM6AEG 1 Fig 9 7 9 Pin Output Waveform 2 Fig 9 7 10 shows TM6IOA pin output wave in the case Simultaneously set for TM6BC and TM6CA Match TM6BC with TM6CA 2 2 T T TM IOA pin output When TM6AEG 0 TMGIOA pin output 7 When TM6AEG 1 Fig 9 7 10 Pin Output Waveform 3 250 Description of Operation Chapter 9 16 bit Timers Fig 9 7 11 shows TM6IOA pin output wave in the case Simultaneously reset for TM6BC and TM6CA Match TM6BC with TM6CA 4 4 TMGIOA pin output When TM6AEG 0 TM6IOA pin output When TMGAEG 1 Fig 9 7 11 Pin Output Waveform 4 Fig 9 7 12 shows TM6IOA pin output wave in the case Toggled output TM6CNE Match TM6BC with TM6CA ai 4 TMGIOA pin output When TM6AEG 0 TM6IOA pin output When TM6AEG 1 Fig 9 7 12 Pin Output Waveform 5 Description of Operation 25 Chapter 9 16 bit Time
82. ASR Arithmetic right shift of any number of bits LSR Logical right shift of any number of bits ASL Arithmetic left shift of any number of bits ASL2 Arithmetic left shift of two bits ROR Rotate right one bit ROL Rotate left one bit 2 5 3 7 Branch Instructions The branch instructions change the flow of program execution according to certain conditions The conditional branch instructions include normal conditional branch instructions and special loop conditional branch instruc tions The special loop conditional branch instructions minimize the branching penalty by using special registers thus speeding up loop execution Subroutine calls and returns are advanced functions that manipulate the PC save and restore multiple registers to and from the stack and allocate and release stack area Table 2 5 9 List of Branch Instructions Bcc Conditional branch PC relative Lec Special loop conditional branch SETLB Set start of loop JMP Unconditional branch PC relative register indirect CALL Subroutine call advanced type CALLS Subroutine call RET Return from subroutine advanced type Return from subroutine advanced fast type RETS Return from subroutine RTI Return from interrupt handler TRAP Subroutine call to fixed address 3 0 Instructions Chapter 2 CPU 2 5 3 8 NOP Instruction The NOP instruction is an instruction that performs no opera
83. Address Registers Register symbol DMnSRC 0 1 2 3 Address x 32000104 0 32000204 1 x 32000404 n22 x 32000804 3 Purpose These registers set the transfer source address for DMA channels 0 to 3 29 2s 22 se zs 2 22 22 2 20 19 n Bit DM Mn DMn DMn DMn DMn DMn DMn name SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 vw e ae eee EM EE Mn DMn DMn DM name SAIS SA14 5 5 og 2 2 2 lt 5 nd 5 J z 3 lt 8 Z lt 8 lt 2 lt nd c lt gt gt Q gt gt e e 2 T gt w A13 SA12 SA11 SA10 SA9 5 x R During a DMA transfer this register shows the next transfer source address When the transfer source is Eg an external device that supports the acknowledge function and one bus cycle transfer mode is in effect the contents of DMnSRC are ignored The transfer address that is set should conform with a 1 byte boundary 8 bits 2 byte boundary 16 bits or 4 byte boundary 32 bits depending on the transfer byte unit 6 3 3 DMA Destination Address Registers Register symbol DMn
84. Bi Bit position Bit name Description 0 DMOBGO DMA channel 0 initiation source LSB 1 DMOBGI DMA channel 0 initiation source 2 DMOBG2 DMA channel 0 initiation source 3 DMOBG3 DMA channel 0 initiation source 4 DMOBG4 channel 0 initiation source MSB 00000 Software source 00001 Setting prohibited 00010 Serial 0 transmission end source 00011 Serial 0 reception end source 00100 Serial 1 transmission end source 00101 Serial 1 reception end source 00110 Serial 2 transmission end source 00111 Serial 2 reception end source 01000 Timer 2 underflow source 01001 Timer 3 underflow source 01010 Timer 6A compare capture source 01011 Setting prohibited 01100 IRQO input source 01101 IRQI input source 01110 External request 0 source 01111 External request 1 source 10000 to 11111 Setting prohibited Continued Description of DMA Registers 129 Chapter 6 DMA Controller Continued Bit position 5 11 12 13 14 16 24 Bit name DMOST DMOSAMO DMOSAM1 DMODAMO DMODAMI DMODIR DMOTMO DMOTMI DMOUTO DMOUTI DMORQM DMOTEN DMORQF Description DMA channel 0 transfer type 0 Two bus cycle transfer 1 One bus cycle transfer Transfer between external memory and an external device that sup ports the acknowledge function DMA channel 0 transfer addressing mode on source side LSB DMA channel 0 transfer addressing mode on source side MSB 00 Increment 01 Decremen
85. Chapter 4 Caches Fig 4 3 1 Fig 4 3 2 Fig 4 5 1 Fig 4 5 2 Fig 4 5 3 Fig 4 5 4 Fig 4 5 5 Fig 4 5 6 Fig 4 5 7 Fig 4 5 8 Instruction Cache Configuration 4 ssecsssssssscessesnesesossnsedssorssssussesterososeuecorsyenecnenanesucsesese 60 Data Cache Configuration 220 0 61 Operation When an Instruction Cache Hit Occurs 65 Instruction Cache Refill Target Way Selection 66 Operation When an Instruction Cache Miss Occurs 67 Operation When Data Cache Read Hit serens 69 Data Cache Refill Target Way Selection Flow 70 Operation When Data Cache Read Miss Occurs sees 7 Operation When Data Cache Write Hit Occurs Write back Mode 72 Operation When a Data Cache Write Miss Occurs Write back 73 4 5 9 Operation When Data Cache Write Hit Occurs Write through Mode 75 4 5 10 Operation When a Data Cache Write Miss Occurs Write through 76 Fig 4 5 11 Purge Addresses 22 222 0002 2010 77 Fig 4 6 1 Array Address Assignments scccscssssssessess
86. Character length Transmission bit sequence Clock source Maximum transfer speed Error detection during reception Buffers Interrupts DMA requests DC mode None 0 fixed 1 fixed even odd 7 bits 8 bits LSB or MSB selectable 1 2 1 8 or 1 32 of IOCLK 1 8 of timer 0 timer 1 or timer 2 timer 3 underflow or 1 2 of timer 2 timer3 underflow External clock 7 5 Mbps when IOCLK is 15 MHz Parity errors overrun errors Independent buffers for transmission and reception Reception and transmission buffers are both double buffers Transmission interrupts Transmission end or transmission buffer empty selectable Reception interrupts Reception end or reception end with error selectable During transmission Transmission end or transmission buffer empty selectable During reception Reception end None 0 fixed 1 fixed even odd 7 bits 8 bits LSB or MSB selectable 1 8 or 1 32 of IOCLK 1 8 of timer 0 timer 1 or timer 2 timer 3 underflow 1 8 of external clock 19 2 kbps when IOCLK is 15 MHz Parity errors overrun errors framing errors Independent buffers for transmission and reception Reception and transmission buffers are both double buffers Transmission interrupts Transmission end or transmission buffer empty selectable Reception interrupts Reception end or reception end with error selectable During transmission Transmission end or transmission buffer empty selec
87. DSDAT 159 SBIO T 40 VDD 80 PVSS P VSS 160 VDD Those pins which two or more pin names are defined are dual purpose pins 7 Leave open 9 Connect a pull up resistor Pin Descriptions 7 Chapter 1 General 8 Top View pa SYSCLK D15 P17 D13 P15 RAS2 CS2 VREF5V in D10 P12 PULL UP 53 53 RAS1 CS1 D12 P14 D14 P16 D8 P10 D7 P07 A28 CS6 D11 P13 D3 P03 27 TMSIO P25 D9 P11 vss TM2IO P22 5 0 02 02 410 24 TM1IO SBT1 P21 00 00 26 TM3IO P23 A27 CS5 A31 CS7 26 54 54 Pin Descriptions 9 Leave the N C Not Connected open Fig 1 4 2 MN103002AYB Pin Assignment Diagram Chapter 1 General 2 MN103002AYB Pin Assignments 4 Table 1 e ceo 7 NI ST ml e 13 15 12 14 11 1 10 12 9 11 8 10 7 P07 6 P06 5 POS 4 P04 3 2 P02 1 P01 a y 1 P31 BI1 BOO P30 BIO 2 P22 1 SBT1 P21 7 P23 BT2 BO2 e 2 tn ej 0 oJ oj o M ATR a N e Ww e N 21 15 2 S S 2 515121 X S 2 v S 3 4 3i Y Ojo o c A a t
88. Dn and udf08 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases The Ist line of SWAPH s Operation po and bits 31 through 24 with The Ist line of SWAPH s Operation p and bits 32 through 24 with Following sentences are added to Programming Cautions of SW The operations of ud 09 imm8 Dn udf09 imm16 Dn and udf09 imm32 Dn not assured In addition system error interrupt does not occur in these cases ix Errors Placement relationship Notes Insert at least one cycle between the instructions Insert at least two cycles between the instructions Preceding instruction Word half word data 1 ultiply and accumulate instruction Word half word data ultiply and accumulate instruction Word half word data ultiply and accumulate instruction Byte data 2 ultiply and accumulate instruction Byte data 2 ultiply and accumulate instruction Following instruction Quick multiplication instruction 3 Multiply and A indien 4 Following accumulate instruction MCRL access instruction 5 Following nseit at least three cycles Following K etween the instructions Multipl y and 4 accumulate instruction MCRL access instruction 5 Insert at least one cycle Following between the instructions Insert at
89. Fig 5 8 6 Timing for Bus Access by Handshaking Fig 5 8 6 Timing for Bus Access by 32 bit Bus Handshaking P 109 Fig 5 8 7 Timing for Access Synchronous Mode Fig 5 8 7 Timing for Access 16 bit Bus Synchronous Mode P 110 Fig 5 8 8 Timing for Access in Synchronous Mode Fig 5 8 8 Timing for Access in 16 bit Bus Synchronous Mode P 110 Fig 5 8 9 Timing for Bus Access by Handshaking Fig 5 8 9 Timing for Bus Access by 16 bit Bus Handshaking 111 Fig 5 8 10 Timing for Access in Asynchronous Mode Fig 5 8 10 Timing for Access in Asynchronous Mode with 32 bit Bus P 112 Fig 5 8 11 Timing for Access in Asynchronous Mode _Fig 5 8 11 Timing for Access in Asynchronous Mode with 32 bit Bus 5 9 Cautions is added P 137 The Address of DMOCTR x 3200100 The Address of DMOCTR x 32000100 P 146 In section 6 3 4 H 0000 Itransfer X FFFF 65 536 transfers In sectoin 6 3 4 x 0000 ltransfer x FFFF 65536 transfers CNotes on the execution of a BSET or BCLR instruction is added P 156 Clock name in Fig 6 4 8 Clock name in Fig 6 4 8 SYSCLK P 156 Fig 6 4 8 DMA sampling Fig 6 4 8 DMR sampling iv In Fig 7 3 2 NMIRQ pin Watchdog timer overflow System error In Fig 7 3 2 Non maskable NMIRQ pin
90. IOCLK 8 MHz sese 311 Xx Chapter 12 Ports Table 12 1 1 List of R gisters aud mene bd cs Et occ oh a 315 Table 12 2 1 Port 0 Configuration cl 319 Table 12 3 1 Port 1 Conti 323 Table 12 4 1 Port 2 Configuration cscccssssesssssssoesssvssssosssecrscsnessorsecoenssencessesseruecassansensesossssassercensenevs 329 Table 12 5 1 3 eed 333 Table 12 6 L Port doa RR 335 Chapter 13 Electrical Characteristics Table 13 1 1 Absolute Maximum Ratings 2 000000000 338 Table 13 2 1 Operating 330 Table 13 3 1 DC Characteristics 1 2 rne aa aa 340 Table 13 3 2 DC Characteristics 341 Table 13 3 3 DC Characteristics 342 Table 13 34 DC Characteristics 4 343 Table 13 4 1 AC Characteristics 1 ae r e a aaan 344 Table 13 4 2 AC Characteristics 2 00000000 1 02 01 0 80100000 346 Table 13 4 3 AC Characteristics 3 348 Table 13 4 4 AC Characteristics 4 20 002 010 22 221 00 teet anann 349 Table 13 4 5 AC Characteristics 5 44000 20 002002 100 351 Table 13 4 6 Characteristics 6 2202024 0000
91. IR3 to IRO corresponds to an interrupt Once an interrupt is accepted the interrupt handler is responsible for clearing the corresponding bit from IR3 to IRO All bits are cleared to 0 when the system is reset The conditions for setting and clearing IR3 to IRO are listed below ID3 to IDO Interrupt Detect Register 38 This field consists of a maximum of four bits and stores the logical product of each bit from to and with each bit from IR3 to IRO If an interrupt that is enabled by IE3 to IEO is generated the ID bit corresponding to that interrupt goes to 1 This field is used to detect specific interrupts within a group during interrupt processing Interrupt requests are cancelled by writing specific values in IR3 to IRO and ID3 to IDO and clearing the interrupt request field Table 2 7 2 Changes in IR GnICR n 0 Table 2 7 3 Changes in IR GnICR n 2 to 10 12 to 21 or 23 to 30 Write IR after write Unchanged 0 IR after write Unchanged 0 Unchanged 1 Interrupt Functions Chapter 2 CPU 2 7 2 3 Interrupt Accept Group Register IAGR The Interrupt Accept Group Register IAGR stores the current lowest interrupt group number amang the group numbers of the interrupts that have been accepted by the CPU with the same interrupt level indicate by IM2 to IMO in the PSW This register is located at address x 34000200 in the control register space The GN4 t
92. Interrupt Control Register GnICR This 3 bit field sets the interrupt priority level When the interrupt level set in LV2 to LVO is smaller than IM2 to IMO in the PSW interrupts in the corresponding interrupt group are enabled interrupts maxi mum of four in the same interrupt group have the interrupt level specified by LV2 to LVO When interrupt requests are generated simultaneously from multiple interrupt groups those with the high est priority level are accepted Furthermore when multiple interrupt groups have the same interrupt prior ity level interrupts from the group with the highest priority ranking the interrupt group with the smallest group number are accepted All bits are cleared to 0 when the system is reset Interrupt Functions 27 Chapter 2 CPU to IEO Interrupt Enable Register This field consists of a maximum of four bits and specifies whether individual interrupts are enabled or not Each bit from IE3 to IEO corresponds to one of the interrupt sources maximum of four in the interrupt group When any of the bits from to are set to 1 the corresponding interrupts are enabled An interrupt is generated when any bit from IR3 to IRO and the corresponding bit from to are set All bits are cleared to 0 when the system is reset IR3 to IRO Interrupt Request This field consists of a maximum of four bits and registers interrupt requests Each bit from
93. Interrupt Source Assignments Changing values LV2 to LVO interrut priorty level register of GnICR or in to interrupt enable register of GnICR must be operated under the condition inhibiting any interruption and Oxf7ff psw clears IE of PSW nop makes it sure that IE to be cleared nop mov dO GnICR mov GnICR psw or 0 0800 psw in pipe line process sets LV2 to LVO and or IE3 to 0 synchronizes with the store buffer sets IE of PSW While the interrupt handler is being operated IE equals to 0 unless IE has been set So it s not necessary to clear IE Nop instruction shown in above example can be replaced with any instruction unless it causes the changing the values in LV2 to LVO and or to 0 As shown above example nop is inserted twice This is just to make it sure to have minimum cycles need to change the value in IE of PSW Le any instruction set require more cycle than nop instruction twice can be used Description of Registers 171 Chapter 7 Interrupt Controller 7 4 21 Group 2 Interrupt Control Register Register symbol G2ICR Address x 34000108 Purpose This register is used to enable group 2 interrupts and to confirm interrupt requests and detection 1to3 5to7 9to 11 172 Description of Registers Bit name TMOID TMOIR TMOIE G2LVO G2LV1 G2LV2 Description Timer 0 underflow interrupt detecti
94. Ite Symbol Conditio i m ymbol Conditions A NOE Unit Bus request signal timing Refer to Figs 13 4 9 and 13 4 10 EG9 Bus request signal setup time 1 bL 15 ie BR B t signal hold time 1 E70 EET signal hold time 0 T L Bus request signal setup time 2 15 3 iis 72 Bus request signal hold time 2 0 _ T BR t ams E73 Bus grant signal fall delay time ibus _ 5 is BG E74 Bus grant signal rise delay time iiis _ 5 ig Bus tri state delay time 75 A31 0 D31 0 RE WE3 0 CS7 0 15 ns RAS4 1 CAS3 0 Bus buffer on delay time E76 31 0 031 0 RE WE3 0 CS7 0 tson 15 ns RAS4 1 CAS3 0 15 AC Characteristics 359 Chapter 13 Electrical Characteristics BR SYSCLK BR SYSCLK ae ey tenor Es 360 AC Characteristics Fig 13 4 10 Bus Request Signal Timing 2 Refresh request generation when bus authority is released Chapter 13 Electrical Characteristics 13 4 5 Signal Timing Table 13 4 11 AC Characteristics 11 VDD 3 3 0 165 V Vss 0V 20 C to 70 C CL 50 pF Allowable values Item Symbol Condition Unit Min Max DMA signal input output timing Refer to Fig 13 4 1 1 Fig 13 4 12 E77 request input pul
95. MEMCTR2 16 x 1F20 32000026 Memory control register 3 MEMCTR3 16 x 1F20 32000028 Memory control register 4 MEMCTR4 16 x 1F20 3200002 Memory control register 5 MEMCTRS 16 x 0020 3200002 Memory control register 6 MEMCTR6 16 x 0020 x 32000 02 Memory control register 7 MEMCTR7 16 x 0020 x 32000040 DRAM control register DRAMCTR 16 x 0000 32000042 Refresh count register REFCNT 16 x FFFF Depends on the value of FRQS Description of Registers 87 Chapter 5 Bus Controller 5 6 1 Bus Control Register Register symbol IOBCTR Address x 32000010 Purpose Sets the I O bus mode and the number of wait states When reset Bit No Bit name Description 0 IOBM I O bus mode 0 Synchronous mode synchronized with IOCLK 1 Asynchronous mode synchronized with MCLK 4 IOWCO Number of I O bus wait state insertions on chip I O other than the port section LSB 5 IOWCI Number of I O bus wait state insertions on chip I O other than the I O port section IOWC2 Number of I O bus wait state insertions on chip I O other than the port section MSB The relationship between the value of IOWC2 to 0 and the number of wait states is shown below Synchronous mode IOBM 0 number of wait states counted by IOCLK Asynchronous mode IOBM 1 number of wait states counted by MCLK Ignore the lowest two bits 0 wait states 1 1 wait sta
96. Mask Levels and Acceptable Interrupt 1 36 Table 2 7 2 Changes in IR GnICR n 0 38 Table 2 7 3 Changes in IR GnICR n 2 to 10 12 to 21 or 23 to 30 38 Table 2 8 1 CPU Register Status Immediately after a Reset 48 Chapter 3 Clock Generator Table 3 4 1 FRQS Modes Versus Input Frequency Ranges ccccccssessssssssessesesasscsesusssaveseaesesessaneess 54 Table 3 4 2 Relationship between the Input Frequency and the SYSCLK MCLK and IOCLK Frequencies a rette tette 55 Chapter 5 Bus Controller Table 5 3 1 Characteristics of Each BUS asset aed tst ei qe ee er 84 Table 5 5 1 External Pin Functions Relating to the Bus Controller 86 Table 5 6 1 List of BC Registers ume eer dene tus du 87 xix Table 5 7 1 Characteristics of Each Block 103 Table 5 7 2 Examples of Devices That Be Connected Each Block 103 Table 5 8 1 Relationship Between the Clock Frequency and the Number of Cycles CPU Cycles Required for Access ES UR dee P 104 Chapter 6 DMA Controller Table 6 3 1 List of Registers 22 0 20000004402 0 0 138 Table 6 4 1 Devices to
97. Number of Cycles nstruction DO DO DO DO DO DO DO Dm is a value which can be expressed with 2 bytes to 1 byte or Dm 0 _ u Dm is a value which can be expressed with 4 bytes to 3 bytes imm32 is a value which can be expressed with 2 _ bytes to I byte or imm32 2 0 imm32 is a value which can be expressed with 4 bytes to 3 bytes Dm is a value which can be expressed with 2 bytes to 1 byte or Dm 0 VR Dm is a value which can be expressed with 4 bytes to 3 bytes imm32 is a value which can be expressed with 2 bytes to 1 byte orimm32 0 24 imm32 is a value which can be expressed with 4 bytes to 3 bytes gt 4 424 Extension Instruction Specifications Appendices Appendix F Package Outline and Dimensions Fig F 1 shows the package outline and dimensions of the MN103002A and Fig F 2 shows the package outline and dimensions of the MN103002AYB Package code QFP160 P 2828B 31 20 3020 Unit mm 28 00 0 10 121 e 2 Du 160 1 325 02519 g 1 60 SEATING PLANE Sealing material Epoxy resin Leads Copper alloy Lead surface treatment Solder plating Fig F 1 Package Outline and Dimensions of MN103002A Package Outline and Dimensions 425 Appendices Hi mm
98. Register n 4 5 sse 231 9 6 2 Timer 6 Mode Register eese entrent nennen etn tenen 232 9 6 3 Timer n Base Register 4 5 235 9 6 4 Timer n Binary Counter 4 5 6 235 9 6 5 Timer 6 Compare Capture Mode Register 2 236 9 6 6 Timer 6 Compare Capture B Mode Register sss 237 9 6 7 Timer 6 Compare Capture Register essent 238 9 6 8 Timer 6 Compare Capture Register sess 239 9 6 9 Prescaler Control Register 240 vii viii 9 7 Chapter 10 10 1 10 2 10 3 10 4 10 5 Chapter 11 11 1 11 2 Description of Operation sse treten tette tetti nsn tent 241 9 7 1 Timers Aand ee diei 241 9 7 1 1 Interval Timer Timer 241 9 7122 Event Counter essere adtet ete eco edet 243 9 7 1 3 Cascaded Connection sssess sees 245 9 7 2 Timer 6 ee epe otto nete de Eee ERE 247 9 7 2 1 Compare Register Setting sese 247 9 7 2 2 Setting for Capture Register sees 248 9 7 2 3 Setting of Pin Output terere 249 9 7 24 Start Up by an External Trigger sees 252 9 7 2 5 Shot Operation 2 254 9 7 2 6 Interval Timer sss tnter tr tetr nens 256 9 7 2 Event Counter aude eet 260 9 7 2 8 Register Setting
99. SCnMD1 and 0 01 SBTn Transmitter Receiver Bi directional transfer SCnMD1 and 0 11 Fig 11 5 1 Connections 1 lt Start stop synchronous mode gt SBTn Transmitter Receiver SBTn Transmitter Receiver Two different connection methods are possible one for unidirectional transfer and the other for bi direc tional transfer The SBOn pin is always an output and the SBIn pin is always an input SBTn SBTn Unidirectional transfer Transmitter Receiver SBTn Transmitter Receiver Bi directional transfer SBTn Transmitter Receiver Fig 11 5 2 Connections 2 Description of Operation 295 Chapter 11 Serial Interfaces I2C mode It is possible to connect devices that are capable of slave transmission and slave reception SDA and SCL require pull up resistors Connect pull up resistors externally The SBOn pin is an open drain input output and the SBTn pin is an open drain output transmitter 1 mi i receiver Slave trans tter Slave transmitter receiver receiver Fig 11 5 3 Connections 3 296 Description of Operation 11 5 1 2 Baud rates lt Start stop synchronous mode gt Chapter 11 Serial Interfaces Select a suitable baud rate and serial interface input clock in start stop synchronous mode Set the input clock as follows Input clock Desired baud rate x 8 When using IOCLK divide it with transfer time
100. Sets the bus mode and the number of wait states to be inserted for external memory space block 2 Bit No Bit name Description 0 B2DRAM Block 2 DRAM space setting 0 Do not use this block as a DRAM space 1 Use this block as a DRAM space 1 B2WM Block 2 wait mode 0 Fixed wait state insertion 1 Handshaking 2 B2BM Block 2 bus mode 0 Synchronous mode synchronized with SYSCLK 1 Asynchronous mode synchronized with MCLK 5 B2BW Block 2 bus width 0 16 bits 1 32 bits 6 B2CAS Block 2 DRAM byte specification 0 Specified by WE3 to 0 1 Specified by CAS3 to 0 8 B2WCO Number of block 2 wait state insertions LSB 9 B2WCI Number of block 2 wait state insertions 10 B2WC2 Number of block 2 wait state insertions 11 B2WC3 Number of block 2 wait state insertions 12 B2WC4 Number of block 2 wait state insertions MSB After reset mode is released block 2 is set to synchronous mode with 15 wait states and the bus width is 32 bits When using block 2 as a DRAM space the number of wait states is as indicated by the setting of the WC bit in the DRAM control register However even when using block 2 as a DRAM space be sure not to set a prohibited value in B2WC4 to 0 The number of wait states that are inserted is the same as set in bits BOWC4 to 0 Refer to the description of memory control register 0 MEMCTRO Description of Registers 93 Chapter 5 Bus Controller 5 6 2 4 Memory Control Register Register symbol
101. TMOIO TM2IO TM3IO TM4IO 5 TM6IOA and 6 Each register for port 2 is described below 12 4 2 1 Port 2 Output Register Register symbol P20UT Address x 36008004 Purpose Sets the data that is to be output on port 2 200 Bit P270 P260 P250 P240 P230 P220 P210 P name 0 o fo o o o 12 4 2 2 Port 2 Output Mode Register Register symbol P2MD Address x 36008024 Purpose This register selects the port 2 pin output content For details on the P27M to P20M settings refer to the description of the port 2 dedicated output control register 326 Port2 Chapter 12 Ports 12 4 2 3 Port 2 Dedicated Output Control Register Register symbol P2SS Address x 36008044 Purpose This register selects the port 2 pin output content in conjunction with P2MD P27M to P22M 0 Timer input outputs 210 TM3IO TM4IO TMSIO TM6IOA TM6IOB 1 General purpose I O port P27 to P22 For details on other bits see below P21M P21S 00 Serial interface input output SBT1 01 Timer input output TM1IO 1 General purpose port P21 P20M P20S 00 Serial interface input output SBTO 01 Timer input output TMOIO 1x General purpose I O port P20 Port2 327 Chapter 12 Ports 12 4 2 4 Port 2 Input Output Control Register Register symbol P2DIR Address x 36
102. There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW 304 Extension Instruction Specifications Appendices MULQU Unsigned quick multiplication instruction between registers Instruction Format Macro Name MULQU Dm Dn Assembler Mnemonic udf01 Dm Dn Operation This instruction performs multiplication quickly using the multiplier in the extension function unit The instruction multiplies the contents of Dm unsigned 32 bit integer multiplicand by the contents of Dn unsigned 32 bit integer multiplier and then stores the upper 32 bits of the 64 bit result in the quick multiply register MDRQ and the lower 32 bits in Dn The range of significant values for the multiplicand that is stored in Dm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the contents that are stored in Dm the quicker the result of the operation can be derived Flag Changes Fg Gage 1 when the MSB of the lower 32 bits of the result is 1 0 in all other cases 1 when the lower 32 bits of the result are all 0 0 in all other cases Programming Cautions There is a one
103. Which Transfer Is Possible s 149 Chapter 7 Interrupt Controller Table 7 4 1 Register List essent 168 Chapter 8 8 bit Timers Table 8 5 1 Function Chart a 209 Table 8 6 1 List of 8 bit Timer Registers 22 0 00002020212 00 0 teens 210 Table 8 6 2 8 bit Timer Clock Source 20 212 Chapter 9 16 bit Timers Table 9 5 1 16 bit Timer Functions oe oec hetero c t dud 229 Table 9 6 1 List of 16 bit Timer Registers 1 1122 230 Table 9 6 2 16 bit Timer Clock Source te tds or th i e Dee acid c Re 232 9 7 1 Pr quencies adesto a oa aang ess 262 PE QAO SI AMET p 263 Chapter 10 Watchdog Timer Table 10 4 1 List of Watchdog Timer Registers 268 Table 10 4 2 Examples of Overflow Cycle 270 Chapter 11 Serial Interfaces Table 11 4 1 List of Serial Interface Registers treten 283 Table 11 5 1 Baud Rates 1 when IOCLK 15 297 Table 11 5 2 Baud Rates 2 when IOCLK 12 MHZ 298 Table 11 5 3 Baud Rates 3 when 10 2 0 2 204001 00000 298 Table 11 5 4 Baud Rate Error 1 When IOCLK 15 MHZ etes 310 Table 11 5 5 Baud Rate Error 2 When IOCLK 12 311 Table 11 5 6 Baud Rate Error 3 When
104. Write gt 4 Write gt cycle cycle Fig 5 8 21 32 bit DRAM Page Mode Write Timing When FRQ 0 122 Description of Operation Chapter 5 Bus Controller TLL LU UU UU UU UU UU uuu A31 0 Golam lii Colum m CAS3 2 c TT WE3 2 D31 16 RD WT Read Read Read Read Read Read Read Read cycle cycle cycle cycle cycle cycle cycle cycle 51281 0 m Fig 5 8 22 16 bit DRAM Page Mode Read Timing When FRQ 0 A31 0 X Ro Column ColumnX ColumnX ColumnX Colum CX RASn CAS3 2 RE WE3 2 LL C RD WT X 4 7 Write Write Write Write Write Write Write Write cycle cycle cycle cycle cycle cycle cycle cycle Fig 5 8 23 16 bit DRAM Page Mode Write Timing When FRQ 0 Description of Operation 123 Chapter 5 Bus Controller DRAM page mode when FRQ 1 Just as when FRQ 0 if the PAGE bit in the DRAM control register is set page mode access is enabled making high speed access in page mode possible for consecutive accesses to DRAM The byte specification by WE3 through 0 is set by clearing the BnCAS bit in memory control registers 1 through 3 The RAS signal and in the case of a write the WE signal are negated as soon as the consecutive accesses to DRAM are co
105. Z HiiZ External device Standby 132 Description of Operation Fig 5 8 34 Bus Arbitration Timing 1 Bus Authority Release Bus Authority Acquisition Chapter 5 Bus Controller SYSCLK MCLK A31 0 CSn 52252 Q gt n m BR 7 BG CEPT DDT i Standby 2 Refresh Fig 5 8 35 Bus Arbitration Timing 2 Refresh Request Generated While Bus Authority Has Been Released and FRQ 0 Description of Operation 133 Chapter 5 Bus Controller 5 9 Cautions These cautions concern the BC These cautions must be heeded since failure to do so may result in misoperation l Interrupts are prohibited and the bus is locked occupied by the CPU when BSET or BCLR is being executed However if a BSET or BCLR instruction is executed during program execution in external memory a bus authority release due to an external bus request or DMA transfer may be interposed between the data read and data write by the BSET or BCLR instruction If the atomic bus cycles of the BSET or BCLR instruction need to be guaranteed in a system that uses multiple processors either of the following measures should be taken 1 A program in which a BSET or BCLR instruction is executed should be placed in instruction cache Note that an external memory access is occurred if a cache mi
106. accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new resulting cumu lative sum back in multiply and accumulate register MCRH and the lower 32 bits in multiply and accu mulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Condition Programming Cautions A non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction Extension Instruction Specifications 405 Appendices MACIHU Unsigned half word data multiply and accumulate operation instruction between immediate value and register Instruction Format Macro Name MACIHU imm Dn Assembler Mnemonic udfu31 imm8 Dn imm8 is zero extended udfu31 immi6 Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the 16 bit data that is obtained by zero extending imm multiplicand by the contents of Dn unsigned 16 bit integer multiplier adds the upper 32 bits and lower 32 bits of the result ing 64 bit product to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 3
107. are all by fixed wait state insertion not by handshaking Fig 5 8 10 is a timing chart for an access with a 32 bit bus in asynchronous mode During a read the RE signal is asserted 1 2 of an MCLK cycle after the start of the bus cycle and is negated 1 2 of an MCLK cycle before the end of the bus cycle During a write the WE signal is asserted 1 2 of an MCLK cycle after the start of the bus cycle and is negated 1 2 of an MCLK cycle before the end of the bus cycle The minimum number of wait states for the bus cycle when FRQ is 0 is one wait state When writing byte 0 WEO is asserted and the data is output on D7 to 0 When writing byte 1 WEI is asserted and the data is output on D15 to 8 When writing byte 2 WE2 is asserted and the data is output on D23 to 16 When writing byte 3 WE3 is asserted and the data is output on D31 to 24 MCLK A31 0 WE3 0 D31 0 RD WT SIZE1 0 1 wait ok 1 wait ok e Read cycle Write cycle Fig 5 8 10 Timing for Access in Asynchronous Mode with 32 bit Bus FRQ 0 One Wait OK Description of Operation 112 Chapter 5 Bus Controller 32 bit bus asynchronous mode when FRQ 1 Fig 5 8 11 is a timing chart for an access with a 32 bit bus in asynchronous mode During a read the RE signal is asserted one MCLK cycle after the start of the bus cycle and is negated one MCLK cycle before the end of the bus cycle During a
108. be done after the initialization 4 Setting for I O port Set TM6IOB as input pin Setting of TM6IOA pin is optional Please refer the chapter of I O port for the register setting 5 Permission for starting up of timer with external trigger Set 1 into TM6TGE of TM6MD register Timer 6 starts up when specified edge is give to TM6IOB TM6CNE flag of TM6MD register is set by hardware 252 Description of Operation Chapter 9 16 bit Timers Steps for operation termination 1 Inhibit starting up of timer by external trigger Set 0 into TM6TGE of TM6MD register 2 Stop count operation Set 0 into TM6CNE of TM6MD register Setting 0 to TM6TGE and TM6CNE simultaneously might cause resetting of TM6CNE due to the pin input timing To avoid this case user must set 0 into TM6TGE first then set 0 to TM6CNE Pin input TM6IOB Edge ditection TM6CNE 0001 Y 0002 Y 0003 Y 0004 Fig 9 7 13 Start Up by an External Trigger When rising edge is selected Description of Operation 253 Chapter 9 16 bit Timers 9 7 2 5 One Shot Operation Timer 6 can be terminating by the matching of TM6BC and TM6CA Fig 9 7 14 15 shows the signal wave while timer 6 is inactivating Compare capture register B can be used as either of compare register or capture register Steps for start up 1 Setting of compare capture register A Set TM6MDA register as shown below 6 2 1 0 optional TM6ACE
109. below Fig F 1 shows the package outline and dimensions of the MN103002A and Fig F 2 shows the package outline and dimensions of the MN103002AYB Fig F 1 Package Outline and Dimensions Fig F 1 Package Outline and Dimensions of MN103002A Fig F 2 Package Outline and Dimensions of 103002 is added In addition to these corrections how to describe the unit is changed but the data are not changed Example In the section 3 3 Block Diagram Error 13 0M 16 6MHz Correction 13 0 MHz to 16 6 MHz Cover MICROCOMPUTER MN10300 Cover MICROCOMPUTER 1030 Special attention and precautions In the number 1 Foreign Exchange and Foreign Trade Control Law Special attention and precautions In the number 1 Foreign Exchange and Foreign Trade Law Special attention and precautions If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation s Sales Department Special attention and precautions Tf you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book Colophon Issued by Matsushita Electric Industrial Co Ltd Matsushita Electronics Corporation Matsushita Electric Industrial Co Ltd Matsushita Electron
110. bits are cleared by software in the interrupt processing program When clearing one of these bits write a 0 to the bit to be cleared and write a 1 to the corresponding bit from IDO to 3 De To 8 11 to Group n interrupt enable register BERN This register is used to specify whether an interrupt is enabled or not When an IE bit is set to 1 the corresponding interrupt is enabled Setting an IE bit while the corresponding IR bit is set generates an interrupt Continued 170 Description of Registers Chapter 7 Interrupt Controller Continued Bit No 12 to 14 Bit name LVO to LV2 Description Group n interrupt priority level register This register sets the interrupt priority levels If the interrupt level set in the LV 2 0 bits is smaller than the IM 2 0 bits in the PSW interrupts of the corresponding interrupt group are permitted Interrupts in the same interrupt group are all of the level specified by the LV 2 0 bits When simultaneous interrupt requests are generated from more than one interrupt group the interrupt with the highest interrupt priority level is accepted In addition if multiple interrupt priority levels are set in the same level the interrupt from the group with the smallest group number is accepted For details on the interrupt sources assigned to each group refer section 7 3 2
111. both the CPU and the peripheral circuits are stopped Indicates a mode in which the CPU is stopped and the peripheral circuits are operating Indicates that wait states are inserted until oscillation stabilizes Fig 2 8 1 Operating Mode Transition Diagram 1 Mode transitions are controlled by programs by setting the CPUM register Operating Modes 47 2 48 2 8 2 Reset Mode Reset mode is the state in which the reset pin is active low If the reset pin goes active the chip resets initializes itself internally and begins waiting for oscillation to stabilize by means of an 18 bit binary counter that is driven by the oscillation clock During fast oscillation Oscillation stabilization wait time for oscillating frequency La tew TEX Ii In other words when f 16 5 MHz t 15 888 ms OSCWz66 MHz Table 2 8 1 shows the status of the CPU registers immediately after a reset Table 2 8 1 CPU Register Status Immediately after a Reset x 40000000 Undefined Undefined Undefined Undefined Undefined Undefined x 0000 After the wait for oscillation stabilization is completed the internal reset is released and the microcontroller enters normal operation mode Operating Modes Chapter 2 CPU 2 8 3 Low Power Consumption Modes Low power consumption is attained by halting the oscillation of the oscillator itself or PLL oscillatio
112. branch processing Supports linear address space of up to 4 GB Cache memory Instruction cache Size 4 Kbytes 2 Kbytes x 2 128 entries lines size 16 bytes 2 way set associative LRU replacement algorithm Individual ways can be used as RAM Three possibilities two way cache one way cache RAM or RAM 2 Overview Features Chapter 1 General Data cache Size 4 Kbytes 2 Kbytes x 2 128 entries 16 byte line size two way set associative Writing policy Switchable between write back and write through Conversion to RAM in way units possible Three possibilities 2 way cache 1 way cache RAM and RAM Flexible clock control Self excited externally excited oscillation Clock is supplied either by connecting an oscillator or by inputting a clock signal Either of the 2 x or 4 x oscillated signal or input clock can be selected for the clock CPU clock Internal maximum 66 6 MHz The external bus clock is identical to the oscillation input clock Low power consumption mode Supports three modes HALT STOP and SLEEP mode High speed high performance bus interface High speed control of the internal bus external bus is possible using the CPU clock Two modes are supported for the internal I O bus and the external bus synchronous mode synchronized with the external bus clock asynchronous mode synchronized with the CPU clock not synchronized with the external clock
113. bus cycles Number of I O bus cycles nous 2 2 Write Synchro Number of I O bus cycles Number of 1 O bus cycles nous 104 102 Asynchro Number of I O bus cycles Number of I O bus cycles nous 1 1 Synchro Number of EX bus cycles Number of EX bus cycles External memory Read nous 003 d Asynchro Number of EX bus cycles Number of EX bus cycles nous 0104 0102 Write Synchro Number of EX bus cycles Number of EX bus cycles nous 3 0103 0102 Asynchro Number of EX bus cycles Number of EX bus cycles nous 0104 0102 synchronous mode wait of a maximum of three cycles for synchronization is generated In synchronous mode when the MCLK frequency is four times the SYSCLK frequency a wait of a maximum of three cycles for synchronization is generated if the MCLK frequency is twice the SYSCLK frequency a wait of a maximum of one cycle for synchronization is generated 104 Description of Operation Chapter 5 Bus Controller 5 8 2 Store Buffer The bus controller has one store buffer with a 32 bit data width built in and is used to avoid a time penalty when conducting a store operation in internal IO or external memory The CPU store operation is completed by storing the address data and access size in the store buffer and is executed with no wait states Writes from the store buffer to internal I O or external memory are conducted in parallel with subsequent CPU operations However if there is a load r
114. detect register MCVF into the V flag In addition depending on the value of Dm or imm amp the following operations per formed 1 2 3 4 When the value of Dm or imm is 32 0x00000020 When the 64 bit result of the multiply and accumulate operation that is stored in the multiply and accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 32 bit signed number 0x000000007 the maximum positive value 0 7 fffffff is stored in Dn If the value stored in the multiply and accumulate registers MCRH and MCRL is equal to or less than the maximum negative value for a 32 bit signed number Oxffffffff80000000 the maximum negative value 0x80000000 is stored in Dn In all other cases the contents of MCRL are stored in Dn When the value of Dm imm is 16 0x00000010 When the 64 bit result of the multiply and accumulate operation that is stored in the multiply and accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 16 bit signed number 0x0000000000007 the maximum positive value 0x00007 is stored in Dn If the value stored in the multiply and accumulate registers MCRH and MCRL is equal to or less than the maximum negative value for a 16 bit signed number 8 000 the maximum negative value Oxf ff 8000 is stored in Dn In all other cases the contents of MCRL are stored in D
115. eene 100 Memory Spaces bertus te bile da 101 Description of 4412 22 2 020 0000000000000000000000 104 5 8 1 Number of Basic Bus Cycles sse eene 104 5 8 2 Store Buffer eae e S ne 105 5 8 3 Accessing the Internal Space sss 105 5 8 3 1 Synchronous Mode 105 5 8 3 2 Asynchronous Mode Access 107 5 8 4 External Memory Space Access non DRAM Spaces 108 5 8 4 1 Bus Synchronous Modes essere tenere 108 5 8 4 2 Asynchronous Modes 0 0444 4 410000000 ettet ternos 113 5 8 5 External Memory Space Access DRAM 117 5 8 5 1 RAS CAS Signal Timing 22 117 5 8 5 2 Normal Mode sse tentent tentn tette tetnts 118 5 6 9 3 Page Mode stetig e atv ned 121 5 8 5 4 Refft slic c ete eti eret db toque oid 127 5 8 5 5 Connection Examples sse tenes 129 5 8 6 Bus Arbitration eode eai UR Pe et dick 132 5 9 QUOS corte pM 134 Chapter 6 Controller 6 1 OVERVIEW dq 136 6 2 inl p 136 6 3 Description of DMA Registers eessseeeeeeee treten eterni ntn 138 6 3 1 DMA Control Regist
116. es uj ps 5j mission end A B D Fig 11 5 12 Timing Chart 9 304 Description of Operation Chapter 11 Serial Interfaces Initial Settings 1 Select the transmission clock 5 2 to 0 Setting an external clock is prohibited 2 The parity bit is used as a substitute for Ack When transmitting set the parity bit to 1 fixed SCnPB2 to 0 When detecting an Ack signal output by the receiving slave device enable the receiving operation even when transmitting The signal is detected as a parity error 3 Set the character length and the transmission bit sequence SCnCLN SCnOD 4 Set the I2C mode selection flag SCnIIC to 0 5 Set the protocol to I2C mode and set the SBT pin as an output only when transmission is in progress SCnMDI and 0 SCnTOE The SBO and SBT pins are open drain outputs 6 Enable the transmission operation 5 Enable reception also when the Ack signal is detected and during master reception SCnRXE A Start sequence send 1 When a 1 is written to the I2C mode selection flag SCnIIC a low signal is output on the SBO pin as the start sequence When the start sequence is generated normally the I2C start sequence detection bit SCnSTF is set to 1 In this case even if there is another simultaneous start the arbitration lost state is not detected B Data transmission 1 1 Data is transmitted once the data is written to the serial transmis
117. fetched by reading the SCnRXB register In the case of a 7 bit transfer the MSB bit 7 is 0 The SCnRXF flag is set to 1 at the start of reception at the falling edge of SBT and is set to 0 at the end of reception The SCnRBF flag is set to 1 at the end of reception and is set to 0 when SCnRXB is read An overrun error is generated when reception of the next data is completed before previously received data has been read from the SCnRXB register In this event the previously received data is lost The overrun error indicator flag SCnOEF is updated at the moment the final data bit is received parity error is generated when the parity bit is fixed to 0 and a 1 is received when the parity bit is fixed to 1 and a 0 is received when even parity is set and an odd number of ones is received or when odd parity is set and an even number of ones is received The parity error indicator flag SCnPEF is updated at the moment the parity bit is received Description of Operation 301 Chapter 11 Serial Interfaces 11 5 1 4 Start stop Synchronous Mode Timing Transmission Transfer with 8 bit data length parity on and 1 stop bit SBO pin st ii bot bes 5 7 s Data write SCnTXF flag SCnTBF flag Interrupt request i A when set to transmission end Interrupt DMA request when set to transmis sion buffer empty
118. flag settings Table 2 5 3 List of Transfer Instructions Instruction Description MOV Transfer of word data between registers Transfer of word data between a register and memory Transfer of an immediate value into a register Transfer of byte data between registers and memory zero extension Transfer of half word data between registers and memory zero extendsion MOVM Transfer between multiple registers and memory EXTHU 32 bit zero extension of half word data CLR Instructions 27 2 2 5 3 2 Arithmetic Operation Instructions The arithmetic operation instructions perform arithmetic operations on the source operands and store the results in aregister of these instructions produce changes in flag settings The 41 and 4 operations which are used frequently in address calculations are provided with separate special instructions Table 2 5 4 List of Arithmetic Operation Instructions Instruction Description ADD Add ADDC Add with carry SUB Subtract SUBC Subtract with borrow MUL Signed multiplication MULU Unsigned multiplication DIV Signed division DIVU Unsigned division INC Increment by 1 INC4 Increment by 4 2 5 3 3 Compare Instruction The compare instruction compares the contents of two registers or the contents of a register with an immediate value This instruct
119. for count operation of timer 6 when 1 8IOCLK or 1 32 IOCLK is used as a clock Source Chapter 9 16 bit Timers 4 Initialization of timer Initialization of timer 6 setting 1 into TM6LDE of TM6MD register is cleared and pin output is reset If TM6CA has double buffer compare register setting value in buffer is load into compare register User must switch to normal operation mode setting 0 is not TM6LDE after the initialization 5 Setting for I O port case using pin output Set I O port to timer pin output Select timer pin output as output signal with I O port register Please refer chapter of I O port for register setting 6 Permission for count operation Count operation starts by setting 1 into TM6CNE of TM6MD register Interrupt request of compare capture A is generated with a specified cycle when count operation is permit ted Changing of the interrupt cycle is available by handling the value in the TM6CA register causing the loading from buffer to compare register when TM6BC is cleared TM6CA must be set to double buffer compare register to change the interrupt cycle during count operation Steps for operation termination 1 Terminate count operation Count operation is stopped if set value 0 into TM6CNE of TM6MD register 2 Initialize timer as necessary Setting 1 into TM6LDE of TM6MD register cause the clearing of TM6BC and the reset of timer output If TM6CA register has double buffer setting value i
120. interrupt enable flag 0 Disabled 1 Enabled 9011 Always returns 0 12 G20LVO Group 20 interrupt priority level register LSB 13 G20LV1 Group 20 interrupt priority level register 14 G20LV2 Group 20 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 189 Chapter 7 Interrupt Controller 7 4 2 19 Group 21 Interrupt Control Register Register symbol G21ICR Address x 34000154 Purpose This register is used to enable group 21 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 SC2TID Serial 2 transmission interrupt detection flag 0 No interrupt detected 1 Interrupt detected 13 Always returns 0 4 SC2TIR Serial 2 transmission interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 SC2TIE Serial 2 transmission interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G21LVO Group 21 interrupt priority level register LSB 13 G21LVI Group 21 interrupt priority level register 14 G21LV2 Group 21 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 190 Description of Registers Chapter 7 Interrupt Controller 7 4 2 20 Group 23 Interrupt Control Register Register symbol G23ICR Address x 3400015C Purpose This register is used to enable group 23 inte
121. interrupts are not accepted The numbers shown in this figure correspond to the step numbers of the processing performed by the interrupt handler as described above Interrupt 11 cycles max Y Program Interrupt Functions Processing for the individual level Handler preprocessing Processing for the au group Processing for the individual source B TET Interrupt processing nterrupt and interrupt request handler cancellation Handler post processing Fig 2 7 5 Flow of Interrupt Sequence Chapter 2 CPU Even faster interrupt response can be attained by assigning only one source or just a few sources to one interrupt level Fig 2 7 6 shows the flow of the interrupt sequence when only one source was assigned to one interrupt level ccm m Lem Processing for the individual source Interrupt 11 cycles max Handler preprocessing Y mE 7 Interrupt 6 Handler post processing LR Si Fig 2 7 6 Flow of Interrupt Sequence Interrupt Functions 45 Chapter 2 CPU 2 7 4 2 Nested interrupts When a level interrupt is generated nested interrupts are prohibited by clearing the IE flag in the PSW Nested interrupts can be enabled even while in the midst of processing a level interrupt by setting the IE flag to 1 However in order for a nested interrupt to be generated the interrupt must st
122. is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes pr CODE JN ne pp e E oe eee a ee ee V N Programming Cautions A non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction Extension Instruction Specifications 407 Appendices MACIBU Unsigned byte data multiply and accumulate operation instruction between immediate value and register Instruction Format Macro Name MACIBU imm Dn Assembler Mnemonic udfu33 imm8 Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the 8 bit data imm multiplicand by the contents of Dn unsigned 8 bit integer multiplier adds the resulting product to the 32 bit cumulative sum that is stored in the multiply and accumulate register MCRL and then stores the new resulting 32 bit cumulative sum back in multiply and accumulate register MCRL If an overflow from the 32 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag e Change Condition Programming Cautions non extension
123. least two cycles Following between the instructions Corrections Placement relationship Notes Insert at least one cycle between the instructions Preceding instruction Word half word data T IM ultiply and accumulate instruction Word half word data IM ultiply and accumulate instruction Word half word data 1 IM ultiply and accumulate instruction Byte data 2 IM ultiply and accumulate instruction Byte data 2 IM ultiply and accumulate instruction Following instruction Quick multiplication instruction 3 Multipl y and 5 instmetion Following IMCRH MCRL access instruction 5 Multiply and 4 accumulate instruction MCRL access instruction 5 Extension Operation instruction Following Insert at least two cycles between the instructions Insert at least three cycles Following between the instructions Insert at least one cycle Following between the instructions Insert at least two cycles Following between the instructions 6 Insert at least one cycle mov regs SP instruction between the instructions Following i None The following note is added 6 This problem can be avoided by an assembler after V3 1R9 At assembling nop instruction is automatically inserted between the mov and extended operation instructions The package outline and dimensions of the MN103002A shown
124. mode Bus release mode L Operating Operating x 9C000000 Operating Hi Z D31 0 Hi Z Operating Hi Z RAS4 1 Operating Hi Z Operating Hi Z Operating Hi Z Operating Hi Z Operating Hi Z Operating Hi Z Operating Hi Z Operating Hi Z Operating L Hi Z High impedance Hold Hold status from immediately preceding external bus cycle Input Input status L Low level output H High level output Because A31 and CS7 as well as A28 through 26 and CS6 through 4 dual purpose pins x 9000000 are output 7 Shows the input signal level Adjust so that the prescribed level is attained External Pin Statuses 371 possoooe st jou st jeu Bare ue 3 jou st payiqryosd si Jou yey 8918 Surssoooy 910N LC ANUS 0 ABM X4L00T8C X X4L00T8C X 1000180 0000782 X3LT008 X 10082 ae 4100082 00082 XT000082 X 0000082 1000002 2000002 o z in o vjep ayors Em 10909 ayp x ndo E 101934 1dnuoju ONANI E z 1 dew seysiBey L O 1000002 X0000002 X 372 List of Register Maps
125. of Operation 117 Chapter 5 Bus Controller MCLK A31 0 CASn RE WE3 0 D31 0 RD WT SIZE1 0 RASn LEE G LL Row ett TE Row Column Write cycle RPCP Fig 5 8 15 RAS CAS Signal Timing When FRQ 1 5 8 5 2 Normal Mode This section explains the timing of the 32 bit DRAM bus cycle for the basic cycle when the DRAMCTR bits 0 RPCP 0 PAGE 0 and WC 0001 For details on the settings of the RTC RPCP PAGE and WC bits refer to Section 5 6 3 1 DRAM Control Register DRAM read write when FRQ 0 Regarding accesses to DRAM spaces the address is shifted down and the row address is output according to the value of the SIZE1 and 0 bits in the DRAM control register The byte specification by WE3 through 0 is set by clearing the BnCAS bit in memory control registers 1 through 3 The RASn signal n corre sponds to the block number and the CAS3 signal are then output according to the values of the RTC bit bit and the WC3 through 0 bits in the DRAM control register The byte specification by CAS3 through 0 is set by setting the BnCAS bit in memory control registers 1 through 3 In this case WE3 is used Fig 5 8 16 shows the 32 bit bus timing and Fig 5 8 17 shows the 16 bit bus timing 118 Description of Operation Chap
126. of that entry is 0 then an instruction cache miss is said to have occurred If a miss occurs in the instruction cache the instruction is fetched from external memory If an instruction is fetched from external memory an entry line for caching that instruction must be simultaneously allo cated in the cache First the refill target way is selected according to the value of the valid bit V in the tag array entry that was accessed the LRU data stored in the LRU field and the way operation mode that is set in the cache control register CHCTR Fig 4 5 2 shows the flow by which the instruction cache refill target way is selected Miss occurs in instruction cache Way operating mode CHCTR 9 8 3 CHCTR 9 8 22 or 1 CHCTR 9 8 0 Way operating mode CHCTR 9 8 2 Go to next access without refilling Select way 0 LRU don t care LRU don t Select way 0 Select the way indicated by LRU Select way 1 LRU 1 LRU update previous value LRU don t care CHCTR 9 8 1 Fig 4 5 2 Instruction Cache Refill Target Way Selection Flow Next after setting the refill bit R in the tag entry of the way that was selected the external bus access refill operation which loads one line of instructions from external memory into cache memory is initi ated The refill is performed in a burst transfer of four words 16 bytes which is one line of data that starts from the a
127. of the built in caches of the MN103002A MN103002A YB are described below 58 Conflicts between instruction accesses and data accesses are avoided since the caches are separated into an instruction cache and a data cache The instruction cache and the data cache are both 4 Kbytes two way set associative caches Way operation can be selected for the instruction cache and the data cache in any of the following three arrangements 1 4 Kbytes cache 2 2 Kbytes cache and 2 Kbytes RAM 3 4 Kbytes RAM In order to minimize the penalty resulting from cache misses refilling begins with the word that was missed The data cache can be written either by the write back method or the write through method selectable The entire contents of the cache can be invalidated in one operation Overview Features Chapter 4 Caches 4 3 Configuration 4 3 1 Instruction Cache The instruction cache has a 4 Kbytes capacity and adopts the two way set associative method for association The instruction cache consists of two data memory blocks two tag memory blocks and an LRU block Data memory The data memory stores instructions in 16 byte units Each way has 2 Kbytes of data memory for a total of 4 Kbytes The data memory line size is 16 bytes and the number of entries is 128 Instruction transfers from external memory to the instruction cache are handled in 16 byte 128 bit units while instruction transfers from the instruction cache to the C
128. of warranty 8 7 4 Example of Prescaler Timer and Cascaded Timer 1 When set clock source of timer 1 to underflow flag of timer 0 After become underflow the value of TMOBR is loaded into TMOBC and the value of TMIBC decrement After TM1BC become underflow the value of TM1BR is loaded into Value in X01 Xx00X a X A X XxO X a 4 X TMOBR value TMnBR value TMOBR value value 1 TMOBR value Interrupt request TMOIRQ Value in mec Y X Interrupt request TMIIRQ Fig 8 7 6 Operation of Timer 0 and 1 1 220 Description of Operation Chapter 8 8 bit Timers 2 When timer0 1 are cascaded During 00 when TMOBC become underflow TMOBC is set to x FF and the value of TMIBC decrement During TM1BC 00 when TMOBC become underflow the value of TMoBR TMIBR are loaded into TMOBC and the interrupt request of timer 1 occurs Value i X x00 XxFF aoo a x00 Larry TMOBR value TMOBR value 1 Interrupt request TMOIRQ Value in Y 5 mmm Interrput request TMIIRQ Fig 8 7 7 Operation of Timer 0 and 1 2 Description of Operation 221 Chapter 8 8 bit Timers 222 Description of Operation Chapter 9 16 bit Timers Chapter 9 16 bit Timers 9 1 Overview The 16 bit timers incl
129. overflow signal output timing Refer to Fig 13 4 16 Watchdog overflow signal rise delay time E85 twpovrro 5 ns WDOVF Watchdog overflow signal fall delay time E86 twooverp 5 5 ns WDOVF SYSCLK Nf twooverp Fig 13 4 16 Watchdog Overflow Output Timing AC Characteristics 365 Chapter 13 Electrical Characteristics 13 4 9 Serial Interface Signal Timing Table 13 4 15 AC Characteristics 15 VDD 3 3 4 0 165 Vss 0V 20 C to 70 C CL 50 pF Allowable values Conditions Unit Min Max i Item Symbol Serial interface signal input output timing Refer to Fig 13 4 17 and Fig 13 4 18 E87 Reception data setup time 5 as SBI2 0 E88 Reception data hold time _ 2 _ us SBI2 0 E89 Transfer data delay time 1 25 _ 8 AG SBO2 0 Transfer data delay time 2 SBO2 0 E90 trxpp2 0 ns Fig 13 4 17 Serial Interface Signal Timing 1 during synchronous serial reception 366 AC Characteristics Chapter 13 Electrical Characteristics SBT2 0 UU TN A N SBO2 0 trxovz Fig 13 4 18 Serial Interface Timing 1 during synchronous serial reception 13 4 10 AC Characteristics Test Conditions Input voltage high level Vit Input voltage low level
130. purpose output port General purpose input port General purpose output port General purpose input port General purpose output port General purpose input port General purpose output port General purpose input port After a reset 1 223 Chapter 12 Ports 12 4 2 12 4 1 Block Diagram Fig 12 4 1 and Fig 12 4 2 shows the block diagram for port 2 Intemal data bus P2OUT W Port i P2OUT R orz pi SBT1 0 3 P21 20 TMOIO 3 Output enable for the above Input P2DIR W Output Control P2DIR R P2SS W P2SS R P2MDIW P2MDIR TMOIO SBTI 0 Fig 12 4 1 Port 2 Block Diagram P21 20 324 2 Chapter 12 Ports Internal data bus P2OUTIW 2 Port 2 pin P2OUT R D n MPX gt TM6IOB TM6IOA 27 22 5 TM3IO LN Output enable for the above P2DIR W MPX x gt Pamo P2MDI R 2 1 TM6IOB TM6IOA TMSIO TM4IO TM3IO Fig 12 4 2 Port 2 Block Diagram P27 to 22 Port 2 325 Chapter 12 1 O Ports 12 4 2 Description of Registers Port 2 is a general purpose input output port that also can be used as serial interface output SBTO and SBT1 and timer input outputs
131. rate error can be calculated as follows Baud rate error ABS IOCLK frequency division ratio 1 division ratio 2 desired baud rate 1 Typical examples are listed in the following table Table 11 5 4 Baud Rate Error 1 When IOCLK 15 MHz High speed UART Baud rate Division Division Error of transmission ratiol ratio2 rate 230 400 1 H 115 200 56 000 38 400 19 200 9 600 4 800 2 400 1 200 LL 600 300 150 310 Description of Operation Chapter 11 Serial Interfaces Table 11 5 5 Baud Rate Error 2 When IOCLK 12 MHz High speed UART Baud ne Division Division Error of transmission ratio J ratio 2 rate 230 400 1 0 16 115 200 0 16 56 000 0 13 38 400 0 16 19 200 0 00 9 600 0 00 4 800 0 00 2 400 0 00 1 200 0 33 T 600 0 33 300 0 01 0 01 Table 11 5 6 Baud Rate Error 3 When IOCLK 8 MHz High speed UART Baud rate Division Pasion Error of transmission ratio 1 ratio rate 34 69 71 104 Because the transfer rate error is large when transferring at a baud rate of 230 4 kbps while IOCLK 8 MHz using that baud rate with that IOCLK frequency is not recommended Description of Operation 311 Chapter 11 Serial Interfaces 11
132. reception end when the SCnRBF flag is 1 the received data is fetched by reading the 5 register In the case of a 7 bit transfer the MSB bit 7 is 0 The SCnRXF flag is set to 1 at the start of reception when the start bit is detected and is set to 0 at the end of reception The SCnRBF flag is set to 1 at the end of reception and is set to 0 when SCnRXB is read An overrun error is generated when reception of the next data is completed before previously received data has been read from the SCnRXB register In this event the previously received data is lost The overrun error indicator flag SCnOEF is updated at the moment the final data bit is received parity error is generated when the parity bit is fixed to 0 and a 1 is received when the parity bit is fixed to 1 and a is received when even parity is set and an odd number of ones is received or when odd parity is set and an even number of ones is received The parity error indicator flag SCnPEF is updated at the moment the parity bit is received framing error is generated when 0 was received for the stop bit The framing error indicator flag SCnFEF is updated at the moment the stop bit is received 11 5 1 5 2 Mode Timing Master transmission SBO pin SDA SCnIIC flag Data write SCnTXF flag EN SE Interrupt i A request set ip Md ppl lt cL
133. registers with regs specification 11 Number of registers with regs specification 0 Number of registers with regs specification 1 Number of registers with regs specification 2 Number of registers with regs specification 53 Number of registers with regs specification 4 Number of registers with regs specification 7 Number of registers with regs specification 8 Number registers with regs specification 9 Number of registers with regs specification 10 JAn d16 PC CALLS Number of registers with regs specification 0 Number of registers with regs specification 1 Number of 1 registers with regs specification 2 Number of registers with regs specification 3 Number of registers with regs specification 4 Number of registers with regs specification 7 Number of registers with regs specification 8 Number of registers with regs specification 9 Number of registers with regs specification 1 0 Number of registers with regs specification 11 Number of registers with regs specification 0 Number of registers with regs specification 1 Number of registers with regs specification 2 Number of registers with regs specification 3 Number of registers with regs specification 4 Number of registers with regs specification 7 Number of registers with regs specification 8 Number of registers with Tegs specification 9 Numbe
134. s5 5 7 6 E 5 u W WIN Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met _ Branch condition met Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met Branch condition met not met _ Branch condition met not met _ Branch condition met not met Branch condition met not met_ Branch condition met not met Branch condition met Appendices SETLB 5 CALL Destination Format Code Lenga Number of sic a r Number of registers with regs specification 0 Number of registers with regs specification 1 Number of registers with regs specification 2 Number of registers with regs specification 3 Number of registers with regs specification 4 Number of registers with regs specification 7 Number of registers with regs specification 8 CAMP NY Ww Number of registers with regs specification 9 Number of registers with regs specification 10 Number of
135. stabilization wait time When recovering from STOP mode 15 888 ms From 4th line to 6th line When recovering from STOP mode is 16 5 MHz Deleted Infig 10 5 2 3 972 to 1016 801 ms In fig 10 5 2 15 888 ms Figure title is added to a figure of section 11 5 2 1 The address of Port 4 Dedicated Output Control Register PASS x 36008084 Register symbol Address The address of Port 4 Dedicated Output Control Register Register symbol PASS Address x 36008048 ITA 20 70 C TA 20 C to 70 133 5 13 3 V 0 165 V Omit is written into the blank spaces on the lines of condition allowance value and unit in the tables between these pages In the Conditions column of item C1 PVdd 3 3 V In the Conditions column of item C1 VDD PVDD 3 3 V Allowable Min Max Symbol Conditions Item Synchronous mode data transfer signal output timing E17 tAD E18 tAHI E25 E26 E27 E28 Allowable Min Max Symbol Conditions Item Synchronous mode data transfer signal output timing E17 4 18 tAHI E25 E26 E27 E28 1 multiply by 4 multiply by 2 n n represents the number of wait states Note m in
136. the access to the contents of RAM that accompanies a tag access requires that the tag access generates a hit In other words when using a way as RAM it is necessary to manipulate the contents of the tag so that the necessary address generates a hit way that is set the mode that does not perform a refill even in the event of a cache miss retains variety of statuses from the moment that the mode was set This is equivalent to locking the cache Even if a cache miss occurs the way is not selected as the target of the refill operation Regarding a way that is used as RAM the contents of the cache cannot be changed by a refill but after disabling the cache an access to the I O space can be used to change the data in the tag array and the data in the data array If all ways are set in the mode that does not perform a refill even in the event of a cache miss set tag data that will definitely result in a cache hit when the cacheable space is accessed With these settings the read data can not be guaranteed in the event of an access to a cacheable space that results in a cache miss The CPU does not stop operating 4 5 4 External Bus Access During Cache Operations Although bus accesses outside of the MN103002A MN103002A YB can be made freely during cache operations if a cache miss occurs external bus access is not possible until the refilling of the cache from external memory and the transfer of data from the cache to external mem
137. the cacheable space consists of instruction data cacheable space in which both instructions and data can be accessed and data only cacheable space in which only data can be accessed Instruction strings can be placed in external memory in either instruction data cacheable space or uncacheable space Data can be stored anywhere in memory and can be referenced via the MOV instruc tion Efficient programming is possible because all addressing modes can be used to access data When using either register indirect with displacement or register indirect with index addressing mode the address pointed to by the base register either Am An or SP the base address and the calculated effec tive address must both be in the same address space either instruction data cacheable space data only cacheable space uncacheable chip space or internal I O space 32 Memory Map Chapter 2 CPU Explanation of the Memory Map The memory map includes a maximum 3 GB of memory spaces from x 00000000 to x BFFFFFFF that can be accessed The space from x 00000000 to x 1FFFFFFF is one cacheable space 512 MB maximum a data only cacheable space in which only data can be accessed The space from x 20000000 10 x 3FFFFFFF is the internal I O space 512 MB maximum which is allocated for the chip s internal ports and various control registers The space from x 40000000 to x 7FFFFFFF is another cacheable space 1 GB maximum an instruction da
138. the in circuit emulator PX ICE103002 0000 0 wait states 0001 1 wait states 0010 2 wait states 0011 3 wait states 0111 7 wait states 0000 0 wait states 0010 2 wait states 0100 4 wait states 0110 6 wait states 14 wait states in odd number of wait states is prohibited DRAM mode is not valid when DRAME is 0 and in the MEMCTRn register is 1 The refresh operation is not performed when DRAME is 0 and REFE is 1 When 0 number of wait states counted by MCLK When 1 number of wait states counted by MCLK 0000 0 wait states 0001 1 wait states 0010 2 wait states 0011 3 wait states 0000 0 wait states 0010 2 wait states 0100 4 wait states 0110 6 wait states 0111 7 wait states 1110 14 wait states Setting an odd number of wait states is prohibited Continued Continued 2 When using the in circuit emulator PX ICE103002 1 When using the emulation function Page mode When FRQ 20 number of wait states counted by MCLK When 1 number of wait states counted by MCLK 0000 Setting prohibited 0000 0 wait states 0001 Setting prohibited 0010 2 wait states 0010 2 wait states 0100 4 wait states 0011 3 wait states 0110 6 wait states 0111 7 wait states 1110 14 wait states Setting an odd number of wait states is prohibited Setting prohibited Setting prohibited Setting p
139. the multiply and accumulate operation is invalid C 0 Always 0 N Undefined Z Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW When ud 03 Dm Dn is operated Dm is ignored The operations of ud 03 imm8 Dn udf03 imm16 Dn and udf03 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases Extension Instruction Specifications 4 1 3 MCST48 Multiply and accumulate operation results 48 bit saturation operation instruction Instruction Format Macro Name MCST48 Dn Assembler Mnemonic udf06 Operation When the 64 bit result of the multiply and accumulate operation that is stored in the multiply and accu mulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 48 bit signed numeric value 0x00007 fffffffff the maximum positive value 0x00007fffffffffffff is output and bits 47 through bits 16 of that output are stored in Dn If the value stored in the multiply and accumulate registers MCRH and MCRL is equal to or less than the maximum negative value for a 48 bit signed numeric value 0x f f 800000000000 the maximum negative value Ox 80000000000 0 is output and bits 47
140. to Programming Cautions of 5 16 The operations of udf04 imm8 Dn udf04 imm16 Dn udf04 imm32 Dn not assured In addition system error interrupt does not occur in these cases viii Following sentences are added to Programming Cautions of SAT24 The operations of ud 05 imm8 Dn udf05 imm16 Dn and udf05 imm32 Dn not assured In addition a system error interrupt does not occur in these cases Instruction Format Macro Name MCST32 MCST16 MCST8 Instruction Format Macro Name MCST Dm Dn MCST imm Dn From Ist line of Operation addition depending on the value of Dm the following operations are performed From Ist line of Operation i In addition depending on the value of Dm imm8 the following operations are performed 1 When the value of Dm is 32 0x00000020 1 When the value of Dm or imm8 is 32 0 00000020 2 When the value of Dm is 16 0x00000010 2 When the value of Dm or imm8 is 16 0x00000010 3 When the value of Dm is 8 0x00000008 3 When the value of Dm or imm8 is 8 0 00000008 4 When the value of Dm is any other value i 4 When the value of Dm or imm8 is any other value i Following sentences are added to Programming Cautions of MCST The operations of udf02 imm16 Dn and udf02 imm32 Dn afe not assured In addition a system error interrupt does not occur in
141. to temporarily store write back data when the data cache is being used in write back mode Data cache memory array way 1 way 0 1111 23 bits 3 i Co ee 4 4 4bytes amp 16 bytes gt 8 8 TAG WB Buffer Data cache address 30 11 4 0 Access space specification address Tag address Entry address Byte address Access space specification address EL meme PERN 0 31 30 11 43 1 Fig 4 3 2 Data Cache Configuration Configuration 6 4 4 4 Description of Registers The cache control register CHCTR stores various settings concerning cache operations as well as some that do not concern cache operations In order to use a cache it is necessary to set the cache control register CHCTR and initialize the cache Writes to the cache control register CHCTR are performed with a one instruction delay In other words the cache control register CHCTR gains control once the instruction that writes to the cache control register CHCTR enters the writing stage in the CPU pipeline This register is mapped at address x 20000070 4 4 1 Cache Control Register Register symbol CHCTR Address x 20000070 Purpose This register sets the operaton of caches 62 maa Bit No 15 3 2 14 13 12 11 10 9 8 7 6 5 DCW DCW ICW ICW INT DC DC IC DC IC
142. to the method set in the DMA control register then the transfer ends when the transfer count set in the transfer word count register reaches Transfer interrupt If a transfer is in progress it is interrupted if a high priority bus request or DMA transfer request is gener ated or a non maskable interrupt is generated For details on priority rankings refer to section 6 4 3 Priority Ranking Description of Operation 151 Chapter 6 DMA Controller 6 4 5 Notes on Programming Notes on setting DMA 1 When enabling DMA complete all of the DMA related settings and wait state bus mode settings before writing a 1 to the DMnTEN bit in the DMA control register 2 The DMA settings and bus mode settings cannot be changed while DMA is running If any of these settings need to be changed write a 0 to the DMnTEN bit in the DMA control register first Notes about DMA for external memory In the case of DMA for external memory areas that span multiple blocks cannot be specified for the transfer source or the transfer destination Notes about intermittent DMA transfer Before operating an intermittent DMA transfer set the registers DMA transfer word count register DMnCNT and DMA intermittent cycle Register DMnCYC to the condition DMA transfer number intermittent cycle x If the numbers of DMA transfer are more than intermittent transfer cycles x N then perform the extra transfer b
143. transmission continues until all of that remaining data has been transferred and then the transmission is interrupted 312 Description of Operation Chapter 12 Ports Chapter 12 Ports 12 1 Overview This microcontroller has a total of 4 I O ports ports 0 to3 built in These ports can all be accessed by programs as internal I O memory space Ports 0 through 2 are 8 bit general purpose input output ports and port 3 is a 2 bit general purpose input output port Each port also has other pin functions as described below The control register within the port can be used to switch between the port function and the other function of each pin Furthermore although not an I O port address output pins A 31 and A 28 26 are also used as chip select signals CS7 through 4 and like an I O port the control register within the port can be used to switch between the two functions of each pin In this manual for convenience sake the dual purpose address output chip select signal pins will be referred to as Port 4 in this manual even though these pins do not constitute an O port Port 0 PO The pins of this port also serve as the data bus signals D 7 0 Port 1 P1 The pins of this port also serve as the data bus signals D 15 8 Port 2 P2 The pins of this port also serve as serial interface input outputs SBTO and SBT1 and timer input outputs TMOIO 210 TM31IO TM4IO TMSIO TM6IOA and TM6IOB
144. upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new resulting cumulative sum back in multiply and accumulate register MCRH and the lower 32 bits in multi ply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Flag Change Condition Flag Change Programming Cautions non extension instruction that consumes at least two cycles must be inserted between this instruction and the next extension instruction 404 Extension Instruction Specifications Appendices MACHU Unsigned half word data multiply and accumulate operation instruction between registers Instruction Format Macro Name MACHU Dm Dn Assembler Mnemonic udf31 Dm Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the contents of Dm unsigned 16 bit integer multiplicand by the contents of Dn unsigned 16 bit integer multiplier adds the upper 32 bits and lower 32 bits of the resulting 64 bit prod uct to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and
145. using one instruction If change the value of TMnBR on counting operation change TMnBR registers simultaneously which are cascaded timers 2 Select clock source Select clock source as the lowest order timer The clock sources of upper order timers are set to cascaded connection example 1 If timer 0 1 are cascaded as 16 bit timer set the clock source of timer 0 set the clock source of timer 1to cascaded connection example 2 If timer 0 1 2 3 are cascaded as 32 bit timer set the clock source of timer 0 set the clock source of timer 1 2 3 to cascaded connection 3 Initialize timer Set all TMnLDE flag in which timers are cascaded then initialize timers no need to set the value to registers simultaneously 4 Permit counting operation Perform one of which listed below due to permit timer counting 1 Start to permit counting operation from upper timer which is cascaded 2 Permit counting all timer which is cascaded simultaneously 5 Stop counting operation Perform one of which listed below due to stop timer counting 1 Start to stop counting operation from lower timer which is cascaded 2 Stop counting all timer which is cascaded simultaneously Description of Operation 219 Chapter 8 8 bit Timers 6 Timer output interrupt Only the timer output or the interrupt request from the highest timer which is cascaded is available The timer output or the interrupt request from the lower timer is out
146. value in the tag field of the instruction fetch address and the valid bit V of that entry has been set to 1 then a hit is said to have occurred in the instruction cache If a hit occurs in the instruction cache the instruction is sent from the corresponding entry line in the data memory section to the CPU Shortage of instructions is prevented with sufficient bandwidth for Bus i e Transfer 64 bits with one access while the process of accessing tag array and instruction fetch requires 2 cycles Furthermore the LRU data is updated simultaneously If a hit occurs in way 0 the LRU data is set to 1 if a hit occurs in way 1 the LRU data is set to 0 EPU COSS MED props bp E T Instruction fetch request Tag address i drda gt tag comparison LRU data update Data address Instruction data bus CAD CBD Instruction buffer low order i Instruction buffer high order Fig 4 5 1 Operation When an Instruction Cache Hit Occurs Description of Operation 65 Chapter 4 Caches 66 Cache Miss Operation If the instruction cache tag array is accessed using the tag entry address field bits 10 to 4 of the instruc tion fetch address as the address and the value in the tag address field TADD of the entry that was accessed does not match the value in the tag field of the instruction fetch address or if they match but the valid bit V
147. x 00 When writing to the serial interface registers first set the I O bus mode to synchronous mode Operation is not guaranteed if the write is performed in asynchronous mode Description of Registers 283 Chapter 11 Serial Interfaces 11 4 1 Serial n Control Register n 0 1 Register symbol SCnCTR Address x 34000800 n 0 x 34000810 n 1 Purpose This register sets the serial interface n operation control conditions Bit No Bit name Description 0 SCnCKO Clock source selection LSB 1 SCnCK1 Clock source selection 2 SCnCK2 Clock source selection MSB 000 1 2 IOCLK valid only in clock synchronous mode 001 1 8 IOCLK 010 1 32 IOCLK 011 1 2 timer 2 timer 3 underflow valid only in clock synchronous mode 100 1 8 timer 0 timer 1 underflow 101 1 8 timer 2 timer 3 underflow 110 1 8 external clock valid only in start stop synchronous mode 111 External clock valid only in clock synchronous mode 3 SCnSTB Stop bit selection valid only in start stop synchronous mode 0 1 bit 1 2 bits SCnPBO Parity bit selection LSB 5 SCnPBI Parity bit selection 6 SCnPB2 Parity bit selection MSB 000 None 001 010 011 Setting prohibited 100 fixed 101 1 fixed 110 Even even number of 1 s 111 Odd odd number of 1 s 7 SCnCLN Character length selection 0 7 bits 1 8 bits Continued 284 Description of Registers Chapter 11 Serial Interfaces Continued Bit No Bit nam
148. 0 One Bus Cycle Transfer Single word Transfer DMR Edge Detection Synchronous Mode 155 One Bus Cycle Transfer Burst Transfer DMR Edge Detection Synchronous Mode 156 One Bus Cycle Transfer Single word Transfer DMR Edge Detection Asynchronous Mode 157 One Bus Cycle Transfer Single word Transfer DMR Edge Detection Asynchronous 158 Two Bus Cycle Transfer Burst Transfer DMR Edge Detection Synchronous Mode 159 Two Bus Cycle Transfer Single word Transfer Serial Reception End 160 5 8 21 5 8 22 5 8 23 5 8 24 5 8 25 5 8 26 5 8 27 5 8 28 5 8 29 5 8 30 5 8 31 5 8 32 5 8 33 5 8 34 5 8 35 6 4 1 6 4 2 6 4 3 6 4 4 6 4 5 6 4 6 6 4 7 6 4 8 6 4 9 32 bit DRAM Page Mode Write Timing When FRQ Chapter 7 Interrupt Controller System 163 Eig 1 3 2 Block Diagram 164 Fig 7 3 3 Block Diagram 2 uo eom 165 Block Diagram st 166 Fig 7 3 5 Block Diagram 167 Chapter 8 8 bit Timers Fig 8 3 1 Timer Connection Dia grain 207 Fig 8 4
149. 0 The number of bits that was set in TM6PM1 and 0 is the number of bits in TM6BC that function as a binary counter Timer 6 initialization flag Initializes timer 6 0 Normal operation 1 Initialize Clears TM6BC so that TM6BC x 0000 When TM6CA and TM6CB are set as a double buffer compare register the value in the buffers is loaded into the compare register Also initializes the pin output Timer 6 enable flag Enable disable the timer 6 counting operation 0 Operation stopped 1 Operation enabled To set 6 1 2 TM6CNE has to be set 0 To set TM6LDE equal to 0 TM6CNE has to be set 1 To set TM6CNE equal to 0 TM6LDE has to be set 1 Operation is not guaranteed when both TM6CNE and TM6LDE are become 1 234 Description of Registers Chapter 9 16 bit Timers 9 6 3 Timer n Base Register n 4 5 Register symbol TMnBR Address x 34001090 n 4 x 34001092 n 5 Purpose This register sets the count cycle for timer n TMn TMn Under the following condition the value in TMnBR is loaded to TMnBC 1 TMnLDE 1 2 When underflow occurs Underflow interrupts are generated whenever TMnBC counts TMnBR value 1 times 9 64 Timer n Binary Counter 4 5 6 Register symbol TMnBC Address 340010 0 n 4 x 340010A2 n 5 340010 4 Purpose This register is the binary counter down counter for timer n The counter value can be read from this register Timer 4 and
150. 000000 Block 64 MB 10000000 45 2 14000000 18000000 16000000 40000000 00000000 External memory 44000000 48000000 4C000000 50000000 54000000 58000000 5c000000 BlockO 64 MB Blocki 64 B k2 64 MB Block3 64 MB 60000000 64000000 68000000 6 000000 70000000 cacheable up to 1 GB 7 000000 uncacheable up to 1 GB A0000000 80000000 84000000 88000000 8 000000 prohibited 90000000 94000000 1 GB 98000000 FFFFFFFF a T 9 000000 BlockO 64 Block 64 MB B kZ 64 ME Block3 64 MB B 4 64 MB Block5 64 MB Block6 64 MB Block7 64 MB C0000000 0000000 000000 8000000 ACO00000 Block1 64 MB Block2 64 MB Block3 64 MB B0000000 Block4 64 MB Internal memory 84000090 Blocks 64 MB _ Space 88099009 Block6 64 MB 000000 Bio CK 64 MB Fig 5 7 2 Space Partitioning Chapter 5 Bus Controller Table 5 7 1 lists the characteristics of each block The settings for each block are made in memory control registers 0 to 7 the register number corresponds with the block number and when DRAM is connected the DRAM control register Table 5 7 1 Characteristics of Each Block DRAM Number of wait Block connection i Bus access style states Mode Output signal Synchronous Block O Not permitted Fixed wait 1 31 aconch
151. 008064 Purpose This register sets the input output direction of the port 2 pins 0 input pin 1 output pin 12 4 2 5 Port 2 Pin Register Register symbol P2IN Address x 36008084 Purpose This register is used to read the value of the port 2 pins mw T7 T LAT TD P27I 261 P251 P24I P23I P221 P1211 201 name Aes R 8 328 Pot2 Chapter 12 I O Ports 12 4 3 Pin Configuration Table 12 4 1 shows the pin configuration of port 2 Table 12 4 1 Port 2 Configuration Port P2nM 1 P2nM 0 P2nS 1 P2nS 0 P2n P2nD 1 P2nD 0 P2nD 1 P2nD 0 pies P20 e TMOIO Timer 0 TMOIO Timer 0 SBTO Serial 0 transfer clock output input input output P2nD invalid p21 Timer 1 Timer 1 SBT1 Serial 1 transfer clock output input input output P2nD invalid P22 Timer2 TM2IO Timer 2 output input P23 TMS3IO Timer 3 TM3IO Timer 3 output port output input P24 General purpose TM4IO Timer 4 TM4IO Timer4 output port output input P25 General purpo TMSIO 5 5 Timer 5 output port output input P26 General purpose TM6IOA Timer 6 TM6IOA Timer 6 output port output input P27 General purpose TM6IOB Timer 6 TM6IOB Timer 6 output port output input After a reset Port 2 329 Chapter 12 Ports 12 5 Port 3 12
152. 0401 0 353 Table 13 4 7 AC Characteristics 7 00 0000022 600 teret teretes 354 Table 13 4 8 AC Characteristics 8 356 Table 13 4 9 AC Characteristics 9 358 Table 13 4 10 AC Characteristics 10 n 359 Table 13 4 11 AC Characteristics 11 1 361 Table 13 4 12 AC Characteristics 2 362 Table 13 4 13 AC Characteristics 13 tette tette 363 Table 13 4 14 AC Characteristics 14 22 2 0 0220 01 2 00 creed 365 Table 13 4 15 AC Characteristics 15 1 tte tette et etel 366 xxi Appendices Table A 1 Treatment OF Ps et eoru at ctae a s te E cR ru e 370 Table B 1 Operating Status of External Pins Concerning 371 Table C 1 Register Map 1 50 reote bota tee pd dea 372 Table E 1 List of Notes xxii Chapter 1 General Chapter 1 General 1 1 Overview The 103002 is 32 bit microcontroller geared towards the development of C programming development that offers ease of use and excellent cost performance with a simple and high performance architecture Built around a compact 32 bit CPU core with a basic instruction word length of one byte this microcontroller includes an instruction cache data cache bus control circuit interrupt control circuit timers serial interfaces DMAC A D
153. 1 Clear to Send signal input serial interface 2 only 10 Pin Descriptions Chapter 1 General Pin function Event count input toggle output dual use UO TM2IO TMS3IO 16 bit timers TM4IO TMSIO TM6IOA TM6IOB Interrupts NMIRQ E IRQ7 Watchdog WDOVF DMAC DMR3 Event count input toggle output dual use Category Pinname Number of pins 8 bit timers TMOIO IO Event count input toggle output dual use Event count input toggle output dual use Event count input toggle output dual use Event count input toggle output dual use Capture input PWM output Event count capture input PWM output External non maskable interrupt signal input External interrupt signal inputs Watchdog overflow output Direct memory access transfer request inputs Direct memory access transfer acknowledge outputs 8 bit O port dual use with DO through D7 P10 P17 Port 1 8 bit I O port dual use with D8 through D15 Port 2 8 bit I O port dual use with TMOIO through TM6IOA and B Port 3 2 bit I O port dual use with SBOO and SBO1 Pin Descriptions 1 Chapter 1 General 12 Pin Descriptions Chapter 2 CPU Chapter 2 CPU 2 1 Overview Structure Load store architecture 9 registers Data registers 32 bit x 4 address registers 32 bit x 4 S
154. 1 When TMnLDE 1 2 When timer underflow is occurred Whenever TMnBC counts the value of resisted value of TMnBR 4 1 TMnBC become undeflow then occurs the request of underflow interrupt 212 Description of Registers Chapter 8 8 bit Timers 8 6 3 Timer n Binary Counter n 0 1 2 3 Register symbol TMnBC Address x 34001020 n 0 x 34001021 n 1 x 34001022 2 x 34001023 3 Purpose This register is the binary counter down counter for timer n The counter value can be read from this register It is down counter Whenever TMnBC counts the value of the value of TMnBR 4 1 TMnBC become undeflow then occurs the request of underflow interrupt 8 6 4 Prescaler Control Register Register symbol TMPSCNT Address x 34001071 Purpose This register controls the prescaler opreation Bit No Bit name When reset Access Bit No Bit name Description 0to 6 n Always returns 0 7 TMPSCNE Prescaler operation enable flag Enables disables operation of the 1 8 IOCLK and 1 32 IOCLK prescaler 0 Operation disabled 1 Operation enabled Description of Registers 213 Chapter 8 8 bit Timers 8 7 Description of Operation 8 7 1 Interval Timer Timer Output While use 8 bit timer as interval timer set as follows Then operate as interval timer which occurs the interrupt signal with every setting cycle refer to figure8 7 1 figure8 7 2 figure8 7 3 If t
155. 1 Timer Configuration Diagram ssscssscssssssssssssssssessssssssssescesesstessecsessruessussnssaussescesseseevons 208 Fig 8 7 1 Interval Timer Operation cssccsescssscsessssssossssssoesssecsssssucssssasetssessnscruscaeesnsssasssuccusssasseascassoens 215 Fig 8 7 2 Interval Timer Operation When Clock Source IOCLK 2 216 Fig 8 7 3 Interval Timer Operation When Use Prescaler csscssessssssssssssssesessessessessesscsusaucsccarssseese 216 Fig 8 7 4 Event Counting Operation Ee D a oet beet dens 218 Fig 8 7 5 Cascaded CODDEGfODo ca ese cope EO pam m es 218 Fig 8 7 6 Operation of Timer 0 and 1 1 stt tete 220 Fig 8 7 7 Operation of Timer 0 1 2 secat tec t poe 221 Chapter 9 16 bit Timers Fig 9 3 1 16 bit Timer Connection Diagram cccssssssessssssessssssssssssssssusssseeseresecsasessesaussssssuccsseccasees 226 Fig 9 4 1 16 bit Timer Block Diagram Timer 4 9 ees 227 9 4 2 16 bit Timer Block Diagram Timer 6 sse 227 Fig 9 4 3 Timer 6 Compare Capture Register Block Diagram etes 228 9 4 4 PWM Output Section tenter tete ttes 228 Fig 9 7 1 Interval Timer Operation dts e opes 242 Fig 9 7 2 Interval Timer Operation When Clock Source 242
156. 2 42 82 VREFSV D14 P16 3 A2 43 IRQ2 83 OSCO D13 P15 4 44 IRQ3 84 OSCI 212 14 5 VSS 45 IRO4 85 SYSCLK 6 A4 46 IRQS 86 vss 211 13 7 5 47 IRQ6 87 DMK3 D10 P12 8 6 48 IRQ7 88 DMR3 D9 P11 9 7 49 VSS 39 DMK2 129 D8 P10 10 VDD 50 NMIRQ 90 DMR2 130 VSS 11 51 CSO 91 131 D7 P07 12 A9 52 RASI CSI DMRI 132 D6 P06 13 10 53 RAS2 CS2 133 05 05 14 54 RAS3 CS3 DMRO 134 04 04 15 VSS 55 135 VDD 16 A12 031 136 D3 P03 17 A13 57 CASI D30 137 2 02 18 14 58 CAS2 D29 138 DI1 POI 19 A15 59 CAS3 D28 139 DO P00 20 VDD 60 VSS VSS 140 VSS 21 16 WE D27 141 RST 22 62 WEI D26 142 TMGIOB P27 23 18 63 WE2 D25 143 TM6IOA P26 24 19 24 144 5 P25 25 VSS 65 VDD 145 P24 26 A20 66 NC D23 146 VDD 27 A21 67 RE D22 TM3IO P23 28 A22 68 RD WT D21 148 2 P22 29 A23 69 SIZEO D20 149 TMIIO SBTI P21 30 vDD 70 SIZEI 110 vss 150 TMOIO SBTO P20 31 A24 71 VSS 111 D19 ps VSS 32 A25 72 DK 112 D18 152 CTS 33 A26 CS4 RASA 73 NC 113 DI7 153 SBT2 34 27 5 74 PULL UP 114 016 154 SBO2 35 vss 75 BG 115 VDD iss SBI2 36 A28 CS6 76 BR 116 BMODE 156 SBO1 P31 37 29 77 WDOVF 117 MMODE 157 SBII 38 A30 78 FRQS 118 DSCLK 158 P30 39 A31 CS7 PVDD 119
157. 2 5 Memory Control Register 4 Register symbol MEMCTR4 Address x 32000028 Purpose Sets the bus mode and the number of wait states to be inserted for external memory space block 4 Bit No Bit name Description 0 B4DRAM Block 4 DRAM space setting 0 Do not use this block as a DRAM space 1 Use this block as a DRAM space B4WM Block 4 wait mode mi 0 Fixed wait state insertion 1 Handshaking 2 Block 4 bus mode 0 Synchronous mode synchronized with SYSCLK 1 Asynchronous mode synchronized with MCLK 5 B4BW Block 4 bus width 0 16 bits 1 32 bits 6 B4CAS Block 4 DRAM byte specification 0 Specified by WE3 to 0 1 Specified by CAS3 to 0 8 B4WCo Number of block 4 wait state insertions LSB 9 BAWCI Number of block 4 wait state insertions 10 BAWC2 Number of block 4 wait state insertions 11 B4WC3 Number of block 4 wait state insertions 12 Number of block 4 wait state insertions MSB After reset mode is released block 4 is set to synchronous mode with 15 wait states and the bus width is 32 bits When using block 4 as a DRAM space the number of wait states is as indicated by the setting of the WC bit in the DRAM control register However even when using block 4 as a DRAM space be sure not to set a prohibited value in BAWCA to 0 The number of wait states that are inserted is the same as set in bits BOWC4 to 0 Refer to the description of memory control register 0 Descript
158. 2 IOCLK that is used by 8 bit timers 240 Description of Registers Chapter 9 16 bit Timers 9 7 Description of Operation 9 7 1 Timers 4 and 5 Timer 4 and 5 have internal register for initialization and down counter Available as both interval timer and event counter 9 7 1 1 Interval Timer Timer Output Use following setting for the case that timer 4 5 is used as a interval timer Each timer works as interval timer to generate an interrupts at the specified cycle Refer to figure 9 7 1 9 7 2 9 7 3 Please refer cascaded connection at section 9 7 1 3 to use them as a 32 bit timer by cascading Steps for start up 1 Set the division ratio Give division ratio into TMnBR The interrupting cycle TMnBR value 1 X clock source cycle 2 Select clock source Give clock source into TMnCK 2 0 of TMnMD register To use 1 8 IOCLK or 1 32 IOCLK as a clock source allow the prescaler operation by setting 1 for TMPSCNE of TMPSCNT before the permission of the counter operation of Timer 4 5 3 Timer initialization Initialize timer n by setting 1 into TMnLDE of TMnMD register Timer output is reset by loading TMnBR value into TMnBC as initial value Must switch to the normal operation mode by setting 0 into TMnLDE just after the initialization 4 port setting case of using the timer output Set output for IO port by handling I O port register Please refer the chapter of I O port for register setting 5 Allow count operat
159. 2 bit boundary is prohibited the SP value must always be set to a multiple of four Therefore as shown in Fig 2 7 7 the stack frame is allocated so that the value of the SP is always a multiple of four As a result the six bytes of information are saved to an eight byte area Smaller address SP after interrupt 1 i SP before interrupt Fig 2 7 7 Stack Frame Configuration 46 Interrupt Functions Chapter 2 CPU 2 8 Operating Modes 2 8 1 Overview The MN103002A MN103002A YB has three basic operating modes In order to support low power consumption this microcontroller is equipped with switching control functions that start stop oscillation and start stop the CPU and peripheral circuits Reset mode RESET Normal operating mode NORMAL Low power consumption modes Stop mode STOP Halt mode HALT Sleep mode SLEEP 1 No matter which state the microcontroller is in a reset always returns the microcontroller to the normal operating mode RESET Reset Y Oscillating Oscillating Interrupt Oscillating Interrupt stopped NORMAL Oscilating Program Interrupt Program Halt mode Sleep mode Stop mode CPU peripheral CPU stopped peripheral CPU stopped peripheral circuits stopped circuits operating circuits stopped C_D Indicates a mode in which both the CPU and the peripheral circuits are operating Indicates a mode in which
160. 2 bits of the new resulting cumulative sum back in multiply and ccumulate register MCRH and the lower 32 bits in multi ply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Condition Programming Cautions A non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction The operations of udfu31 imm32 Dn is not assured In addition a system error interrupt does not occur in these cases 406 Extension Instruction Specifications Appendices MACBU Unsigned byte data multiply and accumulate operation instruction between registers Instruction Format Macro Name MACBU Dm Dn Assembler Mnemonic udf33 Dm Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the contents of Dm unsigned 8 bit integer multiplicand by the contents of Dn unsigned 8 bit integer multiplier adds the resulting product to the 32 bit cumulative sum that is stored in the multiply and accumulate register MCRL and then stores the new resulting 32 bit cumulative sum back in multiply and accumulate register MCRL If an overflow from the 32 bit cumulative sum data
161. 2345677 x 12345678 1 The lower half TM4BR has value x 5677 and the upper half TM5BR has value x 1234 Since 32 bit access is available TM4BR and TMSBR can be set by one instruction simultaneously To change the TMnBR value during the counter operation please change them by one instruction simul taneously 2 Select clock source Set the specified clock source into the lower half of timer Timer 4 Set the cascaded connection for clock source into the upper half of timer Timer 5 3 Initialization of the timer Initializing can be done by set 1 to TMnLDE flag of both timer 4 5 It s not necessary to done setting for timer 4 5 simultaneously 4 Permission for the count operation To permit please use one the following step 1 First give count operation permission to upper half Timer 5 then give permission to the lower half Timer 4 2 Give permission to Timer 4 amp 5 simultaneously 5 Termination of count operation For operation termination please use one of the following 1 First terminate count operation of the lower half Timer 4 then do same for upper half Timer 5 2 Terminate both Timer 4 5 simultaneously 6 Timer output and Interruption Timer output and interruption is available only for the upper half of the timer Timer 5 Timer output and interruption to for the lower half Timer 4 is out of the guarantee Description of Operation 245 Chapter 9 16 bit Timers Fig 9 7 5 shows the op
162. 3 7951 6601 60 3 7954 5968 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2002 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang MALAYSIA Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 GO Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 OG Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division of Matsushita Electric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 Sales Office National Panasonic India Ltd E Block 510 International Trade Tower Nehru Place New Delhi 110019 INDIA Tel 91 11 629 2870 91 11 629 2877 Oe Indonesia Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 62 21 801 5675 GO China Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin C
163. 4 3 2 1 0 IVARn Fig 2 7 4 Interrupt Vector Register For details on how to select the upper 16 bits of the start address refer to section 4 4 1 Cache Control Register Interrupt Functions 39 Chapter 2 CPU 2 7 3 Interrupt Types 2 7 3 1 Reset Interrupt The reset interrupt has the highest priority level and is generated by setting the RST pin low A reset interrupt causes the registers etc to be initialized If the reset pin goes high the microcontroller waits until the oscillation of the internal clock stabilizes and then begins executing program instructions starting from address x 40000000 2 7 3 2 Non maskable Interrupts Nonmaskable interrupts are accepted regardless of the values of the interrupt enable flag and the interrupt mask IM2 to IMO in the PSW Non maskable interrupt sources are the external pin non maskable interrupt source the watchdog timer overflow interrupt source and the system error interrupt source When a nonmaskable interrupt is accepted control transfers to an interrupt handler that starts at address x 40000008 The interrupt handler accesses NMICR to analyze the source of the interrupt performs the interrupt processing cancels the interrupt source and then returns to the normal program using the RTI instruction External pin non maskable interrupts An external nonmaskable interrupt is generated when the NMIRQ pin goes low If an external
164. 4 TM6ACE Timer 6 capture A operation enable flag Enables disables caputure operation for TM6CA 0 Disables caputure operation Pin input is ignored 1 Enables caputure operation 5 TM6AEG Timer 6 A pin polarity selection flag Selects the valid edge for the input on the TM6IOA pin and the output polarity 0 Rising edge valid Positive polarity output Reset L level set H level 1 Falling edge valid Negative polarity output Reset H level set L level 6 TM6AMO Timer 6 compare capture A operating mode setting flag LSB 7 TM6AMI Timer 6 compare capture A operating mode setting flag MSB These bits set the TM6CA operating mode 00 Compare register single buffer 01 Compare register double buffer 10 Capture register single edge operation 11 Capture register dual edge operation When dual edge capture mode is set the setting of TM6AEG is ignored 236 Description of Registers Chapter 9 16 bit Timers 9 6 6 Timer 6 Compare Capture B Mode Register Register symbol TM6MDB Address x 340010B5 Purpose This register sets the operation control conditions for the compare capture register B for timer 6 Bit No Bit name Description 0 TM6BOO Timer 6B output waveform selection flag LSB 1 TM6BOI Timer 6B output waveform selection flag 2 TM6BO2 Timer 6B output waveform selection flag MSB These bits select the waveform that is output to the TM6IOB pin 000 Set when TM6BC matchs TM6CB reset when TM6BC mat
165. 4 of an IOCLK cycle 1MCLK in the no wait states example or after 1 2 IOCLK 2 cycle in the one wait state example the data strobe signals DS3 to 0 are asserted and the I O side begins to drive the data on the data bus During a write the address IOA11 to 0 and the write request signal WR are output in synchronization with the falling edge of IOCLK after 1 4 of an IOCLK cycle 1MCLK in the no wait states example or after 1 2 IOCLK 2MCLK cycle in the one wait state example the data strobe signals DS3 to 0 are asserted and are then negated 1 4 of an IOCLK cycle IMCLK before the end of the I O access cycle The write is performed at the rising edge of the DS3 to 0 signals Note that in the case of a normal internal I O circuit the bus cycle is completed with the number of wait states 0 or 1 IOCLK cycles set by the IOWC bits in the I O bus control register but in the case of the port only the bus cycle is completed at the number of wait states 0 to 3 IOCLK cycles set by the IOPWC bits in the I O bus control register 106 Description of Operation Chapter 5 Bus Controller 5 8 3 2 Asynchronous Mode Access Asynchronous mode access is provided in order to permit high speed access of the internal I O space In order to perform an asynchronous mode access set the IOBM bit in the I O bus control register IOCTR Once the IOBM bit is set all I O accesses are conducted in synchronization with the MC
166. 5 Fig 13 4 3 System Clock Timing tede indc 347 Fig 13 4 4 Synchronous Mode Data Transfer Signal Timing represents the number of wait 2 2 2 44 4160 350 Fig 13 4 5 Asynchronous Mode Data Transfer Signal Timing eee 352 Fig 13 4 6 DRAM Mode Data Transfer Signal 355 Fig 13 4 7 DRAM Page Mode Data Transfer Signal Timing 357 Fig 13 4 8 DRAM Refresh Signal Timing ccccccscscsssessssssssssssessssssessscsucsnecsucsessuecuessucasesseceesssessvees 358 Fig 13 4 9 Bus Request Signal Timing 1 ssssssssssscsssesssesssssssssscssessessesseocesesseaesecsaessecsecseccaezses 360 Fig 13 4 10 Bus Request Signal Timing 2 Refresh request generation when bus authority is released 360 Fig 13 4 11 DMA Request Input Timing in DMR edge detection 361 Fig 13 4 12 DMA Output Timing in internal multiply by 4 bus wait state synchronous mode 362 Fig 134 13 Interrupt Signal Timing rep cti e utc 363 Fig 13 4 14 Timer Counter Input Signal Timing essere 364 Fig 13 4 15 Timer Counter Output Signal Timing 364 Fig 13 4 16 Watchdog Overflow Output 002022022222 222000200
167. 5 2 3 Transmission Interruption Function Bits 2 and 8 of SC2CTR can be used to interrupt and resume a transmission through the status of the CTS pin A transmission is interrupted by the end of the transmission by a transmission buffer empty interrupt or by mask ing the DMA request signal Note that when controlling the transmission through the CTS pin writing data to the transfer buffer while the interrupt signal or DMA request signal is masked is prohibited 11 5 2 4 Notes on Use 1 When using serial interface 2 set SC2CTR before setting the other registers and do not change the SCOCTR setting while transmission reception is in progress or while there is data in the transmission buffer Operation is not guaranteed if the settings are changed under such circumstances 2 Before writing to SC2TXB confirm that the transmission buffer is empty by checking bit 5 of SC2STR or else set bit 4 of SC2ICR to 1 and then write to SC2TXB during the interrupt processing 3 Seta value of 16 or greater in SC2TIM 4 When using an external clock via the SBT2 pin use an input clock that has a high and low pulse width that is at least twice as long as the IOCLK cycle 5 The transmission interruption function through the CTS pin does not disable the actual transmission operation Therefore if there is any data remaining in the transmission buffer or the transmission shift register when a transmission was interrupted through the CTS pin the
168. 63 7 3 2 Interrupt Source Assignments 164 Description of Registers 168 7 4 1 Non maskable Interrupt Control 169 7 4 2 Group n Interrupt Control Registers GnICR n 2 to 30 170 7 4 2 1 Group 2 Interrupt Control Register ee 172 7 4 2 2 Group 3 Interrupt Control Register esses 173 7 4 2 3 Group 4 Interrupt Control Register 2 174 7 4 2 4 Group 5 Interrupt Control Register sees 175 7 4 2 5 Group 6 Interrupt Control Register 176 7 4 2 6 Group 7 Interrupt Control Register 177 7 4 2 7 Group 8 Interrupt Control Register 178 7 4 28 Group 9 Interrupt Control Register 179 7 4 2 9 Group 10 Interrupt Control Register 180 7 4 2 10 Group 12 Interrupt Control Register 2 181 7 4 2 11 Group 13 Interrupt Control Register 182 7 4 2 12 Group 14 Interrupt Control Register 20 183 7 4 2 13 Group 15 Interrupt Control Register 184 7 4 2 14 Group 16 Interrupt Control Register 185 7 4 2 15 Group 17 Interrupt Control Register
169. 7 2 6 Interval Timer Please take the following steps to use timer 6 as an interval timer Timer 6 works as interval timer generate interrupt of compare capture register A with specified cycle fig 9 7 16 17 Compare capture register B is available as either of compare register or capture register Please refer section 9 7 2 1 for compare register setting and section 9 7 2 2 for capture register setting Steps for start up 1 Setting mode of compare capture register A Setting for TM6MDA register TM6A0O2 1 0 optional TM6ACE 0 TMAEG optional TM6AM1 0 00 01 2 Set the division ratio Give division ratio into TM6CA Inhibit capture operation Compare register single buffer or Compare register double buffer Must use double buffer if interrupt cycle is changed during the count operation Interrupt cycle of compare capture register A value in TM6CA 1 X clock source cycle 3 Setting for operation mode Setting of TM6MD register TM6CK2 1 0 optional Select clock source TM6CAE 1 Clear TM6BC if TM6BC matches with TM6CA TM6ONE 0 Inhibit one shot operation 0 Inhibit starting up of timer by external trigger TM6PM1 0 optional No effects to operation TM6PME 0 Select normal wave TM6LDE 0 Normal operation TM6CNE 0 Terminate count operation 256 Description of Operation Permit prescaler operation setting 1 into TMPSCNE of TMPSCNT register before the permission
170. 72 Chapter 7 Interrupt Controller 7 4 2 3 Group 4 Interrupt Control Register G4ICR Address x 34000110 Register symbol This register is used to enable group 4 interrupts and to confirm interrupt requests and detection When reset Bit No Bit name Description 0 TM2ID Timer 2 underflow interrupt detection flag 0 No underflow interrupt detected 1 Underflow interrupt detected 1to3 Always returns 0 4 TM2IR Timer 2 underflow interrupt request flag 0 No underflow interrupt requested 1 Underflow interrupt requested 5107 Always returns 0 8 TM2IE Timer 2 underflow interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 GALVO Group 4 interrupt priority level register LSB 13 G4LV1 Group 4 interrupt priority level register 14 G4LV2 Group 4 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 174 Description of Registers Chapter 7 Interrupt Controller 7 4 2 4 Group 5 Interrupt Control Register Register symbol GSICR Address x 34000114 Purpose This register is used to enable group 5 interrupts and to confirm interrupt requests and detection When reset Access Bit No Bit name Description 0 TM3ID Timer 3 underflow interrupt detection flag 0 No underflow interrupt detected 1 Underflow interrupt detected 1to3 Always returns 0 4 Timer 3 underflow interrupt request flag 0 No underf
171. 858 715 5545 Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 CANADA Tel 1 905 238 2101 Fax 1 905 238 2414 LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 335 9000 55 12 331 3789 EUROPE U K Sales Office Panasonic Industrial Europe Ltd PIEL Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Germany Sales Office Panasonic Industrial Europe GmbH PIEG Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE 65 390 3688 Fax 65 390 3689 e Malaysia Sales Office Panasonic Industrial Company Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60
172. 8IOCLK 1 32IOCLK underflow of timer 0 1 2 External clock count rise edge of input pins Cascaded connection By cascading timer 0 3 they can be used as pure 16 24 32 bit timers Interrupt When timer underflow occurs an interrupt is generated Timer output One half of cycle for timer under flow is possible as output Generation of reference clock for serial interface timer 0 1 2 3 Generation of reference clock for UART timer 0 1 2 3 DMA can be started up when an interrupt request is generated timer 2 3 206 Overview Features 8 3 System Configuration 8 bit Timer Connection Diagram Chapter 8 8 bit Timers Prescaler TMPSCNT Prescaler control register IOCLK port block 2 2 TMIIO Timer interrupt 0 Clock source for 16 bit timer Timer 0 Serial I F 0 a detection Timer interrupt 1 Clock source for 16 bit timer eH Serial I F 1 Timer interrupt 2 Clock source for 16 bit timer 1 Timer 2 Serial I F 0 2 TM2IN6 TM2CLK TM2IN7 Timer interrupt 3 Serial I F 1 2 Timer 3 Edge detection Make the output signal and input output setting n the I O port control Fig 8 3 1 Timer Connection Diagram System Configuration 207 Chapter 8 8 bit Timers 8 4
173. AC 4 WDT 1 system error 1 Timers Four 8 bit timers all are down counters Cascaded connection possible permits use as 16 24 32 bit timer Timer output possible duty ratio 1 1 Internal clock source or external clock source can be selected Can be selected as serial interface clocks Two 16 bit timers 2 down counters Cascaded connection possible permits use as 32 bit timer Timer output possible duty ratio 1 1 Internal clock source or external clock source can be selected One 16 bit timer up counter Internal clock source or external clock source can be selected Input capture function rising edge falling edge or both edges can be selected Various PWM generation functions two internal compare and capture registers One watchdog timer Serial interface Two UART synchronous dual use channels One UART with CTS control channel DMAC Number of channels 4 channels Unit of transfer 8 16 32 bits Maximum transfer count 65536 transfers Initiation sources External requests various interrupts software Transfer format Two bus cycle transfers one bus cycle transfer Transfer modes One word transfer burst transfer intermittent transfer Addressing modes Fixed increment decrement can be specified for the source and the destination separately Incrementation decrementation are performed automatically in accordance with the transfer units Inputoutput ports 26 all dual purpose Packa
174. Block Diagram 8 bit Timer Block Diagram Timer n 0 1 2 3 TMnINO TMnIN1 TMnIN2 TMnIN3 TMnIN4 e p TMnCLK TMnINS Clock output TMnIN6 TMnIN7 TMnBR Base register TMnCI Cascaded signal from higher order timer Count operation enabled gt TMnCO Cascaded signal TMnIRQ Underflow interrupt TMnMD gt TMnOUT Mode register Timer output Reset Fig 8 4 1 Timer Configuration Diagram 208 Block Diagram Chapter 8 8 bit Timers 8 5 List of Functions 8 bit Timer Function Chart Table 8 5 1 Function Chart TimerO Timer1 Timer2 Timer 3 Interval timer Event counter Timer output Interruput Initiation source of DMA 16 bit timer source Reference clock for serial I F 0 Reference clock for serial I F 1 Reference clock for serial I F 2 Cascaded connection List of Functions 200 Chapter 8 8 bit Timers 8 6 Description of Registers Table 8 6 1 List of 8 bit Timer Registers address Name Symbol Number of bits Initial value Access size x 34001000 Timer 0 mode register TMOMD 8 8 16 32 x 34001001 Timer 1 mode register TMIMD 8 x34001002 Timer 2 mode register TM2MD 8 16 34001003 Timer 3 mode register TM3MD 8 x34001010 Timer 0 base register TMOBR 8 16 32 x34001011 Timer 1 base register TMIBR 8 34001012 Timer 2 base register TM2BR
175. BnBW 1 to 0 bit in the memory control registers for blocks 1 to 7 Figs 5 8 7 and 5 8 8 are timing charts for accesses with a 16 bit bus in synchronous mode with fixed wait state insertion In Fig 5 8 7 one wait state is inserted while in Fig 5 8 8 two wait states are inserted In 16 bit bus mode a word access 32 bits is performed through two external accesses one for the lower half word A 1 0 and one for the upper half word 1 1 In the case of a half word access 16 bits or a byte access 8 bits the access is performed through only one external access of the corresponding address The most significant 16 bits D31 to 16 of the data bus are used When writing byte 0 and byte 2 WE2 is asserted and the data is output on D23 to 16 When writing byte 1 and byte 3 WE3 is asserted and the data is output on D31 to 24 gg 1 0 e D31 16 RD WT Eoin 51281 0 1 wait ok 1 wait ok 1 wait ok 1 wait ok Lower half Upper half word Lower half word Upper half word word read cycle read cycle write cycle write cycle Fig 5 8 7 Timing for Access in 16 bit Bus Synchronous Mode with Fixed Wait State Insertion One Wait OK Description of Operation 1 1 1 Chapter 5 Bus Controller secre ppp esp eem EL ST A31 0 V Xp ae
176. C SC2 Bit SC2 SC2 name TIM6 5 TIM4 TIM3 TIM2 TIMI TIMO e The cycle is the value set in the register 1 11 5 Description of Operation 11 5 1 Serial Interfaces 0 and 1 11 5 1 1 Connection Clock synchronous mode gt Two different connection methods are possible one for unidirectional transfer and the other for bi direc tional transfer When the SBTn pin is an output only during transmission SCnTOE 0 it is necessary to pull up the SBTn pin In addition when using the SBOn pin as a data input output SCnMD1 and 0 11 it is necessary to pull up the SBOn pin Connect pull up resistors externally When using the SBOn pin as a data output and the SBIn pin as a data input SCnMDI and 0 01 the SBOn is always an output and the SBIn pin is always an input When using the SBOn pin as a data input output SCnMDI and 0 11 the SBOn is an output only during transmission and is normally an input When SCnTOE is 0 the SBTn pin is an output only during transmission under the internal clock and is normally an input Furthermore when SCnTOE is 1 the SBTn pin is always an output when the internal clock is selected 294 Description of Registers Description of Operation Chapter 11 Serial Interfaces SBTn SBTn Transmitter Receiver Unidirectional transfer SBTn Transmitter Receiver Bi directional transfer
177. Cache Hit Operation If data is read from a cacheable space x 00000000 tox 1FFFFFFF or x 40000000 to x 7FFFFFFF while the data cache is enabled the data cache tag array is accessed using the tag entry address field bits 10 to 4 of the data address as the address If the value in the tag address field TADD of the entry that was accessed matches the value in the tag field of the data address and the valid bit V of that entry has been set to 1 then a hit is said to have occurred when reading the data cache If a hit occurs when reading the data cache the data is sent from the corresponding entry line in the data memory section to the CPU Because tag array accesses and data reads are each performed in one cycle in pipeline fashion then as long as the read accesses keep hitting consecutive reads can be executed each cycle without any waits CPU clock MCLK DEC stage EX stage Tag address Tag comparison A Tag comparison B stage Data address Data read bus WB stage Fig 4 5 4 Operation When a Data Cache Read Hit Occurs Description of Operation 69 Chapter 4 70 Cache Miss Operation If the data cache tag array is accessed using the tag entry address field bits 10 to 4 of the data address as the address and the value in the tag address field TADD of the accessed entry does not match the value in the tag field
178. Control Registers Omit CPU Pipeline Control Register was deleted Figure title is added to a figure of section 2 5 1 Addressing mode d8 d8 An 48 is sign extended 1 416 d8 1 idl6is sign extended 932 Am d8 Register indirect with displacement X Addressing mode Ag 48 48 i d8 is sign extended d16 Am d16 idl6is sign extended Register indirect with displacement ad In the Sign extension column of the transfer instructions EXT EXTB EXTBU EXTH EXT In the Sign extension column of the transfer instructions EXT EXTB EXTBU EXTH EXTHU Note Interrupts are prohibited and the bus is locked occupied by the CPU when BSET or BCLR is being executed A proviso is added to the left mentioned Note From 8th line to 9th line of Explanation of the Memory Map Note that operation is not guaranteed when accessing an unmounted space such as when accessing an internal I O space which no control register has been allocated i From 8th line to 9th line of Explanation of the Memory Map Note that the unmounted space access is prohibited such as access to the internal space without a control register The operation is not assured Reset interrupt NMI interrupts Level interrupt n n 0 to 6 Highest priority ranking Lowest pri
179. DST n 0 1 2 3 Address x 32000108 n 0 x 32000208 n 1 32000408 n 2 x 32000808 n 3 Purpose These registers set the transfer destination address for DMA channels 0 to 3 Bit D DMn DMn DMn DMn DMn DMn DMn DMn DMn DA30 DA29 DA28 DA27 DA26 DA25 DA24 DA23 DA22 gt EIN EN Bit DMn DMn DMn DMn DMa DMn DMn 14 DA13 DA12 DAIO DA9 DA7 DA6 DAS DA4 DA2 Mesi x x Dx During DMA transfer this register shows the next transfer destination address When the transfer desti E E B Ed nation is an external device that supports the acknowledge function and one bus cycle transfer mode is in effect the contents of DMnDST are ignored The transfer address that is set should conform with a 1 byte boundary 8 bits 2 byte boundary 16 bits or 4 byte boundary 32 bits depending on the transfer byte unit Description of DMA Registers 147 Chapter 6 Controller 6 3 4 Transfer Word Count Registers Register symbol DMnCNT 0 1 2 3 Address x 3200010C 0 x 3200020C 1 x 3200040C n 2 x 3200080C n3 Purpose These registers set the transfer word count for DMA channels 0 to 3 Bit position Bit name D
180. EX stage Tag address MEM stage Data address Data read bus Data write bus save Missed data cache write Refill data cache write WB stage Fig 4 5 8 Operation When a Data Cache Write Miss Occurs Write back Mode Description of Operation 73 Chapter 4 Caches If the dirty bit D in the entry that was accessed is set i e 1 then after the refill is completed the external bus access for the write back is initiated and the data that was saved in the write back buffer is written to external memory This operation maintains the consistency of the data in the data cache versus the data in the external memory In the data cache way operation mode settings if both ways are set to make no refill even if a cache miss occurs the write operation is not performed and the CPU executes the next instruction Write through Mode When using the data cache in write through mode use one of the methods shown below a 1 Using the data cache as 4 KB cache system Casel If the stack is located whithin the uncachable space a Before any access to the IO space x 20000000 to x 3FFFFFFF execute the instruction that reads from the uncachable space x 80000000 to x BFFFFFFF Case2 If the stack is located within the cachable space a Before any access to the IO space x 20000000 to x 3FFFFFFF execute the instruction that reads from an uncachable space x 80000000 to x BFFFFFFF
181. Fig 11 5 8 Timing Chart 5 Two byte transfer with 7 bit data length parity on and 1 stop bit SBO pin ors ee Fr pes SP Data write SCnTXF flag SCnTBF flag Interrupt request when set to transmission end Interrupt DMA request A when set to transmis sion buffer empty Fig 11 5 9 Timing Chart 6 302 Description of Operation Chapter 11 Serial Interfaces When transmission is enabled transmission starts when data is written to SCnTXB Continuous transmission is possible by writing data to SCnTXB again while transmission is in progress During a 7 bit transfer the MSB bit 7 is ignored The SCnTXF flag is set to 1 when data is written to SCnTXB and is set to 0 at the end of transmission The SCnTBF flag is set to 1 when data is written to SCnTXB and is set to 0 at the start of transmission Reception Transfer with 8 bit data length parity on and 1 stop bit SCnRXF flag SCnRBF flag Interrupt DMA request 4 1 1 Data read Fig 11 5 10 Timing Chart 7 Two byte transfer with 7 bit data length parity on and 1 stop bit SBI pin SCnRXF flag SCnRBF flag Interrupt DMA request A A Data read A Fig 11 5 11 Timing Chart 8 ts Description of Operation 303 Chapter 11 Serial Interfaces After
182. Fig 9 7 3 Interval Timer Operation When Use 1 243 Fig 9 7 4 Event Counting Operation alte OR bu oA ER 244 Fig 9 7 5 Operation on Cascaded Connection 246 Fig 9 7 6 Operation of Compare Register When Clock Source 247 Fig 9 7 7 Operation of Input Capture When Select Rising Edge 248 Fig 9 7 8 Pin Output Waveform 1 249 Fig 9 7 9 Pin Output Waveform 2 estere papae atu 250 Fig 9 7 10 Pin Output Waveform 3 sedeant tae eie 250 Fig 9 7 11 Pin Output Waveform 4 eee ra r dll 251 Fig 9 7 12 Pin Output Wave 9 duoc MM heres 251 lt gt xvi Fig 9 7 13 Start Up by an External Trigger When Rising Edge is Selected 253 Fig 9 7 14 One shot Operation When Clock Source IOCLK eee 255 Fig 9 7 15 One shot Operation When Using Prescaler c cccssssssessesseesessessessesscssesssssesecsarsavenesneanees 255 Fig 9 7 16 Operation of Interval Timer on Timer 6 1 258 Fig 9 7 17 Operation of Interval Timer on Timer 6 2 258 Fig 9 7 18 Operation of Interval Timer on Timer 6 When Clock Source
183. Functions 229 Chapter 9 16 bit Timers 9 6 Description of Registers Address Table 9 6 1 List of 16 bit Timer Registers Name Symbol Number of bits Initial value Access size 0x34001080 Timer 4 mode register TM4MD 8 00 8 32 0x34001082 Timer 5 mode register TMSMD 8 00 8 0 34001084 Timer 6 mode register TM6MD 16 x 0000 8 16 0x34001090 Timer 4 base register TM4BR 16 x 0000 16 0x34001092 Timer 5 base register TMSBR 16 x 0000 16 0x340010A0 Timer 4 binary counter 16 x 0000 16 0x340010A2 Timer 5 binary counter TMSBC 16 x 0000 16 0x340010A4 Timer 6 binary counter TM6BC 16 x 0000 16 0x340010B4 Timer 6 compare capture A mode register TM6MDA 8 x 00 0 340010 5 Timer 6 compare capture B mode register TM6MDB 8 x 00 0x340010C4 Timer 6 compare capture A register TM6CA 16 x 0000 0x340010D4 Timer 6 compare capture B register TM6CB 16 x 0000 0x34001071 Prescaler control register TMPSCNT Prescaler control register TMPSCNT is also used at 8 bit timer Set I O bus to synchronous mode for read write of 16 bit timer 8 Operation is out of guarantee for read write action under asynchronous mode 230 Description of Registers x 00 Chapter 9 16 bit Timers
184. ICINV in the cache control register CHCTR to invalidate all of the entries and then set the instruction cache enable bit ICEN Examples of an initialization routine are shown below Note that the cache control register CHCTR gains control from the moment that an instruction fetch occurs subsequent to the instruc tion that writes the cache control register CHCTR having entered the writing stage in the CPU pipeline When initializing the instruction cache immediately after a reset mov 0x20000070 d a0 mov 0 00000030 mov 40 a0 Invalidates the cache initialization mov 0x00000003 d d0 mov 40 a0 Enables the instruction cache data cache nop When initializing the instruction cache while it is in operation mov 0x20000070 d a0 mov a0 d0 and mov do 0 Disables the instruction cache setlb nop mov 0 40 btst 0 04 40 Instruction cache busy check lne or 0x00000010 d d0 mov 40 a0 Invalidates the instruction cache initialization 64 Description of Operation Chapter 4 Caches 4 5 1 2 Read Operation Cache Hit Operation If an instruction is fetched from the cacheable space x 40000000 to x 7FFFFFFF while the instruc tion cache is enabled the instruction cache tag array is accessed using the tag entry address field bits 10 to 4 of the instruction fetch address as the address If the value in the tag address field TADD of the accessed entry matches the
185. Interrupt DMA request A uum when set to transmission 1 1 1 1 D 1 buffer empty Fig 11 5 5 Timing Chart 2 Description of Operation 299 Chapter 11 Serial Interfaces When transmission is enabled transmission starts when data is written to SCnTXB Continuous transmission is possible by writing data to 5 again while transmission is in progress i During a 7 bit transfer the MSB bit 7 is ignored The SCnTXF flag is set to 1 when data is written to SCnTXB and is set to 0 at the end of transmission The SCnTBF flag is set to 1 when data is written to SCnTXB and is set to 0 at the start of transmission Reception One byte transfer with 8 bit data length and parity on wr Ter 2 565 865 865 886 897 webs bre SCnRXF flag IE ucc ANN SCnRBF flag i Interrupt 1 request Data read Fig 11 5 6 Timing Chart 3 300 Description of Operation Chapter 11 Serial Interfaces Two byte transfer with 8 bit data length and parity off SBI pin poe oo ps oos b beo bp 1 bp2 bn3 fs bi SCnRXF flag C MELDE CREE SCnRBF flag Interrupt DMA request 2 1 t 1 1 1 Data read A Fig 11 5 7 Timing Chart 4 After reception end when the SCnRBF flag is 1 the received data is
186. Interrupt Control Register Register symbol G7ICR Address x 3400011 Purpose This register is used to enable group 7 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 TMSID Timer 5 underflow interrupt detection flag 0 No underflow interrupt detected 1 Underflow interrupt detected 1to3 Always returns 0 4 TMSIR Timer 5 underflow interrupt request flag 0 No underflow interrupt requested 1 Underflow interrupt requested 5107 Always returns 0 8 TMSIE Timer 5 underflow interrupt enable flag 0 Disabled 1 Enabled 9011 Always returns 0 12 G7LVO Group 7 interrupt priority level register LSB 13 G7LV1 Group 7 interrupt priority level register 14 G7LV2 Group 7 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 177 Chapter 7 Interrupt Controller 7 4 2 7 Group 8 Interrupt Control Register Register symbol Address Purpose When reset Access 5to7 9 to 11 12 13 14 15 178 Description of Registers x G8ICR 34000120 This register is used to enable group 8 interrupts and to confirm interrupt requests and detection Bit name TM6ID TM6IR 6 G8LVO G8LV1 G8LV2 Description Timer 6 underflow interrupt detection flag 0 No underflow interrupt detected 1 Underflow interrupt detected Always returns 0 Timer 6 underfl
187. Item Symbol Conditions Unit Min Typ Max Output pins Output Push pull gt A11 to A31 CS0 to CS3 CASO to CAS3 to BG WDOVE SYSCLK DMKO to DMK3 SBO2 C12 Output voltage high level 2 Vpp or Vss Vpp 0 6 lo 4mA Output voltage low level 012 Vpop or Vss 04 V 0 4 C14 Output leak current 1072 Vo Hi Z state 10 1 10 Input pins Input TTL 5 V level S T IRQO to IRQ7 NMIRQ DK BCR BR FRQS DMRO to DMR3 BMODE MMODE RST CTS SBIO to SBD SBT2 5 Input voltage high level 2 2 5 16 Input voltage low level 00 0 6 V c17 Input leak current 1073 Vss to 10 10 342 DC Characteristics Chapter 13 Electrical Characteristics Table 13 3 4 DC Characteristics 4 VDD PVDD 3 3 V 0 165 V Vss 55 0 0 V TA 20 C to 70 C Allowable values Item Symbol Conditions cin Dp ux Unit OSCI pin when using external clock input Refer to Fig 13 3 1 in the case of self excited oscillation by crystal C18 Input voltage high level Vpp x 0 7 V C19 Input voltage low level ViL4 00 0 3 V Pin capacitance C20 Input pin 0 7 15 C21 Output pin 18 25 C 7 15 C22 Input output pin Cro 7 15
188. LK because there is wait for synchronization with IOCLK in response to CPU requests a wait of up to three MCLK cycles high speed access becomes possible However during serial reception etc if the data changes during the read cycle the read data is not guaranteed therefore it is necessary either to read the data after serial reception is completed or else to change the mode to synchronous mode before reading an internal I O circuit where there is a possibility of the data changing In addition when writing in asynchronous mode operation is not guaranteed due to a problem with the mode switch ing timing therefore do not use asynchronous mode except with certain I O circuits The number of wait states in asynchronous mode is set through the IOWC bits in the I O bus control register Fig 5 8 3 shows the timing for an internal I O access in asynchronous mode when the number of wait states is set to 3 Setting synchronous mode with no wait states is recommended except when otherwise necessary Operation is not guaranteed for accesses in asynchronous mode For details refer to the specifications for the peripheral circuits BILE LB E T IOAL1 0 SISSE ES RR WR DS3 0 IOD31 0 2222 e 3 ok de 3 wait ok m P Read cycle Write cycle Fig 5 8 3 Internal Space Access Asynchronous Mode with Three Wait OK Descriptio
189. LSB 7 SIZE1 DRAM size MSB 00 For the low address shift 8 bits to the low order side 01 For the low address shift 9 bits to the low order side 10 For the low address shift 10 bits to the low order side 11 For the low address shift 11 bits to the low order side 8 WCO DRAM wait state insertion LSB 9 WCI DRAM wait state insertion 10 WC2 DRAM wait state insertion 11 WC3 DRAM wait state insertion MSB The relationship between the value of WC3 to 0 and the number of wait states is shown below Continued 98 Description of Registers Continued Chapter 5 Bus Controller 1 When not using the in circuit emulator PX ICE103002 When 0 number of wait states counted by MCLK When 1 number of wait states counted by MCLK 0000 0 wait states 0001 1 wait states 0010 2 wait states 0011 3 wait states 0111 7 wait states 2 When using the in circuit emulator PX ICE103002 0000 0 wait states 0010 2 wait states 0100 4 wait states 0110 6 wait states 1110 14 wait states Setting an odd number of wait states is prohibited 1 When using the emulation function Page mode When 0 number of wait states counted by MCLK When 1 number of wait states counted by MCLK 0000 Setting prohibited 0001 Setting prohibited 0010 2 wait states 0011 3 wait states 0111 7 wait states 0000 0 wait states 0010 2 wait states 0100 4 wait s
190. MEMCTRO 1 n m 2 1 0 represents the number of wait states 352 AC Characteristics Chapter 13 Electrical Characteristics Table 13 4 6 AC Characteristics 6 VDD 3 3 V 0 165 V Vss 0V 20 C to 70 C CL 50 pF Allowable values Ite Symbol Conditions i m ymbol Conditio um Unit DRAM mode data transfer signal output timing Refer to Fig 13 4 6 tc 2 E46 Row Address output with ko _ B A31 0 5 Column address output with n P E47 P 4 ns A31 0 5 T Row address strobe signal fall delay time traspr V EE TUE ns RAS4 1 m 4 8 4 2 41 E49 Row address strobe signal rise delay time T 5 iis RASA 1 4 50 Column address strobe signal fall delay time e 8 42 is CAS3 0 4 M E i 1 1 E5 Column address strobe signal rise delay time _ lt _ a 3 0 4 Notes 1 1 t is the SYSCLK cycle time 2 and n change according to the DRAMCTR and MEMCTRO setting The correspondence is shown below 2 2RTC 4 wc Nr When 0 2 and when FRQ 1 nr 4 AC Characteristics 353 Chapter 13 Electrical Characteristics Table 13 4 7 AC Characteristics 7 VDD 33Vt0 165 V
191. Max Supply voltage 3 135 3 3 3 465 V B2 PLL supply voltage PVpp 3 135 3 3 3 465 V B3 5 V supply voltage Vpps Vpp 5 0 5 25 V Crystal oscillation OSCI FRQS pin H level 13 0 16 6 B4 Oscillating frequency Fosc MHz _ FROS pin L level 26 0 33 3 Note 5 VDD and PVDD must always be the same voltage Operating Conditions 339 Chapter 13 Electrical Characteristics 13 3 DC Characteristics Tables 13 3 1 through 13 3 4 show the DC characteristics Table 13 3 1 DC Characteristics 1 Vss PVss 0 0 V Ta 20 C to 70 Allowable values Item Symbol Conditions Unit Min Typ Max Supply current during 23 3 V 250 Vi or Vss Fosc 16 7 MHz FRQS level Output open C2 Supply current in SLEEP 1002 Vor PVDD 3 465 V 50 mA mode VDD pin Vpp or Vss Fosc 16 7 MHz FRQS pin H level Output open C3 Supply currentin HALT 1003 Vor PVpp 3 465 V 6 mode VDD Vi Vpp or Vss Fosc 16 7 MHz FRQS pin H level Output open C4 Supply current when PVpp 3 465 V 1 25 mA stopped VDD pin M VpbporVss Fosc Oscillation stopped Output open 5 Supply current during Impp 2 3 3 V 3 0 mA PLL operation PVDD Vpp or Vss pin Fosc 16 7 MHz FRQS pin level C6 Supply curre
192. O 1 2 TMnCNE has to be set 0 To set TMnLDE equal to 0 TMnCNE has to be set 1 To set TMnCNE equal to 0 TMnLDE has to be set 1 Operation is not guaranteed when both TMnCNE and TMnLDE are become 1 Description of Registers 211 Chapter 8 8 bit Timers TMnCK 2 0 Setting Table 8 6 2 8 bit Timer Clock Source Timer 0 Timer 1 Timer 2 Timer 3 000 IOCLK IOCLK IOCLK 001 1 8 IOCLK 1 1 8 IOCLK 1 8 IOCLK 1 8 IOCLK 1 32 IOCLK 1 32 IOCLK 1 32 IOCLK 1 32 IOCLK Setting prohibited Cascaded with timer 0 Cascaded with timer 1 Cascaded with timer 2 Setting prohibited Timer 0 underflow Timer 0 underflow Timer 0 underflow Timer 1 underflow Setting prohibited Timer 1 underflow Timer 1 underflow Timer 2 underflow Timer 2 underflow Setting prohibited Timer 2 underflow TMOIO pin input TMIIO pin input 210 pin input TM3IO pin input You must need to set prescaler control register TMPSCNT when 1 8 IOCLK or 1 32 IOCLK is used If TMnIO pin input is selected count by rise edge of pin input 8 6 2 Timer n Base Register n 0 1 2 3 Register symbol Address Purpose TMnBR 34001010 n 0 x 34001011 n 1 x 34001012 n2 x 34001013 n 3 Set the initial value of the timer n binary counter and the underflow cycle Under below condition the setting value of TMnBR is loaded to TMnBC
193. Output Register Register symbol P1OUT Address x 36008001 Purpose Sets the data that is to be output on port 1 6 P150 4 P130 P120 name 0 o0 o o oo RW 12 3 2 2 Port 1 Output Mode Register Register symbol PIMD Address x 36008021 Purpose This register selects the port 1 pin output content When reset Bit No Bit name Description 0 P10M Port 1 pin output content selection 0 Data input output D15 to D8 1 General purpose I O port P17 to P10 1 to 7 Always returns 0 Port 221 Chapter 12 Ports 12 3 2 3 Port 1 Input Output Control Register Register symbol PIDIR Address x 36008061 Purpose This register sets the input output direction of the port 1 pins 0 input pin 1 output pin Bit name 12 3 2 4 Port 1 Pin Register Register symbol Address x 36008081 Purpose This register is used to read the value of the port 1 pins 322 Pot Chapter 12 Ports 12 3 3 Pin Configuration Table 12 3 1 shows the pin configuration of port 1 Table 12 3 1 Port 1 Configuration P10M 1 PinD 1 PlnD 0 General purpose output port General purpose input port General purpose output port General purpose input port General purpose output port General purpose input port General purpose output port General purpose input port General
194. P 32 bit x 1 Other registers PC 32 bit x 1 PSW 16 bit x 1 multiply divide register 32 bit x 1 branching registers 32 bit x 2 Instructions Number of instructions 46 Number of addressing modes 6 Basic instruction word length 1 byte Code assignment 1 byte to 2 bytes basic part 0 byte to 6 bytes extension Basic performance Maximum internal operating frequency 66 6 MHz external oscillation 16 6 MHz Minimum instruction execution cycle 1 cycle 15 ns Register to register operations 1 cycle Load store 1 cycle Conditional branch 1 cycle to 3 cycles Pipeline 5 stage instruction fetch decode execute memory access write back Address space 4GB Unified space for instructions data However instructions can not be fetched from the data only cache space at x 00000000 tox 1FFFFFFF 1 4 Overview Chapter 2 CPU 2 2 Block Diagram The block diagram focusing on the MN103002A MN103002A YB CPU is shown below Address registers Data registers M ii 0 0 PSW Instruction execution control block Instruction decoder Interrupt Instruction control queue block Program counter block User extension operation unit Extension interface y Operand address Operand data Ins
195. PU when BSET or BCLR is being ex ecuted However if a BSET or BCLR instruction is executed during program execution in external memory a bus authority release due to an external bus request or DMA transfer may be interposed between the data read and data write by the BSET or BCLR instruction If the atomic bus cycles of the BSET or BCLR instruction need to be guaranteed in a system that uses multiple processors either of the following measures should be taken 1 A program in which a BSET or BCLR instruction is executed should be placed in instruction cache Note that an external memory access is occurred if a cache miss occurs in the instruction cache 2 Program so that bus requests cannot be accepted during execution of a BSET or BCLR instruction 154 Description of Operation Chapter 6 Controller 6 4 06 Transfer Examples 6 4 6 1 One Bus Cycle Transfers One bus cycle transfer single word transfer DMR edge detection synchronous mode Transfer devices External memory External device with acknowledge function Transfer method bus cycle single word transfer DMR edge detection Bus mode 32 bit bus synchronous mode one wait state SYSCLK A31 0 CPU ESE a D31 0 a DMR RE e DMK 222 Peg di Jani DMA cycle DMA cycle O DMR sampling Fig 6 4 4 One Bus Cycle Transfe
196. PU are handled in 64 bit units The contents of data memory are not initialized by a reset Tag memory The tag memory has 128 entries each of which consists of a tag address field TADD that stores bits 29 through 11 19 bits of the instruction address a valid bit V that indicates whether an entry is valid or not and a refill bit R that indicates whether an instruction transfer a refill from external memory to the cache is in progress In the event of a reset only the refill bit R is cleared The valid bit V is not cleared it is cleared by the instruction cache invalidate bit in the cache control register CHCTR LRU section The LRU section stores information that is used to select the entry that should be refilled The LRU section is shared by way 0 and way 1 The contents of the LRU section can be referenced as part of the tag entries The LRU section is not initialized by a reset Configuraion 99 Chapter 4 Instruction cache memory array way 1 4bytes lt Instruction cache address 31T 29 11 4 0 Access space specification address Tag address Entry address Byte address LRU Instruction cache tag data twa 31 29 11 43210 Fig 4 3 1 Instruction Cache Configuration 4 3 2 Data Cache The data cache has a 4 Kbytes capacity and adopts the two way set associative method for associatio
197. Pub No 23102 050E MN1030 P X Series TheOnetoWatch for Constant Innovation Making theFuture ComeAlive MICROCOMPUTER MN103002A LSI User s Manual Panasonic sns z i 6 2 Ss qu c PanaX Series is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 1 2 3 4 5 Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standards or Specific
198. Register n 0 1 286 11 4 3 Serial n Transmission Buffer 0 1 essere 287 11 4 4 Serial n Reception Buffer n 0 1 287 11 4 5 Serial n Status Register n 0 288 11 4 6 Serial 2 Control 289 114 7 Serial 2 Interrupt Mode Register 291 11 4 8 Serial 2 Transmission Buffer esee 292 11 4 9 Serial 2 Reception Buffer s c sioe UR Vivam et Ec 292 11 4 10 Serial 2 Status Register 200 tette 293 11 4 11 Serial 2 Timer Setting Register esses 294 11 5 Description of Operation ease tatu OP ae dtd 294 11 5 1 Serial Interfaces 0 and 1 essere 294 11 5 E 1 294 11 5 1 2 Baud rates scsi ss eibi en 297 11 5 1 3 Clock Synchronous Mode Timing sees 299 11 5 1 4 Start stop Synchronous Mode Timing 20 0 302 11 51 55 I2C Mode Timing 304 11 5 1 6 Reception amp ai 307 1 52 Senal Interface2 ee erect ede 309 115 21 Connections nieder eta 309 11 5 2 2 Rate eene eee d reete 310 11 5 2 3 Transmission Interruption Function 312 11 5 2 4 Notes on Use tecla 312 Chapter 12 Ports 121 OVEI
199. Row X RASn DMA cycle O DMR sampling Fig 6 4 7 One Bus Cycle Transfer Single word Transfer DMR Edge Detection Asynchronous Mode Figs 6 4 6 and 6 4 7 show the timing charts for a one bus cycle transfer in asynchronous mode from external memory a non DRAM space in Fig 6 4 6 a DRAM space Fig 6 4 7 to an external device that supports the acknowledge function initiated by edge detection of a DMA request signal DMR from an external source With edge detection the DMR signal is detected at its falling edge but once a DMA request is detected detection does not occur again until the DMA acknowledge signal DMK is asserted 158 Description of Operation Chapter 6 Controller 6 4 6 2 Two Bus Cycle Transfers Two bus cycle transfers burst transfer DMR edge detection synchronous mode Transfer devices External memory gt External memory Transfer method Two bus cycles burst transfer DMR edge detection Bus mode Transfer source 32 bit bus synchronous mode 1 wait state Transfer destination 32 bit bus synchronous mode 1 wait state PME R i A31 0 CPU DMA R YDMA W X DMA R XDMACW CPU BUE apos 031 0 O iaces DMR z 2g DMA read DMA write DMA read DMA write cycle 1 cycle 1 cycle 2 cycle 2 sampling Fig 6 4 8 Two Bus Cycle T
200. S signal Output DRAM CAS signals Output Chip select signals Output Memory read signal Output Memory write signals output in byte units Input Data acknowledge signal RD WT Output Read write status signal SIZEI 0 Output Access size information notification signal 00 1 byte 01 2 bytes 10 3 bytes 11 4 bytes Input Bus authority request signal Output Bus authority release signal BMODE Input Block 0 data bus width specification 0 16 bits 1 32 bits DMR3 0 Input DMA request signals DMK3 0 Output DMA acknowledge signals MMODE Output CAS3 corresponds to D31 to 24 CAS2 corresponds to D23 to 16 CAS1 corresponds to D15 to 8 and CASO corresponds to D7 to 0 WE3 corresponds to D31 to 24 WE2 corresponds to D23 to 16 corresponds to D15 to 8 and corresponds to D7 to 0 Pin Functions Test pin Chapter 5 Bus Controller 5 6 Description of Registers Table 5 6 1 lists the bus controller registers The settings of these registers are used in wait state control DRAM interface control etc Table 5 6 1 List of BC Registers Number Address Name Symbol of bits Initial value 32000010 I O bus control register EL 16 x 0F70 x 3200002 ol Memory control register 0 MEMCTRO 16 x XXXX x 32000022 Memory control register 1 MEMCTRI 16 1 20 32000024 Memory control register 2
201. Startup Operation 1 Set the division ratio of timer Set the division ratio to TMnBR The request of interrupt occurs after count value of TMnBR 1 times rise edge of input 2 Select Clock Source Set clock source to TMnIO pin by handling TMnCK 2 0 field of TMnMD register 3 Initialize Timer Initialize timer n by setting the value 1 to TMnLDE field of TMnMD register Then the value of TMnBR register is loaded into TMnBC register as initial value After initialization return to the normal mode by setting the value 0 to TMnLDE 4 Set I O port Set I O port as input pin Refer to the chapter I O port about setting registers 5 Permit timer counting operation Permit timer counting by setting the value 1 to TMnCNE field of TMnMD register Once permit timer counting the rise edge of the port input are counted then generates interrupt signal on underflow in binary counter and load the value of TMnBR register into TMnBC register If change the value of TMnBR register while counting in progress that is used as initial value when next underflow occurs Sequence of Stopping Operation 1 Stop timer counting Stop timer counting when set the value 0 to TMnCNE field of TMnMD register 2 Initialize timer if it is necessary If set value 1 to TMnLED field of TMnMD register the value of TMnBR register timer is loaded into TMnBC as initial value After timer is stopped if never set the value 1 to TMnLDE the value of binary counter are mai
202. This instruction conducts a bit search within the 32 bit bit string stored in Dm starting from the bit position of the bit number indicated by the contents of Dn 1 and continuing in the direction of descending bit numbers The bit number of the first bit position where a 1 is found is then stored in Dn When the least significant five bits of Dn are zeroes the bit search is conducted from bit 31 and continues in the direction of descending bit numbers If the bit search reaches bit 0 without finding a 1 the flag is set 0 00000000 is written in Dn and execution of this instruction ends When execution of this instruction starts the upper 27 bits of Dn are ignored Dn after execution Dn before execution y Search direction y Bit 31 eid Bit 0 Di i ss GOP MSB LSB Search range Flag Changes When the search was successful a 1 was found Flag Change Condition n Undefined C 0 Indicates that the search was successful N Undefined Z Undefined When the search failed no 1 was found Change Condition V s Undefined C 1 Indicates that the search failed N Undefined Z Undefined E Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However
203. VICW MAIS 314 12 24 ome halen as 316 12 2 1 Block Diagram eene eerte tete reto ee 316 12 2 2 Description of Registers 00 0044 610000100 317 12 2 2 1 Port 0 Output Register esessseeee ertet 317 12 2 22 Port 0 Output Mode Register eese 317 12 2 2 3 Port 0 Input Output Control Register 318 12 2 24 Port 0 Pin Register essent 318 12 2 3 Pin Configuration 2 eececcccessessssesessesesesscsscscssesesarssevsucstscarencensneancansacaess 319 lt ix gt 12 4 12 5 12 6 Chapter 13 13 1 13 2 13 3 Pott 1i 320 12 3 1 320 12 3 2 Description of Registers 0 0 0040414 000000001 321 12 3 2 1 Port 1 Output Register 0 0 0404100 321 12 3 2 2 Port 1 Output Mode Register 321 12 3 2 3 Port 1 Input Output Control Register 322 12 3 2 4 Port 1 Pin Register 322 12 3 3 Pim Configuration sessi 323 Port cee ede 324 12 4 1 Block Diagram seid ete ere 324 12 4 2 Description of Registers reete ns 326 12 4 2 1 Port
204. When using the emulation function External input pin Synchronous mode BOBM 20 number of wait states counted by SYSCLK Asynchronous mode 1 number of wait states counted by MCLK x0000 x0001 x0010 x0011 Setting prohibited Setting prohibited 2 wait states 3 wait states x1111 15 wait states x0000 Setting prohibited 0001 0010 0011 1 wait states 2 wait states 3 wait states x1111 15 wait states 00000 Setting prohibited 00011 Setting prohibited 00100 4 wait states 11111 31 wait states 2 When using the external trace function External input pin Synchronous mode 01 number of wait states counted by SYSCLK Asynchronous mode BOBM 1 1 number of wait states counted by MCLK x0000 Setting prohibited x0001 1 wait states x0010 2 wait states x0011 3 wait states x1111 15 wait states 00000 Setting prohibited 00001 Setting prohibited 00010 Setting prohibited 00011 3 wait states 11111 31 wait states Description of Bit No 11 to 8 The relationship between the value of WC3 to 0 and the number of wait states is shown below When 0 number of wait states counted by MCLK When 1 number of wait states counted by MCLK Description of Bit No 11 to 8 The relationship between the value of WC3 to 0 and the number of states is shown below 1 When not using
205. a multiply and accumulate instructions and MCRH MCRL access instruc tions When executing a byte data multiply and accumulate instruction followed by an MCRH MCRL access in struction the result produced by the byte data multiply and accumulate instruction is used in the execution of the subsequent MCRH MCRL access instruction Therefore it is essential to not initiate the subsequent MCRH MCRL access instruction until after the required result of the byte data multiply and accumlate instruction has been output In addition two cycles must be inserted between the byte data multiply and accumulate instruction and the subsequent MCRH MCRL access instruction Byte data Insert two multiply and accumulate cycle instruction DEC ANN Instruction decoding EX Operation MEM WB This note applies to the following instructions Result can be referenced instruction Multiply and accumulate instruction has output the result that is required by MCRH MCRL access instruction Byte data multiply and accumulate instructions MACB instruction MACIB instruction MACBU instruction MACIBU instruction lt MCRL access instructions PUTCX instruction CLRMAC instruction GETCHX instruction GETCLX instruction Fig E 7 Pipeline Diagram Illustrating This Note 5 Extension Instruction Specifications 423 Appendices Extension Instruction List Includes Code Length
206. ach group Interrupt mask level Can be set for each interrupt group External pin interrupt conditions Positive edge negative edge high level low level Recovery from STOP HALT or SLEEP mode is possible by means of an external pin interrupt 162 Overview Features Chapter 7 Interrupt Controller 7 3 Configuration 7 3 1 System Diagram NMIRQ T Negative edge detection Interrupt request IRQO Edge level detection to CPU IRQI Edge level detection Interrupt 1802 Edge level detection controller IRQ3 Edge level detection IRO4 Edge level detection IRQS Edge level detection IRQ6 Edge level detection IRQ7 Edge level detection Internal interrupts Timer serial DMA RR Fig 7 3 1 System Diagram Configuration 163 Chapter 7 Interrupt Controller 7 3 2 interrupt Source Assignments Interrupt control register address NMIRQ pin Watchdog timer overflow Non maskable interrupts CPU core x 34000100 Eg GROUP 0 2 2 ystem error Level 0 to 6 Lo GROUP Reserved for system 3 Timer 0 underflow x 34000108 GROUP 2 2 Timer underflow GROUP x 3400010C EU Kg ES Timer 2 underflow o x 34000110 3 GROUP al Timer 3 underflow x 34000114 GROUP EH E 2 Timer 4 underflow GROUP on 34000118 Timer 5 underflow
207. ack SP 8 The PC the return address is saved to the stack SP 4 The contents of the PSW are updated IE is cleared and the level of the interrupt that was accepted is stored in IM2 to IMO In the case of non maskable interrupts IM2 to IMO are undefined The contents of the stack pointer are updated SP 8 SP Control jumps to the fixed address corresponding to the source of the interrupt that was accepted or to the address indicated by the Interrupt Vector Register IVARn When an interrupt other than a reset interrupt is accepted control jumps to the fixed address corresponding to the source of the interrupt or to the address indicated by the Interrupt Vector Register The processing indicated below is then performed at the jump destination in order to evaluate the interrupt source in further detail For details on processing in the case of a reset interrupt refer to section 2 7 3 1 Reset Interrupt Tormally a branch instruction JMP instruction etc is placed at the Jump destination for the reset interrupt transferring control to the initialization program 42 Interrupt Functions Chapter 2 CPU Example of preprocessing by the interrupt handler Step 1 contents of the registers are saved The registers that are saved are those that will be used by the interrupt handler Step 2 The interrupt group analysis is performed Step 2 1 The interrupt acknowledge sequence is executed
208. age mode Supports high speed page mode Supports the page mode mix cycle DRAM The DRAM interface be used with an external bus master block 3 only Deleted Interrupts 30 sources External interrupts 9 sources 8 individual IRQs and 1 external NMI Interrupts 30 sources External interrupts 9 sources IRQn n 7 to 0 x 8 and NMIRQ x 1 Following item is added Package e MN103002A QFP160 P 2828B 28 mm square 0 65 mm pitch QFP e MN103002A YB FLGA165 C 1111 11 mm square 0 8 mm pitch CSP Figure 1 4 2 103002 Pin Assignment Diagram is added As the result of adding the diagram and the change on p 9 the pin function list moved to p 10 p 11 and became Table 1 4 3 Table 1 4 2 MN103002A YB Pin Assignments is added i As the result of adding the pin assignments and the change on p 8 the pin function list moved to p 10 p 11 and became Table 1 4 3 Table title is added to a table of section 1 4 2 The column of Pin Function such as Pin name is NMIRQ in the table i External NMI signal input The column of Pin Function such as Pin name is NMIRQ in the table i External non maskable interrupt signal input Minimum instruction execution cycle 1 cycle 15 nsec Manimum instruction execution cycle 1 cycle 15 ns Omit i CPU pipeline control register was deleted from the table 2 3 1 List of
209. al bus access for the write back is initiated and the data that was saved in the write back buffer is written to external memory This operation maintains the consistency of the data in the data cache versus the data in the external memory Description of Operation 71 Chapter 4 Caches 4 5 2 3 Write Operation The data cache supports two types of writing methods write back and write through The write operation varies depending on the writing method that is selected Write back Mode 72 Cache Hit Operation If data is written to a cacheable space x 00000000 tox 1FFFFFFF or x 40000000 7FFFFFFF while the data cache is enabled the data cache tag array is accessed using the tag entry address field bits 10 to 4 of the data address as the address If the value in the tag address field TADD of the accessed entry matches the value in the tag field of the data address and the valid bit V of that entry has been set to 1 then a hit is said to have occurred during the write access to the data cache If a hit occurs in the write access to the data cache the data is sent from the CPU to the corresponding entry line in the data memory section At this point the line in which data was written contains data that is newer than the data that is in the same address in external memory in this state the consistency of the data is not being maintained This state is called the dirty state and the dirty bit D in the c
210. and Acceptable Interrupt Levels Int level MAST Interrupt levels that can be accepted IM2 IMI IMO 0 Interrupts disabled only non maskable interrupts accepted lojo 95 26 Interrupt Functions 2 7 2 2 Chapter 2 CPU Interrupt Control Registers GnICR The Interrupt Control Registers GnICR n 0 2 to 10 12 to 21 and 23 to 30 which control peripheral interrupts external to the CPU actually combine an interrupt priority level register an interrupt enable register an interrupt request register and an interrupt detection register into a single register There are 28 Interrupt Control Registers for each group and they are located the control register space from x 34000100 to x 34000179 GOICR is dedicated for non maskable interrupts so GOICR is also called NMICR from the least significant bit external pin non maskable interrupt watchdog overflow interrupt system error interrupt Fig 2 7 2 shows the Interrupt Control Register GnICR configuration Each field is explained in detail below 15 14 13 12 11 10 9 8 7 6 5 0 GnICR 0 1 0 ID GnICR n 2 10 15 14 13 12 11 10 9 8 7 6 5 0 12 21 0 LV IR ID 23 30 LV2 to LVO Interrupt Priority Level Register gt ee Fig 2 7 2
211. ata array memory map Address x 2800000x x 2800001x T 0 0 offset 0 l offset 0 B A Way 0 entry 0 offset 2 Way 0 entry offset 2 Way 0 entry 126 offset 2 Way 0 entry 127 offset 2 Way 1 entry 0 offset 2 F E D C Way 0 entry O offset 3 Way 0 entry L offset 3 x 280007EX x 280007FX x 2800100x x 2800101x x 280017EX Way 1 entry 126 0ffset 3 Way 1 entry 126 0ffset 2 x 280017FX Way 0 entry 0 offset 1 Way 0 entry offset 1 Way 0 ent Way 0 en Way 0 entry 126 offset 0 Way 0 entry 127 0ffset 0 Way 1 entry 0 offset 0 Way 1 entry 126 offset 0 Way 0 entry 126 offset 1 Way 0 entry 127 offset 1 Way 1 entry 0 offset 1 Way 1 entry Loffset 1 Way 1 entry 126 offset 1 Data cache data array memory map Address F E D 9 8 2820000 Way 0 entry O offset 3 Way 0 entry 0 offset 2 Way 0 entry 0 offset 1 Way 0 entry offset 3 Way 0 entry 1 offset 2 Way 0 entry Loffset 1 2820001 Way 0 entry 126 0 3 Way 0 entry 126 0ffset 2 Way 0 entry 126 offset 1 ae Way 0 entry 127 offset 3 Way 0 entry 127 offset2 Way 0 entry 127 offset 1 Way 0 entry 127 offset 0 Way 1 entry 0 offset 3 Way 1 entry 0 offset 2 Way 1 entry 0 offset 1 Way 1 entry 0 offset 0 Way Loffser3 Way L enuy Lofiser2 Wa
212. ata cache write access results in a miss the data is written to external memory and is not written in the data cache In addition no refill operation is performed CPU clock MCLK UW L L DEC stage EX stage Tag address stage Data address Data read bus Write i to store buffer Data write bus ET lt gt WB stage No write to cache Fig 4 5 10 Operation When a Data Cache Write Miss Occurs Write through Mode When switching between write back mode and write through mode while in operation be certain to first invalidate the entire contents of the data cache through the cache control register 76 Description of Operation Chapter 4 Caches 4 5 2 4 Consistency between the Cache and the External Memory In order to maintain consistency between the data stored in the data cache and the data in the external memory it is necessary to write the data that is stored in the data cache back to the external memory This operation is called purging and the MN103002A MN103002A YB is performed by accessing specific addresses Consistency must be guaranteed by software As shown in the memory map in Fig 4 5 11 purge addresses are assigned for each entry in the data cache Any individual entry can be written back to external memory by making a data access read or write to the correspond ing address For example in order to purge ent
213. ates counted by SYSCLK Asynchronous mode BOBM 1 number of waitstates counted by MCLK When FRQ 0 When 1 26 0 MCLK 52 0 x0000 Setting prohibited x0001 1 wait states x0010 2 wait states x0011 3 wait states x1111 15 wait states 52 0_ MCLK 66 7 x0000 Setting prohibited x0001 1 wait states x0010 2 wait states x0011 3 wait states x1111 15 wait states 00000 Setting prohibited 00001 1 wait states 00010 2 wait states 00011 3 wait states 11111 31 wait states 00000 Setting prohibited 00001 1 wait states 00010 2 wait si 00011 3 wait si 111 31 wait states wait states is shown 1 When not using t Description of Bit No 12 to 8 The relationship between the value of BOWC4 to 0 and the number of below he in circuit emulator PX ICE103002 Basic bus cycle Synchronous mode BOBM 0 number of wait states counted by SYSCLK Asynchronous mode 1 number of wait states counted by MCLK x0000 Setting prohibited 0001 1 wait states 0010 2 wait states x0011 3 wait states x1111 15 wait states 00000 Setting prohibited 00001 1 wait states 00010 2 wait states 00011 3 wait states 11111 31 wait states 00000 Setting prohibited 00001 Setting prohibited 00010 Setting prohibited 00011 3 wait states 11111 31 wait states 2 When using the in circuit emulator PX ICE103002 1
214. ation Chapter 9 16 bit Timers The output pattern of the additional bits is as shown below Table 9 7 2 Output Pattern Low order 8 bits of the value Value of high order 8 bits in the binary counter when set in the compare register additional bits are output in front of basic output b OXXXXXXX b XXXXXXXl 1 3 5 61 63 b XOXXXXXX b XXXXXX10 2 6 10 58 62 b XXOXXXXX b XXXXX100 4 12 20 52 60 b XXXOXXXX b XXXX1000 8 24 40 56 b XXXXOXXX b XXX10000 16 48 b XXXXXOXX b XX100000 32 When the resolution is 12 bits the relationship between the value set in the compare register and the output wave form duty ratio is as follows Compare register setting Output waveform duty ratio X FFFX 0 X FFEX 1 2 X 800X Q 1y2 X 7FFX 1 2 X 001X Q 2y2 X 000x 212 1 212 Description of Operation 263 Chapter 9 16 bit Timers Additional bit style PWM output Basic output Added bits one bit width 8 bit PWM output The output pattern is determined by bp7 to 2 in the compare register nes e di t I cycle PWM output 2 When the resolution is 10 bits Basic output x 4 11 8 12 16 14 64 Fig 9 7 21 Additional Bit Style PWM Output 1 Additional bit style PWM output when resolution is 10 bits Added bits one bit width Low order 2 bits of comparison value bp 7 6 of the compare register 1 cycle basic output x 4
215. ations in advance for more detailsd infomation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book Table of Contents List of Figures and Tables Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 General CPU Clock Generator Caches Bus Controller DMA Controller Interrupt Controller 8 bit Timers 16 bit Timers Watchdog Timer serial Interfaces I O Ports Appendices Chapter 13 Electrical Characteristics Tabel of Contents List of Figures and Tables ii Table of Contents Chapter 1 General 1 1 OVERVIEW sedeant utin 2 1 2 Features osse rere aee tiber in ERG e EROR 2 1 3 Block Diagram ette E e oc eda e leid 5 1 4 Pin Descriptions ise I deii det dae ac bos 6 1 4 1 Pin Assignmenls rediere a e dte ent 6 1 42 Functiofis ted eee t tee ERATES 10 Chapter 2 CPU 2 1 OVER VIC WS nanen dettes RETE Dd ter T d Ae Na tes ce teo 14 2 2 Block Diagram ice necne ie er entend 15 2 3 Programming Model 222 4 42 2 2 200 02 04040200020 000000120 22 0004000 16 2 34 Register Seter 16 2 3 2 Control 6
216. ations during write accesses to the data cache in write through mode are closely related data cache way mode setting The write to the data cache is performed regardless of which operating mode is se lected With regard to the write to external memory however the case where one way was set to the mode in which a refill is not made even if a cache miss occurs is an exception and the bug of writing to external memory for a write to the way that was set to the mode in which a refill is not made even if a cache miss occurs has not been incorporated into the specifications other writes entail writes to external memory In write through mode the CPU halts operations until the writing of data to external memory has been completed DEC stage EX stage Tag address MEM stage Data address Data read bus Data write bus WB stage Cache write Fig 4 5 9 Operation When Data Cache Write Hit Occurs Write through Mode Description of Operation 75 4 Cache Miss Operation If the data cache tag array is accessed using the tag entry address field bits 10 to 4 of the data address as the address and the value in the tag address field TADD of the accessed entry does not match the value in the tag field of the data address or if they match but the valid bit V of that entry is then a data cache write access miss is said to have occurred In write through mode if the d
217. ave might to use buses No treatment to pullup pulldown D15 P17 D14 P16 D13 P15 D12 P14 D11 P13 D10 P12 D9 P11 D8 P10 D7 P07 D6 P06 D5 P05 D4 P04 D3 P03 D2 PO2 D1 P01 DO PO0 Connect to Vpp through resister When only CPU has might to use buses Set as port input connect to When not connected with through register or set as port output signal line leave as floating pin Connected with signal line No treatment to pullup pulldown No treatment to pullup pulldown TM6IOB P27 TM6IOA P26 TMSIO P25 TMAIO P24 23 TM2IO P22 TMIIO SBTI P21 TMOIO SBTO P20 SBO1 P31 SBO0 P30 When not connected with Connect to Voo through resister signal line Connected with signal line No treatment to pullup pulldown Connect to Vss through resister If use serial debugger recommended value for resister is 1 DSCLK DSDAT BG WDOVF OSCO SYSCLK DMKT DMKO No treatment to pullup pulldown Select pullup pulldown Refer to 3 4 1 Connect oscillator Refer to 3 3 Select pullup pulldown Refer to 5 5 Connect to Vss through resister 3770 Treatment of Pins Appendix B External Pin Statuses Table B 1 shows the operating status of external pins concerning the BC Table B 1 Operating Status of External Pins Concerning BC Operating status STOP mode SLEEP mode HALT
218. ber of imm bits is 16 or less the operation results will be derived faster Operation of MULQU The range of significant values for the multiplier that is stored in Dn before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the contents that are stored in Dn the quicker the result of the operation can be derived i Operation of MULQU The range of significant values for the multiplicand that is stored in Dm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the contents that stored in Dm the quicker the result of the operation can be derived Operation of MULQIU The range of significant values for the multiplier that is stored in Dn before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the contents that are stored in Dn the quicker the result of the operation can be derived Operation of MULQIU The range of significant values for the multiplicand that is stored in Dm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only per
219. bit R in the tag entry of the way that was selected the values of the dirty bit D and the tag address field TADD in the same tag entry and the one line of data in the access entry in the data array are saved to the write back buffer This save sequence is performed regardless of the data cache writing method that is selected Next the external bus access refill operation which loads one line of data from external memory into cache memory is initiated The refill is performed in a burst transfer of four words 16 bytes that starts from the word 4 bytes including the access address In the refill sequence the tag address field TADD in the tag array entry is updated the valid bit V is set the dirty bit D is cleared and the target line in the data array is updated In addition the data is passed to the CPU simultaneously Data is passed in 4 byte units the CPU resumes operations as soon as the data is passed LLL LLL DEC stage EX stage Tag address comparison save Tag write comparison MEM stage Data address Data read bus Data write bus Save Refill data de write WB stage Fig 4 5 6 Operation When Data Cache Read Miss Occurs When the data cache writing method is write back mode and the dirty bit D in the entry that was accessed is set i e is 1 then after the refill is completed the extern
220. ble 2 3 1 List of Control 2 0000004001001000 tenerent testate tel th 19 Table 2 3 2 Oscillation Control and Operating Mode Control ccsssssssssssssessesssssseessessessessessecsscasecseesee 21 Table 2 4 1 Types 22 Table 2 5 1 Addressing 25 Table 2 5 2 Instruction Types Total of 46 instructions extension 1 26 Table 2 5 3 List of Transfer Instructions trecenti 27 Table 2 5 4 List of Arithmetic Operation Instructions cccsessessesssecsssssesssessessesssecessaeaveseesussuesaessvenees 28 Table 2 5 5 List of Compare 28 Table 2 5 6 List of Logical Operation 29 Table2 5 7 List of Bit Manipulation Instructions c ccccccsscessssesesesscsssesscsssscscsssvesesesessvacscausucscaransecseaes 29 Table 2 5 8 List of Shift i cov e Fa 30 Table 2 5 9 List of Branch Instructions do I ener nd edite see ra cd E rende 30 Table 2 5 10 NOP TRSICUCEIOD cis acp detegere p pU er tien uibs UR us 31 Table 2 5 11 List of Extension Operations sessseeeeetettettteteete terree tentent teneis 31 Table 2 7 1 Relationship between
221. ble buffer setting to allow the interrupt cycle changing Steps for operation termination 1 Terminate the count operation of the timer Set 0 into TM6CNE of TM6MD register 2 Initialize timer if it s necessary Setting 1 into TM6LDE of TM6MD register causes the clearing of TM6BC and the reset of the timer output If TM6CA register has double buffer setting value in compare register buffer is loaded into compare register Binary counter compare register and pin output keeps the condition before the termination unless TM6LDE is set to 1 after the termination of the timer Le it is possible to start recount from the terminated condition by setting 1 into TM6CNE again Input pulse width must be more than IOCLK x 1 5 since IOCLK being sampled at pin input Event count operation is inhibited when IOCLK is terminated HALT STOP mode Pin input TM6IOB Counting clock V mE Value in TM6BC value 1 A value A 0000 A 0001 Compare capture A interrupt request Fig 9 7 20 Event Counting Operation When Select the Rising Edge Description of Operation 261 Chapter 9 16 bit Timers 9 7 2 8 Register Settings Additional Bit Style PWM Mode l Setting TM6MD register While count operation is stopped set the clock source etc TM6MD register Set additional bit style PWM mode and set the resolution Set TM6CAE to 0 Set output port Set the port output mode regi
222. bongus 50 p Synchronous ACT SAGT Block 1 Permitted 3 Fixed wait 1 31 asynchronous CS1 or RASI Synchronous GA Popes Block2 Permitted Fixed wait handshake 1 31 asynchronous 52 RAS2 Block3 Permitted Fixed wait handshake 1 31 Synchronous G53 or RAS3 asynchronous Block 4 Permitted Fixed wait handshake 1 31 CS4 RAS4 Block 5 Not permitted Fixed wait handshake Same as block 1 Block 6 Not permitted Fixed handshake Same as block 2 Synchronous Block 7 Not permitted Fixed handshake Same as block 3 Synchronous When FRQ is 1 the number of wait states ranges from 3 to 31 When DRAM is connected the number of wait states is determined by the setting of the WC bits in the DRAM control register For details on the number of wait states refer to the description of the BOWC bits in memory control register 0 in section 5 6 Description of Registers Table 5 7 2 shows examples of devices that can be connected to each block Blocks 1 and 5 normally share the same number of wait states Although blocks 3 and 7 normally share the same number of wait states if DRAM is connected to block 3 the number of wait states are set independently because the number of wait states for block 3 becomes the number set by the WC bits in the DRAM control register while the number of wait states for block 7 becomes the number set by the B3WC bits in memo
223. by manipulating the interrupt control register GnICR corresponding to that group and notifying the CPU of the interrupt level The interrupt group number is also set in the interrupt acceptance group register The group interrupt level can be found by reading the interrupt priority level register LV 2 0 in the interrupt control register GnICR If multiple level interrupt signals are received the group to which each belongs is determined and then the interrupt group with the highest priority level is selected When the group levels are the same the group with the smallest group number is given priority For non maskable interrupts a non maskable interrupt request is sent to the CPU without performing the process ing described above 202 Description of Operation Chapter 7 Interrupt Controller 1 Maintain the signal value for at least four SYSCLK cycles when FRQS 0 or for at least two SYSCLK cycles when FRQS 1 in the case of external pin interrupt request signals Level detection is not possible if the signal is not maintained for at least the indicated number of clock cycles The above condition is not required in stop mode 2 When writing a GnICR register in an interrupt program in order to clear IR and ID and then returning from the interrupt program in order to gain synchronization with the bus controller store buffer be certain to per form an I O bus access between the execution of the instruction mo
224. byte data on the MSB side of half word data is the LSB side byte data address 1 and the address of the byte data on the MSB side of word data is the LSB side byte data address 3 For bit data the least significant bit is numbered 0 and the bit numbers increase towards the MSB Table 2 4 1 Data Types 1 Bit data 2 Byte data Unsigned 8 bits Signed 8 bits Sign bit MSB 3 Half word data Unsigned 16 bits Signed 16 bits Sign bit MSB 4 Word data Unsigned 32 bits Signed 32 bits Sign bit MSB MSB LSB U 23 16 8 Bit number 31 24 15 7 0 Address in memory Address 4n 3 Address 4n 2 Word data Half word data Byte data Fig 2 4 1 Little Endian Format 22 Data Formats Chapter 2 CPU 2 5 Instructions 2 5 1 Instruction Format There are 10 instruction formats these are shown below 8 bits L gt Format SO Format S1 OP imm8 48 Format S2 OP imm16 416 abs16 Format S4 OP imm32 432 abs32 Format S6 OP imm48 Format DO OP OP Format D1 OP OP imms a8 Format D2 imm16 416 abs16 Format D4 OP OP imm32 d32 abs32 Format D5 L OP OP immao Fig 2 5 1 Inst
225. ccess address length of the word 4 bytes In the refill sequence the tag address field TADD in the tag array entry is updated the valid bit V is set and the target line in the data array is updated In addition an instruction is passed to the CPU simultaneously Instructions are passed in 8 byte units the CPU resumes operations as soon as the upper four bytes of an instruction aligned with an 8 byte boundary are passed Description of Operation Chapter 4 Caches CPU clock MCLK L L LJ H fetch request Cache tag comparison prion Dv data u date Data address TENE i o Externa memory access Instruction CROCI address Instruction data bus buffer lower Instruction buffer upper i i Fig 4 5 3 Operation When an Instruction Cache Miss Occurs Disabling of the instruction cache during the instruction cache refill might cause mistake in writing the transmitting word in the end of refill In the case if the uncachable memory area is available First finish the instruction disable setting in the uncachable area also never operate the branch instruction pointing cachable area in the following 16 bytes In the case if the uncachable memory area is not available Never operate any branch instruction pointing cachable area during the next 16 bytes j
226. ce 5 6 2 8 Memory Control Register 7 Register symbol MEMCTR7 Address x 3200002 Purpose Sets the wait mode and bus width for external memory space block 7 Bit No Bit name Description 1 B7WM Block 7 wait mode 0 Fixed wait state insertion 1 Handshaking 5 B7BW Block 7 bus width 0 16 bits 1 32 bits 5 The number of wait states for block 7 is indicated by the value set in bits B3WC4 to 0 in memory control register 3 After reset mode is released block 7 is set to synchronous mode with 15 wait states and the bus width is 32 bits Block 7 cannot be used in asynchronous mode or as a DRAM space Description of Registers 97 Chapter 5 Bus Controller 5 6 3 DRAM Control Register 5 6 3 1 DRAM Control Register Register symbol DRAMCTR Address x 32000040 Purpose Stores various DRAM mode settings when DRAM is connected When reset Bit No Bit name Description 0 DRAME DRAM control circuit enable 0 Disabled 1 Enabled 1 PAGE Page mode enable 0 Disabled 1 Enabled 2 REFE Refresh enable 0 Disabled 1 Enabled 3 RPCP RAS precharge cycles 0 2cycles when FRQ 0 1 4 cycles when FRQ 0 4 cycles when FRQ 1 6 cycles when FRQ 1 4 RTC RAS CAS delay cycles 0 1 cycle when FRQ 0 1 2cycles when FRQ 0 2 cycles when FRQ 1 4 cycles when FRQ 1 5 RERP Refresh RAS cycles 0 2cycles when FRQ 0 1 4cycles when 0 4 cycles when FRQ 1 6 cycles when FRQ 1 6 SIZEO DRAM size
227. chs TM6CA 001 Set when TM6BC matchs TM6CB reset when TM6BC overflows 010 Set when TM6BC matchs TM6CB Reset only when the timer is initialized 011 Reset when TM6BC matchs TM6CB 100 Toggled output Output is inverted when TMnBC matches TMnCB 101 110 111 Setting prohibited Always returns 0 4 TM6BCE Timer 6 capture B operation enable flag Enables disables caputure operation for TM6CB 0 Disables caputure operation Pin input is ignored 1 Enables caputure operation 5 TM6BEG Timer 6 B pin polarity selection flag Selects the valid edge for the input on the TM6IOB pin and the output polarity 0 Rising edge valid Positive polarity output Reset L level set level 1 Falling edge valid Negative polarity output Reset H level set L level TM6BMO Timer 6 compare capture B operating mode setting flag LSB TM6BMI Timer 6 compare capture B operating mode setting flag MSB These bits set the TM6CB operating mode 00 Compare register single buffer 01 Compare register double buffer 10 Capture register single edge operation 11 Capture register dual edge operation When dual edge capture mode is set the setting of TM6BEG is ignored Description of Registers 237 Chapter 9 16 bit Timers 9 6 7 Timer 6 Compare Capture Register A Register symbol TM6CA Address x 340010C4 Purpose This register is the compare capture register A for timer 6 Bit name TM6 TM6 15 14 When
228. ck 1 When reset Access Bit No Bit name Description 0 BIDRAM Block 1 DRAM space setting 0 Do not use this block as a DRAM space 1 Use this block as a DRAM space 2 Block 1 bus mode 0 Synchronous mode synchronized with SYSCLK 1 Asynchronous mode synchronized with MCLK 5 BIBW Block 1 bus width 0 16 bits 1 32 bits 6 Block 1 DRAM byte specification 0 Specified by WE3 to 0 1 Specified by CAS3 to 0 BIWCO Number of block 1 wait state insertions LSB BIWCI Number of block 1 wait state insertions 10 BIWC2 Number of block 1 wait state insertions 11 Number of block 1 wait state insertions 12 BIWCA Number of block 1 wait state insertions MSB After reset mode is released block 1 is set to synchronous mode with 15 wait states and the bus width is 32 bits When using block 1 as a DRAM space the number of wait states is as indicated by the setting of the WC bit in the DRAM control register However even when using block 1 as a DRAM space be sure not to set a prohibited value in BIWCA to 0 DRAM mode is not valid when the DRAME bit in the DRAMCTR register is 0 and BIDRAM is 1 The number of wait states that are inserted is the same as set in bits BOWC4 to 0 Refer to the description of memory control register 0 MEMCTR0O 92 Description of Registers Chapter 5 Bus Controller 5 6 2 3 Memory Control Register 2 Register symbol MEMCTR2 Address x 32000024 Purpose
229. cles maximum value x 0000 to x 000F Setting prohibited The refresh interval is the setting value multiplied by the SYSCLK cycle 100 Description of Registers Chapter 5 Bus Controller 5 7 Memory Spaces In the MN103002A MN103002A YB the 2 GB memory space from x 40000000 to x BFFFFFFF is external memory space External memory space is partitioned into 8 blocks block 0 to block 7 When any of these blocks accessed various signals such as CS corresponding to the block in question output Fig 5 7 1 shows the address format for external memory accesses and Fig 5 7 2 shows the memory map Address a31 A29 A28 A26 A25 AQ i External address 64 MB space Block partition CSO to CS7 000 0 CS0 100 Block4 CS4 001 Block1 CS1 101 Block5 55 010 Block2 CS2 110 Block6 56 011 3 CS3 11 Block7 CS7 Space partition However the data only memory space 000 through 011 correspond to blocks 4 through 7 000 Data only external memory space cacheable 001 Internal I O space 01 External memory space for instructions data cacheable 10 External memory space for instructions data uncacheable 11 Access prohibited Fig 5 7 1 Address Format When Accessing External Memory Memory Spaces 101 Chapter 5 Bus Controller 102 Memory Spaces 000000004 4 67 04000000 Block5 64 08000000 TR 6 61 ME 0
230. cles must be inserted between this instruction and the next extension instruction Extension Instruction Specifications 397 Appendices MACI Signed multiply and accumulate operation instruction between immediate value and register Instruction Format Macro Name MACI imm Dn Assembler Mnemonic udf28 imm8 Dn imm8 is sign extended udf28 imm16 Dn imm16 is sign extended udf28 imm32 Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the 32 bit data that is obtained by sign extending imm multiplicand by the contents of Dn signed 32 bit integer multiplier adds the upper 32 bits and lower 32 bits of the resulting 64 bit product to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new result ing cumulative sum back in multiply and accumulate register MCRH and the lower 32 bits in multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Flag Chnz Condition SC Programming Cautions A non extension instruction that consumes at least two cycles must be inserted between th
231. connection when the DRAM byte specification is made through signals WE3 through 0 and Fig 5 8 33 shows an example of external memory connection when the DRAM byte specification is made through signals CAS3 through 0 The memory configuration is listed below Block 0 16 bit bus width 4 Mbit ROM 262144 words x 16 bits Block 1 32 bit bus width 4 Mbit DRAM 262144 words x 16 bits x 2 Block 2 8 bit bus width 1 Mbit SRAM 131072 words x 8 bits Description of Operation 120 Chapter 5 Bus Controller 0 31 24 D 7 0 WE OE CE A 16 0 1 Mbit SRAM WE OE CE A 16 0 1 Mbit SRAM D 15 0 UW LW OE 4 Mbit DRAM D 15 0 Uw LW OE 4 Mbit DRAM D 15 0 OE CE A 17 0 4 Mbit ROM MN103002A MN103002AYB Fig 5 8 32 Memory Connection Example When DRAM Byte Specification Is By WE 130 Description of Operation Chapter 5 Bus Controller D 31 24 WE OE 16 0 1 Mbit SRAM WE OE CE A 16 0 1 Mbit SRAM D 15 0 UCAS LCAS OE RAS WE 4 Mbit DRAM D 15 0 UCAS LCAS OE RAS WE 4 Mbit DRAM ESL A 17 0 4 Mbit ROM A 31 0 WE 3 0 CSO RAS CAS 3 0 MN103002A MN103002AYB Fig 5 8 33 Memory Connection Example When DRAM Byte Specification Is By CAS Description of Operation 131
232. control register if handshaking is specified the bus access ends in the cycle following the cycle in which the data acknowledge signal DK is asserted Figs 5 8 4 and 5 8 5 are timing charts for accesses with a 32 bit bus in synchronous mode with fixed wait state insertion In Fig 5 8 4 one wait state is inserted while in Fig 5 8 5 two wait states are inserted During a read the read enable signal RE is asserted 1 2 of a SYSCLK cycle after the start of the bus cycle and is negated 1 2 of a SYSCLK cycle before the end of the bus cycle During a write the write enable signals to 0 corresponding to the byte being written are asserted 1 2 of a SYSCLK cycle after the start of the bus cycle and are negated 1 2 of a SYSCLK cycle before the end of the bus cycle Therefore the minimum number of wait states in the bus cycle is one When writing byte 0 WEO is asserted and the data is output on D7 to 0 When writing byte 1 WE is asserted and the data is output on D15 to 8 When writing byte 2 WE2 is asserted and the data is output on D23 to 16 When writing byte 3 WE3 is asserted and the data is output on D31 to 24 108 Description of Operation Chapter 5 Bus Controller Sep c r Eg quy deg p MN rM CSn RE WE3 0 D31 0 C nec RD WT N SIZE1 0 it oe NEUEM lag 1 wait ok je 4 1 wait ok B Read cycle Write cycle
233. converter and I O ports in a 160 pin QFP This microcontroller is ideal for multimedia devices which must be able to process large volumes of data for audio stills video etc as well as for real time control equipment that requires fast and precise control When supplied with voltage of 3 3 V 0 165 V the MN103002A operates at 66 MHz and achieves performance of 66 MIPS MN103002AYB is a product with MN103002A package changed to CSP and includes the same function and performance as 103002 1 2 Features Low voltage high speed processing and low power consumption TYP Minimum instruction execution time 15 ns when supplied with 3 3 V and operating with an internal clock speed of 66 6 MHz Power consumption 500 mW when supplied with 3 3 V and operating with an internal clock speed of 66 6 MHz Compact and high performance CPU core Simple and highly efficient instruction set Number of basic instructions 46 number of extension instructions 7 number of addressing modes 6 Excellent coding efficiency with instructions that have a basic word length of one byte Supplied with Sophisticated high performance extension operation unit Supports 30 extension instructions including a fast multiplication instruction a sum of products opera tion instruction and a saturation operation instruction Load store architecture with 5 stage pipeline organization provides fast instruction execution Unique high speed
234. cs 13 4 2 Clock Timing Table 13 4 2 AC Characteristics 2 3 3 0 165 Vss 0V TA 20 C to 70 C CL 50 pF Allowable values Item Symbol Condition T Unit Min Typ Max Clock timing Refer to Fig 13 4 3 FRQS pin L level 30 0 38 External clock input cycle time texccyc FROS pin ns H level 60 0 76 7 External clock input pulse width high texcu LXEXCOYC S z ns 2 texccyc_ s E8 External clock input pulse width low texcL EE E ns E9 External clock input rising time texcr 5 ns I _ E10 External clock input falling time texcr 5 ns Ell System clock output pulse width transition time _ 6 SEES SYSCLK M 2 2 Syst lock out le ime SYSCLK 2 System clock output cycle ime SYSCLK iur NE enm m E13 System clock output pulse width high i Yes 2 9 is SYSCLK 2 2 14 System clock output pulse width low i 7 iN 9 s SYSCLK 2 E15 System clock output rising time SYSCLK ii b z 9 s E16 System clock output falling time SYSCLK T 2 _ 9 ae 346 Characteristics Chapter 13 Electrical Characteristics OSCI SYSCLK Fig 13 4 3 System Clock Timing AC Characteristics 347 Chapter 13 Electrical Character
235. ction MACIHU instruction MACB instruction MACIB instruction MACBU instruction MACIBU instruction 5 The category MCRH MCRL access instructions applies to the following instructions PUTCX instruction CLRMAC instruction GETCHX instruction GETCLX instruction 6 This problem can be avoided by an assembler after V3 1R9 At assembling nop instruction is automatically inserted between the mov and extended operation instructions 418 Extension Instruction Specifications lt 1 Note on the description of word half word data multiply and accumulate instructions and quick multiplica tion instructions common function unit is used to execute word half word data multiply and accumulate instructions and quick multiplication instructions Therefore when executing a word half word data multiply and accumu late instruction on the common function unit it is essential to not initiate the subsequent quick multiplication instruction until after execution of the word half word data multiply and accumulate instruction has been completed In addition one cycle must be inserted between the word half word data multiply and accumu late instruction and the subsequent quick multiplication instruction Word half word data 2 Function unit multiply and accumulate lt gt can be used instruction Quick multiplication instruction DEC Instruction i decoding EX O
236. d accumulate register lower 32 bits x 1 register This register is provided for multiply and accumulate operation instructions A multiply and accumulate operation instruction uses this register to store the low order 32 bits of the 64 bit multiply and accumulate operation result Multiply and accumulate overflow detect flag register 1 bit x 1 register This one bit register is set when an overflow occurs in a multiply and accumulate operation This flag is not cleared until the next CLRMAC instruction or PUTCX instruction is executed 386 Extension Instruction Specifications Appendices Extension Instruction Details PUTX Register transfer instruction for quick multiplication Instruction Format Macro Name PUTX Dm Assembler Mnemonic udf20 Dm Dm Operation This instruction transfers the contents of Dm to the quick multiply register MDRQ Flag Changes Change Condition Programming Cautions When ud 20 Dm Dn is operated Dn is ignored The operations of ud 20 imm8 Dn udf20 imm16 Dn and udf20 imm32 Dn not as sured In addition a system error interrupt does not occur in these cases Extension Instruction Specifications 387 Appendices PUTCX Multiply and accumulate register transfer instruction Instruction Format Macro Name PUTCX Dm Dn Assembler Mnemonic 21 Dm Dn Operation This instruction transfers the contents of Dm to the multiply and acc
237. de and the number of wait states to be inserted for external memory space block 0 Bit No Bit name Description 2 BOBM Block 0 bus mode 0 Synchronous mode synchronized with SYSCLK 1 Asynchronous mode synchronized with MCLK BOWCO Number of block 0 wait state insertions LSB 9 BOWCI Number of block 0 wait state insertions 10 BOWC2 Number of block 0 wait state insertions 11 BOWC3 Number of block 0 wait state insertions 12 BOWC4 Number of block 0 wait state insertions MSB The relationship between the value of BOWC4 to 0 and the number of wait states is shown below 1 When not using the in circuit emulator PX ICE103002 Synchronous mode Asynchronous mode 01 1 1 number of wait states number of wait states counted by SYSCLK counted by MCLK Basic bus cycle 00000 Setting prohibited 00001 1 wait states 00010 2 wait states x0000 Setting prohibited 00011 3 wait states x0001 1 wait states x0010 2 wait states 11111 31 wait states x0011 3 wait states 5 Setting prohibited 1111 15 wait states Setting prohibited Setting prohibited 3 wait states 3 wait states Continued 90 Description of Registers Chapter 5 Bus Controller Continued 2 When using the in circuit emulator PX ICE103002 1 When using the emulation function Synchronous mode Asynchronous mode BOBM 0 1 number of wait states number of wait states counted by SYSCLK co
238. dge function DMA channel 1 transfer addressing mode on source side LSB DMA channel 1 transfer addressing mode on source side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 1 transfer addressing mode on destination side LSB DMA channel 1 transfer addressing mode on destination side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 1 transfer direction Direction of external device that supports the acknowledge function in a one bus cycle transfer 0 Source 1 Destination DMA channel 1 transfer mode LSB DMA channel 1 transfer mode MSB 00 Burst transfer 01 Single word transfer 10 Intermittent transfer 11 Setting prohibited channel 1 transfer unit LSB DMA channel 1 transfer unit MSB 00 8 bits 01 16 bits 10 32 bits 11 Setting prohibited DMA channel 1 DMR signal mode Always set to 1 DMA channel 1 DMA transfer enable 0 DMA transfer disabled 1 DMA transfer enabled DMA channel 1 DMA transfer request flag Automatically set when a startup source is generated automatically reset after one transfer operation in single word transfer mode after all transfers have been completed in intermittent transfer or burst transfer mode or in the event of a forced termination 0 No request 1 Request Note that the external request sources differ from those in DMA x control registers 2 and 3 142 Description of DMA Registers Chapter 6 Controller
239. dition setting LSB 1 IROTGI IRQO pin trigger condition setting MSB 00 Low level 01 High level 10 Negativeedge 11 Positive edge 2 IR1TGO IRQI pin trigger condition setting LSB 3 IRITG1 IRQI pin trigger condition setting MSB 00 Low level 01 High level 10 Negative edge 11 Positive edge IR2TG0 2 pin trigger condition setting LSB 5 IR2TG1 2 pin trigger condition settin g MSB 00 Low level 01 High level 10 Negative edge 11 Positive edge IR3TGO IRQ3 pin trigger condition setting LSB 7 IR3TGI pin trigger condition setting MSB 00 Low level 01 High level 10 Negative edge 11 Positive edge 8 IR4TGO pin trigger condition setting LSB 9 IR4TG1 pin trigger condition setting MSB 00 Low level 01 High level 10 Negative edge 11 Positive edge 10 IRSTGO IRQS pin trigger condition setting LSB 11 IR5TG1 IRQ5 pin trigger condition setting MSB 00 Low level 01 High level 10 Negative edge 11 Positive edge lt Continued gt 200 Description of Registers Chapter 7 Interrupt Controller Continued Bit No Bit name 12 IR6TGO 13 IR6TGI 14 IR7TGO 15 IR7TGI Description IRQ6 pin trigger condition setting LSB IRQ6 pin trigger condition setting MSB 00 Low level 01 High level 10 Negativeedge 11 Positive edge IRQ7 pin trigger condition setting LSB pin trigger condition setting MSB 00 Low level 01 High level 10 Negative edge 11 Positive edge Mainta
240. e Capture register mode Double buffer mode Load timing Single buffer mode Compare capture register A TM6CA 6 Compare capture register Initialization flag TM6LDE Compare register mode Compare register buffer Register Data bus Match interrupt request Register read Fig 9 4 3 Timer 6 Compare Capture Register Block Diagram PWM output section when timer 6 is set to PWM mode with additional bits Overflow Tome T Additional bit control bp15 to 8 bp7 to 2 Compare capture register bpl5 to 8 bp to 2 Compare register buffer TM6CA TM6CB TM6OUTA TM6O0UTB PWM output Fig 9 4 4 PWM Output Section Block Diagram 228 Block Diagram Chapter 9 16 bit Timers Up down counter 9 5 List of Functions Table 9 5 1 16 bit Timer Functions Down counter Up counter O Event counting Rising edge Dual edge Number of compare capture register 2 Toggled output Variable cycle duty Fixed cycle 2 Underflow Overflow Compare capture A Compare capture B 2 Either single edge or both edges One shot output O Initiation source of ascaded connection Compare capture List of
241. e 8 SCnTOE 9 SCnOD 10 SCnMDO 11 SCnMD1 12 SCnIIC 13 SCnBKE 14 SCnRXE 15 SCnTXE Description SBTn pin output control 0 When the internal clock is selected the SBTn pin is an output only while transmission is in progress the SBTn pin is an input when in standby mode or when an external clock is selected 1 When the internal clock is selected the SBTn pin is always an output the SBTn pin is an input when an external clock is selected Transmission reception bit sequence selection 1 From MSB 0 From LSB Protocol selection LSB Protocol selection MSB 00 Start stop synchronous mode 01 Clock synchronous mode 1 the SBOn pin is used as a data output and the SBIn pin is used as a data input 10 mode 11 Clock synchronous mode 2 the SBOn pin is used as a data input and output and input on the pin is ignored I2C mode selection 0 The stop sequence is output when this bit is changed from 1 to 0 1 The start sequence is output when this bit is changed from 0 to 1 Sending break 0 Do not send break 1 Send break The SBOn pin is fixed to output 0 Reception operation enable 0 Disabled 1 Enabled Transmission operation enable 0 Disabled 1 Enabled Description of Registers 285 Chapter 11 Serial Interfaces 11 4 2 Serial n Interrupt Mode Register n 0 1 Register symbol SCnICR Address x 34000804 n 0 x 34000814 1 Purpose Th
242. e WDCNE flag is set to 1 and the watchdog operation is enabled a nonmaskable interrupt is generated if a watchdog timer overflow occurs When an overflow occurs the watchdog timer overflow output is output to the WDOVF pin Pulse output or level output can selected through the WDOVT flag The value output on the WDOVF pin can be read The watchdog timer overflow output is cleared by writing a 1 to the WDRST flag or by reset pin input Overflow Watchdog timer count value Counter reset by writing 1 to the WDRST flag 4 4 Nonmaskable interrupt 4 WDOVF pin output when pulse EE ERES output is selected 1 SYSCLK 255 cycle width WDOVF pin output when level output is selected i 4 Reset by writing a 1 to 3 972 ms to 1016 801 ms the WDRST flag when FRQS is high and the oscillating frequency is 16 5 MHz or by reset pin input Fig 10 5 3 Operation Diagram 3 Watchdog Operation Before setting the WDCNE flag to 1 write a 1 to the WDRST flag to reset the counter When switching to HALT or SLEEP mode set the WDCNE flag to 0 to turn off the watchdog timer 274 Description of Operation Chapter 10 Watchdog Timer 10 5 3 Self reset Operation The chip resets internally when a 1 is written to the CHIPRST bit in the RSTCTR register The oscillation stabilization wait operation is not performed The reset generated by writing the CHIPRST flag is an internal re
243. e instructions Word half word data MCRH MCRL access Insert at least three cycles Multiply and accumulate instruction 1 instruction 5 Following between the instructions Byte data Multiply and accumulate Insert at least one cycle Multiply and accumulate instruction 2 operation instruction 4 Following between the instructions Byte data MCRH MCRL access Insert at least two cycles Multiply and accumulate instruction 2 instruction 5 Following between the instructions Extension Operation Insert at least one cycle mov regs SP instruction 5 Followin g instruction between the instructions 6 1 The category Word half word data multiply and accumulate instructions applies to the following instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instruction MACIHU instruction 2 The category byte data multiply and accumulate instructions applies to the following instructions MACB instruction MACIB instruction MACBU instruction MACIBU instruction 3 The category Quick multiplication instructions applies to the following instructions MULA instruction MULQI instruction MULQU instruction MULQIU instruction 4 The category Multiply and accumulate operation instructions applies to the following instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instru
244. e operation instruction between immediate value and register Instruction Format Macro Name MACIH imm Dn Assembler Mnemonic ud 30 imm8 Dn imm8 is sign extended udf30 imm16 Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the 16 bit data that is obtained by sign extending imm multiplicand by the contents of Dn signed 16 bit integer multiplier adds the upper 32 bits and lower 32 bits of the resulting 64 bit product to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new result ing cumulative sum back in multiply and accumulate register MCRH and the lower 32 bits in multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Programming Cautions non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction The operations of ud 30 imm32 Dn is not assured In addition a system error interrupt does not occur in these cases 400 Extension Instruction Specifications Appendices MACB S
245. ed Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of ud 09 imm8 Dn udf09 imm16 Dn and 14 09 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases Extension Instruction Specifications 4 7 Notes on Extension Operation Programming The extension function unit is equipped with the following dedicated registers that it uses to store the results of quick multiplication operations and multiply and accumulate operations 1 Notes on instruction description These programming notes address instruction descriptions as well as instruction placement and combina tions Failure to heed these notes will result in misoperation A list of these notes is shown below Table E 1 List of Notes V Placement Preceding instruction Following instruction relationship Notes Word half word data Quick multiplication Insert at least one cycle Multiply and accumulate instruction 1 instruction 3 Following between the instructions Word half word data Multiply and accumulate Insert at least two cycles Multiply and accumulate instruction 1 instruction 4 Following between th
246. ed when a capture occurs in TM6CA Always returns 0 One shot operation enable flag Enables disables the halt of timer operation when TM6BC and TM6CA match 0 Disables one shot operation 1 Enables one shot operation If TM6BC and TM6CA match the TM6CNE flag is reset and the timer stops External trigger start enable flag Enables disables timer start by an external trigger 0 Disables timer start by an external trigger The trigger input is ignored 1 Enables timer start by an external trigger When the specified edge is input to the TM6IOB pin the flag is set and the timer starts The timer starts on the edge that is the opposite of the one selected by the TM6BEG flag in the TM6MDB register Always returns 0 Resolution selection LSB Resolution selection MSB Valid only in additional bit style PWM mode 00 10 bits basic output 8 bits additional bits 2 bits 01 11 bits basic output 8 bits additional bits 3 bits 10 12 bits basic output 8 bits additional bits 4 bits 11 14 bits basic output 8 bits additional bits 6 bits Description of Registers 233 Chapter 9 16 bit Timers Continued Bit No Bit name 13 TM6PME 14 TM6LDE 15 TM6CNE Description Timer 6 PWM output waveform selection flag This bit selects the PWM output waveform for timer 6 0 Normal waveform 1 PWM output with additional bits The PWM waveform is output with the resolution that is set in and
247. en an attempt is made to execute an unimplemented instruction The Ist line to 2nd line of System error interrupts System error interrupt occurs when an unaligned memory access an unimplemented instruction is executed or other fatal error occurs Y An Interrupt Status Register Deleted Following note is added Do not change the interrupt enable IE in PSW during non maskable interrupt proccessing In Hardware interrupt processing sequence The PC the return address is saved to the stack SP 4 The contents of the PSW are saved to the stack SP 8 The contents of the PSW are updated IE is cleared and In the case of an NMI IM2 to IMO are undefined Step 1 Step 2 Step 3 In Hardware interrupt processing sequence Step 1 contents of the PSW are saved to the stack SP 8 Step 2 PC the return address is saved to the stack SP 4 Step 3 The contents of the PSW are updated IE is cleared and In the case of non maskable interrupts IM2 to IMO are undefined In the number 3 of Example of preprocessing by the interrupt handler 12 In the case of an NMI In the number 3 of Example of preprocessing by the interrupt handler a In the case of non maskable interrupts In Fig 2 8 1 Interrupt C 7 In Fig 2 8 1 ae Interrupt 1 Program In the mathematical expression 15 888 msec
248. endix D Instruction Set List of Instructions Code Length Number of Cycles Code Length Number of Cycles MOV Dm S0 dl I e eue WA ele _ _ j N t Ine 90 RN AA 4 o T2 AWN TN DWNAWNIWAAYN N The number of execution cycles was calculated under the following conditions 1 No pipeline extension 2 2 cycles for the instruction fetch 1 cycle for the load store Instruction Set 377 Appendices t n 7 6 3 4 6 2 3 6 722 n dec 4 d 6 2 3 1 4 1 6 2 2 3 26 E 3 4 6 3 lt 4 6 2 3 d Number of registers with regs specification 20 Number of registers with regs specification 1 Number of registers with regs specification 2_ Number of registers with regs specification 3 _ Number of registers with regs specification 4 Number of registers with regs specification 7__ Number of registers with regs specification 8 _ Number of registers with regs specification 9 _ _ Number of registers with regs specification 11 __ Number of registers with regs specification 0 Number of registers with regs specification 21 _ Number of registers with regs specification 2 Number of registers with regs specification 2 3
249. equency of the oscillator to external devices 3 2 Features The features of the CG are described below Flexible clock control Supports self excitation external excitation input frequency 13 0 MHz to 33 3 MHz When the input frequency is 16 6 MHz or less a clock that is four times the input frequency is supplied as the CPU clock if the input frequency exceeds 26 MHz a clock that is twice the input frequency is supplied The maximum frequency for MCLK is 66 6 MHz When the input frequency is 16 6 MHz or less a clock that has the same frequency as the input frequency is supplied as the peripheral clock IOCLK if the input frequency exceeds 26 MHz a clock that is one half the input frequency is supplied The maximum frequency for IOCLK is 16 6 MHz 52 Overview Features Chapter 3 Clock Generator Block Diagram IOCLK fio MCLK fc 13 0 MHz to 16 6 MHz 26 0 MHz to 33 3 MHz Fig 3 3 1 Clock Generator Block Diagram 5 3 Chapter 3 Clock Generator 3 4 Description of Operation 3 4 4 Input Frequency Setting The CG input frequency range is set through the external input pin FRQS When the input frequency fosci is generated using an oscillator or resonator such that 13 0 MHz lt fosci 16 6 MHz set FRQS high When the input frequency fosci is generated using an oscillator or resonator such that 26 0 MHz x fosci x 33 3 MHz set FRQS low Using an oscillator or resona
250. equest or a store request directed at internal 1 or external memory from the CPU before the write from the store buffer is completed the execution of that request is delayed 5 8 3 Accessing the Internal I O Space 5 8 3 1 Synchronous Mode Access Accesses to the internal I O space I O register are performed through the I O bus with the bus controller control ling the interface for read write requests from the CPU In synchronous mode accesses between the bus controller and the internal I O space are executed in synchronization with IOCLK and with the number of wait states 0 or 1 set in the bus control register Fig 5 8 1 shows the timing chart when accessing the internal space with no wait states and Fig 5 8 2 shows the timing chart when accessing the internal I O space with one wait state IOCLK Se Ae 10031 0 pom Read cycle Write cycle 0 wait ok 0 wait ok Fig 5 8 1 Internal Space Access Synchronous Mode No Wait OK Description of Operation 105 Chapter 5 Bus Controller IOCLK IOA11 0 IOD31 0 QC pone F 1 wait ok fe 1 wait ok gt Read cycle Write cycle Fig 5 8 2 Internal Space Access Synchronous Mode 1 Wait OK During a read the address 11 to 0 and the read request signal RR are output in synchronization with the rising edge of IOCLK Then after 1
251. er DMOSRC 32 X XXXXXXXX 32 x 32000108 DMAO destination address register DMODST 32 X XXXXXXXX 32 x 3200010C DMAO transfer word count register DMOCNT 16 x 0000 16 x 3200010E DMAO intermittent cycle register DMOCYC 8 x 00 8 x 32000200 control register DMICTR 32 00000000 8 16 32 32000204 source address register DMISRC 2 X XXXXXXXX 32 32000208 DMAI destination address register DMIDST 32 x XXXXXXXX 32 x 3200020C transfer word count register DMICNT 16 x 0000 16 x 3200020E intermittent cycle register DMICYC 8 x 00 8 32000400 DMA2 control register DM2CTR 32 x 00000000 8 16 32 x 32000404 DMA2 source address register DM2SRC 32 X XXXXXXXX 32 32000408 destination address register DM2DST 32 X XXXXXXXX 32 3200040 transfer word count register DM2CNT 16 x 0000 16 x 3200040E DMA2 intermittent cycle register DM2CYC 8 x 00 8 x 32000800 DMA3 control register DM3CTR 32 x 00000000 8 16 32 x 32000804 DMA3 source address register DM3SRC 32 X XXXXXXXX 32 32000808 DMA3 destination address register DM3DST 32 X XXXXXXXX 32 x 3200080c DMA3 transfer word count register DM3CNT 16 x 0000 16 x 3200080E DMA3 intermittent cycle register DM3CYC 8 x 00 8 138 Description of DMA Registers Chapter 6 Controller 6 3 1 DMA Control Registers DMA control register 0 Register symbol DMOCTR Address x 32000100 Purpose Sets the transfer parameters for DMA channel 0
252. eration of Timer 4 5 under cascaded connection condition Select IOCLK as clock source Under condition TM5B x 0000 after TM4BC become underflow TM4BC is set x FFFF and TM5BC is decremented by one Under condition TMSBC x 0000 after TM4BC become underflow the value of TM4BR and TMSBR are loaded into TM4BC and TMSBC respectively and interrupt of timer5 occurs Value i Yers Yoon Xen X 0001 TM4BR value It is not set TM4BR value 1 Interrupt request TM4IRQ Value in TMsBc 00 f x 0000 TMSBR Kristi ate Interrupt request TMSIRQ D ECCE Fig 9 7 5 Operation on Cascaded Connection 246 Description of Operation Chapter 9 16 bit Timers 9 7 2 Timer 6 Timer 6 equips an up counter and 2 compare capture register Each compare capture registers can be used as either of a compare register or a capture register respectively 9 7 2 1 Compare Register Setting Please take the following steps before the initialization of the timer 6 to use compare capture register A B of timer 6 as a compare register For now compare capture register A is used in the example but the steps are same for compare capture register B 1 Set the mode of compare capture register A Set TM6MDA as following TM6A02 1 0 optional TMGACE 0 Inhibit capture operation TM6AEG optional TM6AMI 0 00 Compare regi
253. erations of ud 22 imm8 Dn udf22 imm16 Dn and udf22 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases 292 Extension Instruction Specifications MULQ Signed quick multiplication instruction between registers Instruction Format Macro Name MULQ Dm Dn Assembler Mnemonic udf00 Dm Operation This instruction performs multiplication quickly using the multiplier in the extension function unit The instruction multiplies the contents of Dm signed 32 bit integer multiplicand by the contents of Dn signed 32 bit integer multiplier and then stores the upper 32 bits of the 64 bit result in the quick multi ply register MDRQ and the lower 32 bits in Dn The range of significant values for the multiplicand that is stored in Dm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the absolute value of the contents that are stored in Dm the quicker the result of the operation can be derived Flag Changes Flag Change Undefined Undefined 1 when the MSB of the lower 32 bits of the result is 1 0 in all other cases 1 when the lower 32 bits of the result are all 0 0 in all other cases Programming Cautions There is a one instr
254. erit ita de e E bete i Reo 299 1125 67 Timing Chart 3 dere eerie e ates 300 Eig 11 557 Timing Chart 4 eee ein eade tier eto ledit ie teli iced 301 Fig T 8 Timing Ch rt 302 Eig 11 5 9 Timing Chart 6 eee reiten ti ente eee IER eh pid 302 Fig i11 5 10 Timing Chart entere ie nd 303 Fig 11 5 11 Timing Chart 8 oe out iota 303 Fig 1155 12 Timing Chart 9 vcd sette e c Rak 304 Fig 11 5 13 Timing Chart 10 306 Fig 11 5 14 Timing Chart 11 ein team 307 Chart 12 qe abet RO Oo 308 Fig 11 5 16 Serial Interface 2 Connection 309 Chapter 12 O Ports Fig 12 2 1 Port 0 Block Diagram P07 to 00 tees 316 Fig 12 3 1 Port 1 Block Od E 320 Fig 12 4 1 Port 2 Block Diagram 21 20 0 tees 324 Fig 12 4 2 Port 2 Block Diagram P27 to 22 iuvat tud 325 Fig 12 5 1 Port 3 Block Diagram 31 30 22 00000002 2 00000 2 330 Chapter 13 Electrical Characteristics Fig 13 3 1 Recommended Self excited Oscillation Circuit 343 Fig 13 4 1 Reset Timing 1 345 Fig 13 4 2 Reset Timing 2 b tote 34
255. errupt request flag SYSEF This flag cannot be cleared by writing to the non maskable interrupt control register NMICR This flag can be cleared by generating a reset interrupt by setting the RST pin to L level or by the self reset which is generated by writing to the reset control register RSTCTR of the watchdog timer m No change No change Flag is cleared Non maskable interrupts cannot be generated by software a Description of Registers 169 Chapter 7 Interrupt Controller 7 4 2 Group Interrupt Control Registers GnICR n 2 to 30 These registers are used to control level interrupts in each group from 2 to 30 This register confirms the group interrupt level as well as the enabling request and detection of interrupts within the group This page describes the common elements of G2ICR through G30ICR The level interrupt control registers for group 2 to group 30 are described individually on the pages that follow When reset Access Bit No Bit name Description 0 to 3 IDO to ID3 Group n interrupt detection register This register stores the logical product of the IE and IR bits If an interrupt that is enabled by the IE bits is generated the ID bit corresponding to the interrupt is set to 1 4to7 IRO to IR3 Group n interrupt request register This register stores interrupt requests Each bit corresponds to terrupt After receiving the interrupt these
256. ers essent 139 6 3 2 DMA Source Address Registers sse 147 6 3 3 DMA Destination Address Registers 00 147 6 3 4 Transfer Word Count Registers 148 6 3 5 DMA Intermittent Cycle Registers essere 148 6 4 Description of 2 1 1 4 0440 701 2 0000000000000002050000 000040440000 0000008444844444 144 149 6 4 1 Transter Types cen edere ed tbe ERE 149 6 4 2 Transfer Mode tee cte el GERE RE EUER ERE eR 149 6 4 2 1 Single word Transfer 149 6 4 2 2 Burst Transfer Mode sse 150 6 4 23 Intermittent Transfer Mode 150 6 4 3 Priority Ranking iie ate s a EROR ee e LE EA IER 151 6 4 4 Transfer Start End ees 151 6 4 5 Notes on Programming 2 1 0 0000 0 000000 tnter ettet 152 6 4 6 DMA Transfer Examples esses eterne tens 155 6 4 6 1 One Bus Cycle Transfers 0 c ccccscscseccsscsssesssecsssessssesesesssceeeseas 155 6 4 6 2 Two Bus Cycle Transfers 159 vi Chapter 7 7 1 7 2 7 3 7 4 Interrupt Controller chat eid 162 Feature m M 162 Configuration eed te dam dcs pese Leer de EM 163 7 3 System Diagramm medecin recepere teret etes e Pb edat decedere 1
257. escription 0 1015 DMnCT DMA transfer word count x 0000 1 transfer X FFFF 65536 transfers maximum transfer count 6 3 5 Intermittent Cycle Registers Register symbol DMnCYC 0 1 2 3 Address x 3200010E n 0 3200020 n 1 x 3200040E n 2 x 3200080E 3 Purpose These registers set the intermittent transfer cycle count for DMA channels 0 to 3 Bit position Bit name Description 0 to 7 DMnCYC DMA intermittent cycle count x 00 1 intermittent transfer Minimum number of intermittent cycles releases bus to CPU after one DMA transfer X FF 256 intermittent transfers Maximum number of intermittent cycles releases bus to CPU after 256 DMA transfers 148 Description of DMA Registers 6 4 1 6 4 2 6 4 2 1 Chapter 6 DMA Controller 6 4 Description of Operation Transfer Types Table 6 4 1 Devices to Which Transfer Is Possible Transfer source transfer destination Internal External device with acknowl edge function External memory Internal VO 2 bus cycles 2buscycles Not possible External memory 2 bus cycles 2 bus cycles 1 bus cycle External device with acknowledge function Not possible 1 buscycles Not possible DMA registers etc These registers cannot be the target of a DMA transfer Transfer Mode Single word Transfer Table 6 4 1 li
258. ess x 34000809 0 34000819 1 This register reads in the reception data i BOSCH ROM SCn SCn SCn SCn SCn EM RXB6 P RXB4 2 ee When reset 0 Reception data is gotten by reading this buffer at the end of reception In the case of 7 bit transfer the MSB bit 7 is 0 Description of Registers 287 Chapter 11 Serial Interfaces 11 4 5 Serial n Status Register n 0 1 Register symbol Address Purpose 10 to 15 288 Description of Registers SCnSTR x 3400080C n 0 x 3400081C n 1 This register indicates the status of serial interface n Bit name SCnOEF SCnPEF SCnFEF SCnRBF SCnTBF SCnRXF SCnTXF SCnSTF SCnSPF Description Overrun error indication 0 No error 1 Overrun error occurred Parity error indication 0 No error 1 Parity error occurred Framing error indication 0 No error 1 Framing error occurred Always returns 0 Reception buffer status indication 0 Reception buffer empty 1 Data exists in the reception buffer Transmission buffer status indication 0 Transmission buffer empty 1 Data exists in the transmission buffer Reception status indication 0 Waiting for reception 1 Reception in progress Transmission status indication 0 Ready for transmission 1 Transmission in progress I2C start sequence detection Cleared by reading SCnRXB or by wr
259. est flag 0 No interrupt requested 1 Interrupt requested 57 Always returns 0 8 SCOTIE Serial 0 transmission interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 GI7LVO Group 17 interrupt priority level register LSB 13 GI7LVI Group 17 interrupt priority level register 14 GI7LV2 Group 17 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 186 Description of Registers Chapter 7 Interrupt Controller 7 4 2 16 Group 18 Interrupt Control Register Register symbol G18ICR Address x 34000148 Purpose This register is used to enable group 18 interrupts and to confirm interrupt requests and detection When reset Bit No Bit name Description 0 SCIRID Serial 1 reception interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1 t03 Always returns 0 4 SCIRIR Serial 1 reception interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 SCIRIE Serial 0 reception interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G18LVO Group 18 interrupt priority level register LSB 13 GI8LV1 Group 18 interrupt priority level register 14 GISLV2 Group 18 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 187 Chapter 7 Interrupt Controller 7 4 2 17 Group 19 Interru
260. formed for the range containing these significant values In short if the number of imm bits is 16 or less the operation results will be derived faster Following sentences are added Programming Cautions of MACIH The operations of ud 30 imm32 Dn is not assured In addition system error interrupt does not occur in these cases Following sentences are added to Programming Cautions of MACIB The operations of 14432 imm16 Dn and udf32 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases MACHU Signed half word data multiply and accumulate operation i instruction between registers MACHU Unsigned half word data multiply and accumulate operation instruction between registers Following sentences are added to Programming Cautions of MACIHU The operations of udfu31 imm32 Dn is not assured In addition a system error interrupt does not occur in these cases i MACBU Signed byte data multiply and accumulate operation instruction between registers MACBU Unsigned byte data multiply and accumulate operation instruction between registers i Following sentences are added to Programming Cautions of MACIBU The operations of udfu33 imm16 Dn and udfu33 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases Following sentences are added
261. g Modes 384 Extension Instruction Specifications _ Appendices The notation that is used to express flag changes is described below Nochange Flag change Undefined 0 Reset 1 Flag is the general term that is used to refer to the four lowest bits in the PSW V 2 Extension Function Unit Register Set The extension function unit has the following dedicated registers in which it stores the results of quick multiplication operations and multiply and accumulate operations 31 0 Multiply Register MDRQ 3 0 Multiply amp Accumulate l Register Higher 31 0 Multiply amp Accumulate i RL Register Lower L ME 0 Multiply amp Accumulate MCVF Overflow Detect Flag Register Fig E 2 Extension Function Unit Register Set Extension Instruction Specifications 3 8 5 Appendices Multiply register 32 bits x 1 register This register is provided for high speed multiplication instructions A multiplication instruction uses this register to store the high order 32 bits of the 64 bit multiplication result Multiply and accumulate register higher 32 bits x 1 register This register is provided for multiply and accumulate operation instructions A multiply and accumulate operation instruction uses this register to store the high order 32 bits of the 64 bit multiply and accumulate operation result Multiply an
262. g for Bus Access by 16 bit Bus 2 22 02 204044014000 0 112 Fig 5 8 10 Timing for Access in Asynchronous Mode with 32 bit Bus FRQ 0 One Wait OK 113 Fig 5 8 1 1 Timing for Access in Asynchronous Mode with 32 bit Bus FRQ 1 Three Wait OK 114 5 8 12 Timing for Access Asynchronous Mode with 16 bit Bus FRQ 0 One Wait OK 115 Fig 5 8 13 Timing for Access in Asynchronous Mode with 16 bit Bus FRQ 1 Three Wait OK 116 Fig 5 8 14 RAS CAS Signal Timing When 0 117 5 8 15 RAS CAS Signal Timing When FRQ 1 sse 118 5 8 16 32 bit DRAM Read Write Timing When FRQ 0 One Wait 119 Fig 5 8 17 16 bit DRAM Read Write Timing When FRQ 0 119 Fig 5 8 18 32 bit DRAM Read Write Timing When FRQ 1 sse 120 5 8 19 16 bit DRAM Read Write Timing When 1 121 Fig 5 8 20 32 bit DRAM Page Mode Read Timing When 0 122 xiii lt gt Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig eine 122 16 bit DRAM Page Mode Read Timing When 0 asns 123 16 bit DRAM Page Mode Write Timing When 0
263. ge MN103002A QFP160 P 2828B 28 mm square 0 65 mm pitch MN103002AYB FLGA165 C 1111 11 mm square 0 8 mm pitch CSP Features Chapter 1 General 1 3 Block Diagram Bus controller 32 bit Instruction CPU core cache L Extended operation unit Data cache Clock and Interrupt control system control UE Fig 1 3 1 MN103002A MN103002AYB Block Diagram interface i Block Diagram 5 Chapter 1 General 1 4 Pin Descriptions Pin Assignments 1 4 1 Zid Sta 9Id via 14 51 ld L10 2Id Oia thd 60 Old 8 SSA 108 44 90d 9 504 SQ 704 0d Q 20 t0d A 00d 00 SSA 1SH 12 8OI9W L 92d VOISWL Sed OISWL ved OWL 23 22d led LL8S OILAL 024 0186 OIOW L SSA S19 2185 2085 2198 1894 1095 Has 054 0085 0195 gt E N oodg m o oO d 0 58 Fig 1 4 1 MN103002A Pin Assignment Diagram Pin Descriptions 6 Chapter 1 General Table 1 4 1 MN103002A Pin Assignments No Pin name No Pin name No Pin name Pin name 1 AO 41 IRQO 81 VDD D15 P17
264. gister LSB 13 G24LV1 Group 24 interrupt priority level register 14 G24LV2 Group 24 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 192 Description of Registers Chapter 7 Interrupt Controller 7 4 2 22 Group 25 Interrupt Control Register Register symbol G25ICR Address x 34000164 Purpose This register is used to enable group 25 interrupts and to confirm interrupt requests and detection When reset Bit No Bit name Description 0 IQ2ID External interrupt 2 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 IQ2IR External interrupt 2 interrupt request flag 0 No interrupt requested 1 Interrupt requested 507 Always returns 0 8 IQ2IE External interrupt 2 interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G25LVO Group 25 interrupt priority level register LSB 13 G25LVI Group 25 interrupt priority level register 14 G25LV2 Group 25 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 193 Chapter 7 Interrupt Controller 7 4 2 23 Group 26 Interrupt Control Register Register symbol G26ICR Address x 34000168 Purpose This register is used to enable group 26 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 IQ3ID External interrupt
265. hanged during the counter operation is performed is loaded at the first underflow after the changing Steps for operation termination 1 Stop count operation Count operation stops when 0 is set to TMnCNE of TMnMD register 2 Initialization of timer if it is necessary Load TMnBR value into TMnBC as initial value by giving 1 to TMnLDE of TMnMD register Binary counter keeps the operation condition value unless TMnLDE is set to 1 after the termination of the timer Le Count can be start from the interrupted condition when TMnCNE is given a value 1 again Input pulse width must be more than IOCLK x 1 5 since IOCLK being sampled at pin input a Event count operation is inhibited when IOCLK is terminated HALT STOP mode Pin input TMnIO Counting clock V V Value in TMnBC 0001 0000 value value 1 Interrupt request signal TMnIRQ Fig 9 7 4 Event Counting Operation 244 Description of Operation Chapter 9 16 bit Timers 9 7 1 3 Cascaded Connection Timer 4 5 can be used as pure 32 bit timer by cascading Timer 5 as upper half and Timer 4 as lower half Please use the following setting to use 16 bit timer under cascaded condition 1 Setting of the division ratio Set the division ratio into TMnBR e g Case timer 4 5 is used as 32 bit timer and interrupt cycle is set as x 12345678 To have the given interrupt cycle TMnBR must be set as x 1
266. he SBOn is fixed to output 0 Reception operation enable 0 Disabled 1 Enabled Transmission operation enable 0 Disabled 1 Enabled Chapter 11 Serial Interfaces 11 4 7 Serial 2 Interrupt Mode Register Register symbol SC2ICR Address x 34000824 n 0 Purpose This register selects the sources for transmission interrupts reception interrupts and DMA startup requests for serial interface 2 Bit No Bit name Description 0 SC2RI Reception interrupt source selection 0 Reception end 1 Reception end with error Always returns 0 2 SC2RES Reception error interrupt source selection 0 Interrupt request when an overrun parity or framing error occurs 1 Interrupt request when a parity error occurs Always returns 0 4 SC2TI Transmission interrupt source selection 0 Transmission end 1 Transmission buffer empty 5 SC2TD DMA startup source selection for transmission 0 Transmission end 1 Transmission buffer empty 607 Always returns 0 Description of Registers 29 Chapter 11 Serial Interfaces 11 4 8 Serial 2 Transmission Buffer Register symbol SC2TXB Address x 34000828 Purpose This register writes the transmission data to serial interface 2 SC2 SC2 name TXB7 TXB6 T Data is transmitted by writing it to this buffer 11 4 9 Serial 2 Reception Buffer Register symbol SC2RXB Address x 34000829 Purpose This register reads in the reception data ENNEA 5 2 W
267. he remaining source is reserved Interrupt group Interrupt control Interrupt External interrupts Eight external pin interrupts as well as timer serial interface and other peripheral Group 30 interrupts are allocated to this group 27 sources Interrupt group control ES Interrupt controller INTC Fig 2 7 1 Overview of the Interrupt System Interrupt Interrupt Functions 3 5 Chapter 2 CPU 2 7 2 l nterrupt related Registers 2 7 2 1 Processor Status Word Register PSW Interrupt Enable and Interrupt Mask Level are the two interrupt related flags in the Processor Status Word register PSW These flags can be both read and written For details on the PSW refer to section 2 3 1 Register Set IE Interrupt Enable This flag enables all interrupts except for nonmaskable interrupts and reset interrupts Interrupts are en abled when IE 1 When the system is reset IE 0 Once an interrupt is accepted IE is cleared interrupts are prohibited Set IE when accepting nested interrupts within an interrupt handler IM2 to IMO Interrupt Mask These bits hold the current interrupt mask level When IE 1 the CPU accepts interrupts of a level higher than IM Level 0 000 is set when the system is reset or started up The following table shows the relationship between the mask level and the acceptable interrupt levels Table 2 7 1 Relationship between Mask Levels
268. hen reset EE Aces R Reception data is gotten by reading this buffer at the end of reception In the case of a 7 bit transfer the MSB bit 7 is 0 292 Description of Registers Chapter 11 Serial Interfaces 11 4 10 Serial 2 Status Register Register symbol Address Purpose SC2STR x 3400082C This register indicates the status of serial interface 2 Bit name SC2OEF SC2PEF SC2FEF SC2CTS SC2RBF 5 2 SC2RXF SC2TXF Description Overrun error indication 0 No error 1 Overrun error occurred Parity error indication 0 No error 1 Parity error occurred Framing error indication 0 No error 1 Framing error occurred CTS status indication 0 CTS pin is low 1 CTS is high Reception buffer status indication 0 Reception buffer empty 1 Data exists in the reception buffer Transmission buffer status indication 0 Transmission buffer empty 1 Data exists in the transmission buffer Reception status indication 0 Waiting for reception 1 Reception in progress Transmission status indication 0 Ready for transmission 1 Transmission in progress Description of Registers 203 Chapter 11 Serial Interfaces 11 4 11 Serial 2 Timer Setting Register Register symbol 5 2 Address x 3400082D Purpose This register sets the internal timer for serial interface 2 mw 7 932 5 2 SC2 5 2 S
269. hieve faster loop control Loop Address Register 32 bit x 1 This register is provided for the branch instruction Lcc and is used by the SETLB instruction to store the fetch target address Programming Model 2 2 3 2 Control Registers In the memory mapped I O method used in the MN103002A MN103002A YB the peripheral circuit registers are located in the address space between addresses x 20000000 and x 3FFFFFFF The registers listed below are described in this section For details on other control registers refer to the chapters that explain the various built in peripheral functions Table 2 3 1 List of Control Registers Address Name Register symbol Number of bits Initial value Access size x 20000000 Interrupt vector register O IVARO 16 16 x 20000004 Interrupt vector register 1 IVARI 16 x XXXX x 20000008 Interrupt vector register 2 16 X XXXX x 2000000C Interrupt vector register 3 16 X XXXX x 20000010 Interrupt vector register 4 16 x 20000014 Interrupt vector register 5 16 x XXXX 16 Programming Model 19 Chapter 2 CPU Interrupt Vector Registers Register symbol Addresses x 20000000 0 20000004 1 x 20000008 n 2 x 2000000C 3 x 20000010 4 x 20000014
270. his bit always returns a 0 when it is read 6 DCWTMD Data cache write mode This bit specifies the data cache write mode 0 Write back mode 1 Write through mode 7 INTBR Level interrupt base address setting This bit specifies the interrupt vector base address that is set in the interrupt vector register IVARn n 0 to 6 when a level interrupt is generated 0 x 40000000 1 x 50000000 8 9 ICWMD Instruction cache way mode Bit 8 specifies the operation mode for way 0 and bit 9 specifies the operation mode for way 1 0 Normal operation 1 No refill is performed even if a cache miss occurs 10 11 reserved 12 13 DCWMD Data cache way mode Bit 12 specifies the operation mode for way 0 and bit 13 specifies the operation mode for way 1 0 Normal operation 1 No refill is performed even if a cache miss occurs 14 15 reserved When invalidating a cache switching the write mode or performing a way operation it is necessary to first disable the target cache and then check the busy bit to ensure that the cache is not in operation That cache opera tion has halted should also be confirmed when accessing cache data or before performing a purge operation Description of Registers 63 Chapter 4 Caches 4 5 Description of Operation 4 5 1 instruction Cache 4 5 1 1 Initialization The instruction cache is disabled when the system is reset To enable the instruction cache first set the instruction cache invalidate bit
271. ics Corporation Colophon Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Corrections MULQU MULQIU MULQIU DO Dn Do DO MULQIU McsT9 Do Code Length Length 2 2 3 4 6 Number of Cycles jm Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse Dn is a value that can be expresse by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 by 3 or 4 bytes by 2 or 1 bytes or Dn 0 Corrections MULQIU MULQIU MULQIU xi Dm is a value which can be expressed with 2 bytes to 1 byte or Dm 0 Dm is a value which can be expressed with 4 bytes to
272. ificant 16 bits D31 to 16 of the data bus are used Fig 5 8 12 is a timing chart for a word access with a 16 bit bus in asynchronous mode with FRQ 0 while Fig 5 8 13 is a timing chart for a word access with a 16 bit bus in asynchronous mode with FRQ 1 When writing byte 0 and byte 2 WE2 is asserted and the data is output on D23 to 16 When writing byte 1 and byte 3 WE3 is asserted and the data is output on D31 to 24 31 0 zs Ld D31 16 C E RD WT ES i es ey Gee 1 wait ok wait ok 1 wait ok B 1 wait ok 4 10 00 4 Lower half Upper half Lower half Upper half word read cycle word read cycle word writecycle word writecycle Fig 5 8 12 Timing for Access in Asynchronous Mode with 16 bit Bus FRQ 0 One Wait OK Description of Operation 115 Chapter 5 Bus Controller UUUUUUUUUUUUUUUUUUUL 1 0 1 0 pepe 1 0 1 1 E D31 16 C GNE GEMENS RD WT SIZE1 0 CH yt FE 3 wait ok I 3 wait ok t 3 wait ok 3 wait ok gt Lower half Upper half Lower half Upper half word read cycle word read cycle word write cycle word write cycle Fig 5 8 13 Timing for Access in Asynchronous Mode with 16 bit Bus FRQ 1 Three Wait OK 116 Description of Operation Chapter 5 B
273. igh and oscillating When FRQS is low and oscillating frequency is 16 5 MHz frequency is 33 MHz 000 3 972 ms 3 972 ms 001 15 888 ms 15 888 ms 010 63 550 ms 63 550 ms 011 254 200 ms 254 200 ms 100 1016 801 ms 1016 801 ms Bit No Bit name Description 3 Always returns 0 4 WDOVF Reading this bit returns the value of the WDOVF pin 5 WDOVT Watchdog timer overflow output selection 0 Pulse output 1 Level output 6 WDRST Binary counter reset watchdog timer overflow output reset 0 No reset 1 Reset 7 WDCNE Watchdog timer count operation control 0 Count operation stopped oscillation stabilization wait operation is possible 1 Count operation enabled 1 When resetting the external overflow output by writing the WDRST flag do not simultaneously overwrite the WDOVT flag If this flag is overwritten the external overflow pin signal reset is not guaranteed 2 When changing the value in WDCK0 to 2 first stop the watch dog timer and then reset the counter 270 Description of Registers Chapter 10 Watchdog Timer 10 4 3 Reset Control Register Register symbol RSTCTR Address x 34004004 Purpose This register is used to generate an internal reset through software Bit No Bit name Description 0 CHIPRST This flag is used to generate a self reset internal reset A self reset is generated when this flag is overwritten from 0 to 1 self reset is not generated if this flag is already set to 1 whe
274. igned byte data multiply and accumulate operation instruction between registers Instruction Format Macro Name MACB Dm Dn Assembler Mnemonic udf32 Dm Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the contents of Dm signed 8 bit integer multiplicand by the contents of Dn signed 8 bit integer multiplier adds the resulting product to the 32 bit cumulative sum that is stored in the multiply and accumulate register MCRL and then stores the new resulting 32 bit cumulative sum back in multiply and accumulate register MCRL If an overflow from the 32 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Flag Guge _ Programming Cautions non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction Extension Instruction Specifications 401 Appendices MACIB Signed byte data multiply and accumulate operation instruction between immediate value and register Instruction Format Macro Name MACIB imm Dn Assembler Mnemonic udf32 imm8 Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension functi
275. ill have a higher priority than that indicated by the interrupt mask level bits IM2 to IMO in the PSW In other words the interrupt level indicated by LV2 to LVO in the GnICR must be smaller than the interrupt mask level bits IM2 to IMO in the PSW When a nonmaskable interrupt is generated nesting of level interrupts and nonmaskable interrupts is prohibited until the nonmaskable interrupt handler terminates and executes the RTI instruction 2 7 4 3 Interrupt Acceptance Timing If an interrupt request is generated while an instruction is being executed execution of the instruction is aborted if possible even in the case of an instruction that requires multiple execution cycles such as a multiple or divide instruction and the interrupt is accepted The aborted instruction is executed again after control returns from the interrupt processing By aborting instructions in this case the interval during which interrupt acceptance is prohib ited is kept to no more than 11 cycles The maximum interval of 11 cycles occurs only in special cases such as task or context switching in which all of the registers are being saved or restored by an instruction such as MOVM CALL or RET 2 7 4 4 Stack Frame When an interrupt is accepted a stack frame is allocated and a total of six bytes of information consisting of the PC and the PSW are saved in the stack in order to return from the interrupt later However since the transfer of data that spans a 3
276. imers are cascaded and operate as 16 24 32 bit timer refer to the chapter 8 7 3 Cascaded Connection Sequence of Startup Operation 1 Set the division rate of timer Set the division rate to TMnBR The cycle time for interrupt becomes value of TMnBR 1 cycle time of clock source 2 Select clock source Clock source can be selected by TMnCK 2 0 fields of TMnMD register If use 1 8 IOCLK 1 32 IOCLK as clock source enable prescaler operation by setting vale 1 to TMPSCNE field of TMPSCNT register 3 Initiate timer Initiate the timer n setting vale 1 to TMnLED field of TMnMD register Value of TMnBR is loaded to TMnBC as initial data then reset timer output After initiate time set certainly normal mode by setting value 0 to TMnLED register 4 Set I O ports if use timer output Set I O port to timer output pins by setting I O port register Refer to the chapter I O port how to set port register 5 Permit timer counting operation Start timer counting operation if set value 1 to TMnCNE field of TMnMD register If permit timer counting operation generate the request of underflow interrupt with specified cycle Whenever interrupt occurs condition of output pin is negated then Joad the value of TMnBR to TMnBC If change the value of TMnBR during counting operation when next underflow occurs that is used as initial value and interrupt cycle will be changed 2 1 4 Description of Operation Chapter 8 8 bit Timers
277. in the external pin interrupt signal value for at least four SYSCLK cycles when FRQS 0 or for at least two SYSCLK cycles when FRQS 1 In stop mode level detection is used even if edge detection is set for the external interrupt detection condition In other words when positive edge detection is set high level detection results when negative edge detection is set low level detection results Description of Registers 201 Chapter 7 Interrupt Controller 7 5 Description of Operation The interrupt controller processes the following interrupts Non maskable interrupts NMIRQ pin interrupts Watchdog timer overflow interrupts System error interrupts Level interrupts Internal interrupts Peripheral interrupts from timers serial A D converter watchdog timer DMA External interrupts External pin interrupts 8 pins For external pin interrupt signals maintain the value for at least four SYSCLK cycles when FRQS 0 or for at least two SYSCLK cycles when FRQS 1 In the event of a level interrupt the interrupt group is determined and then an interrupt request is sent to the CPU If an interrupt signal is received a determination is made as to whether it is a non maskable interrupt or a level interrupt If it is a level interrupt the interrupt group is determined by deciding to which group the interrupt source belongs Once the interrupt group is determined an interrupt request is generated
278. ing Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and 1 instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW 306 Extension Instruction Specifications Appendices MAC Signed multiply and accumulate operation instruction between registers Instruction Format Macro Name MAC Dm Dn Assembler Mnemonic udf28 Dm Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the contents of Dm signed 32 bit integer multiplicand by the contents of Dn signed 32 bit integer multiplier adds the upper 32 bits and lower 32 bits of the resulting 64 bit product to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new resulting cumulative sum back in multiply and accumulate register MCRH and the lower 32 bits in multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Flag Change Condition id Programming Cautions A non extension instruction that consumes at least two cy
279. instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW Extension Instruction Specifications 395 Appendices MULQIU Unsigned quick multiplication instruction between immediate value and register Instruction Format Macro Name MULQIU imm Dn Assembler Mnemonic udfu01 imm8 Dn imm8 is zero extended udfu01 imm16 Dn imm16 is zero extended udfu01 imm32 Dn Operation This instruction performs multiplication quickly using the multiplier in the extension function unit The instruction multiplies the 32 bit data that is obtained by zero extending imm multiplicand by the contents of Dn unsigned 32 bit integer multiplier and then stores the upper 32 bits of the 64 bit result in the quick multiply register MDRQ and the lower 32 bits in Dn The range of significant values for the multiplicand that is stored in Dm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short if the number of imm bits is 16 or less the operation results will be derived faster Flag Changes 1 when the MSB of the lower 32 bits of the result is 1 0 in all other cases 1 when the lower 32 bits of the result are all 0 0 in all other cases Programm
280. instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction The operations of udf u33 imm16 Dn and udfu33 imm32 Dn not assured In addition a system error interrupt does not occur in these cases 408 Extension Instruction Specifications Appendices SAT16 16 bit saturation operation instruction Instruction Format Macro Name 5 16 Dm Dn Assembler Mnemonic udf04 Dm Dn Operation When Dm is a 16 bit signed number which is the maximum positive value 0 00007 or more the maximum positive value 0x00007 is stored in Dn When Dm is a 16 bit signed number which is the maximum negative value Oxf f 8000 or less the maximum negative value 0x 8000 is stored in Dn In all other cases the contents of Dm are stored in Dn Flag Changes Condition 1 when the MSB of the operation result is 1 0 in all other cases 1 when the operation result is 0 0 in all other cases Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of ud 04 imm8 Dn udf04 imm16 Dn and ud 04 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases Extension Ins
281. ion is used ahead of a conditional branch instruction The compare instruction produces changes in flag settings Table 2 5 5 List of Compare Instruction Instruction Description CMP Compare 28 Instructions Chapter 2 CPU 2 5 34 Logical Operation Instructions The logical operation instructions perform logic operations on the source operands and store the results in a regis ter of these instructions produce changes in flag settings Table 2 5 6 List of Logical Operation Instructions Instruction Description AND Logical product OR Logical sum XOR Exclusive logical sum NOT Inversion one s complement 2 5 3 5 Bit Manipulation Instructions The bit manipulation instructions perform bit manipulation operations between an immediate value and the con tents of a register between an immediate value and the contents of memory or between the contents of a register and the contents of memory of these instructions produce changes in flag settings Table 2 5 7 List of Bit Manipulation Instructions Instruction Instructions 29 Chapter 2 CPU 2 5 3 6 Shift Instructions The shift instructions shift bits by the specified amount This operation can be performed within one cycle regard less of the shift amount All of these instructions produce changes in flag settings Table 2 5 8 List of Shift Instructions Instruction Description
282. ion of Registers 95 Chapter 5 Bus Controller 5 6 2 0 Memory Control Register 5 Register symbol 5 Address x 3200002A Purpose Sets the wait mode bus mode and bus width for external memory space block 5 When reset Bit No Bit name Description 1 B5WM Block 5 wait mode 0 Fixed wait state insertion 1 Handshaking 2 5 Block 5 bus mode 0 Synchronous mode synchronized with SYSCLK 1 Asynchronous mode synchronized with MCLK 5 BSBW Block 5 bus width 0 16 bits 1 32 bits The number of wait states for block 5 is indicated by the value set in bits BIWCA to 0 in memory control register 1 After reset mode is released block 5 is set to synchronous mode with 31 wait states and the bus width is 32 bits Block 5 cannot be used as a DRAM space 96 Description of Registers Chapter 5 Bus Controller 5 6 2 7 Memory Control Register 6 Register symbol MEMCTR6 Address x 3200002C Purpose Sets the wait mode and bus width for external memory space block 6 Bit No Bit name Description 1 B6WM Block 6 wait mode 0 Fixed wait state insertion 1 Handshaking 5 B6BW Block 6 bus width 0 16 bits 1 32 bits The number of wait states for block 6 is indicated by the value set in bits B2WCA to 0 in memory control register 2 After reset mode is released block 6 is set to synchronous mode with 15 wait states and the bus width is 32 bits Block 6 cannot be used in asynchronous mode or as a DRAM spa
283. ion of timer Count operation starts by setting 1 into TMnCNE of TMnMD register Underflow interrupt is generated with constant cycle with counter operation permission Each interrupt cause the inverting of the pin output and the loading of TMnBR value into TMnBC Changing of the interrupt cycle can be done by loading of TMnBR register value as initial value at the first underflow if the TMnBR register value is replace during the count operation um Description of Operation 24 Chapter 9 16 bit Timers Steps for operation termination 1 Stop the count operation of timer Count operation will stop when 0 is given to TMnCNE register of TMnMD register 2 Initialization of timer if it is necessary Timer output reset is same as loading TMnBR value into TMnBC as initial value when 1 is set to TMnLDE of TMnMD register Binary counter and pin output keep the working condition unless TMnLDE is set to 1 after timer termination Le count can be restart from the same condition before the timer is stopped if TMnCNE is set to 1 again TMnBC value Valuet in TMnBR x 0000 TMnCNE Interrupt request Timer output Fig 9 7 1 Interval Timer Operation Interrupt request signal TMnIRQ Timer output TMnOUT TMnBR value 1 XIOCLK Fig 9 7 2 Interval Timer Operation When Clock Source IOCLK 242 Description of Operation Chapter 9 16 bit Timers Counti
284. is instruction and the next extension instruction 398 Extension Instruction Specifications Appendices MACH Signed half word data multiply and accumulate operation instruction between registers Instruction Format Macro Name MACH Dm Dn Assembler Mnemonic ud 30 Dm Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the contents of Dm signed 16 bit integer multiplicand by the contents of Dn signed 16 bit integer multiplier adds the upper 32 bits and lower 32 bits of the resulting 64 bit product to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new resulting cumulative sum back in multiply and accumulate register MCRH and the lower 32 bits in multiply and accumulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Programming Cautions non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction Extension Instruction Specifications 399 Appendices MACIH Signed half word data multiply and accumulat
285. is register selects the sources for transmission interrupts reception interrupts and DMA startup requests for serial interface n Bit No Bit name 0 SCnRI 2 SCnRES 3 4 SCnTI 5 SCnTD 6 7 SCnDMD 286 Description of Registers Description Reception interrupt source selection 0 Reception end 1 Reception end with error Always returns 0 Reception error interrupt source selection 0 Interrupt request when an overrun parity or framing error occurs 1 Interrupt request when a parity error occurs Always returns 0 Transmission interrupt source selection 0 Transmission end 1 Transmission buffer empty DMA startup source selection for transmission 0 Transmission end 1 Transmission buffer empty Always returns 0 Data output maintenance during external clock transmission valid only in clock synchronous mode 0 Set data pin high at end of transmission 1 Maintain data pin at end of transmission Chapter 11 Serial Interfaces 11 4 8 Serial n Transmission Buffer n 0 1 Register symbol SCnTXB Address x 34000808 n 0 x 34000818 n 1 Purpose This register writes the transmission data to serial interface n Bit No Bit SCn SCn SCn EN SCn SCn name TXB7 TXB6 5 TXB4 TXB3 TXB2 TXB1 TXBO When reset ofo Access Data is transmitted by writing it to this buffer 11 4 4 Serial n Reception Buffer n 0 1 Register symbol SCnRXB Addr
286. ister A Set the TM6MDA as show below TM6A02 1 0 optional TM6ACE 1 Permission for capture operation TM6AEG optional Select either of rising edge or falling edge for single edge operation TM6AM1 0 10 Capture register for single edge or 11 Capture register for dual edge If select dual edge operation setting of TM6AEG is ignored Fig 9 7 7 shows steps after count operation of the timer 6 is permitted Show when to load the value of TM6BC into TM6CA At the next step interrupt of compare capture register A occurs Capturing won t happen unless the count operation is performing If dual edge are selected as reading timing capturing occurs whenever wither of rising edge or falling edge is produced It s hard to tell which edge does input has It is possible to read the electrical level of the pin input By setting 0 to TM6ACE capturing can be avoid even during the count operation If TM6CAE of TM6MD register is set to 1 and if TM6CA is set as a capture register TM6BC is cleared with the capturing operation of TM6CA At this moment value in the buffer is load into compare register if TM6CB has double buffer compare register setting The output pattern of the additional bits is as shown below Pin input TM6IOA Capture timing TM6CA Compare capture A interrupt request Fig 9 7 7 Operation of Input Capture When Select Rising Edge 248 Description of Operation Chapter 9 16 bit Timers
287. istics 13 4 3 Address Data Transfer Signal Timing Table 13 4 3 AC Characteristics 3 VDD 3 3 0 165 V Vss 0V 20 C to 70 CL 50 pF Allowable values iti Unit Item Symbol Condition Min Max Synchronous mode data transfer signal output timing Refer to Fig 13 4 4 E17 Address delay time T 5 4 5 A31 0 RD WT SIZE 0 4 E18 Address hold time 1 5 10 He A31 0 RD WT SIZEI 0 E19 Address hold time 2 iu _ m A31 0 RD WT SIZE1 0 2 E20 Address hold time 3 ien _ 4 A31 0 RD WT SIZEI 0 2 E21 Chip select signal fall delay time 5 2 m CS7 0 E22 Chip select signal rise delay time ids 5 2 n CS7 0 E23 Chip select signal hold delay time 1 ius 7 tere ds CS7 0 2 E24 Chip select signal hold delay time 2 I _ CS7 0 2 E25 Read data enable signal fall delay time iue _ 5 5 ns RE E26 Read data enable signal rise delay time dc 16 5 iis RE E27 Write data enable signal fall delay time fous 2 5 5 ns WE3 0 E28 Write data enable signal rise delay time bun 5 5 ns WE3 0 E29 Write data delay time b 5 is D31 0 Write data hold delay time 1 E30 D31 0 5 ns 348 AC Characteristics Chapter 13 Electrical Characteristics Table 13 4 4 AC Characteri
288. iting SCnTXB 0 Not detected 1 Detected I2C stop sequence detection Cleared by reading SCnRXB or by writing SCnTXB 0 Not detected 1 Detected Always returns 0 Chapter 11 Serial Interfaces 11 4 6 Serial 2 Control Register Register symbol 5 2 Address x 34000820 Purpose This register sets the serial interface 2 operation control conditions Bit No Bit name 0 SC2CKO 1 SC2CKI 2 25 3 SC2STB 4 SC2PBO 5 SC2PB1 SC2PB2 7 SC2CLN 8 SC2TWE 9 5 2 10 to 11 Continued Description Clock source selection LSB Clock source selection MSB 00 IOCLK 01 Timer 2 underflow 10 External clock 11 Timer 3 underflow Always returns 0 Stop bit selection 0 1 bit 1 2 bits Parity bit selection LSB Parity bit selection Parity bit selection MSB 000 None 001 010 011 Setting prohibited 100 0 fixed 101 1 fixed 110 Even even number of 1 s 111 Odd odd number of 1 s Character length selection 0 7 bits 1 8 bits Transmission interruption enable 0 Disabled 1 Enabled Transmission bit sequence selection 0 FromLSB 1 From MSB Always returns 0 Description of Registers 280 Chapter 11 Serial Interfaces Continued Bit No 12 15 290 Description of Registers Bit name SC2TWS SC2BKE SC2RXE 5 2 Description Transmission interruption code selection 0 Interrupt when low 1 Interrupt when high Sending break 0 Do not send break 1 Send break T
289. lag Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Flag Change Condition V 0 Indicates that the multiply and accumulate operation is valid When multiply and accumulate operation overflow was detected MCVF 1 Flag Chage Cond on Indicates that the multiply and accumulate operation is invalid Undefined Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW When udf13 Dm Dn is operated Dm is ignored The operations of ud 13 imm8 Dn udf13 imm16 Dn and 14 13 imm32 Dn not as sured In addition a system error interrupt does not occur in these cases Extension Instruction Specifications 39 Appendices CLRMAC Multiply and accumulate register clean operation Instruction Format Macro Name CLRMAC Assembler Mnemonic udf22 D0 DO Operation This instruction clears the contents of the multiply and accumulate registers MCRH and MCRL This instruction also clears the contents of the multiply and accumulate overflow detect register MCVF Flag Changes Fiag Chage 1 1 1 1 Programming Cautions When udf22 Dm Dn is operated Dm and Dn are ignored The op
290. le Before execution 0 12345678 After execution 0x78563412 Flag Changes Condition Undefined Undefined Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of ud 08 imm8 Dn udf08 imm16 Dn and udf08 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases 416 Extension Instruction Specifications Appendices SWAPH Data swapping instruction high order to low order and vice versa in two byte data Instruction Format Macro Name SWAPH Dm Dn Assembler Mnemonic udf09 Dm Dn Operation This instruction swaps bits 15 through 8 of Dm with bits 7 through 0 and bits 31 through 24 with bits 23 through 16 and then stores the result in Dn Dm before execution Bit 31 Bit 0 Dm 31 24 Dm 23 16 Dm 15 8 Dm 7 0 X 1 toi Ey MSB LSB Dn after execution Bit 31 Bit 0 Dm 23 16 Dm 3124 Dm 7 Dm 15 8 ESSE SE qoe ges me pd quo pes p po d e MSB LSB Execution example Before execution 0 12345678 After execution 0x34127856 Flag Changes Condition Undefined Undefined Undefin
291. le processing that only transfers data to the extension unit or that transfers data to the extension unit and then after allowing several cycles for the execution of another instruction fetches data from the extension unit is assigned to UDF20 to UDF35 Extension operations that require three or more inputs can be implemented by first using an instruction from UDF20 to UDF35 to transfer the input data to the extension function unit and then using an instruc tion from UDFOO to UDF15 to perform the operation A block diagram showing the extension function unit connected to the CPU core for this microcontroller series is shown below The MN103002A MN103002A YB has 32 x 32 multiplier 32 x 32 64 multiply and accumulate unit a priority encoder and a saturation compensation unit on chip Extension instructions that use those extension function units are explained in the next section Extension Instructions Operation Operation extension extension block A 7 blockB Instruction decoding blocky Microcontroller User extension er extension Instruction 3 SEL EXISTS Us tension NEM core instruction instruction instruction queue decoder decoder A decoder B Operation extension interface Program Userextension User extension counter Registers LU function function 0077 block unit A unit B Instruction addres
292. low interrupt requested 1 Underflow interrupt requested 5107 Always returns 0 8 TM3IE Timer 3 underflow interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 GSLVO Group 5 interrupt priority level register LSB 13 GSLVI Group 5 interrupt priority level register 14 GSLV2 Group 5 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 175 Chapter 7 Interrupt Controller 7 4 2 5 Group 6 Interrupt Control Register Register symbol G6ICR Address x 34000118 Purpose This register is used to enable group 6 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 TM4ID Timer 4 underflow interrupt detection flag 0 No underflow interrupt detected 1 Underflow interrupt detected 103 Always returns 0 4 TM4IR Timer 4 underflow interrupt request flag 0 No underflow interrupt requested 1 Underflow interrupt requested 5 07 Always returns 0 8 TM4IE Timer 4 underflow interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G6LVO Group 6 interrupt priority level register LSB 13 G6LV1 Group 6 interrupt priority level register 14 G6LV2 Group 6 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 176 Description of Registers Chapter 7 Interrupt Controller 7 4 26 Group 7
293. lue in TM6BC X TM CA 1 6 value 0000 0001 Compare capture interrupt request Compare capture register A TM6CA Set value 1 Set value 2 Compre register A buffer Set value 1 Set value 2 If double buffer is set the value is loaded from the buffer at the same time that TM6BC is cleared Fig 9 7 19 Operation of Interval Timer on Timer 6 When Using Prescaler Description of Operation 259 Chapter 9 16 bit Timers 9 7 2 7 Event Counter Please take the following steps to use timer 6 as event counter Interrupt of compare capture register A is generated whenever the specified number of edges are counted fig 9 7 20 Compare capture B is available as compare register Please refer section 9 7 2 1 setting of compare register Steps for start up 1 Setting of compare capture register Setting of TM6MDA register 64 02 1 0 optional TM6ACE 0 Inhibit capture operation TM6AEG optional TM6AM1 0 00 Compare register single buffer or 01 Compare register double buffer 2 Select input edge of TM6IOB pin Select either of rising falling edge by TM6AEG of TM6MDB register 3 Set division ratio Set division ratio into TM6CA Interrupt of compare capture register A is generated when selected edge is counted value in TM6CA 1 times at TM6IOB 4 Setting for operation mode Set the TM6MD register as described below TM6CK2 1 0 111 Sets the TM6IOB pin input a
294. ming Model 2 Data Registers 32 bit x 4 These are general purpose registers that can be used for all operations Operations are performed with 32 bit data data sizes are converted either when transferring data to or from memory or by executing the EXTB or EXTH instruction When 8 bit data is loaded into a data register it is zero extended to 32 bits before it is transferred to the register when storing such data in memory only the lower 8 bits of the register are trans ferred to memory When 8 bit data that is loaded into a data register is to be handled as a signed integer it is sign extended from 8 bits to 32 bits by the EXTB instruction When 16 bit data is loaded into a data register it is zero extended to 32 bits before it is transferred to the register when storing such data in memory only the lower 16 bits of the register are transferred to memory When 16 bit data that is loaded into a data register is to be handled as a signed integer it is sign extended from 16 bits to 32 bits by the EXTH instruction Address Registers 32 bit x 4 These registers are used as address pointers only instructions for address calculation addition subtraction and comparison are supported Data in the address registers is used for pointers and is normally transferred to and from memory with a 32 bit length Stack Pointer 32 bit x 1 This pointer points to the top of the stack Program Counter 32 bit x 1 Thi
295. mode 15 888 ms The chip self reset internally by writing the RSTCTR register 266 Overview Features Chapter 10 Watchdog Timer 10 3 Block Diagram Pulse output selection Internal reset signal Internal reset generation System clock 8 bit binary counter RST system clock STOP mode Oscillation stabilization wait release interrupt 8 bit binary counter WDBC Reset Control register WDCTR Clock source selection 16 bit binary counter OSCI FRQS input High 13 0 MHz to 16 6 MHz oscillating frequency FRQS Low 26 0 MHz to 33 3 MHz oscillating frequency Fig 10 3 1 Block Diagram Block Diagram 267 Chapter 10 Watchdog Timer 10 4 Description of Registers Table 10 4 1 List of Watchdog Timer Registers Number Initial Address Name Symbol of bits value 34004000 Watchdog binary counter WDBC x 00 x 34004002 Watchdog timer control register WDCTR x 01 34004004 Reset control register RSTCTR x 00 10 4 1 Watchdog Binary Counter Register symbol WDBC Address x 34004000 Purpose Reading this counter returns the counter value of the high order eight bits of the watchdog timer mu TT 5 9 3 T2 Bit WD WD WD WD WD WD WD W 0 9 9 9 9 9 9 9 Bit No Bit name Description 0107 WDBCO to TDBC7 eu Counter value
296. mpleted The byte specification by CAS3 through 0 is set by setting the BnCAS bit in memory control registers 1 through 3 Just as in the case of byte specification by WE3 through WEO the RAS signal and in the case of a write the WE signal are negated as soon as the consecutive accesses to DRAM are completed The address is shifted down and the row address is output according to the value of the SIZE1 and 0 bits in the DRAM control register The RASn signal n corresponds to the block number and the CAS signal are then asserted according to the values of the RTC bit RPCP bit and the WC3 through 0 bits in the DRAM control register Fig 5 8 24 shows the page mode read timing with a 32 bit bus and Fig 5 8 26 shows the page mode read timing with a 16 bit bus Fig 5 8 25 shows the page mode write timing with a 32 bit bus and Fig 5 8 27 shows the page mode write timing with a 16 bit bus A31 0 Row Column Column Colum X RASn m 4 precharge CAS3 0 HER i ue WE3 0 D31 0 Cs C C nii p SIZE1 0 er TE Read lt Read Read gt 4 Read 9 cycle cycle cycle cycle Fig 5 8 24 32 bit DRAM Page Mode Read Timing When 1 124 Description of Operation Chapter 5 Bus Controller A31 0 Row Column Column us EN
297. mulate instruction 1 DEC Instruction decoding EX MEM WB Insert two cycle Result can be referenced Multiply and accumulatd instruction 2 MM Instruction decoding A w Multiply and accumulate instruction 1 has output the result that is required by multiply and accumulate instruction 2 Fig E 4 Pipeline Diagram Illustrating This Note 2 This note applies to the following instructions Word half word data multiply and accumulate instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instruction MACIHU instruction Multiply and accumulate instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instruction MACIHU instruction MACB instruction MACIB instruction MACBU instruction MACIBU instruction 420 Extension Instruction Specifications Appendices 1 Note on the description of word half word data multiply and accumulate instructions and MCRH MCRL access instructions When executing a word half word data multiply and accumulate instruction followed by an MCRH MCRL access instruction the result produced by the word half word data multiply and accumulate instruction is used in the execution of the subsequent MCRH MCRL access in
298. n When the value of Dm or imm8 is 8 0x00000008 When the 32 bit result of the multiply and accumulate operation that is stored in the multiply and accumulate register MCRL is equal to or greater than the maximum positive value for an 8 bit signed number 0x0000007 the maximum positive value 0x7 is stored in Dn If the value stored in the multiply and accumulate register MCRL is equal to or less than the maximum negative value for an 8 bit signed number Oxf 80 the maximum negative value 0x80 is stored in Dn In all other cases the contents of MCRL are stored in Dn When the value of Dm or imm8 is any other value The value in Dn is undefined Extension Instruction Specifications 411 Appendices Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Flag Change Condition d 0 Indicates that the multiply and accumulate operation is valid 0 Always 0 Undefined Z Undefined When multiply and accumulate operation overflow was detected MCVF 1 Flag Change Condition 1 Indicates that the multiply and accumulate operation is invalid N Undefined 2 Undefined _ Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instruction
299. n The data cache consists of two data memory blocks two tag memory blocks and write back buffers The data cache can be written either through the write back method or the write through method Data memory The data memory stores data in 16 byte units Each way has 2 Kbytes of data memory for a total of 4 Kbytes The data memory line size is 16 bytes and the number of entries is 128 Data transfers from external memory to the data cache are handled in 16 byte 128 bit units while data transfers from the data cache to the CPU are handled in 32 bit units The contents of data memory are not initialized by a reset 60 Configuration Chapter 4 Caches Tag memory The tag memory has 128 entries each of which consists of a tag address field TADD that stores bits 30 through 11 20 bits of the instruction address a valid bit V that indicates whether an entry is valid or not a refill bit R that indicates whether a data transfer a refill from external memory to the data cache is in progress and a dirty bit D that indicates there was a write to the corresponding entry in write back mode In the event of a reset only the refill bit R is cleared The valid bit V is not cleared it is cleared by the data cache invalidate bit in the cache control register CHCTR Write back buffer There is a one line 16 bit write back buffer in the data array and a one entry write back buffer in the tag array The write back buffers are used
300. n and by stopping the clock that is supplied to the CPU and peripheral circuits The three low power consumption modes are listed below STOP mode In this mode oscillation of the oscillator itself and PLL oscillation are stopped When an interrupt is generated the oscillator and the PLL start operating the microcontroller waits for the oscillation to stabi lize and then the microcontroller enters the NORMAL operation mode HALT mode In this mode although the oscillator itself and the PLL are operating the clock that is supplied to the CPU and peripheral circuits is stopped and the CPU and peripheral circuits stop operating When an interrupt is generated the microcontroller enters the NORMAL operation mode SLEEP mode In this mode although the oscillator itself and the PLL are operating the clock that is supplied to the CPU is stopped so that the CPU stops but the peripheral circuits are operating When an interrupt is generated the microcontroller enters the NORMAL operation mode immediately Operating Modes 49 Chapter 2 CPU 50 Operating Modes Chapter 3 Clock Generator Chapter 3 Clock Generator 3 1 Overview The clock generator CG in the MN103002A MN103002A YB has a built in PLL circuit and in addition to sup plying clock pulses at a frequency that is a multiple of the oscillating frequency of the oscillator the CG also supplies clock pulses with the same frequency as the oscillating fr
301. n Mode 0 0 cs ceesesssesesssssessscscesescsesescsesesescscscscssscssscavsvsvsvenenenens 78 4 5 4 External Bus Access During Cache Operations s sees 78 Cache Entry Address Assignments ettet treten 79 4 6 1 uc ELTE 79 4 6 2 Data m 80 Bus Controller OVervIeW 82 PAUL eS ser oett Ren a 82 Bus Configuration eiat iei vi reri cea ae a aec Eee oe REND 83 Block Diagram erase 85 Pin Functions s ictu Reti Sie et o o I EU d 86 Description of Registers essent ettet tnnt tette netten tenen 87 5 6 1 Bus Control Register eese entente 88 5 6 2 Memory Control Registers eese ettet ette tenentnn 90 5 6 2 1 Memory Control Register 0 0 20 90 5 6 2 2 Memory Control Register 1 sessssseeeeeerettees 92 5 6 2 3 Memory Control Register 2 0022 2 2 201 11 0000000 93 5 6 24 Memory Control Register 3 94 5 6 2 5 Memory Control Register 4 eseeeseeeeeeeerrrens 95 5 6 2 6 Memory Control Register 5 eres 96 5 6 2 7 Memory Control Register 6 c ccccccssssessssscecssecssscsescscevavsvevsnseeensens 97 5 6 2 8 Memory Control Register 7 97 5 6 3 DRAM Control Register sess tenentes 98 5 6 3 1 DRAM Control Register eese ette 98 5 6 3 2 Refresh Count Register eese
302. n compare register buffer is loaded to compare register Binary counter compare register and pin output keep the level before the termination unless TM6LDE is set to 1 after the termination Le continuing of the count from the terminated condition is available by setting 1 into TM6CNE Description of Operation 257 Chapter 9 16 bit Timers TM6BC value Value set in TM6CA usin 0000 Compare capture interrupt request Fig 9 7 16 Operation of Interval Timer on Timer 6 1 TM6BC value If double buffer is set the value is loaded from the Change the value of TM6CA buffer when register is matched Value set in TM6CA x 0000 TM6CNE Compre capture A interrupt request Fig 9 7 17 Operation of Interval Timer on Timer 6 2 258 Description of Operation Chapter 9 16 bit Timers Yom prom Y Reese ce Y sm Compare capture interrupt request gt 4 TM6CA value 1 XIOCLK Compare capture register A TM6CA Set value 1 Set value 2 Compare register A buffer Set value 1 Set value 2 If double buffer is set the value is loaded from the buffer at the same time that TM6BC is cleared Fig 9 7 18 Operation of Interval Timer on Timer 6 When Clock Source Counting clock TI T Va
303. n it is written with a 1 The value stored in this flag is retained even after the reset The CHIPRST flag is cleared either by an external reset signal or by writing a 0 to this flag through the software Description of Registers 271 Chapter 10 Watchdog Timer 10 5 Description of Operation 10 5 1 Oscillation Stabilization Wait Operation The watchdog timer operates as an oscillation stabilization wait timer after the reset state is released or when the microcontroller recovers from STOP mode The watchdog timer operates in this capacity even if the WDCNE flag is 0 If the WDCNE flag is 1 a non maskable interrupt is not generated even when recovering from STOP mode SYSCLK AAAAA Internal clock SYSCLK supply enabled HE cT Watchdog timer count value 15 888 ms when FRQS is high and the oscillating frequency is 16 5 MHz Fig 10 5 1 Operation Diagram 1 When Reset Is Released 272 Description of Operation Chapter 10 Watchdog Timer Interrupt Stop mode 3 release request external pin interrupt HG OSCI input SYSCLK Internal clock SYSCLK supply enabled Watchdog timer count value 15 888 ms when 5 is high and the oscillating frequency is 16 5 MHz Fig 10 5 2 Operation Diagram 2 When Recovering from Stop Mode Description of Operation 273 Chapter 10 Watchdog Timer 10 5 2 Watchdog Operation If th
304. n of Operation 107 Chapter 5 Bus Controller During a read the address IOA11 to 0 and the read request signal RR are output in synchronization with the rising edge of MCLK After one MCLK cycle the data strobe signals DS3 to 0 are asserted and the I O side begins to drive the data on the data bus During a write the address IOA11 to 0 and the write request signal WR are output in synchronization with the rising edge of MCLK After one MCLK cycle the data strobe signals DS3 to 0 are asserted and are then negated one MCLK cycle before the end of the I O access cycle The write is performed at the rising edge of the DS3 to 0 signals Note that in the case of a normal internal circuit the bus cycle is completed at the number of wait states 0 to 7 MCLK cycles set by the IOWC bits in the bus control register but in the case of the I O port only the bus cycle is completed at the number of wait states 0 to 15 MCLK cycles set by the IOPWC bits in the I O bus control register 5 8 4 External Memory Space Access non DRAM Spaces 5 8 4 1 Bus Synchronous Modes 32 bit bus synchronous mode Setting of the various parameters for external memory access is performed in memory control registers 0 to 7 corresponding to each block In synchronous mode the bus access is initiated in synchronization with SYSCLK When fixed wait state insertion is specified the bus access ends after the number of wait states set in the memory
305. nal and the data is read the external memory is addressed and then the data is written on the bus Transfer from external memory to an external device While external memory is addressed and the data is read the external device is accessed through the DMK signal and the data is written on the bus Addressing modes Fixed increment or decrement can be specified for the source address and the destination address respectively Incrementation and decrementation are performed automatically in accordance with the size of the transfer unit 136 Overview Features Chapter 6 Controller Transfer modes Single word transfer In this mode transfers are performed the required number of times releasing the bus to the CPU after each word is transferred Burst transfer In this mode transfers are performed consecutively the required number of times Intermittent transfer In this mode transfers are performed continuously releasing the bus to the CPU after a set number of transfers Priority ranking The priority ranking of the channels is as follows ch0 gt DMA ch3 If there are simultaneous transfer requests from multiple channels the transfer on the channel with the highest priority ranking is executed If while a DMA transfer is in progress there is a transfer request on a channel with a higher priority ranking the transfer with the higher priority is executed after the next time the bus is
306. nf 2 and when 1 nr 4 Fig 13 4 11 Request Input Timing 1 P 361 i Fig 13 4 11 DMA Request Input Timing P 361 Title Fig 13 4 15 Timer Counter Input Signal Timing was deleted P 367 Japanese fonts in Fig 13 4 19 put into English The Treatment of DSCLK DSDAT in Table 1 recommended value for resister is P 370 The Treatment of DSCLK and DSDAT in Table A 1 recommeded value for resister is 1 P 370 i In Table A 1 VDD was changed into VDD and VSS was changed into Vss P 372 In the Table C 1 the row of address 2000002 was deleted P 372 to 376 Folloing note is added under the Register Maps Note Accessing areas that are not mounted is prohibited Operation is not guaranteed if an area that is not mounted is accessed List of Instructions Code Length Number of Cycles 377 List of Instructions Code Length Number of Cycles 377 Folloing annotation is added under the table number of execution cycles was calculated under the following conditions 1 No pipeline extension 2 2 cycles for the instruction fetch 1 cycle for the load store vi
307. ng Rise edge Fall edge or both edge Two signals Interrupts request occurs upon capture If it s set to both rising and falling edge interrupts occur at both rising and fall edge nterrupts Occur when binary counter overflows Occur when compare register and binary counter matches or when capture occur Two signals Counter start due to external trigger Counter starts with the TMn6IOB pin input Rising edge falling edge DMA request Occur when binary counter and compare capture register matches For the case of additional bit style PWM output mode DMA request occurs when binary counter overflow happens Features 225 Chapter 9 16 bit Timers 9 3 System Configuration Prescaler control register TMPSCNT o c 5 95 2 E 3 N o amp EUR IOCLK prescaler IOCLK 1732 1 8 x trma Y TM4IN2 TM4IRQ Timer 4 derflow interrupt TM4IN3 Timer 4 ER Underflow interrup TM4IN4 TMAINS 41 6 TM4CO TM4IN7 Edge I O port block detect Timer 5 Underflow interrupt TM6INO TM6INi TM6IN2 ew Timer6 TM6INS TM6IN6 TMGIN7 Timer 4 Overflow interrupt Timer 6 Timer 6 Compare capture A interrupt Compare capture B interrupt A TM6INA TM6INB Edge gt
308. ng clock Value in TMnBC 999 x 0000 value value TMnBR value 2 Interrupt request signal TMnIRQ Timer output TMnOUT Fig 9 7 3 Interval Timer Operation When Use Prescaler 9 7 1 2 Event Counter Use the following setting when Timer 4 5 is used as a event counter Please refer to cascaded connection section 9 7 3 1 to use them as 32 bit counter by cascading Steps for start up 1 Set the division ratio Set the division ratio of TMnBR Interrupt is generated whenever TMnBR value 1 counts of the pin input rising edge 2 Select clock source TMnCK 2 0 of TMnMD register contains value for clock source to TMnIO pin input 3 Initialization of timer Initialize timer n by giving 1 into TMnLDE of TMnMD register Load TMnBR value into TMnBC as initial value Must switch to normal operation mode by setting 0 into TMnLDE after the initialization 4 I O port setting Set I O port to pin input Please refer chapter of I O port for resister setting 5 Permission for the count operation Give permission for the count operation of the timer by setting value 1 to TMnCNE of TMnMD register Description of Operation 243 Chapter 9 16 bit Timers With the permission to count operation counter start to count the rising edge of the pin input And load TMnBR value into TMnBC as the underflow of the binary counter occurs Fig 9 7 4 TMnBR register value c
309. nnel 3 transfer addressing mode on source side LSB DMA channel 3 transfer addressing mode on source side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 3 transfer addressing mode on destination side LSB DMA channel 3 transfer addressing mode on destination side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 3 transfer direction Direction of external device that supports the acknowledge function in a one bus cycle transfer 0 Source 1 Destination DMA channel 3 transfer mode LSB DMA channel 3 transfer mode MSB 00 Burst transfer 01 Single word transfer 10 Intermittent transfer 11 Setting prohibited DMA channel 3 transfer unit LSB DMA channel 3 transfer unit MSB 00 8 bits 01 16 bits 10 32 bits 11 Setting prohibited DMA channel 3 DMR signal mode Always set to 1 DMA channel 3 DMA transfer enable 0 DMA transfer disabled 1 DMA transfer enabled DMA channel 3 DMA transfer request flag Automatically set when a startup source is generated automatically reset after one transfer operation in single word transfer mode after all transfers have been completed in intermittent transfer or burst transfer mode or in the event of a forced termination 0 No request 1 Request 1 Note that the external request sources differ from those in DMA E control registers 0 and 1 146 Description of DMA Registers Chapter 6 Controller 6 3 2 Source
310. nonmaskable interrupt is generated the external non maskable interrupt request flag NMIF in the Non maskable Inter rupt Control Register NMICR is set to 1 Watchdog timer overflow interrupts A watchdog overflow interrupt is generated when the watchdog timer enable flag WDCNE in the Watch dog Timer Control Register WDCTR is 1 and a watchdog timer overflow occurs If a watchdog inter rupt is generated the watchdog overflow interrupt request flag WDIF in the Nonmaskable Interrupt Control Register NMICR is set to 1 System error interrupts System error interrupt occurs when an unaligned memory access or an unimplemented instruction is ex ecuted or other fatal error occurs If a system error interrupt is generated the system error interrupt request flag SYSEF in the Non maskable Interrupt Control Register NMICR is set to 1 Do not change the interrupt enable IE in PSW during non maskable a interrupt proccessing 40 Interrupt Functions Chapter 2 CPU 2 7 3 3 Level Interrupts Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable flag and interrupt mask 2 to IMO bits in the PSW Level interrupts are interrupts from the interrupt group control lers that are external to the CPU in other words peripheral interrupts There are 27 groups and 27 interrupt sources Each interrupt group controller includes an interrupt control register GnICR
311. ns 0 1 84 Description of Registers Chapter 7 Interrupt Controller 7 4 2 14 Group 16 Interrupt Control Register Register symbol GIGICR Address x 34000140 Purpose This register is used to enable group 16 interrupts and to confirm interrupt name requests and detection Bit No Bit name Description 0 SCORID Serial 0 reception interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1 to 3 Always returns 0 4 SCORIR Serial 0 reception interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 SCORIE Serial 0 reception interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G16LVO Group 16 interrupt priority level register LSB 13 Group 16 interrupt priority level register 14 G16LV2 Group 16 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 185 Chapter 7 Interrupt Controller 7 4 2 15 Group 17 Interrupt Control Register Register symbol Address x 34000144 Purpose This register is used to enable group 17 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 SCOTID Serial 0 transmission interrupt detection flag 0 No interrupt detected Interrupt detected 1103 Always returns 0 4 SCOTIR Serial 0 transmission interrupt requ
312. nsmission The dummy DMA transmission setting is as follows set the dummy DMA before the original DMA setting Use the higher priority channel for the dummy DMA than that of the original DMA For instance when the original DMA use channel 2 the dummy DMA must use channel 0 or channel 1 For the dummy the transfer addressing modes of source side and destination side DMnSAM field and DMnDAM field of DMnCTR register must be fixed The transfer mode DMnTM field of DMnCTR register for the dummy DMA must be set as single word transfer mode For the transfer word register DMnCNT of the dummy DMA give the number twice of the original transfer word number plus 2 Due to the possibility another initiate source can be generated during the time difference of the setting the dummy DMA and the original DMA The source address register DMnSRC and the destination address register DMnDST for the dummy DMA must be set to the unused address of the internal IO area for instance 0x38000000 By setting above mentioned when there is an initiation source first the dummy DMA is performed After the dummy DMA perform a single word transmission the original DMA is activated The original DMA transfer is correctly performed only once Description of Operation 153 Chapter 6 Controller Notes on the execution of a BSET or BCLR instruction Interrupts are prohibited and the bus is locked occupied by the C
313. nt when PLL 1552 3 465 V 10 0 is stopped PVDD Vi Vpp or Vss Fosc Oscillation stopped C7 Supply Current of 5 V Ivrers 3 465 V 10 0 supply VREFS 5 5 25 V Voo or Vss Fosc Oscillation stopped 340 DC Characteristics Chapter 13 Electrical Characteristics Table 13 3 2 DC Characteristics 2 VDD 3 3 V 0 165 V 5 Vss PVss 0 0 20 C to 70 Allowable values Item Symbol Conditions Unit Min Typ Max Input output pins Output Push pull Input TTL 5 V level A0 to A10 RD SIZEO to SIZE1 DO to 31 DSCLK DSDAT SBOO to SBO1 TMOIO to TMSIO TM6IOA TM6IOB C7 Input voltage high level 2 2 5 V C8 Input voltage low level 0 0 0 6 C9 Output voltage high level Vss Vpp 0 6 V 4 C10 Output voltage low level Vss 04 lo 4mA Output leak current 1071 Vo Hi Z state 10 10 HA DC Characteristics 34 Chapter 13 Electrical Characteristics Table 13 3 3 DC Characteristics 3 VDD PVDD 3 3 V 0 165 V 5 5 Vss PVss 0 0 20 to 70 Allowable values
314. ntained the last modified value If set the value 1 to TMnCNE again restart counting from the last stopping condition Description of Operation 217 Chapter 8 8 bit Timers Input pulse width must be more than IOCLK 1 5 since IOCLK being sampled at pin input Event count operation is inhibited when IOCLK is terminated HALT STOP mode Pin input TMnIO Counting clock V V V Value in TMnBC x 01 00 TMnBR value ALMnBR value 1 Interrupt request signal TMnIRQ Be M Fig 8 7 4 Event Counting Operation 8 7 3 Cascaded Connection When use as 16 bit timer Higher Lower Higher Lower Higher Lower When use as 24 bit timer Higher Lowest Highest Lowest When use as 32 bit timer Highest Lowest Fig 8 7 5 Cascaded Connection Ww 218 Description of Operation Chapter 8 8 bit Timers If use as cascaded timers set as follows 1 Set the division ratio of the timer Example 1 If the cascaded timer 0 1 cascaded 16 bit timer it is necessary to set x 1233 1234 1 to TMnBR register that division ratio is set to x 1234 Then set x 33 to TMODR x 12 to TMIBR TMnBR register can be accessed with 16 32 bit width so set the value to the plural TMnBR register by using one instruction If timer 1 2 are cascaded as 16 bit timer or 3 timers are cascaded as 24 bit timer never set to these TMnBR by
315. nterrupt detected 1 Interrupt detected 1 03 Always returns 0 4 DM2IR DMAQ2 transfer end interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 DM2IE DMAQ2 transfer end interrupt enable flag 0 Disabled 1 Enabled 911 Always returns 0 12 GI4LVO Group 14 interrupt priority level register LSB 13 GIALVI Group 14 interrupt priority level register 14 141 2 Group 14 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 183 Chapter 7 interrupt Controller 7 4 2 13 Group 15 Interrupt Control Register Register symbol GISICR Address x 3400013C Purpose This register is used to enable group 15 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 DMGID transfer end interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1103 Always returns 0 4 DM3IR transfer end interrupt request flag 0 No interrupt requested 1 Interrupt requested 5 07 Always returns 0 8 DM3IE DMAS transfer end interrupt enable flag 0 Disabled 1 Enabled 9to 11 Always returns 0 12 GISLVO Group 15 interrupt priority level register LSB 13 GISLVI Group 15 interrupt priority level register 14 GISLV2 Group 15 interrupt priority level register MSB Sets a level from 6 to 0 15 Always retur
316. nterrupt detected 1 Interrupt detected Always returns 0 External interrupt 6 interrupt request flag 0 No interrupt requested 1 Interrupt requested Always returns 0 External interrupt 6 interrupt enable flag 0 Disabled 1 Enabled Always returns 0 Group 29 interrupt priority level register LSB Group 29 interrupt priority level register Group 29 interrupt priority level register MSB Sets a level from 6 to 0 Always returns 0 Description of Registers 197 Chapter 7 Interrupt Controller 7 4 2 27 Group 30 Interrupt Control Register Register symbol G30ICR Address x 34000178 Purpose This register is used to enable group 30 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 IQ7ID External interrupt 7 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 IQ7IR External interrupt 7 interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 IQ7IE External interrupt 7 interrupt enable flag 0 Disabled 1 Enabled 91011 Always returns 0 12 G30LVO Group 30 interrupt priority level register LSB 13 G30LVI Group 30 interrupt priority level register 14 G30LV2 Group 30 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 198 Description of Registers Chapter 7 Interrupt Controller
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318. o necessary to check the relationship between data that is expelled from an entry that is to be allocated with the data in external memory in order to maintain the consistency of the data First the refill target way is selected according to the value of the valid bit V in the tag array entry that was accessed the way operation mode that is set in the cache control register CHCTR and the informa tion on the way that was selected the last time that data was accessed The flow by which the refill target way is selected is the same as when a data cache read miss occurs Refer to Fig 4 5 5 Next after setting the refill bit R in the tag entry of the way that was selected the values of the dirty bit D and the tag address field TADD in the same tag entry and the one line of data in the access entry in the data array are saved to the write back buffer This save sequence is performed regardless of the data cache writing method that is selected Next the external bus access refill operation which loads one line of data from external memory into cache memory is initiated The refill is performed in a burst transfer of four words 16 bytes that starts from the word 4 bytes that includes the access address In the refill sequence the tag address field TADD in the tag array entry is updated the valid bit V and the dirty bit D are set and the target line in the data array is updated CPU clock MCLK DEC stage
319. o GNO field 5 bits corresponds to the interrupt group number One way to determine the branch destination of the interrupt program for an individual group is by referencing the contents of the address that is the sum of the starting address of the interrupt vector table and the value in the Interrupt Accept Group Register The Interrupt Accept Group Register is a read only register and cannot be written If an interrupt source of the appropriate interrupt level does not exist 0 is returned when IAGR is read Accessing the IAGR has no meaning during non maskable interrupts 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IE o GN BE Fig 2 7 3 Interrupt Accept Group Register 2 7 2 4 Interrupt Vector Registers The Interrupt Vector Registers IVARO to IVAR store the lower 16 bits of the start address of the interrupt handler for interrupts of the accepted level These registers are located at addresses x 20000000 to x 2000001B in the control register space IVARO to IVAR6 store the start addresses corresponding to interrupt levels O through 6 When an interrupt is generated control is transferred to the 32 bit address of which the upper 16 bits are either x 4000 or x 5000 and the lower 16 bits are the value stored in the IVARn register that corresponds to the level of the interrupt that was generated These registers are undefined when the system is reset 15 14 13 12 11 109 8 7 6 5
320. ode Data Transfer Signal Timing AC Characteristics 355 Chapter 13 Electrical Characteristics Table 13 4 8 AC Characteristics 8 VDD 3 3V 0 165 V Vss 0V 20 C to 70 C CL 50 pF Allowable val Item Symbol Condition DUNS Unit Min Max DRAM page mode data transfer signal output timing Refer to Fig 13 4 7 Column add idth LS NN pao Column address output widt NN as A31 0 5 1 E61 Row address strobe signal rise delay time RN _ tcvc _ ak RAS4 1 4 1 po Column address strobe signal fall delay time _ 8 vc 2 sie CAS3 0 4 4 1 E63 Column address strobe signal rise delay time 4 26 A _teyc_ 22 ne CAS3 0 4 1 Read data enable signal fall delay time dev 2 3DF 8 64 RE 4 4 ns E65 p data enable signal rise delay time us E 22 ae Note ty is the SYSCLK cycle time 356 AC Characteristics Chapter 13 Electrical Characteristics tea pla gt 1 0 Row Address Column Address Column Address XL RASA 1 ME lenaspn traspr 0 tcason tecaspr lt read gt 4 gt D31 0 in 32 bit bus mode D31 16 in 16 bit bus mode toros toros lt write gt WE3 0 gt
321. of the data address or if they match but the valid bit V of that entry is 0 then a data cache miss is said to have occurred If a miss occurs during a data cache read the data is accessed in external memory If data is read from external memory an entry line for caching that data must be simultaneously allocated in the cache In addition it is also necessary to check the relationship between data that is expelled from an entry that is to be allocated with the data in external memory in order to maintain the consistency of the data First the refill target way is selected according to the value of the valid bit V in the tag array entry that was accessed the way operation mode that is set in the cache control register CHCTR and the informa tion on the way that was selected the last time that data was accessed Fig 4 5 5 shows the flow chart how the data cache refill target way is selected Miss occurs in data cache Wav operating mode 13 121 3 CHCTR 13 12 22 or 1 CHCTR 13 12 0 Way operating mode Way0 V 1 and CHCTR 13 12 2 CHCTR 13 12 1 Way 1 V 1 Select way 0 Go to next access without refilling Select V 0 way Select way 0 Select the way that was not selected for the previous access Select way 1 Fig 4 5 5 Data Cache Refill Target Way Selection Flow Description of Operation Chapter 4 Caches Next after setting the refill
322. of the high order eight bits of the watchdog timer The value that is read is not guaranteed if the value of the high order eight bits of the watchdog timer changes while it is being read 268 Description of Registers Chapter 10 Watchdog Timer 10 4 2 Watchdog Timer Control Register Register symbol WDCTR Address x 34004002 Purpose This counter sets the watchdog timer operation control conditions Bit No 7 6 5 Bit wD wo wo wp name CNE RsT Bit No Bit name Description 0 WDCKO Clock source selection LSB 1 WDCKI Clock source selection 2 WDCK2 Clock source selection MSB These bits select the clock source for the high order 8 bits of the counter When FRQS is high When FRQS is low 000 1 28 of the OSCI input 000 1 2 of the OSCI input 001 1 2 of the OSCI input 001 1 2 of the OSCI input 010 1 2 of the OSCI input 010 1 2 of the OSCI input 011 1 2 of the OSCI input 011 1 2 of the OSCI input 100 1 2 5 of the OSCI input 100 1 2 of the OSCI input 101 Setting prohibited 101 Setting prohibited 110 Setting prohibited 110 Setting prohibited 111 Setting prohibited 111 Setting prohibited The specific overflow cycle for each FRQS value is shown in Table 10 4 2 Continued Description of Registers 269 Chapter 10 Watchdog Timer Continued Table 10 4 2 Examples of Overflow Cycle Overflow cycle Selection nen PROS is h
323. on flag 0 No underflow interrupt detected 1 Underflow interrupt detected Always returns 0 Timer 0 underflow interrupt request flag 0 No underflow interrupt requested 1 Underflow interrupt requested Always returns 0 Timer 0 underflow interrupt enable flag 0 Disabled 1 Enabled Always returns 0 Group 2 interrupt priority level register LSB Group 2 interrupt priority level register Group 2 interrupt priority level register MSB Sets a level from 6 to 0 Always returns 0 Chapter 7 Interrupt Controller 7 4 2 2 Group 3 Interrupt Control Register Register symbol G3ICR Address x 3400010C Purpose This register is used to enable group 3 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 TMIID Timer 1 underflow interrupt detection flag 0 No underflow interrupt detected 1 Underflow interrupt detected 1 to3 Always returns 0 4 TMIIR Timer 1 underflow interrupt request flag 0 No underflow interrupt requested 1 Underflow interrupt requested 5107 Always returns 0 8 Timer 1 underflow interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G3LVO Group 3 interrupt priority level register LSB 13 G3LVI Group 3 interrupt priority level register 14 G3LV2 Group 3 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 1
324. on unit The instruction multiplies the 8 bit data imm multiplicand by the contents of Dn signed 8 bit integer multiplier adds the resulting product to the 32 bit cumulative sum that is stored in the multiply and accumulate register MCRL and then stores the new resulting 32 bit cumulative sum back in multiply and accumulate register MCRL If an overflow from the 32 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes Flag Change 1 Condon Programming Cautions non extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction The operations of udf 32 imm16 Dn and udf32 imm32 Dn not assured In addition system error interrupt does not occur in these cases 402 Extension Instruction Specifications Appendices MACU Unsigned multiply and accumulate operation instruction between registers Instruction Format Macro Name MACU Dm Dn Assembler Mnemonic udf29 Dm Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the contents of Dm unsigned 32 bit integer multiplicand by the contents of Dn unsigned 32 bit integer multiplier adds the upper 32 bits and lower 32 bits of
325. onized with MCLK are supported for the internal I O bus and external buses In asynchronous mode wait control in units of CPU cycles is possible External memory is managed through partitioning into 8 blocks There is a chip select output for each block The bus width can be set to 16 or 32 bits for each block Blocks 2 to 7 permit switching between fixed wait state insertion and handshaking Blocks 0 to 5 permit switching between synchronous mode and asynchronous mode Blocks 1 to 4 can be used as DRAM space DRAM interface Address multiplexing function The low address shift amount can be selected from between 8 bits to 11 bits Supports two byte specification methods CAS or WE Support for high speed page mode Supports the page mode mix cycle DRAM Support for CAS before RAS refresh Programmable refresh cycle Avoids time penalty during storage operations through use of store buffer one word Support for storage in on chip peripheral circuits and external devices When the storage buffer is empty storage operations are completed with no wait states and the CPU can execute subsequent processing Overview Features Chapter 5 Bus Controller 5 3 Bus Configuration Fig 5 3 1 shows the bus configuration in the MN103002A MN103002A YB The chip s internal buses are the ICH bus between the CPU core and the instruction cache the DCH bus between the CPU core and the data cache the BC bus between the CPU core and the bu
326. ority ranking Reset interrupt Highest priority ranking Non maskable interrupts Level interrupt n n 0 to 6 Lowest priority ranking Interrupt mask level Interrupt levels that can be accepted IM2 IMI IMO Interrupts disabled only NMI accepted 0 0 0 Interrupt mask level Interrupt levels that can be accepted IM2 IMI IMO 0 0 0 Interrupts disabled only non maskable interrupts accepted In the 5th line of 2 7 2 2 Interrupt Control Registers GnICR GOICR is an NMI only register i In the 5th line of 2 7 2 2 Interrupt Control Registers GnICR GOICR is dedicated for non maskable interrupts Table number is added to a table of section 2 7 2 2 In the 9th line of 2 7 2 3 Interrupt Accept Group Registers IAGR Accessing the IAGR has no meaning during an NMI interrupt In the 9th line of 2 7 2 3 Interrupt Accept Group Registers IAGR Accessing the IAGR has no meaning during non maskable interrupts In the 2nd line of External pin non maskable interrupts the external NMI request flag NMIF in the In the 2nd line of External non maskable interrupts the external non maskable interrupt request flag NMIF in the The 1st line to 2nd line of System error interrupts system error interrupt is generated when a fatal error occurs such as wh
327. orresponding tag entry is set to I This dirty line is written back to external memory when the line is refilled It is important to remember that until the line is written back to external memory the consistency between the data in the data cache and the data in external memory is not being maintained Because tag array accesses and data writes are each performed in one cycle in pipeline fashion then as long as the write accesses keep hitting consecutive writes can be executed each cycle without any waits CPU clock MCLK DEC stage EX stage Tag address EO Address AX Address B comparison A MEM stage Data address Data write bus WB stage Fig 4 5 7 Operation When a Data Cache Write Hit Occurs Write back Mode Description of Operation Chapter 4 Caches Cache Miss Operation If the data cache tag array is accessed using the tag entry address field bits 10 to 4 of the data address as the address and the value in the tag address field TADD of the entry that was accessed does not match the value in the tag field of the data address or if they match but the valid bit V of that entry is 0 then a data cache write access miss is said to have occurred In write back mode even if the data cache write access results in a miss the data is written in the cache Therefore it is necessary to allocate an entry line in the cache for writing the data In addition it is als
328. ory control registers 1 through 3 Just as in the case of byte specification by WE3 through WEO the RAS signal and in the case of a write the WE signal are negated as soon as the consecutive accesses to DRAM are completed The address is shifted down and the row address is output according to the value of the SIZE and 0 bits in the DRAM control register The RASn signal n corresponds to the block number and the CAS signal are then asserted according to the values of the RTC bit RPCP bit and the WC3 through 0 bits in the DRAM control register Fig 5 8 20 shows the page mode read timing with a 32 bit bus and Fig 5 8 22 shows the page mode read timing with a 16 bit bus Fig 5 8 21 shows the page mode write timing with a 32 bit bus and Fig 5 8 23 shows the page mode write timing with a 16 bit bus Description of Operation 121 Chapter 5 Bus Controller MCLK A31 0 RASn CAS3 0 RE WE3 0 D31 0 RD WT 17 1 0 2 Row Read cycle precharge Read gt 4 Read gt cycle cycle Fig 5 8 20 32 bit DRAM Page Mode Read Timing When FRQ 0 MCLK A31 0 RASn CAS3 0 RE WE3 0 D31 0 RD WT SIZE1 0 m Column X X Column AL Eu 4 Write cycle Write cycle lt precharge gt gt
329. ory due to a write back purge operation is completed Resources mapped in the I O space x 20000000 to x 3FFFFFFF within the MN103002A MN103002A YB can be accessed while a refill write back or purge operation is in progress However this does not include accesses to cache entries during cache operations Description of Operation Chapter 4 Caches 4 6 Cache Entry Address Assignments The cache memory tag array and data array are mapped in the internal I O area and can be read and written directly The access size of these arrays is the word 32 bits It is essential to note that if the contents of the tag array and the data array are overwritten while the area is being used as a cache the contents of external memory will no longer match the contents of the cache 4 6 1 Tag Array Instruction cache tag array O memory Address x 2810000x x 2810001x Way 0 entry 0 Way 0 entry 1 x 281007EX x 281007FX Nay 0 7 x 2810100x WaylhenryO x 2810101x WayLenry 281017 x 281017FX Data cache tag array I O memory map Address x 2830000x x 2830001X Way 0 entry 1 x 283007EX x 283007FX x 2830100x x 2830101x Way 1 entry 126 x 283017EX x 283017FX Fig 4 6 1 Tag Array Address Assignments Cache Entry Address Assignments 79 Chapter 4 4 6 2 Data Array Instruction cache d
330. ow interrupt request flag 0 No underflow interrupt requested 1 Underflow interrupt requested Always returns 0 Timer 6 underflow interrupt enable flag 0 Disabled 1 Enabled Always returns 0 Group 8 interrupt priority level register LSB Group 8 interrupt priority level register Group 8 interrupt priority level register MSB Sets a level from 6 to 0 Always returns 0 Chapter 7 Interrupt Controller 7 4 28 Group 9 Interrupt Control Register Register symbol G9ICR Address x 34000124 Purpose This register is used to enable group 9 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 T6AID Timer 6A interrupt detection flag 0 No interrupt detected 1 Interrupt detected l to3 Always returns 0 4 T6AIR Timer 6A interrupt request flag 0 No interrupt requested 1 Interrupt requested 5to7 Always returns 0 8 T6AIE Timer 6A interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G9LVO Group 9 interrupt priority level register LSB 13 G9LV1 Group 9 interrupt priority level register 14 G9LV2 Group 9 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 179 Chapter 7 Interrupt Controller 7 4 2 9 Group 10 Interrupt Control Register Register symbol G10ICR Address x 34000128 Purpose This register is used to enable group
331. peration MEM Completion of execution of multiply and accumulate instruction on common function unit Fig E 3 Pipeline Diagram Illustrating This Note 1 This note applies to the following instructions Word half word data multiply and accumulate instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instruction MACIHU instruction Quick multiplication instruction instruction MULQI instruction MULQU instruction MULQIU instruction Extension Instruction Specifications 419 Appendices 1 b Note on the description of word half word data multiply and accumulate instructions and multiply and accu mulate instructions When executing a word half word data multiply and accumulate instruction followed by a multiply and accumulate instruction the result produced by the word half word data multiply and accumulate instruction is used in the execution of the subsequent multiply and accumulate instruction Therefore it is essential to not initiate the subsequent multiply and accumulate instruction until after the required result of the word halfword data multiply and accumlate instruction has been output In addition two cycles must be inserted between the word half word data multiply and accumulate instruction and the subsequent multiply and ac cumulate instruction Word half word data multiply and accu
332. pt Control Register Register symbol GI9ICR Address x 3400014C Purpose This register is used to enable group 19 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 SCITID Serial 1 transmission interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1 to3 Always returns 0 4 SCITIR Serial 1 transmission interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 SCITIE Serial 1 transmission interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 GI9LVO Group 19 interrupt priority level register LSB 13 GI9LVI Group 19 interrupt priority level register 14 GI9LV2 Group 19 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 188 Description of Registers Chapter 7 Interrupt Controller 7 4 218 Group 20 Interrupt Control Register Register symbol G20ICR Address 34000150 Purpose This register is used to enable group 20 interrupts and to confirm interrupt requests and detection When reset Bit No Bit name Description 0 SC2RID Serial 2 reception interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 5 2 Serial 2 reception interrupt request 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 SC2RIE Serial 2 reception
333. r Single word Transfer DMR Edge Detection Synchronous Mode Fig 6 4 4 shows the timing chart for a one bus cycle transfer in synchronous mode from external memory to an external device that supports the acknowledge function initiated by edge detection of a DMA request signal DMR from an external source With edge detection the DMR signal is detected at its falling edge Once a DMA request is detected detection does not occur until the acknowledge signal is asserted External memory the transfer source is addressed and the data is read at the same time that the external device the transfer destination is accessed and written in coordination with the DMK signal Note that the number of bus cycles and the bus mode for an external memory access are determined by the values set in the memory control register just as in the case of an external access by the CPU However in a one bus cycle transfer the bus widths of external memory and the external device must be the same Description of Operation 155 Chapter 6 Controller One bus cycle transfer burst transfer DMR edge detection synchronous mode Transfer devices External device with acknowledge function External memory Transfer method One bus cycle burst transfer DMR edge detection Bus mode 32 bit bus synchronous mode one wait state SYSCLK 31 0 CPU DMA DMA DMA e 1 1 1 pd HM
334. r of registers with regs specification 10 Number of registers with regs specification 11 Instruction Set 381 Appendices 0200 15 UDFOO 15 UDFO00 15 UDFOO 15_ UDFU00 15 UDFU00 15 UDFU00 15 Number of Remarks UDF Dm Dn DO n UDF20 35 _ UDF20 35 UDF20 35 UDF20 35 UDFU20 35 UDFU20 35 UDFU20 35 ARWARWNALWA AW 382 Instruction Set Appendices Appendix E Extension Instruction Specifications Operation Extension Functions The MN1030 Series 32 bit microcontrollers are provided with 32 extension instructions that can be de fined by users By assigning extension functions that are suited for applications such as multiply multi ply and accumulate saturation and other operations for each model expansion and connecting the exten sion function unit through the extension function interface of the CPU core it becomes possible to perform the desired processing faster Extension instructions include the instructions UDFOO through UDF15 which transfer the contents of register or an immediate value through the extension function unit and then loads the operation results into a data register and instructions UDF20 to UDF35 which only transfer the contents of a register to the extension function unit Processing that performs user defined operations and then immediately uses the result is assigned to the UDF0O through UDF15 instructions whi
335. ransfer Burst Transfer DMR Edge Detection Synchronous Mode Fig 6 4 8 shows the timing chart for a two bus cycle burst transfer in synchronous mode from external memory to external memory initiated by edge detection of a DMA request signal DMR from an external source In two bus cycle transfer initiated by the DMR signal the acknowledge signal DMK is asserted during the write transfer cycle of the DMA transfer Note that the number of bus cycles and the bus mode for external memory access are determined by the values set in the memory control register just as in the case of external accesses performed by the CPU Transfer between devices with different bus widths is possible Description of Operation 159 Chapter 6 Controller Two bus cycle transfer single word transfer serial reception end interrupt Transfer devices Serial reception buffer External memory Transfer method bus cycles single word transfer serial reception end interrupt Bus mode Transfer source 32 bit bus synchronous mode 0 wait states Transfer destination 32 bit bus asynchronous mode 3 wait states IOCLK MCLK Serial Receive dataX Receive Serial reception m REES M end interrupt EE Hii 10431 0 IOD31 0 HO iid ig i iii f Receivedatai i iii i A31 0 PU CX DMACW X__ PU CSn a T 0
336. ransmission interrupt Sending break request Transmission bit Reception interrupt counter request Interrupt request generation DMA request generation _ request qu counter SBIn Status register SCnSTR Shift register Reception butter Start bit detection Reception buffer Parity bit check Stop bit check Reception buffer read Open drain output in I2C mode Output control SBTn Control register SCnCTR Output control Transfer clock Transfer clock control IOCLK Timer 0 timer 1 underflow Timer 2 timer 3 underflow Fig 11 3 1 Serial Interface 0 Serial Interface 1 Block Diagram Block Diagram 28 1 Chapter 11 Serial Interfaces 11 3 2 Serial Interface 2 Serial interface 2 Parity bit addition Stop bit addition Interrupt mode register SC2ICR Transmission interrupt request Reception interrupt request DMA request Control register SC2CTR Interrupt request generation DMA request generation bit counter Status register SC2STR Shift register Transfer clock Transmission buffer write Transmission buffer Shift register Transmission bit counter Reception buffer Reception buffer read Transfer clock control Timer register 5 2 Start bit Sending break Start bit detection Parity bit check Stop bit check l
337. red Dn before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the contents that are stored in Dn the quicker the result of the operation be derived Programming Cautions is added for CLRMAC Operation of MULQ The range of significant values for the multiplicand that is stored in Dm before the operation is evaluated starting point LSB evaluation unit i 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the absolute value of the contents that are stored in Dm the quicker the result of the operation can be derived i Operation of MULQI The range of significant values for the multiplier that is stored in Dn before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short the smaller the contents that are stored in Dn the quicker the result of the operation can be derived Operation of The range of significant values for the multiplicand that is stored in imm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range contain i ing these significant values In short if the num
338. released after one word is transferred if single word transfer mode is in effect after the transfer is completed if burst transfer mode is in effect or after the transfer for the set number of intermittent cycle transfers is completed if intermittent transfer mode is in effect Transfer requests from external sources The DMR signal can be used to issue a transfer request from an external source Edge detection is sup ported for the DMR signal sampling timing DMA interruption When a non maskable interrupt external bus request or DRAM refresh request is issued the DMA trans fer is interrupted Transfer is resumed after the external bus has been used or the DRAM refresh operation has been completed DMA forced end A DMA transfer can be forcibly ended by writing a 0 to the corresponding DMnTEN bit in the DMA control register Be careful not to overwrite any other bits in the DMA control register Features 137 Chapter 6 Controller 6 3 Description of DMA Registers The DMAC includes the registers that are listed in Table 6 3 1 These registers set the transfer initiation source the transfer word count etc Table 6 3 1 List of Registers Address Address Name Symbol Initial value of bits size x 32000100 DMAO control register DMOCTR 32 00000000 8 16 32 x 32000104 DMAO source address regist
339. reset 1 If set as compare register Interrupts is generated when TM6BC equal to TM6CA Cycle of timer 6 can be set to setting value 41 by clearing TM6BC when it matches with TM6CA 2 If set as compare register of double buffer The data written to TM6CA will be stored into buffer for a moment This might cause reading of the previous value rather than the new one when the reading occur just after writing to TM6CA Under following condition value in buffer is loaded into compare register 1 Initialization of timer 6 2 When overflow occurs In the case of TM6CA 0 3 When TM6BC matches with TM6CA in the case of TM6CAE 1 3 If set as capture register If TM6IOA pin gets edge selected in TM6AEG flag value of TM6BC is captured into TM6CA and then an interrupt occurs Under both edge capture setting capturing happens at either of rising or falling edge and interrupt occurs 238 Description of Registers Chapter 9 16 bit Timers 9 6 8 Timer 6 Compare Capture Register Register symbol Address x 340010D4 Purpose This register is the compare capture register B for timer 6 8 T2 uw o Ts 7v e s 2 2 1 TM6 TM6 TM6 TM6 6 TM6 TM6 6 TM6 TM6 TM6 TM6 Bit name CB12 CB10 CB8 CB7 5 CB2 CBO When reset
340. ress x 36008065 Purpose This register sets the input output direction of the port 3 pins 0 input pin 1 output pin Bi name 12 5 2 4 Port 3 Pin Register Register symbol P3IN Address x 36008085 Purpose This register is used to read the value of the port 3 pins 332 Port3 Chapter 12 Ports 12 5 3 Pin Configuration Table 12 5 1 shows the pin configuration of port 3 Table 12 5 1 Port 3 Configuration Port P3nM 1 P3nM 0 P3n P3nD 1 P30 General purpose neral purpose SBOO Serial 0 data Port 3 output port input output P3nD invalid P31 General purpose General purpose SBOI Serial 1 data output port i input output P3nD invalid After a reset Pot3 333 Chapter 12 Ports 12 6 4 12 6 1 Description of Resisters Port 4 consists of dual purpose pins that are used for address outputs A 31 and A 28 26 and chip select signals CS7 to 4 Although these pins do not actually form an I O port for the sake of convenience they are referred to as port 4 in this manual Like an I O port the control register within the port can be used to switch between the two functions of each pin The register that is used for switching the function of each pin is described below 12 6 1 1 Port 4 Dedicated Output Control Register Register symbol Address Purpose P4SS x 36008048 This port selects the pin output content CSI EC CON
341. ritten to the serial transmission buffer 5 the clock is output and the data is received The reception interrupt can be replaced with the transmission end interrupt 2 After the end of reception the SBOn pin output and the SBTn pin output are both maintained low To continue receiving write the dummy data x FF to the serial transmission buffer SCnTXB again 306 Description of Operation Chapter 11 Serial Interfaces F Stop bit send 1 When ending the data transmission write a 0 to the I2C mode selection flag SCnIIC Be sure to write 0 to this flag only when transmission possible flag SCnTXF is 0 and reception buffer is empty flag SCnRBF is 0 2 Simultaneously with the write the SBTn pin output goes high After one cycle the SBOn pin output goes high and the stop sequence is sent At this point the I2C stop sequence detection bit SCnSPF is set to 1 3 After the stop sequence is sent disable the reception operation and initialize reception The I2C start sequence detection bit SCnSTF and the I2C stop sequence detection bit SCnSPF are cleared when the serial transmission buffer SCnTXB is written or the serial reception buffer SCnRXB is read 11 5 1 6 Reception Errors Transfer in start stop synchronous mode with 8 bit data length parity on and 1 stop bit 1 1 SCnRXF ee eee ___ SCnRBF flag spin OT wat we OST we s
342. rns 0 when read Always write 0 2 SLEEP CPU operating mode control flag SLEEP transition request 3 HALT CPU operating mode control flag HALT transition request 4 STOP CPU operating mode control flag STOP transition request 5 OSCID Always returns when read 6015 Always returns 0 when read The various operating modes can be set by setting the bits as shown in the table below Table 2 3 2 Oscillation Control and Operating Mode Control Operating mode STOP HALT SLEEP OSCI OSCO Clock oscillation CPU operation clock Peripheral function operation clock NOMAL 0 0 0 0 0 Oscillating Running Running Oscillating Stopped Stopped Oscillating Stopped Running Stopped Stopped Stopped Programming Mode 21 Chapter 2 CPU 2 4 Data Formats This microcontroller can process four data types bits bytes half words and words Byte data half word data and word data can each be handled as signed or unsigned data The most significant bit is the sign bit Data in memory must be properly aligned In other words the two least significant bits of an address where word data is stored must be 00 indicating an address that is a multiple of four and the least significant bit of an address where half word data is stored must be 0 indicating an address that is a multiple of two The Little Endian format is used for the placement of bytes and bits Therefore the address of the
343. rohibited 3 wait states 0000 Setting prohibited 0010 2 wait states 0100 4 wait states Not used 0110 6 wait states PAGE 1110 14 wait states Setting an odd number of wait states is prohibited 7 wait states 2 When using the external bus trace function When 0 number of wait states counted by MCLK When 1 number of wait states counted by MCLK Page mode 0000 0 wait states 0001 1 wait states 0010 2 wait states 0011 3 wait states 0000 0 wait states x 0010 2 wait states 0111 7 wait states 0100 4 wait states 0110 6 wait states 0000 Setting prohibited 1110 14 wait states 0001 Setti hibited Setting an odd number of M x d wait states is prohibited 0010 2 wait states 0011 3 wait states Not used 1 0111 7 states When BnDRAM of MEMCTRn is 1 DRAME is 0 DRAM mode is not valid The refresh operation is not performed when REFE is 1 and DRAME is 0 In table 5 8 1 L MCLK 40 MHz SYSCLK 20MHz IOCLK 10 MHz In table 5 8 1 FROS L 66 MHz SYSCLK 33MHz IOCLK 16 5 MHz P 107 Fig 5 8 4 Timing for Access in Synchronous Mode Fig 5 8 4 Timing for Access 32 bit Bus Synchronous Mode P 107 Fig 5 8 5 Timing for Access in Synchronous Mode 5 8 5 Timing for Access in 32 bit Bus Synchronous Mode P 108
344. rrupts and to confirm interrupt Bi name requests and detection Bit No Bit name Description 0 IQOID External interrupt O interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 IQOIR External interrupt O interrupt request flag 0 No interrupt requested 1 Interrupt requested 5to7 Always returns 0 8 IQOIE External interrupt O interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G23LVO Group 23 interrupt priority level register LSB 13 G23LVI Group 23 interrupt priority level register 14 G23LV2 Group 23 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 191 Chapter 7 Interrupt Controller 7 4 2 21 Group 24 Interrupt Control Register Register symbol G24ICR Address x 34000160 Purpose This register is used to enable group 24 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 IQI1ID External interrupt 1 interrupt detection flag 0 No interrupt detected 1 Interrupt detected 1 03 Always returns 0 4 External interrupt 1 interrupt request flag 0 No interrupt requested 1 Interrupt requested 5107 Always returns 0 8 IQUE External interrupt 1 interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G24LVO Group 24 interrupt priority level re
345. rs 9 7 2 4 Start Up by an External Trigger Timer 6 be start up with the input to TM6IOB pin Fig 9 7 13 shows the signal wave at the start up Compare capture register A B can be use as either of compare register or capture register Steps for start up 1 Select the input edge Select input edge by setting TM6BEG of TM6MDB Start up edge is oppose to the normal setting When TM6BEG 0 Falling edge of input causes starting up When TM6BEG 1 Rising edge of input causes starting up 2 Setting for the operation mode Setting for TM6MD register is shown as follows TM6CK2 1 0 optional Select any clock source TM6CAE optional 1 when setting one shot operation and the interrupt cycle TM60NE optional 1 for one shot operation TM6TGE 0 This disables timer start by an external trigger TM6PM1 0 optional This setting is ignored TM6PME 0 Selects the normal waveform TM6LDE 0 Normal operation TM6CNE 0 Stops counting operation Permission for prescaler operation set 1 into TMPSCNE of TMPSCNT register must be done before the permission for count operation of timer 6 when 1 8 IOCLK or 1 32 IOCLK is used as clock source 3 Initialization of timer Initialize timer 6 set 1 into TM6LDE of TM6MD register Clear the TM6BC Reset pin output When compare capture register has double buffer compare setting load the value from buffer into compare register Switch to the normal mode set 0 into TM6LDE must
346. rs 0 and 2 timers 1 and 3 Set the division ratio as follows Timer division ratio ABS IOCLK frequency desired baud rate 8 0 5 When the division rate is large either use timer O as a prescaler or else cascade timers 1 and 2 timers 2 and 3 When using IOCLK as the input clock the baud rate that can actually be set is as follows Baud rate IOCLK frequency timer division ratio 8 In this case the baud rate error is determined according to the following formula Baud rate error ABS IOCLK frequency timer division ratio 8 desired baud rate 1 Examples using IOCLK are shown below Baud rate bps Table 11 5 1 Baud Rates 1 when IOCLK 15 MHz When cascaded When using prescalers Timer division ratio Transfer rate error Timer division ratio Transfer rate error 19 200 98 0 35 98 0 35 9 600 195 x 0 16 96 195 x 0 16 96 4 800 391 0 10 390 195 x2 0 16 2 400 781 0 03 780 195 X4 0 16 96 1200 1563 0 03 1560 195 8 0 16 Description of Operation 297 Chapter 11 Serial Interfaces Tabie 11 5 2 Baud Rates 2 when IOCLK 12 MHz When cascaded When using prescalers Baud rate bps Timer division ratio Transfer rate error Timer division ratio Transfer rate error T 19 200 78 x 0 16 78 0 35 9 600 0 16 156 0 16 4800 0 16 312 156
347. ruction Format Types Instructions 22 Chapter 2 CPU 24 Normally the opcode is followed by an 8 16 or 32 bit immediate value displacement value or absolute value However in instruction formats S2 S4 S6 D2 and D5 above the opcode is followed by two or more immediate values displacement values or absolute values together representing a 16 bit immediate value imm16 a 32 bit immediate value imm32 a 40 bit immediate value imm40 or a 48 bit immediate value imm48 Using this notation the following instructions use 16 32 40 or 48 bit immediate values imml16 RET regs imm8 RETF regs imm8 BTST imm8 d8 An BSET 11118 d8 An BCLR imm8 d8 An imm32 CALL d16 PC regs imm8 imm40 BTST imm8 abs32 BSET imm8 abs32 BCLR imm8 abs32 imm48 CALL 432 regs imm8 2 5 2 Addressing Mode This microcontroller supports the 6 addressing modes described below that are frequently used by compilers All six addressing modes register direct immediate value register indirect register indirect with displacement absolute and register indirect with index can be used with data transfer group instructions The two addressing modes register direct and immediate addressing can be used with register operation instruc tions Register indirect with index addressing is used to efficiently address arrays and other data Instructions 2 Table 2 5 1 Addressing Mode
348. ry 0 of way 0 all that is necessary is to perform a data access on address x 28400000 mov 0 28400000 40 or mov 0 0x28400000 The most efficient way to purge multiple entries is to use the setlb instruction etc to form a loop Address 2 1 0 2840000 2840001 Way 0 entry 0 x 284007EX Way 0 entry 126 x 284007FX Way 0 entry 127 x 2840100X Way l entry 0 x 2840101x x 284017EX Way entry 126 x 284017FX Way 1 entry 127 Fig 4 5 11 Purge Addresses Before performing a purge disable the data cache and then confirm that the data cache busy bit DCBUSY in the cache control register CHCTR has been reset to 0 The data accesses that are made to the specific addresses that are used to initiate purges are dummy accesses If the data access is a read access the data that is returned is undefined If the data access is a write access no data is actually written anywhere Description of Operation 77 Chapter 4 Caches 78 4 5 3 Way Operation Mode The operation mode can be set for each way for both the instruction cache and the data cache through the cache control register CHCTR In normal operation mode the way functions as a cache but in the mode in which the refill operation is not performed even if a cache miss occurs each way can be used as RAM The RAM in this case is positioned as a cache in which a hit is always generated Therefore just as with a normal cache
349. ry control register 3 In addition because block 6 uses the same number of wait states as block 2 they are used via handshaking Note that handshaking can only be used in synchronous mode Table 5 7 2 Examples of Devices That Can Be Connected Each Block Block device Bus access style Mode Output signal Block 0 ROM Fixed wait MEMCTRO Asynchronous cso Block 1 SRAMI Fixed wait MEMCTRI Asynchronous CS1 Block 2 SRAM2 Fixed wait MEMCTR2 Synchronous CS2 Block 3 DRAMI Fixed wait DRAMCTR RAS3 1 4 DRAM2 Fixed wait DRAMCTR RASA Block5 device 1 Fixed wait MEMCTRS Asynchronous CS5 Block 6 device 2 Handshake Synchronous 56 Block 7 I O device 3 Handshake Synchronous CS7 Memory Spaces 103 Chapter 5 Bus Controller 5 8 Description of Operation 5 8 1 The frequency of the CPU operation clock MCLK can be selected through the setting of the FRQS external input pin If FRQS is high the frequency of the CPU operation clock is four times the input frequency which is the same frequency as SYSCLK if FRQS is low the frequency of the CPU operation clock is twice the input frequency Furthermore the frequency of the internal I O section operation clock IOCLK is also determined by the setting of the FRQS external input pin If FRQS is high the frequency of the internal I O section operation clock is equal to
350. s Addressing mode Address calculation Effective address Register direct Dm Dn EN a Am Immediate value imm8 regs imm16 imm32 imm40 imm48 Register indirect Am An a 725 E Gir address J Register indirect 21 48 48 with displacement d8 is sign extended d16 Am d16 An 31 0 32 bit address T d16 is sign extended d32 Am d32 An 28 48 31 0 31 0 d8 is sign extended 32 bit address 416 PC d16 is sign extended E A d32 PC 932 416 48 Branch instructions only 48 SP ae e mi is zero extended 32 bit address d16 SP d16 is zero extended nq ee 432 416748 932 SP Absolute abs16 3 4 abs 16 is zero extende abs32 abs16 32 bit address abs32 Register indirect with index 2i si 0 Di Am Di An Am An 32 bit address 31 0 1 When accessing data in register indirect with displacement and register 1 indirect with index modes the base address the contents of Am An and SP and the calculated effective address must be located within the same address space For details on memory spaces refer to section 2 6 Memory Mode Types and Selection Instructions 25 2 2 5 3 Instruc
351. s Y Operand data Operand address Instruction data Fig E 1 Block Diagram of the Extension Function Unit Extension Instruction Specifications 383 Appendices Extension Instructions Explanation of Notation The notation that is used in the explanations of the extension instruction specifications is listed below OP Dm Dn SP imm imm8 imm16 imm32 d8 416 abs 16 abs 32 d32 MDR MDRQ MCRL MCRH MCVF LIR LAR Opcode Address register m n 3 to 0 Data register m n 3 to 0 Stack pointer Immediate value used in the general sense 8 bit immediate value 16 bit immediate value 32 bit immediate value 8 bit displacement 16 bit displacement 16 bit absolute 32 bit absolute 32 bit displacement Multiply divide register built into core Quick multiply divide register built into Extension Function unit Multiply and accumulate register built into Extension Function unit Multiply and accumulate register built into Extension Function unit Multiply and accumulate flag built into Extension Function unit Loop instruction register Loop address register Program status word Program counter Indirect addressing Multiple register specification Hexadecimal notation The number that follows appears in hexadecimal notation For details on indirect addressing refer to section 2 5 2 Addressin
352. s always an output and the SBI2 pin is always an input SBT2 SBT2 SBT2 Transmitter Receiver Transmitter Receiver Unidirectional transfer Bidirectional transfer __ Fig 11 5 16 Serial Interface 2 Connection Diagram Description of Operation 309 Chapter 11 Serial Interfaces 11 5 2 2 Baud Rate Serial interface 2 is equipped with an internal 7 bit dedicated counter and has a configuration that allows it to maintain a fast transfer speed even with a comparatively slow clock source For example the following settings are recommended when using IOCLK and performing a transfer at a certain speed Division ratio 1 INT IOCLK frequency desired baud rate 127 1 Division ratio 2 INT IOCLK frequency desired baud rate division ratio 1 4 0 5 Write to SC2TIM the result that is obtained by subtracting 1 from division ratio 2 If the value of division ratio 1 is 2 or higher timer 2 or timer 3 must be used for division For example set bits 0 and 1 of SC2CTR to 01 and set the timer 2 control register so that the clock is divided by the value of division ratio 1 If the value of division ratio 1 is 1 set bits 0 and 1 of SC2CTR to 00 and select IOCLK The baud rate that can actually be set is determined as follows Baud rate IOCLK frequency division ratio 1 division ratio 2 In this case the baud
353. s being ex ecuted However if a BSET or BCLR instruction is executed during program execution in external memory a bus authority release due to an external bus request or DMA transfer may be interposed between the data read and data write by the BSET or BCLR instruction If the atomic bus cycles of the BSET or BCLR instruction need to be guaranteed in a system that uses multiple processors either of the following measures should be taken 1 A program in which a BSET or BCLR instruction is executed should be placed in instruction cache Note that an external memory access is occurred if a cache miss occurs in the instruction cache 2 Program so that bus requests cannot be accepted during execution of a BSET or BCLR instruction 26 Instructions 2 2 5 31 Transfer Instructions Transfer instructions transfer data between registers or between memory and a register Transfer instructions are grouped in three types MOV type instructions EXT type instructions and the CLR instruction The MOV type instructions provide data transfer functions using the various addressing modes The displacement or the immedi ate value is sign extended depending on the operation The EXT type instructions provide the inter register trans fer functions that accompany sign extension The CLR instruction clears the contents of a register by loading 0 into it Except for the CLR function these functions do not produce changes in
354. s can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of 24 02 imm16 Dn and udf02 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases 4 1 2 Extension Instruction Specifications Appendices 579 Multiply and accumulate operation results 9 bit saturation operation instruction positive value conversion instruction Instruction Format Macro Name MCST9 Dn Assembler Mnemonic udf03 Dn Dn Operation When the 32 bit result of the multiply and accumulate operation that is stored in the multiply and accu mulate register MCRL is equal to or greater than the maximum positive value for a 9 bit signed numeric value 0x000000 the maximum positive value 0x is stored in Dn If the value stored in the multiply and accumulate register MCRL is equal to or less than the maximum negative value for a 32 bit signed numeric value 0x00000000 the maximum negative value 0x00 is stored in Dn In all other cases the contents of MCRL are stored in Dn This instruction also sets the contents of the multiply and accumulate operation overflow detect register in the V flag Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Undefined When multiply and accumulate operation overflow was detected MCVF 1 Flag Change Condition V 1 Indicates that
355. s controller and the I O bus between the bus controller and on chip I O The EX bus is an external bus user bus Table 5 3 1 lists the characteristics of each bus ICH bus CPU core IO peripherals Bus controller EX bus 6 32 1 9 External ss Address bus memory Data bus Fig 5 3 1 Bus Configuration Diagram Bus Configuraion 82 Chapter 5 Bus Controller 84 1 2 3 Table 5 3 1 Characteristics of Each Bus Bus name Blocks Bus width Operating clock ICH bus CPU instruction cache 64 MCLK DCH bus CPU data cache 32 MCLK BC bus CPU BC 32 MCLK BC internal 32 IOCLK synchronous mode MCLK asynchronous mode EX bus BC external memory SYSCLK synchronous mode external bus MCLK asynchronous mode The MCLK frequency is either four times the input frequency when FRQS high or two times the input frequency when FRQS low IOCLK is the operation clock for the internal block The IOCLK frequency is either the same as the input frequency when FRQS high or one half the input frequency when FRQS low The SYSCLK frequency is the same as the input frequency Bus Configuration Chapter 5 Bus Controller snq puau 3g sso1ppe purayu 3g 5 81 I9gjnq 21015
356. s counter points to the address of the instruction that is currently being executed Multiply Divide Register 32 bit x 1 This register is provided for multiply and divide instructions It holds the upper 32 bits of 64 bit multiplication results for multiply instructions and the 32 bit remainder for divide instructions Also for divide instructions the upper 32 bits of the dividend are loaded into this register before the division operation is executed Processor Status Word 16 bit x 1 This register indicates the status of the CPU The operation result flags interrupt mask level etc are stored in this register For details on changes in the flag settings refer to the Instruction Set Manual 15 0 0 51 so vai o of o o v e w z Fig 2 3 2 Processor Status Word Programming Model 17 Chapter 2 CPU 18 Z Zero Flag This flag is set when an operation result is all zeroes and is cleared by any other result This flag is also cleared by a reset N Negative Flag This flag is set when the MSB of an operation result is 1 and is cleared if the MSB is 0 This flag is also cleared by a reset C Carry Flag This flag is set when a carry or borrow to or from the MSB is generated in the course of executing an operation and is cleared if no carry or borrow is generated This flag is also cleared by a reset V Overflow Flag This flag is set when an overflow occurs in a signed value in the cour
357. s the clock source TM6CAE 1 Clears TM6BC when TM6CA matches TM6BC 6 0 Disables one shot operation TM6TGE 0 Disables timer start by an external trigger TM6PM1 0 optional This setting is ignored TM6PME 0 Selects the normal waveform TM6LDE 0 Normal operation TM6CNE 0 Stops counting operation 5 Initialization of timer Initialize timer 6 by setting 1 into TM6LDE of TM6MD register TM6BC is cleared and pin output is reset If TM6CA has double buffer compare register setting value in the buffer is loaded into compare register User must switch to normal mode setting 0 into TM6LDE after the initialization 6 Setting for I O port Set I O port to input pin Please refer the chapter of I O port for the register setting 7 Permission for count operation Setting 1 into TM6CNE of TM6MD register causes the starting up of count operation 260 Description of Operation Chapter 9 16 bit Timers By permitting count operation interrupt request of compare capture register A is generated whenever TM6IOB counts the specified edge value compare capture register A 1 times TM6BC is up counted with the specified edges and is cleared at the value in compare capture register A 1 times counts Changing of the interrupt cycle is available by changing TM6CA register value during count operation causing to load value in buffer into compare capture register at the fist time TM6BC is cleared TM6CA must have dou
358. se of executing an operation and is cleared if no overflow is generated This flag is also cleared by a reset IM2 to IMO Interrupt Mask These bits indicate the CPU interrupt mask level The three bits define the mask level from level 0 000 to level 7 111 with level 0 being the highest mask level The CPU accepts only those interrupt requests of a level higher than the mask level indicated here When an interrupt is accepted the IM bits are set to the priority level of that interrupt The CPU then does not accept any interrupts of the same interrupt level or lower until the processing of the interrupt that was accepted is completed The interrupt mask level is set to level 0 000 by a reset IE Interrupt Enable This bit is normally set to 1 and allows interrupts to be accepted Once the CPU accepts an interrupt request the IE bit is cleared to 0 and further acceptance of interrupts is prohibited Therefore it becomes necessary to set the IE bit again when processing nested interrupts This bit is cleared by a reset 51 to SO Software Bits These are software control bits that are used by the operating system This bits cannot be used by general user programs These bits are cleared by a reset Loop Instruction Register 32 bit x 1 This register is provided for the branch instruction Lcc and is used by the SETLB instruction to store the branch target instruction This register works together with the Lcc instruction in order to ac
359. se width edge input _ _ uk DMR3 0 ni DMA level transfer initiation setup time E78 t x 5 ns DMK3 0 DMKDD DMA level transfer initiation hold time E79 5 ns DMK3 0 Notes is the SYSCLK cycle time nr change according to the MEMCTRO setting When 0 nr 2 and when FRQ 1 4 0 tom REW Fig 13 4 11 DMA Request Input Timing in DMR edge detection mode AC Characteristics 261 Chapter 13 Electrical Characteristics SYSCLK 0 A31 0 32 bit bus mode A31 16 in 16 bit bus mode Fig 13 4 12 Output Timing in internal multiply by 4 bus wait state synchronous mode 13 4 6 Interrupt Signal Timing Table 13 4 12 AC Characteristics 12 VDD 3 3 0 165 V Vss 0V TA 20 C to 70 C CL 50 pF Allowable values Symbol Conditions KIV Min Mi Interrupt signal input timing Refer to Fig 13 4 13 Item FRQS pi l lt External interrupt signal pulse width EET s E80 iow 1800 7 FRQS pin 1 5 tcvc ns level FRQS pin 3 5 ns 81 External NMI signal pulse width 7L devel gt _ 1 5 tcvc ns _ level Notes ty is the SYSCLK cycle time 362 AC Characteristics
360. set signal within the chip and does not manifest itself on the external reset pin Description of Operation 275 Chapter 10 Watchdog Timer 276 Description of Operation Chapter 11 Serial Interfaces Chapter 11 Serial Interfaces 11 1 Overview This microcontroller has two types of serial interfaces built in One type has two channels serial interfaces 0 and 1 and permits specification of start stop synchronous mode clock synchronous mode and I2C mode The other type has one channel serial interface 2 and is a start stop synchronous only interface Serial interface 0 Transmission interrupt 0 SBOO Transmitter SBTO Reception interrupt 0 Receiver IOCLK SBIO Timer 0 underflow Timer 2 underflow Serial interface 1 Transmission interrupt 1 SBOI Transmitter E SBTI Reception interrupt 1 Receiver IOCLK SBII Timer underflow Timer 3 underflow Serial interface 2 CTS Transmission interrupt 2 SBO2 Transmitter SBT2 Reception interrupt 2 Receiver IOCLK SBI2 Timer 2 underflow Timer 3 underflow Fig 11 1 1 Structural Diagram 278 Overview Chapter 11 Serial Interfaces 11 2 Features 11 2 4 Serial Interface 0 and 1 Clock synchronous mode Parity Character length Transmission bit sequence Clock source Maximum transfer speed Error detection during reception Buffers Interrupts DMA requests lt Start stop synchronous mode Parity
361. sion buffer 5 The SBOn pin output changes after the falling edge of the SBTn pin signal 2 After the transmission ends the SBOn pin output and the SBTn pin output are both maintained low C Data transmission 2 1 When sending data continuously write the data to the serial transmission buffer SCnTXB D Stop bit send 1 When ending the data transmission write a 0 to the mode selection flag SCnIIC Be sure to write 0 to this flag only when transmission possible flag SCnTXF is 0 and reception buffer is empty flag SCnRBF is 0 2 Simultaneously with the write the SBTn pin output goes high After one cycle the SBOn pin output goes high and the stop sequence is sent At this point the I2C stop sequence detection bit SCnSPF is set to 1 Description of Operation 305 Chapter 11 Serial Interfaces Master reception SBO pin SDA SBT pin SCL Interrupt DMA request set to transmis sion end Fig 11 5 13 Timing Chart 10 In order to enter master reception mode it is necessary to send the first byte in master transmission mode There fore the explanation below covers the settings needed after a master transmission Reception settings 1 Enable the reception operation SCnRXE 2 The parity bit is used as a substitute for Ack When receiving set the parity bit to 0 fixed SCnPB2 to 0 E Data reception 1 Once the dummy data x FF is w
362. ss occurs in the instruction cache 2 Program so that bus requests cannot be accepted during execution of a BSET or BCLR instruction 134 Cautions Chapter 6 Controller rm Chapter 6 Controller 6 1 Overview The MN103002A MN103002A YB has a built in four channel DMAC Direct Memory Access Controller that permits high speed data transfers between external devices internal I O except for the CPU s internal I O regis ters without using the CPU 6 2 Features The DMAC has the following features Number of channels 4 channels Transfer unit 8 bit 16 bit or 32 bit units Maximum transfer count 65536 Startup sources External requests Transfer requests from the DMR3 to 0 pin2 four channels External interrupts External interrupts from the IRQI pin and the IRQO pin Internal interrupts 2 3 underflow TM6A compare capture Serial 0 1 2 Transmission end reception end Software execution Set enable bit in the control register Transfer types Two bus cycle transfer Addressing is handled on both the source side and the destination side and the transfer is accomplished over two bus cycles a read cycle and a write cycle One bus cycle transfer Transfers between external memory and an external device that supports the acknowledge function are per formed in one bus cycle Transfer from an external device to external memory While the external device is accessed through the DMK sig
363. sssessucssessssessucsusesscseeseesucsuesasnucsussauestecnees 79 Fig 4 6 2 Data Array Address Assignments ttt 80 Chapter 5 Bus Controller Fig 5 3 1 Configuration 2 2 2 000 83 Fig 5 4 1 Bus Controller Block Diagram 22 00 00001 85 Fig 5 7 1 Address Format When Accessing External Memory 2 101 Fig 5 7 2 Space Re ca d at De o WE ted RES 102 Fig 5 8 1 Internal I O Space Access Synchronous Mode No Wait 105 Fig 5 8 2 Internal Space Access Synchronous Mode 1 Wait OK e 106 Fig 5 8 3 Internal I O Space Access Asynchronous Mode with Three Wait OK 107 Fig 5 8 4 Timing for Access 32 bit Bus Synchronous Mode with Fixed Wait State Insertion One Wait 109 Fig 5 8 5 Timing for Access in 32 bit Bus Synchronous Mode with Fixed Wait State Insertion Two Wait 2022 02 2 200 0 24100000 109 Fig 5 8 6 Timing for Bus Access by 32 bit Bus Handshaking c scccscccsssessssssssessecsessseestessessseeses 110 Fig 5 8 7 Timing for Access in 16 bit Bus Synchronous Mode with Fixed Wait State Insertion One Wait 111 Fig 5 8 8 Timing for Access in 16 bit Bus Synchronous Mode with Fixed Wait State Insertion Two Wait 112 Fig 5 8 9 Timin
364. ster single buffer or 01 Compare register double buffer Please select double buffer mode if the compare register s value need to be changed during the count operation 2 Give value to be compared with into compare capture register A Set value into TM6CA If the setting is double buffer the specified value won t be loaded into compare capture register at this moment Even in the case of the reading of TM6CA the previous value is read The specified value is loaded when timer 6 is initialized Fig 9 7 6 shows the timing of an interrupt for compare capture register A under counter operation of the timer 6 If it s set to double buffer mode the value is loaded from buffer into compare capture register A with the timing of clearing TM6BC When TM6CAE 1 TA A 0000 A 0001 x 0002 Compare caprure A interrupt request Fig 9 7 6 Operation of Compare Register When Clock Source IOCLK Value in TM6BC When TM6CAE 0 Description of Operation 247 Chapter 9 16 bit Timers 9 7 2 2 Setting for Capture Register Take the following steps when Timer 6 compare capture register A B as capture register before the timer 6 is initialized In this section compare capture register A is used to explain the steps however steps for compare capture register B is exactly same 1 Mode setting for the compare capture reg
365. ster to timer output set the port output control register to output and set the TM6IOA and B pins to output Set the compare capture register modes TM6MDA and B registers Set compare capture registers A and B to compare registers double buffer Set the output waveform to set when there is a match with TM6CA TM6CB and reset when there is an overflow in TM6BC Set the comparison values in TM6CA and TM6CB Write the values after performing a left shift on the data so that the register MSB and the data MSB overlap In the case of 10 bit data shift the data 6 bits to the left and write the data to bits bp15 to 6 in the TM6CA and TM6CB registers Permit count operation Once the counting operation is enabled the PWM waveform is output The basic output is an 8 bit PWM waveform and when the clock source is set to IOCLK the frequency is constant at 58 4 kHz regardless of the resolution When IOCLK 15 MHz The basic output duty ratio is determined by the high order 8 bits of the compare register The output cycle is determined the resolution The cycles the same for the corresponding 10 11 12 and 14 bit free run counters respectively Table 9 7 1 Frequencies Resolution Frequency for one cycle 10 bits 24 4 kHz 11 bits 12 2 kHz 12 bits 6 1 kHz 14 bits 1 5 kHz 1 For details on the register settings refer to Chapter 12 I O Ports 262 Description of Oper
366. ster transfer instruction Instruction Format Macro Name GETCHX Dn Assembler Mnemonic udf12 Dn Dn Operation This instruction transfers the contents of the multiply and accumulate register MCRH to Dn The contents of the multiply and accumulate overflow detect register MCVF are set into the V flag Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Flag Condition 0 Indicates that the multiply and accumulate operation is valid Always 0 Undefined Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW When udf12 Dm Dn is operated Dm is ignored The operations of ud 12 imm8 Dn udf12 imm16 Dn and udf12 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases 300 Extension Instruction Specifications Appendices GETCLX Low order 32 bit of multiply and accumlate register transfer instruction Instruction Format Macro Name GETCLX Dn Assembler Mnemonic udfi3 Dn Dn Operation This instruction transfers the contents of the multiply and accumulate register MCRL to Dn The contents of the multiply and accumulate overflow detect register MCVF are set into the V f
367. stics 4 VDD 3 3 0 165 V 55 0 20 to 70 CL 50 pF Allowable values Item Symbol Conditions Unit _ _ Min Synchronous mode data transfer signal output timing Refer to Fig 13 4 4 1 Write data hold time 2 tuns 5 ns D31 0 2 E32 Read data setup time dux 12 E ns D31 0 E33 Read data hold time k 0 2 ns D31 0 1 T E24 Data acknowledge signal setup time toks 2 12 s DK E35 Data acknowledge signal hold time isis 0 ns DK AC Characteristics 349 Chapter 13 Electrical Characteristics lcvc X n ala SYSCLK 1 5 1 57 0 1 0 LIlL LA gt RC tani RD WT ZEE RED gt lat bo E 4 tan SIZE1 0 X ERE gt read gt lt bo RE gt lt 1 tacos D31 0 in 32 bit bus mode D31 16 s in 16 bit bus mode tros toks tokn lt write gt gt tweor gt tweort D31 0 in 32 bit bus mode 031 16 in 16 bit bus mode twop twon Fig 13 4 4 Synchronous Mode Data Transfer Signal Timing n represents the number of wait states 350 Characteristics Chapter 13 Electrical Characteristics Table 13 4 5 AC Characteristics 5 VDD 3 3 V 0 165
368. struction Therefore it is essential to not initiate the subsequent MCRH MCRL access instruction until after the required result of the word halfword data multiply and accumlate instruction has been output In addition three cycles must be inserted between the word half word data multiply and accumulate instruction and the subsequent MCRH MCRL access in struction Word half word data ea multiply and accumulat Insert three cycle ks instruction 0 MCRH MCRL accesginstruction DEC Instruction Instruction decoding _ decoding i MEM WB Multiply and accumulate instruction has output the result that is required by MCRH MCRL access instruction Fig E 5 Pipeline Diagram Illustrating This Note 3 This note applies to the following instructions Word half word data multiply and accumulate instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instruction MACIHU instruction lt MCRL access instructions PUTCX instruction CLRMAC instruction GETCHX instruction GETCLX instruction Extension Instruction Specifications 421 1 4 Note on the description of byte data multiply and accumulate instructions and multiply and accumulate in structions When executing a byte data multiply and accumulate instruction followed by a multiply and accumulate instruction the res
369. sts the types of DMA transfers that can be supported Note that in a one bus cycle transfer the transfer source and the transfer destination are accessed in one bus cycle while in a two bus cycle transfer the transfer source and the transfer destination are accessed in two bus cycles External devices that support the acknowledge function use one cycle transfer The selection of one bus cycle transfer or two bus cycle transfer is made through the DMnST bits in the DMA control register Excludes the I O registers in the CPU and the I O registers in the bus controller the memory control registers The transfer modes are single word transfer mode burst mode and intermittent mode The transfer mode is se lected by setting the DMnTMI and 0 bits in the DMA control register One transfer is performed in response to one transfer request An interrupt request is generated once the number of transfers 1 to 65536 specified in the DMA transfer word count register are completed Transfer count 1 to 65536 Transfer request Transfer request Transfer request Interrupt request Fig 6 4 1 Example of Transfer in Single word Transfer Mode Description of Operation 149 Chapter 6 DMA Controller 6 4 2 2 Burst Transfer Mode The number of transfers specified in the DMA transfer count register are performed in response to one transfer request The bus is not released until the transfer is completed Transfers are only interr
370. sup ports the acknowledge function DMA channel 2 transfer addressing mode on source side LSB DMA channel 2 transfer addressing mode on source side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 2 transfer addressing mode on destination side LSB DMA channel 2 transfer addressing mode on destination side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 2 transfer direction Direction of external device that supports the acknowledge function in a one bus cycle transfer 0 Source 1 Destination DMA channel 2 transfer mode LSB DMA channel 2 transfer mode MSB 00 Burst transfer 01 Single word transfer 10 Intermittent transfer 11 Setting prohibited DMA channel 2 transfer unit LSB DMA channel 2 transfer unit MSB 00 8 bits 01 16 bits 10 32 bits 11 Setting prohibited DMA channel 2 DMR signal mode Always set to 1 DMA channel 2 DMA transfer enable 0 DMA transfer disabled 1 DMA transfer enabled DMA channel 2 DMA transfer request flag Automatically set when a startup source is generated automatically reset after one transfer operation in single word transfer mode after all transfers have been completed in intermittent transfer or burst transfer mode or in the event of a forced termination 0 No request 1 Request Note that the external request sources differ from those in control registers 0 and 1 144 Description of DMA Registers Chapter
371. t Timer 2 underflow IOCLK Timer 3 underflow Output control CTS SBO2 SBT2 Fig 11 3 2 Serial Interface 2 Block Diagram 282 Block Diagram 11 4 Description of Registers Address Table 11 4 1 List of Serial Interface Registers Name Symbol Number bits Chapter 11 Serial Interfaces Initial value Access size x 34000800 Serial O control register 1 SCOCTR 16 x 0000 8 16 x 34000804 Serial 0 interrupt mode register SCOICR 8 x 00 x 34000808 Serial 0 transmission buffer SCOTXB 8 x 00 x 34000809 Serial 0 reception buffer SCORXB x 00 x 3400080C Serial 0 status register SCOSTR x 0000 x 34000810 Serial 1 control register SCICTR x 0000 x 34000814 Serial 1 interrupt mode register SCIICR 00 x 34000818 Serial 1 transmission buffer SCITXB x 00 x 34000819 Serial 1 reception buffer SCIRXB x 00 x 3400081C Serial 1 status register SCISTR x 0000 x 34000820 Serial 2 control register SC2CTR x 0000 x 34000824 Serial 2 interrupt mode register SC2ICR x 00 x 34000828 Serial 2 transmission buffer SC2TXB x 00 x 34000829 Serial 2 reception buffer SC2RXB x 00 x 3400082C Serial 2 status register SC2STR x XX x 3400082D Serial 2 timer register SC2TIM
372. t 10 Fixed 11 Setting prohibited DMA channel 0 transfer addressing mode on destination side LSB DMA channel 0 transfer addressing mode on destination side MSB 00 Increment 01 Decrement 10 Fixed 11 Setting prohibited DMA channel 0 transfer direction Direction of external device that supports the acknowledge function in a one bus cycle transfer 0 Source 1 Destination DMA channel 0 transfer mode LSB DMA channel 0 transfer mode MSB 00 Burst transfer 01 Single word transfer 10 Intermittent transfer 11 Setting prohibited DMA channel 0 transfer unit LSB DMA channel 0 transfer unit MSB 00 8 bits 01 16 bits 10 32 bits 11 Setting prohibited DMA channel 0 DMR signal mode Always set to 1 DMA channel 0 DMA transfer enable 0 DMA transfer disabled 1 DMA transfer enabled DMA channel 0 DMA transfer request flag Automatically set when a startup source is generated automatically reset after one transfer operation in single word transfer mode after all transfers have been completed in intermittent transfer or burst transfer mode or in the event of a forced termination 0 No request 1 Request Note that the external request sources differ from those in DMA control registers 2 and 3 140 Description of DMA Registers Chapter 6 Controller DMA control register 1 Register symbol DMICTR Address x 32000200 Purpose Sets the transfer parameters for DMA channel 1 Bit US
373. ta cacheable space in which both instructions and data can be accessed Finally the space from 80000000 to x BFFFFFFF 1 GB maximum is uncacheable space Note that the unmounted space access is prohibited such as access to the internal space without a control register The operation is not assured 00000000 External memory cachable 512 MB 20000000 Internal I O 7512 MB 40000000 External memory cachable 1GB 80000000 External memory uncachable 1GB C0000000 System reserved i 1GB FFFFFFFF lt lt Fig 2 6 1 MN103002A MN103002AYB Memory Memory Map 33 Chapter 2 CPU 27 Interrupt Functions 2 7 1 Overview The most important key to real time control is the ability to shift quickly to interrupt handler processing If an interrupt is generated during the execution of an instruction that requires multiple cycles for execution multiplica tion or division instructions for example interrupt response is improved by aborting the execution of the instruc tion and immediately accepting the interrupt After control returns from the interrupt processing program the aborted instruction is re executed The speed of interrupt processing and the flexibility of software control are both improved by minimizing the system resources saved to memory when an interrupt occurs to just the six bytes of the PC and the PSW
374. table During reception Reception end Master transmission master reception possible No start sequence conflict detection function Features 279 Chapter 11 Serial Interfaces 11 2 2 Serial Interface 2 Parity Character length Transmission bit sequence Clock source Maximum transfer speed Error detection during reception Transmission interrupt Buffers Interrupts DMA requests 280 Features None 0 fixed 1 fixed even odd 7 bits 8 bits LSB or MSB selectable IOCLK Timer 2 or timer 3 underflow External clock 115 2 kbps when IOCLK is 15 MHz Parity errors overrun errors framing errors Transmission operation can be interrupted through the CTS pin Independent buffers for transmission and reception Reception and transmission buffers are both double buffers Transmission interrupts Transmission end or transmission buffer empty selectable Reception interrupts Reception end or reception end with error selectable During transmission Transmission end or transmission buffer empty selectable During reception Reception end Chapter 11 Serial Interfaces 11 3 Block Diagram 11 3 1 Serial Interface 0 and 1 Serial interface n n 0 1 Transmission buffer write Transmission buffer Shift register Start bit Open drain output for I2C mode SBOn Parity bit addition Stop bit addition Interrupt mode register SCnICR T
375. tates 0110 6 wait states 1110 14 wait states Setting an odd number of wait states is prohibited Not used PAGE 1 0000 Setting prohibited 0001 Setting prohibited 0010 Setting prohibited 0011 3 wait states 0111 7 wait states 0000 Setting prohibited 0010 2 wait states 0100 4 wait states 0110 6 wait states 1110 14 wait states Setting an odd number of wait states is prohibited Description of Registers 99 Chapter 5 Bus Controller 2 When using the external bus trace function When 0 When FRQ 1 Page mode number of wait states number of wait states counted by MCLK counted by MCLK 0000 0 wait states 0001 1 wait states 0010 2 wait states 0011 3 wait states 0000 0 wait states 0010 2 wait states 0100 4 wait states 0110 6 wait states 0111 7 wait states Setting prohibited 1110 14 wait states i ihi Setting an odd number of Not used Setting prohibited wait states is prohibited 1 2 wait states 3 wait states 7 wait states When BnDRAM of MEMCTRn is 1 and DRAME is 0 DRAM mode is not valid The refresh operation is not performed when REFE is 1 and DRAME is 0 5 6 3 2 Refresh Count Register Register symbol REFCNT Address x 32000042 Purpose Sets the DRAM refresh interval when DRAM is connected Bit No Bit name Description 0 to 15 REFC DRAM refresh interval x 0000 1 cycle X FFFF 65536 cy
376. ter 5 Bus Controller MCLK A31 0 Row RASn CAS3 0 RE WE3 0 D31 0 RD WT SIZEI 0 lt lt Read cycle 1 wait ok Write cycle OU OUUU U cm 3 lt precharge Fig 5 8 16 32 bit DRAM Read Write Timing When FRQ 0 One Wait OK A31 0 RowX Column RASn HA rge CAS3 2 RE WE3 2 D31 16 RD WT SIZE1 0 Row Column Upper half word read cycle Lower half word read cycle Lower half word write cycle TE X Row Column word write cycle Upper half Fig 5 8 17 16 bit DRAM Read Write Timing When FRQ 0 Description of Operation 119 Chapter 5 Bus Controller DRAM read write when FRQ 1 Fig 5 8 18 shows the 32 bit bus DRAM read write timing when FRQ 1 and Fig 5 8 19 shows the 16 bit bus DRAM read write timing when FRQ 1 Just as when 0 the address is shifted down and the row address is output according to the value of the SIZE1 and 0 bits in the DRAM control register The RASn signal n corresponds to the block number and the CAS signal are then asserted according to the values of the RTC bit RPCP bit and the WC3 through 0 bits in the DRAM control register Byte specifi cation is the same as when FRQ 0
377. tes Continued 88 Description of Registers Setting prohibited 001 Setting prohibited 2 wait states 011 3 wait states 14 wait states 101 5 wait states 6 wait states 111 7 wait states Chapter 5 Bus Controller Continued Bit No Bit name Description 8 IOPWCO Number of bus wait state insertions port section LSB 9 IOPWCI Number of bus wait state insertions I O port section 10 IOPWC2 Number of bus wait state insertions I O port section 11 IOPWC3 Number of bus wait state insertions port section MSB The relationship between the value of IOPWC3 to 0 and the number of wait states is shown below Synchronous mode 0 Asynchronous mode IOBM 1 number of wait states counted by IOCLK number of wait states counted by MCLK Ignore the lowest two bits 00 0 wait states 01 1 wait states Not supported 10xx 2 wait states 11 3 wait states Note that accesses to the I O port section can only be made in synchronous mode Accesses to on chip I O other than the I O port section are made in synchronous mode with 1 wait state after reset mode is released Accesses to the I O port section are made in synchronous mode with 3 wait states Description of Registers 89 Chapter 5 Bus Controller 5 6 2 Memory Control Registers 5 6 2 1 Memory Control Register 0 Register symbol MEMCTRO Address x 32000020 Purpose Sets the bus mo
378. the input frequency if FRQS is low the frequency of the internal I O section operation clock is one half the input frequency Table 5 8 1 shows examples of the number of CPU cycles that are needed for various types of CPU access when FRQS is high and when FRQS is low Table 5 8 1 Relationship Between the Clock Frequency and the Number of Cycles CPU Cycles Required for Access D 2 3 Number of Basic Bus Cycles FRQS H FRQS L Destinati f MCLK 66 MHz MCLK 66 MHz estimation SYSCLK 16 5 MHz SYSCLK 33 MHz IOCLK 16 5 MHz IOCLK 16 5 MHz L LLL Instruction cache Instruction Hit 2 2 read Miss Number of external memory Number of external memory cycles x 2 2 cycles x2 2 Data cache Read Hit 1 1 Number of external memor Number of external memory Miss cycles 2 cycles 2 Write Hit 1 1 Miss Number of external memory Number of external memory cycles 2 cycles 2 Control register in CPU Read write Read 3 write 2 Read 3 write 2 If the store buffer is used all writes to internal I O and external memory are executed in one cycle Control register in BC Read write Read 3 write 2 Read 3 write 2 Internal I O Read Synchro Number of I O bus cycles Number of 1 bus cycles nous 2105 2to3 Asynchro Number of I O
379. the output pin Refer to chapter of I O port about register setting When the timer is to be started up by an external trigger set the TM6IOB pin to input pin 254 Description of Operation Chapter 9 16 bit Timers 6 Enable the timer counting operation The counting operation starts when the TM6CNE in the TM6MD register is set to 1 If the timer is to be started by an external trigger leave TM6CNE set to 0 and set TM6TGE to 1 When starting to count up again after TM6BC and TM6CA have matched the hardware clears the TM6CNE flag to stop the counting operation TM6BC is also cleared Steps for operation termination When use output pin 1 Inhibit Starting up of timer by external trigger Set 0 into of TM6MD register 2 Terminate count operation Set 0 into TM6CNE of TM6TGE register Setting 0 to TM6TGE and TM6CNE simultaneously might cause resetting of TM6CNE due to the pin input timing To avoid this case user must set 0 into first then set 0 to TM6CNE Compare capture A interrupt request TM6CNE flag s c Fig 9 7 14 One shot Operation When Clock Source Counting clock Value 6 6 value 1X TM6CA value x 0000 Compare capture A interrupt request TM6CNE flag de Fig 9 7 15 One shot Operation When Using Prescaler Description of Operation 255 Chapter 9 16 bit Timers 9
380. the resulting 64 bit prod uct to the upper and lower 32 bits respectively of the 64 bit cumulative sum that is stored in the multiply and accumulate registers MCRH and MCRL and then stores the upper 32 bits of the new resulting cumu lative sum back in multiply and accumulate register MCRH and the lower 32 bits in multiply and accu mulate register MCRL If an overflow from the 64 bit cumulative sum data is generated when the product is added to the cumula tive sum multiply and accumulate overflow detection flag 1 is output to register MCVF Flag Changes eee e Programming Cautions A non extension instruction that consumes at least two cycles must be inserted between this instruction and the next extension instruction Extension Instruction Specifications 403 Appendices MACIU Unsigned multiply and accumulate operation instruction between immediate value and register Instruction Format Macro Name MACIU imm Dn Assembler Mnemonic udfu29 imm8 Dn imm8 is zero extended udfu29 imm16 Dn imm16 is zero extended udfu29 imm32 Dn Operation This instruction performs the multiply and accumulate operation using the multiplier and adder in the extension function unit The instruction multiplies the 32 bit data that is obtained by zero extending imm multiplicand by the contents of Dn unsigned 32 bit integer multiplier adds the upper 32 bits and lower 32 bits of the result ing 64 bit product to the
381. these cases Instruction Format Macro Name MCST9 Dn Instruction Format Macro Name MCST9 Dn Dn Following sentences are added Programming Cautions of MCST9 When ud 03 Dm Dn is operated Dm is ignored The operations of ud 03 imm8 Dn udf03 imm16 Dn and udf03 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases i Instruction Format Macro Name MCST48 Dn Dn Instruction Format Macro Name MCST48 Dn i Following sentences are added to Programming Cautions of MCST48 When ud 06 Dm Dn is operated Dm is ignored The operations of ud 06 imm8 Dn udf06 imm16 Dn and udf06 imm32 Dn are not assured In addition system error interrupt does not occur in these cases Following sentences are added Programming Cautions of BSCH The operations of ud 07 imm8 Dn udf07 imm16 Dn and udf07 imm32 Dn are not assured In addition a system error interrupt does not occur in these cases From 3rd line to 6th line of SWAP s Operation As a result bits 32 through 24 of Dm are stored in bits 32 through 24 in Dn From 3rd line to 6th line of SWAP s Operation As a result bits 31 through 24 of Dm are are stored in bits 31 through 24 in Dn Following sentences are added Programming Cautions of SW The operations of ud 08 imm8 Dn udf08 imm16
382. through bits 16 of that output are stored in Dn In all other cases the contents of MCRH and MCRL are output and bits 47 through bits 16 of that output are stored in Dn This instruction also sets the contents of the multiply and accumulate operation overflow detect register MCVF in the V flag Flag Changes When multiply and accumulate operation overflow was not detected MCVF 0 Flag Change v Indicates that the multiply and accumulate operation is valid Always 0 Undefined Undefined When multiply and accumulate operation overflow was detected MCVF 1 Flag Change Condition Indicates that the multiply and accumulate operation is invalid 1 0 Always 0 a Undefined Z Undefined Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lec instructions can evaluate the flags without waiting for the flag changes to be m reflected in the PSW When udf 06 Dm Dn is operated Dm is ignored The operations of udf 06 imm8 Dn udf06 immi6 Dn and udf06 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases 414 Extension Instruction Specifications Appendices BSCH Bit Search Instruction Format Macro Name BSCH Dm Dn Assembler Mnemonic udf07 Dm Dn Operation
383. tion This instruction is used to wait one cycle without having any effect on any of the system resources Table 2 5 10 Instruction Instruction Description NOP No operation 2 5 3 9 Extension Instructions The extension instructions are defined for the add on extension operation unit The instruction format is predeter mined and the instruction map is also reserved In the MN103002A MN103002A YB 30 extension instructions are implemented including a high speed multiplication instruction and a sum of products instruction For details on these instructions refer to Appendix E Extension Operation Instructions Table 2 5 11 List of Extension Operations UDF User extension instruction sign extension UDFU User extension instruction zero extension Instructions 31 2 2 6 Types of Memory Space The MN103002A MN103002A YB has a 4 GB linear address space in which addresses are expressed with 32 bits The address space consists of internal I O space for the chip s internal I O ports and various control regis ters and an external memory space for memory that is external to the chip The external memory space consists of cacheable space from which instructions and data that are accessed once are moved to a cache so that they can be subsequently accessed at high speed and uncacheable space the contents of which are not moved to a cache when accessed Furthermore
384. tion Set The instruction set has a simple organization and features the generation of compact and optimized code through a C compiler The instruction code size is reduced by making the basic instruction word length one byte As a result increases in the size of the assembly language program can be kept to a minimum even though the instruction set is simple since data transfers to and from memory are limited to load and store operations Table 2 5 2 Instruction Types Total of 46 instructions extension instructions Transfer instructions Transfers Sign extension Clear MOV EXT EXTH MOVBU EXTB EXTHU MOVHU EXTBU Arithmetic instructions Addition Subtraction Multiplication Division ADD INC SUB MUL ADDC INC4 Compare RE Logical operation instructions Logical product Inversion Exclusive logical sum JOR 1 AND Bit manipulation instructions Test and set est and clear 5 BSET CLR fi Shift ASR ROR Subroutine call MULU Compare instruction Shift instructions ga zs ROL Branch instructions c c SETLB A ET Lec CALLS RETF JMP TRAP RETS RTI NOP instruction No operation 2 NOP Extension instructions Extension UDF UDFU Note Interrupts are prohibited and the bus is locked occupied by the CPU when BSET or BCLR i
385. tor that generates a frequency lower than 13 0 MHz between 16 6 MHz and 26 0 MHz or higher than 33 3 MHz is prohibited The correspondence between the input frequency range and the FRQS mode is shown in Table 3 4 1 Table 3 4 1 FRQS Modes Versus Input Frequency Ranges Input frequency range FRQS mode 13 0 MHz S fosci 16 6 MHz 26 0 MHz lt fosci lt 33 3 MHz 3 4 2 Internal Clock Supply Depending on the value of the external input pin FRQS the CPU core internal RAM bus controller operating clock MCLK frequency is either twice or four times the input frequency and the internal peripheral function operating clock IOCLK frequency is either the same as or one half the input frequency Note that the clock SYSCLK that is supplied to external devices is the same frequency as the input frequency with a 50 duty ratio When the reset state is released SYSCLK MCLK and IOCLK are supplied starting after a certain oscillation stabilization wait time At 16 5 MHz the oscillation stabilization wait time is 15 888 ms Notes on use Using an oscillator with an input frequency between 16 6 MHz and 26 MHz lower than 13 0 MHz or higher than 33 3 MHz is prohibited because the operation of the PLL circuit cannot be guaranteed When using an externally supplied clock input the clock to the OSCI pin and leave the OSCO pin open Note When changing the input frequency during operation be cer
386. truction Specifications 409 SAT24 24 bit saturation operation instruction Instruction Format Macro Name SAT24 Dm Dn Assembler Mnemonic udf05 Dm Dn Operation When Dm is a 24 bit signed number which is the maximum positive value 0x007 or more the maximum positive value 0x007 is stored in Dn When Dm is 24 bit signed number which is the maximum negative value 0x 800000 or less the maximum negative value 0x 80000 0 is stored in Dn In all other cases the contents of Dm are stored in Dn Flag Changes Condition Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW The operations of ud 05 imm8 Dn udf05 imm16 Dn 14 05 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases 410 Extension Instruction Specifications Appendices MCST Multiply and accumulate operation results 8 16 32 bit saturation operation instruction Instruction Format Macro Name MCST Dm Dn MCST imm8 Dn Assembler Mnemonic ud 02 udf02 8 Only 0x20 0x10 and 0x08 are valid as values for imm8 Operation This instruction sets the contents of the multiply and accumulate operation overflow
387. truction address t Instruction data Instruction Data cache cache y Y Bus control block External interface Internal peripheral functions Fig 2 2 1 CPU Core Block Diagram Block Diagram 15 Chapter 2 CPU 2 3 2 3 1 The register set is divided into data registers that are used for arithmetic operations etc and address registers and a stack pointer that are used for pointers This arrangement contributes greatly to the improved performance of the internal architecture through reduction of instruction code sizes improved parallelism in pipeline processing etc This register set permits programming in C and other high level languages The Loop Instruction Register LIR and the Loop Address Register LAR are used for fast execution of branch instructions Loop control is made faster by using the SETLB instruction to store the branch target instruction and Programming Model Register Set Address Registers 31 0 Data Registers DO D2 D3 31 0 Stack Pointer SP 31 0 Program Counter PC 31 0 Multiply Divide Register MDR 15 0 Processor Status Word PSW 31 0 Loop Instruction Register LIR 31 0 Loop Address Register Fig 2 3 1 Register Set the instruction fetch target address and then using the Lcc instruction to perform the loop 16 Program
388. uction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW Extension Instruction Specifications 393 Appendices MULQI Signed quick multiplication instruction between immediate value and register Instruction Format Macro Name MULQI imm Dn Assembler Mnemonic udf00 imm8 Dn imm8 is sign extended udf00 immi6 Dn 111016 is sign extended udf00 imm32 Dn Operation This instruction performs multiplication quickly using the multiplier in the extension function unit The instruction multiplies the 32 bit data that is obtained by sign extending imm multiplicand by the contents of Dn signed 32 bit integer multiplier and then stores the upper 32 bits of the 64 bit result in the quick multiply register MDRQ and the lower 32 bits in Dn The range of significant values for the multiplicand that is stored in imm before the operation is evaluated starting point LSB evaluation unit 2 bytes and the operation is only performed for the range containing these significant values In short if the number of imm bits is 16 or less the operation results will be derived faster Flag Changes Flag Chage Condton 7 Undefined Undefined 1 when the MSB of the lower 32 bits of the result is 1 07 in all other cases Love Ec ex Programming Cautions
389. ude three built in 16 bit timer Two of them are reload timers down counter and can be used as either of interval timer or events counter The other one is up counter and has internal two compare capture registers 9 2 Features Timer 4 5 Reload timer Down counter Clock source Available to use either of internal clock or external clock as clock source Internal clock IOCLK 1 8 IOCLK 1 32 IOCLK Under flow of timer 0 2 are available External clock Count the rising edge of the pin input Cascaded connection By cascading timer 4 5 they can be used as pure 32 bit timer nterrupts Generate interrupt when a timer underflow occurs Timer output One half of cycle for timer underflow is possible as output Timer 6 Up counter Clock source Internal External clock are available for clock source Internal clock IOCLK 1 8 IOCLK 1 32 IOCLK Under flow of timer 0 2 are available External clock count either of rising edge or falling edge of TM6IOB pin input Compare capture register Has two compare capture register built in 224 Overview Features Chapter 9 16 bit Timers Pin output Capable of PWM output with variable cycle and duty ratio One signal Capable of PWN output with added bit Resolution 8 2 bits 8 3 bits 8 4 bits 8 6 bits Capable of one shot output Two signals Output polarity setting possible Input capture For each pin it is available to set to one of followi
390. ult produced by the byte data multiply and accumulate instruction is used in the execution of the subsequent multiply and accumulate instruction Therefore it is essential to not initiate the subsequent multiply and accumulate instruction until after the required result of the byte data multiply and accumlate instruction has been output In addition one cycles must be inserted between the byte data multiply and accumulate instruction and the subsequent multiply and accumulate instruction Insert one multiply and accumulate 7 be referenced instruction 1 Multiply and late instruction 2 t DEC ae Instruction decoding decoding EX MEM WB Multiply and accumulate instruction 1 has output the result that is required by multiply and accumulate instruction 2 Fig E 6 Pipeline Diagram Illustrating This Note 4 This note applies to the following instructions lt Byte data multiply and accumulate instructions gt MACB instruction MACIB instruction MACBU instruction MACIBU instruction lt Multiply and accumulate instructions MAC instruction MACI instruction MACH instruction MACIH instruction MACU instruction MACIU instruction MACHU instruction MACIHU instruction MACB instruction MACIB instruction MACBU instruction MACIBU instruction 422 Extension Instruction Specifications Appendices 1 e Note on the description of byte dat
391. umulate register MCRH This instruction also transfers the contents of Dn to the multiply and accumulate register MCRL The contents of the V flag are set into the multiply and accumulate overflow detect register MCVF Flag Mm Programming Cautions The operations of ud 21 imm8 Dn udf21 imm16 Dn and udf21 imm32 Dn not as sured In addition a system error interrupt does not occur in these cases 388 Extension Instruction Specifications Appendices GETX Quick multiply register transfer instruction Instruction Format Macro Name GETX Dn Assembler Mnemonic udf15 Dn Dn Operation This instruction transfers the contents of the quick multiply register MDRQ to Dn Flag Changes Chang Condition SSCs v 0 Awass 7 1 when the MSB of the transfer result is 17 0 in all other cases cn the 2 he Programming Cautions There is a one instruction delay in the updating of the PSW to reflect flag changes However the Bcc and Lcc instructions can evaluate the flags without waiting for the updating of the PSW to reflect flag changes When udf15 Dm Dn is operated Dm is ignored The operations of ud 15 imm8 Dn ud 15 imm16 Dn and udf15 imm32 Dn are not as sured In addition a system error interrupt does not occur in these cases Extension Instruction Specifications 389 Appendices GETCHX High order 32 bit of multiply and accumulate regi
392. underflow 110 Timer 2 underflow Timer 2 underflow Timer 2 underflow 111 TM4IO pin input TMSIO pin input TM6IOB pin input To use 1 8 IOCLK 1 32IOCLK it is necessary to specify the setting of the prescaler register TMPSCNT For timer 4 and 5 count at the rising edge of pin input if TMnIO pin input is selected For timer 6 count according to the TM6MDB register setting if TM6IOB pin input is selected 9 6 2 Timer 6 Mode Register Register symbol TM6MD Address 34001084 This register sets the operation control conditions for timer 6 Bit No 15 TM6 6 6 TM6 Bit name CNE LDE PME PMI When reset 0 0 0 Bit No Bit name Description 0 TM6CKO Clock source selection LSB 1 Clock source selection 2 TM6CK2 Clock source selection MSB Refer to Table 9 6 2 about clock source setting 3 Always returns 0 Continued 232 Description of Registers Continued Bit No Bit name 4 TM6CAE 5 TM6ONE 7 TM6TGE 8 to 10 11 TM6PMO 12 TM6PMI Continued Chapter 9 16 bit Timers Description Counter clear enable flag Enables disables clearing of TM6BC when TM6BC and TM6CA match 0 Do not clear TM6BC becomes a 16 bit free running counter 1 Clear When TM6CA is set as a compare register is cleared if TM6BC and TM6CA match When is set as a capture register TM6BC is clear
393. unted by MCLK External input pin x0000 Setting prohibited x0001 Setting prohibited 0010 2 wait states 0011 3 wait states 00000 Setting prohibited aia Lele Wait states 00011 Setting prohibited 00100 4 wait states 0000 Setting prohibited x0001 1 wait states x0010 2 wait states x0011 3 wait states 11111 31 wait states 1111 15 wait states 2 When using the external trace function Synchronous mode Asynchronous mode number of wait states number of wait states counted by SYSCLK counted by MCLK External input pin FRQS L x0000 Setting prohibited 00000 Setting prohibited 0001 1 wait states 00001 Setting prohibited 0010 2 wait states 00010 Setting prohibited x0011 3 wait states 00011 3 wait states FRQS H x1111 15 wait states 11111 31 wait states Bit No Bit name Description 15 FRQ Bus sequence setting 0 Basic 2 cycles 1 Basic 4 cycles For details refer to the individual timing charts The initial value of FRQ is determined by FRQS After reset mode is released block 0 is set to synchronous mode with 15 wait states and the bus width is as specified by the BMODE pin Block 0 cannot be used as a DRAM space Description of Registers 91 Chapter 5 Bus Controller 5 6 2 2 Memory Control Register 1 Register symbol MEMCTRI Address x 32000022 Purpose Sets the bus mode and the number of wait states to be inserted for external memory space blo
394. upt priority level register 14 G12LV2 Group 12 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 Description of Registers 181 Chapter 7 Interrupt Controller 7 4 2 11 Group 13 Interrupt Control Register Register symbol G13ICR Address x 34000134 Purpose This register is used to enable group 13 interrupts and to confirm interrupt requests and detection When reset Access Bit No Bit name Description 0 DMIID transfer end interrupt detection flag 0 No interrupt detected 1 Interrupt detected 103 Always returns 0 4 DMIIR transfer end interrupt request flag 0 No interrupt requested 1 Interrupt requested 5to7 Always returns 0 8 DMIIE DMAI transfer end interrupt enable flag 0 Disabled 1 Enabled 9 to 11 Always returns 0 12 G13LV0 Group 13 interrupt priority level register LSB 13 G13LV1 Group 13 interrupt priority level register 14 GI3LV2 Group 13 interrupt priority level register MSB Sets a level from 6 to 0 15 Always returns 0 182 Description of Registers Chapter 7 Interrupt Controller 7 4 2 12 Group 14 Interrupt Control Register Register symbol G14ICR Address x 34000138 Purpose This register is used to enable group 14 interrupts and to confirm interrupt requests and detection Bit No Bit name Description 0 DM2ID transfer end interrupt detection flag 0 No i
395. upted by non maskable interrupts external bus requests and DRAM refresh requests pouce Ti Transfer count 1 to 65536 Transfer request Interrupt request Fig 6 4 2 Example of Transfer in Burst Transfer Mode 6 4 2 3 Intermittent Transfer Mode The number of transfers specified in the DMA transfer word count register are performed in response to one transfer request However the bus is released once after the number of transfers specified in the DMA transfer word count register are completed During continuous transfer during the transfer of the number of intermittent cycles the bus is not released except because of a non maskable interrupt an external bus request or a DRAM refresh request Number of intermittent cycles 1 to 256 Number of intermittent cycles 1 to 256 Transfer count 1 to 65536 Transfer request Interrupt request Fig 6 4 3 Example of Transfer in Intermittent Transfer Mode 150 Description of Operation Chapter 6 Controller 6 4 3 Priority Ranking When there are multiple requests to use the bus they are processed according to the following rankings Internal bus DMA 0 gt DMA 1 gt DMA ch2 gt DMA ch3 CPU External bus DRAM refresh gt External bus request gt DMA 0 gt DMA chl gt DMA ch2 gt DMA ch3 CPU Processing proceeds as follows when there is a transfer request on a channel with a higher priority while a DMA transfer is in progress
396. us Controller 5 8 5 External Memory Space Access DRAM Space 5 8 5 1 RAS CAS Signal Timing Blocks 1 to 4 be used as DRAM space by setting the BnDRAM bits in memory control registers 1 to 4 By setting the DRAME bit in the DRAM control register it is possible to generated multiplexed address output RAS CAS signal output etc When BnDRAM 1 and DRAME 0 operation is the same as if 0 For the byte specification output is on the CAS3 through 0 signals when the BnCAS bit is set in memory control registers 1 through 4 When the BnCAS bit is cleared output is on the WE3 through 0 signals When using CAS3 through 0 WE3 is used as the WE signal when using WE3 through 0 CAS3 is used as the CAS signal The DRAM bus cycle is always asynchronous with the external clock and synchronized with MCLK The RAS CAS signal output timing can be set through the RTC bit RPCP bit and WC3 through 0 bits in the DRAM control register Figs 5 8 14 and Fig 5 8 15 show the timing charts The number of cycles is always given in terms of the number of MCLK cycles S u z A31 0 Row Cem C uim gt pan L dete ltt RTC gt wc RD WT TELE i SIZE1 0 Read Tm Write cycle Fig 5 8 14 RAS CAS Signal Timing When FRQ 0 Description
397. ust after the disable setting of instruction cache Invalidate the cache entry containing instruction sets disabling instruction cache and a following entry Description of Operation 67 4 4 5 2 4 5 2 1 Initialization The data cache is disabled when the system is reset To enable the data cache first set the data cache invalidate bit DCINV in the cache control register CHCTR to invalidate all of the entries and then set the data cache enable bit DCE Examples of an initialization routine are shown below Note that the cache control register CHCTR gains control from the moment that a data access occurs subsequent to the instruction that writes the cache control register CHCTR having entered the writing stage in the CPU pipeline When initializing the instruction cache immediately after a reset mov 0x20000070 d a0 mov 0 00000030 mov 40 a0 Invalidates the cache initialization mov 0x20000003 d d0 mov 40 a0 Enables the instruction cache data cache nop When initializing the instruction cache while it is in operation mov 0x20000070 d a0 mov 0 40 and Oxfffffffd d dO mov 0 a0 Disables the data cache setlb nop mov a0 d0 btst 0 08 40 Data cache busy check lne or 0x00000020 d d0 mov d0 a0 Invalidates the data cache initialization 68 Description of Operation Chapter 4 Caches 4 5 2 2 Read Operation
398. vhu etc that is used to write the clear data to the GnICR register and the execution of the instruction to return from the interrupt program Example After clearing a GnICR register read it again mov OxOf b dO d0 clear data movbu d0 GnICR Clears the GnICR flags GnICR address of GnICR register to be cleared movhu GnICR d1 I O bus access Reads the GnICR register that was cleared rti Return from interrupt program If there is no I O bus access between the instruction that is used to write the clear data to the GnICR register and the instruction to return from the interrupt program the return from the interrupt program is not guaran teed Particularly in a case such as that shown below where the return instruc tion follows immediately after the writing of the clear data the interrupt program will be mistakenly executed again after the return mov OxOf b dO movbu d0 GnICR Clears the GnICR flags rti Return from interrupt program 3 Before changing a GnICR register clear the IE bits in the PSW Description of Operation 203 Chapter 7 Interrupt Controller 204 Description of Operation Chapter 8 8 bit Timers Chapter 8 8 bit Timers 8 1 Overview The 8 bit timers have four built in 8 bit reload timers and can be used as interval timers or as event counters 8 2 Features Clock source Internal external clock can be selected as clock source Internal clock IOCLK 1
399. write the WE signal is asserted one MCLK cycle after the start of the bus cycle and is negated one MCLK cycle before the end of the bus cycle The minimum number of wait states for the bus cycle when FRQ is 1 is three wait states When writing byte 0 WEO is asserted and the data is output on D7 to 0 When writing byte 1 WEI is asserted and the data is output on D15 to 8 When writing byte 2 WE2 is asserted and the data is output on D23 to 16 When writing byte 3 WE3 is asserted and the data is output on D31 to 24 A31 0 ees E n Mem Ce rl D31 0 Cy RD WT wo N SIZEI 0 C GINE GERM PENNE bu bus ee Read cycle Write cycle Fig 5 8 11 Timing for Access Asynchronous Mode with 32 bit Bus FRQ 1 Three Wait OK 114 Description of Operation Chapter 5 Bus Controller 16 bit bus asynchronous mode 16 bit bus mode can be entered by inputting 0 to the BMODE pin for block 0 or by setting 0 in the BnBW 1 to 0 bit in the memory control registers for blocks 1 to 7 In 16 bit bus mode a word access 32 bits is performed through two external accesses one for the lower half word A 1 0 and one for the upper half word A 1 1 In the case of a half word access 16 bits or a byte access 8 bits the access is performed through only one external access of the corresponding address The most sign
400. y 1 entry Laffset 1 Way L entry x 282017EX Way 1 entry 126 offset 3 Way 1 entry 126 offset 2 Way 1 entry 126 offset 1 Way 1 entry 126 offset 0 x 282017FX Way 1 entry 127 offset 3 127 0ffset 2 l Way 1 entry 127 offset 1 Way 1 entry 127 0ffset 0 I 0 Way 0 entry 0 offset 0 Way 0 entry offset 0 Way 0 entry 126 offset 0 x 282007EX x 282007FX x 2820100x x 2820101x 1 ent Fig 4 6 2 Data Array Address Assignments 80 Entry Address Assignments Chapter 5 Bus Controller Chapter 5 Bus Controller 5 1 Overview In this LSI the bus controller BC controls interfacing between the CPU core on chip I O peripherals and devices external to the chip The bus controller also has DMA control functions and handles arbitration between the internal and external buses The bus controller outputs eight chip select signals RAS CAS signals and other signals for an external bus interface permitting ROM SRAM DRAM and other peripheral LSIs to be connected directly to this LSI without the need for any additional external circuits 5 2 Features The features of the bus controller are described below 1 82 High speed control of the internal and external buses through the CPU clock MCLK is possible Synchronous mode and asynchronous mode synchr
401. y using one of the following methods Method 1 Generate a DMA transfer end interrupt and have the CPU perform the transfer Method 2 Set the remaining transfer in burst transfer mode with the same transfer source on a channel with a lower priority than the transfers described above As a result of doing so the remaining transfer will be executed as soon as the above transfers are completed 1 For details on blocks refer to section 5 7 Memory Spaces 15 2 Description of Operation Chapter 6 Controller Notes on the single word transfer When the DMA single word transfer is performed in response to the initiation source of serial I F timer or interrupt sometime the transfer is performed twice for the one request of the transfer During the 2nd transfer the source destination address will be updated again They are calculated with setting in DMAC control register increment decrement or specified formula The DMA initiation source mentioned above are following serial 0 transmission end source serial 0 reception end source serial 1 transmission end source serial 1 reception end source serial 2 transmission end source serial 2 reception end source timer 2 underflow source timer 3 underflow source timer 6A compare capture source IRQO input source IRQI input source When use the above initiation source set the dummy DMA transmission generated by same request of the original DMA tra

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