- Dataman Programmers Ltd.
Contents
1. High Priority Timer 0 Overflow TFO e o eo lt TCON 5 Low ETO PTO Priority IE 1 IP 1 Timer 1 Overflow TF4 e o e o SS TCON 7 gt ET PT1 IE 3 IP 3 Timer 2 Overflovv TF2 gt 1 gt T2CON 7 es M P1 1 T2EX 9 2 2 2 2 6 IES IP 5 EXEN2 T2CON 3 RI gt 1 PA UART SCON 0 oo eo cn p T ES PS SCON 1 EA 14 P ESI P3 2 Se IEO eo e o INTO Al A TCON 1 ITO EXO PXO TCON 0 IE 0 IP 0 E P3 3 121 eo eo INT1 S ol 3 x TCON 3 IT1 EX1 EA PX1 TCON 2 IE 2 1 7 IP 2 Low level triggered Falling edge triggered Figure 5 Interrupt Request Sources 24 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Source Request Flags Vectors Vector Address RESET IEO TFO IE1 TF1 RI TI TF2 EXF2 RESET External interrupt O Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt 00004 0003H 000 0013H 001BH 0023H 002BH Table 8 Interrupt Sources and their Corresponding Interrupt Vectors A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority in terrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is servi2. Address Register Bit 7 6 5 4 3 2 1 0 80H PO 81H SP 82H DPL 83H DPH 87H PCON SMOD GF1 GFO PDE IDLE 88H TCON TF1 TR1 TFO TRO IE1 IT1 IEO ITO 89H TMOD GATE C T M1 MT GATE C T M1 MO 8AH TLO 8BH TL1 8CH THO 8 TH1 8EH AUXRO AO 8FH CKCON X2 90H P1 98H SCON SMO SM1 SM2 REN TB8 RB8 Tl RI 99H SBUF Au P2 A8H IE EA ET2 ES ET1 EX1 ETO EXO BOH P3 B8H IP PT2 PS PT1 PX1 PTO PXO Table 3 Contents of SFRs SFRs in Numeric Order SFR bit and byte addressable SFR not bit addressable this bit location is reserved 16 Sep 2004 Ver 1 01 599 515 525 545 565 585 Address C8H 9 D1H 0 0 Register T2CON T2MOD RC2L RC2H TL2 TH2 PSW FCON ACC B MagnaChip Bit 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CPIRL2 E S T20Et DCEN CY AC FO RS1 RSO OV F1 P FRSEL2 FRSEL1 FRSELO ERASESEL ENBOOT NTROM EN PGMSEL1 PGMSELO Table 3 Contents of SFRs SFRs in Numeric Order cont d AO AO ALE Signal Disable bit 0 Enable ALE Signal Generated ALE Signal 1 Disable ALE Signal Not Generated ALE Signal 8Fy
3. Boot ROM 2K x 8 HSB 1x8 FLASH ROM 4K 8K 16K 24K 32K x 8 PORT 3 lt WO lt VO lt UO gt IO Sep 2004 Ver 1 01 Mannath p 599 515 525 545 565 585 PIN CONFIGURATION 44 PLCC Pin Configuration top view CX r 5555 NDEX EES CORNER A CEA ASS SSS onto fFF P15 07 39 P0 4 AD4 P1 6 O 8 38 P0 5 AD5 P1 7 9 37 P0 6 ADG RESET 10 36 P0 7 AD7 RxD P3 0 41 35 EA Vpp N C 012 34 N C TxD P3 1 013 33 ALE PROG INTO P3 2 414 32 PSEN INT1 P3 3 015 31 P2 7 A15 T0 P3 4 016 30 P2 6 A14 T1 P3 5 017 29 P2 5 A13 SFRNNKARAAAR CREE 2 ss S zo c ria gt x lt N N GS le BO N C No connection 4 Sep 2004 Ver 1 01 599 515 525 545 565 585 40 PDIP Pin Configuration top view T2 P1 0 1 40 Voc T2EX P1 1 2 39 P0 0 ADO P1 2 3 38 P0 1 AD1 P1 3 4 37
4. X2 X2 CPU amp Peripheral Clock Select bit 0 Select 12 clock periods per machine cycle 1 Select 6 clock periods per machine cycle 9 T20E Sep 2004 Ver 1 01 T20E Timer2 Output Enable bit 0 Disable Timer2 Output 1 Enable Timer2 Output 17 Mannath p HMS99C51S 52S 54S 56S 58S SFR bit and byte addressable SFR not bit addressable this bit location is reserved 18 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups X2 MODE The HMS99C51S 52S 54S 56S 58S core needs only 6 clock periods per machine cycle in X2 mode This fea ture called X2 provides the following advantages Divide frequency crystals by 2 cheaper crystals while keeping same CPU power Save power consumption while keeping same CPU power oscillator power saving Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes Increase CPU power by 2 while keeping same crystal frequency In order to keep the original C51 compatibility a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core phase generator This divider may be disabled by software X2 Mode Description The clock for the whole circuit and peripheral 1s first divided by two before being used by the CPU core and peripherals This allow
5. 13 X DE a uU I uU D e C d E 19 TIMER COUNTER siii 21 TIMER Zas T 22 SERIAL INTERFACE UART sezen aa da mot 23 INTERRUPTS Y STEM sac ld pleat 24 POWER SAVING MODES tanta desta 26 ELECTRICAL CHARACTERISTICS estarse 27 OSCIEEATOR CIRCUIT z rb d n sen 39 FLASH MEMORY atun n li 43 IN SYSTEM PROGRAMMING GP 55 ISP METHOD FOR PC MAGNACHIP WINISP 66 Sep 2004 Ver 1 01 Mannath p 599 515 525 545 565 585 Sep 2004 Ver 1 01 599 515 525 545 565 585 DEVICE NAMING STRUCTURE HMS99C5XS XX 11 FLASH version MagnaChip semiconductor MCU MagnaChip Package Type Blank 40PDIP PL 44PLCC Q 44MQFP ROM size 1 4k bytes 2 8k bytes 4 16k bytes 6 24k bytes 8 32k bytes Operating Voltage C 4 5 5 5V 599 515 525 545 565 585 SELECTION GUIDE Operating ROM size bytes RAM size Device Nama Operating Voltage V FLASH bytes Frequency MHz 4K HMS99C51S 8K HMS99C52S 4 5 5 5 16K 256 HMS99C54S 40 24K HMS99C56S 32K HMS99C58S Sep 2004 Ver 1 01 Mannath p 599 515 525 545 565 585 FEATURE Fully compatible to standard MCS 51 microcontroller D Wide operating frequency up to 40MHz for more detail See HMS99C51S 52S 54S 56S 58S SELECTION GUIDE on page 1 X2 Speed Improvement capability X2 Mode 6 clocks machine cycle 20MHz 5V Equivalent to 40MHz 5V ISP In Sy
6. R tien 3 5 to 12MHz Unit Min Max Min Max RD pulse width RLRH 400 I 6tcLcL 100 ns WR pulse width ba wu 400 6tcLcL 100 ns Address hold after ALE LLAX2 53 CLCL 30 ns RD to valid data in tRLDV 252 5tcLcL 165 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 97 2tcicL 70 ns ALE to valid data in LLDV 517 8tcLcL 150 ns Address to valid data in tAVDV 585 9tci cL 165 ns ALE to WR or RD LLVVL 200 300 3tcicL 50 3teLeL 50 ns Address valid to WR or RD tAVWL 203 4tcLcL 130 ns WR or RD high to ALE high 43 123 tcLcL 40 tcLcL 40 ns Data valid to WR transition tovwx 33 CLCL 50 ns Data setup before VVR tovwH 433 7tcLcL 150 S ns Data hold after WR twHax 33 CLCL 50 ns Address float after RD RLAZ 0 x 0 ns Advance Information 12MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 12MHz Unit Min Max Oscillator period Vcc 5V CLCL 83 3 285 7 ns High time 20 tcLcL tcLcx ns Low time teLex 20 CLCL CHCX ns Rise time CLCH 20 ns Fall time CHCL 20 ns Sep 2004 Ver 1 01 31 as Mannath p 599 515 525 545 565 585 Characteristics for HMS99C51S 52S 54S 56S 58S 24MHz version SV 10 1590 Vss OV 40 C to 85 C CL for port 0 ALE and PSEN outputs 100pF Cr for all other outputs 80pF External Program Memory Characteristics
7. reserved XX D7H reserved XXu 2 DFH reserved XX 0 ACC 1 00 8 reserved 2 Eiu reserved XXu 2 E9H reserved XX E2H reserved XXu 2 EAH reserved XX 2 3 reserved XXu 2 EBH reserved XXH 2 4 reserved 2 reserved XX 5 reserved XXu 2 EDH reserved XX 6 reserved XXu 2 EEH reserved XX 7 reserved XXu 2 EFy reserved 2 FOH B 1 00H 8 reserved 2 1 reserved XXu 2 F9H reserved XXH 2 F2H reserved 2 reserved 2 3 reserved 2 reserved XX 2 F4u reserved 2 reserved XX F5H reserved XXu 2 reserved XX F6H reserved XXu 2 FEH reserved XX F7H reserved XXu 2 FFH reserved 2 Table 1 Special Function Registers in Numeric Order of their Addresses cont d 1 Bit addressable Special Function Register 2 X means that the value is indeterminate and the location is reserved 3 FCON access is reserved for the ISP software 14 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Contents Block Symbol Name Address after Reset CPU ACC Accumulator 0 1 00H B B Register 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H PSW Program Status Word Register D0H 1 00H SP Stack Pointer 81H 07H Interrupt System IE Interrupt Enable Register A8H 1 0X000000g 2 IP Interrupt Priority Register B84 1 XX000000g 2 Ports PO
8. 15 Vss OV 40 C to 85 C CL for port ALE and PSEN outputs 100pF CL for all other outputs 80pF Vcc 5V jee 3 5 MHz to 12 MHz Variable clock External Program Memory Characteristics Variable Oscillator Parameter Symbol 551 35 to 12MHz Unit Min Max Min Max ALE pulse width tLHLL 127 2tcicL 40 ns Address setup to ALE tAVLL 43 CLCL 40 ns Address hold after ALE LLAX 30 CLCL 53 ns ALE lovv to valid instruction in LLIV 233 4tci cL 100 ns ALE to PSEN LLPL 58 CLCL 25 ns PSEN pulse vvidth PLPH 215 z 3tcLcL 35 ns PSEN to valid instruction in tPLIV 150 3 CLCL 100 ns nput instruction hold after PSEN Px x 0 0 ns nput instruction float after PSEN tpxiz T 63 CLCL 20 ns Address valid after PSEN tpxAv T 75 CLCL 8 ns Address to valid instruction in taviv 302 B CLCL 115 ns Address float to PSEN AZPL 0 2 0 ns t Interfacing the HMS99C51S 52S 54S 56S 58S to devices with float times up to 75 ns is permissible This limited bus conten tion will not cause any damage to port 0 Drivers 30 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups AC Characteristics for HMS99C51S 52S 54S 56S 58S 12MHz External Data Memory Characteristics Parameter Symbol
9. Another communication interface Different protocol other data format encrypted data etc Flash areas protection Flash areas checks CRC etc Access via Specific Protocol Bootloader Flash Memory Access From User Application Figure 14 Diagram Context Description 52 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Bootloader Functional Description External Host with 3 Specific Protocol 1 User Application Communication External Host with a External Host with Specific Protocol gt Specific Protocol Communication Communication 5 External Host with Specific Protocol Communication Flash Memory 32K Bytes Figure 15 Bootloader Functional Description On the above diagram the on chip bootloader processes are ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on chip bootloader and a external device The on chip boot ROM implement a serial protocol This process translate serial commu nication frame UART into Flash memory access read write erase Flash Memory Management This process manages low level access to Flash memory performs read write and erase access Sep 2004 Ver 1 01 53 Mannath p 599 515 525 545 565 585 Bootloader Process The bootloader can be activ
10. Flash Programming and Erasure There are three methods of programming the Flash memory First the on chip ISP bootloader may be invoked which will use low level routines to program The interface used for serial downloading of Flash memory is the UART Second the Flash may be programmed or erased in the end user application by calling low level routines through a common entry point in the Boot ROM Third the Flash may be programmed using the parallel method by using conventional EPROM programmer The commercially available programmers need to have support for the HMS99C51S 525 545 565 585 The bootloader routines are located in the Boot ROM Sep 2004 Ver 1 01 43 Mannath p 599 515 525 545 565 585 Flash Memory Architecture HMS99C51S 52S 54S 56S 58S feature two on chip Flash memories Flash memory FMO 4K 8K 16K 24K 32K bytes user program memory Flash memory FM1 2K bytes for bootloader The and FM1 can be programmed by both parallel programming and Serial In System Program ming The ISP mode is detailed in the In System Programming section FFFFH ISP 807FH HSB Ibyte ao Flash Management Reserved 8 FM1 2K bytes Boot Loader 4K 8K 16K 24K 32K Bytes User Application FMO 00004 FMO Memory Architecture 4K 8K 16K 24K 32K bytes User Program Memory Hardware Security Bits HSB User Space This space is composed of a 4K 8K 16K 24K 32K bytes Flash memor
11. 2 9FH reserved XX P2 1 FFy ASH IE 1 0X000000g 2 1 reserved XXu 2 A9H reserved XX 2 reserved XXu 2 AAH reserved XX A3H reserved XXu 2 ABH reserved XX Adu reserved XXu 2 ACH reserved XX Abu reserved XXu 2 ADH reserved XX A6H reserved XXu 2 AEH reserved XX 2 ATH reserved XXu 2 AFH reserved XX P3 1 FFH 8 IP 1 000000 2 1 reserved XXu 2 B9H reserved XX B2H reserved 2 BAH reserved XX 2 B3H reserved XXu 2 BBH reserved XX B4y reserved 2 reserved XX 2 B5H reserved XXu 2 BDH reserved xx2 D reserved XXu 2 BEH reserved 2 7 reserved XXu 2 BFH reserved XX Table 1 Special Function Registers in Numeric Order of their Addresses cont d Sep 2004 Ver 1 01 13 Mannath p 599 515 525 545 565 585 Address Register d Address Register 0 reserved C8H T2CON 1 00H 1 reserved XXu 2 9 T2MOD XXXXXX00g 2 C2H reserved 2 RC2L 1 00H C3H reserved XXu 2 CBH RC2H 1 00H C4y reserved XXu 2 CCH TL2 1 00H C5H reserved XXu 2 CDH TH21 00H reserved 2 reserved XX C7H reserved XXu 2 CFy reserved XXu 2 D H PSW 1 FFH D8H reserved 2 D1y FCON 3 0000 2 9 reserved 2 D2u reserved 2 reserved XX 2 D3H reserved XXu 2 DBH reserved XXy 2 D4H reserved XXu 2 DCH reserved XX 2 D5H reserved XXu 2 DDH reserved XX D6u reserved 2
12. Command Aborted Wait Programming Y e Wait COMMAND OK Le Ee eh Send COMMAND_OK Command Finished Erase Write Flow b Example HOST 01 0010 00 55 9A BOOTLOADER 01 0010 00 55 9A CR LF Programming Data write 55g at address 0010y in the Flash HOST 02 0000 03 05 01 FS BOOTLOADER 02 0000 03 05 01 F5 CR LF Programming Lockbit function write Software Security to level 2 62 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups 3 2 Blank Check Command a Description Host Bootloader Blank Check Command Send Blank Check Command gt Wait Blank Check Command OR Wait Checksum Error amp CR amp LF Command Aborted OR Wait COMMAND OK Command Aborted amp CR 8 LF Y D H Y Wait Address not erased e Address CR amp LF Send first Address not erased Command Finished Blank Check Flow b Example HOST 05 0000 04 0000 7FFF 01 78 BOOTLOADER 05 0000 04 0000 7FFF 01 78 CR LF Blank Check ok BOOTLOADER 05 0000 04 0000 7FFF 01 70 X CR LF CR LF Blank Check with checksum error HOST 05 0000 04 0000 7FFF 01 70 BOOTLOADER 05 0000 04 0000 7FFF 01 78 xxxx CR LF Blank Check failure at add
13. Port 0 80H 1 FFy P1 Port 1 904 1 FFH P2 Port 2 A0y 1 FFH P3 Port 3 FFH Serial Channels PCON 3 Povver Control Register 87H 0XXX0000g 2 SBUF Serial Channel Buffer Reg 99H XXu 2 SCON Serial Channel 0 Control Reg 98H 1 00H Timer 0 Timer 1 TCON Timer 0 1 Control Register 88H 1 00H THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H 00H Timer 2 T2CON Timer 2 Control Register C8H 1 00H T2MOD Timer 2 Mode Register C9H 00H RC2H Timer 2 Reload Capture Reg High Byte CBu 00H RC2L Timer 2 Reload Capture Reg Low Byte CAH 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCy 00H AUXRO Aux Register 0 XXXXXXX B 2 Power Saving 3 Power Control Register 87H 0XXX0000g 2 Modes FLASH FCON 4 Flash Control Register Diy XXXX0000p 2 Table 2 Special Function Registers Functional Blocks 1 Bit addressable Special Function register 2 X means that the value is indeterminate and the location is reserved 3 This special function register is listed repeatedly since some bit of it also belong to other functional blocks 4 This special function register is reserved for the ISP software Sep 2004 Ver 1 01 15 Mannath p 599 515 525 545 565 585
14. for reading these spaces in accordance with address of Table 12 Region Addr 15 Addr 14 11 Addr 10 7 Addr 6 0 HSB 1 Bytes 0000 0111 1111 Boot 2K Bytes 1111 Variable Variable User 32K Bytes 0 Variable Variable Variable Sep 2004 Ver 1 01 Table 12 FMO Blocks Select Bits 45 as Mannath p 599 515 525 545 565 585 Flash Registers and Memory The HMS99C51S 52S 54S 56S 58S Flash memory uses several registers for its management Hardware registers can only be accessed through the parallel programming modes which are han dled by the parallel programmer Hardware Register The only hardware register of the HMS99C51S 52S 54S 56S 58S is called Hardware Security Byte HSB BLJB_EN BLJB LB2 LB1 LBO Table 13 Hardware Security Byte HSB Bit No Bit Mnemonic Description 7 5 Reserved BLJN_EN Enable BLJB Bit 4 1 BLJB is enabled for ISP Mode 0 BLJB is disabled After finishing of download must be programmed 3 BLJB Boot Loader Jump Bit 1 Start the user s application on next reset at address 0000H 0 Start the boot loader at address F800y Default 2 0 LB2 0 User Memory Lock Bits See Table 14 1 Unprogrammed 0 Programmed Note HSB can be read but can not be programmed in ISP Mode and only programmable by specific tools 46 Sep 2004 Ver 1 01 599 515 525 545 565 585 Flash Memory Lock Bits M
15. fosc Serial data enters and exits through RxD 0 0 0 TxD outputs the shift clock 8 bit are transmit ted received LSB first 8 bit UART 1 0 1 Timer 1 2 overflow rate 10 bits are transmitted through TxD or received RxD 2 i R foscor fosc 9 bit UART 32 64 11 bits are transmitted TxD or received RxD 9 bit UART 1 1 L Timer a overflow rate Like mode 2 except the variable baud rate Table 6 UART Operating Modes Baud Rate Interface Mode Baudrate derived from fosc 12 Oscillator SMOD 2 2 ei fosc 28MOD 1 3 x Timer 1 overflow Timer 1 16 bit timer 32 8 bit timer with 8 bit auto reload MOD fosc 1 3 32 12x1256 THT fosc Timer2 1 3 32 x 65536 RC2H RC2L Table 7 Formulas for Calculating Baud rates Sep 2004 Ver 1 01 23 Mannath p HMS99C51S 52S 54S 56S 58S INTERRUPT SYSTEM The HMS99C51S 52S 54S 56S 58S provide 6 above 8K bytes ROM version interrupt sources with two pri ority levels Figure 5 gives a general overview of the interrupt sources and illustrates the request and control flags
16. in four operating modes as listed in Table 4 MagnaChip TMOD Input Clock Mode Description Gate C T M1 MO internal external Max 0 8 bit timer counter with a X X 0 0 fosc 12x32 fosc 24x32 divide by 32 prescaler 1 16 bit timer counter X X 0 1 fosc 12 fosc 24 2 8 bit timer counter with X X 1 0 fosc 12 fosc 24 8 bit auto reload 3 Timer counter 0 used as X X 1 1 fosc 12 fosc 24 one 8 bit timer counter and one 8 bit timer Timer 1 stops In the timer function C T 0 the register is incremented every machine cycle Therefore the count rate is fosc 12 In the counter function the register is incremented in response to a 1 to 0 transition at its corresponding ex ternal input pin P3 4 T0 P3 5 T1 Since it takes two machine cycles to detect a falling edge the max count rate is fosc 24 External inputs INTO and INT 1 P3 2 P3 3 can be programmed to function as a gate to facilitate Table 4 Timer Counter 0 and 1 Operating Modes pulse width measurements Figure 4 illustrates the input clock logic fosc gt 12 P3 4 TO P3 5 T1 Max fosc 24 TR0 1 TCON Gate 1 TMOD 21 P3 2 INTO P3 3 INT1 fosc 12 Timer 0 1 Input Clock Figure 4 Timer Counter 0 and 1 Input
17. lt Vss the Voltage on Vcc pins with respect to ground Vss must not exceed the values defined by the absolute maxi mum ratings Sep 2004 Ver 1 01 27 Mannath p DC Characteristics 599 515 525 545 565 585 DC Characteristics for HMS99C51S 52S 54S 56S 58S 5V 10 15 Vss OV TA 40 C to 85 C Limit Values Parameter Symbol pi Test Conditions Min Max l Input low voltage z except EA RESET VIL 0 5 0 2Vcc 0 1 V Vec 5 5V Input low voltage EA 0 5 0 2Vcc 0 1 V Vec 5 5 Input low voltage RESET ViL2 0 5 0 2Vcc 0 1 V Vec 5 5 Input high voltage except 0 2Vcc E XTAL1 EA RESET Vin 0 9 Vcc 0 5 y Vcc 4 5V Input high voltage to XTAL1 ViH1 0 7Vcc Vcc 0 5 V Vec 4 5 Input high voltage to EA Ge 9 0 6 Voc 05 V Vcc 4 5V Output low voltage 1 d 1 ports 1 2 3 VoL 0 45 V Vcc 5 5V lor 1 6mA Output low voltage _ m z 1 port 0 ALE PSEN VoL1 0 45 V Vec 5 5V loi 3 2mA Output high voltage VoH 2 4 v Vec 4 5V loH 80A ports 1 2 3 0 9Vcc 4 5V lon 10A Output high voltage VoH1 2 4 4 5V loH 800uA 2 port 0 in external bus 0 9Vcc V 4 5V loH 80uA 2 mode ALE PSEN Logic 0 input current z ports 1 2 3 lit 10 65 HA Vin 0 45V Logical 1 to 0 transition cur E rent ports 1 2 3 ITL 65 650 HA Vin 2 0V Input leakage current
18. port 0 EA Iu 1 HA 0 45 lt VIN lt Vec Clo fc 1MHz Pin capacitance 10 pF Ta 25 C Power supply current Active mode 4MHz 3 lec 8 mA Vec 5V 4 Idle mode 4MHz 4 lec 4 mA 5V 5 Active mode 24 MHz 4 lcc 25 mA Vec 5V Idle mode 24MHz lec 10 mA Vcc 5V a Active mode 40 MHz 4 ma 30 m oor oV e Idle mode 40 MHz 4 es 15 m 4 CC Power Down Mode 4 IPD 50 T 28 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups 1 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VoL of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 tran sitions during bus operation In the worst case capacitive loading gt 50pF at 3 3V gt 100pF at 5V the noise pulse on ALE line may exceed 0 8V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input 2 Capacitive loading on ports O and 2 may cause the Vou on ALE and PSEN to momentarily fall below the 0 9Vcc specifica tion when the address lines are stabilizing 3 Icc Max at other frequencies is given by active mode Icc 1 27 x fosc 5 73 idle mode Icc 0 28 x fosc 1 45 except OTP devices where fosc is the oscillator frequency in MHz Icc values are given in mA and measured at Vcc 5V 4 Icc active mode is measured with XTAL1 driv
19. the signature byte device ID Family code 0700 read the software security bits 0703 read the oscillation information cc checksum Example 020000050001F0 read copy of the signature byte device id Table 20 Intel Hex Records Used by In system Programming Sep 2004 Ver 1 01 57 Magnathip 599 515 525 545 565 585 Data 0 Data 1 Command Effect Program Data Byte 00H Program Data Bootloader will accept up to 128 data bytes 01H End Of File End Of File Data 0 write times low 02H Specify E W Pulse Data 1 erase times high Erase Write pulse information setup Data 2 erase times low Bit Erase BIk0 0000y 07FFH 2K bytes Bit 1 Erase B k1 0800H 0FFFHu 2K bytes Bit 2 Erase Blk2 10004 17FFH 2K bytes 01H Block Bit 3 Erase Blk3 18004 1FFFH 2K bytes index Bit 4 Erase Blik4 20004 3FFFH 8K bytes 03H Write function Bit 5 Erase B k5 4000H 5FFFH 8K bytes Bit 6 Erase BIk0 60004y 7FFFH 8K bytes Bit 7 not used 05H Program Security Lockbit 07H Erase User Memory fully max 32K bytes Data 0 1 start address Data 2 3 end address 04H Display function Datal4 00h Display Display Data Blank Check Data 4 01h Blank check 00H 01H Read Device id 05H Read Function 00H Read Security Information 07H 03H Read Oscillator Information Table 21 ISP Commands Summary 58 S
20. 1 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The DD string represents the data bytes The maximum number of data bytes in a record is limited to 16 decimal The CC string represents the checksum byte ISP commands are summarized in Table 22 As a record is received by the HMS99C51S 52S 54S 56S 58S the information in the record is stored inter nally and a checksum calculation is performed and compared to CC The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the HMS99C518S 528 548S 568 58S will send an X out the serial port indicating a checksum error If the check sum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port displaying the contents of the internal program memory is an exception In the case of a Data Record record type 00 an additional check is made A character will NOT be sent unless the record checksum matched the calcu lated checksum and all of the bytes in the record were successfully programmed For a data record an X indicates that the checksum failed to match and an R character indicates that one of the bytes did not properl
21. 2 is an 8 bit bidirectional 1 O port with internal pull ups Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 2 pins that are externally pulled low will source current because of the pulls ups lii in the DC characteristics Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups when outputting 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 emits the contents of the P2 special function register Some Port 2 pins receive the high order address bits during flash program verify and erase operations PSEN 32 29 26 The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory RESET 10 9 4 RESET A high level on this pin for two machine cycles while the oscillator is running resets the device The port pins will be driven to their reset condition when a minimum voltage is applied whether the oscillator is running or not An internal dif
22. 24 MHz Oscillator 4 es as AME f arameter Symbol Unit Min Max Min Max ALE pulse width LHLL 43 2tcLCL 40 ns Address setup to ALE AVLL 17 CLCL 25 ns Address hold after ALE LLAX 17 CLCL 25 ns ALE lovv to valid instruction in LLIV 80 4tcLcL 87 ns ALE to PSEN LLPL 22 tci cL 20 ns PSEN pulse width tPLPH 95 3tcLcL 30 ns PSEN to valid instruction in tPLIV 60 3tcLc_ 65 ns Input instruction hold after PSEN Px x 0 0 ns nput instruction float after PSEN tpxiz t 32 CLCL 10 ns Address valid after PSEN 37 CLCL 5 ns Address to valid instruction in AVIV 148 5tcLic_ 60 ns Address float to PSEN tAZPL 0 I 0 ns t Interfacing the HMS99C51S 52S 54S 56S 58S to devices with float times up to 35 ns is permissible This limited bus conten tion will not cause any damage to port 0 Drivers 32 Sep 2004 Ver 1 01 599 515 525 545 565 585 AC Characteristics for HMS99C51S 52S 54S 56S 58S 24MHz External Data Memory Characteristics MagnaChip 24 MHz Oscillator Variable Oscillator 1 tcLcL 3 5 to 24MHz Parameter Symbol Unit Min Max Min Max RD pulse width RLRH 180 I 6tcLcL 70 ns WR pulse width ba wu 180 6tcLcL 70 ns Address hold after ALE LLAX2 15 CLCL 27 ns RD to valid data in tRLDV 118 B CLCL 90 ns Data ho
23. 5 545 565 585 Description Erase Option Select blocks for Erasure AUTO Blank Check amp Program amp Verify Auto Lock If selected with check mark the security locking is performed after erasure Connect Connect a MCU in your target Board with displaying as Connected in the status box Users have to press this button at least one time to initialize a target MCU for entering the ISP mode If failed to enter the ISP mode all the buttons are unavailable And after entering successfully the Connect button will be unavailable Edit Buffer Modify the data in the selected address in your buffer memory Fill Buffer Fill the selected area with a data Goto Display the selected page OSC MHz Display your target system s oscillator value with discarding below point Start Starting address End End address Checksum 8000 Display the checksum Hexdecimal after reading the target device Com Port Select serial port Baud Rate Select UART baud rate Select Device Select target device Page Up Key Display the previous page of your memory buffer Page Down Key Display the higher page than the current location 68 Table 22 ISP Function Description Sep 2004 Ver 1 01 599 515 525 545 565 585 Hardware Conditions to Enter the ISP Mode The In System Programming ISP is performed without removing the microcontrolle
24. 599 515 525 545 565 585 Maonat bups Basic Information H MagnaChip HMS99C5XS ISP S W ES OSC t os MHz 0000 0010 Address Range 0030 ooo 0040 end m Lee Es Erase 0040 Auto Lock SCH Connected 0000 000 0060 Checksum FF Use Key board to edit HEX data Available kevs are following Com Port Baud Rate Select Device Arrow Keys Page Up Down Enter key to update Hex data COM vi 57600 599 585 Fil Buffer Goto Function Description Load HEX File Load the data from the selected file storage into the memory buffer Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel HEX format Erase Erase the data in your target MCU before programming it Blank Check Verify whether or not a device is in an erased or unprogrammed state Program This button enables you to place new data from the memory buffer into the target device Read Read the data in the target MCU into the buffer for examination The checksum will be displayed on the checksum box Verify Assures that data in the device matches data in the memory buffer If your device is secured a verification error is detected Lock Secures devices so that their content can no longer be examined or modified Table 22 ISP Function Description Sep 2004 Ver 1 01 67 MagnaChip 599 515 52
25. ALE high VVHLH 10 40 tcLcL 20 tcLcL 20 ns Data valid to WR transition tovwx 5 CLCL 25 ns Data setup before VVR tovwH 142 7tcLcL 70 S ns Data hold after WR twHax 10 teLci 20 ns Address float after RD RLAZ 0 0 ns Advance Information 40MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 40MHz Unit Min Max Oscillator period CLCL 30 3 285 7 ns High time tcHCX 11 5 tcLcL tcLcx ns Low time CLCX 11 5 CLCL CHCX ns Rise time CLCH 5 ns Fall time CHCL 5 ns Sep 2004 Ver 1 01 35 MagnaChip 599 515 525 545 565 585 ALE PSEN PORT 0 PORT 2 LHLL i LLPL AVLE PLPI iLv tpv A8 A15 A8 A15 36 Figure 6 External Program Memory Read Cycle Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups ALE MA PORT 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH Figure 7 External Data Memory Read Cycle ALE PSEN WR PORT 0 INSTR IN PORT 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH Figure 8 External Data Memory Write Cycle Sep 2004 Ver 1 01 37 MagnaChips 599 515 525 545 565 585 Vcc 0 5V ee 0 2Vcc 0 9 b Test Points 0 2Vcc 0 1 AC Inputs during testing are driven at Vcc 0 5V for a logic 1 and 0 45V for a logic 0 Timing measurements a
26. Clock Logic Sep 2004 Ver 1 01 as Mannath p 599 515 525 545 565 585 TIMER 2 Timer 2 is a 16 bit timer Counter with an up down count feature It can operate either as timer or as an event counter which is selected by bit C T2 T2CON 1 It has three operating modes as shown in Table 5 T2CON MR A Input Clock Mode Remarks RCLK cpi exe 12 external TCLK RL2 N N2 EX P1 0 T2 16 bit Auto 0 0 1 0 0 X reload upon over fosc 12 Max Reload flow fosc 24 0 0 1 0 1 reload trigger falling edge 0 0 1 1 X 0 Down counting 0 0 1 1 X 1 Up counting 16 bit 0 1 1 X 0 X 16 bit Timer fosc 12 Capture Counter only up fosc 24 counting 0 1 1 x 1 4 capture TH2 TL2 RC2H RC2L Baud Rate 1 X 1 X 0 X no overflow fosc 12 Max Generator interrupt request fosc 24 TF2 1 x 1 x 1 extra external interrupt Timer 2 Off X X 0 X X X Timer 2 stops Table 5 Timer Counter 2 Operating Modes Note 4 S falling edge 22 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups SERIAL INTERFACE UART The serial port is full duplex and can operate in four modes one synchronous mode three asynchronous modes as illustrated in Table 6 The possible baud rates can be calculated using the formulas given in Table 7 SCON Mode Baudrate Description SMO SM1
27. LIV 56 4tcicL 65 ns ALE to PSEN LLPL 15 tc cL 15 ns PSEN pulse width tPLPH 80 3tci cL 20 ns PSEN to valid instruction in tPLIV 35 3 CLCL 55 ns nput instruction hold after PSEN Px x 0 0 ns nput instruction float after PSEN tpxiz t 20 CLCL 10 ns Address valid after PSEN 25 CLCL 5 ns Address to valid instruction in AVIV 91 5btci cL 60 ns Address float to PSEN tAZPL 0 I 0 ns t Interfacing the HMS99C51S 52S 54S 56S 58S to devices with float times up to 20 ns is permissible This limited bus conten tion will not cause any damage to port 0 Drivers 34 Sep 2004 Ver 1 01 599 515 525 545 565 585 AC Characteristics for HMS99C51S 52S 54S 56S 58S 40MHz External Data Memory Characteristics MagnaChip Parameter Symbol 277771 er to 40MHz Unit Min Max Min Max RD pulse width RLRH 132 I 6tcLcL 50 ns WR pulse width ba wu 132 6tcLcL 50 ns Address hold after ALE LLAX2 10 CLCL 20 ns RD to valid data in tRLDV 81 5tcLcL 70 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 46 2tCLCL 15 ns ALE to valid data in LLDV 153 StcLcL 90 ns Address to valid data in AVDV 183 9tcLcL 90 ns ALE to WR or RD LLVVL 71 111 32 20 3teLci 20 ns Address valid to WR or RD tavwL 66 4tcLci 55 ns WR or RD high to
28. MAGNACHIP SEMICONDUCTOR LTD 8 BIT SINGLE CHIP MICROCONTROLLERS WITH EMBEDDED FLASH HMS99C518 HMS99C528 HMS99C548 HMS99CS56S HMS99CS58S User s Manual Ver 1 01 Mag aChip Revision History Ver 1 01 Sep 10 2004 this book The company name Hynix Semiconductor Inc changed to MagnaChip Semiconductor Ltd Ver 1 0 Dec 01 2003 The first released document Version 1 01 Published by MCU Application Team 2004 MagnaChip Semiconductor Ltd All right reserved Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distrib utors and Representatives listed at address directory MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however MagnaChip semi conductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual 599 515 525 545 565 585 Maonat bups CONTENTS DEVICE NAMING STRUCTURE coca eege eege E 1 HMS99C51S 52S 54S 56S 58S SELECTION GUIDE 1 FEATURE uuu uiaiia Aa on booten UEM ae ass 2 4 PIN DEFINITIONS AND FUNCTIONS 8 FUNC TIONAL DESCRIPTION corte Ep oae l Eee estos 11 CELD RE 12 SPECIAL FUNCTION REGISTERS
29. MM 1 03 0 73 lt 1 60 REF DETAIL A 42 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups FLASH MEMORY Overview The Flash memory increases EPROM and ROM functionality with in circuit electrical erasure and program ming It contains 4K 8K 16K 24K or 32K bytes of program memory This memory is both parallel and serial In System Programmable ISP ISP allows devices to alter their own program memory in the actual end product under software control A default serial loader bootloader program allows ISP of the Flash The programming does not require 12V external programming voltage The necessary high programming voltage is generated on chip using the standard Vcc pins of the microcontroller Features Flash memory internal program memory Default loader in Boot ROM allows programming via the serial port without the need of a user pro vided loader Up to 64K byte external program memory if the internal program memory is disabled EA 0 Programming and erase voltage with standard 5V Vcc supply Read Programming Erase Programming time per byte 20us TBD Block erase Total Erase time 200ms TBD Typical programming time 32K bytes is 10s at ISP mode TBD Parallel programming with Atmel Philips chip compatible hardware interface to programmer Programmable security for the code in the Flash Endurance 10 000 cycles TBD Data retention 10 years TBD
30. P0 2 AD2 P1 4 5 36 P0 3 AD3 P1 5 6 35 P0 4 AD4 P1 6 07 34 P0 5 AD5 P1 7 8 33 P0 6 AD6 RESET 9 32 P0 7 AD7 RxD P3 0 10 31 EA Vpp TxD P3 1 11 30 ALE PROG INTO P3 2 12 29 PSEN NT1 P3 3 13 28 P2 7 A15 TO P3 4 14 27 P2 6 A14 T1 P3 5 15 26 P2 5 A13 WR P3 6 16 25 P2 4 A12 RD P3 7 17 24 P2 3 A11 XTAL2 18 Q 23 P2 2 A10 XTAL1 19 22 P2 1 A9 Vss 20 21 P2 0 A8 Sep 2004 Ver 1 01 5 Mannath p 599 515 525 545 565 585 44 MQFP Pin Configuration top view 555 BR lt lt lt lt 0506056660 D D Os m Oe nn Y 90 e O O r OW x st st st SB o 2 CO OY P1 5 1 O 33 P0 4 AD4 P1 6 2 32 P0 5 ADS P17 3 31 P0 6 AD6 RESET 4 30 P0 7 AD7 RxD P3 0 5 29 EA Vpp N C 6 28 N C TxD P3 1 7 27 ALE PROG INTO P3 2 8 26 PSEN INT1 P3 3 9 25 P2 7 A15 TO P3 4 10 24 P2 6 A14 T1 P3 5 11 23 P2 5 A13 NOXSOSLS RAN EE 2 922 ooo Zor gt ria gt lt AAN St ER BERE N C No connection 6 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Lo
31. SET CPU i Timer 0 Port 0 ALE PROG lt Port 0 8 bit Digit 1 0 PSEN Timer 1 k POR a I 8 bit Digit Timer 2 1 Port 2 Pot2 KC 8 bit Digit UO 1 Interrupt Unit Port 3 BURNER 10m Digit l O Serial Channel i I Figure 1 Block Diagram of the HMS99C51S 52S 54S 56S 58S Sep 2004 Ver 1 01 11 Mannath p 599 515 525 545 565 585 CPU The HMS99C51S 52S 54S 56S 58S are efficient both as a controller and as an arithmetic processor It has ex tensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of pro gram memory results from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 12 MHz crystal 58 of the instructions are executed in 1 0us 40MHz 300ns Special Function Register PSW MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr DO4 CY AC FO RS1 RSO OV F1 P PSW Bit Function CY Carry Flag AC Auxiliary Carry Flag for BCD operations FO General Purpose Flag RS1 RSO Register Bank select control bits 0 0 Bank selected data address 00y 074 0 1 Bank 1 selected data address 08y OFH 1 0 Bank 2 selected data address 10H 17H 1 1 Bank 3 selected data address 18H 1FH OV Overflow Flag F1 General Purpose Flag P Parity Flag Set cleared by hardware each i
32. agnaChip The three lock bits provide different levels of protection for the on chip code and data when programmed as shown in Table 14 Program Lock Bit Protection Description Security Cen LB1 LB2 Level 1 U U U No program lock features enabled MOVC instruction executed from external program memory is disabled from fetching code bytes from 2 P U U internal memory EA is sampled and latched on reset and further parallel programming of the Flash is disabled ISP and software programming with ISP are still allowed Same as 2 also verify through parallel programming 3 X P U ji interface is disabled 4 X X P Same as 3 also external execution is disable Table 14 Program Lock Bits Note U unprogrammed or 1 P programmed or 0 X don t care Note Security level 2 and 3 should only be programmed after Flash and code verification These security bits protect the code access through the parallel programming interface They are set by default to level 1 Though at level 2 3 and 4 the code access through the ISP is still possible Default Values The default value of the HSB provides parts ready to be programmed with ISP BLJB EN BLJB bit is enabled or disabled default disabled BLJB Programmed force ISP operation Default ISP inactivated LB2 0 Security level four to protect the code from a parallel access with maximum security Default Level 1 Software S
33. astic Package P LCC 44 Plastic Leaded Chip Carrier 44PLCC UNIT INCH 0 695 0 685 ti 0 656 min 0 020 0 650 gt A SE T oy r SS Le woe oo Sis SS 28 88 Los SS oco gt oo ET ET El Y B 0 012 1 0 050 BSC 0 0075 E 0428 0 090 0 180 0 165 40 Sep 2004 Ver 1 01 599 515 525 545 565 585 Plastic Package P DIP 40 Plastic Dual in Line Package MagnaChip 40DIP ERA E S A Ss MATAS r li TERA EE RFT bal 136 R 81 ET EA EE A ea E EK EE E EK s ES MS n 2 075 i 2 045 x bai E 3 a 2 X S 1 iS Me uzi Sis AN PASS 28 4 0 022 0 065 0 100 0 015 gt 7 0 045 gt lt ojo UNIT INCH 0 600 BSC 0 550 0 530 jue Bm Sep 2004 Ver 1 01 41 Mannath p Plastic Package P MPQF 44 Plastic Metric Quad Flat Package 599 515 525 545 565 585 SEE DETAIL A 44MQFP B 13 45 12 95 5 10 10 9 90 A A qa CS QIN 20 Y A 2 35 max 0 45 0 80 BSC I 9 30 UNIT
34. ated by Hardware conditions The Hardware conditions PSEN 0 EA 1 ALE 1 during the Reset falling edge force the on chip bootloader execution This allows an application to be built that will normally execute the end user s code but can be manually forced into default ISP operation As PSEN is a an output port in normal operating mode running user application or bootloader code after reset it is rec ommended to release PSEN after falling edge of reset signal The hardware conditions are sampled at reset sig nal falling edge thus they can be released at any time when reset input is low The on chip bootloader boot process is shown in Figure 16 If BLJB then ENBOOT amp INTROM_EN bit FCON is set Hardware Condition BLJB 1 EN ENBOOT 0 PSEN 0 EA 1 and ALE 1 INTROM EN 0 BLJBzO Yes 2 BLJB 0 ENBOOT 1 INTROM_EN 1 M3 Y User Application CMagnaChip Bootloader gt 00004 F800H Figure 16 Bootloader Process by hardware 54 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups IN SYSTEM PROGRAMMING ISP The In System Programming ISP is performed without removing the microcontroller from the system The ISP facility consists ofa series of internal hardware resources coupled with internal firmware to facilitate remote programming of the HMS99C51S 52S 54S 56S 58S through the serial port The MagnaChip Microcontrollers ISP facility has made in ci
35. ced If requests of the same priority are received simultaneously an internal polling sequence determines which re quest is serviced Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9 Interrupt Source Priority External Interrupt 0 IEO High Timer 0 Interrupt TFO External Interrupt 1 IE1 Timer 1 Interrupt TF1 Serial Channel RI TI y Timer 2 Interrupt TF2 EXF2 Low Table 9 Interrupt Priority Within Level Sep 2004 Ver 1 01 25 Mannath p 599 515 525 545 565 585 Power Saving Modes Two power down modes are available the Idle Mode and Power Down Mode The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode respectively If the Power Down mode and the Idle mode are set at the same time the Power Down mode takes precedence Table 10 gives a general overview of the power saving modes Entering Mode Instruction Leaving by Remarks Example Idle mode ORL PCON 01H Enabled interrupt CPU is gated off Hardware Reset CPU status registers maintain their data Peripherals are active Power Down mode ORL PCON 02H Hardware Reset Oscillator is stopped contents of on chip RAM and SFR s are maintained leaving Power Down Mode means redefinition of SFR contents Table 10 Power Saving Modes Overview In the Power Down mode of operation Vcc can be reduced to minimiz
36. ct Bit7 Bit6 VEEIOPT 1 0 A SUBE Sipe e Kos SS ar 10 VEEI 2 11V Bit5 Bit4 VPPIOPT 1 0 7 Fun pd i 7 oV 10 VPPI 2 11V Bit3 DNWOPT Define DNWELL Bias ANE E 7 1 Down the level to check a Bit2 ER VFY ER VFY erased cell around 1V 0 default around 2V 1 Up the level to check a pro Bit1 PGM VFY PGM VFY grammed cell around 6V 0 default around 5V BitO Reserved For Other Test Table 18 Power Register Bit Position Name Function Function Effect Bito EBRO Erase Block 0000H 07FFH Erase 2K Bytes Bit1 EBR1 Erase Block 0800H 0FFFu Erase 2K Bytes Bit2 EBR2 Erase Block 1000H 17FFH Erase 2K Bytes Bit3 EBR3 Erase Block 1800H 1FFFu Erase 2K Bytes Bit4 EBR4 Erase Block 2000H 3FFFu Erase 8K Bytes Bit5 EBR5 Erase Block 4000H 5FFFu Erase 8K Bytes Bit6 EBR6 Erase Block 6000H 7FFFu Erase 8K Bytes Table 19 Erase Block Register EBR Sep 2004 Ver 1 01 51 Mannath p 599 515 525 545 565 585 Bootloader Architecture Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory Furthermore all accesses and routines can be called from the user application The Flash bootloader includes The serial communication protocol The ISP command decoder In order to access User FLASH area at a custom bootloader User must modify the related FLASH registers directly This may be necessary in case of
37. e power consumption It must be ensured however that Vcc is not reduced before the Power Down mode is invoked and that Vcc is restored to its normal operating level before the Power Down mode is terminated The reset signal that terminates the Power Down mode also restarts the oscillator The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize similar to power on reset 26 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias Ca 40 to 85 C Storage temperature Cer 65 to 150 C Voltage on Vcc pins with respect to ground Vss sse 0 5V to 6 5V Voltage on any pin with respect to ground Neel 0 5V to Vcc 0 5V Input current on any pin during overload cond on aaa 10mA to 10mA Absolute sum of all input currents during overload conditon sss 100mA Ne EE EE 200mW Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the de vice This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for longer periods may affect device reliability During overload conditions Vin gt Vcc or Vin
38. ecifies the 16 bit starting load offset of the data bytes therefore this field is used only for Data Program Record see Table 20 e Record Type Record Type specifies the command type This field is used to interpret the remaining information within the frame The encoding for all the current record types is described in Table 20 Data Info D Data Info is a variable length field It consists of zero or more bytes encoded as pairs of hexadecimal digits The meaning of data depends on the Record Type e Checksum The two s complement of bytes that result from converting each pair of ASCII hexadecimal digits to one byte of binary and including the Reclen field to and including the last byte of the Data Info field Therefore the sum of all the ASCII pairs in a record after converting to binary from the Reclen field to and including the Checksum field is zero Note 1 A data byte is represented by two ASCII characters 2 When the field Load Offset is not used it should be coded as four ASCII zero characters 0 60 Sep 2004 Ver 1 01 599 515 525 545 565 585 Protocol Description 1 Overview Magnathip An initialization step must be performed after each Reset After microcontroller reset the bootloader waits for an autobaud sequence When the communication is initialized the protocol depends on the record type request ed by the host 2 Communication Initialization The host initializes the commun
39. ecurity The software security provide two different levels of protection for the on chip code and data Level 1 No program lock features enabled Level 2 ISP programming and verify of the Flash is disabled Sep 2004 Ver 1 01 47 Mannath p 599 515 525 545 565 585 Flash Memory Status HMS99C51S 52S 54S 56S 58S themselves are delivered in standard with the ISP boot code in the Flash mem ory After ISP or parallel programming the possible contents of the Flash memory are summarized on Figure 13 TFFFH HMS99C58S 32KB SFFFH HMS99C56S 24KB r 1 HMS99C54S 16KB 1FFFH HMS99C52S 8KB OFFFH HMS99C51S 4KB Virgin Application Application 0000H Default After ISP After Parallel Figure 13 Flash Memory Possible Contents Memory Organization In the HMS99C51S 52S 54S 56S 58S the lowest 4K SK 16K 24K or 32K of the 64 KB program memory ad dress space is filled by internal Flash cells When the EA pin is high the processor fetches instructions from internal program Flash memory Bus expansion for accessing program memory from 4K SK 16K 24K or 32K is upward since external instruction fetches occur automatically when the program counter exceeds FFFh 4K 1FFFh 8K 3FFFh 16K SFFFh 24K or 7FFFh 32K If the EA pin is tied low all program memory fetches are from external memory 48 Sep 2004 Ver 1 01 599 515 525 545 565 585 Flash Manag
40. ement Block Flash Management Block is controlled by ISP Command FLASH DIGITAL BLOCK P3 6 P3 7 P2 6 P2 7 EA PSEN PROG t o WR MagnaCh RESET DPTR lt 15 0 gt ACC lt 7 0 gt FLASH Parallel Mode FLASH Lock Control Block Control Block 4 Z FLASH RWE ADD Reg 2 0 Z Control Block DATA Reg 7 0 j Y CONTROL Reg 1 0 Y POWER Reg 6 0 j Y FLASH Memory FRSEL 2 0 bi EBR Reg 7 0 mA I 32K Decoder FLASH Management Block FLASH ANALOG BLOCK HV High Voltage Generator Pumps Regulators lt gt D ATA BUS lt 7 0 gt FLASH ARRAY 4K 8K 16K 24K 32KB USER AREA 2KB BOOTLOADER 1B HSB X Decoder ES X Decoder Y Decoder amp Multiplexer Sense Amp amp IO Buffer Sep 2004 Ver 1 01 ips 49 Mannath p 599 515 525 545 565 585 SFR Register for a ISP Mode FCON register exists in Diz in SFR region and defines selection of Flash register operation R W for a Flash Registers BOOT Flash usage selection of Flash Memory Space and selection of Program location PCON FCON DOH 00000000g 000000005 D7H Table 15 SFR Register for a Flash memory FCON Flash Control Register Dig Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B
41. en with tci cH tcHcL 5ns Vss 0 5V Vcc 0 5V XTAL2 N C EA Port0 RESET Vcc all other pins are disconnected Icc would be slightly higher if a crystal oscillator is used appr 1mA 5 Icc Idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Vcc 0 5V XTAL2 N C RESET EA Vss Port0 Vcc all other pins are disconnected 6 Ipp Power Down Mode is measured under following conditions EA 0 Vcc RESET Vss XTAL2 N C XTAL1 Vss all other pins are disconnected Sep 2004 Ver 1 01 29 as Mannath p 599 515 525 545 565 585 AC Characteristics Explanation of the AC Symbols Each timing symbol has 5 characters The first character is always a t stand for time The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address T Time C Clock V Valid D Input Data W WR signal H Logic level HIGH X No longer a valid logic level I Instruction program memory contents Z Float L Logic level LOW or ALE P PSEN For example Q Output Data tavLL Time from Address Valid to ALE Low R RD signal up Time from ALE Low to PSEN Low AC Characteristics for HMS99C51S 52S 54S 56S 58S 12 2 version Vec 5V Vec 5V 10
42. ep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Serial Protocol This application note describes the Serial Protocol used to program the Flash code memory from MagnaChip microcontrollers Commands sent over the serial line are interpreted by the on chip bootloader program This applied for HMS99C51S 52S 54S 56S 58S This protocol is a serial UART protocol HMS99C518 52S 548 568 588 Bootloader Serial Protocol FLASH ROM SC de gt UART Protocol Configuration 1 Physical Layer The UART used to transmit information has the following configuration Character 8 bit data Parity none Stop 1 bit Flow control none Baudrate autobaud is performed by the bootloader to compute the baudrate chosen by the host 2 Frame Description The Serial Protocol is based on the Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below Record Mark Reclen Load Offset Record Type Data or Info Checksum 1 Byte 1 Byte 2 Byte 1 Byte n Byte 1 Byte Sep 2004 Ver 1 01 59 Magnathip 599 515 525 545 565 585 D Record Mark Record Mark is the start of frame This field must contain Reclen Reclen specifies the number of bytes of information or data which follows the Record Type field of the record Load Offset e Load Offset sp
43. es of the 80C51 family as listed below 11 10 5 P3 0 RxD receiver data input asynchronous or data input output synchronous of serial interface 0 13 11 7 P3 1 TxD transmitter data output asynchronous or clock output synchronous of the serial interface 0 14 12 8 P3 2 INTO interrupt O input timer 0 gate control 15 13 9 P3 3 INT1 interrupt 1 input timer 1 gate control 16 14 10 P3 4 TO counter 0 input 17 15 11 P3 5 T1 counter 1 input 18 16 12 P3 6 WR the write control signal latches the data byte from port 0 into the external data memory 19 17 13 P3 7 RD the read control signal enables the external data memory to port 0 XTAL2 20 18 14 O XTAL2 Output of the inverting oscillator amplifier 8 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Symbol Pin Number PLCC PDIP MQFP 44 40 44 Input Output Function XTAL1 21 19 15 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times as well as rise and fall times specified in the AC characteristics must be observed P2 0 P2 7 24 31 21 28 18 25 1 0 Port 2 Port
44. f the Lock bits are programmed EA will be internally latched on reset P0 0 P0 7 36 43 32 39 30 37 1 0 Port 0 Port 0 is an 8 bit open drain bidirectional UO port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port O also receives and outputs the code bytes during program and verification respectively in the GMS99X5X External pull up resistors are required during program verification Vss 22 20 16 Circuit ground potential Vcc 44 40 38 Supply terminal for all operating modes N C 1 12 6 17 23 34 28 39 No connection 10 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups FUNCTIONAL DESCRIPTION The HMS99C51S 52S 54S 56S 58S are fully compatible to the standard 8051 microcontroller family It is compatible with the general 8051 family while maintaining all architectural and operational characteristics of the general 8051 family Figure 1 shows a block diagram of the 599 515 525 545 565 585 L 4 RAM FLASH Boot isp XTAL1 OSC amp TIMING 256 4K 8K 16K ires Du TAO 24K 32K RE
45. fused resistor to Vss permits power on reset using only an external capacitor to Vcc Sep 2004 Ver 1 01 MagnaChip 599 515 525 545 565 585 Symbol Pin Number PLCC PDIP MQFP 44 40 44 Input Output Function ALE PROG 33 30 27 The Address Latch Enable Program pulse Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory This pin is also the program pulse input PROG during EPROM programming If desired ALE operation can be disabled by setting bit O of SFR location 8Ey With this bit set the pin is weakly pulled high The ALE disable feature will be terminated by reset Setting the ALE disable bit has no affect if the microcontroller is in external execution mode EA Vpp 35 31 29 External Access Enable Program Supply Voltage EA must be externally held low to enable the device to fetch code from external program memory locations 00004 to FFFFH If EA is held high the device executes from internal program memory unless the program counter contains an address greater than its internal memory size This pin also receives the 12 75V programming supply voltage Vpp during EPROM programming Note however that if any o
46. gic Symbol Vcc Vss XTAL1 z Port 0 SE 8 bit Digital UO Port 1 RESET 4 8 bit Digital UO Port 2 8 bit Digital UO ALE PROG Port 3 D SEN 8 bit Digital UO PSEN Sep 2004 Ver 1 01 7 Magnathip 599 515 525 545 565 585 PIN DEFINITIONS AND FUNCTIONS Pin Number Input Symbol Pop MQFP Output Function 44 40 44 P1 0 P1 7 2 9 1 8 40 44 1 0 Port1 1 3 Port 1 is an 8 bit bidirectional I O port with internal pull ups Port 1 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 1 pins that are externally pulled low will source current because of the pulls ups li in the DC characteristics Port also serves alternate functions of Timer 2 as follows P1 0 T2 Clock Out Timer counter 2 external count input Clock Out 2 1 40 P1 1 T2EX Timer counter 2 trigger input 3 2 41 Port1 receives the low order address bytes during Flash programming and verifying P3 0 P3 7 11 10 17 5 7 13 1 0 Port 3 13 19 Port 3 is an 8 bit bidirectional 1 O port with internal pull ups Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 3 pins that are externally pulled low will source current because of the pulls ups li in the DC characteristics Port 3 also serves the special featur
47. ication by sending a U character to help the bootloader to compute the baudrate autobaud Host U Init communication If not received U Else Communication opened 3 Command Data Stream Protocol All commands are sent using the same flow Host Sends first character of the frame Sends frame made of 2 ASCII characters per byte Echo analysis Wi p Initialization 66 99 66 99 raf Command Flow Bootloader Performs autobaud and sends back the received byte Bootloader m gt If not received 172 1 Else Sends echo and start reception Gets frame and sends back echo for each received byte Note All commands sent with the echo mechanism will be represented by Sep 2004 Ver 1 01 61 Mannath p 599 515 525 545 565 585 3 1 Write Program Commands This flow is common to the following frames Flash Programming Data Frame EOF or MagnaChip Frame only Programming MagnaChip Frame Erase Write Timing Frame Lockbit Programming Data Frame a Description Host Bootloader Send Write Command Write Command Send Write Command F Wait Write Command Wait Checksum Error amp CR amp LF Command Aborted Wait Security Error P amp CR 8 LF
48. it 1 Bit 0 FRSEL2 FRSEL1 FRSELO ERASESEL ENBOOT INTROM_EN PGMSEL1 PGMSELO Bit No Bit Mnemonic Description Select Register Operation for Flash Access 7 5 FRSEL 2 0 This bits define register operation for Flash Memory Access See Figure 16 ERASESEL 4 ERASESEL 0 Erase Mode is deselected 1 Erase Mode is selected Enable Boot Flash 3 ENBOOT Cleared to disable boot ROM Set to map the boot ROM between F800y OFFFFH Internal ROM Access Enable bit 2 INTROM EN 0 External Memory Access over 32K bytes 1 Internal Memory Access to use Boot ROM The Program Location Select 00 Reserved 1 0 PGMSEL 1 0 01 1 Byte Program 10 4 Byte Program 11 8 Byte Program FRSEL 2 0 Operation 0 000p Reset CONTREG 7 0 Default Very Rede DATA BUS 7 0 gt ACC 7 0 DPTR 14 0 ADDREG 14 0 4 100p Write Address and Data ACC 7 0 gt DATAREG 7 0 5 101g Write CONTREG ACC 7 0 CONTREG 7 0 6 1105 Write EBR ACC 7 0 EBR 6 0 7 111B VVrite PVVR ACC 7 0 gt PVVR 7 01 50 Table 16 Register Operation Table for Flash Access Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Bit Position Name Function BitO PGM SET Program Power Setup Positive Gate Pump Setup Bit1 ER SET Erase Power Setup Negative Positive Gate Pump Setup Bit2 Bit7 Reserved Table 17 Control Register Bit Position Name Function Function Effe
49. ld after RD RHDX 0 0 ns Data float after RD RHDZ 63 2tCLCL 20 ns ALE to valid data in LLDV 200 8tcLcL 133 ns Address to valid data in tAVDV 220 9tci cL 155 ns ALE to WR or RD LLVVL 75 175 3tcLoL 50 3teLeL 50 ns Address valid to WR or RD tavwL 67 4tcLci 97 ns WR or RD high to ALE high VVHLH 17 67 CLCL 25 tcLcL 25 ns Data valid to WR transition tovwx 5 CLCL 37 ns Data setup before VVR tovwH 170 7tcici 122 S ns Data hold after WR twHax 15 tcLcL 27 ns Address float after RD RLAZ 0 S 0 ns Advance Information 24MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 24MHz Unit Min Max Oscillator period CLCL 41 7 285 7 ns High time 12 tcLcL tcLcx ns Low time teLex 12 CLCL CHCX ns Rise time CLCH 12 ns Fall time CHCL 12 ns Sep 2004 Ver 1 01 33 S WE Mannath p 599 515 525 545 565 585 AC Characteristics for HMS99C51S 52S 54S 56S 58S 40MHz version SV 10 15 Vss OV 40 C to 85 C CL for port 0 ALE and PSEN outputs 100pF CL for all other outputs 80pF External Program Memory Characteristics 40 MHz Oscillator 4 es f arameter Symbol Unit Min Max Min Max ALE pulse width LHLL 40 2tcLCL 20 ns Address setup to ALE AVLL 10 CLCL 20 ns Address hold after ALE LLAX 10 CLCL 20 ns ALE lovv to valid instruction in L
50. mand Aborted Value amp CR amp LF Wait ValueofData 11 Le Command Finished b Example HOST 02 0000 05 00 01 F8 Read Flow BOOTLOADER 02 0000 05 00 01 F8 Value CR LF Read function read device ID Sep 2004 Ver 1 01 MagnaChip Bootloader Wait Read Command Send checksum error Fs gt Read Value Y Send Data Read 65 Mannath p 599 515 525 545 565 585 ISP METHOD FOR PC MAGNACHIP WINISP Getting Started Installation The following section details the procedure for accomplishing the installation procedure 4 5 Connect the serial RS 232C cable between a target board and the 1 serial port of your PC Configure the COM serial port of your PC as following Baudrate 115 200 Data bit 8 Parity No Stop bit 1 Flow control No Turn your target B D power switch ON Your target B D must be configured to enter the ISP mode Run the MagnaChip ISP software Press the Reset Button in the ISP S W If the status windows shows a message as Connected all the conditions for ISP are provided If you press the Reset button again after connected the status windows will show the message as Disconnect ed Please discard it because the HMS99C518 528 548 568 58S can not check the reset button after connected successfully 66 Sep 2004 Ver 1 01
51. nction Code 05 Program Software Security Bits ff 05 program software security bit Level 2 inhibit reading writing to Flash Example 0100000305F7 program security bit 56 Table 20 Intel Hex Records Used by In system Programming Sep 2004 Ver 1 01 599 515 525 545 565 585 Magnathip RECORD TYPE COMMAND DATA FUNCTION Display Device Data or Blank Check Record type 04 causes the contents of the entire Flash array to be sent out the serial port in a formatted display This display consists of an address and the contents of 16 bytes starting with that address No display of the device contents will occur if security bit 2 has been programmed The dumping of the device data to the serial port is terminated by the reception of any character General Format of Function 04 05xxxx04sssseeeeffcc Where 04 05 number of bytes hex in record xxxx required field but value is a don t care 04 Display Device Data or Blank Check function code ssss starting address eeee ending address ff subfunction 00 display data 01 blank check cc checksum Example 0500000440004FFF0069 display 4000H 4FFFH Miscellaneous Read Functions General Format of Function 05 02xxxx05ffsscc Where 02 number of bytes hex in record xxxx required field but value is a don t care 05 05 Miscellaneous Read function code ffss subfunction and selection code 0001 read copy of
52. nstruction cycle to indicate an odd even number of one bits in the accumulator i e even parity Reset value of PSW is 00H 12 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks reside in the special func tion register area The 28 special function registers SFR include pointers and registers that provide an interface between the CPU and the other on chip peripherals There are also 128 directly addressable bits within the SFR area All SFRs are listed in Table 1 Table 2 and Table 3 In Table 1 they are organized in numeric order of their addresses In Table 2 they are organized in groups which refer to the functional blocks of the HMS99C51S 52S 54S 56S 58S Table 3 illustrates the contents of the SFRs Address Register 7 Address Register 7 80H Po FFH 88H TCON 1 00H 81H SP 07H 89H TMOD 00H 82H DPL 00H 8AH TLO 00H 83H DPH 00H 8Bu TL1 00H 84H reserved XXu 2 8CH THO 00H 85H reserved XXu 2 8Du TH1 00H 86H reserved 2 8EH AUXRO 2 87H PCON 0 0000 2 8FH CKCON XXXXXXX B 2 90H 1 1 FFy 98H SCON 1 00H 91H reserved 00H 99H SBUF XX 92H reserved XXu 2 9AH reserved XX 93H reserved XXH 2 9BH reserved XXH 2 94H reserved XXu 2 9CH reserved XX 95H reserved XXu 2 9DH reserved 2 96 reserved 2 9 reserved 2 97H reserved XXH
53. r from the system The In System Programming ISP facility consists of a series of internal hardware resources coupled with internal firm ware through the serial port The In System Programming ISP facility make in circuit programming in an em bedded application possible with a minimum of additional expense in components and circuit board area MagnaChip The bootloader can be executed by holding PSEN LOW EA Vpp greater than such as 5V and ALE PROG HIGH at the falling edge of RESET The ISP function block uses four pins TxD RxD Vss and Vcc Only a small connector needs to be available to interface your application to an external circuit in order to use this feature HMS99C58S RESET Vcc RxD P3 0 TxD P3 1 EA Vpp ALE PROG PSEN XTAL2 XTAL1 Vss ISP Configuration Vec 5V Voc 5V 1 Voc t5V 1 0 Vsgs 0V Sep 2004 Ver 1 01 69
54. rcuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function through UART uses four pins TxD RxD Vss and Vcc Only a small connector needs to be available to interface the application to an external circuit in order to use this feature Using In System Programming ISP The ISP feature allows a wide range of baud rates in the user application It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the 599 515 525 545 565 585 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initial ization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC HMS99C518S 52S 548S 568 58S will accept up to 16 10H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 0
55. re made a V Hmin for a logic 1 and Vii max for a logic 0 0 45V Figure 9 AC Testing Input Output Waveforms Vi oap 0 1 VoH 0 1 e 0 2Vcc 0 1 VLOAD Timing Reference Points Vioap 0 1 Vo 0 1 For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded Vor VoL level occurs lot lon gt 20mA Figure 10 Float Waveforms 0 2 Vcc 0 1 0 45V Figure 11 External Clock Cycle 38 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups OSCILLATOR CIRCUIT CRYSTAL OSCILLATOR MODE DRIVING FROM EXTERNAL SOURCE XTAL2 XTAL2 P LCC 44 Pin 20 P LCC 44 Pin 20 P DIP 40 Pin 18 P DIP 40 Pin 18 M QFP 44 Pin 14 M QFP 44 Pin 14 External Oscillator XTAL1 Signal XTAL1 P LCC 44 Pin 21 P LCC 44 Pin 21 P DIP 40 Pin 19 P DIP 40 Pin 19 M QFP 44 Pin 15 M QFP 44 Pin 15 C1 C2 30pF 10pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 12 Recommended Oscillator Circuits Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user should consult the crystal manufacturer for ap propriate values of external components Sep 2004 Ver 1 01 39 a Mannath p 599 515 525 545 565 585 Pl
56. ress xxxx Sep 2004 Ver 1 01 63 Mannath p 599 515 525 545 565 585 3 3 Display Data a Description Host Bootloader Display Command Send Display Command Pee See Wait Display Command OR Wait Checksum Error BA amp CR 8 LF Command Aborted OR Wait security error Le amp CR amp LF Command Aborted ra Y n Address s Reading value Wait Display Data ri PECRELE l Send Display Data All duci Command Finished Display Flow Note The maximum size of display block is equal to the Flash ROM size b Example HOST 05 0000 04 0000 0020 00 D7 BOOTLOADER 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000 data CR LF 16 data BOOTLOADER 0010 data CR LF 16 data BOOTLOADER 0020 data CR LF 1 data Display data from address 00004 to 00204 64 Sep 2004 Ver 1 01 599 515 525 545 565 585 3 4 Read Function This flow is similar for the following frames Reading Frame EOF Frame MagnaChip Frame only reading MagnaChip Frame a Description Host Send Read Command Kl Wait Checksum Error Command Aborted GH Read Command XK amp CR amp LF raf Wait security error L amp CR amp LF Com
57. s any cyclic ratio to be accepted on XTAL I input In X2 mode as this divider is bypassed the signals on XTAL1 must have a cyclic ratio between 40 to 60 Figure 2 shows the clock generation block diagram X2 bit is validated on XTAL 1 2 rising edge to avoid glitches when switching from X2 to STD mode Figure 3 shows the mode switching waveforms XTAL1 fosc 2 0 State Machine 6 clock cycles CPU control 1 X2 CKCON Register Figure 2 Clock Generation Diagram The X2 bit in the CKCON register allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa At reset the standard speed is activated STD mode Setting this bit activates the X2 feature X2 mode CAUTION In order to prevent any incorrect operation while operating in X2 mode user must be aware that all peripherals using clock frequency as time reference UART timers will have their time reference divided by two For ex ample a free running timer generating an interrupt every 30 ms will then generate an interrupt every 15 ms UART with 2400 baud rate will have 4800 baud rate Sep 2004 Ver 1 01 19 TW Mannath p 599 515 525 545 565 585 CPU Clock 3 Mu x ae STD Mode gt lt X2 Mode gt STD Mode Figure 3 Mode Switching Waveforms 20 Sep 2004 Ver 1 01 599 515 525 545 565 585 TIMER COUNTER 0 AND 1 Timer Counter 0 and 1 can be used
58. stem Programming using Standard Vcc Power Supply Boot ROM Contains Low Level FLASH Programming Routines and a Default Serial Loader 4K 8K 16K 24K 32K bytes FLASH user program memory Byte Write and Block 2K 8K Bytes Erase 2K bytes FLASH boot loader 1 byte Hardware Security Byte HSB 256 bytes RAM 64K bytes external program memory space e e 64K bytes external data memory space Four 8 bit ports Three 16 bit Timers Counters Timer2 with up down counter feature UART One clock output port e Programmable ALE pin enable disable Low EMI e Six interrupt sources two priority levels Power saving Idle and power down mode P DIP 40 P LCC 44 P MQFP 44 package Temperature Ranges 40 C 85 C e Description The Flash memory increases EPROM and ROM functionality with in circuit electrical erasure and program ming It contains 4K 8K 16K 24K or 32K bytes of program memory This memory is both parallel and serial In System Programmable ISP The ISP allows devices to alter their own program memory in the actual end product under software control through UART ports A default serial loader bootloader program supports ISP of the Flash memory The programming does not require external 12V programming voltage The necessary high programming voltage is generated on chip using the standard Vcc pins of the microcontroller 2 Sep 2004 Ver 1 01 599 515 525 545 565 585 Block Diagram MagnaChip T2
59. y HMS99C51S 52S has only sectors of 2K byte unit block and HMS99C54S 56S 58S has 4 sectors of 2K byte unit block and other sectors of SK byte unit block It contains the user s application code Hardware Security Byte The Hardware Security Byte space is a part of HSB and has a size of 1 byte 44 Sep 2004 Ver 1 01 599 515 525 545 565 585 Maonat bups Cross Flash Memory Access Description The and FM1 memory can be programmed by parallel programming The memory can be programmed from FM1 But programming FM1 from or from external memory is impossible 1 memory can be programmed only by parallel programming Action FM0 FM1 User Flash Boot Flash 2 Read oK gt FMO Write Erase o E Read OK OK 2 FM1 8 Write Erase OK Table 11 Cross Flash Memory Access Overview of FM0 Operations The CPU interfaces to the Flash memory through the FCON register of SFR FCON register is used to Select Register for operation of Flash Access FRSEL 2 0 Erase Mode Select ERASESEL Enable Boot Flash ENBOOT 64K Bytes Internal Rom Access INTROM EN Program Mode Select PGMSEL Mapping of the Memory Space By default the user space is accessed by MOVC instruction for read only The other memory spaces user BOOT HSB are made accessible in the code segment by programming bits INTROM EN ENBOOT in FCON register in advance A MOVC instruction is then used
60. y program MagnaChip ISP a software utility to implement ISP programming with a PC is available from the MagnaChip web site The users of this ISP function should use this MagnaChip ISP software for proper flash ROM control and operation Sep 2004 Ver 1 01 55 Mannath p 599 515 525 545 565 585 COMMAND DATA FUNCTION 00 Program Data Record nnaaaa00dd ddcc Where nn number of bytes hex in record aaaa memory address of first byte in record dd dd databytes cc checksum Example 05008000AF5F67F060B6 01 End of File EOF no operation xXXXXXx016cc Where xxxxxx required field but value is a don t care cc checksum Example 00000001FF 02 Specify Erase Write Pulse 03xxxx02wweellcc Where xxxx required field but value is a don t care ww write pulse ee erase pulse high byte l erase pulse low byte cc checksum Example 03000002789C40A7 03 Miscellaneous Write Functions nnxxxxO3ffssddcc Where nn number of bytes hex in record xxxx required field but value is a don t care 03 Write Function ff subfunction code ss selection code dd data input as needed cc checksum Subfunction Code 01 Erase Block ff 01 ss block index in bits 6 0 block number is designated by bit position Example 020000030122D8 erase block 1 and 5 position of bit 1 and 5 Subfu
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