MSC8144AMC-S Advanced Mezzanine Card User Manual
Contents
1. Figure 5 4 TDM Routing The TDM routing to the AMC connector is configured as 32 TDM lines 16 Tx and 16 Rx with frame sync and clock This is a proprietary connection to the extended options section of the AMC connector It is designed to match the interface on the Freescale Torridon2 ATCA carrier The TDM signals themselves are multiplexed with two x4 serial RapidIO streams at the backplane connector The selection between the serial RapidIO interface and TDM interface on this proprietary interface is made via Do Not Populate zero Q resistors Typically this populate no populate option is carried out during assembly The default is for the TDM option not to be populated see Figure 5 5 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 7 MSC8144AMC S Functional Description AN Connector Figure 5 5 Zero Ohm Resistor Selection for TDM or Serial RapidlO Interfaces Table 5 5 details the end to end TDM comnectivity on the AMC Card Table 5 5 TDM Connectivity on AMC Card and CPLD Mapping AMC Side DSP Side AMC AMC Connector Connector CPLD CPLD Pin Name Pin Number Pin CPLD Net Name Pin CPLD Net Name Number Number TX20 AMC_TDM_CLK_A DSP_TDM_TXCLK AG3 TDMOTCLK K K H M G M G M G E M K E DSP Pin Name F4 AFS TOMOTSYA TOMITCLK Kis i AMC_TDM_FSYNC_B DSP_TDM_RXSYNC AE5 TDMITSYN AMC_TDM_RX15 K16 DSP_TDM_RXD15 C4 TDM7RDT TX19 AMC_TDM_TX15 DSP_TDM_TXD15 C52. I2CMA O single byte peripheral address 1 multi byte peripheral address I2CSA 1 0 Pull Down DNP Internal pull up Optional pull down to activate on DIE scope Option Remove pull down for internal pull up I2CSEL 1 Pull Down DNP Pulled low Address 0bxxxxx00 Option Remove pull down for internal pull up Obxxxxxxx Pulled low Single bvte selected Remove pull down for internal resistor pull up option There are two switches available that control the Serial Port speed of the TSI 578 shown in Table 5 14 Table 5 14 Serial Port Speed Select SW3 1 SW3 2 SP IO SPEEDIO 1 Select TSI578 serial RapidlO clock speed ON ON 00 1 25 GHz 01 3 125 GHz 10 2 5 GHz 11 illegal ON OFF OFF ON OFF OFF 522 12 C Interface The TSI578 is connected to the MSC8144 FC bus via zero Q DNP resistors to allow direct programming from DSPI MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 19 MSC8144AMC S Functional Description 5 3 MSC8144 to Backplane Ethernet Connectivity The AMC board uses a Marvell 88E6185 Ethernet switch to connect the Ethernet connections to the backplane 5 3 1 Marvell 88E6185 Ethernet Switch The 88E6185 interfaces the backplane to the MSC8144 subsystem Two ports from the backplane are connected to the switch The switch then routes Ethernet traffic to the DSP Farm In addition the switch connects to an Ethernet debug port via the expansion connector 5
3. MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 23 MSC8144AMC S Functional Description Table 5 21 AMC Connector Site Pin Definitions Serial RapidlO Version continued AMC Definition Specific Signal Description EI AMC Definition Specific Signal Description sa IES IN as ese wo as eno N a ae is E ENABLE ENABLE_N RX15 AMC3_SrRIO_RXD_P3 Ce av a axis AMC3_SrRIO_RXD_N3 ca ep qs en AMC1_sRIO_TXD_PO TX14 AMC3_SrRIO_TXD_P2 AMC1_sRIO_TXD_NO TX14 AMC3_SrRIO_TXD_N2 II as O AMC1_sRIO_RXD_PO RX14 AMC3_SrRIO_RXD_P2 AMC1_sRIO_RXD_NO RX14 AMC3_SrRIO_RXD_N2 ca eo ECH Dj AMC1_sRIO_TXD_P1 TX13 AMC3_SrRIO_TXD_P1 AMC1_sRIO_TXD_N1 TX13 AMC3_SrRIO_TXD_N1 tr feno AMC1_sRIO_RXD_P1 RX13 AMC3_SrRIO_RXD_P1 ND N ND ND ND G el mp al eno EI eno O ee TX7 AMC1 sRIO TXD_N3 RX11 AMC2_SrRIO_RXD_N3 SCL_L AMC_SCL TX12 AMC3_SrRIO_TXD_PO 29 gt IT mae AMC3_SrRIO_TXD_NO 60 ee AMC1 sRIO TXD_N2 RX12 AMC3_SrRIO_RXD_NO AMC1_sRIO_RXD_P3 TX10 AMC2_SrRIO_TXD_P2 D 169 Di AMCI sRIO RXD N3 TX10 AMC2_SrRIO_TXD_N2 Ceti cit i E o AMC1_sRIO_TXD_P2 RX12 AMC3_SrRIO_RXD_PO AMC1_sRIO_RXD_N1 RX13 AMC3_SrRIO_RXD_N1 GND RAR AO AMO2 SIRIO AXD AN ms en ss oD o 95 SE TOLKAN 86 me AMO2 SIRIO Eu w mw em MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 24 F
4. 5 4 Freescale Semiconductor A MSC8144AMC S Functional Description 5 1 3 MSC81 44 Ethernet Interface The MSC8144 supports two UCC Gigabit Ethernet Controllers UECs coordinated through the QUICC Engine Controller On the MSC8144AMC S the MSC8144s are configured to use the RGMII interface This UEC interface selection is restricted to RGMII because of the requirements for x4 serial RapidIO signals which use the SGMII pins 5 1 3 1 Ethernet Connections Each MSC8144 connects its RGMII Ethernet port to the Marvell 88E1145 Ethernet transceiver which performs RGMII to SGMII conversion A 10 port Marvell 88E6185 SGMII Ethernet switch then switches between the MSC8144s and the 1000Base X Common Option Ports O and 1 at the AMC connector Additionally one port of the Ethernet switch 1s connected to a front plane Ethernet port through a Marvell 88E1111 Due to PCB space restrictions the RJ45 connector is located on the expansion connector RGMII 0 SERDE RGMII DSP3 E EM TE 1000 Base x Port 0 RGMII Gen DSP2 E ou gt Ek 1000 Base x Port 1 Plane RGMII SERDES DSP 1 MDIO_PHY t H MDC PHY A Front Panel V RGMII Interface GEI D E EI GEI _TXD 0 3 Palos Figure 5 3 Ethernet Hardware Block MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 5 MSC8144AMC S Functional Description The MSC8144 UECI interfaces to a Marvell 88E1145 Quad PHY device conn
5. TDM7RCK SCH sos RS TALK nm rem e i CEET m AMG_TOM Txi4___ Em DSP_TOM_TXDi4 DA TOM7TOT as Im Gi AMC TOM RX13 f Kis Ip msn AB4 TOMGRDT as Im le amo TOM TX Fie DSP TOM TXDI3 AB7 TOM6ROK mus 146 Fs AMO TOM_RX12_ Lia DSP_TOM_RxDI2 ACS TOMRSYN Roe Iw Iw k ma w Is _ ma Im o wa de E mr Im Iw ms Im Fr i mae Im k i es i a TOMGTOT ABS TOMSROT TOMSRCK AA3 JTDMSRSVN TOMSTDT TOMARDT TOMARCK TOMARSYN AAB ITDMATDT as 138 F2 _ AMC_TDM AX7 Mis DSP_TOM_RxD7 AD9 TOMSRDT 5 5 6 2 1 3 4 L2 FS 3 2 LI 2 2 FI 2 3 L4 F2 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 8 Freescale Semiconductor MSC8144AMC S Functional Description Table 5 5 TDM Connectivity on AMC Card and CPLD Mapping continued AMC Side DSP Side AMC AMC Connector Connector CPLD CPLD Pin Name Pin Number Pin CPLD Net Name Pin CPLD Net Name Number Number DSP Pin Name AEB_ TOMSRGK TOMBRSYN AD7 TOMSTOT TOM2ADT AGB JTDMEROK TOMERSYN mmer AF6_ TOMIROT TOMTROK AF7 TOMIASYN TOMTTOT AFA TOMOROT TOMORCK TOMORSYN AGG JTDMOTDT 5 1 5 MSC8144 UART Interface The individual DSP UARTs are multiplexed in the system CPLD with a single UART routed to the expansion connector as shown in Figure 5 6 Switch 4 is used to select which UART is routed through the CPLD The ICL3225 is configured to power down when there is no active signal by connecting the INVA
6. This indicates the board power is applied Check for completion of the reset sequence by verifying the following LEDs a Verify the DSP PORESET LD609 and PORESET LD612 LEDs illuminate and then turn off to indicate that the MSC8144 reset sequence is complete b The four MSC8144 RGMII Activity LEDs LD610 LD606 LD607 LD608 illuminate and then turn off Ethernet port activity LEDs LD614 LD615 indicate any Ethernet link to the backplane system dependent Pressing the front panel reset button SW1 power cycles the board and starts the reset sequence 10 Pressing the reset button SW2 resets the board and starts the reset sequence 11 Operate the CodeWarrior IDE software to verify that the board is installed properly MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor Chapter 3 Memory Map Each of the four MSC8144s has an identical memory map as described in Table 3 1 Table 3 1 MSC8144 Memory Map Address Range Memory Type Device Name Size E Empiyspaco syes Dono oF Empty space Gbyte 0xE8000000 OxFEDFFFF Empyspaco 366 tos 0xFEE40000 0xFEEFFFF AN Empty Space 768 Kbytes 0xFEF00000 0xFEF17FFF Boot ROM 96 Kbytes 0xFEF18000 0xFFFFFFFF Emptv Space 928 Kbvtes MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 3 1 Memory Map MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 3 2 Freescale Semiconductor Chapt
7. 3 2 Marvell 88E6185 Ethernet Switch Configuration Table 5 15 summarizes the port allocation and physical interconnect interface on the 88E6185 Table 5 15 Ethernet Switch Ports SGMII 88E1111 Eth PHY PHY RJ45 1000BASE X AMC Connector Port 0 GigE Control a Te 1000BASE X AMC Connector Port 1 GigE Control Table 5 16 88E6185 Switch Configuration Settings 88E6185 Signal PinSetting Description SW_MODEO Pull Down DNP Internal pull up gt SW MODE 1 0 11 EPROM Attached Mode SW_MODE1 Pull Down DNP SMI Address Oxi The default configuration of the 88E6185 does not support SGMII on ports 0 3 and 6 so programming of certain registers is required after reset The programming of these registers is done via the external EEPROM which 1s read after reset is released MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 20 Freescale Semiconductor MSC8144AMC S Functional Description 9 3 3 Marvell 88E1145 Quad PHY The 88E1145 is the interface between the MSC8144 RGMII and the SGMII Ethernet switch Each port operates in an identical manner performing RGMII to SGMII conversion Port configuration is via configuration pins and a serial management interface 5 3 4 Marvell 88E1145 Configuration The PHY is reset from the Reset CPLD during power up via the CPLD signal QPHY_RESET_N Each of the four ports has an interrupt that is fed back to the MSC8144 via the system logic CPLD The polarity of this interrupt is programma
8. 3 V The output voltage of the YM12S05 is set using the following equation 20 5 Rtr1 AAA zii tim Vout 0 7525 A 22 45 KQ trim resistor gives the required 1 25 V This is provided via two 40 2 KQ resistors in parallel for enhanced stability Two Maxim MAX8869 1 A DC to DC converters are used to generate the Ethernet Switch 1 5 V and 1 2 V voltages ESW_1V5 and ESW 1V2 A third MAX8869 is used to generate the M3 2 5 voltage The output voltage of the MAX8869 is set using the following equation R1 a RI Vout 0 8 e Where Rout connects the SET pin to Vout and R2 connects the SET pin to ground For 1 5 V RI 10 KQ and R2 11 3 KQ For 1 2 V R1 10 KQ and R2 20 KQ For 2 5 V R1 10 KQ and R2 4 7 KQ MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 31 MSC8144AMC S Functional Description The 1 8 V DDR voltage is supplied by a4 A Maxim MAX8556 DC to DC converter The output voltage is set using the following equation Vout ii 1 R2 R3 105 Where R2 connects the FB pin to Vout and R3 connects the FB pin to ground For 1 8 V R2 2 6 KQ and R3 1 KQ All the DC to DC converters are controlled by the Reset CPLD The CPLD controls the ENABLE signals to bring the power up in a controlled manner as required by the various device specifications In turn the POWER GOOD signals are fed back from the various devices to the Reset CPLD to enable it to manage the power
9. AMC 2 Ethernet AMC Link Type Extension 00h Link grouping ID 00h Independent AMC Asymmetric Match 00b Match Exact MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 40 Freescale Semiconductor MSC8144AMC S Functional Description Table 5 31 FRU Point to Point Connectivity Record continued Description AMC Link Descriptor 2 AMC Link Descriptor Breakdown below Link Designator AMC Channel ID 1 AMC Link Designator Lane 0 1 2 3 Bit Flag included AMC Link Type Link Type AMC 4 SRIO AMC Link Type Extension Link grouping ID Independent AMC Asymmetric Match Match Exact AMC Link Descriptor 3 AMC Link Descriptor Breakdown below Link Designator AMC Channel ID 3 AMC Link Designator Lane 0 1 2 3 Bit Flag included AMC Link Type Link Type AMC 4 SRIO AMC Link Type Extension Link grouping ID Independent AMC Asymmetric Match Match Exact Table 5 32 FRU Module Current Requirements om me me ese i Fred Last Record Record lengih fLemgih 6bjiss Fixed Record Format version 00 a Kieli MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 41 MSC8144AMC S Functional Description 5 8 Boundary SCAN Testing The card is designed to enable high percentage boundary scan test coverage Two JTAG interfaces are used for boundary scan testing as follows e The DSP JTAG header HD2 provides boundary scan coverage for the MSC8144s e The reset CPLD routes
10. Bytes MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 38 Freescale Semiconductor MSC8144AMC S Functional Description Table 5 29 FRU Board Information Area continued Board Manufacturer bytes 46726565 Freescale 736361 6c 65 Board Product Name type length byte 8 bit ASCII Length 12 Bytes Board Product Name bytes 4D504338 MPC8144AMC S 31343441 4D432D53 Board Serial Number type length byte 8 bit ASCII Length 5 Bytes Board Serial Number bytes 30303030 00000 30 9 Board Part Number Bytes 3730302D 32323534 39 MW IMMA a 30303030 34382D30 3031 required fields ini 1 5 00 any remaining unused space 00 00 00 Board area checksum Table 5 30 FRU Product Information Area om mm me een Product Area lenghi Lagp pne OO 1 Manufacturer Name tvpe length 9 8 bit ASCII Length 9 Bytes byte Manufacturer Name bytes 467265657363616065 Product Name type length byte 8 bit ASCII Length 12 Bytes M Product Name bytes 4D504338313434414D432D53 MPC8144AMC S MPC8144AMC S 1 1 1 1 N 1 1 Product Part Model Number CC 8 bit ASCII Length 12 Bytes type length byte Product Part Model Bytes 4D504338313434414D432D53 MPC8144AMC S 1 Product Version type length byte CD 8 bit ASCII Length 12 Bytes ASCII 12 bytes Product Version Bytes 5265762042202850696C6F 7429 Rev B Pilot 1 Product Serial Number C6 8 bit ASCII Length 6 Bytes type length bytes Product Serial Number 3132
11. Configures the order of 4x Nite Up DNP Internal Pull down selects 0 A B C D receive lanes on serial ports Optional pull up resistor for setting 1 0 2 4 6 14 D C B A ordering MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 18 Freescale Semiconductor MSC8144AMC S Functional Description Table 5 13 TSI578 Configuration continued set tation Pom See SP_TX_SWP Configures the order of 4x transmit lanes on serial ports 0 2 4 6 14 SP_IO_SPEEDI O 1 Serial Port Tx RX operating frequency 00 1 25Gbit s 01 3 125Gbit s default 10 2 5Gbit s 11 illegal Power down the port 0 Powered Up 1 Powered Down Power down the port 0 Powered Up 1 Powered Down SP 1 3 5 7 9 11 13 15 PWRDN SP 2 4 6 8 10 12 14 PWRDN Pull Up DNP Internal Pull down selects 0 A B C D Optional pull up resistor for setting 1 D C B A ordering Connectedto switch Switch controlled and system CPLD Not connected internal pull up Port powered down Pulled low Port powered up SP 0 2 4 6 8 10 12 14 0 x4 mode Pull up DNP Internal Pull down for x4 Optional pull up MODE SEL 1 x1 mode resistor available for up for x1 mode MCES Multicast Event symbol Connected to test Debug use output point BCE Boundary Scan Compatibility Enable IZCSEL 0 12CSA 1 0 bits ignore lower bits of EPROM address default to 00 1 12CSA 1 0 bits used as lower bits of EPROM address LSB 2 bit so address
12. GHz Default 8 10 2 5 GHz GC 11 illegal RST MMC w SW3 3 2 B 0 Reset CPLD controlled Power Up default 1 ColdFire device controlled MMC SW4 4 Future use SW4 Configuration SW4 1 SW4 2 Select MSC8144 UART output 00 DSP1 default 01 DSP2 10 DSP3 UARTO gt 11 DSP4 UARTI N SW4 3 RCW SRC co 0 RCW Source from 12C pins Boot Port Serial RapidlO interface default T A 1 RCW Source from External pins Boot Port IEC DBG SW4 4 0 MSC8144 does not enter Debug Mode but operates normally default 1 MSC8144 enters Debug Mode after reset see MSC8144 Reference Manual for details Figure 4 2 DIP Switch Settings Table 4 1 MSC8144AMC S Clock Values Ref Clock SW4 3 ON SW4 3 OFF CLKIN 66 MHz 66 MHz Cores 800 MHz System Clock 400 MHz 400 MHz M QUICC Engine Serial RapidlO MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 4 2 Freescale Semiconductor Controls and Indicators 4 2 Jumpers There is one jumper on the board described in Table 4 2 that is used to configure the CPLD JTAG chain Table 4 2 Jumper Position Selects the Reset and System JTAG Chain e When in position 1 2 the Reset CPLD only is in the chain e When in position 2 3 both the Reset and System CPLDs are in the chain Note If the reset CPLD is blank then use position 1 2 to program the Reset CPLD 4 3 LEDs Table 4 3 describes the LED functions and Figure 4 1 shows the LED location on the MSC8144AMC
13. MSC8144 Debug Chained JTAG header for four MSC8 144s e Board Management Hot Swapping FRU Storage Status LEDs Temperature and voltage monitoring e Power Supply 12 V and 3 3 V IPMCV provided from AMC edge connector or terminal connector On board voltage requirements are generated via DC DC voltage regulators 3 3 V for I O 1 0 V for the MSC8144 cores and PLLs 2 5 V for M3 memory 1 25 V for MSC8144 M3 memories and the TSI578 core 1 8 V 0 9 V DDR2 1 2 V 1 5 V and 2 5 V for the Ethernet switches MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 1 3 General Information 1 3 2 External Connectors The MSC8144AMC S interconnects with external devices via the following set of connectors see Figure 1 1 and Figure 1 2 AMC connector for connecting to ATCA and uTCA backplanes P1 MSC8144 OnCE 14 pin Debug connector HD2 CPLD programming header 10 pin HD 1 Standalone power connector P2 Expansion connector J1 giving access to the following MSC8144 UART Front panel Ethernet RJ45 Ethernet Switch EEPROM programming header ColdFire MMC BDM ColdFire MMC UART External FC EEPROM programming header P1 AMC Connector E te RL E P2 External Power HD1 CPLD Programming 7 Header remove Front panel for access HD2 MSC8144 JTAG Header Figure 1 1 MSC8144AMC S Board External Connections MSC8144AMC S Advanced Mezzanine Card User Ma
14. TDM connection consisting of 8x TX RX and common clock and sync on an AMC connector Each MSC8144 UART interface is multiplexed via the CPLD to a single RS 232 connector on the expansion connector FC Bus connecting MSC8144s for boot and configuration MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 1 2 Freescale Semiconductor General Information e Hardware Blocks Four MSC8144 DSPs four cores per device each with the following x4 serial RapidIO interface routed to a serial RapidIO switch RGMII interface routed to an Ethernet switch TDM routed to a CPLD for multiplexing to the backplane FC interface for boot 256 Mbytes of 32 bit DDR2 memory Tundra TSI578 serial RapidIO switch 4 lanes of x4 serial RapidIO lines from the MSC8144 farm 2 lanes of x4 serial RapidIO lines to ports 4 7 and 8 11 of the backplane 2 lanes of x4 serial RapidIO lines to ports 12 15 and 17 20 of the backplane Controlled via I C or master MSC8144 Ethernet switch 4lanes of RGMII from the MSC8144 farm 2lanes of 1000Base X to ports 0 and 1 of the backplane 1 lane of SGMII to the front panel expansion connector TDM MSC8144 TDM routed to backplanes ports 12 15 and 17 20 multiplexed with the serial RapidIO lines UART MSC8144 UARTs multiplexed to the expansion connector e Boot Boot mode defined by switch Serial RapidIO interface via the backplane From the on board DC e
15. slave EEPROM using the address b1010111 The slaves DSPs DSP2 3 4 then access DSPI to read their RCW The EPROM is clocked at 66 MHz so the CNG_CLKIN_RNG is set to 0 via the System Logic CPLD for a CLKIN range of 0 66 MHz The DC EPROM can be programmed via DSPI the expansion header or the system CPLD Table 5 8 and Table 5 9 list the FC layout as programmed in the EPROM NOTE The RCW can be changed depending on the user requirements The values below represent the default values programmed in the PC Table 5 8 RCWLR Load from I C Pan awo fm oes OOS ss O o es Reseed _ Rapid Rapid IO Vpp Select 1 0V n Rapid IO Vpp Select 1 0V n Select 1 0V El NL H I M Erre G RapidlO clock is 3 125 GHz is RIE Powers enabled on Dad O O O OO o e ila Select 4x Rapidio configuration a Sim Disable Sem Co e f some IT Depu O O O O ooo y D RES 000 reserved 0 Bleif SSS SyS AS o Ree y Coo e T om o o Eeoa CP LH Enable Core Pt SCSC SCSCS Co 6e sm o Enable System PIL DSP1 RCWLR 0x0078180A DSP2 RCWLR 0x0078180A DSP3 RCWLR 0x0078180A DSP4 RCWLR 0x0078180A MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 12 Freescale Semiconductor MSC8144AMC S Functional Description Table 5 9 RCWHR Load from EC 1 Reset Initiator 0 Reset Target EWDT 0 Disable watch Dog Timer 001001 Boot Port serial RapidlO interface no IEC 1 RIO access to internal memory enab
16. switch is point to point connected to the MSC8144 device through a serial RapidIO link The MSC8144 routes the serial RapidIO interface to the backplane via the Tundra TSI578 serial RapidIO switch as shown in Figure 5 2 The interface can work in x1 or x4 mode and is selectable The signals are detailed in Table 5 2 I2C i Port 4 7 x4 156 25MHz Port 8 11 Oscillator x4 y 8 11 TSI578 Port 12 15 MSC8144 Port 17 20 AMC MSC8144 156 25MHz CONNECTOR Figure 5 2 Serial RapidlO Connectivity Table 5 2 MSC8144 Serial RapidlO x4 Signals A ae Description SRIO TXD PIO 3 Transmit ve differential signal SRIO TXD NJO 3 Transmit ve differential signal SRIO_AXD_PIOS en ma DSP SD REFOLK P Ger SD REFOLK N Both the MSC8144 and TSI578 run with a fixed clock frequency of 156 25 MHz The transmission frequency of the MSC8144 serial RapidIO interface is dependent on the Reset Configuration Word SCLK bits The various options are described below in Table 5 3 The default setting is to run at 3 125 GHz using the 156 25 MHz clock One restriction when booting from external pins is that the clock must be 100 MHz for 1 25 GHz Table 5 3 MSC8144 RapidlO Settings 1 25 GHz 100 MHz 001 RCW from external Signals RCW_SRC 011 2 5 GHz 156 25 MHz RCW from IEC RCW_SRC 001 1 25 GHz 156 25 MHz RCW from I C RCW_SRC 001 3 125 GHz 156 25 MHz 111 Default RCW from IEC RCW_SRC 001 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1
17. 0 MHz depending on the RCW source The default setting 1s to run the core at 1 GHz using clock mode 10 Figure 5 10 described the internal clocking in the MSC8144 NOTE PCI_CLKIN is not used so all internal frequencies are derived from CLKIN Cock 0 400hiH2 CLASS Clock Dock EDOMHzJ CLASS Clock B Clock 20041H2 CLEOUT Source PED ELK e Clock 400hMH2 QUICC Engine Clock 1 Clock 4 SERIO PCI Source Gli Hz ES 55 c Clock 5 1GHz Extended Core D Clock amp 1 GHz Extended Core 1 Clock 7 16 He Extended Core 2 1259112 Zero Delay buffer Clock 8 IGHzj Extended Core 3 Clock 9 125MH2 CLEOUT Source 1 PLL1 gt Clock 10 BE MH ELKOUT Source Clock 11 400hH2 OOR Clock Clock 12 ODMHEJ Mi Clock Sourne O 4 PLLA Figure 5 10 MSC8144 Clocking MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 16 Freescale Semiconductor MSC8144AMC S Functional Description 5 1 8 GPIO IRQ Distribution Each DSP on the MSC8144AMC S connects several multiplexed pins to the system logic CPLD The pins chosen can be configured as Timers Interrupts or GPIO This enables the MSC8144s to generate interrupts to each other and receive a timer input from the system logic In addition each DSP routes its dedicated INT_OUT pin to the system logic CPLD providing lower overhead interrupt generation Table 5 12 and Figure 5 11 illustrate the implementatio
18. 144 has 256 Mbytes of associated 32 bit wide DDR2 High throughput serial RapidIO links connect the four MSC8144s to each other and to the data backplane The serial RapidIO interfaces can run in x1 or x4 mode and are interconnected via a TSI578 serial RapidIO switch For the control plane each MSC8144 RGMII Gigabyte Ethernet port is linked to the backplane ports via an Ethernet switch The 32 TDM lines 16 Rx and 16 Tx are routed to the backplane from each MSC8 144 All TDM Modules with two links per module are connected together over a common bus to achieve the 32 TDM line requirements This TDM linkage to the backplane is optional and can be isolated when not required For bootstrap purposes a common serial FC bus and EEPROMs are connected between the MSC8144s The EEPROM is programmed through a master MSC8144 or an in circuit programmer attached to a header AMC board management is handled via a CorEdge enabled Module Management Controller based around a Freescale MCF5213 The provides the board with power sequencing hot swap functionality temperature sensing and FRU record storage Due to space restrictions on the PCB a number of debug and programming headers are offloaded to an expansion card via the front panel MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 1 1 General Information 1 2 Working Configurations There are two configurations for use of the MSC8144AMC S board system development e
19. 33343536 123456 012345 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 39 MSC8144AMC S Functional Description Table 5 30 FRU Product Information Area continued om mm me een ma ies TE o R_ FRUTleIDbyes 1 mn Custom product into area fes 1 C1htype length byte encoded for no CI no more fields more fields v 00h any unused fields Pad th 00 Product Info Area Checksum Table 5 31 FRU Point to Point Connectivity Record em ed me tion tf Recordiength fej tf Record Cheeksum II a Heedercheeksum O r S C a Record Format version 00 o a OoOO 1 OEM GUID Count 1 OEM GUID 1 1 record defined record defined 16 OEM GUID List 30303030 0000000000000000 30303030 30303030 30303030 Resordiyge o eS 3 AMC Channel Descripior0 FFFFEOh Lane 0 Port Number A Lanest 2 3 not used ____ s AMG Channel Descripiort _FFFFEth Lane 0 Port Number 1 Lanest 2 3 not used ___ AMC Link Descriptor 0 FC00005100 AMC Link Descriptor Breakdown below Link Designator 00h AMC Channel ID 0 AMC Link Designator 1h Lane 0 Bit Flag included AMC Link Type 05h Link Type AMC 2 Ethernet AMC Link Type Extension 00h Link grouping ID 00h Independent AMC Asymmetric Match 00b Match Exact AMC Link Descriptor 1 FC00005101 AMC Link Descriptor Breakdown below Link Designator 01h AMC Channel ID 1 AMC Link Designator 1h Lane 0 Bit Flag included AMC Link Type 05h Link Type
20. I2C 5 12 Loading Reset Configuration Word from External Sgenals ss eeeennzzzzz 5 14 MSCS IAA ee e EE 5 16 GPIO IRQ Distribution rt rr nn rna nngrannzztnzzzzzznzzntznzzzzat 5 17 SPEE ios 5 18 MSC8144 to Backplane Serial RapidIO Connectivity eeeennnnnznnenenznnnnnnnnzzzn 5 18 Tundra TSI578 Serial RapidlO Switch 5 18 Lenci 5 19 MSC8144 to Backplane Ethernet Connectivity an 5 20 Marvell 88E6135 EthiernetSwitchi ia 5 20 Marvell 88E6185 Ethernet Switch Configuration 5 20 Marvel seb kid WAG PEHY d a A 5 21 Mary ell 33E 1145 ee NEE 5 21 Marvell 88E1111 Ethernet PHY Configuration eeennnnzznnenennnnnnnzzzznnnnnna 522 Backplate Concord td dida 5 23 General Board Con Ur MOM 5 26 Reset Operation and Connect VI serisine 5 26 Ir E 5 27 System CPD dada 5 28 POWELL SUDD i e l N 5 29 POWEL EE 5 29 ETH 5 30 Module Management Controller MMC nn zz nn nt 5 32 euer edd 5 33 KL RE EE 5 34 Module Inserta 5 34 FEoapina thie TT 5 34 A a A 5 35 HOLS Wap WC EE 5 35 Module Management Communications Bus IPMB L occccccnnnnnnncncnnnnncnnnnnnnonos 5 36 Geographical Address GALO Dani ara 5 36 Module temperature SENSORS eiii 5 36 Module Voltage SCS OLS ut iia 5 36 MME UAR dci 5 36 BDM Depu Header sa o B E S 5 36 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor Contents Paragraph Num
21. It supports the following e Positioning of the DOS output during writes to DDR memory e Sampling of input data from DDR memory e Synchronize the incoming DDR data to the Internal Clock e Control the relationship between output data and CLK_OUT 5 1 1 2 Terminations and UO Voltage The DDR2 interface operates with 1 8 V I O voltages Reference voltages of 0 9 V are synthesized from the 1 8 V via filtered 2 1 voltage dividers 2x1 Kbyte resistors with low impedance to the 1 8 V supply The references are applied to each DDR2 device at VREF pin and the MSC8144 at pin MVREF Because the device fan out is low FO 2 Data 2 Address 2 Control and the clock frequency is relatively low for DDR2 200 MHz the MSC8144 and DDR2 devices can be programmed for reduced power using a series termination scheme In addition to the benefits of the power heat series termination allows the removal of a 0 9 V regulator from the design MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 3 MSC8144AMC S Functional Description 5 1 2 MSC8144 Serial RapidlO Interface The RapidIO controller supports a high performance point to point low pin count packet switched level interconnect that can be used in a variety of applications as an open standard The MSC8144 serial RapidIO subsystem complies with the RapidIO Interconnect Specification Revision 1 2 which connects directly to a serial RapidIO switch Each port in the
22. KKKKk Port Card Management SW KKKKKKKKKKKKE Nov 9 2007 15335237 40 000048 000 Disable dc Power Read Temperatures Write DS2431P Read Card Status Turn OFF WD Toggle Red led Enable dc Power Read Voltages Read DS2431P Write DS2431P Test Disable WD Pulse Reset Turn ON WD Toggle Blue led I OF AA a A OWN WH vo Figure 5 19 FRU State Transition Diagram 5 7 3 3 FRU records The MMC contains FRU information that describes the board capabilities e keying and power and inventory data The records are described in Table 5 28 through Table 5 32 Table 5 28 FRU Common Header Common Header Format Version fixed value fixed value 111100 Internal Use Area Starting Offset Internal Use Area not present Multiple of 8 bytes 00 not present Chassis Use Area starting Offset Chassis Use Area not present Multiple of 8 bytes 00 not present Multi record Area present offset 128 bytes I Muli o ores o not presen O A TA Multiple of 8 bytes 00 not present Multiple of 8 bytes 00 not present PAD fixed to 00 CommonneaderCheksm J PI 1 Board Area starting Offset 01 Board Area present offset 8 bytes Multiple of 8 bytes 00 not present Table 5 29 FRU Board Information Area Board Area Format version Board Area length 08 Length 56 Bytes Language Code English 3 Mfg Date Time 40D562 Number of mins from 1 1 96 little endian Board Manufacturer type length 8 bit ASCII Length 9
23. LID signal to the FORCE_ON signal The INVALID signal goes low when no RS232 levels are detected on any transceiver input System CPLD DSP1_UART_TXD sE Expansion Connector CF_UART_TXD UART TXD1 MCF5212 CF_UART_RXD UART RXD1 DSP2 UART TXD ICL3225E DSP2 UART RXD UART_TXD2 UART_RXD2 DSP_UART_TXD DSP_UART_RXD DSP3_UART_TXD DSP3_UART_RXD UART selectable via DSP4 UART TXD Switch 4 DSP4_UART_RXD Figure 5 6 UART Connectivity MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 9 MSC8144AMC S Functional Description 5 1 6 MSC8144 JTAG Interface The MSC8144 OCE module allows non intrusive interaction with the SC3400 core enabling examination analysis of registers memory and on chip peripherals The OCE module connects with the debugging system through on chip JTAG TAP controller pins as shown in Figure 5 7 The MSC8144 OCE JTAG debug ports are connected in a chain configuration to allow simultaneous debug of the complete DSP Array The signals available on the JTAG connector are as follows e TMS This signal is pulled up so that after reset 5 TCK clocks put the TAP into the Test Logic Reset State e TSRI The Reset signal is pulled low to force the JTAG into reset by default e TCK tThe clock signal is pulled low to save power in low power stop mode e TDI The input signal is pulled high to save power in low power stop mode All JTAG ports hav
24. MHz input frequency To use this data rate the user must change the clock Y602 to 100 MHz Table 5 10 RCWLR Load from External Pins emie e e A e Cs s ELE ELE 24 VCI In SerDes VCO Current reference Ca w o RIO VDD is 1 V 22 20 SCLK RIO SGMII reference clock is 100 MHz SerDes is 1 25 GBaud RIOE RC 16 E 1 Serial RapidlO signals enabled on SerDes RC 16 Serial RapidlO x4 Protocol SGMII1 RC 16 Disable Disable SGMII 1 on SerDes i 1 on SerDes i Lem mees Jemen _ ren lm mm Iess fs 7 See GltelPiLie JG O Lc TE ee Ere ob PEN feo Eesti ee ue sie Table 5 11 RCWHR Load from External Pins Description No reset Slaves to be configured MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 14 Freescale Semiconductor MSC8144AMC S Functional Description Table 5 11 RCWHR Load from External Pins EWDT 9 Watchdog Timer disable iii emie e Boot Port 001000 IEC SPATII 6 sn Ro Seal Rapa Host Access is enabled RSC ees Resend es Reed RO SEDES CTLS Common Transport type is a Large System RCWHR 0x046C0401 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 15 MSC8144AMC S Functional Description 5 1 7 3 MSC8144 Clocking The MSC8144AMC S implements a point to point clocking scheme for the MSC8 144s The CLKIN is a 66 MHz clock distributed through a Zero Delay Buffer The MSC8144 runs at frequencies of 1 GHz or 80
25. MSC8144AMC S Advanced Mezzanine Card User Manual MSC8144AMCSUM Rev 1 06 2008 ZC freescale semiconductor How to Reach Us Home Page www freescale com Web Support http www freescale com support USA Europe or Locations Not Listed Freescale Semiconductor Inc Technical Information Center EL516 2100 East Elliot Road Tempe Arizona 85284 1 800 521 6274 or 1 480 768 2130 www freescale com support Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French www freescale com support Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor China Ltd Exchange Building 23F No 118 Jianguo Road Chaoyang District Beijing 100022 China 86 010 5879 8000 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 1 303 675 2140 Fax 1 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MSC8144AMCSUM Rev 1 06 2008 Information in this document is provided solely to enable system and software im
26. S Processor Board Table 4 3 LED Descriptions CNC mn mam D Y E D E Y E Y v vi vi LD60 SP2 RGMII Activity thernet activity No Ethernet activity MMC Red LED Status Red Fault condition Normal operation Critical Indicator MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 4 3 Controls and Indicators 4 4 Push Buttons Figure 4 3 describes the MSC8144AMC S Processor Board push buttons SW1 Pressing button SW1 on the front panel recycles the board Power Cycle power Restarts the power sequencing on the board SW2 Pressing button SW2 on the back of the board causes a Hard Reset Power On Reset to all Components Figure 4 3 MSC8144AMC S Push button Switches MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 4 4 Freescale Semiconductor Chapter 5 MSC8144AMC S Functional Description This chapter describes the design details of the various MSC8144AMC S hardware blocks The hardware description has been partitioned into the following logical sections e MSC8144 Digital Signal Processing Block e MSC8144 to Backplane SRIO Connectivity e MSC8144 to Backplane Ethernet Connectivity e Board Control Power Reset Clock JTAG and others The MSC8144AMC S is designed to comply with the PICMG AMC 0 R2 0 specification with AMC A serial RapidIO interface fitting into a single width full height mezzanine card The card contains four MSC8144 devices with assoc
27. TE iren Y HEEE PHY_RESET QPHY_RESET SCL_L ESW_RESET SDA_L SW_RESET SRIO_RESET STSTEM_CPLD_RESET PS1 EPROM STORAGE PSO Expansion AMC connector Connector Figure 5 17 MMC Reset CPLD Implementation 5 7 2 MMC Operation Overview The following subsections give a general overview of MMC operation 5 7 2 1 Module Insertion Last mate pins PSO_N and PS1_N are used to indicate that the module is inserted The PS1_N is pulled high by the IPMC either by ATCA carrier or MicroTCA MCH The module when fully inserted pulls PS1_N to module ground via a diode PS1_N going low indicates the module presence to the IPMC The IPMC senses low signal on PSI and supplies Management Power MP The MP IPMCV is 3 3 V and cannot draw more than the AMC 0 specified 150 mA limit 5 7 2 2 Enabling the MMC Upon insertion the MMC powers up and is held in a reset state until the AMC_ENABLE_N signal is pulled low The carrier IPMC releases the module from this state by driving the AMC_ENABLE_N signal high This is routed through the Reset CPLD to the Coldfire via the signal CF_RESET_N MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 34 Freescale Semiconductor MSC8144AMC S Functional Description 5 7 2 3 Status LEDs Two LEDs for system status are mandated by the AMC 0 specification These are the Blue LED and Red LED The Red LED switches on to indicate a fault condition The IPMC drives the state of the Blue LED dur
28. ails on hardware preparation see the MSC8 44AMC S Hardware Getting Started Guide MSC8144AMCSHWGSO 2 1 Unpacking Instructions NOTE If the shipping carton is damaged upon receipt request that the carrier agent to be present during unpacking and inspection of equipment CAUTION Avoid touching areas of integrated circuitry static discharge can damage circuits e Unpack equipment from shipping carton e Refer to packing list and verify that all items are present e Save packing material for storing and reshipping of equipment MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 2 1 Hardware Preparation and Installation 2 2 Perform the following steps in the order listed to install the MSC8144AMC S Processor Board properly 2 2 1 9 Installation Instructions Verify that jumpers and switches are in their default positions See Chapter 4 Controls and Indicators for a list of default positions Connect external cables in accordance with your needs See Section 1 3 2 External Connections for more details Insert the board into the carrier chassis as per the specific chassis operating instructions Switch on the power to the chassis Check for completion of the reset sequence indicated by the LEDs see Figure 4 1 for locations A full description of the LEDs is given in Table 4 3 When powered up verify that the 12 V LD601 and 3 3 V LD602 LEDs illuminate and stay lit
29. ber Title 5 7 2 11 Persistent SOTE iaa Iko MME User Opera Oi Siti ele een La ae diodi Hot Swapping a Board In SEN Hot Swapping a Board Out De pow UART Terminal ads dida PRURITO sale 5 8 Boundary SCAN Teste ar ti dada Sa Ma ita go B aa 5 9 Thermal Requirements ansiosa Chapter 6 Revision History MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor Page Number Contents Paragraph Page Number Title Number MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 vi Freescale Semiconductor Chapter 1 General Information 1 1 Introduction This document describes the MSC8144AMC S AdvancedMC AMC Card The MSC8144AMC S provides an AMC debugging environment for engineers developing applications for the MSC8144 series of Freescale Processors The MSC8144 is a highly integrated DSP processor that contains four StarCore SC3400 DSP subsystems 512 Kbytes of M2 shared memory 10 Mbytes of M3 shared memory L1 instruction and data caches 128 Kbytes of shared L2 instruction cache a DDR memory controller a serial RapidIO interface two 10 100 1000Base T Ethernet Controllers an ATM Controller Supporting various ATM adaptation layers eight 512 channel time division multiplexing TDM interfaces a 16 channel DMA Controller 32 bit PCI interfaces UART interface and an IC interface The MSC8144AMC S single width AMC board is designed around four Freescale MSC8144s Each MSC8
30. ble The 88E1145 register block can be programmed via the management interface with each port connected to its associated MSC8144 MDIO MDC interface The configuration of Ports 0 3 of the 88E1145 PHY is detailed in Table 5 17 Table 5 17 Ethernet Port Configuration Port 0 Config DSP1 Bit Description MEN RC SE 0001 ME e SS ooo CONFIGO 0011 Address 0x3 CONFIG 1 0110 RGMII to SGMII Conversion RGMII to SGMII Conversion 222 Global Configuration Description MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 21 MSC8144AMC S Functional Description 5 3 5 Marvell 88E1111 Ethernet PHY Configuration The Marvell 88E1111 Gigabit PHY is used to terminate the Gigabyte Ethernet frontplane traffic via the expansion connector The PHY is configured at Reset via its CONFIG 6 0 pins These pins are tied to ground Vcc or one of the LED pins to give the bit settings described in Table 5 18 Table 5 18 88E1111 Pin to Constant Encoding LED_LINK100 LED_LINK1000 LED TX ON EE y The PHY on the MSC8144AMC S is configured as shown in Table 5 19 and Table 5 20 Table 5 19 88E1111 PHY Configuration Settings Hardware Connection TOONFIGT ENA PAUSE PHYADRI4 Lann Im e Table 5 20 88E1111 PHY Configuration Description Configuration Description PHYADR 4 0 0x00110 PHY is on Ethernet Switch Port 6 0x00110 ENA PAUSE Default register 4 11 10 to 00 copper AME TA 1100 Aut
31. cale Semiconductor MSC8144AMC S Functional Description 5 6 Power Supply There are two separate power rails inputs to the card as follows e 3 3 V Management Power IPMCV used to power MMC circuitry e 12 V Payload Power used to power the rest of the board All of the required voltages for the card are generated locally on board from the 12 V supply using DC DC converters 5 6 1 Power Requirements The MSC8144AMC S has a number of on board peripheral chips each with its own voltage and power requirements Table 5 27 highlights the main peripheral chips used on the MSC8144AMC S and their individual voltage power requirements Table 5 27 Estimated Board Power Requirements Comments asse Aw eum ess eem SW se WI woen O WA ween LA oo ESC ny sovo AB LS LT A A C5912 There are a number of devices that have voltage rail ramp up dependencies described as follows e The Ethernet switch can power up in two ways as follows All voltages at the same time Highest to lowest 3 3 V 2 5 V 1 5 V 1 2 V e The TSI should be powers up with 1 2 V first followed by 3 3 V s The MSC8144 powers up with 1 0 V first followed by 3 3 V MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 2 MSC8144AMC S Functional Description 5 6 2 Power Supply Operation To accommodate all the various power up requirements use the power scheme shown in Figure 5 15 with all timing contr
32. e a weak internal TDI pull up s TDO The output signal is pulled high e HRESET This signal is pulled high and also connects to the Reset CPLD The JTAG control signals are buffered into two sets of signals each supplying two MSC8144s This reduces device and cable loading of the signals The JTAG TRST signal is buffered via an open drain buffer with individual signals being fed to the DSPs TO T TO TOO To T TO To DSP 1 DSP 2 DSP 4 nc THE TER THET THE TEX TAHET H THE TEX TANT THE TEX THET 03P JTAG Header Figure 5 7 MSC8144 JTAG Connections For debugging there are a number of zero resistors in the JTAG chain to allow isolation of either of the MSC8144s not shown in Figure 5 7 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 10 Freescale Semiconductor MSC8144AMC S Functional Description 5 1 7 Reset Configuration The MSC8 144 has three external reset sources Power on Reset PORESET Hard Reset HRESET and Soft Reset SRESET The soft reset is not used in the system and 1s pulled high The reset control for all devices is described in Section 5 5 1 Reset Operation and Connectivity PORESET is the high level reset of the MSC8144 and when asserted drives all other resets within the DSP The rising edge of PORESET is used by the MSC8144 to latch external Reset Configuration Word RCW signals The Reset Configuration Words Source RCW_SRC 0 2 opt
33. ecting to each of the four ports Table 5 4 describes the signals Table 5 4 MSC8144 RGMII Signals Description GEI TX CLK 125 MHz clock source GE1_TX_ER Transmit clock GE1_TX_EN Transmit Control GE1_TXD 0 3 Transmit data GE1_RX_DV Receive Control GET PADI MDIO Management data 5 1 3 2 Ethernet Initialization Each DSP has a MDIO connection to the 88E1145 QPHY enabling each DSP to independently configure its own 88E1145 port DSPs 1 2 3 and 4 have been given the SMI address 0 1 2 and 3 respectively DSP 1 configures the Ethernet switch which resides at address 0x10 The switch contains a PHY Polling Unit PPU which transfers link speed duplex and pause information from the 88E1111 to the switch For this feature to function the 88E1111 SMI address 0x6 matches the switch port that it is connected to Port 6 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 6 Freescale Semiconductor MSC8144AMC S Functional Description 5 1 4 MSC8144 TDM Interface Each MSC8144 TDM interface is routed to the AMC edge connector via a common open drain bus through a CPLD as shown in Figure 5 4 The TDM modules on the MSC8144s are configured in Common Frame and Sync mode AMC CONNECTOR DSP_TDM 7 0 TX AMC TDM RXI0 151 Es DSP_TDM 7 0 RX AMC_TDM_TX 0 15 psp tom Txcik _ System id DSP TDM TXSYNC_ ogic Du DSP_TDM_RXCLK 9 I psp Tom Rxsvnc CPLD DSP1 DSP1 MN Sal DSP1 mi E HH DSP1
34. ectofS sesessererererssesesserasesesesssrasssesosesosonraresesossnrasesesene 1 4 MSCSI44AMEG S Block EEN eege 1 5 Definitions Acronyms and Abbreviations ii 1 6 Related Documentation cccccccccsececcececsccececcececcececcececsececctascancscenseces 1 7 SPC CLECATIONS rro Chapter 2 Hardware Preparation and Installation 2 1 Unpackne TiS tru CH OM comia 900 Installation eer e da ie ciale Chapter 3 Memory Map Chapter 4 Controls and Indicators 4 1 DIP SWVC GS caido EE 4 2 TDO A dai 4 3 ED iti 4 4 FUS bi HEEL Chapter 5 MSC8144AMC S Functional Description 5 1 MSC8144 Digital Signal Processing BIOCK 5 1 1 NSCS 144 DDR Ee 5 1 1 1 DORSO 5 1 1 2 Terminations and I O Voltage i iZ MSC8144 Serial RapidlO Interface 5 1 3 MSC8144 Ethernet Interface MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor Page Number Paragraph Number Slo Dow 5 1 4 SLS 5 1 6 5 1 7 Jkl 5 1 7 2 SLE 5 1 8 5 129 5 2 ZZ 5 3 Hol HZ D929 5 3 4 dE 5 4 5 5 Sal o PI 5 9 2 5 6 1 5 6 2 af Ll Diaz Salza S122 SES 5 7 2 4 Dl 5 7 2 6 lol 5 7 2 8 De 12 0 5 7 2 10 Contents Page Title Number Ethernet ee Te CEET 5 5 Eemer Initiali a O iii e i G A N 5 6 MSE SAA TOM Itaca eda 5 7 MSC SIEUA R E MEAC yA 5 9 MSCS LAH JIAG TE AGE ii 5 10 Reset Conti ci 5 11 Loading Reset Configuration Word from External
35. en powers up the board via the CPLD Power Sequencer Details can be found in Section 5 5 2 System CPLD and Section 5 7 Module Management Controller MMC The CPLD Reset Sequencer is used to control the reset of all devices on the board To facilitate BSCAN testing of all the Ethernet and serial RapidIO components their JTAG signals have been routed to the CPLD for use by the BSCAN tester shown in Figure 5 20 A 66 MHz clock oscillator is used to internally clock the device This 1s connected to the general purpose clock pin GCLKO There are two reset CPLD DIP switches that provide the configuration shown in Table 5 22 Table 5 22 Reset CPLD Switches Settings OFF 1 ON 0 OFF Settings OFF 1 ON 0 0 a SW3 3 ON Reset a HE controlled Power Up OFF ColdFire controlled MMC T a T There are two status LEDs that provide the information shown in Table 5 23 Table 5 23 Reset CPLD LEDs Color Comments LD602 Yellow ON 3 3 V present OFF 3 3 V not present LD601 Green ON Power Good OFF Power Fail MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 26 Freescale Semiconductor MSC8144AMC S Functional Description 5 5 1 1 Reset Control The reset scheme is shown in Figure 5 14 The CPLD controls the reset to all the devices A single reset controls the Ethernet Quad PHY 88E1145 and Single PHY 88E1111 For the Ethernet switch 88E6185 a single reset from the CPLD is combined with a reset
36. er 4 Controls and Indicators This chapter describes the controls and indicators for the MSC8144AMC S processor board which includes switches jumpers LEDs and push button switches shown in Figure 4 1 LD603 Blue MMC LED Reset Button power recycle LD5 Red MMC LED Configuration Switches 4321 FE SWS Pa on 321 J2 Jumper mos LD611 DSP2 LD613 DSP4 nda e er User Programmable User Programmable i ort 1 Activity SW reset 9 a LD615 AMC Port 0 Activity eL D612 HRESET LD609 PORESET RGMII Activity eLD608 DSP4 LD607 DSP3 LD610 DSP1 _D606 DSP2 LD605 Ethernet Front Panel Activity LD603 MMC Blue LED LD602 3 3V LD601 Power Good LD600 DSP1 LD604 DSP3 User Programmable User Programmable Figure 4 1 MSC8144AMC S Switches Jumpers LEDs and Push Buttons Locations MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 4 1 Controls and Indicators 4 1 DIP Switches Figure 4 1 shows the location on the board of the DIP switches in their default position Figure 4 2 describes the possible settings of the switches Note that when ON the value of the switch is zero For a detailed description of the bits and fields see the MSC8144 Reference Manual Check the default positions and make sure that the board is operational before changing any settings SW3 Configuration SW3 1 SW3 2 SP_IO_SPEEDI O 1 Select TSI578 SRIO Speed 00 1 25 GHz SP 100 01 3 125
37. from the EPROM programmer for reset control The CPLD produces two resets for the TSI578 the Hard Reset SRIO_RESET_N and the Soft Reset SW_RESET_N EF RESET A bald Fire Reset em PHY REETH A ven RESET QP HY RESET H CPLD AD AESETN e AA A ESM AESETN 4 _ SET E M BFOFERETN gu open CE Dealer D a wagering Header ES EER FIEBET Fi a rain Bu fer Ta OP_JUELREBETN Header DPI HHEEETN g TETEM_GPLO RESET SS TEM CPLO Woks 1 ISP S eselpuled high OEP FOREST N 3 S8E1145 BENI TEE SP PORESETN JTAG TASTconeckd lo Dee ReselCPLO DSP PORESET A 03PJ PORESET A _J 245 Bufer Figure 5 14 Reset Scheme The JTAG resets for the 88E1111 88E1145 and TSI578 are routed from the CPLD so the CPLD can control both JTAG and device reset The MSC8144 has three external reset sources Power on Reset PORESET Hard Reset HRESET and Soft Reset SRESET The soft reset is not used in the system and is pulled high The DSP sub system reset is controlled from the Reset CPLD via the signal SYSTEM_RESET_CPLD This signal controls the reset sequencer in the System CPLD The System CPLD controls the PORESET M3_RESET and HRESET of the four MSC8144s The SRESET signals for the MSC8144s are pulled high To facilitate FC programming the programmer reset signal from the expansion connector is combined with the DSP HRESET signal Note that the M3 reset is not 3 3 V tolerant which is why the board includes the level shif
38. g sections 5 7 3 1 1 Hot Swapping a Board In Use the following steps to install the board when hot swapping 1 Set switch SW4 3 to OFF to select the MMC option 2 Insert the AMC board with the handle extracted into an empty slot in the chassis The BLUE LED switches ON once the board is inserted The 3 3 V IPMCV also switches on 3 Close the handle The BLUE LED flashes and then switches OFF The board powers up in the following standard LED sequence a The 3 3V IPMCV stays ON b The Power Good lights and stays ON c The four MSC8144 RGMII activity LEDs switch ON and then OFF d Ethernet port activity LEDs switch ON to indicate any Ethernet link to the backplane system dependent e The DSP HRESET and PORESET LEDs switch ON and then OFF to indicate the reset sequence is complete 5 7 3 1 2 Hot Swapping a Board Out Use the following steps to remove the board when hot swapping 1 Extract the hot swap handle 2 The BLUE LED flashes and then stay ON All LEDs except the 3 3 V IPMCV switch OFF 3 When the BLUE LED is ON the AMC can be removed from the chassis MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 37 MSC8144AMC S Functional Description 9 7 3 2 UART Terminal The MMC output can be viewed through the UART terminal of the Coldfire device via the expansion card The UART operates at 19200 8 N 1 terminal setting The output is displayed in Figure 5 19 KKAKKKAKKAKKKA
39. h clock line AMC_SCL and data line AMC_SDA 5 7 2 6 Geographical Address GA 2 0 Three Geographic Address AMC_GA 0 2 pins represent the module address to the IPMC Each GA line is in one of 3 states High Ground or Unconnected The MMC senses the logical states of these pins to determine its unique IPMB L address 5 7 2 7 Module temperature Sensors The MMC supports two temperature sensors The MMC monitors the temperature sensors and this data can be identified in the MMC Sensor Data Records 5 7 2 8 Module Voltage Sensors Voltage sensors report the status of the power within the module The MMC supports 5 power sources e 12V gt DS e DIN e ISV e ISV 5 7 2 9 MMC UART The MMC can be interrogated by the user via the ColdFire UART connector which is located on the expansion card 5 7 2 10 BDM Debug Header The ColdFire device can be programmed via the BDM header which is located on the expansion header 5 7 2 11 Persistent Store The module contains a serial EEPROM SEEPROM which can be used to store relevant data about the AMC Serial number and so on The FRU data is stored in the Coldfire device internal memory MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 36 Freescale Semiconductor MSC8144AMC S Functional Description 5 7 3 MMC User Operation The following sections describe how to use the MMC functionality 5 7 3 1 Hot Swapping To hot swap a board complete the steps listed in the followin
40. iated DDR2 memory Each MSC8144 has gigabit Ethernet connectivity to the AMC backplane via an Ethernet switch There is serial RapidIO connectivity to the backplane via a serial RapidIO switch In addition 32 TDM lines 16 Rx and 16 Tx are routed to the backplane from each DSP All eight TDM Modules with two links per module are connected together over a common bus to achieve 32 TDM lines For bootstrap purposes a common serial FC bus is connected between the devices with an FC EEPROM hanging of the bus The programming of the EEPROM is through the master MSC8144 or through an in circuit programmer attached to a header on the FC bus 5 1 MSC8144 Digital Signal Processing Block The MSC8144 Digital Signal Processing Block consists of four MSC8144s DDR2 and associated interfaces In the design DSPI is referred to as the master managing the bootstrap of itself and the three slave devices The three slave devices are all identical MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 1 ANO MSC8144AMC S Functional Description 5 1 1 MSC8144 DDR2 Memory Each MSC8144 integrates a DDR2 controller and is provided with 32 bit wide 256 Mbyte external DDR2 SDRAM The memory is constructed with two 400 MHz 8 Mbytes x 16 bits x 8 banks 512 Mbit DDR2 SDRAM devices 200 MHz external clock The DDR2 SDRAM is configured with 13 row address lines 10 column address lines and 8 banks Control of each memory 1s via the CSO
41. ing power up hot swap operations Figure 5 18 details the states M3 Ma FRU Activation FRU Aclivalion complete vat In Progress The Ha LED OFF Blue LED OFF Wees pe e Ba M7 gt Ix l FRU Ti qe si Communication Lost E A 5 4 E Blue LED OFF us f Se aL i A M2 Ve AI M5 FRU d KA FRU Activation i Ce S Deactivation Request e ty Xe d Request Blue LED long x Blue LED short blink blink Deactiva te FRU inse Extraction Criteria a Mat Un Criteria Me Me FRU D O ti B Inactive 0 eag vaton n Progress Blue LED OFF Blue LED short blink Figure 5 18 FRU State Transition Diagram 5 7 2 4 Hot Swap Switch Criteria Mei Deactvate of Unexpected Deactivabon The Hot Swap Switch is activated by the Module latching mechanism and is used to confirm insertion or indicate a request for an extraction to the MMC This switch signal is pulled up to Management Power so that it can be read when Payload Power is not applied The MMC sends an event to the Carrier IPMC when the Hot Swap Switch changes state MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 35 MSC8144AMC S Functional Description 5 7 2 5 Module Management Communications Bus IPMB L Out Of Band OOB module management may be facilitated by utilizing messages carried over IPMB L The IPMB L is an FC bus wit
42. ions enable the MSC8144 to load the 32 bit Reset Configuration Word from a variety of sources Table 5 6 lists the RCW sources on the MSC8144AMC S card Note that this is a subset of available device resources The two options below are selectable via switch 4 Table 5 6 RCW Sources RCW_SRC_0 2 Description Load RCW from I C using a frequency specified by RCFG_CLKIN_RNG RC 0 16 loaded from external pins RC 17 31 are default Loading the RCW from FC allows a different value for each MSC8144 while loading from external pins as shown in Figure 5 8 means each has the same RCW bs di s a g ore e System ee CPLD Ep ig 7 Address DxA0 mm pm e mm pm pm mm pm mm emm pm mm eg Figure 5 8 Reset Configuration from 1 C MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 11 MSC8144AMC S Functional Description 5 1 7 1 Loading Reset Configuration Word from External 1 C When the RCW from FC is selected the board powers up and samples the RCW_SOURCE pins and reads 001 for FC boot as shown in Table 5 7 The MSC8144 then accesses the EC bus at address B 7 0 b1010000 which represents the EPROM Bits B 7 4 b1010 are hard coded into the EPROM device while the bits B 3 1 are defined by the A 2 0 pins which are tied low The final bit BO is set by the read write signal Table 5 7 EEPROM Address After the master MSC8144 DSP1 has read its RCW it configures itself as a
43. led 011000 Serial RapidlO prescale value 200 MHz 8 1 i Lieengd 0001 Pin Mux option 1 DSP1 b000000 DSP Device ID DSP2 b000001 DSP3 b000010 DSP4 b000011 1 Extended reset duration Normal SerDes operation Common Transport is large 16 bit system DSP1 RCWHR 0x44EC0409 DSP2 RCWHR 0x04EC0419 DSP3 RCWHR 0x04EC0429 DSP4 RCWHR 0x04EC0439 DSPI which 1s designated as the F C master controls the STOP BS pins of the three slave DSPs using GPIOI 2 3 as shown in Figure 5 9 DSPI drives these signals during the FC boot process after the DSP exits the reset sequence the signals revert back to standard GPIO STOP_BS STOP_BS STOPES Figure 5 9 PC Multi Boot Control MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 13 MSC8144AMC S Functional Description 5 1 7 2 Loading Reset Configuration Word from External Signals This boot option when RCW_SRC 0 2 is read as b011 uses a combination of pins and default values to set the RCW These values are described in Table 5 10 The RC 0 16 pins are tied together and driven from the System CPLD during Power up The RCWH and RCWL settings are described in Table 5 10 and Table 5 11 Some values can be changed via the system CPLD 1f required NOTE The following restrictions apply when the RCW is loaded from external pins The MSC8144 core frequency is 800 MHz The serial RapidIO interface is restricted to 1 25 GHz data rate with a 100
44. mple Kanda Serial EEPROM Programmer Note that the header provides a reset signal that is used to hold the DSPs in Reset whilst programming from the ICP EEPROM Programming Header Do Not Expansion DSP1 Populate Connector 88E6185 SPI_SCK GPIO21 SPI MISOJGPIO23 SPI MOSI GPIO22 SPI SELIGPIO24 Figure 5 12 MSC8144 SPI 5 2 MSC8144to Backplane Serial RapidlO Connectivity The board uses a Tundra TSI578 Switch to connect the MSC8144 serial RapidIO interface to the backplane The switch also connects to the MSC8144 FC bus 5 2 1 Tundra TSI578 Serial RapidlO Switch The TSI578 provides high performance serial RapidIO interfaces that provide connectivity for control and data plane applications It features eight x4 Serial Rapid IO ports running at up to 3 125 Gbps Four of the ports are connected to the MSC8144s and four are connected to the AMC backplane Two of these connections connect to the fat pipes section of the AMC Connector Ports 4 7 and Ports 8 11 The final two ports connect to the Extended Options region Ports 12 15 and Ports 17 20 These two are for proprietary use and are multiplexed with the TDM interface via a three pad populate no populate zero resistor option Table 5 13 lists the configuration settings for the TSI578 Table 5 13 TSI578 Configuration Description Pin Setting Gemeen DISABLE Disable IC register loading Pull CG Loading is not required after reset SP_RX_SWP
45. mplementation The MMC uses a 32 bit MCF5213 ColdFire microcontroller that communicates with the intelligent platform management controller IPMC on the carrier card or uTCA Carrier Hub MCH in a uTCA system over the intelligent platform management bus IPMB as shown in Figure 5 16 The MMC uses the signal CF_ENABLE_PWR to control the power and reset sequence generators in the Reset CPLD see Figure 5 17 In addition the AMC was designed so that in environments in which the MMC is not present the Reset CPLD can power up the board in standalone mode switch selectable using SW3 3 The Coldfire device supports a UART port and a Background Debug Module BDM via the expansion connector ATCA Carrrier Card Figure 5 16 IPMC IPMB Module Management MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 33 MSC8144AMC S Functional Description Reset Monito E o E Power Cycle VDD1_1vO_ENABLE H Se PORST Tree lt O essa Be ERNST VDD2_1v0_ENABLE iii AA bo Voltage ji 4 ad Monitor res Divider VDD_1V2_ENABLE Ba en E ji SS 3V3_ENABLE EE Be 4 8 E AMC_ENABLE VDD_2V5_ENABLE CF RESET N VDDR_1V8_ENABLE Ci ESW_1V5_ENABLE e o 3 pin connector EE ESW_1V2_ENABLE gt HA RSTO_N RSTIN for external power DSP CLOCKS ENABLE CE EN PAVLOAD PWR SE CG Lav VDD1_1v0_PG Isolate a VDD2_1v0_PG IPMCV 1V8_PG 3V3 PG AMC ENABLE NA ae ea 5 raphic GAJO 2 TA
46. n The configuration can be changed by the user through System CPLD logic Table 5 12 GPIO IRQ Options MSC8144 Pin pe Description Configuration AD3 GPIO13 Timero Can be connected to AMC clocks via CPLD AG2 GPIO16ARQO RQO l Interrupt input to the DSP L3 GPIO17 Timer1 GPIO17 Timer Input L6 GPIO18 Timer2 GPIO18 Can be used to assert an interrupt to other DSPs via the CPLD INT_OUT INT_OUT Low overhead Interrupt output GPIO13 Timer0 GPIO16 IRQO GPIO17 Timeri GPIO18 Timer2 INT OUT DSP1 GPIO13 Timer0 TCLKA cic GPIO16 IRQO TCLKC GPIO17 Timeri TOLKE GPIO18 Timer2 TCLKD NT OUT GPIO13 Timer0 DSP1_PHY_INT GPIO16 IRQO DSP2 PHV INT GPIO17 Timert DSP3 PHV INT GPIO18 Timer2 DSP4_PHY_INT INT_OUT II GPIO13 Timero GPIO16 IRQO GPIO17 Timeri GPIO18 Timer2 INT OUT Goo Figure 5 11 MSC8144 IRQ Timer Resources MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 17 MSC8144AMC S Functional Description 5 1 9 SPI Interface The SPI bus connects between the Ethernet Switch configuration EEPROM DSP 1 and expansion connector and is used to program the Ethernet Switch during the reset phase This gives the user various EEPROM programming options The default programming interface is to program the EEPROM via a header on the expansion card This header is pinned out to allow connection to an in circuit programmer ICP driven from a PC for exa
47. nual Rev 1 Freescale Semiconductor General Information kal 1 MSC8144 UART 2 Coldire MMGIUART 3 Front panel Ethernet AJ45 4 Ethernet Switch EEPROM programming header 5 Extemal DC EEPROM programming header 8 Goldiira MMC BDM Figure 1 2 MSC8144AMC S Expansion Card External Connections 1 4 MSC8144AMC S Block Diagram Expansion Connector 12C h C eader Ce es ee Eth EPROM RapidlO x4 Port 4 7 MSC8144 SN 2 Port D DDR ej d X x4 RapidlO p x4 Port 17 20 rt 17 20 i DDR GigE RapidlO lt TDM i Reset Control Control CPLD MMC Figure 1 3 MSC8144AMC S Block Diagram MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 1 5 General Information 15 Definitions Acronyms and Abbreviations Table 1 1 Definitions Acronyms and Abbreviations mr o bane O O 1 6 Related Documentation This document references the following documents s MSC8144AMC S Getting Started Guide e MSC8144 Reference Manual e MSC8144 Data Sheet e PICMG AMC 0 R2 0 Advanced Mezzanine Card Base Specification e PICMG 2 15 PCI Telecom Mezzanine Carrier card Specification MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 1 6 Freescale Semiconductor General Information 1 7 Specifications Table 1 2 specifies the board physical characteristics Table 1 3 specifies the DSP processing support Table 1 2 MSC8144AMC S Board Characteristic
48. nvironment or standalone 1 2 1 System Development Environment Freescale recommends that the AMC be run using an ATCA uTCA picoTCA chassis or equivalent This delivers the correct power and air flow to the board I nsert the board into the carrier chassis as defined by the specific carrier instructions As in standard development systems these chassis provide direct connections to the JTAG debugger and external connections 1 2 2 Standalone Operation An external keyed power supply connector is provided for standalone operation When using a standalone board you must ensure that adequate cooling is provided for the board Remove the front panel to access the connector 1 3 MSC8144AMC S Processor Board The following subsystems provide a detailed description of the board and its connectors 1 3 1 MSC8144AMC S Features e Target use System component for baseband media gateway and RNC systems Software development platform for baseband media gateway and RNC solutions Design reference and enablement platform for customers and third parties e Form factor Single width AMC size full height Module e Connectivity Two serial RapidIO x4 interfaces from backplane ports 4 and 8 11 routed to DSP farm via a serial RapidIO switch 1000 Base X Gigabit Ethernet from backplane ports 0 and 1 routed to DSP farm via Ethernet switch Gigabit Ethernet routed to front plane expansion connector via a switch E1 T1
49. o Neg advertise all capabilities forced Master 0100 HWCFGMODE 3 0 Auto Neg to Copper Disable fibre SERDES copper auto selection CAC Slt DONO me OO o oo 7550 HM 050 ohm termination for Fibre SERDES O MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 22 Freescale Semiconductor MSC8144AMC S Functional Description 5 4 Backplane Connector The connector provides connectivity to conductive traces on both sides of the AMC PCB There are 170 traces in total The connector interfaces to the following e Four 4x serial RapidIO interface 16 wire e Two Gigabyte Fiber interface for control data e AMC clocks e Propriety TDM Interface e The card is mechanically designed to fit into an AMC slot via its PI connector The connector is hard gold plated for improved insertion durability This connector pin out is described in Table 5 21 Table 5 21 AMC Connector Site Pin Definitions Serial RapidlO Version EI AMC Definition Specific Signal Description EI AMC Definition Specific Signal Description To ND PO el o e o awe GAS GAS AMIG_TMS ml Senn mw o AMO TO 07 mw Jea oo o Peng ale me Deo masono oo ev TI X2O MERO ml en ae eno ANIG_TXD_PO_P ml eno as eno is GDID is stv mu AMDA SIRIO AXD AN ml eno se eno 22777 mp jj GDID el ter AMA SO TD NO __ as eno Je eno S S si IT mp LE lm enp__
50. olled by the Reset CPLD Backplane Connector 9 30 12v ZY1120 VDD1 1V0 ENABLE 1V0 DSP1 a 1V0 DSP2 4 VDD 1V2 ENABLE Power recycle Push Button VDD2_1V0 ENABLE switch IPMCV 3 3V ME Wie A e ZY1120 3V 0 T 2V5 1V2 3V3_ENABLE VDD 2V5 ENABLE VDDR_1V8 ENABLE ESW_1V5_ENABLE ESW_1V2 ENABLE 1V2 Figure 5 15 Power Distribution MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor MSC8144AMC S Functional Description The board receives IPMCV 3 3 V 12 V and ground from the AMC edge connector or 3 pin terminal for standalone operation The 12 V is fed to four DC DC power modules Two vertical Power One ZY 1120 20 A capable modules are used to generate the DSP Core voltages two DSPs per module A third ZY 1120 is used to generate the 3 3 V A fourth Power One YM12S05 5A module supplies power to the 1 25 V rail This supplies the TSI578 and the MSC8144 M3 memory The 3 3 V is also used to generate a number of the peripheral voltages These include 2 5 V M3 1 8 V DDR2 1 5 V and 1 2 V both Ethernet switches NOTE The different power sequencing requirements of the TSI578 and the 88E6185 require separate core supplies The output voltage of the ZY 1120 power modules is defined by the following equation 20 x 5 5 Vout Rtrim Vout An 88 7 KQ trim resistor is used for 1 0 V and a 13 KQ is used for 3
51. onal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale the Freescale logo QUICC Engine StarCore ColdFire and CodeWarrior are trademarks or registered trademarks of Freescale Semiconductor Inc in the U S and other countries RapidlO is a registered trademark of the RapidlO Trade Association All other product or service names are the property of their respective owners O Freescale Semiconductor Inc 2008 All rights reserved bg f freescale semiconductor Contents Paragraph Number Title Chapter 1 General Information 1 1 at ze OCMC A ence nile ection ae iii iaia 1 2 ANERER 1 2 1 System Development EN ee re di lr 1 2 2 Stand alone Operation srne dicta 1 3 MSC8144AMC SS Processor Board 2ccecoecececceccecececcececsececeecscess 1 3 1 MSC8144AMC S Features c ccecsccecsccsceccscsccececsececcscsseccececcscass 1 3 2 External Conn
52. plementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where pers
53. reescale Semiconductor MSC8144AMC S Functional Description Table 5 21 AMC Connector Site Pin Definitions Serial RapidlO Version continued TCLKB_P AMC2_SrRIO_RXD_P1 TCLKB_N AMC2_SrRIO_RXD_N1 ano e end FOLKA AMG2 S RIO TXD PO ANIC2_SrRIO_TXD_NO GND eT AMG2 SFRIO AXD PO nl A AX AMOZ SIRIO AXD NO as GND CIS The serial RapidIO x4 pipes that connect to the extended options region Ports12 20 are multiplexed with the TDM interface The layout routing 1s designed to maintain the desired levels of signal integrity on the SIO signals RapidlO Interface l AMIZ SS Connector RapidlO Interface D de SI i d Figure 5 13 Serial RapidlO TDM Signal Multiplexing MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 25 MSC8144AMC S Functional Description 5 5 General Board Configuration The following subsections described general board configuration issues 5 5 1 Reset Operation and Connectivity Reset control of the board is provided by the Reset CPLD It provides the following functions e Power Control e Reset Control e JTAG routing non MSC8144 The CPLD is powered from IPMCV 3 3 V and can work stand alone or in conjunction with the MMC to power up and control the board When in a chassis the CPLD receives control signals from the AMC backplane and powers up the board When in standalone mode switch selectable The CPLD waits for the detection of a 12 V signal and th
54. s Specifications Power Requirements No external power supply for AMC modes powered from ATCA Carrier uTCA Chassis In standalone mode the recommended PSU should supply 12 V at5A and 3 3 V at 150 mA Operating temperature 0 C to 70 C Storage Temperature 25 C to 85 C Relative humidity 5 to 90 non condensing Dimensions Single width AMC form factor Length 180 6 mm Width 73 5 mm Thickness 1 6 mm Table 1 3 Processing Support Subsystem Specifications MSC8144 DSPs Cores per DSP 4 cores each running at 1 GHz Memory Internal M2 M3 Total 10 96 Mbytes External DDR 256 Mbytes of 32 bit wide DDR2 400 IC EEPROM 64 Kbyte serial EEPROM for Boot Code Communication Ports Gigabit Ethernet RGMII GigE DSP to switch SerDes from switch to backplane frontplane Serial RapidlO Interface x1 x4 serial RapidlO protocols Hardware configurable to 1 25 GHz 2 5 GHz and 3 125 GHz data rates TDM Eight TDM ports shared between DSPs and routed to the backplane via optional DNP resistors UART RS 232 transceiver allows data exchange at 115 Kbps MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 1 7 General Information MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 1 8 Freescale Semiconductor Chapter 2 Hardware Preparation and Installation This chapter provides unpacking instructions hardware preparation and installation instructions for the MSC8144AMC S Processor Board For det
55. signal Individual differential clocks and their associated enable signal are routed to each memory EEC is not supported in this configuration and the unused signals are pulled high low The physical mapping of the signals is shown in Figure 5 1 DSP_DDR_DQJ31 0 DDR DQI15 0 DSP_DDR_DM 3 0 DDR_DM 1 0 DSP DDR DQSI3 0 DDR_DQS 1 0 DSP DDR DQSj3 0 ni DDR_DQS 1 0 DSP_DDR_BAJ2 0 DDR_BA 2 0 EE ose por oso ce l enes Tose mn osonmas Persone oo il once MSC8144 ELT DSPODDRWE DSP_DDR_CLK0 ll DSP_DDR_CLKO ose oon ot e Ill ese vor co OR DSP_DDR_CLK1 DSP_DDR_CLK1 DSP_DDR_CKE1 DDR_DQ 31 16 DDR_DM 3 2 DDR_DQS 3 2 DDR DQSI 3 2 DDR_BA 2 0 DDR_A 12 0 DSP_DDR_CSO DSP_DDR_RAS DSP_DDR_CAS DSP_DDR_WE DSP_DDR_CLK1 DSP_DDR_CLK1 DSP_DDR_CKE1 Figure 5 1 DDR2 Connectivity MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 2 Freescale Semiconductor MSC8144AMC S Functional Description 5 1 1 1 DDR Groups Every DDRII signal can be considered to be a member of one of four separate groups Each group has unique rules in terms of signal connection and signal routing The four groups are shown in Table 5 1 Table 5 1 DDR2 Interface Signals naa Y ent TI o Row Address Strobe Conia Clocks MCK 1 On Oock 8A 0 eee MCK 1 0 E Complement Complex DDR2 timing adaptation is available via the DDR clocking subsystem of the MSC8144
56. ter logic for 2 5 V MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 5 27 MSC8144AMC S Functional Description 5 5 2 System CPLD The system CPLD provides the following functionality e Interfaces MSC8144 TDM to the AMC backplane connector e Drives the reset and configuration for the MSC8144 e Collect and distribute the GPIO Interrupts on the board e Multiplexes MSC8144 UARTS and routes a single UART to the expansion connector There are six System CPLD DIP switches described in Table 5 24 and Table 5 25 Table 5 24 System CPLD Switches Feature Settings Der ON 0 Comments SW3 1 ON Not used in CPLD SW3 2 e Switches connect directly to TSI578 to control serial RapidlO frequency Table 5 25 System CPLD Switches Settings OFF 1 ON 0 Comments SW4 1 SW4 2 Select MSC8144 UART output ON ON 00 DSP1 ON OFF 01 DSP2 OFF ON 10 DSP3 OFF OFF 11 DSP4 SW4 3 ON Reset Configuration Word from IEC Boot port serial RapidlO interface OFF Reset Configuration Word from pins Boot Port IC SW4 4 ON Debug OFF EE0 0 OFF Debug ON EE0 1 There are also two status LEDs which provide the information shown in Table 5 26 Table 5 26 Reset CPLD LEDs Feature Color Comments LD612 MSC8144 HRESET Logical AND of all DSP HRESET signals E MSC8144 PORESET Logical AND of all DSP PORESET signals MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 28 Frees
57. the TSI578 88E1111 88EE6185 and 88E1145 JTAGs to the AMC backplane JTAG SPHY_TDO SPHY AMC QPHY_TDO Connector E q QPHYTDI QPHY_TDI QPHY AMC_TDO AMC_TDI 5 SRIO_TDI SRIO_TDO BSCAN Tester PHY_TRST_N AMC_TRST_N AMC_TMS Figure 5 20 Boundary Scan Routing 5 9 Thermal Requirements A heatsink is used to cool the MSC8144 and TSI578 devices The heatsink definition is based on thermal simulation within an ATCA chassis with an air flow of 22 m s A small slip is used to ensure the heatsink makes contact with the lower profile TSI578 The AMC should be placed near the fan outlet to maximize cooling MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 42 Freescale Semiconductor Chapter 6 Revision History Table 6 1 Revision History CT i i Added detailed O information on pages 1 1 1 3 4 2 4 3 and in Section 6 2008 E 5 7 starting on page 5 32 MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 Freescale Semiconductor 6 1 Revision History MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 6 2 Freescale Semiconductor
58. up process The power up sequence is as follows 1 MSC8144 Core Voltages 1 0 V TSI578 M3 Core voltages 1 25 V I O voltage 3 3 V Ethernet Switch IO voltage and M3 voltage 2 5 V DDR 1 8 V Ethernet Switch IO voltage 1 5 V 7 Ethernet Switch Core voltage 1 2 V rat ae a This power up procedure satisfies the main sequencing requirements which are that the MSC8144 and TSI578 Core voltages should be up before the 3 3 V It also meets the reverse requirement for the Ethernet switch which is that the 3 3 V I O voltage should be up before its 1 25 V Core voltage 5 7 Module Management Controller MMC The MSC8144AMC S incorporates a module management controller which resides on the on board ColdFire device The MMC software is supplied by CorEdge and is programmed into the Coldfire device internal Flash The MMC provides the following functions e Module Hot Swap manger to facilitate AMC insertion and extraction e Monitors and controls power using the voltage sensors and power switches e Monitors temperature using 2 temperature sensors e Monitors faults and reset MMC in event of fault using MMC Watch dog timer WDT e Provides Flash memory for FRU records e Provides visible module status information using the mandatory blue LED hot swap state and red LED fault condition MSC8144AMC S Advanced Mezzanine Card User Manual Rev 1 5 32 Freescale Semiconductor MSC8144AMC S Functional Description 5 7 1 MMC I
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