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DesignWare IP Family Reference Guide

1. DW_apb_ssi APB Synchronous Serial Interface DW_apb_ssi Transmit i is APB pein ae Interface o Logic lt gt Receive 2 FIFO N Control fo D Register z Block Interrupt Transmit Logic FIFO Memory DMA Interface Receive FIFO Clock FSM Control This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_ssi Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 45 DesignWare IP Family DW_apb_timers APB Programmable Timers DW_apb_timers APB Programmable Timers e Up to eight programmable timers e Configurable option for a single or e Configurable timer width 8 to 32 bits combined interrupt output flag e Support for two operation modes e Configurable option to have read write free running and user defined count coherency registers for each timer e Support for independent clocking of e Configurable option to include timer timers toggle output which toggles each time counter reloads e Configurable polarity for each individual interrupt DW_apb_timers Timer2 TimerN N lt 8 This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_timers Databook is available at http www synopsys com pr
2. gt conditional signals These signals are for simulation purposes and should be left unconnected at the system level More information on the DW_rambist MacroCell can be found at http www synopsys com products designware docs ds i DW_rambist_ds pdf 68 Synopsys Inc June 2009 DesignWare IP Family Microprocessors Microcontrollers The components detailed in this section contain a page reference in the following table Component Name Component Description DW_IBM460 S DW_IBM405 S PowerPC 440 Microprocessor Core from IBM page 177 DWC_n2p Nios II Processor Core page 182 DW_6811 8 bit Microcontroller page 70 DW8051 8 bit Microcontroller page 72 g r Q lt S gt D b N D 7 D 5 a Synthesizable RTL of the processor cores are available through the Star IP Program For more information on this program visit http www synopsys com designware June 2009 Synopsys Inc 69 DesignWare IP Family DW_ 6811 6811 Microcontroller DW_6811 6811 Microcontroller 70 e Compatibility with industry standard 68HC11 microcontroller o 8 bit CPU with 8 bit 16 bit ALU e Two 8 bit accumulators that can be concatenated to provide 16 bit addition 16 bit subtraction 16 x 16 division 8 x 8 multiplication shift and rotate e Up to 18 maskable interrupt sources 17 maskable internal interrupts and 1 maskable external interrupt e Power saving STOP and
3. DesignWare IP Family DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect All Models e Compliant with AXI 1 0 specification e Support all AXI data address widths e Support all protocol transfer types and response types e Checks for all protocol violations e Logs transactions and reports on protocol coverage e Configurable message formatting e Support VCS Native Testbench NTB e Support OpenVera Reference Verification Methodology RVM e Support Verification Methodology Manual VMM for SystemVerilog AXI Master axi_master_vmt e Configurable outstanding transactions e Out of order transaction completion e Unaligned data transfers using byte strobes e Protected accesses and Atomic access e Response through command and notification AXI Slave axi_slave_vmt e Configurable multiple transaction e Out of order completion e Read interleaving e Unaligned data transfers using byte strobes Variable Slave response Supports FIFO memory e Slave aliases up to 3 additional portsResponse through notification at the end of Read Write transactions January 2009 AXI Bus Monitor axi_monitor_vmt Full protocol checking for AXI interface protocol Up to 32 Master and 32 Slave ports Independent of interconnect support for shared buses Shared address shared data SASD Configurable data bus widths Configurable ID bus widths Master ID p
4. two with and two without clock enables Low gate count implementation minimum configuration below 2K gates e Sub optimal throughput performance non buffered architecture High clock speed operations fully registered outputs operating frequency more than 300 MHz AHB Master Interface R 32 Configurable AHB address width 32 or 64 bits Configurable AHB data width 32 64 128 or 256 bits Configurable endianness HLOCK generation HBUSREQ generation HTRANS generation of IDLE or NSEQ bus cycles Non pipelined transfers address phase always followed by IDLE cycles until data phase completes HBURST fixed to SINGLE e All other AHB control signals forwarded unchanged AHB Lite configuration to remove redundant logic Deadlock detection Synopsys Inc AHB Slave Interface Deadlock protection SPLIT response generation after deadlock detection at the master interface Bus held off HREADY low until the secondary transfer data phase completes and is acknowledged back from the master interface SPLIT response from secondary forwarded back to primary as RETRY Component ID code retrievable from read data bus Support for locked transfers any HTRANS through HMASTLOCK IDLE and BUSY non locked cycles ignored June 2009 DesignWare IP Family DW_ahb_h2h AHB to AHB Bridge g m wo lt m gt D a N D D 5 cl
5. 7 D E DW_6811_biu sfr_bus DW_6811_alu spi_sck_in spi_sck_out spi_miso_in spi_miso_out spi_mosi_in spi_mosi_out spi_ss_n spi_miso_out_en spi_mosi_out_en spi_sck_out_en mem_bus interrupts DW_6811_spi optional sci_txd sci_rxd txd_en irom_bus Internal ROM iROM OK 4K 8K 16K 32K or 64K DW_6811_sci optional ir stop_mode walt_mode test_addr The DesignWare DW_6811 MacroCell Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 71 DesignWare IP Family DW8051 8051 Microcontroller DW8051 8051 Microcontroller e Compatible with industry standard 803x 805x o Standard 8051 instruction set o Optional full duplex serial ports selectable through parameters o Optional third timer selectable through parameter o Control signals for standard 803x 805x I O ports e High speed architecture o Four clocks per instruction cycle o 2 5X average improvement in instruction execution time over the standard 8051 o Runs greater than 300 MHz in 90 nanometer process technology o Wasted bus cycles eliminated o Dual data pointers 72 Synopsys Inc Io 1O Can Parameterizable internal RAM address range Parameterizable internal ROM address range Simple integration of user defined peripherals through external Special Function Register SFR interface Enhanced memory interface with 16 bit address bus Var
6. Registers a co faa g T g 5 USB 1 1 OHCI gt m im Host Controller I with AHB VCI O gt Initiator AHB VCI Target g Transaction Controller AHB 2 USB 1 1 OHCI VCI m Host Controller Arbiter I with AHB VCI O gt The dwcore_usb2_host datasheet is available at http www synopsys com cgi bin dwcores pdfrl cgi file dwc_usb_2_0_host_subsystem pci ahb pdf 010 MA June 2009 Synopsys Inc 161 DesignWare IP Family dwc_usb_2_ 0_hs_otg_subsystem ahb Synthesizable Hi Speed USB On The Go OTG Controller Subsystem dwc_usb_ 2 0 hs_otg_subsystem ahb Synthesizable Hi Speed USB On The Go OTG Controller Subsystem The DesignWare Hi Speed USB On The Go HS OTG Controller Subsystem operates as either a Hi Speed USB compliant peripheral host or OTG Dual Role Device DRD This core has earned Hi Speed USB OTG certification with the Synopsys USB OTG PHY in three semiconductor processes Features include the following General Features Supports different clocks for AHB and the PHY interfaces for ease of integration Uses the coreConsultant utility to configure the core to user requirements Supports Slave External DMA Controller Interface or Internal DMA modes Includes USB power management features Includes power saving features clock gating two power rails for advanced power management Supports packet based Dynamic FIFO memory allocation
7. System Bus PRIMARY ON_CHIP BUS Data Cache Data Tag amp Victum DTCM SECONDARY ON_CHIP BUS Instruction Cache Data Tag amp BHT Bridge F CD SRAM Nios Il FPGA Base Configuration Options Table 1 shows the Nios II FPGA base configuration options Table 1 Nios Il FPGA Base Configuration Options Nios II f Nios II s Nios II e Fast Processor Standard Processor Economy Processor Pipeline 6 stage 5 stage None Hardware multiplier and 1 cycle 3 cycle Emulated in software barrel shifter Branch prediction Dynamic Static None Instruction cache Configurable Configurable None Data cache Configurable None None Custom instructions Up to 256 June 2009 Synopsys Inc 183 Index Numerics 10 Gigabit Ethernet Models 82 A ahb_bus_vmt 76 ahb_master_vmt 76 ahb_monitor_vmt 76 ahb_slave_vmt 76 AMBA AHB Models 76 AMBA APB Models 78 AMBA QuickStart 61 apb_master_vmt 78 apb_monitor_vmt 78 apb_slave_vmt 78 axi_interconnect_vmt 79 axi_master_vmt 79 axi_monitor_vmt 79 axi_slave_vmt 79 B Board Verification IP listing 20 C Cores overview 108 D DesignWare Core dwe_ddr2 3 Lite 125 dwe_ddr2 tsmc_130g_33 127 dwc_usb2_hsotg_phy 168 dwc_usb2_nanophy 172 dwc_usb2_phy 166 DesignWare Cores overview 108 DesignWare FlexModels listing 96 DesignWare FlexModels overview 96 DesignWare Foundry Libraries 100 184 DesignWare IP Family Index DesignWare Hard IP dwc
8. WiMedia MAC PHY Interface 010 MA The DesignWare dwc_wiusb_device_controller datasheet is available at http www synopsys com products designware wiusb_solutions html June 2009 Synopsys Inc 171 DesignWare IP Family dwc_usb2_nanophy USB 2 0 nanoPHY dwc_usb2_nanophy USB 2 0 nanoPHY The USB 2 0 nanoPHY provides designers with a complete Physical Layer PHY IP solution designed for low power mobile and consumer applications such as next generation handheld game machines feature rich smart phones digital cameras and portable audio video players The DesignWare USB 2 0 nanoPHY IP delivers approximately half the power and die area compared to other solutions for longer battery life and lower silicon cost Designed for high yield the DesignWare USB 2 0 nanoPHY implements architectural features that make it less sensitive to variations in foundry process device models package and board parasitics Other features include the following e Small area 0 6 mm Complete mixed signal physical layer for single chip USB 2 0 OTG and non OTG applications Low power 100 mW during HS packet transmission 2 High yield Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process chip and board parasitics and process device model variations Designed for the latest 65 90 and 130 nm low power LP CMOS processes e Low pin count 172 USB 2 0 Transce
9. behavioral 98 FlexModels 96 SmartModel behavioral simulation 98 O ocp_master_svt 86 ocp_monitor_svt 86 ocp_slave_svt 86 Open Core Protocol OCP Models 86 186 Synopsys Inc DesignWare IP Family P PCI PCI X Bus Verification Models 90 PCI Express Models 88 pcie_txrx_vmt 88 PCle AHB Bridge 135 pcimaster_fx 90 pcimonitor_fx 90 pcislave_fx 90 Q QuickStart AMBA 61 R rmiirs_fx 83 S sata_device_vmt 92 sata_monitor_vmt 92 SCL 10 Serial ATA Models 92 Serial Input Output Interface Models 94 sio_monitor_vmt 94 sio_txrx_vmt 94 SmartModel Library SWIFT interface connection through 98 SmartModels listed in IP Directory Web site 98 Star IP Core DW_CoolFlux 179 DW_IBM440 177 DWC_n2p 182 Star IP overview 176 SWIFT interface connection between SmartModels and simulators 98 Synopsys Common Licensing 10 T TSMC Libraries 100 June 2009 DesignWare IP Family Index U USB On The Go Models 95 usb_device_vmt 95 usb_host_vmt 95 V Verification IP for Bus and I O Standards listing 19 Verification IP overview 74 June 2009 Synopsys Inc 187
10. e Support for 32 memories per BIST controller e Highly configurable memory interface to suit most types of memories Supported Memory Configurations e True at speed testing of memories in parallel e Memory array test via single port and multi port e Ability to enable disable testing of individual memories e Multiple controller scheduling e Support for incomplete address space Synopsys Inc 67 g m wo lt m gt D 2 N D D 5 DesignWare IP Family M oy DW_rambist C J Memory Built In Self Test s Design for test Design for Verifiability e Configuration of shadow logic capture e simulation_mode signal to provide verification of very large configurations and to quickly check system level interconnection e Sample script for scan chain creation and connection part of example design e Integration with DFT Compiler BSD Compiler and TetraMax DW_rambist monitor_bus bist_mode gt clk clk_t simulation_mode J Controller oO DW_rambist_ctrl BIST I F_O 3 E mode_reg_si Pals Capture_0 e shift_dr T parallel_dr 3 mode_reg_in mbrun E E rst_n_a S debug_so fe debug_out_N T mode_reg_out 3 mode_reg_so o o lt x 2 z oO 3 O Z oO lt n o 3 P number of ports 0 lt P lt 3 Mode Register width 1 0 2 N Memory number 0 lt N lt 31 2 Address width 1 0 _ conditional blocks 3 Number of Memories 1 0
11. e Transfers o Support for memory to memory memory to peripheral peripheral to memory and peripheral to peripheral DMA transfers o DW_ahb_dmac to or from APB peripherals through the APB bridge e Component parameters for configurable software driver support e coreAssembler ready Channel 0 AHB Slave I F The DesignWare DW_ahb_dmac Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 29 DesignWare IP Family DW_ahb_eh2h Enhanced AHB to AHB Bridge DW_ahb eh2h Enhanced AHB to AHB Bridge Clocks AHB Master interface e Asynchronous or synchronous clocks e Data width 32 64 128 or 256 bits any clock ratio e Address width 32 or 64 bits e Fully registered outputs e Big or little endian e Optional pipeline stages to reduce e Lock and bus request generation logic levels on bus inputs e SINGLE INCR burst type generation for writes AHB Slave interface e Any burst type generation for reads e Data width 32 64 128 or 256 bits e Downsizing of wider transfers Address width 32 or 64 bits Write operations e Big or little endian e Zero or two wait states OKAY e Configurable depth write buffer response e Buffered writes always HPROT is e ERROR response don t care e No RETRY response e SPLIT response on write buffer full e SPLIT response e Maximum of two wait states on e HSPLIT generation non sequential access e Handling of multiple
12. page 53 DW_axi_hmx AMBA AXI Slave to AHB Master Interface page 54 DW_axi_rs AMBA AXI Register Slice page 55 DW_axi_x2h AXI to AHB Bridge page 56 DW_axi_x2p AXI to APB Bridge page 57 DW_axi_x2x AXI Master to AXI Slave Bridge page 59 A brief introduction to DesignWare AMBA components is available at the following location http www synopsys com products designware dw_amba html Source Licenses Available You can configure any of the DesignWare AMBA synthesizable components and write out encrypted RTL using only a DesignWare license If you want to write unencrypted RTL source code you must purchase a special source license For more information about licenses please refer to the DesignWare AMBA Synthesizable Components Installation Guide www synopsys com products designware docs doc amba latest dw_amba_install pdf DesignWare AMBA QuickStart The DesignWare AMBA QuickStart page 61 is a collection of example designs for AMBA subsystems built with DesignWare AMBA synthesizable components The QuickStart example designs are static non reconfigurable examples of complete subsystems that use DesignWare AMBA synthesizable and verification components 26 Synopsys Inc June 2009 DW_ahb Advanced High Performance Bus e Configuration of AMBA Lite system e Configuration of up to 15 masters in a non AMBA Lite system e Configuration of up to 15 slaves e Configuration of data bus width of up to 256 b
13. 0 15 0 13 micron Nexsys 90 nanometer and Nexsys 65 nanometer Standard Cells and I Os are available to DesignWare Library licensees at no additional cost A selection of memory compilers for TSMC Nexsys 90LP and TSMC Nexsys 65LP process described on page 105 are also available and licensed independently from the DesignWare Library TSMC Libraries are developed by TSMC and process tuned to TSMC s semiconductor technologies Each logic and I O cell is validated in silicon and meets the company s rigorous library quality criteria TSMC libraries are in production in multiple customer designs Table 1 on page 101 shows the TSMC Standard I O categories Table 2 on page 102 shows the TSMC Standard Cell categories For more information about the TSMC Libraries visit http www synopsys com products designware tsmc html 100 Synopsys Inc June 2009 DesignWare IP Family Chapter 3 DesignWare Foundry Libraries Table 1 TSMC Standard I O Categories Technology Process Core Voltage I O Voltage Configuration Library Name 65nm Low Power 1 2V All 2 5V 3 3V tol Staggered TPZNO65LPGV2 Universal All Staggered TPBN65GV Universal 90nm General Purpose 1 0V 2 5V Staggered TPDN90G2 1 8V Staggered TPDN90G18 3 3V Staggered TPDN90G3 130nm General Purpose 1 2V HVT 2 5V 3 3V tol Staggered TPZ013G2 3 3V 5V tol Staggered TPZ013G3 1 2V 2 5V Linear TPDO13N2 eee Linear TPD
14. 2 e Packet error injection detection g e Suspend resume reset signaling a e Link Power Management LPM e Supports SRP and HNP e Supports VCS Native Testbench W NTB e Supports Verification Methodology Manual VMM for System Verilog and OpenVera RVM DUT USB Hub USB Host USB Device USB OTG Device A guide to all USB VIP documentation is available at https www synopsys com dw doc php vip usb latest doc usb__overview pdf June 2009 Synopsys Inc 95 Listing of FlexModels DesignWare IP Family DesignWare FlexModels FlexModels are binary simulation models that represent the bus functionality of microprocessors cores digital signal processors and bus interfaces FlexModels utilize the industry standard SWIFT interface to communicate with simulators FlexModels have the following features e Built with a cycle accurate core and a controllable timing shell so that you can run the model in function only mode for higher performance or with timing mode enabled when you need to check delays You can switch between timing modes dynamically during simulation using simple commands in your testbench e Feature multiple different control mechanisms You can coordinate model behavior with simulation events synchronize different command processes and control several FlexModels simultaneously using a single command stream e Allow you to use different command sources You can send commands to DesignWare Li
15. 54 16 Synopsys Inc June 2009 DesignWare IP Family Chapter 1 Overview Component Name DesignWare AMBA Synthesizable IP DW_axi_rs AMBA AXI Register Slice page 55 DW_axi_x2h AXI to AHB Bridge page 56 DW_axi_x2p AXI to APB Bridge page 57 DW_axi_x2x AXI to AXI Bridge page 59 Component Name DesignWare AMBA Component Description Verification IP ahb_bus_vmt ahb_master_vmt ahb_monitor_vmt ahb_slave_vmt AHB Bus Interconnect page 76 AHB Master page 76 AHB Monitor page 76 AHB Slave page 76 apb_master_vmt apb_monitor_vmt apb_slave_vmt APB Master page 78 APB Monitor page 78 APB Slave page 78 axi_master_vmt axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt DesignWare VIP for AMBA 3 AXI page 79 DesignWare AMBA QuickStart The DesignWare AMBA QuickStart page 61 is a collection of example designs for AMBA subsystems built with DesignWare AMBA components The QuickStart example designs are static non reconfigurable examples of complete subsystems that use DesignWare AMBA synthesizable IP and VIP components Star IP Microprocessor and DSP Cores Component Name Component Description Component Type DW_IBM460 S PowerPC 440 32 Bit Microprocessor Cores Synthesizable RTL DW_IBM405 S from IBM page 177 Verification Model DW_CoolFlux CoolFlux 24 bit DSP Core from Philips Synthesizable RTL page 179 Verification Model DWC_n2p Nio
16. Buffers activity on all of the AXI channels minimizing waits on o Single clock or two clocks of any AXI control data and response clock integer ratio e Support for different clock domains o Supports a wide range of O Support for quasi synchronous user selectable depths for the clocking single clock with the command queues response buffer use of a pclk_enable allows APB read data and write data buffers side of bridge to issue at a slower rate than the system June 2009 Synopsys Inc 57 DesignWare IP Family DW_axi_x2p Connects AMBA AXI Slave to AHP Master AXI Interconnect AXI Bus Width AXI Slave Port AXI Clock Domain X2PP DW_axi_x2p X2P2 APB Clock Domain APB Master Port APB Bus Width This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler htm Documentation for this product is available at http www synopsys com products designware docs 58 Synopsys Inc June 2009 DesignWare IP Family DW_axi_x2x Connects AMBA AXI Master to AXI Slave DW axi x2x Connects AMBA AXI Master to AXI Slave e Translates AXI transactions into APB e Data Channel Features transfers o Data Ports 8 16 32 64 128 256 o Compliance with AMBA AXI Protocol Rev 1 0 from ARM o Transparent Operation transaction attributes altered when necessary to fit on secondary bus o Accepts simultaneous AXI
17. DesignWare XAUI PHY supports the 10 gigabit Ethernet standards that are commonly used in high speed communications applications Based on Synopsys s silicon proven and award winning high speed SERDES technology the XAUI PHY provides a cost effective and extremely low power solution designed to meet the needs of today s XAUI designs Designed for advanced manufacturing processes the XAUI PHY is targeted to popular low power and high performance CMOS digital logic processes The XAUI PHY integrates high speed mixed signal custom CMOS circuitry compliant with the XAUI IEEE base specification 802 3ae While extremely low in power consumption and area requirements the DesignWare XAUI PHY substantially exceeds the electrical specifications in key performance areas such as jitter and receiver sensitivity To handle increasing communication system speeds the XAUI standard was designed to take a 10 Gbps serial stream and divide it into four 2 5 Gbps serial streams that run over copper traces and chip to chip connections using 8b10b coding at 3 125 Gbaud By taking advantage of copper links higher performance communications applications can be cost effectively deployed 174 Synopsys Inc June 2009 June 2009 Features e Supports 1 OGBASE CX4 Transmits 3 125 Gbps differential NRZ serial stream Receives 3 125 Gbps differential NRZ serial stream Supports asynchronous operation e Supports both 10 bit and 20 bit parallel ASIC interfa
18. Master interface Takes care of the 1KB boundary breakup Includes optional interface to an external DMA controller data is transferred through the AHB Slave interface Optional support for a dedicated transmit FIFO for each of the device IN endpoints in Slave and DMA modes Each FIFO can hold multiple packets DWC Hi Speed USB OTG Controller June 2009 DesignWare IP Family Og dwc_usb_2 0 hs_otg_subsystem ahb S Synthesizable Hi Speed USB On The Go OTG Controller Subsystem 5 l J Single Tx Single Rx Non Periodic Non Periodic Host and Host and Device Device n v I gt CSRs Synchronizer PHY AHB Clock Clock Domain Domain Clock Fg ee me te et rm I a A A AEE AA E Power Generator gt PERES E E Ee ae Control I paa ULPI UTMI Configuration Option PHY Level 3 PHY 010 MA The dwcore_usb2_hsotg datasheet is available at http www synopsys com products designware docs ds c dwc_usb_2_0_hs_otg_subsystem ahb html June 2009 Synopsys Inc 163 DesignWare IP Family dwc_usb_2 0 device Synthesizable USB 2 0 Device Controller dwc_usb 2 0 device Synthesizable USB 2 0 Device Controller The USB 2 0 Device Controller UDC20 features industry standard interfaces that easily integrate the USB 2 0 transceiver and application logic The RapidScript utility builds the core and test environment in source code for the targeted application Other features in
19. SEREDES PHY CSR Access Control Power Sequence a SEREDES PHY Power Control Control OR MDIO Interface MCI Interface The dwc_ether_xgxs_pcs datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_ether_xgxs_pcs pdf 118 Synopsys Inc June 2009 K dwc_mobile_storage Mobile Storage Host Controller Core Features June 2009 e SD 2 00 SDIO 2 0 MMC 4 2 and CE ATA 1 1 e Configured either as an MMC only controller or SD_MMC controller e 1 30 MMC cards in MMC only mode or 1 16 cards in SD_MMC mode e SD_MMC mode supports CE ATA e Command Completion Signal and interrupts to host for CE ATA e Command Completion Signal disables CRC generation and checking in CE ATA mode e SD_MMC mode supports 1 bit 4 bit and 8 bit cards e Programmable baud rates supports up to four clock dividers for simultaneous operation of cards with different clock speed requirements e Card detection and write protection e Host pullup control e SDIO interrupts in 1 bit and 4 bit modes e l to 65 535 byte blocks e Suspend and resume operations e Low power system option with individual clock and power ON OFF features to each card e Lane reversal and polarity inversion Bus Interface Features e Supports either AMBA 2 0 AHB or APB slave interfaces Synopsys Inc DesignWare IP Family dwc_mobile_storage Mobile Storage Host Controller Supports 16 32 or 64 bit data widths S
20. Support for VLAN tag inclusion replacement detection on transmit Separate transmission reception and control interfaces Optional forwarding of received pause control frames Automatic transmission of zero quanta pause frame on flow control input deassertion 32 bit CRC generation for transmit frames Per frame CRC checking and stripping on receive Transmission and receive padding enabled for less than 64 bits Jumbo Ethernet frame support up to 64KB 64 bit status returned for each transmitted or received packet Programmable address inclusion replacement for transmit frames 010 MA IPv4 header checksum procession for transmit and receive Optional Network statistics with ROM MIB counters Optional internal loop back on XGMII for system packet debugging Configurable filtering transition layer Tx Rx FIFO and debugging support TCP UDP or ICMP checksum offload IPv4 and IPv6 for transmission and reception June 2009 Synopsys Inc 115 DesignWare IP Family dwc_ether_xgmac XGMAC 10G Ethernet MAC Control Status Registe CSR x gt O ro 0 a y e Sarr Control Status Registe CSR The dwc_ether_xgmac datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_ether_xgmac pdf 116 Synopsys Inc June 2009 DesignWare IP Family Og dwc_ethernet_pcs S Ethernet Extension Sub layer dwc_ethernet_pcs Ethernet Extension Sub layer The DesignWare Ethernet PCS Core c
21. This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html Documentation for this product is available at http www synopsys com products designware docs June 2009 Synopsys Inc 53 DesignWare IP Family DW_axi_hmx Connects AMBA AXI Slave to AHB Master DW_axi_hmx Connects AMBA AXI Slave to AHB Master e Connects a single AHB master to a Big endian AHB to AXI conversion single AXI slave without use of AHB bus fabric Locked transactions Support for all AHB burst types e Single clock design with quasisynchronous fell Timing mode options to ease timing closure Buffer rite transactions Sc tered We angat e Option to block writes Wate errance ot hy hardy e Static setting of AWPORT ARPORT interface secure bit e Low power interface DW_axi_hmx AHB AXI Master Master AHB Slave AXI Master AXI Interconnect This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html Documentation for this product is available at http www synopsys com products designware docs 54 Synopsys Inc June 2009 DesignWare IP Family DW_axi_rs AMBA AXI Register Slice DW_axi_rs AMBA AXI Register Slice e Full support of the AXI protocol e No throughput penalty for any of the g e Supports the following timing modes pune meade opacus m o P
22. WAIT modes o Standard 68HC11 instruction set e Simple integration of user defined peripherals through external Special Function Register SFR interface within SFR array space e Fully synchronous implementation Synopsys Inc Io 1O Can e A BIU unit to provide control signals for memory and I O ports o Programmable memory map for internal RAM GRAM and SFR array spaces o Parameterized internal ROM GROM size o De multiplexed external memory interface e Optional peripherals o 16 bit timer e Three Input Capture IC channels e Four Output Compare OC channels e One software selectable IC or OC channel o 8 Bit pulse accumulator o COP watchdog timer system o SPI synchronous serial port basic or enhanced SPI or SPI o SCI UART basic or enhanced SCI or SCI o Up to 3 external reset interrupt sources o Up to 17 internal interrupt sources June 2009 DesignWare IP Family Mg DW_6811 6811 Microcontroller timer_nocop timer_pai timer_ici timer_ic2 timer_ic3 timer_ic4 timer_oct timer_oc2 DW_6811_timer optional Internal RAM iRAM 256 512 or 1024 includes timer_oc3 pulse timer_oc4 iram_bus accumulator timer_oc5 and timer_oc1_en timer_oc2_en timer_oc3_en timer_oc4_en timer_oc5_en DW_6811_math COP watchdog DW_6811_cpu optional DW_6811_contro DW_6811_interrupt DW_6811_opdecoder g m Q gt D o N D
23. a synthesizable solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following Complies to PCI Express Base Specification Revision 2 0 Modular design including a base core CXPL plus additional support modules for Endpoint specific functionality Operating mode EP or RC determined by state of input pin at power on reset Type 0 configuration space in EP mode type configuration space in RC mode 62 5MHz 125MHz 250MHz SOOMHz Up to 16 2 5 Gbps Lanes x1 x2 x4 x8 or x16 e 32 64 or 128 bit datapath width Support for 8 16 32 bit PHYs through the PIPE e Ultra low transmit and receive latency e Configurable retry buffer size Configurable number of outstanding Requests Configurable Max_Payload_Size size 128 bytes to 4 KB 4 KB maximum Request size e Very high accessible bandwidth 144 Automatic Lane reversal as specified in the PCI Express Base Specification transmit and receive Synopsys Inc In RC mode application initiated Lane reversal for situations where the EP Core does not detect Lane 0 for example an x4 EP Core connected to an x8 device that has its Lanes reversed Polarity inversion on receive Multiple Virtual Channels VCs Multiple Traffic Classes TCs Multiple functions Supports bypass cut through and store and forward queues for received TLPs Configurable for infini
24. b APB Slave MyExtApbSlv apb_rap BFM i_intr1 i_uart1 SIO BIM gt DW_apb_ictl DW _apb_uart see tests i_gpio I I i_uart2 A DW _apb_gpio gt DW _apb_uart z i_wdt 2 DW_apb_wadt EEPROM DW _apb_ssi i_rtc testbench i_ssi2 loopback DW_apb_rtc connections DW_apb_ssi i_timer i_i2c1 I2C BIM_1 ae DW_apb_timers l2C_BIM_2 DW_apb_i2c Sa I2C_BIM_3 i_i2c2 I DW_apb_i2c s slave s11 m master DW_amba_subsystem_SingleLayer v 2 DW_apb_ssi i_ssil can also communicate with an EEPROM as opposed to the other DW_apb_ssi i_ssi2 3 DW_memctl i_memctl connects to five external memories three SRAMs one SDRAM and one FLASH 62 Synopsys Inc June 2009 DesignWare IP Family DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems testbench v Testbench Slave AHB APB Configuration BFM Monitor and Stimulus EMi Masters Slaves 12C_BIM_2 0 12C_BIM_3 m3 gm4 m5 s6 s7 rm r o DW_apb_i2c1 lt i_i2c1 gt DW_apb_i2c1 2 i_i2c2 N DW_apb_rap e i_rap oO DW_ahb_h2h DW_apb_wat v i_h2hi a i_wdt DW_ahb_h2h i_h2h2 AHB AHB AHB AHB BFM APB Clock Monitor Monitor Monitor or DSM Monitor Generation EEPROM Master z DW_apb_ssi i_s
25. cece cece eee e teen enenens 38 DW_apb_i2s ME AG shes yg ee ee 40 DW_apb_ictl AFB ere Ces leg kedcnekseeaseens te ddanceudsegnnt cies 4 DW_apb_rap AFB Kemapond PaE 3 ooo cee bk eee bie eee ks eee REg 42 DW_apb_rtc AFB Real Time Clock vee canecs badenbs ttrt ita EP ERRO e EREA oben 43 DW_apb_ssi APB Synchronous Serial Interface 6 o66ce se oesseosese tie ese Ge tabounee se 44 DW_apb_timers APB Programmable TIMErS sco sek cinesdidasae sd bhebneesadeebe bs kEi 46 DW_apb_uart APB Universal Asynchronous Receiver Transmitter 0 000 5 47 DW_apb_wdt SPB Veer TA ee ie soe he oh eB eee eae eee dese 49 DW_axi Multiple Address Multiple Data AXI Interconnect 4 50 DW_axi_gm Generic Interface GIF to AMBA AXI Module 004 52 DW_axi_gs AMBA AAI Slave to Generic Interface GIF 25226cccaivsstdeesisa stead 33 DW_axi_hmx Connects AMBA AXI Slave to AHB Master 0 0 ee eee eee 54 DW_axi_rs AMBA AXI Register SCO scciacceaeibaeceadebakberei eaten eee bas ben xs 55 DW_axi_x2h ATGA B Bnd oh eb oho 4 be oS en eed eh bee ee seers E ee 56 DW_axi_x2p Connects AMBA AXI Slave to AHP Master 0 eee eeeee 57 DW_axi_x2x Connects AMBA AXI Master to AXI Slave 2c c cece cece ence 59 DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems 4 61 Re IY coteeeetiaete ken ee adeds uiwate ORAN beseaneseas 64 DW_memctl Memory nh 8 oS oa
26. depth allows external slave to reorder and or interleave read data up to this depth Configurable write interleaving depth 59 DesignWare IP Family DW_axi_x2x Connects AMBA AXI Master to AXI Slave DW_axi_x2x AXI Read Address Channel AXI Read Data Channel Master Slave Port Port AXI Write Address Channel AXI Write Data Channel AXI Write Response Channel Optional AXI Slave only with write interleaving fan out This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html Documentation for this product is available at http www synopsys com products designware docs 60 Synopsys Inc June 2009 DesignWare IP Family DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems DesignWare AMBA QuickStart is a collection of example designs for AMBA subsystems built with DesignWare AMBA On chip Bus synthesizable IP and verification IP components The QuickStart demonstrates the following e How the DesignWare AMBA components and peripherals synthesizable IP integrate together e How to initialize and program using C or Verilog BFM commands the synthesizable component blocks to perform basic operating functions e How the DesignWare AMBA verification models and synthesizable components work together e How to connec
27. designware docs AXI AXI AXI AXI Master Master Master Master E A v A APB K Slave APB Slave APB AXI AXI AXI to APB Slave Slave Bridge AMBA APB it v VY Vv Slave APB gt Synopsys Inc PRELIMINARY Slave APB lt YY v APB Monitor Slave January 2009 DesignWare IP Family Board Verification IP Simulation models for Board Verification Board Verification IP Simulation models for Board Verification The DesignWare Library contains over 18 500 simulation models for ASIC SoC and Board verification For a complete search visit http www synopsys com ipdirectory Component Group Component Reference VMT Models Refer to DesignWare Library Verification IP on page 74 FlexModels Refer to DesignWare FlexModels on page 96 DesignWare Memory Models Refer to Memory Models on page 85 SmartModel Library Refer to DesignWare SmartModels on page 98 June 2009 Synopsys Inc 81 g m S O o e gt Ea DesignWare IP Family Ethernet 10 100 1G 10G Models Transceiver and Monitor Ethernet 10 100 1G 10G Models Transceiver and Monitor Transceiver ethernet_txrx_vmt e Supports
28. e Standard MAC PHY interface for e Protocol Adaptation Layer PAL connection to external discrete PHYs based on Wireless USB from the or internal integrated PHYs USB IF e Asynchronous clock domains support e Adaptive Packet Processor APP different PHY frequencies This allows for post silicon upgrades to allows the use of a separate PHY clock firmware and protocol processing and and MAC clocks additional features sold separately Buffer Management Unit BMU e Device controller includes features for adding CWUSB to a PC peripheral e Flexible interface can be configured such as a printer or a portable CE for high performance and throughput device such as a camera 170 Synopsys Inc June 2009 DesignWare IP Family dwe_wiusb_ device_controller Wireless USB Device Controller AHB Master or Native DMA Interface AHB Slave Interface A A Buffer Management Interface Unit la AHB Slave Data AHB Master or Native DMA Bus FIFO lt gt P RAM Bus Control Unit ower p Packet FIFO Controller ii APP Code RAM 4 Wireless USB PAL APP Data RAM Adaptive RAM aS Packet Access gt MAC e Processor Control Scheduler Serial Flash BE i ia WiMedia MAC S Control N R C CCM e i Tx Ctl z rame Security Parser P CRC 32 lt o PHY Interface Unit PIU r yt
29. gt Interrupt Table Controller Optional 4 gt LU j _ SSS Address Data Output Block The dwcore_pcix datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_pci x pdf 134 Synopsys Inc June 2009 DesignWare IP Family PCle AHB Bridge PCI Express to AMBA 2 0 AHB Bridge PCle AHB Bridge PCI Express to AMBA 2 0 AHB Bridge The DesignWare PCI Express to AMBA 2 0 AHB Bridge PCle AHB Bridge enables designers who use the AMBA 2 0 AHB on chip bus to easily add PCI Express external connectivity to their AMBA 2 0 AHB bases System on Chip SoC devices Other features include the following June 2009 AHB Master and Slave interfaces for inbound and outbound PCI Express requests Supports full PCI Express configuration I O requests traffic class EP TD etc through PClIe AHB Bridge AHB Slave interface for PCI Express core CDM register access through the PCI Express core s DBI interface Programmable buffer sizes for AHB Master and Slave requests and response queuing Independent programmable clock rates for the PCI Express core and AHB subsystem Programmable maximum number of inbound and outbound read requests for AHB All burst sizes supported for both AHB Master and Slave interfaces Programmable burst lengths to support 4K read write burst over AHB Master and Slave interfaces More information is available at Independent maximum read request and transfer sizes between A
30. is achieved without additional system overhead The core configuration offers one click integration with the DesignWare IP SATA PHY removing the effort of integrating the digital and mixed signal portions of the SATA interface design Reduced gate count and very low power consumption is achieved by utilizing the set of highly configurable options which enable the core to optimized based on the exact design requirements The test environment for the digital device controller IP includes a number of the DesignWare Verification IP components offering SATA transactions generation SATA protocol monitoring and AMBA subsystem transaction generation Verilog based tests are provided as examples to accelerate system integration e Compliant SATA Device for any e Data scrambling application HDD ODD SSD e Speed negotiation when TX OOB e Supports 1 5 Gb sec 3 0 Gb sec and signaling is enabled 6 0 Gb sec speeds e Full Power Management Features e Compliant with SATA 2 6 Supported specification Draft 2 7 for 6Gb sec e Supports SATA defined BIST Modes e Internal DMA engine with flexible e Configurable AMBA System programming model Interface e Included Example Command Layer e Supports disabling of RX and TX firmware clocks during power modes e Optional RX Buffer elasticity buffer e Highly configurable PHY interface for recovered clock systems e Additional user defined PHY status e Optional 8B 10B encoding decoding and control ports Optional
31. least one pin name pin but others are optional pin2 pinN TopMenu gt SubMenu Pulldown menu paths such as File gt Save As Synopsys Common Licensing SCL You can find general Licensing SCL information on the Web at http www synopsys com Support Licensing 10 Synopsys Inc June 2009 DesignWare IP Family Preface Getting Help If you have a question about using Synopsys products please consult product documentation that is installed on your network or located at the root level of your Synopsys product CD ROM if available You can also access documentation for DesignWare products on the Web e Product documentation for many DesignWare products http www synopsys com dw dwlibdocs php e Datasheets for individual DesignWare IP components located using Search for IP http www synopsys com designware You can also contact the Synopsys Support Center in the following ways e Open a call to your local support center by clicking this link and then accessing Open a Support Case http www synopsys com Support e Support center contact information http www synopsys com Support GlobalSupportCenters Comments To report errors or make suggestions please send e mail to support_center synopsys com To report an error that occurs on a specific page select the entire page including headers and footers and copy to the buffer Then paste the buffer to the body of your
32. library for audio decoding and advanced sound enhancement algorithms e Dual Harvard architecture e Full 24 bit data paths June 2009 Synopsys Inc Two 24 x 24 bit signed multipliers Three ALUs Four 56 bit accumulators Extensive addressing modes with modulo protection bit reversal Saturation and rounding units RISC instruction set suitable for control as well as DSP Highly efficient stack support e Zero overhead loops nested up to 4 levels 64 Kwords address space each for P X Y IO DMA ports for program and data memories e Three maskable low latency interrupts Extensive power management support stop restart instructions JTAG based Joint Test Action Group IEEE 1149 1 std test interface debug port 179 DesignWare IP Family DW_CoolFlux IE fp CoolFlux 24 bit DSP Core from NXP Program X Data Y Data Memory Memory Memory 32 16 A24 16 A24 16 LA Program X Address Y Address Control Generation Generation Operand Registers X Y Multiplier X ALU 0 Multiplier Y ALU X ALU Y Accumulator Registers A B Rounding Saturation Data Computation SS SS Ee Se 7 Interrupts JTAG DMA O Also see the following web page for additional information http www synopsys com IP Design Ware StarIP Pages CoolFlux aspx 180 Synopsys Inc June 20
33. mechanism for host to hub communication Hub specific status and control commands permit the host to configure a hub and to monitor and control its individual downstream ports Other features include the following e Silicon proven e Downstream device connect e USB 1 1 compliant disconnect detection e Verilog source code e Supports suspend resume for power e Supports low speed and full speed en a devices on downstream ports e Supports one interrupt endpoint in e Integrated DPLL for clock and data paca fo endpoint 0 recovery e Approximately 12K gates for four ports 158 Synopsys Inc June 2009 DesignWare IP Family as dwc_usb_1_1_hub native S Synthesizable USB 1 1 Hub Controller a ie Transceiver A UHO1 Hub Root Port Frame Timer gt Hub Controller v Hub Functional State il Machine Hub Repeater Bowarand Hub Command Overcurrent Interpreter A Control Port State Port State Port State Port State Machine Machine Machine Machine Downstream Downstream Downstream Downstream Port 1 Port 2 Port 3 Port 4 Transceiver Transceiver Transceiver Transceiver m m m m op N ip ip 5 010 MA The dwcore_usb1_hub datasheet is available at http www synopsys com cgi bin dwcores pdfrl cgi file dwc_usb_1_1_hub native pdf June 2009 Syno
34. site http www synopsys com designware 128 Synopsys Inc June 2009 K dwc_jpeg Synthesizable JPEG CODEC DesignWare IP Family dwc_jpeg Synthesizable JPEG CODEC The Synopsys DesignWare JPEG CODEC is part of an SoC based multimedia solution that enables fast and simple image compression and decompression The simplicity of the design allows for easy SoC integration high speed operation and suitability for multimedia and color printing applications Individual Encoder and Decoder products are available from Synopsys Other JPEG CODEC features include the following 100 baseline ISO IEC 10918 1 JPEG compliant Verified in hardware e 8 bit channel pixel depths June 2009 Up to four programmable quantization tables Single clock Huffman coding and decoding Fully programmable Huffman tables two AC and two DC Fully programmable Minimum Coded Unit MCU Encoding decoding support non simultaneous Single clock per pixel encoding and decoding according to the JPEG baseline algorithm Hardware support for restart marker insertion Synopsys Inc Support for single grayscale components Support for up to four channels of component color Internal register interface Fully synchronous design Available as fully functional and synthesizable VHDL or Verilog Includes testbench Simple external interface Four channel interface Low gate count total gate count is 35K gates Stallable design
35. supported by all Synopsys simulators and by all other major simulator vendors Smarter verification is achieved by using the models debugging utilities You can search through the thousands of memory models using the memory model search capabilities offered as part of DesignWare Memory Central at http www synopsys com memorycentral DesignWare Memory Models provide the following capabilities e The DesignWare Memory Models all have built in memory debug utilities The debug utilities can be controlled from a VHDL Verilog OpenVera or SystemC testbench The verification engineer has access to memory load dump peek poke and trace commands g m S O o e gt 5 e Debugging the memory model content interactively during run time simulation reduces the effort required to debug memory subsystems The DesignWare MemScope allows users to view and modify all the memory model data as well as monitoring the transaction types taking place on the selected models The MemScope connects directly to the DesignWare Memory Model technology core and not through the simulator This results in no simulation performance degradation even with the MemScope connected e The memory transaction history can be viewed dynamically during simulation or in a post processing fashion The address and data fields can be searched to locate selected values quickly e The memory model content can be viewed or modified dynamically during the simul
36. to maximize bus utilization e Automatic scheduling of activate and precharge commands e Automatic scheduling of refreshes e Configurable multi port arbiter supporting multiple independent user ports June 2009 e Configurable quality of service capability per user port e Programmable ECC generation checking and correction e Supports ARM AMBA AXI amp AHB protocols e Real time DQS drift detection and compensation PHY IP e Configurable PHY easily goes around die corner o PHY compiler available o Lane based PHY architecture for maximum flexibility e Precision master slave DLLs provide 90 phases of the clock strobes o Automatic calibration o Immune to voltage and temperature drift o Ultra low jitter e Per bit timing adjustment on data and strobe signals to improve timing margin e Data training for DQS gating Synopsys Inc 127 010 MA DesignWare IP Family DDR2 DDR SDRAM PHY and Controller DDR2 DDR SDRAM Complete Solution Verification IP e Verifies complete memory system with verification IP of physical memories memory models and on chip interfaces AXI and OCP e Provides directed and constrained random traffic generation e Supports major simulators and testbench languages including Verilog System Verilog OpenVera and VHDL Verification Environment AMBA 2 AMBA 3 AXI Memory Controller Digital Core The product datasheet can be downloaded from the following
37. transfers on all 5 channels passes to primary secondary AXI bus o Configurable buffer depths for all 5 channels to allow off loading of payload source bus to sink bus o Support for asynchronous clocks on Slave Port and Master Port sides o Optimizations for quasi synchronous clocking of any integer ratio e Address Channel Features o Address width configurable to any value in range 32 64 on both Slave and Master Ports o Changes attributes for transactions that cannot fit on the secondary bus o For upsizing increases SIZE of transaction and decreases length to generate transaction of SIZE equal to maximum on secondary bus o Configures which channels exist write only read and write allows for use in purely write interleaving fan out mode oO Supports burst lengths of up to 256 June 2009 Synopsys Inc 512 bits wide Master Port and Slave Port data widths can be configured to different widths Transfer unpacking done to translate larger Master Port data width to smaller Slave Port data width on return from Slave Port to Master Port transfers packed to match size of original transaction from primary bus g m Q lt S gt D o N D 7 D Can upsize transactions that is pack data from primary into shorter transaction of larger SIZE on secondary AXI little and big endian Byte Ordering byte invariant is individually configurable for each interface Configurable read interleaving
38. transmit and receive operations Cycle master and node controller capability Automatic isochronous resource manager detection Synopsys Inc Automatic acknowledge packet generation for received asynchronous packets Automatic 32 bit CRC generation and error detection interface Flexible 32 bit Virtual Component Interface VCI for host Asynchronous and isochronous FIFO interface with burst and non burst access modes Multi speed concatenated isochronous packet support Configurable number of isochronous transmit receive channels Status reporting by extensive maskable interrupt register set Supports inbound and outbound single phase retry protocol RapidScript custom IP configuration e Verilog source code Optional 1394 verification environment 121 010 MA DesignWare IP Family l Co dwc_1394_av_link Ne Qs Synthesizable IEEE 1394 AVLink DTCP AV1394Link Isochronous TX VCIF Link Layer Core TX_AV IBUF s gt ITX VCF TX_IIP gt Isochronous ITF TX RX VCIF RX_IIP 4 gt RX VCIF lt IRF e RX_AV e RET CRC Asynchronous PHY TX VCIF ABUF i an ATX_VCIF i gt Cyc IF eae m Monitor Asynchronous aed gt RX VCIF gt 4 gt ARX_VCIF ATX_Res 4 RX Host ARX VCIF A lt HOST _VCIF e gt V
39. 09 DesignWare IP Family S l Ib DW_CoolFlux CoolFlux 24 bit DSP Core from NXP June 2009 Synopsys Inc 181 DesignWare IP Family DWC_n2p Nios Il Processor Core DWC_n2p Nios Il Processor Core The Designware Nios II Processor from Synopsys also referred to as DWC_n 2p in this document is an ASIC implementation of Altera s popular Nios II configurable general purpose 32 bit RISC processor DWC_n2 2p is a single module that contains an embedded Nios II Processor and additional logic for system level debug through a JTAG interface Users can specify configuration parameters to optimize the DWC_n2p hardware to match their system requirements Features Full 32 bit Instruction Set Thirty two 32 bit general purpose registers Four external interrupt sources Combined instruction and data system port Von Neumann Architecture Support for a single optional Instruction Tightly Coupled Memory e Support for up to 4 optional Data Tightly Coupled Memories e Exported interface for Cache TCM memories Optional exported interface for data cache memories data cache can be omitted e Dynamic branch prediction minimizes taken branch penalty 6 stage pipelines to achieve maximum DMIPS MHz 500 DMIPS Performance e Single instruction barrel shifter e Single instruction 32 x 32 multiply producing a 32 bit result Single instruction 32 x 32 divide producing a 32 bit result Embedded hardware assist
40. 0GHP Purpose G Low VT with Multi VDD support TCBNOOGHPLVT High VT with Multi VDD support TCBN90GHPHVT Nominal VT with MTCMOS support TCBN90GHPCG Low VT with MTCMOS support TCBN90GHPCGLVT High VT with MTCMOS support TCBN9O0GHPCGHVT Nominal VT with Back Bias support TCBN90GHPWB Low VT with Back Bias support TCBN9OGHPLVTWB High VT with Back Bias support TCBN9O0GHPHVTWB Overdrive Nominal VT TCBN90GHPOD Overdrive Low VT TCBN90GHPODLVT Overdrive High VT TCBN9O0GHPODHVT High Nominal VT TCBN90GTHP ao Low VT TCBNOOGTHPLVT High VT TCBN90GTHPHVT Low Power LP Nominal VT with Multi VDD support TCBN90LPHP Low VT with Multi VDD support TCBN90LPHPLVT High VT with Multi VDD support TCBN9OLPHPHVT Ultra High VT TCBN9OLPHPUHVT Nominal VT with Back Bias support TCBN90LPHPWB Low VT with Back Bias support TCBN9OLPHPLVTWB High VT with Back Bias support TCBN9O0LPHPHVTWB Nominal VT with MTCMOS support TCBN9O0LPHPCG Low VT with MTCMOS support TCBN9OLPHPLVTCG High VT with MTCMOS support TCBN9OLPHPHVTCG June 2009 Synopsys Inc 103 z T ie c gt Q lt E o o p o Chapter 3 DesignWare Foundry Libraries DesignWare IP Family Table 2 TSMC Standard Cell Categories Continued Tech Process Feature Library Name 130nm_ General Purpose Nominal VT TCBO13GHP Low VT TCBO13GHPLVT High VT TCBO13GHPHVT Low Voltage Nominal VT TCBO13LVHP High VT TCBO13LVHPHVT Ove
41. 129 010 MA DesignWare IP Family dec Co dwc_jpeg Qs Synthesizable JPEG CODEC DCTRam ZigRam0O ZigRam1 QMem HuffEnc ft pixout l hopi TH dct zigzag Dy quant ip code eng m gt unstuff DS store addr gt decode H regctrl a din dout gt 4 4 JPEG CODEC HuffMin HuffBase HuffSymb The dwcore_jpeg_codec datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_jpeg pdf Synopsys Inc June 2009 130 DesignWare IP Family C Og dwc_pci S Universal PCI Controller dwc_pci Universal PCI Controller The DesignWare IP core for PCI is available as synthesizable RTL source code and provides an interface between the application and the PCI bus Some of the key features include the following June 2009 e PCI specification 2 3 compliant e 15 application optimized PCI IP available in Verilog e Silicon proven 33 MHz and 66 MHz performance e 32 bit or 64 bit PCI bus path e 32 bit or 64 bit application data path e Zero Latency Fast Back to Back transfers e Zero Wait State Burst Mode transfers Synopsys Inc Support for Memory Read Line Multiple and Memory Write and Invalidate commands Dual Add
42. A Bus Fabric and Peripheral IP AMBA AXI Bus Fabric and Peripheral IP Chapter 2 Describes the available DesignWare Library DesignWare Library Verification IP verification models Chapter 3 This chapter briefly describes the DesignWare Foundry Libraries DesignWare Foundry Libraries June 2009 Synopsys Inc 9 Preface DesignWare IP Family Chapter 4 Contains a brief description of each DesignWare Cores Digital and Mixed DesignWare Core Signal IP Chapter 5 Contains a brief description of each DesignWare Star IP DesignWare Star IP core Typographical and Symbol Conventions Table 1 lists the conventions that are used throughout this document Table 1 Documentation Conventions Convention Description and Example Represents the UNIX prompt Bold User input text entered by the user cd LMC HOME hd1 Monospace System generated text prompts messages files reports No Mismatches 66 Vectors processed 66 Possible Italic or Italic Variables for which you supply a specific value As a command line example setenv LMC HOME prod dir In body text In the previous example prod_dir is the directory where your product must be installed Vertical rule Choice among alternatives as in the following syntax example effort_level low medium high Square brackets Enclose optional parameters pinli pin2 pinwN In this example you must enter at
43. B Slave page 76 apb_master_vmt apb_monitor_vmt apb_slave_vmt DesignWare VIP for AMBA 2 0 APB Models APB Master APB Monitor and APB Slave page 78 Verification Models axi_master_vmt axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt DesignWare VIP for AMBA 3 AXI page 79 Verification Model ethernet_txrx_vmt ethernet_monitor_vmt 10 100 1G 10G Gigabit Ethernet Models page 82 Verification Models enethub_fx rmiirs_fx i2c_txrx_vmt 20 Ethernet RMI Transceiver and Hub page 83 PC Bi Directional Two Wire Bus page 84 Synopsys Inc Verification Models Verification Model June 2009 DesignWare IP Family Chapter 1 Overview pcie_txrx_vmt pcie_monitor_vmt pcimaster_fx pcislave_fx pcimonitor_fx PCI Express 1 00a page 88 PCI PCI X Simulation Model and Test Suite page 90 Verification Model Verification Models usb_host_vmt usb_device_vmt usb_monitor_vmt USB On The Go Models 1 1 2 0 OTG UTMI and UTMI page 95 Verification Model sio_txrxvmt sio_monitor_vmt Serial Input Output Interface Models page 94 DesignWare Design Views of Star IP Cores Verification Models DW_IBM460 S DW_IBM405 S PowerPC 440 Microprocessor Cores from IBM page 177 Verification Model DW_CoolFlux CoolFlux 24 bit DSP Core from Philips page 179 Verification Model DWC_n2p DesignWare Memory Nios II Pro
44. BI TBI SGMII AXI AHB Slave Interface GMAC CORE The dwc_ethernet_mac10_100_1G_universal datasheet is available at http www synopsys com cgi bin dwcores pdfrl cgi file dwce_ether_mac10_100_1000_universal pdf 114 Synopsys Inc June 2009 DesignWare IP Family dwc_ether_xgmac XGMAC 10G Ethernet MAC dwc_ether_xgmac XGMAC 10G Ethernet MAC The DesignWare XGMAC core is specifically designed for easy integration with 1G 2 5G 10G Ethernet host applications The XGMAC core has a simple FIFO interface on the transmit and receive sides for transferring data to the application The generic interface provides simple controls for the data transfer and extraction of FIFO status information This enables the host application to access the XGMAC s control and status registers CSRs thus giving the host CPU easy access to the native 32 bit read write bus The XGMAC subsystem provides a 10 Gigabit Media Independent Interface XGMII an IEEE 802 3ae compliant reconciliation sub layer for communication with the 10 Gigabit PHY The XGMAC IP also provides a Management Data Input Output MDIO interface capable of addressing MDIO devices that comply with Clause 45 of the IEEE 802 3ae standard and Clause 22 of the 802 3 2005 standards Features IEEE 802 3ae XGMII TEEE 802 3ae 31 bit flow control IEEE 802 3 2005 Clause 35 GMI Interface IEEE 802 3x Flow Control for full duplex operation IEEE 802 1Q VLAN receive tag detection
45. HB and PCI Express transfers can be split into multiple transfers Response AHB Slave request gathering from split PCI Express completions Response AHB Master request gathering from multiple AHB responses Out of order transactions for transactions with unique Master IDs Interrupt and Message handling Response error mapping between PCI Express errors UR CA CRS poisoned and ECRC error and AHB Slave response errors Response error mapping between PCI Express errors UR CA CRS poisoned and ECRC error and AHB Master response error PCle AHB Bridge handles completion time outs http www synopsys com products designware pciexpress html Synopsys Inc 135 010 MA DesignWare IP Family PCle AXI Bridge PCI Express to AMBA 3 AXI Bridge PCle AXI Bridge PCI Express to AMBA 3 AXI Bridge The DesignWare PCI Express to AMBA 3 AXI Bridge PCle AXI Bridge enables designers who use the AMBA 3 AXI on chip bus to easily add PCI Express external connectivity to their AMBA 3 AXI bases System on Chip SoC devices Other features include the following 136 AXI Master and slave interfaces for inbound and outbound PCI Express requests Supports full PCI Express configuration I O requests traffic class EP TD etc through PClIe AXI Bridge AXI Slave interface for PCI Express core CDM register access through the PCI Express core s DBI interface Independent configuration of bus width for PCI Express core dat
46. I Synchronization e IEEE 802 3z compliant TBI RTBI e Complies with the full IEEE with auto negotiation support 802 3 2002 specification e Supports SGMII e Supports IEEE 802 1Q VLAN tag e Supports Serial MII SMII detection for reception frames P e MDIO Master interface optional for PHY device configuration and management e Configurable to support the following data transfer rates o 10 100 or 1000 Mbps o 10 or 100 Mpbs only o 1000 Mbps only e Supports CSMA CD protocol for Application Interface Features e The following application interfaces half duplex operation are configurable e Supports Full Duplex Only GMAC only with native interface configuration GMAC with MTL native interface e Supports packet bursting and frame DMA with native interface extension in 1000 Mbps Half Duplex DMA with AHB interface mode DMA with AXI interface g e Supports IEEE 802 3x flow control for e Data interface configurable to support a full duplex operation ess AHB interfaces e Supports a variety of flexible address e CSR interface configurable to AHB filtering modes Slave or APB Slave 32 bit interface e Complete network statistics optional e Supports 32 64 or 128 bit data on with RMON MIB counters the AHB Master port RFC2819 RFC2665 June 2009 Synopsys Inc 113 DesignWare IP Family dwc_ether_mac10_ 100 1000 universal Ethernet MAC 10 100 1000 Universal Core Optional PHY Interfaces RGMII RT
47. L layer page 117 dwc_xaui_phy XAUI PHY page 174 Hard IP Mobile Storage Core dwc_mobile_storage Secure Digital SD Multimedia Card Synthesizable RTL MMC and CE ATA page 119 DDRn SDRAM Core DDR2 3 Lite SDRAM High performance DDR2 3 SDRAM Synthesizable RTL Complete Solution interfaces up to 1066 Mbps page 125 and Hard IP 108 Synopsys Inc June 2009 DesignWare IP Family Chapter 4 DesignWare Cores Digital and Mixed Signal IP DDR2 DDR SDRAM PHY DDR2 DDR SDRAM Complete Solution Synthesizable RTL and Controller page 127 and Hard IP IEEE 1394 Cores dwc_1394_av_link TEEE 1394 AVLink page 121 Synthesizable RTL dwce_1394_cphy native IEEE 1394 Cable PHY page 123 Synthesizable RTL JPEG Core dwc_jpeg JPEG CODEC page 129 Synthesizable RTL PCI Cores dwce_pci 32 64 bit 33 66 MHz PCI Core page 131 Synthesizable RTL dwce_pci x 32 64 bit 133 MHz PCI X Core Synthesizable RTL page 133 PCI Express Cores dwc_pci_express_ep PCI Express Endpoint Core page 138 Synthesizable RTL dwc_pci_express_rc PCI Express Root Port Core page 140 Synthesizable RTL dwc_pci_express_sw PCI Express Switch Port Core page 142 Synthesizable RTL dwc_pci_express_dm PCI Express Dual Mode Core page 144 Synthesizable RTL dwcore_pcie_phy PCI Express PHY Core page 146 Hard IP SATA Cores dwc_sata_ahci SATA AHCI page 148 Synthesizable RTL DWC_dsata SATA Devi
48. O13N3 Low Voltage 1 0V HVT 2 5V 3 3V tol Staggered TPZO13LG2 1 0V OD 2 5V 3 3V tol Staggered TPZ013LODG2 1 0V HVT 3 3V 5V tol Staggered TPZO13LGV3 Universal 1 0V OD 3 3V 5V tol Staggered TPZO13LODGV3 Universal All All Staggered TPBO13GV Universal Pads Low Power 1 5V 2 5V Linear TPDO13LPN2 3 3V Linear TPDO13LPN3 150nm General Purpose 1 5V 3 3V 5V tol Staggered TPZO15G Low Voltage 1 2V 3 3V 5V tol Staggered TPZOISLG June 2009 Synopsys Inc 101 z T e c gt a x lt o o p 7 Chapter 3 DesignWare Foundry Libraries DesignWare IP Family Table 2 TSMC Standard Cell Categories Tech Process Feature Library Name 65nm G Plus Nominal VT TCBN65GPLUS Low VT TCBN65GPLUSLVT High VT TCBN65GPLUSHVT Nominal VT with MTCMOS support TCBN65GPLUSCG Low VT with MTCMOS support TCBN65GPLUSCGLVT High VT with MTCMOS support TCBN65GPLUSCGHVT Low Power LP Nominal VT TCBN65LP Low VT TCBNO6SLPLVT High VT TCBN65LPHVT Nominal VT with MTCMOS support TCBN65LPCG Low VT with MTCMOS support TCBN65LPLVTCG High VT with MTCMOS support TCBN65LPHVTCG 102 Synopsys Inc June 2009 DesignWare IP Family Chapter 3 DesignWare Foundry Libraries Table 2 TSMC Standard Cell Categories Continued Tech Process Feature Library Name 90nm General Nominal VT with Multi VDD support TCBN9
49. OOB detection generation e Validated against Synopsys and other logic PHYs 150 Synopsys Inc June 2009 DesignWare IP Family Oh 5 DWC_dsata SATA Device Interface DWC_dsata PHY Interface AHB Slave Bus Interface Device Bus DWC_dsata Rx Clock ster Port DS RxFIFO Port DMA FIFO BIU Master PHY Transport PDMA Bus I F Link Layer Interface Layer Unit TxFIFO Port Registers PCSR BIU Slave Port Power Control Module The DesignWare DWC_dsata datasheet is available at http www synopsys com products designware docs ds c dwc_sata_csds pdf 010 MA June 2009 Synopsys Inc 151 DesignWare IP Family dwc_sata_phy Serial ATA PHY IP dwc_sata_phy Serial ATA PHY IP The DesignWare SATA PHY IP integrates high speed mixed signal custom CMOS circuitry for easy integration into SoC designs The high margin robust SATA PHY architecture tolerates manufacturing variations such as process voltage and temperature The DesignWare SATA PHY integrates seamlessly with the DesignWare SATA Host core to help reduce design time and achieve first pass silicon success While extremely low in power consumption and area the SATA PHY is compliant with the SATA 2 6 specification and substantially exceeds its electrical specifications in key performance areas such as jit
50. SYNOPSYS DesignWare IP Family Reference Guide DesignWare IP Family Copyright Notice and Proprietary Information Copyright 2009 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys AMPS Cadabra CATS CRITIC CSim Design Compiler DesignPower DesignWare EPIC Formality HSIM HSPICE iN Phase in Sync Le
51. Scirocco i Shadow Debugger Silicon Blueprint Silicon Early Access SinglePass SoC Smart Extraction SmartLicense Softwire Source Level Design Star RCXT Star SimXT Taurus TimeSlice TimeTracker Timing Annotator TopoPlace TopoRoute Trace On Demand True Hspice TSUPREM 4 TymeWare VCS Express VCSi Verification Portal VFormal VHDL Compiler VHDL System Simulator VirSim and VMC are trademarks of Synopsys Inc Service Marks s MAP in SVP Caf and TAP in are service marks of Synopsys Inc SystemC is a trademark of the Open SystemC Initiative and is used under license ARM and AMBA are registered trademarks of ARM Limited Saber is a registered trademark of SabreMark Limited Partnership and is used under license PCI Express is a trademark of PCI SIG All other product or company names may be trademarks of their respective owners Synopsys Inc 700 E Middlefield Road Mountain View CA 94043 www synopsys com 2 Synopsys Inc June 2009 DesignWare IP Family Contents PRA 6664 KEES ROK RAEAS AEE ALE SARS CAMREAARR NADER ERS Abont This Manyal cc tesl genet eet ee boieeeeus booed eb seeds Manual OOVETVIEW cacckegeccetsosseeeeeaeu teen eee oe sees Typographical and Symbol Conventions Synopsys Common Licensing SCL 200 220 Creme IGS 45 4 955 Ka ew os HGS 09S ee ee Additonal IG oes ce iee bien teees oesseeeeuet 2 COMMENT icdiencrkbadivad bendensscheotesesauoises saeeds Chapte
52. Serial ATA Models page 92 Verification sata_monitor_vmt sio_txrx_vmt Serial Input Output Interface Models page 94 Verification sio_monitor_vmt usb_host_vmt USB On The Go Models 1 1 2 0 OTG UTMI and Verification June 2009 Synopsys Inc 19 Chapter 1 Overview DesignWare IP Family Board Verification IP The DesignWare Library contains over 18 500 simulation models for ASIC SoC and Board verification For a complete search visit http www synopsys com ipdirectory Component Group Component Reference VMT Models Refer to DesignWare Library Verification IP on page 74 FlexModels Refer to DesignWare FlexModels on page 96 DesignWare Memory Models Refer to Memory Models on page 85 SmartModel Library Refer to DesignWare SmartModels on page 98 VCS Verification Library The VCS Verification Library contains a broad portfolio of verification IP for the industry s most popular bus protocols including AMBA 3 AXI AMBA 2 0 PCI Express USB 2 0 OTG Ethernet Serial ATA and thousands of memory models The following table identifies the various components that make up this library ahb_master_vmt ahb_monitor_vmt ahb_slave_vmt Component Name Component Description Component Type DesignWare Bus amp I O Standards ahb_bus_vmt DesignWare VIP for AMBA 2 0 AHB Models Verification Models AHB Bus Interconnect AHB Master AHB Monitor and AH
53. Technologies MIPS Technologies NEC and Philips June 2009 Synopsys Inc 13 Chapter 1 Overview DesignWare IP Family DesignWare Library The DesignWare Library provides designers with a comprehensive collection of synthesizable IP verification IP and foundry libraries The library contains the following principal ingredients for ASIC SoC and FPGA design and verification e Building Block IP Datapath Data Integrity DSP Test and more e AMBA Bus Fabric Peripherals and Verification IP e Memory portfolio memory controller memory BIST memory models and more e Verification models of popular bus and I O Standards PCI Express PCI X PCI USB On the Go and more e Microprocessor and DSP cores from industry leading Star IP providers e Foundry Libraries e Board verification IP e Microcontrollers 8051 and 6811 A single license gives you access to all the IP in the library For more information on the DesignWare Library refer to the following http www synopsys com products designware dwlibrary html For a detailed search of the available IP refer to the following http www synopsys com products designware 14 Synopsys Inc June 2009 DesignWare IP Family Building Block IP The DesignWare Building Block IP is a collection of over 200 technology independent high quality high performance IP Most of these IP elements include multiple implementations to provide a variety of performance and area tradeoff opti
54. VCS NTB and Verification e Interfaces for 10 100 1G and 10G Methodology Manual VMM for XGMI XAUI MII GMII SMI System Verilog and OpenVera RVM SGMII QSGMII RMIT RGMII 1000BASE KX 1OGBASE KR and Monitor ethernet_monitor_vmt 10GBASE KX4 TBI RTBI e Protocol checking for supported frame e Half and full duplex MAC operation types and errors e Multiple frame types MAC VLAN e Transaction logging for frames fault tagged control and jumbo messaging and cycle level bus activity e Auto Negotiation for SGMII and TBI Configurable to match TxRx model e User defined frame content e Watchpoint monitoring e Flow control with Pause frames e Cumulative simulation coverage e Adjusts IPG for effective data rate e Dynamic start stop e Frame error generation and recognition Command set control e Code error generation injection e Supports VCS NTB e Link fault support e Supports Verification Methodology e IEEE 1588 Precision Clock Manual VMM for SystemVerilog and e IEEE 802 3ap Backplane Ethernet OpenVera RVM Ethernet VIP a 1 ca 2 Tx Rx direction Port 1 _ Port Rx ee Pori Tx Port 2 a Port Rx m Pori Tx Port 16 Port Rx Port Tx The DesignWare Ethernet Verification IP documentation is available at http www synopsys com dw doc php vip ethernet latest doc ethernet__overview pdf 82 Synopsys Inc June 2009 DesignWare IP Family Ethernet Models RMII Trans
55. W_ahb Parameterizable Master Signals Arbiter Master 1 lt gt Master 2 Address and control MUX Write data MUX Master i Read data MUX i upto15 Decoder internal lt gt Slave 1 lt Slave 2 Slavej The DesignWare DW_ahb Databook is available at http www synopsys com products designware docs 28 Synopsys Inc Parameterizable Slave Signals j upto15 June 2009 DW_ahb_ dmac DesignWare IP Family DW_ahb_dmac AHB Central Direct Memory Access DMA Controller AHB Central Direct Memory Access DMA Controller e AHB slave interface used to program the DW_ahb_dmac e AHB master interface s o Up to four independent AHB master interfaces that allows e Upto four simultaneous DMA transfers e Masters that can be on different AMBA layers multi layer support e Source and destination that can be on different AMBA layers pseudo fly by performance o Configurable data bus width up to 256 bits for each AHB master interface o Configurable endianness for master interfaces e Configurable identification register e Encoded parameters DMA Hardware Request I F Master I F e Channels o Up to eight channels one per source and destination pair o Unidirectional channels data transfers in one direction only o Programmable channel priority g m Q S gt D o N D 7 D E
56. X FIFOs Block 2s PS Clock ea Generation le This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_i2s Databook is available at http www synopsys com products designware docs 40 Synopsys Inc June 2009 DesignWare IP Family DW_apb_ictl APB Interrupt Controller DW_apb _ictl APB Interrupt Controller e 2 to 64 IRQ normal interrupt sources e Priority filtering optional g e to 8 FIQ fast interrupt sources e Masking optional e Scan mode optional e Vectored interrupts optional e Programmable interrupt priorities D e Software interrupts after configuration X p T Note 3 DW_apb_ictl is an exact replacement for the original component DW_amba_ictl name change only DW_apb_ictl IRQ Generation Interrupt FIQ Registers Generation Vector Generation amp Masking This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_ictl Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 41 DesignWare IP Family DW_apb_rap APB Remap and Pause DW_apb_rap APB Remap and Pause e Configuration of APB data bus width 8 16 or 32 e Remap Control Used to switch the DW_ahb addr
57. Y Hard IP page 168 dwc_wiusb_device_controller Wireless USB Device Controller Synthesizable RTL page 170 dwc_usb2_nanophy USB 2 0 nanoPHY page 172 Hard IP XAUI dwc_xaui_phy XAUI PHY page 174 Hard IP Also visit the DesignWare Cores web page at http www synopsys com products designware dwcores html June 2009 Synopsys Inc 23 Chapter 1 Overview DesignWare IP Family DesignWare Star IP Synopsys offers DesignWare Library users the ability to evaluate and design easily at their desktop using the following high performance high value IP cores from leading Star IP providers Component Name Component Description Component Type DW_IBM460 S PowerPC 440 Microprocessor Core from Synthesizable RTL DW_CoolFlux CoolFlux 24 bit DSP Core from NXP Synthesizable RTL page 179 Simulation Model DWC_n2p Nios I Processor Core page 182 Synthesizable RTL Simulation Model a Simulation models of these cores are included in the DesignWare Library and DesignWare Verification Library Synthesizable RTL of these cores are available through the Star IP Program Also visit the DesignWare Star IP web page at http www synopsys com products designware star_ip html 24 Synopsys Inc June 2009 DesignWare IP Family 1 AMBA Bus Fabric and Peripheral IP g m Q lt S gt D b N D 7 D 5 AMBA is a standard bus architecture system developed by ARM for rapid development of processor d
58. a bus AXI master bus and AXI slave bus Programmable buffer sizes for AXI master and slave requests and response queuing Independent programmable clock rates for the PCI Express core the AXI master bus the AXI slave bus and the AXI slave DBI bus Programmable AXI master and slave address widths data bus widths and ID bus widths Programmable maximum number of inbound and outbound read requests for AXI All burst sizes supported for both AXI master and slave interfaces Programmable burst lengths to support 4K read write burst over AXI master and slave interfaces Synopsys Inc Supports unaligned AXI transfers using WSTRB and RTSRB for both AXI master and slave interfaces Supports independent maximum read request and transfer sizes between AXI and PCI Express transfers can be split into multiple transfers Supports response AXI slave request gathering from split PCI Express completions Supports response AXI master request gathering from multiple AXI responses Supports out of order transactions for transactions with unique IDs Supports Interrupt and Message handling Supports response error mapping between PCI Express errors UR CA CRS poisoned and ECRC error and AXI slave response errors SLVERR and DECERR Supports response error mapping between PCI Express errors UR CA CRS poisoned and ECRC error and AXI master response error DECERR_W and DECERR_R Support for byte parity check for th
59. ansition to DDR3 IP should the equivalent DDR3 products become less expensive This transition from DDR2 to DDR3 can be implemented if the DRAMs used by the system are 512Mb devices or larger 1 Gb is the recommended minimum for the ultimate long term security of supply because DDR3 devices are only offered in this range In situations where the DDR3 based design requires performance levels of over 1066 Mbps the DesignWare DDR3 2 IP product should be considered Optimized for low area and power the DesignWare DDR2 3 Lite SDRAM IP complete solution includes configurable digital controller IP an integrated hard macro PHY and verification IP VIP The high quality silicon proven DDR2 3 Lite IP enables designers to focus on product differentiation and not on the memory subsystem design issues that are present as data rates exceed 400 Mbps thus significantly reducing design integration risk and accelerating overall development time As part of the Lite DDR3 mandate for this product the DDR3 write leveling feature is not implemented and thus this interface solution is not recommended for those applications that require an interface to DDR3 DIMMs Verification Environment AMBA 2 AMBA 3 AXI Memory Controller Digital Core Memory Models June 2009 Synopsys Inc 125 010 MA DesignWare IP Family DDR2 3 Lite SDRAM Complete Solution DDR2 3 Lite SDRAM Complete Solution Highlights Solution Complete DDR2 3 SDRAM Memo
60. ass Through e Sideband signaling support g o Forward Registered e eau eats ene cre panies H o Fully Registered k ata width ID width and burst N o Backward Registered o e Same clock domain for attached master 5 e Configurable timing mode option on a per and slave channel basis The timing mode option selected for a channel is independent of the option selected for the other AXI channels e Adds one cycle of latency on registered paths AXI Master AXI Slave Read Address Read Address Channel Channel Write Address Write Address Channel Channel Write Data Channel Read Data Channel Write Data Channel Read Data Channel AXI Master Port AXI Slave Port Write Response Write Response Channel Channel This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html Documentation for this product is available at http www synopsys com products designware docs June 2009 Synopsys Inc 55 DesignWare IP Family DW_axi_x2h AXI to AHB Bridge DW_axi_x2h AXI to AHB Bridge e Bridge from AXI to AHB bus e All transactions passed through allowing for easy integration of legacy AHB designs with newer AXI designs e Configurable AXI Slave interface Configurable AHB Master interface includes AHB Lite support AMBA AXI and AMBA 2 0 AHB industry standard DesignWare FIFOs Supports transfer d
61. ation The data contents can be saved to a file for use as a pre load file in subsequent simulations The Memory Model documentation is available at http www synopsys com products designware docs June 2009 Synopsys Inc 85 DesignWare IP Family Open Core Protocol OCP Models Master Slave and Monitor Open Core Protocol OCP Models Master Slave and Monitor 86 All Models e Full range of OCP configurations e Multi threading and bursts e Configure as core or system e Example VMM testbench with predefined test sequences and scenario generators to provide functional coverage of OCP 2 0 2 1 or 2 2 e Randomized stimulus generation and configuration e Generates logs and reports to observe OCP transactions e Multiple testbench language support SystemVerilog Verilog VHDL e Supports all major simulators e Supports Native Testbench NTB in VCS and VCS MX e Supports Verification Methodology Manual VMM for System Verilog testbenches e Includes a utility to create OCP trace files for postprocessing OCP Master Model ocp_master_svt e Initiates OCP dataflow transactions e Initiates and responds to activity on sideband signals e Can be set up as an OCP core or system master Synopsys Inc OCP Slave Model ocp_slave_svt e Automatically manages responses to dataflow transactions e Slave s response can be generated randomly or supplied from the testbench e May initiate and respond to ac
62. axi 50 DW_axi_gm 52 June 2009 Index DW_axi_gs 53 DW_axi_hmx 54 DW_axi_rs 55 DW_axi_x2h 56 DW_axi_x2p 57 DW_axi_x2x 59 DW_CoolFlux 179 DW_hsata 148 150 DW_IBM440 177 DW_memectl 65 DW_rambist 67 DW8051 72 dwc_1394_av_link 121 dwc_1394_cphy native 123 dwe_ddr2 tsmc_130g_33 125 127 dwc_ethernet_mac10_100_1G_universal dwc_ethernet_mac10_100_universal 111 115 117 dwc_jpeg 129 dwc_mobile_storage 119 DWC_n2p 182 dwc_pci 131 dwc_pci_express_dm 144 dwc_pci_express_ep 138 dwc_pci_express_rc 140 dwc_pci_express_sw 136 142 dwc_pci x 133 dwc_usb_1_1_device 154 dwc_usb_1_1_hub native 158 dwc_usb_1_1_ohci_host 156 dwc_usb_2_0_device 164 dwc_usb_2_0_host_subsystem pci ahb dwc_usb_2_0_hs_otg_subsystem ahb 162 dwc_usb2_hsotg_phy 168 dwc_usb2_nanophy 172 dwc_usb2_phy 166 dwc_wiusb_device_controller 170 dwc_xaui_phy 174 dwcore_pcie_phy 146 DWMM See also DesignWare Memory Models Synopsys Inc 185 Index DWMM See also Memory IP E enethub_fx 83 ethernet_monitor_vmt 82 ethernet_txrx_vmt 82 F FlexModels 96 Foundry Libraries See also DesignWare Foundry Libraries I I2C Models 84 i2c_txrx_vmt 84 Interfaces SWIFT connection for SmartModels 98 L Licensing for Synopsys products 10 M Memory IP listing 18 Memory Models See also DesignWare Memory Models Microprocessors Microcontroller Cores 69 Microprocessors Microcontroller Cores listing 17 18 Models
63. ayer tasks e Requester and Completer operate concurrently using independent command channels e Power management support e Supports VCS Native Testbench NTB e Supports the Reference Verification Methodology RVM e Support Verification Methodology Manual VMM for SystemVerilog 88 Synopsys Inc Highly configurable number of lanes process rates for received packets and completion packets transaction ordering rules packet payload sizes symbol times between transmissions of Ack Data Link layer packets number of SKIP symbols in a SKIP ordered set time out parameters etc Requester Generates single word read and write transfers to memory I O and configuration space Generates block read and write transfers to memory space Generates message transfers Transmits raw request packets created by user Custom error injection Automatic handling of completion packets or optional handling of completion packets by testbench Completer Reads and writes internal address spaces in response to link requests Allows modification and review of internal address spaces with zero cycle commands Allows configuration of address ranges for internal memory and I O spaces Returns raw request packets Transmits raw completion packets Creates completion packets for incoming requests Notifies testbench of significant events June 2009 DesignWare IP Family PCI Express Models Transceiver and Monitor Monitor e Pro
64. ble to provide portability to any foundry or process technology 460 S and 405 S e Customizable to enable you to target various performance power area or other implementation goals e AMBA AHB interface supports connection to industry standard peripherals for example DesignWare AMBA components for ease of SoC integration e Integrated functions in the PowerPC 460 405 CPUs include instruction and data caches memory management unit MMU timers and a JTAG debug port e Acomprehensive portfolio of the PowerPC family support tools is available through the IBM Business Partners network Offerings include operating systems compilers debuggers simulators and emulators and design services DesignWare PowerPC IBM 460 405 Benefits e Complete silicon tested processor subsystem e Ready to use just add your choice of memories and peripherals 460 S and 405 S A set of CoreConnect PLB4 peripherals are available at no extra charge to PowerPC 460 405 licensees e Industry standard DesignWare IP delivery package e Industry leading technical support team e Implementation View delivered as Verilog source e AMBA AHB for easy connection to peripherals e Tested against latest versions of Synopsys tools and other third party simulation tools June 2009 Synopsys Inc 177 DesignWare IP Family No DW_IBM460 S DW_IBM405 S a i s IBM PowerPC 460 and 405 CPU Cores Table 1 PowerPC 460 405 CPU Core Sample Specifications T
65. brarys using processes in a Verilog or VHDL testbench a C program or a OpenVera testbench You can switch between the HDL or OpenVera testbench and a compiled C program as the source for commands Listing of FlexModels Table 1 lists the FlexModels that are available including a brief description Table 1 Listing of FlexModels Model Name Vendor Description Bus Models enethub_fx Ethernet Emulates the protocol of Ethernet Hub at the pin and bus cycle levels handles data routing from TX to RX rmiis_ fx Ethernet Interface between MII and reduced RMII interface pcimaster_fx PCI PCI X Emulates the protocol of PCI PCI X initiators at the pin and bus cycle levels Initiates read and write cycles pcislave_fx PCI PCI X Responds to cycles initiated by the pcimaster_fx model or by the user s PCI master device pcimonitor_fx PCI PCI X Monitors logs and arbitrates activity on the PCI or PCI X bus Support Models sync8_fx Synopsys 8 bit synchronization model 96 Synopsys Inc June 2009 DesignWare IP Family Listing of FlexModels More information on these models is available from the following Web page http www synopsys com products designware dwverificationlibrary html The FlexModel User s Manual is available at http www synopsys com products designware docs g m S O o e gt 5 June 2009 Synopsys Inc 97 SmartModel Features DesignWare IP Family DesignWare Sma
66. c Lane reversal as specified in the PCI Express Base Specification transmit and receive Polarity inversion on receive e Multiple Virtual Channels VCs 138 Synopsys Inc Multiple Traffic Classes TCs Multiple functions Supports bypass cut through and store and forward queues for received TLPs Configurable for infinite credits for all types of traffic ECRC generation and checking PCI Express beacon and wake up mechanism PCI power management PCI Express Active State Power Management ASPM PCI Express Advanced Error Reporting MSI and MSI X All in band Messages for PCI Express Endpoint Configurable Endpoint filtering rules for Posted Non Posted and Completion traffic Configurable BAR filtering I O filtering and configuration filtering Programmable completion timeout June 2009 K e Supports up to three independent client interfaces for transmitting TLPs e Access to configuration space registers and external application registers through local bus controller e Automatic generation of Completions for devices that require only simple access to an application register block More information is available at DesignWare IP Family dwc_pci_express_ep PCI Express Endpoint Synthesizable Core e Selectable arbitration mechanism for transmit interfaces or use an external arbiter e Supports expansion ROM e Implements parity checking on transmit buses memory buses and internal
67. ce page 150 Synthesizable RTL dwc_sata_phy SATA PHY page 152 Hard IP June 2009 Synopsys Inc 109 010 MA Chapter 4 DesignWare Cores Digital and Mixed Signal IP DesignWare IP Family USB Cores dwc_usb_1_1_device USB 1 1 Device Controller page 154 Synthesizable RTL dwc_usb_1_1_ohci_host USB 1 1 OHCI Host Controller page 156 Synthesizable RTL dwc_usb_1_1_hub native USB 1 1 Hub Controller page 158 Synthesizable RTL dwc_usb_2_0_host_subsyste USB 2 0 Host Controller UHOST2 Synthesizable RTL m pci ahb page 160 dwc_usb_2_0_hs_otg_subsyst USB 2 0 Hi Speed On the Go Controller Synthesizable RTL em ahb Subsystem page 162 dwc_usb_2_0_device USB 2 0 Device Controller page 164 Synthesizable RTL dwc_usb2_phy USB 2 0 PHY page 166 Hard IP dwc_usb2_hsotg_phy USB 2 0 Hi Speed On the Go PHY Hard IP page 168 dwc_wiusb_device_controller Wireless USB Device Controller Synthesizable RTL page 170 dwc_usb2_nanophy USB 2 0 nanoPHY page 172 Hard IP 110 Synopsys Inc June 2009 DesignWare IP Family Co Te dwc_ethernet_mac10_100_universal S Ethernet MAC 10 100 Universal Core dwc_ethernet_mac10_ 100_universal Ethernet MAC 10 100 Universal Core The DesignWare Ethernet MAC 10 100 Universal Core enables the host to communicate data using the Ethernet protocol IEEE 802 3 This silicon proven core is configurable and scalable to meet multiple Ethernet application req
68. ce AuxData p a Interrupt Interrupts Detection e xpins O This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_gpio Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 37 DesignWare IP Family DW_apb_i2c APB IC Interface aaa DW_apb_i2c APB I C Interface Two wire C serial interface Three speeds o Standard mode 100 Kb s o Fast mode 400 Kb s o High speed mode 3 4 Mb s Supports clock synchronization e Master or slave I7C operation 38 Supports multi Master operation bus arbitration 7 or 10 bit addressing 7 or 10 bit combined format transfers Slave bulk transfer mode Component parameters for configurable software driver support Ignores CBUS addresses an older ancestor of C that used to share the C bus Transmit and receive buffers Interrupt or polled mode operation e Handles Bit and Byte waiting at all bus speeds Simple software interface consistent with DesignWare APB peripherals Digital filter for the received SDA and SCL lines Support for APB data bus widths of 8 16 and 32 bits DMA handshaking interface compatible with the DW_ahb_dmac handshaking interface DW_apb_i2c APB Sla
69. ceiver and Hub Ethernet Models RMII Transceiver and Hub The Synopsys Ethernet FlexModel set consists of two models and system testbenches in OpenVera Verilog C and VHDL e rmiirs_fx The RMII interface is a low pin count MII interface intended for use between the ethernet PHY and switch or repeater ASICs The interface has the following features supports 10 Mb s and 100 Mb s data rates single clock reference is sourced from the MAC to PHY or from an external source and independent 2 bit wide transmit and receive paths e enethub_fx This FlexModel is the BFM that supports hub functionality for the MII MII 100 and GMII Ethernet MAC The following types of operations are performed by the model acts as a common PHY for all MACs connected on its MII ports and propagates the transmitted data from the transmitting MAC to all the MACs in the g m S h system 8 e gt 5 HUB in full Ethernet FlexModels Duplex Mode Rx0 Rx1 T Fg gt rmiirs fx RMI rmiirs fx x Mil e l l sN nm ie Tx0 Tx enethub_ fx The individual DesignWare FlexModel databooks can be found with each model at http www synopsys com products designware ipdir June 2009 Synopsys Inc 83 DesignWare IP Family I2C Model Jransceiver IC Model Transceiver i2c_txrx_vmt Model Full I C Master and Slave functionality Start repeat start and stop for all poss
70. ces Supports popular data rates 3 125 Gbps 3 0 Gbps 2 5 Gbps 1 5 Gbps and 1 25 Gbps Provides on die scope and diagnostics for fast system verification e Small cost effective die size Supports popular 130 nm 90 nm and 65 nm common platform processes e Supports 4x and 8x lane widths Supports many reference clock frequencies 25 MHz 156 25 MHz including popular 125 MHz and 156 25 MHz clocks Interoperable with the Synopsys DesignWare XGXS PCS IP Provides flexible Tx pre emphasis and Rx equalization settings to support a variety of lossy channels DesignWare IP Family dwc_xaui_phy XAUI PHY IP Performance e Low jitter PLL technology with excellent supply isolation Low offset high sensitivity receiver with high resolution CDR Robust PHY architecture tolerates wide PVT variations Short training sequences and fast transitions between power states enable highly efficient operation 10 supply variation Excellent performance margin and receive sensitivity Very low power design down to half the power compared to conventional PHYs The DesignWare dwc_xaui_phy datasheet is available at http www synopsys com products designware docs ds c dwe_xaui_phy pdf Synopsys Inc 175 010 MA Chapter 5 DesignWare Star IP DesignWare IP Family 5 DesignWare Star IP Design engineers who use the DesignWare Library have the ability to evaluate and design easily at their desktop using th
71. cessor Core page 182 Access to the full suite of memory IP is made available through DesignWare Memory Central a memory focused Web site that lets designers download DesignWare Memory IP and documentation Visit Memory Central at http www synopsys com products designware memorycentral Synthesizable RTL Also visit the DesignWare Verification Library web page at http www synopsys com products designware dwverificationlibrary html June 2009 Synopsys Inc 21 Chapter 1 Overview DesignWare IP Family DesignWare Cores Digital and Mixed Signal The DesignWare Cores shown in the following table provide system designers with silicon proven digital and analog connectivity IP DesignWare Cores are licensed individually on a fee per project business model Component Name Component Description Component Type Ethernet Cores dwc_ethernet_mac10_100_un Ethernet MAC 10 100 Universal Synthesizable RTL iversal page 111 dwc_ether_mac10_100_1000 Ethernet MAC 10 100 1G Universal Synthesizable RTL _universal page 113 Mobile Storage Core dwc_mobile_storage Secure Digital SD Multimedia Card Synthesizable RTL MMC and CE ATA page 119 IEEE 1394 Cores dwc_1394_av_link TEEE 1394 AVLink page 121 Synthesizable RTL dwe_1394_cphy native IEEE 1394 Cable PHY page 123 Synthesizable RTL JPEG Core dwc_jpeg JPEG CODEC page 129 Synthesi
72. cimaster_fx Performs timing violation checks and emulates the protocol of PCI PCI X initiators at the pin and bus cycle levels Initiates read and write cycles In PCI X mode pcimaster_fx can function as a target for split transactions e pcislave_fx Responds to cycles initiated by the pcimaster_fx model or by the user s PCI master device In PCI X mode the pcislave_fx also functions as an initiator for split transactions e pcimonitor_fx Monitors logs and arbitrates activity on the PCI or PCI X bus e PCI and PCI X system testbenches Provides ready to use example testbenches for both conventional PCI mode and PCI X mode Each system testbench uses two pcimaster_fx models two pcislave_fx models and a pcimonitor_fx model PCI system level testbench HDL control OpenVera command stream gt Pcimaster_fx ae Cc control file a ee HDL control i OpenVera command stream gt pcislave_fx onc control file See HDL control i OpenVera command stream gt Pcimonitor_fx or C control file p S bus trace output file 90 Synopsys Inc June 2009 DesignWare IP Family PCI PCI X Bus Models Master Slave and Monitor The individual DesignWare FlexModel databooks are available with each model at http www synopsys com products designware ipdir g m S O o e gt Ea June 2009 Synopsys Inc 91 DesignWar
73. clk_in_sample Control cclk_in optional The DesignWare DWC_mobile_storage datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_mobile_storage pdf 120 Synopsys Inc June 2009 dwe_1394_av_link Synthesizable IEEE 1394 AVLink DTCP DesignWare IP Family dwce_1394 av_link Synthesizable IEEE 1394 AVLink DTCP The Synopsys DesignWare IEEE 1394 AVLink DTCP intellectual property IP is a set of highly configurable blocks that implements complete 1394 interface functions tailored to support audio visual AV oriented IEC 61883 applications Configured through our RapidScript utility this device can also be optimized to act as a generic 1394 device controller Therefore AVLink can be effectively used in a wide range of applications such as digital still cameras video conferencing cameras printers scanners digital audio devices electronic musical instruments digital VCRs VTRs and storage devices Other features include the following Silicon proven IEEE 1394 Link Layer Controller for both audio visual A V and non A V applications Support for common isochronous packet CIP headers time stamping and padded zeros for A V data transactions TEEE 1394 1995 and 1394a 2000 specification compliance IEC 61883 requirement for A V data streaming compliance Supports 100 200 400 Mbps data rates Full link layer implementation e Asynchronous isochronous and PHY June 2009 packet
74. clude the following 164 Complies with USB 2 0 and USB 1 1 protocols Integrates the UDC20 UDCVCI USB device controllers from Synopsys Supports high speed 480 MHz full speed 12 MHz and low speed 1 5 MHz operations for UDC20 and supports full speed and low speed operations for UDCVCI Supports AHB clock hclk_i frequencies of 12 133 MHz for UDC VCTI For UDC20 the range is 16 to 133 MHz Supports up to 16 IN and 16 OUT physical endpoints which can be tied to different interfaces and configurations to achieve logical endpoints Permits user control through memory mapped control and status registers CSRs Enables user configurable endpoint information Supports both DMA option and Slave Only modes Supports true scatter gather DMA implementation Supports descriptor based memory structures in application memory when in DMA mode Synopsys Inc Ideally suited for portable handheld applications requiring optimal memory usage Supports adaptive buffering for efficient IN endpoint buffer management Completely synchronous design clock boundary is in the subsystem e Supports power management In full and high speed operation UDC AHB subsystem is compatible with UTMI level 3 PHY Supports the following UTMI data bus interfaces o Unidirectional 8 bit interface o Unidirectional 16 bit interface O Bidirectional 8 bit interface O Bidirectional 16 bit interface ULPI functions defined in the ULPI speci
75. cycles elocan coume doek o Long time base counter clocked Interrupt polarity level with a very slow clock signal Interrupt clock domain location Counter enable mode O O O 0 Counter wrap mode DW_apb_rtc Counter APB Interface Synchronization Register Interrupt Generation Block P Read Write Up Counter Coherency This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_rtc Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 43 DesignWare IP Family DW_apb_ssi APB Synchronous Serial Interface DW_apb _ ssi APB Synchronous Serial Interface e AMBA APB interface Allows for e Programmable features easy integration into an AMBA o Serial interface operation Choice System on Chip SoC of Motorola SPI Texas implementation Instruments Synchronous Serial e Scalable APB data bus width Protocol or National Supports APB data bus widths of 8 Semiconductor Microwire 16 and 32 bits o Clock bit rate Dynamic control e Serial master or serial slave operation of serial bit rate of data transfer Enables serial communication with used in only serial master mode serial master or serial slave peripheral o Data Item size 4 to 16 bits Item devices size of each data transfer u
76. da MAST ModelTools NanoSim OpenVera PathMill Photolynx Physical Compiler PrimeTime SiVL SNUG SolvNet System Compiler TetraMAX VCS and Vera are registered trademarks of Synopsys Inc Trademarks Active Parasitics AFGen Apollo Astro Astro Rail Astro Xtalk Aurora AvanTestchip AvanWaves BOA BRT ChipPlanner Circuit Analysis Columbia Columbia CE Comet 3D Cosmos CosmosEnterprise CosmosLE CosmosScope CosmosSE Cyclelink DC Expert DC Professional DC Ultra Design Advisor Design Analyzer Design Vision DesignerHDL DesignTime Direct RTL Direct Silicon Access Discovery Dynamic Macromodeling Dynamic Model Switcher EDAnavigator Encore Encore PQ Evaccess ExpressModel Formal Model Checker FoundryModel Frame Compiler Galaxy Gatran HANEX HDL Advisor HDL Compiler Hercules Hercules ll Hierarchical Optimization Technology High Performance Option HotPlace HSIMP S HSPICE Link iN Tandem Integrator Interactive Waveform Viewer i Virtual Stepper Jupiter Jupiter DP JupiterXT JupiterXT ASIC JVXtreme Liberty Libra Passport Library Compiler Libra Visa Magellan Mars Mars Rail Mars Xtalk Medici Metacapture Milkyway ModelSource Module Compiler Nova ExploreRTL Nova Trans Nova VeriLint Orion_ec Parasitic View Passport Planet Planet PL Planet RTL Polaris Power Compiler PowerCODE PowerGate ProFPGA ProGen Prospector Raphael Raphael NES Saturn ScanBand Schematic Compiler Scirocco
77. data buses optional http www synopsys com products designware pciexpress html 010 MA June 2009 Synopsys Inc 139 DesignWare IP Family dwc_pci_express_rc PCI Express Root Port Synthesizable Core dwc_pci_express rc PCI Express Root Port Synthesizable Core The DesignWare Root Port core for PCI Express 2 0 is a synthesizable RC solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following Complies to PCI Express Base Specification Revision 2 0 Modular design including a base core CXPL plus additional support modules for Root Port specific functionality e Type 1 configuration space e 62 5MHz 125MHz 250MHz 500MHz Up to 16 2 5 5 0 Gbps Lanes x1 x4 x8 or x16 e 32 64 or 128 bit datapath width Support for 8 16 32 bit PHYs through the PIPE e Ultra low transmit and receive latency e Configurable retry buffer size Configurable number of outstanding Requests Configurable Max_Payload_Size size 128 bytes to 4 KB 4 KB maximum Request size e Very high accessible bandwidth e Automatic Lane reversal as specified 140 in the PCI Express Base Specification transmit and receive Application initiated Lane reversal for situations where the EP Core does not detect Lane 0 for example an x4 EP Core connected to an x8 device that has its Lanes reversed Synopsys Inc Polarity inversi
78. databooks or datasheets How to configure and operate the model Any timing parameters that differ from the vendor specifications How to program the device if applicable or otherwise use it in simulation Differences between the model and the corresponding hardware device Models are partitioned by function including Processors VLSI Programmables Memories Standards Buses General Purpose SmartModel datasheets have standard sections that apply to all models and model specific sections whose contents depend on the model type June 2009 Synopsys Inc 99 g m S O g e gt Ea Chapter 3 DesignWare Foundry Libraries DesignWare IP Family 3 DesignWare Foundry Libraries This chapter briefly describes the DesignWare Foundry Libraries Synopsys is teaming with foundry leaders to provide DesignWare Library licensees access to standard cells memories and I Os optimized for their process technologies Each library is delivered in a set of front end and back end views The front end views enable a complete evaluation of the libraries all the way through layout and complete verification The back end views include the GDSII data and tech files necessary for tape out TSMC Libraries TSMC and Synopsys offer a complete path from RTL to GDSII by ensuring a tight integration of the TSMC Libraries and the Synopsys Galaxy platform through the TSMC Reference Flow 8 0 Both the front end and back end views of the TSMC
79. de Partial power off during USB Suspend mode and Session Off mode Hierarchy to support multiple power rails Input signals to powered off blocks driven to safe 0 Data FIFO RAM chip select deasserted when not active Data FIFO RAM clock gating support Application Features Interfaces for the application via the AHB AHB Slave interface for accessing Control and Status Registers CSRs the Data FIFO and queues Optional AHB Master interface for Data FIFO access when Internal DMA is enabled Supports AHB clock frequencies up to 180 MHz with suitable technology for example a standard 0 13 micron technology Supports only 32 bit data on the AHB Supports Little or Big Endian mode selectable by pin Supports all AHB burst types in AHB Slave interface Supports Split Retry and Error AHB responses on the AHB Master interface these are not generated on the AHB Slave interface Software selectable AHB burst type on AHB Master interface If INCR4 is chosen core only uses INCR4 If INCR8 is chosen core normally uses INCR8 but at the beginning and at the end of a transfer it can use INCR4 depending on the size of the transfer If INCR16 is chosen core normally uses INCR16 but at the beginning and at the end of a transfer it can use INCR4 INCR8 depending on the size of the transfer Handles the fixed burst address alignment For example INCR16 is used only when lower addresses 5 0 are all 0 Generates AHB Busy cycles on the AHB
80. dge Synthesizable Core dwc_pci_express sw PCI Express Switch Bridge Synthesizable Core The DesignWare Switch Bridge core for PCI Express 2 0 is a synthesizable SW solution that can be configured to address multiple applications ranging from server and desktop systems to mobile devices Other features include the following Complies to PCI Express Base Specification Revision 2 0 Modular design including a base core CXPL plus additional support modules for Switch specific functionality e Type 1 configuration space e 62 5MHz 125MHz 250MHz 500MHz Up to 16 2 5 5 0 Gbps Lanes x1 x4 x8 or x16 e 32 64 or 128 bit datapath width Configurable as upstream Switch Port downstream Switch Port PCI X to PCI Express Bridge or PCI Express to PCI X e Full PCI Bridge to Bridge support Support for 8 bit and 16 bit PHYs through the PIPE e Supports prefetchable memory space Transaction filtering and routing look up Multiple Virtual Channels VCs Multiple Traffic Classes TCs Configurable VC TC mapping Full PCI Express Message passing and processing Ultra low transmit and receive latency e Configurable retry buffer size 142 Synopsys Inc Configurable number of outstanding Requests Configurable Max_Payload_Size size 128 bytes to 4 KB 4 KB maximum Request size Very high accessible bandwidth Lane reversal transmit and receive Polarity inversion transmit and receive Supports bypass c
81. dth as follows width 3 16 x bit period as specified in the IrDA physical layer specification Programmable serial data baud rate Configurable baud clock reference output signal Modem and status lines are independently controlled Programmable Loopback mode that enables greater testing of Modem Control and Auto Flow Control features Loopback support in IrDA SIR mode is available Selectable clock gate enable output s used to indicate that the TX and RX pipeline is clear no data and no activity has occurred for more than one character time so clocks may be gated Separate system resets for each clock domain to prevent metastability Selectable FIFO access mode for FIFO testing so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master g m wo lt m gt D 2 N D D 5 Also see the block diagram on the following page June 2009 Synopsys Inc 47 DesignWare IP Family DW_apb_uart APB Universal Asynchronous Receiver Transmitter FIFO APB Block Interface Optional Register Block Timeout Detector Optional Baud Clock Generator Serial Transmitter This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_uart Databook is available at http www synopsys com products designware docs 48 Synopsys Inc June 2009 DW_a
82. e address and data buses though the PClIe AXI Bridge PCle AXI Bridge handles completion time outs June 2009 DesignWare IP Family e O PCle AXI Bridge S PCI Express to AMBA 3 AXI Bridge More information is available at http www synopsys com products designware pciexpress html 010 MA June 2009 Synopsys Inc 137 DesignWare IP Family dwc_pci_express_ep PCI Express Endpoint Synthesizable Core dwc_pci_express_ ep PCI Express Endpoint Synthesizable Core The DesignWare Endpoint Core for PCI Express implements the port logic required to build a PCI Express 2 0 Endpoint device The silicon proven Endpoint core is configurable and scalable to meet multiple endpoint application requirements ranging from server and desktop systems to mobile devices Other features include the following Complies to PCI Express Base Specification Revision 2 0 Modular design including a base core CXPL plus additional support modules for Endpoint specific functionality Type 0 configuration space e 62 5Mhz 125MHz 250MHz S00Mhz e Upto 16 2 5 5 0 Gbps Lanes x1 x2 x4 x8 or x16 32 64 or 128 bit datapath width e Support for 8 16 32 bit PHYs through the PIPE Ultra low transmit and receive latency Configurable retry buffer size e Configurable number of outstanding Requests Configurable Max_Payload_Size size 128 bytes to 4 KB e 4 KB maximum Request size Very high accessible bandwidth Automati
83. e IP Family Serial ATA Models Device and Monitor Serial ATA Models Device and Monitor Device sata_device_vmt 92 Gen 1 and Gen 2 support SATA PHY Interface Differential NRZ serial stream Transfer support includes o PIO o First party DMA o Legacy and Legacy Queued DMA o Non Data and PACKET command transfers Power on sequencing and speed negotiation CRC computation 8B 10B encoding and decoding Scrambling Descrambling Native command queuing Power management Far end retimed loop back Far end transmit only and Far end analog loop back BIST modes OOB signal detection and transmission Error injection detection Supports VCS Native Testbench NTB Supports OpenVera Reference Verification Methodology RVM Supports Verification Methodology Manual VMM for System Verilog Synopsys Inc Monitor sata_monitor_vmt Gen 1 and Gen 2 support Snoops bus information Protocol coverage Checks the validity of the following aspects for the corresponding layers o Physical Serialization Deserialization SERDES Out of band signaling o Link Framing CRC 8B 10B encoding scrambling running disparity o Transport FIS sequencing o Command Legacy DMA Legacy queued DMA Packet PIO Register and First party DMA commands Native command queuing Issues informative messages Supports VCS Native Testbench NTB Supports OpenVera Reference Verification Methodology RVM Supports Verification Methodology Ma
84. e following high performance high value IP cores from leading Star IP providers All DesignWare Star IP cores are packaged with the Synopsys coreConsultant tool which guides the user through the installation configuration verification and implementation Component Name Component Description Component Type DW_IBM460 S PowerPC 32 Bit Microprocessor Cores from Synthesizable RTL DW_IBM405 S IBM page 177 Simulation Models DW_CoolFlux CoolFlux 24 bit DSP Core from NXP page 179 Synthesizable RTL Simulation Model DWC_n2p Nios II Processor Core page 182 Synthesizable RTL a Simulation models of these cores are available to all active DesignWare Library licensees and accessed through the Synopsys website Synthesizable RTL implementation views of these cores are available from Synopsys and or their respective IP providers 176 Synopsys Inc June 2009 DesignWare IP Family S fy ld DW_IBM460 S DW_IBM405 S IBM PowerPC 460 and 405 CPU Cores DVW_IBM460 S DW_IBM405 S IBM PowerPC 460 and 405 CPU Cores Overview The IBM PowerPC 460 405 cores are portable and synthesizable implementations of the PowerPC 460 and 405 32 bit RISC CPU cores The Power PC 405 S core employs the scalable and flexible Power ISA 2 03 and the PowerPC 460 S core employs the powerful Book E Enhanced PowerPC Architecture Both cores are optimized for embedded applications Highlights e Fully synthesiza
85. e mail message This will provide us with information to identify the source of the problem June 2009 Synopsys Inc 11 Preface DesignWare IP Family 12 Synopsys Inc June 2009 DesignWare IP Family Chapter 1 Overview 1 Overview Synopsys DesignWare IP the world s most widely used silicon proven IP provides designers with a broad portfolio of synthesizable implementation IP hardened PHYs and verification IP for ASIC SoC and FPGA designs The DesignWare family includes the following products e DesignWare Library on page 14 contains the principal ingredients for design and verification including high speed datapath components AMBA On Chip Bus memory portfolio verification models of standard bus and I Os foundry libraries popular Star IP cores and board verification IP e VCS Verification Library on page 20 is a subset of the DesignWare Library and contains reusable pre verified verification IP of the industry s most popular bus and interface standards such as AMBA PCI Express PCI X PCI USB On the Go Ethernet I7C and thousands of memory models e DesignWare Cores Digital and Mixed Signal on page 22 silicon proven digital and mixed signal standards based connectivity IP such as PCI Express PCI X PCI USB 2 0 On the Go OTG USB 2 0 PHY USB 1 1 and Ethernet e DesignWare Star IP on page 24 high performance high value cores from leading Star IP providers such as IBM Infineon
86. echnology 90nm Worst case conditions Temperature 125 C Voltage 1 08 v Frequency 400 MHz 460 S 400 MHz 405 S Die Size 8 31 mm 460 S 1 69 mm 405 S Power Dissipation 5 27 mw MHz WC Process 460 S 0 96 mw MHz WC Process 405 S See the following web page for additional information http www synopsys com IP Design Ware StarIP Pages IBMPowerPC aspx 178 Synopsys Inc June 2009 DW_CoolFlux CoolFlux 24 bit DSP Core from NXP DesignWare IP Family DW_CoolFlux CoolFlux 24 bit DSP Core from NXP The NXP CoolFlux DSP is a synthesizable 24 bit DSP Core for ultra low power applications like portable audio encoding decoding sound enhancement and noise suppression The core targets specific applications such as headsets hearing instruments and portable audio players The NXP CoolFlux DSP is designed with a highly efficient ILP optimizing C compiler The compiler can exploit all the parallelism in the core and generates very efficient code both from a cycle and code density perspective Other features include the following e Ultra low power consumption o lt 0 1mW MHz 1 2V 0 13u CMOS o lt 0 2m W MHz 1 8V 0 18u CMOS e Highly optimizing C compiler e Minimal core size 43K gates excluding debug interface 4 5k gates e Small memory footprint e Performance worst case commercial conditions o 175 MHz 0 13u CMOS o 135 MHz 0 184 CMOS gt 1000 MOPs e Extensive software
87. ed On Chip Debug OCD module enabling start stop and step e 5 pin JTAG interface with embedded tap controller for OCD debug e Embedded JTAG UART for stdio comm e Embedded timer module for Nios II software backward compatibility e Full compatibility with the Nios II Integrated Development Environment Compatible with software environment based on the GNU C C tool chain and Eclipse 182 Synopsys Inc Unsupported NIOS II Features No Separate Instruction and Data Master ports Harvard architecture No Avalon burst protocol Nios II Processor transfers are issued as single No floating point instructions for single precision floating point operations No instructions for computing 64 bit and 128 bit products Data Master system memory port is not removable needed for OCD No level 2 amp level 3 debug support no support for HW breakpoint and trace Key Configurability Options Instruction Cache Size 512 64K Instruction TCM Interfaces 0 or 1 Instruction TCM Size 512 64K Allow Data Writes to ITCM Yes No Number of Data TCM 0 4 Data TCM Size 512 64K Data Cache Size 0 64K Cacheless Option to remove both Data Cache and DTCM External Interrupts 0 4 Configurable Priority Level per Interrupt June 2009 8 DesignWare IP Family ap Ip DWC_n2p Nios Il Processor Core User s Subsystem Design J gt Memory JTAG 5 pin Master 1 eee Nios II Processor ontro DWC_n2p
88. errig ett ake EIER CEEL 172 dwc_xaui_phy RAUPA 2 aici Sposa hese eaea a aa aa ae mas 174 Chapter 5 DesignWare Star IP side hoi oe edie startat SHAS SERS RARER RE TREES 176 DW_IBM460 S DW_IBM405 S IBM PowerPC 460 and 405 CPU Cores osc ve cee diesseeutiessvessiess 177 DW_CoolFlux CoolFlux 24 bit DSP Core trom NXP 2c cago teesse beckon deabigece bas 179 DWC_n2p Nios I Processor CoO 3 0 a oo a a ee 182 PEaMIIES 6 6 0 654 025 6505 64 Hho 056 S4 PEO RS dik eode 61 08609 kha OKRA 182 LODGE 45 55 6 WH EKG PERE ECE KS CREE PADS CREHS EGG ED RUE EEA 6S KER EEUE FREE EERE 184 June 2009 Synopsys Inc 7 Contents DesignWare IP Family 8 Synopsys Inc June 2009 DesignWare IP Family Preface Preface About This Manual This manual is a brief overview of the DesignWare Family of synthesizable and verification IP For detailed product information refer to individual product databooks and manuals mentioned in the following chapters TS Note DesignWare Building Block component information has been moved from this document to a separate document the DesignWare Building Blocks Quick Reference Guide Manual Overview This manual contains the following chapters Preface Describes the manual and typographical conventions and symbols tells how to get technical assistance Chapter 1 Contains an overview and general description Overview of the DesignWare Library product offering Chapter 1 Describes the available DesignWare Library AMB
89. ess decoder from boot mode to normal mode operation e Pause Mode Used to put the DW_ahb s arbiter into low power pause mode e In pause mode the dummy master is granted the AHB bus until an interrupt occurs e Reset Status Register Keeps track of status from up to eight separate system reset signals e Identification Code Register Implements a configurable read only ID register DW_apb_rap APB Interface Registers Remap Pause This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_rap Databook 1s available at http www synopsys com products designware docs 42 Synopsys Inc June 2009 DesignWare IP Family DW_apb_rtc APB Real Time Clock DW_apb_rtc APB Real Time Clock e APB slave interface with read write e Some uses of the DW_apb_trtc are o coherency for registers o Real time clock used with e Incrementing counter and comparator software for keeping track of time for interrupt generation o Long term exact chronometer a e Free running pclk When clocked with a 1 Hz clock N e User defined parameters it can keep track of time from now up to 136 years in the future 5 o APB data bus width o Alarm function generates an o Counter width 8 interrupt after a programmed o Clock relationship between bus number of
90. ffusion programmable csm25ro144 0 35 um Standard Cells Logic csm35o0s142 I Os In line 3 3V 5V tolerant csm35i0122 In line PCI 3 3V 5V tolerant csm35pc132 RAM Compilers Single port synchronous csm35rs142 Single port asynchronous csm35ral12 Dual port asynchronous csm35rd112 Two port asynchronous csm35ra122 ROM Compiler Synchronous diffusion programmable csm35ro122 June 2009 Synopsys Inc 107 z ma 5 2 2 lt T o z oD D z Chapter 4 DesignWare Cores Digital and Mixed Signal IP DesignWare IP Family 4 DesignWare Cores Digital and Mixed Signal IP DesignWare Cores provide system designers with silicon proven digital and analog connectivity IP Provided as heavily annotated synthesizable RTL source code or in GDS format these cores enable you to design innovative cost effective systems on chip and embedded systems DesignWare Cores are licensed individually on a fee per project business model The following table identifies the DesignWare Cores offering Component Name Component Description Component Type Ethernet Cores dwc_ethernet_mac10_100_un Ethernet MAC 10 100 Universal Synthesizable RTL iversal page 111 dwc_ether_mac10_100_1000 Ethernet MAC 10 100 1G Universal Synthesizable RTL _universal page 113 dwc_ether_xgmac 10 Gigabit Ethernet Mac page 115 Synthesizable RTL dwc_ethernet_pcs PCS Layer of 10 Gigabit Extended sub Synthesizable RT
91. fication version 1 0rc are supported with the following exceptions ULPI in Low Speed mode is not supported 60 MHz only clock speed UTMI data width is normally 8 bits input output DDR nibble operation is supported OTG Carkit features are not supported June 2009 DesignWare IP Family C Og dwc_usb_2 0 device S Synthesizable USB 2 0 Device Controller VCI Application Control VCI State Status Block Machine PEA Suspend Synchronization Block Resume Block Protocol Management BaN Block Command Bridge Laver Layer Protocol Parallel Serial Interface Interface Engine Engine PIE SIE PHY Macrocell Transceiver The dwcore_usb2_device datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_usb_2_0_device pdf June 2009 Synopsys Inc 165 010 MA DesignWare IP Family dwc_usb2_phy USB 2 0 Transceiver Macrocell Interface PHY dwc_usb2_phy USB 2 0 Transceiver Macrocell Interface PHY The USB 2 PHY includes all the required logical geometric and physical design files to implement USB 2 0 capability in a System on Chip SOC design and fabricate the design in the designated foundry The initial foundry process for the USB 2 PHY is the 0 18 micron CMOS digital logic process Alternatively design services are available for porting the USB 2 PHY to other semiconductor processes The USB 2 PHY integrates high speed mixed signal custom CMOS circuitry compl
92. for endpoints for small FIFOs and flexible efficient use of RAM Uses single port RAM instead of dual port RAM for smaller area and lower power Provides support to change an endpoint s FIFO memory size during transfers Supports endpoint FIFO sizes that are not powers of 2 to allow the use of contiguous memory locations Shares the hardware registers in the Host and Device modes to reduce gate count Supports the Keep Alive in Low Speed mode and SOFs in High Full Speed modes Power optimized design Optional support for Transmit and Receive thresholding in DMA mode when dedicated Tx FIFO is selected in Device mode Thresholding and threshold length selectable through global registers For supporting thresholding the AHB must be run at 60 MHz or higher NoteDedicated FIFO operation refers to the core configuration in which each Device mode IN endpoint has individual transmit FIFOs Shared FIFO operation refers to the core configuration in which all non periodic IN endpoints share a common TX FIFO and periodic IN endpoints have separate individual FIFOs USB 2 0 Supported Features 162 Complies with the On The Go Supplement to the USB 2 0 Specification Revision 1 0a Operates in High Speed HS 480 Mbps Full Speed FS 12 Mbps and Low Speed LS 1 5 Mbps modes Supports the UTMI Level 3 interface Revision 1 0 February 25th 2004 8 16 and 8 16 bit data buses are supported Supports ULPI interface Revision 1 1rc Se
93. gb 8 eee eee es es 65 DW_rambist Memory Hyilt In Se Tee jonas tessnnseceadssae be tedeeeeeeenee pense 67 Wheroprocessoriicrorgniollete g ces iced end ie seuesdigegeeabiveueesciee 69 DW_6811 Synopsys Inc June 2009 DesignWare IP Family Contents poli MierOconiOUlel 4 4 44iiw lao or i ad ened ee ahd Hh ea ees 70 DW8051 BUS Microcontroller sssrcrrsre b eve eee need BAS HOE OOOR EOE OOO ni 72 Chapter 2 DesignWare Library Verification IP ccc ccc ce cece cee eee eee 74 WERE 44 Bode cked ed EA EE T EEN bones deen od kos E ieee RES 74 METH Models 9444 64443 44 0 Hid 4S a eK es 75 DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect 0 0 0 0 e eee ee eee 76 DesignWare AMBA APB Models Dae ae Mol ooo eee cadat enee ere raas orae orraa 78 DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect issirisciieirisaiisdrid kii kirii ki 79 Board Verification IP Simulation models for Board Verification 0 0 0c cece eee eee 81 Ethernet 10 100 1G 10G Models Transceiver and Monitor cc euddeue ends hee bbws been iw ee ed dhe ERS 82 Ethernet Models RMIT Transceiver and AU i404 eaccn cab erdeer ee esdd eaeeeea ees ESI 83 IC Model TBC CI CAE oi hd eg ek be heck eh a ew ee Re RS ek ee 84 Memory Models Simulation models of memory devices 4 66544424nredeeeudiee cee xeduads 85 Open Core Protocol OCP Models Master Slave and Monitor sceso 4644 eeabiwie ine cdiweeivesivubewnbiuws 86 PCI Exp
94. ge of applications such as SCSI Fibre Channel Gigabit Ethernet and graphics Other features include the following PCI X 1 0a compliant Host Bridge functionality Dual Address Cycles DAC Message Signaled Interrupts MSI PCI 2 3 compliant External EEPROM support 32 bit or 64 bit PCI X bus path Comprehensive Test Environment 64 bit application data path Device Under Test linkable to the test Supports 0 133 MHz PCI X bus ee Supports up to 32 outstanding delayed split transactions e RapidScript parameterized configuration for fast customization e Synthesizable Verilog source code June 2009 Synopsys Inc 133 010 MA DesignWare IP Family dwc_pci x x Qs Synthesizable PCI X Controller and Test Environment e Address Data Input Block R E i TA Defer Split lt lt Table Target Target State lt _ _ gt F Sequence EOIN gt Controller gt lt gt Ba EEPROM Controller gt Optional g j 3 Master Configuration Register IS ae Controller E x 3 O N A 2 F lt M Power anagement Controller lt Optional d gt lt gt Master Master State Sequence Message gt Machine Master Signaled 3 Controller Defer Split lt
95. h memory data widths 16 32 64 or 128 with 1 1 or 1 2 ratios with AHB data width DDR SDRAMs memory data width 8 16 32 or 64 with 1 2 or 1 4 ratios with the AHB data width DesignWare IP Family DW_memctl Memory Controller e Programmable row and column address bit widths e Supports 2K to 64K rows 256 to 32K columns and 2 to 16 banks e Supports up to 8 chip selects with a maximum of 4 GB of address space per chip select g m Q lt S gt D o N D 7 D e Supports asynchronous SRAMs page mode FLASHes and ROMs e Supports up to three sets of timing registers e Supports external READY handshake pin to interface non SRAM type device Note Does not generate split retry or error responses on the AHB bus Also see the block diagram on the following page June 2009 Synopsys Inc 65 DesignWare IP Family DW_memctl Memory Controller DW_memecll Host Interface Unit HIU Address Decoder SDRAM HIU Interface Control 4 gt Controller Registers AHB lt p Data SDR SDRAM Controller FIFO Static DDR SDRAM Controller Memory Address Interface FIFO 4 gt Refresh Unit Static Memory Controller Note Conditional Instantiations The DesignWare DW_memctl MacroCell Databook is available at http www synopsys com products designware docs 66 Synopsys Inc June 2009 MY Q Cro DW_rambist Memory Buil
96. i D D Pull up Cauca Daas n Machine NRZI Bit Tx Shift HS FS LS FS and Hold Transmitters f Transceiver MUX i USB 1 1 Single Ended A Serial Interface Transceiver Block USB 2 PHY Macro The dwcore_usb2_phy datasheet is available at 010 MA http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_usb2_phy pdf June 2009 Synopsys Inc 167 DesignWare IP Family dwc_usb2_hsotg_phy USB 2 0 Hi Speed OTG PHY dwc_usb2_hsotg_phy USB 2 0 Hi Speed OTG PHY The Synopsys DesignWare Hi Speed USB 2 0 On The Go HS OTG PHY is a complete mixed signal semiconductor intellectual property IP solution designed for single chip USB 2 0 integration in OTG applications The USB 2 0 OTG PHY includes all the required logical geometric and physical design files to implement USB 2 0 Hi Speed OTG capability in a system on chip SoC design and to manufacture it in the designated foundry The USB 2 0 OTG PHY is available in 90 nanometer nm 130 nm and 180 nm CMOS digital logic processes 168 Complete mixed signal physical layer PHY for single chip USB 2 0 OTG applications USB 2 0 Transceiver Macrocell Interface UTMI Level 3 specification 8 bit interface at 60 MHz operation and 16 bit interface at 30 MHz operation Hi Speed 480 Mbps Full Speed 12 Mbps and Low Speed 1 5 Mbps operation is compliant to the USB OTG Supplement Su
97. iable length MOVX to access fast slow RAM peripherals Fully static synchronous design June 2009 20 1O Coy AY 128 or 256 bytes iram_bus DesignWare IP Family DW8051 8051 Microcontroller DW8051_core DW8051_timer Timers 0 and 1 DW8051_cpu le gt DW8051_ alu DW8051_ control gt DW8051_biu DW8051_main_regs DW8051_op_decoder DW8051_timer2 Timer 2 optional or DW8051_intr_1 DW8051_ serial Serial Port 0 optional DW8051_serial gt Serial Porti lt W optional irom_bus 0 to 64 KB The DesignWare DW_8051 MacroCell Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc tO t1 tO_out t1_out t2 t2ex t2_out sfr_bus txdO rxd0_in rxdO_out g m wo lt m gt D a N D D 5 txd1 rxd1_in gt rxd1_out interrupts port_control mem_bus clk por_n rst_in_n rst_out_n test_mode_n idle_mode_n stop_mode_n 73 Chapter 2 DesignWare Library Verification IP DesignWare IP Family 2 DesignWare Library Verification IP Overview The following table identifies the various components that make up the DesignWare Library s Verification IP offering See page 81 for a listing of the Board Verification IP component group
98. iant with the UTMI Specification version 1 05 supports the USB 2 0 480 Mbps protocol and data rate and is backward compatible to the USB 1 1 legacy protocol at 1 5 Mbps and 12 Mbps Other features include the following 166 Complete mixed signal physical layer PHY for single chip USB 2 0 applications USB 2 0 Transceiver Macrocell Interface UTMI Specification compliant 8 bit interface at 60 MHz operation and 16 bit interface at 30 MHz operation chip Compatible with the Synopsys USB 2 0 Device and Host components USB 2 0 Device automatic switching between full and high speed modes Host Device automatic switching between full high and low speed modes Synopsys Inc Designed for minimal power dissipation for low power and bus powered devices Low power design enables host enumeration of an unpowered device Sea wall and decoupling structures reduce on chip noise Suspend Resume and Remote Wake up mode support USB 2 0 test mode support Additional built in analog testability features USB Implementers Forum certified June 2009 DesignWare IP Family dwc_usb2_phy USB 2 0 Transceiver Macrocell Interface PHY Test SYNC Bit Rx Shift Af Interface Detector Unstuffer and Hold HS FS LS NRZI Receivers HS DLL Squelch Elasticity Disconnect Buffer Receive State Machine Common Receiver Transmitter Block Local Bias Control FS DPLL kogig Pi D D
99. ible transfers Supports all I7C clocking speeds 7b 10b configurable slave address Configurable Slave FIFOs allows testing of varied bus traffic patterns Supports VCS Native Testbench NTB Supports the Reference Verification Methodology RVM SDA Supports Verification Methodology Manual YMM for System Verilog Multiple command streams allow Slave and Master to operate concurrently Compares read data with expected results Bus accurate timing e Notifies the testbench of significant events such as transactions warnings and protocol errors SCL Model CLK Clock pushd_slave_tx_fifo pop_slave_rx_fifo Test Bench read write The DesignWare PC Verification IP Databook is available at http www synopsys com products designware docs 84 Synopsys Inc June 2009 DesignWare IP Family Memory Models Simulation models of memory devices Memory Models Simulation models of memory devices DesignWare Memory Models are pre verified simulation models of memory devices The DesignWare Memory Models are built on top of the Synopsys memory model technology thus ensuring model accuracy quality and reliability With thousands of pre verified memory models to choose from supporting over 30 memory vendors it s very easy to find a match to a systems memory requirement The models integrate with the simulator through the de facto industry standard SWIFT interface which is
100. injection at each layer Provides functional coverage of PCI Express packet types http www synopsys com products designware docs ds c dwc_pcie_phy html Synopsys Inc 147 010 MA DesignWare IP Family dwc_sata_ahci Serial ATA AHCI dwc_ sata ahci Serial ATA AHCI The DesignWare SATA AHCI intellectual property IP is designed for use in system on chip SoC solutions The IP uses the popular AHB standard for a host interface and a configurable PHY link interface to support a number of industry PHYs Synopsys provides a large set of parameters to enable the IP s integration in systems with different requirements By leveraging these parameters the DWC SATA AHCI can optimize gate count and reduce time to market Features Supports SATA 1 5 Gbps Generation 1 and 3 Gbps Generation 2 speeds Compliant with Serial ATA Specification 2 6 and AHCI Revision 1 1 specifications Highly configurable PHY interface e Provides additional user defined PHY 148 status and control ports Optional Rx Data Buffer for recovered clock systems Optional data alignment circuitry when Rx Data Buffer is also included Optional OOB signalling detection and generation Gen speed negotiation when Tx OOB signalling is selected Digitally supports device hot plugging when Tx OOB signalling is selected Optional 8b 10b encoding decoding Synopsys Inc Features Supports power management features Supports BIST loopback
101. ir process technologies Each library includes a complete set of front end and back end views for Standard Cells and I Os Memory compilers are also included when available The current offering includes e TSMC Libraries for 0 15um 0 13um and 90nm and 65nm described on page 100 e Chartered Libraries for 0 35um 0 25um 0 18um and 0 13um described on page 106 18 Synopsys Inc June 2009 DesignWare IP Family Chapter 1 Overview Verification IP for Bus and I O Standards usb_device_vmt usb_monitor_vmt UTMI Low Pin Interface ULPI page 95 Component Name Component Description Type ahb_bus_vmt DesignWare VIP for AMBA 2 0 AHB Models Verification ahb_master_vmt page 76 ahb_monitor_vmt ahb_slave_vmt apb_master_vmt DesignWare VIP for AMBA 2 0 APB Models Verification apb_monitor_vmt page 78 apb_slave_vmt axi_master_vmt DesignWare VIP for AMBA 3 AXI page 79 Verification axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt ethernet_txrx_vmt 10 100 1G 10G Ethernet Models page 82 Verification ethernet_monitor_vmt enethub_fx Ethernet RMI Transceiver and Hub page 83 Verification rmiirs_ fx i2c_txrx_vmt PC Bi Directional Two Wire Bus page 84 Verification pcie_txrx_vmt PCI Express 1 00a page 88 Verification pcie_monitor_vmt pcimaster_fx PCI 2 3 and PCI X 2 0 Simulation Models and Test Verification pcislave_fx Suite page 90 pcimonitor_fx sata_device_vmt
102. its e System address width of 32 or 64 bits e Configuration of system endianness big or little endian can be controlled by external input or set during configuration of component Optional arbiter slave interface Optional internal decoder Programmable arbitration scheme Weighted token Programmable or fixed priority Fair Among Equals Arbitration for up to 15 masters Individual grant signals for each master DesignWare IP Family DW_ahb Advanced High Performance Bus Support for split burst and locked transfers Optional support for early burst termination Configurable support for termination of undefined length bursts by masters of equal or higher priority g m wo lt m gt D 2 N D D 5 Configurable or programmable priority assignments to masters Disabling of masters and protection against self disable Optional support for AMBA memory remap feature Optional support for pausing of the system immediately or when bus is IDLE Contiguous and non contiguous memory allocation options for slaves External debug mode signals giving visibility Also see the block diagram on the following page This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html June 2009 Synopsys Inc 27 DesignWare IP Family DW_ahb Advanced High Performance Bus D
103. iver Macrocell Interface UTMI Level 3 specification 8 bit interface at 60 MHz operation and 16 bit interface at 30 MHz operation Synopsys Inc Hi speed 480 Mbps full speed 12 Mbps and low speed 1 5 Mbps operation is compliant with the USB 2 0 OTG Supplement Supports all OTG features including Host Negotiation Protocol HNP and Session Request Protocol SRP Designed for rapid integration with the Synopsys USB 2 0 Hi Speed OTG controller On chip PLL reduces clock noise and eliminates external clock generator requirement Built in VBUS pulsing and discharge SRP circuitry Built in VBUS threshold comparators Supports off chip charge pump regulator to generate 5 V VBUS signals Designed for minimal power dissipation for low power and bus powered devices Supports Suspend Resume and Remote Wakeup modes Supports USB 2 0 test modes June 2009 DesignWare IP Family dwc_usb2_nanophy USB 2 0 nanoPHY PHY Macro Transceiver Common Squelch Receiver Disconnect Tuning Digital Core Transmitter The dwc_usb2_nanophy datasheet is available at http www synopsys com products designware docs ds c dwe_usb2_nanophy pdf 010 MA June 2009 Synopsys Inc 173 DesignWare IP Family dwc_xaui_phy XAUI PHY IP dwc_xaui_phy XAUI PHY IP The DesignWare XAUI PHY IP is designed for use in any networking or high end computing SoC solutions Designed for the latest high speed backplanes the
104. ller IP based on the Wireless USB specification from the USB IF provides designers with a high performance WiUSB IP core for SoC integration The WiUSB Device Controller enables a wide range of portable electronics or PC peripherals the ability to connect without cables and delivers a conservative timing for implementation into a broad range of ASIC and FPGA technologies Synopsys designed its DesignWare WiUSB IP core using low power flows and a low power architecture with clock gating and two power rails to minimize area and power consumption An extensive verification process which includes simulation and hardware interoperability testing enables Synopsys to deliver a high quality IP core that lowers overall integration risk and shortens time to results As a technical contributor to the Certified Wireless USB specification and a member of the WiMedia Alliance standards committee Synopsys focuses on delivering the highest quality interoperable Wireless USB IP for our customers WiMedia Ultra Wideband e AHB Master or Native interface with UWB MAC DMA engine reduces microprocessor loading and maximizes performance e Supports WiMedia Ultra Wideband UWB Common Radio Platform e FIFO sizes are adjustable to tune for performance or die area to focus on throughput or cost e Support for MIC generation with Wireless USB Protocol UWB AES 128 bit encryption block Adaptation Layer PAL e Modular design for power savings in all layers
105. loped by ARM for rapid development of processor driven systems The AMBA standard also allows a number of bus peripherals and resources to be connected in a consistent way The following is a complete listing of the Synopsys DesignWare IP for the AMBA protocol Component Name DesignWare AMBA Synthesizable IP DW_ahb AHB bus arbitration decode and control logic page 27 DW_ahb_dmac AHB Central Direct Memory Access DMA Controller page 29 DW_ahb_h2h AHB to AHB Bridge page 32 DW_ahb_eh2h Enhanced AHB to AHB Bridge page 30 DW_ahb_icm AHB Multi layer Interconnection Matrix page 34 DW_ahb_ictl AHB Interrupt Controller page 35 DW_apb APB bus decode and bridge page 36 DW_apb_gpio APB General Purpose I O GPIO page 37 DW_apb_i2c APB C Interface page 38 DW_apb_i2s APB IS Interface page 40 DW_apb_ictl APB Interrupt Controller page 41 DW_apb_rap APB Remap amp Pause page 42 DW_apb_rtc APB Real Time Clock page 43 DW_apb_ssi APB Synchronous Serial Interface page 44 DW_apb_timers APB Timer page 46 DW_apb_uart APB UART page 47 DW_apb_wdt APB Watch Dog Timer page 49 DW_memctl Memory Controller page 65 DW_axi Multiple Address Multiple Data AXI Interconnect page 50 DW_axi_gm Generic Interface GIF to AMBA AXI Module page 52 DW_axi_gs AMBA AXI Slave to Generic Interface page 53 DW_axi_hmx Connects AMBA AXI Slave to AHB Master page
106. modes Supports up to 8 SATA devices configurable from 1 to 8 ports Configurable AMBA AHB interface one master and one slave Internal DMA engine per port Supports hardware assisted Native Command Queuing for up to 32 entries Supports 64 bit addressing Supports Port Multiplier with command based switching Optional mechanical presence switch cold presence detect and activity LED support Supports disabling Rx and Tx Data clocks during power down modes June 2009 DesignWare IP Family C Og dwc_sata_ahci S Serial ATA AHCI AHCI HBA SATA Devices PHY Interface DWC_ahsata AHB Master AHB Slave Bus Interface The DesignWare dwc_sata_ahci datasheet is available at http www synopsys com products designware docs ds c dwc_sata_ahci pdf 010 MA June 2009 Synopsys Inc 149 DesignWare IP Family DWC_dsata Serial ATA Device DWC_dsata Serial ATA Device The DesignWare IP for Serial ATA SATA Device Core is compliant to the SATA 2 6 specification for 1 5 and 3 Gb sec and the draft SATA 3 0 specification for 6Gb sec operation ensuring scalability and reuse in your current and future SoC The digital device core offers a well defined flexible programming model that minimizes software overhead during data transfers ensuring maximum operational performance Sample device firmware for various applications is available on request With its integrated DMA this high speed operation
107. mplete range of device behavior e Bus Functional Models BFMs simulate all device bus cycles FlexModels are a type of BFM in the SmartModel Library which you can control using Verilog VHDL OpenVera or C For some devices more than one type of model may be available but these are exceptions not the general rule For detailed information about a specific SmartModel including FlexModels refer to the model s datasheet For an overview of the FlexModels see DesignWare FlexModels on page 96 98 Synopsys Inc June 2009 DesignWare IP Family SmartModel Timing Definitions SmartModel Timing Definitions All SmartModels have at least one timing version To see what timing versions are available for a particular model use the Browser tool to display a list of timing versions for that model If you need a timing version that is not supplied with the library or if you want to back annotate customized delays into the model s simulation you can create a custom timing version as described in User Defined Timing in the Smartmodel Library User s Manual Specific Model Information SmartModel datasheets provide specific user information about each model in the library The model datasheets supplement but do not duplicate the manufacturer s datasheets for the hardware parts In general the model datasheets describe Supported hardware IP and devices Bibliographic sources used to develop the model specific vendor
108. nder e DMA Controller Interface Enables control of programmer the DW_apb_ssi to interface to a e Configurable features DMA controller over the AMBA bus using a handshaking interface for transfer requests o FIFO depth Configurable depth of transmit and receive FIFO buffers from 2 to 256 words deep e Independent masking of interrupts FIFO width fixed at 16 bits Master collision transmit FIFO overflow transmit FIFO empty receive FIFO full receive FIFO underflow and receive FIFO overflow interrupts can all be masked independently o Hardware software slave select Dedicated hardware slave select lines or software control for targeting serial slave device o Number of slave select outputs When operating as serial master 1 to 16 serial slave select output signals can be generated e Multi master contention detection Informs the processor of multiple serial master accesses on the serial o Combined or individual interrupt e Bypass of meta stability flip flops for lines synchronous clocks When the APB o Interrupt polarity Selects clock pclk and the DW_apb_ssi serial clock phase of SPI format serial clock ssi_clk are synchronous directly after reset meta stable flip flops are not used when transferring control signals across these clock domains 44 Synopsys Inc June 2009 DesignWare IP Family
109. nfiguration and up to 15 alternate settings per interface Supports all USB standard commands Easy to add Vendor Class commands Suspend resume logic provided Approximately 12K gates for 5 physical endpoints June 2009 DesignWare IP Family Or dwe_usb_1_1_device S Synthesizable USB 1 1 Device Controller Function Interface Logic Transceive Block L 4 EPINFO Block The dwcore_usb1_ device datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_usb_1_1_device pdf 010 MA June 2009 Synopsys Inc 155 DesignWare IP Family dwc_usb_1_1_ohci_host Synthesizable USB 1 1 OHCI Host Controller dwc_usb_1_1_ohci_host Synthesizable USB 1 1 OHCI Host Controller The Synopsys DesignWare USB 1 1 Host Controller OHCI Synthesizable IP is a set of synthesizable building blocks that ASIC FPGA designers use to implement a complete USB OHCI Host Controller function Features include the following e Silicon proven e Configuration data stored in Port e USB 1 1 compliant Configurable Block e AHB interface e Single 48 MHz input clock e Compatible with Open HCI 1 0 e Simple application interface facilitates specification bridging the host to other system bus such as PCI and the integration of the e Verilog source code controller with chipsets and e Supports low speed and full speed microcontrollers devices e Integrated DPLL e Configurable root hub supporting
110. nnel scopes for capture of eye diagram or coherent capture of periodic signals e Supports loopbacks serial analog for wafer probe and digital Tx to Rx e Supports full analog ATE test on low cost digital tester using only pass fail JTAG vectors The DesignWare dwc_sata_phy datasheet is available at June 2009 http www synopsys com products designware docs ds c dwc_sata_phy pdf Synopsys Inc 153 0109 MA DesignWare IP Family dwc_usb_1_1_device Synthesizable USB 1 1 Device Controller dwc_usb 1 1 device Synthesizable USB 1 1 Device Controller The Synopsys DesignWare USB Device Controller UDC is a set of synthesizable building blocks for implementing a complete USB device interface Features include the following 32 bit Virtual Component Interface VCI Maintains address pointer for endpoint 0 transactions Silicon proven e USB 2 0 Full Speed compatible 154 AMBA High Performance Bus AHB interface enables rapid integration into ARM based designs Option to include internal DMA or interface to external DMA controller Standard register set specification available Applications supported include pointing devices scanners cameras faxes printers speakers monitor Verilog source code Synopsys Inc Supports low speed and full speed devices Programmable number of endpoints Easily configurable endpoint organization Supports up to 15 configurations up to 15 interfaces per co
111. nual VMM for System Verilog June 2009 DesignWare IP Family Serial ATA Models Device and Monitor Design Under Test SATA Host Internal Bus Bus Interface Link Layer Transport Layer SAPIS like I F The DesignWare SATA Verification IP User Manual is available at http www synopsys com products designware docs g m S O o e gt 5 June 2009 Synopsys Inc 93 DesignWare IP Family Serial Input Output Interface Models Tranceiver and Monitor Serial Input Output Interface Models Tranceiver and Monitor SIO TxRx Model sio_txrx_vmt SIO Monitor Model e Full duplex operation sio_monitor_vmt e Fully configurable serial interface e Protocol checking e Both GPIO and SIO port interfaces e Transaction logging e Configurable receive FIFO depth e Watchpoint monitoring e Configurable internal baud clock e Configurable to match TxRx model e Programmable hardware flow control e Configurable internal baud clock e IrDA SIR infrared mode support e Programmable hardware flow control e Error generation injection capability e IrDA SIR infrared mode support e Parity generate check odd even none e Parity generation and checking space mark e Command set control e Robust command set control e Supports VCS Native Testbench e Supports VCS Native Testbench NTB NTB e Supports OpenVera Reference e Supports OpenVera Reference Verification Methodology RVM Verification Method
112. ock domain boundary 4 This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_ahb_h2h Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 33 DesignWare IP Family DW_ahb_icm AHB Multi layer Interconnection Matrix DW_ahb_ icm AHB Multi layer Interconnection Matrix e Layer arbitration and master e User defined parameters multiplexing o AMBA Lite e Input stage address and control o AHB address bus width same holding registers for each layer width on all layers e Mapping of slave response onto o AHB data bus width same width correct layer on each layer e Returning of splits onto the correct o AHB master layers up to 4 layer o Split or non split capable slave e Common clock and reset shared o Slave with without multiple select amongst all layers lines DOESN ay o Slave with without protection control Slave with without burst control Slave with without lock control Layer release scheme Baseline arbitration scheme O O CO 0 0O External arbitration priority control DW_ahb Layer 1 N DW_ahb_icm eang F d Slave DW_ahb 4 lt gt Layer N The DesignWare DW_ahb_icm Databook is available at http www synopsys com products designware docs 34 Synopsys Inc June 2009 De
113. oducts designware docs 46 Synopsys Inc June 2009 DW_apb_uart DesignWare IP Family DW_apb_uart APB Universal Asynchronous Receiver Transmitter APB Universal Asynchronous Receiver Transmitter e AMBA APB interface allows easy integration into AMBA SoC implementations e Configurable APB data bus widths of 8 16 and 32 e Functionality based on the 16550 industry standard that is as follows o Programmable character properties such as number of data bits per character 5 8 optional parity bit with odd or even select and number of stop bits 1 1 5 or 2 o Line break generation and detection o DMA signaling with two programmable modes o Prioritized interrupt identification e Configurable selection of additional DMA interface signals for compatibility with DesignWare DMA interface e Configurable selection of DMA interface signal polarity e Configurable transmit and receive FIFO depths of none 16 32 64 2048 e Configurable internal or external FIFO RAM selection e Programmable FIFO enable disableExternal read enable signal for RAM wake up when using external RAMs e Configurable selection of the use two clocks pcelk and sclk instead of one pelk Programmable Auto Flow Control mode as specified in the 16750 standard Programmable Transmitter Holding Register Empty THRE interrupt mode Configurable IrDA 1 0 SIR mode support with up to 115 2 Kbaud data rate and a pulse duration wi
114. ology RVM e Supports Verification Methodology e Supports Verification Methodology Manual VMM for SystemVerilog Manual VMM for System Verilog Sin a sout sout gt sin cts_n A i rts_n rts_n m cts_n i sio_txrx_vmt DW_apb_uart or DUT A 2701 j gpi n 2 sclk presetn ji g rst_n yyt sio_monitor_vmt The DesignWare SIO Verification IP Databook is available at http www synopsys com products designware docs 94 Synopsys Inc June 2009 USB On The Go Models Host and Device USB Host Model usb_host_vmt e 1 1 2 0 OTG UTMI ULPI HSIC and IC_USB e High full and low speeds e Operation at packet and transaction levels e USB signaling with programmable timers Suspend resume reset signaling Link Power Management LPM Error generation capabilities Programmable inter packet and end to end delays e Supports VCS Native Testbench NTB e Supports Verification Methodology Manual VMM for System Verilog and Open Vera RVM USB On The Go VIP DP DM Interface USB Host or USB Device DesignWare IP Family USB On The Go Models Host and Device USB Device Model usb_device_vmt e 1 1 2 0 OTG UTMI ULPI HSIC and IC_USB e Configures to Non OTG SRP Host only SRP Peripheral only Dual Role OTG A Dual Role OTG B e Operation at packet and transaction levels e High full and low speeds z e Programmable response for endpoints
115. omplies with the IEEE 802 3ae specifications Clause 47 and Clause 48 for XGXS applications and complies with the IEEE 802 3ap specification Clause 36 Clause 45 Clause 48 and Clause 73 for supporting 1OOOB KX L OGBASE KX4 and auto negotiation The core is verified using state of the art methodologies to reduce risk This includes RTL design verification hardware verification and interoperability tests The Ethernet PCS is easily configured with a user friendly application interface which enables you to achieve functional and implementation objectives to meet design requirements such as datapath width and operating frequency Using the Ethernet PCS core with the DesignWare Cores XG MAC a configurable Media Access Control MAC core that supports 1 2 5 and 10 Gigabit Ethernet applications and with the DesignWare XAUI PHY a complete XAUI solution for 10 Gigabit Ethernet enables easy SoC integration into a 10 Gigabit design General Features Receive Path e Compliant with IEEE 802 3ae Clauses 47 e Lane synchronization on received side to and 48 for XGXS applications and IEEE determine code group boundaries 802 3ap Clauses 36 45 48 and 73 for e De skew of all received code groups to an 1000B KX 1OGBASE KX4 and auto alignment pattern with a maximum negotiation allowed skew over 5 cycles e Backplane Ethernet for KX and KX4 KX e 10B 8B decoding per lane only or KX4 only with KX configurations capable of 2 5 Gigabit Ethernet speeds simpl
116. on on receive Multiple Virtual Channels VCs Multiple Traffic Classes TCs Multiple functions Supports bypass cut through and store and forward queues for received TLPs e Configurable for infinite credits for all types of traffic Supports ECRC generation and checking Supports PCI Express beacon and wake up mechanism Supports PCI power management e Supports PCI Express Active State Power Management ASPM Supports PCI Express Advanced Error Reporting Supports all in band Messages for PCI Express Root Port Configurable filtering rules for Posted Non Posted and Completion traffic Supports two application transmit clients by default additional third client optional Access to configuration space registers from the application through the DBI June 2009 K e Automatic generation of Completions for Requests that require Unsupported Request UR or Completer Abort CA responses e Supports external priority arbiter in addition to the internally implemented transmit arbitration More information is available at DesignWare IP Family dwc_pci_express_rc PCI Express Root Port Synthesizable Core e Supports expansion ROM e Implements parity checking on transmit buses memory buses and internal data buses optional http www synopsys com products designware pciexpress html June 2009 Synopsys Inc 141 010 MA DesignWare IP Family dwc_pci_express_sw PCI Express Switch Bri
117. ons Chapter 1 Overview Component groups for the Building Block IP are identified in the following table For more detail refer to the DesignWare Building Blocks Quick Reference Guide Component Group Description Component Type Low Power New components and enhanced DWBB components Synthesizable that incorporate power saving features such as clock RTL gating piplining and operand isolation NOTE A special implementation and license Ipwr DesignWare LowPower is required to enable these new low power components and DWBB low power enhancements Datapath Arithmetic floating point trigonometric and Synthesizable sequential math IP RTL Data Integrity Data integrity IP such as CRC ECC 8b10b Synthesizable RTL Digital Signal FIR and UR filters Synthesizable Processing DSP RTL Application Debugger IP Synthesizable Specific RTL Logic Combinational sequential and control IP Synthesizable RTL Interface Clock Domain Crossing CDC Synthesizable RTL Memory Registers FIFO synchronous and asynchronous Synthesizable RAM and stack IP RTL Test JTAG IP such as boundary scan TAP controller Synthesizable RTL GTECH Technology independent IP library to aid users in Synthesizable developing technology independent parts RTL June 2009 Synopsys Inc 15 Chapter 1 Overview DesignWare IP Family DesignWare AMBA Family of Components AMBA is a standard bus architecture system deve
118. or ERROR responses Configurable Slave Signals up to 16 Slave 0 Address AHB Slave Decoder Interface Read Data MUX Slave j_ j upto15 This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb Databook is available at http www synopsys com products designware docs 36 Synopsys Inc June 2009 DesignWare IP Family DW_apb_gpio APB General Purpose Programmable I O DW_apb_gpio APB General Purpose Programmable I O e Up to 128 independently configurable e Independently controllable port bits g pins If more than 128 pins are e Configurable interrupt mode for Port m required another DW_apb_gpio A L should bota stontatad e Configurable debounce logic with an a e Up to four ports A to D which are external slow clock to debounce N separately configurable interrupts z e Separate data registers and data e Option to generate single or multiple v direction registers for each port interrupts e Configurable hardware and software e GPIO Component Type register control for each port or for each bit of each port e GPIO Component Version register e Configurable reset values on output e Separate auxiliary data input data Boies output and data control for each I O in Hardware Control mode DW_apb_gpio External Data je Port 0 interface gt Interfa
119. ore_pcie_phy 146 DesignWare IP Family overview 13 DesignWare Library Synthesizable IP DW_6811 70 DW_ahb 27 DW_ahb_dmac 29 DW_ahb_eh2h 30 DW_ahb_h2h 32 DW_ahb_icm 34 DW_ahb_ictl 35 DW_apb 36 DW_apb_gpio 37 DW_apb_i2c 38 DW_apb_i2s 40 DW_apb_ictl 41 DW_apb_rap 42 DW_apb_rtc 43 DW_apb_ssi 44 DW_apb_timers 46 DW_apb_uart 47 DW_apb_wadt 49 DW_axi 50 DW_axi_gm 52 DW_axi_gs 53 DW_axi_hmx 54 DW_axi_rs 55 DW_axi_x2h 56 DW_axi_x2p 57 DW_axi_x2x 59 DW_memctl 65 DW_rambist 67 DW8051 72 Memory IP 64 DesignWare Library Verification IP overview 74 DesignWare Memory Models features 85 overview 85 DesignWare Silicon Libraries TSMC Libraries 100 Synopsys Inc June 2009 DesignWare IP Family DesignWare Star IP overview 176 DesignWare Synthesizable Core dwc_1394_av_link 121 dwc_1394_cphy native 123 dwc_ether_xgmac 115 dwc_ether_xgxs_pcs 117 dwc_ethernet_mac10_100_1G_universal dwc_ethernet_macl0_100_universal dwc_jpeg 129 dwc_pci_express_dm 144 dwc_pci_express_ep 138 dwc_pci_express_rc 140 dwc_pci_express_sw 135 136 142 dwe_pci x 133 dwc_usb_1_1_device 154 dwc_usb_1_1_hub native 158 dwc_usb_1_1_ohci_host 156 dwc_usb_2_0_device 164 Og ener a a a 162 DW_6811 70 DW_ahb 27 DW_ahb_dmac 29 DW_ahb_eh2h 30 DW_ahb_h2h 32 DW_ahb_icm 34 DW_ahb_ictl 35 DW_apb 36 DW_apb_gpio 37 DW_apb_i2c 38 DW_apb_i2s 40 DW_apb_ictl 41 DW_apb_rap 42 DW_apb_rtc 43 DW_apb_ssi 44 DW_apb_timers 46 DW_apb_uart 47 DW_apb_wadt 49 DW_
120. orts configure from 1 8 bits Slave ID ports configure from 1 13 bits Includes checks on channel handshake ordering Includes run time control of checkers Transaction logging for AXI Supports configurable coverage analysis and reporting Automated coverage g m S O g e gt u AXI Interconnect axi_interconnect_vmt Shared address shared data SASD Arbiter and Decoder on each channel bus Default Slave device supported Up to 32 Masters and 32 Slaves e Configurable system address bus of 32 or 64 bits Configurable data bus up to 1024 bits All type of responses supported including burst and atomic access e Unlimited memory map for each Slave e Pipelined operation on each channel Synopsys Inc with input stage concept 79 DesignWare IP Family DesignWare VIP for AMBA 3 AXI Master Slave Monitor Interconnect AXI Port Monitor axi_port_monitor_vmt e Interface to a single AXI port e Multiple instantiations e Supports any number of ports more than 64 by using multiple independent instances e Independent of bus architecture multiple address data channels ID ports configurable from 0 to 32 bits Complete AXI Protocol checking Run time control of protocol checking Transaction logs Predefined coverage Sideband support that allows expansion to AXI protocol Using the DesignWare Verification Models for the AMBA 3 AXI Interface is available at 80 http www synopsys com products
121. outstanding split e Zero wait states full bandwidth on transactions sequential access e Multiple HSELs e Zero BUSY cycles full bandwidth e HREADY low alternative to SPLIT secondary burst generation response operation mode poner op Read operations Software interface e Configurable depth read buffer e Interrupt signal on write errors e Pre fetched reads e Interrupt status clear registers e Non prefetched reads e SPLIT response on non sequential Sideband signals non yet aes m e Input sstall pin to qualify an address e Zero wait states full bandwidth on phase for HREADY low operation prefetched read data mode e Output sflush pin to monitor the flushing operation on the read buffer 30 Synopsys Inc June 2009 DesignWare IP Family DW_ahb_eh2h Enhanced AHB to AHB Bridge Write Buffer Secondary AHB Primary AHB Read Buffer g m wo lt m gt D 2 N D D 5 sHCLK mHCLK This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_ahb_eh2h Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 31 DesignWare IP Family DW_ahb_h2h AHB to AHB Bridge DW_ahb_h2h AHB to AHB Bridge System Level Configurable asynchronous or synchronous clocks any clock ratio Four clocking modes for synchronous clock configurations
122. ownsizing AHB data width can be the same as AXI or narrower Configurable synchronous or asynchronous AXI AHB clock compliant operations with any clock ratio e Configurable depths on command data and response queues Clock DomainA lt i Clock Domain B M Master S Slave Interconnect AXI Interconnect port width This component is coreAssembler ready For more information about coreAssembler refer here http www synopsys com products designware core_assembler html The DesignWare DW_axi_x2h Databook is available at http www synopsys com products designware docs 56 Synopsys Inc June 2009 DesignWare IP Family DW_axi_x2p Connects AMBA AXI Slave to AHP Master DW_axi_x2p Connects AMBA AXI Slave to AHP Master e Translates AXI transactions into APB e Flexible address and data port o transfers configurations o Compliance with AMBA 3 APB o AXI data ports 8 16 32 64 128 Protocol Specification Rev 1 0 256 or 512 bits wide a and AMBA AXI Protocol Rev 1 0 o APB data ports 8 16 or 32 bits N from ARM wide z o Configuration option for AMBA 2 o AXI address ports 32 or 64 bits v APB compatibility o APB address ports 32 bits o AXI little or big endian byte ordering byte invariant APB is o APB attempts to honor AXI data always little endian transfer intent on each APB transfer o Accepts simultaneous read write AXI transactions e Buffers AXI transactions o
123. pb_wdt APB Watchdog Timer AMBA APB interface used to allow easy integration into AMBA System on Chip SoC implementations Configurable APB data bus widths of 8 16 and 32 bits Configurable watchdog counter width of 16 to 32 bits Counter counts down from a pre set value to zero to indicate the occurrence of a timeout Optional external clock enable signal to control the rate at which the counter counts If a timeout occurs the DW_apb_wdt can perform one of the following operations o Generate a system reset o First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset DW_apb_wdt DesignWare IP Family DW_apb_wdt APB Watchdog Timer Programmable timeout range period The option of hard coding this value during configuration is available to reduce the register requirements Optional dual programmable timeout period used when the duration waited for the first kick is different than that required for subsequent kicks The option of hard coding these values is available g m wo lt m gt D 2 N D D 5 Programmable and hard coded reset pulse length Prevention of accidental restart of the DW_apb_wdt counter Prevention of accidental disabling of the DW_apb_wdt Optional support for Pause mode with the use of external pause enable signal Test mode signal to decrease the time required during f
124. performance margin and receive sensitivity Consumes very low power up to half the power compared to conventional PCIe PHYs Occupies very small die size up to half the size of conventional PCIe PHYs Provides robust PHY architecture and tolerates wide PVT variations Supports flip chip and low cost wirebond packages Implements low jitter PLL technology with excellent supply isolation Provides low offset high sensitivity receiver with high resolution CDR Supports 10 supply variation e Uses 100 MHz 125 MHz and 156 25 MHz reference clocks More information is available at June 2009 DesignWare IP Family dwcore_pcie_phy PCI Express PHY IP Verification Features Supports verification at PIPE 10b and serial interface Supports automatic handling of transaction data link and physical layer tasks Provides full Requester and Completer functions Supports up to eight virtual channels Supports full LTSSM Link Training Supports power management Supports automatic generation of flow control packets Supports single word read and write transfers to memory I O and configuration space Supports block read and write transfers to memory space Supports message transfers Supports orders packets based on PCI Express ordering rules Supports transaction reordering and out of order completions Supports modification and review of internal address spaces with zero cycle commands Supports error
125. pports all OTG features including Host Negotiation Protocol HNP and Session Request Protocol SRP Synopsys Inc Designed for rapid integration with Synopsys s HS USB 2 0 OTG controller Designed for minimal power dissipation for low power and bus powered devices Verified in 90 nm 130 nm and 180 nm silicon Based on Synopsys s USB Implementers Forum certified HS USB 2 0 PHY architecture June 2009 DesignWare IP Family dwc_usb2_hsotg_phy USB 2 0 Hi Speed OTG PHY Test SYNC Bit Rx Shift Af Interface Detector Unstuffer and Hold HS FS LS NRZI Receivers Decoder Squelch Elasticity Disconnect Buffer Receive State Machine gt Common Tee ransmitter Bock Local Bias Control FS DPLL Logic lt D D D D Pull up Transmit Pull down Mev Veus Logic achine oa NRZI Bit Tx Shift i x Shi HS FS LS Stuffer and Hold Transmitters FS Transceiver MUX i USB 1 1 Single Ended R Serial Interface OTG Transceiver Block USB 2 0 OTG PHY Macro The dwc_usb2_hsotg_phy datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwc_usb2_hsotg_phy pdf 010 MA June 2009 Synopsys Inc 169 DesignWare IP Family dwc_wiusb_device_ controller Wireless USB Device Controller dwc_wiusb device controller Wireless USB Device Controller Synopsys DesignWare Wireless USB WiUSB Device Contro
126. psys Inc 159 DesignWare IP Family dwc_usb_2_ 0 host_subsystem pci ahb Synthesizable USB 2 0 Host Controller dwc_usb_ 2 0 host_subsystem pci ahb Synthesizable USB 2 0 Host Controller The Synopsys DesignWare USB Host Controller UHOST2 is a set of synthesizable building blocks that ASIC FPGA designers use to implement a complete USB 2 0 host for 480 Mbps operation The UHOST2 can be customized and optimized as a stand alone host chip or as an integrated ASIC for applications such as game consoles set top boxes PCs PDAs and telecommunications equipment In addition the design can be easily processed in most technologies and can be easily bridged to any industry standard bus and includes both the PCI and ARM AHB interfaces The application interface screens USB host controller design complexities making it easy to integrate the UHOST2 device to customer target applications Other features include the following General Application e Design methodology supports full scan for testability e All clock synchronization is handled within the controller e coreConsultant utility provided for design configuration e Descriptor and data prefetching configuration option e No bidirectional or three state buses e No level sensitive latches Software e Complies with Enhanced Host Controller Interface EHCI Specification Version 1 0 and the Open Host Controller Interface OHCI Specification Version 1 0a Power Optimiza
127. ptember 1st 2004 8 bit SDR 4 bit DDR 6 pin Serial 3 pin Serial and Carkit The UTMI L3 and ULPI can both exist and be selected by software or only the required interface can be specified during coreConsultant configuration Supports Session Request Protocol SRP Supports Host Negotiation Protocol HNP I2C interface for support of Mini USB Analog Carkit Interface Specification CEA 936 Revision 2 not intended for use with other devices Supports up to 16 bidirectional endpoints including control endpoint 0 Supports up to 16 host channels In Host mode when the number of device endpoints to be supported is more than the number of host channels software can reprogram the channels to support up to 127 devices each having 32 endpoints IN OUT for a maximum of 4 064 endpoints Supports a generic root hub Includes automatic ping capabilities Synopsys Inc Software Features To increase flexibility and reduce gate count certain functions are implemented in software Software assists hardware for Device mode non periodic IN sequencing applicable only in Shared FIFO operation Software handles USB commands SETUP transactions are detected and their command payloads are forwarded to the application for decoding Software handles USB errors Power Optimization Features PHY clock gating support during USB Suspend mode and Session Off mode AHB clock gating support during USB Suspend mode and Session Off mo
128. r 1 OVERVIEW cies esd ee be ceae eden denewsiencds ne eeewneeneeeus DesignWare LIDELY cscs 6h lt deaicbadateaadens sensi saatua sd Pie Block IF nn aoueas due ehus owed iyisi ei rei naa DesignWare AMBA Family of Components Star IP Microprocessor and DSP Cores 4 Micrmcomolles sd cake xan os ERE RONG eee eee et hae Memay EY 25 kee eddbeNe reed eew hee nds ik naa Poi LS 4s hes chase eed es cee ede dened wane SEENI Verification IP for Bus and I O Standards Beer Vericahon IP ocio52 96 e5n6ss 559 sheos o64ceude 26952 Vie VORTIONLY 45 he se cbs CENTE EENE TENENSA EE DesignWare Cores Digital and Mixed Signal DIE 5 89 4 oe ees Chapter 1 AMBA Bus Fabric and Peripheral IP 000 DW_ahb Advanced High Performance Bus DW_ahb_dmac AHB Central Direct Memory Access DMA Controller DW_ahb_eh2h Enhanced AHB to AHB Bridge lt 2262se8eesesseeues DW_ahb_h2h AHB to AHB Bridge 6 sis cavende ae gues steri trpis rids DW_ahb_icm AHB Multi layer Interconnection Matrix DW_ahb ictl AHB Interrupt Controller s 1 44sc08sheacheedesacuees DW_apb Advanced Peripheral BUS iccsacceeeieasceedesasine es June 2009 Synopsys Inc Contents Contents DesignWare IP Family DW_apb_gpio APB General Purpose Programmable VO 2 20 c4sceneeeesesescewes 37 DW_apb_i2c APB C Interface 0 0 ccc eee cece
129. r Drive 1 2V TCBO13LVHPOD Over Drive 1 2V High VT TCBO13LVHPODHVT Low Power Nominal VT TCBO13LPHP Low VT TCBO13LPHPLVT 150nm_ General Purpose Nominal VT TCBO15GHD Low Voltage Nominal VT TCBOISLVHD 104 Synopsys Inc June 2009 DesignWare IP Family Chapter 3 DesignWare Foundry Libraries TSMC Memory Compilers for 9OLP and 65LP Table 3 shows TSMC Nexsys Memory Compilers for 65LP technology Table 3 TSMC 65LP compilers Single Port SRAM W o Redundancy HVT Description Features Single Port SRAM With Redundancy 1K 256K Single Port SRAM W o Redundancy 64 256K Dual Port SRAM 64 1152K 1 Port Register File 16 18K 2 Port Register File 16 72K ROM 64 1152K 64 256K Low Leakage Dual Port SRAM HVT 64 1152K Low Leakage 1 Port Register File HVT 2 Port Register File HVT ROM HVT 16 18K Low Leakage 16 72K Low Leakage 64 1152K Low Leakage Table 4 shows TSMC Nexsys Memory Compilers for 90LP technology Table 4 TSMC 90LP compilers Description Single Port SRAM With Redundancy HD Features 64 512Kbits 0 999um bitcell Single Port SRAM W o Redundancy HD HVT 64 512Kbits 0 999um bitcell Dual Port SRAM 64 256Kbits Dual Port SRAM HVT 64 256Kbits Low Leakage 2 Port Register File 32 32Kbits 2 Port Register File with Redundancy 64 256Kbits 2 Port Register File HVT 32 32Kbits Low Leakage ROM 1K 2Mbi
130. re_pcie_phy PCI Express PHY IP The DesignWare PCI Express PHY IP integrates high speed mixed signal custom CMOS circuitry for easy integration into system on chip designs The high margin robust PCI Express PHY architecture tolerates manufacturing variations such as process voltage and temperature While extremely low in power up to 50 less than conventional PHYs and area the DesignWare PCI Express PHY substantially exceeds the electrical specifications defined in the PCI Express base specification in key performance areas such as jitter and receive sensitivity The unique advanced built in diagnostics and ATE test vectors available in the DesignWare PCI Express PHY enables designers to implement complete at speed production testing without the need for expensive test equipment Furthermore the PCI Express PHY provides on chip visibility into the actual link performance and quickly identifies signal integrity issues This method is superior to the traditional loopback mechanism 146 Synopsys Inc June 2009 PHY Features Fully complies with PCI Express 1 1 2 5 Gbps and 2 0 5 0 Gbps specifications Complies with 1 87 PIPE specification Supports popular 65 90 and 130 nm processes in multiple foundries e 8 and 16 bit PIPE PHY interfaces Supports x1 x4 and x8 lanes Supports all power down modes and spread spectrum clocking Supports beaconing receiver detection and electrical idle Provides excellent
131. ress Models Transcetver arid MONIO 4 446 scr dace cd been er EUS LRI RORIS ERI IESI 88 PCI PCI X Bus Models Waster Slave and Monitor 2 05 cs oe coed be ed oad ed oe os Sa ede ids 90 Serial ATA Models Device ai WICH 4 dato cte cdot awe dc eee aa kGedshedwkesen sa kbods 92 Serial Input Output Interface Models Tranceiver and MOmitor oats end deans Cy eeeeee dee heeds eh eo eres Chk eae 94 USB On The Go Models nel a RVING o ca cieak tka bik eke eked been hee Ree RE beaks 95 DesignWare Pies Ming chcawseuceseeeee snes es eeeesons ETET se suee ee ees 96 Linns OF Tle Ge sc ckceeecdeossueidduecsdeiebecegiieedeueuseets ees 96 Desin Ware SmaiModels 2 625 ceed G5ccdns nsec rbadies 6aGarensskeodeessenns 98 Smart Model Features gg 4 5k G4 aS retis RDI A A ed 98 SmartModel Types wi cb beheaded deebea chee o48s be pe aes CORE EARS ERE SER 98 SmartModel Timing Definitions 445445 ce0 lt seserecsecdon wand inr kpr ERUTEN 99 Specific Model Information sissycesecssirerkiu sareti drite hin CUALES 99 June 2009 Synopsys Inc 5 Contents DesignWare IP Family Chapter 3 DesignWare Foundry Libraries sssssssosssossooessoesoeesoeeoe 100 TOOR A aonar rE E EA a EA 100 TSMC Memory Compilers tor SULP and G5LP 2204 cescies bi ceueded censeeu sien 105 Charered LANAMGS 4400 5 eed cond been eae se ere Puedes 4nd OHS Ewes ease eases 106 Chapter 4 DesignWare Cores Digital and Mixed Signal IP e ee eeee 108 dwc_ethernet_mac10_100_uni
132. ress cycles Loadable configuration space Universal configuration optimized for use in both Host Bridge and Add in Card designs Delayed Read support PCI power management support PCI multifunction support 131 010 MA DesignWare IP Family dwc_pci Universal PCI Controller 132 M PCI Controller PCI Interface bA Multiplexer Master Write Register FIFO PCI ADout Register PCI Bus Master Read Output Register gt FIFO g Mux 9 O i E Master State R haa a am E ba PCI Parity Machine eques t DMA Register 2 pos 2 Configuration Multiplexer Ly Target Read i M gt Registers aee FIFO oO gt Z PCI Bus Target Write gt Register FIFO m gt Address FIFO gt Target State hm commend Machine Address Compare VY The dwcore_pci datasheet is available at http www synopsys com cgi bin dwcores pdfr1 cgi file dwe_pci pdf Synopsys Inc June 2009 DesignWare IP Family Q Og dwc_pci x S Synthesizable PCI X Controller and Test Environment dwc_pci x Synthesizable PCI X Controller and Test Environment The DesignWare IP core for PCI X is available as synthesizable RTL source which enables designers to implement a complete PCI X interface PCI X is highly suitable in a wide ran
133. rive impedance and ODT The product datasheet can be downloaded from the following site http www synopsys com designware June 2009 K DesignWare IP Family DDR2 DDR SDRAM PHY and Controller DDR2 DDR SDRAM Complete Solution DDR2 DDR SDRAM PHY and Controller DDR2 DDR SDRAM Complete Solution The DesignWare IP for DDR2 DDR interfaces is a complete silicon proven system level IP interface solution for ASICs ASSPs System on Chip SoC and System in Package applications requiring high performance DDR2 DDR SDRAM interfaces operating at up to 1066 Mpbs This silicon proven DDR2 DDR SDRAM complete solution includes scalable digital controller IP an integrated hard macro PHY and verification IP The pre qualified and interoperable interface unburdens developers from memory subsystem design issues that come into play when memory data rates move beyond 400 Mbps enabling them to focus their energy on value added development while significantly reducing design risk and development time Highlights Solution e Complete integration DDR2 DDR SDRAM Memory Interface solution including digital controller PHY and verification IP e High performance operating at up to 1066 Mbps e Integrated solution eases timing closure with optimized interface between PHY and controller e Silicon proven PHYs are available in leading 65nm 90nm and 130nm process technologies Digital Controller e Advanced command re ordering and scheduling
134. riven systems AMBA also allows a number of bus peripherals and resources to be connected in a consistent way The following Synopsys DesignWare AMBA 2 0 and 3 0 compliant components are briefly described in this section Component Name DesignWare AMBA Synthesizable IP DW_ahb AHB bus arbitration decode and control logic page 27 DW_ahb_dmac AHB Central Direct Memory Access DMA Controller page 29 DW_ahb_eh2h Enhanced AHB to AHB Bridge page 30 DW_ahb_h2h AHB to AHB Bridge page 32 DW_ahb_icm AHB Multi layer Interconnection Matrix page 34 DW_ahb _ ictl AHB Interrupt Controller page 35 DW_apb APB bus decode and bridge page 36 DW_apb_gpio APB General Purpose I O GPIO page 37 DW_apb_i2c APB C Interface page 38 DW_apb_i2s APB IPS Interface page 40 DW_apb_ictl APB Interrupt Controller page 41 DW_apb_rap APB Remap amp Pause page 42 DW_apb_rtc APB Real Time Clock page 43 DW_apb_ssi APB Synchronous Serial Interface page 44 DW_apb_timers APB Timer page 46 June 2009 Synopsys Inc 25 DesignWare IP Family Component Name DesignWare AMBA Synthesizable IP DW_apb_uart APB UART page 47 DW_apb_wdt APB Watch Dog Timer page 49 DW_memctl Memory Controller page 65 DW_axi Multiple Address Multiple Data AXI Interconnect page 50 DW_axi_gm Generic Interface GIF to AMBA AXI Module page 52 DW_axi_gs AMBA AXI Slave to Generic Interface
135. rtModels The SmartModel Library is a collection of over 3 000 binary behavioral models of standard integrated circuits supporting more than 12 000 different devices The library features models of devices from the world s leading semiconductor manufacturers including microprocessors controllers peripherals memories and general purpose logic SmartModels connect to logic simulators through the SWIFT interface which is integrated with over 30 commercial simulators including Synopsys VCS and VCS MX Cadence Verilog XL and Mentor Graphics QuickSim II Instead of simulating devices at the gate level SmartModels represent integrated circuits and system buses as black boxes that accept input stimulus and respond with appropriate output behavior Such behavioral models are distributed in object code form because they provide improved performance over gate level models while at the same time protecting the proprietary designs created by semiconductor vendors All SmartModels and model datasheets are listed in the IP Directory http www synopsys com dw ipsearch php SmartModel Features e Support for Windows allowing you to view and change internal register values e Consistent SWIFT interface across most simulators e Simulation efficient behavorial level models e Industry standard as well as configurable timing behavior SmartModel Types There are two basic types of SmartModels e Full functional Models FFMs simulate the co
136. ry Interface IP solution including digital controller PHY and VIP Services data rates up to 1066 Mbps Area optimized PHY IP for lower performance range of DDR3 Integrated solution eases timing closure with optimized interface between PHY and controller PHY IP is available in leading 65nm process technologies Digital Controller 126 DDR2 3 Lite PHY IP is compatible with DesignWare Protocol PCTL and Memory Controller MCTL Automatic scheduling of activate and precharge commands PCTL MCTL Automatic scheduling of refreshes PCTL MCTL Advanced command re ordering and scheduling to maximize bus utilization MCTL Configurable multi port arbiter supporting multiple independent user ports MCTL Programmable ECC generation checking and correction MCTL Supports AMBA AXI and Native Interface NIF PCTL MCTL Synopsys Inc PHY IP Configurable PHY IP easily goes around die corner o PHY IP compiler available o Lane based PHY IP architecture for maximum flexibility Precision master slave delay locked loops DLLs provide 900 phases of the clock strobes o Automatic calibration o Immune to voltage and temperature drift o Ultra low jitter Per bit timing adjustment on data and strobe signals to improve timing margin Data training for DQS gating Real time DQS drift detection and compensation PVT compensated I Os using DDR3 ZQ pad with external precision resistor o Calibrates output d
137. s DesignWare Verification IP can also be licensed individually and is available as part of the VCS Verification Library Component Name Component Description Model Technology DesignWare Bus amp I O Standards ahb_bus_vmt DesignWare VIP for AMBA 2 0 AHB Models VMT ahb_master_vmt page 76 ahb_monitor_vmt ahb_slave_vmt apb_master_vmt DesignWare VIP for AMBA 2 0 APB Models VMT apb_monitor_vmt page 78 apb_slave_vmt axi_master_vmt DesignWare VIP for AMBA 3 AXI page 79 VMT axi_slave_vmt axi_monitor_vmt axi_interconnect_vmt axi_port_monitor_vmt ethernet_txrx_vmt 10 100 1G 10G Ethernet Models page 82 VMT ethernet_monitor_vmt enethub_fx rmiirs_fx Ethernet RMII Transceiver and Hub page 83 FlexModels page 96 i2c_txrx_vmt IC Bi Directional Two Wire Bus page 84 VMT 74 Synopsys Inc June 2009 DesignWare IP Family Chapter 2 DesignWare Library Verification IP pcie_txrx_vmt PCI Express 2 0 protocol page 88 VMT pcie_monitor_vmt pcimaster_fx PCI PCI X Simulation Models and Test Suite FlexModels page 96 pcislave_fx page 90 pcimonitor_fx sata_device_vmt Serial ATA Models page 92 VMT sata_monitor_vmt sio_txrx_vmt Serial Input Output Interface Models page 94 VMT sio_monitor_vmt usb_host_vmt USB On The Go Models 1 1 2 0 OTG UTMI VMT usb_device_vmt and UTMI page 95 usb_monitor_vmt g DesignWare Design Views of Star IP Microproce
138. s II Processor Core page 182 Synthesizable RTL a Verification models of these cores are included in the DesignWare Library and the DesignWare Verification Library Synthesizable RTL of these cores are available through the Star IP Program For more information visit http www synopsys com designware star_ip html June 2009 Synopsys Inc 17 Chapter 1 Overview DesignWare IP Family Microcontrollers Component Name Component Description Component Type DW_6811 8 Bit Microcontroller page 70 Synthesizable RTL DW8051 8 Bit Microcontroller page 72 Synthesizable RTL Memory IP Component Name Component Description Component Type Memory Models DesignWare contains thousands of pre verified Verification Models memory models with over 10 000 devices from more than 25 vendors page 85 DW_memctl DesignWare Memory Controller page 65 Synthesizable RTL DW_rambist DesignWare Memory BIST solution page 67 Synthesizable RTL DW Memory Building DesignWare Building Block IP contains many Synthesizable RTL Block IP memory related IP For details see the DesignWare Building Blocks Quick Reference Guide To view the complete DesignWare memory portfolio refer to the following http www synopsys com memorycentral Foundry Libraries Synopsys is teaming with foundry leaders to provide DesignWare Library licensees access to standard cells and I Os optimized for the
139. si1 DW_apb_ssi i_ssi2 m Li DW_apb_uart 2 i_uart1 DW_ahb_dma DW_apb_uart AHB2 Lite i_uart2 DW_apb_gpio SIO_BIM i_gpio see tests DW_apb_rtc i_rtc DW_apb_timers i_timers DW_memctl DW_memcetl DW_apb_ictl Static Dynamic Static i_ictl i_memctl_ i_memctl_ Slave s slave m master Slave BFM 2 The DW_apb_ssi component i_ssil in the example subsystem can also communicate with an EEPROM as opposed to another DW_apb_ssi i_ssi2 June 2009 Synopsys Inc 63 DesignWare IP Family Memory IP The following Memory IP are briefly described in this section Component Name Component Description Component Type DW_memctl Memory Controller page 65 Synthesizable RTL DW_rambist DesignWare Memory BIST solution page 67 Synthesizable RTL To view the complete DesignWare memory portfolio refer to the following http www synopsys com products designware memorycentral 64 Synopsys Inc June 2009 DW_memctl Memory Controller Supports AHB data widths of 32 64 or 128 bits AHB address width of 32 bits Supports pin based little or big endian modes of operation Supports separate or shared memory address and or data buses between SDRAM and Static memories Glueless connection to all JEDEC compliant SDRAM Supports up to 16 SDRAM address bits SDR SDRAM Mobile SDRAM and SyncFlas
140. signWare IP Family DW_ahb_ictl AHB Interrupt Controller DW_ahb_ictl AHB Interrupt Controller e 2 to 64 IRQ normal interrupt sources e Priority filtering optional g e to 8 FIQ fast interrupt sources e Masking m optional e Scan mode optional e Vectored interrupts optional e Programmable interrupt priorities D e Software interrupts after configuration X e Configuration ID registers e Encoded parameters a e Note Does not support split transfers DW_ahb_ictl IRQ Generation Interrupt FIQ Registers Generation Vector Generation amp Masking This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler htm The DesignWare DW_ahb_ictl Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 35 DesignWare IP Family DW_apb Advanced Peripheral Bus DW_apb Advanced Peripheral Bus e APB Bridge and APB bus functionality e Supports 32 64 128 256 AHB data incorporated buses e AHB slave e Supports 8 16 and 32 bit APB data e Supports up to 16 APB slaves buses e Supports single and burst AHB e Supports big and little endian AHB transfers systems e Supports synchronous hclk pclk hcelk e Supports little endian APB slaves i is an integer multiple of pclk e The AHB slave side does not support SPLIT RETRY
141. ss_sw PCI Express Switch Bridge Synthesizable Core 2 04 4 i0ce4s0dsdeeseadas 142 dwc_pci_express_dm PCI Express RC EP Dual Mode Synthesizable Core 0000055 144 dwcore_pcie_phy 6 Synopsys Inc June 2009 DesignWare IP Family Contents Pi Bite PHY IF a io ne a i ee 146 dwc_sata_ahci Dera ATA AHCI opererat irr DENIRA EDENI EEO ERE ARORA 148 DWC_dsata Pee E ike E ees eeGiee ts ouseeorsedsaoanw ee E E 150 PL e a kee chee eeteeutelentebiewblldeketdeteatieukise eee bees 150 dwc_sata_phy SO Pd Ferrera HF OE TRS ew 152 dwc_usb_1_1 device Synthesizable USE 1 1 Device Controller lt c dicadaseisestsncsigei anes 154 dwc_usb_1_1_ohci_host Synthesizable USB 1 1 OHCI Host Controller c 22 esiccesedesaceen des 156 dwc_usb_1_1_hub native synthesizable USB 1 1 Hub Controller cucceaccsccteccieacenaceeeasceds 158 dwc_usb_2_0_host_subsystem pci ahb Synthesizable USB 2 0 Host Controller c0c2cncieeseeicdenseundiwise ged 160 dwc_usb_2_0_hs_otg_subsystem ahb Synthesizable Hi Speed USB On The Go OTG Controller Subsystem 162 dwc_usb_2_0_device Synthesizable USB 2 0 Device Controller c 62s1506 00060 es44eeeuues bees 164 dwc_usb2_phy USB 2 0 Transceiver Macrocell Interface PHY 20 lt s046 os0edeanees aees 166 dwc_usb2_hsotg_phy USB 20 Hi Speed OTG PHY 422 ccdnaensetodsebeseecdaeb ERAS RETRE 168 dwc_wiusb_device_controller Wireless USB Device Controller crscrsoricidcesireacsesiieadetiitiai 170 dwc_usb2_nanophy VSB CoP c
142. ssors and DSP Core z DW_IBM460 S PowerPC 440 32 Bit Microprocessor Core from Compiled model S DW_IBM405 S IBM page 177 fa DW_CoolFlux CoolFlux 24 bit DSP Core from NXP Compiled model page 179 5 Ea DesignWare Memory Access to the full suite of memory IP is made Memory Models available through DesignWare Memory Central a memory focused Web site that lets designers download DesignWare Memory IP and documentation Visit Memory Central at http www synopsys com products designware memorycentral SmartModel Library is a collection of over 3 000 binary behavioral SmartModels page 98 models of standard integrated circuits supporting more than 12 000 different devices Verification Models The following datasheet pages are ordered alphabetically and briefly describe each Verification Model June 2009 Synopsys Inc 75 DesignWare IP Family DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect All Models AHB Bus Interconnect e Multiple command streams ahb_bus_vmt e Verilog VHDL or OpenVera Up to 15 Masters and 15 Slaves testbenches Configurable message formatting Event driven testbenches Support VCS Native Testbench NTB Support OpenVera Reference Verification Methodology RVM e Support Verification Methodology Manual VMM for System Verilog Unlimited Slave memory maps Priority based arbitra
143. ster WRITE response channel READ data channel Response Buffer Generic Response Channel v This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html Documentation for this product is available at http www synopsys com products designware docs 52 Synopsys Inc June 2009 DesignWare IP Family DW_axi_gs AMBA AXI Slave to Generic Interface GIF DW_axi_gs AMBA AXI Slave to Generic Interface GIF e Full support of the AXI protocol e Independent request and response GIF g e Configurable number of exclusive channels m access monitors e Configurable number of outstanding e Full support of AXI low power transactions a interface e Synchronous clock support including N a e Two way flow control slower GIF clock J e Configurable microarchitecture U e Synchronous point to point communication on GIF e Configurable I O signals to support simple peripherals DW_axi_gs Request datapath a gt WRITE data channel Write Data Buffer ic R t Ch WRITE address channel T Generic Request Chanine 2 READ address channel Request Buffer MEE cere Se ae Custom Response datapath Third Party WRITE response channel Slave rr ES BID Buffer RID Buffer READ data channel Generic Response Channel 4 Response Buffer
144. ster Default Slave Arbiter Decoder Write Mux and Read Mux are part of the AHB Bus VIP model The DesignWare AHB Verification IP Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 77 DesignWare IP Family DesignWare AMBA APB Models Master Slave Monitor DesignWare AMBA APB Models Master Slave Monitor All Models e Constrained random test transactions e Multiple command streams using random file memory or FIFO e Verilog VHDL or OpenVera data testbenches e Internal or external data mux e Configurable message formatting e Error injection capability e Event driven testbenches e Support VCS Native Testbench NTB APB Slave apb_slave_vmt e Support OpenVera Reference Data Address width 8 32 bits Configurable memory fill patterns Big endian or little endian FIFO memory at any memory location Verification Methodology RVM e Support Verification Methodology Manual VMM for System Verilog APB Master apb_master_vmt APB Monitor apb_monitor_vmt e 1 16 Slaves e Transaction logging e Data Address width 8 32 bits e Protocol checking e Incremental coverage reporting APB Monitor AAAAAA APB APB Slave 1 Slave 2 AHB APB Master gt Ye AHB APB Bridge Slave 3 Slave 4 The DesignWare APB Verification IP Databook is available at http www synopsys com products designware docs 78 Synopsys Inc June 2009
145. stomization Synthesis scripts Verilog source code Approximately 14K gates 3 port Proven in ASIC applications 123 010 MA DesignWare IP Family dwc_1394_cphy native Synthesizable IEEE 1394 Cable PHY y y CPHYSHELL Low Speed Digital Block CPHY Port Controller PHY Link PHY PE Interface Port Controller b Controller Link Port Mux 4 lt Interface Pi lt q PHY Registers Port Controller Lp Mixed Signal Interface The dwcore_1394_cphy datasheet is available at 124 http www synopsys com cgi bin dwcores pdfrl cgi file dwce_1394_cphy native pdf Synopsys Inc June 2009 DesignWare IP Family Q Og DDR2 3 Lite SDRAM Complete Solution S DDR2 3 Lite SDRAM Complete Solution DDR2 3 Lite SDRAM Complete Solution DDR2 3 Lite SDRAM Complete Solution The DesignWare DDR2 3 Lite IP is a complete silicon proven system level IP interface solution for ASICs ASSPs System on Chip SoC and System in Package applications requiring highperformance DDR2 3 SDRAM interfaces operating at up to 1066 Mbps The DDR2 3 Lite IP part of the comprehensive DesignWare DDRn IP product line is ideal for systems that do not require the higher performance or lower power consumption of DDR3 It is targeted at designs that are initially going to market using DDR2 IP with the ability to tr
146. t In Self Test Interfaces e IEEE 1149 1 TAP controller interface e Two clock interface one for a slower TAP I F second for at speed BIST execution e Optional MUX block that supports either embedded multiplexers inside the memories or user specified multiplexers e Flexible configuration for embedded MUX block providing a better interface to memory control signals with different widths and polarities Error Diagnostics e Pause on first and subsequent failures mode serial debugging e Failing address and data may be scanned out for examination e Quick debug mode continue on failures mode failing addresses not recorded e Parallel debug port to observe the failing memory data bits BIST Tests e User choice of March LR 14n March C 10n and MATS 6n e Custom user defined patterns option e Optional SRAM retention test Sn delay auto pause mechanism e Selection of background and complement background data patterns June 2009 DesignWare IP Family DW_rambist Memory Built In Self Test e Default sequence or run time selection of individual test e Improved test execution time through reduced memory read write cycles each access to synchronous memory occurs in one clock cycle e Configuration of Mode Register reset value to provide easy power up tests e Higher speed clock frequency Supported Memories e Synchronous and asynchronous SRAM e Asymmetrical pipelining support up to four stages
147. t and use a microprocessor model within a DesignWare AMBA subsystem QuickStart currently includes two example designs e QuickStart_SingleLayer This is a single layer subsystem This subsystem is an enhanced version of the QuickStart example that was included in the DesignWare AMBA 2004 05 release e QuickStart_MultiLayer This is a multi layer subsystem with DMA PCI USB ICM AHB bridge and other peripheral components The QuickStart_SingleLayer and QuickStart_MultiLayer subsystems include pre configured instances of DesignWare AMBA Bus IP and peripheral components as shown in the following figures respectively For more information about using DesignWare AMBA QuickStart refer to the DesignWare AMBA QuickStart_SingleLayer Guide and the DesignWare AMBA QuickStart_MultiLayer Guide June 2009 Synopsys Inc 61 g m wo lt m gt D 2 N D D i DesignWare IP Family DesignWare AMBA QuickStart Collection of example designs for AMBA subsystems Testbench Clock AHB testbench v Configuration Generation Monitor and Stimulus i_intr2 i_memctl k memory y 0 AHB Master DW_ahb_ictl DW_memctl SRAM BFM MyExtAhbMstr1 3 int 1 OF S93 Int regs SRAM CPU Model Decoder 4 4 SRAM mO sO AHB Slave Paras 25 SDRAM gt BFM APB Monitor f l i_remap DW
148. te credits for all types of traffic ECRC generation and checking PCI Express beacon and wake up mechanism PCI power management PCI Express Active State Power Management ASPM PCI Express Advanced Error Reporting e MSI and MSI X All in band Messages for the current mode EP or RC Configurable filtering rules for Posted Non Posted and Completion traffic June 2009 June 2009 Configurable BAR filtering I O filtering and configuration filtering e Programmable completion timeout Supports up to three independent client interfaces for transmitting TLPs Access to configuration space registers and external application registers through local bus controller Automatic generation of Completions for devices that require only simple access to an application register block EP mode More information is available at DesignWare IP Family dwc_pci_express_dm PCI Express RC EP Dual Mode Synthesizable Core Automatic generation of Completions for Requests that require Unsupported Request UR or Completer Abort CA responses RC mode Selectable arbitration mechanism for transmit interfaces or use an external arbiter Supports expansion ROM Implements parity checking on transmit buses memory buses and internal data buses optional http www synopsys com products designware pciexpress html Synopsys Inc 145 0109 MA DesignWare IP Family dwcore_pcie_phy PCI Express PHY IP dwco
149. ter and receive sensitivity The unique advanced built in diagnostics and ATE test vectors available in the DesignWare SATA PHY enables designers to implement complete at speed production testing without the need for expensive test equipment Furthermore the DesignWare SATA PHY provides on chip visibility into the actual link performance and quickly identifies signal integrity issues This method is superior to the traditional loopback mechanism 152 Synopsys Inc June 2009 PHY Features Provides excellent performance margin and receive sensitivity Implements very low power design up to half the power compared to conventional PHYs Provides ATE test vectors for complete at speed production testing Includes on board scope and diagnostics for fast system verification Supports popular 130 nm 90 nm and 65 nm processes Occupies small cost effective die size e Supports hot pluggable devices Implements low jitter PLL technology with excellent supply isolation Provides low offset high sensitivity receiver with high resolution Implements robust architecture that tolerates wide PVT variations DesignWare IP Family dwc_sata_phy Serial ATA PHY IP Test Features e Provides built in per channel BERTs e Supports flexible fixed and random pattern generation e Supports error counting on patterns or disparity e Supports digital phase or voltage margining bathtub curves e Provides built in per cha
150. tion 160 e ULPI Reduced Power mode with ULPI wrapper operates at 60 MHz with the remainder of the Root Hub operating at 30 MHz Synopsys Inc e AHB interface to the application e Complies with the AMBA Specification Revision 2 0 Bus Interface Unit BIU handles retry error and split transactions on the AHB As an AHB Master supports 8 or 32 bit data transfers on the AHB Supports 32 bit addressing on the AHB e USB 2 0 Supported Features e Complies with the USB 2 0 Specification e Supports ping and split transactions e UTMI or ULPI interface to the PHY e UTMI PHY interface clock supports 30 MHz operation for a 16 bit interface or 60 MHz operation for an 8 bit interface ULPI PHY interface clock supports 60 MHz operation for both 8 and 4 bit interfaces June 2009 DesignWare IP Family Co Ry dwc_usb_2_ 0 host_subsystem pci ahb Synthesizable USB 2 0 Host Controller UHOST2 Subsystem PCI Controller with AHB VCI evel Vel gt USB Target Bridge Decoder 5z Device AHB VCI USB 2 0 S Initiator EHCI g Transaction LN S gt Host 3 FL USB Controller am Controller ppr Device with AHB VCI PCI DER Controller E DA Device g with Asynch Control 9 a 0 0 aa FIFO N and Status 5 Q ON Interface Na
151. tion algorithm All types of Master transfers All types of Slave responses Configurable early burst termination and undefined length burst termination AHB Master ahb_master_vmt e Data width 8 1024 bits e Single or burst transfers e Burst rebuild capability e Constrained random test transactions using random file memory or FIFO data e Compare with expected data AHB Slave ahb_slave_vmt e OK Error Retry or Split responses Programmable wait states Configurable memory fill patterns FIFO memory at any memory location Constrained random test transactions using random file memory or FIFO data AHB Monitor ahb_monitor_vmt e Cycle based or transaction based event monitoring e Protocol checking e Incremental coverage reporting 76 Synopsys Inc June 2009 DesignWare IP Family DesignWare AMBA AHB Models Master Slave Monitor Bus Interconnect Dummy f Default 2 Decoder x Master a Slave Read AHB g _ AHB Master 1 a i T slave 1 a e l AHB gt AHB Master n lt 4 a Slave n Write A Mux A SS SS SS g m S O o e gt Ea L e gt Arbiter a lt t Ww 4 t y q AHB Monitor D Used when the Slave is being certified Used when the Master is being certified Dummy Ma
152. tivity on the sideband and signals e Can be set up as an OCP core or system slave OCP Monitor Model ocp_monitor_svt e Observes dataflow transactions and control signals e Generates log files and coverage reports to track verification progress e Log files show a record of observed transactions e Functional coverage reports June 2009 DesignWare IP Family Open Core Protocol OCP Models Master Slave and Monitor g m S O o e gt 5 June 2009 Synopsys Inc 87 DesignWare IP Family PCI Express Models Transceiver and Monitor PCI Express Models Transceiver and Monitor pcie_txrx_vmt pcie_monitor_vmt Models Overview e PCI Express is a high speed serial interface replacement for the older PCI and PCI X parallel bus standards e The transceiver is fully bus functional and can verify PCI Express endpoints switches and root complex devices e The monitor provides detailed transaction logging and coverage of the PCI Express Compliance Checklist Major Features e Verification at PHY MAC interface of x1 x2 x4 x8 x12 x16 lanes e Supports Gen2 features and data rates Full Link Training LTSSM support e Protocol and compliance monitor which generates transaction and symbol log files e Full Requester and Completer functions e Multiple transfers initiated concurrently e Automatically generates flow control packets e Automatically handles Transaction Data Link and Physical l
153. tolerant chrt13sio222 Staggered 1 2 3 3V 5V tolerant chrt13sio0322 Inline PCI 133MHz I Os 1 2 3 3V chrt13pc322 Staggered PCI 133MHz I Os 1 2 3 3V chrt13spc322 RAM Compilers High Density synchronous single port chrt13rs 162 Synchronous dual port chrt13rd142 Asynchronous two port chrt13rt162 ROM Compiler Synchronous diffusion programmable chrt13ro152 106 Synopsys Inc June 2009 DesignWare IP Family Table 5 Chartered Libraries Continued Chapter 3 DesignWare Foundry Libraries Tech Library Description Name 0 18 um Standard Cells Logic csm180s120 I Os In line 1 8 3 3V 5V tolerant csm18i0221 Staggered 1 8 3 3V 5V tolerant csm18sio0221 In line PCI I Os 1 8 3 3V 5V tolerant csm18pc220 Staggered PCI I Os 1 8 3 3V 5V tolerant csm18spc220 RAM Compilers Single port HD synchronous csm18rs161 Dual port synchronous csm18rd131 Two port asynchronous csm18rt151 ROM Compiler Synchronous diffusion programmable csm18ro151 0 25 um Standard Cells Logic csm250s163 I Os In line 3 3V 5V tolerant csm2510223 Staggered 3 3V 5V tolerant csm25si0223 In line PCI 3 3V 5V tolerant csm25pc223 Staggered PCI 3 3V 5V tolerant csm25spc223 RAM Compilers Single port synchronous csm25rs144 Single port HD synchronous csm25rs160 Dual port asynchronous csm25rd114 Two port asynchronous csm25rt134 Single port asynchronous csm25ral 14 ROM Compiler Synchronous di
154. ts ROM HVT 1K 2Mbits Low Leakage June 2009 Synopsys Inc 105 z T e c gt Q lt o o n Chapter 3 DesignWare Foundry Libraries Chartered Libraries Synopsys and Chartered Semiconductor have partnered to develop license and distribute a complete offering of high performance standard cells I Os and memory compilers optimized for Chartered s 0 35um 0 25um 0 18um and 0 13um process offerings Based on Synopsys library development technology and methodology the Chartered libraries are a set of technology aggressive high performance and high density foundation intellectual property IP specifically targeted for manufacture of IC designs at Chartered Semiconductor Table 5 lists the library components which includes standard cells I Os and memory compilers All are optimized to Chartered s process design rules The libraries have been silicon tested to validate maximum performance and reliability The libraries support an open electronic design automation EDA environment DesignWare IP Family The Chartered Libraries distributed through DesignWare are an ideal solution for both all digital integrated circuit and mixed signal designs Table 5 Chartered Libraries Tech Library Description Name 0 13 um Standard Cells Logic chrt13fs 122 I Os Inline 1 2 2 5V 3 3V tolerant chrt1310222 Inline 1 2 3 3V 5V tolerant chrt13i0322 Staggered 1 2 2 5V 3 3V
155. ts all AHB burst types in AHB frames slave interface Y p 7 e Software can select the type of AHB PHY Interface Features burst in an AHB master interface e Supports SMU MII RMII interfaces e Receive checksum offload for IP e MDIO Master Interface optional for TCP UDP packets PHY device configuration and management June 2009 Synopsys Inc 111 DesignWare IP Family dwc_ethernet_mac10 100 universal Ethernet MAC 10 100 Universal Core Master Interface Optional PHY Interfaces MAC RMII MAC i CSR Interface MAC CORE The dwc_ethernet_mac10_100_universal datasheet is available at http www synopsys com cgi bin dwcores pdfrl cgi file dwc_ether_mac10_100_universal pdf 112 Synopsys Inc June 2009 DesignWare IP Family G Og 5 dwc_ether_mac10 100 1000 universal Ethernet MAC 10 100 1000 Universal Core dwc_ether_maci0 100 1000 universal Ethernet MAC 10 100 1000 Universal Core The Synopsys DesignWare Ethernet MAC 10 100 1G Universal Core enables the host to communicate using the Gigabit Ethernet protocol IEEE 802 3 The Ethernet MAC 10 100 1G Universal Core is composed of three main layers the Gigabit Ethernet Media Access Controller GMAC the MAC Transaction Layer MTL and the MAC DMA Controller MDC Other features include the following General Features PHY Interface Features e Compliant with IEEE 1588 2002 and e IEEE 802 3 compliant GMII RGMII TEEE 1588 2008 Precision Clock MII RMI
156. uirements and system architectures Its high performance architecture is optimized for low latency and low gate count The Synopsys Ethernet MAC 10 100 Universal Core enables Ethernet functionality for switch NIC and system on chip applications The DesignWare Ethernet MAC implements more functionality than standard Ethernet MACs including MAC station management address check IP checksum offload engine time stamping and Control Status Register CSR blocks These additional features provide higher level system functionality usually implemented in firmware or using separate products With these additional capabilities the Ethernet MAC simplifies system implementation General Features Application Interface e Complies with the full IEEE Features 802 3 2002 specification e Data interface configurable to support e Supports IEEE 802 1Q VLAN tag FIFO interface or AHB interface detection for reception frames e CSR interface configurable to e Supports CSMA CD protocol for AHBTM Slave or APBTM Slave half duplex operation 32 bit interface e Supports Full Duplex Only e Supports 32 64 128 bit data on the configuration AHB master and slave ports e Supports IEEE 802 3x flow control for e Supports SPLIT RETRY and ERROR full duplex operation AHB responses in AHB master e Supports IEEE 1588 2002 precision interface clock synchronization e Configurable for little or big endian e Optional module for LAN wakeup modes g frames and AMD Magic Packet e Suppor
157. unctional test coreAssembler ready APB Register Interface Block Interrupt amp System Reset Control The DesignWare DW_apb_i2c Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 49 DesignWare IP Family DW_axi Multiple Address Multiple Data AXI Interconnect DW_axi Multiple Address Multiple Data AXI Interconnect e High performance multiple address e Data widths of 8 16 32 64 128 256 bus multiple data MAMD bus AXI and 512 bits interconnect architecture e Equal data widths of master and slave e Configurable number of master and ports slave ports up to 16 each e Support for data bursts up to 256 beats Configurable system decoder e Single clock frequency for all master optional and slave ports e Configurable master and slave e Equal data widths of master and slave priorities used for arbitration ports configured statically or driven dynamically throush inp t ports e No buffering of AXI channel payload in interconnect e Default slave included Tocked transter support e Configurable slave visibility per master Automatically optimized in single AXI e Built in out of order deadlock master subsystems avoidance f e Optional user sideband signals for each e Address width of 32 or 64 bits AXI channel allowing additional e coreAssembler ready control status per channel for example data parit
158. up e Support for SMI interrupts to 15 downstream ports e Approximately 25K gates with 2 ports 156 Synopsys Inc June 2009 DesignWare IP Family Oh dwc_usb_1_1_ohci_host S Synthesizable USB 1 1 OHCI Host Controller A l RCFG_RegData 32 xl i APP_SADR Ue i Control ei 2 APP_SData 3 X i y SB List ED Processor TD_Data 32 Block ED TD_Status 32 Teos HC_Data 8 HCI Bus a DF_Data 8 DF_Data 8 8 8 Ext FIFO Status Addr 6 lt HCF_Data FIFO_Data FIFO 64x8 The dwcore_usb1_host datasheet is available at http www synopsys com cgi bin dwcores pdfrl cgi file dwc_usb_1_1_ohci_host pdf 0109 MA June 2009 Synopsys Inc 157 DesignWare IP Family dwc_usb_1_1_hub native Synthesizable USB 1 1 Hub Controller dwc_usb_1_1_hub native Synthesizable USB 1 1 Hub Controller The Synopsys DesignWare USB Hub UH01 is a set of synthesizable building blocks that ASIC FPGA designers use to implement a complete USB Hub The RapidScript utility enables designers to easily configure the device by setting the number of downstream ports The Synopsys UHO1 product consists of the Hub Repeater and the Hub Controller The Hub Repeater is responsible for connectivity setup and tear down and supports exception handling such as bus fault detection recovery and connect disconnect detection The Hub Controller provides the
159. upports descriptor based DMA interface Separate clocks for bus interface and card interface for easy integration Supports 8 to 4096 deep configurable FIFO Single FIFO optimized for area and power savings without compromising performance Default register based FIFO RAM which can be replaced by FAB specific dual port SRAM Supports FIFO over run and under run prevention by stopping card clock In AHB mode supports pin based little endian and big endian modes Verification Environment Features VMT based AMBA bus functional models and monitors VMT based MMC SDMem SDIO and SDCombo CE ATA BFMs can be used in VERA Verilog Environment Exhaustive constrained random and directed testing Verified with AMBA Compliance Test 100 Line and FSM coverage 99 9 ATPG coverage SD MMC_CE ATA independent SD MMC protocol specific bus drive APIs 119 010 MA DesignWare IP Family dwc_mobile_storage On Os Mobile Storage Host Controller Example Linux Demonstration Features e SD MMC CE ATA specific host driver APIs ok BIU clu Regulators Interrupts Power status Switches socket oO write APB AHB X protect Int rface E e Gah 4 gt fe a card 3 protect i ra am DMA z Cards Interface optional cclk 4 gt ccmd l cdata Pies e m cclk_in_drv optional Clock c
160. ut through and store and forward queues for received TLPs Configurable for infinite credits for all types of traffic Supports ECRC checking and error reporting optional Supports PCI Express beacon and wake up mechanism Supports PCI power management e Supports PCI Express Active State Power Management ASPM Supports PCI Express Advanced Error Reporting Full PCI Express Message passing and processing Configurable filtering rules for Posted Non Posted and Completion traffic June 2009 DesignWare IP Family Q Og dwc_pci_express_sw S PCI Express Switch Bridge Synthesizable Core e Configurable BAR filtering I O e Supports external priority arbiter filtering configuration filtering round robin used for internal e Supports two application transmit arbitration clients by default additional third e Supports expansion ROM client optional e Implements parity checking on e Access to configuration space transmit buses memory buses and registers and external application internal data buses optional registers through local bus controller More information is available at http www synopsys com products designware pciexpress html 010 MA June 2009 Synopsys Inc 143 DesignWare IP Family dwc_pci_express_dm PCI Express RC EP Dual Mode Synthesizable Core dwc_pci_express dm PCI Express RC EP Dual Mode Synthesizable Core The DesignWare Dual Mode Root Port Endpoint Core for PCI Express 2 0 is
161. v Isochronous Control Control and Status Unit Reai T CSRs Control The dwcore_1394_avlink datasheet is available at http www synopsys com cgi bin dweores pdfr1 cgi file dwc_1394_av_link pdf 122 Synopsys Inc June 2009 K dwc_1394_cphy native Synthesizable IEEE 1394 Cable PHY DesignWare IP Family dwc_1394_cphy native Synthesizable IEEE 1394 Cable PHY The Synopsys industry proven DesignWare 1394 Cable Physical Layer CPHY enables devices to interface with the 1394 serial bus The 1394 CPHY is a synthesizable RTL design that provides all the necessary features to implement the complete IEEE 1394a specification for the digital portion of the cable PHY CPHY can be combined with an analog PHY and used in a stand alone ASIC or it can be integrated into an ASIC with a Link Layer controller CPHY is well suited for multimedia and mass storage applications requiring high bandwidth and is suitable for a wide range of applications from basic low cost devices 1 port to sophisticated high performance ASICs up to 16 ports Other features include the following e Complete IEEE 1394a support e Supports 100 200 400 Mbps bus speeds e Configurable number of ports 1 to 16 e Simple silicon proven interface to mixed signal analog circuitry e Supports suspend resume protocol June 2009 e Supports Link On LPS protocol Synopsys Inc RapidScript configuration utility for design cu
162. ve C Interface Master Slave DMA Controller Interface TX FIFO Interrupts RX FIFO RX Filter 2 Clock k a Generator ebug Synopsys Inc June 2009 DesignWare IP Family DW_apb_i2c APB I C Interface This component is coreAssembler ready For more information about coreAssembler http www synopsys com products designware core_assembler html The DesignWare DW_apb_i2c Databook is available at http www synopsys com products designware docs g m wo lt m gt D a N D D 5 June 2009 Synopsys Inc 39 DesignWare IP Family DW_apb_i2s APBI S Bus aaa DW_apb_i2s APB I S Bus e APB data bus widths of 8 16 and 32 bits e IS transmitter and or receiver based on the Philips I7S serial protocol e Configurable number of stereo channels up to 4 for both transmitter and receiver e Full duplex communication due to the independence of transmitter and receiver e Asynchronous clocking of APB bus and I S sclk e Master or slave mode of operation e Audio data resolutions of 12 16 20 24 and 32 bits e External sclk gating and enable signals e Configurable FIFO depth of 2 4 8 16 bits e Configurable support for programmable DMA registers e Programmable FIFO thresholds e Component parameters for configurable software driver support DW_apb_i2s APB Slave S Interface Register Block TX FIFOs 25 Transmitter R
163. versal Ethernet MAC 10 100 Universal Core 3 n60 cccetee ss cbesase segue heoascdes 111 dwc_ether_mac10_100_1000_universal Ethernet MAC 10 100 1000 Universal Core 0 0 0 0 ee eee eee 113 dwc_ether_xgmac XOMAC 10G Ethernet MAC icsiee cee a cdeeei ede dsahebentaned bax anes 115 dwc_ethernet_pcs Ethernet Extension SUb l4yer og dc kde eeceundeeeetenSegesddeseaseh cas 117 dwc_mobile_storage Mobile Storage Host Controller 6 sos 459 504s ode Gos bR OES DOW roos DEX 119 dwc_1394_av_link Synthesizable IEEE 1394 AVLink DTCP cciccecsewswisaeieiwaeeereds 121 dwc_1394_cphy native Synthesizable IEEE 1394 Cable PHY cecossectse een set eecw ee teteeneds 123 DDR2 3 Lite SDRAM Complete Solution DDR2 3 Lite SDRAM Complete Solution 220 eee eee 125 DDR2 DDR SDRAM PHY and Controller DDR2 DDR SDRAM Complete Solution 0220 02 e eee eee 127 dwc_jpeg Synthesizable IJPEGCUODEC oe ch ese rhe ee hee se eden eee cies 129 dwc_pci Ae nc nwe hes aren I EN ewe a Nn rE ss Kes 131 dwc_pci x Synthesizable PCI X Controller and Test Environment 133 PClIe AHB Bridge PCI Express to AMBA 2 0 AHB Bridge 2 cocecadaseisestseasaveiancs 135 PCle AXI Bridge PCI Express to AMBA 3 AXI Bridge i242 0dcehedveusceeuddeadeeysseas 136 dwc_pci_express_ep PCI Express Endpoint Synthesizable Core 222 c2scienteacenaseensceas 138 dwc_pci_express_rc PCI Express Root Port Synthesizable Core cisrccscsiiricroiceni derei 140 dwc_pci_expre
164. vides coverage of PCI Express compliance checklist Coverage reports show checks passed checks failed and checks not hit e Logging of PCI Express transactions Configurable to show start time stop time direction packet type sequence credits and many other packet attributes e Records coverage for TLP types TESTBENCH new_buffer pcie_txrx_vmt ae read write_mem Write stops ueue here posted g m S O o e gt Ea I Requester Completer I T A P m Tx L H Queue Y Ack i Queue I TL Link PHY I PHY Rx Results 7 Queue L P Buffer iq L H y O viy PCI Express Monitor pcie_monitor_vmt TL Header Data Transaction and Symbol LL Seq Header Data CRC Log Files PHY STP Seq Header Data CRC END The DesignWare PCI Express Verification IP Databook is available at http www synopsys com products designware docs June 2009 Synopsys Inc 89 DesignWare IP Family PCI PCI X Bus Models Master Slave and Monitor PCI PCI X Bus Models Master Slave and Monitor Overview The Synopsys PCI PCI X FlexModel set consists of three separate PCI PCI X FlexModels and a set of system level testbenches The models support the PCI 2 3 and the PCI X 1 0 and 2 0 specifications e p
165. y The following page contains a block diagram of the DW_axi Documentation for this product is available at http www synopsys com products designware docs 50 Synopsys Inc June 2009 DesignWare IP Family DW_axi Multiple Address Multiple Data AXI Interconnect Default AXI Master Port 1 Slave Read Address Channel Write Address Channel Write Data Channel Write Response Channel g w lt m gt D a N D D 5 my sSnNODO Write Data Channel Read Data Channel Write Response Channel yzmaconw i up to 16 j up to 16 Figure 1 DW_axi Block Diagram June 2009 Synopsys Inc 51 DesignWare IP Family DW_axi_gm Generic Interface GIF to AMBA AXI Module DW_axi_gm Generic Interface GIF to AMBA AXI Module e Full support of the AXI protocol e Independent request and response GIF except for exclusive accesses channels e Full support of AXI low power e Unlimited outstanding transactions interface e Synchronous clock support including e Two way flow control slower GIF clock e Synchronous point to point e Configurable micro architecture communication on generic interface e Transaction block control GIF A DW_axi_gm Request datapath WRITE data ch data channe Write Data Buffer Generic Request Channel WRITE address channel 2 a READ address channel Request Buffer Custom E aa Third Party Response datapath Ma
166. y by a clock frequency increase e Link status reporting for faulty conditions e Clock rate compensation in which idle characters are inserted or deleted to Transmit Path compensate for the frequency variations between the recovered clock and the local clock maximum allowed variation between clocks is 200 ppm e Conversion of dual data rate XGMII to single data rate 312 5 MHz data bus e Optional conversion of double data width e Optional conversion the single data rate 64 bit XGMII operating with 156 25 32 bit at 312 5 MHz to double data MHz clock to single data rate 32 bit width 64 bit at 156 25 MHz epee aon Wua Se ECS e Diagnostic logic for BER testing in e Conversion of XGMII idle control compliance to the IEEE 802 3ae Annex characters to a randomized sequence of 48A specification eed Caen eae alignment e Supports XGMII internal loop back for i debugging receive to transmit digital path and clock rate compensation e 8B 10B encoding to convert the binary MID Manaeedvie Homes MMD data to 10 bit encoded data for each lane e Error status and statistics for debug e Supports loopback control of the SERDES PHY transmit to receive 010 MA June 2009 Synopsys Inc 117 DesignWare IP Family Co dwc_ethernet_pcs lt Os Ethernet Extension Sub layer TX Interface SERDES PHY Analog TX Path RX Interface SERDES PHY Analog TX Path Ss Control Status y SEREDES PHY 1 0 Control Register CSR Sets CSR Port
167. zable RTL PCI Cores dwc_pci 32 64 bit 33 66 MHz PCI Core page 131 Synthesizable RTL dwce_pci x 32 64 bit 133 MHz PCI X Core Synthesizable RTL page 133 PCI Express Cores dwc_pci_express_ep PCI Express Endpoint Core page 138 Synthesizable RTL dwc_pci_express_rc PCI Express Root Port Core page 140 Synthesizable RTL dwc_pci_express_sw PCI Express Switch Port Core page 142 Synthesizable RTL dwc_pci_express_dm PCI Express Dual Mode Core page 144 Synthesizable RTL dwcore_pcie_phy PCI Express PHY Core page 146 Hard IP 22 Synopsys Inc June 2009 DesignWare IP Family Chapter 1 Overview SATA Cores dwc_sata_ahci SATA Host page 148 Synthesizable RTL DWC_dsata SATA Host page 150 Synthesizable RTL dwc_sata_phy SATA PHY page 152 Hard IP USB Cores dwc_usb_1_1_device USB 1 1 Device Controller page 154 Synthesizable RTL dwc_usb_1_1_ohci_host USB 1 1 OHCI Host Controller page 156 Synthesizable RTL dwc_usb_1_1_hub native USB 1 1 Hub Controller page 158 Synthesizable RTL dwc_usb_2_0_host_subsyste USB 2 0 Host Controller UHOST2 Synthesizable RTL m pci ahb page 160 dwc_usb_2_0_hs_otg_subsyst USB 2 0 Hi Speed On the Go Controller Synthesizable RTL em ahb Subsystem page 162 dwc_usb_2_0_device USB 2 0 Device Controller page 164 Synthesizable RTL dwc_usb2_phy USB 2 0 PHY page 166 Hard IP dwc_usb2_hsotg_phy USB 2 0 Hi Speed On the Go PH

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