COM-1931 L/S-band burst spread-spectrum modem
Contents
1. Demodulator Configuration Tx Rx loopback REGI121 7 enable 1 or disable 0 loopback test mode Nominal chip rate 32 bit integer expressed as fehip_rate_rx lite a 27 Tak aac The maximum practical chip rate is fak aac 2 The maximum allowed error between transmitted and received chip rate is 100ppm REG91 LSB REG94 MSB Linear feedback shift register A initialization REG97 LSB REG98 2 0 MSb Nominal channel Nominal I channel symbol rate defined as symbol rate Loud diii T 2 feik ade e iae 3 REG103 LSB REG106 MSB I channel spreading Approximate 1 e rounded ratio of chip rate symbol rate factor Range 3 2047 Processing gain Note to effectively achieve this processing gain the code period must be longer than one symbol duration REGI11 LSB REGI 12 4 0 MSb Nominal input center The nominal center frequency is a fixed frequency offset applied to the input samples It is used for frequency f fine frequency corrections for example to correct clock drifts 32 bit signed integer 2 s complement representation expressed as L2 L In addition to this fixed value an optional time dependent frequency profile can be entered future REGI15 LSB REGI18 MSB Spectrum inversion Invert Q bit 0 off on REGI19 0 AGC response time Users can to optimize AGC response time while avoiding instabilities depends on external factors such as gain signal filtering at the RF fro2. 512 In particular selecting the fax aa demod clock as phase signed fek ade real time sampling clock allows one to have the Ene sss pes The ComScope user manual is available at 2 Code replica 8 bit 2 512 spread input 161 436 411 386 361 336 311 286 261 236 211 186 161 136 111 86 61 36 il 14 39 4 Symbol tracking 8 bit 1 sample 512 phase accumulated signed symbol Trace 3 signals Format Nominal Buffer sampling length 461 436 411 386 361 336 311 286 261 236 211 186 161 136 111 86 61 35 11 14 3 Plot Settings Trigger Settings rate samp les Autoscale X Min X Max Y Min Y Max Rescale Signal Representation Threshold Edge Position B v 336 335 65 64 1 v 1 bit Unsigned w 1 v Rising 90 w 1 I channel after 8 bit 2 samples FFT frequency signed chip Close Apply Changes Re arm Trigger Force Trigger Plot correction resampling and channel LPF Q channel signed Q symbol phase correction signed symbol accumulated 13 EJ ComScope COM1831A Burst mode DSSS modem Trace Settings Trace Signal Representation Sampling Clock Decimation Visible Plot style Color _ Export D i g ita l Test P O i n ts 2 2 w 8 bit Signed w Nominal see specs w 1 1 OFF v Lines N X ammm 51 31 11 9 29 49 69 89 109 129 149 169 189 209 229 249 269 289 309 329 349 369 389 409 429 The test points are only accessible after opening the 127 A enclo
3. Gaithersburg Maryland 20878 1676 U S A Telephone 240 631 1111 Facsimile 240 631 1676 E mail sales comblock com 19
4. NAND flash sectors must be less than 10 SREGI6 18 0x22 00 87 Power supply check SREG4 0 PGOOD1 RF1 3 1V SREG4 1 PGOOD2 IF1 _3 1V SREG4 2 PGOOD3 A_ 4 75V SREG4 3 PGOOD4 MOD 44 8V SREG4 4 PGOOD5 TX SYNTH _ 3 3V SREG4 5 PGOOD6 RX 4 75V SREG4 6 PGOOD7 RX SYNTH 3 3V Overall valid response 0x7F Received signal strength indicator 12 bit number Practical range 75 to 0 dBm after LNA and first bandpass filter See RF POWER DETI in schematic SREGS LSB SREG6 3 0 MSB Received power at RF mixer Power detection at RF mixer See RF POWER DET 2 in schematic IF output power Power detection at IF after bandpass filter and IF gain control See IF POWER DET in schematic SREG9 LSB SREG10 3 0 MSB Transmit power Power detection at the RF transmit output See TX POWER DET in schematic SREG11 LSB SREG12 3 0 MSB RF synthesizers locked 1 when locked SREG19 0 rx synthesizer locked SREG19 1 tx synthesizer locked DSSS demodulator monitoring FEC decoder input BER The burst mode FEC decoder computes the input BER prior to decoding Mesasured in measurement a frame This method works with any bit sequence SREG20 LSB SREG22 MSB SREG23 0 1 when the BERT is synchronized with the received PRBS 11 test sequence Bit error rate Monitors the BER number of bit errors over 10 000 received bits when the modulator is sending a PRBS 11 test sequence SREG24 LSB 27 MSB Number of tran
5. is an external 10 MHz signal supplied through the front panel B firmware option or an internal 19 2 MHz VC TCXO A firmware option Both A and B firmware options are pre loaded and can be switched easily Warning when selected as external frequency reference the 10 MHz frequency reference must be present prior to powering on the modem Click on the button below to switch between installed firmware options A ComBlock Control Center File Operations Functions Help x wm e us Output 10 MHz frequency reference A 10 MHz frequency reference signal can be multiplexed with RF signals on the RF input to an external LNB and RF output to an external BUC The same 10 MHz is also available as an output on the front panel labeled 10 MHz OUT Each one of these three clocks signals can be enabled or disabled by software command Spreading codes Each burst undergoes spectrum spreading with user selected pseudo random codes All fields preambles sync word data are spread Spreading codes are user selected among a group of 2047 period Gold codes irrespective of the symbol rate The codes are selected by their 11 bit A and C registers initialization Register A I Channel Register B Q Channel Code Register C Note Stage contents indicate initial conditions indicates user unique initial conditions Burst format The modulator input consists of a 512 bit fixed length payload data frame
6. received over LAN UDP The payload data frame is encoded with a convolutional code K 9 rate 2 resulting in an encoded frame of length 1040 bits including the 16 tail bits When transmitting a single frame the frame 1s encapsulated in a spread spectrum burst comprising four distinct fields e no data preamble e toggling bits preamble e 32 bit synchronization field e 1040 bit encoded payload field 512 bit data from UDP port e x 1040 bit FEC encoded data E 010101 preamble 000000 preamble 32 bit sync When transmitting multiple frames follow on frames are appended without preamble separated only with a 32 bit sync word Transmission timing A data frame received over UDP is transmitted without delay The transmission time uncertainty is small lt TBD us The user application is therefore fully in control of the burst scheduling for example to prevent collisions in a multi node network When the modulator is configured in PRBS11 test mode the PRBS11 pseudo random test sequence is generated internally packetized in 512 bit frame 15 and transmitted one frame every 100 ms The UDP input is ignored while in this mode Input elastic buffer When more than 512 bits of payload data 1s needed multiple data frames can be queued for transmission in the elastic buffer The modulator expects any follow on frame to be entirely within the input elastic buffer before the previous frame transmission is comp
7. the range 1 106 M is a multiplier in the range 2 0 to 64 0 by steps of 1 0 Fixed point format 7 3 O is a divider in the range 2 0 to 128 0 by steps of 1 0 Fixed point format 7 3 Note the graphical use interface computes the best values for M D and O fak tx recommended range 80 160 MHz REG48 6 0 D REG49 M 7 0 REG50 1 0 M 9 8 REGS1 O 7 0 REG52 2 0 O 10 8 Chip rate The modulator chip rate is in the form fenip rate tx fek tx 2 nip rate tx where n ranges from 1 2 samples per chip to 15 chip rate far tx 32768 n is defined in REG53 3 0 Linear feedback shift register initialization As per 1 REGS54 LSB REG55 2 0 MSb Q Code REG56 LSB REG57 2 0 MSb I channel symbol rate The I channel symbol rate can be set independently of the spreading code period as 32 j rate i fsymbol rate up E Tak tx Q channel symbol rate The Q channel symbol rate can be set independently of the spreading code period as T iobol vase Lobo rats i 27 fak tx REG69 LSB REG66 MSB Output center frequency The modulated signal center frequency can be shifted in frequency fe 32 bit signed integer 2 s complement representation expressed as f 27 fork tx REG73 LSB REG70 MSB Sinusoidal frequency In addition to the fixed frequency offset above a sinusoidal frequency offset can be generated to offset mimic Doppler rate in highly mobile applications This offset is characterized by two paramet
8. Com Block COM 1931 L S band burst spread spectrum transceiver Key Features L S band modem to send and receive short UDP frames over wireless satellite or cable Direct Sequence Spread Spectrum DSSS modulation Nominal frequency of operation 950 2175 MHz for direct connection to external LNB or BUC Customization to other frequency bands is possible Burst mode operation o fixed length 512 bit data frames from to LAN UDP ports o Multiple frames transmitted efficiently with only 32 symbol separation Acquisition 1600 symbol preamble with no apriori knowledge of arrival time Large frequency acquisition range chip rate 64 or 1 8 symbol rate whichever is smaller with no apriori knowedge End to end latency 2672 symbol modulation symbol rate For example 1 2ms at 2 5Msymbols s Programmable chip rate up to 79 5 Mchips s 2047 chip Gold codes Data rate practical range from chip rate 2047 to chip rate 30 Supply voltage 18 36VDC with reverse voltage and surge protection e Frequency reference internal TCXO or input for an external higher stability 10 MHz frequency reference e Built in tools PRBS 11 pseudo random test sequence BER tester AWGN generator internal loopback mode e Monitoring o Carrier frequency error o SNR o BER ComScope enabled key internal signals can be captured in real time and displayed on host computer For the latest data sheet please
9. P address EA 16 Gateway address 172 16 Destination IP address 172 15 1 68l destination port 1024 MAC address 00 00 00 00 00 00 Configuration Advanced Alternatively users can access the full set of configuration features by specifying 8 bit control registers as listed below These control registers can be set manually through the ComBlock Control Center Advanced configuration or by software using the ComBlock API see www comblock com download M amp C reference pdf All control registers are read write Definitions for the Control registers and Status registers are provided below Control Registers The module configuration parameters are stored in volatile SRT command or non volatile memory SRG command The stored configuration is automatically loaded up at power up All control registers are read write Note several multi byte fields like the IP addresses are enacted upon re writing to the last control register REGIA1 Several key parameters are computed on the basis of the 160 MHz ADC clock far aac or the 120 MHz internal processing clock fax p Configuration Stored frequency Preselected transmitter or receiver frequency fo one of eight stored frequencies fo Valid range 925 MHz 2 175 GHz expressed in Hz REGO bit 7 0 LSB REGI bit 15 8 REG2 bit 23 16 REG3 bit 31 24 MSB Receiver frequency selection Use to switch the receiver center freque
10. ailable Utilization Schematics FF 38577 126800 30 42 LUT 35720 63400 56 34 The board schematics are available on line at Pe EE en ips http comblock com download com_1900schematics pdf 1 0 132 285 46 32 BRAM 33 135 24 44 DSP48 57 240 23 75 Configuration Management BUFG 9 32 28 12 P l l l MMCM 4 6 66 67 This specification is to be used in conjunction with VHDL software revision 1 and ComBlock control center revision 3 09q and above The maximum chip rate is limited by the FPGA technology For example nearly 80 Mchips s for It is possible to read back the option and version of Xilinx Artix 7 1 speed XC7A100T 1 the FPGA configuration currently active Using the ComBlock Control Center highlight the COM The IP core which includes all VHDL source code 1931 module then go to the advanced settings The can be purchased separately It is not needed to option and version are listed at the bottom of the operate the ready to use COM 1931 transceiver configuration panel See www comblock com download coml 831 soft pdf Troubleshooting Checklist Demodulator can t achieve lock even at high signal to noise ratios e Make sure the modulator baseband I Q signals do not saturate as such saturation would strongly distort the modulation phase information this is a phase demodulator 18 P ComBlock Ordering Information COM 1931 L S band burst spread spectrum transceiver ECCN 5A001 b 3 MSS 845 Quince Orchard Boulevard Ste Ne
11. ced settings window Two firmware options are available for this receiver A firmware uses an internal VCTCXO frequency reference B firmware option requires an external 10 MHz frequency reference Recovery The toggle button under the backpanel can be used to a prevent the FPGA configuration at power up This can be useful if a bad FPGA configuration was loaded which resulted in loss of communication with the user b reset the LANI IP address to 172 16 1 128 To prevent the FPGA configuration at power up turn off power Toggle the button Turn on power wait second then toggle the button a second time To reset the LANI IP address to a factory default of 172 16 1 128 Turn on power Toggle the button wait at least 30 seconds during which time the red led blinks then toggle the button a second time Wait another 10 seconds then cycle power off on Interfaces 10 100 1000 Ethernet LAN for data monitoring and control 10 MHz frequency reference input 10 MHz frequency reference output RJ45 Supports auto MDIX to alleviate the need for crossover cable 10 MHz frequency reference input for frequency synthesis Sinewave clipped sinewave or squarewave SMA female connector Input is AC coupled Minimum level 0 6Vpp Maximum level 3 3Vpp 10 MHz frequency reference output generated either from the 10 MHz frequency reference input B firmware option or from the internal TCXO A firmware
12. ers amplitude and period The amplitude a frequency is expressed as f amplitude 27 fer tx in the following control registers REG74 LSB REG77 MSB The period is expressed as 2 fak T in the following control registers REG78 LSB REG81 MSB Digital Signal gain 16 bit amplitude scaling factor for the modulated signal The maximum level should be adjusted to prevent saturation The settings may vary slightly with the selected chip rate Please check for saturation see test points when changing either the chip rate or the signal gain REG82 LSB REG83 MSB Additive White Gaussian 16 bit amplitude scaling factor for additive white Gaussian noise eae Because of the potential for saturation please check for saturation see test points when changing this parameter REG84 LSB REG85 MSB Input selection 0 from UDP port 1024 1 internal pseudo random test sequence 100ms repetition 2 internal pseudo random test sequence continuous transmission 3 unmodulated test mode carrier only Spectrum inversion Invert Q bit 0 off on REG86 3 TX ENB control The TX ENB signal at the interface controls the RF transmit circuit During normal operations 9 the transmitter and ancillary circuits RF LO are muted outside of a transmit burst REG86 5 0 However during tests the transmitter can be forced to stay ON at all times for example when the AWGN is generated within REG86 5 1
13. lete so as to avoid transmissing another long preamble In this case the modulator only inserts a 32 bit synchronization word between payload frames The input elastic buffer size 1s 8Kbit large enough for 7 encoded frames Symbol rate The symbol rate refers to the coded stream The symbol rate can be set independently of the chip rate and code period The demodulator includes an autonomous symbol tracking loop separate from the code tracking loop Frequency acquisition amp tracking The frequency acquisition range depends on the chip rate and symbol rate as defined by chip rate 64 or 1 8 symbol rate whichever is smaller with no apriori knowedge Once locked the carrier tracking loops tracks the carrier phase over a very wide frequency range Modulation Baseline BPSK spread with I channel code Customization The transceiver design can be customized to meet alternate customer requirements The customizable features are e Custom radio frequency bands within 400 MHz 3GHz at no extra charge e Trade off preamble length versus acquisition threshold Eb No The baseline preamble is 1600 symbols for a threshold E No of 16 dB PER gt 99 9 Lower threshold are achievable by increasing the integration time and thus the preamble length down to E No of 5 dB for a preamble length of 32K symbols Customization has to be specified and quoted at the time of order Load Software Updates From time t
14. ment Receiver RF AGC loop 0 open loop RF path gain is fixed by control registers 1 AGC on Out of range conditions are detected at the RF mixer and IF power detector REG39 l Receiver IFAGC loop 0 open loop IF1 path gain is fixed by control registers 1 AGC on Out of range conditions are detected at the IF power detector Transmitter ON REG39 6 LNB supply The transceiver is capable of supplying up to 500mA at 13VDC or 18VDC to an external LNB This supply voltage is multiplexed with the RF input signal onto the RF Rx input 0 LNB supply off 1 LNB supply on 0 LNB supply 13V vs 18V 0 13VDC LNB supply 1 18VDC LNB supply REG43 1 General Parameters Configuration Internal External 10 MHz output generated from 10 MHz input B firmware option or 19 2 MHz TCXO A frequency reference firmware option REG46 1 enable 1 disable 0 CLKREF OUT special connector on front panel REG46 2 enable 1 disable 0 CLK LNB multiplexed with received signal REG46 3 enable 1 disable 0 CLK TX multiplexed modulated transmit signal 10 MHz FEC encoding K 9 rate convolutional code with zero tail bits 0 bypassed FEC encoding enabled REG47 0 FEC decoding 0 bypassed 1 FEC decoding enabled REG47 1 Modulator Processing clock Modulator processing clock Also serves as DAC sampling clock fok tx Expressed as as Tak tx Tok p M D T Q where D is an integer divider in
15. ncy among preselected values Range 0 through 7 REG6 2 0 Transmitter frequency Use to switch the transmitter center frequency among preselected values selection Range 0 through 7 The rx tx frequencies change is enacted upon writing to REG6 REG6 6 4 Stored frequency Seven additional preselected frequencies fx x through 7 Same format as f REG 3 4 x bits 7 0 LSB REG 4 4 x bits 15 8 REG 5 4 x bits 23 16 REG 6 4 x bits 31 24 MSB Receiver RF Gain Initial RF gain before the RF AGC takes over 12 bit 0 for the minimum gain 4095 for the maximum gain The receiver RF gain change is enacted upon writing to REGS REG4 bits 7 0 LSB REGS5 3 0 bits 11 8 Receiver IF Gain Initial IF gain before the IF AGC takes over 12 bit 0 for the minimum gain 4095 for the maximum gain The receiver IF gain change is enacted upon writing to REG36 REG35 bits 7 0 LSB REG36 3 0 bits 11 8 Receiver LNA Gain LNA gain 10 bit 0 for the minimum gain 1023 for the maximum gain The receiver IF gain change is enacted upon writing to REG41 REG40 bits 7 0 LSB REG41 3 0 bits 11 8 Transmitter ALC target The transmit gain is automatically adjusted so that the measured tx power equals this field The transmitter gain change is enacted upon writing to REG38 REG37 bits 7 0 LSB REG38 3 0 bits 11 8 Receiver LNA AGC loop 0 open loop LNA path gain is fixed by control registers 1 AGC on Gain is adjusted on the basis of the RSSI measure
16. nt end and chip rate The AGC DAC gain control signal is updated as follows 0 every chip every 2 input chips 2 every 4 input chips 3 every 8 input chips etc 10 every 1000 input chips Valid range 0 to 14 REG121 4 0 Network Interface Configuration LAN MAC REG123 To ensure uniqueness of MAC address The MAC address most significant bytes are tied to the address LSB FPGA DNA ID However since Xilinx cannot guarantee the DNA ID uniqueness this register can be set at the time of manufacturing to ensure uniqueness Static IP address 4 byte IPv4 address Example 0x AC 10 01 80 designates address 172 16 1 128 REG124 MSB REG125 REG126 REG127 LSB REG128 MSB REGI31 LSB Gateway IP REG132 MSB REG135 LSB address Destination IP 4 byte IPv4 address address Destination IP address for UDP frames with decoded data REG136 MSB REG139 LSB Destination ports 1 channel data is routed to this user defined port number REG140 LSB REG141 MSB Note several multi byte fields like the IP addresses are enacted upon re writing to the last control register REG141 Monitoring Status Registers Parameters Monitoring Hardware self check At power up the hardware platform performs a quick self check The result is stored in status registers SREGO 4 SREG16 18 Properly operating hardware will result in the following sequence being displayed SREGO SREG4 01 F1 ID xx 7F where xx bad
17. o time ComBlock software updates are released To manually update the software highlight the ComBlock and click on the Swiss army knife button ComBlock Control Center A File Operations Functions Help x ow Z e 6 HH BS The receiver can store multiple personalities The list of personalities stored within the ComBlock Flash memory will be shown upon clicking on the Swiss army knife button COM1931A band burst spread spectrum transceiver Personalities Index Personality Option Default Authorized Boot Protection Address 1 0013 Yes Ma 0 2 1931 A D Yes Ma 2830400 3 1905 Yes No 19660800 4 1905 Yes No 29491200 Add Remove Modify Personality Index Personality Option Password Set Default Add ModiFy The default personality loaded at power up or after a reboot is identified by a D in the Default column Any unprotected personality can be updated while the Default personality is running Select the personality index and click on the Add Modify button 16 CombBlock Control Center File Operations Functions Help x weg d Hs COM193 1 ur ADM a iM ectrum transceive Download From local File Ok Cancel The software configuration files are named with the bit extension The bit file can be downloaded via the Internet from the ComBlock CD or any other local file The option and revision for the software currently running within the FPGA are listed at the bottom of the advan
18. option Receiver input 50 Ohm SMA female connector Operating range 60 to 10 dBm Maximum no damage input level 20 dBm Two other signals can be multiplexed onto the same coaxial connection between the COM 1931 transceiver and an external LNB e 10 MHz frequency reference software enabled Level 2 dBm typ e 13 18V supply software enabled Transmitter output 50 Ohm SMA female connector Transmit level 30 to 0 dBm user selectable One other signal can be multiplexed onto the same coaxial connection between the COM 1931 transceiver and an external BUC e 10 MHz frequency reference software enabled Level 0 dBm typ 17 Operating input voltage range Supply voltage 18V min 36V VHDL code IP core max The FPGA code is written in VHDL It does not use 400mA typ under any third party software It occupies the following 28VDC FPGA resources Supply voltage when no LNB 5 6V min 36V Utilization Post Implementation 13 18V supply needed max FF a The positive voltage is on the center pin the ground on the outer barrel LUT 9 Memory LUT Absolute maximum ratings 1 0 Supply voltage BRAM 20dBm max DSP48 BUFG MMCM J Mechanical Interface Aluminum enclosure with rubberized end caps 25 50 75 100 LxWxH 168 5mm x 138 96 mm x 40 98 mm Utilization 96 Includes two optional 40mm mounting flanges for Teee mounting to a flat support plate Resource Utilization Av
19. refer to the ComBlock web site http www comblock com download com 931 pdf These specifications are subject to change without notice For an up to date list of ComBlock modules please refer to http www comblock com product list html MSS 845 Quince Orchard Boulevard Ste N Gaithersburg Maryland 20878 1676 U S A Telephone 240 631 1111 Facsimile 240 631 1676 www ComBlock com O MSS 2015 Issued 8 24 2015 Com Block COM 1931 L S band burst spread spectrum modem 80 Mchips s Modem Traffic POWER ON Sync Rx Power Tx on Tx C C Alarm E O OO s O Q RF Rx 10MHz DATA LAN M amp C LAN 36VDC 3 max Q MSS 845 Quince Orchard Boulevard Ste N Gaithersburg Maryland 20878 1676 U S A Telephone 240 631 1111 Facsimile 240 631 1676 www ComBlock com MSS 2015 Issued 8 24 2015 Functional Block Diagram LAN for data and M amp C LAN Ethernet MAC UDP IP Stack Block mode convolutional FEC encoder Block mode convolutional FEC decoder Burst DSSS modulator Burst DSSS demodulator TX RF synthesizer RF quadrature modulator super heterodyne RF receiver Rx RF synthesizer L S band RF output L S band RF input Configuration Basic The easiest way to configure the COM 1931 is to use the ComBlock Control Center software supplied with the module on CD Please follow the few simple steps described in the user manual ccchelp pdf document
20. riables are latched upon re reading SREGI6 Lak ad imScope COM1831A Burst mode DSSS modem s i 4 2 S N N after 8 bit Symbol ComScope Monitoring despreading Valid unsigned rate 2 5 l l only if code is Key internal signals can be captured in real time locked and displayed on a host computer using the Linear i e not in ComScope feature of the ComBlock Control the signal traces and trigger are defined as follows 2 Missed burst Binary Trace 1 signals Format Nominal Buffer detection at end sampling length of expected burst rate samples 3 Demod sync input directly from signed ADC could be at Demodulated L 8 bit 1 sample 512 software control by adjusting the decimation factor channel signed I svmbol and or selecting the f ae demod clock as real time 3 FFT magnitude 8 bit ADC clock 512 sampling clock unsi ened fax adc Trace 2 signals Format Nominal Buffer same time scale for all signals sampling length 1 I channel spread 8 bit ADC clock 512 pital neaei Fon sac www comblock com download comscope pdf center frequency 7 Compare with signed samples chip e signals 3 last demod AGC 8 bit 1 sample 212 gain I channel unsigned symbol EROR un Center Click on the button to start then select 1 End of Binary demodulated burst 1 I channel spread 8 bit ADC clock word detection IF Signals sampling rates can be changed under ADC clock
21. smitted frames SREG28 LSB 30 MSB Number of received frames SREG31 LSB 33 MSB Number of parallel code acquisition The number of parallel code acquisition circuits is expressed as circuits NACQ NACQ DIV NMUX SREG34 NACQ DIV SREG35 NMUX Non coherent integration and dump SREG36 period N NCID Measured modulated signal power SREG37 LSB SREG38 SREG39 MSB Measured AWGN power Approximation noise power is uniform over a range of fek 2 Therefore the noise density depends on the selected modulator chip rate see fax tx equation above SREG40 LSB SREG41 SREG42 MSB Carrier frequency offset Residual frequency offset with respect to the nominal carrier frequency i e after frequency profile correction Part 1 2 32 bit signed integer expressed as fcerror 27 fer SREG43 LSB SREG46 MSB Carrier frequency offset2 Residual frequency offset with respect to the nominal carrier frequency i e after frequency profile correction Part 2 2 32 bit signed integer expressed as fcerror 2 fai rate SREG47 LSB SREG50 MSB 2 S N N ratio valid only during code lock Linear not in dBs Fixed point format 14 2 SREG51 LSB SREG52 MSB Receiver decimation factor from fek aac to 4 fenip rate rx Valid range 1 16384 SREGS53 LSB SREG54 MSB 12 Network Monitoring Parameters Monitoring LAN PHY ID Expect 0x22 when LAN adapter is plugged in SREGIO Multi byte status va
22. sure They are intended to be used only for 82 3 debugging purposes i y i in i 1 IT na j l y ur if uu n Y WT HIND a Pi ML ATS RAT fi uu NAT TIVE PIAA ps d ME Mese je hal W Po i n t 51 31 11 9 29 49 69 89 109 129 149 169 189 209 229 249 269 289 309 329 349 369 389 409 429 Plot Settings Trigger Settings Autoscale X Min X Max Y Min Y Max Rescale Signal Representation Threshold Edge Pi D emo d signal pre sence detected at FF T v 74 142 117 3 w l bit Unsi d iv Risi d e JA 5 Demodulator recovered carrier center Close Apply Changes Re arm Force Trigger Plot fre quenc coarse Demod data field s demod state 3 J47 Demod d detecti received spread signal after RRC filter green vs code T q E ee Em replica red FEC decoder input bit error BER tester synchronized J4 11 BER tester matched filter output detects start of PRBS11 sequence J4 12 Byte error detected by BER tester ComScope example showing code lock with aligned LED Green when power 1s applied Red when one of these conditions occur Tx RF frequency synthesizer is out of lock Rx RF frequency synthesizer is out of lock Blink green when a frame from LAN UDP is being transmitted forwarded to the LAN UDP Transmitter must send PRBS11 test sequence is synchronized 14 Operation Frequency reference Depending on the firmware version loaded the frequency reference
23. to install the ComBlock Control Center software ComBlock Control Center windows rev exe Connect the LAN cable between PC and transceiver RJ45 connector labeled M amp C LAN Turn the transceiver power supply on and wait approximately 5 10 seconds In the ComBlock Control Center window click on the left most button and select LAN as primary communication media The default IP address is 172 16 1 128 In the ComBlock Control Center window detect the ComBlock module s by clicking the A Detect button next click to highlight the COM 1931 module to be configured next click the Em Settings button to display the Settings window shown below File Operations Functions Help x wi e 0 H3 COM1931A S band burst spread spectrum transceive Frequency index EN RF frequency 925000000 Hz Tx ALC target level 2000 0 4095 Transmitter on Receiver Frequency index 0 7 RF Frequency Hz Initial LNA gain 1023 0 1023 Initial RF gain 0 4095 Initial IF gain 0 0 4095 RF AGC IF AGC LNE supply General Frequency 0 Frequency 1 Frequency 2 Frequency 3 Frequency 4 1500000000 Frequency 5 1800000000 Frequency 6 2000000000 Frequency 7 EJ COM1931 S band burst spread spectrum transceiver Basic Settings FJ COM1931 S band burst spread spectrum transceiver Basic Settings FG COM1931 band burst spread spectrum transceiver Basic Settings diga 1j 128 Subnet mask 255 255 255 Static I
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