PCL-850 CLOCK GENERATOR User` Manual
Contents
1. 6 bits selection signals 64CH 1 bit SET signal Within 5mS Time between transferring a delimiter code and obtaining the set frequency in the case of serial data Time between giving a SET signal and obtaining the set frequency in the case of memory CH selection 40x32 5x13 mm page 2 2 2 Environmental conditions Operating temperature range 0 C 50 C Storage temperature range 30 C 70 C 3 Outer dimensions 0 00 27 94 37 80 35 56 33 02 30 48 13 00 22 86 20 32 17 78 15 24 BOTTOM VIEW 0 00 12 7 10 16 5 00 0 6typ 21PL 5 08 2 54 0 00 2 20 2 20 30 30 4 Pin assignments GND TXD RXD DO D1 D2 D3 D4 D5 OUT SET OUT GND GND TOP VIEW page 3 5 Pin names and descriptions Pin No Name Description 1 GND Power supply signal GND 2 3 3V Power supply pin to which 3 3V 5 should be supplied 3 DO Memory CH selection signal Input of signal selection bit 0 2 4 D1 Memory CH selection signal Input of signal selection bit 1 21 5 D2 Memory CH selection signal Input of signal selection bit 2 22 6 D3 Memory CH selection signal Input of signal selection bit 3 23 7 D4 Memory CH selection signal Input of signal selection bit 4 24 8 D5 Memory CH selection signal Input of signal selection bit 5 25 9 SET Set signal for memory CH selection As it is pulled up 10KQ internally the frequency in the memory CH selected by DO2. CR LF 63 fffffffff CR LF 66699 FFE on the first line is the default frequency to be output at power on On the second line to the 121st line frequency data is saved in the memory CHs Here fffffffff is the output frequency in each memory CH displayed in Hz 6 4 Caution for setting data consecutively In the case of switching frequencies at high speed data may drop out because the PCL850 does not perform flow control Upon completion of processing by sending a 66699 frequency setting command in 6 3 1 the prompt is returned therefore confirm the receiving of this prompt and then send the next frequency setting command page 7 7 Memory CH selection by parallel data It is designed so that frequency data saved in the maximum 64CH memory can be easily set by seven selection signals and one SET signal 7 1 Example of SW connection circuit Ul PCL850 gt OUT gt IOUT 53 l O swPUsHBUTTON EDA Remarks Only the SET signal is pulled up internally When not using DO D5 connect them to VCC or GND The input data of DO D5 is loaded on the falling edge of SET When not using RXD and TXD open them page 8 8 Shipping inspection 8 1 Electrical inspection 100 inspection shall be performed for the electrical specifications in 2 1 8 2 Appearance inspection Inspection shall be performed for contamination and bends in pins 9 Soldering conditions Perform soldering at a temperatu
3. D5 is set by connecting it to GND Data is loaded on the falling edge 10 GND Power supply signal GND 11 GND Power supply signal GND 12 OUT PECL differential output terminal 13 OUT PECL differential output terminal 14 RXD Asynchronous serial data input pin The level is 3 3V CMOS When not in use open it 15 GND Power supply signal GND 16 TXD Asynchronous serial data output pin The level is 3 3V CMOS When not in use open it page 4 6 Control by serial data How to set from a PC serial port RS 232C is explained below 6 1 Communication specifications Communication speed 9600bps Data bit 8 bits Parity None Stop bit 1 bit Flow control None Level 3 38V CMOS 6 2 RS 232C connection The electric signal level of PCL 850 serial communications is 3 83V CMOS which cannot be directly connected to a PC serial port etc RS 232C level Level conversions between RS 232C and 3 3V CMOS are made via the level converter as shown in the following figure Ul PCL850 La SO 0 Lo a bo Gay a ICL3232CP page 5 Note The U2 level conversion IC is ICL3232CP manufactured by INTERSIL The other ICL32XX series of level conversion ICs are also usable 6 3 Command definitions Character strings enclosed in double quotation marks mean ASCII codes and CR and LF which are control codes mean OD hex and OA hex If any invalid command is input INVALID DATA LF CR is returned All chara
4. PCL 850 CLOCK GENERATOR User Manual History REV1 0 10 1 2002 issued REV1 1 11 27 2002 revised Digital Signal Technology Inc 1 7 30 Higashi Benzai Asaka Saitama 351 0022 Japan TEL 81 48 468 6094 FAX 81 48 468 6210 Mail info dst co jp URL http www dst co jp en page 1 1 Functional outline As a signal source desired clock signals can be generated with 1Hz resolution in an extremely wide band of 1MHz to 850MHz Wideband signals up to 850MHz are generated by PLL multiplication of the signal generated by a 32 bit DDS direct signal synthesizer The frequency is set with asynchronous serial data Also the frequency can be easily set by selecting CHs saved in the incorporated 64CH memory with parallel data 2 Specifications 2 1 Electrical specifications Power supply voltage Consumption current Output level Output freguency range Freguency resolution Output waveform duty Freguency accuracy Jitter Spurious level Freguency control Memory CH selection Freguency setting time Outer dimensions 3 3V 5 250mA or less LVPECL differential output 3 3V 1MHz 850MHz 1Hz 50 20 20ppm 0 50 C 1MHz 400MHz 30pSrms 400MHz 850MHz 50pSrms Cycle to Cycle Jitter 1MHz 100MHz 45dB or more 400MHz 820MHz 32dB or more Serial input two signal lines 9600bps 8 bits No parity 1 stop bit ASCII 9 digit numerical data line feed code Parallel input eight signal lines
5. cters used for input should be uppercase If a normal command is input i S returned Also the input data is echoed back 6 3 1 Freguency setting command For frequency setting inputs can be made in MHz KHz and Hz 1 Setting in MHz For setting 123MHz input the following data 123M CR In this case all the data below 100KHz is set to 0 2 Setting in KHz For setting 123456KHz input the following data 123456K CR In this case all the data below 100Hz is set to 0 3 Setting in Hz For setting 123456789Hz input the following data 123456789 CR 6 3 2 SAVE command By inputting SAVE CR the currently set frequency is saved in nonvolatile RAM The saved frequency is output when the power is turned on again By inputting SAVE xxx yyy CR the frequency can be saved in the specified memory CH Here xxx is a memory address of 64CH specified by 0 63 at the maximum yyyyyy is the frequency data explained in 6 3 1 page 6 For saving a freguency of 123MHz in memory CH address 0 input the following data SAVE 0 123M CR For saving a frequency of 123456KHz in memory CH address 63 input the following data SAVE 63 123456K CR 6 3 3 READ command By inputting READ CR the currently saved data in all memory CHs is output The response is as follows ffffffftr CR LF 00 fffffffff CR LF 01 fffffffff CR LF 02 fffffffff
6. re of 260 C or less within 10 seconds 10 Warranty If any defect is found due to the manufacturer s improper production or design within one year after delivery repair or replacement shall be performed at the manufacturer s responsibility 11 Other 11 1 This product which employs a CMOS device may be easily damaged by static electricity 11 2 Keep in mind that immersion cleaning is not allowed 11 3 Special damp proof control is not necessary Descriptions in this manual are subject to change without notice No part of this manual may be reproduced without our permission We shall assume no liability for any user damage as a result of an accident etc Descriptions in this manual shall not guarantee the practice of industrial property and other rights or grant a license for them We shall assume no liability for any third party s industrial property rights attributable to the use of circuits etc described in this manual Digital Signal Technology Inc page 9
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