ART2932 User`s Manual
Contents
1. Chapter 4 Connection Ways for Each Signal 4 1 AD Single ended Input Connection Single ended mode can achieve a signal input by one channel and several signals use the common reference ground This mode is widely applied in occasions of the small interference and relatively many channels AIO analog sienal All i lg AD e e Lg ALS O act MAN ke J Figure 4 1 single ended input connection 4 2 AD Double ended Input Mode Double ended input mode which was also called differential input mode uses positive and negative channels to input a signal This mode is mostly used when biggish interference happens and the channel numbers are few Single ended double ended mode can be set by the software please refer to ART2932 software manual According to the diagram below ART2932 board can be connected as analog voltage double ended input mode which can effectively suppress common mode interference signal to improve the accuracy of acquisition Positive side of the 8 channel analog input signal is connected to AIO AI7 the negative side of the analog input signal is connected to AI8 AI15 equipments in industrial sites share the AGND with ART2932 board AIO analog signal e AGND device AIS All AGND BI devi e evice AI9 eo eN CO device A115 AGND Figure 4 2 double ended input connection ART2932 Data Acquisit2. ART2932 User s Manual g Beijing ART Technologv Development Co Ltd ART2932 Data Acquisition V6 021 Contents A 7 SE ES ES ones E A E E E E er 2 OT VOT i e RET eam ones EET TEE ai a a E FEDE TEDE REED FEET E DEER LEREE 3 Chapter 2 Components Layout Diagram and a Brief Description ss ssseseennnnnznnnenznznninzznnnenzznnnzzzznnnnnnzznnzzznnnnnnnn nn 5 2 1 The Main Component Layout Dias ss sies a eda hu 5 2 2 The Function Description for the Main Component a 5 2 2 1 Signal Input and Output Connectors A AAAAAAAAAAAAA nanna tana n nanna 5 2 22 DOL E IC ee ee E oe none Sonne er mene Semen ee nee Se arene ee ney ee eee ee 6 229 Board Base Address SCLC CUO Mi a i a a a ini ada 6 DD SEO L sas ee ze ss sss se E ns css ses ns cies a ews stan peso neta eoe beeen sees ese eee 7 Chapter SIQNG CONTCCIONS io is d 8 3 1 The Definition of Signal Input and Output Connectors eee e eee eennnnnnnnnnnnnnnnnnnznnnnnznnnnnnnnznnzznzzzZZAZZZZZZZZZZZZZZZZAAA 8 I ID al lapt OG DAL COME LOES eee eee eee nen tee eee eee tee REESE mb delete ence ee eee ee eee er 9 Chapter 4 Connection Ways for Each Signal ss ss ssennnnnnnnnnn anna na aa A AAEAAAAAA EEA EEA A ANA EEE ZEA MM EEE EEEEAG GAA G AAA EEEEEEEEEES 10 4 1 AD Single ended Input Connection EA E EEA EEA A EEA EE EEI EE EEAAA MAKE MARE EE AE At rr rna ran ntnntnta 10 42 D Doubls ended Input Mod ia na EEN son 10 AS Oier C onne en 11 4 4 Methods of Realizing the Mult
3. Analog Trigger Signal The waiting time _ Pause AD Sampling Status Figure 5 2 3 High Level Trigger When ADPara TriggerDir ART2932 TRIGDIR POSIT NEGAT it means the trigger level is low or high The effect is the same as the internal software trigger 5 2 2 DTR Trigger When the trigger signal is the digital signal standard TTL level using the DTR trigger source ART2932 Data Acquisition V6 021 Edge Trigger Function Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal to trigger AD conversion When ADPara TriggerDir ART2932 TRIGDIR NEGATIVE choose the trigger mode as the falling edge trigger That is When the DTR trigger signal is on the falling edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition AD Start Pulse Digital Trigger Signal Ra feesesseensesnesesenersverveeneveevneen The falling edge before The waiting time p The first falling edge after the the AD started is i AD started is valid i invalid en MA OP eee eee eee sees esse Koll AD working pulse Figure 5 2 4 Falling edge Trigger When ADPara TriggerDir ART2932 TRIGDIR POSITIVE choose the trigger mode as rising edge trigger That is when the DTR trigger signal is on the rising edge AD will immediately access to the conversion process and its follow up changes have no
4. NE Te gee geen ecg RR kl ra The waiting line RX E tnte _V The falling edge s i The first falling edge after the before the AD started nn AD started is valid l En i da as we OO mei Tonseconesonssonosososososomososssoosonsssnonst pulse after triggered ka AD Working Pulse snuser TUTTUU En Figure 5 2 1 Falling edge Trigger When ADPara TriggerDir ART2932 TRIGDIR POSITIVE choose the trigger mode as rising edge trigger That is when the ATR trigger signal is from lower than O channel output voltage to higher than l channel output voltage AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition When ADPara TriggerDir ART2932 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger That is when the ATR trigger signal is from higher than 1 channel output voltage to lower than 0 channel output voltage or when the ATR trigger signal is from lower than O channel output voltage to higher than l channel output voltage AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition This function can be used in the case that the acquisition will occur if the exoteric signal changes Triggering Level Function Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger AD conversion When ADPara TriggerDir ART2932 TRIGDIR NEGATIVE it me
5. RPO RPIO P Cyclone IT EP 336 ui kit Page s SEJ l File f ME ii La nn a ss mm E E E E E E E E E ss mn E E i SS mn OE T E W T W E X E E E EEE E E E T 2 2 The Function Description for the Main Component 2 2 1 Signal Input and Output Connectors P1 analog signal input output connectors P2 digital input output port ADDRI ART2932 Data Acquisition V6 021 2 2 2 Potentiometer RPI AD analog signal input zero point adjustment potentiometer RP2 AD analog signal input full scale adjustment potentiometer RP3 AOO analog signal output zero point adjustment potentiometer RP4 AOO0 analog signal output full scale adjustment potentiometer RPS AOI analog signal output zero point adjustment potentiometer RP6 AOI analog signal output full scale adjustment potentiometer RP7 AO2 analog signal output zero point adjustment potentiometer RP8 AO2 analog signal output full scale adjustment potentiometer RP7 AO3 analog signal output zero point adjustment potentiometer RP8 AO3 analog signal output full scale adjustment potentiometer 2 2 3 Board Base Address Selection ADDRI board base address DIP switches Board base address can be set to binary code which from 200H to 3EOH be divided by 16 board base address defaults 300H will occupy the base address of the date of 28 consecutive I O addresses Switch No 5 6 7 8 correspond to address bits A6 A7 A8 A9 are the base address of selector switch S
6. channels External signal cycle 1 external signal frequency Under the external clock mode External signal frequency AD sampling frequency cycle signal points the total number of channels BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 18 ART2932 Data Acquisition V6 021 External signal cycle 1 external signal frequency Start enable Pulse conversion ren Figure 6 1continuous acquisition in internal clock Note a sample cycle 6 3 2 AD Grouping Sampling Function Grouping acquisition pseudo synchronous acquisition function refers to the sampling clock frequency conversion among the channels of the group in the AD sampling process and also a certain waiting time exists between every two groups this period of time is known as the Inter group Spacing Cycles of Group refers to numbers of the cycle acquisition for each channel in the same group In the internal clock mode and the fixed frequency external clock mode the time between the groups is known as group cycles The conversion process of this acquisition mode as follows a short time stop after the channels conversion in the group that is Inter group Group Interval and then converting the next group followed by repeated operations in order so we call it grouping acquisition The purpose of the application of the grouping acquisition is that at a relatively slow frequency to ensure that all of the time difference between
7. effect on AD acquisition When ADPara TriggerDir ART2932 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger That is when the DTR trigger signal is on the rising or falling edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition This function can be used in the case that the acquisition will occur if the exoteric signal changes Triggering Level Function Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger AD conversion When ADPara TriggerDir ART2932 TRIGDIR NEGATIVE it means the trigger level is low When DTR trigger signal is in low level AD is in the conversion process once the trigger signal is in the high level AD conversion will automatically stop when the trigger signal is in the low level again AD will re access to the conversion process that is only converting the data when the trigger signal is in the low level ART2932 Data Acquisition V6 021 AD Start ref Digital Trigger Sighal ppesrmeessssesesesessssennot Beca The high level before 4 The waiting time gt the AD started is invalid P TA i ause Cecescsssscosososocososesososososososeoosest AD Working Pulse P AD triggered Figure 5 2 4 High Level Trigger When ADPara TriggerDir ART2932 TRIGDIR POSITIVE it means the trigger level is high When DTR trigger s
8. starts to count from the initial count value again in the count period the output has remained high level When the count reduction of the counter has not yet reached zero but it is given a new value N1 Only when it is the rising edge of GATE the counter starts to count from N1 Time diagram is shown in figure 6 ART2932 Data Acquisition V6 021 Mode 5 GATE E ur eae GATE ii fy L lg 4 OUT n 4 i Figure 6 ART2932 Data Acquisition V6 021 Chapter 8 Address Allocation Table Address Assignment base address offset address ART2932 register address allocation table Offset address Function Read Function Write First channel 3 0 Last channel 7 4 D 9 8 Gain D 12 0 Read AD data from FIFO 00b 1 time D 15 13 Null 01b 2 times 10b 4 times 11b 8 times D 15 10 Reservation D 0 Sample Mode 0 Continuous sampling base address 0x00 Grouping sampling D 1 Trigger Mode 0 Software trigger Hardware Trigger D 1 Trigger Source 0 Analog trigger Digital trigger FIFO status D 3 Trigger Type D 0 EF Level trigger non empty 0 Edge trigger 0 empty D 5 4 Trigger Direction D 1 HF Edge Trigger not half full 00 Falling edge trigger base address 0x02 0 half full 01 Rising edge trigger D 2 FF 10 11 Either rising or falling edge trigger not overflow Level Trigger 0 overflow 00 Low level trigger 01 High level trigger 10 11 Either low or high level t
9. 021 Write base address 0X14 first Write DA register 23 16 DA is 12 bit Power register must be configured to write write once 0x10 we should write the following two registers for each time of DA output 1 DA output range register D7 D3 00001 fixed value The range of each channel can be independently controlled D2 D0 DA channel selection 000 AOO 001 AOI 010 AO2 011 AO3 2 DA channel selection and data output register D7 D3 00001 fixed value D2 D0 DA channel selection 000 AOO 001 AOI 010 AO2 011 AO3 100 All start base address 0x1A Read Back D 15 0 counter0 initial value D 2 0 counter 0 work mode base address 0x1C J D 15 0 the current value of counter 0 i D 15 3 Reservation base address OxlE J Read Back D 15 0 counter initial value D 2 0 counter 1 work mode base address 0x20 D 15 0 the current value of counter 1 i D 15 3 Reservation base address 0x16 Read Back base address 0x22 J Read Back D 15 0 counter2 initial value D 2 0 counter 2 work mode base address 0x24 D 15 0 the current value of counter 2 i D 15 3 Reservation D 7 01 digital input DI 7 01 digital output base address 0x26 7 0 dig M 7 0 dig 7 di D 15 8 null D 15 8 Reservation ART2932 Data Acquisition V6 021 Chapter 9 Notes Calibration and Warranty Policy 9 1 Notes In our products packing user can find a user manual ART2932 m
10. INDOWS Choose channel 0 10V input range and start sampling adjust potentiometer RP2 in order to make voltage value is 9999 69mV or about 9999 69mV Full scale adjustment of other channels is alike 3 Repeat steps above until meet the requirement 9 3 Analog Signal Output Calibration In the manual we introduce how to calibrate ART2932 in 10V range calibrations of other ranges are similar 1 Connect the ground of the digital voltage meter to any analog AGND Connect the input side of the voltage meter to the output channel which needs calibration Run ART2932 test procedure under Windows select the AO output detection 2 To set DA output 2048 adjust potentiometer RP3 in order to make AOO output 0 000V 3 To set DA output 4095 adjust potentiometer RP4 in order to make AOO output 9995 11 mV 4 Repeat steps above until meet the requirement 9 4 DA use In demonstration program the continuous output interval of waveform output can not be carried out the main objective is to test the strength of DA output BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 30 ART2932 Data Acquisition V6 021 9 5 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please atta
11. al clock sample cycle b AD chips conversion time c inter group interval d group cycle Under the external clock mode the requirement is the external clock cycle gt the internal clock sampling period x the total number of sampling channelsx cycles of group AD chip conversion time otherwise the external clock appearing in the group conversion time will be ignored Under the fixed frequency external clock mode for example when sampling data of two channel 0 1 then channel 0 and channel 1 consist of a group Sampling frequency Frequency 100000Hz the cycle is 10uS cycles of group is 2 then the acquisition process is to collect the first set of data including two data of channel 0 and two data of channel 1 the order of conversion 0 1 0 1 We need 10uS to sample the four data and 40uS to convert of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the next edge of the external clock triggers AD to do the next acquisition and the conversion is going on in this way as the diagram following shows Start Enabled External Clock ka entl Convert Pulse The external clock before the start pulse is ignored Figure 6 3 Grouping sampling under the fixed frequency external clock mode Notes a internal clock sample cycle b AD chips conversion time d group cycle external clock cycle Under an unfixed frequency ext
12. ans the trigger level is low When ATR trigger signal is smaller than O channel output voltage AD is in the conversion process once the trigger signal is higher than l channel output voltage AD conversion will automatically stop when the trigger signal is smaller than O channel output voltage again AD will re access to the conversion process that is only converting the data when the trigger signal is smaller than O channel output voltage BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 14 ART2932 Data Acquisition V6 021 AD Start Pulse Bee FEE IM Output voltage of AO1 li The first low level after the ii e i AD started is valid Pereosoovevedeesverseeversvveeveevevverseresvevververveverveenet The first working pulse after triggered n AD Working Pulse ikuszzzz ja 11 l is i Figure 5 2 2 Low Level Trigger When ADPara TriggerDir ART2932 TRIGDIR POSITIVE it means the trigger level is high When ATR trigger signal is higher than l channel output voltage AD is in the conversion process once the trigger signal is smaller than O channel output voltage AD conversion will automatically stop when the trigger signal is higher than l channel output voltage again AD will re access to the conversion process that is only converting the data when the trigger signal is higher than l channel output voltage AD Start Pulse Output voltage of AOI Output voltage of AOO
13. art all the slave cards as the main card has not been activated and there is no output clock signal so the slave card enters the wait state until the main card was activated At this moment the multi card synchronization has been realized When you need to sample more than channels of a card you could consider using the multi card cascaded model to expand the number of channels Master Card CLKOUT kI jid e CLKIN gt Slave Card 1 Y a gt Slave Card 2 i When using the common external trigger please make sure all parameters of different ART2932 are the same At first configure hardware parameters and use analog or digital signal triggering ATR or DTR then connect the signal that will be sampled by ART2932 input triggering signal from ART pin or DTR pin then click Start Sampling button at this time ART2932 does not sample any signal but waits for external trigger signal When each module is waiting for external trigger signal use the common external trigger signal to startup modules at last we can realize synchronization data acquisition in this way See the following figure ART2932 External Trigger Signal ATR DTR e p HE DIR gt ART2932 EE Rn V_ATRDIR 4 ART2932 When using the common external clock trigger please make sure all parameters of different ART2932 are the same At first configure hardware parameters and use external cloc
14. ata from the two channels After the conversion time of an AD chip AD will automatically cut off to enter into the waiting state until the 50uS group interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows Start Enabled cee ee Convert Pulse ILI lal lal INI en bic a d aib Figure 6 1 Grouping Sampling which grouping cycle No is 1 under the Internal Clock Mode Note a internal clock sample cycle b AD chips conversion time c inter group interval d group cycle Change the group cycles into 2 then the acquisition process is to collect the first set of data including two data of channel 0 and two data of channel 1 the conversion order is 0 1 0 1 We need 10uS to sample each of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the 50uS group interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 20 ART2932 Data Acquisition V6 021 Start Enabled oc ne Convert Pulse Figure 6 2 Grouping Sampling which grouping cycle No is 2 under the Internal Clock Mode Notes a intern
15. ch an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s guarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments 1 e high temperatures high humidity or volatile chemicals VV Vv V Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company website ART2932 Data Acquisition V6 021 Pro
16. channels to become smaller in order to make the phase difference become smaller thus to ensure the synchronization of the channels so we also say it is the pseudo synchronous acquisition function In a group the higher the sampling frequency is the longer inter group interval is and the better the relative synchronization signal is The sampling frequency in a group depends on ADPara Frequency the cycles of a group depends on ADPara Loops of Group and the inter group interval depend on ADPara Group Interval Based on the grouping function it can be divided into the internal clock mode and the external clock mode Under the internal clock mode the group cycle is decided by the internal clock sampling period the total number of sampling channels group cycles and inter group interval together In each cycle of a group AD only collects a set of data Under the external clock mode external clock cycle gt internal clock sampling cycle x the total number of sampling channels x cycles of Group AD chip conversion time AD data acquisition is controlled and triggered by external clock The external clock mode is divided into fixed frequency external clock mode and unfixed frequency external clock mode Under the fixed frequency external clock mode the group cycle is the sampling period of the external clock The formula for calculating the external signal frequency is as follows Under the internal clock mode Group Cycle the internal clock
17. ducts Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin definition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to dr
18. ealer or sales gt ART2932 Data Acquisition Board gt ART Disk a user s manual pdf b drive c catalog gt Warranty Card FEATURES Analog Input gt Converter Type AD7321 gt Input Range 10V 5V default 2 5 0 10V gt 12 bit resolution gt Sampling Rate 1Hz 250KHz Note each channel actual sampling rate sampling rate the number of sampling channels gt Analog Input Mode 16SE 8DI gt Data Read Mode non empty half full inquiry mode gt Memory Depth 8K word FIFO memory gt Memory Signs full non empty and half full gt AD Mode continuum sampling grouping sampling gt Group Interval software configurable minimum value is sampling period maximum value is 3276us gt Loops of Group software configurable minimum value is one time maximum value is 255 times gt Trigger Mode software trigger hardware trigger external trigger gt Trigger Type level trigger edge trigger gt Trigger Direction negative positive positive and negative trigger gt Trigger Source ATR DTR gt Analog Trigger Source ATR Input Range SAO0 and PAOI AO1 gt AO0 gt Trigger Source DTR Input Range standard TTL level gt AD Conversion Time lt 1 6us gt Amplifier Set up Time 785ns 0 001 max o BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 3 ART2932 Data Acquisition V6 021 Programmable Gain 1 2 4 8 AD8251 default or 1 2 5 10 AD8250 or 1 10 100 1000 AD8253 Analo
19. ernal clock mode for example the grouping sampling principle is the same as that of the fixed frequency external clock mode Under this mode users can control any channel and any number of data BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 21 ART2932 Data Acquisition V6 021 Users will connect the control signals with the clock input of the card CLK_IN set the required sampling frequency and sampling cycles When there are external clock signals it will sample the data which is set by users Because the external clock frequency is not fixed the size of external clock cycle is inconsistent but to meet the external clock cycle gt the internal clock sampling period x the total number of sampling channels x cycles of group AD chip conversion time otherwise the external clock edge appearing in the group conversion time will be ignored Start Enabled External Clock eae eae aa gt gt Convert Pulse Figure 6 4 Grouping sampling under the not fixed frequency external clock mode Note a internal clock sample cycle b AD chips conversion time BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 22 ART2932 Data Acquisition V6 021 Chapter 7 Timer Counter Function Mode 0 Interrupt on terminal count Under this mode when given the initial value if GATE is high level the counter immediately begins to count by subtracting 1 each time the counter
20. g Input Impedance 10OMQ Non linear error 1 LSB Max System Measurement Accuracy 0 01 Operating Temperature Range 0 C 55 C VV VV VV Storage Temperature Range 20 C 70 C Analog Output Converter Type AD5724 Output Range 10 8V 410V 5V 0 10 8V 0 10V 0 5V 12 bit resolution Channel No 4 channel Non linear error 1 LSB Maximum Output Error full scale 1LSB Operating Temperature Range 0 C 55 C VV VV Vv vvv Storage Temperature Range 20 C 70 C Digital Input gt Channel No 8 ch gt Electric Standard TTL compatible gt High Voltage 2V gt Low Voltage 0 8V Digital Output gt Channel No 8 ch gt Electrical Standard TTL compatible gt High Voltage 3 8V gt Low Voltage 0 44V gt Power on Reset CNT Counter timer gt 16 bit counter timer 3 independent subtraction counters gt Count Mode 6 modes gt Electrical Standard TTL level gt Input Electrical Standards low level 0 8V high level 2V gt Output Electrical Standards low level 0 5V high level 2 4V gt Clock Source frequency range 1Hz 10MHz gt Gate rising edge high level low level gt Counter Output high level low level Other Features Board Clock Oscillation 40MHz Dimension 90 3mm L 96mm VV 16mm H ART2932 Data Acquisition V6 021 Chapter 2 Components Layout Diagram and a Brief Description 2 1 The Main Component Layout Diagram RPI RP2 RP3 RP4 RPS RP6 RP7 RPS
21. gnal Output Calbraltoti sterersserssersdedenersdersseprdeindersderroatrdeiineridermpannderdnersbernbetsdeinderndenibetndeindersderndedsd 30 ADD 30 DES AE PO r ane nee OE eRe en ne RP RP en E A N AANE AN 31 Products Rapid Installation and Self check Anna nanna nn 32 ES coe Installa nn 32 Belt CCC E E N E N E N E A E N E E emeti estimen eminent dm 32 DEE Wrone iS talla One a ee a a TO 32 ART2932 Data Acquisition V6 021 Chapter I Overview In the fields of Real time Signal Processing Digital Image Processing and others high speed and high precision data acquisition modules are demanded ART2932 data acquisition module which brings in advantages of similar products that produced in China and other countries is convenient for use high cost and stable performance ART2932 is a data acquisition module based on PC104 bus It can be directly connected with PC104 interface of computer to constitute the laboratory product quality testing center and systems for different areas of data acquisition waveform analysis and processing It may also constitute the monitoring system for industrial production process Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local d
22. i card Synchronization unu unnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnns 11 Chapter 5 The Instruction of the AD Trigger Function ss seeeenennnzznnnnenknznnzzzzzntrznzzzinizzzarrnntztnzzzzzrarnnznnnzzzzznannnnnttnn 13 ILADI a ERO OC NIOO ia l tea 13 9 2 D Ec wu l Soc NOG ne ene een olle delden 13 LAAR T icp sd ncn so ck ca st ao gd ac td cd acid ac ed nt ob did sesh ad ed nt of died aes Sed at et Soi aes abled ad ed abi E 13 DD DIR Bn 15 Chapter 6 Methods of using AD Internal and External Clock Function ss eeeeeeeennnzzznnnnnnnnnnnnnznznnnnnnnnnnnnnzzznnnnna 18 gl Miemal Clock Wain in of D steenen adic ce atin Hea eis NERE EEN ERNEST ER SSL ENERET ner eternet 18 62 External Clock Funcion of Dn 18 6 3 Methods of Using AD Continuum and Grouping Sampling Function 20 2 0 nnnnnnnnnnnnanznnnznnnnananznnnnnannnnana na 18 6 3 1 AD Continuum Sampling Pun Oi ina 18 6 35 2 AD Groupes samplins PCO ti cassette tt ERE Se RER SEERNE RAE 19 Chapter 7 Jimer c ounter FIN CU OM mamnmmmenmnmssm sssmnmtmtamess tzm nsnametmyamntmtstbsnsmtemya mats nt 23 Chapter 6 Address Allocation IQDLE saneren neee eneen 21 Chapter 9 Notes Calibration and Warranty POLICY vicccccccccccssscccccccccccneeeeessceceeeeaeeeeseeeeeeeeeaeeeeeeeeeeeesaaaeseeeeeeeesaaaesseeeeeeeaaaaees 30 Ol INU a a E ka a ous nected ates aka denet tae dn 30 9 2 AD Analog Signal Input Calibration Ana Annnnnnnnnnnnnn nn nn tna nn nata n ttanta 30 9 3 Analog Si
23. ignal is in high level AD is in the conversion process once the trigger signal is in the low level AD conversion will automatically stop when the trigger signal is in the high level again AD will re access to the conversion process that is only converting the data when the trigger signal is in the high level When ADPara TriggerDir ART2932 TRIGDIR POSIT NEGAT it means the trigger level is low or high The effect is the same as the internal software trigger ART2932 Data Acquisition V6 021 Chapter 6 Methods of using AD Internal and External Clock Function 6 1 Internal Clock Function of AD Internal Clock Function refers to the use of on board clock oscillator and the clock signals which are produced by the user specified frequency to trigger the AD conversion regularly To use the clock function the hardware parameters ADPara ClockSource ART2932 CLOCKSRC IN should be installed in the software The frequency of the clock in the software depends on the hardware parameters ADPara Frequency For example if Frequency 100000 that means AD work frequency is 100000Hz that is 100 KHz 10 us point 6 2 External Clock Function of AD External Clock Function refers to the use of the outside clock signals to trigger the AD conversion regularly The clock signals are provide by the CLKIN pin of the CNI connector The outside clock can be provided by ART2932 clock output CLKOUT of P1 as well as other equipments for example clock fre
24. ion V6 021 4 3 Other Connections Doo switch signal _ 4 A00 analog signal VIE AOI B DO i a A03 o device DO7 b j device aa switch device N switch devite AGND DGND FJ sewa Figure 4 3 analog signal output connection Figure 4 5 digital signal output connection Dio switch signal MW ME A Mona A CLK IN J pn 8 Gu In 1 DTR e lt e DI7 Ja ATR a A switch device Gun e AGND switch d yice DGND DGND TX ll Figure 4 4 digital signal input connection Figure 4 6 Clock Input Output and Trigger Signal Connection NN GATE CLK in 1 1 OUT DGND OX L Figure 4 7 CNT Timer Counter signal connection 4 4 Methods of Realizing the Multi card Synchronization Three methods can realize the synchronization for the ART2932 the first method is using the cascade master slave card the second one is using the common external trigger and the last one is using the common external clock When using master slave cascade card programs the master card generally uses the internal clock source model while the slave card uses the external clock source mode After the master card and the slave card are initialized according to the 11 ART2932 Data Acquisition V6 021 corresponding clock source mode At first st
25. iver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others gt SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 32
26. k then connect the signal that will be sampled bv ART2932 input trigger signal from ART pin or DTR pin then click Start Sampling button at this time ART2932 does not sample any signal but wait for external clock signal When each module is waiting for external clock signal use the common external clock signal to startup modules at last we realize synchronization data acquisition in this way See Ext I clock signal xternal cloc ds CLR IN gt ART2932 CLK_IN gt the following figure ART2932 mma EES AEN gt ART2932 12 ART2932 Data Acquisition V6 021 Chapter 5 The Instruction of the AD Trigger Function 5 1 AD Internal Trigger Mode When AD is in the initialization if the AD hardware parameter ADPara TriggerMode ART2932 TRIGMODE SOFT we can achieve the internal trigger acquisition In this function when calling the StartDeviceProAD function it will generate AD start pulse AD immediately access to the conversion process and not wait for the conditions of any other external hardware It also can be interpreted as the software trigger As for the specific process please see the figure below the cycle of the AD work pulse is decided by the sampling frequency The first working pulse after the AD 4 start pulse Figure 5 1 Internal Trigger Mode 5 2 AD External Trigger Mode When AD is in the initialization if the AD hardware parameter ADPara TriggerM
27. ode ART2932 TRIGMODE POST we can achieve the external trigger acquisition In this function when calling the StartDeviceProAD function AD will not immediately access to the conversion process but wait for the external trigger source signals accord with the condition then start converting the data It also can be interpreted as the hardware trigger Trigger source includes the DTR Digital Trigger Source and ATR Analog Trigger Source 5 2 1 ATR Trigger When the trigger signal is the analog signal using the ATR trigger source Trigger level needs to be set when using the ATR trigger source two channels output voltages of DA AO0 and AO1 codetermines the trigger level in this case we need set O channel output voltage higher than l channel output voltage There are two trigger types edge trigger and level trigger ART2932 Data Acquisition V6 021 Edge Trigger Function Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal to trigger AD conversion When ADPara TriggerDir ART2932 TRIGDIR NEGATIVE choose the trigger mode as the falling edge trigger That is when the ATR trigger signal is from higher than O channel output voltage to lower than l channel output voltage AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition AD Start Pulse Output voltage of AO1 A Analog Trigger Siggal er
28. odule and a quality guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using ART2932 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of ART2932module 9 2 AD Analog Signal Input Calibration Every device has to be calibrated before sending from the factory It is necessary to calibrate the module again if users want to after using for a period of time or changing the input range In the manual we introduce how to calibrate ART2932 in 10V calibrations of other input ranges are similar Prepare a digital voltage instrument which the resolution is more than 5 5 bit install the ART2932 module and then power on warm up for fifteen minutes 1 Zero adjustment select one channel of analog inputs take the channel AIOfor example connect OV to AIO and then run ART Data Acquisition Measurement Suite in the WINDOWS Choose channel 0 10V input range and start sampling adjust potentiometer RPI in order to make voltage value is 0 000V or about 0 000V Zero adjustment of other channels is alike 2 Full scale adjustment select one channel of analog inputs take the channel AIO for example connect 9999 69mV to AIO and then run ART Data Acquisition Measurement Suite in the W
29. output OUT turns into low level when the count ends and the count value becomes 0 the counter output OUT becomes and keeps high level until given the initial value or reset If a counter which is counting is given a new value the counter will begin to count from the new value by subtracting 1 each time GATE can be used to control the count GATE 1 enables counting GATE 0 disables counting OUT signal changes high from low can be used as interrupt request Time diagram is shown in Figure 1 Mode 0 WR n 4 f neg 2 1 DD 2 1 Q wh 8 OUT GATE H 4 Et OUT U Figure 1 Mode 1 Hardware retriggerable one shot The mode can work under the role of GATE After given the initial count value N OUT becomes high level the counter begins to count until the appearance of the rising edge of GATE at this moment OUT turns into low level when the count ends and the count value becomes 0 OUT becomes high level that is the output one shot pulse width is determined by the initial count value N If the current operation does not end and another rising edge of GATE appears then the current count stops the counter begins to count from N once again and then the output one shot pulse will be widened When the count reduction of the counter has not yet reached zero but it is given a new value N1 Only when it is the rising edge of GATE the counter starts to count from N1 Time diagram is shown in Figure 2 BUY ONLINE at art cont
30. quency generators To use the external clock function the hardware parameters ADPara ClockSource ART2932 CLOCKSRC OUT should be installed in the software The clock frequency depends on the frequency of the external clock and the clock frequency on board that is the frequency depends on the hardware parameters ADPara Frequency only functions in the packet acquisition mode and its sampling frequency of the AD is fully controlled by the external clock frequency 6 3 Methods of Using AD Continuum and Grouping Sampling Function 6 3 1 AD Continuum Sampling Function The continuous acquisition function means the sampling periods for every two data points are completely equal in the sampling process of AD that is completely uniform speed acquisition without any pause so we call that continuous acquisition To use the continuous acquisition function the hardware parameters ADPara ADMode ART2932 ADMODE SEQUENCE should be installed in the software For example in the internal clock mode hardware parameters ADPara Frequency 100000 100KHz should be installed and 10 microseconds after the AD converts the first data point the second data point conversion starts and then 10 microseconds later the third data point begins to convert and so on The formula for calculating the external signal frequency is as follows Under the internal clock mode External signal frequency AD sampling frequency cycle signal points the total number of
31. rigger D 6 Clock Source 0 Internal clock External clock D 7 Clock Output 0 Sample clock output disable Sample clock output enable D 15 8 Reservation D 15 0 set AD sample frequency base address 0x04 Read back Sample rate 500K max 27 ART2932 Data Acquisition V6 021 D 15 0 input range control first write fixed value 0x8020 D 0 Single ended and Differential 0 SE 1 DI D 10 1 0000000000 fixed value Read back base address 0x06 D 2 0 Input Range 00 10V Ol SV 10 2 5V 11 0 10V D 15 13 101b fixed value base address 0x08 J Read back D 15 0 Group interval D 7 0 Loops of Group base address 0x0A f Read back i D 15 8 Reservation D 0 AD Enable 0 Disable AD 1 Enable AD D 15 1 Reservation D 7 0 Trigger sensitivity base address 0x0E Read back I DI 15 81 Reservation base address 0x10 D 15 0 hardware version high 16 bit Clear FIFO base address 0x12 D 7 0 hardware version low 8 bit Write DA Register 15 0 DA is 12 bit Power register must be configured to write write once 0x001F 1 DA range output register D15 D3 Reservation D2 D0 Output Range 000 0 5V 001 0 10V 010 0 10 8V 011 5V 100 10V 101 10 8V base address 0x0C Read back Read Back base address 0x14 2 DA channel selection and data output register D15 D4 12 bit DA data D3 D0 Reservation ART2932 Data Acquisition V6
32. rol com englishs or CALL 86 0 10 51289836 CN 23 ART2932 Data Acquisition V6 021 Mode 1 Figure 2 Mode 2 Rate Generator Under this mode the counter is given the initial count value N and begins to count from N 1 OUT becomes high level When the count value becomes 0 OUT turns into low level After a CLK cycle OUT resumes high level and the counter automatically load the initial value N and begin to count from N 1 Thus the output will continue to output a negative pulse its width is equal to one clock cycle the clock number between the two negative pulses is equal to the initial value that is given to the counter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT If change the initial count when counting it will be effective next time Time diagram is shown in figure 3 Mode 2 OUT n 4 Figure 3 Mode 3 Square wave mode Similar to Mode 2 the counter is given the initial count value N and begins to count from N 1 When the signal of GATE is high level it starts to count timer counter begins to count by subtracting 1 each time more than half the initial count value The output OUT has remained high level when the count value is more than half of the initial count value but the output OUT becomes low level when the count value is less than half of the initial value If the initial count value N is an even number the output is 1 1 square wave if the initial count value N i
33. s an odd number the output OUT has remained high level during the previous n 1 2 count period but the output OUT becomes low level during the post n 1 2 count period that is the high level has one clock cycle more than the low level If change the initial BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 24 ART2932 Data Acquisition V6 021 count when counting it will be effective next time When GATE 0 the count is prohibited when GATE 1 the count is permitted Time diagram is shown in figure 4 Mode 3 Figure 4 Mode 4 Software triggered strobe Under this mode the counter is given the initial count value N and begins to count the output OUT becomes high level When the count value becomes 0 it immediately outputs a negative pulse which is equal to the width of one clock cycle If given a new count value when counting it will be effective immediately GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT Time diagram is shown in figure 5 Mode 4 GATE H GATE A l QUT Figure 5 Mode 5 Hardware triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it is called hardware trigger the output OUT has remained high level When the count value becomes 0 it outputs a negative pulse which is equal to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter
34. sampling period x the total number of sample channels x group cycles AD chips conversion time inter group interval External signal cycle cycle signal points group cycles x Group cycle External signal frequency 1 external signal cycle BUY ONLINE at art control com englishs or CALL 86 0 10 51289836 CN 19 ART2932 Data Acquisition V6 021 Under the external clock mode a fixed frequency external clock Group Cycle external clock cycle External signal cycle cycle signal points group cycles x group cycle External signal frequency 1 external signal cycle Formula Notes The internal sampling clock cycle 1 AD Para Frequency The total number of sampling channels AD Para Last Channel AD Para First Channel 1 Cycles of Group AD Para Loops of Group AD Chips conversion time see AD Analog Input Function parameter Inter group interval AD Para Group Interval Signal Cycle Points with the display of the waveform signal in test procedures we can use the mouse to measure the signal cycle points Under the internal clock mode for example sample two channel 0 1 and then 0 and 1 become a group Sampling frequency Frequency 100000Hz cycle is 10uS cycles of group is 1 inter group interval Group Interval 50uS then the acquisition process 1s to collect a set of data first including a data of channel 0 and a data of channel 1 We need 10uS to sample the two data 20uS to convert the d
35. ter 3 Signal Connectors 3 1 The Definition of Signal Input and Output Connectors 34 pin PI definition AOO 34 AO1 AQ2 32 AO3 ATR 30 AGND AGND 28 AGND AIQ 26 AII AD 24 AI3 Al4 22 AIS Al6 20 Al7 AIS 18 A19 AILO 16 AIII All2 14 All3 All4 12 AllS AGND 10 AGND AGND 8 AGND DTR 6 CLKOUT DGND 4 DGND DGND 2 DGND Pin definition PAGND __ Analog ground This AGND pin should be connected to the system s AGND plane DGND Digital ground Ground reference for Digital circuitry This DGND pin should be connected to the system s DGND plane CLK OUT Internal clock output when allow clock output it is internal clock output otherwise it is CNT counter output DGND for reference ground Analog trigger signal input choose AGND as reference ground Digital trigger signal input choose DGND as reference ground ART2932 Data Acquisition V6 021 3 2 Digital Input Output Connectors 34 pin P2 definition 5 V l 5V DIO 3 DII DI2 5 DI3 DI4 7 DIS DI6 9 DI7 DGND 11 DGND DOO 13 DOI DO2 15 DO3 DO4 17 DOS DO6 19 DO7 DGND 21 DGND OUTO 23 GATEO CLKO 23 QUTI GATEI 27 CLKI OUT2 29 GATE2 CLK2 3 DGND CLK 33 DGND Pin definition about P1 DIO DI7 Digital input DO0 DO7 Digital output Digital ground DGND GND CLKO CLK2 Input GATEO GATE2 OUTO OUT2 Output Counter 0 3 channels clock input Counter 0 3 channels gate Counter 0 3 channels output Output 45V ART2932 Data Acquisition V6 021
36. witch No 1 2 3 4 correspond to address bits A2 A3 A4 A5 are reserved bit Board base address selection is as follows when the ADDRI switches dial to ON that means high virtual value is 1 the switch to the other side means the low virtual is 0 Board base address selection switch ADDR I shown as following Base address configuration methods Address bit All A10 I The third hex bits The second hex bits The first hex bits Note in the table the bit which is labeled O is a fixed value only the bit that labeled x can be changed by the ADDRI For example the default base addresses is300H A8 A9 ON shown as the following A9 A8 A7 A6 A5 A4 A3 A2 8 6 5 4 3 2 1 ADDRI ON ART2932 Data Acquisition Common base address All Al0O A9 A8 A7 A6 6 5 4 3 2 I All AlO A9 A8 A7 A6 6 5 4 3 2 l All AlO A9 A8 A7 A6 All AlO A9 A8 A7 A6 6 5 4 3 2 1 6 5 4 All AlO A9 A8 A7 A6 3 2 l 6 5 4 3 2 l All Al0O A9 A8 A7 A6 6 5 4 3 All AlO A9 A8 A7 A6 2 l 6 5 4 3 2 l All AlO A9 A8 A7 A6 6 5 4 3 2 1 2 2 4 Status Lights EF FIFO non emptv indicator HF FIFO half full indicator FF FIFO overflow indicator ART2932 Data Acquisition V6 021 Chap
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