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MIPS32® 4KEc™ Processor Core Datasheet October 29

1. Table 1 4KEc Core High Performance Integer Multiply Divide Unit Latencies and Repeat Rates Operand Size mul r Repeat Opcode div rs Latency Rate MULT MULTU 16 bits 1 1 MADD MADDU MSUB MSUBU 32 bits 2 2 16 bits 2 1 MUL 32 bits 3 2 8 bits 12 11 16 bits 19 18 DIV DIVU 24 bits 26 25 32 bits 33 32 The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers Using the Move From HI MFHI and Move From LO MFLO instructions these values can be transferred to the general purpose register file In addition to the HI LO targeted operations the MIPS32 architecture also defines a multiply instruction MUL which places the least significant results in the primary register file instead of the HI LO register pair By avoiding the explicit MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Two other instructions multiply add MADD and multiply subtract MSUB are used to perform the multiply accumulate and multiply subtract operations The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD and MSUB operations are commonly used in DSP algorith
2. Integer register file sets 1 2 or 4 Integer register file implementation style Flops or generator N A TLB Size TLB support for 1KB pages TLB data array implementation style MIPS 16e support 16 or 32 dual entries Config mmusize Present or not Config3sp Flops or generator Present or not N A Configlca MIPS 16e implementation style Min area or max speed N A EJTAG TAP controller Present or not N A Instruction data hardware breakpoints 0 0 2 1 or 4 2 DCRjp IBSgcn DCRpp DBSgcn MIPS Trace support Present or not Config3 77 MIPS Trace memory location MIPS Trace on chip memory size On core or off chip 256B 8MB TCBCONFIGoy1 TCBCONFIG6pr TCBCONFIG 7 MIPS Trace triggers TCBCONFIGzRIG Watch registers WatchHiy CorExtend interface Pro only Coprocessor2 interface Instruction ScratchPad RAM interface Data ScratchPad RAM interface Present or not Configypr Present or not Configlc2 Present or not Configysp Present or not Configpsp I cache size 0 64 KB Config Config ys I cache associativity 1 2 3 or 4 Configl i These bits indicate the presence of an external block Bits will not be set if interface is present but block is not 18 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserve
3. 000 8 1 Trace clock is eight times the core clock 001 4 1 Trace clock is four times the core clock 2 1 Trace clock is double the core clock 1 1 Trace clock is same as the core clock 1 2 Trace clock is one half the core clock 1 4 Trace clock is one fourth the core clock 1 6 Trace clock is one sixth the core clock 1 8 Trace clock is one eight the core clock TC_CRMax 2 0 Maximum clock ratio supported This static input sets the CRMax field of the TCBCONFIG register It defines the capabilities of the Probe Interface Block PIB module This field determines the minimum value of TC_ClockRatio TC_CRMin 2 0 TC_ProbeWidth 1 0 TC_PibPresent TC_TrEnable MIPS32 4KEc Processor Core Datasheet Revision 02 01 Minimum clock ratio supported This input sets the CRMin field of the TCBCONFIG register It defines the capabilities of the PIB module This field determines the maximum value of TC_ClockRatio This static input will set the PW field of the TCBCONFIG register If this interface is not driving a PIB module but some chip level TCB like module then this field should be set to 2 b11 reserved value for PW Number physical TC_ProbeWidth data pin on PIB 00 4 bits 01 8 bits 10 16 bits 11 Not directly to PIB Must be asserted when a PIB is attached to the TC Interface When de asserted low all the other inputs are disregarded Trace
4. EB_BE 3 EB_RData 31 24 EB_WData 31 24 EB_A 35 2 o Address lines for external bus Only valid when EB_AValid is asserted EB_A 35 32 are tied to 0 in this core EB_WData 31 0 O Output data for writes EB_RData 31 0 I Input Data for reads Indicates that the target is driving read data on EB_RData lines EB_RdVal must always be EB_RdVal I valid EB_RdVal may never be sampled asserted until the rising edge after the corresponding EB_ARdy was sampled asserted MIPS32 4KEc Processor Core Datasheet Revision 02 01 29 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 13 4KEc Signal Descriptions Continued Signal Name Type Description Indicates that the target of a write is ready The EB_WData lines can change in the next clock EB_WDRdy I cycle EB_WDRdy will not be sampled until the rising edge where the corresponding EB_ARdy is sampled asserted Bus error indicator for read transactions EB_RBErr is sampled on every rising clock edge EB_RBErr I until an active sampling of EB_RdVal EB_RBErr sampled with asserted EB_RdVal indicates a bus error during read EB_RBErr must be deasserted in idle phases Bus error indicator for write transactions EB_WBErr is sampled on the rising clock edge EBL WBE l following an active sample of EB_WDRdy EB_WBErr must be deasserted in idle phases Indicates that any external write buffers are empty The external write buffers must deassert EB_EWBE I EB_EWBE in the cycl
5. Rt TrapException TN Trap if Not Equal if Rs int Immed TrapException WAIT Wait for Interrupts Stall until interrupt occurs WRPGPR Write to GPR in Previous Shadow Set SGPR SRSCtlpgg Rd Rt WSBH Word Swap Bytes Within HalfWords eo ee l Rt7 0 Rtis s E XOR Exclusive OR Rd Rs Rt R TNEI Trap if Not Equal Immediate ZEB Zero extend byte MIPS16 only t ubyte Rs ZEH Zero extend half MIPS16 only Rt uhalf Rs External Interface Signals The pin direction key for the signal descriptions is shown in Table 12 below This section describes the signal interface of the 4KEc microprocessor core The 4KEc core signals are listed in Table 13 below Note that the signals are grouped by logical function not by expected physical location All signals with the exception of EJ_TRST_N are active high signals EJ_DINT and MIPS32 4KEc Processor Core Datasheet Revision 02 01 25 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved SI_NMI go through edge detection logic so that only one exception is taken each time they are asserted Dir I Input to the 4KEc core sampled on the rising edge of the appropriate CLK signal Output of the 4KEc core unless otherwise noted driven at the rising edge of the appropriate CLK signal Asynchronous inputs that are synchronized by the core Table 12 4KEc Core Signal Direction Key Description Static input to the 4KEc core
6. Specifies which outstanding From COP Op the data is for Valid only when CP2_fds_0 is asserted CP2_forder_O 2 0 Order 000 Oldest outstanding From COP Op data transfer 0015 2nd oldest From COP Op data transfer 010 3rd oldest From COP Op data transfer CP2_forder_0 2 0 I Olly 4th oldest From COP Op data transfer 1005 5th oldest From COP Op data transfer 1015 6th oldest From COP Op data transfer 110 7th oldest From COP Op data transfer 111 8th oldest From COP Op data transfer Note Only values 000 and 001 are allowed see CP2_fordlim_0 2 0 below From Coprocessor Data Out of Order Limit This signal sets the limit on how much the coprocessor can reorder From COP Data The value on this signal corresponds to the maximum allowed value to be used on CP2_forder_0 2 0 CP2_fordlim_0 2 0 O Note The 4KEc core can handle one Out of Order From Data transfer CP2_fordlim_0 2 0 is therefore tied to 001 The core will also never have more than two outstanding From COP instructions issued which also automatically limits CP2_forder_O 2 0 to 0015 CP2_fdata_0 31 0 I From Coprocessor Data Data to be transferred from coprocessor Valid when CP2_fds_0 is asserted Coprocessor Condition Code Check These signals are used to report the result of a condition code check to the 4KEc core from the COP2 coprocessor This is only used for BC2 instructions CP2 cecs 0 I Coprocessor Condition Code Check Strobe Asserted when coprocessor condition
7. These signals are normally tied to either power or ground and should not change state while S7_ColdReset is deasserted Table 13 4KEc Signal Descriptions Signal Name Description System Interface SI_ColdReset SI_NMI SI_Reset Power Management Signals Clock Signals Clock Input All inputs and outputs except a few of the EJTAG signals are sampled and or SLClkIn i cares asserted relative to the rising edge of this signal SI ClkOut Reference Clock for the External Bus Interface This clock signal provides a reference for deskewing any clock insertion delay created by the internal clock buffering in the core Reset Signals Hard Cold Reset Signal Causes a Reset Exception in the core Non Maskable Interrupt An edge detect is used on this signal When this signal is sampled asserted high one clock after being sampled deasserted an NMI is posted to the core Soft Warm Reset Signal Causes a Reset Exception in the core Sets Status SR bit if SI_ColdReset is not asserted but is otherwise ORed with S7_ColdReset before it is used internally This signal represents the state of the ERL bit 2 in the CPO Status register and indicates the SI_EICPresent SILERL error level The core asserts S1_ERL whenever a Reset Soft Reset or NMI exception is taken This signal represents the state of the EXL bit 1 in the CPO Status register and indicates SI_EXL the exception level The cor
8. 1 for the 4KEc core when CorExtend is not enabled e External Interrupt Controller EIC mode which Ov Execution of an arithmetic instruction redefines the way in which interrupts are handled to that overflowed provide full support for an external interrupt controller handling prioritization and vectoring of interrupts This Execution of a trap when trap Tr condition is true presence of this mode denoted by the VEIC bit in the Config3 register Again this mode is architecturally PAG Data Address Break address optional On the 4KEc core the VEIC bit is set DDBL DDBS only or EJTAG Data Value Break on Bit externally by the static input SI _EICPresent to allow Store address value mee system logic to indicate the presence of an external WATCH A reference to an address in one of the interrupt controller watch registers data Load address alignment error The reset state of the processor is to interrupt compatibility AdEL uae Aki mode such that a processor supporting Release 2 of the OPES 10 protected address Architecture like the 4KEc core is fully compatible with Store address alignment error implementations of Release 1 of the Architecture AdES Store to protected address f i VI or EIC interrupt modes can be combined with the TLBL Load TLB miss optional shadow registers to specify which shadow set should be used upon entry to a particular vector The shadow registers further improve interru
9. COP2 Condition True PC int offset MIPS32 4KEc Processor Core Datasheet Revision 02 01 19 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 20 Instruction Table 11 4KEc Core Instruction Set Continued Description Branch On COP2 Condition True Likely Branch On Equal Branch On Equal Likely Branch on Greater Than or Equal To Zero if COP2Condition cc 1 PC int offset else Ignore Next Instruction if Rs Rt PC int offset if Rs Rt PC int offset else Ignore Next Instruction BGEZAL BGEZALL Branch on Greater Than or Equal To Zero And Link Branch on Greater Than or Equal To Zero And Link Likely GPR 31 if Rs PC else Ignore Next Instruction Branch on Greater Than or Equal To Zero Likely if Rs 31 PC int offset else Ignore Next Instruction Branch on Greater Than Zero Branch on Greater Than Zero Likely BLEZ Branch on Less Than or Equal to Zero Branch on Less Than or Equal to Zero Likely Branch on Less Than Zero if Rs 31 amp amp Rs 0 PC int offset if Rs 31 amp amp Rs 0 PC int offset else Ignore Next Instruction if Rs 31 Rs 0 PC int offset if Rs 31 Rs 0 PC int offset else Ignore Next Instruction BLTZAL BLTZALL Branch on Less Than Zero And Link Branch on Less Than Zero And Link Likely if Rs 3
10. Enable when asserted the PIB must start running its output clock and can expect valid data on all other outputs Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 35 Signal Name Type Table 13 4KEc Signal Descriptions Continued Description TC_Calibrate This signal is asserted when the Cal bit in the TCBCONTROLB register is set For a simple PIB which only serves one TCB this pin can be ignored For a multi core capable PIB which also uses TC_Valid and TC_Stall the PIB must start producing the calibration pattern when this signal is asserted TC_DataBits 2 0 TC_Valid This input identifies the number of bits picked up by the probe interface module in each cycle If TC_ClockRatio indicates a clock ratio higher than 1 2 then clock multiplication in the Probe logic is used The cycle is equal to each core clock cycle If TC_ClockRatio indicates a clock ratio lower than or equal to 1 2 then cycle is clock ratio 2 of the core clock cycle For example with a clock ratio of 1 2 a cycle is equal to core clock cycle with a clock ratio of 1 4 a cycle is equal to one half of core clock cycle This input controls the down shifting amount and frequency of the trace word on TC_Data 63 0 The bit width and the corresponding TC_DataBits value is shown in the table below Probe uses following bits from TC_Data each TC_DataBits 2 0 cycle 000 TC_Data 3
11. O CP2_inst32_0 O CP2_kd_mode_0 O Big Endian Byte Ordering When asserted the processor is using big endian byte ordering for the dispatched instruction When deasserted the processor is using little endian byte ordering Valid the cycle before CP2_as_0 CP2_fs_0 or CP2_ts_0 is asserted MIPS32 Compatibility Mode Instructions When asserted the dispatched instruction is restricted to the MIPS32 subset of instructions Please refer to the MIPS64 architecture specification for a complete description of MIPS32 compatibility mode Valid the cycle before CP2_as_0 CP2_fs_0 or CP2_ts_0 is asserted Note The 4KEc core is a MIPS32 core and will only issue MIPS32 instructions Thus CP2_inst32_0 is tied high Kernel Debug Mode When asserted the processor is running in kernel or debug mode Can be used to enable privileged coprocessor instructions Valid the cycle before CP2_as_0 CP2_fs_0 or CP2_ts_0 is asserted a To Coprocessor instruction To Coprocessor Data These signals are used when data is sent from the 4KEc core to the COP2 coprocessor as part of completing CP2_tds_0 O Coprocessor To Data Strobe Asserted when To COP Op data is available on CP2_tdata_0 31 0 CP2_torder_0 2 0 O Coprocessor To Order Specifies which outstanding To COP Op the data is for Valid only when CP2_tds_0 is asserted CP2_torder_0 2 0 Order 0005 Oldest outstanding To COP Op data transfer 001 2nd oldest To COP Op dat
12. The 4KEc core provides two mechanisms for system level low power support e Register controlled power management e Instruction controlled power management Register Controlled Power Management The RP bit in the CPO Status register provides a software mechanism for placing the system into a low power state The state of the RP bit is available externally via the SI _RP 14 signal The external agent then decides whether to place the device in a low power mode such as reducing the system clock frequency Three additional bits Statusgy Statusppy and Debugpm support the power management function by allowing the user to change the power state if an exception or error occurs while the 4KEc core is in a low power state Depending on what type of exception is taken one of these three bits will be asserted and reflected on the S _EXL SI_ERL or EJ_DebugM outputs The external agent can look at these signals and determine whether to leave the low power state to service the exception The following 4 power down signals are part of the system interface and change state as the corresponding bits in the CPO registers are set or cleared e The SI_RP signal represents the state of the RP bit 27 in the CPO Status register e The SI_EXL signal represents the state of the EXL bit 1 in the CPO Status register e The SI_ERL signal represents the state of the ERL bit 2 in the CPO Status register e The EJ_DebugM signal represents
13. This allows the controller to advance to another pending higher priority interrupt if desired Active high Interrupt pins These signals are driven by external logic and when asserted indicate an interrupt exception to the core The interpretation of these signals depends on the interrupt mode in which the core is operating the interrupt mode is selected by software The S _Int signals go through synchronization logic and can be asserted asynchronously to SI_Clkin In External Interrupt Controller EIC mode however the interrupt pins are interpreted as an encoded value so they must be asserted synchronously to SJ_ClkIn to guarantee that all bits are received by the core in a particular cycle The interrupt pins are level sensitive and should remain asserted until the interrupt has been serviced In Release 1 Interrupt Compatibility mode e All 6 interrupt pins have the same priority as far as the hardware is concerned e Interrupts are non vectored In Vectored Interrupt VI mode The SI_Int pins are interpreted as individual hardware interrupt requests e Internally the core prioritizes the hardware interrupts and chooses an interrupt vector In External Interrupt Controller EIC mode e An external block prioritizes its various interrupt requests and produces a vector number of the highest priority interrupt to be serviced The vector number is driven on the S _Int pins and is treated as a 6 bit encoded value in the range
14. bit and a lock bit There is an additional array holding dirty bits and LRU replacement algorithm bits 0 6b depending on associativity for each set of the cache In addition to instruction cache locking the 4KEc core also supports a data cache locking mechanism identical to the instruction cache Critical data segments are locked into the cache on a per line basis The locked contents can be updated on a store hit but cannot be selected for replacement on a cache miss The cache locking function is always available on all data cache entries Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction Cache Memory Configuration The 4KEc core incorporates on chip instruction and data caches that can each be accessed in a single processor cycle Each cache has its own 32 bit data path and can be accessed in the same pipeline clock cycle Table 9 lists the 4KEc core instruction and data cache attributes Table 9 4KEc Core Instruction and Data Cache Attributes Size 0 64 Kbytes 0 64 Kbytes associative associative Line Size 16 bytes 16 bytes Read Unit 32 bits 32 bits write through with write allocate Write Policies na wale through without write allocate write back with write allocate Miss restart after r miss word miss word transfer of Cache Locking per line per line Cache Protocols The 4KEc core supports the following cache protocols e Unca
15. e A 16x16 or 32x16 multiply operation performs the carry propagate add The actual register writeback is performed in the W stage e A MUL operation makes the result available for writeback The actual register writeback is performed in the W stage W Stage Writeback During the Writeback stage e For register to register or load instructions the instruction result is written back to the register file 4KEc Core Required Logic Blocks The 4KEc core consists of the following required logic blocks shown in Figure 1 These logic blocks are defined in the following subsections e Execution Unit e Multiply Divide Unit MDU e System Control Coprocessor CPO e Memory Management Unit MMU e Transition Lookaside Buffer TLB e Cache Controller Bus Interface Unit BIU e Power Management Execution Unit The 4KEc core execution unit implements a load store architecture with single cycle ALU operations logical shift add subtract and an autonomous multiply divide unit The 4KEc core contains thirty two 32 bit general purpose registers used for integer operations and address calculation Optionally one or three additional register file shadow sets each containing thirty two registers can be added to minimize context switching overhead during interrupt exception processing The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline The execut
16. mask can be applied to the virtual address to set breakpoints on a range of instructions Data breakpoints occur on load store transactions Breakpoints are set on virtual address and ASID values similar to the Instruction breakpoint Data breakpoints can be set on a load a store or both Data breakpoints can also be set based on the value of the load store operation Finally masks can be applied to both the virtual address and the load store value MIPS Trace The 4KEc core includes optional MIPS Trace support for real time tracing of instruction addresses data addresses and data values The trace information is collected in an on chip or off chip memory for post capture processing by trace regeneration software On chip trace memory may be configured in size from 0 to 8 MB it is accessed through the existing EJTAG TAP interface and requires no additional chip pins Off chip trace memory is accessed through a special trace probe and can be configured to use 4 8 or 16 data pins plus a clock Testability Testability for production testing of the core is supported through the use of internal scan and memory BIST Internal Scan Full mux based scan for maximum test coverage is supported with a configurable number of scan chains ATPG test coverage can exceed 99 depending on standard cell libraries and configuration options Memory BIST Memory BIST for the cache arrays and on chip trace memory is optional but can be i
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18. to zero Indicates the base endianness of the core EB_Endian Base Endian Mode 0 Little Endian 1 Big Endian SI_MergeMode 1 0 SI_SimpleBE 1 0 The state of these signals determines the merge mode for the 16 byte collapsing write buffer Encoding Merge Mode 00 No Merge Ol Reserved 10 Full Merge 11 Reserved The state of these signals can constrain the core to only generate certain byte enables on EC interface transactions This eases connection to some existing bus standards SI_SimpleBE 1 0 Byte Enable Mode 00 All BEs allowed Naturally aligned bytes half words and words only 102 Reserved 01 11 Reserved External Bus Interface 28 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 13 4KEc Signal Descriptions Continued Signal Name Type Description Indicates whether the target is ready for a new address The core will not complete the EB_ARdy I address phase of a new bus transaction until the clock cycle after EB_ARdy is sampled asserted EB AValid o When asserted indicates that the values on the address bus and access types lines are valid E signifying the beginning of a new bus transaction EB_AValid must always be valid EB Instr o When asserted indicates that the tr
19. 0 001 TC_Data 7 0 010 TC_Data 15 0 011 TC_Data 31 0 100 TC_Data 63 0 Others Unused This input might change as the value on TC_ClockRatio 2 0 changes Asserted when a valid new trace word is started on the TC_Data 63 0 signals TC_Valid is only asserted when TC_DataBits is 100 TC_Stall When asserted a new TC_Valid in the following cycle is stalled TC_Valid is still asserted but the TC_Data value and TC_Valid are held static until the cycle after TC_Stall is sampled low TC_Stall is only sampled in the cycle before a new TC_Valid cycle and only when TC_DataBits is 100 indicating a full word of TC_Data TC_Data 63 0 Trace word data The value on this 64 bit interface is shifted down as indicated in TC_DataBits 2 0 In the first cycle where a new trace word is valid on all the bits and TC_DataBits 2 0 is 100 TC_Valid is also asserted The Probe Interface Block PIB will only be connected to N 1 0 bits of this output bus N is the number of bits picked up by the PIB in each core clock cycle For clock ratios 1 2 and lower N is equal to the number of physical trace pins legal values of N are 4 8 or 16 For higher clock ratios N is larger than the number of physical trace pins TC_ProbeTrigIn Rising edge trigger input The source should be the Probe Trigger input The input is considered asynchronous i e it is double registered in the core TC_ProbeTrigOut Single cycle re
20. 1 PC int offset else Ignore Next Instruction MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 11 4KEc Core Instruction Set Continued Instruction Description if Rs 31 PC int offset else Branch on Less Than Zero Likely Ignore Next Instruction if Rs Rt Branch on Not Equal Bo 4a ah Sitst if Rs Rt PC int offset else Branch on Not Equal Likely Ignore Next Instruction BREAK Breakpoint Break Exception CACHE Cache Operation See Software User s Manual Move Control Word From Coprocessor 2 CCR 2 n Count Leading Ones NumLeadingOnes Rs Count Leading Zeroes Rd NumLeadingZeroes Rs Coprocessor 0 Operation See Software User s Manual COP2 Coprocessor 2 Operation See Coprocessor 2 Description CTC2 Move Control Word To Coprocessor 2 DERET Return from Debug Exception Peet Exit Debug Mode Atomically Disable Interrupts Rt Status Statustp 0 LO int Rs int Rt HI int Rs int Rt Divide LO uns Rs uns Rt Unsigned Divide HI uns Rs uns Rt Stop instruction execution Execution Hazard Barrier until execution hazards are cleared Atomically Enable Interrupts Rt Status Status 1 if SR 2 PC ErrorEPC Return from Exception Rt ExtractField Rs pos size Extract Bit Field Rt InsertField Rs Rt pos size Ins
21. B ITLB and a 4 entry fully associative data TLB DTLB When an instruction address is calculated the virtual address is compared to the contents of the 4 entry ITLB If the address is not found in the ITLB the JTLB is accessed If the entry is found in the JTLB that entry is then written into the ITLB If the address is not found in the JTLB a TLB refill exception is taken When a data address is calculated the virtual address is compared to both the 4 entry DTLB and the JTLB If the address is not found in the DTLB but is found in the JTLB that address is immediately written to the DTLB If the address is not found in the JTLB a TLB refill exception is taken Figure 4 shows how the ITLB DTLB and JTLB are implemented in the 4KEc core Instruction Cache Tag RAM Virtual Address Instruction Address Calculator Instruction Hit Miss Data Hit Miss Data Comparator Address DTLB P Calculator Virtual Address Figure 4 Address Translation During a Cache Access Translation Lookaside Buffer TLB The TLB consists of three address translation buffers e 16 dual entry fully associative Joint TLB JTLB e 4 entry fully associative Instruction TLB ITLB e 4 entry fully associative Data TLB DTLB Joint TLB JTLB The 4KEc core implements a 16 or 32 dual entry fully associative JTLB that maps 32 virtual pages to their corresponding physical addresses The purp
22. Coprocessor 2 Rt Rd sel 3 MFHI Move From HI Rd Move From LO if Rt 0 then Move Conditional on Not Zero Rd Rs 22 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 11 4KEc Core Instruction Set Continued me if Rt h MOVZ Move Conditional on Zero 5 Xe he pagn MSUB Multiply Subtract HI LO int Rs int Rt MSUBU Multiply Subtract Unsigned HI LO uns Rs uns Rt Move To Coprocessor 0 CPR 0 n Sel Rt Move To Coprocessor 2 CPR 2 n sel Rt CPR 2 Rd sel Move To High Half of Coprocessor 2 CPR 2 Rd sells o Move To HI Move To LO LO Unpredictable Multiply with register write int Rs int Rt 31 0 MULT Integer Multiply HI LO int Rs int Rd MULTU Unsigned Multiply HI LO uns Rs uns Rd C kiicawwe RI Rt Rs O Logical OR Immediate Immed S PREF Prefetch Load Specified Line into Cache Allows unprivileged access to RDHWR Read Hardware Register registers enabled by HWREna register RDPGPR Read GPR from Previous Shadow Set Rt SGPR SRSCtlpgg Rd Restore registers and deallocate stack frame RESTORE MIPS16 only See Architecture Reference Manual ROTR Rotate Word Right Rd Rtsa 1 0 Rt31 sa ROTRV Rotate Word Right Variable R Rtrs 1 0 Rt31 Rs d Save registers and allocate stack frame MIPS 16
23. Coprocessor 2 interface CorExtend User Defined Instruction UDI interface e MIPS16e support e Enhanced JTAG EJTAG Controller The section entitled 4KEc Core Required Logic Blocks on page 4 discusses the required blocks The section entitled 4KEc Core Optional Logic Blocks on page 15 discusses the optional blocks Pipeline Flow The 4KEc core implements a 5 stage pipeline with performance similar to the R3000 pipeline The pipeline allows the processor to achieve high frequency while minimizing device complexity reducing both cost and power consumption The 4KEc core pipeline consists of five stages e Instruction I Stage e Execution E Stage e Memory M Stage e Align A Stage e Writeback W stage The 4KEc core implements a bypass mechanism that allows the result of an operation to be forwarded directly to MIPS32 4KEc Processor Core Datasheet Revision 02 01 the instruction that needs it without having to write the result to the register and then read it back Figure 2 shows a timing diagram of the 4KEc core pipeline ee bee ay i I E M A w i Bypass l i Bypass I Cache_ __ RegRa _ALUO l l I TLB I Dec D AC D Cache _ Align l i D TLB i i i LAI LA2 i l l i i Bypass i i i Mul 16x16 32x16 Ree RegW l i X l Bypass l i Div J Ac RegW l i Figure 2 4KEc Core Pipeline I Stage Instruction Fetch During t
24. EB_BFirst EB Blast EB AValid EB_RData 31 0 V EB_RdVal EB_RBErr EB _Write ZU Figure 10 Burst Read Transaction Timing Diagram Figure 10 shows an example of a burst read transaction Burst read transactions initiated by the 4KEc core always contain four data transfers in a sequence determined by the critical word the address that caused the miss and EB_SBlock In addition the data requested is always a 16 byte aligned block The order of words within this 16 byte block varies depending on which of the words in the block is being requested by the execution unit and the ordering protocol selected The burst always starts with the word requested by the execution unit and proceeds in either an ascending or descending address order wrapping when the block boundary is reached Table 14 and Table 15 show the sequence of address bits 2 and 3 Table 14 Sequential Ordering Protocols Starting Address Address Progression EB_A 3 2 of EB_A 3 2 00 00 01 10 11 01 01 10 11 00 10 10 11 00 01 11 11 00 01 10 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 15 Sub Block Ordering Protocols Starting Address Address Progression EB_A 3 2 of EB_A 3 2 00 00 01 10 11 01 01 00 11 10 10 10 11 00 01 11 11 10 01 00 The 4KEc core drives address and contro
25. EJTAG Interface TAP interface These signals comprise the EJTAG Test Access Port These signals will not be connected if the core does not implement the TAP controller Active low Test Reset Input TRST for the EJTAG TAP At power up the assertion of EJ_TRST_N causes the TAP controller to be reset Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 33 Table 13 4KEc Signal Descriptions Continued Signal Name Type Description EJ_TCK I Test Clock Input TCK for the EJTAG TAP EJ_TMS I Test Mode Select Input TMS for the EJTAG TAP EJ_TDI I Test Data Input TDD for the EJTAG TAP EJ_TDO O Test Data Output TDO for the EJTAG TAP Drive indication for the output of TDO for the EJTAG TAP at chip level 1 The TDO output at chip level must be in Z state EJ_TDOzstate O 0 The TDO output at chip level must be driven to the value of EJ_TDO IEEE Standard 1149 1 1990 defines TDO as a 3 stated signal To avoid having a 3 state core output the 4KEc core outputs this signal to drive an external 3 state buffer Debug Interrupt EJ DINTsu s Value of DINTsup for the Implementation register When high this signal indicates that the P EJTAG probe can use the DINT signal to interrupt the processor Debug exception request when this signal is asserted in a CPU clock period after being EJ_DINT I deasserted in the previous CPU clock period The request is cleared when debug mode is entered Requests when in debug
26. Figure 8 shows the basic timing relationships of signals during a simple read transaction During a single read cycle the 4KEc core drives the address onto EB_A 35 2 and byte enable information onto EB_BE 3 0 To maximize performance the EC interface does not define a maximum number of outstanding bus cycles Instead it provides the EB_ARdy input signal This signal is driven by external logic and controls the generation of addresses on the bus In the 4KEc core the address is driven whenever it becomes available regardless of the state of EB_ARdy However the 4KEc core always continues to drive the address until the clock after EB_ARdy is sampled asserted For example at the rising edge of the clock 2 in Figure 8 the EB_ARdy signal is sampled low indicating that external logic is not ready to accept the new address However the 4KEc core still drives EB_A 35 2 in this clock as shown Signal Name Description Scan Test Interface These signals provide an interface for testing the core The use and configuration of these pins are implementation dependent This signal should be asserted while scanning vectors into or out of the core The gscanenable I gscanenable signal must be deasserted during normal operation and during capture clocks in test mode This signal should be asserted during all scan testing both while scanning and during capture gscanmode I clocks The gscanmode signal must be deasserted during normal operation This
27. Mis TECHNOLOGIES MIPS32 4KEc Processor Core Datasheet October 29 2004 The MIPS32 4KEc core from MIPS Technologies is a member of the MIPS32 4KE processor core family It is a high performance low power 32 bit MIPS RISC core designed for custom system on silicon applications The core is designed for semiconductor manufacturing companies ASIC developers and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high performance RISC processor It is highly portable across processes and can be easily integrated into full system on silicon designs allowing developers to focus their attention on end user products The 4KEc core is ideally positioned to support new products for emerging segments of the digital consumer network systems and information management markets enabling new tailored solutions for embedded applications The 4KEc core implements the MIPS32 Release 2 Architecture with the MIPS 16e ASE and the 32 bit privileged resource architecture The Memory Management Unit MMU contains 4 entry instruction and data Translation Lookaside Buffers TLB DTLB and a 16 or 32 dual entry joint TLB JTLB with variable page sizes The synthesizable 4KEc core includes a Multiply Divide Unit MDU that implements single cycle MAC instructions which enable DSP algorithms to be performed efficiently It allows 32 bit x 16 bit MAC instructions to be issued every cycle while a 32 bit x 32 bit MAC ins
28. PS MIPS I MIPS II MIPS III MIPS IV MIPS V MIPS 3D MIPS16 MIPS16e MIPS32 MIPS64 MIPS Based MIPSsim MIPS Technologies logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc 4KSd M4K 5K 5Kc 5Kf 20Kc 25Kf 24K 24Kc 24Kf R3000 R4000 R5000 ASMACRO ATLAS At The Core Of The User Experience BusBridge CorExtend CoreFPGA CoreLV EC FastMIPS JALGO MALTA MDMX MGB MIPS RISC CERTIFIED POWER logo PDTrace the Pipeline Pro Series QuickMIPS SEAD SEAD 2 SmartMIPS SOC it and YAMON are trademarks or registered trademarks of MIPS Technologies Inc in the United States and other countries All other trademarks referred to herein are the property of their respective owners Template B1 11 Built with tags 2B MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved
29. a transfer 0105 3rd oldest To COP Op data transfer oll 4th oldest To COP Op data transfer 1002 5th oldest To COP Op data transfer 101 6th oldest To COP Op data transfer 110 7th oldest To COP Op data transfer 1113 8th oldest To COP Op data transfer Note The 4KEc core will never send Data Out of Order thus CP2_torder_0 2 0 is tied to 0005 CP2_tordlim_0 2 0 S To Coprocessor Data Out of Order Limit This signal forces the integer processor core to limit how much it can reorder To COP Data The value on this signal corresponds to the maximum allowed value to be used on CP2_torder_0 2 0 Note The 4KEc core will never send Data Out of Order thus CP2_tordlim_O 2 0 is ignored CP2_tdata_0 31 0 O To Coprocessor Data Data to be transferred to the coprocessor Valid when CP2_tds_0 is asserted From Coprocessor Data These signals a From Coprocessor instruction are used when data is sent to the 4KEc core from the COP2 coprocessor as part of completing CP2_fds_0 I Coprocessor From Data Strobe Asserted when From COP Op data is available on CP2_fdata_0 31 0 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 31 Table 13 4KEc Signal Descriptions Continued Signal Name Type Description Coprocessor From Order
30. ables access via the RDHWR 7 instruction to selected hardware registers Reports the address for the most 8 BadVAddr SP recent address related exception 9 Count Processor cycle count 10 EntrvHi3 High order portion of the TLB y entry 11 Timer interrupt control 12 Status Processor status and control 12 IntCtl Interrupt system status and control Register Register Number Name Function T 23 User Trace control register Data 23 TraceBPC Trace breakpoint control 24 DEPC Program counter at last debug exception 25 Reserved in the 4KEc core 26 Used for software testing of cache arrays Shadow register set status and 12 SRSCtl control Provides mapping from vectored 1 liz nash interrupt to a shadow set 27 Reserved Reserved in the 4KEc core TagLo Low order portion of cache tag 28 DataLo interface 29 Reserved Reserved in the 4KEc core 30 ErrorEPC Program counter at last error 31 DESAVE Debug handler scratchpad register 1 Registers used in exception processing 2 Registers used during debug 3 Registers used in memory management 13 Cause Cause of last general exception 14 EPC Program counter at last exception 15 PRId Processor identification and revision 15 EBASE Exception vector base register 16 Configuration register 16 Configuration register 1 16 Config2 Configuration register 2 16 Config3 Conf
31. actions are used to empty one of the write buffers A burst write transaction is only performed if the write buffer contains 16 bytes of data associated with the same aligned memory block otherwise individual write transactions are performed Figure 11 shows a timing diagram of a burst write transaction Unlike the read burst a write burst always begins with EB_A 3 2 equal to 00b MIPS32 4KEc Processor Core Datasheet Revision 02 01 Clock 1 2 3 4 5 6 7 8 EB_Cik UHI EB_ARdy EB_A 35 2 Aari N Aar N Aars N Aan EB_BE 3 0 EB_Write EB_Burst EB_BFirst Driven by _ EB_BLast system logic EB_AValid EB_WData 31 Datat Data2 Data3 X Dfta4 EB_WDRdy it ra EB_WBErr LIX Figure 11 Burst Write Transaction Timing Diagram The 4KEc core drives address and control information onto the EB_A 35 2 and EB_BE 3 0 signals on the rising edge of clock 2 As in the single read cycle these signals remain active until the clock edge after the EB_ARdy signal is sampled asserted The 4KEc core continues to drive EB_AValid as long as a valid address is on the bus The 4KEc core asserts the EB_Write EB_Burst and EB_AValid signals during the time the address is driven EB_Write indicates that a write operation is in progress The assertion of EB_Burst indicates that the current operation is a burst EB_AValid indicates that valid address is on the bus T
32. ag Entry Fields Field Name Description Global Bit When set indicates that this entry is global to all processes and or threads and thus disables inclusion of the ASID in the comparison Address Space Identifier Identifies with ASID 7 0 which process or thread this TLB entry is associated Virtual Page Number divided by 2 This field contains the upper bits of the virtual page number Because it represents a pair of TLB pages it is divided by 2 Bits 31 25 are always included in the TLB lookup comparison Bits 24 11 are included depending on the page size VPN2 31 25 VPN2 24 11 Compressed page mask value This field is a compressed version of the page mask It defines the page size by masking the appropriate VPN2 bits from being involved comparison It is also used to determine which address bit is used to make the even odd page determination CMASK 7 0 Figure 7 and Table 6 show the TLB data array entry format MIPS32 4KEc Processor Core Datasheet Revision 02 01 11 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved PFN 31 12 or 29 10 C 2 0 D v 20 3 1 1 Figure 7 TLB Data Array Entry Format Table 6 TLB Data Array Entry Fields Field Name Description Physical Frame Number Defines the upper bits of the physical address The 29 10 range illustrates that if 1Kbytes page granularity is enabled in the PageGrain register
33. al values in the mask register and the selected page size Table 4 Mask and Page Size Values Even Odd Bank Pagemask 28 11 Page Size Select Bit 000000000000000000 VAddr 10 00000000000000001 1 4KB VAddr 12 000000000000001 111 16KB VAddr 14 000000000000111111 64KB VAddr 16 000000000011111111 256KB VAddr 18 000000001111111111 1MB VAddr 20 000000111111111111 4MB VAddr 22 000011111111111111 16MB VAddr 24 001111111111111111 64MB VAddr 26 111111111111111111 256MB VAddr 28 TLB Tag and Data Formats Figure 6 shows the format of a TLB tag entry The entry is divided into the follow fields e Global process indicator e Address space identifier e Virtual page number e Compressed page mask Setting the global process indicator G bit indicates that the entry is global to all processes and or threads in the system In this case the 8 bit address space identifier ASID value is ignored since the entry is not relative to a specific thread or process The ASID helps to reduce the frequency of TLB flushing on a context switch The existence of the ASID allows multiple processes to exist in both the TLB and instruction caches The current ASID value is stored in the EntryHi register and is compared to the ASID value of each entry Figure 6 and Table 5 show the TLB tag entry format G ASID 7 0 VPN2 31 25 VPN2 24 11 Jemaskr7 o 1 8 7 14 Figure 6 TLB Tag Entry Format Table 5 TLB T
34. and tag write value For tag comparison the bus usage is PA 31 10 2 b0 and contains the address to DSP TagCmpValue 23 0 9 determine hit miss For tag writes the bus contains PA 31 10 Lock Valid from the TagLo register DSP_DataAddr 19 2 Virtual index into the SPRAM used for data reads and writes DSP_DataWrValue 31 0 Data Write Value Data value to be written to the data array DSP_DataRdStr Data Read Strobe Indicates that the data array should be read DSP_DataWrStr Data Write Strobe Indicates that the data array should be written ololojojo DSP_DataWrMask 3 0 Data Write Mask Byte enables for a data write MIPS32 4KEc Processor Core Datasheet Revision 02 01 37 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 13 4KEc Signal Descriptions Continued Signal Name Type Description DSP_DataRdValue 3 1 0 I Data Read Value Data value read from the data array Tag Read Value Tag value read from the tag array Written to TagLo register on a CACHE DSP_TagRdValue 23 0 l instruction Read value maps into these TagLo fields PA 31 10 Lock Valid DSP_Hit I Hit Indicates that this read was to an address covered by the SPRAM DSP_Stall I Stall Indicates that the read has not yet completed DSP_Present S Present Indicates that a SPRAM array is connected to this port ISP_Addr 19 2 O Virtual index into the SPRAM used for bot
35. ansaction is an instruction fetch versus a data reference T EB_Instr is only valid when EB_AValid is asserted EB_ Write o When asserted indicates that the current transaction is a write This signal is only valid when EB_AValid is asserted When asserted indicates that the current transaction is part of a cache fill or a write burst EB Burst O Note that there is redundant information contained in EB_Burst EB_BFirst EB_BLast and EB_BLen This is done to simplify the system design the information can be used in whatever form is easiest EB_BFirst O When asserted indicates the beginning of the burst EB_BFirst is always valid EB_BLast O When asserted indicates the end of the burst EB_BLast is always valid Indicates the length of the burst This signal is only valid when EB_AvValid is asserted EB_BLength 1 0 Burst Length 0 reserved EB_BLen 1 0 O 1 4 2 reserved 3 reserved Static input which determines burst order When asserted sub block ordering is used When EB_SBlock S R deasserted sequential addressing is used Indicates which bytes of the EB_RData or EB_WData buses are involved in the current transaction If an EB_BE signal is asserted the associated byte is being read or written EB_BE lines are only valid while EB_AValid is asserted EB BE Read Data Bits Write Data Bits Signal Sampled Driven Valid EB_BE 3 0 9 EB_BE 0 EB_RData 7 0 EB_WData 7 0 EB_BE 1 EB_RData 15 8 EB_WData 15 8 EB_BE 2 EB_RData 23 16 EB_WData 23 16
36. at cover the information in this document The information contained in this document shall not be exported reexported transferred or released directly or indirectly in violation of the law of any country or international law regulation treaty Executive Order statute amendments or supplements thereto Should a conflict arise regarding the export reexport transfer or release of the information contained in this document the laws of the United States of America shall be the governing law The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MI
37. be asserted in the same cycle that CP2_ts_0 or CP2_fs_0 is asserted CP2_as_0 O Coprocessor2 Arithmetic Busy When asserted a coprocessor2 arithmetic instruction will CP2abusy 0 l not be dispatched CP2_as_0 will not be asserted in the cycle after this signal is asserted Coprocessor2 To Strobe Asserted in the cycle after a To COP2 Op instruction is available on CP2_ir_0 31 0 If CP2_tbusy was asserted in the previous cycle this signal will not be asserted This signal will never be asserted in the same cycle that CP2_as_0 or CP2_fs_0 is asserted CP2_ts_0 O To Coprocessor2 Busy When asserted a To COP2 Op will not be dispatched CP2_ts_0 will CE2 itbusyi0 l not be asserted in the cycle after this signal is asserted Coprocessor2 From Strobe Asserted in the cycle after a From COP2 Op instruction is available on CP2_ir_0 31 0 If CP2_fbusy_0 was asserted in the previous cycle this signal will not be asserted This signal will never be asserted in the same cycle that CP2_as_0 or CP2_ts_0 is asserted CP2_fs_0 O From Coprocessor2 Busy When asserted a From COP2 Op will not be dispatched CP2_fbusy_0 CP2_fs_0 will not be asserted in the cycle after this signal is asserted 30 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 13 4KEc Signal Descriptions Continued Signal Name Type Description CP2_endian_0
38. bit Address and Data Paths MIPS32 Compatible Instruction Set Multiply Accumulate and Multiply Subtract Instructions MADD MADDU MSUB MSUBU Targeted Multiply Instruction MUL Zero One Detect Instructions CLZ CLO Wait Instruction WAIT Conditional Move Instructions MOVZ MOVN Prefetch Instruction PREF MIPS32 Enhanced Architecture Release 2 Features Vectored interrupts and support for external interrupt controller Programmable exception vector base Atomic interrupt enable disable GPR shadow registers optionally one or three additional shadows can be added to minimize latency for interrupt handlers Bit field manipulation instructions Improved virtual memory support smaller page sizes and hooks for more extensive page table manipulation MIPS 16e Code Compression 16 bit encodings of 32 bit instructions to improve code density Special PC relative instructions for efficient loading of addresses and constants SAVE amp RESTORE macro instructions for setting up m and tearing down stack frames within subroutines Improved support for handling 8 and 16 bit datatypes e Programmable Cache Sizes Individually configurable instruction and data caches Sizes from 0 64KB E Direct Mapped 2 3 or 4 Way Set Associative Loads block only until critical word is available Write back and write through support 16 byte cache line size l Virtually indexed physically tagged Cache line locking support Non bl
39. ched Addresses in a memory area indicated as uncached are not read from the cache Stores to such addresses are written directly to main memory without changing cache contents e Write through no write allocate Loads and instruction fetches first search the cache reading main memory only if the desired data does not reside in the MIPS32 4KEc Processor Core Datasheet Revision 02 01 15 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved cache On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache contents are updated and main memory is also written If the cache look up misses only main memory is written e Write through write allocate Similar to above but stores missing in the cache will cause a cache refill The store data is then written to both the cache and main memory e Write back write allocate Stores that miss in the cache will cause a cache refill Store data however is only written to the cache Caches lines that are written by stores will be marked as dirty If a dirty line is selected for replacement the cache line will be written back to main memory Scratchpad RAM The 4KEc core also supports replacing up to one way of each cache with a scratchpad RAM Scratchpad RAM is accessed via independent external pin interfaces for instruction and data scratchpads The external block which connects to a scrat
40. chpad interface is user defined and can consist of a variety of devices The main requirement is that it must be accessible with timing similar to an internal cache RAM Normally this means that an index will be driven one cycle a tag will be driven the following clock and the scratchpad must return a hit signal and the data in the second clock The scratchpad can easily contain a large RAM ROM or memory mapped registers Unlike the fixed single cycle cache timing however the scratchpad interface can also accommodate backstalling the core pipeline if data is not available in a single clock This backstalling capability can be useful for operations which require multi cycle latency It can also be used to enable arbitration of external accesses to a shared scratchpad memory The core s functional interface to a scratchpad RAM is slightly different than to a regular cache RAM Additional index bits allow access to a larger array 1 MB of scratchpad RAM versus 4KB for a cache way These bits come from the virtual address so on a 4KEc core care must be taken to avoid virtual aliasing The core does not automatically refill the scratchpad way and will not select it for replacement on cache misses Additionally stores that hit in the scratchpad will not generate writes to main memory MIPS16e Application Specific Extension The 4KEc core has optional support for the MIPS 16e ASE This ASE improves code density through the use of 16 bit encod
41. code T check bits are available on CP2_ccc_0 Coprocessor Conditions Code Check Valid when CP2_cccs_0 is asserted When asserted CP2_ccc_0 I the branch instruction checking the condition code should take the branch When deasserted the branch instruction should not branch Coprocessor Exceptions These signals are used by the COP2 coprocessor to report exception for each instruction CP2 excs 0 I Coprocessor Exception Strobe Asserted when coprocessor exception signalling is available 7 T on CP2_exc_0 and CP2_exccode_0 CP2 exc 0 I Coprocessor Exception When asserted a Coprocessor exception is signaled on SEE CP2_exccode_0 4 0 Valid when CP2_excs_0 is asserted 32 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 13 4KEc Signal Descriptions Continued Signal Name Type Description Coprocessor Exception Code Valid when both CP2_excs_0 and CP2_exc_0 are asserted CP2_exccode 4 0 Exception 01010 RD Reserved Instruction Exception IS1 Available for Coprocessor CP2_exccode_0 4 0 I specific Exception IS1 Available for Coprocessor specific Exception C2E Exception All others Reserved Instruction Nullification These signals are used by the 4KEc core to signal nullification of each instruction to the COP2 coprocessor CP2_nulls_0 CP2_null_0 O Coprocessor Null Strobe Asserted when a nullification sig
42. d Table 10 Build time Configuration Options Choices Software Visibility D cache size 0 64 KB Configlp Configl ps D cache associativity 1 2 3 or 4 Config pa Memory BIST Integrated March C or IFA 13 custom or none N A Scan options for improved coverage Present or not N A around cache arrays Top level integer register file array TLB array fine Clock gating grain or none These bits indicate the presence of an external block Bits will not be set if interface is present but block is not Instruction Set The 4KEc core instruction set complies with the MIPS32 instruction set architecture Table 11 provides a summary of instructions implemented by the 4KEc core Table 11 4KEc Core Instruction Set ADD Integer Add Rt ADDI Integer Add Immediate ADDIU Unsigned Integer Add Immediate Unsigned Integer Add Immediate to PC ADDIVEG MIPS16 only ADDU Unsigned Integer Add AND Logical AND ANDI Logical AND Immediate Rt Rs amp 046 Immed Unconditional Branch J Assembler idiom for BEQ 10 r0 offset PC int offset Branch and Link GPR 31 PC 8 Assembler idiom for BGEZAL 10 offset PC int offset if COP2Condition cc Branch On COP2 Condition False Be de ine LoREact if COP2Condition cc PC int offset else Ignore Next Instruction Branch On COP2 Condition False Likely if COP2Condition cc 1 BC2T Branch On
43. e To aid in attaching the 4KEc core to structures which cannot easily handle arbitrary byte enable patterns there is a mode that generates only simple byte enables Only byte enables representing naturally aligned byte half and word transactions will be generated Legal byte enable patterns are shown in Table 7 Table 7 Valid SimpleBE Byte Enable Patterns EB_BE 3 0 0001 0010 0100 1000 0011 1100 1111 The only case where a read can generate non simple byte enables is on an uncached tri byte load LWL LWR In SimpleBE mode such reads will be converted into a word read on the external interface Writes with non simple byte enable patterns can arise when a sequence of stores is processed by the merging write buffer or from uncached tri byte stores SWL SWR In SimpleBE mode these stores will be broken into two separate write transactions one with a valid halfword and a second with a single valid byte This splitting is independent of the merge pattern control in the write buffer Hardware Reset For historical reasons within the MIPS architecture the 4KEc core has two types of reset input signals S7_Reset and SI_ColdReset Functionally these two signals are ORed together within the core and then used to initialize critical hardware state 13 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Both reset signals can be asserted either synchro
44. e after the corresponding EB_WDRdy is asserted and keep EB_EWBE deasserted until the external write buffers are empty EB_WWBE O When asserted indicates that the core is waiting for external write buffers to empty CorExtend User Defined Instruction Interface On the 4KEc Pro core an interface to user defined instruction block is possible See MIPS32 Pro Series CorExtend Instruction Integrator s Guide for a description of this interface Coprocessor Interface Instruction dispatch These signals are used to transfer an instruction from the 4KEc core to the COP2 coprocessor Coprocessor Arithmetic and To From Instruction Word CP2_ir_0 31 0 O fon Valid in the cycle before CP2_as_0 CP2_ts_0 or CP2_fs_0 is asserted Enable Instruction Registering When deasserted no instruction strobes will be asserted in the following cycle When asserted there may be an instruction strobe asserted in the CP2_irenable_0 O following cycle Instruction strobes include CP2_as_0 CP2_ts_0 CP2_fs_0 Note This is the only late signal in the interface The intended function is to use this signal as a clock gate condition on the capture latches in the coprocessor for CP2_ir_O 31 0 Coprocessor2 Arithmetic Instruction Strobe Asserted in the cycle after an arithmetic coprocessor instruction is available on CP2_ir_0 31 0 If CP2_abusy_0O was asserted in the previous cycle this signal will not be asserted This signal will never
45. e asserts SI __EXL whenever any exception other than a Reset Soft Reset NMI or Debug exception is taken This signal represents the state of the RP bit 27 in the CPO Status register Software can SI_RP i a a a A write this bit to indicate that a reduced power mode may be entered SI Slee This signal is asserted by the core whenever the WAIT instruction is executed The assertion eek of this signal indicates that the clock has stopped and that the core is waiting for an interrupt Interrupt Signals Indicates whether an external interrupt controller is present Value is visible to software in the Config3 ypc register field SI_EISS 3 0 General purpose register shadow set number to be used when servicing an interrupt in EIC interrupt mode 26 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Signal Name Type Table 13 4KEc Signal Descriptions Continued Description SI_TAck SI_Int 5 0 SI_IPL 5 0 VA Interrupt acknowledge indication for use in external interrupt controller mode This signal is active for a single SZ_ClkIn cycle when an interrupt is taken When the processor initiates the interrupt exception it loads the value of the SI_Int 5 0 pins into the Cause pypy field overlaid with Cause p7_ p2 and signals the external interrupt controller to notify it that the current interrupt request is being serviced
46. e signals provide the interface to optional integrated memory BIST capability for testing the SRAM arrays within the core gmbinvoke I Enable signal for integrated BIST controllers gmbdone O Common completion indicator for all integrated BIST sequences gmbddfail O When high indicates that the integrated BIST test failed on the data cache data array gmbtdfail O When high indicates that the integrated BIST test failed on the data cache tag array gmbwdfail O When high indicates that the integrated BIST test failed on the data cache way select array gmbdifail O When high indicates that the integrated BIST test failed on the instruction cache data array gmbtifail O When high indicates that the integrated BIST test failed on the instruction cache tag array gmbwifail o When high indicates that the integrated BIST test failed on the instruction cache way select array 38 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 13 4KEc Signal Descriptions Continued EC Interface Transactions The 4KEc core implements the EC interface for its bus transactions This interface uses a pipelined in order protocol with independent address read data and write data buses The following subsections describe the four basic bus transactions single read single write burst read and burst write Single Read
47. eference Manual Store Word Right See Architecture Reference Manual SYNCI Synchronize Synchronize Caches to Make Instruction Writes Effective See Software User s Manual Force D cache writeback and I cache invalidate on specified address SYSCALL System Call Trap if Equal SystemCallException if Rs Rt TrapException Trap if Equal Immediate MIPS32 4KEc Processor Core Datasheet Revision 02 01 if Rs int Immed TrapException Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 11 4KEc Core Instruction Set Continued if int Rs gt int Rt TrapException TGE Trap if Greater Than or Equal int Rs gt int Immed Trap if Greater Than or Equal Immediate TrapException Trap if Greater Than or Equal Immediate if uns Rs gt uns Immed Unsigned TrapException uns Rs gt uns Rt TrapException Trap if Greater Than or Equal Unsigned Write Indexed TLB Entry Software Users Manual Write Random TLB Entry Software Users Manual Probe TLB for Matching Entry Software Users Manual Read Index for TLB Entry Software Users Manual int Rs lt int Rt TrapException Trap if Less Than int Rs lt int Immed Trap if Less Than Immediate TrapException Trap if Less Than Immediate Unsigned oO ATE uns mmeg TrapException uns Rs lt uns Rt TrapException TLTU Trap if Less Than Unsigned if Rs
48. ers match and is deasserted when the Compare register is written This hardware pin represents the value of the Cause register field For Release 1 Interrupt Compatibility mode or Vectored Interrupt mode In order to generate a timer interrupt the SJ_Timer nt signal needs to be brought back into the 4KEc core on one of the six S _ nt interrupt pins in a system dependent manner Traditionally this has been accomplished by muxing S _TimerInt with SI_Int 5 Exposing SI_TimerInt as an output allows more flexibility for the system designer Timer interrupts can be muxed or ORed into one of the interrupts as desired in a particular system The S7_Int hardware interrupt pin with which the S7_TimerInt signal is merged is indicated via the SI_IPTI static input pins For External Interrupt Controller EIC mode The S _TimerInt signal is provided to the external interrupt controller which then prioritizes the timer interrupt with all other interrupt sources as desired The controller then encodes the desired interrupt value on the SZ_Int pins Since S _Int is usually encoded the SI_IPTI pins are not meaningful in EIC mode SI_CPUNum 9 0 SI_Endian Unique identifier to specify an individual core in a multi processor system The hardware value specified on these pins is available in the CPUNum field of the EBase register so it can be used by software to distinguish a particular processor In a single processor system this value should be set
49. ert Bit Field J Unconditional Jump PC PC 31 28 offset lt lt 2 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 11 4KEc Core Instruction Set Continued GPR 3 PG 8 Tump and Link PC eee offset lt lt 2 P Jump and Link Register Like JALR but also clears JALR HB Jump and Link Register with Hazard Barrier execution and instruction hazards Jump and Link Register Compact do not execute instruction in jump delay slot MIPS16 only Jump Register Like JR but also clears Jump Register with Hazard Barrier execution and instruction hazards Jump Register Compact do not execute instruction in jump delay slot MIPS16 only Load Byte byte Mem Rs offset Unsigned Load Byte ubyte Mem Rs offset Load Halfword half Mem Rs offset Unsigned Load Halfword uhalf Mem Rs offset Load Linked Word Load Upper Immediate immediate lt lt 16 Load Word Mem Rs offset Load Word To Coprocessor 2 CPR 2 n 0 Mem Rs offset Load Word PC relative Rt Mem PC offset Load Word Left See Architecture Reference Manual Load Word Right See Architecture Reference Manual Multiply Add HI LO int Rs int Rt Multiply Add Unsigned HI LO uns Rs uns Rt Move From Coprocessor 0 CPR 0 Rd sel Move From Coprocessor 2 CPR 2 Rd sel MFHC2 Move From High Half of
50. fig3 registers The ITLB is managed by hardware and is transparent to software The larger JTLB is used as a backing store for the ITLB If a fetch address cannot be translated by the ITLB the JTLB is used to attempt to translate it in the following clock cycle If successful the translation information is copied into the ITLB for future use There is a two cycle ITLB miss penalty Data TLB DTLB The DTLB is a small 4 entry fully associative TLB dedicated to performing translations for loads and stores Similar to the ITLB the DTLB only maps either 1 Kbyte or 4 Kbyte pages subpages depending on the PageGrain and Config3 registers The DTLB is managed by hardware and is transparent to software The larger JTLB is used as a backing store for the DTLB The JTLB is looked up in parallel with the DTLB to minimize the DTLB miss penalty If the JTLB translation is successful the translation information is Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved copied into the DTLB for future use There is a one cycle DTLB miss penalty Virtual to Physical Address Translation Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the TLB there is a match when the virtual page number VPN of the address is the same as the VPN field of the entry and either e The Global G bit of the TLB entry is set or e The ASID field of the
51. g hardware instruction DIB break matched DBE Load or store bus error WATCH A reference to an address in one of the DDBL EJTAG data hardware breakpoint watch registers fetch matched in load data compare Fetch address alignment error AdEL Interrupt Handling Fetch reference to protected address TLBL Fetch TLB miss The 4KEc core includes support for six hardware interrupt pins two software interrupts and a timer interrupt These TLBL Fetch TLB hit to page with V 0 interrupts can be used in any of three interrupt modes as IBE Thsiichion fetch bucero defined by Release 2 of the MIPS32 Architecture p e Interrupt compatibility mode which acts identically to EJTAG Breakpoint execution of R DBp SDBBP instruction that in an implementation of Release 1 of the i Architecture Sys Execution of SYSCALL instruction e Vectored Interrupt VI mode which adds the ability to Bp Execution of BREAK instruction prioritize and vector interrupts to a handler dedicated to that interrupt and to assign a GPR shadow set for RI Execution of a Reserved Instruction use during interrupt processing The presence of this Execution of a coprocessor instruction mode is denoted by the VInt bit in the Config3 register CpU for a coprocessor that is not enabled This mode is architecturally optional but it is always present on the 4KEc core so the VInt bit will always CEU Execution of a CorExtend instruction read as a
52. ged software may need to reference all GPRs in the register file even specific shadow registers that are not visible in the current mode The RDPGPR and WRPGPR instructions are used for this purpose The CSS field of the SRSC l register provides the number of the current shadow register set and the PSS field of the SRSCtl register provides the number of the previous shadow register set that which was current before the last exception or interrupt occurred If the processor is operating in VI interrupt mode binding of a vectored interrupt to a shadow set is done by writing to the SRSMap register If the processor is operating in EIC interrupt mode the binding of the interrupt to a specific shadow set is provided by the external interrupt controller and is configured in an implementation dependent way Binding of an exception or non vectored interrupt to a shadow set is done by writing to the ESS field of the SRSC l register When an exception or interrupt occurs the value of SRSCtl egg is copied to SRSCtlpgg and SRSCtl agg is set to the value taken from the appropriate source On an ERET the value of SRSCtlpgg is copied back into SRSCtlcgg to restore the shadow set of the mode to which control returns Modes of Operation The 4KEc core supports three modes of operation user mode kernel mode and debug mode User mode is most often used for applications programs Kernel mode is typically used for handling exceptions and operating s
53. h cache has its own 32 bit data path and both caches can be accessed in the same pipeline clock cycle Refer to the section entitled 4KEc Core Optional Logic Blocks on page 15 for more information on instruction and data cache organization The cache controllers also have built in support for replacing one way of the cache with a scratchpad RAM See the section entitled Scratchpad RAM on page 16 for more information on scratchpad RAMs 12 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Bus Interface BIU The Bus Interface Unit BIU controls the external interface signals Additionally it contains the implementation of the 32 byte collapsing write buffer The purpose of this buffer is to store and combine write transactions before issuing them at the external interface When using the write through cache policy the write buffer significantly reduces the number of write transactions on the external interface and reduces the amount of stalling in the core due to issuance of multiple writes in a short period of time When using a write back cache policy the write buffer gathers the 4 words of dirty line writebacks The write buffer is organized as two 16 byte buffers Each buffer contains data from a single 16 byte aligned block of memory One buffer contains the data currently being transferred on the external interface while the other buffer c
54. h reads and writes of tag and data ISP_RdStr o Read Strobe indicates a read of the tag and data arrays Hit and Stall signals are also based off of this strobe ISP_TagWrStr o Tag Write Strobe If SPRAM tag is software configurable this signal will indicate when to update the tag value Write Compare Data For data writes this is the value to be written to the data array For tag writes the bus contains the 8 b0 PA 31 10 Lock Valid from the TagLo register ISP_DataTag Value 3 1 0 O F T EA or tag comparison the bus has the address to be used for hit miss determination in the format 8 b0 PA 31 10 Uncacheable 1 b0 When high the Uncacheable bit indicates that the physical address bits PA 31 10 are to an uncacheable address when the Uncacheable bit is low the physical address is to a cacheable address ISP_DataWrStr O Data Write Strobe Indicates that the data array should be written ISP_DataRdValue 31 0 I Data Read Value Data value read from the data array i Tag Read Value Tag value read from the tag array Written to TagLo register on a CACHE ISP_TagRdValue 23 0 l instruction Read value maps into these TagLo fields PA 31 10 Lock Valid ISP_Hit I Hit Indicates that this read was to an address covered by the SPRAM ISP_Stall I Stall Indicates that the read has not yet completed ISP_Present S Present Indicates that a SPRAM array is connected to this port Integrated Memory BIST Interface Thes
55. he 4KEc core asserts the EB_BFirst signal in the same clock as address 1 is driven to indicate the start of a burst cycle In the clock that the last address is driven the 4KEc core asserts EB_BLast to indicate the end of the burst transaction In Figure 11 the first data word Data1 is driven in clocks 2 and 3 due to the EB_WDRdy signal being sampled deasserted at the rising edge of clock 2 causing a wait state When EB_WDRdy is sampled asserted on the rising edge of clock 3 the 4KEc core responds by driving the second word Data2 41 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved External logic drives the EB_WBErr signal one clock after the corresponding assertion of EB_WDRdy if a bus error has occurred as shown by the arrows in Figure 11 42 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Revision History In the left hand page margins of this document you may find vertical change bars to note the location of significant changes to this document since its last release Significant changes are defined as those which you should take note of as you use the MIPS IP Changes to correct grammar spelling errors or similar may or may not be noted with change bars Change bars will be removed for changes which are more than one revision old Please note Limitations on the authoring tools make it difficult to place change bars
56. he Instruction fetch stage e An instruction is fetched from instruction cache e MIPS16e instructions are expanded into MIPS32 like instructions E Stage Execution During the Execution stage e Operands are fetched from register file e The arithmetic logic unit ALU begins the arithmetic or logical operation for register to register instructions The ALU calculates the data virtual address for load and store instructions e The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions e Instruction logic selects an instruction address e All multiply and divide operations begin in this stage M Stage Memory Fetch During the Memory fetch stage e The arithmetic ALU operation completes e The data cache access and the data virtual to physical address translation are performed for load and store instructions Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved e Data cache look up is performed and a hit miss determination is made e A 16x16 or 32x16 multiply calculation completes e A 32x32 multiply operation stalls the MDU pipeline for one clock in the M stage e A divide operation stalls the MDU pipeline for a maximum of 34 clocks in the M stage Early in sign extension detection on the dividend will skip 7 15 or 23 stall clocks A Stage Align During the Align stage e Load data is aligned to its word boundary
57. iguration register 3 17 LLAddr Load linked address 18 WatchLo Low order watchpoint address 19 High order watchpoint address 20 22 Reserved in the 4KEc core 23 Debug control and exception status 23 Trace PC Data trace control register Control BISSL Trace nt 23 2 Additional PC Data trace control Control2 Coprocessor 0 also contains the logic for identifying and managing exceptions Exceptions can be caused by a variety of sources including boundary cases in data external events or program errors Table 3 shows the exception types in order of priority Table 3 4KEc Core Exception Types Exception Description Assertion of SI_ColdReset or SI_Reset Reset i signals DSS EJTAG Debug Single Step EJTAG Debug Interrupt Caused by the DINT assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register NMI Assertion of SI_NMI signal Machine Check TLB write that conflicts with an existing entry Assertion of unmasked hardware or Interrupt software interrupt signal MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 3 4KEc Core Exception Types Continued Table 3 4KEc Core Exception Types Continued Deferred Watch Deferred Watch unmasked by KIDM TLBS Store TLB hit to page with V 0 gt KIDM transition TLB Mod Store to TLB page with D 0 EJTAG debu
58. ings of MIPS32 instructions plus some MIPS 16e specific instructions PC relative loads allow quick access to constants Save Restore macro instructions provide for single instruction stack frame setup teardown for efficient subroutine entry exit Sign and zero extend instructions improve handling of 8 bit and 16 bit datatypes Coprocessor 2 Interface The 4KEc core can be configured to have an interface for an on chip coprocessor This coprocessor can be tightly coupled to the processor core allowing high performance solutions integrating a graphics accelerator or DSP for example The coprocessor interface is extensible and standardized on MIPS cores allowing for design reuse The 4KEc core supports a subset of the full coprocessor interface standard 32b data transfer no Coprocessor support single issue in order data transfer to coprocessor one out of order data transfer from coprocessor The coprocessor interface is designed to ease integration with customer IP The interface allows high performance communication between the core and coprocessor There are no late or critical signals on the interface CorExtend User Defined Instruction Extensions An optional CorExtend User Defined Instruction UDI block enables the implementation of a small number of application specific instructions that are tightly coupled to the core s execution unit The interface to the UDI block is external to the 4KEc Pro core Such instruction
59. ion unit includes e 32 bit adder used for calculating the data address e Address unit for calculating the next instruction address e Logic for branch determination and branch target address calculation e Load aligner e Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results e Leading Zero One detect unit for implementing the CLZ and CLO instructions e Arithmetic Logic Unit ALU for performing bitwise logical operations e Shifter amp Store Aligner Multiply Divide Unit MDU The 4KEc core includes a multiply divide unit MDU that contains a separate pipeline for multiply and divide operations This pipeline operates in parallel with the integer unit IU pipeline and does not stall when the IU pipeline stalls This setup allows long running MDU operations such as a divide to be partially masked by system stalls and or other integer unit instructions The MDU consists of a 32x16 booth recoded multiplier result accumulation registers HI and LO a divide state machine and the necessary multiplexers and control logic The first number shown 32 of 32x16 represents the rs operand The second number 16 of 32x16 represents the rt operand The 4KEc core only checks the value of the latter rt operand to determine how many times the operation must pass through the multiplier The 16x16 and 32x16 operation
60. l information onto the EB_A 35 2 and EB_BE 3 0 signals on the rising edge of clock 2 As in the single read cycle these signals remain active until the clock edge after the EB_ARdy signal is sampled asserted The 4KEc core continues to drive EB_AValid as long as a valid address is on the bus The EB_Instr signal is asserted if the burst read is for an instruction fetch The EB_Burst signal is asserted while the address is on the bus to indicate that the current address is part of a burst transaction The 4KEc core asserts the EB_BFirst signal in the same clock as the first address is driven and the EB_BLast signal in the same clock as the last address to indicate the start and end of a burst cycle The 4KEc core first samples the EB_RData 31 0 signals two clocks after EB_ARDy is sampled asserted External logic asserts EB_RdVal to indicate that valid data is on the bus The 4KEc core latches data internally whenever EB_RdVal is sampled asserted Note that on the rising edge of clocks 3 and 6 in Figure 10 the EB_RdVal signal is sampled deasserted causing wait states in the data return There is also an address wait state caused by EB_ARdy being sampled deasserted on the rising edge of clock 4 Note that the core holds address 3 on the EB_A bus for an extra clock because of this wait state External logic asserts the EB_RBErr signal in the same clock as data if a bus error occurs during that data transfer Burst Write Burst write trans
61. lative to the cycle defined the description of TC_DataBits high strobe trigger output The target of this trigger is intended to be the external probe s trigger output TC_ChipTrigIn Rising edge trigger input The source should be on chip The input is considered asynchronous i e it is double registered in the core 36 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Signal Name Table 13 4KEc Signal Descriptions Continued Description TC_ChipTrigOut O Performance Monitoring Interface Single cycle relative to core clock high strobe trigger output The target of this trigger is intended to be an on chip unit These signals can be used to implement performance counters which can be used to monitor hardware software performance PM_DCacheHit O This signal is asserted whenever there is a data cache hit PM_DCacheMiss O This signal is asserted whenever there is a data cache miss PM_DTLBHit O This signal is asserted whenever there is a hit in the data TLB PM_DTLBMiss O This signal is asserted whenever there is a miss in the data TLB PM_ICacheHit O This signal is asserted whenever there is an instruction cache hit PM_ICacheMiss O This signal is asserted whenever there is an instruction cache miss PM_InstComplete O This signal is asserted each time an instruction completes in
62. mode are ignored Debug Mode Indication Asserted when the core is in Debug Mode This can be used to bring the core out of a low EJ_DebugM O power mode In systems with multiple processor cores this signal can be used to synchronize the cores when debugging Device ID bits These inputs provide an identifying number visible to the EJTAG probe If the EJTAG TAP controller is not implemented these inputs are not connected These inputs are always available for soft core customers On hard cores the core hardener can set these inputs to their own values EJ_ManufID 10 0 EJ_PartNumber 15 0 S Value of the ManufID 10 0 field in the Device ID register As per IEEE 1149 1 1990 section 11 2 the manufacturer identity code shall be a compressed form of JEDEC standard manufacturer s identification code in the JEDEC Publications 106 which can be found at http www jedec org ManufID 6 0 bits are derived from the last byte of the JEDEC code by discarding the parity bit ManufID 10 7 bits provide a binary count of the number of bytes in the JEDEC code that contain the continuation character 0x7F Where the number of continuations characters exceeds 15 these 4 bits contain the modulo 16 count of the number of continuation characters Value of the PartNumber 15 0 field in the Device ID register EJ_Version 3 0 S Value of the Version 3 0 field in the Device ID register System Implementation Dependent Outp
63. mplemented either through the use of integrated BIST features provided with the core or inserted with an industry standard memory BIST CAD tool Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Integrated Memory BIST The core provides an integrated memory BIST solution for testing the internal cache SRAMs using BIST controllers and logic tightly coupled to the cache subsystem Several parameters associated with the integrated BIST controllers are configurable including the algorithm March C or IFA 13 User specified Memory BIST Memory BIST can also be inserted with a CAD tool or other user specified method Wrapper modules and signal buses of configurable width are provided within the core to facilitate this approach Build Time Configuration Options The 4KEc core allows a number of features to be customized based on the intended application Table 10 summarizes the key configuration options that can be selected when the core is synthesized and implemented For a core that has already been built software can determine the value of many of these options by querying an appropriate register field Refer to the MIPS32 4KEc Processor Core Family Software User s Manual for a more complete description of these fields The value of some options that do not have a functional effect on the core are not visible to software Table 10 Build time Configuration Options Option Choices Software Visibility
64. ms System Control Coprocessor CP0 In the MIPS architecture CPO is responsible for the virtual to physical address translation and cache protocols the exception control system the processor s diagnostics capability the operating modes kernel user and debug and whether interrupts are enabled or disabled Configuration information such as cache size and set associativity is also available by accessing the CPO registers listed in Table 2 Table 2 Coprocessor 0 Registers in Numerical Order Register Register Number Name Function 0 Index Index into the TLB array 1 Random Randomly generated index into the TLB array Low order portion of the TLB 2 EntryLo0 entry for even numbered virtual pages Low order portion of the TLB 3 EntryLol entry for odd numbered virtual pages 4 Context Pointer to page table entry in memory Context Controls the layout of the Context Config register 3 Control for variable page sizes in 5 PageMask TLB entries 3 Controls the layout of the EntryLo gt PageGrain PageMask and EntryHi registers MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Table 2 Coprocessor 0 Registers in Numerical Order Table 2 Coprocessor 0 Registers in Numerical Order Register Register Number Name Function 33 Controls the number of fixed 6 wired TLB entries En
65. nal is available on CP2_null_0 Nullify Coprocessor Instruction When deasserted the 4KEc core is signalling that the instruction is not nullified When asserted the 4KEc core is signalling that the instruction is nullified and no further transactions will take place for this instruction Valid when CP2_nulls_0 is asserted Instruction Killing These signals are used by the 4KEc core to signal killing of each instruction to the COP2 coprocessor EJ_TRST_N MIPS32 4KEc Processor Core Datasheet Revision 02 01 CP2_kills_0 O Coprocessor Kill Strobe Asserted when kill signalling is available on CP2_kill_O 1 0 Kill Coprocessor Instruction Valid when CP2_kills_0 is asserted CP2_kill_O 1 0 Type of Kill Instruction is not killed and results can be committed CP2_kill_O 1 0 O 10 Instruction is killed 2 not due to CP2_exc_0 11 Instruction is killed 2 due to CP2_exc_0 If an instruction is killed no further transactions will take place on the interface for this instruction Miscellaneous COP2 signals CP2_reset O Coprocessor Reset Asserted when a hard or soft reset is performed by the integer unit COP2 Present Must be asserted when COP2 hardware is connected to the Coprocessor 2 CP2_present S Interface CP2 idle I Coprocessor Idle Asserted when the coprocessor logic is idle Enables the processor to go into sleep mode and shut down the clock Valid only if CP2_present is asserted
66. nously or asynchronously to the core clock SZ_CIkIn and will trigger a Reset exception The reset signals are active high and must be asserted for a minimum of 5 SZ_ClkIn cycles The falling edge triggers the Reset exception The primary difference between the two reset signals is that SZ _Reset sets a bit in the Status register this bit could be used by software to distinguish between the two reset signals if desired The reset behavior is summarized in Table 8 Table 8 4KEc Reset Types SI_Reset SI_ColdReset Action 0 0 Normal Operation no reset 1 0 Reset exception sets Status SR bit X 1 Reset exception One or both of the reset signals must be asserted at power on or whenever hardware initialization of the core is desired A power on reset typically occurs when the machine is first turned on A hard reset usually occurs when the machine is already on and the system is rebooted In debug mode EJTAG can request that a soft reset via the SI_Reset pin be masked It is system dependent whether this functionality is supported In normal mode the SI_Reset pin cannot be masked The S7_ColdReset pin is never masked Power Management The 4KEc core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports slowing or halting the clocks which reduces system power consumption during idle periods
67. ocking prefetches b e Scratchpad RAM Support MIPS32 Privileged Resource Architecture Can optionally replace 1 way of the I and or D cache with a fast scratchpad RAM Independent external pin interfaces for I and D scratchpads 20 index address bits allow access of arrays up to 1MB Interface allows back stalling the core Count Compare registers for real time timer interrupts I and D watch registers for SW breakpoints Programmable Memory Management Unit 16 or 32 dual entry JTLB with variable page size 4 entry ITLB 4 entry DTLB Simple Bus Interface Unit BIU All I O s fully registered Separate unidirectional 32 bit address and data buses Two 16 byte collapsing write buffers Designed to allow easy conversion to other bus protocols CorExtend User Defined Instruction Set Extensions available in 4KEc Pro core Allows user to define and add instructions to the core at build time Maintains full MIPS32 compatibility Supported by industry standard development tools Single or multi cycle instructions Separately licensed a core with this feature is known as the 4KEc Pro core Multiply Divide Unit Maximum issue rate of one 32x16 multiply per clock Maximum issue rate of one 32x32 multiply every other clock Early in iterative divide Minimum 11 and maximum 34 clock latency dividend rs sign extension dependent Coprocessor 2 interface 32 bi
68. of 0 63 e When the core starts the interrupt exception signaled by the assertion of SJ_IAck it loads the value of the SJ_Int 5 0 pins into the Causepypy field overlaid with Cause p7_ p2 The interrupt controller can then signal another interrupt Current interrupt priority level from the Cause p register field provided for use by an external interrupt controller This value is updated whenever SJ_IAck is asserted SI_IPTI 2 0 Timer interrupts can be muxed or ORed into one of the interrupts as desired in a particular system This input indicates which S _Int hardware interrupt pin the timer interrupt pin SI_TimerInt is combined with external to the core The value of this bus is visible to software in the IntCtl p7 register field SLIPTI Combined w SI_Int None SL Int 0 SL Int 1 SL Int 3 SL Int 4 SL int 5 2 3 4 SI_Int 2 5 6 7 SL_SWInt 1 0 O Software interrupt request These signals represent the value in the ZP 1 0 field of the Cause register They are provided for use by an external interrupt controller MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 27 Signal Name Type Table 13 4KEc Signal Descriptions Continued Description SL TimerInt Configuration Inputs Timer interrupt indication This signal is asserted whenever the Count and Compare regist
69. on changes to figures Change bars on figure titles are used to denote a potential change in the figure itself Certain parts of this document Instruction set descriptions EJTAG register definitions are references to Architecture specifications and the change bars within these sections indicate alterations since the previous version of the relevant Architecture document Revision Date Description 02 00 e Added this revision history table November 8 2002 e Various updates to describe new MIPS32 Release 2 capabilities included in version 3 0 or higher core releases e Added SYNCI instn to table Added assembler idioms such as b bal e Corrected description of EntryLo0 register in Table 2 Externalized CorExtend interface 02 01 September 1 2004 e Added CEU CorExtend Unusable exception type e Exception table referred to EB_NMI instead of SI_NMI e Added option for 32 entry JTLB e Added table summarizing key build time configuration options MIPS32 4KEc Processor Core Datasheet Revision 02 01 43 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Unpublished rights if any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing
70. only See Architecture Reference Manual SB Store Byte byte Mem Rs offset Rt if LL 1 SC Store Conditional Word mem Rs offset Rt Rt LL SDBBP Software Debug Break Point Trap to SW Debug Handler SEB Sign Extend Byte Rd byte Rs MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 24 Instruction Table 11 4KEc Core Instruction Set Continued Description Sign Extend Half Rd half Rs Store Half half Mem Rst offset Shift Left Logical Rd Rt lt lt sa Shift Left Logical Variable Set on Less Than Set on Less Than Immediate Set on Less Than Immediate Unsigned Set on Less Than Unsigned Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Rd Rt lt lt if int Rs lt int Rt Rd 1 else if int Rs lt int Immed Rt 1 else if uns Rs lt uns Immed Rt 1 else if uns Rs lt uns Immed Rd 1 else Rd 0 Rd int Rt gt gt sa Rd int Rt gt gt Rs 4 0 Rd uns Rt gt gt sa Shift Right Logical Variable Rd uns Rt gt gt Rs 4 0 Superscalar Inhibit No Operation NOP Unsigned Subtract SW Integer Subtract Store Word Store Word From Coprocessor 2 Rt int Rs int Rd Rt uns Rs uns Rd Mem Rst offset Rt Mem Rstoffset CPR 2 n 0 Store Word Left See Architecture R
71. ontains accumulating data from the core Data from the accumulation buffer is transferred to the external interface buffer under one of these conditions e When a store is attempted from the core to a different 16 byte block than is currently being accumulated e SYNC Instruction e Store to an invalid merge pattern e Any load or store to uncached memory e A load to the line being merged e A complete 16B block has been gathered Note that if the data in the external interface buffer has not been written out to memory the core is stalled until the memory write completes After completion of the memory write accumulated buffer data can be written to the external interface buffer Merge Control The 4KEc core implements two 16 byte collapsing write buffers that allow byte halfword or word writes from the core to be accumulated in the buffer into a 16 byte value before bursting the data onto the bus in word format Note that writes to uncached areas are never merged The 4KEc core provides two options for merge pattern control e No merge e Full merge MIPS32 4KEc Processor Core Datasheet Revision 02 01 In No Merge mode writes to a different word within the same line are accumulated in the buffer Writes to the same word cause the previous word to be driven onto the bus In Full Merge mode all combinations of writes to the same line are collected in the buffer Any pattern of byte enables is possible SimpleBE Mod
72. ose of the TLB MIPS32 4KEc Processor Core Datasheet Revision 02 01 is to translate virtual addresses and their corresponding ASIDs into a physical memory address The translation is performed by comparing the upper bits of the virtual address along with the ASID against each of the entries in the tag portion of the joint TLB structure The JTLB is organized as pairs of even and odd entries containing pages that range in size from 4 Kbytes or 1 Kbyte to 256 Mbytes into the 4 Gbyte physical address space By default the minimum page size is normally 4 Kbytes on the 4KEc core as a build time option it is possible to specify a minimum page size of 1 Kbyte The JTLB is organized in page pairs to minimize the overall size Each tag entry corresponds to 2 data entries an even page entry and an odd page entry The highest order virtual address bit not participating in the tag comparison is used to determine which of the data entries is used Since page size can vary on a page pair basis the determination of which address bits participate in the comparison and which bit is used to make the even odd determination is decided dynamically during the TLB look up Instruction TLB ITLB The ITLB is a small 4 entry fully associative TLB dedicated to performing translations for the instruction stream The ITLB only maps minimum sized pages subpages The minimum page size is either 1 Kbyte or 4 Kbyte depending on the PageGrain and Con
73. pace identifier ASID which reduces the frequency of TLB flushing during a context switch This 8 bit ASID contains the number assigned to that process and is stored in the CPO EntryHi register Hits Misses and Multiple Matches Each JTLB entry contains a tag portion and a data portion If a match is found the upper bits of the virtual address are replaced with the page frame number PFN stored in the corresponding entry in the data array of the joint TLB JTLB The granularity of JTLB mappings is defined in terms of TLB pages The 4KEc core s JTLB supports pages of different sizes ranging from 1 KB to 256 MB in powers of 4 If no match occurs TLB miss an exception is taken and software refills the TLB from the page table resident in memory Software can write over a selected TLB entry or use a hardware mechanism to write into a random entry MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved The 4KEc core implements a TLB write compare mechanism to ensure that multiple TLB matches do not occur On the TLB write operation the write value is compared with all other entries in the TLB If a match occurs the 4KEc core takes a machine check exception sets the TS bit in the CPO Status register and aborts the write operation Table 4 shows the address bits used for even odd bank selection depending on page size and the relationship between the leg
74. pled asserted If a bus error occurs during the data transaction external logic asserts EB_RBErr in the same clock as EB_RdVal Single Write Figure 9 shows a typical write transaction The 4KEc core drives address and control information onto the EB_A 35 2 and EB_BE 3 0 signals on the rising edge of clock 2 As in the single read cycle these signals remain active until the clock edge after the EB_ARdy signal is sampled asserted The 4KEc core asserts the EB_Write signal to indicate that a valid write cycle is on the bus and EB_AValid to indicate that valid address is on the bus The 4KEc core drives write data onto EB_WData 31 0 in the same clock as the address and continues to drive data until the clock edge after the EB_WDRdy signal is sampled asserted If a bus error occurs during a write operation external logic asserts the EB_WBErr signal one clock after asserting EB_WDRdy Clock 1 o Address and Cantrol held Until clock B EB_ARdy sampled asserted EB_Write EB BEI 77X36 NUNN EB_AValid Data is Driven until lock after EB_WDRay Valid S lie TTA TTETTTATTT HE Figure 9 Single Write Transaction Timing Diagram EB_WData 31 0 EB_WDRady EB_WBErr Burst Read The 4KEc core is capable of generating burst transactions on the bus A burst transaction is used to transfer multiple data items in one transaction 40 Clock EB_Cik EB_ARdy EB_Burst
75. pt latency by TLBS Store TLB miss avoiding the need to save context when invoking an interrupt handler TLBL Load TLB hit to page with V 0 MIPS32 4KEc Processor Core Datasheet Revision 02 01 7 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved GPR Shadow Registers Release 2 of the MIPS32 Architecture optionally removes the need to save and restore GPRs on entry to high priority interrupts or exceptions and to provide specified processor modes with the same capability This is done by introducing multiple copies of the GPRs called shadow sets and allowing privileged software to associate a shadow set with entry to kernel mode via an interrupt vector or exception The normal GPRs are logically considered shadow set zero The number of GPR shadow sets is a build time option on the 4KEc core Although Release 2 of the Architecture defines a maximum of 16 shadow sets the core allows one the normal GPRs two or four shadow sets The highest number actually implemented is indicated by the SRSCtlyg field If this field is zero only the normal GPRs are implemented Shadow sets are new copies of the GPRs that can be substituted for the normal GPRs on entry to kernel mode via an interrupt or exception Once a shadow set is bound to a kernel mode entry condition reference to GPRs work exactly as one would expect but they are redirected to registers that are dedicated to that condition Privile
76. rocessor 0 CPO register set The DEBUG register shows the cause of the debug exception and is used for setting up single step operations The DEPC or Debug Exception Program Counter register holds the address on which the debug exception was taken This is used to resume program execution after the debug operation finishes Finally the DESAVE or Debug Exception Save register enables the saving of general purpose registers used during execution of the debug exception handler To exit debug mode a Debug Exception Return DERET instruction is executed When this instruction is executed the system exits debug mode allowing normal execution of application and system code to resume EJTAG Hardware Breakpoints There are several types of simple hardware breakpoints defined in the EJTAG specification These stop the normal operation of the CPU and force the system into debug mode There are two types of simple hardware breakpoints implemented in the 4KEc core Instruction breakpoints and Data breakpoints The 4KEc core can be configured with the following breakpoint options e No data or instruction breakpoints e One data and two instruction breakpoints MIPS32 4KEc Processor Core Datasheet Revision 02 01 e Two data and four instruction breakpoints Instruction breaks occur on instruction fetch operations and the break is set on the virtual address Instruction breaks can also be made on the ASID value used by the MMU A
77. s may operate on a general purpose register immediate data specified by the instruction word or local state stored within the UDI block The destination may be a general purpose register or local UDI state The operation may complete in one cycle or multiple cycles if desired EJTAG Debug Support The 4KEc core provides for an optional Enhanced JTAG EJTAG interface for use in the software debug of MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved application and kernel code In addition to standard user mode and kernel modes of operation the 4KEc core provides a Debug mode that is entered after a debug exception derived from a hardware breakpoint single step exception etc is taken and continues until a debug exception return DERET instruction is executed During this time the processor executes the debug exception handler routine Refer to the section called External Interface Signals on page 25 for a list of EJTAG interface signals The EJTAG interface operates through the Test Access Port TAP a serial communication port used for transferring test data in and out of the 4KEc core In addition to the standard JTAG instructions special instructions defined in the EJTAG specification define what registers are selected and how they are used Debug Registers Three debug registers DEBUG DEPC and DESAVE have been added to the MIPS Cop
78. s pass through the multiplier once A 32x32 operation passes through the multiplier twice The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issuance of back to back 32x32 multiply operations The multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple 1 bit per clock iterative algorithm An early in detection checks the sign extension of the dividend rs operand If rs is 8 bits wide 23 iterations are skipped For a 16 bit wide rs 15 iterations are skipped and for a 24 bit wide rs 7 iterations are skipped Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed Table 1 lists the repeat rate peak issue rate of cycles until the operation can be reissued and latency number of cycles until a result is available for the 4KEc core multiply and divide instructions The approximate latency and repeat rates are listed in terms of pipeline clocks For a more detailed discussion of latencies and repeat rates refer to Chapter 2 of the MIPS32 4KE Processor Core Family Software User s Manual
79. signal controls the read and write strobes to the cache SRAM when gscanmode is gscanramwr I asserted gscanin_X I These signal s are the inputs to the scan chain s gscanout_X O These signal s are the outputs from the scan chain s BistIn n 0 I Input to user specified BIST controller BistOut n 0 O Output from user specified BIST controller On the rising edge of clock 3 the 4KEc core samples EB_ARdy asserted and continues to drive the address until the rising edge of clock 4 Clock 1 2 3 4 5 6 7 8 eck Lay Address and Control held until clock J EB_ARady sampled asserted EB_ARdy it EB_A 35 2 Valid EB _Instr EB_BE 3 0 valid EB AValid Driven by system logi EB_RData 31 0 Valid EB_RdVal EB _RBErr EB _Write Figure 8 Single Read Transaction Timing Diagram The EB_Instr signal is only asserted during a single read cycle if there is an instruction fetch from non cacheable memory space The EB_AValid signal is driven in each clock that EB_A 35 2 is valid on the bus The 4KEc core drives EB_Write low to indicate a read transaction The EB_RData 31 0 and EB_RdVal signals are first sampled on the rising edge of clock 4 one clock after MIPS32 4KEc Processor Core Datasheet Revision 02 01 39 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved EB_ARzdy is sampled asserted Data is sampled on every clock thereafter until EB_RdVal is sam
80. t accesses to the page are permitted If the bit is cleared accesses to the page cause a TLB Invalid exception Page Sizes and Replacement Algorithm To assist in controlling both the amount of mapped space and the replacement characteristics of various memory regions the 4KEc core provides two mechanisms First the page size can be configured on a per entry basis to map a page size of 1Kbyte to 256Mbytes in multiples of 4 The CPO PageMask register is loaded with the mapping page size which is then entered into the TLB when a new entry is written Thus operating systems can provide special purpose maps For example a typical frame buffer can be memory mapped with only one TLB entry The second mechanism controls the replacement algorithm when a TLB miss occurs To select a TLB entry to be written with a new mapping the 4KEc core provides a random replacement algorithm However the processor also provides a mechanism where a programmable number of mappings can be locked into the TLB via the CPO Wired register thus avoiding random replacement Cache Controllers The 4KEc core instruction and data cache controllers support caches of various sizes organizations and set associativity For example the data cache can be 2 Kbytes in size and 2 way set associative while the instruction cache can be 8 Kbytes in size and 4 way set associative Each cache can each be accessed in a single processor cycle In addition eac
81. t interface to an external coprocessor Power Control Minimum frequency 0 MHz Power down mode triggered by WAIT instruction Support for software controlled clock divider Support for extensive use of local gated clocks EJTAG Debug and MIPS Trace Support for single stepping Virtual instruction and data address value breakpoints PC and data tracing w trace compression TAP controller is chainable for multi CPU debug Cross CPU breakpoint support Testability Full scan design achieves test coverage in excess of 99 dependent on library and configuration options Optional memory BIST for internal SRAM arrays Architecture Overview The 4KEc core contains both required and optional blocks Required blocks are the lightly shaded areas of the block diagram in Figure 1 and must be implemented to remain MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved MIPS compliant Optional blocks can be added to the 4KEc core based on the needs of the implementation The required blocks are as follows e Execution Unit e Multiply Divide Unit MDU e System Control Coprocessor CPO e Memory Management Unit MMU Transition Lookaside Buffer TLB e Cache Controllers e Bus Interface Unit BIU e Power Management Optional blocks include e Instruction Cache e Data Cache e Scratchpad RAM interface e
82. the PFN is shifted to the right before being appended to the untranslated part of the virtual address In this mode the upper two physical address bits are not covered by PFN but forced to zero PFN 31 12 or 29 10 For page sizes larger than the minimum configured page size only a subset of these bits is actually used Cacheability Contains an encoded value of the cacheability attributes and determines whether the page should be placed in the cache or not The field is encoded as follows CS 2 0 Coherency Attribute Cacheable noncoherent write through no write allocate 000 Cacheable noncoherent write through write allocate 001 C 2 0 010 Uncached Cacheable noncoherent write back write allocate 100 Maps to entry 011b 101 Maps to entry 011 b 110 Maps to entry 011b 111 Maps to entry 010b 011 Values 2 and 3 are the required MIPS32 mappings for uncached and cacheable references other values may have different meanings in other MIPS32 processors Dirty or write enable bit Indicates that the page has been written and or is D writable If this bit is set stores to the page are permitted If the bit is cleared stores to the page cause a TLB Modified exception Table 6 TLB Data Array Entry Fields Continued Field Name Description Valid bit Indicates that the TLB entry and thus the virtual page mapping are valid If V this bit is se
83. the pipeline PM_ITLBHit O This signal is asserted whenever there is an instruction TLB hit PM_ITLBMiss O This signal is asserted whenever there is an instruction TLB miss PM_JTLBHit O This signal is asserted whenever there is a joint TLB hit PM_JTLBMiss O This signal is asserted whenever there is a joint TLB miss PM_WTBMerge O This signal is asserted whenever there is a successful merge in the write through buffer PM_WTBNoMerge O This signal is asserted whenever a non merging store is written to the write through buffer ScratchPad RAM interface This interface allows a ScratchPad RAM SPRAM array to be connected in parallel with the cache arrays enabling fast access to data There are independent interfaces for Instruction and Data ScratchPads Signals related to the Instruction Scratchpad interface are prefixed with ISP_ Signals related to the Data Scratchpad interface are prefixed with DSP_ Note In order to achieve single cycle access the ScratchPad interface is not registered unlike the other core interfaces This requires more careful timing considerations DSP_TagAddr 19 4 O Virtual index into the SPRAM used for tag reads and writes DSP_TagRdStr O Tag Read Strobe Hit Stall TagRdValue use this strobe DSP_TagWrStr o Tag Write Strobe If SPRAM tag is software configurable this signal will indicate when to update the tag value Tag Compare Value This bus is used for both tag comparison
84. the state of the DM bit 30 in the CPO Debug register Instruction Controlled Power Management The second mechanism for invoking power down mode is through execution of the WAIT instruction When the WAIT instruction is executed the internal clock is suspended however the internal timer and some of the input pins SZ_Int 5 0 SINMI SI_Reset and SI_ColdReset continue to run Once the CPU is in instruction controlled power management mode any interrupt NMI or reset condition causes the CPU to exit this mode and resume normal operation The 4KEc core asserts the S7_Sleep signal which is part of the system interface bus whenever the WAIT instruction is executed The assertion of S _Sleep indicates that the clock has stopped and the 4KEc core is waiting for an interrupt Local clock gating The majority of the power consumed by the 4KEc core is in the clock tree and clocking registers The core has support for extensive use of local gated clocks Power conscious implementors can use these gated clocks to significantly reduce power consumption within the core MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved 4KEc Core Optional Logic Blocks The 4KEc core contains several optional logic blocks shown in the block diagram in Figure 1 Instruction Cache The instruction cache is an optional on chip memory block of up to 64 Kbytes Because the ins
85. truction cache is virtually indexed the virtual to physical address translation occurs in parallel with the cache access rather than having to wait for the physical address translation The tag holds 22 bits of physical address a valid bit and a lock bit The LRU replacement bits 0 6b per set depending on associativity are stored in a separate array The instruction cache block also contains and manages the instruction line fill buffer Besides accumulating data to be written to the cache instruction fetches that reference data in the line fill buffer are serviced either by a bypass of that data or data coming from the external interface The instruction cache control logic controls the bypass function The 4KEc core supports instruction cache locking Cache locking allows critical code or data segments to be locked into the cache on a per line basis enabling the system programmer to maximize the efficiency of the system cache The cache locking function is always available on all instruction cache entries Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction Data Cache The data cache is an optional on chip memory block of up to 64 Kbytes This virtually indexed physically tagged cache is protected Because the data cache is virtually indexed the virtual to physical address translation occurs in parallel with the cache access The tag holds 22 bits of physical address a valid
86. truction can be issued every 2 cycles Instruction and data caches are fully configurable from 0 64 Kbytes in size In addition each cache can be organized as direct mapped or 2 way 3 way or 4 way set associative Load and fetch cache misses only block until the critical word becomes available The pipeline resumes execution while the remaining words are being written to the cache Both caches are virtually indexed and physically tagged to allow them to be accessed in the same clock that the address is translated An optional Enhanced JTAG EJTAG block allows for single stepping of the processor as well as instruction and data virtual address value breakpoints Additionally real time tracing of instruction program counter data address and data values can be supported Figure shows a block diagram of the 4KEc core The core is divided into required and optional blocks as shown Off On Chip Trace I F i z Trace ae cache ff Chip TAP Debug I F User defined T Cop 2 block Ge Execution 2 Core MMU Cache D User defined on RF ALU Shift Controller a CorExtend 5 block 5 System 2 Coprocessor Ee Deade Mgmt Fixed Required Optional Figure 1 4KEc Core Block Diagram MIPS32 4KEc Processor Core Datasheet Revision 02 01 Document Number MD00111 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Features is e 5 stage pipeline 32
87. uts These signals come from EJTAG control registers They have no effect on the core but can be used to give EJTAG debugging software additional control over the system Soft Reset Enable EJTAG can deassert this signal if it wants to mask soft resets If this BJ_SRstE 9 signal is deasserted none some or all soft reset sources are masked Peripheral Reset EJTAG can assert this signal to request the reset of some or all of the EJ_PerRst O peripheral devices in the system 34 MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved Signal Name Table 13 4KEc Signal Descriptions Continued Description EJ_PrRst TCtrace Interface Processor Reset EJTAG can assert this signal to request that the core be reset This can be fed into the S _Reset signal These signals enable an interface to optional off chip trace memory The TCtrace interface connects to the Probe Interface Block PIB which in turn connects to the physical off chip trace pins Note that if on chip trace memory is used access occurs via the EJTAG TAP interface and this interface is not required TC_ClockRatio 2 0 Clock ratio This is the clock ratio set by software in TCBCONTROLB CR The value will be within the boundaries defined by TC_CRMax and TC_CRMin The table below shows the encoded values for clock ratio TC_ClockRatio Clock Ratio
88. virtual address is the same as the ASID field of the TLB entry This match is referred to as a TLB hit If there is no match a TLB miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual physical addresses in memory Figure 5 shows a flow diagram of the address translation process for two different page sizes Virtual Address with 1M 22 4 Kbyte pages 39 32 31 20 bits 1M pages 12 11 0 12 AN J Virtual to physical translation in TLB Bit 31 of the virtual address selects user and 32 bit Physical Address Y Offset passed unchanged to physical memory kernel address spaces ot PFN 0 Offset Virtual to physical translation in TLB f 39 32 31 Offset passed unchanged to physical memory 8 bits 256 pages Offset 24 Virtual Address with 256 28 16 Mbyte pages Figure 5 32 bit Virtual Address Translation The top portion of Figure 5 shows a virtual address for a 4 Kbyte page size The width of the Offset in Figure 5 is defined by the page size The remaining 20 bits of the address represent the virtual page number VPN and index the 1M entry page table The bottom portion of Figure 5 shows the virtual address for a 16 Mbyte page size The remaining 8 bits of the address represent the VPN and index the 256 entry page table In this figure the virtual address is extended with an 8 bit address s
89. ystem kernel functions including CPO management and I O device accesses An additional Debug mode is used during system bring up and software development Refer to the EJTAG section for more information on debug mode OxFFFFFFFF Memory Mapped OxFF400000 OxFF3FFFFF OxFF200000 Memory EJTAG kseg3 OxF1FFFFFF Memory Mapped 0xE0000000 DFFFFFFF ox Kernel virtual address space kseg2 Mapped 512 MB 0xC0000000 OxBFFFFFFF Kernel virtual address space Unmapped 512 MB kseg1 0xA0000000 Uncached Ox9FFFFFFF Kernel virtual address space Unmapped 512 MB kseg0 0x80000000 Ox7FFFFFFF User virtual address space kuseg Mapped 2048 MB 0x00000000 1 This space is mapped to memory in user or kernel mode and by the EJTAG module in debug mode Figure 3 4KEc Core Virtual Address Map Memory Management Unit MMU The 4KEc core contains a fully functional MMU that interfaces between the execution unit and the cache controller Although the 4KEc core implements a 32 bit architecture the MMU is modeled after that found in the 64 bit R4000 family as defined by the MIPS32 Privileged Resource Architecture PRA MIPS32 4KEc Processor Core Datasheet Revision 02 01 Copyright 2001 2002 2004 MIPS Technologies Inc All rights reserved The 4KEc core implements a TLB based MMU The TLB consists of three translation buffers a 16 or 32 dual entry fully associative Joint TLB JTLB a 4 entry fully associative Instruction TL

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MIPS32® 4KEc™ Processor Core Datasheet October 29