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ERTEC 400 Enhanced Real-Time Ethernet Controller with 32

1. 199 JTAG Connector Pin Assignment sss eee 208 Preliminary Users Manual A17812EE1V1UM00 14 Preliminary Users Manual A17812EE1V1UM00 Table 1 1 Table 1 2 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Table 2 13 Table 2 14 Table 2 15 Table 3 1 Table 4 1 Table 5 1 Table 5 2 Table 5 3 Table 6 1 Table 6 2 Table 7 1 Table 7 2 Table 7 3 Table 8 1 Table 8 2 Table 8 3 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 9 8 Table 10 1 Table 11 1 Table 11 2 Table 11 3 Table 12 1 Table 12 2 Table 12 3 Table 12 4 Table 12 5 Table 13 1 Table 13 2 Table 13 3 Table 14 1 Table 14 2 Table 15 1 Table 15 2 Table 15 3 List of Tables Pin Configuration of ERTEC 400 22 Pin GOntiiGation cc 27 External Memory Interface Pin 33 PCI Interface Pin 34 Local Bus Interface Pin 2 4024 00 35 RMII Interface Pin E 36 Interface Pin Functions eeeeeeeesceeeeseeeeseseee eese nennen nennen 37 General Purpose I O Pin
2. 70 Write to External Device Using RDY PER Active Data 71 32 bit Write to External 8 bit Device Active Data 71 External Memory Connection Example 72 IRVEC IRQ Interrupt Vector Register 2 4 0 79 FIVEC FIQ Interrupt Vector Register sssssssseeeneneeeenennne enne 80 LOCKREG IRQ Interrupt Priority Lock Register 2 440 81 FIQ1SREG Interrupt Select Register 82 FIQ2SREG Interrupt Select Register 83 IRQACK IRQ Interrupt Acknowledge Register 84 FIQACK FIQ Interrupt Acknowledge Register 85 IRCLVEC IRQ Interrupt Request Clear Register 86 MASKALL Mask All IRQ Interrupt Request Register 86 IRQEND End of IRQ Interrupt Signaling Register sssseeeess 87 FIQEND End of FIQ Interrupt Signaling Register 87 FIQPRO 7 Interrupt Priority Register 88 FIQISR FIQ Interrupt In Service Register 2 88 FIQIRR FIQ Interrupt Request Register 89 FIQ MASKREG FIQ Interrupt Mask Register sse 89 IRREG IRQ Interrupt Request Register sse 90 MASKREG IRQ Interrupt Mask Register 90
3. 143 GPIO Register Initialization Example for External Serial Flash 150 RMII Interface Pin Functions een ennemis 152 Interface Pin 154 Address Assignment of Timer 0 and Timer 1 157 F Timer Pin FUNCTIONS wats esis ior eine eh i ed e dera ee tile ess 165 Address Assignment of F Timer 166 Preliminary User s Manual A17812EE1V1UMOO 15 Table 16 1 Table 17 1 Table 18 1 Table 19 1 Table 19 2 Table 21 1 Table 21 2 Table 21 3 16 Address Assignment of Watchdog Registers 169 Address Assignment of System Control nn 175 Overview of ERTEC 400 195 BOOT 2 0 Pin Functions ti inei ec ree Deed rette Lee d Eod 201 CONFIG 4 0 Pin Functions nennen nennen nennen nnns 201 Memory Map Decode Regions in ETM9 on ERTEC 400 205 Trace Port Pin 206 JTAG and Debug Interface Pin 207 Preliminary Users Manual A17812EE1V1UMO0 Chapter 1 Introduction 1 1 General ERTEC 400 is a powerful communication block for d
4. 199 19 1 Hardware 1 199 19 2 Watchdog 22 2 2 2 ee ee eee 200 19 3 Software iriiritia ea Ieee ee Rex RR he 200 19 4 PCI Bridge Reset noL ae ee eee AE ete xe 200 19 5 Actions when HW Reset is Active 201 Chapter 20 Address Space and Timeout 0 203 20 1 AHB Bus Monitoring 203 20 2 APB Bus 203 20 3 External Memory Interface Monitoring 204 20 4 PCI Slave 0 204 Chapter 21 Test and 205 211 ETM9 Embedded Trace 205 21 2 ETM9 Registers 292 eee NANE eres 206 21 3 5 E ERI eet 206 21 4 JTAG Interface on sc senses l4 ERR IET eru eate 207 21 5 Debugging 1 208 Preliminary User s Manual A17812EE1V1UMOO 9 10 Preliminary Users Manual A17812EE1V1UM00 Figure 1 1 Figure 1 2 Figure 3 1 Figure
5. 97 Address Assignment of PCI 100 Local Bus Interface Pin ene nene 103 Page Size Settings 2 enm cat ede ene eee ape xad 105 Page Offset Setting 106 Local Bus Unit Address Mapping Example see 107 LBU Register Initialization 108 32 bit Accesses in Various Address Ranges sse 109 Possible Host Accesses to ERTEC 400 110 Address Assignment of LBU Registers 113 Supported Download Modes ccccceeeececeeeeeeeeeeeeeeeeesaeeeseaeeeseaeeeeeaaeeseeeeseeeeseneeeneas 117 GPIO Pin and Related Drive 119 Address Assignment of GPIO Registers 2 120 Alternative Functions of GPIO 125 UART1 UART2 Pin 127 Baud Rates and Tolerances for 50 MHz UART Operation Clock 129 Address Assignment of UART1 2 130 GPIO Register Initialization Example for Two wire 140 GPIO Register Initialization Example for Five wire 140 SPINPINVEUNCUONS ote emet enue 141 Address Assignment of SPI
6. 135 UARTFR1 2 Registers 1 2 000 137 UARTIIR UARTICR1 2 Registers 139 Block Diagram of SPI Interface 2 4 0 1 1 142 SSPCRO SPI Control Register 0 1 2 144 SSPCR1 SPI Control Register 1 12 146 SSPDR SPI Rx Tx FIFO Data Register 2 147 SSPSR SPI Status Register 23 148 SSPCPSR SPI Clock Prescale Register 149 SSPIIR SSPICR SPI Interrupt Identification and Clear Register 149 Connection of Serial Flash Memory to ERTEC 400 SPI Interface 150 PHY Connection via Example esses enne 153 Simplified Block Diagram of Timers 0 and 1 155 Control Status Register 0 STATO 1 2 157 Control Status Register 1 CTRL_STAT1 12 159 Reload Register for Timer 0 RELDO 161 Reload Register for Timer 1 RELD1 161 Control Register for Prescaler 0 and 1 CTRL_PREDIV 1 2 162 Reload Register for Prescaler 0 and 1 RELD PREDIV 163 Current Timer Value Register for Timer 0 1 164 Current Timer Value Register for Timer 1 164 F Timer Block Diagram ee eel eel ee ele eee eae 165
7. PHY CLK REF CLK 50 MHz 25 MHz 198 Preliminary User s Manual 17812 1 10 00 Chapter 19 Reset Logic of ERTEC 400 The reset logic resets the entire circuit of ERTEC 400 except the PCI portion of the AHB PCI bridge A reset of ERTEC 400 is activated by the following events Hardware reset via external RESET N Software reset via XRES SOFT bit in the reset control register Watchdog reset via watchdog timer overflow The triggering reset event can be read out in the reset status register RES STAT REG 19 1 Hardware Reset The external hardware reset circuitry is connected to the RESET N pin of ERTEC 400 If the hardware reset is activated the entire ERTEC 400 circuit except the PCI portion is reset internally The hardware reset must be present steadily for at least 35 us see Figure 19 1 Afterwards the PLL powers up within a lock time of toc 400 ps The lock status of the PLL is monitored The state of the PLL can be read out from the STAT REG status register A filter is integrated at the RESET N input which suppresses spikes up to 10 ns In case of a hardware reset bit 2 is set in the reset status register RES STAT REG This bit remains unaffected by the triggering reset function and can be evaluated after a restart Figure 19 1 shows the power up phase of the PLL after a reset Figure 19 1 PLL Power up Phase fpi our MHz t Loc 400 us Power up of PLL Prelimina
8. 156 15 1 5 Address Assignment of Timer 0 1 Registers 157 15 1 6 Detailed Description of Timer 0 1 157 19 2 ie cats en hA uie Dia gta LP Rr 165 15 2 1 Functional Description of the 165 15 2 2 Address Assignment of F Timer 166 15 2 3 Detailed F Timer Register 166 Chapter 16 Watchdog 167 16 1 Watchdog Timer 167 16 2 Address Assignment of Watchdog 169 16 3 Detailed Watchdog Register 170 Chapter 17 System Control 175 8 Preliminary Users Manual A17812EE1V1UM00 17 1 Address Assignment of System Control Registers 175 17 2 Detailed System Control Register lt 176 Chapter 18 ERTEC 400 Clock 195 18 1 Clock Supply in ERTEC 400 195 18 2 Specific Clock Supplies 197 Chapter 19 Reset Logic of 400
9. FFFF FFFFH Watchdog timer 1 counter register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary Users Manual A17812EE1V1UM00 169 Chapter 16 Watchdog Timers 16 3 Detailed Watchdog Register Description Figure 16 3 Watchdog Control Status Register CTRL STATUS 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 reserved 1 0 Bit position Bit name Function Key bits Key bits Must be written with 9876H in order to make a write access effective read OOOOH Reserved Status Counter 1 Represents the current status of watchdog timer 1 counter Status Counter 1 Watchdog timer 1 counter status Status Watchdog 1 has not expired initial value Counter 1 Watchdog 1 has expiredNote Note This bit can only be read as 1 when the Run xStop 21 bit is set Status Counter 0 Represents the current status of watchdog timer 0 counter Status Counter 0 Watchdog timer 0 counter status Status_ Watchdog 0 has not expired initial value Counter 0 Watchdog 0 has expiredNote Note This bit can only be read as 1 when the Run xStop 20 bit is set to Load Common load trigger for both watchdog timer counters Reload for watchdog timer counters No effect initial value Watchdog counters 0 and 1 are loaded with their respective reload register values
10. 70 6 4 External Memory Connection 72 Chapter 7 Interrupt 73 71 Prioritization of 74 7 22 Tngger Modes TE See eee BC tee SSE 75 7 3 Masking the Interrupt 75 7 44 Software Interrupts for 75 7 5 Nested Interrupt Structure 75 7 6 76 7 7 IRQ Interrupts as FIQ Interrupt Sources 76 7 8 interrupt Control Register 77 7 9 Detailed ICU Register lt 79 Chapter 8 PCI Interface ice oo vol REEL RE ED E kde reus 95 8 1 PC Functionality eee ph eee xa Soh Sie 96 8 1 1 PCI Interrupt Handling 97 8 1 2 PCI Power 98 8 1 3 Accesses to the AHB 98 Preliminary User s Manual A17812EE1V1UMO00 7 8 2 400 Applications with
11. 99 8 2 1 ERTEC 400 in a PC 99 8 2 2 400 as a Station on the Local 99 8 3 Address Assignment of PCI Registers 100 Chapter9 Local Bus Unit 103 94 PageSizeSelting ci ru eine iL NERA eid 105 92 Page Offset Setting 106 93 LBU Address Mapping 107 94 Page Control 0 109 9 5 Host Accesses to ERTEC 400 110 96 Address Assignment of LBU 113 97 Detailed LBU Register lt 114 Chapter 10 Boot ROM carrs psr RR 5545 117 10 1 Booting from External 118 10 2 Booting via SPI lol il eee ee ie eee eee 118 10 3 Booting Via 2 2 2 1 eee 118 10 4 Booting via PCI or oie iR cee ew ee 118 Chapter 11 General Purpose I O GPIO 119 111 Address Assignment of GPIO 120 11 2 Detailed GPIO R
12. IRVEC 3 0 Acknowledge of highest priority pending interrupt request by reading the associated IRQ interrupt vector number IRVEC 3 0 IRQ Interrupt vector number 0000 Valid IRQO with highest priority pending Valid IRQ15 with highest priority pending or default vector initial value 11115 84 Preliminary Users Manual A17812EE1V1UMOO Chapter 7 Interrupt Controller Figure 7 7 FIQACK FIQ Interrupt Acknowledge Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0018H FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vector ID FIVEC Bit position Bit name Function Vector ID 28 0 Differentiates valid FIQ interrupt vectors from the default FIQ vector Vector ID Vector ID 28 0 FIQ interrupt vector identification 0000 0000H Valid FIQ interrupt vector pending 1FFF FFFFH Default interrupt vector initial value FIVEC 2 0 Acknowledge of highest priority fast interrupt request by reading the associated FIQ interrupt vector number FIVEC 2 0 FIQ Interrupt vector number 000 Valid FIQO with highest priority pending Valid FIQ7 with highest priority pending or default vector initial value Preliminary Users Manual A17812EE1V1UM00 85 Chapter 7 Interrupt Controller Figure 7 8 IRCLVEC IRQ Interrupt Request Clear Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 001CH undefined 1
13. General purpose signal TXD2 General purpose signal CTS1_N ETMEXTOUT General purpose signal DSR1_N TRACEPKT3 General purpose signal DCD1_N TRACEPKT2 GPIO9 General purpose I O signal RXD1 TRACEPKT1 GPIO8 General purpose signal TXD1 TRACEPKTO GPIO 7 0 General purpose O signal Note Function alternative functions are selected with the PORT MODE GPIO PORT MODE L registers In this table the I O types are listed for the GPIO function 38 Preliminary Users Manual A17812EE1V1UMOO Chapter 2 Pin Functions Table 2 7 UART1 and UART2 Pin Functions Pin Name oNote Function Alternate FunctionN te UARTI transmit data output GPIO8 TRACEPKTO UARTI receive data input GPIO9 TRACEPKT1 UART1 carrier detection signal GPIO10 TRACEPKT2 UART1 data set ready signal GPIO11 TRACEPKT3 UARTI transmit enable signal GPIO12 ETMEXTOUT UART2 transmit data output GPIO13 UART2 receive data input GPIO14 UART2 carrier detection signal GPIO15 WDOUTO N DSR2 N UART2 data set ready signal GPIO16 SSPCTLOE ETMEXTIN1 CTS2 N UART2 transmit enable signal GPIO17 SSPOE Note Function and alternative functions selected with the GPIO PORT MODE GPIO PORT MODE L registers In this table the I O types are listed for the UART1 and UART2 func tion Table 2 8 SPI Pin Functions Pin Name Function Alternate Function ete SSPRX
14. 122 GPIO PORT MODE Register 2 123 GPIO PORT MODE H Register 124 UART1 2 Macro Block 128 UARTDR1 2 Data Register eren 131 Preliminary User s Manual A17812EE1V1UMOO 11 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 12 9 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 14 1 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 15 10 Figure 15 11 Figure 15 12 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 9 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 Figure 17 8 Figure 17 9 Figure 17 10 Figure 17 11 Figure 17 12 Figure 17 13 Figure 17 14 Figure 17 15 Figure 17 16 Figure 17 17 Figure 17 18 Figure 17 19 Figure 17 20 Figure 17 21 UARTRSR UARTEGR1 2 Registers 132 UARTLCR_H1 2 Registers 1 2 2 442 00 0 00 133 UARTLCOR_M1 2 Register 134 UARTLCR L1 2 Register eene eene nens streiten nnne nns 135 UARTCR 1 2 Registers 1 2
15. Preliminary Users Manual A17812EE1V1UM00 89 Chapter 7 Interrupt Controller Figure 7 16 IRREG IRQ Interrupt Request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0058H 0000 0000H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 IRREG Bit position Bit name Function 31 16 Reserved IRREG 15 0 Individual indication of IRQ interrupt requests that have been recognized by the ICU Bit 0 corresponds to IRQO etc IRREGn n 0 15 Recognition of IRQ interrupt request Interrupt request IRQn not recognized by ICU initial value Interrupt request IRQn has been recognized by ICU Figure 7 17 MASKREG IRQ Interrupt Mask Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 6 MASKREG Bit position Bit name Function 31 16 Reserved MASKREG 15 0 Individual masking of IRQ interrupt inputs Bit 0 corresponds to IRQO etc MASKREGn 0 15 Masking of IRQ interrupt inputs Interrupt request IRQn enabled MASKREG Interrupt request IRQn masked initial value 90 Preliminary Users Manual A17812EE1V1UMOO Chapter 7 Interrupt Controller Figure 7 18 ISREG IRQ Interrupt In Service Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0060H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISREG Bit position Bit name Function 31 16 Reserved
16. 12 5 MHz REF_CLK 25 50 MHz Divider 1 Lock Timer PLL_IN PLL_OUT Osc 12 5 MHz 300 MHz CLKP B 4 APLL CLK_50 Clock D 50 MHz Power up Generation CLK_100 D gt 100 MHz 650 us gt PLL_LOCK_STATE Divider T CONFIG1 196 Preliminary Users Manual A17812EE1V1UM00 Chapter 18 ERTEC 400 Clock Supply 18 2 Specific Clock Supplies The clock supply of the bridge is implemented using two different clock inputs Using the external CLK PCI pin with a frequency of up to 66 MHz Using the internal CLK 50 clock that is enabled to the AHB PCI bridge per SW via the CLK CTRL REG register in the system control register block After a power up reset the CLK 50 clock supply on the AHB side of the AHB PCI bridge is enabled If the LBU interface is used instead of the PCI interface by pulling CONFIG2 to low level during reset CLK 50 is enabled for the LBU clock supply The clock supply for the LBU is automatically disabled in PCI mode On the other hand it is recommended that in LBU mode the AHB clock for the PCI bridge is disabled Configuration pin CONFIG2 is used to select PCI or LBU mode CONFIG2 0 LBU mode CONFIG2 1 PCI mode Remark If neither the PCI interface not the LBU interface of ERTEC 400 is used the device must be configured to LBU mode anyhow by pulling CONFIG2 to low level The clock supply for the JTAG interface is implemented using the JTA
17. 38 UART1 and UART2 Pin 39 SPI PIM FUNCHONS i a ee 39 MG PLL Piri F hctlons iei erectione ener reete 40 Clock and Reset Pin Functions sss 40 JTAG and Debug Interface Pin 40 Trace Port Pin F nctions anco iecit ene erue ene e n d EE e dns 41 Power Supply Pin en 41 Pin Characteristics iin eec Ur e Mel A UL RE Rae Pe Pd 42 Pin Status During Reset and Recommended 44 CP15 Coprocessor Registers nennen nennen tentent enne 50 Possible AHB Master slave Combinations 52 Memory Area Partitioning 53 Detailed Description of Memory Segment sse 54 Memory Map and Used Address Range 56 External Memory Interface Pin 59 External Memory Interface Control 61 FIG Intemmpt SOUrGes n nee er etia 73 IRQ Interr pt SOUFC6S oon reve et eut ue Bea e 74 Interrupt Control Registers ennemi 77 PCI Interface Pin 95 POlInterr pt Routing io
18. L 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 00 0010H 0000H 00 0020H 0000H 00 0030H 0000H LBU Pn RG L R W Bit 15 8 of the LBU page n size setting Always Op writing has no effect Figure 9 7 LBU Page Range Register High LBU Pn RG H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 00 0012H 0000H 00 0022H 0000H 00 0032H 0000H Always 0p writing has no effect LBU Pn RG H R W Bit 21 16 of the LBU page n size setting 114 Preliminary Users Manual A17812EE1V1UMOO Chapter 9 Local Bus Unit LBU Figure 9 8 LBU Page Offset Register Low LBU Pn 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 OF L Address 00 0004H 00 0014H 00 0024H 00 0034H Initial value 0000H 0000H 0000H 0000H LBU Pn OF L R W Bit 15 8 of the LBU page n offset setting Always 0p writing has no effect Figure 9 9 LBU Page Offset Register High LBU Pn _ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LBU Pn OF H OF H Address 00 0006H 00 0016H 00 0026H 00 0036H Initial value 0000H 0000H 0000H 0000H LBU Pn OF H Bit 31 16 of the LBU page n offset setting Preliminary Users Manual A17812EE1V1UM00 115 116 Chapter 9 Local Bus Unit LBU Figure 9 10 LBU Page Configuration Register LBU Pn CFG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value reserved 00 0008H 0000H 00 0018H 0000H 00 0028H 0000H 00 0038H 0000H Bit position Bit name Funct
19. O O OJ O O O O O O Chip select to static memories peripherals Byte enable to static memories peripherals and SDRAM RDY PER N Ready signal from static peripherals DTR OE DRIVER N Direction signal for external driver or scan clock Enable signal for external driver or scan clock Note The BOOT 2 0 and CONFIG 4 0 pins used as inputs and read into the Boot_REG respectively Config_REG system configuration registers during the active RESET phase After a reset these pins are available as normal function pins and used as outputs Preliminary User s Manual A17812EE1V1UMO00 33 Pin Name AD31 VoNote Chapter 2 Pin Functions Table 2 2 PCI Interface Pin Functions Function PCI address data bit Alternate FunctionMote LBU CS RN AD 30 29 PCI address data bits LBU SEG 1 0 AD 28 24 PCI address data bits LBU AB 20 16 AD 23 16 PCI address data bits LBU_AB 13 6 AD 15 0 PCI address data bits LBU_DB 15 0 IDSEL PCI initialization device select LBU AB14 CBE3_N PCI byte enable LBU_AB15 2 PCI byte enable PCI byte enable LBU AB5 LBU BE1 N PCI byte enable LBU BEO N PCI power management PCI request LBU RDY N LBU CS M N PCI grant LBU CFG RES PCI N PCI clock PCI reset INTA N PCI INTA LBU IRQO N INTB N PCI INTB N PCI clock selection IRQ1
20. 5000 0080 PRIOREG4 0000 000 5000 0084H PRIOREG5 0000 0000H 5000 0088H PRIOREG6 0000 000FH 5000 008CH 5000 0090H PRIOREG7 PRIOREG8 0000 000FH 0000 0000 5000 0094 PRIOREG9 0000 000FH 5000 0098H PRIOREG10 0000 000 5000 009CH PRIOREG 1 1 0000 0000H 5000 00A0H PRIOREG12 0000 0000H 5000 00A4H 5000 00A8H PRIOREG13 PRIOREG14 0000 000 0000 000FH 5000 00 Note Reserved bits in all registers are undefined when read always write the initial reset values to PRIOREG15 these bits 78 0000000FH Description IRQ priority registers for inputs IRQO to IRQ15 of the IRQ interrupt controller Preliminary Users Manual A17812EE1V1UMOO0 Chapter 7 Interrupt Controller 7 9 Detailed ICU Register Description Figure 7 1 IRVEC IRQ Interrupt Vector Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0000 FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Vector ID IRVEC Bit position Bit name Function Vector ID 27 0 Differentiates valid IRQ interrupt vectors from the default IRQ vector Vector ID Vector ID 27 0 IRQ interrupt vector identification 000 0000 Valid IRQ interrupt vector pending FFF FFFFH Default interrupt vector initial value IRVEC 3 0 Number of the currently pending valid IRQ interrupt vector with the highest pr
21. Else initial value Receive FIFOs are enabled and full or FIFOs are disabled and receive holding registers are full TXFF Indicates whether transmit FIFO is full Else initial value Transmit FIFOs are enabled and full or FIFOs are disabled and transmit holding registers are full RXFE Indicates whether receive FIFO is empty Else Receive FIFOs are enabled and empty or FIFOs are disabled and receive holding registers are empty initial value BUSY Indicates that the UART is busy BUSY UART busy flag ELM NEN 1 Sending data is in progress or transmit FIFO is not empty 5 or both Preliminary Users Manual A17812EE1V1UMOO 137 Bit position Chapter 12 UART1 UART2 Figure 12 8 UARTFR1 2 Registers 2 2 Bit name Function DCD DoD This flag reflects the inverse logical level of the DCD1 2 N input pin DSR DSR This flag reflects the inverse logical level of the DSR1 2_N input pin 138 CTS CTS This flag reflects the inverse logical level of the CTS1 2_N input pin Preliminary Users Manual A17812EE1V1UM00 Chapter 12 UART1 UART2 Figure 12 9 UARTIIR UARTICR1 2 Registers 7 6 5 4 3 2 1 0 Address Initial value 4000 241CH 00H Bit position Bit name Function Reserved undefined when read RTIS Receive timeout interrupt status bit indicates if a receive timeout interrupt was generated within UART1 2 RTIS Receive timeout interrupt statu
22. PCI parity LBU_WR_N PERR_N PCI system error PCI parity error LBU_POL_RDY LBU_RD_N STOP_N PCI stop LBU_ABO DEVSEL_N TRDY_N PCI device select PCI target ready LBU AB1 LBU AB2 IRDY_N FRAME_N PCI initiator ready PCI cycle frame LBU_AB3 LBU_AB4 Note PCI pins are alternatively used as local bus interface pins in this table the type is listed for the PCI function 34 Preliminary Users Manual A17812EE1V1UMOO Pin Name LBU_AB 20 16 Table 2 3 Local Bus Interface Pin Functions VoNote Chapter 2 Pin Functions Function LBU address bits Alternate Function te AD 28 24 LBU_AB15 LBU address bit CBE3_N LBU_AB14 LBU address bit IDSEL LBU_AB 13 6 LBU address bits AD 23 16 LBU AB5 LBU address bit CBE2 N LBU 4 LBU address bit FRAME N LBU ABS LBU address bit IRDY_N LBU_AB2 LBU AB1 LBU address bit LBU address bit TRDY DEVSEL N LBU ABO LBU address bit STOP N LBU DB 15 0 LBU WR LBU data bits LBU write control signal AD 15 0 PAR LBU RD N LBU read control signal PERR N LBU BE 1 0 N LBU SEG 1 0 LBU byte enable LBU page selection signal CBE 1 0 N AD 30 29 LBU_IRQ_1_N LBU interrupt request signal INTB_N LBU IRQ LBU interrupt request signal LBU ready signal INTA_N LBU chip select
23. RELD 0 RELD 1 Control Status 16 1 Watchdog Timer Function Watchdog timer 0 is a 32 bit down counter to which the WDOUTO N output is assigned This output can be used as an alternative function 2 of the GPIO15 pin see Chapter 11 2 The timer is locked after a reset It is started by setting the Run xStop 70 bit in the CTRL STATUS watchdog register maximum monitoring time of 85 89 s with a resolution of 20 ns can be programmed Watchdog timer 1 is a 36 bit down counter in which only the upper 32 bits can be programmed The WDOUT 1 output signal is assigned to watchdog timer 1 This output signal is not routed to the outside it triggers a hardware reset internally The timer is locked after a reset It is started by setting the Run xStop 21 bit in the CTRL STATUS watchdog register A maximum monitoring time of 1374 3 s with a resolution of 320 ns can be programmed When the Load bit is set in the CTRL STATUS watchdog register both watchdog timers are simultaneously reloaded with the applicable reload values of their reload registers In the case of watchdog timer 1 bits 35 4 are loaded with the reload value bits 3 0 are set to 0 The count values of the watchdog timers can also be read When watchdog timer 1 is read bits 35 4 are read out The status of the two watchdog timers can be checked by reading the CTRL STATUS register The WDINT interrupt of the watchdog timer 0 is routed to the input FIQO of the FIQ interrup
24. Size of region Cache and write buffer configuration Read write access enable for privileged users users They have to be made in the following registers of the ARM946E S Register 2 Cache configuration register Register 3 Write buffer control register Register 5 Access permission register Register 6 Protection region base size register The base address defines the start address of the region It must always be a multiple of the size of the region Example The region size is 4 kBytes The starting address is then always a multiple of 4 kBytes Before the MPU is enabled at least one region must have been specified Otherwise the ARM946E S can enter a state that can only be cancelled by a reset The MPU can be enabled by setting Bit 0 of the CP15 control register If the MPU is locked neither the nor the D cache can be accessed even if they are enabled 3 5 Bus Interface of ARM946E S The ARM946E S uses an AHB bus master interface to the multilayer AHB bus for opcode fetches and data transfers The interface operates at a fixed frequency of 50 MHz independently of the CPU frequency The two uni directional data buses and the address bus each have a width of 32 bits The AHB bus supports burst transfers that are typically used during cache operations To improve system performance the AHB bus master interface contains a write buffer that reduces CPU stall times during data cache misses The wr
25. 6 3 2 1 Minor Revision 7 0 Function Major revision code initial value OOH Minor Revision Minor revision code initial value OOH Preliminary Users Manual A17812EE1V1UMOO 61 Chapter6 External Memory Interface EMIF Figure 6 2 Async_Wait_Cycle_Config Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved Wait polarity Selects if RDY_PER_N signal is interpreted as active high or active low Wait polarity Wait if RDY_PER_N is low Wait if RDY_PER_N is high initial value Reserved Max_Ext_Wait Determines the number of AHB cycles before termination of an asynchronous memory or peripheral access with an IRQ Max_Ext_Wait 7 0 Wait cycle setting This value multiplied by 16 is equivalent to the number of AHB clock cycles that the asynchronous controller waits for RDY_PER_N before access is terminated with timeout IRQ The initial setting is 80H corresponding to 2048 AHB cycles or 40 96 us in case of 50 MHz AHB clock n FFH 62 Preliminary User s Manual 17812 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 3 SDRAM Bank Config Register 1 2 31 _ 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 fos Wa e ral ROWS es BANK Peso Bit position
26. ARM PrimeCell Synchronous Serial Port PL021 Technical Refer ence Manual DDI0171BN te ARM Embedded Trace Macrocell Architecture Specification 0014 0 ARM Multi ICE System Design Considerations Application Note 72 DAIOO72ANote Note These documents are available from ARM Limited www arm com 6 Preliminary User s Manual 17812 1 10 00 Table of Contents Chapter 1 Introduction sane 17 1d General 20222 a r Aigner kem eee ie 17 1 2 Device 19 1 3 Ordering Information 21 14 Pin Configuration cise ee er rers re a timed eee 22 1 5 Pinldentification 2 22 4 27 1 6 Configuration of Functional 29 1 6 1 Block Diagram of ERTEC 400 29 1 6 2 Orncchip Urits d het REM WEE ER oe ved ee 30 Ghapter2 Pin Functions vp ze xe kn xRERRRLE ERG x 33 2 1 List of Pin Functions 21 ict tee ll il EIER Bee 33 22 Pin Characteristics cards aana eel ee A lI Re Run eee 42 2 3 Pin Status and Recommended Connections 44 Chapter3 CPU Function koh RR ka RR 47 3 4 Structure of
27. Local SRAM slave interface External memory interface slave interface AHB to APB bridge slave interface The current AHB master can access the remaining I O devices that are connected to the APB bus via an AHB to APB bridge PCI and LBU masters must be used exclusively i e only one can be active The selection is made during reset using the CONFIG2 input pin 4 1 Multilayer AHB Bus The multilayer AHB bus in ERTEC 400 is characterized by high bus availability and data throughput The multilayer AHB bus is a 32 bit wide bus with multiple master capability It runs at a frequency of 50 MHz and has the functionality of the ARM AHB bus see documents listed on page 6 By combina tion of multiple AHB segments to the multilayer AHB bus three AHB masters can access various AHB slaves simultaneously PCI and LBU masters must be used exclusively i e only one can be active The selection is made during reset using the CONFIG2 input pin 1 AHB Arbiters Arbiters control the access when multiple AHB masters try to access a slave simultaneously Each of the AHB arbiters uses the same round robin arbitration scheme The round robin arbitration scheme prevents mutual blocking of the AHB masters over a long period on the multilayer AHB bus 2 AHB Master Slave Coupling As can be seen in the block diagram in Figure 1 2 not every AHB master is connected to an arbi trary AHB slave Table 4 1 shows the possible AHB master slave commun
28. Mask for all interrupts 5000 0024 IRQEND Ox End of IRQ interrupt 5000 0028H 5000 002CH FIQEND FIQPRO Ox 0000 0007H 5000 0030H FIQPR1 0000 0007H 5000 0034H 5000 0038H FIQPR2 FIQPR3 0000 0007H 0000 0007H 5000 003CH FIQPR4 0000 0007H 5000 0040H 5000 0044H FIQPR5 FIQPR6 0000 0007H 0000 0007H 5000 0048H FIQPR7 0000 0007H End of FIQ interrupt FIQ priority registers for inputs FIQO to FIQ7 of the FIQ interrupt controller 5000 004CH 5000 0050H FIQISR FIQIRR 0000 0000H 0000 0000 FIQ in service register FIQ request register 5000 0054H FIQ MASKREG 0000 00FFH FIQ interrupt mask register 5000 0058H IRREG 0000 0000H Interrupt request register 5000 005CH MASKREG 0000 FFFFH Interrupt mask register 5000 0060H ISREG 0000 0000H In service register 5000 0064H TRIGREG 0000 0000H Trigger select register 5000 0068H EDGEREG 0000 0000H Edge select register 5000 006CH SWIRREG 0000 0000H Software interrupt register Preliminary Users Manual A17812EE1V1UM00 77 Chapter 7 Interrupt Controller Table 7 3 Interrupt Control Registers 2 2 Address 5000 0070H Register Name PRIOREGO Initial value 0000 000 5000 0074H 5000 0078H PRIOREG1 PRIOREG2 0000 000FH 0000 0000 5000 007 PRIOREG3 0000 000
29. PCI Interface Host bridge functionality Master target functions 32 bit 66 MHz PCI bus 32 bit AHB bus configuration registers can be initialized from ARM946E S side Power Management V1 1 PCI interrupt outputs INTA_N INTB N and SERR_N PCI segment of max 2 GBytes can be addressed 3 3 V interface 5 V compatible Fully compatible with PCI Local Bus Specification 2 2 Local Bus Unit LBU 16 bit data bus width 21 bit address bus width Host access to LBU paging registers via chip select signal CS Host access to any address area of ERTEC 400 via chip select signal CS M N Maximum of 4 pages can be addressed Adjustable page range and page offset for each page reconfigurable at any time Other I O Interfaces 32 bit General Purpose I O GPIO Input outputs can be assigned on a bit by bit basis All GPIO equipped with internal pull up resistor 4 GPIO inputs are interruptible active Low level is not a supported interrupt level GPIOs be assigned up to 4 different functions see Table 2 6 8 16 32 bit access to registers is possible UART 1 and 2 Based ARM PrimeCell UART PL010 and widely 16550 compatible SPI Supports Motorola SPI TI SSI and National Instruments microwire modes Programmable data frame size and bit rate Master and slave mode capability Send and Receive FIFOs with 8 16 bit entries Group and overrun error interrupts Timers Two 32 bit down counters with load
30. SMI MDIO Schmitt 3 3 V CMOS RES PHY 3 3 V CMOS TXD Pn 1 0 Note 1 3 3 V CMOS RXD_Pn 1 0 Note 1 Schmitt 50 kQ pull down TX EN pnNete 1 3 8 V CMOS CRS_DV_PnNote 1 Schmitt 50 kQ pull down ER pnNete 1 Schmitt 50 kO pull down TXD Pn 3 0 Note 2 3 8 V CMOS RXD_Pn 3 0 Note 2 TX EN PnNete2 Schmitt 3 3 V CMOS 50 kQ pull down 2 _ _ Schmitt Schmitt 50 kQ pull down 50 kQ pull down TX ERR PnNote2 3 3 V CMOS RX Dv pnNete Schmitt 50 kO pull down COL pete RX_CLK_PnNote 2 Schmitt Schmitt 50 kQ pull down 50 kQ pull down TX CLK PnNote2 Schmitt 50 kO pull down GPIO 31 23 Schmitt 3 3 V CMOS 50 kQ pull up GPIO 22 19 Schmitt 3 3 V CMOS 50 kQ pull up GPIO 18 12 Schmitt 3 3 V CMOS 50 kQ pull up GPIO 11 0 Schmitt 3 3 V CMOS 50 kQ pull up TRACECLK 3 3 V CMOS CLKP_A Osc in CLKP_B Osc out F_CLK 3 3 V CMOS REF_CLK 3 3 V CMOS RESET_N Schmitt 50 kQ pull up TRST_N Schmitt TCK Schmitt 50 kQ pull up TDI Schmitt 50 kQ pull up TMS Schmitt 50 kQ pull up TDO 3 3 V CMOS DBGREQ TAP_SEL Schmitt Schmitt 50 kQ pull down 50 kQ pull up Notes 1 The number can take the integer values 0 to 3 and refers to the R
31. 001 9 column address lines 010 10 column address lines 011 11 column address lines others Reserved 64 Preliminary User s Manual 17812 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 4 SDRAM Refresh Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value res Mes reserved 7000 000CH 0000 0190H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved refresh rate Bit position Bit name Function Reserved Asynchronous timeout Indicates whether the interval that is specified with the Async Wait Cycle Control register has elapsed Asynchronous timeout Interval that is specified with the Async Wait Cycle Control register has not yet elapsed initial value Interval that is specified with the Async Wait Cycle Control register has elapsed SDRAM initialization done Indicates if the SDRAM initialization sequence is completed SDRAM initialization done SDRAM initialization sequence is not completed initial value init done SDRAM initialization sequence is completed Reserved Refresh rate Specifies the number of AHB clock cycles between 2 SDRAM refresh cycles the initial setting of 190H corresponds to a refresh cycle of 8us with 50 MHz SDRAM clock refresh rate Preliminary Users Manual A17812EE1V1UM00 65 Chapter6 External Memory Interface EMIF Figure 6 5 Bank 3 0 Config Reg
32. ISREG 15 0 Individual indication of IRQ interrupt requests that have been confirmed by the CPU Bit 0 corresponds to IRQO etc ISREGn O 15 Confirmation of IRQ interrupt request Interrupt request IRQn not confirmed initial value Interrupt request IRQn has been confirmed Figure 7 19 TRIGREG IRQ Trigger Mode Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0064H 0000 0000H 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 7 TRIGREG Bit position Bit name R W Function 31 16 Reserved TRIGREG 15 0 Individual selection of edge or level trigger mode for each IRQ interrupt input Bit 0 corresponds to IRQO etc TRIGREG TRIGREGn 0 15 Selection of IRQ trigger mode Edge trigger mode for IRQn initial value Level trigger mode for IRQn Preliminary Users Manual A17812EE1V1UM00 91 Chapter 7 Interrupt Controller Figure 7 20 EDGEREG IRQ Trigger Edge Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 EDGEREG Bit position Bit name R W Function 31 16 Reserved EDGEREG 15 0 Individual selection of positive or negative trigger edge for each IRQ interrupt input The setting of this bit is only relevant if edge trigger mode has been set for the respective IRQ input using the TRIGREG register Bit 0 corresponds to IRQO etc EDGEREG ED
33. LBU ready signal LBU chip select for ERTEC 400 internal resources LBU CS N LBU chip select for page configuration registers LBU RD WR control selection LBU polarity selection for LBU RDY N pin LBU CFG LBU POL RDY total Four different pages within ERTEC 400 can be accessed via the LBU Each page can be set individu ally The settings for the four pages are made via the LBU page registers Five registers are available per page the LBU CS R N chip select signal can be used to access the page registers The following settings are possible for each page Access size of a page between 256 Bytes and 2 MBytes with two page range registers LBU Pn Hand LBU Pn L Offset segment of page in 4 GBytes address area with two page offset registers LBU Pn OF H and LBU Pn OF L Access type data bit width with a single page control register Pn The ERTEC 400 internal address area is accessed via the LBU CS M N chip select signal The two chip select signals LBU CS R N for LBU registers and LBU CS M N for ERTEC 400 internal resources must not be simultaneously active The LBU supports accesses to the address area with two separate read and write lines or with a com mon read write line The access type is selected via the LBU_CFG input LBU CFG 0 LBU CFG 1 use separate read and write lines LBU WR N and LBU RD N use LBU WR N as common read write control line Prelimina
34. NEC Preliminary User s Manual ERTEC 400 Enhanced Real Time Ethernet Controller 32 Bit RISC CPU Core Hardware py PD800232F1 012 HN2 Document No A17812EE1V1UMOO Date Published July 2007 NEC Electronics Corporation 2007 Printed in Germany NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and MIN due to noise etc the device malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vit MAX Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to
35. e Boot 8 ROM Slave Slave Slave Master APB 8 kBytes A 1 32 bit 50 MHz Y Input MUX Arb MUX Arb Decode T GPIO Ko a 5 Bridge 8 js I Multilayer amp 2x UART 4 P orts input Input 32 bit 50 MHz o 32 sie MUX Arb g ri 1 e WDT ivi g SPI Master Slave 8 Interface 6 AHB AHB 2 Wrapper Wrapper a Slave Master T Master Master Slave MC Bus 32 bit 50 MHz SC Bus 32 bit 50 MHz i 2 x Timer a CAES 8 Watchdog F Timer Local PCI Communi i Bridge Switch Control lep cation Bus Unit SRAM o System LBU 32 bit 66 MHz 192 kBytes E Control A Master Target 16 bit capable at 1 Register Ethernet Ethernet Ethernet Ethernet IRT la gt MC MC_PLL j gt Channel Channel Channel gt Channel Switch 2 Port 0 Port 1 Port 2 Port 3 Macro la gt SMI 7 52 4 REF_CLK gt I 2 x Ml gt lt gt PCl Local Bus Preliminary Users Manual A17812EE1V1UMOO 29 Chapter 1 Introduction 1 6 2 On chip Units 1 2 3 4 5 6 7 8 30 CPU ARM946E S ERTEC 400 uses an ARM946E S 32 bit RISC processor core running at a maximum speed of 150 MHz This core processes 32 bit instructions according to the ARM5v5TE instruction set architecture as well as 16 bit wide THUMB instructions Instruction throughput is in
36. Bit name Function Reserved Write burst type Selects between single writes and burst writes Write burst type Use burst length as programmed in Extended_Config register initial value Single write not permitted if 16 bit wide SDRAM bank has been selected CAS latency CAS latency 2 CAS latency 3 initial value CAS latency Reserved Row address select Configures the number of used row address lines ROWS 2 0 Number of used row address lines 000 8 row address lines initial value 9 row address lines 10 8 Nete 10 row address lines 11 row address lines 12 row address lines 101 13 row address lines others Reserved Reserved Note Writing to the SDRAM_Bank_Config register executes the Mode Register Set command on the SDRAM if Bit 29 init_done is set in the SDRAM_Refresh_Control register i e the SDRAM power up sequence has been executed Preliminary Users Manual A17812EE1V1UM00 63 Chapter6 External Memory Interface EMIF Figure 6 3 SDRAM Bank Config Register 2 2 Bit position Bit name Function Internal SDRAM bank setup IBANK 2 0 Number of internal SDRAM banks 1 bank 2 banks 4 banks initial value Reserved Reserved Page size Configures the SDRAM page size by selection of the number of column address lines Page size 2 0 Number of column address lines 000 8 column address lines initial value Page size
37. Expansion ROM Base Address reserved 0000 0000H 8000 0034H 8000 0038H Reserved Reserved Capability __ Pointer 0000 0048H 0000 0000H 8000 003CH Max Lat Min Gnt Interrupt Pin Interrupt Line 0000 0000H 8000 0040H 8000 0044H Device ID Subsystem ID Vendor ID Subsystem Vendor ID 0000 0000H 0000 0000H 8000 0048H PM Capability PM next item ptr PM Capabilit y id 0002 0001H 8000 004CH PM Data PM CSR BS E PM Control Status 0000 0000H 8000 0050H PCI Base Address Mask RegisterO 0000 0000H 8000 0054H PCI Base Address Mask Register1 0000 0000H 8000 0058H PCI Base Address Mask Register2 0000 0000H 8000 005CH PCI Base Address Mask Register3 0000 0000H 8000 0060H PCI Base Address Mask Register4 0000 0000H 8000 0064H PCI Base Address Mask Register5 0000 0000H 8000 0068H PCI Base Address Translation RegisterO 0000 0000H 8000 006CH PCI Base Address Translation Register1 0000 0000H 8000 0070H PCI Base Address Translation Register2 0000 0000H 8000 0074H PCI Base Address Translation Register3 0000 0000H 8000 0078H PCI Base Address Translation Register4 0000 0000H 8000 007CH 100 PCI Base Address Translation Register5 Preliminary Users Manual A17812EE1V1UMOO 0000 0000H Chapter 8 PCI Interface Table 8
38. ISREG IRQ Interrupt In Service Register 91 TRIGREG IRQ Trigger Mode Select Register 91 EDGEREG IRQ Trigger Edge Select Register 92 SWIRREG Software IRQ Interrupt Register 92 PRIOREGO 15 IRQ Interrupt Priority Register 93 PCI lInterr pt Handling e 97 Example for LBU Address Line 108 LBU Read from ERTEC 400 with Separate Read Control Line 110 LBU Write to ERTEC 400 with Separate Write Control 111 LBU Read from ERTEC 400 with Common Read Write Control Line 111 LBU Write to ERTEC 400 with Common Read Write Control 112 LBU Page Range Register Low LBU Pn RQG L sene 114 LBU Page Range Register High LBU Pn 114 LBU Page Offset Register Low LBU Pn OF L 115 LBU Page Offset Register High LBU Pn OF H seen 115 LBU Page Configuration Register LBU Pn CFQG see 116 GPIO Cells of ERTEC 400 20 124 1 00000000 0 119 GPIO IOGTRL Register dt nhe inn c ir 121 GPIO QUT Register zone doeet ae ie aie ee ege en eee ees 121 GPIOIN cud I E
39. N 3 3 V CMOS 6 mA 6 mA 3 0 DQM 3 0 3 3 V CMOS 9 mA 9 mA RDY PER N Schmitt 50 kQ pull up DTR 3 3 V CMOS 9 mA 9 mA OE DRIVER N OO OO O OF O 3 3 V CMOS 9 mA 9 mA AD 31 0 2 Pc Note 2 IDSEL CBE 3 0 _N pc Note 2 pPc Note 2 Pc Note 2 PME_N pc Note 2 pcNote 2 REQ N pcNote 2 GNT CLK PCI pc Note 2 pc Note 2 RES PCI N pc Note 2 Pc Note 2 INTB_N Schmitt Pc Note 2 Pc Note 2 pc Note 2 Pc Note 2 pc Note 2 Pc Note 2 STOP_N pc Note 2 pc Note 2 Pc Note 2 Pc Note 2 DEVSEL_N TRDY_N pc Note 2 pc Note 2 Pc Note 2 Pc Note 2 IRDY_N pc Note 2 Pc Note 2 FRAME_N Notes 1 The address pins A 23 16 are used as inputs only during the active reset phase pc Note 2 Pc Note 2 Pc Note 2 2 PCI I Os can be either 3 3 V PCI if the PCI interface is operated with 3 3 V or 5 V tolerant PCI if the PCI interface is configured to 5 V tolerant operation Drive capability complies to the PCI specification R2 2 42 Preliminary Users Manual A17812EE1V1UMOO0 Pin Name PIPESTA 2 0 Chapter 2 Pin Functions Table 2 14 Pin Characteristics 2 2 Input type Output type 3 3 V CMOS Internal pull up down Drive capability TRACESYNC 3 3 V CMOS SMI MDC 3 8 V CMOS
40. SDRAM power up initial value Delay after system reset is immediately terminated Normal function initial value All SDRAM accesses are misses Reserved Active data bus for SDRAM accesses With an active data bus the data bus is driven actively to high level after each access to the SDRAM in order to support the integrated pull up resistors Active data bus for SDRAM No active data bus after SDRAM accesses Active data bus after SDRAM accesses initial value Active data bus for asynchronous accesses With an active data bus the data bus is driven actively to high level after each access to an asynchronous device in order to support the integrated pull up resistors Active data bus for asynchronous accesses No active data bus after asynchronous accesses Active data bus after asynchronous accesses initial value 68 Preliminary User s Manual A17812EE1V1UMOO Chapter6 External Memory Interface EMIF Figure 6 6 Extended_Config Register 2 2 Bit position Bit name Function Reserved Test mode 3 Test mode 3 Normal function initial value DTR_N is test output Reserved SDRAM burst length burst length 1 0 SDRAM burst length 00 burst_length 01 Full Page Read INCR_S burst length 4 Full Page Read INCR_S burst length 8 initial value Reserved Time between the SDRAM commands Activate and read write pre charge
41. and read into the Boot REG respectively Config REG system configuration registers during the active RESET phase After a reset these pins are available as normal function pins and used as address out puts The external memory interface supports all transfer types transfer sizes and burst operations as described in the ARM AMBA specification see page 6 except for the Split and Retry functions All AHB burst accesses to asynchronous blocks are divided into individual accesses on the external bus All AHB burst accesses with a non specified length to the SDRAM controller are divided into 8 beat burst accesses on the external bus Preliminary User s Manual A17812EE1V1UMOO 59 Chapter6 External Memory Interface EMIF The SDRAM controller has the following features e 16 bit or 32 bit data bus width selectable PC100 SDRAM compatible at 50 MHz SDRAM clock frequency Up to 256 MBytes of SDRAM for 32 bit data bus width Up to 128 MBytes of SDRAM for 16 bit data bus width e Supports various SDRAMs with the following properties CAS latency 2 or 3 clock cycles 1 2 4 internal banks can be addressed A1 0 8 9 10 11 bit column address A13 11 2 Maximum of 13 row addresses A14 2 SDRAMs with a maximum of 4 banks are supported The SDRAM controller can keep all 4 banks open simultaneously In terms of addresses these four banks correspond to one quarter of the SDRAM address area on the AHB bus As long as the alter
42. it can only be reset by overriding itNote INT_LOCK_ INT_LOCK_STATE INT_LOCK_STATE interrupt status STATE o Interrupt request is not active Interrupt request is active initial value PLL_INPUT_CLK_LOSS Represents the current monitoring status of the PLL input clock PLL_INPUT_ PLL_INPUT_ CLOCK LOSS PLL input clock monitoring status CLK_LOSS PLL input clock present initial value No PLL input clock present Note These interrupts are connected via wired OR and then routed to the FIQ3 input of the FIQ interrupt controller Preliminary Users Manual A17812EE1V1UM00 181 Chapter 17 System Control Registers Figure 17 6 PLL Status Register PLL_STAT_REG 3 3 Bit position Bit name Function PLL_LOCK Indicates if the PLL is currently locked PLL_LOCK PLL_LOCK PLL locking status Ob PLL is not locked 1p PLL is locked initial value Figure 17 7 Clock Control Register CLK CTRL REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved m oQ9 eA Bit position Bit name R W Function Reserved Clk_Ctrl Enables the clock on the AHB side of the PCI bridge Clk_Ctrl CIk Ctrl Clock control on AHB side of PCI bridge 0 Clock AHB side is disabled 1p Clock on AHB side is enabled initial value 182 Preliminary User s Manual 17812 1 10 00 Chapter 17 System Control Registe
43. 0 Bit position Bit name Function Reserved Boot mode Reflect the logical level of the BOOT 2 0 pins during the active reset phase see Table 19 1 for possible settings Note that the boot mode cannot be changed using this register as it is a read only register Boot mode 176 Preliminary User s Manual A17812EE1V1UMOO Chapter 17 System Control Registers Figure 17 3 Config Pin Register CONFIG_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2608H H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved Config pins Reflect the logical level of the CONFIG 4 0 pins during the active reset phase see Table 19 2 for possible settings Note that the configuration cannot be changed using this register as it is a read only register Config pins Figure 17 4 Reset Control Register RES_CTRL_REG 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 260CH 0000 0100H 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 XRES XRES WD _ reserved PCL PULSE_DUR res _SOF RES_ STATE T FREI Bit position Bit name Function 31 10 Reserved XRES PCI STATE Reflects the status of the RES PCI input pin XRES PCI XRES PCI STATE PCI reset status STATE NE I PCI reset is active initial value PCI reset is not active XRES PCI AHB SOFT Allows to trigger a SW reset of the A
44. 10 Asia amp Oceania NEC Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 010 8235 1155 http www cn necel com NEC Electronics Shanghai Ltd Room 2511 2512 Bank of China Tower 200 Yincheng Road Central Pudong New Area Shanghai P R China P C 200120 Tel 021 5888 5400 http www cn necel com NEC Electronics Hong Kong Ltd Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 2886 9318 http www hk necel com NEC Electronics Taiwan Ltd 7F No 363 Fu Shing North Road Taipei Taiwan 02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11 Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com 907 1 Preliminary User s Manual 17812 1 10 00 Readers Purpose Organization Legend Preface This manual is intended for users who want to understand the functions of the ERTEC 400 This manual presents the hardware manual of ERTEC 400 This user s manual describes the following sections e Pin function e CPU function Internal peripheral function Test function Symbols and notation are used as fo
45. 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bit position Bit name Function Reserved PCI SOFT RESACK Indicates whether a soft reset was executed by the PCI bridge PCI SOFT PCI SOFT RESACK PCI soft reset executed RESACK Soft reset request not acknowledged initial value Soft reset request acknowledged Figure 17 18 Memory Swap Register MEM SWAP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bit position Bit name Function Reserved MEM SWAP Re maps the internal SRAM to the original internal ROM address location MEM SWAP Memory mapping MEM SWAP Ob Boot ROM at address 0000 OOOOH initial value 1p Internal SRAM at address 0000 0000H Preliminary Users Manual A17812EE1V1UM00 189 Chapter 17 System Control Registers Figure 17 19 PCI Interrupt Control Register PCI INT CTRL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ed PCI INT SREIMS CTRL Bit position Bit name Function Reserved PCI INT CTRL Controls routing of interrupts to PCI bus pins PCI INT CTRL PCI interrupt routing Bit 0 SERR N INTB N PCI INT CTRL IRQo HP IRQO HP 2 IRQ ERR IRQO HP IRQO HP or IRQ IRT API ERR 190 Preliminary User s Manual A17812EE1V1UMOO Chapter
46. 4 STOP NNeles Pull upNete 2 4 Notes 1 The address pins A 23 16 are used as inputs only during the active reset phase in order to read the device s proper start up configurations A 23 16 must therefore be equipped with external pull up down resistors according to the desired start up configuration Please consult the user s manual for details 2 These resistors are required when neither the PCI interface nor the LBU interface are used In this case ERTEC 400 must be configured to LBU mode CONFIG2 0j 3 The reset signal that affects these pins is RES PCI N 4 These pull up resistors are required when the interface is operated in PCI mode 5 These resistors are required when the interface is operated in LBU mode 44 Preliminary Users Manual A17812EE1V1UMOO Chapter 2 Pin Functions Table 2 15 Pin Status During Reset and Recommended Connections 2 3 Pin Name DEVSEL_NNote 1 Internal pull up down during reset Level during reset External pull up down required Pull upNete 2 4 TRDY NNO Pull upNote 2 4 IRDY NNote 1 Pull upNote 2 4 FRAME NNete 1 PIPESTA 2 0 Pull upNote 4 TRACESYNC SMI MDC SMI RES PHY N TXD_Pn 1 0 Note 3 RXD_Pn 1 0 Note 3 50 kQ pull down TX_EN_PnNote 3 CRS_DV_PnNote 3 50 kQ pull down RX_ER_PnNete 3 50 kQ pull down TXD_Prigio Noes RXD Pn 3 0 Nete 5 TX EN pnNe
47. 400 These clocks are generated with an internal PLL that is in turn supplied by a quartz or oscillator The input clock is selected using the CONFIGO configuration pin CONFIGO 0 Input clock is fed with a quartz via the CLKP_A CLKP_B pins CONFIGO 1 Input clock is fed with an oscillator clock via the REF_CLK pin In the case of direct clock input at the REF_CLK pin the input clock frequency can be set with the CONFIG1 configuration pin CONFIG1 0 50 MHz input clock CONFIG1 1 25 MHz input clock Remark 400 is used a four port configuration the external PHYs must be connected via an RMII interface and 50 MHz clock for the RMII interface must be supplied at the REF_CLK pin Preliminary User s Manual A17812EE1V1UMO00 195 Chapter 18 ERTEC 400 Clock Supply The PLL generates the CLK_50 50 MHz and CLK_100 100 MHz system clocks as well as the clock for the ARM946E S This clock can be selected the CONFIG 4 3 configuration pins CONFIG4 CONFIG3 00 ARM946E S processor clock 50 MHz CONFIG4 CONFIG3 01 ARM946E S processor clock 100 MHz CONFIG4 CONFIG3 10 ARM946E S processor clock 150 MHz CONFIG4 CONFIG3 11 reserved Figure 18 1 shows the structure of the clock unit with the individual input and output clocks Figure 18 1 Detailed Representation of Clock Unit CONFIG4 HCLKEN to ARM946E S CONFIG3 CONFIGO gt CLK_ARM CLKP_A 50 100 150 MHz 12 5 MHz
48. 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 8 1 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 12 1 Figure 12 2 List of Figures Pin Configuration of ERTEC 400 304 Pin Plastic FBGA 19 mm x 19 mm 22 Internal Block Diagrar 29 ARM 946E S Processor System in ERTEC 400 47 Revision Code and Status Register 61 Async Wait Cycle Config Register 224042 000 62 SDRAM Bank Config Register 1 2 63 SDRAM Refresh Control Register 65 Async Bank 3 0 Config Registers 1 2 66 Extended Config Register 1 2 ssssssssssssssesesesee eene nnne 68 Write to External Device Active Data 70 Read from External Device Active Data
49. LBU DB12 ADOS LBU DB05 GND IO AD08 LBU_DB08 VDD IO PERR N LBU RD N AD10 LBU DB10 AD14 LBU DB14 IRDY N LBU ABOS CBE1 N LBU BE1 N VDD IO FRAME N LBU 04 SERR N LBU POL RDY DEVSEL N LBU ABO1 CBE2 N LBU 05 AD19 LBU 09 VDD IO VDD Core AD16 LBU 06 AD17 LBU ABO7 N LBU 15 AD21 LBU_AB11 AD27 LBU_AB19 VDD IO AD23 LBU_AB13 AD25 LBU_AB17 REQ_N LBU_CS_M_N AD29 LBU_SEG_0 VDD IO 22 AD31 LBU_CS_R_N Preliminary Users Manual A17812EE1V1UMO00 Pin Number Table 1 1 Pin Name 1 Pin Number Introduction Pin Configuration of ERTEC 400 2 5 Pin Name B19 PCI 15 P5V PCI B20 INTB N LBU IRQ1 N E16 GND IO B21 RXD_P3 1 RXD_P1 3 E17 RES_PCI_N B22 RXD_P3 0 RXD_P1 2 E18 VDD Core C1 A2 E19 VDD Core C2 1 21 RX_ER_P3 COL_P1 TXD_P3 1 TXD_P1 3 E22 RXD_P2 1 RXD_P1 1 TXD P3 0 TXD P1 2 F1 4 F2 A6 F4 A16 BOOTO ADOO LBU F5 A15 ADO4 LBU DB04 F6 VDD Core VDD Core F7 GND IO CBEO N LBU BEO N ADOS LBU DB09 F8 P5V PCI AD15 LBU DB15 VDD Core GND Core STOP N LBU ABOO TRDY N LBU ABO2 GND IO AD24 LBU AB16 P5V PCI AD28 LBU AB20 IDSEL LBU AB14 ADSO LBU SEG 1 GND Core VDD Core VDD C
50. LNete XXXX XXXX XXXX 0101 XXXX XXXX XXXXp GPIO IOCTRLNete XXXX XXXX XXXX XXXX XXXX XX10 XXXX XXXXp 13 function 1 14 function 1 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXXp XX01 01xx Xxxx XXXX XXXX XXXX XXXX XXXXp XXXX XXXX X10X XXXX XXXXp Table 12 5 GPIO Register Initialization Example for Five wire UARTs UART pin Realized with function GPIO8 function 1 GPIOS function 1 GPIO10 function 1 11 function 1 12 function 1 GPIO PORT MODE HNote XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXXp GPIO PORT MODE LNete XXXx xx01 0101 0101 XXXX XXXX XXXX XXXXp GPIO IOCTRLNete XXXX XXXX XXXX XXXX XXX1 1110 XXXXp 13 function 1 14 function 1 15 function 1 16 function 1 140 17 function 1 XXXX XXXX XXXX XXXX 0101 In Table 12 4 12 5 x stands for don t care 0101 01 XXXX XXXX XXXXp Preliminary User s Manual 17812 1 10 00 XXXX XXXX 11 110 XXXX XXXXp Chapter 13 Synchronous Serial Interface SPI An synchronous serial interface SPI is implemented in ERTEC 400 The inputs and outputs of the SPI interface are available as an alternative function at GPIO port 23 16 To use the SPI i
51. Nete Note Reload is executed irrespective of the Run xStop Z1 0 bits Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1 to this bit is sufficient to trigger the timer a 0 1 edge is not needed 170 Preliminary Users Manual A17812EE1V1UMOO Chapter 16 Watchdog Timers Figure 16 3 Watchdog Control Status Register CTRL STATUS 2 2 Bit position Bit name Function Run xStop_Z1 Starts stops watchdog timer 1 counter Run Run xStop Z1 Watchdog 1 start stop xStop Z1 Watchdog 1 is stopped initial value Watchdog 1 is running Run xStop 70 Starts stops watchdog timer 0 counter Run xStop 70 Watchdog 0 start stop Ob Watchdog 0 is stopped initial value Tp Watchdog 0 is running Figure 16 4 Reload Register Low for Watchdog 0 RELDO_LOW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Key bits 4000 2104H 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ReloadO Bit position Bit name Function Key bits Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload0 Holds the reload value for bits 15 0 of watchdog timer 0 counter ReloadO Preliminary Users Manual A17812EE1V1UM00 171 Chapter 16 Watchdog Timers Figure 16 5 Reload Register High for Watchdog 0 RELDO HIGH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value K
52. Preliminary Users Manual A17812EE1V1UMOO Chapter 8 PCI Interface 8 2 ERTEC 400 Applications with PCI 8 2 1 ERTEC 400 in a PC System In PC systems ERTEC 400 can be integrated into the system on a PC card with host and master functionality The PC card can be operated on the 32 bit bus at a maximum bus frequency of 66 MHz Interrupt INTB_N must then be disabled because with respect to the PC interface ERTEC 400 is only a single function device However in order for a low priority interrupt to be interrupted by a high priority interrupt from the IRT switch the IRQO HP interrupt can be output on the SERR_N output In the case of PC processors this results an NMI interrupt Optionally IRT interrupt IRQ ERR can also be placed on the SERR N output Power management support is an additional requirement In such applications the PC card can be operated in different power modes The PC card is also able to generate certain events in the host system that wake up the host system WAKE function If the Wake function is employed for the PC card it must be ensured that the PC card can still operate at reduced function in power down state and that an interrupt can be generated via the PME N output The following sequence illustrates the functioning of a power management state A power down state e g D3hot is requested by the PC host Interrupt is requested at the local processor e Current state is backed up with
53. Registers 4000 2600H 4000 26FFH 256 Bytes 4000 2600H 4000 26A3H 164 Bytes Not used F Counter 4000 2700H 4000 27FFH 256 Bytes 4000 2700H 4000 2707H 8 Bytes Not used Not used 4000 2800H 4FFF FFFFH almost 256 MBytes Not used Interrupt controller 5000 0000H 5FFF FFFFH 256 MBytes 5000 0000H 5000 007F 128 Bytes Not used Internal SRAM 6000 0000H 6FFF FFFFH 256 MBytes 6000 0000H 6000 1FFFH 8 kBytes Not used External memory interface register 7000 0000H 7FFF FFFFH 256 MBytes 7000 0000H 7000 003FH Not used 64 Bytes PCI Bus 8000 0000H FFFF FFFFH 2 GBytes Configuration dependent Preliminary Users Manual A17812EE1V1UM00 57 MEMO 58 Chapter 5 ERTEC 400 Memory Preliminary User s Manual 17812 1 10 00 Chapter6 External Memory Interface EMIF In order to access external memory areas an External Memory Interface EMIF is incorporated in ERTEC 400 The interface contains an SDRAM memory controller for standard SDRAM and an SRAM memory controller for asynchronous memories and peripherals Both interfaces can be configured separately as active interfaces That is the data bus is driven actively to high level at the end of each access The internal pull up resistors keep the data bus actively at high level external pull up resistors are not r
54. The ARM946E S Processor System 47 3 2 Cache Structure of 946 6 48 3 3 Tightly Coupled Memories 48 3 4 Memory Protection Unit 49 3 5 Bus Interface of 946 5 49 3 6 ARM946E S Embedded Trace Macrocell ETM9 49 3 7 ARM946E S 50 Chapter 4 ERTEC 400 Bus 51 41 Multilayer AHB 51 42 2 Bac ae e ue ee 52 Chapter5 400 Memory 53 5 1 Memory Partitioning of ERTEC 400 53 5 2 Detailed Memory Map 54 5 3 Memory 56 Chapter6 External Memory Interface 59 6 1 Address Assignment of EMIF Registers 61 6 2 Detailed EMIF Register lt 61 6 3 Asynchronous Access Timing
55. Timer Register Description Figure 15 11 F Timer Counter Value Register F Counter Val 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value F Cnt Val 4000 2700H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F Cnt Val Bit position Function F Cnt Val 31 0 pong This register contains the current value of the F timer s counter Figure 15 12 F Timer Counter Reset Register F Counter Res 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 F Cnt Res Bit position Bit name Function Reserved Write arbitrary data F Cnt Res Reset value for F timer a reset of the F timer s counter is only performed if F Cnt Res the pattern 55AAH is written to the lower 16 bits of the counter reset register Consequently an F timer reset could also be performed with a 16 bit write access 166 Preliminary User s Manual 17812 1 10 00 Chapter 16 Watchdog Timers Two watchdog timers are integrated in ERTEC 400 The watchdog timers are intended for stand alone monitoring of processes Like the processor clock their working clock of 50 MHz is derived from the PLL Figure 16 1 shows a simplified block diagram of the watchdog timers Figure 16 1 Watchdog Timer Block Diagram CLK_50 Watchdog Timer 0 Watchdog Timer 1 WDOUT1_N to reset controller WDOG 0 WDOG1 gt WDOUTO to FIQO input of ICU and GPIO15
56. UARTECR1 2 Registers 7 6 5 4 3 2 1 0 Address Initial value 4000 2404H 00H Bit position Bit name Function Reserved undefined when read OE Overrun error is detected when the FIFO is full and a new character is received No overrun error detected initial value Overrun error detected BE A break error is detected when the received data are at low for longer than a standard character with all control bits lasts No break error detected initial value Break error detected PE A parity error is detected when the parity of received character does not match the parity that is configured in the EPS bit No parity error detected initial value Parity error detected FE A framing error is detected when the received character does not have a valid stop bit No framing error detected initial value Framing error detected UARTECR1 2 All error flags are cleared when a write access is performed to this register Note When new data are displayed the UARTDR data register must be read out first and then the UARTRSR UARTECR error register The error register is not updated until the data register is read 132 Preliminary Users Manual A17812EE1V1UMOO Chapter 12 UART1 UART2 The UART line control registers UARTLCR1 2 consist of 3 Bytes each that are distributed over the registers UARTLCR_H1 2 UARTLCR_M1 2 and UARTLCR_L1 2 Writing the UARTLCR register is complete when UARTLCR_H h
57. and activate trcd tcd Time between two SDRAM commands 0 2 AHB clocks between SDRAM commands initial value 1 AHB clock between SDRAM commands trcd tcd Reserved SDRAM bank size sdsize SDRAMbanksize bank size sdsize Sa LL 32 bit data bus initial value 16 bit data bus Asynchronous access timeout enable After the watchdog expires 256 AHB clock cycles an interrupt is triggered Setting Bit 7 to 0 deletes the interrupt request Asynchronous access timeout enable Timeout watchdog for asynchronous accesses disabled initial value Timeout watchdog for asynchronous accesses enabled Reserved Preliminary Users Manual A17812EE1V1UM00 69 Chapter6 External Memory Interface EMIF 6 3 Asynchronous Access Timing Examples The following Figures 6 7 to 6 10 illustrate the access timing for asynchronous devices like SRAM that are connected to the ERTEC 400 external memory interface The accesses that are asynchronous from the external viewpoint are internally synchronized to the 50 MHz clock signal CLK_50 that is shown in the subsequent timing diagrams for reference Below timings are based on a specific setting of the Async_Bank 3 0 Config registers and vary of course on the individual setting of these registers Figure 6 7 Write to External Device Active Data Bus 50 int A 23 0 valid address D 31 0 valid data CS_PER 3 0 _N W_SU 3 0 0
58. as P Target Bridge PCI Master Bridge Interrupt Status Register ridge as AHB Bridge AHB _ Master 0000 0000H 0000 0000H 8000 00D8H AHB Interrupt Enable Register 0000 0000H 8000 00DCH PCI Interrupt Enable Register 0000 0000H 8000 00 0 8000 00F4H not used 8000 00F8H 8000 00FCH Preliminary Users Manual A17812EE1V1UM00 SERR Generation By Software Enable Configuration From PCI 0000 0000H 0000 0000H 101 Chapter 8 PCI Interface MEMO 102 Preliminary User s Manual 17812 1 10 00 Chapter 9 Local Bus Unit LBU ERTEC 400 can also be operated from an external host processor via a local bus interface The bus system is selected using the CONFIG2 input pin CONFIG2 0 LBU bus system is active The LBU interface uses a 16 bit data bus and a 21 bit address bus The externally connected uC is always the master with respect to this interface All registers of the LBU are 16 bits wide write accesses to these registers must be 16 bit wide Table 9 1 Local Bus Interface Pin Functions Pin Name LBU_AB 20 0 Function LBU address bits Number of pins LBU_DB 15 0 LBU data bits LBU_WR_N LBU write control signal LBU_RD_N LBU read control signal LBU_BE 1 0 _N LBU SEG 1 0 LBU byte enable LBU page selection signals LBU IRQ 1 0 N LBU interrupt request signals LBU RDY N LBU CS M N
59. baud rate and the divisor are calculated according to the following formulas 50MHz BAUDDIV 1 x 16 BRx 16 This yields the following error tolerance calculation X BR BRI 100 with BRI being the ideal bit rate 128 Preliminary Users Manual A17812EE1V1UMOO Chapter 12 UART1 UART2 The following table shows the baud rate values to be set and the deviations from the standard baud rates The associated error percentages are within the baud rate tolerance range Table 12 2 Baud Rates and Tolerances for 50 MHz UART Operation Clock 115200 BAUDDIV 115740 0 47 76800 76219 0 76 57600 57870 0 47 38400 38580 0 47 19200 19171 0 15 14400 14400 9 0 006 9600 9585 9 0 15 2400 2400 15 0 006 1200 1200 077 0 006 110 110 0004 0 0003 UART1 can also be used as a BOOT medium if for example functions from an external PC are to be loaded to ERTEC 400 and executed The BOOT medium is selected by the BOOT 2 0 inputs during the active reset phase see Chapter 10 3 The BOOT loader then takes over setting of the UART1 signal pins and loading of the program code The Boot strap loader functionality is also used If the user does not utilize UART1 it can also be used as a debugging interface Preliminary Users Manual A17812EE1V1UM00 129 Chapter 12 UART1 UART2 12 1 Add
60. bits Receive data port 1 bits Receive data port 1 bits Transmit enable port 1 Carrier sense port 1 2 CRS DV P2 RX ER P1 Receive error port 1 RX ER P2 TX ERR P1 RX DV P1 Transmit error port 1 Receive data valid port 1 TX EN P3 CRS DV P3 COL P1 RX CLK P1 TX CLK P1 Collision port 1 Receive clock port 1 Transmit clock port 1 RX ER Note The alternate functions of MII pins are RMII pins therefore some pin names are identical for both config urable functions In this table I O types are listed for the MII configuration Preliminary Users Manual A17812EE1V1UM00 37 Chapter 2 Pin Functions Table 2 6 General Purpose I O Pin Functions Pin Name Function Alternate FunctionNete GPIO 31 26 General purpose signal GPIO25 General purpose signal TGEN OUT1 N 24 General purpose I O signal PLL_EXT_IN_N GPIO23 General purpose signal SCLKIN DBGACK GPIO22 General purpose signal SFRMIN TRACEPKT7 21 General purpose signal SFRMOUT TRACEPKT6 20 General purpose signal SCLKOUT TRACEPKT5 GPIO19 General purpose I O signal SSPTXD TRACEPKT4 General purpose signal SSPRXD General purpose signal CTS2_N SSPOE General purpose I O signal DSR2_N SSPCTLOE ETMEXTIN1 General purpose signal DCD2_N WDOUTO_N General purpose signal RXD2
61. cycles Determines the number of AHB clock cycles between valid address and chip select and falling edge of the read signal RD r su 3 0 Read strobe setup cycles n 0H EH 1 AHB cycles FH 16 AHB cycles initial value Read strobe duration cycles Determines the number of AHB clock cycles between falling and rising edges of the read signal RD r strobe r strobe 5 0 Read strobe duration cycles 1 AHB cycles 3FH 64 AHB cycles initial value Read strobe hold cycles Determines the number of AHB clock cycles between rising edge of the read signal RD_N and change of address and chip select r_hold 2 0 Read strobe hold cycles n 20H 6H 1 AHB cycles 7H 8 AHB cycles initial value Reserved Data bus width Defines the assumed width of the data bus for each chip select individually asize 1 0 Data bus width 8 bit data bus 16 bit data bus 32 bit data bus initial value 32 bit data bus Remark An AHB clock cycle normally has a length of 20 ns Preliminary Users Manual A17812EE1V1UM00 67 Chapter6 External Memory Interface EMIF Figure 6 6 Extended_Config Register 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res tcd reserved e reserved tcd size Bit position Bit name Function Reserved Test mode 1 Test mode 1 200 us delay after system reset
62. for ERTEC 400 internal resources LBU_CFG LBU chip select for page configuration registers LBU RD WR control selection LBU_POL_RDY Note LBU polarity selection for LBU_RDY_N pin Preliminary Users Manual A17812EE1V1UM00 Local bus interface pins are alternatively used as PCI pins in this table the I O type is listed for the local bus function 35 Pin NameNote SMI MDC Chapter 2 Pin Functions Table 2 4 RMI Interface Pin Functions Function SMI clock Alternate FunctionNete SMI MDC SMI MDIO SMI input output SMI MDIO RES TXD P0 1 0 Reset PHY Transmit Data Port 0 bits RES PHY N TXD 0 1 0 RXD_PO 1 0 Receive Data Port 0 bits RXD_PO 1 0 TX_EN_PO Transmit Enable Port 0 TX_EN_PO CRS DV PO Carrier Sense Data Valid Port 0 CRS PO RX ER PO TXD 1 1 0 Receive Error Port 0 Transmit Data Port 1 bits ER PO TXD P0 3 2 RXD 1 1 0 Receive Data Port 1 bits RXD 3 2 TX EN P1 CRS DV P1 Transmit Enable Port 1 Carrier Sense Data Valid Port 1 TX ERR RX DV PO RX ER P1 TXD P2 1 0 RXD 2 1 0 Receive Error Port 1 Transmit Data Port 2 bits Receive Data Port 2 bits COL PO TXD P1 1 0 RXD 1 1 0 TX EN P2 Transmit Enable Port 2 TX EN P1 CRS DV P2 RX ER P2 TXD P3 1 0 Carrier Sense Data Valid Port 2 Receive Error Port 2 Transmit Data Port 3 bits CRS P
63. initial value 1p Even parity selected PEN Enables or disables parity checking and generation Parity checking generation enable bit Parity checking generation disabled initial value Parity checking generation enabled BRK Selects if a low level is sent continuously at the transmit output 0080 Do not send break initial value Send break continuous low level Figure 12 5 UARTLCR M1 2 Register 7 6 5 4 3 2 1 0 Address Initial value BAUD DIVMS 4000 230CH 00H 4000 240CH 00H Bit position Function BAUD BAUD DIVMS 7 0 DIVMS Higher byte of 16 bit wide baud rate divisor 134 Preliminary Users Manual A17812EE1V1UMOO Chapter 12 UART1 UART2 Figure 12 6 UARTLCR_L1 2 Register 7 6 5 4 3 2 1 0 Address Initial value BAUD DIVLS 4000 2310H 00H 4000 2410H 00H BAUD BAUD DIVLS 7 0 DIVLS Lower byte of 16 bit wide baud rate divisor Note The baud rate divisor is calculated according to the following formula 50MAz BAUDDIVLS 16 Zero is not a valid divisor this case sending or receiving is not possible Figure 12 7 UARTCR1 2 Registers 1 2 7 6 5 4 3 2 1 0 Address Initial value 4000 2414H 00H Bit position Bit name Function LBE Activates loop back mode for testing purposes Loop back mode enable bit Ob Loop back mode disabled initial value 1p Loop back mode enabled RTIE Enables receive timeout interrupt enable RTIE Receive timeou
64. integrated in ERTEC 400 They can be used for internal monitoring of diverse software routines Each timer has an interrupt output that is connected to the IRQ interrupt controller of the ARM946E S CPU Access to the timer registers is always 32 bits in width Both timers have the following functionality 32 bit count register Input clock can be switched to 50 MHz clock default setting 8 bit prescaler per timer can be assigned separately Down counting Load reload function Start stop and continue functions Interrupt when counter state 0 is reached Count register can be read write accessed Figure 15 1 shows a simplified block diagram of Timers 0 and 1 Figure 15 1 Simplified Block Diagram of Timers 0 and 1 CLK 50 Prescaler 0 gt IRQO Prescaler 1 Timer 1 IRQ1 Control Status Preliminary User s Manual A17812EE1V1UMO00 155 Chapter 15 ERTEC 400 Timers 15 1 1 Operation Mode of Timers Both timers are deactivated after a reset The timers are enabled by setting the Run xStop bit in the status control register of the respective timer The timer then counts downwards from its loaded 32 bit starting value When the timer value reaches 0 a timer interrupt is generated The interrupt can then be evaluated by the IRQ interrupt controller The interrupt generated by Timer 0 is connected to the IRQO input of the IRQ interrupt controller the interrupt from Timer 1 is connected
65. is software configurable in the SSPCRO register Furthermore the SPI interface has the following features Separate send and receive FIFOs for 8 entries with 16 bit data width Data frame sizes of 4 to 16 bits can be selected in steps of 1 bit e Master and slave mode operation Bitrate from 769 Hz to 25 MHz in master mode Maximum bit rate of 4 16 MHz in slave mode Preliminary User s Manual A17812EE1V1UMOO 141 Chapter 13 Synchronous Serial Interface SPI Figure 13 1 Block Diagram of SPI Interface TxFIFO 16 x 8 bit RxFIFO 16 x 8 bit SSP TX INTR AMBA bus 4 5 interface Transmit receive logic APB Clock CLK 50 Tx Rx SSP TX INTR interrupt parameters SSP RX INTR Logic Register Clock SSP ROR INTR block prescaler Divided Clock Internal Reset EE SSP INTR SSP ROR INTR The SPI interface talks to the rest of ERTEC 400 via the APB bus and via two interrupt lines that are connected to the IRQ interrupt controller of the ARM946E S CPU these are SSP INTR SPI group interrupt wired to IRQ10 SSP ROR INTR SPI receive overrun error interrupt wired to IRQ11 For the synchronous clock output of the SPI interface the SPI has an internal clock divider Clock division is performed in two steps and must be programmed in two registers The prescaler is configured in the SSPCPSR register and the serial clock
66. memory inter face 65 PER 3 0 External memory inter face CS PER 3 0 External memory inter face CS PER 3 0 4000 0000H 4FFF FFFFH 5000 0000H 5FFF FFFFH 6000 0000H 6FFF FFFFH 7000 0000H 7FFF FFFFH 8000 0000H FFFF FFFFH AHB to APB bridge Not used AHB to APB bridge Interrupt controller Not used Not used Internal SRAM Internal SRAM Internal SRAM External memory interface registers External memory Not used interface registers PCI PCI Not used Preliminary User s Manual A17812EE1V1UMOO0 53 Chapter 5 ERTEC 400 Memory 5 2 Detailed Memory Map Description Table 5 2 below presents a more detailed description of the memory segments Memories in address ranges that are handled by external chip select signals are mirrored over the complete address range of the respective chip select However mirrored segments should not be used for addressing to ensure compatibility in case of future memory expansions When a locked or D cache and D TCM are used they can only be addressed by the ARM946E S and not by PCI or IRT When the is used it cross fades the first 4 kBytes addresses 0000 0000 to 0000 OFFFH of the memory area The D TCM memory can be positioned flexibly in the address space of the ARM946E S with the Tightly Coupled Memory Region register of the CP15 system control coprocessor Table 5 2 Detailed Description of Memory Segment
67. rate parameter SCR is configured in the SSPCRO register The resulting frequency is calculated according to the assigned SPI registers Based on the settings made in the respective fields of these registers the output clock frequency is calculated as follows SMH 0 SCLKOUT CpSDRVx 1 SCR The SPI parameters can be set to the following values CPSDRV from 2 to 254 SCR from 0 to 255 This results in an overall frequency range of 769 Hz for CPSDRV 254 SCR 255 25 MHz for CPSDRV 2 SCR 0 The SPI interface can also be used as a BOOT medium if for example functions from a serial EEPROM are to be loaded to ERTEC 400 and executed The BOOT medium is selected by the BOOT 2 0 inputs during the active reset phase see Chapter 10 2 The BOOT loader then takes over setting of the SPI signal pins and loading of the program code For BOOT mode with SPI interface the pin GPIO22 is used as a chip select signal 142 Preliminary Users Manual A17812EE1V1UMOO0 13 1 Address Assignment of SPI Registers Chapter 13 Synchronous Serial Interface SPI The SPI registers are 16 bits in width For meaningful read write accesses to the SPI registers 16 bit accesses are required However a byte by byte write operation is not intercepted by the hardware Address 4000 2200H Table 13 2 Address Assignment of SPI Registers Register Name SSPCRO Initial value Description SPI control register 0 4000 2204H SSPCR1 SPI contro
68. register for both prescalers 4000 2018H TIMO 0000 0000H Timer 0 value register 4000 201CH TIM1 0000 0000H Timer 1 value register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits 15 1 6 Detailed Description of Timer 0 1 Registers Figure 15 2 Control Status Register 0 CTRL STATO 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2000H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 Relo reserved Sta res ad Load RUN tus xStop Mode Bit position Bit name Function Reserved Status Timer 0 status indication Timer 0 status indication Status Timer 0 has not expired initial value Timer 0 has expired Note Note This bit can only be read as 1 when the Run xStop bit is set to 1p Reserved Preliminary Users Manual A17812EE1V1UM00 157 Chapter 15 ERTEC 400 Timers Figure 15 2 Control Status Register 0 CTRL_STATO 2 2 Bit position Bit name Function Reload Mode Timer 0 reload mode selectionN te Reload Mode Timer 0 reload mode selection Timer 0 stops at value 0000 0000h initial value Reload Mode Timer 0 is loaded with the reload register value when the timer value is 0000 0000h and the timer continues to run Note If Timers 0 and 1 are cascaded the reload mode setting of Timer 0 is irrelevant Load Load trigger f
69. same way than the watchdog reset Again a bit is set in the reset status register RES STAT REG when the reset is triggered 19 4 PCI Bridge Reset All reset mechanisms that have been described up to now have left the PCI side of the AHB PCI bridge that is under control of the PCI clock unaffected A hardware reset of the PCI bridge can be generated using the following functions Activating hardware reset pins RES PCI N and RESET N Activating the AHB PCI software reset by setting the XRES PCI AHB SOFT bit in the reset control register RES REG The PCI bridge side that is clocked with CLK PCI typically 33 66 MHz is reset by the RES PCI N input The current state of RES PCI N can be read in the reset control register RES REG The PCI bridge side that is clocked with CLK 50MHz is reset by the XRES SOFT and XRES PCI SOFT software resets the watchdog reset and the normal reset via RESET In order to ensure a defined state of the PCI bridge through the reset sources indicated above you must make sure that both sides of the PCI bridge are reset in the sequence shown above A hardware reset of the PCI bridge clears all bridge and configuration registers To prevent the PCI registers from being cleared a warm reset is possible for the PCI bridge This requires that the PCI RESREQ bit is set in the PCI RES register The PCI bridge termi nates all transactions at this moment and issues
70. status indication SSP_RX_INTR not active initial value SSP_RX_INTR active With any write access to this register the SPI receive FIFO overrun interrupt SSP_ROR_INTR is deleted without checking whether data are currently being written Preliminary Users Manual A17812EE1V1UMOO 149 Chapter 13 Synchronous Serial Interface SPI 13 3 GPIO Register Initialization for SPI Usage Due to the fact that all SPI pins are shared with GPIO pins on ERTEC 400 the GPIO registers need to be initialized properly before the SPI on ERTEC 400 can be used Below an example are given for a simple three wire SPI connection to an external serial Flash memory as it iis typically used for boot purposes Note that in the specific case of a serial Flash for boot purposes two extra GPIOs are used in order to identify the type of external memory and to control the chip select signal of the serial Flash These two GPIOs are not directly involved in the SPI communication Table 13 3 GPIO Register Initialization Example for External Serial Flash Memory SPI pin function SSPRXD GPIO18 function 1 SSPTXD GPIO19 function 1 Realized with SCLKOUT 20 function 1 GPIO PORT MODE HNote XXXX XXXX XXXX 01 0101 GPIO_PORT_ MODE LNete XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXXp GPIO IOCTRLNete XXXO 01 XXXX XXXXp Chip select GPIO22
71. the physically implemented size For example for the watchdog timers 28 Bytes are physically implemented The next higher power of two is 32 Bytes and thus the watchdog registers are mirrored every 32 Bytes over a 256 Byte range Accesses to the gaps in this address area do not activate the bus monitoring circuitry that is described in Chapter 20 1 read and write accesses to these addresses result in undefined data IRT registers and Communication SRAM may only be accessed at the first 2 MBytes of memory segment 1 Accesses to the gaps in this address area do not activate the bus monitoring circuitry that is described in Chapter 20 1 read and write accesses to these addresses result in undefined data These 2 MBytes are mirrored every 8 MByte over the complete 256 MByte range of segment 1 Preliminary Users Manual A17812EE1V1UM00 55 Chapter 5 ERTEC 400 Memory 5 3 Memory Map Example In this chapter a memory map example for a stripped down memory system consisting of 64 MBytes of external SDRAM and 4 MBytes of external parallel Flash memory connected to chip select 5 is shown The representation in Table 5 3 is somewhat different than in the previous tables as the last two columns illustrate the actually used address ranges to which programmers should limit their addressing operations Users are discouraged from using mirrors of the addressing ranges shown in Table 5 3 in order to avoid the risk of future software co
72. used to select the type GPIO23 Op SPl compatible Data Flash e g AT45DB011B 23 1 SPI compatible EEPROM e g AT25HP256 The serial protocols by Motorola Texas Instruments and NSC are in principle supported 10 3 Booting via UART1 The UART interface is set to a fixed baud rate of 115200 baud during the boot operation The boot loader performs the serial download of the second level loader to the internal SRAM The internal SRAM is then mapped to address 0000 0000 see Table 5 2 and the second level loader is started The second level loader downloads the user firmware to the various memory areas of the ERTEC 400 and starts the firmware once the download is complete 10 4 Booting via PCI or LBU Booting of user software via PCI must be actively performed by an external PCI master For this purpose the PCI slave macro is enabled during the boot operation in the ARM946E S This allows the user software to be loaded from the PCI master to the various memory areas of the ERTEC 400 At the end of the data transfer the PCI master sets an identification bit in the SRAM in order to communicate to the ARM processor that the download is complete An external host can perform a boot via the LBU the same way as via the PCI bus The primary difference lies in the larger memory area available for selection via the PCI interface The PCI LBU selection is made via the system control register Config REG 118 Preliminary User s Manual 178
73. 0 0000H Table 6 2 Register Name Revision Code and Status 32 bit Initial value 0000 0000H External Memory Interface Control Registers Description Contains revision code and status register information 7000 0004H Async Wait Cycle Config 32 bit 4000 0080H Configures number of wait cycles for asynchronous accesses 7000 0008H SDRAM Bank Config 32 bit 0000 20A0H Sets SDRAM bank configuration number of row and column addresses and latency 7000 000CH SDRAM Refresh Control 32 bit 0000 0190H Sets refresh rate indication for timeout 7000 0010H Async BANKO Config 32 bit FFF2H 7000 0014H Async BANK1 Config 32 bit FFF2H 7000 0018H 7000 001CH Async BANK2 Config Async BANKS Config 32 bit FFF2H FFF2H Configures access timing and data bus width for asynchronous chip selects C8 PER 3 0 individually 7000 0020H Extended Config 0303 0000H Sets miscellaneous other functionalities Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits 6 2 Detailed EMIF Register Description 31 30 29 28 27 26 25 24 23 22 21 Figure 6 1 19 18 17 Revision Code and Status Register 16 Address Initial value 15 14 13 12 11 10 9 8 7 Major Revision 7 0 Bit position 31 16 Bit name Reserved Major Revision
74. 0 0000h initial value Timer 1 is loaded with the reload register value when the timer value is 0000 0000h and the timer continues to run Preliminary Users Manual A17812EE1V1UM00 159 Chapter 15 ERTEC 400 Timers Figure 15 3 Control Status Register 1 2 2 Bit position Bit name Function Load Load trigger for Timer 1 No effect initial value Timer 1 is loaded with the reload register value Note Reload is executed irrespective of the Run xStop bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer a 0 1 edge is not needed Run xStop Starts and stops the counter in Timer 1 Run xStop Run xStop Timer 1 start stop Timer 1 is stopped initial value Timer 1 is running 160 Preliminary User s Manual 17812 1 10 00 Chapter 15 400 Timers Figure 15 4 Reload Register for Timer 0 RELDO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reload 31 0 This register holds the 32 bit reload value for Timer Figure 15 5 Reload Register for Timer 1 RELD1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reload 31 0 This register holds the 32 bit reload value for Timer 1 Preliminary Users M
75. 00 256 kBytes LBU_AB 0000 0000 00 00 1 XXXX XXXXp 0000 0000 512 kBytes LBU_AB 0000 0000 00 01 XXXX XXXXp 0000 0000 1 MByte LBU_AB 0000 0000 00 1X XXXXp XXXX XXXXp 0000 0000 2 MBytes LBU AB Note Bit numbers in the table refer to the complete 32 bit address that is formed by concatenating LBU Pn and LBU Pn L registers X Remark stands for don t care The largest of all configured pages determines the number of address lines that have to be connected to the LBU In Table 9 2 above the largest page is 2 Mbyte and the most significant bit that is set to 1p is Bit 21 In this case the number of required address lines is calculated from Amax 21 1 20 Therefore address lines LBU_AB 20 0 are required This addressing mechanism results in a mirroring of the specified page size in the total segment Preliminary Users Manual A17812EE1V1UM00 105 Chapter 9 Local Bus Unit LBU 9 2 Page Offset Setting The page offset of each page is set in the LBU Pn OF H and LBU Pn OF L registers n 0 to 3 Bit 7 0 of LBU Pn OF L are hardwired to Op Together the two page offset registers yield a 32 bit address register The register is evaluated in such a way that the offset is evaluated only down to the most significant bit of the associated page range register that is set to 15 These bits are then put on the AHB bus as the upper part o
76. 001 STROBE 5 0 00 0011 i HOLD 2 0 2 010 Figure 6 8 Read from External Device Active Data Bus CLK 50 int 23 0 valid address valid data timning determihed by ext rnal device D 31 0 CS PER 3 0 N R U 3 0 0010 R_STROBE 5 0 00 0004 i R HOLD 0 0114 lt 3 gt lt gt lt gt 70 Preliminary User s Manual 17812 1 10 00 Chapter 6 External Memory Interface Figure 6 9 Write to External Device Using RDY PER Active Data Bus CLK 50 int 23 0 valid address D 31 0 valid data CS PER 3 0 N W_SU 3 0 0001 W STROBEj5 0 00 001 max 3 x To so iW HOLDQ2 0 001 RDY PER N Figure 6 10 32 bit Write to External 8 bit Device Active Data Bus CLK 50 int A 23 0 valid address valid address valid address valid address D 7 0 least significant byte most significant byte CS_PER 3 0 _N w_HoLD 2 0 o W_su 3 0 W 5 0 W HOLD 0 0 Preliminary Users Manual A17812EE1V1UM00 71 Chapter6 External Memory Interface EMIF 6 4 External Memory Connection Example Figure 6 11 shows an example for a memory system consisting of two external SDRAMs with 16M x 16 bit organization and an additional parallel boot Flash memory of 2M x 16 bit In a typical application the code is copied
77. 1 A 19 0 Host Chapter 9 Local Bus Unit LBU A20 A21 Example for LBU Address Line Connection LBU_AB 19 0 LBU_SEGO LBU_SEG1 LBU_AB20 ERTEC 400 In order to program a setting according to Table 9 4 the LBU registers must be initialized as shown in Table 9 5 Table 9 5 LBU Register Initialization Example Register n 0 n 1 n 2 n 3 LBU_Pn_RG_L 0000H 0000H 0000H 4000H LBU Pn RG 0010H 0002H 0002H 0000H LBU Pn OF L LBU Pn OF H 108 0000H 2000H Preliminary Users Manual A17812EE1V1UMOO 0000H 1010H 0000H 3000H 0000H 4000H Chapter 9 Local Bus Unit LBU 9 4 Page Control Setting The user can program the page control register to set the type of access to the relevant page Certain areas of ERTEC 400 must be accessed 32 bit wide in order to ensure data consistency For other areas an 8 bit or 16 bit data access is permitted or even required Table 9 6 lists the areas where 32 bit accesses are allowed respectively obligatory Table 9 6 32 bit Accesses in Various Address Ranges other access than 32 bit allowed ERTEC 400 address range 32 bit access required System control registers Timer 0 1 F counter Watchdog IRT register SDRAM User RAM Communication SRAM Remaining APB I O UARTs SPI GPIO A setting is made in the paging control registers to indicate whether the relevant page area is address
78. 1 RX ER P1 TXD P1 3 2 RXD 1 0 TX EN P3 Receive Data Port 3 bits Transmit Enable Port 3 RXD P1 3 2 TX ERR P1 CRS DV Carrier Sense Data Valid Port 3 RX DV P1 RX ER P3 Receive Error Port 3 COL P1 Note The alternate functions of RMII pins are MII pins therefore some pin names are identical for both config urable functions In this table I O types are listed for the RMII configuration 36 Preliminary Users Manual A17812EE1V1UMOO Pin NameNote SMI MDC Chapter 2 Pin Functions Table 2 5 Interface Pin Functions Function Serial management interface clock Alternate FunctionMete 5 MDC SMI MDIO Serial management interface data input output SMI MDIO RES PHY N TXD 3 2 Reset signal to PHYs Transmit data port O bits RES PHY N TXD P1 1 0 TXD P0 1 0 Transmit data port O bits TXD PO 1 0 RXD PO 3 2 Receive data port 0 bits RXD_P1 1 0 RXD PO0 1 0 Receive data port 0 bits RXD PO 1 0 TX EN CRS PO Transmit enable port 0 Carrier sense port 0 TX EN PO CRS DV PO RX ER PO Receive error port 0 RX_ER_PO TX_ERR_PO RX_DV_PO Transmit error port 0 Receive data valid port 0 TX_EN_P1 CRS_DV_P1 COL PO Collision port 0 RX ER P1 RX CLK PO TX CLK PO Receive clock port 0 Transmit clock port 0 Transmit data port 1 bits Transmit data port 1
79. 11 JTAG and Debug Interface Pin Functions Pin Name Function Alternate FunctionN te TRST N JTAG reset signal JTAG clock signal JTAG data input signal JTAG test mode select signal TDO JTAG data output signal DBGREQ Debug request signal DBGACK Debug acknowledge signal GPIO23 SCLKIN TAP SEL TAP controller select signal Note The DBGACK pin is alternatively used as GPIO or SPI pin the function is selected with the GPIO PORT MODE H register In this table the I O type is listed for the DBGACK function 40 Preliminary Users Manual A17812EE1V1UMOO Pin Name TRACEPKT7 Table 2 12 Trace Port Pin Functions VoNote Chapter 2 Pin Functions Function Trace packet bit Alternate FunctionNote GPIO22 SFRMIN TRACEPKT6 Trace packet bit GPIO21 SFRMOUT TRACEPKT5 Trace packet bit GPIO20 SCLKOUT TRACEPKT4 Trace packet bit GPIO19 SSPTXD Trace packet bit GPIO11 DSR1_N TRACEPKT2 Trace packet bit GPIO10 DCD1 TRACEPKT1 Trace packet bit GPIO9 RXD1 TRACEPKTO PIPESTA 2 0 Trace packet bit CPU pipeline status GPIOS TXD1 O O O O CO O TRACESYNC ETMEXTIN1 ETMEXTOUT Trace sync signal External input to the ETM GPIO16 DSR2 N SSPCTLOE GPIO12 CTS1 N Output signal from the ETM Note Several trace port pins are alternatively used as GPIO UART or SPI pins the function is selec
80. 12 1 10 00 Chapter 11 General Purpose I O GPIO A maximum of 32 general purpose inputs outputs is available in ERTEC 400 After a reset these are set as GPIO inputs GPIO 31 24 and GPIO 7 0 are always available as I O because no additional functions can be assigned GPIO 23 8 are shared with other interfaces and functions like watchdog F counter UARTs SPI or the ETM Depending on the internal circuitry the GPIOs may have different current drive capabilities ERTEC 400 users drives with 6 mA or 9 mA capability the relation between GPIO pin number and drive capability is summarized in Table 11 1 Table 11 1 GPIO Pin and Related Drive Capabiliy GPIO pin number Drive capability GPIO 31 23 GPIO 18 12 6 mA GPIO 22 19 GPIO 11 0 9 mA Input values are stored in the GPIO IN register output values must be written to the GPIO OUT register The direction of the I O can be programmed bit by bit in the GPIO IOCTRL register The special I O function selection can be programmed in the GPIO PORT MODE L and GPIO PORT MODE H registers and the direction input or output in the GPIO IOCTRL register GPIO 1 0 and GPIO 31 30 can also be used as external interrupt inputs They are connected to the IRQ interrupt controller of the ARM946E S An interrupt can be generated only with an active High input level rising edge or falling edge for parameter assignment refer to Chapter 7 9 The following Figure 11 1 shows the struc
81. 17 System Control Registers Figure 17 20 AHB Master Lock Control Register M_LOCK_CTRL 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 20 19 18 17 16 Address Initial value 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name R W Function Reserved M_LOCK_CTRL M_LOCK_CTRL Enables AHB master bus locking for each AHB master Setting AHB master bus locking selection AHB master bus locking disabled for IRT initial value AHB master bus locking enabled for IRT AHB master bus locking disabled for PCI LBU initial value AHB master bus locking enabled for PCI LBU AHB master bus locking disabled for ARM946E S initial value AHB master bus locking enabled for ARM946E S Preliminary Users Manual A17812EE1V1UM00 191 Chapter 17 System Control Registers Figure 17 21 ARM9 Control Register ARM9_CTRL 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2650H 0000 1939H 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSOPT Bit position Bit name Function 31 14 Reserved BIG ENDIAN Indicates whether the processor is running in big endian mode Processor is running in little Endian mode initial value Processor is running in big Endian mode DisableGateTheClk Determines if ARM9 CPU clock runs freely or not DisableGateTheClk CPU clock run mode DisableGale ARM9 processor clock is paused by a Wait TheClk for Interrupt 9 proces
82. 3 Address Assignment of PCI Registers 2 2 Register Name Address 8000 0080H 8000 0084H Bit 31 24 Max_Lat Bit 23 16 Min_Gnt Bit 15 8 Bit 7 0 PCI Arbiter Config Register INT Pin Reserved 32 bit Initial value 0000 0000H 0000 0000H 8000 0088H PM Capability Rese rved 0002 0000H 8000 008CH Class Code Revision ID 0000 0000H 8000 0090H AHB Base Address RegisterO 0000 0001H 8000 0094H AHB Base Address Register1 0000 0000H 8000 0098H 8000 009CH AHB Base Address Register2 AHB Base Address Register3 0000 0000H 0000 0000H 8000 00A0H AHB Base Address Register4 0000 0000H 8000 00A4H AHB Base Address Mask RegisterO BFFF 0001H 8000 00A8H AHB Base Address Mask Register1 3F00 0007H 8000 00ACH AHB Base Address Mask Register2 0000 0000H 8000 00BOH 8000 00B4H AHB Base Address Mask Register3 AHB Base Address Mask Register4 0000 0000H 0000 0000H 8000 00B8H Reserved 8000 00BCH 8000 00COH Reserved AHB Base Address Translation Register2 0000 0000H 8000 00C4H AHB Base Address Translation Register3 0000 0000H 8000 00C8H 8000 00CCH AHB Base Address Translation Register4 AHB Status Register AHB Function Register 0000 0000H 0000 0000H 8000 00D0H 8000 00D4H Wait States Wait States Wait States B Wait States Bridge
83. 400 uPD80232 RAS_SDRAM_N BE3_DQM3_N CS_SDRAM_N CLK_SDRAM WE SDRAM N BEO DOMO BE2 DQN2 eraereeneogr 2295229 22 222z222 2 A A A AB A A A A A A A A A A A A2 A2 228 2R 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 22 72 Preliminary User s Manual 17812 1 10 00 Chapter 7 Interrupt Controller The interrupt controller ICU on ERTEC 400 supports the FIQ and IRQ interrupt levels of the ARM946E S processor An interrupt controller with 8 interrupt inputs is implemented for FIQ Six FIQ interrupt inputs are assigned to internal peripherals of the ERTEC 400 and two interrupt inputs are available for external events Table 7 1 summarizes the possible FIQ interrupt sources Function Block Watchdog Table 7 1 Interrupt Sources Signal name Default setting Rising edge Comment APB bus Rising edge Access to a non existing address at the APB bus Note 1 Multilayer AHB bus Rising edge Access to a non existing address at the AHB bus Note 1 PLL Status Registe
84. 5 14 13 12 11 10 9 8 3 0 Bit position Bit name Function Reserved IRCLVEC 3 0 Writing an IRQ interrupt vector number to these bits clears the respective request the interrupt request register IRREG IRCLVEC IRCLVEC 3 0 IRQ Interrupt vector number to be cleared clears IRQO in interrupt request register IRREG clears IRQ15 in interrupt request register IRREG Figure 7 9 MASKALL Mask All IRQ Interrupt Request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAS KALL Bit position Bit name Function Reserved MASKALL Masks all pending IRQ interrupt requests independent of their individual mask bit setting in MASKREG register MASKALL IRQ interrupt request masking MASKALL Enable all IRQ interrupt requests that are not individually masked in MASKREG Mask all IRQ interrupt requests independent of their individual mask bit setting in MASKREG register ini tial value 86 Preliminary Users Manual A17812EE1V1UMOO Chapter 7 Interrupt Controller Figure 7 10 IRQEND End of IRQ Interrupt Signaling Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value don t care 5000 0024H undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 don t care Don t care 31 0 W A write to this register indicates the completion of the interrupt service routine associated with the cu
85. 600H 4000 26FFH 256 Bytes 256 Bytes 32 Bytes physicalNete 1 164 Bytes physical General register blockNote 1 F Counter 4000 2700H 4000 27FFH 256 Bytes 8 Bytes physicalNote 1 Not used Interrupt controller 54 4000 2800H 4FFF FFFFH 5000 0000H 5FFF FFFFH 256 MBytes ARM interrupt controller 128 Bytes physicalNote 1 Preliminary Users Manual A17812EE1V1UMOO Segment Chapter 5 ERTEC 400 Memory Table 5 2 Detailed Description of Memory Segments 2 2 Contents Address range Comment Mirror area of internal SRAM Int SRAM 6000 0000 6FFF FFFFH 256 MByt mema g kBytes physicalNote 1 Notes 1 Control registers for external memory interface 64 Bytes physicalNote 1 External memory 7000 OOOOH 7FFF FFFFH 256 MBytes interface register Access from AHB to area Maximum of 4 out of 5 regions 64 kBytes to internal registers 16 MBytes to PCI configuration registers in other PCI devices up to 1GByte prefetchable PCI PCI Bus 8000 0000H FFFF FFFFH 2 GBytes memory up to 1GByte non prefetchable PCI memory upto 1GByte PCI I O Note Details can be found in the related AHB to PCI bridge document see page 6 Memories respectively register sets are mirrored over the complete partial segment size the address distance of the mirrored blocks corresponds to an integer power of two that is greater or equal to
86. 7 Interrupt Controller Figure 7 5 FIQ2SREG Interrupt Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0010H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIQ2S reserved ENA reserved FIQ2SREG BLE Bit position Bit name Function Reserved FIQ2SENABLE Enables or disables the re routing of an IRQ interrupt to FIQ7 routi hani FIQ2SENABLE FIQ2SENABLE Interrupt re routing mechanism enable Ob Interrupt re routing to FIQ7 disabled initial value 1p Interrupt re routing to FIQ7 enabled Reserved FIQ2SREG 3 0 Declaration of an IRQ interrupt as FIQ input FIQ7 on FIQ interrupt controller FIQ2SREG 3 0 Interrupt number selection FIQ2SREG IRQO interrupt request can be re routed to FIQ7 0000 ane initial value IRQ15 interrupt request can be re routed to FIQ7 Preliminary Users Manual A17812EE1V1UM00 83 Chapter 7 Interrupt Controller Figure 7 6 IRQACK IRQ Interrupt Acknowledge Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0014H FFFF FFFFH 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 Vector ID IRVEC Bit position Bit name Function Vector ID 27 0 Differentiates valid IRQ interrupt vectors from the default IRQ vector Vector ID VectorID 27 0 IRQ interrupt vector identification 000 0000 Valid IRQ interrupt vector pending FFF FFFFH Default interrupt vector initial value
87. 93 MEMO 94 Chapter 7 Interrupt Controller Preliminary User s Manual 17812 1 10 00 Chapter 8 PCI Interface The AHB PCI bridge of Fujitsu Siemens is used as the PCI interface 2 GBytes segment starting at address 8000 0000 offset 2 GBytes is visible from the perspective of the AHB bus see also section 4 1 The configuration area of the PCI macro is addressed here Mapping of addresses of the AHB bus to the address area of the PCI bus can be set in the configuration area For a detailed descrip tion of the PCI bridge refer to the documents listed on page 6 ERTEC 400 can be configured to use a PCI bus interface or a local bus interface for connection of an external host uC the bus system is selected using the CONFIG2 input CONFIG2 1 PCI bus system is active The 32 bit PCI interface operates at a maximum frequency of 66 MHz and corresponds to the PCI specification R2 2 The following signal pins are available for the PCI interface on ERTEC 400 Table 8 1 PCI Interface Pin Functions Pin Name Function Number of pins AD 31 0 PCI address data bits IDSEL PCI initialization device select PCI byte enable PCI power management PCI request GNT N PCI grant CLK PCI PCI clock RES PCI N PCI reset INTA PCI INTA INTB N PCI INTB N M66EN PCI clock selection PCI parity PCI system error STOP N PCI parity error PCI stop DEVS
88. A18 GPIO11 DSR1 N TRACEPKTS3 W2 D9 AA19 GPIO10 DCD1 N TRACEPKT2 WA D12 AA20 GPIOS TXD1 TRACEPKTO W5 D25 21 PIPESTA2 W6 CS_PER2_N AA22 PIPESTA1 Preliminary Users Manual A17812EE1V1UM00 25 Chapter 1 Introduction Table 1 1 Pin Configuration of ERTEC 400 5 5 TUM Pin Name Sear Pin Name AB2 D14 AB12 TAP_SEL AB3 VDD IO AB13 GND IO AB4 D27 AB14 GPIO16 DSR2 N SSPCTLOE ETMEXTIN 1 ABS D29 AB15 VDD IO AB6 D31 AB16 TRACECLK AB7 VDD IO AB17 GPIO21 SFRMOUT TRACEPKT6 AB8 CS PERO N AB18 GPIO19 SSPTXD TRACEPKT4 AB9 RD N AB19 VDD IO AB10 GPIO26 AB20 GPIO9 RXD1 TRACEPKT1 AB11 VDD IO AB21 TRACESYNC Preliminary Users Manual A17812EE1V1UMOO Chapier 1 1 5 Pin Identification A 23 0 D 31 0 WR_N RD_N CLK_SDRAM BE 3 0 _DQM 3 0 _N CS_SDRAM_N RAS_SDRAM_N CAS_SDRAM_N WE_SDRAM_N CS PER 3 0 N RDY PER N DTR N OE DRIVER N BOOT 2 0 CONFIG 4 0 GPIO 31 0 TXD 2 1 RXD 2 1 DCD 2 1 DSR 2 1 N CTS 2 1 N AD 31 0 IDSEL CBE 3 0 N PME N REQ N GNT_N RES PCI 66 Introduction Table 1 2 Pin Identification 1 2 Address bus Data bus Write strobe Read strobe Clock to SDRAM Byte enable Chip select to SDRAM Row address strobe to SDRAM Column address strobe to SDRAM RD WR SDRAM Chip select Ready signal Direction signal for external driv
89. ARM9 CTRL register ARM9 WE ARM9 WE CTRL 9 CTRL register write enable CTRL ARM9_CTRL register write disabled initial value ARM9_CTRL register write enabled Preliminary Users Manual A17812EE1V1UM00 193 Chapter 17 System Control Registers MEMO 194 Preliminary User s Manual 17812 1 10 00 Chapter 18 ERTEC 400 Clock Supply The clock system of ERTEC 400 basically consists of four clock domains that are decoupled through asynchronous transfers these are ARM946E S together with AHB bus APB bus and IRT JTAG interface PCI bus RMII MIl interfacing of Ethernet MACs 18 1 Clock Supply in ERTEC 400 The required clocks are generated in the ERTEC 400 by means of an internal PLL and or through direct clock supply The following Table 18 1 provides a detailed list of the clocks Table 18 1 Overview of ERTEC 400 Clocks Clock generation Module Frequency Name ARM946E S CLK ARM int 50 100 150 MHz selectable AHB EMIF ICU CLK 50 int CLKP A CLKP Band 50 Mpz subsequent PLL and IRT except MII RMII 50 100 int divider 50 and 100 MHz APB CLK 50 int 50 MHz PCI PCI clock CLK 0 66 MHz RX CLK RX TX clocks MII TX CLK 25 MHz MII REF CLK RMII REF CLK 50 MHz RMII F Timer F Clock F CLK 0 1 6666 MHz JTAG clock The synchronous clocks CLK 50 and CLK 100 are used primarily in ERTEC
90. ARM946E S by re routing these interrupts to the FIQ interrupt controller After reset IRQO_SP is by default re routed to the FIQ6 interrupt see Table 7 1 Figure 8 1 illustrates the PCI interrupt handling in ERTEC 400 based system Figure 8 1 PCI Interrupt Handling S SUR FERES ERTEC 400 See RE EHE ARM946E S Embedded pu 2 E E i oy T G 37 amp BL a 2 12 it SW 17 55 Ok E lex d PE ICU a IRQO HP Host PC Y IRQ1 IRT After a reset PCI signal SERR_N is only generated from the PCI bridge address parity error IRT interrupts IRQO HP and IRQ IRT ERR synchronization problems in the IRT API can be enabled according to the setting in the PCI INT CTRL register see Table 8 2 Interrupt output SERR N is a PCl synchronous signal When used the IRQO HP and IRQ ERR interrupts are synchronized to the PCI clock and kept active for the duration of one PCI clock cycle Table 8 2 PCI Interrupt Routing PCI INT CTRL INTB N Bit 1 Bit 0 IRQO HP IRQO HP IRQ ERR IRQO HP IRQO HP or IRT ERR Preliminary Users Manual A17812EE1V1UM00 97 Chapter 8 PCI Interface 8 1 2 PCI Power Management Requests to change the power state are made by the PCI host in the PM_Control_ Status register in the PCI configuration area The ARM946E S can read the requested power state in t
91. BLE LOCKENABLE Enables or disables lock mechanism LOCKENABLE Interrupt locking mechanism enable Interrupt locking disabled initial value Interrupt locking enabled Reserved LOCKPRIO LOCKPRIO 3 0 Specification of a priority for blocking interrupt requests of lower and equal priority LOCKPRIO 3 0 Blocked interrupt priority Interrupts with priority 0 or lower can be blocked initial value Interrupts with priority 15 or lower can be blocked Preliminary Users Manual A17812EE1V1UM00 81 Chapter 7 Interrupt Controller Figure 7 4 FIQ1SREG Interrupt Select Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 000CH 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1016 reserved ENA reserved FIQ1SREG BLE Bit position Bit name Function Reserved FIQ1SENABLE Enables or disables the re routing of an IRQ interrupt to FIQ6 FIQ1SENABLE FIQ1SENABLE Interrupt re routing mechanism enable 0 Interrupt re routing to FIQ6 disabled initial value Interrupt re routing to FIQ6 enabled Reserved FIQ1SREG 3 0 Declaration of an IRQ interrupt as FIQ input FIQ6 on FIQ interrupt controller FIQ1SREG 3 0 Interrupt number selection FIQISREG IRQO interrupt request can be re routed to FIQ6 initial value 1111 IRQ15 interrupt request can be re routed to FIQ6 82 Preliminary Users Manual A17812EE1V1UMOO Chapter
92. D SPI receive data input GPIO18 SSPTXD SPI transmit data output GPIO19 TRACEPKT4 SCLKOUT SPI clock output GPIO20 TRACEPKT5 SFRMOUT SPI serial frame input signal GPIO21 TRACEPKT6 SFRMIN SPI serial frame output signal GPIO22 TRACEPKT7 SCLKIN SPI clock input GPIO23 DBGACK SSPCTLOE SPI clock and serial frame output enable GPIO16 DSR2 N ETMEXTIN1 SSPOE SPI output enable GPIO17 CTS2 N Note Function and alternative functions are selected with the GPIO PORT MODE register In this table the I O types are listed for the SPI function Preliminary Users Manual A17812EE1V1UM00 39 Chapter 2 Pin Functions Table 2 9 MC_PLL Pin Functions PLL_EXT_IN_N MC_PLL input signal 24 TGEN OUT1 N MC PLL output signalNote 2 GPIO25 Notes 1 Function and alternative functions are selected with the GPIO PORT MODE register In this table the I O types are listed for the MC PLL function 2 For a PROFINET IRT application GPIO25 must be configured as TGEN OUT1 N output pin A syn chronous clock signal is then output at this pin during certification of a PROFINET IO device with IRT support this signal must be accessible from the outside Table 2 10 Clock and Reset Pin Functions Pin Name Function Alternate Function TRACECLK ETM trace or scan clock CLKP A Quartz connection CLKP B Quartz connection F CLK F CLK for F counter REF CLK Reference clock RESET N Hardware reset Table 2
93. DY 1 and incremented when HREADY 0p There are three possible reasons for the timeout a Actual timeout in the slave If HREADY is still 0 after a maximum of 255 AHB clock cycles access to the master is terminated with an error response and the timeout interrupt is activated The access to the slave continues As long as the slave does not supply HREADY 1p all other accesses to the slave must be blocked with an error response The interrupt is triggered only once If the address phase of a non IDLE access is pending in parallel to the extended data phase this access is cancelled and an IDLE address phase is output to the slave Note This behavior does not conform to the AHB specification b Too many retries in a row for the same access Access to the master is terminated with an error response and the timeout interrupt is activated Because there is no requirement that an access that has been rejected with Retry has to be repeated the next access of the master can be switched to the slave c HSPLIT is missing after a split response Access to the master is terminated with an error response and the timeout interrupt is activated The slave must continue to wait for signal HSPLIT 1p As long as the signal to the slave is missing all other accesses to the slave must be blocked with an error response According to the AHB specification once the slave outputs HSPLIT 1 access must be repeated However because access
94. E1V1UM00 123 Chapter 11 General Purpose I O GPIO Figure 11 6 GPIO_PORT_MODE_H Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 Address Initial value 6 GPIO31_ GPIO30 GPIO29 GPIO28 GPIO27 GPIO26_ GPIO25 GPIO24_ PO MO PO MO PO PO MO PO MO 14 13 11 10 9 P 15 12 8 7 6 5 4 3 2 1 0 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19_ GPIO18 GPIO17 GPIO16_ PO MO PO MO PO MO 4000 2510H 0000 0000H Bit position Bit name Function 1 PO MO Selects one of max four different functions for pin GPIO31 GPIO31 PO MO GPIO31 function selection 00 Select function 0 for pin 1 GPIO31 PO 01 Select function 1 for pin GPIO31 if available 10 Select function 2 for GPIOS1 if available 11 Select function 3 for pin GPIO31 if available GPIO16 PO MO Selects one of max four different functions for pin GPIO16 GPIO16 PO MO GPIO16 function selection 00 Select function 0 for pin GPIO16 GPIO16 PO MO 01 Select function 1 for pin GPIO16 if available Select function 2 for pin GPIO16 if available Select function 3 for pin GPIO16 if available 124 Preliminary Users Manual A17812EE1V1UMOO Chapter 11 General Purpose I O GPIO The following Table 11 3 describes the GPIO pins and their alternative functions th
95. E1V1UMOO Chapter 15 400 Timers Figure 15 6 Control Register for Prescaler 0 and 1 CTRL_PREDIV 2 2 Bit position Bit name Function Run xStop VO Starts and stops Prescaler 0 for Timer 0 Run Run xStop VO Prescaler 0 start stop xStop VO 0 Prescaler 0 is stopped initial value 1p Prescaler 0 is running Remark The current counter value of the prescalers cannot be read In addition there are no status bits for the prescalers indicating when the counter state is 0 The prescalers always run continuously in Reload mode after they have been started Figure 15 7 Reload Register for Prescaler 0 and 1 RELD PREDIV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2014H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prediv V1 Prediv VO Bit position Bit name R W Function 31 16 Reserved Prediv_V1 This register holds the 8 bit reload value for Prescaler 1 Prediv_V1 Prediv VO Q This register holds the 8 bit reload value for Prescaler 0 Preliminary Users Manual A17812EE1V1UM00 163 Chapter 15 ERTEC 400 Timers Figure 15 8 Current Timer Value Register for Timer 0 TIMO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 21 0 oR This register holds the current counter value for Timer 0 Figure 15 9 Current Timer Value Register f
96. EL N PCI device select TRDY IRDY_N PCI target ready PCI initiator ready FRAME_N cycle frame total Preliminary User s Manual A17812EE1V1UMO00 95 Chapter 8 PCI Interface 8 1 PCI Functionality The PCI functions are described in general terms in this chapter The PCI interface has the following characteristics Compliant with PCI Specification R2 2 Host functionality Master target interface Internal 32 bit AHB interface 32 bit PCI interface 3 3 V supply 5 V compatible Maximum operating frequency of 66 MHz Loading of PCI configuration registers from ARM946 processor 2 PCI interrupt outputs INTA N and INTB N Power Management Version 1 1 No PCI interrupt inputs No support of lock transfers As mentioned above the PCI interface can operate as PCI master as well as PCI target As PCI master the interface has the following capabilities The following accesses are supported Memory Read Memory Read Line Memory Read Multiple Memory Write Single Burst Memory Write and Invalidate 1 delayed instruction queue Write data FIFO with a depth of 16 Delayed read data FIFO with a depth of 16 Configuration area is loaded from the ARM946 not from an EPROM As PCI target the interface has the following capabilities 96 The following accesses are supported Memory Read Memory Read Line Memory Read Multiple Memory Write Memory Write and Invalidate Confi
97. F Timer Counter Value Register 166 F Timer Counter Reset Register F Counter Res 166 Watchdog Timer Block 167 Watchdog Timer Output Timing 2 2 168 Watchdog Control Status Register CTRL STATUS 1 2 170 Reload Register Low for Watchdog 0 RELDO 171 Reload Register High for Watchdog 0 RELDO HIGH 172 Reload Register Low for Watchdog 1 RELD1 172 Reload Register High for Watchdog 1 RELD1_ HIGH 173 Counter Register for Watchdog 0 0 2 173 Counter Register for Watchdog 1 WDOG1 sse 173 Device Identification Register ID REG sse 176 Boot Mode Pin Register BOOT REG sse 176 Config Pin Register CONFIG REG 177 Reset Control Register RES CTRL REG 1 2 sse 177 Reset Status Register RES STAT REG sess 179 PLL Status Register PLL STAT REG 1 3 seen 180 Clock Control Register CLK CTRL 182 PCI Power State Request Register PM STATE REQ 183 PCI Power State Acknowledge Regis
98. FFH Remarks 1 130 UARTIIR2 UARTICR2 Interrupt identification register read Interrupt clear register write Reserved During reset all GPIO pins are configured as input port pins Thus I O direction and alternative pin function usage have to be configured first before using the UARTs Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary Users Manual A17812EE1V1UMOO Chapter 12 UART1 UART2 12 2 Detailed UART1 2 Register Description The registers for both UARTs are identical except their address Therefore they are described only once Figure 12 2 UARTDR1 2 Data Register 7 6 5 4 3 2 1 0 Address Initial value UARTDR1 2 4000 2300H xxH 4000 2400H xxH Bit position Bit name Function UARTDR 1 2 Write access If FIFO is enabled the written data are entered in the FIFO If FIFO is disabled the written data are entered in the transmit holding register the first word of the transmit FIFO UARTDR1 2 Read access If FIFO is enabled the received data are entered in the FIFO If FIFO is disabled the received data are entered in the receive holding register the first word of the receive FIFO Note When data are received the UARTDR data register must be read out first and then the UARTRSR UARTECR error register Preliminary Users Manual A17812EE1V1UM00 131 Chapter 12 UART1 UART2 Figure 12 3 UARTRSR
99. F_CLK pin 14 1 4 Channel RMII Operation Table 14 1 shows the set of signal pins for the RMII interfaces if ERTEC 400 is configured to 4 channel RMII operation For each port there are two data lines for each direction and three control lines A com mon serial management interface SMI allows configuration of the PHY internal registers ERTEC 400 also provides common reset signal RES PHY N for all external PHYs If it is necessary to have indi vidual reset signals for each PHY RES PHY can additionally be gated with GPIO pins Preliminary User s Manual A17812EE1V1UMOO0 151 Chapter 14 External PHY Interface Table 14 1 RMII Interface Pin Functions Pin Name 1 0 Function Number of pins SMI_MDIO SMI input output 1 RES Reset PHY 1 TXD_P0 1 0 Transmit Data Port 0 bits RXD P0 1 0 Receive Data Port 0 bits TX EN PO Transmit Enable Port 0 CRS DV PO Carrier Sense Data Valid Port 0 TXD_P1 1 0 Transmit Data Port 1 bits RXD_P1 1 0 Receive Data Port 1 bits TX_EN_P1 Transmit Enable Port 1 CRS_DV_P1 Carrier Sense Data Valid Port 1 RX_ER_P1 Receive Error Port 1 TXD_P2 1 0 Transmit Data Port 2 bits RXD_P2 1 0 Receive Data Port 2 bits TX_EN_P2 Transmit Enable Port 2 CRS_DV_P2 Carrier Sense Data Valid Port 2 RX_ER_P2 Receive Error Port 2 TXD_P3 1 0 Transmit Data Port 3 bits RXD_P3 1 0 Receive Data Port 3 bits TX_EN_P3 Transmit Enable Port 3 CRS_DV_P3 Carrier Sense Data Valid Port 3 RX_ER_
100. GEREGn 0 15 Selection of IRQ trigger edge Positive edge trigger for IRQn initial value Negative edge trigger for IRQn Figure 7 21 SWIRREG Software IRQ Interrupt Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWIRREG Bit position Bit name R W Function 31 16 s Reserved SWIRREG 15 0 Generation of individual IRQ interrupts by software This register is primarily used for debugging purposes SWIRREG SWIRREGn 0 15 Generation of IRQ interrupts Do not generate interrupt request for IRQn initial value Generate interrupt request for IRQn 92 Preliminary Users Manual A17812EE1V1UMOO Chapter 7 Interrupt Controller Figure 7 22 PRIOREGO 15 IRQ Interrupt Priority Register 31 30 29 28 27 26 25 24 23 22 21 15 14 13 12 11 reserved 10 9 8 20 19 18 17 16 Address Initial value 5000 00xxH 0000 000FH 3 0 Bit position Bit name Reserved Function PRIOREG PRIOREG 3 0 PRIOREGn 3 0 Specifies priority for individual IRQ interrupt requests PRIOREGO corresponds to IRQO etc It is not allowed to assign equal priorities to more than one IRQ interrupt request IRQn interrupt request priority Assigns priority 0 highest to IRQ interrupt IRQn Assigns priority 15 lowest to IRQ interrupt IRQn initial value Preliminary Users Manual A17812EE1V1UM00
101. G_CLK pin The frequency range is between 0 and 10 MHz The boundary scan and the ICE macro cell of the ARM946E S are enabled via the JTAG interface With respect to the Ethernet ports there are two operation modes MII mode 2 Ethernet ports to 2 MII PHYs RMII mode 4 Ethernet ports to quad RMII PHY In RMII mode the Ethernet ports and the PHYs are typically operated from an external 50 MHz system clock This clock is supplied to ERTEC 400 via the REF pin Communication between the Ether net ports and the PHYs is synchronous In MII mode the two PHYs are supplied with an external 25 MHz PHY clock The clock for the Ethernet ports of the ERTEC 400 is then supplied as part of the MII signals namely the RX CLK and TX CLK clock lines Like in the RMII case the external 25 MHz clock can be used for ERTEC 400 operation via the REF CLK input The clock for the Ethernet ports is enabled disabled via the clock control register in the IRT switch Preliminary Users Manual A17812EE1V1UM00 197 Chapter 18 400 Clock Supply Figure 18 2 shows the two different Ethernet modes with their clock supply schemes Figure 18 2 Clock Supply of Ethernet Interface ERTEC400 in MII Mode Interface via MII to two 1 port PHYs ERTECA00 in RMII Mode Interface via RMII to 4 port PHY Ethernet Ethernet Ethernet Ethernet REF CLK REF CLK RX CLK PO PHYO PHY1 PHY2 PHY3 RMI
102. HB side of the AHB PCI bridge XRES PCI _AHB_SOF a 7 Reset is not active initial value XRES PCI AHB SOFT PCI AHB bridge reset control Preliminary Users Manual A17812EE1V1UM00 177 Chapter 17 System Control Registers Figure 17 4 Reset Control Register RES_CTRL_REG 2 2 Bit position Bit name Function PULSE DUR Extends the duration of a software or a watchdog reset generated by watchdog timer 1 in multiples of the AHB clock period With being the AHB clock period typically 20 ns the resulting pulse duration is given by PULSE_DUR 8x PULSE_DUR 1 Toy x TRES PULSE Reserved XRES_SOFT Allows to trigger a reset under software control This bit is not stored as the reset that is initiated by writing 1 to this bit automatically resets the bit again XRES_SOFT XRES_SOFT Software reset Do not trigger software reset initial value Trigger software reset WD RES FREI Enables disables a reset triggered by watchdog timer 1 WD RES FREI Watchdog reset enable Disable watchdog reset initial value Enable watchdog reset 178 Preliminary User s Manual A17812EE1V1UMOO Chapter 17 System Control Registers Figure 17 5 Reset Status Register RES_STAT_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 14 HW SW WD reserved RES RES RES ET ET ET Bit position Bit name Function Reserved HW_RESE
103. IF_ADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value QVZ_EMIF_ADR 4000 2638H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 9 QVZ_EMIF_ADR QVZ_EMIF_ADR 31 0 QVZ_EMIF_ADR Holds the address in case of an external memory access that caused a timeout Preliminary Users Manual A17812EE1V1UM00 187 Chapter 17 System Control Registers Figure 17 16 PCI Reset Request Register PCI RES REQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value DELAY PCI 4000 263CH FFFF 0002H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bit position Bit name Function MAX DELAY PCI MAX DELAY PCI Specifies the number of AHB clock cycles allowed to elapse without a response on the AHB PCI bridge before a timeout is triggered Reserved PCI QVZ EN Enables timeout monitoring of AHB accesses to the AHB PCI bridge PCI QVZ EN Timeout monitoring enable PCI QVZ EN 20 Timeout monitoring disabled 1 Timeout monitoring enabled initial value PCI SOFT RESREQ Requests a soft reset to the AHB PCI bridge this bit has to be reset manually PCI SOFT RESREQ PCI soft reset request Request for soft reset inactive initial value PCI SOFT RESREQ Request for soft reset active 188 Preliminary User s Manual A17812EE1V1UMOO Chapter 17 System Control Registers Figure 17 17 PCI Reset Acknowledge Register PCI RES 31 30 29 28 27 26 25 24 23 22 21
104. MHz Trace in half rate mode at an operating frequency of 150 MHz 4 8 bit trace data width selectable Trace can be restricted to selected address ranges and memory regions External Memory Interface SDRAM memory controller Adjustable 16 32 bit data bus width PC100 SDRAM compatible 50 MHz clock frequency Maximum of 256 MBytes 32 bit or 128 Mbytes 16 bit SDRAM Adjustable RAS CAS latency 2 3 for Write 1 2 for Read 2 bit bank address 1 2 4 banks via address bits A1 and AO 8 9 10 11 bit column address 13 11 2 Maximum 13 bit row address A 14 2 Asynchronous memory controller for SRAM Flash I O Adjustable 8 16 32 bit data bus width 4 chip selects with individual timing control for each chip select Default setting for boot operation timing is slow Maximum of 16 Mbytes can be addressed for each chip select Chip select CS_PERO_N can be used for boot memory Data bus width of boot ROM at C8 PERO Ni is selectable via BOOT 2 0 pins Adjustable timeout monitoring DTR N direction and OE DRIVER enable control signals for direct control of an external driver for chip select signals C8 PER 3 0 e IRT Switch 4 Fast Ethernet ports 10 100 Mbps and full duplex half duplex mode support Supports RT and IRT data traffic Autonegotiation Broadcast filter IEEE 1588 time stamping 192 kBytes of Communication SRAM Preliminary Users Manual A17812EE1V1UM00 19 20 Chapter 1 Introduction
105. MII ports 2 The number can take the integer values 0 and 1 and refers to the MII ports Remark Shared pins are not listed with all possible pin names Please check Tables 2 1 to 2 12 for possible pin names first before looking up pin characteristics in Table 2 14 Preliminary Users Manual A17812EE1V1UM00 43 Chapter 2 Pin Functions 2 3 Pin Status and Recommended Connections Table 2 15 Pin Status During Reset and Recommended Connections 1 3 Pin Name A 23 16 ypNote 1 Internal pull up down during reset Level during reset External pull up down required A 15 0 D 31 0 50 kQ pull up WR N RD N SDRAM CS_SDRAM N RAS SDRAM CAS SDRAM WE SDRAM CS PER 3 0 BE 3 0 _DQM 3 0 _N RDY_PER_N DTR_N OE DRIVER N O O O O O O O OOJOO O O O O O O O O O II TL AD 31 0 Pull upNote 2 IDSEL Pull upNote 2 CBE 3 0 _N Pull upNote 2 PME NNote 3 Pull upNote 4 REQ NNote 3 tri state Pull upNete 2 4 GNT NNote 3 Pull upNete 2 4 CLK pojNetes Pull downNete 2 5 RES PCI N Pull upNete 2 4 5 INTA_NNote 3 tri state Pull upNote 4 INTB NNote3 tri state Pull upNote 4 MeeENNote 3 PARNote 3 SERR NNote 3 Pull downNete 2 5 Pull upNote 2 4 PERR_NNote 3 Pull upNote 2
106. N R19 GPIO6 L5 BE2 DQM2 N R21 RES PHY N L18 GND Core R22 REF CLK L19 VDD Core T1 D4 121 TXD P1 1 TXD PO 3 T2 D5 L22 TXD P1 0 TXD PO 2 4 BE3_DQM3_N M1 GND IO T5 D23 M2 WE_SDRAM_N 6 GND IO M4 VDD Core 17 GND Core M5 D17 T18 GND IO M18 SMI MDC T19 GPIO7 M19 TX EN P1 TX ERR PO T21 GPIOO M21 RXD PO 1 RXD PO 1 T22 VDD IO M22 RX ER P1 COL PO U1 GND Core N1 BEO DQMO N U2 D6 24 Preliminary Users Manual A17812EE1V1UMOO Table 1 1 Chapter 1 Introduction Pin Configuration of ERTEC 400 4 5 U4 VDD Core W7 VDD Core U5 GND Core Ws VDD Core U6 VDD Core w9 28 U7 GND Core 27 DTR_N W11 AVDD GND Core CLKP B AGND GPIO12 CTS1 N ETMEXTOUT GND Core VDD Core GND Core VDD Core GPIO14 RXD2 GPIO15 DCD2 N WDOUTO N GND IO VDD Core VDD Core TDI GND Core TCK TMS DBGREQ GPIO1 GPIO18 SSPRXD GND IO VDD IO BE1_DQM1_N D10 D7 PIPESTAO D24 GPIO23 SCLKIN DBGACK VDD Core D11 CS GND IO OE_DRIVER_N GND Core D28 29 D30 GPIO30 CS_PER1_N V12 GPIO31 AA8 RDY_PER_N V13 GND IO AAQ WR_N V14 VDD Core AA10 GPIO25 TGEN OUT1 N V15 GPIO13 TXD2 AA11 GPIO24 PLL EXT IN N V16 TDO AA12 F CLK V17 GND Core AA13 CLKP A V18 VDD Core AA14 GPIO17 CTS2 N SSPOE V19 TRST AA15 RESET N V21 GPIO3 AA16 GPIO22 SFRMIN TRACEPKT7 V22 GPIO2 AA17 GPIO20 SCLKOUT TRACEPKT5 W1 D8 A
107. OUT1_N internal i generates reset Counter 0 0 Trigger Counters start Counter 1 0 WDOUTO N deleted by Run xStop Z0 Stop gt Start 168 Preliminary Users Manual A17812EE1V1UMOO Chapter 16 Watchdog Timers 16 2 Address Assignment of Watchdog Registers The watchdog registers are 32 bits in width For meaningful read write accesses to the watchdog registers 32 bit accesses are required However a byte by byte write operation is not intercepted by the hardware To prevent the watchdog registers from being written to inadvertently e g in the event of an undefined computer crash the writable watchdog registers are provided with a write protection mechanism The upper 16 bits of the registers are so called key bits In order to write a valid value in the lower 16 bits the key bits must be set to 9876 yyyyH where yyyyH is the 16 bit value to be written Address 4000 2100H Table 16 1 Address Assignment of Watchdog Registers Register Name CTRL STATUS Initial value 0000 0000H Description Control status register watchdog 4000 2104H RELDO_LOW 0000 FFFFH Reload register 0 low 4000 2108H RELDO_HIGH 0000 FFFFH Reload register 0 high 4000 210CH RELD1_LOW 0000 FFFFH Reload register 1 low 4000 2110H RELD1_HIGH 0000 FFFFH Reload register 1 high 4000 2114H WDOGO FFFF FFFFH Watchdog timer 0 counter register 4000 2118H WDOG1
108. P3 Receive Error Port 3 total 152 Preliminary Users Manual A17812EE1V1UMOO Chapter 14 External PHY Interface Figure 14 1 shows a typical connection between ERTEC 400 and four external PHYs via RMII PHY Connection via RMII Example Figure 14 1 899 1 ZHW 899 09 849 1 0199 910199 sH 6ZOld9 820199 N AHd S3M AHd olan TYHLO XL XY 7 THLO XL XY oIan THLO XL XY Z THLO XL XY 1 LAHd zezogadn 007 9313 THIO XLIXH Mod TH LO XL XH sau 4 oIan OIAW IWS OAW INS X19 Sau waxy Od H3 t E Od Ad Suo MID 3H Od N3 XL Sau z LOxel 0 THLO XL XY 00d Sau 00d 153 Preliminary Users Manual A17812EE1V1UM00 Chapter 14 External PHY Interface 14 2 2 Channel MII Operation Table 14 2 shows the set of signal pins for the MII interfaces if ERTEC 400 is configured to 2 channel MII operation For each port there are four data lines for each direction six control lines and two clocks A common serial management interface SMI allows configuration of the PHY internal registers ERTEC 400 also provides a common reset signal RES PHY N for all external PHYs If it is necessary to have individual reset signals fo
109. PCI AVDD AGND AVDD PCI AGND PCI JTAG reset JTAG clock JTAG data in JTAG test mode select JTAG data out Debug request to ARM9 Debug acknowledge Select TAP controller Quartz connection Quartz connection Reference clock input Clock for F counter HW reset Watchdog output Power supply for core 1 5 V GND for core Power supply for IO 3 3 V GND for IO Power supply for PCI 5 V Analog power Supply for PLL 1 5 V Analog GND for PLL Analog power supply for PLL in PCI I F 1 5 V Analog GND for PLL in PCI VF Chapter 1 1 6 Configuration of Functional Blocks 1 6 1 Block Diagram of ERTEC 400 Figure 1 2 Introduction Internal Block Diagram Trace 12 5 MHz External Memory Interface JTAG Debug Port REF CLK rA 1 74 k Clock 4 Reset ARM946E S Unit BS External with TAP ES v SRAM ARM 1 8 kBytes 2 E ay iv y kB Interrupt D Cache 4 kBytes og 8 tes Interface 88 Controller D TCM 4 kBytes 4 EMIF 50 100 150 MHz
110. RQ and FIQ interrupts Priorities 0 to 15 can be assigned to IRQ interrupts while priorities O to 7 can be assigned to FIQ interrupts The highest priority is O for both interrupt levels After a reset all IRQ interrupt inputs are set to priority 15 and all FIQ interrupt inputs are set to priority 7 A priority register is associated with each interrupt input PRIOREGO to PRIOREG15 are for the IRQ interrupts and FIQPRO to FIQPR7 are for the FIQ interrupts A priority must not be assigned more than once The interrupt control logic does not check for assignment of identical priorities All interrupt requests with a lower or equal priority can be blocked at any time in the IRQ priority resolver by assigning a priority in the LOCKREG register If an interrupt that is to be blocked is requested at the same time as the write access to the LOCKREG register an IRQ signal is output However the signal is revoked after two clock cycles If an acknowledgement is to be generated nonetheless the transferred interrupt vector is the default vector 74 Preliminary Users Manual A17812EE1V1UMOO Chapter 7 Interrupt Controller 7 2 Trigger Modes Edge trigger or level trigger modes are available for each interrupt input The trigger type is defined by means of the assigned bit in the TRIGREG register For the edge trigger mode setting differentiation can be made between a positive and negative edge evaluation This is set in the EDGEREG register Edge trigger with posi
111. SS STATE interrupt masking LOSS 3 Interrupt is enabled Interrupt is masked initial value INT MASK LOCK Interrupt masking for INT LOCK STATE interrupt INT_MASK_LOCK INT_LOCK_STATE interrupt masking 0 Interrupt is enabled Interrupt is masked initial value Reserved 180 Preliminary User s Manual A17812EE1V1UMOO Chapter 17 System Control Registers Figure 17 6 PLL Status Register PLL_STAT_REG 2 3 Bit position Bit name Function INT_QVZ_EMIF_STATE External memory interface timeout interrupt status This bit corresponds to bit 7 of the Extended Config register in the EMIF Note INT_QVZ_ EMIF_ eum MIF INT_QVZ_EMIF_STATE interrupt status STATE Interrupt request is not active initial value Interrupt request is active INT_QVZ_PCI_SLAVE_STATE PCI slave timeout interrupt status INT_QVZ_ INT_QVZ_PCI_ PCI SLAV SLAVE STATE INT QVZ PCI SLAVE STATE interrupt status E STATE Interrupt request is not active initial value Note Interrupt request is active INT LOSS STATE Indicates if the PLL input clock has once been lost This bit is not reset when the PLL input clock returns Once set it can only be reset by overriding it Note INT LOSS STATE Interrupt request is not active initial value Interrupt request is active INT LOCK STATE Indicates if the PLL has once been unlocked This bit is not reset when the PLL locks again Once set
112. T Indicates if the last reset event was a hardware reset Note HW_RESET Hardware reset status Last reset event was no hardware reset te Last reset event was a hardware reset initial value SW_RESET Indicates if the last reset event was a software reset Note SW_RESET Software reset status SW_RESET HW_RESET Last reset event was no software reset initial value Last reset event was a software reset WD_RESET Indicates if the last reset event was a watchdog reset triggered by watchdog timer 1 Note WD_RESET atchdog reset status Last reset event was no watchdog reset initial value D d 1 Last reset event was a watchdog reset Note Only the bit of the most recent reset event is set the other two bits are reset Preliminary Users Manual A17812EE1V1UM00 179 Chapter 17 System Control Registers Figure 17 6 PLL Status Register PLL_STAT_REG 1 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2614H 0007 0005H 15 14 13 12 11 10 9 8 7 6 Bit position Bit name Function Reserved INT MASK QVZ PCI SLAVE Interrupt masking for INT QVZ PCI SLAVE STATE interrupt INT_MASK_ INT_MASK_QVZ_ QVZ PCI PCI SLAVE INT QVZ PCI SLAVE STATE interrupt masking SLAVE Interrupt is enabled Interrupt is masked initial value INT MASK LOSS Interrupt masking for INT LOSS STATE interrupt INT_MASK_ INT MASK LOSS INT LO
113. UART 16C550 the functional differences between the PLO10 macro and a 16C550 are as follows Receive FIFO trigger level is set permanently to 8 bytes e Receive errors are stored in the FIFO Receive errors do not generate an interrupt The internal register address mapping and the register bit functions are different 1 5 Stop bits are not supported Forcing stick parity function is not supported An independent receive clock is not possible Modem signals DTR RTS and RI are not supported For a detailed description of the PLO10 macro please refer to the list of documents on page 6 Preliminary User s Manual A17812EE1V1UMOO 127 Chapter 12 UART1 UART2 Figure 12 1 below shows the structure of UART1 respectively UART2 Figure 12 1 UART1 2 Macro Block Diagram read data 10 0 10 0 TxFIFO RxFIFO 16 x 8 bit 16 x 8 bit Internal Reset Control amp status X if Transmitter Baud rate divisor Baudi6 AMBA APB APB bus C interface and Baud rate register Generator block Receiver Transmit FIFO Receive FIFO status status CLK 50 Operation clock FIFO Flags CTS1 2_N FIFO status UART INTR1 2 lt and interrupt DSR1 2 N generation DCD1 2 N Each UART has a single interrupt source that is wired to the IRQ interrupt controller see Table 7 2 UART INTR1 UART group interrupt wired to IRQ8 UART INTR2 UART2 group interrupt wired to IRQ9 The
114. _PER_N ready signal can be monitored In order to enable monitoring the Extended Wait Mode bit must be switched on in the Async BANK 0 Config to Async BANK 3 Config configuration registers If one of the four memory areas that are selected via the 5 PER 3 0 chip select outputs is addressed the memory controller of the ERTEC 400 waits for the RDY PER N input signal The monitoring duration is set in the Async Wait Cycle Config register and it is active if timeout monitoring Bit 7 is set in the Extended Config register The specified value maximum of 255 multiplied by 16 yields the monitoring time given in AHB clock cycles i e the time that the memory controller waits for the Ready signal After this time elapses an internal ready signal is generated for the memory controller and an FIQ interrupt is generated at input FIQO of the ARM946E S interrupt controller In addition the address of the incorrect access is stored in the QVZ system control register The QVZ EMIF ADR system control register is locked for subsequent address violations until it has been read The set FIQO interrupt is then removed if timeout monitoring is reset 20 4 PCI Slave Monitoring The internal HREADY signal of the PCI slave is monitored with an 8 bit wide counter i e monitoring is triggered after 256 AHB clock cycles Monitoring can be enabled or disabled in the PCI RES REQ system control register The monitoring counter is reset when HREA
115. a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up
116. alid data Preliminary Users Manual A17812EE1V1UM00 111 Chapter 9 Local Bus Unit LBU Figure 9 5 LBU Write to ERTEC 400 with Common Read Write Control Line LBU CS R LBU CS MN LBU WR N LBU AB 20 0 LBU SEG 1 0y Valid address LBU BE 1 0 N LBU RDY N LBU DB 15 0 nm Valid data m 112 Preliminary Users Manual A17812EE1V1UM00 9 6 Address Assignment of LBU Registers Chapter 9 Local Bus Unit LBU The LBU registers are 16 bit wide the registers can be written to with 16 bit accesses only The LBU page configuration registers are addressed via the LBU CS R N signal Table 9 8 summarizes the implemented registers Address 00 0000H Table 9 8 Address Assignment of LBU Registers Register Name LBU RG L Initial value Description LBU page 0 range register low 00 0002H PO LBU page 0 range register high 00 0004H LBU OF L LBU page 0 offset register low 00 0006H LBU PO OF H LBU page 0 offset register high 00 0008H CFG LBU page 0 configuration register 00 0010H L LBU page 1 range register low 00 0012H LBU P1 RG H LBU page 1 range register high 00 0014H LBU P1 OF L LBU page 1 offset register low 00 0016H LBU P1 OF H LBU page 1 offset register high 00 0018H 00 0020H LBU P1 CFG LBU P2 RGL LBU page 1 configuration register LBU page 2 range r
117. an acknowledgement with the PCI SOFT RESACK bit This state can be scanned in the PCI RES register by the ARM946E S user software All new transactions from the AHB and PCI bus are rejected with Retry This also pertains to the bridge and configuration registers on the AHB side The state is retained until the PCI SOFT RESREQ bit is deleted again All the registers indicated above can be addressed in the system control register area 200 Preliminary User s Manual A17812EE1V1UMOO Chapter 19 Reset Logic of ERTEC 400 19 5 Actions when HW Reset is Active During the active HW reset phase the states of the 3 boot pins BOOT 2 0 are latched into the BOOT_REG register and the states of the 5 config pins CONFIG 4 0 are latched into the CONFIG_REG register After the hardware reset phase these pins are available as normal EMIF func tion pins Tables 19 1 and 19 2 summarize the function of the BOOT and CONFIG pins Note that BOOT and CONFIG pins are only latched in case of a hardware reset a watchdog reset or a software reset do not have this effect Table 19 1 BOOT 2 0 Pin Functions Selected download mode Via external ROM NOR flash with 8 bit width Via external ROM NOR flash with 16 bit width Via external ROM NOR flash with 32 bit width Reserved Reserved SPI e g for use with EEPROMs with serial interface UART1 bootstrap method PCI slave LBU from external host CONFIG pin Function 50 MHz CPU c
118. anual A17812EE1V1UM00 161 Chapter 15 ERTEC 400 Timers Figure 15 6 Control Register for Prescaler 0 and 1 CTRL_PREDIV 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Reserved 4000 2010H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Run Run reserved E Stop i xStop Vt V0 Bit position Bit name Function Reserved Load V1 Load trigger for Prescaler 1 Load V1 Reload for Prescaler 1 No effect initial value Prescaler 1 is loaded with the prescaler reload Load V1 register value Note Reload is executed irrespective of the Run xStop V1 bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer a 0 1 edge is not needed Run xStop V1 Starts and stops Prescaler 1 for Timer 1 Run xStop V1 Prescaler 1 start stop Prescaler 1 is stopped initial value Prescaler 1 is running Load VO Load trigger for Prescaler 0 Load VO Reload for Prescaler 0 BEEN No effect initial value Prescaler 0 is loaded with the prescaler reload Load VO 1b n register value Reload is executed irrespective of the Run xStop VO bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer 0 1 edge is not needed 162 Preliminary User s Manual A17812E
119. as been written If one of the first two bytes is to be changed UARTLCR_H must be written at the end following the change Example Write UARTLCR_L and or UARTLCR_M then write UARTLCR_H to accept the changes Write UARTLCR_H only means write and accept UARTLCR_H bits Figure 12 4 UARTLCR_H1 2 Registers 1 2 7 6 5 4 3 2 1 0 Address Initial value 4000 2408H 00H Bit position Bit name R W Function 7 Reserved WLEN The word length indicates the number of data bits within a frame WLEN Word length 00 5 bit data initial value 01 6 bit data 10 7 bit data 11 8 bit data FEN FIFO modes for sending and receiving data are enabled or disabled If the FIFOs are disabled sending receiving is performed via 1 Byte holding registers actually the first elements of the FIFOs FIFO disable initial value 1p FIFO enable STP2 Two stop bits are appended at the end of the frame when sending The receive logic does not check the received character for two stop bits STP2 Two stop bit select Insert one stop bit initial value Insert two stop bits Preliminary Users Manual A17812EE1V1UM00 133 Chapter 12 UART1 UART2 Figure 12 4 UARTLCR_H1 2 Registers 2 2 Bit position Bit name Function EPS Selects even or odd parity for check and generation The setting of this bit is irrelevant when parity is disabled with the PEN bit Parity type selection 0 Odd parity selected
120. at are configurable with the GPIO PORT MODE L H registers Table 11 3 Alternative Functions of GPIO pins Function GPIO pin 0 2 3 1 GPIO 7 0 GPIO 7 0 GPIO8 GPIO8 TXD1 TRACEPKTONote 1 GPIO9 GPIO9 RXD1 TRACEPKT 1 Nete 1 GPIO10 GPIO10 DCD1 N TRACEPKT2Note 1 GPIO11 GPIO11 DSR1_N TRACEPKT3Note 1 GPIO12 GPIO12 CTS1 N ETMEXTOUT GPIO13 GPIO13 GPIO14 GPIO14 GPIO15 GPIO15 WDOUTO N GPIO16 GPIO16 DSR2 N SSPCTLOE ETMEXTIN1 GPIO17 GPIO17 CTS2 N GPIO18 GPIO18 SSPRXD GPIO19 GPIO19 SSPTXD TRACEPKTANete 2 GPIO20 GPIO20 SCLKOUT TRACEPKT5Nete 2 GPIO21 21 SFRMOUT 6 2 GPIO22 GPIO22 SFRMIN TRACEPKT 7Nete 2 GPIO23 GPIO23 SCLKIN DBGACK GPIO24 GPIO24 PLL EXT IN N GPIO25 GPIO25 TGEN OUT1 N GPIO 31 26 GPIO 31 26 Notes 1 If the ETM9 module is activated via debug SW it is configured as an 4 bit wide or 8 bit wide ETM port function TRACEPKT 3 0 is set regardless of the value of GPIO PORT MODE L bits 23 16 2 If the ETM9 module is activated via debug SW and it is set as an 8 bit wide ETM port function TRACEPKT 7 4 is set regardless of the value of GPIO PORT MODE H bits 13 6 Remark There is no protection against the selection of non existing alternative GPIO functions implemented in this case the behaviour of ERTEC 400 is unpredictable Preliminary Users Manual A17812EE1V1UM00 125 Chapter 11 General Purpo
121. ata input signal JTAG test mode select signal TDO JTAG data output signal DBGREQ Debug request signal DBGACK Debug acknowledge signal TAP_SEL TAP controller select signal Besides for the debug function the JTAG interface is also used for the boundary scan function selec tion between these two functions is made with the TAP_SEL input pin TAP_SEL 0 Boundary scan function selected TAP_SEL 1p Debug function selected The TAP_SEL input is equipped with an internal pull up resistor and must be at high level for normal operation of the ERTEC 400 In addition to the JTAG interface the DBGREQ signal is provided at a dedicated pin and the DBGACK signal is available as alternative function at GPIO23 for debugging Due to the different debuggers an internal pull up resistor at the TRST_N JTAG pin is not included The user has to ensure the proper cir cuitry for the utilized debugger Preliminary Users Manual A17812EE1V1UM00 207 Chapter 21 Test and Debugging The standard connector for JTAG interfaces is a low cost 20 pin connector with a pin spacing of 0 1 inch All JTAG pins and the two additional DBGREQ and DBGACK pins are connected here the TAP_SEL configuration pin is not wired to the JTAG connector The connector pins are assigned as follows Figure 21 4 JTAG Connector Pin Assignment TRST_N TDI TMS TCK RTCKNote TDO RST Note DBGREQ DBGACK N
122. case the address area access must be assigned as Little Endian access If an external host accesses ERTEC 400 ERTEC 400 behaves like 16 bit little endian device with 8 bit and 16 bit access possibilities Table 9 7 lists all allowed access types Table 9 7 Possible Host Accesses to 400 LBU BE1 N LBU BEO N Internal AHB access 8 bit low byte 8 bit high byte 16 bit Others Not allowed Accesses from the external host are typically asynchronous to the ERTEC 400 internal AHB clock therefore they are synchronized to the internal AHB clock Figures 9 2 to 9 5 show typical read and write sequences for different control signal configurations Figure 9 2 LBU Read from ERTEC 400 with Separate Read Control Line SRN N LBU CS M N LBU AB 20 0 LBU SEG 1 0y Valid address LBU BE 1 0 N LBU_RDY_N LBU_DB 15 0 am Valid data 110 Preliminary Users Manual A17812EE1V1UMOO Chapter 9 Local Bus Unit LBU Figure 9 3 LBU Write to ERTEC 400 with Separate Write Control Line LBU CS R N LBU CD M N WR N N AB 20 0 SEG 1 0 Valid address LBU BE 1 0 N LBU_RDY_N LBU_DB 15 0 _ Valid data Figure 9 4 LBU Read from ERTEC 400 with Common Read Write Control Line LBU_CS_R_N LBU_CS_M_N LBU_WR_N LBU_AB 20 0 LBU_SEG 1 0 Valid address LBU BE 1 0 LBU N ji 10 gt LBU_DB 15 0 Gal V
123. creased using a five stage pipeline 8 kBytes of I cache 4 kBytes of D cache and 4 kBytes of D TCM Multilayer AHB Bus The Multilayer AHB bus is the data highway within ERTEC 400 It connects all major functional blocks with a 32 bit 50 MHz segmented bus structure that is able to run three bus transfers in parallel without blocking External Memory Interface Access to external memories is provided with a double memory controller that supports 256 MBytes of standard SDRAM with an access speed of 50 MHz and a total of 64 MBytes of static memory with one dynamic and four static chip select signals The static chip select signals can be used for SRAM Flash and peripheral devices External bus width is configurable to 16 32 bit for SDRAM and 8 16 32 bit for the static portion of the interface Access timings are individually selectable for each chip select Internal SRAM ERTEC 400 provides 8 kBytes of internal SRAM in a 32 bit organization the SRAM can be accessed with the multilayer AHB speed i e 50 MHz Interrupt Controller The ARM processor core on ERTEC 400 has a normal interrupt input IRQ and a fast interrupt input FIQ With the on chip interrupt controller the interrupt processing capabilities are extended to 16 IRQs and 8 FIQs with prioritization and vectorization These interrupts are partly assigned to internal resources and partly accessible to the external world via GPIO pins IRT Switch The IRT switch bloc
124. d Reserved SPI e g for use with EEPROMS with serial interface UART1 bootstrap method PCI slave LBU from external host Booting from NOR Flash or EEPROM with 8 16 32 bit data width via EMIF I O Bank 0 CS PERO Booting from serial EEPROMsS Flashes via the SPI interface The GPIO22 control line is then used as the chip select for the serial BOOT ROM The storage medium Flash or EEPROM is selected by means of the GPIO23 control line Booting from PCI slave interface or a host processor system via the LBU bus Booting from UART1 With the bootstrap method a routine for operation of the serial interface is executed first This routine then controls the actual program download During the boot operation a portion of the communication RAM from 1010 0000H to 1010 102FH is reserved for the boot sequence During the boot sequence the IRT switch can only be accessed in the area 1010 1030H to 1012 FFFFH Note A more detailed description of the boot modes and the operation of the related program parts is given in the documentation that is listed on page 6 Preliminary User s Manual A17812EE1V1UMOO0 117 Chapter10 Boot ROM 10 1 Booting from External ROM This boot mode is provided for applications for which the majority of the user firmware runs on the ARM946E S 10 2 Booting via SPI SPI compatible EEPROMs as well as SPl compatible Data Flash memories be used as an SPI source GPIO23 is
125. d to GPIO pins Table 7 2 summarizes the possible IRQ interrupt sources Function Block Timer Timer Table 7 2 Signal name TIM INTO TIM INT1 IRQ Interrupt Sources Default setting Rising edge Rising edge Comment Timer 0 interrupt Timer 1 interrupt GPIO GPIO 1 0 Configurable External input ERTEC 400 GPIO 1 0 GPIO 31 30 Configurable External input ERTEC 400 31 30 ARM CPU COMM_Rx Rising edge Debug receive communications channel interrupt ARM CPU COMM_Tx Rising edge Debug transmit communications channel interrupt UART_1 UART_INTR1 High level Group interrupt UART1 UART 2 SPI UART INTR2 SSP INTR High level Rising edge Group interrupt UART2 Group interrupt SPI SPI SSP ROR INTR Rising edge Receive overrun interrupt SPI IRT Switch IRT Switch IRQO SP IRQ1 SP Rising edge Rising edge High priority IRT interrupt Low priority IRT interrupt IRT Switch IRQ ERR Rising edge Synchronization error in IRT API cannot be masked in IRT PCI The interrupt controller is operated at a clock frequency of 50 MHz AHB INT L Rising edge AHB PCI bridge Interrupt request signals that are generated at a higher clock frequency must be extended accordingly for error free detection 7 1 Prioritization of Interrupts It is possible to set priorities for the I
126. e UARTs an SPI channel two timers a watchdog an additional fail safe timer F timer and a GPIO block with up to 32 individually configurable I Os The interfaces share their pins with the GPIOs so that depending on the selected configuration a reduced number of GPIOs is available 4 GPIOs can be used as interrupt sources Clock and Power Supply The ERTEC 400 can be operated with a single external 12 5 MHz crystal An internal oscillator and PLL generate all required clocks for the ARM946E S the IRT block the internal buses and other peripherals Alternatively an external reference clock of 50 MHz can be supplied Two supply voltages are required for operation of ERTEC 400 The internal logic is running at 1 5 V and I Os are operating at 3 3 V The PCI interface has 5 V compatible I Os Preliminary Users Manual A17812EE1V1UMOO Chapter 1 Introduction 1 2 Device Features ARM946E S Processor Adjustable operating frequency 50 100 150 MHz System control co processor CP15 4 kBytes of Data TCM Interface with Write buffer on 32 bit multilayer AHB bus 8 kBytes and 4 kBytes D cache with lock functionality Memory Protection Unit Cacheability attribute setting for regions Read write access rights for certain modes only 2 interrupt controllers with 16 inputs for IRQ and 8 inputs for FIQ Debug trace functionality by ETM9 module via JTAG interface Trace in full rate mode at operating frequencies of 50 and 100
127. e communication RAM The IRT switch evaluates these mirror areas thus ensuring consistency for un aligned 16 bit and 32 bit accesses This functionality corresponds to that of the LOCK mechanism of the PCI bridge Preliminary Users Manual A17812EE1V1UM00 99 Chapter 8 PCI Interface 8 3 Address Assignment of PCI Registers The PCI registers are 32 bits wide the registers can be read or written to with 8 bit 16 bit or 32 bit accesses Table 8 3 gives an overview of the PCI registers For a detailed description the reader is referred to the documents listed on page 6 Table 8 3 Address Assignment of PCI Registers 1 2 Register Name Address 8000 0000H Bit 31 24 Bit 23 16 Device ID Bit 15 8 Bit 7 0 Vendor ID Initial value 4026110AH 8000 0004H Status Command 0230 0000H 8000 0008H Class Code Revision ID 0000 20A0H 8000 000CH Header Type Latency Timer Cache Line Size 0000 0000H 8000 0010H PCI Base Address RegisterO 0000 0000H 8000 0014H PCI Base Address Register1 0000 0000H 8000 0018H PCI Base Address Register2 0000 0000H 8000 001CH 8000 0020H PCI Base Address Register3 PCI Base Address Register4 0000 0000H 0000 0000H 8000 0024H PCI Base Address Register5 0000 0000H 8000 0028H 8000 002CH Cardbus CIS Pointer Subsystem ID Subsystem Vendor ID 0000 0000H 0000 0000H 8000 0030H
128. e current prescaler value cannot be read out In addition there are no status bits for the prescalers The prescalers always operate in reload mode 15 1 4 Cascading of Timers If the cascading bit is set both 32 bit timers can be cascaded to a 64 bit timer This cascaded timer is enabled via the status control register of Timer 1 The interrupt of Timer 1 is active The interrupt of Timer 0 must be disabled when the timers are cascaded When prescalers are specified additionally only the prescaler of Timer 1 is used The user must ensure data consistency in the user software when initialising or reading out the 64 bit timer 156 Preliminary User s Manual A17812EE1V1UMOO Chapter 15 400 Timers 15 1 5 Address Assignment of Timer 0 1 Registers The timer registers are 32 bits in width For read write access of the timer registers to be meaningful a 32 bit access is required However an 8 bit or 16 bit access is not intercepted by the hardware Table 15 1 Address Assignment of Timer 0 and Timer 1 Registers Address Register Name Initial value Description 4000 2000H CTRL_STATO 0000 0000H Control status register timer 0 4000 2004H CTRL_STAT1 0000 0000H Control status register timer 1 4000 2008H RELDO 0000 0000H Reload register timer 0 4000 200CH RELD1 0000 0000H Reload register timer 1 4000 2010H CTRL_PREDIV 0000 0000H Control register for both prescalers 4000 2014H RELD PREDIV 0000 0000H Reload
129. e logical level at the GPIO pins on a bit by bit basis under the assumption that the pin is actually configured as input GPIO IN GPIO INn GPIO input data Ob Low level is applied to pin High level is applied to GPlOn pin 122 Preliminary Users Manual A17812EE1V1UMOO Chapter 11 General Purpose I O GPIO Figure 11 5 GPIO PORT MODE L Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO15 GPIO14 GPIO13 GPIO12 GPIO11_ GPIO10 GPIO9 GPIO8_ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO7_ GPIO6_ GPIO5 GPIO4 GPIO3_ GPIO2 GPIO1_ GPIOO_ PO_MO PO MO PO MO PO MO Bit position Bit name Function GPIO15 PO MO Selects one of max four different functions for pin GPIO15 GPIO15 PO MO GPIO15 function selection 005 Select function 0 for pin GPIO15 GPIO15 PO MO 01 Select function 1 for pin GPIO15 if available 10 Select function 2 for pin GPIO15 if available 11 Select function 3 for pin GPIO15 if available GPIO0 PO MO Selects one of max four different functions for pin GPIOO PO MO GPIOO function selection GPIO0 PO MO 00 Select function 0 for pin GPIOO 01 Select function 1 for GPIOO if available Select function 2 for pin GPIOO if available Select function 3 for pin GPIOO if available Preliminary Users Manual A17812E
130. ed according to a 16 bit or 32 bit organization In case of a page with 16 bit organization each 8 bit or 16 bit access is forwarded to the AHB bus In case of a page with 32 bit organization a 32 bit read access is implemented on the AHB bus when the LOW word is read In addition the LOW word is forwarded and the HIGH word is stored temporarily in the LBU A subsequent read access to the HIGH word address outputs the temporarily stored value This ensures consistent reading of 32 bit data ona 16 bit bus In the case of 32 bit write access the LOW word is first stored temporarily in the LBU area When the HIGH word is write accessed a 32 bit access to the AHB bus is implemented Eight bit accesses are forwarded directly to the AHB bus and are therefore not useful for a 32 bit page Preliminary Users Manual A17812EE1V1UM00 109 Chapter 9 Local Bus Unit LBU 9 5 Host Accesses to ERTEC 400 When the host uC accesses address areas of the ERTEC 400 a distinction must be made between 16 bit and 32 bit host processors The data width of the variables is defined for a 16 bit host processor The various compilers implement the accesses in any order In case of a 32 bit access by the user Software it must be ensured that the lower 16 bit half word access to the 32 bit address area precedes the upper 16 bit half word access In case of a 32 bit host processor the access order is defined by setting the external bus controller of the host processor In this
131. egister 121 Chapter 12 2 252 22 2252 55 555 5 555555 ERR e 127 12 1 Address Assignment of UART1 2 130 12 2 Detailed UART1 2 Register lt 131 12 3 GPIO Register Initialization for UART Usage 140 Chapter 13 Synchronous Serial Interface 1 141 13 1 Address Assignment of SPI lt 143 13 2 Detailed SPI Register Description 144 13 3 GPIO Register Initialization for SPI 0 150 Chapter 14 External PHY 151 14 1 4 Channel RMII 151 14 2 2 Channel MII Operation 154 Chapter 15 ERTEC 400 155 15 1 Timer 0 and 1 155 15 1 1 Operation Mode of Timers 156 15 1 0 Timer eee Ree Te Bee la ae 156 Taka TimerPrescalet sos ot eens ek RE ORE AU pud 156 15 1 4 Cascading
132. egister low 00 0022H LBU_P2_RG_H LBU page 2 range register high 00 0024H 00 0026H LBU P2 OF L LBU P2 OF H LBU page 2 offset register low LBU page 2 offset register high 00 0028H LBU P2 CFG LBU page 2 configuration register 00 0030H 00 0032H LBU P3 RGL LBU page range register low LBU page 3 range register high 00 0034H LBU OF L LBU page 3 offset register low 00 0036H 00 0038H LBU P3 OF H LBU P3 CFG LBU page 3 offset register high LBU page 3 configuration register Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Table 9 8 shows that the LBU registers are seen at the lower 64 Bytes of the 2MByte address range that is opened by the LBU 20 0 signals In case that LBU AB 20 6 are different from 0 while an LBU register is accessed the registers are mirrored every 64 Bytes During an access to LBU registers CS N 0 the level of the page selection signals LBU SEG 1 0 is not relevant Preliminary Users Manual A17812EE1V1UM00 113 Chapter 9 Local Bus Unit LBU 9 7 Detailed LBU Register Description This chapter gives a detailed description of the LBU register bit functions As there is an identical set of five LBU registers for each configurable page only one set will be described as representative Figure 9 6 LBU Page Range Register Low LBU Pn
133. el is generated from external pull up resistor and not by internal device circuitry 2 The reset signal that affects these pins is TRST_N Remark Shared pins are not listed with all possible pin names Please check Tables 2 1 to 2 13 for possible pin names first before looking up reset characteristics and recommended connections in Table 2 15 46 Preliminary User s Manual 17812 1 10 00 Chapter 3 CPU Function 3 1 Structure of ARM946E S Processor System An ARM946E S processor system is used in ERTEC 400 Figure 3 1 shows the structure of the proces sor In addition to the ARM9E S processor core the system contains a data cache an instruction cache a memory protection unit MPU a system control co processor and a tightly coupled data memory The processor system has an interface to the integrated AHB bus Figure 3 1 ARM 946E S Processor System in ERTEC 400 To from AHB bus D TCM System AHB I F l l Cache D Cache control control TCM control Dout Addr Din a VF VF System control coprocessor CP15 System control To from external coprocessors ARM946E S processor system is a member of the ARM9 Thumb family It has a processor core
134. emory map decoders for decoding the physical address area of ERTEC 400 1 sequencer 2 counters Supplemental to the ETM specification 8 memory map decode MMD regions have been decoded out via hardware these regions are summarized in Table 21 1 Table 21 1 Memory Map Decode Regions in ETM9 on ERTEC 400 Address range Affected accesses 0000 0000H 0000 OFFFH Instruction cache l cache 0000 1000H 0000 1FFFH Data cache D TCM 0000 2000H OFFF FFFFH All accesses User RAM in all mirrored areas 1000 OOOOH 100 FFFFH Data IRT registers all mirrored areas 1010 OOOOH 101F FFFFH All accesses communication RAM in all mirrored areas 2000 0000H 2FFF FFFFH All accesses SDRAM in all mirrored areas 3100 0000H 31FF FFFFH All accesses via EMIF CS PER1 N address range 8000 0000H FFFF FFFFH Data PCI in the entire 2 Gbytes area For more information on the ETM refer to the additional documents listed on page 6 Preliminary User s Manual A17812EE1V1UMOO0 205 Chapter 21 Test and Debugging 21 2 ETM9 Registers The ETM registers are not described in this document because they are handled differently according the ETM version being used For a detailed description please refer to the documents listed on page 6 21 3 Trace Interface In order to read out the trace information collected by the ETM9 a trace port is provided ERTEC 400 for tracing internal processor states T
135. equired When writing this occurs after the end of the strobe phase When reading this occurs after a specified time has elapsed after the end of the strobe phase to avoid driving against the externally read block For the SDRAM controller this time is equivalent to one AHB bus cycle For the asynchronous controller the time is equivalent to the time required for the hold phase to elapse which corresponds to the time from the rising edge of RD_N to the rising edge of the chip select signal By default the active interface is switched on The following signal pins are available for the EMIF on ERTEC 400 Table 6 1 External Memory Interface Pin Functions Pin Name Function Number of pins A 23 16 External memory address bus 23 16 A 15 0 External memory address bus 15 0 External memory data bus 31 0 Write strobe signal Read strobe signal CLK SDRAM Clock to SDRAM CS SDRAM N Chip select to SDRAM RAS SDRAM N Row address strobe to SDRAM CAS SDRAM N Column address strobe to SDRAM WE SDRAM N RD WR signal to SDRAM CS PER 3 0 N Chip select to static memories peripherals BE 3 0 DQM 3 0 Byte enable to static memories peripherals and SDRAM RDY PER N Ready signal from static peripherals DTR N Direction signal for external driver or scan clock OE DRIVER N Enable signal for external driver or scan clock total Note The pins A 23 16 are used as inputs BOOT 2 0 and CONFIG 4 0
136. er or scan clock Enable signal for external driver or scan clock Boot mode System configuration GPIO pins UART transmit data output UART receive data input UART carrier detection signal UART data set ready signal UART transmit enable signal PCI address data bits PCI initialization device select PCI byte enable PCI power management PCI request PCI grant PCI clock PCI reset PCI interrupt PCI interrupt INTB PCI clock selection PAR SERR N PERR N STOP N DEVSEL N TRDY N IRDY_N FRAME_N LBU_AB 20 0 LBU_DB 15 0 LBU_WR_N LBU_RD_N LBU_BE 1 0 _N LBU_SEG_ 1 0 LBU IRQ 1 0 N LBU RDY LBU CS M N LBU CS R LBU CFG LBU POL RDY SSPRXD SSPTXD SCLKOUT SFRMOUT SFRMIN SCLKIN SSPCTLOE SSPOE TXD P 3 TXD P 3 TXD P 1 TXD P 3 RXD P 3 0 0 1 0 0 0 0 2 3 0 Preliminary Users Manual A17812EE1V1UMOO PCI parity PCI system error PCI parity error PCI stop PCI device select PCI target ready PCl initiator ready PCI cycle frame LBU address bus LBU data bus LBU write control LBU read control LBU byte enable LBU page selection LBU interrupt request LBU ready signal LBU chip select to ERTEC 400 internal resources LBU chip select to page configuration registers LBU separate RD WR LBU polarity selection for pin LBU_RDY_N SPI recei
137. essor Registers Access type Comment ID code register Cache type register Tightly coupled memory size register Control register Cache configuration register Write buffer control register Reserved Access permission register Protection region base size register Cache operation register Reserved Cache lock down register Tightly coupled memory region Reserved Reserved Reserved Trace process ID register Reserved RAM TAG BIST test register Test state register Cache debug index register Trace control register These register locations provide access to several registers that are selected with the opcode 2 or CRm field of the ARM register access instructions Separate registers implemented for instruction and data Undefined when read do not write Details about the ARM946E S processor system and its components can be found in the related ARM documents see page 6 Preliminary Users Manual A17812EE1V1UMOO Chapter 4 ERTEC 400 Bus System ERTEC 400 has two internal buses respectively bus systems High performance communication bus multilayer AHB bus O bus APB bus The following functional blocks are directly connected to the multilayer AHB bus e ARM946E S processor system master interface IRT switch master slave interface Local bus unit master interface PCI master slave interface Interrupt controller slave interface
138. evelopment of industrial Ethernet devices ERTEC 400 contains a 32 bit RISC processor an external memory interface with SDRAM and SRAM controller a PCI LBU interface a 4 channel real time Ethernet interface synchronous and asynchro nous serial ports and general purpose l Os Its robust construction specific automation functions and openness to the IT world are distinguishing features The ERTEC 400 is housed in a 304 pin plastic FBGA package 19 mm x 19 mm 1 2 3 ARM946E S Processor ERTEC 400 uses an ARM946E S processor with configurable clock frequencies of 50 100 or 150 MHz This processor however is based on the ARM9E S core that supports the ARM5vTE instruction set architecture with 32 bit wide normal instructions and the 16 bit wide THUMB instruction set It includes support for separate instruction and data caches as well as tightly coupled memory In case of ERTEC 400 8 kBytes of instruction cache I cache and 4 kBytes of data cache D cache are available The tightly coupled memory TCM has a size of 4 kBytes and can be accessed with full CPU speed An integrated memory protection unit MPU allows to restrict access permission to eight program mable portions of the ERTEC 400 address space The processor core is extended with two on chip interrupt controllers one of which is connected to the core s FIQ input while the other one is connected to the IRQ input The IRQ interrupt controller handles up to 16 interru
139. ey bits 4000 2108H 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ReloadO Bit position Bit name Function Key bits Key bits Must be written with 9876H in order to make a write access effective read 0000H ReloadO Reload0 Holds the reload value for bits 31 15 of watchdog timer 0 counter Figure 16 6 Reload Register Low for Watchdog 1 RELD1_LOW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Key bits 4000 210CH 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reload1 Bit position Bit name R W Function Key bits Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload1 Reload1 Holds the reload value for bits 19 4 of watchdog timer 1 counter bits 3 0 are always reloaded to 0000p 172 Preliminary Users Manual A17812EE1V1UMOO Chapter 16 Watchdog Timers Figure 16 7 Reload Register High for Watchdog 1 RELD1_HIGH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Key bits 4000 2110H 0000 FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reload1 Bit position Bit name Function Key bits Key bits Must be written with 9876H in order to make a write access effective read 0000H Reload1 Holds the reload value for bits 35 20 of watchdog timer 1 counter Reload1 Figure 16 8 Counter Register for Watchdog 0 WDOGO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Ini
140. f 50 MHz All registers in the peripheral I O blocks are memory mapped into the address space of the ARM946E S processor system Remark A detailed specification of the internal bus systems of ERTEC 400 can be found in the related ARM documents see page 6 52 Preliminary User s Manual A17812EE1V1UMOO Chapter 5 ERTEC 400 Memory This section presents a detailed description of the memory areas of all integrated function blocks The memory map depends on the device configuration selected during reset on register settings and finally on the block that actually accesses the memory 5 1 Memory Partitioning of ERTEC 400 The memory partitioning is explained from the position of the multilayer AHB bus Basically the AHB bus has an 32 bit address range that corresponds to 4 GBytes of memory Every potential master on the multilayer AHB bus has its own perception of the memory range These different perceptions are summarized in Table 5 1 Table 5 1 Memory Area Partitioning Start address End address 0000 0000H OFFF FFFFH 1000 0000H 1FFF FFFFH 2000 0000H Segment ARM946E S IRT Switch PCI LBU Internal boot ROM or internal SRAM Internal boot ROM or internal SRAM Internal boot ROM or internal SRAM IRT Switch Not used IRT Switch 2FFF FFFFH External memory inter face CS SDRAM External memory inter face CS SDRAM External memory inter face CS SDRAM 3000 0000H FFFFH External
141. f the address This mechanism guarantees that the offset is always an integer multiple of the selected page size The following Table 9 3 shows some examples for offset calculations for various page sizes Table 9 3 Page Offset Setting Examples Page size LBU Pn OF H LBU Pn OF L ofpagen Bit 31 24 Note Bit 23 16 Note Bit 15 8 Bit 7 0 256 Bytes 0000 0000 0000 0000 0000 0001 0000 0000 256 Bytes 256 Bytes 0000 0000 0000 0000 0001 0000 0000 0000 4kBytes Resulting offset 2 MBytes 0100 0000 00000000 0000 0000 0000 0000 1 GByte 512 kBytes 0001 0000 00000000 0000 0000 0000 0000 256 MBytes 8 kBytes 0000 0000 0000 0001 0000 0000 0000 0000 64 kBytes 8 kBytes 00000000 0000 0001 0100 0000 0000 0000 80 kBytes Note Bit numbers in the table refer to the complete 32 bit address that is formed by concatenating LBU Pn OF H and LBU Pn OF L registers Because the host computer can always access the page registers the pages can be reassigned at any time This is useful for example if a page is to be used to initialize the I O If access to this address area is no longer required after the initialization the page can then be reassigned in order to access other address areas of ERTEC 400 106 Preliminary Users Manual A17812EE1V1UMOO0 Chapter 9 Local Bus Unit LBU 9 3 LBU Address Mapping Example The following Table 9 4 illustrates how an external host processor loo
142. fast interrupt requests that have been confirmed by the CPU Bit 0 corresponds to FIQO etc FIQISR FIQISRn n 0 7 Confirmation of FIQ interrupt request Fast interrupt request FIQn not confirmed initial value Fast interrupt request has been confirmed 88 Preliminary Users Manual A17812EE1V1UMOO Chapter 7 Interrupt Controller Figure 7 14 FIQIRR FIQ Interrupt Request Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 5000 0050H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FARR Bit position Bit name Function Reserved FIQIRR 7 0 Individual indication of fast interrupt requests that have been recognized by the ICU Bit 0 corresponds to FIQO etc FIQIRRn n O 7 Recognition of FIQ interrupt request FIQIRR Fast interrupt request not recognized by ICU initial value Fast interrupt request has been recognized by ICU Figure 7 15 FIQ MASKREG FIQ Interrupt Mask Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 6 5 4 3 2 1 Bit position Bit name Function 31 8 Reserved FIQ MASKREG 7 0 Individual masking of fast interrupt inputs Bit 0 corresponds to FIQO etc FIQ MASKREOn n 0 7 Masking of fast interrupt inputs FIQ MASK 3 alis REG Fast interrupt request FIQn enabled Fast interrupt request FIQn masked initial value
143. from the boot Flash memory to SDRAM during the system startup phase and subse quently executed from SDRAM for optimized system performance Figure 6 11 External Memory Connection Example 1033V mE E D 15 0 Flash 2M x 16 bit o9gz92 X 22522 14 1 2125 D 31 16 Di D D D D D Di 0 Di D 1 1 1 1 CKE SDRAM 16M x 16 bit A 14 0 D 15 0 1033V _ bi D gt 0 gt bi 0 D 1 n 1 CKE SDRAM 16M x 16 bit 8 lt 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 228 CS0 PER ERTEC
144. function 0 control Memory 3 GP1023 function 0 detection XXXX XXXX 0000 XXXXp Note In Table 13 3 x stands for don t care XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXXp 01 XXXX XXXX XXXXp Figure 13 8 shows a simple circuit diagram for the connection of a serial Flash memory to ERTEC 400 based on above initialization Figure 13 8 Connection of Serial Flash Memory to ERTEC 400 SPI Interface GPIO23 ERTEC 400 pPD80232 GPIO22 RESET N WP SI Serial Flash AT45DB011 150 SSPRXD SCLKOUT 50 SCK Preliminary User s Manual 17812 1 10 00 Chapter 14 External PHY Interface The ERTEC 400 device has an integrated 4 channel IRT switch with 4 fast Ethernet ports In order to integrate ERTEC 400 into an Ethernet based network external PHY components need to be connected to these ports For easy connection of external PHY components the ports have standardized interfaces 2 media independent interfaces for 2 channel operation mode 4 reduced media independent interface RMII for 4 channel operation mode Selection between these two operation modes is implicitly done with the CONFIG1 CONFIG1 0 4 channel RMII operation and 50 MHz input clock to REF_CLK pin CONFIG1 1 2 channel MII operation and 25 MHz input clock to RE
145. guration Read Write Type 0 Read Write 6 ERTEC 400 internal address spaces 1 IRT communication function 1 delayed instruction queue Write data FIFO with a depth of 16 Delayed read data FIFO with a depth of 16 Configuration area is loaded from the ARM946 not from an EPROM Preliminary Users Manual A17812EE1V1UMO00 Chapter 8 PCI Interface 8 1 1 PCI Interrupt Handling Interrupt outputs INTA_N INTB_N and SERR_N are available at the PCI interface An interrupt request from the ARM946E S to the PCI bus takes place by write accessing the interrupt controller integrated in the IRT switch The interrupts are masked and saved in the IRT switch This enables operation of a mailbox from the ARM946E S to the PCI host An interrupt request from the PCI bus to the ARM946E S takes place by write accessing an IRT switch internal register The interrupts are masked and saved in the interrupt controller of the ARM946E S This enables operation of a mailbox from the PCI host to the ARM946E S When PC based systems are linked only INTA_N is used single function in the PCI bridge the INTB_N output is not used When an embedded host processor is linked both INTA_N and INTB_N can be used The local ARM processor is linked via the IRQO SP and IRQ1 SP interrupts Both are linked via the internal logic structure of the interrupt controller unit ICU to the IRQ input of the ARM946E S Optionally the option exists to link these interrupts to the
146. he PM_State_Req register in the system control register area The current power state is stored in the PM_State_Ack register in the PCI configuration area If the requested power state differs from the current power state the PCI macro module issues an interrupt to the interrupt controller of the ARM946E S The 946 5 can then change the local power state to the requested power state by writing to the PM_State_Ack register The PCI host can then scan the current state by reading the PM_Control_Status register in the PCI configuration area The output signal PME_N can be activated by writing to the PME_REG register in the system control register area However this requires that the PME Enable bit in the PM_Control_Status register in the PCI configuration area is set ERTEC 400 requires the PCI clock to initiate the PME N signal If the power state of ERTEC 400 is not DO all PCI interrupts in ERTEC 400 must be disabled via the software according to the PCI specification PCI interrupts may only be enabled in the DO state There is no hardware support for disabling the interrupts 8 1 3 Accesses to the AHB Bus When accesses to the AHB bus are not aligned the AHB PCI bridge behaves as follows Not Aligned Posted Writes are separated on the AHB side into 2 individual accesses with a lock Not Aligned Delayed Reads are issued on the AHB side as full 32 bit accesses All other not aligned accesses are rejected with Target Abort 98
147. he page varies between 256 Bytes and 2 MBytes Therefore Bits 7 0 and 31 22 of the PAGEn RANGE register remain unchanged at a value of 0 even if a value of 1 is written If no bit at all is set in one of the page size registers the size of this page is set to 256 Bytes by default If several bits are set to 1 in one of the page range registers the size is always calculated based on the most significant bit that is set to 15 Table 9 2 summarizes the possible settings Table 9 2 Page Size Settings LBU Pn RG H Pn RG L Page size Required Bit 31 22 Note Bit 21 16 Note Bit 15 8 Bit 7 0 of page n address lines 0000 0000 00 00 0000 0000 00015 0000 0000 256 Bytes LBU_AB 7 0 0000 0000 00 00 0000 0000 001 0000 0000 512 Bytes LBU_AB 8 0 0000 0000 00 00 0000 0000 01 0000 0000 1 kByte LBU_AB 9 0 0000 0000 00 00 0000 0000 1 0000 0000 2kBytes LBU_AB 0000 0000 00 00 0000 0001 0000 0000 4kBytes LBU_AB 10 0 11 0 0000 0000 00 00 0000 001x xxxxp 0000 0000 8 kBytes LBU_AB 12 0 0000 0000 00 00 0000 01 XXXXp 0000 0000 16 kBytes LBU_AB 13 0 0000 0000 00 00 0000 1XXX XXXXp 0000 0000 32 kBytes LBU_AB 14 0 0000 0000 00 00 0001 XXXX XXXXp 0000 0000 64 kBytes LBU AB 15 0 0000 0000 00 00 001 XXXX XXXXp 0000 0000 128 kBytes LBU AB 16 0 17 0 18 0 19 0 20 0 0000 0000 00 00 01 XXXX XXXXp 0000 00
148. he trace port is controlled enabled and disabled using a suitable hardware debugger that is connected to the JTAG interface This trace port uses the following signals Table 21 2 Trace Port Pin Functions Pin Name Function Number of pins PIPESTA 2 0 CPU pipeline status TRACESYNC Trace sync signal TRACECLK ETM trace or scan clock TRACEPKT 7 0 Trace packet bits total The TRACEPKT 7 0 signals are alternative signal pins at the GPIO port The trace interface can be configured to a data width of 4 bits or 8 bits in the debugger If a data width of 4 bits is selected the TRACEPKT 3 0 signals at GPIO 11 8 are automatically switched to the trace function If a data width of 8 bits is assigned the TRACEPKT 7 4 signals at GPIO 21 18 are also switched to the trace function For connectors pinning and hardware circuitry for the trace interface please consult the additional documents listed on page 6 206 Preliminary Users Manual A17812EE1V1UMOO Chapter 21 Test and Debugging 21 4 JTAG Interface ERTEC 400 has a serial debug interface that conforms to the JTAG standard If this interface is made accessible in a system it can be used for the connection of hardware debuggers from different manu facturers Table Table 21 3 on page 207 summarizes the debug interface pins Table 21 3 JTAG and Debug Interface Pin Functions Pin Name VoNote Function Number of pins TRST_N JTAG reset signal JTAG clock signal JTAG d
149. ial value Receive FIFO half full or less interrupt SSP RX INTR is enabled Notes 1 The SSP INTR interrupt is mapped to the IRQ11 input of the IRQ interrupt controller 2 The interrupts SSP TX INTR and SSP RX INTR are combined wired OR to the SSP INTR interrupt that is wired to the IRQ10 input of the IRQ interrupt controller Figure 13 4 SSPDR SPI Rx Tx FIFO Data Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value Data 4000 2208H xxxxH Data 15 0 Data R W Accesses the first position of the transmit receive FIFOs when read the receive FIFO is accessed when written the transmit FIFO is accessed Note Note If data with less than 16 bits width is used the user must write the data to the Transmit FIFO in the proper format When data are read they are read out correctly from the Receive FIFO Preliminary Users Manual A17812EE1V1UMOO 147 Chapter 13 Synchronous Serial Interface SPI Figure 13 5 SSPSR SPI Status Register 15 14 13 12 11 10 9 8 7 6 5 Address Initial value 4 3 2 1 0 Bit position Bit name Function Reserved BSY SPI busy status indication Busy status indication SPI is not busy initial value SPI is sending and or receiving a frame or the transmit FIFO is not empty RFF Receive FIFO full indication Receive FIFO full indication Receive FIFO is not full initial value Receive FIFO is full RNE Receive FIFO not empty indicati
150. ication combinations Preliminary User s Manual A17812EE1V1UMOO0 51 Chapter 4 ERTEC 400 Bus System Table 4 1 Possible AHB Master slave Combinations AHB slaves AHB External master memory priority interface Interrupt controller ARM high IRT medium PCI LBU low AHB masters Remark x stands for possible stands for impossible For closed loop control applications attention must be paid that AHB masters do not block each other over a long period This would be possible if for example a PCI master and ARM master want to access the same IRT slave with a time lag In this case the ARM master would have to pause in a Wait until the PCI master enables the IRT slave again To prevent this situation monitoring is inte grated into the AHB master interfaces of PCI LBU and IRT switch which enables the slave momentarily via an IDLE state after 8 consecutive data transfers burst or single access In this phase another AHB master can access this slave In case of simultaneous accesses of two AHB masters to the same address the characteristics of the higher priority master s access are stored in several system control registers see Chapter 20 1 for details 4 2 APBI O Bus All less demanding peripherals are connected to the ARM946E S processor system via the multilayer AHB bus an AHB to APB bridge and an APB bus The APB bus itself has a width of 32 bits and operates at a frequency o
151. ing bits are switched on the falling edge of SCLKIN OUT initial value Received bits are latched on the falling edge of SCLKIN OUT outgoing bits are switched on the rising edge of SCLKIN OUT FRF Selects one of the possible operation modes Frame format Motorola SPI frame format initial value TI synchronous serial frame format National Microwire frame format Reserved 144 Preliminary Users Manual A17812EE1V1UMOO Bit position Bit name Chapter 13 Synchronous Serial Interface SPI Figure 13 2 SSPCRO SPI Control Register 0 2 2 DSS DSS 3 0 Function Selects data word size for serial transmission reception Data size select Reserved initial value Reserved Reserved 4 bit data words 5 bit data words 16 bit data words Preliminary Users Manual A17812EE1V1UM00 145 Chapter 13 Synchronous Serial Interface SPI Figure 13 3 SSPCR1 SPI Control Register 1 1 2 15 14 13 12 11 10 9 8 7 Address Initial value 6 5 4 3 2 1 0 Bit position Bit name Function Reserved SOD The slave mode output enable bit This bit is only relevant in slave mode In Multiple slave systems the master can send a broadcast message to all slaves in the system in order to ensure that only one slave drives data at its transmit output Slave mode output enable bit SPI operates the SSPTXD output in slave mode initial value SPI does n
152. ion Reserved Page n 32 Configures 32 bit or 16 bit pages Page n 32 Page n 32 Page width configuration 16 bit page width initial value 32 bit page width Preliminary User s Manual 17812 1 10 00 Chapter 10 Boot ROM ERTEC 400 is equipped with a pre programmed boot ROM that allows software to be downloaded from an external storage medium The boot ROM has a size of 2k x 32 bits 8 kBytes and may only be read with 32 bit accesses Various routines are available for the different boot and download modes In order to select the boot source and mode three BOOT 2 0 inputs are available on ERTEC 400 During the active reset phase the boot pins are read in and stored in the Boot_REG register in the system control register area After start up of the processor the system branches to the appropriate boot routine based on the previously read boot mode selection and the download is performed After the download is complete the newly loaded functions are executed The following actions lead to a boot operation HW reset Watchdog reset Software reset caused by setting the XRES_SOFT bit in the reset control register SCR area Table 10 1 summarizes the supported download modes Table 10 1 Supported Download Modes Selected download mode Via external ROM NOR flash with 8 bit width Via external ROM NOR flash with 16 bit width Via external ROM NOR flash with 32 bit width Reserve
153. iority IRVEC 3 0 Interrupt vector number Valid IRQO with highest priority pending Valid IRQ15 with highest priority pending or default vector initial value Preliminary Users Manual A17812EE1V1UMOO 79 Chapter 7 Interrupt Controller Figure 7 2 FIQ Interrupt Vector Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value Vector ID 5000 0004 FFFF FFFFH 15 14 13 12 11 0 8 7 6 5 4 3 2 1 0 Vector ID FIVEC Bit position Bit name Function Vector ID 28 0 Differentiates valid FIQ interrupt vectors from the default FIQ vector Vector ID Vector ID 28 0 FIQ interrupt vector identification 0000 0000H FIQ interrupt vector pending 1FFF FFFFH Default interrupt vector initial value FIVEC 2 0 Number of the currently pending valid FIQ interrupt vector with the highest priority FIVEC 2 0 Interrupt vector number Valid FIQO with highest priority pending Valid FIQ7 with highest priority pending or default vector initial value 80 Preliminary Users Manual A17812EE1V1UMOO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 Bit position Chapter 7 Interrupt Controller Figure 7 3 LOCKREG IRQ Interrupt Priority Lock Register 12 11 10 reserved Bit name Address Initial value 5000 0008H 0000 0000H 7 6 5 4 3 2 1 0 LOCK ENA reserved LOCKPRIO BLE Function Reserved LOCKENA
154. is already terminated for the master the data phase can no longer be handled correctly Note In contrast to the AHB specification access is no longer repeated in this case 204 Preliminary User s Manual 17812 1 10 00 Chapter 21 Test and Debugging 21 1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM946E S of ERTEC 400 to enable instructions and data to be traced The ARM946E S supplies the ETM module with the signals needed to carry out the trace functions The ETM9 module is operated by means of the Trace interface or JTAG interface The trace information is stored in an internal FIFO and forwarded to the debugger via the interface The following trace modes are supported Normal mode with 4 or 8 data bit width Transmission mode Full rate mode at 50 or 100 MHz CPU core clock frequency Half rate mode at 150 MHz CPU core clock frequency The ETM9 embedded trace macrocell is available in different complexity levels ERTEC 400 has the medium complexity version of the ETM9 implemented Thus the ETMO provides the following features 4 address comparator pairs 2data comparators with filter function 4 direct trigger inputs one of which can be connected via GPIO16 if the alternative function for GPIO16 ETMEXTIN1 has been selected 1 trigger output that is also available at GPIO12 for external purposes if the alternative function 3 for GPIO12 ETMEXOUT has been selected 8 m
155. isters 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 r su r strobe r hold reserved Bit position Bit name Function Reserved Extended wait mode Decides if the RDY PER N signal is ignored or not Extended wait mode Ignore RDY PER N signal initial value Check timeout condition based on Async Wait Cycle Config register setting and generate IRQ if required Write strobe setup cycles Determines the number of AHB clock cycles between valid address data and chip select and falling edge of the write signal WR w_su 3 0 Write strobe setup cycles n 0H EH 1 AHB cycles FH 16 AHB cycles initial value Write strobe duration cycles Determines the number of AHB clock cycles between falling and rising edges of the write signal WR w_strobe w_strobe 5 0 Write strobe duration cycles 1 AHB cycles 3FH 64 AHB cycles initial value Write strobe hold cycles Determines the number of AHB clock cycles between rising edge of the write signal WR_N and change of address data and chip select w_hold 2 0 Write strobe hold cycles n 0OH 6H 1 AHB cycles 7H 8 AHB cycles initial value 66 Preliminary User s Manual 17812 1 10 00 Chapter6 External Memory Interface EMIF Figure 6 5 Bank 3 0 Config Registers 2 2 Bit position Bit name Function Read strobe setup
156. it is reset in the IRREG register Each bit that is set in the IRREG register can be deleted via software For this purpose the number of the bit to be reset in the IRCLVEC register is transferred to the interrupt controller 7 4 Software Interrupts for IRQ Each IRQ interrupt request can be triggered by setting the bit corresponding to the input channel in the SWIRREG software interrupt register Multiple requests can also be entered in the 16 bit SWIRREG register The software interrupt requests are received directly in the IRREG register and thus treated like a hardware IRQ Software interrupts can only be triggered by the ARM946E S processor because only this processor has access rights to the interrupt controller 7 5 Nested Interrupt Structure When enabled by the interrupt priority logic an IRQ interrupt request causes an IRQ signal to be output Similarly an FIQ interrupt request causes the FIQ signal to be output to the CPU If the request is accepted by the CPU in the IRQACK or FIQACK register the bit corresponding to the physical input is set in the ISREG or FIQISR register The IRQ FIQ signal is revoked The ISR bit of the accepted interrupt remains set until the CPU returns an End of interrupt command to the interrupt controller As long as the ISR bit is set interrupts with lower priority in the priority logic of the interrupt controller are disabled Interrupts with a higher priority are allowed by the priority logic to pas
157. ite buffer operation is normally transparent however there is indirect control over the write buffer using the MPU If a memory region is specified as non cacheable and non bufferable in the MPU the write buffer is effectively bypassed 3 6 ARM946E S Embedded Trace Macrocell ETM9 An ETM9 module is connected at the ARM946E S This module permits debugging support for data and instruction traces in the ERTEC 400 The module contains all signals required by the processor for the data and instruction traces The ETM9 module is operated by means of the JTAG interface The trace information is provided outwards to the trace port via a FIFO memory A more detailed description is in section 21 1 Preliminary Users Manual A17812EE1V1UM00 49 Chapter 3 CPU Function 3 7 ARM946E S Registers Beside the working registers that are part of the ARM9E S core architecture the ARM946E S proces sor system includes a CP15 coprocessor with a register set for system control These registers are used for functions like Cache type and cache memory area configuration Tightly coupled memory area configuration Memory protection unit setting for various regions and memory types Assignment of system option parameters Configuration of Little Endian or Big Endian operation Table 3 1 summarizes the function of the CP15 coprocessor registers and their access options Notes 1 Remark 50 Register Table 3 1 15 Coproc
158. k on ERTEC 400 provides four 10 100 Mbps Ethernet channels due to special control features and the large Communication SRAM of 192 kBytes all channels support real time and isochronous real time communication Connection to an Ethernet network is realized with external PHYs that are either wired to four RMII interfaces 4 channel operation or two MII interfaces 2 channel operation PCI Interface ERTEC 400 has a 32 bit 66 MHz PCI R2 2 compatible interface host bridge functionality is provided and the PCI clock is applied externally On the PCI bus side the interface can act as a master or a target on the AHB side it can act as master or slave The PCI configuration register set can be programmed from PCI or AHB bus i e ARM946E S side The interface supports PCI power management according to the V1 1 specification 3 3 V and 5V PCI environments can be used Local Bus Interface The PCI interface pins are shared with a local bus interface LBU to an external host controller it offers 21 address bits and 16 data bits ERTEC 400 is a slave with respect to this interface The external host can look through four configurable in size and position windows into ERTEC 400 s address space Read write control is either done with separate read and write lines or with a common read write line Preliminary Users Manual A17812EE1V1UM00 9 10 11 12 13 14 15 Chapter 1 Introduction AHB to APB Bridge The slower
159. ks into the ERTEC 400 memory space for a given page range and offset register setting The example is based on a 1 MByte segment size which can be achieved by connecting the lower 20 address lines of the external host processor to ERTEC 400 as shown in Figure 9 1 Selection of the segment is done by connecting the host address lines A 21 20 to the segment select inputs LBU SEG 1 0 of ERTEC 400 Table 9 4 Local Bus Unit Address Mapping Example Host address ERTEC 400 Memory area seen LBU_SEG 1 0 LBU 19 0 internal address DY NOSI 0 0000H 2000 0000H Range 0010 0000H Lower 1 MByte of external Offset 2000 0000H SDRAM F FFFFH 200F FFFFH 0 0000H 1010 0000H Setting Lower 128 kBytes of commu nication SRAM Range 0002 0000H 1 FFFFH 1011 FFFFH Offset 1010 0000H 2 0000H Dioon Mirrors of lower 128 kBytes of communication SRAM F FFFFH 1011 FFFFH 0 0000H 300000004 l Rower tae kBytes of external memory connected to CS_PERO_N Range 0002 0000H 10 1FFFFH 3001FFFFH Offset 3000 0000H 2 0000H 3000 0000 Mirrors of lower 128 kBytes of external memory connected to CS_PERO_N F FFFFH 3001 FFFFH 0 0000H 4000 0000H 16 kBytes of APB peripherals Range 0000 4000H tij O3FFFH 40003FFFH Offset 4000 0000H vat TT Mirrors of 16 kBytes of APB peripherals F FFFFH 4000 3FFFH Preliminary Users Manual A17812EE1V1UM00 107 Figure 9
160. l register 1 4000 2208H SSPDR Rx Tx FIFO data register 4000 220CH SSPSR SPI status register 4000 2210H SSPCPSR SPI clock prescale register 4000 2214H SSPIIR SSPICR Interrupt identification register read Interrupt clear register write 4000 2218H 4000 22FFH Reserved Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary Users Manual A17812EE1V1UM00 143 Chapter 13 Synchronous Serial Interface SPI 13 2 Detailed SPI Register Description Figure 13 2 SSPCRO SPI Control Register 0 1 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SCR DSS 4000 2200H 0000H Bit position Bit name Function SCR Selects serial transmission speed for master mode The value that has been programmed in this field determines transmission speed via the following formula SOMH __ SCLKOUT CpSDRVx 14 SCR SPH Selects phase of transmitted bits This bit is only applicable to Motorola SPI frame format Serial transmission phase Received MSB is expected immediately after frame signal goes low initial value Received MSB is expected half a clock period after frame signal goes low SPO Selects serial clock output polarity This bit is only applicable to Motorola SPI frame format Serial clock output polarity Received bits are latched on the rising edge of SCLKIN OUT outgo
161. llows Weight in data notation Left is high order column right is low order column Active low notation N capital letter before or after signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary Decimal XXXx Hexadecimal or Ox XXXX Prefixes representing powers of 2 address space memory capacity k kilo 210 1024 M mega 220 10242 1 048 576 G giga 230 1024 1 073 741 824 Data Type Word 32 bits Halfword 16 bits Byte 8 bits Preliminary User s Manual A17812EE1V1UMO00 5 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Document Name Document No ERTEC 400 Preliminary Data Sheet A17364EE1V1DS00 ERTEC 400 Preliminary User s Manual Boot Mode Description TPS HE A 1065 CB 12 Family L M Type Block Library 1535 4 0 00 CB 12 Family L M Type Product Data A14937EJ3VODMOO ARM946E S Technical Reference Manual DDI0201CNete ARMO9E S Rev 1 Technical Reference Manual DDIO0165BNote ARM AMBA Specification Rev 2 0 IH10011 ANote AHB PCI Bridge Rev 2 5 2002 Fujitsu Siemens Computers ARM PrimeCell UART PL010 Technical Reference Manual DDI0139BM te
162. mpatibiliy problems Table 5 3 Memory Map and Used Address Range Example 1 2 Available Segment Contents Address range Size Address range Size Boot ROM 0000 0000H a 8 kBytes 90 0000 1FFFH g Internal SRAM OFFF FFFFH 236 MBytes Not used 1000 0000H Not disclosed Not disclosed 1 MBytes 100F FFFFH Not used 1 IRT switch 1010 0000H 1010 0000H 1012 FFFFH 192 kBytes 1FFF FFFFH 239 MBytes Not used 2000 0000H 2000 0000H 23FF FFFFH 64 MBytes 2 SDRAM 2FFF FFFFH 256 MBytes Not used 3000 0000H 3000 0000H 303F FFFF 4 MBytes 3 Parallel Flash 3FFF FFFFH 256 MBytes Not used Internal boot 4000 0000H 4000 0000H ROM 4000 1FFFH 4000 1FFFH 4000 2000H Queis 32 Bytes i 4000 201 Timers 4000 20FFH 256 Bytes Not used 4000 2100H eta 28 Bytes 4000 211BH Watchdog 4000 21 256 Bytes Not used 4 4000 2200 4000 2200 SI 4000 22FFH 256 Bytes 4000 22FFH PSS EMES 4000 2300H 4000 2300H UART1 4000 23FFH 256 Bytes 4000 23FFH 256 Bytes 4000 2400H 4000 2400H UART2 4000 24FFH 256 Bytes 4000 24FFH 256 Bytes 4000 2500H 32 Bytes 7 4000 251 GPIO 4000 25FFH 256 Bytes Not used 56 Preliminary Users Manual A17812EE1V1UMOO Segment Table 5 3 Contents Chapter 5 ERTEC 400 Memory Memory Map and Used Address Range Example 2 2 Available Used Address range Size Address range Size System Control
163. nating accesses are in the respective page no page miss can occur The asynchronous memory controller has the following features 8 bit 16 bit or 32 bit data bus width can be selected 4chip select signals Maximum of 16 MBytes per chip select can be addressed Different access timing can be assigned for each chip select Ready signal can be assigned differently for each chip select Chip select CS PERO N can be used for boot operations from external memory Data bus width of the external boot memory selected via the BOOT 2 0 input pins Default setting Slow timing for boot operation Timeout monitoring can be assigned Supports the following asynchronous devices SRAM Flash memory ROM External I O devices Care must be taken when configuring the asynchronous access timing The maximum asynchronous access duration must not exceed the time between two refresh cycles because otherwise an SDRAM refresh may get lost It must also be taken into account that a 32 bit access to an 8 bit external device requires four sequential accesses that are not interruptible for an SDRAM refresh 60 Preliminary User s Manual 17812 1 10 00 6 1 Address Assignment of EMIF Registers Chapter6 External Memory Interface EMIF The EMIF registers are 32 bits wide The registers can be written to with 32 bit accesses only Table 6 2 gives an overview of all external memory interface control registers Address 700
164. nitial reset values to these bits 120 Preliminary Users Manual A17812EE1V1UMOO Chapter 11 General Purpose I O GPIO 11 2 Detailed GPIO Register Description Figure 11 2 GPIO_IOCTRL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO IOCTRL 4000 2500H FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO IOCTRL Bit position Bit name Function GPIO IOCTRL Controls if GPIO pin is used as input or output pin GPIO IOCTRLn GPIO pin direction control GPIO IOCTRL is used as output is used as input initial value Figure 11 3 GPIO OUT Hegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO OUT 4000 2504H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIO OUT Bit position Bit name Function GPIO OUT Data written into this register is output at the GPIO pins on a bit by bit basis under the assumption that the pin is actually configured as output GPIO OUT GPIO OUTn GPIO output data Op Output low level at GPIOn pin initial value Tp Output high level at GPIOn pin Preliminary Users Manual A17812EE1V1UM00 121 Chapter 11 General Purpose I O GPIO Figure 11 4 GPIO IN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value GPIO IN 4000 2508H xxx xxxxH 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function GPIO IN This register reflects th
165. nitial value Incorrect access was a write access Preliminary Users Manual A17812EE1V1UM00 185 Chapter 17 System Control Registers Figure 17 13 AHB Timeout Master Register QVZ AHB M 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARM LBU reserved a Bit position Bit name Function Reserved IRT Monitors whether the IRT switch was master during the incorrect multilayer AHB access IRT bus mastership IRT switch was not bus master initial value IRT switch was bus master LBU PCI Monitors whether the LBU PCI block was master during the incorrect multilayer AHB access LBU PCI LBU PCI block was not bus master initial value LBU PCI block was bus master ARM946E S Monitors whether the ARM946E S CPU core was master during the incorrect multilayer AHB access ARM946E S ARM946E S was not bus master initial value ARM946E S was bus master 186 Preliminary User s Manual A17812EE1V1UMOO Chapter 17 System Control Registers Figure 17 14 APB Timeout Address Register QVZ_APB_ADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value QVZ_APB_ADR 4000 2634H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QVZ_APB_ADR f QVZ_APB_ADR 31 0 QVZ Holds the address in case of an incorrect APB access Figure 17 15 EMIF Timeout Address Register QVZ_EM
166. nter Res register is cleared again at the next clock cycle The current count value can be read out by a 32 bit read access Though an 8 bit or 16 bit read access is possible it is not useful because it can result in an inconsistency in the read count values Note The maximum input frequency for the F_CLK pin is one quarter of the APB clock In the event of a quartz failure on ERTEC 400 a minimum output frequency between 40 and 90 MHz is set at the PLL This results in a minimum APB clock frequency of 40 MHz 6 6 6666 MHz To prevent a malfunction in the edge evaluation the F CLK frequency must not exceed a quarter of the minimum APB clock frequency thus 6 66 MHz 4 1 6666 MHz The figure below shows the function blocks of the F timer Figure 15 10 F Timer Block Diagram CONFIG 4 3 32 bit Down Counter F COUNTER EN EN F Counter Val Read F Counter Val F_CLK XXXX55AAH Counter Res to APB Bus Preliminary Users Manual A17812EE1V1UM00 165 Chapter 15 ERTEC 400 Timers 15 2 2 Address Assignment of F Timer Registers The F timer registers are 32 bits in wide The registers should be read or written to with 32 bit accesses only in order to avoid inconsistencies Table 15 3 Address Assignment of F Timer Registers 4000 2700H F Counter Val 32 bit R 0000 0000H F timer value register 4000 2704H F Counter Res 32bit W 0000 0000H F timer reset register 15 2 3 Detailed F
167. ntification register ERTEC 400 4000 2604H BOOT REG Boot mode pin register 4000 2608H CONFIG REG Config pin register 4000 260CH RES CTRL REG 0000 0100H Control register for ERTEC 400 reset 4000 2610H RES STAT REG 0000 0004H Status register for ERTEC 400 reset 4000 2614H 4000 2618H PLL STAT REG CLK CTRL REG 32 bit 0007 0005H 0000 0001H Status register for PLL FIQ3 Control register for ERTEC 400 clock 4000 261CH 4000 26H20 4000 26H24 PM State Req REG PM State Ack REG PME REG 32 bit 32 bit 0000 0000H 0000 0000H 0000 0000H Required power state of the PCI host Current power state of ERTEC 400 Power management event PME 4000 2628H QVZ AHB ADR 0000 0000H Address of incorrect addressing on multilayer AHB 4000 262CH QVZ AHB CTRL 0000 0000H Control signals of incorrect addressing on multilayer AHB 4000 2630H QVZ AHB M 0000 0000H Master detection of incorrect addressing on multilayer AHB 4000 2634H 4000 2638H QVZ APB ADR QVZ EMIF ADR 0000 0000H 0000 0000H Address of incorrect addressing on APB Address that leads to timeout on EMIF 4000 263CH PCI RES REQ FFFF 0002H Request register for placing a SW reset request on the PCI bridge 4000 2640H PCI RES ACK 0000 0000H ACK for display of an implemented SW reset request 4000 2644H MEM SWAP 0000 0000H Memory swapping in Segment 0 be
168. of an access violation by PCI or LBU as an AHB master an interrupt request is also enabled and stored in the IRT macro The interrupt is issued to the PCI LBU bus as an INTA N interrupt In case of an access violation by the PCI user Bit 0 for write accesses or Bit 1 for read accesses is set in the AHB status register of the PCI bridge and the INTA N interrupt is activated If more than one AHB master causes an access violation simultaneously within a single AHB clock cycle only the violation of the highest priority AHB master is protocoled in the registers see Table 4 1 Diagnostic registers QVZ AHB ADR QVZ AHB CTRL and QVZ AHB M remain locked for subsequent access violations until the QVZ AHB CTRL register has been read 20 2 APB Bus Monitoring The APB address space is monitored on the APB bus If incorrect addressing is detected in the APB address space access to the APB side and AHB side is terminated with an OKAY response because the APB bus does not recognize response type signalling An FIQ interrupt is triggered at input FIQ1 of the ARM946E S interrupt controller The incorrect access address is placed in the QVZ APB ADR system control register The QVZ APB ADR system control register is locked for subsequent address violations until it has been read Preliminary User s Manual A17812EE1V1UMOO0 203 Chapter 20 Address Space and Timeout Monitoring 20 3 External Memory Interface Monitoring In case of the EMIF the external RDY
169. of the CP15 control register the D cache can be enabled by setting Bit 2 of the CP15 control register Access to this area is blocked if the cache is not enabled When enabled the caches can be accessed with the full CPU speed i e with a maximum of 150 MHz 3 3 Tightly Coupled Memories A 4 kBytes data TCM D TCM is implemented in the ARM946E S processor of ERTEC 400 A TCM is a mostly small portion of memory that is close to the core that can be accessed with full CPU speed but that is not subjected to automatic control mechanisms like a cache It is typically used to keep the data for time critical routines The D TCM is locked after a reset it can be mapped to various positions in the address space of the ARM946E S and must be used together with a region of the memory protection unit The D TCM can be enabled by setting Bit 16 of the CP15 control register In addition the address position of the D TCM must be set in the Tightly Coupled Memory Region register 48 Preliminary Users Manual A17812EE1V1UMOO0 Chapter 3 CPU Function 3 4 Memory Protection Unit MPU The memory protection unit enables the user to partition the address space of the ARM946E S proces sor into several regions and to assign various attributes to these regions A maximum of 8 regions of variable size can be set If regions overlap the attributes of the higher region number apply The possible settings for each region are as follows Base address of region
170. of the IRQ FIQ interrupt inputs must not be changed because the ICU can otherwise no longer correctly assign the EOI commands An IRQ FIQ request is accepted by the CPU by reading the IRVEC FIVEQ register This register contains the binary coded vector number of the highest priority interrupt request at the moment Each of the two interrupt vector registers can be referenced using two different addresses The interrupt controller interprets the reading of the vector register with the first address as an interrupt acknowledge This causes the sequences for this interrupt to be implemented in the ICU logic Reading of the vector register with the second address is not linked to the acknowledge function This is primarily useful for the debugging functions in order to read out the content of the interrupt vector register without starting the acknowledge function of the interrupt controller 7 7 IRQ Interrupts as FIQ Interrupt Sources The interrupts of the FIQ interrupt controller are used for debugging monitoring of address space accesses and high priority switch functions High priority IRT interrupt IRQO_SP can be used as an FIQ by means of interrupt input FIQ 6 Selection of the high priority interrupt source is specified in the IRQO_SP interrupt controller of the IRT switch IRQ interrupts No 6 and 7 are the interrupts of embedded ICE RT communication The UART can also be used as a debugger in place of the ICE An effective real time deb
171. on Receive FIFO not empty indication Receive FIFO is empty initial value Receive FIFO is not empty TNE Transmit FIFO not full indication Transmit FIFO not full indication 0 Transmit FIFO is full initial value Transmit FIFO is not full TFE Transmit FIFO empty indication Transmit FIFO empty indication zai Transmit FIFO is not empty initial value Transmit FIFO is empty 148 Preliminary Users Manual A17812EE1V1UMOO Chapter 13 Synchronous Serial Interface SPI Figure 13 6 SSPCPSR SPI Clock Prescale Register 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 Address Initial value Bit position Bit name Function Reserved CPSDVSR Sets the divisor for the SPI clock prescaler CPSDVSR is always an even CPSDVSR number even when this field is written with an odd number bit 0 returns a 0 The resulting SPI clock frequency can be calculated with the formula in Figure 13 2 Figure 13 7 SSPIIR SSPICR SPI Interrupt Identification and Clear Register 14 11 1 Address Initial value Bit position Bit name Function Reserved RORIS SPI receive FIFO overrun interrupt status SSP_ROR_INTR status indication SSP_ROR_INTR not active initial value SSP ROR INTR active TIS SPI transmit FIFO service request interrupt status SSP TX INTR status indication 0 SSP_TX_INTR not active initial value SSP_TX_INTR active RIS SPI receive FIFO service request interrupt status SSP_RX_INTR
172. or Timer 0 Reload Timer 0 No effect initial value Timer is loaded with the reload register value Note Reload is executed irrespective of the Run xStop bit Even though this bit can be read back it only has an effect at the instance of writing Writing a value of 1p to this bit is sufficient to trigger the timer 0 1 edge is not needed Run xStop Starts and stops the counter in Timer oNete Run xStop Timer 0 start stop Run xStop Timer 0 is stopped initial value Note If Timers 0 and 1 are cascaded the Run xStop bit setting of Timer 0 is irrelevant 158 Preliminary User s Manual A17812EE1V1UMOO Chapter 15 ERTEC 400 Timers Figure 15 3 Control Status Register 1 CTRL_STAT1 1 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2004H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 Cas Relo reserved cad Sta res ad 1044 tus xStop ing Mode Bit position Bit name Function Reserved Cascading Selects if Timers 0 and 1 are cascaded Cascading Cascading of Timers 0 and 1 Timers 0 and 1 are not cascaded initial value Timers 0 and 1 are cascaded Status Timer 1 status indication Status Timer 1 has not expired initial value Timer 1 has expired Note Note This bit can only be read as 1 when the Run xStop bit is set to 1 Reserved Reload Mode Timer 1 Reload mode selection Timer 1 stops at value 000
173. or Timer 1 TIM1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 0 This register holds the current counter value for Timer 1 164 Preliminary User s Manual A17812EE1V1UMOO Chapter 15 400 Timers 15 2 F Timer An F timer is integrated in ERTEC 400 in addition to the system timers This timer works independently of the system clock and can be used for fail safe applications for example The F timer is operated with an external clock that is supplied via the F_CLK input pin The following signal pins are available for the F timer on ERTEC 400 Table 15 2 F Timer Pin Functions F_CLK F_CLK for F timer total 15 2 1 Functional Description of the F Timer The asynchronous input signal of the external independent time base is applied at a synchronization stage via the F CLK input pin To prevent occurrences of metastable states at the counter input the synchronization stage is implemented with three flip flop stages The count pulses are generated in a series connected edge detection All flip flops run at the APB clock of 50 MHz The F Counter Val register is reset using an asynchronous block reset or by writing the value xxxx 55AAH x means don t care to the F counter register F Counter Res The next count pulse sets the counter to FFFF FFFFH and the counter is decremented at each additional count pulse The F Cou
174. ore GND IO PME N LBU RDY N GNT N LBU CFG CRS DV P3 RX DV P1 RXD P2 0 RXD 1 0 INTA N LBU IRQO N AVDD PCI M66EN A9 D21 TX EN P3 TX ERR P1 G2 A8 D22 VDD IO G4 A17 BOOT1 1 VDD IO G5 GND IO E2 A5 G6 GND Core E4 14 17 GND Core E5 VDD Core G18 CRS DV P2 CRS P1 E6 GND Core G19 CRS DV P1 RX DV PO E7 ADOG LBU DBO6 G21 AGND PCI E8 AD11 LBU DB11 G22 TXD P2 1 TXD P1 1 E9 AD13 LBU DB13 H1 A11 E10 PAR LBU WR N H2 A10 E11 AD18 LBU 08 H4 VDD Core E12 AD20 LBU_AB10 H5 A20 CONFIG1 E13 AD22 LBU_AB12 H6 A19 CONFIGO E14 AD26 LBU_AB18 H17 leave open Preliminary Users Manual A17812EE1V1UM00 23 Table 1 1 Chapier 1 Introduction Pin Configuration of ERTEC 400 3 5 oe Pin Name SUN Pin Name H18 RX CLK P1 N2 DO H19 CRS DV PO CRS PO N4 D18 H21 TXD P2 0 TXD P1 0 N5 VDD Core TX EN P2 TX EN P1 N6 D16 A13 GPIO4 12 SMI_MDIO A18 BOOT2 VDD Core A22 CONFIG3 TXD PO 1 TXD PO 1 A21 CONFIG2 RXD PO 0 RXD PO 0 TX CLK P1 D1 RX ER P2 RX ER P1 D2 VDD Core VDD Core RXD P1 1 RXD PO 3 D19 VDD IO GND IO RAS SDRAM N leave open CS SDRAM N VDD Core VDD Core GPIO5 A23 CONFIG4 TX PO TX GND Core TXD_PO0 0 TXD_PO0 0 TX_CLK_PO VDD IO RX ER PO RX ER PO RX CLK PO RXD P1 0 RXD PO 2 GND IO D20 VDD IO GND IO CLK SDRAM VDD Core L4 CAS SDRAM
175. ore clock frequency 100 MHz CPU core clock frequency CONFIG 4 3 150 MHz CPU core clock frequency reserved Local bus interface selected CONFIG2 PCI interface selected 50 MHz clock input to REF CLK pin 25 MHz clock input to REF CLK pin Clock input via CLKP A and CLKP B Clock input via REF CLK pin CONFIG1 CONFIGO Preliminary Users Manual A17812EE1V1UM00 201 Chapter 19 Reset Logic of ERTEC 400 MEMO 202 Preliminary User s Manual 17812 1 10 00 Chapter 20 Address Space and Timeout Monitoring Several monitoring mechanisms are incorporated in ERTEC 400 for detection of incorrect addressing illegal accesses and timeout The following blocks are monitored AHB bus APB bus PCI slave The monitoring mechanisms for these blocks will be described in detail in the subsequent chapters 20 1 AHB Bus Monitoring Separate address space monitoring is implemented for each of the three AHB masters If an AHB master addresses an unused address space the access is acknowledged with an error response and an FIQ interrupt is triggered at input FIQ2 of the ARM946E S interrupt controller The incorrect access address is stored in the QVZ AHB ADR system control register and the associated access type HBURST HSIZE HWRITE is stored in the QVZ AHB CTRL system control register The master that caused the access error is stored in the QVZ AHB M register In case
176. ot have to operate the SSPTXD output in slave mode MS Master slave mode selection Device is master initial value Device is slave SSE Synchronous serial port enable bit Synchronous serial port enable SPI is disabled initial value SPI is enabled LBM Activates the loop back mode Loop back mode activation 0 Loop back mode is disabled initial value Loop back mode is enabled the output of the transmit shift register is internally connected to the input of the receive shift register 146 Preliminary Users Manual A17812EE1V1UMOO Chapter 13 Synchronous Serial Interface SPI Figure 13 3 SSPCR1 SPI Control Register 1 2 2 Bit position Bit name Function RORIE Receive FIFO overrun interrupt enable RORIE Receive FIFO overrun interrupt enable FIFO overrun display interrupt SSP ROR INTRNete 1 js disabled when this bit is deleted the SSP INTR interrupt is also deleted if this interrupt was currently being enabled initial value FIFO overrun display interrupt SSP ROR INTR is enabled TIE Transmit FIFO interrupt enable Transmit FIFO interrupt enable Transmit FIFO half full or less interrupt SSP TX INTRNete 2 is disabled initial value Transmit FIFO half full or less interrupt SSP TX INTR is enabled RIE Receive FIFO interrupt enable Receive FIFO interrupt enable Receive FIFO half full or less interrupt SSP INTRNete is disabled init
177. ote These optional pins are not supported on ERTEC 400 For connector type pinning signal description and hardware circuitry for a standard JTAG interface for the ARM Multi ICE debugger for example refer to the documents listed on page 6 In addition to the standard JTAG connector the pins can also be connected with the trace signals at a single connector For connectors pinning and hardware circuitry for JTAG signals at the Trace interface please refer to the documents listed on page 6 21 5 Debugging via UART1 If UART1 is not used for user specific tasks it can also be used as a debugging interface 208 Preliminary Users Manual A17812EE1V1UMO00
178. peripherals of ERTEC 400 are connected to an internal 32 bit 50 MHz APB bus that can be accessed via an AHB to APB bridge from the AHB side From the programmers point of view these peripherals are memory mapped like any other Boot ROM ERTEC 400 has 8 kBytes of 32 bit wide boot ROM it is pre defined with a boot loader program that supports various external boot sources external Flash via EMIF serial Flash or EEPROM via SPI PCI LBU with an external host and UART1 Selection of boot sources is done via the BOOT 2 0 configuration pins GPIO Block ERTEC 400 has a total of 32 GPIO pins that are individually programmable as input or output Four of these GPIOs can be used as interrupts 16 of these GPIOs are shared with the UARTs and the SPI UART Two identical UARTs can be used for asynchronous serial communication They are based on the ARM prime cell PLO10 and are widely 16550 compatible 2 data lines and 3 handshake lines are used The internal 50 MHz clock is used for the UART operation and with a baud rate generator standard baud rates up to 115 kbps can be selected SPI The SPI is used for synchronous serial communication according to Motorola TI and National quasi standards Frame size protocol and speed are software programmable The maximum transmission speed is 25 MHz in master mode and 4 16 MHz in slave mode The SPI is based on the ARM prime cell PLO21 Timers Watchdog ERTEC 400 has three timers and two watchdogs T
179. power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device All other product brand or trade names used in this publication are the trademarks or registered trademarks of their respective trademark owners Product specifications are subject to change without notice To ensure that you have the latest product data please contact your local NEC Electronics sales office 2 Preliminary Users Manual A17812EE1V1UMOO The information contained in this document is being issued in advance of the production cycle for the product The parameters for the product may change before final production or NEC Electronics Corporation at its own discretion may withdraw the product prior to its production Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties b
180. pt sources that can be prioritized the FIQ interrupt controller can handle up to 8 sources Most interrupt sources are assigned to internal peripheral units however GPIO pins can be used as interrupt sources as well For easy debugging ERTEC 400 is equipped with an ETM9 debug and trace module In addition to the on chip debug capabilities of the ARM946E S core the ETM9 module allows instruction and data trace The ETM cell can be operated in full rate mode as long as the CPU core frequency is 50 or 100 MHz otherwise half rate mode must be selected Bus System ERTEC 400 s internal bus structure is made up of a multilayer AHB bus and an APB bus Both run at a maximum speed of 50 MHz The multilayer AHB bus offers multimaster capability and up to three simultaneous bus communi cation processes between masters and slaves Thus a very high availability of the AHB bus is achieved Potential bus masters are the ARM core the PCI LBU interface and the IRT switch slaves are the external memory interface the PCI interface the IRT switch interrupt controller on chip SRAM and the AHB to APB bridge The APB bus connects to the less demanding peripherals like UARTs SPI GPIOs etc On chip Memories ERTEC 400 has two categories of on chip memories the caches and the data TCM that are regarded as belonging to the core and SRAM as well as ROM that are on chip but off core The on chip SRAM has a size of 8 kBytes and an 32 bit organization It i
181. r Rising edge Group interrupt of several blocksNote 2 EMIF QVZ PCI Slave QVZ PLL Loss state PLL Lock state IRT Switch IRQ_IRT_END Rising edge End of the IRT phase cannot be masked in IRT IRT Switch IRQ_LOW_WATER Rising edge Low water mark is violated Selectable Configurable from IRQ Rising edge Default IRQO SP Selectable Configurable from IRQ Rising edge User programmable by IRQ Notes 1 Access to a non existing address is detected by the individual function blocks of ERTEC 400 and triggers an interrupt pulse with duration Tp 2 50 MHz For evaluation of this interrupt the connected FIQ input must be specified as an edge triggered input 2 SeePLL Stat Reg register description in Chapter 17 2 Preliminary User s Manual A17812EE1V1UMOO0 73 Chapter 7 Interrupt Controller An interrupt controller for 16 interrupt inputs is implemented for IRQ Of the 16 IRQ inputs 2 IRQ sources can be selected for processing as fast interrupt requests The assignment is made by specifying the IRQ number of the relevant interrupt input in the FIQ1REG FIQ2REG register The interrupt inputs selected as FIQ must be disabled for the IRQ logic All other interrupt inputs can continue to be processed as IRQs Twelve IRQ interrupt inputs are assigned to internal peripherals of the ERTEC 400 and four IRQ interrupt inputs are available for external events as they are route
182. r each PHY RES PHY can additionally be gated with GPIO pins 154 Pin Name SMI MDC Table 14 2 MII Interface Pin Functions Function Serial management interface clock Number of pins SMI MDIO Serial management interface data input output RES PHY N TXD P0 3 0 Reset signal to PHYs Transmit data port O bits RXD 3 0 Receive data port 0 bits TX EN PO Transmit enable port 0 CRS RX ER PO Carrier sense port 0 Receive error port 0 TX ERR PO Transmit error port 0 RX DV PO COL PO Receive data valid port 0 Collision port 0 RX CLK PO Receive clock port 0 TX CLK PO TXD P1 3 0 Transmit clock port 0 Transmit data port 1 bits RXD_P1 3 0 Receive data port 1 bits TX_EN_P1 CRS_P1 Transmit enable port 1 Carrier sense port 1 RX_ER_P1 Receive error port 1 TX_ERR_P1 RX_DV_P1 Transmit error port 1 Receive data valid port 1 COL_P1 Collision port 1 RX_CLK_P1 1 Receive clock port 1 Transmit clock port 1 Preliminary User s Manual 17812 1 10 00 Chapter 15 ERTEC 400 Timers ERTEC 400 has two types of timers integrated Timer 0 and Timer 1 are two almost identical but cascadable timers that work with an internal clock Timer F however works from an external clock source All timers can interrupt the processor 15 1 Timer 0 and Timer 1 Two independent timers are
183. reload capability Start stop continue functions and interrupts Cascadable to a 64 bit timer and additional 8 bit prescaler selectable Timers run on 50 MHz internal clock Additional 32 bit fail safe F Timer Runs from external clock F CLK Watchdog 32 bit count down watchdog 0 with output pin WDOUTO N 36 bit count down watchdog 1 Load reload function Write protection for watchdog Watchdog interrupt on the FIQ interrupt controller Preliminary Users Manual A17812EE1V1UMOO Chapter 1 Introduction 1 3 Ordering Information Device Part Number Package 800232 1 012 2 400 P FBGA304 19 19 mm 800232 1 012 2 Remark Products with A at the end of the part number are lead free products Preliminary Users Manual A17812EE1V1UM00 21 Chapier 1 Introduction 1 4 Pin Configuration Figure 1 1 Pin Configuration of ERTEC 400 304 Pin Plastic FBGA 19 mm x 19 mm OO 00000000000000000000 AAWURNL JGECA INDEX MARK ABY VT P MK H Table 1 1 Pin Configuration of 400 1 5 Pin Pin Number Pin Name Number Pin Name ADO1 LBU DBO1 GND IO VDD IO AO ADO7 LBU DBO07 VDD IO ADO2 LBU DB02 ADOS LBU AD12
184. ress Assignment of UART1 2 Registers The UART registers are 8 bits in width When they are accessed with 16 or 32 bit read operations the upper bits are undefined The following Table 12 3 gives an overview of the address assignment for the UART1 2 registers Address 4000 2300H Table 12 3 Address Assignment of UART1 2 Registers Register Name UARTDR1 Initial value Description Read write data from interface 4000 2304H UARTRSR1 UARTECR1 Receive status register when read error clear register when written 4000 2308H UARTLCR H1 Line control register high byte 4000 230CH UARTLCR 1 Line control register middle byte 4000 2310H UARTLCR L1 Line control register low byte 4000 2314H UARTCR1 Control register 4000 2318H UARTFR1 Flag register 4000 231CH 4000 2320H 4000 23FFH UARTIIR1 UARTICR1 Interrupt identification register read Interrupt clear register write Reserved 4000 2400H 4000 2404H UARTDR2 UARTRSR2 UARTECR2 Read write data from interface Receive status register when read error clear register when written 4000 2408H 4000 240CH UARTLCR H2 UARTLCR M2 Line control register high byte Line control register middle byte 4000 2410H UARTLCR L2 Line control register low byte 4000 2414H 4000 2418H UARTCR2 UARTFR2 Control register Flag register 4000 241CH 4000 2420H 4000 24
185. ronics products means any product developed or manufactured by or for NEC Electronics as defined above M5D 02 11 1 Preliminary User s Manual A17812EE1V1UMOO For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 Dusseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0 511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 M nchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691 133 Succursale Francaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 3067 5800 Sucursal Espa a Juan Esplandiu 15 28007 Madrid Spain Tel 091 504 2787 Tyskland Filial Taby Centrum Entrance S 7th floor 18322 Taby Sweden Tel 08 638 72 00 Filiale Italiana Via Fabio Filzi 25 20124 Milano Italy Tel 02 667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The Netherlands Tel 040 265 40
186. rrent IRQ request to the IRQ interrupt controller the value that is written to this register does not matter Figure 7 11 FIQEND End of FIQ Interrupt Signaling Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value don t care 5000 0028H undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 don t care Don t care 81 0 W A write to this register indicates the completion of the interrupt service routine associated with the current FIQ request to the FIQ interrupt controller the value that is written to this register does not matter Preliminary Users Manual A17812EE1V1UM00 87 Chapter 7 Interrupt Controller Figure 7 12 FIQPRO 7 FIQ Interrupt Priority Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 0 8 7 6 5 4 3 2 1 Bit position Bit name R W Function Reserved FIQPRO 7 2 0 Sets priority of the fast interrupt request at inputs FIQO to FIQ7 of the FIQ interrupt controller FIQPRO 7 2 0 FIQ Interrupt request priority FIQPRO 7 Assigns priority O highest to FIQ interrupt FIQO 7 Assigns priority 7 lowest to FIQ interrupt FIQO 7 initial value Figure 7 13 FIQISR FIQ Interrupt In Service Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit Function Reserved FIQISR 7 0 Individual indication of
187. rs Figure 17 8 PCI Power State Request Register PM_STATE_REQ_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 261CH 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d PM STA reserve TE REQ Bit position Bit name Function Reserved PM STATE REQ Indicates the power state that was requested by the PCI host PM STATE REQ Requested power state PM STATE Power state DO requested initial value REQ Power state D1 requested Power state D2 requested Power state D3 hot requested Figure 17 9 PCI Power State Acknowledge Register STATE ACK REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PM STA reserved TE ACK Bit position Bit name Function Reserved PM STATE ACK Indicates the current power state of ERTEC 400 PM STATE ACK Current power state of ERTEC 400 PM STATE Current power state is DO initial value _ACK Current power state is D1 Current power state is D2 Current power state is D3 hot Preliminary Users Manual A17812EE1V1UMOO 183 Chapter 17 System Control Registers Figure 17 10 PME Register PME REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 2624H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Bit name Function Reserved PME Setting this bit activates the PCl bu
188. ry User s Manual 17812 1 10 00 103 Chapter 9 Local Bus Unit LBU If usage of LBU WR N as common read write control line is configured the unused LBU RD N input must be pulled to its inactive high level with a pull up resistor The polarity of the ready signal is set via the LBU POL RDY input LBU POL RDY 0 LBU RDY N low active LBU POL RDY 1 LBU RDY N high active LBU RDY N is a tri state output and must be pulled to its normally ready level by an external pull down or pull up resistor During an access from an external host via the LBU interface to ERTEC 400 the RDY N output is first driven to its inactive level first When ERTEC 400 is ready to take or to provide data LBU RDY N will be active for approximately 20 ns 50 MHz internal clock period After that LBU RDY N is switched back to tri state and the external pull down or pull up generates the ready state again The four pages that were defined using the page registers are addressed via the SEG 1 0 inputs LBU SEG 1 0 00 LBU PAGEO addressed LBU SEG 1 0 01 PAGE 1 addressed LBU SEG 1 0 10 LBU 2 addressed LBU SEG 1 0 11 PAGES addressed 104 Preliminary Users Manual A17812EE1V1UMOO Chapter 9 Local Bus Unit LBU 9 1 Page Size Setting The page size of each page is set in the LBU Pn RG H and LBU Pn RG L range registers n 0 to 3 Together the two page range registers yield a 32 bit address register The size of t
189. ry User s Manual A17812EE1V1UMOO0 199 Chapter 19 Reset Logic of ERTEC 400 19 2 Watchdog Reset The watchdog reset involves software monitoring with hardware support The monitoring process is based on a time set in the watchdog timer reload registers Re triggering and thus reloading the timer with a specified reload value prevents the watchdog reset from being triggered If the timer is not re triggered the watchdog reset is activated after the timer expires if the watchdog function is enabled with the WD RES FREI bit in the reset control register RES CTRL REG As the reset pulse that is generated by the watchdog is too short the watchdog reset is extended in ERTEC 400 by means of a programmable pulse stretching PV The maximum duration that can be programmed in the RES REG register is approximately 5 1 us in case of a 50 MHz APB clock The watchdog reset resets the complete ERTEC 400 circuit The watchdog event can signalled to the host system via the GPIO15 pin if this pin was configured to serve as the WDOUTO N pin As in the case of a hardware reset a bit is set in the reset status register RES STAT REG This bit remains unaffected by the triggering reset function This register can be evaluated after a restart 19 3 Software Reset A software reset can be triggered in ERTEC 400 by setting the XRES_SOFT bit in the reset control register RES REG this bit is not stored The subsequent reset will be extended in the
190. s 1 2 Segment Contents Boot ROM Internal SRAM Address range 0000 0000 OFFF FFFFH 256 MBytes Comment After reset Boot ROM 8 kBytes physical Note 1 After memory swap using MEM_SWAP register Internal SRAM 8 kBytes physical Note 1 IRT switch EMIF SDRAM 1000 0000H 1FFF FFFFH 2000 0000H 2FFF FFFFH 256 MBytes 256 MBytes 1000 0000H 100F FFFFH for registers Nete 2 1010 0000H 101F FFFFH for Communication SRAM 192 kBytes physical Note 2 Smaller external memory ranges are mirrored over the entire 256 MByte range Bank 0 Bank 1 3000 0000 30FF FFFFH 3100 0000H 31FF FFFFH 16 MBytes 16 MBytes Bank 2 3200 0000H 2 FFFFH 16 MBytes Bank Not used 3300 0000H 33FF FFFFH 3400 0000H 3FFF FFFFH 16 MBytes 192 MBytes Smaller external memory ranges are mirrored over the entire 16 MByte range Internal boot ROM Timers Watchdog 4000 0000H 4000 1FFFH 4000 2000H 4000 20FFH 4000 2100H 4000 21FFH 8 kBytes 256 Bytes 256 Bytes 8 kBytes physical 32 Bytes physicalNote 1 28 Bytes physicalNote 1 SPI 4000 2200H 4000 22FFH 256 Bytes 256 Bytes physical UART1 4000 2300H 4000 23FFH 256 Bytes 256 Bytes physical UART2 4000 2400H 4000 24FFH 256 Bytes 256 Bytes physical GPIO System Control Registers 4000 2500H 4000 25FFH 4000 2
191. s and generate an IRQ FIQ signal to the CPU As soon as the CPU accepts this interrupt the corresponding ISR bit in the ISREG or FIQISR register is also set The CPU then interrupts the lower priority interrupt routine and executes the higher interrupt routine first Lower priority interrupts are not lost They are entered in the IRREG register and are processed at a later time when all higher priority interrupt routines have been executed Preliminary Users Manual A17812EE1V1UM00 75 Chapter 7 Interrupt Controller 7 6 EOI End Of Interrupt A set ISR bit is deleted by the End of Interrupt command The CPU must use the EOI command to communicate this to the interrupt controller after the corresponding interrupt service routine is processed To communicate the EOI command to the interrupt controller the CPU writes any value to the IRQEND FIQEND register The interrupt controller autonomously decides which ISR bit is reset with the EOI command If several ISR bits are set the interrupt controller deletes the ISR bit of the interrupt request with the highest priority at the time of the EOI command The interrupt controller regards the interrupt cycle as ended when all of the set ISR bits have been reset by the appropriate number of EOI commands Afterwards low priority interrupts that occurred in the meantime and were entered in the IRREG register can be processed in the priority logic During one or more accepted interrupts the priority distribution
192. s bit Receive timeout interrupt did not occur initial value Receive timeout interrupt occurred TIS Transmit interrupt status bit indicates if a transmit interrupt was generated within UART 1 2 Transmit interrupt status bit Transmit interrupt did not occur initial value Transmit interrupt occurred RIS Receive interrupt status bit indicates if a receive interrupt was generated within UART 1 2 Receive interrupt status bit Receive interrupt did not occur initial value Receive interrupt occurred MIS Modem interrupt status bit indicates if a modem interrupt was generated within UART 1 2 Modem interrupt status bit Modem interrupt did not occur initial value Modem interrupt occurred MIS bit is cleared when a write access with any value is performed to this register Preliminary Users Manual A17812EE1V1UM00 139 12 3 GPIO Register Initialization for UART Usage Chapter 12 UART1 UART2 Due to the fact that all UART pins are shared with GPIO pins on ERTEC 400 the GPIO registers need to be initialized properly before any of the UARTs on ERTEC 400 can be used Below two examples are given for two wire UARTs and for five wire UARTs Table 12 4 GPIO Register Initialization Example for Two wire UARTs UART pin Realized with function GPIO8 function 1 GPIOS function 1 GPIO PORT MODE HNote XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXXp GPIO PORT MODE
193. s connected as an AHB slave to the multilayer AHB bus and can be accessed with the full bus clock without wait states Additionally there are 8 kBytes of boot ROM that are implemented as an APB peripheral The boot ROM content is pre defined and cannot be altered by the user It contains a boot loader program with the ability to choose among various other boot sources if desired Preliminary User s Manual A17812EE1V1UMOO0 17 4 5 6 7 8 9 18 Chapter 1 Introduction External Memory Interface The memory controller on ERTEC 400 supports synchronous DRAM as well as static memories like SRAM or Flash Additionally static peripherals can be connected For SDRAM a data bus width of 16 or 32 bits can be configured the addressing capabilities allow connection of up to 256 MBytes of SDRAM SDRAM is accessed with the clock speed of the multilayer AHB bus therefore the maximum SDRAM speed is 50 MHz with a CAS latency of 2 For static devices 4 chip selects with an address range of 16 MBytes each are prepared They are independently configurable to 8 16 or 32 bit bus width and to individual access timings Slow peripherals are supported with a ready signal input and a timeout function Static chip select 0 can be used for an external boot device typically a flash memory as an alternative to using the boot loader in the on chip ROM IRT Switch The IRT switch block provides 4 Ethernet channels for 10 or 100 Mbps respec
194. s signal PME However this requires that the PME ENABLE bit is set in the power management configuration register of the AHB PCI bridge PME N activation requires a rising edge of the PME bit so make sure that the PME bit is reset before you set it PME signal activation oo Do not activate PME_N initial value ty PME_N rising edge required Figure 17 11 AHB Timeout Address Register QVZ AHB ADR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value QVZ AHB ADR 4000 2628H 0000 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QVZ AHB ADR QVZ_AHB_ADR 31 0 QVZ AHB ADR Holds the address in case of an incorrect multilayer access 184 Preliminary User s Manual A17812EE1V1UMOO Chapter 17 System Control Registers Figure 17 12 AHB Timeout Control Signal Register QVZ_AHB_CTRL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value reserved 4000 262CH 0000 0000H 14 HW reserved HBURST HSIZE ju Bit position Bit name Function Reserved HBURST HBURST Holds the logical level of the HBURST 2 0 signals in case of an incorrect multilayer AHB access HSIZE Holds the logical level of the HSIZE 2 0 signals in case of an incorrect multilayer AHB access HWRITE Holds the logical level of the HWRITE signal in case of an incorrect multilayer AHB access HWRITE HWRITE status of incorrect access HWRITE Incorrect access was a read access i
195. se I O GPIO MEMO 126 Preliminary User s Manual 17812 1 10 00 Chapter 12 UART1 UART2 Two UARTs are implemented in ERTEC 400 The inputs and outputs of the UARTs are available as an alternative function at GPIO 13 9 UART1 and GPIO 18 14 UART2 To use UART1 respectively UART2 it is required to set input output direction accordingly for the affected pins using the GPIO_IOCTRL register to configure alternative function 1 for the affected pins using the GPIO PORT MODE L H registers Note that after reset all GPIO pins are configured as GPIO inputs an eventually configured UART1 or UART2 is lost If the UARTs are used the affected pins are no longer available as standard I O The baud rate generation is derived from the internal 50 MHz APB clock The data bit width for read write accesses to UART registers on the APB bus is 8 bits The following signal pins are available for UART 1 and UART 2 on ERTEC 400 Table 12 1 UART1 UART2 Pin Functions Pin Name Function Number of pins UART1 transmit data output UART1 receive data input UART1 carrier detection signal UART1 data set ready signal UART1 transmit enable signal UART2 transmit data output UART2 receive data input UART2 carrier detection signal UART2 data set ready signal UART2 transmit enable signal Both UARTs are implemented as ARM PLO10 macros These are similar to standard
196. sed on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics products depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Elect
197. sor clock runs freely initial value DBGEN Reflects enable status of embedded ARM9 debugger DBGEN Embedded debugger enable Embedded debugger disabled Embedded debugger enabled initial value MICEBYPASS Allows to bypass synchronisation to ARM9 clock MICEBYPASS is synchronized to 9 clock initial value is not synchronized to ARM9 clock 192 Preliminary User s Manual 17812 1 10 00 Chapter 17 System Control Registers Figure 17 21 ARM9 Control Register ARM9_CTRL 2 2 Bit position Bit name Function INITRAM Indicates whether the TCMs are enabled to use Note INITRAM TCM enable INITRAM 0 TCMs disabled initial value 1p TCMs enabled Note This bit is not affected by soft or watchdog reset it is only affected by a hardware reset via RESET_N SYSOPT SYSOPT Displays the implemented ETM options the default value of this field is 139H Details can be found in the documents listed on page 6 Remark This register may only be changed for debug purposes Writing to this register must be enabled in the ARM9 WE register prior to accessing this register Figure 17 22 ARM9 Control Write Enable Register ARM9 WE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bit position Bit name Function Reserved ARM9 WE CTRL Enables to write to and change the
198. t controller The interrupt is only active High if watchdog timer 0 is in RUN mode and watchdog timer 0 has reached zero The exception to this is a load operation with reload value 0 Preliminary User s Manual A17812EE1V1UM00 167 Chapter 16 Watchdog Timers WDOUTO N output is at Low after a reset If watchdog timer 0 is set in RUN mode and the timer value does not equal zero the output changes to High The output changes to Low again when the count has reached zero The output can also be reset by stopping and then restarting watchdog timer O The signal can be used as an external output signal at the GPIO15 port if the alternative function 2 is configured for this pin The output can thus inform an external host about an imminent watchdog event The internal WDOUT1_N signal is at high inactive level after a reset when watchdog timer 1 goes to Stop If watchdog timer 1 is started WDOUT1 changes to Low when the timer reaches zero It remains Low until watchdog timer 1 is loaded with the reset value again by setting the LOAD bit The exception is when reload value 0 is loaded A hardware reset is triggered internally with WDOUT1 N Figure 16 2 below shows the time sequence of the watchdog interrupt and the two watchdog signals Figure 16 2 Watchdog Timer Output Timing xRESET p Jp 2 2 Run xStop Z1 _ internal Run xStop ZO lt intemal WDOUTO N WDINT internal WD
199. t interrupt enable bit 0 Receive timeout interrupt disabled initial value Receive timeout interrupt enabled Preliminary Users Manual A17812EE1V1UM00 135 Bit position Bit name Chapter 12 UART1 UART2 Figure 12 7 UARTCR1 2 Registers 2 2 Function TIE Transmit interrupt enable bit Transmit interrupt enable bit Transmit interrupt disabled initial value Transmit interrupt enabled RIE Receive interrupt enable bit Receive interrupt enable bit Receive interrupt disabled initial value Receive interrupt enabled MSIE Modem status interrupt enable bit MSIE Modem status interrupt enable bit Modem status interrupt disabled initial value Modem status interrupt enabled 136 UARTEN Reserved UARTEN UART enable bit UARTEN UART enable bit UART disabled initial value 1 UART enabled reception and transmission of data 9 is possible Preliminary Users Manual A17812EE1V1UMOO Chapter 12 UART1 UART2 Figure 12 8 UARTFR1 2 Registers 1 2 7 6 5 4 3 2 1 0 Address Initial value TXFE RXFF TXFF RXFE BUSY 4000 2318H 9xH 4000 2418H 9xH Bit position Bit name Function TXFE Indicates whether the transmit FIFO is empty TXFE Transmit FIFO empty flag Else Transmit FIFOs are enabled and empty or FIFOs are disabled and transmit holding registers are empty initial value RXFF Indicates whether receive FIFO is full
200. t is required to set input output direction accordingly for the affected pins using the GPIO_IOCTRL register to configure alternative function 1 for the affected pins using the GPIO PORT MODE H register Note that after reset all GPIO pins are configured as GPIO inputs an eventually configured SPI is lost If the SPI is used the affected pins are no longer available as standard I O The base frequency for the internal bit rate generation is the 50 MHz APB clock The data bit width for read write accesses to the SPI registers is 16 bits The following signal pins are available for the SPI interface on the ERTEC 400 Table 13 1 SPI Pin Functions Pin Name Function Number of pins SSPTXD SPI transmit data output SSPRXD SPI receive data input SCLKIN SPI clock input SCLKOUT SPI clock output SSPCTLOE SPI clock and serial frame output enable SPI output enable SPI serial frame input signal SPI serial frame output signal The SPI interface is implemented as ARM PrimeCell M PLO21 macro For a detailed description please refer to the list of documents on page 6 Figure 13 1 shows the structure of the SPI macro In order to support a wide range of connectable devices the SPI interface provides several operation modes Motorola SPl compatible mode Texas Instruments synchronous serial interface compatible mode National Semiconductor microwire interface compatible mode The operation mode
201. te 5 50 kO pull down CRS PnNete PnNeie 5 50 kQ pull down 50 kQ pull down TX ERR PnNote 5 DV PnNete5 50 kQ pull down L COL PpnNete 5 50 kQ pull down L RX_CLK_PnNote 5 50 kQ pull down E TX PnNete 5 50 kQ pull down L GPIO 31 0 50 kQ pull up H TRACECLK L 7 CLKP_B z i E REF CLK T 50 kQ pull Note 6 F Notes 1 The reset signal that affects these pins is RES_PCI_N 2 These resistors are required when neither the PCI interface nor the LBU interface are used In this case ERTEC 400 must be configured to LBU mode CONFIG2 0p a number can take the integer values 0 to 3 The number can take the integer values 0 and 1 RESET_N must be externally driven low in order to reset the device Preliminary Users Manual A17812EE1V1UM00 These pull up resistors are required when the interface is operated in PCI mode 45 Chapter 2 Pin Functions Table 2 15 Pin Status During Reset and Recommended Connections 3 3 Internal pull during Level External pull up down reset during reset up down required Pin Name TRST_N HNote 1 Pull up TOKNote 2 50 kQ pull up H TDINote 2 50 kQ pull up TMsSNote 2 50 kQ pull up TAP_SEL 50 kQpull up Notes 1 High lev
202. ted with the GPIO PORT MODE H and GPIO PORT MODE L registers In this table the I O types are listed for the trace port pin functions Table 2 13 Power Supply Pin Functions Pin Name Function VDD Core GND Core VDD IO GND IO P5V PCI AVDD AGND AVDD PCI AGND PCI Power supply for core 1 5 V GND for core Power supply for IO 3 3 V GND for IO Power supply for PCI 5v Note Analog power supply for PLL 1 5 V Analog GND for PLL Analog power supply for PLL in PCI I F 1 5 V Analog GND for PLL in PCI I F Note In PCI mode the P5V PCI pins must be connected to the PCI bus supply pins Vio name according to PCI specification In LBU mode the P5V PCI pins must be connected to VDD IO Preliminary Users Manual A17812EE1V1UM00 41 2 2 Pin Characteristics Pin Name A 23 16 Chapter 2 Pin Functions Table 2 14 Pin Characteristics 1 2 y o pNote 1 Input type SchmittNote 1 Output type 3 3 V CMOS Internal pull up down A 15 0 3 3 V CMOS Drive capability loH 9 9 9 9 D 31 0 Schmitt 3 3 V CMOS 50 kQ pull up 9 mA 9 mA WR N 3 3 V CMOS 9 mA 9 mA RD N 3 3 V CMOS 9 mA 9 mA CLK SDRAM 3 3 V CMOS 9 mA 9 mA CS SDRAM N 3 3 V CMOS 9 mA 9 mA RAS SDRAM N 3 3 V CMOS 9 mA 9 mA CAS SDRAM N 3 3 V CMOS 9 mA 9 mA WE SDRAM N 3 3 V CMOS 9mA 9 mA CS PER 3 0
203. ter PM STATE REQ 183 PME Register PME 00244 0 0 0 en 184 AHB Timeout Address Register QVZ AHB ADR 184 AHB Timeout Control Signal Register QVZ AHB 185 AHB Timeout Master Register QVZ AHB M 186 APB Timeout Address Register QVZ ADR 187 EMIF Timeout Address Register QVZ EMIF ADR 187 PCI Reset Request Register PCI RES REQ 188 PCI Reset Acknowledge Register PCI RES 189 Memory Swap Register MEM 5 189 PCI Interrupt Control Register PCI INT 190 AHB Master Lock Control Register M LOCK 191 ARM9 Control Register ARM9 CTRL 1 2 192 Preliminary User s Manual A17812EE1V1UMOO 12 Figure 17 22 Figure 18 1 Figure 18 2 Figure 19 1 Figure 21 4 13 ARM9 Control Write Enable Register ARM9 WE Di diea ista TT 193 Detailed Representation of Clock Unit sess 196 Clock Supply of Ethernet 198 PLL Phases
204. the corresponding registers and the requested state is set by the ERTEC 400 PCI interrupts are disabled Requested state is confirmed PCI bus is powered down and functions are disabled by the PC host Data traffic is monitored for a certain event by the ERTEC 400 The PME interrupt is triggered when the monitored event is detected PC host system is powered up when the individual devices request the Power UP state Backed up state is restored by the ERTEC 400 The last state is established in the PC host system Transition to requested Power UP power state occurs 8 2 2 ERTEC 400 as a Station on the Local PCI Bus In contrast to PC systems the configuration can be changed during operation in local PCI systems where a host is active on the PCI system In systems where a PCI interface is implemented only between several ERTEC 400s one of the ERTEC 400s can also assume the host function This enables very simple single master communication to be established between several ERTEC 400s via the PCI bus In the case of local on board PCI bus systems the IRQO HP interrupt high priority IRT interrupt can be switched to the INTB N output because an independent software structure is provided in this case For consistent non aligned accesses where IRT switch data must be accessed consistency assurance for non aligned accesses is implemented The alignment is signalled via accesses to the various mirror areas of th
205. tial value e WDOGO O 40002114 FFFFFFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position Function WDOGO 31 0 weed Holds the current counter value for watchdog timer 0 Figure 16 9 Counter Register for Watchdog 1 WDOG1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value WDOG1 40002118H FFFF FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDOG1 WDOG 1 31 0 WDOG1 Holds bit 35 4 of the current counter value for watchdog timer 1 bits 3 0 of the current counter value cannot be read Preliminary Users Manual A17812EE1V1UM00 173 Chapter 16 Watchdog Timers MEMO 174 Preliminary User s Manual 17812 1 10 00 Chapter 17 System Control Registers The system control registers are no peripheral in the original sense but rather an ERTEC 400 specific register set that can be read and written to from the PCI LBU side or from the ARM946E S The system control registers provide a certain level of self diagnosis capabilities A listing of all system control registers and their address assignments as well as a detailed description are included in the following sections 17 1 Address Assignment of System Control Registers The system control registers are 32 bits wide they are summarized in Table 17 1 below Address 4000 2600H Table 17 1 Register Name ID REG Initial value 4026 0100H Address Assignment of System Control Registers Description Device ide
206. tive edge is the default trigger mode assignment for all interrupts The active level in level trigger mode is always high The interrupt input signal must be present for at least one clock cycle in edge trigger mode The input signal must be present until confirmation of the ARM946E S CPU in level trigger mode Shorter signals result in loss of the event 7 3 Masking the Interrupt Inputs Each IRQ interrupt can be enabled or disabled individually The MASKREG register is available for this purpose The interrupt mask acts only after the IRREG interrupt request register That is an interrupt is entered in the IRREG register in spite of the block in the MASKREG register After a reset all mask bits are set and thus all interrupts are disabled At a higher level all IRQ interrupts can be disabled globally via a command When IRQ interrupts are enabled globally via a command only those IRQ interrupts that are enabled by the corresponding mask bit in the MASKREG register are enabled For the FIQ interrupts only selective masking by the mask bits in the FIQ MASKREG register is possible After a reset all FIQ interrupts are disabled A detected FIQ interrupt request is entered in the FIQ interrupt request register If the interrupt is enabled in the mask register processing takes place in the priority logic If the interrupt request is accepted by the ARM946E S CPU and an entry is made in the in service request register ISR the corresponding b
207. tively half or full duplex operation The IRT switch is connected to the multilayer AHB bus as a master and a slave and to the external world via a 4 channel RMII interface that can be re configured to 2 channel MII operation A large internal Communication SRAM with 192 kBytes in size helps to support RT and IRT data communication over Ethernet PCI Interface For easy integration into a PC style environment respectively for easy connection to PC peripher als ERTEC 400 has a 32 bit 66 MHz PCI interface that conforms to the PC specification R2 2 and to the PCI Power Management specification V1 1 The PCI interface can be master or slave to the multilayer AHB bus and master or target to the PCI bus Host bridge functionality is implemented and the interface can work in 3 3 V and 5 V environments Local Bus Unit The PCI interface shares its pins with the Local Bus unit LBU that allows to run ERTEC 400 as a peripheral to an external host controller The LBU is a master to the multilayer AHB bus and has separate address 21 bit and data 16 bit buses to the external world Seen with the eyes of the external host the LBU opens a total of four configurable windows into the ERTEC 400 that allow to configure ERTEC 400 and to access all internal resources Other Peripherals The ERTEC 400 has several additional communication interfaces that can be accessed over the AHB to APB bridge and the subsequent APB bus These are two widely 16550 compatibl
208. to IRQ1 If the Reload Mode bit is set to Op the timer stops when 0 is reached if the Reload Mode bit is 1 the timer is reloaded with the 32 bit reload value and automatically restarted The timer can also be reloaded with the reload value during normal timer function count value 0 This happens by setting the LOAD bit in the status control register of the timer Normally the timers operate at the 50 MHz clock which is generated by the internal PLL Each timer can also be operated with an 8 bit prescaler that can be used to increase the timer period accordingly 15 1 2 Timer Interrupts The timer interrupt is active High starting from the point at which the timer value is counted down to 0 The timer interrupt is deactivated Low when the reload value is automatically reloaded or the LOAD bit is set by the user The interrupt is not reset if the loaded reload value is 0 If the timer is deactivated Run XStop bit set to 0p the interrupt is also deactivated If the timer operates in reload mode without a prescaler the interrupt is present for only one 50 MHz cycle This must be taken into account when assigning the relevant interrupt input level edge evaluation 15 1 3 Timer Prescaler An 8 bit prescaler is available for each timer Settings can be made independently for each prescaler Each prescaler has its own 8 bit reload register If the reload value or starting value of the prescaler is 0 prescaling does not occur Th
209. ture of a GPIO pin as a standard I O function or as an alternative function Figure 11 1 GPIO Cells of ERTEC 400 Alternate input function 1 2 3 if available e e GPIO_OUTn Alternate output function 1 2 3 if available GPIOn GPIO PORT MODE L H 2n 1 2n GPIO IOCTRLn Preliminary User s Manual A17812EE1V1UMOO0 119 Chapter 11 11 1 Address Assignment of GPIO Registers General Purpose I O GPIO The GPIO registers are 32 bits wide However the registers can be read or written to with 8 bit 16 bit or 32 bit accesses In case of accesses with less than 32 bits note that the ERTEC 400 memory organization is Little Endian Address 4000 2500H Table 11 2 Address Assignment of GPIO Registers Register Name GPIO IOCTRL Initial value FFFF FFFFH Description Configuration register for GPIOs 4000 2504H GPIO OUT 0000 0000H Data output register for GPIOs 4000 2508H GPIO IN xxxx H Note 1 Data input register for GPIOs 4000 250CH 4000 2510H GPIO PORT MODE L GPIO PORT MODE 0000 0000H 0000 0000H Function selection for GPIO 15 0 Function selection for GPIO 31 16 Notes 1 During reset all GPIO pins are configured as input port pins Thus the content of the GPIO IN register reflects the logical level of the GPIO 31 0 pins during reset 2 Reserved bits in all registers are undefined when read always write the i
210. tween ROM and RAM 4000 2648H PCI INT CTRL 0000 0000H Control PCI interrupts 4000 264CH M LOCK CTRL 0000 0000H AHB master lock enable Master selec tive enable of AHB lock functionality 4000 2650H ARM9 CTRL 0000 1939H Controller of ARM9 and ETM inputs 4000 2654H ARM9 WE 0000 0000H Write protection register for 9 4000 2658H 4000 26 Reserved Note Reserved bits in all registers are undefined when read always write the initial reset values to these bits Preliminary User s Manual A17812EE1V1UMOO 175 Chapter 17 System Control Registers 17 2 Detailed System Control Register Description Figure 17 1 Device Identification Register ID_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value ERTEC 400 ID 4000 2600H 4026 0100H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etal Fix Bit position Bit name Function ERTEC 400 ID Holds an ERTEC 400 identification pattern that corresponds to the device ID of the bridge 4026H ERTEC 400 ID HW release FIN elease Holds a number representing the HW release step currently 01H Metal Fix Metal Fix Holds a number representing the metal fix step currently 00H Figure 17 2 Boot Mode Pin Register BOOT_REG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Address Initial value 40002604H 15 14 13 12 11 0 9 8 7 6 5 4 8 eserved 2 1
211. ugging is possible if the IRQ interrupt sources of the UART or the ICE communication channel are mapped to the FIQs with numbers 6 or 7 This enables debugging of interrupt routines 76 Preliminary Users Manual A17812EE1V1UMO00 7 8 Interrupt Control Register Summary Chapter 7 Interrupt Controller The interrupt control registers are used to specify all aspects of control prioritization and masking of the IRQ FIQ interrupt controllers they are located at address 5000 0000 and beyond in the 32 bit AHB address space Interrupt control registers can only be accessed by the ARM946E S CPU table 7 3 summarizes these registers Address 5000 0000H Table 7 3 Register Name IRVEC Initial value FFFF FFFFH Interrupt Control Registers 1 2 Description Interrupt vector register 5000 0004H FIVEC FFFF FFFFH Fast interrupt vector register 5000 0008H LOCKREG 0000 0000H Priority lock register 5000 000CH FIQ1SREG 0000 0000H Fast int request 1 select register FIQ6 on FIQ interrupt controller 5000 0010H FIQ2SREG 0000 0000H Fast int request 2 select register FIQ7 on FIQ interrupt controller 5000 0014H IRQACK FFFF FFFFH Interrupt vector register with IRQ acknowledge 5000 0018H FIQACK FFFF FFFFH Fast interrupt vector register with FIQ acknowledge 5000 001CH 5000 0020H IRCLVEC MASKALL undefined 0000 0001H Interrupt request clear vector
212. ve data SPI transmit data SPI clock out SPI serial frame output SPI serial frame input SPI clock in SPI clock and serial frame output enable SPI output enable R MII transmit data bit 0 R MII transmit data bit 1 MII transmit data bit 2 MII transmit data bit 3 R MII receive data bit 0 27 RXD_P 3 0 1 RXD_P 1 0 2 RXD_P 1 0 3 TX_EN_P 3 0 TX_ERR_P 1 0 CRS_DV_P 3 0 RX_ER_P 3 0 CRS_P 1 0 RX_DV_P 1 0 COL_P 1 0 RX_CLK_P 1 0 TX_CLK_P 1 0 SMI_MDC SMI_MDIO RES PLL EXT IN N TGEN OUT1 TRACEPKT 7 0 ETMEXTOUT PIPESTA 2 0 TRACESYNC TRACECLK 28 Chapier 1 Table 1 2 Pin Identification 2 2 R MII receive data bit 1 MII receive data bit 2 MII receive data bit 3 R MII transmit enable MII transmit error RMII carrier sense data valid R MII receive error MII carrier sense MII receive data valid MII collision MII receive clock MII transmit clock R MII SMI clock R MII SMI input output Reset to PHY MC_PLL input signal MC_PLL output signal Trace pins of ETM ETM output signal ETM input signal Trace pipeline status Trace sync signal ETM trace or scan clock Preliminary Users Manual A17812EE1V1UMOO Introduction TRST_N TCK TDI TMS TDO DBGREQ DBGACK TAP_SEL CLKP_A CLKP_B REF_CLK F_CLK RESET_N WDOUTO_N VDD Core GND Core VDD IO GND IO P5V
213. with Harvard architecture Compared to the standard ARM9 family the ARM946E S has an enhanced 5vTE architecture permitting faster switching between ARM and Thumb code segments and an enhanced multiplier structure In addition the processor has an integrated JTAG interface The processor can be operated at 50 MHz 100 MHz or 150 MHz The operating frequency is set during the reset phase via the CONFIG3 and CONFIGA configuration pins Communication with the compo nents of the ERTEC 400 takes place via the AHB bus at a frequency of 50 MHz Preliminary User s Manual A17812EE1V1UMOO0 47 Chapter 3 CPU Function 3 2 Cache Structure of ARM946E S The following caches are integrated in the ARM946E S processor system 8 kBytes of instruction cache with lock function 4 kBytes of data cache D cache with lock function Both caches are 4 way set associative and have 1 kByte segments Each segment consists of 32 lines with 32 Bytes 8 x 4 Bytes The D cache has a write buffer with write back function The lock function enables the user to freeze the contents of the cache segments This function allows the code for fast routines to be kept permanently in the This mechanism can only be imple mented on a segment specific basis in the ARM946E S Both caches are locked after a reset The caches can be enabled only if the memory protection unit is enabled at the same time The can be enabled by setting Bit 12
214. wo of the timers are driven with the internal 50 MHz clock and based on 32 bit respectively 36 bit down counters that are cascadable and that can be configured with an additional 8 bit prescaler The third timer the F timer runs under the control of an external clock The watchdog timers are also based on 32 bit and 36 bit down counters Watchdog 0 32 bit is generating an output signal on the WDOUTO N pin watchdog 1 36 bit generates a reset System Control Registers A bundle of specific system control registers help to configure the processor and to analyse internal problems like access right and or address range violations or timeouts Preliminary Users Manual A17812EE1V1UM00 31 MEMO 32 Chapter 1 Introduction Preliminary User s Manual 17812 1 10 00 2 1 List of Pin Functions Pin Name Table 2 1 pNote Chapter 2 Pin Functions External Memory Interface Pin Functions Function External memory address bus 23 19 Alternate Function CONFIG 4 0 Note pNote External memory address bus 18 16 BOOT 2 0 Note External memory address bus 15 0 External memory data bus 31 0 Write strobe signal Read strobe signal CLK_SDRAM Clock to SDRAM CS_SDRAM_N RAS SDRAM Chip select to SDRAM Row address strobe to SDRAM CAS SDRAM N Column address strobe to SDRAM WE SDRAM RD WR signal to SDRAM CS PER 3 0 N 3 0 3 0
215. y or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed ba

ERTEC 400 Enhanced Real-Time Ethernet Controller with 32

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