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Manual - Excalibur Systems, Inc.

1. 3 17 3 6 MIL STD 1553A B Operation BC Mode 3 18 4 Remote Terminal Operation 4T Control Registers Es 4 2 4 1 1 Control Register 4 3 4 1 2 Operational Status Register 4 5 4 1 3 Current Command Block Register 4 6 4 1 4 Interrupt Mask Register 4 6 4 1 5 Pending Interrupt Register 4 7 4 1 6 Interrupt Log List Pointer Register 4 8 4 1 7 BIT Word Register vag sie tee eae le tee ema 4 8 4 1 8 Time Tag Register iss tae es RE ee Baek ee Rs RU EGO a 4 9 4 1 9 RT Descriptor Pointer Register 4 9 4 1 10 1553 Status Word Bits Register 4 10 4 1 11 Illegalization Registers 4 11 42 Descriptor Bloc out SLE aterra e 4 13 4 2 1 Receive Control Word 4 15 4 2 2 Transmit Control Word 4 16 4 2 3 Mode Code Receive Control Word 4 17 4 2 4 Mode Code Transmit Control Word 4 18 4 2 5 Data Pointer A and B Mode 0O 4 19 4 2 6 Ping pong Handshake Mode 0 4 21 4 2 7 Broadcast Data Pointer Mode 0
2. 4 22 4 3 Data Structures 4 23 4 3 4 Subaddress Receive Data 4 23 4 3 2 Subbaddress TransmitData 4 24 4 3 3 Mode Code Dala cor Pf wardens ae 4 25 page ii Excalibur Systems Table of Contents 4 4 RT Circular BufferModes 4 27 4 4 1 Mode 1 Operation 4 27 4 4 2 Mode 2 Operation 4 30 4 5 Mode Code and Subaddress 4 33 4 6 Encoder and Decoder 4 35 4 7 RT to RT Transfer Compare 4 36 4 8 Terminal Address 4 36 BD A wo gu tere IN us 4 36 4 10 MIL STD 1553A B Operation RT Mode 4 37 5 Bus Monitor Operation 5 1 Bus Monitor Message Processing 5 2 5 1 1 Error Condition Message Processing 5 2 5 1 Control Registers BM Mode 5 3 51 1 Control Register oos eR eee Ee RE bee e REG 5 4 5 1 2 Operational Status Register 5 5 5 1 3 Current Command Register 5 6 5 1 4 Interrupt Mask Register 5 6 5 1 5 Pending Interrupt Register 5 7 5 1 6 Interrupt Log List Pointer Registe
3. 2 5 2 3 8 Latency Timer Register LAT 2 5 2 3 9 Header Type Register HDR 2 5 2 3 10 Built In Self Test Register BIST 2 5 2 3 11 Base Address Registers BADR 2 6 2 3 12 Cardbus CIS Pointer 2 6 2 3 13 SubsystemiID 2 7 2 3 14 SubvendorID 2 7 2 3 15 Expansion ROM Base Address Register XROM 2 7 2 3 16 MRHesermed i oues eee des ap ee eae Wd ees d 2 7 2 3 17 Interrupt Line Register INTLN 2 7 2 3 18 Interrupt Pin Register INTPIN 2 8 2 3 19 Minimum Grant Register MINGNT 2 8 2 3 20 Maximum Latency Register MAKLAT 2 8 2 4 Channel Memory Space 2 9 2 4 1 Channel External Timer Clock Register 2 11 2 4 2 Channel Reset Register 2 11 2 5 Global Registers Map 2 12 2 5 1 Board Identification Register 2 12 2 5 2 Software Reset Register 2 13 2 5 8 Interrupt Status Register 2 13 2 5 4 Interrupt Reset R
4. 4 7 4 1 6 Interrupt Log List Pointer Register 4 8 4 1 7 BIT Word Register 4 8 4 1 8 Time TagRegister 4 9 4 1 9 RT Descriptor Pointer Register 4 9 4 1 10 1553 Status Word Bits Register 4 10 4 1 11 Illegalization Registers 4 11 4 2 Descriptor Block 2 eee eh eee eee RR Il 4 13 4 2 1 Receive Control Word 4 15 4 2 2 Transmit Control Word 4 16 4 2 8 Mode Code Receive Control Word 4 17 4 2 4 Mode Code Transmit Control Word 4 18 4 2 5 Data Pointer A and B Mode 0 4 19 4 2 6 Ping pong Handshake Mode 0 4 21 4 2 7 Broadcast Data Pointer Mode 0 4 22 4 3 Data Structures ceso ool a eee ele adn 4 23 4 3 1 Subaddress Receive Data 4 23 4 3 2 Subbaddress TransmitData 4 24 4 3 3 ModeCodeData 4 25 4 4 RT Circular Buffer Modes 4 27 4 4 1 Mode 1 Operation 4 27 4 4 2 Mode 2 Operation 4 30 4 5 Mode Code and Subaddress 4 33 46 Encoder and Decoder oooocooococcoo e
5. 5 5 5 1 3 Current Command Register 5 6 5 1 4 Interrupt Mask Register 5 6 5 1 5 Pending Interrupt Register 5 7 5 1 6 Interrupt Log List Pointer Register 5 7 5 1 7 BIT Word Register 5 8 5 1 8 Time TagRegister 5 8 5 1 9 Initial Monitor Block Pointer Register 5 9 5 1 10 Initial Monitor Data Pointer Register 5 9 5 1 11 Monitor Block Counter Register 5 9 5 1 12 Monitor Filter Hi Register 5 10 5 1 13 Monitor Filter Lo Register 5 10 Bus Monitor Architecture 5 11 5 1 1 Message Information Word 5 11 5 1 2 Command Words 00 0 ees 5 12 5 4 3 Data Pointer y s e a a dea rita 5 12 5 1 4 Status Words 0 al io ane Bae 5 13 5445 Time AU Rr eg te ee Peu X UE ERU 5 13 5 1 6 Reserved is ge lea sae ain de a es ea 5 13 Bus Monitor Block Chaining 5 13 Memory Architecture 5 14 RT Concurrent Monitor Operation 5 15 MIL STD 1553A B Operation BM Mode 5 16 EXC 1553PCI MCH User s Manual page 5 1 Chapter 5 5 1 page 5 2 Bus Monitor Op
6. BA CA TA CONTROL WORD Descriptor Block Figure 4 6 RT Mode 1 Descriptor Block And Circular Buffer EXC 1553PCI MCH User s Manual Remote Terminal Operation Figure 4 6 describes the relationship between The top address TA bottom address BA and current address CA page 4 29 Chapter 4 4 4 2 4 4 2 1 page 4 30 Remote Terminal Operation Mode 2 Operation In this mode the channel separates message data and message information into unique circular buffers The separation of data from message information simplifies the software that loads and unloads data from the buffers The message information buffer contains Time Tag and Message Information Words for each message transacted on the bus while the data buffer contains the message Data Words After processing a pre determined number of messages both buffers wrap around MODE 2 DESCRIPTOR BLOCK Each subaddress and mode code both transmit and receive has a unique pair of circular buffers The channel decodes the Command Word T R bit subaddress mode field and Word count mode code field to select a unique descriptor block that contains Control Word TA CA and MIB see Figure 4 7 RT Mode 2 Descriptor Block on page 4 32 To implement Circular Buffer 2 s architecture the descriptor block and Control Register are different than in Mode 0 Bits 15 through 08 of the Control Word specify the Message Inform
7. 3 17 Control Registers Map RT Mode 4 2 Descriptor Table ocios ies XR HEC mae s Mns 4 14 RT Non broadcast Receive Message Indexing 4 20 EXC 1553PCI MCH Descriptor Block Receive 4 20 EXC 1553PCI MCH Descriptor Bock Transmit 4 21 RT Mode 1 Descriptor Block And Circular Buffer 4 29 RT Mode 2 Descriptor Block 4 32 Control Registers Map BM Mode 5 3 Message Information Word 5 11 Bus Monitor Block Structuring 5 13 Memory Architecture for Bus Monitor Mode 5 14 EXC 1553PCI MCH Board Layout 7 2 EXC 1553cPCI MCH Board Layout 7 3 DIP Switch SW1 with all switches set to closed on Select ID 0 7 5 Connector J1 Front View 7 8 Synchronization of a single EXC 1553PCI MCH to an external system 7 10 Synchronization of an external system to a single EXC 1553PCI MCH 7 10 Synchronization Between EXC 1553PCI MCH Boards 7 10 Base Address Registers Definition 2 6 MIL STD 1553A B Operation BC Mode 3 18 Illegalization Register Blocks 4 11 Illegalization Register Map
8. 4 12 RT Mode 2 Control Word and MIB Pointer Structure 4 31 Mode Code Description 4 33 MIL STD 1553A B Operation RT Mode 4 37 MIL STD 1553A B Operation BC Mode 5 16 Interrupt Ring Buffer 2 2 llli 6 3 Jumper Settings Required to Select Coupling Mode 7 6 Channel Jumper Groups 7 6 Connector JI Pinouts EIA tee 7 8 Communication I O Signals Descriptions of Connector J1 7 9 PCI Bus Edge Connector Pinouts 7 11 cPCI Bus Connector Pinouts 7 12 EXC 1553PCI MCH User s Manual page v Table of Contents page vi Excalibur Systems Chapter 1 1 1 Introduction Introduction Chapter 1 provides an overview of the EXC 1558PCI MCH avionics communication board The following topics are covered Tl OVervieW irrita 1 1 12 Installation 120 esl ad da ae LEER 1 4 1 2 1 Installngithe Board iius ket RR ER RICE ER 1 4 1 2 2 Adding Excalibur Software Tools 1 4 13 1553 Bus Connections 1 5 1 4 Note About Pointer Registers 1 7 1 5 Technical Support ooocooccnccn enne 1 7 This User s Manual supports both the EXC 1553PCI MCH and the EXC 1553cPCI MCH Unless otherwise indicated all re
9. N Table 4 4 Mode Code Description Continued Encoder and Decoder The EXC 1558PCI MCH receives the Command Word from the MIL STD 1553 bus and processes it either by the primary or secondary decoder Each decoder checks for the proper sync pulse and Manchester waveform edge skew correct number of bits and parity If the Command is a receive Command the channel processes each incoming Data Word for correct format Word count and contiguous data If a message error is detected the channel stops processing the remainder if any of the message suppresses Status Word transmission and asserts bit 09 ME bit of the Status Word The channel automatically compares the transmitted Word encoder Word with the reflected decoder Word by way of the continuous loopback feature If the encoder Word and reflected Word do not match the WRAPF bit is asserted in the BIT Word Register and an interrupt will be generated if enabled In addition to the loopback compare test a timer precludes a transmission greater than 800isec by the assertion of Fail Safe Timer This timer is reset upon receipt of another Command Remote Terminal Response Time MIL STD 1553A 7 usec MIL STD 1553B 10 psec Data Contiguity Time Out 1 0 msec EXC 1553PCI MCH User s Manual page 4 35 Chapter 4 Remote Terminal Operation 4 7 RT to RT Transfer Compare The RT to RT Terminal Address compare logic ensures that the incoming Status Word s Terminal Addr
10. 2 5 6 page 2 14 PCI Architecture Bit Description 01 1 resets channel 1 interrupt 0 no effect 00 1 resets channel 0 interrupt 0 no effect Interrupt Reset Register Channel Info Registers Address 08 OA OC OE H Length 16 bits each The Channel Info Registers provide identification information for each of the four channels respectively Bit Description 12 45 Channel ID 00 H Channel 0 Info register 01 H Channel 1 Info register 02 H Channel 2 Info register 03 H Channel 3 Info register 05 11 Reserved set to 0 00 04 Channel detect 03 H Channel present 1F H No channel installed Channel Info Registers External Timer Clock Source Register Address 10 H Length 16 bits The External timer Clock Source Register is used by all the channels to set either an internal or external source for the External Timer Clock See section 2 4 1 Channel External Timer Clock Register on page 2 11 Bit Description 01 15 Reserved set to 0 00 External Timer Clock Source 1 External Source 0 Internal Source Default Time Tag Clock Select Register If an external source is used take care to ensure that it is as close to 1 MHz as possible otherwise deviations the desired external clock will occur See section 7 5 2 Communication I O Signals Description of Connector J1 on page 7 9 Excalibur Systems Chapter 3 Bus Controller Operation 3 Bus Controller Operation Chapter 3 describes EXC 1553PCI MC
11. The channel is idle This read only bit is not applicable Channel Ready This read only bit is cleared on reset 1 The channel has completed initialization or BIT and regular operation may begin Channel Terminal Active This read only bit is cleared on reset 1 The channel is presently processing a 1553 message EXC 1553PCI MCH User s Manual page5 5 Chapter 5 page 5 6 Bus Monitor Operation Current Command Register Address 0004 H Read only The Current Command register contains the last valid command that was trans mitted over the 1553 bus In an RT to RT transfer this register will update as each of the two commands are received by the Bus Monitor Bit Bit Name Description 00 15 CC 15 0 Current Command These bits contain the latest 1553 command that was transmitted by the Bus Monitor Interrupt Mask Register Address 0006 H Read Write The EXC 1558PCI MCH interrupt architecture allows the host to mask or tem porarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event An interrupt is masked only if the corresponding bit of this register is set to a logic 0 Bit Bit Name Description 12 15 Reserved Set to 0 11 MERR Message Error Interrupt 01 10 Reserved Set to 0 00 MBC Monitor Block Counter Interrupt Excalibur Systems Chapter 5 5 1 5 5 1 6
12. 02 SSYSF Subsystem Flag Bit This bit sets the Subsystem Flag bit of the MIL STD 1553B Status word Bit 17 of the Status Word 01 Reserved Setto0 00 TF Terminal Flag Assertion of this bit is reflected in the outgoing MIL STD 1553B Status Word The channel automatically sets this bit if a BIT failure occurs Inhibit Terminal Flag mode code prevents the assertion by the host Override Inhibit Terminal Flag Mode Code re establishes the Terminal Flag option Bit 19 of the Status Word 1553 Status Word Bits Register MIL STD 1553B Excalibur Systems Chapter 4 Remote Terminal Operation For MIL STD 1553A applications the 1553 Status Word Bits register Bit Bit Name Description 15 IMCLR Immediate Clear Function 1 Enables the Immediate Clear Function IMF of the channel Enabling the IMF results in the clearing of the bits 10 19 immediately after a Status Word is transmitted To enable this function set this bit when writing to bits 10 19 This bit should be used consistently since once set it will remain set and once cleared it will remain cleared 10 14 Reserved Set to 0 09 SB10 Status bit time 10 08 SB11 Status bit time 11 07 SB12 Status bit time 12 06 SB13 Status bit time 13 05 SB14 Status bit time 14 04 SB15 Status bit time 15 03 SB16 Status bit time 16 02 SB17 Status bit time 17 01 SB18 Status bit time 18 00 SB19 Status bit time 19 1553 Status Word Bits Register MIL STD 1553A 4 1 11 Illegalization Reg
13. 1 Bus B high connection BUSBL1 Channel 1 Bus B low connection BUSAH2 Channel 2 Bus A high connection BUSAL2 Channel 2 Bus A low connection BUSBH2 Channel 2 Bus B high connection BUSBL2 Channel 2 Bus B low connection BUSAH3 Channel 3 Bus A high connection BUSALS Channel 3 Bus A low connection BUSBH3 Channel 3 Bus B high connection BUSBL3 Channel 3 Bus B low connection SHIELD case Provided for 1553 cables shield connection This signal is connected to the case of the computer EXTTCLKI External Timer Clock Source Input required value 1 MHz This signal supplies an external global clock to all of the channels It provides the basis for the External Timer Clock see section 2 4 1 Channel External Timer Clock Register on page 2 11 Use this signal to synchronize the External Timer Clocks on the channels to other boards or systems See section 2 5 6 External Timer Clock Source Register on page 2 14 EXTTCLKO External Timer Clock Source Output 1 MHz This is the global clock that is supplied to all the channels that forms the basis for their External Timer Clock see section 2 4 1 Channel External Timer Clock Register on page 2 11 Use this signal to synchronize other boards or systems to the External Timer Clock The source of this clock is either the External Timer Clock Source Input EXTTCLKI or the Internal Clock Source See section 2 5 6 External Timer Clock Source Register on page 2 14 GND
14. Interrupt Line Register INTLN Address 3C H Power up value 00 H Size 8 bits The Interrupt Line register indicates the interrupt routing for the PCI Controller The value of this register is system architecture specific For x86 based PCs the values in this register correspond with the established interrupt numbers associated with the dual 8259 controllers used in those machines the values of 1 to F H correspond with the IRQ numbers 1 through 15 and the values from 10 H to FE H are reserved The value of 255 signifies either unknown or no connection for the system interrupt EXC 1553PCI MCH User s Manual page 2 7 Chapter 2 2 3 18 2 3 19 2 3 20 page 2 8 PCI Architecture Interrupt Pin Register INTPIN Address 3D H Power up value 01H Size 8 bits Set to INTA Minimum Grant Register MINGNT Address 3E H Power up value 00 H Size 8 bits The Minimum Grant register is not implemented on the EXC 1558PCI MCH Maximum Latency Register MAXLAT Address 3F H Power up value 00 H Size 8 bits The Maximum Latency register is not implemented on the EXC 1558PCI MCH Excalibur Systems Chapter 2 PCI Architecture 2 4 Channel Memory Space The Channel Memory Space resides in the first memory block The 523 Kbytes of memory is broken up into four memory blocks of 128 Kbyte Each 128 Kbyte memory block represents the Address Space of a specific channel Each Channel Address Space is
15. The following suffixes must be added to the name of the board to indicate the specific options The suffixes must be added tot he EXC 1558PCI MCH or EXC 1553cPCI MCH in the order in which they appear in the table Suffix Description X Number of channels 1 4 E Ruggedized extended temperature option 40 85 C ORDERING EXAMPLES Part Number EXC 1553PCI MCH 1 EXC 1553cPCI MCH 2 EXC 1553cPCI MCH 2 E EXC 1553PCI MCH 3 EXC 1553cPCI MCH 4 EXC 1553cPCI MCH 4 E EXC 1553PCI MCH User s Manual Description Single channel MIL STD 1553 interface board for PCI systems Supports BC RT RT Concurrent BM and BM modes Dual channel MIL STD 1553interface board for compact PCI systems Supports BC RT RT Concurrent BM and BM modes Same as above with ruggedized extended temperature option 40 85 C Three channel MIL STD 1553 interface board for PCI systems Supports BC RT RT Concurrent BM and BM modes Four channel MIL STD 1553 interface board for compact PCI systems Supports BC RT RT Concurrent BM and BM modes Same as above with ruggedized extended temperature option 40 85 C page 8 1 Chapter 8 Ordering Information page 8 2 Excalibur Systems Appendix A MIL STD 1553 Word Formats Register Bits 15 14 13 12 11 10 7 5 4 3 2 1 1553 Bit Times 1 2 3 4 5 7 10 11 12 13 14 15 16 17 18 19 20 Command Word Sync RT Address TH SubAddress Mod
16. and B The remote terminal retrieves data from a buffer or stores data into a buffer depending on the message type 1 e transmit or receive Command During ping pong operation the Remote Terminal determines the active subaddress or mode code buffer at the beginning of message processing the remote terminal complements bit 02 of the Descriptor Control Word to access the alternate buffer on the following message 1 e ping pong The application software disables ping pong operation by writing a logical O to Control Register bit 02 The disable of ping pong operation is acknowledged by bit 09 of the Control Register Bit 09 of the Control Register acknowledges the ping pong disable by transitioning from a logical 1 to a logical 0 The application software interrogates bit 02 of each Descriptor Control Word to determine the active buffer on a subaddress or mode code basis If bit 02 is a logical O the remote terminal uses Buffer A and the application software off loads or loads Buffer A The application software enables ping pong operation by writing a logical 1 to Control Register bit 02 The enable of ping pong operation is acknowledged by bit 09 of the Control Register Bit 09 of the Control Register acknowledges the ping pong enable by transitioning from a logical 0 to a logical 1 EXC 1553PCI MCH User s Manual page 4 21 Chapter 4 Remote Terminal Operation 4 2 7 Broadcast Data Pointer Mode 0 The Broadcast Data Pointer c
17. no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice December 2007 Rev A 4
18. rupt will be generated if enabled The channel will start over at the initial point ers as identified in the Initial Monitor Block Pointer Register and the Initial Monitor Data Pointer Register Note It is recommended that this register not be changed while the BM mode is active 1 e Operational Status Register bit 03 1 Bit Bit Name Description 00 15 MBC 15 0 Monitor Block Count These bits indicate the number of Monitor Blocks to log EXC 1553PCI MCH User s Manual page5 9 Chapter 5 5 1 12 5 1 13 page 5 10 Bus Monitor Operation Monitor Filter Hi Register Address 001C H Read Write The Monitor Filter Hi Register determines which RTs RT 31 through RT 16 the channel will monitor Bit Bit Name Description 00 15 MFH 31 16 Monitor Filter These bits determine which RT to monitor Monitor Filter Lo Register Address 001E H Read Write The Monitor Filter Lo Register determines which RTs RT 15 through RT 0 the channel will monitor Bit Bit Name Description 00 15 MFL 15 00 Monitor Filter These bits determine which RT to monitor Excalibur Systems Chapter 5 5 1 Bus Monitor Operation Bus Monitor Architecture To meet the MIL STD 1553 monitor requirements the channel uses a Monitor Block architecture that takes advantage of both Control Registers and RAM The Monitor Block that is located 1n contiguous memory requires eight 16 bit loca tions for each message These eigh
19. the EXC 1558PCI MCH can operate in many different systems that use various protocols Specifically two of the protocols that the channel may be used with are MIL STD 1553A and MIL STD 1553B To meet these protocols configure the channel through the Control register ERTO Bit 09 and the Operational Status register A B_STD Bit 07 Table 3 1 defines the four ways to program the EXC 1553PCI MCH A B_STD ERTO RESULT 0 0 1553B standard 1553B response in 14 usec 0 1 1553B standard extended response in 30 psec 1 0 1553A standard 1553A response in 9 usec 1 1 1553A standard extended response in 21 usec Table 3 1 MIL STD 1553A B Operation BC Mode When configured as a MIL STD 1553A bus controller the channel will operate as follows Looks for the RT response within 9 usec Defines all mode codes without data defines subaddress 00000 as a mode code Excalibur Systems Chapter 4 Remote Terminal Operation 4 Remote Terminal Operation Chapter 4 describes EXC 1558PCI MCH operation in Remote Terminal RT mode The topics covered in this chapter are 41 Control Registers 4 2 4 1 1 Control Register 4 3 4 1 2 Operational Status Register 4 5 4 1 8 Current Command Block Register 4 6 4 1 4 Interrupt Mask Register 4 6 4 1 5 Pending Interrupt Register
20. too many or too few MIL STD 1553 Word parity bit count errors too many or too few and protocol errors If not masked this bit is always set and an interrupt generated when the channel asserts bit time 9 Message Error of the 1553 status Word e g illegal Commands invalid Data Word etc Subaddress Accessed Interrupt 1 A pre selected subaddress has transacted a message To determine the exact subaddress the host interrogates the interrupt log IAW Broadcast Command Received Interrupt 1 The channel s receipt of a valid broadcast Command The channel suppresses status Word transmission Index Equal Zero Interrupt The channel sets this bit to 1 to indicate the completion of a pre defined number of Commands by the RT Upon assertion of this interrupt the host updates the subaddress descriptor to prevent the potential loss of data Illegal Command Interrupt 1 The channel received an illegal Command Upon receipt of this Command the channel responds with a status Word only Bit time 09 Message Error of the 1553 status Word is set to a logic 1 Ignore on read page4 7 Chapter 4 page 4 8 Remote Terminal Operation Interrupt Log List Pointer Register Address 000A H Read Write The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1558PCI MCH
21. Block architecture resembling the BC these bits default to a 00 state If the monitor must switch to the BC the retries will be set at four per message 09 Bus A B This bit defines on which of the two buses the command was received Logic 1 Bus A Logic O Bus B 08 RT to RT Transfer This bit defines whether or not the message associated with this Monitor Block was an RT to RT transfer and whether the channel saved the second command word This bit will be set only if the channel is instructed to monitor the Receive RT 00 07 Message Information Bits These bits define the conditions of the message received by the channel for that particular Monitor Block In an RT to RT transfer the information applies to the complete message 07 Message Error This bit will be set if the monitor detects an error in either the Command Word Data Words or the RT s status 06 Mode Code without Data This bit will be set if the monitor detects that the command being processed is a mode code without data words 05 Broadcast This bit will be set if the monitor detects that the command being processed is a broadcast message 04 Reserved 03 Time Out Error This bit will be set if the RT did not receive the proper number of Data Words e g the number of Data Words received was less than the word count specified in the Command Word 02 Overrun Error This bit will be set if the RT received a word when none were expected or the number of Da
22. Clear Function does not affect the operation of the Transmit Last Status Word and Transmit Last Command Word Mode Codes Transaction of a legal valid Command with the INS bit set to a logic one and the Immediate Clear Function enabled results in the transmission of a 1553 Status Word with bit 10 asserted If the ensuing Command is a Transmit Last Status Word or Last Command mode code bit 10 of the outgoing 1553 Status Word remains a logic 1 For MIL STD 1553B applications the 1553 Status Word Bits register is as follows Bit Bit Name Description 15 IMCLR Immediate Clear Function 1 Enables the Immediate Clear Function IMF of the channel Enabling the IMF results in the clearing of the INS BUSY TF SRQ and or SUBF bit immediately after a message is completed To enable this function set this bit to 1 when setting bit s INS BUSY TF SRQ and or SSYSF to 1 This bit should be used consistently since once set it will remain set and once cleared it will remain cleared 10 14 Reserved Set to 0 09 INS Instrumentation Bit This bit sets the Instrumentation bit of the MIL STD 1553B Status Word Bit 10 of the Status Word 08 SRQ Service Request Bit This bit sets the Service Request bit of the MIL STD 1553B Status Word Bit 11 of the Status Word 04 07 Reserved Set to 0 03 BUSY Busy Bit Assertion of this bit is reflected in the outgoing MIL STD 1553B Status Word 1 Prevents memory accesses Bit 16 of the Status Word
23. Co DN Co set in outgoing Status Word if enabled in the Control Register Status Word transmitted Command Word stored Time Tag counter reset to 0000 H Status Word transmitted Table 4 4 Mode Code Description EXC 1553PCI MCH User s Manual page 4 33 Chapter 4 T R Mode Code Function Remote Terminal Operation Operation 1 00010 1 00011 1 00100 1 00101 1 00110 1 001111 1 01000 1 01001 0 1111 1 10000 1 10001 Transmit Status Word Initiate Self Test Transmitter Shutdown Override Transmitter Shutdown Inhibit Terminal Flag Bit Override Inhibit Terminal Flag Reset Remote Terminal Reserved Transmit Vector Word Reserved 1 Command Word stored 2 Last Status Word 3 Status Word cleared after reset Note The channel updates Status Word if illegalized Command Word stored Status Word transmitted BIT initiated TF bit set if BITF bit asserted RON Command Word stored Status Word transmitted Alternate bus disabled On 1 Command Word stored 2 Status Word transmitted 3 Alternate bus enabled Note Reception of the override transmitter shut down mode code does not enable a channel not previously enabled in the Control Register Reset remote terminal mode code clears the transmitter shutdown function 1 Command Word stored 2 Terminal flag bit set to 0 and assertion disabled 3 Status Word tran
24. RT message EXC 1553PCI MCH User s Manual page 5 15 Chapter 5 5 1 page 5 16 Bus Monitor Operation MIL STD 1553A B Operation BM Mode To maximize flexibility the EXC 1558PCI MCH can operate in many different systems that use various protocols Specifically two of the protocols that the channel may be used with are MIL STD 1553A and MIL STD 1553B To meet these protocols configure the channel through the Control register ERTO Bit 09 and the Operational Status register A B STD Bit 07 Table 5 1 defines the four ways to program the EXC 1553PCI MCH A B STD ERTO RESULT 0 0 1553B standard 1553B response in 14 usec 0 1 1553B standard extended response in 30 usec 1 0 1553A standard 1553A response in 9 usec 1 1 1553A standard extended response in 21 usec Table 5 1 MIL STD 1553A B Operation BC Mode When configured as a MIL STD 1553A bus controller the EXC 1553PCI MCH will operate as follows Looks for the RT response within 9 usec Ignores the T R bit for all mode codes Defines all mode codes without data Defines subaddress 00000 as a mode code Excalibur Systems Chapter 6 6 6 1 Channel Interrupt Architecture Channel Interrupt Architecture Chapter 6 describes the channel interrupt architecture The topics covered are 6 Overview c WAA We Mere xe PIE ee 6 1 6 1 1 Interrupt Identification Word IIW 6 2 6 1 2 Interrupt Address Word
25. an illegal Command 03 TO Time Out Error 1 The channel did not receive the proper number of Data Words i e the number of Data Words received was less than the Word count specified in the Command Word 02 OVR Overrun Error 1 The channel received a Word when none was expected or the number of Data Words received was greater then expected 01 PRTY Parity Error 1 The channel observed a parity error in the incoming Data Words 00 MAN Manchester Error 1 The channel observed a Manchester error in the incoming Data Words Receive Information Word EXC 1553PCI MCH User s Manual page 4 23 Chapter 4 4 3 2 page 4 24 Remote Terminal Operation Subbaddress Transmit Data The user is responsible for organizing the data packet 1 e N Data Words into memory and establishing the applicable Data Pointer The user can allocate two 16 bit memory locations at the top of the data packet for the storage of the Transmit Information Word and the Time Tag Word An example transmit Data structure for three Words is shown below Data Pointer A 0200 H XXXX Reserved for Transmit Info Word equals 0100 H 0202 H XXXX Reserved for Time Tag Word 0204 H FFFF Data Word 1 0206 H FFFF Data Word 2 0208 H FFFF Data Word 3 Note Data pointer A points to the top of the Data structure not to the top of the Data Words Bit Bit Name Description 11 15 WC 4 0 Word Count Bits These five bits contain Word count informati
26. architecture Read this register to deter mine the location and number of interrupts within the Interrupt Log List least significant 5 bits Bit Bit Name Description 00 15 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 05 15 indicate the starting Base address while bits 00 04 indicate the ring location of the Interrupt Log List EXC 1553PCI MCH User s Manual page5 7 Chapter 5 5 1 7 BIT Word Register Bus Monitor Operation Address 000C H Read Write The BIT Word Register contains information on the current status of the channel hardware The user defines the lower 8 bits of this register Bit Bit Name Description 15 DMAF DMA Fail 1 All the channel s internal DMA activity was not completed within 7 usec 13 14 Reserved Ignore on read 12 BITF BIT Fail 1 A BIT failure Interrogate bits 11and 10 to determine the specific bus that failed 11 BUAF Bus A Fail 1 A BIT test failure in Bus A 10 BUBF Bus B Fail 1 A BIT test failure in Bus B 09 MSBF Memory Test Fail Most significant memory byte failure 08 LSBF Memory Test Fail Least significant memory byte failure 00 07 UDB 7 0 User Defined Bits 5 1 8 Time Tag Register Address 000E H Read only The Time Tag register reflects the state of a 16 bit free running ring counter in the RT and Bus Monitor modes This counter will remain a free running counter as long as the channel is not in a reset mode The resolution of this counter is 64
27. architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K memory space The lower 5 bits of this register should be initialized to a logic 0 The channel controls the lower 5 bits to implement the ring buffer architecture Read this register to determine the location and number of interrupts within the Interrupt Log List least significant 5 bits Bit Bit Name Description 00 15 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 05 15 indicate the starting Base Address while bits 00 04 indicate the ring location of the Interrupt Log List Interrupt Log List Pointer Register BIT Word Register Address 000C H Read Write The BIT Word register contains information on the current status of the channel hardware The RT transmits the contents of the register upon reception of a Transmit BIT Word Mode Code The user defines the lower 8 bits of this register Bit Bit Name Description 15 DMAF DMA Fail 1 All the channel s internal DMA activity was not completed within 16 usec 14 WRAPF Wrap Fail The channel automatically compares the transmitted word encoder word to the reflected decoder word by way of the continuous loop back feature If the encoder word and reflected word do not match the WRAPF bit is set The loopback path is via the MIL STD 1553 bus transceiver 13 TAPF Terminal Address Par
28. assists the channel in message processing The following bits describe the receive subaddress descriptor Control Word The descriptor Control Word is initialized by the host and updated by the channel during Command post processing Bit Bit Name Description 08 15 07 06 05 04 03 02 01 00 Receive Control Word INDX INTX IWA IBRD BAC Reserved A B BRD NII Index Field These bits define multiple message buffer length The host uses this field to instruct the channel to buffer N messages N can range from 0 00 H to 256 FF H If buffer ping ponging is enabled the INDX field is don t care i e does not contain applicable information During ping pong mode operation you should initialize the index field to 00 H The RT does not perform multiple message buffering in the ping pong mode of operation The index decrements each time a complete message is transacted no message errors The index does not decrement if the subaddress is illegalized The channel can generate an interrupt when the index field transitions from one to zero see bit 07 Interrupt Index Equals Zero 1 Enables the generation of an interrupt when the index field transitions from 1 to 0 The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt When Accessed 1 Enables the generation of an interrupt when the
29. bits are active high and are reset to 0 unless otherwise stated Figure 5 1 illustrates the control registers for Bus Monitor mode Reserved Monitor Filter Register Lo Monitor Filter Register Hi Monitor Block Counter Register Initial Monitor Data Pointer Register Initial Monitor Command Block Pointer Register Reserved Time Tag Register BIT Word Register Interrupt Log List Pointer Register Pending Interrupt Register Interrupt Mask Register Current Command Block Register Operational Status Register Control Register Figure 5 1 Control Registers Map BM Mode EXC 1553PCI MCH User s Manual 0020 003E H 001E H 001C H 001A H 0018 H 0016 H 0010 0014 H 000E H 000C H 000A H 0008 H 0006 H 0004 H 0002 H 0000 H page 5 3 Chapter 5 5 1 1 page 5 4 Control Register Bus Monitor Operation Address 0000 H Read Write Use the Control Register to configure the channel for BM operation To make changes to the BM and to this register the STEX bit bit 15 must be logic 0 Note The user has 5 usec after the TERACT bit bit 00 of the Operational Status Register is active to stop operation Bit Bit Name Description 15 14 11 13 10 09 06 08 05 04 02 03 01 00 STEX SBIT Reserved ETCE ERTO Reserved BMTC BCEN Reserved INTEN Reserved Start Execution 1 Initiates cha
30. masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event An interrupt is masked only if the corresponding bit of this register is set to a logic 0 Bit Bit Name Description 12 15 Reserved Set to 0 11 MERR Message Error Interrupt 06 10 Reserved Set to 0 05 EOL End Of List Interrupt 04 ILLCMD Illegal Command Interrupt 03 ILLOP Illogical Opcode Interrupt 02 RTF Retry Fail Interrupt 01 CBA Command Block Accessed Interrupt 00 Reserved Set to 0 Interrupt Mask Register page 3 6 Excalibur Systems Chapter 3 Bus Controller Operation 3 2 5 Pending Interrupt Register Address 0008 H Read only The Pending Interrupt register is used to identify which of the interrupts occurred during operation The assertion of any bit in this register generates an interrupt Note All register bits are cleared on a host read Bit Bit Name Description 12 15 Reserved 11 MERR 06 10 Reserved 05 EOL 04 ILLCMD 03 ILLOP 02 RTF 01 CBA 00 Reserved Pending Interrupt Register EXC 1553PCI MCH User s Manual Ignore on read Message Error Interrupt 1 A message error occurred The channel can detect Manchester sync field word count 1553 word parity bit count and protocol errors This bit will be set and an interrupt generated if not masked after message processing is complete Ignore on read End Of List Interrupt 1
31. met the opcode appears as an execute and continue Excalibur Systems Chapter 3 Bus Controller Operation Opcode Field Name Definition 1010 Interrupt Continue This opcode instructs the channel to interrupt and continue pro cessing on the next command block When using this opcode no 1553 processing occurs 1011 Call This opcode instructs the channel to go to the command block as specified in the branch address location without processing this block The next command block address is saved in an internal register so that the channel may remember one address and return to the next command block No command processing takes place i e no 1553 1011 Call This opcode instructs the channel to go to the command block as specified in the branch address location without processing this block The next command block address is saved in an internal register so that the channel may remember one address and return to the next command block No command processing takes place i e no 1553 1100 Return to Call This opcode instructs the channel to return to the command block address saved during the Call opcode No command pro cessing takes place i e no 1553 1101 Reserved The channel will generate an illegal opcode interrupt if interrupt enabled and automatically stop execution if a reserved opcode is used 1110 Load Minor Frame This opcode instructs the channel to load the minor frame timer Timer MFT with the valu
32. set to 0 Current Command Block Register Interrupt Mask Register Address 0006 H Read Write EXC 1558PCI MCH interrupt architecture allows for the masking of all interrupts An interrupt is masked if the corresponding bit of this register is set to logic 0 This feature allows the host to temporarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event Bit Bit Name Description 12 15 Reserved Set to 0 11 MERR Message Error Interrupt 10 SUBAD Subaddress Accessed Interrupt 09 BDRCV Broadcast Command Received Interrupt 08 IXEQO Index Equal Zero Interrupt 07 ILLCMD Illegal Command Interrupt 00 06 Reserved Set to 0 Interrupt Mask Register Excalibur Systems Chapter 4 Remote Terminal Operation 4 1 5 Pending Interrupt Register Address 0008 H Read only The Pending Interrupt Register is used to identify events that generate interrupts The assertion of any bit in this register generates an interrupt A register read of the Pending Interrupt Register will clear all bits Bit Bit Name Description 12 15 Reserved 11 MERR 10 SUBAD 09 BDRCV 08 IXEQO 07 ILCMD 00 06 Reserved Pending Interrupt Register EXC 1553PCI MCH User s Manual Ignore on read Message Error Interrupt 1 A message error occurred The channel can detect Manchester sync field Word count errors
33. subaddress receives a valid Command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt Broadcast Received 1 Enables the generation of an interrupt when the subaddress receives a valid broadcast Command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Block Accessed The host initializes this bit to zero the channel overwrites the zero with a logic one upon completion of message processing Upon reading a one the host resets this bit to zero in preparation for the next message Set to 0 Buffer A B Indicates the last buffer accessed when buffer ping pong is enabled During initialization the host designates the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled Broadcast Received 1 Reception of a valid broadcast Command Notice II 1 Enables the use of the Broadcast Data Pointer as a buffer for Broadcast Command information 0 Broadcast information is stored in the same buffer as non broadcast information EXC 1553PCI MCH User s Manual page4 15 Chapter 4 4 2 2 page 4 16 Remote Terminal Operation Transmit Control Word Information contained in the Transmit Control Word assists the EXC 1558PCI MCH in message
34. 1 5V VCC B62 5V VCC Table 7 5 PCI Bus Edge Connector Pinouts EXC 1553PCI MCH User s Manual in ames Board Signa Names Ai TRSTA A2 12V TV A3 TMS A4 TDI A5 5V VGC A6 INTAF INTAn A7 INTC A8 5V VCC A9 RESERVED Ato 45V ATi RESERVED A12 Ae CONNECTOR KEY Ai4 RESERVED Ai5 RST RSTn A16 45V AT7 CNTF GNTn A18 GROUND GND A19 RESERVED A20 AD 30 AD30 A21 43 3V 13 8V A22 ADS AD28 A23 AD 26 AD26 A24 GROUND GND A25 AD 24 AD24 A26 IDSEL IDSEL A27 43 3V 13 8V A28 AD 22 AD22 A29 AD 20 AD20 A30 GROUND GND A31 AD 18 AD18 A32 AD 16 AD16 A33 3 3V 13 8V A34 FRAME FRAMEn A35 GROUND GND A36 TRDY TRDYn A37 GROUND GND A38 STOP STOPn A39 3 3V 13 8V A40 SDONE Adi SBOR A42 GROUND GND A43 PAR PAR A44 AD 15 AD15 A45 43 3V 13 8V A 6 AD 13 AD13 A47 ADIT ADTI A48 GROUND GND A49 ADIOS ADS A30 CONNECTOR KEY A51 A52 C BE OF C BEOUn A53 3 3V 3 8V A54 ADIOS ADG A55 AD 04 ADA A56 GROUND GND A57 AD O2 AD2 A58 AD 00 ADO A59 5V A60 REQG4 A61 45V VGC A62 5V VCC page 7 11 Chapter 7 7 5 4 7 6 page 7 12 cPCI Bus Connector Pinouts Mechanical And Electrical Specifications 25 5V N C N C 3 3V 5V GND 24 AD 1 45V N C AD 0 N C GND 23 3 3V AD 4 AD 3 5V AD 2 GN
35. 14 18 1C 20 24 H Power up value 00000000 H for each Size 32 bits The Base Address Registers are used by the system BIOS to determine the number size and base addresses of memory pages required by the board within host address space Two memory pages are required by the EXC 1553PCI MCH one for the dual port RAM and one for the Global Registers Register Offset Size Function Base Address 0 10H 512 K Byte Dual port RAM Base Address 1 14H 64 Byte Global registers Table 2 1 Base Address Registers Definition Each Base Address Register contains 32 bits Bit Description 04 31 Address of memory region with lower 4 bits removed 03 Always 0 memory is not prefetchable 01 02 Always 0 memory may be mapped anywhere 00 Always 0 indicates memory space Base Address Register 2 3 12 Cardbus CIS Pointer Address 28 H Power up value 00000000 H Size 32 bits The Cardbus Pointer is not implemented on the EXC 1558PCI MCH page 2 6 Excalibur Systems Chapter 2 2 3 13 2 3 14 2 3 15 2 3 16 2 3 17 PCI Architecture Subsystem ID Address 2C H Power up value 0000 H Size 16 bits Subvendor ID Address 2E H Power up value 0000 H Size 16 bits Expansion ROM Base Address Register XROM Address 30 H Power up value 00000000 H Size 32 bits The Expansion ROM Space is not implemented on the EXC 1558PCI MCH Reserved Address 34 3A H Power up value 0000000000000000 H Size 64 bits
36. 1553A B Operation RT Mode When configured as a remote terminal to meet MIL STD 1553A the EXC 1558PCI MCH will operate as follows Responds with a Status Word within 7usec Ignores the T R bit for all mode codes All mode codes are defined without data All mode codes use mode code transmit control and information Words Mode code 00000 is defined as dynamic bus control DBC Subaddress 00000 defines a mode code ME and TF bits are defined in the 1553 Status Word all other Status Word bits are programmable 1 e NO BUSY mode etc Broadcast of all mode codes except Mode Code 00000 DBC and mode code 00010 transmit Status Word if enabled 1s allowed To illegalize a Mode Code the user needs to illegalize both the receive and transmit versions llegalization of row 1F H is not automatic EXC 1553PCI MCH User s Manual page4 37 Chapter 4 Remote Terminal Operation page 4 38 Excalibur Systems Chapter 5 5 Bus Monitor Operation Bus Monitor Operation Chapter 5 describes EXC 1553PCI MCH operation in Bus Monitor BM mode The topics covered are 5 1 5 1 5 1 5 1 5 1 5 1 5 1 Bus Monitor Message Processing 5 2 5 1 1 Error Condition Message Processing 5 2 Control Registers BM Mode 5 3 5 1 1 Control Register 5 4 5 1 2 Operational Status Register
37. 553 Coupling Mode Select Jumpers JP2 JP17 on page 7 6 2 Make certain the computer power source is disconnected Insert the EXC 1558PCI MCH board into any PCI compatible slot EXC 1553cPCI MCH board into any cPCI compatible slot 3 For the EXC 1553PCI MCH tighten the board s PCI bracket with the slot screw to ground the board to the computer 4 Attach the user constructed cable to the board and to the communication bus The cable may be connected to and disconnected from the board while power to the computer is turned on but not while the board is transmitting Adding Excalibur Software Tools The standard software included with the EXC 1553PCI MCH carrier board is for Windows operating systems Software compatible with other operating systems is available and can be downloaded from our website www mil 1553 com To add the Excalibur Software Tools drivers see the readme txt file on the software diskette that came with your specific board Excalibur Systems Chapter 1 1 3 Introduction 1553 Bus Connections For short distances direct coupling may be used to connect the EXC 1553PCI MCH directly to another 1553 device To ensure data integrity you must make certain that the cable connecting the two devices is properly terminated with 78 Ohm resistors see Figure 1 2 High 78 Ohm lt Terminating gt Resistors Low 1553 Device Transformer Coupled EXC 1553PCI MCH Direct Coupled F
38. 6 Channel Interrupt Architecture page 6 4 Excalibur Systems Chapter 7 Mechanical And Electrical Specifications 7 Mechanical And Electrical Specifications Chapter 7 describes the mechanical and electrical specifications of the EXC 1558PCI MCH The topics discussed are TA Board Layout 00000 e rex ER SERE 7 2 7 1 1 EXC 1553PCI MCH Board Layout 7 2 7 1 2 EXC 1553cPCI MCH Board Layout 7 3 7 2 LED Indicators cebo lio A DERI 7 4 7 2 1 EXC 1553PC MCH LED Indicators 7 4 7 2 2 EXC 1553cPCI MCH LED Indicators 7 4 7 3 DIP Switches AIKA io a ab 7 4 7 3 1 Selected ID DIP Switch SW1J 7 4 7 3 2 Multiple Board Applications 7 5 T4 Jumpers 2 2 2 3 40x ce eee ee ae 7 6 7 4 4 Channel 0 Channel 3 1553 Coupling Mode Select Jumpers JP2 JP17 7 6 7 4 2 Factory Default Jumper Settings 7 6 7 5 Connectors oll leu murale E a a a 7 7 7 5 1 Connector Ji Pinouts 7 8 7 5 2 Communication I O Signals Description of Connector J1 7 9 7 5 3 PCI Bus Edge Connector Pinouts 7 11 7 5 4 CPCIBus Connector Pinouts 7 12 7 6 Power Requirements 000 e cece eee eee eee 7 12 EXC 1553PCI MCH User s Manual pa
39. Boards page 7 10 Excalibur Systems Chapter 7 7 5 3 PCI Bus Edge Connector Pinouts Mechanical And Electrical Specifications in ames oard Signa Names B1 12V 12V B2 TCK B3 GROUND GND B4 TDO B5 5V VCC B6 5V VCC B7 INTB B8 INTD B9 PRSNT1 GND B10 RESERVED B11 PRSNT2 E CONNECTOR KEY B14 RESERVED B15 GROUND GND B16 CLK CLK B17 GROUND GND B18 REQ REQn B19 5V 1 0 B20 AD 31 AD31 B21 AD 29 AD29 B22 GROUND GND B23 AD 27 AD27 B24 AD 25 AD25 B25 3 3V 3 3V B26 C BE 3f C BE3n B27 AD 23 AD23 B28 GROUND GND B29 AD 21 AD21 B30 AD 19 AD19 B31 3 3V 3 3V B32 AD 17 AD17 B33 C BE 21 C_BE2n B34 GROUND GND B35 IRDY IRDYn B36 3 3V 3 3V B37 DEVSEL DEVSELn B38 GROUND GND B39 LOCK LOCKn B40 PERR PERRn B41 3 3V 3 3V B42 SERRA SERRn B43 3 3v 3 3V B44 C BE 1 C_BEin B45 AD 14 AD14 B46 GROUND GND B47 AD 12 AD12 B48 AD 10 AD10 B49 GROUND GND E CONNECTOR KEY B52 AD 08 AD8 B53 AD 07 AD7 B54 3 3V 3 3V B55 AD 05 AD5 B56 AD 03 AD3 B57 GROUND GND B58 AD 0O1 AD1 B59 5V 1 0 B60 ACK64 B6
40. Bus Monitor Operation Pending Interrupt Register Address 0008 H Read only The Pending Interrupt register is used to identify which of the interrupts occurred during operation All register bits are cleared on a host read Bit Bit Name Description 12 15 Reserved Ignore on read 11 MERR Message Error Interrupt 1 A message error occurred The channel can detect Manchester sync field word count 1553 word parity bit count and protocol errors This bit will be set and an interrupt generated if not masked after message processing is complete 01 10 Reserved Ignore on read 00 MBC Monitor Block Counter Interrupt This bit is set if the channel s monitor block counter reaches 0 transition from 1 to 0 Note The monitor does not discriminate between error free messages and those messages with errors Interrupt Log List Pointer Register Address 000A H Read Write The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1558PCI MCH architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K word memory space Initialize the lower 5 bits of this register to a logic O by the host The channel controls the lower 5 bits to implement the ring buffer
41. CA larger than BA storage of next message begins at the address location pointed to by the TA pointer and CA is made equal to TA If CA is less than BA CA points to the next available memory location in the buffer 1 e CA 1 For transmit Commands the channel begins transmission of data from memory location CA 2 Reserve the first two locations for the message information Word and Time Tag Word After message processing completes the channel enters the message information Word and Time Tag Word into the circular buffer At the end of message processing the channel updates CA if no errors detected For CA larger than BA storage of the next message begins at the address location pointed to by the TA pointer and CA is made to equal TA If CA is less than BA CA points to the next available memory location in the buffer 1 e CA 1 Note In this mode the Message Information Word bit 5 reflects the reception of broadcast message via the BRD bit The channel generates a circular buffer empty full interrupt when the buffer reaches the end i e CA greater than BA and begins a new message at the top of the buffer Bit 08 of the Mask Register and bit 07 of the Descriptor Control Word mask enables the generation of the Full Empty interrupt Excalibur Systems Chapter 4 Data Words Time Tag Message Info Word CIRCULAR BUFFER Data Words Time Tag Message Info Word
42. Control Word information allows the channel to generate interrupts buffer messages and control message processing For a receive Command the Data List Pointer is read to determine the top of the data buffer The channel stores data sequentially from the top of data buffer plus two locations e g 0100H 0102H 0104H 0106H etc When processing a transmit Command the Data List Pointer is read to determine where Data Words are retrieved The channel retrieves Data Words sequentially from the address the Data List Pointer designates plus two 16 bit address locations The Broadcast Data Pointer allows for separate storage of non broadcast data from broadcast data per MIL STD 1553B Notice II The user enables or disables this feature via the Control Word s least significant bit When disabled the non broadcast and broadcast data is stored via Data List Pointer A or B For transmit Commands the Broadcast Data Pointer is not used The channel does not transmit any information on the receipt of a broadcast transmit Command The channel reads the descriptor block during Command processing i e after assertion of TERACT The channel reads the Control Word and three Data Pointers The channel then begins the acquisition of Data Words for either transmission or storage After transmission or reception the channel begins post processing The Descriptor Block is updated An optional interrupt log entry is performed after a descriptor update During
43. D 22 AD 7 GND 3 3V AD 6 ADI5 GND 21 3 3V ADI 9 AD 8 N C C BE O GND 20 AD 12 GND N C AD 11 AD 10 GND 19 3 3V AD 15 AD 14 GND AD 13 GND 18 SERR GND 3 3V PAR C BE 1 GND 17 3 3V N C N C GND PERR GND 16 DEVSEL GND N C STOPH LOCK GND 15 3 3V FRAME IRDY GND TRDY GND 12 14 KEY AREA 11 AD 18 AD 17 AD 16 GND C BE 2 GND 10 AD 21 GND 3 3V AD 20 AD 19 GND 9 C BE 3 IDSEL AD 23 GND AD 22 GND 8 AD 26 GND N C AD 25 AD 24 GND 7 AD 30 AD 29 AD 28 GND AD 27 GND 6 N C GND 3 3V CLK AD 31 GND 5 N C N C RST GND N C GND 4 N C GND N C N C N C GND 3 INTA N C N C 5V N C GND 2 N C 5V N C N C N C GND 1 5V 12V N C N C 5V GND PIN A B C D E F Table 7 6 cPCI Bus Connector Pinouts Power Requirements The power requirements for each channel installed on the EXC 1553PCI MCH board is 5V 9 200mA 0 duty cycle non transmitting on 1553 bus 5V O 400mA 25 duty cycle transmitting on 1553 bus 5V O 560mA 50 duty cycle transmitting on 1553 bus 5V 9 800mA 87 5 duty cycle transmitting on 1553 bus Example The maximum power requirements for a 2 channels installed 25 duty cycle per channel will be 5V 400mA x 2 800mA Excalibur Systems Chapter 8 Ordering Information 8 Ordering Information The EXC 1553PCI MCH and EXC 1553cPCI MCH are available in one two three or four channel versions When ordering the board indicate the number of channels you require
44. EXC 1553PCI MCH EXC 1553cPCI MCH MIL STD 1553 Test And Simulation Board For PCI Systems User s Manual ZN XCALISus EXCALIBUR SYSTEMS 311 Meacham Avenue Elmont NY 11003 Tel 516 327 0000 Fax 516 327 4645 e mail excalibur 9 mil 1553 com website www mil 1553 com Table of Contents Table of Contents 1 Introduction Al OVGOIVIQW cabra la Qe RUN a i 1 1 A sare egos Se repo td ECLERES SEDES 1 4 1 2 1 InstalingtheBoard 1 4 1 2 2 Adding Excalibur Software Tools 1 4 1 3 1553 Bus Connections 1 5 1 4 Note About Pointer Registers 1 7 1 5 Technical Support 1 7 2 PCI Architecture 2 1 Memory Structure 2 1 2 2 PCI Configuration Space Header 2 2 2 3 PCI Configuration Registers 2 3 2 3 1 Vendor Identification Register VID 2 3 2 3 2 Device Identification Register DID 2 3 2 3 3 PCI Command Register PCICMD 2 3 2 3 4 PCI Status Register PCISTS 2 4 2 3 5 Revision Identification Register RID 2 4 2 3 6 Class Code Register CLCD 2 5 2 3 7 Cache Line Register Size Register CALN
45. H operation in Bus Controller BC mode The topics covered are 3 4 Bus Controller Message Processing 3 2 3 2 Control Registers BC Mode 3 3 3 3 BC Architecture 3 10 3 341 Gontrol Wore io ci A RS Slee ius dee 3 11 3 3 2 1553 Command Words 3 14 dig Data Polnter eto beim aves v iube Mew vere We Emus 3 15 3 3 4 1553 Status Words llleeeee rn 3 15 3 35 Branch Address AA eee eee eee 3 15 3 36 Timer Value AA A ESIE ARA 3 15 3 4 Command Block Chaining 3 16 3 5 Memory Architecture 3 17 3 6 MIL STD 1553A B Operation BC Mode 3 18 EXC 1553PCI MCH User s Manual page 3 1 Chapter 3 3 1 page 3 2 Bus Controller Operation Bus Controller Message Processing To process messages the EXC 1558PCI MCH uses data supplied in the control registers along with data stored in RAM memory The channel accesses eight words stored in RAM memory called a command block The command block is accessed at the beginning and end of command processing Note In BC mode the channel does not need to re read the Command Block on a retry situation The user allocates memory spaces for the minor frame The top of the command blocks can reside at any address location Defined and entered into memory by th
46. I BUS I ADDR DATA lt gt ADDR DATA PCI Bus CNTRL SuMMIT XT 0 XFRMRS I gt ji CNTRL Interface EA Eusa BUS B T 1 0 CONNECTIONS XFRMRS Selected ID SuMMIT XT 1 ate BUSA DipSw BUSB I I I I I 1 I XFRMRS i SuMMIT XT 2 Busa BUS B I I I I 1 I I I 1 XFRMRS SuMMIT XT 3 gt BUS A BUS B LAA y Figure 1 1 EXC 1553PCI MCH Block Diagram EXC 1553PCI MCH User s Manual page 1 3 Chapter 1 1 2 1 2 1 1 2 2 page 1 4 Introduction Installation To operate the EXC 1558PCI MCH board Install the board in your computer Install the EXC 1558PCI MCH Software Tools Installing the Board Installation of the EXC 1553PCI MCH board is similar to that of all PCI Local bus boards The EXC 1558PCI MCH complies with the Plug and Play specification of the PCI standard As such its absolute address is determined by the BIOS at start up Warning Wear a suitably grounded electrostatic discharge wrist strap whenever handling the Excalibur board and use all necessary antistatic precautionary measures To install the EXC 1553PCI MCH 1 1553 devices may be connected to the 1553 bus either directly direct cou pled or via a bus coupling stub transformer coupled Use JUmpers JP2 JP17 to set the coupling mode to the 1553 bus es See 7 4 1 Channel 0 Channel 3 1
47. IAW 6 2 6 1 3 Interrupt Log List Address 6 3 Overview The EXC 1558PCI MCH interrupt architecture involves three Control Registers an Interrupt Log List and the interrupt line The three Control Registers include a Pending Interrupt Register Interrupt Mask Register and Interrupt Log List Register The Pending Interrupt Register contains information that identifies the events generating the interrupts The Interrupt Mask Register allows the user to mask or disable the generation of interrupts The Interrupt Log List Register contains the base address of a 32 word interrupt ring buffer The lower twelve interrupt bits of the Pending Interrupt Register are entered into the Interrupt Log List if the Interrupt Log List is enabled The interrupt architecture allows for the entry of 16 interrupts into a 32 word ring buffer The EXC 1558PCI MCH automatically handles the interrupt logging overhead Each interrupt generates two words of information to assist the host in performing interrupt processing The Interrupt Identification Word IIW identifies the type s of interrupt that occurred The Interrupt Address Word IAW identifies the interrupt source e g subaddress or command block via a 16 bit address EXC 1553PCI MCH User s Manual page6 1 Chapter 6 Channel Interrupt Architecture 6 1 1 Interrupt Identification Word IIW The Interrupt Identification Word is a 16 bi
48. N bit of the Control Register are don t care Excalibur Systems Chapter 4 4 4 2 2 Remote Terminal Operation MODE 2 CIRCULAR BUFFER RECEIVE MESSAGE PROCESSING The channel begins all message processing by reading the descriptor block of the subaddress or mode code Command received i e Control Word TA CA and MIB The channel begins storage of Data Word s starting at the location contained in the CA pointer The channel automatically updates the CA pointer internally as message processing progresses The channel stores the message information Word and Time Tag Word into the MIB after receiving the correct number of Data Words At the end of message processing the channel updates CA and the MIB Current Address Field CAF If CAF equals the specified MIB length CA is updated to TA and the MIB CAF is reset to zero If CAF is less than the specified MIB length CA and MIB CAF point to the next available memory location in each buffer Control Word bits 15 to 08 specify the MIB length For transmit Commands the channel begins transmission of data from memory location CA After message processing completes the channel enters the message information Word and Time Tag Word into the MIB At the end of message processing the channel updates CA and the MIB CAF If CAF equals the specified MIB length CA is updated to TA and the MIB CAF is reset to zero If CAF is less than the specified MIB length CA and MIB CAF point to the n
49. PCI Configuration Space Header as required by the PCI specification The registers contained in this header enable software to set up the Plug and Play operation of the board and set aside system resources MAX_LAT MIN_GNT Interrupt Pin Interrupt Line 3C H Reserved 0s 38 H Reserved 0s Cap pointer 34 H Expansion ROM Base Address not used 30H Subsystem ID Subsystem Vendor ID 2C H Cardbus CIS Pointer not used 0s 28 H Base Address Register 5 not used 24 H Base Address Register 4 not used 20 H Base Address Register 3 not used 1C H Base Address Register 2 not used 18 H Base Address Register 1 Global Registers 14H Base Address Register 0 Dual port RAM 10H BIST Header Type 0 Latency Timer Cache Line Size 0C H Class Code Rev ID 08 H Status Register Command Register 04 H Device ID Vendor ID 00 H 31 24 23 16 15 08 07 00 Figure 2 1 PCI Configuration Space Header page2 2 Excalibur Systems Chapter 2 2 3 2 3 1 2 3 2 2 3 3 PCI Architecture PCI Configuration Registers Vendor Identification Register VID Address 00 01 H Power up value 1405 H Size 16 bits The Vendor Identification register contains the PCI Special Interest Group vendor identification number assigned to Excalibur Systems Device Identification Register DID Address 02 03 H Power up value 4004 H Size 16 bits The Device Identifi
50. Provides ground reference for the digital signal connections Table 7 4 Communication I O Signals Descriptions of Connector J1 a To Synchronize with External Sources To synchronize a single EXC 1553PCI MCH board to an external system the external clock source must be connected to the EXTTCLKI signal See Figure 7 5 EXC 1553PCI MCH User s Manual page7 9 Chapter 7 Mechanical And Electrical Specifications SYNCHRONIZATION CLOCK OUT Becta EXTERNAL SYSTEM EXC 1553PCI MCH Figure 7 5 Synchronization of a single EXC 1553PCI MCH to an external system To synchronize an external system to a single EXC 1558PCI MCH board the EXTTCKLO signal needs to be connected to the external clock source SYNCHRONIZATION CLOCK IN EXTTCLKO EXTERNAL SYSTEM EXC 1553PCI MCH Figure 7 6 Synchronization of an external system to a single EXC 1553PCI MCH Note The synchronization clock signal may be connected to multiple targets to achieve system wide synchronization To Synchronize Between EXC 1553PCI MCH Boards To synchronize multiple EXC 1558PCI MCH boards the EXTTCLKO signal of one board needs to be connected to all the EXTTCLKI signals of the remaining boards EXTTCLKO gt e EXTTCLKI EXC 1553PCI MCH EXC 1553PCI MCH SELECTED ID 0 SELECTED ID 1 EXTTRSOn e EXTTCLKI EXC 1553PCI MCH SELECTED ID 2 Figure 7 7 Synchronization Between EXC 1553PCI MCH
51. T R bit 1 Broadcast Receive Mode Codes and Broadcast Transmit Mode Codes use the same decode scheme as receive mode codes Table 4 2 shows the illegalization register map For Receive Transmit Broadcast Receive and Broadcast Transmit blocks the numbers shown in the column under each bit number identify the specific subaddress or mode code in hex that the register bit illegalizes Logical O legal Logical 1 illegal Name Register Address H Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0020 OF OE OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Receive 0022 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 f 0024 OF OE OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Transmit 0026 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Broadcast 0028 OF 0E OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Receive 002A 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Broadcast 002C XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Transmit 002E XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Mode 0030 OF OE OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Code 0032 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Receive Mode 0034 OF 0E OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Code 0036 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Transmit Mode 0038 OF OE OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Broadcast 003 1F 4E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Receive Mode 003C OF 0E OD OC 0B OA 09 08 07 06 05 04 03 02 01 00 Br
52. The channel is at the end of the command block Illogical Command Interrupt The channel checks for RT to RT Terminal address field match RT to RT transmit receive bit mismatch and correct order and broadcast transmit commands If illogical commands occur the channel will halt execution 1 An illogical command i e Transmit Broadcast or improperly formatted RT to RT message has been written into the Command Block Illogical Opcode Interrupt 1 An illogical opcode i e any reserved opcode was used in the command block The channel halts operation if this condition occurs Retry Fail Interrupt 1 All programmed retries failed Command Block Accessed Interrupt 1 A command block was accessed Opcode 1010 if enabled Ignore on read page 3 7 Chapter 3 3 2 6 3 2 7 page 3 8 Bus Controller Operation Interrupt Log List Pointer Register Address 000A H Read Write The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1553PCI MCH architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K word memory space Initialize the lower 5 bits of this register to a logic O by the host The channel controls the lower 5 bit
53. a Pointer 1s read to determine where to store data words The channel stores data sequentially from the top memory location The channel also stores each status word associated with the message in the appropri ate location For normal 1553 commands only the first status word location will contain data For RT to RT commands the second status word location will con tain data The channel begins monitoring after Control Register bit 15 1 e Setting TERACT and STEX bits to 1 After reception the channel begins post processing Command post processing involves storing data to memory An optional interrupt log entry is performed after a monitor 1s entered Monitor Time Out MIL STD 1553A 9 usec MIL STD 1553B 15 usec Error Condition Message Processing When the monitor detects as error condition either in the Command Word Data Words or the RT s status the monitor block will not store the data The monitor block counter increments The initial message Data Pointer remains constant The monitor block pointer increments Message information bits of the monitor block are changed to reflect the error An interrupt is given indicating a message has occurred See Message Information Bits page page 12 Excalibur Systems Chapter 5 5 1 Control Registers BM Mode Bus Monitor Operation The control registers are read write unless otherwise stated All control registers must be accessed in word mode All Control Register
54. alibur Systems Chapter 3 3 2 8 3 2 9 Bus Controller Operation Minor Frame Time Register Address 000E H Read only The Minor Frame Timer register MFT reflects the state of the 16 bit MFT counter This counter is loaded via the Load Minor Frame Timer opcode Opcode 1110 Bit Bit Name Description 00 15 MFT 15 0 Minor Frame Timer These bits indicate the value of the timer Minor Frame Time Register Command Block Pointer Register Address 0010 H Read Write The Command Block Pointer register contains the location to start the Command Blocks After execution begins this register is automatically updated with the address of the next block Bit Bit Name Description 00 15 CBA 15 0 Command Block Address These bits indicate the starting location of the Command Block Command Block Pointer Register EXC 1553PCI MCH User s Manual page3 9 Chapter 3 3 3 page 3 10 Bus Controller Operation BC Architecture As defined in MIL STD 1553 the Bus Controller initiates all communications on the bus To comply with MIL STD 1553 bus controller requirements the EXC 1558PCI MCH uses a Command Block architecture that takes advantage of both control registers and RAM Each Command Word transmitted over the bus must be associated with a Command Block The Command Block requires eight contiguous 16 bit memory locations for each message These eight locations include a Control Word 1st location Com
55. ame Description 00 15 TT 15 0 Time Tag Counter Bits Time Tag Register RT Descriptor Pointer Register Address 0010 H Read Write Each subaddress and mode code has a reserved block of memory containing information about how to process a valid Command to that subaddress or mode code Located contiguously in memory these reserved memory locations are called a descriptor space The RT Descriptor Pointer register contains an address that points to the top of this memory space The channel uses the T R bit subaddress mode code field and mode code to select one block in the descriptor table for message processing The RT Descriptor Pointer register is static during message processing Bit Bit Name Description 00 15 RTDA 15 0 RT descriptor Address Bits RT Descriptor Pointer Register EXC 1553PCI MCH User s Manual page4 9 Chapter 4 4 1 10 page 4 10 Remote Terminal Operation 1553 Status Word Bits Register Address 0012 H Read Write The 1553 Status Word Bits register controls the outgoing MIL STD 1553 Status Word The host controls the Instrumentation Busy Terminal Flag Service Request and Subsystem Flag by writing to bits 09 through 00 of this register The channel s Status Word response reflects assertion of these bit s until negated by the host unless the Immediate Clear Function is enabled The Immediate Clear Function automatically clears these bits after being transmitted in a Status Word The Immediate
56. are Control Word Data Pointer A Data Pointer B Broadcast Data Pointer Data Buffer Data Buffer Broadcast Buffer N Message Message Information Word Time Tag N Data Words Figure 4 4 EXC 1553PCI MCH Descriptor Block Receive Excalibur Systems Chapter 4 4 2 6 Remote Terminal Operation Control Word Data Pointer A Data Pointer B M Inf Message Information Word XXXX hex Time Tag Data Data N Data Words Buffer Buffer A B Message N Figure 4 5 EXC 1553PCI MCH Descriptor Bock Transmit Ping pong Handshake Mode 0 The EXC 1558PCI MCH provides a mechanism to enable and disable buffer ping pong operation If ping pong is enabled during Remote Terminal operation data will be stored retrieved in alternative buffers each time a new message is processed If ping pong is disabled a single buffer will be used for all message processing The Handshake mechanism operates as follows Prior to starting Remote Terminal operation enable the buffer ping pong feature by writing a logical 1 to bit 02 of the Control Register During ping pong operation the remote terminal ping pongs between the two data buffers for each subaddress or mode code on a message by message basis Each unique MIL STD 1553 subaddress and mode code is assigned two data buffer locations A
57. at the RT s Status Word has the Message Error bit set 05 Status Word Response with the Busy bit set Bit time 16 in 1553A mode This condition is met if the channel detects that the RT s Status Word has the Busy bit set 04 Status Word Response with the Terminal Flag bit set Bit time 19 in 1553A mode This condition is met if the channel detects that the RT s Status Word has the Terminal Flag bit set 03 Status Word Response with the Subsystem Fail bit set Bit time 17 in 1553A mode This condition is met if the channel detects that the RT s Status Word has the Subsystem Fail bit set 02 Status Word Response with the Instrumentation bit set Bit time 10 in 1553A mode This condition is met if the channel detects that the RT s Status Word has the Instrumentation bit set 01 Status Word Response with the Service Request bit set Bit time 11 in 1553A mode This condition is met if the channel detects that the RT s Status Word has the Service Request bit set Condition Codes 1553 Command Words The next two locations of the BC Mode Command Block are for 1553 Command Words In most 1553 messages only the first Command Word needs to be initialized However in an RT to RT transfer the first Command Word 1s the Receive Command and the second Command Word is the Transmit Command Excalibur Systems Chapter 3 3 3 3 3 3 4 3 3 5 3 3 6 Bus Controller Operation Data Pointer The fourth location of the BC Mode Command Bl
58. ation Buffer MIB length the maximum MIB size is 256 Table 4 3 shows how the Control Word s most significant bits select the depth of the MIB The Control Words eight most significant bits remain static during message processing The second Word of the description block defines the top address TA of the Data circular buffer The TA pointer remains static during message processing The third descriptor Word identifies the current address 1 e CA of the Data circular buffer The application software reads the dynamic CA pointer to determine the current address of the Data buffer The channel increments the CA pointer at the end of message processing until the MIB buffer is full When the MIB wraps around the SuMMIT loads the CA pointer with the TA pointer The fourth Word in the descriptor block defines the top or base address of the Message Information Buffer 1 e MIB and the current MIB address 1 e offset from base address The SuMMIT enters the message information Word and Time Tag Word into the MIB for each message until the end of the MIB is reached When the MIB reaches the end the next message s message information Word and Time Tag Word is entered at the top of the MIB The MIB pointer is a semi static pointer The channel updates the current address field at the end of message processing The Base Address field remains static Note In this mode of operation bits INDX NII and A B of the descriptor Control Word and the PPE
59. atus Word 1 Allows the channel to automatically execute the Transmit Status Word mode code when configured for MIL STD 1553A mode operation Control Register Continued Excalibur Systems Chapter 4 Remote Terminal Operation 4 1 2 Operational Status Register Address 0002 H Read Write The Operational Status register provides pertinent status information for RT Mode and is not reset to 0000 H on reset Instead the bits A B_STD and RTA 4 0 are set to 1 Bit Bit Name Description 11 15 RTA 4 0 Remote Terminal Address Bits These five bits contain the remote terminal address The RTA4 bit is the MSB bit while the RTAO bit is the LSB bit 10 RTAPTY Terminal Address Parity Bit This bit is appended to the remote terminal address bus RTA 4 0 to supply odd parity The channel requires odd parity for proper operation 09 MSEL1 Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation 08 MSELO Mode Select 0 In conjunction with Mode Select 1 this bit determines the channel s mode of operation MSEL1 MSELO Mode Of Operation 0 0 BC Mode 0 1 RT Mode 1 0 BM Mode 1 1 RT Concurrent Monitor mode 07 A B STD Military Standard 1553A or 1553B This bit determines whether the channel will operate under MIL STD 1553A or 1553B protocol 1 Enables the XMTSW bit Bit 00 of the Control Register 15534 0 Automatically allows the channel to operate under the MIL STD 1553B pr
60. bed in section 7 5 4 cPCI Bus Connector Pinouts on page 7 12 EXC 1553PCI MCH User s Manual page 7 7 Chapter 7 7 5 1 page 7 8 Connector J1 Pinouts DN a ee al oo 3 42 e Figure 7 4 Connector J1 Front View Mechanical And Electrical Specifications 1 BUSALO 22 SHIELD 43 BUSAL1 2 BUSAHO 23 SHIELD 44 BUSAH1 3 BUSBLO 24 SHIELD 45 BUSBL1 4 BUSBHO 25 SHIELD 46 BUSBH1 5 N C 26 GND 47 NC 6 BUSAL2 27 SHIELD 48 BUSALS 7 BUSAH2 28 SHIELD 49 BUSAH3 8 BUSBL2 29 SHIELD 50 BUSBL3 9 BUSBH2 30 SHIELD 51 BUSBH3 10 N C 31 SHIELD 52 N C 11 N C 32 GND 53 N C 12 N C 33 SHIELD 54 N C 13 NC 34 SHIELD 55 N C 14 N C 35 SHIELD 56 N C 15 N C 36 SHIELD 57 N C 16 N C 37 GND 58 N C 17 EXTTCLKI 38 N C 59 EXTTCLKO 18 N C 39 N C 60 N C 19 N C 40 N C 61 N C 20 N C 41 N C 62 N C 21 NIC 42 GND 0 Table 7 3 Connector J1 Pinouts N C not connected Excalibur Systems Chapter 7 Mechanical And Electrical Specifications 7 5 2 Communication I O Signals Description of Connector J1 Signal Description BUSAHO Channel 0 Bus A high connection BUSALO Channel 0 Bus A low connection BUSBHO Channel 0 Bus B high connection BUSBLO Channel 0 Bus B low connection BUSAH1 Channel 1 Bus A high connection BUSAL1 Channel 1 Bus A low connection BUSBH1 Channel
61. cation register contains the EXC 1553PCI MCH device identification number PCI Command Register PCICMD Address 04 05 H Power up value 0000 H Size 16 bits The PCI Command register contains the PCI Command Bit Bit Name Description 10 15 Reserved Set to Os 09 Fast Back to Back Always set to 0 Enable 08 System Error Enable Always set to 0 07 Address Stepping Always set to 1 Support 06 Parity Error Enable Always set to 0 05 VGA Palette Snoop Always set to 0 Enable 04 Memory Write and Always set to 0 Invalidate Enable 03 Special Cycle Enable Always set to 0 02 Bus Master Enable Always set to 0 01 Memory Access Enable Always set to 1 00 I O Access Enable Since the EXC 1553PCI MCH board does not use l O space the value of this register is ignored PCI Command Register EXC 1553PCI MCH User s Manual page2 3 Chapter 2 2 3 4 PCI Status Register PCISTS Power up value 0080 H Size 16 bits PCI Architecture Address 06 07 H The PCI Status register contains the PCI status information Bit Bit Name Description 15 Detected Parity This bit is set whenever a parity error Error is detected It functions independently from the state of Command Register Bit 6 This bit may be cleared by writing a 1 to this location 14 Signaled System Not used Error 13 Received Master Not used Abort 12 Received Target Not used Abort 11 Signaled Target This bit is set whenever this device Abort aborts a cycle when ad
62. cessed by channel 0 LD3 CH 1 A message is being processed by channel 1 LD4 CH 2 A message is being processed by channel 2 LD5 CH 3 A message is being processed by channel 3 EXC 1553PCI MCH LED Indicators 7 2 2 EXC 1553cPCI MCH LED Indicators The EXC 1553cPCI MCH contains four LEDs on the front panel Each Led indicates that a message 1s being processed by that specific channel LED Name Indication LD1 CH 0 A message is being processed by channel 0 LD2 CH 1 A message is being processed by channel 1 LD3 CH 2 A message is being processed by channel 2 LD4 CH 3 A message is being processed by channel 3 EXC 1553cPCI MCH LED Indicators 7 3 DIP Switches The EXC 1558PCI MCH contains one DIP switch SW1 7 3 1 Selected ID DIP Switch SW1 This four contact DIP switch provides the board s Select ID It represents a four bit number of which position 1 is the most significant bit When a specific bit of the switch is open or off a value of 1 will be set for that bit closed or on a value of 0 will be set for that bit page 7 4 Excalibur Systems Chapter 7 Mechanical And Electrical Specifications 7 3 2 Multiple Board Applications To provide a unique Selected ID to identify a board by the application software in a multiple board application the DIP switch should be set differently for each board For example Board ID 1 ID 3 Bit 1 closed on closed on Bit 2 closed on closed on Bit 3 cl
63. channel loads the Terminal Address upon completion of the Control Register write that activates RT mode 4 9 Reset The software reset see Channel Reset Register page 2 11 is also equivalent to a hardware power on reset and takes 5 usec to complete Setting the Reset bit to 1 results in the immediate reset of the channel and termination of Command processing The user is responsible for the re initialization of the RT Mode for operation A Reset Remote Terminal mode code Mode Code 01000 T R 1 clears the encoder decoders resets the Time Tag enables the buses to the programmed host state and re enables the Terminal Flag for assertion This reset is performed after the transmission of the 1553 Status Word page 4 36 Excalibur Systems Chapter 4 Remote Terminal Operation 4 10 MIL STD 1553A B Operation RT Mode To maximize flexibility the EXC 1558PCI MCH can operate in many different systems that use various protocols Specifically two of the protocols that the channel may be used with are MIL STD 1553A and MIL STD 1553B To meet these protocols configure the channel through the Control register XMTSW Bit 00 and the Operational Status register A B_STD Bit 07 Table 4 5 defines the three ways to program the channel A B STD XMTSW RESULT protocol selected 0 X 1553B response 1553B Standard 1 0 1553A response 1553A Standard 1 1 1553A response auto execute the TRANSMIT STATUS WORD mode code Table 4 5 MIL STD
64. codes is defined in section 3 3 1 1 OPCODE DEFINTION on page 3 12 10 11 Retry Number These bits define the number of retries for each individual Command Block and if retry opcode is used If the Ping Pong Enable Bit bit 02 of the Control Register is not enabled all retries will occur on the programmed bus However if bit 02 is enabled the first retry will always occur on the alternate bus the second retry will occur on the primary bus the third retry will occur on the alternate bus and the fourth retry will occur on the primary bus Bit 11 Bit 10 No of Retries 0 1 1 1 0 2 1 1 3 0 0 4 09 Bus A B This bit defines on which of the two buses the command will be transmitted i e primary bus Logic 1 Bus A Logic 0 Bus B 08 RT RT This bit defines whether or not the present Command Block is an RT to Transfer RT transfer and if the channel should transmit the second command word Data associated with an RT to RT is always stored by the channel 01 07 Condition These bits define the condition code the channel uses for that particular Codes Command Block Each of the available condition codes is defined in section3 3 1 2 BC CONDTION CODES on page 3 14 00 Block Access The channel sets this bit to 1 indicating a protocol message error Message occurred in the RT s response For this occurrence the channel will Error overwrite this bit prior to storing the Control Word into memory An example of this type of error would be noi
65. command blocks and store Data Words until the count reaches 0 When the count reaches 0 the channel will simply wrap back to the initial values and start again Register Monitor Blocks Table 1 Register Data Storage Register Interrupt Log List Initial Monitor Block Pointer Register Msg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved Initial Monitor Data Pointer Register Memory Interrupt Log List Pointer Register Int Info Wd Monitor Block Figure 5 4 Msg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved Msg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved Memory Architecture for Bus Monitor Mode Excalibur Systems Chapter 5 5 1 Bus Monitor Operation RT Concurrent Monitor Operation For applications that require simultaneous Remote Terminal and Bus Monitor operation the channel should be configured as both a Remote Terminal and Bus Monitor This feature allows the RT to communicate on the bus for one specific address and to monitor the bus for other specific addresses Configuration as both Bus Monitor and RT precludes the channel from monitoring its own Remote Ter minal address When the channel is configured as both RT and Bus Monitor the RT has priority over the Bus Monitor For example commands to the RT will always take priority over commands for the Bus Monitor T
66. dressed as a target This bit can be reset by writing a 1 to this location 09 10 Device Select Set to 10 slow timing DEVSEL Timing Status 08 Data Parity Not used Reported 07 Fast Back to Set to 1 Back Capable 06 Reserved 05 66MHz capable Setto 0 04 Capability List Set to 1 enable 00 03 Reserved PCI Status Register 2 3 5 Revision Identification Register RID Address 08 H Power up value 01H Size 8 bits The Revision Identification register contains the revision identification number of the EXC 1553PCI MCH page 2 4 Excalibur Systems Chapter 2 2 3 6 2 3 7 2 3 8 2 3 9 2 3 10 PCI Architecture Class Code Register CLCD Address 09 0B H Power up value FF0000 H Size 24 bits The Class code Register value indicates that the EXC 1558PCI MCH does not fit into any of the defined class codes Cache Line Register Size Register CALN Address 0C H Power up value 00 H Size 8 bits Not used Latency Timer Register LAT Address 0D H Power up value 00 H Size 8 bits Not used Header Type Register HDR Address 0E H Power up value 00 H Size 8 bits The EXC 1558PCI MCH is a single function PCI device Built In Self Test Register BIST Address OF H Power up value 00 H Size 8 bits The Built In Self Test register is not implemented in the EXC 1558PCI MCH EXC 1553PCI MCH User s Manual page2 5 Chapter 2 PCI Architecture 2 3 11 Base Address Registers BADR Address 10
67. e A Channel Registers Block 32 20000 2003F H Control Registers Reserved 10000 1FFFF H Channel Reset Register OFFFE H 5 7 s Channel jdn Time Clock OFEFC H e egister c S Channel Memory Block 1553 x O Message Control Data Storage Wa ERSE Channel Registers Block 32 00000 0003F H Control Registers PCI Architecture Figure 2 2 EXC 1553PCI MCH Channel Memory Map Chapters 3 4 and 5 of the User s Manual explain the operation of the channels of the EXC 1553PCI MCH in each of the three modes Bus Controller Remote Terminal and Bus Monitor In each chapter the mode specific Control Registers and Memory Block are described page 2 10 Excalibur Systems Chapter 2 2 4 1 2 4 2 PCI Architecture Channel External Timer Clock Register Address OFFFC 2FFFC 4FFFC 6FFFC H Read Write The Channel External Timer Clock Register selects the external timer clock value for the channel s timer In normal operation the channel uses an internal fixed clock 64 usec However the channel can be programmed to use an external user defined clock See the ETCE bit 10 in Bus Controller Control Register on page 3 4 and Bus Monitor Mode Control Register on page 5 4 A hardware or software reset will reset the external timer clock to its default value 64 usec The external timer clock has a range of 4 usec 250 KHz to 126 usec 8 KHz Bit Description 06 15 Don t care 00 05 Timer Clock Value Valid valu
68. e BC Mode Command Block is the Timer Value This timer 1s used Toset up minor frame schedules when using the Load Minor Frame Timer opcode 1110 The MFT counter is clocked by a 15 625 KHz 64 usec internal clock The MFT counter runs continuously during message processing and must decrement to zero prior to loading the next Minor Frame time value Asa message to message timer MMT when using the Skip opcode 0001 The MMT timer 1s clocked at the 24 MHz 41 666 nsec rate and allows for scheduling of specific time between message execution EXC 1553PCI MCH User s Manual page 3 15 Chapter 3 3 4 page 3 16 Bus Controller Operation Command Block Chaining To determine the first Command Block set the initial start address in the Command Block Pointer Register Address 0010 H The Command Blocks will execute in a contiguous fashion as long as no go to branch call or return opcodes are used With the use of these opcodes almost any memory configuration is possible Figures 3 5 and 3 6 show how several Command Blocks may be linked together to form a command frame and how branch opcodes may be used to link minor frames The minimum BC intermessage gap is 28 0 usec FRAME SN RETRIES CONDITIONAL FAIL BRANCH ERROR SERVICE FRAME FRAME RETURN RETURN h Figure 3 5 Message Conirol Options The example in Figure 3 6 shows a configuration o
69. e Word Count Mode P Code Data Word Status Word Sync RT Address Reserved P Message Error Instrumentation Service Request Broadcast Command Received Busy Subsystem Flag Dynamic Bus Control Acceptance Terminal Flag Figure A 1 MIL STD 1553 Word Formats Note T R Transmit Receive P Parity EXC 1553PCI MCH User s Manual page A 1 page A 2 Excalibur Systems Appendix B MIL STD 1553 Message Formats Receive Data Data Data Status Next Command Word Word Word Word Command Transmit A Status Data Data Data i Next Command Word Word Word Word Command Receive Transmit A Status Data Data Data x Status t Next Command Command Word Word Word Word Word Command Mode M Status Next Command Word Command Mode n Status Data Next Command Word Word Command Mode Data n Status Next Command Word Word Command Receive Data Data Data Next Command Word Word Word Command Receive Transmit Status Data Data Data Command Command Word Word Word Word Mode s Next Command Command Mode Data Next Command Word Command Figure B 1 MIL STD 1553 Message Formats Note Response time ntermessage Gap EXC 1553PCI MCH User s Manual Next Command page B 1 The information contained in this document is believed to be accurate How ever no responsibility is assumed by Excalibur Systems Inc for its use and
70. e data into a circular buffer along with message information For each valid receive message the channel enters a message information Word Time Tag Word and Data Word s into a unique receive circular buffer For each valid transmit message the channel enters a message information Word and Time Tag Word into reserved memory locations within the transmit circular buffer The channel automatically controls the wrap around of circular buffers MODE 1 DESCRIPTOR BLOCK Each subaddress and mode code both transmit and receive has a unique circular buffer assignment The channel decodes the Command Word T R bit subaddress mode code field and Word count mode code field to select a unique descriptor block that contains Control Word TA CA and BA see Figure 4 6 RT Mode 1 Descriptor Block And Circular Buffer on page 4 29 To implement Circular Buffer 1 s architecture the 4 word descriptor block and Control Register are different than in the Mode 0 Bits 15 through 08 of the Control Word are don t care The second Word of the descriptor block defines the buffer s starting or top address TA The TA pointer remains static during message processing The fourth entry into the descriptor block identifies the buffer s bottom address i e BA and remains static during message processing The third descriptor block Words represent the current address 1 e CA in the buffer and 1s dynamic If the channel observes no message error condition
71. e stored in the eighth location of the current command block The timer will be loaded after the previous MFT has decremented to zero After the MFT timer is loaded with the new value the channel will proceed to the next com mand block No command processing takes place i e no 1553 1111 Return to Branch This opcode instructs the channel to return to the command block address saved during a Branch opcode No command processing takes place i e no 1553 Opcode Definition Continued Note For entries with interrupts enabled all interrupts are logged after message processing 1s completes EXC 1553PCI MCH User s Manual page 3 13 Chapter 3 3 3 1 2 3 3 2 page 3 14 Bus Controller Operation BC CONDTION CODES Condition codes have been provided as a means for the EXC 1553PCI MCH to perform certain functions based on the RT s Status Word In an RT to RT transfer the conditions apply to both of the Status Words Each bit of the condition codes is defined below Bit Number Description 07 Message Error This condition will be met if the channel detects an error in the RT s response or if it detects no response The channel will wait 15 usec in 1553B mode and 9 usec in 1553A mode before declaring an RT no response see section 3 6 MIL STD 1553A B Operation BC Mode on page 3 18 06 Status Word Response with the Message Error bit set Bit time 09 in 1553A mode This condition is met if the channel detects th
72. e user the control registers are linked to the Command Block via the Command Block Pointer Register contents Each command block contains a Control Word Command Word1 Command Word2 Data Pointer Status Word 1 Status Word 2 Branch Address Timer Value Figure 3 1 Command Block Architecture BC Mode See section 3 3 BC Architecture on page 3 10 for a description of each location Control Word information allows the channel to control the commands transmitted over the 1553 bus The Control word allows the channel to transmit commands on a specific bus perform retries initiate RT to RT transfers and interrupt on certain conditions The host defines each Command Word associated with each command block For normal 1553 commands only the first Command Word location will contain valid data For RT to RT commands as specified in the Control Word the host must define the first Command Word as a receive and the second Command Word as a transmit For a receive command the Data Pointer 1s read to determine where Data Words are retrieved The channel retrieves Data Words sequentially from the address specified by the Data Pointer For a transmit command the Data Pointer is read to determine the top memory location The channel stores Data Words sequentially from this top memory location The channel reads the command block during minor frame processing The channel then begins the acquisition of Data Wo
73. e user reads the ring buffer pointer value to determine the number of interrupts that have occurred By extracting the least significant five bits from the Interrupt Log List Register and logical shifting the data once to the right the host determines the number of interrupt events Ring Buffer Pointer T Base Address 00 H IIW 1 Base Address 20 H IIW 9 Base Address 02 H IAW 1 Base Address 22 H IAW 9 Base Address 04 H IIW 2 Base Address 24 H IIW 10 Base Address 06 H IAW 2 Base Address 26 H IAW 10 Base Address 08 H IIW 3 Base Address 28 H IIW 11 Base Address OA H IAW 3 Base Address 2A H IAW 11 Base Address OC H IW 4 Base Address 2C H IIW 12 Base Address OE H IAW 4 Base Address 2E H IAW 12 Base Address 10 H IIW 5 Base Address 30 H IIW 13 Base Address 12 H IAW 5 Base Address 32 H IAW 13 Base Address 14 H IW 6 Base Address 34 H IIW 14 Base Address 16 H IAW 6 Base Address 36 H IAW 14 Base Address 18 H IW 7 Base Address 38 H IIW 15 Base Address 1A H IAW 7 Base Address 3A H IAW 15 Base Address 1C H IW 8 Base Address 3C H IIW 16 Base Address 1E H IAW 8 Base Address 3E H IAW 16 Interrupt Log List Interrupt Log List Address Register Contents Address Register Contents Table 6 1 Interrupt Ring Buffer EXC 1553PCI MCH User s Manual page 6 3 Chapter
74. eee eee eee eee 4 35 4 7 RT to RT Transfer Compare 4 36 48 Terminal Address nnananan 4 36 4 9 Heset o oue rue lup ee ERR ha cha cad 4 36 4 10 MIL STD 1553A B Operation RT Mode 4 37 Note The EXC 1553PCI MCH can be configured both as a Remote Terminal and as a Bus Monitor For more information about this feature see section 5 1 RT Concurrent Monitor Operation on page 5 15 EXC 1553PCI MCH User s Manual page4 1 Chapter 4 4 1 page 4 2 Control Registers Remote Terminal Operation The Control registers are read write unless otherwise stated All Control registers must be accessed in Word mode All Control register bits are active high and are reset to 0 unless otherwise stated Figure 4 1 below illustrates the Control registers for Remote Terminal mode Illegalization Registers 16 registers Reserved 1553 Status Word Bits Register RT Descriptor Pointer Register Time Tag Register BIT Word Register Interrupt Log List Pointer Register Pending Interrupt Register Interrupt Mask Register Current Command Block Register Operational Status Register Control Register 0020 003E H 0014 001E H 0012 H 0010 H 000E H 000C H 000A H 0008 H 0006 H 0004 H 0002 H 0000 H Figure 4 1 Control Registers Map RT Mode Excalibur Systems Chapter 4 4 1 1 Control Register R
75. egister 2 13 2 5 5 Channel Info Registers 2 14 2 5 6 External Timer Clock Source Register 2 14 EXC 1553PCI MCH User s Manual page i Table of Contents 3 Bus Controller Operation 3 1 Bus Controller Message Processing 3 2 3 2 Control Registers BC Mode 3 3 3 2 1 Control Register 3 4 3 2 2 Operational Status Register 3 5 3 2 3 Current Command Register 3 6 3 2 4 Interrupt Mask Register 3 6 3 2 5 Pending Interrupt Register 3 7 3 2 6 Interrupt Log List Pointer Register 3 8 3 2 7 BIT Word Bi IIIA KAA ka tees 3 8 3 2 8 Minor Frame Time Register 3 9 3 2 9 Command Block Pointer Register 3 9 3 3 BC Architecture 3 10 SSA Gontrol Wordt ta a tons AINA aio PR S 3 11 3 3 2 1553 Command Words 000 cece tenes 3 14 33 39 Data POMOR eiere tE sorda ra E be ad fx 3 15 33 4 1553 Status Words 10 tii ad 3 15 33 5 Branch Address ssi ns elu rara va 3 15 3 39 6 Timer Vall II E ai 3 15 3 4 Command Block Chaining 3 16 3 5 Memory Architecture
76. el Executing This read only bit indicates whether the channel is presently executing or is idle 1 The channel is executing 0 The channel is idle 02 Reserved This read only bit is not applicable 01 Ready Channel Reagy This read only bit is cleared on reset 1 The channel has completed initialization or BIT and regular operation may begin 00 TERACT Channel Terminal Active This read only bit is cleared on reset 1 The channel is presently processing a 1553 message Note When STEX transitions from 1 to 0 EX and TERACT stay active until command processing is complete Operational Status Register EXC 1553PCI MCH User s Manual page3 5 Chapter 3 Bus Controller Operation 3 2 3 Current Command Register Address 0004 H Read only The Current Command register contains the last 1553 command that was transmitted by the channel Upon the execution of each Command Block this register will automatically be updated This register is updated when transmission of the Command Word begins In an RT to RT transfer the register will reflect the latest Command Word as it is transmitted Bit Bit Name Description 00 15 CC 15 0 Current Command These bits contain the latest 1553 command that was transmitted by the Bus Controller Current Command Register 3 2 4 Interrupt Mask Register Address 0006 H Read Write The BC Mode interrupt architecture allows the host to mask or temporarily disable the service of interrupts While
77. emote Terminal Operation Address 0000 H Read Write Use the Control register to configure the channel for RT operation To make changes to the RT mode and this register the STEX bit Bit 15 must be logic 0 Bit Bit Name Description 15 14 13 12 11 10 09 07 08 05 06 04 STEX SBIT Reserved BUAEN BUBEN Reserved PPACK RTM 1 0 Reserved BCEN Control Register EXC 1553PCI MCH User s Manual Start Channel Execution 1 Initiates channel operation 0 Inhibits channel operation A remote terminal address parity error prevents RT Mode operation regardless of the logical state of this bit If an RT address parity error exists bit 03 of the Operational Status Register will be set low and bit 02 of the Operational Status Register will be set high Start Channel BIT 1 Places the channel into the Built In Test routine The BIT routine takes 1 msec to execute and has a fault coverage of 93 4 If the channel has been started the host must halt the channel in order to place the channel into the Built In Test mode STEX 0 Note f Start BIT SBIT and Start Execution STEX are both set on one register write SBIT has priority Set to 0 Bus A Enable 1 Enables Bus A operation 0 The channel does not recognize Commands received over Bus A Bus B Enable 1 Enables Bus B operation 0 The channel does not recognize Commands received over Bus B Set to 0 Ping P
78. ents the logging of interrupts as they occur Set to 0 Excalibur Systems Chapter 5 Bus Monitor Operation 5 1 2 Operational Status Register Address 0002 H Read Write The Operational Status Register reflects pertinent status information for the channel and is not reset to 0000 H on reset Instead the bit A B_STD is set to 1 Note To make changes to the Monitor and this register the STEX bit Bit 15 in the Control Register must be logic 0 Bit Bit Name Description 10 15 09 08 07 04 06 03 02 01 00 Reserved MSEL1 MSELO A B_STD Reserved EX Reserved Ready TERACT Set to 0 Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation Mode Select 0 In conjunction with Mode Select 1 this bit determines the channel s mode of operation MSEL1 MSELO Mode of Operation 0 0 BC 0 1 RT 1 0 BM 1 1 RT Concurrent BM Mode Military Standard 1553A or 1553B This bit determines if the channel will operate under MIL STD 1553A or 1553B protocol 1 Forces the channel to declare a time out error condition if the RT9 has not responded in 9 usec 0 Allows the channel to declare a time out error condition if the RT has not responded in 15 usec These read only bits are not applicable Channel Executing This read only bit indicates whether the channel is presently executing or is idle 1 The channel is executing 0
79. eration Bus Monitor Message Processing To process messages the EXC 1553PCI MCH uses data supplied in the Control Registers along with RAM memory There are eight 16 bit memory locations for each message called a monitor block seven are used and one is reserved The monitor block is updated at the end of command processing The following para graphs discuss the command block in detail The user allocates memory spaces for each monitor block The top of the monitor blocks can reside at any address location The Control Registers are initialized by the host and linked to the Monitor Block via the Initial Monitor Block Pointer Register and the Monitor Block Counter Register contents Each monitor block contains a Message Information Word Command Word 1 Command Word 2 Data Pointer Status Word 1 Status Word 2 and Time Tag For a full description of each location see section Bus Monitor Architecture on page 11 The Message Information Word allows the channel to inform the user on which bus the command was received whether the message was an RT to RT transfer and conditions associated with the message The channel also stores each Com mand Word associated with the message in the appropriate location For normal 1553 commands only the first Command Word location will contain data For RT to RT commands the second Command Word location will contain data and bit 08 in the Message Information Word will be set For each command the Dat
80. es Supports up to 4 MIL STD 1553 independent dual redundant channels Operating Environment Humidity 5 90 noncondensing Temperature 0 70 C 40 85 C Extended temp option Physical Characteristics Dimensions PCI board 157 mm x107 mm cPCI board 160 mm x100 mm Weight with 4 channels 220 grams EXC 1553PCI MCH Half size PCI card EXC 1553cPC MCH Standard cPCI size Host Interface PCI Compliance Target 16 bit 5V only 8 and 32 bit operations may not be performed Memory space occupied 512 Kbytes Interrupts INTA Power Depends on configuration Software Support C Drivers with source code Features per Channel Operates as BC RT BM or RT Concurrent BM Multiple protocol capability MIL STD 1553A MIL STD 1553B Autonomous operation in all modes e 32K Word memory mapped RAM e 32 Control registers Polling or interrupt driven Real time operation Built in Test capability BC Mode Major Minor frames Programmable Intermessage gap Automatic retry RT Mode Single RT simulation Subaddress double buffering Circular buffer mode Message illegalization 16 bit Time Tag Programmable broadcast mode BM mode 16 bit Time Tag Filtering per RT Interrupt history list Programmable monitor block count See Chapter 8 Ordering Information for exact part numbers Excalibur Systems Chapter 1 Introduction Figure 1 1 is a block diagram of the EXC 1553PCI MCH PCI J1 I
81. es 0001 H 250 KHz 003E H 7 94 KHz Channel External Timer Clock Register To formulate the Timer Clock Value TCV 1 000 000 2xF F Desired frequency HZ 7 94 KHz 250 KHz TCV 1 Example Desired programmable Timer Clock frequency is 10 KHz 100 usec resolution 1 000 000 210 000 Write 00031 H to the register TCV 1 50 1 49Dec 31 H Channel Reset Register Address OFFFE 2FFFE 4FFFE 6FFFE H Read Write Writing to a Channel Reset Register data don t care performs a software reset of that channel The channel will act as if the power had been switched off and then on encoder decoder all control registers and associated logic will be reset Note Writing to this register immediately terminates command processing The reset operation takes 5 psec to execute EXC 1553PCI MCH User s Manual page 2 11 Chapter 2 PCI Architecture 2 5 Global Registers Map The board global registers reside in the second memory block Board ID 00 H Software Reset 02 H Interrupt Status 04 H Interrupt Reset 06 H Channel 0 Info 08 H Channel 1 Info 0A H Channel 2 Info 0C H Channel 3 Info OE H External Timer Clock 10 H Source Register Reserved 12 SF H Figure 2 3 EXC 1553PCI MCH Global Registers Map 2 5 1 Board Identification Register Address 0 H Length 16bits The Board Identification register comprises three identification items Bit Descriptio
82. ess matches the Terminal Address of the transmitting RT specified in the Command Word An incorrect match results in setting the message error bit and suppressing transmission of the Status Word RT to RT transfer time out 55 to 59 usec The channel does not check ME or SSYSF of the transmitting remote terminal when receiving 4 8 Terminal Address The EXC 1558PCI MCH Terminal Address is programmed via the most significant six bits in the Operational Status Register RTA 4 0 and RTPTY The Terminal Address parity 1s odd RTPTY is set to a logic state to satisfy this requirement When the Operational Status Register bit 02 TAPF is set this indicates incorrect Terminal Address parity The Operational Status Register bit 02 is valid after the rising final edge of a reset For example RTA 4 0 05 H 00101 RTPTY 1 H 1 Sum of 1s 3 odd Operational Status Register Bit 02 0 RTA 4 0 04 H 00100 RTPTY 0 H 0 Sum of 1s 1 odd Operational Status Register Bit 02 0 RTA 4 0 04 H 00100 RTPTY 1 H 0 Sum of 1s 2 even Operational Status Register Bit 02 0 Note The channel checks the Terminal Address and parity after RT mode operation has been started With Broadcast disabled RTA 4 0 11111 operates as a normal RT address The BIT Word Register parity fail bit is valid after RT mode has been started The Terminal Address is also programmed via a write to the Operational Status Register The
83. ext available memory location in each buffer Note In this mode the BRD bit is added to the Message Information Word bit 05 The channel generates a circular buffer empty full interrupt when the MIB reaches the end and begins a new message at the top of the buffer Bit 08 of the Mask Register and bit 07 of the Descriptor Control Word mask enable the generation of the Full Empty interrupt Control Word Length of MIB MIB Pointer Structure Bits 8 15 messages Base and CAF FF 128 8 Bit Base Address 8 Bit Current Address Field 7F 64 9 Bit Base Address 7 Bit Current Address Field 3F 32 10 Bit Base Address 6 Bit Current Address Field 1F 16 11 Bit Base Address 5 Bit Current Address Field OF 8 12 Bit Base Address 4 Bit Current Address Field 07 4 13 Bit Base Address 3 Bit Current Address Field 03 2 14 Bit Base Address 2 Bit Current Address Field 01 1 15 Bit Base Address 1 Bit Current Address Field Table 4 3 RT Mode 2 Control Word and MIB Pointer Structure EXC 1553PCI MCH User s Manual page 4 31 Chapter 4 Remote Terminal Operation Figure 4 7 describes the relationship between the top address TA current address CA and Message Information Buffer MIB Message Info Word c Message Info Word Data Circular Buffer Message Information Circular Buffer MIB Length 15 8 7 0 Descriptor Block Control Word Figure 4 7 RT Mode 2 Descriptor Block page 4 82 Excalibur System
84. f four minor frames in which Message A is sent in every frame Message B is sent in every other frame and Message C is sent once Each minor frame goes out at 10 msec 100Hz If each minor frame is 10 usec long Message A is sent every 10 msec Message B is sent every 20 usec and Message C is sent every 40 usec MINOR MINOR MINOR MINOR FRAME FRAME FRAME FRAME 1 2 3 4 A A A A B B Cc 10 msec 10 msec 10 msec 10 msec MN 4 Figure 3 6 Minor Frame Sequencing Excalibur Systems Chapter 3 Bus Controller Operation 3 5 Memory Architecture After reviewing the control registers it is advantageous to look at how to set up memory to configure the EXC 1553PCI MCH as a Bus Controller This section shows one method for defining the memory configuration The configuration shows the Command Blocks data locations and the Interrupt Log List as separate entities Figure 3 7 shows that the first block of memory is allocated for the Command Blocks Notice that the Command Block Pointer Register initially points to the control word of the first Command Block After completing execution of that first Command Block the Command Block Pointer Register will automatically be updated to show the address of the next Command Block Following the Command Block locations is the memory required for all the data words In BC applications the number of data word
85. ferences to the EXC 1553PCI MCH apply also to the EXC 1558cPCI MCH For mechanical and electrical differences between the PCI and the cPCI boards see Chapter 7 Mechanical And Electrical Specifications on page 7 1 Overview The EXC 1553PCI MCH is an intelligent MIL STD 1553 PCI interface board for avionics test and simulation applications Available in one two three or four channel versions the EXC 1553PCI MCH provides a complete solution for developing and testing 1553 interfaces and performing system simulation of the MIL STD 1553 bus All standard variations of the MIL STD 1553 protocol are handled by the board Each channel of the EXC 1558PCI MCH contains 32k x 16 of dual port RAM for Data blocks Control registers and Look up tables All Data blocks and Control registers are memory mapped and may be accessed in real time Each of the independent dual redundant 1553 channels may be programmed to operate in one of four modes of operation Bus Controller Remote Terminal RT Concurrent Bus Monitor and Bus Monitor The EXC 1558PCI MCH comes complete with Windows software and a C driver software library including source code and one mating connector The EXC 1553PCI MCH E option is an extended temperature 40 to 85 C ruggedized version of the board for industrial or harsh environmental conditions EXC 1553PCI MCH User s Manual page 1 1 Chapter 1 page 1 2 Introduction EXC 1553PCI MCH and EXC 1553cPCI MCH Board featur
86. for all 16 Jumpers Coupling Mode Setting Direct Coupled Short pins 2 and 3 of channel 0 3 jumper group Transformer Coupled Short pins 1 and 2 of channel 0 3 jumper group Table 7 1 Jumper Settings Required to Select Coupling Mode Table 7 2 defines the Jumper groups for each channel Ww c o Channel 0 Jumper Group JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12 JP13 JP14 JP15 JP16 JP17 W gt U gt uwu uv gt ou gt Cc wo N N Table 7 2 Channel Jumper Groups Example To set channel 0 to transformer coupled short with a shorting block pins 1 and 2 of JP2 JP3 JP4 and JP5 Factory Default Jumper Settings The factory default settings are JP2 JP17 Pins1 amp 2 Shorted Transformer coupled mode Excalibur Systems Chapter 7 Mechanical And Electrical Specifications 7 5 Connectors The EXC 1553PCI MCH and the EXC 1553cPCI MCH each contain two connectors 1 Afemale high density DB 62 pin connector J1 P N HDL 628LC PCB that contains all the communications signals required for the four channels Mating connectors P N HDT 62 DB with plastic hoods are included The connector pinouts and signals are described in sections 7 5 1 and 7 5 2 2 EXC 1553PCI MCH PCI Bus Edge Connector The connector pinouts and signals are described in section 7 5 3 PCI Bus Edge Connector Pinouts on page 7 11 Or EXC 1553cPCI MCH Compact PCI Bus Connector The connector pinouts and signals are descri
87. ge 7 1 Chapter 7 Mechanical And Electrical Specifications 7 1 Board Layout 7 1 1 EXC 1553PCI MCH Board Layout Lis PWR CH 0 en pua pu hie zl zA il m imm OL CHANNEL 1 CHANNEL 2 CHANNEL 3 SL T6 3 15 N e co a m lu m Sl m 5 a LA CHANNEL4O AA m 1 n Lo M 2 E u im O 157mm 6 18 a 6 18 Figure 7 1 EXC 1553PCI MCH Board Layout page 7 2 Excalibur Systems 107mm 4 2 Chapter 7 Mechanical And Electrical Specifications 7 1 2 EXC 1553cPCI MCH Board Layout Iz T8 LL LEDS ws L Front Panel JP15 TN T7 mm o 2 E CHANNEL 1 CHANNEL 2 CHANNEL 3 gt T6 T a y a yg P U2 U6 U8 T4 q 13 TT Compact PCI BUS MATING CHANNEL O i CONNECTOR 1 83 L o mm O WH S um r n la a IN U1 P1 160mm 6 29 YN T Figure 7 2 EXC 1553cPCI MCH Board Layout EXC 1553PCI MCH User s Manual page7 3 Chapter 7 Mechanical And Electrical Specifications 7 2 LED Indicators 7 2 1 EXC 1553PCI MCH LED Indicators The EXC 1553PCI MCH contains five LEDs LED Name Indication LD1 PWR Power is being supplied to the board LD2 CH 0 A message is being pro
88. he examples below describe what happens if the RT 1s defined for terminal address 1 and the Bus Monitor is to monitor ter minal address 12 Example 1 Bus A CMD TA 12 Bus B CMD TA 1 In this example the Bus Monitor will decode the first command on bus A realize the message is for terminal address 12 and start monitoring the message How ever as soon as the channel realizes the second command on bus B is to terminal address 1 the RT will take priority and begin RT message processing Example 2 Bus A CMD TA 1 Bus B CMD TA 12 In Example 2 the RT will decode the first command on bus A realize the message is for terminal address 1 and start message processing As the message on bus B 1s received the channel will realize it is to terminal address 12 but since the RT has priority the Bus Monitor will not switch to the bus monitor mode The above examples also apply to an RT to RT message For example if the first command in an RT to RT transfer matches the terminal address of the RT the entire message will be stored Message 1 However if the first command in an RT to RT transfer matches the terminal address of the Bus Monitor and the sec ond command matches the terminal address of the RT the RT will take priority and only the RT message is stored Message 2 Example 3 Message 1 CMD TA 1 CMD TA 12 Message 2 CMD TA 12 CMD TA 1 This is an RT to
89. ialize the descriptor Control Word and the channel updates it during Command post processing Note In MIL STD 1553A all mode codes are without data and the T R bit is ignored Bit Bit Name Description 07 15 Reserved Setto 0 06 IWA Interrupt When Accessed 1 Enables the generation of an interrupt when mode code Command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing 05 IBRD Interrupt Broadcast Received 1 Enables the generation of an interrupt when a broadcast mode code is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing 04 BAC Block Accessed The host initializes this bit to 0 the channel overwrites the O with a logic 1 upon completion of message processing Upon reading a 1 the host resets this bit to O in preparation for the next message 03 Reserved Set to 0 02 A B Buffer A B This bit indicates the last buffer accessed when buffer ping pong is enabled During initialization you designate the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled 01 BRD Broadcast Received 1 Reception of a broadcast Command 00 Reserved Setto 0 Mode Code Transmit Control Word Excalibur Systems Chapter 4 4 2 5 Remote Ter
90. igure 1 2 Direct coupled connection one bus shown If operating in the more standard Transformer coupling mode use stub coupler devices which are available from Excalibur Systems Two terminators are required for each coupler which services a single bus 1 e BUS A see Figure 1 3 For more information see our website www mil 1553 com To other 1553 device mm 1553 Device Transformer Coupled EXC 1553PCI MCH Transformer Coupled s A s B s C Terminator 78 Ohm Terminator 78 Ohm Three Stub Coupler Figure 1 3 Transformer coupled Connection one bus shown EXC 1553PCI MCH User s Manual page 1 5 Chapter 1 Introduction Example of MIL STD 1553 Bus Connection BUS A BUS B Figure 1 4 MIL STD 1553 Bus Connection page 1 6 Excalibur Systems Chapter 1 1 4 1 5 Introduction Note About Pointer Registers When a register s value is a pointer to an address the value is a word address not a byte address However the addresses listed in the memory maps or control register maps in this manual are byte addresses To convert the word address to the byte address multiply the address value by two For example when the value of the Initial Monitor Data Pointer register at address 0x0018 is 0x1000 the data for the first message 1s stored at address 0x2000 and the data for the next message will be stored in the next available memory loca
91. ist Address 6 3 EXC 1553PCI MCH User s Manual page iii Table of Contents 7 Mechanical And Electrical Specifications fal Board Davoll c ca e e os 7 2 7 1 1 EXC 1553PCI MCH Board Layout 7 2 7 1 2 EXC 1553cPCI MCH Board Layout 7 3 T2 LED NICATION S a AI AAA 7 4 7 2 1 EXC 1553PCI MCH LED Indicators 7 4 7 2 2 EXC 1553cPCI MCH LED Indicators 7 4 t DIP SWINE Seere e Od a a e a tac tae baste i 7 4 7 3 1 Selected ID DIP Switch SW1J 7 4 7 3 2 Multiple Board Applications 7 5 TA JUMPE ca ua una S atk Se Ba ERE EXER BA S E 7 6 7 4 44 Channel 0 Channel 3 1553 Coupling Mode Select Jumpers JP2 JP17 7 6 7 4 2 Factory Default Jumper Settings 7 6 LS KG OMMECIONS s trato dear A cda NM RR EE 7 7 7 5 1 Connector Ji Pinouts 7 8 7 5 2 Communication I O Signals Description of Connector J1 7 9 7 5 3 PCI Bus Edge Connector Pinouts 7 11 7 5 4 CPCIBus Connector Pinouts 7 12 7 6 Power Reguirements 7 12 8 Ordering Information Appendix A MIL STD 1553 Word Formats Appendix B MIL STD 1553 Message Formats page iv Excalibur Systems Figure
92. isters Address 0020 003E H The 16 registers are divided into eight blocks two registers per block as shown in Table 4 1 Block Name Address H Receive 0020 and 0022 Transmit 0024 and 0026 Broadcast Receive 0028 and 002A Broadcast Transmit Automatically lllegalized O02C and 002E Mode Code Receive 0030 and 0032 Mode Code Transmit 0034 and 0036 Broadcast Mode Code Receive 0038 and 003A Broadcast Mode Code Transmit 003C and 003E Table 4 1 Illegalization Register Blocks The blocks correspond to the following types of Commands Register address 0020 H and 0022 H illegalize receive Commands to 32 subaddresses The most significant bit of register 0020 H controls the illegalization of subaddress 01111 The least significant bit controls subaddress 00000 Register 0022 H controls EXC 1553PCI MCH User s Manual page 4 11 Chapter 4 Remote Terminal Operation illegalization of subaddresses 10000 through 11111 The least significant bit relates to subaddress 10000 the most significant bit relates to subaddress 11111 Transmit Commands and Broadcast Commands both receive and transmit use the same encoding scheme as receive subaddress illegalization Register 0030 H through 003E H controls the illegalization of mode codes Register 0030 H governs the illegalization of receive mode codes T R bit 0 00000 through 01111 and register 0032 H mode codes 10000 through 11111 Register blocks Transmit Mode Code
93. ity Fail This bit reflects the outcome of the remote terminal address parity check 1 A parity failure When a parity error occurs the channel does not begin operation STEX bit forced to a logic 0 and bus A and B do not enable 12 BITF BIT Fail 1 ABIT failure Interrogate bits 11 through 08 to determine the specific failure 11 BUAF Bus A Fail 1 A BIT test failure in Bus A 10 BUBF Bus B Fail 1 A BIT test failure in Bus B 09 MSBF Memory Test Fail Most significant memory byte failure 08 LSBF Memory Test Fail Least significant memory byte failure 00 07 UDB 7 0 User Defined Bits BIT Word Register Excalibur Systems Chapter 4 Remote Terminal Operation Time Tag Register Address 000E H Read Only The Time Tag register reflects the state of a 16 bit free running counter The resolution of this counter is 64 usec bit The Time Tag counter is automatically reset when the channel receives a valid synchronize without Data mode code The channel automatically loads the Time Tag counter with the data associated with reception of a valid synchronize with Data mode code The Time Tag counter begins operation in one of two cases Either within 64 usec of the rising final edge of a reset Or the receipt of one of the following valid mode codes reset of the remote terminal sync with without data When the channel is halted STEX bit 15 in the Control register 0 the Time Tag continues to run Bit Bit N
94. l Word The descriptor control Word is initialized by the host and updated by the channel during Command postprocessing Note In MIL STD 1553A all mode codes are without data and the T R bit is Bit ignored Bit Name Description 08 15 07 06 05 04 03 02 01 00 INDX INTX IWA IBRD BAC Reserved A B BRD Nil Index Field These bits define multiple message buffer length The host uses this field to instruct the channel to buffer N messages N can range from 0 00 H to 256 FF H If buffer ping ponging is enabled the INDX field is don t care i e does not contain applicable information The channel does not perform message buffering in the ping pong mode of operation The index decrements each time a complete message is transacted no message errors The index does not decrement if the mode code is illegalized The channel can generate an interrupt when the index field transitions from one to zero see bit 07 Interrupt Index Equals 0 1 Enables the generation of an interrupt when the index field transitions from 1 to 0 The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt When Accessed 1 Enables the generation of an interrupt when mode code Command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An inte
95. mand Word1 2nd location Command Word2 Data Pointer Status Word 1 Status Word 2 Branch Address Timer Value 8th location Figure 3 3 BC Command Block Architecture The host must initialize each of the locations associated with each Command Block The exception is for the two status locations that will be updated as Command Words are transmitted and corresponding Status Words are received Command Blocks may be linked together in such a manner as to allow the generation of Major and Minor message frames In addition the BC can detect the assertion of Status Word bits and generate interrupts or branch to a new message frame depending of course on the specific conditions that arise Excalibur Systems Chapter 3 3 3 1 Bus Controller Operation Control Word The first memory location of each BC Mode Command Block contains the Control word Each control word contains the opcode retry number bus definition RT to RT instruction condition codes and the block access message error The control word is defined below 15 12 11 10 09 08 07 01 00 Opcode Retry BUSA B RT RT Conditions Codes Block Access ME Figure 3 4 Control Word Definition Bit Bit Name Description 12 15 Opcode These bits define the opcode to be used by the channel for that particular Command Block If the opcode does not perform any 1553 function all other bits are ignored Each of the available op
96. minal Operation Data Pointer A and B Mode 0 Data List Pointer A and B contains address information for the retrieval and storage of message Data Words In the index mode of operation the channel reads Data Pointer A to determine the location of data for retrieval or storage The channel uses the Data Pointer to initialize an internal counter which increments after each Data Word For a receive Command the channel stores the incoming Data Word sequentially into memory As part of Command post processing the channel writes a new Data pointer into the descriptor block The channel continues to update the Data pointer until the Control Word index field decrements to zero An example is shown in Figure 4 3 RT Non broadcast Receive Message Indexing on page 4 20 The index feature is not applicable for transmit Commands 1 e T R bit 1 Bit Bit Name Description 00 15 DP 15 0 Data Pointer Bits The second and third Words of the descriptor block contain the data buffer location The channel accesses either Data Pointer A or Data Pointer B depending on the state of Control Word Bit 02 during ping pong operation For index operation the channel accesses only Data Pointer A The channel updates Data pointer A after message processing is complete and the index field is not equal to zero and ping pong operation disabled Bit 15 is the most significant bit bit 00 is the least significant bit Data Pointer A and B For ping pong buffer o
97. n 08 15 Hard coded to the value 40 H 04 07 FPGA revision 00 03 Selected ID Board Identification Register page 2 12 Excalibur Systems Chapter 2 PCI Architecture 2 5 2 Software Reset Register Address 2 H Length 16bits The Software Reset register performs reset operations of the channels Individual channels may be reset Bit Description 04 15 Reserved set to 0 03 Channel 3 reset 1 reset channel 0 no effect 02 Channel 2 reset 1 reset channel 0 no effect 01 Channel 1 reset 1 reset channel 0 no effect 00 Channel 0 reset 1 reset channel 0 no effect Software Reset Register 2 5 3 Interrupt Status Register Address 4 H Length 16 bits The Interrupt Status register indicates which channels are currently interrupting Bit Description 04 15 Reserved set to 0 03 1 indicates that channel 3 is interrupting 02 1 indicates that channel 2 is interrupting 01 1 indicates that channel 1 is interrupting 00 1 indicates that channel 0 is interrupting Interrupt Status Register 2 5 4 Interrupt Reset Register Address 6 H Length 16 bits The Interrupt Reset register resets the interrupting channels by writing to the relevant bits of the register Bit Description 04 15 Reserved set to 0 03 1 resets channel 3 interrupt 0 no effect 02 1 resets channel 2 interrupt 0 no effect Interrupt Reset Register EXC 1553PCI MCH User s Manual page 2 13 Chapter 2 2 5 5
98. n After execution begins writing a logic O will halt the channel after completing the current 1553 message 14 SBIT Start BIT 1 Places the channel into the Built In Test routine The BIT test takes 1 msec to execute and has a fault coverage of 93 496 Once the channel has been started the host must halt the channel in order to place it into the Built In Test mode STEX 0 Note f Start BIT SBIT and Start Execution STEX are both set on one register write BIT has priority 11 13 Reserved Setto 0 10 ETCE External Timer Clock Enable 1 Enables an external clock used with an internal counter for variable minor frame timing Note The user can only change the clock frequency before starting the device i e setting bit 15 of register 0 to a login 1 09 ERTO Extended Response Time Out 1 Enables the extended response time out option and forces the BC Mode to look for an RTs response time in 30 usec or generate time out errors 0 Enables for the standard time out in 14 usec 05 08 Reserved Setto0 04 BCEN Broadcast Enable 1 Enables the broadcast option for BC Mode 0 Enables Remote Terminal 31 as a unique remote terminal address When enabled the channel does not expect a Status Word response from the Remote Terminal 03 Reserved Set to0 02 PPEN Ping Pong Enable This bit controls the method by which the channel will retry messages 1 Allows the channel to ping pong between buses during retries 0 All retries will be performed o
99. n Word contains Word count message type and message error information The Time Tag Word is a 16 bit Word containing the Command validity time The Time Tag Word data comes from the channel s internal Time Tag counter Subaddress Receive Data For receive Commands the channel stores Data Words plus two additional Words The channel adds a Receive Information Word and Time Tag Word to each receive Command data packet The channel places the Receive Information Word and Time Tag Word ahead of the Data Words associated with a receive Command see Figures 4 3 4 4 and4 5 above When message errors occur the channel stores the Receive Information Word and Time Tag Word Once a message error condition 1s observed all Data Words are considered invalid Data storage occurs at the memory location pointed to by the Data pointer plus two 16 bit locations Bit Bit Name Description 11 15 WC 4 0 Word Count Bits These five bits contain Word count information extracted from the Command Word bits 15 to 19 10 Reserved Ignore on read 09 BUA B Bus A B 1 The message was received on Bus A 0 The message was received on Bus B 08 RTRT Remote Terminal to Remote Terminal Transfer The Command processed was an RT to RT transfer 07 ME Message Error 1 A message error condition was observed during processing See bits 00 to 04 for details 05 06 Reserved Ignore on read 04 ILL Illegal Command Received 1 The Command received was
100. n the programmed bus as defined in the Retry Number field of the Command Block control word 01 INTEN Interrupt Log List Enable 1 Enables the interrupt log list 0 Prevents the logging of interrupts as they occur 00 Reserved Setto 0 Control Register page 3 4 Excalibur Systems Chapter 3 Bus Controller Operation 3 2 2 Operational Status Register Address 0002 H Read Write The Operational Status Register provides pertinent status information for BC Mode and is not reset to 0000H on reset Instead the bit A B_STD is set to 1 Note To make changes to the BC and this register the STEX bit Bit 15 in the Control Register must be logic 0 Bit Bit Name Description 10 15 Reserved Setto0 09 MSEL1 Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation 08 MSELO Mode Select 0 In conjunction with Mode Select 1 this bit determines the channel s mode of operation MSEL1 MSELO Mode of Operation 0 0 BC 0 1 RT 1 0 BM 1 1 RT Concurrent BM Mode 07 A B STD Military Standard 1553A or 1553B This bit determines if the channel will operate under MIL STD 1553A or 1553B protocol 1 Forces the channel to look for all responses in 9 usec or generate time out errors 0 Automatically allows the channel to operate under the MIL STD 1553B protocol see section 3 6 MIL STD 1553A B Operation BC Mode on page 3 18 04 06 Reserved These read only bits are not applicable 03 EX Chann
101. nnel operation 0 Inhibits channel operation After execution begins writing a logic O will halt the channel after completing the current 1553 message Start BIT 1 Places the channel into the Built In Test routine The BIT test takes 1 msec to execute and has a fault coverage of 93 496 Once the channel has been started the host must halt the channel in order to place it into the Built In Test mode STEX 0 Note If Start BIT SBIT and Start Execution STEX are both set on one register write BIT has priority Set to 0 External Timer Clock Enable 1 Enables an external clock used with an internal counter for variable minor frame timing Note The user can only change the clock frequency before starting the device i e setting bit 15 of register 0 to a login 1 Extended Response Time Out 1 Enables the extended response time out option and forces the BM Mode to look for an RTs response time in 30 usec or generate time out errors 0 Enables for the standard time out in 14 usec Set to 0 Bus Monitor Control This bit determines whether the channel will monitor all RTs or selected RTs 1 The channel will monitor only the RTs as specified in the Monitor Filter Hi and Lo registers 0 The channel will monitor all RTs Broadcast Enable 1 Enables RT 31 to be used as a message broadcast 0 Enables RT 31 as a normal address Set to 0 Interrupt Log List Enable 1 Enables the interrupt log list 0 Prev
102. oadcast 0035 YY YY YY YY YY YY YY YY YY YY YY YY YY YY YY YY Transmit Table 4 2 Illegalization Register Map page 4 12 1 XX Automatically illegalized by the channel YY Automatically illegalized by the channel in 1553B only 3 ZZ Automatically illegalized by the channel in 1553B and 1553A if XMTSW 1s enabled WW Automatically illegalized in 1553A 5 UU Automatically illegalized in 1553A if XMTSW enabled Excalibur Systems Chapter 4 4 2 Remote Terminal Operation Descriptor Block To process messages the channel uses data from the Control Registers with data stored in the RAM The channel accesses a 4 word descriptor block stored in RAM The descriptor block is accessed at the beginning and end of Command processing Multiple descriptor blocks are sequentially entered into memory to form a descriptor table The following paragraphs discuss the descriptor block in detail The host controlling the channel allocates 512 consecutive memory spaces for the subaddress and mode code Descriptor Table see Figure 4 2 page 4 14 The top of the Descriptor Table can reside at any address location The Control registers are linked to the descriptor table via the Descriptor Address Register contents Each descriptor block contains a Control Word Data Pointer A Data Pointer B and Broadcast Data Pointer Each subaddress and mode code is assigned a descriptor for receive and transmit Commands T R bit equals 0 or 1
103. ock is the data pointer that points to the first memory location to store or retrieve the Data Words associated with the message for that command block This data structure allows the channel to store or retrieve the exact specified number of Data Words thus saving memory space and providing efficient space allocation Note In an RT to RT transfer the channel uses the data pointer as the location in memory to store the transmitted data in the transfer One common application for the data pointer occurs when the channel needs to send the same data words to several RTs Here each Command Block associated with those messages would contain the same data pointer value and therefore retrieve and transmit the same data Note that the Data Pointer is never updated i e the channel reads and writes the pointer but never changes its value 1553 Status Words The next two locations in the BC Mode Command Block are for Status Words As the RT responds to the BC s command the corresponding Status Word will be stored in Status Word 1 In an RT to RT transfer the first Status Word will be the status of the Transmitting RT while the second Status Word will be the status of the Receiving RT Branch Address The seventh location in the BC Mode Command Block contains the starting location of the branch This location simply allows the channel to branch to another location in memory when certain opcodes are used Timer Value The last location in th
104. on extracted from the Command Word bits 15 to 19 10 Reserved Ignore on read 09 BUA B Bus A B 1 The message was received on Bus A 0 The message was received on Bus B 08 Reserved Ignore on read 07 ME Message Error 1 A message error condition was observed during processing See bits 00 to 04 for more detail 05 06 Reserved Ignore on read 04 ILL Illegal Command Received 1 The Command received was an illegal Command 03 Reserved Ignore on read 02 OVR Overrun Error 1 The channel received a Data Word with a Transmit Command 00 01 Reserved Ignore on read Transmit Information Word Excalibur Systems Chapter 4 4 3 3 Remote Terminal Operation Mode Code Data The Transmit and Receive Data Structures for mode codes are similar to those for a subaddress The receive Data structure contains an Information Word Time Tag Word and message Data Word All receive mode codes with data have one associated Data Word Data storage occurs at the memory location pointed to by the Data pointer plus two 16 bit locations Reception of the synchronize with Data mode code automatically loads the Time Tag counter and stores the Data Word at the address defined by the Data pointer plus two 16 bit locations The transmit mode code Data structure contains an Information Word Time Tag Word and associated Data Word The host is responsible for linking the channel Data Pointer to the data e g Transmit Vector Word For mode codes with in
105. ong Acknowledge This read only bit acknowledges the Ping Pong operation The Ping Pong Enable is acknowledged by transitioning from a logical zero to a logical one while the Ping Pong Disable is acknowledged by transitioning from a logical one to a logical zero Remote Terminal Mode bits These two bits determine the RT mode of operation RTM 1 0 RT Mode 0 0 Mode 0 Index or Ping pong operation 0 1 X Reserved 1 0 Mode 1 Circular buffer 1 operation 1 1 Mode 2 Circular buffer 2 operation Set to 0 Broadcast Enable 1 Enables the broadcast option for RT Mode 0 Enables remote terminal address 31 as a unique remote terminal address page4 3 Chapter 4 page 4 4 Bit Bit Name Remote Terminal Operation Description 03 02 01 00 DYNBC PPEN INTEN XMTSW Dynamic Bus Control Acceptance This bit controls the channel s ability to accept the dynamic bus Control mode code 1 Allows the channel to respond to a dynamic bus Control mode code with status Word bit 18 set to a logic one 0 Prevents the assertion of status Word bit 18 upon reception of the dynamic mode code Ping Pong Enable 1 Enables the ping pong buffer feature of the channel and disables the message indexing feature 0 Disables the ping pong feature and enables the message indexing feature Interrupt Log Enable 1 Enables the interrupt logging feature 0 Prevents the logging of interrupts Transmit Last St
106. ontains the address for the Message Information Word Time Tag Word and Data Words associated with a broadcast Command The following bits describe the receive subaddress mode code descriptor Broadcast Data Pointer If ping pong operation is disabled the channel automatically increments this Data Pointer during Command post processing Bit Bit Name Description 00 15 BP 15 0 Broadcast Data Pointer The fourth Word of the descriptor block contains the broadcast data buffer location This pointer can reside anywhere in memory space The channel accesses this pointer when Control Word bit 00 is a logic 1 and broadcast is enabled Bit 15 is the most significant bit bit 00 is the least significant bit Note 1 If ping pong is enabled this pointer does not update 2 When the broadcast Command is followed by a Transmit Last Command or Last Status Word mode code the channel transmits a Status Word with bit 15 of the Status Word set to a logic 1 The broadcast bit is cleared when the next valid non Broadcast Command is received Broadcast Data Pointer page 4 22 Excalibur Systems Chapter 4 4 3 4 3 1 Remote Terminal Operation Data Structures The following sections discuss the Data structures that result from Command processing For each complete message processed the EXC 1558PCI MCH generates a Message Information Word and Time Tag Word These Words aid the host in further message processing The Message Informatio
107. osed on open off Bit 4 open off open off Dip Switch settings for unique Selected ID For multiple board applications each board s device number may be set by using the Excalibur configuration utility program provided with the drivers and by setting the unique ID to match that set on the DIP switch shown in Figure 7 3 Select ID 1 2 3 4 EXC 1553PCI MCH EXC 1553cPCI MCH 0 0 0 0 0 OPEN 1 0 0 0 1 1 2 3 4 2 0 0 1 0 ON 3 0 0 1 1 Note Bits 1 and 2 are not used and 159 A EXC 1553PCI MCH User s Manual should be kept closed Figure 7 3 DIP Switch SW1 with all switches set to closed on Select ID 0 page7 5 Chapter 7 7 4 7 4 1 7 4 2 page 7 6 Mechanical And Electrical Specifications Jumpers Jumper Headers are provided on the board The headers are mounted with 2 mm shorting blocks according to the default board setup See section 7 4 2 Factory Default Jumper Settings on page 7 6 In high vibration environments these jumpers can be soldered or wire wrapped The EXC 1553PCI MCH board contains sets of Jumper arrays that control the 1553 interface Direct Transformer Coupled and a Jumper that controls the Shield Signal Channel 0 Channel 3 1553 Coupling Mode Select Jumpers JP2 JP17 Each channel can be either direct coupled or transformer coupled to the 1553 bus Groups of four Jumpers select the coupling mode for each channel Table 7 1 defines the Jumper settings
108. otocol 04 06 Reserved These read only bits are not applicable 03 EX Channel Executing This read only bit indicates whether the channel is presently executing or is idle 1 The channel is executing 0 The channel is idle 02 TAPF Terminal Address Parity Fail Read only This bit indicates the observance of a terminal address parity error The channel checks for odd parity This bit reflects the parity of Operational Status Register bits 10 15 01 READY Channel Ready This read only bit is cleared on reset 1 The channel has completed initialization or BIT and regular operation may begin 00 TERACT Channel Terminal Active This read only bit is cleared on reset 1 The channel is presently processing a 1553 message Operational Status Register Note 1 Remote Terminal Address and Parity are checked on start of execution 2 To make changes to the RT Mode and this register the STEX bit Bit 15 in the Control Register must be logic 0 EXC 1553PCI MCH User s Manual page4 5 Chapter 4 4 1 3 page 4 6 Remote Terminal Operation Current Command Block Register Address 0004 H Read only This 16 bit register contains the last valid 1553 Command processed by the channel Bit Bit Name Description 00 15 CC 15 0 Current Command These bits contain the latest valid 1553 Command that was received by the channel This register is valid 13 psec after the TERACT bit Bit 00 of the Operational Status Register is
109. parity error in the incoming Data Words 00 MAN Manchester Error 1 The channel observed a Manchester error in the incoming Data Words EXC 1553PCI MCH User s Manual page 4 25 Chapter 4 page 4 26 Remote Terminal Operation Mode Code Transmit Information Word Bit BitName Description 11 15 MC 4 0 Mode Code These five bits contain the mode code information extracted from the Command Word bits 15 to 19 10 Reserved Ignore on read 09 BUA B Bus A B 1 The message was received on Bus A 0 The message was received on Bus B 08 Reserved lgnore on read 07 ME Message Error 1 A message error condition was observed during processing See bits 00 to 04 for details 05 06 Reserved lgnore on read 04 ILL Illegal Command Received 1 The Command received was an illegal Command 03 Reserved Ignore on read 02 OVR Overrun Error 1 The channel received a Data Word with a Transmit Command 00 01 Reserved lgnore on read Excalibur Systems Chapter 4 4 4 4 4 1 4 4 1 1 Remote Terminal Operation RT Circular Buffer Modes The RT circular buffer modes simplify the software service of remote terminals implementing bulk or periodic data transfers Select the preferred mode at start up by writing to Control Register bits 07 and 08 see Control Register on page 4 3 The two modes Mode 1 and Mode 2 are discussed in sections 4 4 1 and 4 4 2 Mode 1 Operation In this mode the channel merges transmit or receiv
110. peration the host uses either Data Pointer A or Data Pointer B The channel determines which pointer to access via the state of Control Word bit 02 The channel retrieves or stores Data Words from the address contained in the Data pointer automatically incrementing the Data Pointer as Data Words are received The Data pointer is never updated as part of Command postprocessing in the ping pong mode of operation See Figures 4 4 and 4 5 EXC 1553PCI MCH User s Manual page4 19 Chapter 4 page 4 20 Receive Address Descriptor Block Command 1 Receive three words Command 2 Receive two words Command 3 Receive three words CONTROL WORD DATA POINTER A DATA POINTER B BROADCAST DATA POINTER Message Info Word Time Tag Data Word 1 Data Word 2 Data Word 3 Message Info Word Time Tag Data Word 1 Data Word 2 Message Info Word Time Tag Data Word 1 Data Word 2 Data Word 3 Remote Terminal Operation Index Field Contents O3xx H Data Pointer A 0100 H Data Pointer B Xxxx H Broadcast Data Pointer Xxxx H Index equals three Index decrements two Index equals two Index decrements to one Index equals one 0218 H 021A H Data pointer A updated to 010e H interrupt generated enabled Index decrements to zero Figure 4 3 RT Non broadcast Receive Message Indexing X don t c
111. processing The following bits describe the transmit subaddress descriptor Control Word The descriptor control Word is initialized by the host and updated by the channel during Command post processing Bit Bit Name Description 07 15 Reserved Setto 0 06 IWA Interrupt When Accessed 1 Enables the generation of an interrupt when the subaddress receives a valid Command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing 05 Reserved Setto 0 04 BAC Block Accessed The host initializes this bit to zero the channel overwrites the zero with a logic one upon completion of message processing Upon reading a one the host resets this bit to zero in preparation for the next message 03 Reserved Setto 0 02 A B Buffer A B Indicates the Data pointer to access when buffer ping pong is enabled During initialization the host designates the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled 01 BRD Broadcast Received 1 Reception of a Broadcast Command 00 Reserved Setto 0 Transmit Control Word Excalibur Systems Chapter 4 Remote Terminal Operation 4 2 3 Mode Code Receive Control Word Information contained in the Mode Code Receive Control Word assists the EXC 1558PCI MCH in message processing The following bits describe the receive mode code descriptor Contro
112. r 5 7 5 1 7 BIT Word Regist r 2 soriana REESE E SEDE dE 5 8 5 1 8 Time Tag Register 0 02 ee nne 5 8 5 1 9 Initial Monitor Block Pointer Register 5 9 5 1 10 Initial Monitor Data Pointer Register 5 9 5 1 11 Monitor Block Counter Register 5 9 5 1 12 Monitor Filter Hi Register 5 10 5 1 13 Monitor Filter Lo Register 5 10 5 1 Bus Monitor Architecture 5 11 5 1 1 Message Information Word 5 11 5 1 2 Command Words 5 12 51 3 Data Pointe bss ci Stee teh dase Set oe ree dee x ERR 5 12 5 1 4 Status Word Ka tees 5 13 5 1 5 Time Tags ee ete Ee ete sog ete Ee ded 5 13 SLO Reserved iius coeleste t aee Rus ta teer Ri Ros Pre Eu RAE S 5 13 5 1 Bus Monitor Block Chaining 5 13 5 1 Memory Architecture 5 14 5 1 RT Concurrent Monitor Operation 5 15 5 1 MIL STD 1553A B Operation BM Mode 5 16 6 Channel Interrupt Architecture 6 1 Overview 6 1 6 1 1 Interrupt Identification Word IIW 6 2 6 1 2 Interrupt Address Word IAW 6 2 6 1 3 Interrupt Log L
113. rds for either transmission or storage After transmission or reception the channel begins post processing The command block is updated The channel modifies the Control Word as required An optional interrupt log entry is performed after the command block update Excalibur Systems Chapter 3 Bus Controller Operation 3 2 Control Registers BC Mode The control registers are read write unless otherwise stated All control registers must be accessed in word mode All control register bits are active high and are reset to 0 unless otherwise stated Figure 3 2 below illustrates the control registers for Bus Controller mode Reserved 0012 003E H Command Block Pointer Register 0010 H Minor Frame Timer 000E H BIT Word Register 000C H Interrupt Log List Pointer Register 000A H Pending Interrupt Register 0008 H Interrupt Mask Register 0006 H Current Command Block Register 0004 H Operational Status Register 0002 H Control Register 0000 H Figure 3 2 Control Registers Map BC Mode EXC 1553PCI MCH User s Manual page 3 3 Chapter 3 3 2 1 Control Register Bus Controller Operation Address 0000 H Read Write Use the Control register to configure the channel for BC mode operation To make changes to the BC and this register the STEX bit Bit 15 must be logic 0 Bit Bit Name Description 15 STEX Start Execution 1 Initiates channel operation 0 Inhibits channel operatio
114. rrupt is generated after message processing Interrupt Broadcast Received 1 Enables the generation of an interrupt when a valid broadcast mode code Command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Block Accessed The host initializes this bit to zero the channel overwrites the zero with a logic 1 upon completion of message processing Upon reading a one the host resets this bit to zero in preparation for the next message Set to 0 Buffer A B Indicates the last buffer accessed when buffer ping pong is enabled During initialization you designate the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled Broadcast Received 1 Reception of a valid broadcast Command Notice II 1 Enables the use of the Broadcast Data Pointer as a buffer for broadcast Command information 0 Broadcast information is stored in the same buffer as non broadcast information Mode Code Receive Control Word EXC 1553PCI MCH User s Manual page 4 17 Chapter 4 4 2 4 page 4 18 Remote Terminal Operation Mode Code Transmit Control Word Information contained in the Mode Code Transmit Control Word assists the EXC 1558PCI MCH in message processing The following bits describe the transmit mode code descriptor Control Word You init
115. s Chapter 4 4 5 Mode Code and Subaddress The EXC 1553PCI MCH provides subaddress and mode code decoding that meets MIL STD 1553B requirements In addition the channel has automatic internal illegal Command decoding for reserved MIL STD 1553B mode codes Table 4 4 shows the channel s response to all possible mode code combinations T R Mode Code Function Remote Terminal Operation Operation 0 00000 01111 10000 10001 10010 10011 10100 10101 10110 11111 00000 00001 Undefined w o data Undefined with data Synchronize with data Undefined Undefined Selected Transmitter Shutdown Override Selected Transmitted Shutdown Reserved Dynamic Bus Control Synchronize On wn On On On A Onm On AO Command Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Time Tag counter loaded with Data Word value Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored 2 Dynamic Bus Acceptance bit
116. s Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 2 1 Figure 2 2 Figure 2 3 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Tables Table 2 1 Table 3 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 5 1 Table 6 1 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table of Contents EXC 1553PCI MCH Block Diagram 1 3 Direct coupled connection one bus shown 1 5 Transformer coupled Connection one bus shown 1 5 MIL STD 1553 Bus Connection 1 6 PCI Configuration Space Header 2 2 EXC 1553PCI MCH Channel Memory Map 2 10 EXC 1553PCI MCH Global Registers Map 2 12 Command Block Architecture BC Mode 3 2 Control Registers Map BC Mode 3 3 BC Command Block Architecture 3 10 Control Word Definition 3 11 Message Control Options 3 16 Minor Frame Seguencing 3 16 Memory Architecture for BC Mode
117. s the CA pointer updates at the end of message processing The application software reads the dynamic CA pointer to determine the current bottom of the buffer The TA top of buffer and BA bottom of buffer pointers define the circular buffer s length The CA pointer identifies the current address i e last accessed address plus one The circular buffer wraps to the top address after completing a message that results in CA being greater than or equal to BA If CA increments past BA during intra message processing the channel will access memory read or write address locations past BA Delimit all circular buffer boundaries with at least 34 address locations Note In this mode of operation bits INDX NII and A B of the Descriptor Control Word and the PPEN bit of the Control Register are don t care EXC 1553PCI MCH User s Manual page 4 27 Chapter 4 4 4 1 2 page 4 28 Remote Terminal Operation MODE 1 CIRCULAR BUFFER RECEIVE MESSAGE PROCESSING The channel begins all message processing by reading a unique descriptor block after reception and validation of a subaddress or mode code Command Word The channel internally increments the CA pointer to store the receive Data Word s After message processing completes the channel stores the Message Information Word and Time Tag Word into the circular buffer preceding the message data At the end of message processing the channel updates CA if no errors detected For
118. s for each Command Block is known In Figure 3 7 for example the first Command Block has allocated several memory locations for expected data Conversely the second Command Block has only allocated a few memory locations Since the number of data words associated with each Command Block is known memory may be used efficiently Also shown as a separate memory area is the Interrupt Log List see Interrupt Log List Pointer Register on page 3 8 Notice that the Interrupt Log List Pointer Register points to the top of the initial Log List After execution of that first BC Command Block the Interrupt Log List Pointer Register will automatically be updated if interrupt condition exists Command Data Interrupt Register Block Storage Register Log List Command gt Control Word gt Memory Interrupt gt Int Info Word j Block CMD Words Log List CMD Block Pointer Reg Data Pointer Pointer Reg Status Words Int Info Word Branch Add CMD Block Msg Timer cmm OE Int Info Word ontrol Wor L CMD Words eee Data Pointer gt Status Words li Branch Add Msg Timer HL 4 Control Word CMD Words Data Pointer do Status Words CMD Block Branch Add Msg Timer Figure 3 7 Memory Architecture for BC Mode EXC 1553PCI MCH User s Manual page 3 17 Chapter 3 3 6 page 3 18 Bus Controller Operation MIL STD 1553A B Operation BC Mode To maximize flexibility
119. s to implement the ring buffer architecture Read this register to determine the location and number of interrupts within the Interrupt Log List least significant 5 bits Bit Bit Name Description 00 15 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 05 15 indicate the starting Base address while bits 00 04 indicate the ring location of the Interrupt Log List Interrupt Log List Pointer Register BIT Word Register Address 000C H Read Write The BIT Word register contains information on the current status of the channel hardware The user defines the lower 8 bits of this register Bit Bit Name Description 15 DMAF DMA Fail 1 All the channel s internal DMA activity was not completed within 16 usec 14 WRAPF Wrap Fail The channel automatically compares the transmitted word encoder word to the reflected decoder word by way of the continuous loop back feature If the encoder word and reflected word do not match the WRAPF bit is set The loopback path is via the MIL STD 1553 bus transceiver 13 Reserved Ignore on read 12 BITF BIT Fail 1 A BIT failure Interrogate bits 11 through 08 to determine the specific failure 11 BUAF Bus A Fail 1 A BIT test failure in Bus A 10 BUBF Bus B Fail 1 A BIT test failure in Bus B 09 MSBF Memory Test Fail Most significant memory byte failure 08 LSBF Memory Test Fail Least significant memory byte failure 00 07 UDB 7 0 User Defined Bits BIT Word Register Exc
120. se on the 1553 bus Control Word Description EXC 1553PCI MCH User s Manual page 3 11 Chapter 3 3 3 1 1 page 3 12 OPCODE DEFINTION Opcode Field Name Bus Controller Operation Definition 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 End Of List Skip Go To Built in Test Execute Block Continue Execute Block Branch Execute Block Branch on Condition Retry on Condition Retry on Condition Branch Retry on Condition Branch if all Retries Fail Opcode Definition This opcode instructs the channel that the end of the command block has been encountered Command processing stops and the interrupt is generated if the interrupt is enabled No command processing takes place i e no 1553 This opcode instructs the channel to load the message to message timer with the value stored in timer value location The channel will then wait the specific time before proceeding to the next command block This opcode allows for scheduling a specific time between message execution No command processing takes place i e no 1553 This opcode instructs the channel to go to the command block as specified in the branch address location No command process takes place i e no 1553 This opcode instructs the channel to perform an internal built in test If the channel passes the built in test then processing of the next command block will continue However if
121. shared between the Channel Register Block for the 32 control registers Channel Memory Block for 1553 Message Control Data storage Channel External Timer Clock Register to set the external timer clock value and the Channel Reset Register to carry out the software reset of the channel For each channel a powerful RISC processing unit UTMC SuMMIT XT 1553 protocol controller provides automatic message handling message status general operational status and interrupt information The user has direct access to all control registers and data blocks in Real Time The EXC 1553PCI MCH may be configured to support MIL STD 1553A as well as MIL STD 1553B protocol EXC 1553PCI MCH User s Manual page2 9 Chapter 2 Reserved 70000 7FFFF H Channel Reset Register 6FFFE H e Channel External Time Clock 6FFFC H 0 Register c Channel Memory Block 1553 E o Message Control Data Storage eS es Channel Registers Block 32 60000 6003F H Control Registers Reserved 50000 5FFFF H Channel Reset Register 64FFFE H a 5 Channel ps Time Clock AFFFC H 2 egister c g Channel Memory Block 1553 x o Message Control Data Storage Oo Channel Registers Block 32 40000 4003F H Control Registers Reserved 30000 3FFFF H Channel Reset Register 2FFFE H Channel External Time Clock 2FFFC H E Register c Channel Memory Block 1553 _ o Message Control Data Storag
122. smitted 1 Command Word stored Terminal flag bit enabled for assertion Status Word transmitted M Co Command Word stored Status Word transmitted Software reset On Command Word stored Status Word transmitted pa Command Word stored Service request bit set to a logic zero in out going Status Status Word transmitted Data Word transmitted Clears the SRQ bit in the 1553 Status Word Bits Register mM oak OW Command Word stored Status Word transmitted 3 Data Word stored mM Table 4 4 page 4 34 Mode Code Description Continued Excalibur Systems Chapter 4 4 6 Remote Terminal Operation T R Mode Code Function Operation 1 10010 Transmit Last Command 1 Command Word stored 2 Last Status Word transmitted 3 Last Command Word transmitted 4 Data Word stored Transmit Last Command 5 Transmitted Data Word is all O after reset Note The channel stores the Transmit Last Command mode code if illegalized and updates Status Word 1 10011 Transmit BIT Word Command Word stored Status Word transmitted BIT Word transmitted from BIT Word Register 4 Data Word stored Transmit BIT Word Co m Command Word stored Status Word transmitted Data Word transmitted 1 10100 10101 Undefined with data on 1 10110 11111 Reserved Command Word stored Status Word transmitted 3 Data Word transmitted
123. t BM mode the user determines if the IAW contains information for the RT or the BM The determination 1s made by comparing the contents of the IAW base address with the descriptor base address If a match occurs then the IAW contains a subaddress or mode code identifier If no match occurs the IAW contains monitor counter information page 6 2 Excalibur Systems Chapter 6 6 1 3 Channel Interrupt Architecture Interrupt Log List Address The Interrupt Log List resides in a 32 word ring buffer The host defines the location buffer within the memory space via the Interrupt Log List Register Restrict the ring buffer address to a 32 word boundary During initialization write a value to the Interrupt Log List Pointer Register Initialize the least significant five bits to a logic 0 The most significant 11 bits determine the base address of the buffer The channel increments the ring buffer pointer on the occurrence of the first interrupt storing the IIW and IAW at buffer locations 00 H and 02 H respectively The channel logs ensuing interrupts sequentially into the ring buffer until interrupt number 16 occurs The channel enters interrupt 16 s IIW in buffer location 3C H and the IAW at location 3E H The channel increments the ring buffer pointer as interrupts occur The least significant five bits of the Interrupt Log List Pointer register reflect the ring buffer pointer value Table 6 1 shows the ring buffer architecture Th
124. t locations include A Message Information Word Two Command Word locations A Data Pointer Two Status Word locations A Time Tag location Areserved location The user must initialize the starting locations of the Monitor Block the Data Pointer the Block Counter and the Interrupt Log Pointer From then on the channel will build a Monitor Block for each message it receives over the 1553 bus Figure 5 2 shows a diagram of the Monitor Block followed by a description of each location associated with the Monitor Block Message Info Word Command Word 1 Command Word 2 Data Pointer Status Word 1 Status Word 2 Time Tag Reserved Message Information Word The first memory location of each Monitor Block contains the message informa tion word Each information word contains the opcode retry number bus defini tion RT to RT messages and the message information 15 12 11 10 09 08 07 00 0100 0 0 BUSA B RT RT Message Information Figure 5 2 Message Information Word EXC 1553PCI MCH User s Manual page 5 11 Chapter 5 page 5 12 Bus Monitor Operation Bit Number Description 12 15 Default With the Monitor Block architecture resembling the BC Command Block architecture these bits default to a 0100 state which is the Execute and Continue opcode in case the monitor must switch to the BC mode of operation 10 11 Default With the Monitor
125. t word identifying the interrupt type The format is similar to the Pending Interrupt Register The host reads the IIW to determine which interrupt event occurred The bit description for the IIW is Bit Bit Name Description 12 15 Reserved Set to 0 11 MERR Message Error Interrupt All modes 10 SUBAD Subaddress Accessed Interrupt RT Mode 09 BDRCV Broadcast Command Received Interrupt RT Mode 08 IXEQO Index Equal Zero Interrupt RT Mode 07 ILCMD Illegal Command Interrupt RT Mode 06 Reserved Set to 0 05 EOL End Of List BC Mode 04 ILLCMD Illogical Command BC Mode 03 ILLOP Illogical Opcode BC Mode 02 RTF Retry Fail BC Mode 01 CBA Command Block Accessed BC Mode 00 MBC Monitor Block Count Equal Zero BM Mode Interrupt Identification Word IIW 6 1 2 Interrupt Address Word IAW The Interrupt Address Word is a 16 bit word that identifies the interrupt source Depending on the mode of operation 1 e RT BC or BM the IAW has different meanings In the RT mode operation the IAW identifies the subaddress or mode code descriptor that generated the interrupt For the BC mode of operation the IAW points to the command block addressed when the interrupt occurred In the BM mode of operation the IAW marks the monitor counter count when the interrupt occurred Use the IAW with the Initial Monitor Command Block Pointer Register to determine the monitor command block that generates the interrupt When in RT Concurren
126. ta Words received was greater than expected 01 Parity Error This bit will be set if a parity error has occurred on the Data Words or the RT s status word 00 Manchester Error This bit will be set if a Manchester error has occurred on either the Data Words or the RT s status word Command Words The next two locations in the channel Monitor Block are for Command Words In non RT to RT 1553 messages only the first Command Word will be stored How ever in an RT to RT transfer the first command word is the Receive Command and the second Command Word is the Transmit Command Data Pointer The fourth location in the Monitor Block 1s the Data Pointer This pointer points to the first memory location to store the Data Words associated with the message for this block The data associated with each individual message will be stored contiguously This data structure allows the channel to store the specified number of data words Excalibur Systems Chapter 5 5 1 Bus Monitor Operation Note In an RT to RT transfer the BM uses the Data Pointer as the location in memory to store the transmitting data in the transfer Status Words The next two locations 1n the Monitor Block are for Status Words As the RT responds to the BC s command the corresponding Status Word will be stored in Status Word 1 However in an RT to RT transfer the first status word will be the status of the Transmitting RT while the second Status Word will be the s
127. tatus of the Receiving RT Time Tag The seventh location in the Monitor Block is the Time Tag associated with the message The Time Tag is stored into this location at the end of message process ing i e captured after the command is validated Reserved The last location 1n the Monitor Block 1s reserved Bus Monitor Block Chaining The host determines the first Monitor Block by setting the start address in the Initial Monitor Block Pointer Register Figure 5 3 shows the Monitor Block as the blocks execute in a contiguous fashion Monitor Block 1 Monitor Block 2 L__s Monitor Block 3 gt Monitor Block 4 gt Monitor Block 5 Monitor Block 36 Figure 5 3 Bus Monitor Block Structuring EXC 1553PCI MCH User s Manual page 5 13 Chapter 5 5 1 page 5 14 Memory Architecture Bus Monitor Operation The configuration shows the Monitor Blocks data locations and the Interrupt Log List as separate entities Figure 5 4 shows that the first block of memory is allo cated for the Monitor Blocks Notice that the Initial Monitor Block Pointer Regis ter points to the initial Monitor Block location the Initial Monitor Data Pointer Register points to the initial Data location Interrupt Log List Pointer Register points to the Interrupt Log and the Monitor Block Counter Register contains the Monitor Block count After execution begins the channel will build
128. ternally generated Data Words e g Transmit BIT Word Transmit Last Command the transmitted Data Word is added to the Data structure For MIL STD 1553A mode of operation all mode codes are defined without Data Words For mode codes without data the Data structure contains the Message Information Word and Time Tag Word only Note In MIL STD 1553A all mode codes are without data and the T R bit is ignored Mode Code Receive Information Word Bit Bit Name Description 11 15 MC 4 0 Mode Code These five bits contain the mode code information extracted from the receive Command Word bits 15 to 19 10 Reserved Ignore on read 09 BUA B Bus A B 1 The message was received on Bus A 0 The message was received on Bus B 08 RTRT Remote Terminal to Remote Terminal Transfer 1 The Command processed was an RT to RT transfer 07 ME Message Error 1 A message error condition was observed during processing See bits 00 to 04 for details 05 06 Reserved Ignore on read 04 ILL Illegal Command Received 1 The Command received was an illegal Command 03 TO Time out Error 1 The channel did not receive the proper number of Data Words i e the number of Data Words received was less than the Word count specified in the Command Word 02 OVR Overrun Error 1 The channel received a Word when none was expected or the number of Data Words received was greater than expected 01 PRTY Parity Error 1 The channel observed a
129. the channel fails the built in test then processing stops No command processing takes place i e no 1553 This opcode instructs the channel to execute the current command block and proceed to the next command block This opcode allows for continuous operations This opcode instructs the channel to execute the current command block and unconditionally branch to the location as specified in the branch address location This opcode instructs the channel to execute the current command block and branch only if the condition is met If no conditions are met the opcode appears as an execute and continue This opcode instructs the channel to perform automatic retries as specified in the control word if particular conditions occur If no conditions are met the opcode appears as an execute and continue This opcode instructs the channel to perform automatic retries as specified in the control word if particular conditions occur If the conditions are met the channel retries Once all retries have executed the channel branches to the location as specified in the branch address location If no conditions are met the opcode appears as an execute and branch This opcode instructs the channel to perform automatic retries as specified in the control word if particular conditions occur If the conditions are met and all the retries fail the channel branches to the location as specified in the branch address location If no conditions are
130. the descriptor update the channel modifies the Control Word index field and bits 4 2 and 1 if required The channel updates Data Pointer A if no message errors occurred during the message transaction Reception of a broadcast Command with no message errors results in the update of the Broadcast Data Pointer Neither Data Pointer A or B is updated if the channel has the ping pong mode of operation enabled EXC 1553PCI MCH User s Manual page4 13 Chapter 4 Remote Terminal Operation Single Descriptor Block 6 Broadcast Data Pointer 4 Data Pointer B 2 Data Pointer A 0 Control Word RELATIVE ADDRESS 0000 H RECEIVE SUBADDRESS 0 RELATIVE ADDRESS 0008 H RECEIVE SUBADDRESS 1 RECEIVE SUBADDRESS 30 RELATIVE ADDRESS 00F8 H RECEIVE SUBADDRESS 31 RELATIVE ADDRESS 0100 H TRANSMIT SUBADDRESS 0 TRANSMIT SUBADDRESS 1 TRANSMIT SUBADDRESS 30 RELATIVE ADDRESS 01F8 H TRANSMIT SUBADDRESS 31 RELATIVE ADDRESS 0200 H RECEIVE MODE CODE 0 RECEIVE MODE CODE 1 RECEIVE MODE CODE 30 RELATIVE ADDRESS 02F8 H RECEIVE MODE CODE 31 RELATIVE ADDRESS 0300 H TRANSMIT MODE CODE 0 TRANSMIT MODE CODE 1 TRANSMIT MODE CODE 30 RELATIVE ADDRESS 03F8 H TRANSMIT MODE CODE 31 Figure 4 2 Descriptor Table page 4 14 Excalibur Systems Chapter 4 Remote Terminal Operation 4 2 1 Receive Control Word Information contained in the Receive Control Word
131. tion after the data of the first message Technical Support Excalibur Systems is ready to assist you with any technical questions you may have For technical support see the Technical Support section of our website www mil 1553 com You can also contact us by phone To find the location nearest you see the Contact section of our website EXC 1553PCI MCH User s Manual page 1 7 Chapter 1 Introduction page 1 8 Excalibur Systems Chapter 2 PCI Architecture 2 PCI Architecture Chapter 2 describes the PCI architecture The following topics are covered 24 MemoryStructure unansa 2 1 2 2 PCI Configuration Space Header 2 2 2 3 PCI Configuration Registers 2 3 2 4 ChannelMemorySpace 2 9 2 5 Global RegistersMap 2 12 2 1 Memory Structure The EXC 1558PCI MCH requests two memory blocks The first memory block is 512K bytes in size and contains the memory space for the channels This block 1s described in detail in section 2 4 Channel Memory Space on page 2 9 The second memory block is 64 bytes in size and contains the Global Registers which are explained in more detail in section 2 5 Global Registers Map on page 2 12 EXC 1553PCI MCH User s Manual page2 1 Chapter 2 PCI Architecture 2 2 PCI Configuration Space Header The EXC 1558PCI MCH includes a
132. usec bit The Time Tag counter begins operation on the falling final edge of the reset pulse Bit Bit Name Description 00 15 page 5 8 TT 15 0 Time Tag Counter Bits These bits indicate the state of the 16 bit internal counter Excalibur Systems Chapter 5 5 1 10 5 1 11 Bus Monitor Operation Initial Monitor Block Pointer Register Address 0016 H Read Write The Initial Monitor Block Pointer register contains the starting location of the Monitor Blocks Note Do not change this register while BM mode is active 1 e Operational Sta tus Register bit 03 1 Bit Bit Name Description 00 15 MBA 15 0 Initial Monitor Block Address These bits indicate the starting location of the Monitor Block Initial Monitor Data Pointer Register Address 0018 H Read Write The Initial Monitor Data Pointer register contains the starting location of the Monitor Data Note Do not change this register while BM mode is active i e Operational Sta tus Register bit 03 1 Bit Bit Name Description 00 15 MBA 15 0 Initial Monitor Data Address These bits indicate the starting location of the Monitor Data Monitor Block Counter Register Address 001A H Read Write The Monitor Block Counter register contains the number of Monitor Blocks the user wants to log After execution begins the register automatically decrements as commands are logged When the register is decremented from 1 to 0 an inter

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