AMT-1 & 2 User`s Manual - Atlas Japan
Contents
1. BSR Pin name Input Output Comment 0 RESETP I LVDS input RESETM 1 ENCCONTP I LVDS input ENCCONTM 25 2 HITP 23 0 I LVDS input HITM 23 0 26 BUNCHRSTP I LVDS input BUNCHRSTM 27 EVENTRSTP I LVDS input EVENTRSTM 28 TRIGP I LVDS input TRIGM 29 CLKP CLKM I LVDS input 30 DIOEN O 31 do 0 O see Fig 13 32 di 0 I see Fig 13 53 do 11 O see Fig 13 54 di 11 I see Fig 13 74 55 do 31 12 O see Fig 13 75 GETDATA I 76 START I 77 DSPACE I 78 WR I 79 CS I 84 80 RA 4 0 I 85 CLKOUT O 86 DREADY O 87 ERROR O 88 SERIOUTP O LVDS output SERIOUTM 89 STROBEP O LVDS output STROBEM 34 Table 7 AMT 2 Boundary Scan Registers BSR Pin name Input Output Comment 0 ASDMOD I 1 RESETB I inverted 2 ENCCONTP I LVDS input ENCCONTM 26 3 HITP 23 0 I LVDS input HITM 23 0 27 BUNCHRSTB I inverted 28 CLKOEN I 29 EVENTRSTB I inverted 30 CLKO O 31 TRIGGER I 32 CLKP CLKM I LVDS input 33 DIOEN O 34 do 0 O see Fig 13 35 di 0 I see Fig 13 56 do 11 O see Fig 13 57 di 11 I see Fig 13 69 58 do12_23 11 0 O 70 dio24_27 0 O 71 dio24 27 0 I 76 dio24_27 3 O 77 dio24_27 3 I 81 78 do28_31 3 0 O 82 GETDATA I 83 START I 84 DSPACE I 85 WR I 86 CS I 91 87 RA 0 4 I 92 CLKOUT O 93 DREADY O 94 ERROR O2. Error flag bit in enable_error Description error_flags and error word Coarse count error 0 A parity error in the coarse count has been detected in a channel buffer Channel select error 1 A synchronization error has been detected in the priority logic used to select the channel being written into the L1 buffer more than 1 channel are selected L1 buffer error Parity error detected in L1 buffer Trigger FIFO error Parity error detected on trigger FIFO Matching state error Illegal state detected in trigger matching logic Read out FIFO error Parity error detected in read out FIFO Read out state error Illegal state detected in read out logic Control parity error Parity error detected in control registers COAL A NM AIIN JTAG error Parity error in JTAG instruction 2 10 2 Temporal Errors Temporal errors are embedded in data and available only through an error word Effective error bits are different depend on the setting of enable_match Caution in AMT 1 the hard errors and the temporal errors are located in same bit positions in the error word so it is not possible to distinguish these errors However you can disable the hard error with CSR12 or enable_errmark CSR11 8 bit 22 Table 3 Temporary Errors AMT1 enable_ Error flag bit in Description Comments match error word C
3. A simple example is given to illustrate this A coarse_time_offset of 100 Hex decimal 256 and a bunch_count_offset of 000 Hex gives an effective trigger latency of 100 Hex decimal 256 Normally it is preferable to have a coarse time offset of zero and in this case the trigger count offset must be chosen to 000 Hex 100 Hex modulus 2 FOO Hex C Alignment between trigger time tag and reject count offset The workings of the reject counter is very similar to the trigger time tag counter The difference between the course time counter offset and the reject counter offset is used to detect when an event has become older than a specified reject limit The rejection limit expression is coarse_time_offset reject_count_offset modulus 2 The rejection limit should be set equal to the trigger latency plus a small safety margin In case the extraction of masking hit flags are required the reject limit should be set larger than the trigger latency masking window safety margin For a trigger latency of 100 Hex same as in example in the section above a reject limit of 108 Hex can be considered a good choice no mask detection This transforms into a reject count offset of EF8 Hex when a coarse time offset of zero is used 4 1 Example of Offset Setting In the LHC experiments there are 3564 clock cycles 88 924 usec 24 9501 ns in a beam revolution Thus the count_roll_over csr8 should be set 3563 deb in hex For
4. MO ONL A tap_state ir_wpdate_reg vave do28_31 2 ASDDOWN o wave do28_31 1 ASDCLK vave do28_31 0 Mats D M A B wave Bdio24_27 3 AS D N Fig 16 Simulated timing diagram of the ASD control signal when the TDO register in the ASD is removed 4 Time alignment between hits clock and trigger matching The TDC contains many programmable setups which have effects on the performed time measurements and their trigger matching The main time reference of the TDC is the clock and the bunch reset which defines the TO time The time alignment can basically be divided into three different areas as shown in the figure below A Time relationship between the hits clock and the bunch count reset generating the basic timing measurements of the TDC B Time relationship between the performed time measurements and the trigger time tag C Time relationship between the time measurements and the automatic reject 39 read out FIFO trigger maching Trigger FIFO L1 buffer rasei s e om Hit channel buffers Y reset a a a a a Fig 12 Time alignment between hits trigger and automatic reject A Basic time measurement As previously stated the basic time reference of the TDC measurements is the rising edges of the clock The bunch count reset defines the TO reference time where the coarse time count is loaded with its offset value The TDC also contains internal delay paths of the clock and its channe
5. Controller 16 Ciapa Bona ia dd Hee 24ch Clock Fig 1 Block diagram of the AMT 1 amp 2 2 Circuit Description Fig 1 shows a block diagram of the AMT 1 amp 2 chip There are 24 channels of inputs Table 1 summarizes the main features of the AMT 1 amp 2 chip 2 1 Table 1 AMT 1 amp 2 MAIN FEATURES System Clock Frequency is 40 MHz otherwise noted e Least Time Count e Time Resolution e Dynamic range e Integral Non Linearity e Differential Non Linearity e Difference between channels e Stability e Input Clock Frequency e PLL mode e Internal System Clock e No of Channels e Level 1Buffer e Read out Buffer e Trigger Buffer e Double Hit Resolution e Max recommended Hit rate e Hit Input Level e Supply Voltage e Temperature range e Process e Package 0 78 ns bit rising edge 0 78 100ns bit falling edge RMS 300 ps rising edge RMS 300ps 29ns falling edges 13 4 17 bit 102 4 usec Max 80 ps Max 80 ps Maximum one time bin lt 0 1 LSB 3 0 3 6 V 0 70 C 10 70 MHz x2 mode x1 x2 x4 or x8 Input Clock x PLL mode 2 24 Channels 256 words 64 words 8 words lt 10 ns 500 kHz per channel Low Voltage Differential Signaling LVDS Internal 100 Ohm termination 3 3 0 3V lt 200 mA 0 85 Deg Cent 0 3 um CMOS Sea of Gate Toshiba TC220G die size 6 mm x 6 mm 0 5 mm lead pitch 144 pin plastic QFP Fine Time M
6. t2 E 2 13 O I n Fig 2 a Asymmetric ring oscillator b extracted timing signal 2 2 Coarse Counter The dynamic range of the fine time measurement extracted from the state of the VCO is expanded by storing the state of a clock synchronous counter The hit signal may though arrive asynchronously to the clocking and the coarse counter may be in the middle of changing its value when the hit arrives To circumvent this problem two count values 1 2 a clock cycle out of phase are stored when the hit arrives Fig 3 Based on the fine time measurement from the PLL one of the two count values will be selected such that a correct coarse count value is always obtained The coarse counter has 13 bits and is loaded with a programmable coarse time offset the LSB is always 0 at reset The coarse counter of the TDC will in ATLAS be clocked by the two times higher frequency than the bunch crossing signal thereby the upper 12 bit of the coarse counter becoming a bunch count ID of the measurement The bunch structure of LHC is not 10 compatible with the natural binary roll over of the 12 bit coarse time counter The bunch counter can therefore be reset separately by the bunch count reset signal and the counter can be programmed to roll over to zero at a programmed value The programmed value of this roll over is also used in the trigger matching to match triggers and hits across LHC machine cycles coarse_cou nt_oftset 0 bunc
7. 95 SERIOUTP O LVDS output SERIOUTM 96 STROBEP O LVDS output STROBEM 35 scan out N Boundary Scan Register scan_in enable output buffer dioen gt bsr_in BSR bsr out scan_out scan_in do 0 C gt bsr_in BSR bsr out scan_out scan_in dilo lt bsr_out BSR bsr in scan out scan_in dol1 5 bsr_in BSR bsr out scan_out scan_in dili lt I bsr_out BSR bsr in scan_out Dolo scan_in do 12 55 bsr_in BSR bsr out scan_out ms bio 12 scan_in ts da a dol13 LD bsr_in BSR bsr out scan_out scan_in do 11 gt bsr_in BSR bsr out gt DIO 11 f scan_out sonan m dol31 D bsr_in BSR bsr out gt DIO 31 scan_out scan_in dil111 lt I bsr_out BSR bsr in A f scan out scan_in Fig 13 JTAG boundary scan circuit for the DIO port 3 3 3 ID code register A 32 bit chip identification code can be shifted out when selecting the ID shift chain 0 Start bit 1 11 1 manufacturer code 0001 0011 000 AMT 1 Toshiba Co 11 1 manufacturer code 0000 0011 000 AMT 2 Toshiba Co 27 12 TDC part code 1000 1011 1000 0011 AMT 1 27 12 TDC part code 1000 1011 1000 0101 AMT 2 31 28 Version code 0001 Thus the total ID code in hex formats are 18B83131 AMT 1 and 18B85031 AMT 2 3 3 4 Control registers The JTAG control scan path is used to set CSRO 14 registers that should not be changed while the TDC is actively running See section 3 1 f
8. In case an error condition L1 buffer overflow Trigger FIFO overflow memory parity error etc has been detected during the trigger matching a special word with error flags is generated if enable_errmark and corresponding enable_error bits are set All data belonging to an event is written into the read out FIFO with a header and a trailer if enable_header and enable_trailer bits are set respectively The header contains an event id and a bunch id The event trailer contains the same event id plus a word count An example of setting is shown in 4 1 The trigger matching function may also be completely disabled enable_matching 0 whereby all data from the L1 buffer is passed directly to the read out FIFO In this mode the TDC have an effective FIFO buffering capability of 256 64 320 measurements Since the matching circuit which control the L1 buffer is disabled there is no overflow control to the L1 buffer Thus old data will be overwritten by new data if the overflow occur 2 7 Trigger amp Reset Interface The trigger interface takes care of receiving the trigger signal and generate the required trigger time tag to load into the trigger FIFO In addition it takes care of generating and distributing all signals required to keep the TDC running correctly during data taking The TDC needs to receive a global reset signal that initializes and clears all buffers in the chip before data taking A bunch count reset and event count reset i
9. TDC channel number Coarse Time Coarse time measurement in bins of 25ns Fine Time Fine time measurement from PLL in bins of 25ns 32 T Edge type 1 leading edge O trailing edge E Error An error has been detected in the hit measurement a coarse counter error a channel select error or a rejected hit error 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Coarse Time Fine Time 20 Combined measurement Combined measurement of leading and trailing edge 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0100 TDC ID Channel Width Coarse Time Fine Time Width Width of pulse in programmed time resolution CSR9 width_select If the pulse width excees the width range the width will be FF Coarse Time Coarse time measurement of leading edge relative to trigger in bins of 25ns Fine Time Fine time measurement of leading edge in bins of 25ns 32 Errors Error flags sent if an error condition have been detected AMT 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 TDC ID Error flags Error flags see Tabl
10. The trigger matching function is capable of working across roll over in all its internal time counters For a paired measurement the trigger matching is performed on the leading edge of the input pulse The search for hits matching a trigger is performed within an extended search window to guarantee that all matching hits are found even when the hits have not been written into the L1 buffer in strict temporal order For normal applications it is sufficient to make the search window 8 larger than the match window The search window should be extended for applications with very high hit rates or in case paired measurements of wide pulses are performed a paired measurement is not written into the L1 buffer before both leading and trailing edge have been measured To prevent buffer overflow and to speed up the search time an automatic reject function can reject hits older than a specified limit when no triggers are waiting in the trigger FIFO and enable_auto_reject bit is set A separate reject counter runs with a programmable offset to detect hits to reject The trigger matching can optionally search a time window before the trigger for hits which may have masked hits in the match window if enable_mask bit is set A channel having a hit within the specified mask window will set its mask flag The mask flags for all channels are in the end of the trigger matching process written into the read out FIFO if one or more mask flags 13 have been set
11. are generated separately the error word only contains one kind of error flags 2 10 1 Hard Errors All functional blocks in the TDC are continuously monitored for error conditions Memories are continuously checked with parity on all data All internal state machines have been implemented with a one hot encoding scheme and is checked continuously for any illegal state The JTAG instruction register have a parity check to detect if any of the bits have been corrupted during down load The CSR control registers also have a parity check to detect 1f any of the bits have been corrupted by a Single Event Upset SEU The error status of the individual parts can be accessed via the CSR status registers Table 2 21 Any detected error condition in the TDC sets its corresponding error status bit The error bits are reset by a global reset or when error_reset CSRO 10 bit is set or when error error word is marked The error bits are also reset by bunch count reset or event count reset if enable_errrst_bcrevr is set All the available error flags are OR ed together with individual programmable mask bits to generate an ERROR signal When the ERROR signal becomes active the TDC can respond following ways Ignore No special action will be performed enable_errmark 0 Mark events All events being generated after the error has been detected will be marked with a special error flag enable_errmark 1 Table 2 Hard Errors
12. bit tfifo_nearly_full trigger FIFO nearly full bit trigger_fifo_empty trigger FIFO empty bit 3 2 4 CSR19 11_start_address L1 buffer start address tfiffo_occupancy trigger FIFO occupancy number of word in trigger FIFO coarse_counter Coarse counter bit 0 3 2 5 CSR20 coarse_counter 12 1 Coarse counter bit 12 1 3 2 6 CSR21 rfifo_occupancy 5 0 Read out FIFO occupancy number of word in read out FIFO general_in 3 0 4 bit general purpose inputs Input level of the DIO27 DIO24 can be read through this register if ASDMOD pin is set to high level AMT 2 only general_in 3 is shared with ASDIN signal 3 3 JTAG Port JTAG Joint Test Action Group IEEE 1149 1 standard boundary scan is supported to be capable of performing extensive testing of TDC modules while located in the system Testing the functionality of the chip itself is also supported by the JTAG INTEST and BIST capability In addition special JTAG registers have been included in the data path of the chip to be capable of performing effective testing of registers and embedded memory structures Furthermore it is also possible to access the CSR registers from the JTAG port JTAG TAP Test Access Port state diagram is shown in Fig 12 31 Test Logic Reset 0 Run Test 1 Select 1 Select 1 lde DR Scan IR Scan 4 0 0 1 Capture DR e 1 Capture IR 6 0 0 Shift DR Eso Shift IR amp 2 1 E 1 Exit1 IR 9 OS E E
13. full custom CMOS process based on the 32 channel TDC for the quick test of front end electronics and MDT chambers On the other hand it was decided to use a Toshiba s 0 3 um CMOS process for a final production To develop and test many critical elements in the 0 3 um process a TEG Test Element Group chip AMT TEG 2 was designed fabricated and tested successfully at KEK The AMT TEG was processed in a new 0 3 um process which will be used in final mass production The present AMT 1 design is based on the AMT 0 but many modifications are done since the technology is different and many experience was obtained A time bin size 0 78 ns is obtained using the basic gate delay as the base for the time measurement This scheme prevents the use of very high speed clocks in the circuit and results in a low power device 20 mW channel The gate delay of CMOS devices normally have very large variations as function of process voltage and temperature In this TDC a phase locked loop PLL circuit is implemented to stabilize the gate delay Oscillation frequency of the internal ring oscillator is multiplied by two with the PLL thus generate 80 MHz clock This oscillator has 16 taps and time difference of two taps are exactly 1 16 of the clock period When a hit enters state of these 16 taps are latched and generate a fine time The fine time measurement is extended by a 13 bit coarse counter Although the PLL clock is 80 MHz most of the logic run
14. level DIO pins are used for ASD control when ASDMOD 1 Pin assignment change between AMT 1 and AMT 2 AMT 1 AMT 2 Pin No Name Signal Level Name Signal Level Comments 1 RESETM LVDS In RESETB CMOS In negative logic 2 RESETP LVDS In ASDMOD CMOS In 65 BUNCHRSTM LVDS In BUNCHRSTB CMOS In negative logic 66 BUNCHRSTP LVDS In CLKOEN CMOS In 67 EVENTRSTM LVDS In EVENTRSTB CMOS In negative logic 68 EVENTRSTP LVDS In CLKO CMOS Out 69 TRIGM LVDS In TRIGGER CMOS In 70 TRIGP LVDS In VSS VSS 88 DIO12 CMOS Out DIO12 OUTO CMOS Out ASDMOD 0 1 89 DIO13 CMOS Out DIO13 OUT1 CMOS Out ASDMOD 0 1 91 DIO14 CMOS Out DIO14 0UT2 CMOS Out ASDMOD 0 1 92 DIO15 CMOS Out DIO15 OUT3 CMOS Out ASDMOD 0 1 93 DIO16 CMOS Out DIO16 OUT4 CMOS Out ASDMOD 0 1 94 DIO17 CMOS Out DIO17 OUTS CMOS Out ASDMOD 0 1 95 DIO18 CMOS Out DIO18 OUT6 CMOS Out ASDMOD 0 1 96 DIO19 CMOS Out DIO19 OUT7 CMOS Out ASDMOD 0 1 97 DIO20 CMOS Out DIO20 OUT8 CMOS Out ASDMOD 0 1 99 DIO21 CMOS Out DIO21 OUT9 CMOS Out ASDMOD 0 1 100 DIO22 CMOS Out DIO22 0UT10 CMOS Out ASDMOD 0 1 101 DIO23 CMOS Out DIO23 0UT11 CMOS Out ASDMOD 0 1 102 DIO24 CMOS Out DIO24 INO CMOS Out In ASDMOD 0 1 103 DIO25 CMOS Out DIO25 IN1 CMOS Out In ASDMOD 0 1 104 DIO26 CMOS Out DIO26 IN2 CMOS Out In ASDMOD 0 1 105 DIO27 CMOS Out DIO27 ASDIN IN3 CMOS Out In ASDMOD 0 1 107 DIO28 CMOS Out DIO2
15. the trigger latency of 3 usec 120 clock bunch_count_offset should be set to 3564 120 3444 This is summarized in Table 9 41 Table 9 An example of register value setting Assumptions number of clock cycles per beam revolution CC 3564 cycles trigger latency TL 100 cycles 2 5 usec maximum drift time DT 32 cycles 800 ns register name contents typical value csr0 000 csrl mask_window gt DT 32 020 csr2 search_window gt match_window 8 40 028 csr3 match_window gt DT 32 020 csr4 reject_count_offset lt CC TL 8 mask_window 1 3423 D5F csr5 event_count_offset 0 000 csr6 bunch_count_offset CC TL 3463 D74 csr7 coarse_time_offset 0 000 csr8 count_roll_over 2 CC 1 3563 DEB csr9 strobe 2 c00 csr10 auto_reject match serial header a71 trailer leading csr11 enable E11 csr12 enable_sepa enable_error 1FF csr13 enable_channel 11 0 FFF csr14 enable_channel 23 12 FFF 1 if enable_mask 1 2 At present design count_roll_over must be greater than 800 search_window If the bunch count reset signal is applied in each cycle you can assume larger value for CC such as CC 4096 xxx_window indicates window size so all these parameter is positive value 0x001 means 1 clock tick window and OxFFF means 4095 clock tick window xxx_offset indicates relative time between each coun
16. trigger FIFO runs full the trigger time tags of following events will be lost The trigger interface keeps track of how many triggers have been lost so the event synchronization in the trigger matching and the DAQ system is never lost For each event with a lost trigger time tag the trigger matching will generate an event with correct event id and a special error flag signaling that the whole event has been lost 2 7 6 Separators The TDC is capable of running continuously even when bunch count resets and event count resets are issued Matching of triggers and hits across bunch count resets different machine cycles are handled automatically if the correct roll over value have been programmed Alternatively it is possible to insert special separators in the trigger FIFO and the L1 buffer when a bunch count reset or an event count reset have been issued enable_sepa_bcrst or enable_sepa_evrst These will make sure that hits and triggers from different event count or bunch count periods machine cycles never are mixed In this mode it is not possible to match hits across bunch count periods This separator can be readout if enable_sepa_readout bit is set This mechanism is conceptually shown in Fig 9 17 Data Out Trigger separator read out FIFO maching Trigger FIFO separator Bunch Count Reset or Event Count Reset L1 buffer Hit Time Fig 9 Conceptual view of the separator insertion and matching 2 8 Re
17. 12 A hit measurement have This error is set when the data been corrupted channel with hit_error comes in trigger select error or coarse count matching circuit error 0 Channel buffer 13 Channel buffer becomes This error is set when the data oveflow full with rejected comes 3 CSR Registers amp JTAG access There are two kinds of 12 bits registers CONTROL and STATUS registers The CONTROL registers are readable and writable registers which control the chip functionality The STATUS registers are read only registers which shows chip statuses There are 15 Control registers CSRO 14 and 6 Status registers CSR16 21 These 23 registers are accessible from 12 bit bus DIO 11 0 or through JTAG interface DIO 11 0 RA 4 0 WR CS M TDI U es Xx Bypass reg To ASD Control TAP Controller AMT 2 Only Fig 11 Structure of JTAG CSR registers 24 3 1 Control registers Table 4 Bit assignment of the control registers BIT 1 10 9 8 To E SA E E o CSRO global_r error_ disable_ enable_ test_ test_ enable_ disable_ clkout pl multi eset E reset encode errrst_ mode E invert E direct _ringosc mode E 0 O beer O 0 010 0 9 08 7 6 5 94 0 0 P P E E 3 2 CSRI l mask window 0 23 12 CSR2 search_window 0 35 24 CSR3 match_window 0 47 36 CSR4 reject_count_offset 0 59 48 CSR5 event_coun
18. 8 ASDLOAD CMOS Out ASDMOD 0 1 108 DIO29 CMOS Out DIO29 ASDCLK CMOS Out ASDMOD 0 1 109 DIO30 CMOS Out DIO30 ASDDOWN CMOS Out ASDMOD 0 1 110 DIO31 CMOS Out DIO31 ASDOUT CMOS Out ASDMOD 0 1 112 ERROR CMOS Out ERRORB Open Drain negative logic 120 TCK CMOS In TCK Schmitt Trigger CMOS In 0 4 Known Bug s in AMT 1 This is not a bug but internal clock may shift half cycle 12 5 ns if reset pulse is not issued after power on see section 2 7 0 5 Known Bug s in AMT 2 If enable_rejected 0 rejected hit in channel buffer does not set rejected flag at next hit If you need to know the occurrence of the rejected hit please set enable_reject bit Global reset CSRO 11 should be issued after power on to secure all internal logic to initial State When connecting AMT 2 and ASD chip developed by Harvard Univ both chips have TDO register Therefore it looks there is 1 additional scan register in the scan chain 1 Introduction This manual describes about both AMT 1 and AMT 2 chips Attributes which apply AMT 1 or AMT 2 only is denoted The ATLAS Muon TDC AMT is a Time to Digital Converter TDC designed for the Monitored Drift Tubes MDT of the ATLAS muon detector It is processed in Toshiba 0 3 um CMOS Sea of Gate Technology TC220G Basic requirements on the AMT chip were summarized in ATLAS note MUON NO 179 May 1997 by J Christiansen and Y Arai Then AMT 0 1 was designed in a 0 7 um
19. AMT 1 amp 2 ATLAS Muon TDC version 1 amp 2 User s Manual Yasuo Arai KEK National High Energy Accelerator Research Organization 1 1 Oho Tsukuba Ibaraki 305 Japan yasuo arai kek jp http atlas kek jp tdc Tel 81 298 64 5366 Fax 81 298 64 2580 AMT 1 ES chip produced on Mar 2000 AMT 2 ES chip produced on May 2001 Rev 0 92b May 30 2002 teh hh hh LL TT ee ee a fe i hs fee LL Ae FPS REP PRS ERR ERE E 7 me ko X he te gt x E E La E E se E se E E 4 0 Contents O NOTICE dotacerccues cous DAREA AA dts cued ante AEE duet cunt suevdetsuevdunteaeveates 4 0 1 DOCUMENT CHANGE eriaren hren EEEE tartera dactilar liada add darle ratios 4 0 2 BUGS FIXEDIN AM TL coda ota 4 0 3 CHANGES NAM T Z co Ai 4 0 4 KNOWN BUG S INAM T T ii aaa da 5 0 5 KNOWN BUG SINAM D 2 ocn ts 6 1 gt INTRODUCTION tas 7 2 CIRCUIT DESCRIPTION ooer en E AAEE a ei ii 8 2 1 FINE TIME MEASUREMENT assccsecevaccvateescuyecevadcvscevsdcnetdvadcvatensccyatevadevatevsdenativadcvatenadeyatevadcvandvidcyatevadevatenadeeeidenes 9 2 2 COARSE COUNTE R aona T TE T R E A TA 10 2 3 GHANNEL BUFFER ccoo 11 2 4 ENCODER aio odo oasis 11 2 5 ET BUFFER sic secs TO 12 2 6 TRIGGER MATCHING wc tac odes tisctsca ioan od 13 2 7 TRIGGER amp RESET INTERFACE urraca 14 2 7 1 Encoded trigger and Os Sii sundieecsubstvecsuucivertuberversuacevecsebel s 15 2 7 2 EVENT COUNT TOS Otitis ecscts castes
20. SR10 9 1 L1 buffer overflow 0 L1 buffer becomes full and hit data have been lost 1 Trigger FIFO 1 Trigger fifo becomes full trigger_lost overflow and events have been lost 1 Readout FIFO 2 Readout fifo becomes full enable_rofull_reject amp overflow and hit data have been lost readout_fifo_full amp enable_11full_reject amp nearly_full enable_trfull_reject amp trigger_fifo_nearly_full enable_11full_reject amp enable_trfull_reject 1 Hit error 3 A hit measurement have This error is set when the data been corrupted channel with hit_error comes in trigger select error or coarse count matching circuit error 4 0 not used 0 L1 buffer overflow 5 Enabled by enable_errmark_ovr 0 Channel buffer 6 Channel buffer becomes The data with rejected comes oveflow full AMT2 enable_ Error flag bit in error Description Comments match word CSR10 9 0 L1 buffer overflow 9 L1 buffer becomes full and Enabled by enable_errmark_ovr hit data have been lost 1 L1 buffer overflow 9 L1 buffer becomes full and hit data have been lost 1 Trigger FIFO 10 Trigger fifo becomes full trigger_lost overflow and events have been lost 1 Readout FIFO 11 Readout fifo becomes full enable_rofull_reject amp overflow and hit data have been lost readout_fifo_full amp enable_11full_reject amp nearly_full enable_trfull_reject amp trigger_fifo_nearly_full enable_11full_reject amp enable_trfull_reject 1 Hit error
21. _load see Appendix A for internal format matching_state 10 0 state_waiting state_write_event_header state_write_occupancy state_active state_write_mask_flags state_write_error state_write_event_trailer state_generating_lost_event_header state_generating_lost_event_trailer state_waiting_for_separator state_write_separator 3 3 7 ASD Control AMT 2 only 00000000001 00000000010 00000000100 00000001000 00000010000 00000100000 00001000000 00010000000 00100000000 01000000000 10000000000 To control ASD chip developed by Harvard Univ ASD control signals are implemented in the AMT 2 Simulated timing diagram is shown in Fig 15 and its simulation model is shown in Fig 14 Unfortunately both chip has TDO register so 2TDO registers are connected serially at the end of the scan chain Thus the scan chain looks 1 additional scan register If the TDO register in the ASD is removed the timing diagram will be Fig 16 37 AMT 2 ASDOUT ASDLOAD ASDDOWN E aso Fig 14 AMT 2 ASD control simulation model There are 2 TDO registers at the end of scan chain Therefore there looks 1 additional scan register exist in the chain lt lt AAA UU wave do28_31 3 ASDOUT Mc ST ST wave do28_31 0 y S B VB wave Bdio24 2713 HEN BT IN ve asdchain asdl dac ve asdchain asd0 dac Fig 15 Simulated timing diagram of the ASD control signals 38 EXE 3675 000
22. _n 1_ empty nearly ver_ over write_address full cover flow 001 010 0 23 22 21 20 19 12 CSR18 tfifo_ tfifo tfifo_ running 1 empty nearly full read_address full ag 0 35 34 33 32 31 24 CSR19 coarse_ tfifo_ 11 counter E occupancy start_address O 0 0 0 47 46 44 43 36 CSR20 coarse_counter 12 1 0 59 48 CSR21 general_ 0 O rfifo_ in 3 0 occupancy 5 0 DIO27 24 0 0 0 71 68 67 66 65 60 Q initial value at reset JTAG bit No 3 2 1 CSR16 error_flags 8 0 status of error monitoring see section 2 10 bit NYDN fF WN KF CO oo control_parity parity of control data see section 2 10 rfifo_full 0 rfifo_empty 0 3 2 2 CSR17 11_write_address 7 0 11_ overflow 11 buffer parity error trigger FIFO parity error trigger matching error state error readout FIFO parity error readout state error control parity error JTAG instruction parity error read out FIFO full read out FIFO empty L1 buffer write address L1 buffer overflow bit 30 coarse error parity error in the coarse counter channel select error more than 1 channel are selected 11_over_recover L1 buffer overflow recover bit 11_nearly_full L1 buffer nearly full bit 11_empty L1 buffer empty bit 3 2 3 CSR18 11_read_address 7 0 L1 buffer read address running status of START signal tfifo_full trigger FIFO full
23. a trigger time tag and the time measurements them selves The trigger time tag is taken from the trigger FIFO and the time measurements are taken from the L1 buffer Hits matching the trigger are passed to the read out FIFO Optionally the trigger time tag can be subtracted from the measurements enable_relative 1 such that all time measurements read out are referenced to the time bunch crossing when the event of interest occurred coarse time coarse time reject_count_offset reject 4 a a bunch_count_offset matching_window time search_window mask_window trigger time Fig 5 Trigger latency and trigger window related to hits on channels There are 3 time counters coarse time trigger time and reject time counters A match between the trigger and a hit is detected within a programmable time window Fig 5 if enable_match is set The trigger is defined as the coarse time count bunch count ID when the event of interest occurred All hits from this trigger time until the trigger time plus the matching window will be considered as matching the trigger The trigger matching being based on the coarse time means that the resolution of the trigger matching is one clock cycle 40MHz and that the trigger matching window is also specified in steps of clock cycles The maximum trigger latency which can be accommodated by this scheme equals half the maximum coarse time count 2 2 2048 clock cycles 51 us
24. ad out FIFO and Buffer Full Control The read out FIFO is 64 words deep and its main function is to enable one event to be read out while another is being processed in the trigger matching If the read out FIFO runs full there are several options of how this will be handled Back propagate enable_rofull 0 enable_11full_reject 0 enable_trfull_reject 0 The trigger matching process will be blocked until new space is available in the read out FIFO When this occurs the L1 buffer and the trigger FIFO will be forced to buffer more data If this situation is maintained for extended periods the L1 buffer or the trigger FIFO will finally become full and the measurement is stopped Nearly full reject enable_11full_reject 1 and or enable_trfull_reject 1 In this mode the trigger matching will be blocked if either the L1 buffer is nearly full 256 64 191 words occupied or the trigger FIFO is nearly full contains 4 triggers If this occurs event data will be rejected to prevent the L1 buffer and the trigger FIFO to overflow The event header and event trailer data will never be rejected as this would mean the loss of event synchronization in the DAQ system Any event which have lost data in this way will be marked with an error flag Reject enable_rofull_reject 1 As soon as the read out FIFO full event data not event headers and trailers will be rejected Any loss of data will be signaled with an error flag 2 9 Read out I
25. asurement enable_relative 0 28 27262524 2322212019 161514131211109876543210 pay oo iv o rE data 60 E Hit Error 11_data 31 11_data 30 T Edge Type 11_data 17 Single Measurement enable_relative 1 44 28 27262524 2322212019 1615141312111098765 43210 parity 0 0 1 1 11 data 29 25 coarse_relative 11 0 11_data 4 0 Combined Measurement enable_relative 0 28 27 26 25 24 23 22 21 201918171615 14131211 109876543210 parity 0 1 0 0 11_data 29 17 11_data 10 0 Combined Measurement enable_relative 1 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1098765 43210 parity 0 1 0 0 11_data 29 17 corase_ 11_data 4 0 relative 5 0 Separator 27 26 25 24 23 22 21 20 19 18 1716 15 14 13 12 11109876543210 pa o O ger sra Buffer Occupancy 27262524 23222120 191817161514131211109 8 76543210 aaa foo oa TR oca R Readout FIFO full Trigger FIFO 23 22 21 20 19 18 17 16 15 14 13 12 11109876543210 N EON 6 Appendix B Buffer Overflow Controls May 7 2002 Buffer control mechanism of the AMT is somewhat complicated Although the detailed explanations are available in reference 4 and this manual brief summary is presented here for your understanding All description here assumes the AMT 2 chip and enable_match bit is set Fig 18 shows buffer structure of the AMT chip Overflow control is done for each buffer and described below In real situations all these controls has st
26. ata bits If number of 1 bits in the data is odd the parity bit will be 1 The serialization speed is programmable from 80 to 10 Mbits s A S Uara Serial data stop start bit31 bit30 lt 36 bits word Fig 9 Serial frame format with start bit and parity bit In addition to the serialized data an LVDS pair can carry strobe information in a programmable format as shown in Fig 10 Leading Strobe Direct serializing clock to strobe data on rising edge DS Strobe DS strobe format as specified for transputer serial links DS strobe only changes value when no change of serial data is observed For each format there are two modes one is continuous strobe regardless of data existence another mode generate strobe signal only when data is available 19 Data Packet 44444H4444H444444 stop start Data parity stop DS Strobe strobe_select 0 Serial data DS Strobe 4 strobe_select 1 Leading Strobe strobe_select 2 NANA Leading Strobe strobe_select 3 PA ar fica Fig 10 Different strobe types 2 9 3 Packet format Data read out of the TDC is contained in 32 bits data packets For the parallel read out mode one complete packet word can be read out in each clock cycle In the serial read out mode a packet is sent out bit by bit The first four bits of a packet are used to define the type of data packet The followi
27. cted from the leading and trailing edge measurement taking into account the programmed roll over value The resolution of the width measurement is programmable In case the pulse width is larger than what can be represented with a 8 bit number the width will be forced to a value of FF Hex When several hits are waiting in the channel buffers an arbitration between pending requests is performed New hits are only allowed to enter into the active request queue when all pending requests in the queue have been serviced Arbitration between channels in the active request queue is done with a simple hardwired priority channel 0 highest priority channel 23 lowest priority The fact that new requests only are accepted in the active request queue when the queue is empty enables all channels to get fair access to the L1 buffer 255 L1 Buffer The L1 buffer is 256 hits deep and is written into like a circular buffer Reading from the buffer is random access such that the trigger matching can search for data belonging to the received triggers If the L1 buffer runs full the latest written hit will be marked with a special full flag When the buffer recovers from being full the first arriving hit will be marked with a full recover flag These flags are used by the following trigger matching to identify events which may have lost hits because of the buffer being full 12 2 6 Trigger Matching Trigger matching is performed as a time match between
28. e 2 and Table 3 Errors Error flags sent if an error condition have been detected AMT 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0O 1 1 0 TDC ID Error flags Error flags see Table 2 and Table 3 Debugging data Additional information for system debugging Separator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 TDC ID 0 01010 Bunch ID Bunch ID Trigger time tag counter when separator was generated Buffer Occupancy 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 TDC ID 0 0 0 1 R L1 Occupancy L1 occupancy L1 buffer occupancy R Read out FIFO full 2 10 Error monitoring There are two kinds of error hard errors and temporal errors Hard errors are enabled with enable_error bits CSR12 8 0 and read through error_flags CSR16 8 0 Temporal errors are such as buffer overflow and resumed automatically if data rate decreases These errors are embedded within data stream and available only through error word Since the hard error and temporal error
29. easurement The original idea of the TDC which use internal gate delay as a fine time element and stabilize the element with a feedback circuit was born in 1986 3 The chip was called TMC Time Memory Cell chip Initial TMC chip use a DLL Delay Locked Circuit technique and then PLL Phase Locked Loop technique has been used in recent chips In the PLL version we have been using a new kind of voltage controlled ring oscillator asymmetric ring oscillator Fig 2 To obtain lt 1 ns timing resolution 16 taps are extracted from the oscillator Fig 2 shows a simplified schematics and its timing diagram of the asymmetric ring oscillator Fig 2 only shows 8 stages but the actual chip implements 16 stages The asymmetric ring oscillator was creates equally spaced even number 16 of timing signals The PLL circuit comprises a phase frequency detector PFD a charge pump a loop filter LPF and a voltage controlled oscillator VCO asymmetric ring oscillator in this case An external capacitor Cvg is required in the loop filter The PLL has divide by 2 4 and 8 counter thus the frequency of the VCO can be either the same or the multiplied by 2 4 or 8 of the input frequency The propagation delay of the delay elements that determine the oscillation frequency of the VCO is controlled through a control voltage VGN When a hit occurs the state of the 16 taps and coarse counter are latched into a hit register
30. eet certs AAA ae ere eee eit ie 16 2 7 3 Bunch c nt reseta e e a a ae 16 2 7 4 Global reset Fas aaraa raaa aa AA a A daa au daat aiian Aias 16 2 7 5 TUGI crar r a a E Able E Ta A i ie 16 2 7 6 SODA viii nata ta 17 2 8 READ QUT FIFO AND BUFFER FULL CONTROL cviucicostaaaarirtdas 18 2 9 PIEAD OU TsINTERE ACE atar ooo I E T 18 2 9 1 Parallel read O Uh ii A deo e tacos cela teed baed teats 18 2 9 2 DOM al Ie O DUE A A E 19 2 9 3 Paket fo A a a a Bessa aa a a a dele sass aa betasger cl aaa a aa a ira 20 2 10 ERROR MONITORING ec ced er A O E O E O O 21 2 10 1 Hard EOTS aa TD omen ieee Seas 21 2 10 2 Temporal EMTS ernen eiei ba bah eben tated 22 3 CSR REGISTERS amp JTAG ACCESS s 23 3 1 CONTROL REGISTERS coi A gee a c 25 3 1 1 ES a 25 3 1 2 OSA OO AD OO IO ahi rhe ett 26 3 1 3 COR raae Iin a R io bio ratios 26 3 1 4 SAD PAE E EEA E Sass e EE E A E E pg Susie E E E E suse DeLee 26 3 1 5 OSMA A A eed edb etd ete ested ener 26 3 1 6 OS A A A CETTE CEST TRE 26 3 1 7 COR a PENE laa loans Lara Ao ao E ooo da ia 27 3 1 8 A E ER A NN 27 3 1 9 CSAS ranita abc ciclo acababan ecc E atts 27 3 1 10 CSRI ii A ee esis ee a 27 3 1 11 ESA Oierzs die cess doze chs essa cbac ASAAN RINE ease chat IS on a obad daze dhe NE Dota DINO dao caidas Dada 27 3 1 12 CSA oaran Abloeh eh ee Ailes vhs Aes hile ete thee tie tie eee ees 28 3 1 13 ES Li A An s 29 3 1 14 ESA A des 29 3 1 15 CSRS AMT 2 OMY 00 00 ea 29 3 2 STATUS REGISTERS ci
31. en the external clock and the internal ring oscillator frequency is determined by these bits as shown below 25 pll_multi 1 pll_multi 0 Input frequency Synthesized frequency clkout_mode 1 0 CLKOUT pin mode 0 Start_Sync Synchronized output of the START signal 1 40MHz clk PLL clock 2 output This is the system clock used in most of logics 2 80 MHz clk PLL clock outpuut 3 Coarse Counter Carry Carry outout of the Coarse Counter This can be used to extend the time range disable_ringosc Stop the oscillation of the ring oscillator and disable charge pump circuit of the PLL enable_direct enable direct input pins 0 trigger reset signals are came from encoded input encontp enccontm 1 trigger reset signals are came from direct input pins trigp trigm bunchrstp bunchrstm eventrstp eventrstm test_invert automatic inversion of test pattern in test mode test_mode enable test mode enable_errrst_bcrevr enable error reset when bunch count reset or event count reset is came disable_encode disable fine time encoder and output 111 error_reset clear error bits in CSR16 8 0 global_reset Global reset of the TDC This reset does not clear the contents of the setup registers 3 1 2 CSRI mask window 11 0 mask window in number of clock cycles 3 1 3 CSR2 search_window 11 0 search window in number of clock cycles 3 1 4 CSR3 match_window 11 0 matching window in numbe
32. error words the readout FIFO always stores header and trailer irrespective of enable_header and enable_trailer bits settings The event header and trailer are removed from the readout FIFO at readout time if above bits are not set When the readout FIFO becomes full there are two modes to handle data back propagate mode enable_rofull_reject 0 In this mode trigger matching will be blocked when the readout FIFO becomes full This will resume when a new space is available in the readout FIFO When this occurs the L1 buffer and the trigger FIFO will be forced to store more data and finally the measurement is stopped If this situation lasts longer than count_roll_over 2 period the data integrity can not be guaranteed data reject mode enable_rofull_reject 1 In this mode data in the L1 buffer will be rejected when the readout FIFO becomes full so this prevent to stop the measurement Instead only header error word with Readout FIFO overflow bit 11 flag and trailer are written to the readout FIFO This rejection occurs 47 irrelevant to the data volume in the L1 buffer and Trigger FIFO if enable_11full_reject 0 and enable_trfull_reject 0 If enable_11full_reject 1 the above rejection starts when the L1 buffer becomes nearly full at 191 words 255 64 If enable_trfull_reject 1 the above rejection starts when trigger FIFO becomes nearly full at 4 triggers References 1 AMT 0 manual http micdigi
33. ets Selection between the encoded signals and the direct signals are schematically shown in Table 1 Encoded signal bit pattern Meaning bit 210 Trigger 100 Bunch count reset 110 Global reset 101 Event count reset 111 15 CLKP PLL clock clk80M gt S0MHz Clock CLKM 1 gt reset clk40M C gt 40MHz Clock bla controller reset pa a reset global_reset encoded signal ENCCONTP decoder enable_mreset_code enccont trigger esr11 3 E bunch_count_reset 7 qlobal_reset _ clock reset init TRIP TRIGM BUNCHRSTP F BUNCHRSTM ENCCONTM VV C gt trigger master_reset C gt bunch_count_reset e C gt event_count_reset Fig 7 Simplified diagram of the clock reset and trigger signals V enable_mreset_evrst esr11 1 EVENTRSTP EVENTRSTM enable_direct RESETP esrO 5 VV RESETM 2 7 2 Event count reset An event count reset loads the programmed event_count_offset into the event ID counter In addition a separator can be injected into the L1 buffer and the trigger FIFO if enable_sepa_evrst is set 2 7 3 Bunch count reset The bunch count reset loads the programmed offsets into the coarse time counter the trigger time tag bunch id counter and the reject counter In addition a separator can be injected into the L1 buffer and the trigger FIFO if enable_sepa_bcrst is set From a bunch count reset is given to the TDC u
34. h_count_reset Load count_roll_over O Coarse counter 80MHz Clock cook LIL ont wt NN centz Ko Nt XX ON Coarse Count CNT2 CNT1 CNT2 Hit E PLL select Coarse Count Fig 3 Phase shifted coarse counters loaded at hit 2 3 Channel Buffer Each channel can store 4 TDC measurements before being written into the common L1 buffer The channel buffer is implemented as a FIFO controlled by an asynchronous channel controller The channel controller can be programmed to digitize individual leading and or trailing edges of the hit signal Alternatively the channel controller can produce paired measurements consisting of one leading edge and the corresponding trailing edge In paired measurement the edge data are always handled as pair so you can think the channel buffer is 2 words depth in this case If the channel buffer is full when a new hit arrives it will be ignored rejected However the information of the rejected hit is transferred with next valid hit If the enable_rejected bit in CSR10 is set the information of the rejected hit is transferred as soon as the channel buffer is available The data of the rejected has time when the buffer becomes available and Hit error flags on For the hits stored in the channel buffers to be written into the clock synchronous L1 buffer a synchronization of the status signals from the channel buffers is performed Double synchronizers are used to prevent any metastable state to pr
35. l inputs which influences the actual time measurement obtained These effects can be considered as a time shift in relation to the ideal measurement The time shifts of individual channels may be slightly different but care has been taken to insure that the channel differences are below the bin size 1 ns of the TDC The time shift of the measurements also have some variation from chip to chip and variations with supply voltage and temperature These variations have also been kept below the bin size of the TDC by balancing the delay paths of the clock and the channels In Fig 17 a hit signal is defined such that the time measurement equals zero coarse_time_offset 0 The delay from the rising edge of the clock where the bunch reset signal was asserted to the rising edge of the hit signal is for a typical chip 55ns two clock periods plus 5ns external clock T L L L l bunch_count _reset Hit i OOOO L Fig 17 Definition of reference time measurement B Alignment between coarse time count and trigger time tag To perform an exact trigger matching the basic time measurement must be aligned with the 40 positive trigger signal taking into account the actual latency of the trigger decision The effective trigger latency in number of clock cycles equals the difference between the coarse time offset and the bunch count offset The exact relation ship is latency coarse_time_offset bunch_count_offset modulus 2
36. nable_pair 1 under_flow 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 1211109876543210 reject_out enable_pair reject_first reject_second reject_first hit_error select_error coarse_error 43 Readout FIFO Event Header 27262524 2322212019 18171615 1413 1211 109876543210 parity 1 0 1 0 trigger_data 23 0 event id E bunch id Lost Event Header 27 26 25 24 23 222120 19 18 17 16 15 14 13 12 11109876543210 1 0 1 0 lost_trigger 11 0 lost event id trigger_data 11 0 Event Trailer 27 26 25 24 23 2221 20 19 18 17 16 15 14 13 1211 109876543210 parity 1 1 0 0 Lost Event Trailer 28 27 26 25 24 23 2221 20 19 18 17 16 15 14 13 12 11109876543210 parity 1 10 0 lost_trigger 11 0 lost event id Error AMT 1 28 27 26 25 24 23 22 21 201918171615 1413121110987 6543210 Error AMT 2 28 27 26 25 24 23 a 14 py o11o 0 eno error_data 0 enable_matching amp 11 buffer overflow error_data 1 enable_matching amp trigger_lost error_data 2 enable_matching amp full_rejected enable_rofull_reject amp readout_fifo_full amp enable_11full_reject amp nearly_full enable_trfull_reject amp trigger_fifo_nearly_full enable_11full_reject amp enable_trfull_reject error_data 3 enable_matching amp hit_error error_data 4 enable_matching amp reject_out Mask Flags 27 26 25 24 23 22 212019 18 17 16 15 14 13 12 11 109876543210 0 0 1 0 mask_flags 23 0 Single Me
37. neasta 30 3 2 1 A NN 30 3 2 2 CORT epe ooo iio io oido eee epee tee 30 3 2 3 NN 31 3 2 4 OSTIAS A E E E angel 31 3 2 5 ESA A A ee er Ten 31 3 2 6 OS A A AA ta 31 3 3 JTAG PORT en 31 3 3 1 JTAG controller and INStrUCTIONS 21 csccccecceceececenceceneeeeeeeeaeeseneeteaeeseneeesaseseaeeseaeeseneeeeeasenenereneeteds 32 3 3 2 Boundary SCAM registers miii cies sate idee dee AE E ee diy bee NETEN edie edie 33 3 3 3 ID COAG TODISTO Nc cia tr ss RA EA a AAE tbe ea 36 3 3 4 COMUOL TOUS Ei A A eae een Eo 36 3 3 5 Status TOGISLONS E NN 3 3 6 O A E cian cast sdu desde AA OE R OEA E OSA EA AOSA 3 3 7 ASD Control AMT 2 only ccoo ii 4 TIME ALIGNMENT BETWEEN HITS CLOCK AND TRIGGER MATCHING c ccesesseseeesseeeseeeeeeeeneeees 4 1 EXAMPLE OF OFFSET SETTING 4 2485 Sika hl BAAR AA Raa SAAR Dea RAR RA 5 APPENDIX A INTERNAL DATA FORMAT 0 cccscceeeceeeseeeseeeeeneenneenneenneeeeeenneeneeeneeeneeeneeeneeeneeeneeneeeneesneeeas 6 APPENDIX B BUFFER OVERFLOW CONTROLS MAY 7 2002 cessceseceseeseeeseeeseeeseeeseeeneeeseeeseeeneeees The AMT chip project was started in collaboration with CERN microelectronics group in 1996 Especially Jorgen Christiansen did large contribution to the design of the AMT 0 Notice 0 1 Document Change Packet format p 18 were unintentionally modified and had wrong bit assignments Corrected on Sep 26 2001 0 2 Bugs fixed in AMT 2 Control Parity Error C
38. ng 4 bits are used to identify the ID of the TDC chip programmable generating the data Only 7 out of the possible 16 packet types are defined for TDC data The remaining 9 packet types are available for data packets added by higher levels of the DAQ system TDC header Event header from TDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 18 7 6 5 4 3 2 1 10 1 0 1 0 TDC ID Event ID Bunch ID TDC Programmed ID of TDC Event ID Event ID from event counter Bunch ID Bunch ID of trigger trigger time tag TDC trailer Event trailer from TDC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1100 TDC ID Event ID Word Count Word count Number of words from TDC incl headers and trailers Mask flags Channel flags for channels having hits with in mask window 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11110 9 8 7 6 5 4 3 2 1 0 00 1 0 TDC ID Mask flags Mask flags Channels flagged as having hits with in mask window Single measurement Single edge time measurement 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 001 1 TDC ID Channel T E Channel
39. nterface All accepted data from the TDC can be read out via a parallel or serial read out interface in words of 32 bits The event data from a chip typically consists of a event header if enabled accepted time measurements mask flags if enabled error flags if any error detected for event being read out and finally a event trailer if enabled 2 9 1 Parallel read out Read out of parallel data from the TDC is enabled by setting enable_serial 0 and performed 18 via a clock synchronous bus Several TDC s may share one read out bus and each TDC will be selected with CS chip select and DSPACE data space signals The read out of individual hits are controlled by a DREADY data ready GETDATA get data handshake If the GETDATA signal is constantly held active independent of DREADY it is interpreted as the read out can be performed at the full speed of the TDC The effective read out speed can be slowed down by using the DREADY GETDATA handshake protocol to introduce wait cycles The number of clock periods that the GETDATA signal is asserted is used to determine the word count for the event available in the global trailer 2 9 2 Serial read out The accepted TDC data can be transmitted serially over twisted pairs using LVDS signals by setting enable_serial 1 Data is transmitted in words of 32 bits with a start bit set to one and followed by a parity bit and 2 stop bit The parity is odd parity exclusive OR of the 32 d
40. ntil this is seen in the hit measurements themselves a latency of the order of 2 clock cycles is introduced by internal pipelining of the coarse time counter The definition of time 0 in relation to the bunch count reset is described in more detail in section 4 2 7 4 Global reset The global reset generate master_reset signal if enable_mreset_code is set see Fig 7 The master_reset clears all buffers in the TDC and initializes all internal state machines to their initial state Before data taking an event count reset and a bunch count reset must also have been issued As shown in Fig 7 decoder circuit CSR JTAG contrioller and PLL circuit are not reset by the master_reset 2 7 5 Trigger The basis for the trigger matching is a trigger time tag locating in time where hits belong to 16 an event of interest The first level trigger decision must be given as a constant latency yes no trigger signal The trigger time tag is generated from a counter with a programmable offset When a trigger is signaled the value of the bunch counter trigger time tag is loaded into the trigger FIFO The effective trigger latency using this scheme equals the difference between the coarse_time_offset and the bunch_count_offset bunch_count_offset event_count_offset count_roll_over bunch_count event_count _reset _reset 4OMHz clock Bunch Count Event Count trigger Trigger FIFO AAA A Fig 8 Generation of trigger data If the
41. ontrol Parity Error error_flags 7 bit is prepared to indicate whether SEU Single Event Upset is occured or not in the control registers When you set a value to the control register control parity error may occur in 50 probability This occurs only if the JTAG tck cycle is longer than two clock cycle 50ns In the case when you write the CSR register through CIO lines this error will occur if the CS chip Select signlal width is longer than two clock cycle Serial transmitter Setup time violation 10 ps was found in simulation for some strobe signal circuit Although unstable strobe signal is not observed in actual chips please be careful if you use following mode Table Comment on serial mode in AMT 1 strobe speed comments 0 0 40Mbps OK gated DS 1 20Mbps OK 2 10Mbps OK 3 SOMbps OK 2 stop bits 1 0 OK cont DS 1 OK 2 OK 3 might be unstable strobe 2 0 strobe 1 cycle ahead gated clock 1 strobe 1 2 cycle ahead 2 strobe 1 4 cycle ahead 3 might be unstable strobe 3 0 might be unstable strobe cont clock 1 might be unstable strobe 2 might be unstable strobe 3 OK 0 3 Changes in AMT 2 LVDS receiver Design of LVDS recever is changed to low power version 4 CSR9 4 error_test added Error flags are extended from 9 bits to 14 bits Pin Assignments Input signal level of some signals will be changed from LVDS to CMOS
42. opagate to the rest of the chip running synchronously at 40 MHz When paired measurements of a leading and a trailing edge is performed the two measurements are taken off the channel buffer as one combined measurement 2 4 Encoder When a hit has been detected on a channel the corresponding channel buffer is selected the time measurement done with the ring oscillator is encoded into binary form vernier time the 11 correct coarse count value is selected and the complete time measurement is written into the L1 buffer together with a channel identifier Although the ring oscillator and the coarse counter runs at 80 MHz the base LHC clock is 40 MHz and bunch number is counted at 40 MHz Most of logics in the AMT are designed to run at 40 MHz To shift from 80 MHz to 40MHz regime we would like to define different name to measured time We call the upper 12 bit of the coarse counter as a coarse time and the LSB of the coarse counter plus the vernier time as a fine time Thus the coarse time will be equivalent to the bunch count Coarse Counter 13 bit Ring Oscillator 16 bit Vernier Time 4 bit Coarse Time Fine Time 12 bit 5 bit Fig 4 Definition of coarse time and fine time In case a paired measurement of leading and trailing edge has been performed the complete time measurement of the leading edge plus a 8 bit pulse width is written into the L1 buffer The 8 bit pulse width is extra
43. or register details 3 3 5 Status registers The JTAG status scan path is used to get access to the status of the TDC while it is running 36 or after a run See section 3 1 15 for register details 3 3 6 Core registers The JTAG core register scan path is used to perform extended testing of the TDC chip This scan path gives direct access to the interface between the channel buffers and first level buffer logic It is used in connection with the test_mode bits CSRO 7 and is only intended for verification and production tests of the TDC chip If the test_invert CSRO 6 1 and hit_load 1 in the test mode contents of the hit_data hit_channel and hit_select_error are inverted in every cycle Table 8 Bit assignment of the core registers JTAG bit name R W comments 10 0 matching _state 10 0 R monitoring of trigger matching state 37 11 trigger_data 26 0 R monitoring of active trigger data 38 trigger_ready R monitoring of active trigger 74 39 11_data 35 0 R monitoring of hit data to trigger matching 75 11_empty R monitoring of 11_empty flag 76 11_data_ready R monitoring of 11_data_redy flag 168 77 hit_data 91 0 R W monitoring generation of hit_data 173 169 hit_channel 4 0 R W monitoring generation of hit_channel 174 hit_select_error R W monitoring generation of hit_select_errort 175 hit_load R W monitoring generation of hit
44. r from overflow to normal state The overflow event will have an error word with L1 buffer overflow bit 9 flag if the overflow occur in corresponding matching mask windows C Trigger FIFO overflow Trigger FIFO is 8 words depth If the trigger FIFO runs full the trigger time tags of following events will be lost The trigger interface keeps track of how many triggers have been lost so the event synchronization in the trigger matching and the DAQ system is never lost A full flag in the trigger FIFO together with the event number of the triggers are used to detect the loss of triggers If a positive trigger is signaled when the trigger FIFO is full the trigger interface stores the fact that one or several triggers have been lost As soon as the trigger FIFO is not any more full the event number of the latest lost trigger is written to the FIFO together with a trigger lost flag and bunch id of that time For each event with a lost trigger time tag the trigger matching will generate an event with correct event id and an error word with Trigger FIFO overflow bit 10 flag However the bunch id of the header indicates the time when the overflow was recovered D Trigger Matching and Readout FIFO overflow The trigger matching circuit continuously compares data with reject time counter and if the data is older than the reject time the data will be removed from the L1 buffer The readout FIFO is 64 words deep In addition to data and
45. r of clock cycles 3 1 5 CSR4 reject_count_offset 11 0 rejection counter offset 3 1 6 CSR5 event_count_offset 11 0 event number offset 26 3 1 7 CSR6 bunch_count_offset 11 0 trigger time tag counter offset 3 1 8 CSR7 coarse_time_offset 11 0 coarse time counter offset 3 1 9 CSR8 count_roll_over 11 0 counter roll over value 3 1 10 CSR9 tdc_id 3 0 TDC identifier This ID is attached to the output data error_test set all error flags to test error circuit Don t set this bit in normal operation AMT 2 only width_select 2 0 Set pulse width resolution in pair measurement width select width output resolution max width full_width 7 0 0 78125 ns 200 ns 0 full wih flict 5 full width 103 4 5 6 at 40 MHz clock readout_speed 1 0 readout_speed speed 0 40Mbps 1 20 Mbps 2 10 Mbps 3 80 Mbps strobe_select 1 0 enable_serial strobe_select strobe mode gated DS strobe continuous DS strobe gated leading edge clock continuous leading edge clock 0 AMT 2 only Continuous parallel output milo 0 fry le lof Handshaked parallel output 3 1 11 CSR10 enable_leading enable leading edge measurement 27 enable_trailing enable_pair enable_rejected enable_trailer enable_header enable_serial enable_relative enable_mask enable_match enable_lloccup_readout enable_auto_rejec
46. rong relations Data Out Readout Trigger FIFO yO a maching Trigger FIFO OOOO 1 AA PA PA ee Channel t Buffer Hit Fig 18 Buffer controls A Channel buffer overflow The depth of the channel buffer is 4 If the channel buffer is full when a new hit arrives the new hit will be rejected discarded The occurrence of the rejection is reported by E flag of a data word if enable_rejected bit is set Otherwise user can not detect the occurence of the rejection The information of the rejected hit is transferred as soon as the channel buffer is available Therfore the time of the data with E flag is the time when the buffer is available and not actual data Therefore the data should be discarded after error reporting In combined measurement enable_pair 1 there is no E flag in the data word but the rejected hit can appear in the data if enable_rejected bit is set This may cause some confusion so in this mode enable_rejected bit should not be set B L1 buffer overflow There are 256 words depth in the L1 buffer If enable_llovr_detect bit is not set there is 46 no pointer control so the L1 write pointer may pass the L1 read pointer This bit should be set in normal use If the L1 buffer becomes full 253words L1 buffer overflow bit is set for next data and further data will be discarded When the data size becomes less than 251 words the situation will recove
47. s at 40MHz which is same as that of the LHC clock Each channel can buffer 4 measurements until they can be written into a common 256 words deep level 1 buffer The individual channel buffers works as small derandomizer buffers before the merging of hit measurements into the common L1 buffer A trigger matching function can select events related to a trigger The trigger information consisting of a trigger time tag and an event ID can be stored temporarily in an eight words deep trigger FIFO Measurements matched to the trigger are passed to a 64 words deep read out FIFO or A time window of programmable size is available for the trigger matching to accommodate the time spread of hits related to the same event Optionally channels with hits in a time window before the trigger can be flagged The trigger time tag can optionally be subtracted from the measurements so only time measurements relative to the trigger needs to be read out Accepted data can be read out in a direct parallel format or be serialized at a programmable frequency Control amp Data I O JTAG signals JTAG TAP y y cool Serial Control Registers y Data Status Registers Serial Strobe Built In Self Test Trigger pC Event Count Trigger Time 12b 12b Reject Time Counter EA Trigger Mask Window Start Pointer gt i Status Channel Pulse Width Edge Time gt 6b 5b 8b 17 b Level 1 Buffer T _____ _ e ees Channel Encoder amp Formatter
48. s required to correctly identify the event ID and the bunch ID of accepted events These signals can either be generated separately or be coded on a single serial line at 40 MHz Fig 6 shows PLL reset circuit of the AMT 1 and the AMT 2 In AMT 1 there are 2 divide by 2 flip flops F1 and F2 so the phase between the external clock and the internal clock may shift a half cycle if both flip flops are not cleared at power on Since there is only 1 divide by 2 flip flop in the AMT 2 this phenomenon never happen in the AMT 2 14 a AMT 1 Control Voltage Ext 40 MHz CLK gt phase i Frequency Detector Ring Oscillator reset Y Int 40MHz CLK RESETP gt RESETM gt o b AMT 2 Ext 40 MHz CLK Phase i Frequency Detector Ring Oscillator bce Int 40MHz CLK RESET D Q A D QH F3 F2 c Cc Qe Qe Ext 40MHz CLK Fig 6 PLL reset circuit of the AMT 1 and the AMT 2 Encoded trigger and resets Four basic signals are encoded using three clock periods Table 1 The simple coding scheme is restricted to only distribute one command in each period of three clock periods A command is signaled with a start bit followed by two bits determining the command When using encoded trigger and resets an additional latency of three clock periods is introduced by the decoding compared to the use of the direct individual trigger and res
49. s when L1 buffer overflows effective only in enable_matching 0 enable error mark event if rejected hit seen effective only in enable_matching 0 double the internal clock frequency Test Only in AMT 2 enable error mark word if hard error exists enable event data rejection if trigger FIFO nearly full see section 2 8 enable event data rejection if L1 buffer nearly full 28 see section 2 8 enable_rofull_reject enable event data rejection when read out FIFO full see section 2 8 3 1 13 CSR12 enable_error 8 0 ERROR signal is asserted if corresponding enable_error bit is set enable_sepa_evrst enable generate separator on event reset enable_sepa_bcrst enable generate separator on bunch count reset enable_sepa_readout enable read out of internal separators debugging 3 1 14 CSR13 14 enable_channel 23 0 enable individual channel inputs 3 1 15 CSR15 AMT 2 only general_out 11 0 12 bit general purpose outputs The value written to this register is available from the DIO23 DIO12 pins if ASDMOD pin is set to high level JTAG access to this register is independent from CSRO 14 JTAG path 29 3 2 Status registers Table 5 Bit assignment of the status registers all these registers are read only 11 10 9 8 7 6 5 4 3 2 1 0 CSR16 rfifo_ e E error _ empty full arity E flags OO O 0 11 10 9 8 0 CSR17 HW ul n
50. t 3 1 12 CSR11 enable _setcount_bcrst enable _mreset_evrst enable_resetcb_sepa enable_mreset_code enable_llovr_detect enable _errmark_ovr enable_errmark_rejected inclk_boost enable_errmark enable_trfull_reject enable_11full_reject enable trailing edge measurement enable pair leading and trailing edge measurement If this bit 1s set enable_leading and enable_trailing bits are masked enable force generation of rejected hit If the channel buffer is full when a new hit arrives it will be ignored rejected If this bit is set the information of the rejected hit is transferred as soon as the channel buffer is available even there is no hit see section 2 3 enable trailer in read out data enable header in read out data enable serial read out otherwise parallel read out enable read out of relative time to trigger time tag enable search and read out of mask flags enable trigger matching enable read out of 11 occupancy for each event use for debugging enable of automatic rejection of hits from the L1 buffer see section 2 6 enable all time counters to be reset on bunch count reset enable master reset on event reset enable channel buffer reset when a separator is inserted enable master reset from global reset of the encoded_control enable L1 buffer overflow detection If this bit is not set write pointer of the L1 bufer will pass read_pointer if the L1 buffer become full enable error marking event
51. t_offset 0 71 60 CSR6 bunch_count_offset 0 83 72 CSR7 coarse_time_offset 0 95 84 CSR8 count_roll_over FFF 107 96 CSR9 strobe_select readout_speed width_select error_ tde_id 1 0 0 0 test 0 0 119 118 117 116 115 113 112 111 10 i i 8 CSR10 enable_ enable_ enable_ enable_ enable_ enable_ enable_ enable_ enable_ enable_ enable_ enable auto_ lloccup match mask relative serial header trailer rejected pair trailing leading reject _readou D tO WM O O O O 0 O O CD 131 130 129 128 127 126 125 124 123 122 121 120 CSR11 enable_ enable_ enable_ enable_ inclk_b enable_ enable_ enable_ enable_ enable_ enable_ enable rofull_ lifull_ trfull_ errmark oost ermark_ errmark llovr mreset_ resetcb_ mreset_ setcount reject reject reject rejected _ovr _detect code sepa evrst _bcrst oO O oOo O O 0 O O O 143 142 141 140 139 138 137 136 135 134 133 132 CSR12 enable_ enable_ enable_ enable_ sepa_ sepa_ sepa_ error 8 0 readout E berst E evrst E O O FF 155 154 153 152 144 CSR13 enable_channel 11 0 FFF 167 156 CSR14 enable_channel 23 12 FFF 179 168 CSR15 general_out 11 0 0 O initial value at reset JTAG bit No Bold AMT2 only 3 1 1 CSRO pll_multi 1 0 The frequency ration betwe
52. tal web cern ch micdigital amt htm 2 AMT chips web page http atlas kek jp tdc 3 Y Arai and T Ohsugi An Idea of Deadtimeless Readout System by Using Time Memory Cell Proceedings of the Summer Study on the Physics of the Superconductiong Supercollider Snowmass 1986 p 455 457 4 Y Arai and J Christiansen Requirements and Specifications of the TDC for the ATLAS Precision Muon Tracker ATLAS Internal note MUON NO 179 14 May 1997 Also available from http atlas kek jp tdc Documents TDCspec pdf 48
53. ters These offset is loaded into respective counters when bunch count reset is asserted All counters are roll over at value count_roll_over Thus larger value than count_roll_over has no meaning for the window size and the offsets 42 5 Appendix A Internal Data Format Channel Buffer na nm 42 41 40 424140 323130 30 282726 181716 181716 EEUE 1413 3210 Ss rs se vernier parity parity A 88 87 888786 747576 747576 74 747372 606162 72 60 61 62 616059 444546 60 59 44 45 46 EA coarse2 ER coarsel vernier parity parity if enable_pair 0 edge 0 trailing edge edge leading edge if enable_pair 1 edge 0 trailing edge found edge 1 trailing edge not found rejected data is rejected since the channel buffer is full Level 1 Buffer buffer_ overflow see below separator_ overflow stored overflow level 1 buffer overflow start buffer_size gt 253 buffer_overflow set to 1 when overflow occured and kept 1 until overflow recover I buffer_size lt 251 make_separator_stored separator flag data 31 0 0 parity parity of data 34 0 enable_pair 0 29 28 27 26 25 24 23 22 21 20 19 18 16 15 1413 1211109876543210 eS INT enable_pair 1 normal data 29 28 27 26 25 24 232221201918 17 161514131211109876543210 enable_pair 1 over_flow 29 28 27 26 25 24 232221201918 17 161514131211109876543210 e
54. xiti DR l 1 Pause DR Exit2 DR Exit2 IR 0 8 Update DR Update IR 5 d ty 0 ly l Fig 12 JTAG TAP controller state diagram Numbers in each states shown are state variable of the TAP controller 3 3 1 JTAG controller and instructions The JTAG instruction register is 4 bits long plus a parity bit 3 0 ins 3 0 JTAG instruction 4 parity 0 parity of JTAG instruction 32 Table 6 JTAG Instructions Parity Instruction Name Description 0 0000 EXTEST Boundary scan for test of inter chip connections on module 1 0001 IDCODE Scan out of chip identification code 1 0010 SAMPLE Sample of all chip pins via boundary scan registers 0 0011 INTEST Using boundary scan registers to test chip itself 0100 0111 not used 1 1000 CONTROL Read Write of control data 0 1001 ASD control AMT 2 only 0 1010 STATUS Read out of status register information 1 1011 CORETEST Read Write internal registers for debugging 0 1100 BIST Built In Self Test for Memories 1 1101 General purpose output port AMT 2 only 0 1110 not used 0 1111 BYPASS Select BYPASS register 3 3 2 Boundary scan registers All signal pins of the TDC are passed through JTAG boundary scan registers All JTAG test modes related to the boundary scan registers are supported EXTEST INTEST SAMPLE 33 Table 7 AMT 1 Boundary Scan Registers
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