THDB-HDMI
Contents
1. LL Ax Rod RES the ig 1 8 L7 a a 47 31 23 REX xw za 28 Ax EET a EET gt x EN Rx 5 RE NT n 2 4 38 e 85 0 N ax Ts 42 RO E d I RE ROT 2 Hs i5 E Es EDiD WM E 58 E ex r ans eo 5 an PE dex a Ax OD a RE Ld i al L a7 e Fa TeS 2 ee POXIDA ee BE Rx EVEHODD 5 2 Oe Se mas S 4 DD SEA Ax vu mel qe 55 Fee 1 HE S xn Hi lu eae Tx 508 le 85 GER e TX abe a TX st r S 2 Tx RDS aig 199 TX RD s rx Rs IL ANN TT 113 z TX ROS 118 TX Sr 31 8 117 130 XR 188 1 87 env TDC2TDI x T TX Le ET TX 2n A Wt ai Eo ij Gir gH EX U LI 148 TX Gi E IX B TE Bi Tx CEDE zy TX 2797 Bi IET i CE RT TX DE Aj2. Figure 4 5 Configuration of System Library Audio Test users would like to test audio during HDMI transmitting only mode please remove the constant definition TX VPG COLOR CTRL DISABLED from main c Users will hear a tone sound from the built in speaker of HDMI monitor when pressing BUTTON of DES board 29 CHAPTER 5 Appendix 5 1 Revision History Revision Date Change Log DEC 02 2008 Initial Version APR 06 2009 Support Receiver Revision A2 JAN 04 2010 Figure 2 1 Corrected 5 2 Always Visit THDB HDMI Webpage for Update We will be continuing providing interesting examples and labs on our THDB HDMI web page Please visit www altera com or hdmi terasic com for more information 30
3. bak HOM COMMON h mcu h typedef ic E i berasic_lib h debug h E I2C h terasic includes h ic debug c c I2C c application stf readme txt E 81 155 HDMI TX RX svslib SOPC Figure 4 3 NIOS Program File List System Configuration To use the HDMI library in NIOS II the const should be defined in the configuration settings as shown in Figure 4 4 Two on chip memories are created to store the NIOS program and data separately The size of each on chip memory is 128 K bytes One on chip memory is used to store program and the other one is used to store data The option Small C Library must be enabled to reduce the size of the program The associated configuration is shown in Figure 4 5 28 Properties Tor DES HDMI TX KX type fiter text C C Build Info Associated System Librar Builders Project Type Build C C Documentation iv C C File Types C C Include Paths ant i Tool Settings Build Settings Build Steps Error Parsers Binary Parser Environment Macros CiC Make Project Yd a C C Project Paths 8 8 ju II Compiler Defined Symbols xj gm jy Project References 33 Preprocessor IS BUG Refactoring History 23 General 3 Linker 49 General Active configuration Configuration Set
4. me Figure 2 5 HSTC Connector of HDMI board The table below lists the HSMC signal direction and description Note The power pins are not shown in the table 12 Signal Name Pin Direction Description 12513 3 input 25 serial data output doubles as DSD Serial Right CH2 data output RX SCK 4 input 25 serial clock output doubles as DSD me RX WS 5 input 25 word select output doubles as DSD Serial Right CHO data output mu _ 9 Digital Video Output Pis Digital Video Output Pins RX HPD 1 22 output Enable Hardware Plug Detection for Digital Video Output Pins RX_CEC 1 24 inout CEC Consumer Electronics Control for 1251 27 input 25 serial data output doubles as DSD Serial Right CH1 data output 12512 29 input 25 serial data output doubles as DSD serial Left CH2 data output RX SCDT 30 input Indication for active HDMI signal at input mo eem RX SPDIF 33 input S PDIF audio output doubles as DSD Serial Left CH2 data output RX INT N Interrupt output Default active low I2S 0 25 serial data output doubles as DSD 13 Serial Left CHO data output RD 11 input Digital Video Output Pins 39 RX MUTE input Mute output doubles as DSD Serial mm Right CH3 data output non Digtal Video Output Prs Digital Video Output Prs _ RDI 6 Digi
5. www terasic com THDB HDMI Terasic HDMI Video Daughter Board User Manual 2 ge Se oo 1 ERES i bdo ls F I C359 60 Preliminary Version 2008 by Terasic MINT ROD 1 1 1 PAB OUT 1 1 2 ASSEMBLEE THE HOMI BOARD 2 1 3 UP oee 2 BOSH 3 2 1 acs nee E o 3 2 2 2 5 2 3 BLOCK DIAGRAM HDMI SIGNAL TRANSMISSION siscsseseacdcssocedsusaceecbasacvediadacvacbcesonadecgeseaddesancedeanednedaasbevadaasadeadeoseonndaeieres 7 2 4 BLOCK DIAGRAM OF HDMI SIGNAL RECEIVING cccccceecccccccccccccccccccccccuceccuseccccusececesscecuucececuuccecueuccecaucececauceceuscees 8 2 5 GENERATE di EI SERERE 10 2 6 PIN DEFINITION OF CONNECTOR cscccccseeccccsecccccscccccucccceecccccucecccaceccu
6. The THDB HDMI package as shown in Figure 1 1 contains e THDB HDMI board x 1 e System CD ROM x 1 The CD contains technical documents of the HDMI receiver and transmitter and one reference design for HDMI transmitting and receiving with source code EM E zF T is i Nl c E jM uw a Figure 1 1 THDB HDMI Package 1 2 Assemble the HDMI Board This section describes how to connect the HDMI daughter board to a main board and use DE3 as an example The HDMI board connects to main boards through the HSTC interface For DE3 the HDMI daughter board can be connected to any one of four HSTC connectors DES Figure 1 2 shows a HDMI daughter board connected to the HSTC connector of DE3 Due to high speed data rate in between users are strongly recommended to screw the two boards together Note Do not attempt to connect remove the HDMI daughter board to from the main board when the power is on or the hardware could be damaged Figure 1 2 Connect HDMI daughter board to board 1 3 Getting Help Here are some places to get help if you encounter any problem Email to support terasic com Taiwan amp China 886 3 550 8800 Korea 82 2 512 7661 English Support Line 1 408 512 12336 5 Ss S CHAPTER 2 HDMI Board This chapter will illustrate technical details of HDMI board Users ma
7. 6 20 24 bit YCbCr 4 2 2 v 8 10 12 bit YCbCr 4 2 2 ITU BT 656 v 12 15 18 bit double data rate interface data bus width halved clocked with both rising and falling edges for RGB YCbOr 4 4 4 v 24 30 36 0 double data rate interface full bus width pixel clock rate halved clocked with both rising and falling edges v channel swap v swap 5 Bi direction Color Space Conversion CSC between RGB and YCbCr color space with programmable coefficients Up down sampling between YCbCr 4 4 4 and YCbCr 4 2 2 Dither for conversion from 12 bit 10 bit to component to 10 bit 8 bit Support Gammat Metadata packet Digital audio output interface supporting v to four 125 interface supporting 8 channel audio with sample rates of 32 192 kHz and sample sizes of 16 24 bits v interface supporting PCM Dolby Digital DTS digital audio at up to 192kHz frame rate Optional support for 8 channel DSD audio up to 8 channels at 88 2kHz sample rate v lt for high bit rate HBR audio such as DTS HD and Dolby TrueHD through the four 125 interface or the S PDIF interface with frame rates as high as 768kHz v Automatic audio error detection for programmable soft mute preventing annoying harsh output sound due to audio error or hot unplug 10 Auto calibrated input termination impedance provides process voltage and temperature invariant matching to the input transmission lines 11 Integra
8. M MUX 4 3 NIOS Program This section describes the design flow and how Nios ll processor controls transmitter and receiver Figure 4 2 shows the software stack of the NIOS program The 2 block implements the 2 read write functions based on GPIO system call The HDMI transmitter block and receiver block are referred as the HDMI driver The HDMI transmitter chip and receiver chip are managed and controlled through the 2 protocol The 125 driver block is in charge of sending audio data to the transmitter Application HDMI HDMI Transmitter Receiver 25 Driver NIOS GPIO Driver Figure 4 2 Software Stack Figure 4 3 shows the file list of the NIOS program The control center is located in main c The beep c includes audio raw data for generating a tone sound The folder named terasic_lib includes the 2 driver The folder named HDMI Lib includes transmitter and receiver drivers The platform dependent functions are located in mcu c under HDMI Lib 27 m altera components l HDMI TX RX lt gt Binaries E3 Includes it Debug B E HOMI Lib 5 2 HDMI GH cat z3 h E 0 HDMI RX h uc 23 Gl 16 HDMI RX c HDMI TX GH cat amp 613 drv h E lh cat amp 613 svs h dss sha h Hh edid h E Tx h hdmiEx uc 613 drv c 6 cab6613 svs c ic dss sha c fic EDID c uc Tx c EDID c bak k cat6 13
9. RASIC DOD004 TERASIC DOD004 TERASIC oo004 TERASIC DO007 808 HPDChange TERASIC DO007 00010 TERASIC DDO010 00010 00010 00010 00010 TERASIC DOD10 00010 00010 TERASIC DDO010 00010 00010 00010 00010 00010 00010 00010 TERASIC o0011 TERASIC OO007 Figure 3 5 NIOS program trace log of transmitting only demonstration 756 25 register button callback success 750 EX hardware Reset 111 RX hardware Reset 541 Chip Revision Lih 543 RE HW Reset 546 hardware Reset 694 RZ Active Port 509 HPD On 577 Support Color 575 Support Color 501 HDMI 563 HDMI 565 HDMI 5588 HDMI 590 592 HDMI 595 HDMI 597 HDMI 539 HDMI 601 604 HDMI oink Sink ink Sink Sink ink Sink Sink ink Sink VIC Video VIC Video VIC Video VIC Video VIC Video VIC Video VIC Video VIC Video VIC Video VIC Video Display found 505 HDMITX Setoutput 653 gt Pattern Generator Mode z Set Tx Color Depth 704 Set Tx Color Convert RGB4i4242 RGcB4434 441 Confidg vIInfoFrame 20 OUV444 YUVAzZ2 Identity Identity Identity Identity Identity Identity Iden
10. RASIC OD0Z9 531 V Display 1080 TERASTC 00029 650 FPorch 4 29 8811 syne 44 TERASTIC O0029 707 BPorch 5 TERASIC O000z9 713 V SycnToDE 41 TERASIC 000259 776 VIC 16 1920x1060pe60 TERASIC O0029 770 Ratio 16 9 TERASIC O0029 779 709 No 1900089 7961 Color Space EGB444 TERS TC DDESSH 75S TERS 00049 703 Video 00029 990 HDNITSA Setoutput TERASIC UDUS0 717 ConfigAVIInfoFrame VIC 16 TERASIC O0035 109 Ex Color Convert RGR444 gt RG8444 TERASIC O00355 156 5et Tx Color Depth 24 bits TERASIC O0035 155 Tx Color Convert RGB444 gt RG8444 TERASIC UDUS3 8856 Config VIInfoFrame VIC 16 Figure 3 6 NIOS program trace log of loopback demonstration 22 CHAPTER Case Study This chapter describes the design concepts for the HDMI demonstration in the previous chapter 4 1 Overview This section describes the overview of the reference design This reference design shows how to use DE3 to control HDMI board Please refer to the pervious chapter for the demonstration of this reference design The source code of the reference design can be found in the THDB HDMI CD under the directory of Examples folder The demonstration includes the following two major functions e Transmission only Generate HDMI Video Audio signal for transmission including various video
11. Temp Sensor Group D Enable Connector Group Enable Connector Type Type Standard Standard Name GPIO 0 Name GPIO 1 Group Enable Connector Group Enable Connector Type HSTC Standard 3 3 LVTTL Standard Name HDMI 7 HDMI Mame GROUP Um 2 Yoltage Level Indicator 1 Add HDMI Board 10 Board Name Ppa ane HDMI 1 Connect and HDMI Board by drag and drop the mouse System Configuration Connection Board Configuration Board Description DE3 Board 3 35 EST TL HSTC Male J5 HSTC C TOP Female 3 3 EST TL HSTC Female Jb BOT TOM 1 DMI 3 32 EV T TL HSTC Female 1 11 1 Click Generate to generate the desired top level and pin assignments for a HDMI project 2 6 Pin Definition of HSTC Connector This section describes pin definition of the HSTC interface onboard All the control and data signals of HDMI transmitter and receiver are connected to the HSTC connector so users can fully control the HDMI daughter board through the HSTC interface Power is derived from 3 3V and 5V pins of the HSTC connector Figure 2 4 shows the physical pin location and signal name on the HSTC connector 11 Ax Ed ri Rx Sok 5 IE E LA m ER Opi Rx RD2
12. ce is removed HPD flag is off B Perform proper actions according to various interrupt events 2 4 Block Diagram of HDMI Signal Receiving This section describes the block diagram of HDMI signal receiving Figure 2 4 shows the block diagram of HDMI signal receiving Please refer to the schematic included in the CD for more details The HDMI receiver is controlled through the 2 interface where the host works as master and the transmitter works as a slave Because the pin PCADR is pulled low the transmitter 12C device address is set to 0x90 Through the 2 interface the host board can access the internal registers of receiver to control its behavior The receiver can support two receiving ports but only one port can be activated at the same time RST N RX INT N EEPROM 12C RX1_SCL RX1_SDA RX2 Figure 2 4 The block diagram of HDMI signal receiving The host can use the reset pin RX_RST_N to reset the receiver and listen to the interrupt pin RX_INT_N to detect change of the receiver status When interrupt happens the host needs to read the internal register to find out which event is triggered and perform proper actions for the interrupt Here are the steps to control the receiver 1 Reset the receiver from the RX_RST_N pin 2 Read the EEPROM EDID to check whether the EEPROM contents need be updated When writing data to EEPROM remember to pull low t
13. d 2 Video synchronization process Please search the global variable Is A2 in cat6023 c for detail information The NIOS program controls the receiver to perform the following procedures step by step o Initialize the HDMI receiver chip o Detect if a HDMI source device is attached or detached o Select one of the receiving ports and activate it o Read and parse the EDID content to find the capability of the HDMI source device The capability includes supported color space video format VIC code and color depth etc o Perform HDCP authentication o Reportthe input video VIC and audio format of the attached HDMI source device o Configure the color space of input and output The receiver can provide color space transformation Video Pattern Generator The video pattern generator is designed to generate test pattern for HDMI transmitting only mode The supported video formats are listed in Table 4 2 Video Format VIC PCLK MHZ 720x480p60 1024x76pP60 1280x720p50 1280x720p60 1280x1024 1920x1080i60 1920x1080i50 1920x1080p60 1920x1080p50 26 1600x1200p5 1920 10801120 Table 4 2 Built in video formats It also supports three color spaces which RGB444 YUV422 YUV444 The required PCLK is generated from Megafunction ALTPLL and ALTPLL RECONFIG IP The required PLL reconfigure data is stored in on chip ROMs Video Source Selector The source selector is implemented using Megafunction LP
14. formats and color space There are 11 video formats available The color space includes RGB444 YUV422 and YUV444 e Loopback Loopback internal bypass the HDMI Video Audio Signals The audio and video output pins of the receiver are directly connected to the input audio and video pins of the transmitter 4 2 System Function Block 23 This section will describe the system behavior in function blocks Figure 4 1 shows the system function block diagram of this demonstration In the design SOPC is included because NIOS II processor is used to control both transmitter and receiver through 2 interface The NIOS program is designed to run on the on chip memory A customized 125 controller is designed to generate 125 48K stereo audio for the HDMI transmitting only mode The audio data is stored in the on chip memory and sent to the HDMI transmitter by II processor The video pattern generator is designed to generate test patterns for HDMI transmitter only mode It provides eleven video formats in three color spaces The source selector circuit is designed to select the desired video source between the video pattern generator and the video from the receiver Four LEDs and two BUTTONSs on are used for human interface BUTTONSs are designed to change the test pattern and associated color space for transmission LEDs are designed to indicate the HDMI status which is illustrated in Table 4 1 BUTTONS are designed to change the
15. he EEPROM write protection pin EDID_WP Finally make sure EDID_WP 15 pulled high and configure the both 2 pins as input pins so the attached HSTC source device can read the EDID successfully Initialize the receiver through the 2 interface Pull Low the RX1_HPD_N and RX2_PHD_N pins to enable HPD pins of receiving ports Set receiver port 1 as active port Ss Polling the interrupt pin RX_INT_N Switch to another receiver port every three seconds and activate it if no HDMI source device found on the current active port B f a HDMI source device is detected Perform HDCP authentication Read the input video format including color space and color depth lii Configure input and output color space B X Perform proper actions according to various interrupt events 2 5 Generate Pin Assignments This section describes how to automatically generate a top level project including HDMI pin assignments Users can easily create the HDMI board pin assignments by utilizing the DES System Builder V 1 3 1 or later Here are the procedures to generate a top level project for THDB HDMI 1 Launch DE3 System Builder 1 Add a board Enable the HSTC C connector and type desired pin pre fix name in the dialog of DES Configuration DE3 Configuration General Enable Led Enable Dip Switch Board Name DE3 Enable Seg Enable Usb Enable Button Enable 5dcard FPGA Type EP3SL15 F1152C2ES
16. ignal transmission Please refer to the schematic included in the CD for more details The HDMI transmitter is controlled through I2C interface where the host works as master and the transmitter works as a slave Because the PCADR 15 pulled low the transmitter 2 device address is set to 0x98 Through the 2 interface the host board can access the internal registers of transmitter to control its behavior TMDS p DDC 12C p HDMI Transmitter HPD av Regulator 5V Figure 2 3 The block diagram of the HDMI signal transmission The host can use reset pin TX_RST_N to reset the transmitter and listen to the interrupt pin TX_INT_N to detect change of the transmitter status When interrupt happens the host needs to read the internal register to find out which event is triggered and perform proper actions for the interrupt Here are the steps 1 2 3 to control the transmitter 1 Reset the transmitter from the TX_RST_N pin Initialize the transmitter through the 2 interface Polling the interrupt pin INT N continuously B f a HDMI sink device is detected flag is on l Read and parse EDID to determine the capacity of the attached HDMI sink device 7 Configure desired output video audio including color space color depth lil Perform HDCP authentication IV Output video audio signals to the Video Audio bus B Stop video output if a video sink devi
17. ins X 18 output Digital video input pins SD SC X X RX HPDIO output Enable Hardware Plug Detection for HDMP Port 0 Low Active TX output TX RD 9 Digital video input pins TX RD 5 Digital video input pins TX Digital video input pins 25 serial clock for on board EEPROM 11 Digital video input pins TX_GD 6 Digital video input pins TX RD 10 Digital video input pins TX GDJT Digital video input pins TX GD 4 Digital video input pins TX PCSCL Clock for DDC TX_PCSDA Data for DDC TX RST N Hardware reset pin Active LOW TX Digital video input pins TX INT N Interrupt output Default active low TX 605 Digital video input pins 15 TX Digital video input pins TX 080 DSD Serial Left data input Digital video input pins TX 080 050 Serial Right data input Digital video input pins TX DSD LI 2 DSD Serial Left CH2 data input TX Digital video input pins TX DSD DSD Serial Right CH2 data input TX Digital video input pins TX 080 050 Serial Left CH1 data input TX 8009 Digital video input pins TX 080 R 1 DSD Serial Right CH1 data input Input data clock TX DSD LIO DSD Serial Left CHO data input TX 8 Digital video input pins TX DSD R 0 Digital video input pins TX BDI7 Digital video input pins TX DCLK DSD Serial audio clock input TX BD 6 Digital vide
18. o input pins TX SCK 25 serial clock input TX 5 Digital video input pins TX WS 25 word select input TX Digital video input pins TX_BD 3 Digital video input pins TX 12510 25 serial data input TX Digital video input pins TX 1251 I2S serial data input Digital video input pins TX MCLK Audio master clock input TX 125121 I2S serial data input TX BD O Digital video input pins TX 12548 25 serial data TX VS Vertical sync signal TX HS Horizontal sync signal TX SPDIF S PDIF audio input TX CEC CEC Consumer Electronics Control Figure 2 6 The HSTC pin definition of the THDB HDMI board 16 CHAPTER 3 Demonstration This chapter illustrates the video audio demonstration for the HDMI board 3 1 Introduction This section describes the functionality of the demonstration briefly This demonstration shows how to use DES to control the HDMI board The demonstration includes two parts Transmission Only Generate HDMI Video Audio signal for transmission including various video formats and color space There are 11 video formats available The color space includes RGB444 YUV422 and YUV444 e Loopback Loopback Internal bypass the HDMI Video Audio Signals The audio and video output pins of the receiver are directly connected to the input audio and video pins of the transmitter 3 2 System Requirements The following items are required for transmission only and loo
19. pback demonstrations Transmission Only e THDB HDMI x 1 e DE3 Board x 1 e CD monitor with at least one HDMI input x 1 e HDMI Cable x 1 Loopback HDB HDMI x 1 DES Board x 1 e CD monitor with at least one HDMI input x 1 17 e HDMI Source Device x 1 e HDMI Cable x 2 3 3 Setup the Demonstration Figure 3 1 and 3 2 show how to setup hardware for transmission and loop back demonstrations respectively Transmission Only Figure 3 1 HDMI Transmission Only Demonstration Setup Loopback Video in Figure 3 2 HDMI Loopback Demonstration Setup 18 3 4 Operation This section describes the procedures of running the demonstration FPGA Configuration Please follow the steps below to configure the FPGA Make sure hardware setup is completed Connect PC and with a USB cable Power DES Make sure Quartus II is installed on your PC Execute the batch file hdmi_demo bat under the folder examples DE3_xxx_TX_RX demo batch HDMI Transmission Only After FPGA is configured please follow the steps below to run the HDMI transmission only demonstration Connect the HDMI LCD monitor and the HDMI transmitting port with a HDMI cable Power on the LCD monitor and make sure the LCD monitor is set to the mode where HDMI input is the source Please refer to the user manual of your HDMI Display for more details When LCD monitor is detected the LED2 of DES will be turned on After approximatel
20. rates as high as 768kHz v Support for 8 channel DSD audio through dedicated inputs 3 10 11 12 13 14 15 16 17 v Compatible with IEC 60958 and IEC 61937 v Audio down sampling of 2X and 4X Software programmable auto calibrated TMDS source terminations provide for optimal source signal quality Software programmable HDMI output current level MCLK input is optional for audio operation Users could opt to implement audio input interface with or without MCLK Integrated pre programmed HDCP keys Purely hardware HDCP engine increasing the robustness and security of HDCP operation Monitor detection through Hot Plug Detection and Receiver Termination Detection Embedded full function pattern generator Intelligent programmable power management Table 2 1 lists supported input video format Input Pixel Clock Frequency MHz es Color Video Bus Hsync zz 28577 7425 425 room a fart et ae Lx p mw Table 2 1 Input video formats supported by the HDMI board Separate 5 108 pe 5 p HDMI Receiver Features 2 4 Dual Port HDMI 1 3 receiver Compliant with HDMI 1 HDCP 1 2 and DVI 1 0 specifications Supporting link speeds of up to 2 25 Gbps link clock rate of 225MHZ Various video input interface supporting digital video standards such as v 24 30 36 bit RGB YCbCr 4 4 4 v 1
21. rator 1 Table 4 2 Button Operation Definition Transmitter Controlled by NIOS Il Processor The transmitter is controlled by NIOS program through 2 interface Based on 2 protocol the NIOS program can read write the internal registers of the transmitter and control the behavior of the transmitter The NIOS program controls the transmitter to perform the following procedures step by step o Initialize the HDMI chip o Detect if a HDMI sink device is attached or detached e g LCD Display Read and parse the EDID content to find the capability of the HDMI sink device The capability includes supported color space video format VIC code and color depth etc o Perform HDCP authentication o Configure the color space of input and output The transmitter offers color space transformation and outputs RGB444 YUVA22 or YUV444 25 o Configure the color depth of output video o Send VIC to the video sink device o Configure the audio interface and format of output video Receiver Controlled by NIOS Il Processor The receiver is controlled by NIOS program through 2 interface Based on 2 protocol the NIOS program can read write the internal registers of the receiver and control the behavior of the receiver The revision number of receiver is either A1 or A2 which can be determined by querying the register 4 of receiver The major differences between both revisions are 1 Receiver initialization process an
22. scceccuseeceuseseceusescceuuceceuaesecuececceucecensesss 11 DEMONSTRATION 17 3 1 INTRODUCTION O 17 3 2 Ye UIE IIE INTs RR 17 3 3 SETUP THE DEMONSTRATION RR e 18 3 4 OPERATION aeae E E EE E O 19 STUDY oere E EA E A E 23 4 1 anui has eG ara sates 23 4 2 SYSTEM FUNCTION PPSP EPSP 23 4 3 PRO RAN He 27 Pai ed Pica B b M 30 5 1 PEV ONR TOR Y a E 30 5 2 ALWAYS VISIT THDB HDMI WEBPAGE FOR 0 400 0 00000000000000 30 CHAPTER 1 Introduction THDB HDMI is a HDMI transmitter receiver daughter board with HSTC High Speed Terasic Connector interface Host boards supporting HSTC compliant connectors can control the HDMI daughter board through the HSTC interface This THDB HDMI kit contains complete reference designs with source code written in Verilog and C for HDMI signal transmitting and receiving Based on reference designs users can easily and quickly develop their applications 1 1 About the KIT This section describes the package content
23. tal Video Output Pins Lu RX_BDI9 igital Vi input Digital Video Output Pins input Digital Video Output Pins input Digital Video Output Pins Digital Video Output Pins Digital Video Output Pins DE RX BD 0 RX PCSDA inout Serial Programming Data for chip programming 75 81 RX_HS Horizontal sync signal BDI4 83 Digital Video Output Pins RX_PCSCL 84 inout Serial Programming Clock for chip programming SDA 1 DDC 12 Data for HDMI Port 1 EVENODD Indicates whether the current field is 14 Digital Video Output Pins nput nput nput nput nput nput nput nput input nput Input Input Input Input Even or Odd for interlaced format DDC I2C Clock for HDMI Port 1 RX_VS Vertical sync signal RX_DDC_SDA O RX_DDC_SCL 1 89 BB DDC 2 Data for HDMI Port 0 RX_BD 5 Digital Video Output Pins RX SCL 0 DDG 2 Clock for HDMI Port 0 6 96 input Digital Video Output Pins 100 Digital Video Output Pins TX GD 8 Digital video input pins CEC O 102 inout CEC Consumer Electronics Control for HDMI Port 0 TX 0 9 105 Digital video input pins TX Digital video input pins TX_GD 11 Digital video input pins TX_RD 3 Digital video input pins TX Digital video input pins TX Digital video input pins TX RD 2 Digital video input pins TX RD 8 Digital video input p
24. ted pre programmed HDCP keys 12 Intelligent programmable power management Table 2 2 lists the supported output video formats Color Video Bus Hsync 480 720p 10800 SXGA 1080p UXGA space Format Width Vsync iss 2r os pmo mo we pes Separate 195 z 6 mo 2 a creme eR 485 162 S fass 27 e 7425 7425 we wes 1215 18 Separate 135 27 65 7425 749 enop Separate 135 27 7425 7425 1495 Embedded 135 27 7425 74 25 1485 amor Separate 27 54 1485 858 Embedded 27 54 1485 1485 Table 2 2 Output video formats supported by the HDMI board 2 2 Layout and Componets The photo of the HDMI board is shown in Figure 2 1 and Figure 2 2 It indicates the location of the connectors and key components RX 2 RX 2 EEPROM HSTC Connector RX 1 EEPROM Figure 2 2 On the back of the HDMI board with HSTC connector and HDMI ports The THDB HDMI board includes the following key components e Receiver U3 e Receiver port 1 2 J2 J3 e Transmitter U6 e Transmitter port J4 27MHZ OSC Y1 expansion connector J1 Receiver 2 EEPORM 04 05 e RX Regulator REG1 Regulator REG2 e Level shifter U2 2 3 Block Diagram of HDMI Signal Transmission This section describes the block diagram of HDMI signal transmission Figure 2 3 shows the block diagram of HDMI s
25. tings Undefined Symbols Restore Defaults Figure 4 4 Define MCU constant Properties for DES HDMI TX RX syslib System Library Target Hardware Builders CiC Build SOPC Builder System D NIOS_IT DAUGHTER_BOARD HDMI DES_341 CiC Documentation C C File Types C C Include Paths ant system Library Contents Linker Script C C Indexer 2 Tos Make Project RTOS none single threaded iv Custom linker script C C Project Paths RTOS Options none Project References TH Refactoring History stdout jtag_uart j Use auto generated linker script System Library CPU 7 j stderr jtag_uart Program memory text onchip mem stdin jtag_uart Read only data memory rodata mem data System clock timer timer 3 Read write data memory rwdata onchip mem data Timestamp timer Heap memory onchip_mem_data Max file descriptors 32 Stack memory onchip_mem_data never exits Clean exit Flush buffers v Support device drivers Exception stack memory C Lightweight device driver API Small C library C Link with profiling library only no hardware support Maximum exception stack size bytes Unimplemented instruction handler Run time stack checking Software Components Use separate exception stack
26. tity Identity Identity Identity 24 bits WIC Code 3 Code lt 18 Code lt 4 Codei 19 Codej 5 Code 20 Codeji 16 Codey 31 Code 9 Code 1 D 720 480 60 VIC 3j HDMI Internal Loopback After FPGA is configured please follow the steps below to run the HDMI loopback demonstration Connect the HDMI LCD and the HDMI TX port with a HDMI Cable Power on the LCD monitor and make sure the LCD monitor is set to the mode where HDMI input is the source Connect the HDMI source device and HDMI RX port with a HDMI Cable Power on the HDMI source device and make sure its HDMI port is selected as the output Users will be able to see the video displayed on the LCD monitor and hear the sound if there is a speaker built in Users can change the RX port connected to the HDMI source device The demonstration can automatically detect the RX port and activate it Figure 3 6 shows the NIOS program trace log when a HDMI LCD source device is detected It indicates the input video resolution is 1280 x 720 VIC 4 with color space RGB444 36 bits color depth Both input color and output color of the receiver and transmitter are configured as RGB444 In another words the color format doesn t change from the source to the LCD monitor during the loopback process The output color depth of the transmitter is configured as 24 bits 21 TER amp sSIC O00016 656 HW Reset TERASIC O00016 656 R2 hard
27. video format and color space of the build in video pattern generator which is illustrated in Table 4 2 HDMI IN IN Y Y RX Port t FPGA EER ee ETE Peg Sa ee eee eee ae ee PE ee SOPC Video J4 Patern PICO Selection EFH Video Pattern Petit Aaa Generator ITITITITTPTEITTEITIITIITIITTIIITITIITITIET 125 Audio TX PI tud db d Rc RARE RBS Rcx eR Video Video Source Selector Source Selecnon MIGS Program On chip memory hfs EE i SSS SSS Ses eee a me ie LLILL LL LL Mom epar rn LLLLLLLIJIILILLLPJLLLLIIIIILLLLLLLLIIIILIIILILLLLLLZSLIIIILLLLLQELIILIIIPILLELIIIIILE LLLI ILIILILLLLLLLIIIILLLILILILLL 1 HDMI OUT Figure 4 1 System Function Block Diagram 24 HDMI sink device is detected and synchronized HDMI source device is detected and synchronized Table 4 1 LED Indications Press to change active video format of the built in video pattern generator BUTTONO Press to change active video color space of the built in video pattern gene
28. ware Reset TERASIC 00016 815 Revision of Receiver 2 TERASIC O0016 907 InitcaTsdes i uccurrentHbMIPort 1 TERASIC O0019 862 Active Port TERASTIC O0022 950 RE HW Reset 00022 955 hardware Reset TERASIC O0023 109 Revision of Receiver 42h TERASIC n023 200 Initc T560231 OC uccurrentHDMIPort 0 TERASIC O0026 175 RE Active Port TERASTC O0027 256 CDR RESET reglO 01 TERASTC O0027 521 VState 1 VSTATE SyncWait TERASTIC O0027 970 RAINT VideoMode Chg gt VSTATE SyncWait TERASTIC O0028 059 RA VState 3 VSTATE SyncChecking TERASTC O0026 554 RA VState 5 VSTATE ModeDetecting TERASIC O0026 506 REINT VideoMode Chg gt VSTATE 2ynclWait 00028 558 RX VState 3 syncChecking TERASTC O00028 620 RE VState 5 VSTATE ModeDetecting TERASIC n0238 98437 7 7 Video On TERAS IC 00029 455 E VState 7 VSTATE Videoon TERASTC O00029 490 RS AState 4 ASTATE Audioon 22 523 Input Display Res 1920 x 1080 36bps TERASIC O00029 539 Input Audio Rate 4a 000 Valid Channel Mask Olh TERASTIC O0029 551 0 Total 2200 TERASTIC O0029 555 0H Display 1920 TERASIC O0029 563 H FPorch TERASIC O0029 573 syne 44 TERASTC 00029 614 0 BPorch 146 TERASTIC O0029 629 Total 1125 TE
29. y 10 seconds a test pattern will be displayed on the LCD monitor The first displayed pattern is 480p 720x480p60 pattern Press BUTTONO to change test patterns Please refer to Table 5 1 for built in test patterns There are eleven built in test patterns available in this demonstration You will not be able to see all the test patterns if your LCD monitor doesn t support such resolution Press BUTTON to change the color space of pattern source The color space includes RGB444 YUV422 and YUVAAA Figure 3 3 and 3 4 show the test pattern of FULL HD 1920x1080p60 in RGB and YUV color space respectively It will take approximately 10 seconds to display a new pattern on the LCD when users change test pattern or color space Figure 3 3 FULL HD in RGB444 Color Space Figure 3 4 FULL HD in YUV Color Space Figure 3 5 shows the NIOS program trace log when a HDMI LCD monitor is detected It indicates the LCD monitor in use supports color space YUV444 and YUV422 but not RGB444 Various video formats supported are listed according to Video Identify Code VIC The format of input and output color of the transmitter is RGB444 and RGB444 respectively It implies there is no change of color format in between 00000 001 HDMI Demo 00000 0021 TX hardware Reset Chip Revision ID 1 755 125 register callback success TERASIC DDDO0 TERASIC DODOD TERASIC DODOD TERASIC DD 003 TE
30. y modify the reference designs for various purposes accordingly 2 1 Features This section describes the major features of the HDMI board Board Features e One HSTC interface for connection purpose One HDMI transmitter with single transmitting port One HDMI receiver with duel receiving ports Two 2K EEPROM for storing EDID of two receiver ports separately e Powered from 3 3V pins of HSTC connector HDMI Transmitter Features 1 HDMI 1 3 transmitter 2 Compliant with HDMI 1 HDCP 1 2 and DVI 1 0 specifications 3 Supporting link speeds of up to 2 25 Gbps link clock rate of 225MHZ 4 Various video input interface supporting digital video standards such as v 24 30 36 bit RGB YCbCr 4 4 4 v 16 20 24 bit YCbCr 4 2 2 v 8 0 12 bit YCbCr 4 2 2 CCIR 656 5 Bi direction Color Space Conversion CSC between RGB and YCbCr color space with programmable coefficients Up down sampling between YCbCr 4 4 4 and YCbCr 4 2 2 Dither for conversion from 12 bit 10 bit to component to 8 bit Support Gammat Metadata packet iX p Digital audio input interface supporting v Upto four 125 interface supporting 8 channel audio with sample rates of 32 192 kHz and sample sizes of 16 24 bits v S PDIF interface supporting PCM Dolby Digital DTS digital audio at up to 192kHz frame rate v Support for high bit rate HBR audio such as DTS HD and Dolby TrueHD through the four 125 interface or the S PDIF interface with frame
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