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T940/T964 User Manual - Astronics Test Systems

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1. J1B J1A 4 Model T940 User Manual Note that connectors J1A and J1B have been rotated 180 and the location of Pin 1 is as shown Figure H 6 DR9 J1A J1B J2A J2B J3A and J3B Signal Connectors Astronics Test Systems DR9 Driver Receiver Board H 13 Model T940 User Manual DRA Resources Publication No 980938 Rev K Table H 5 DRA Resources Name Pin No Description CH 1 CH 24 Various Bi directional High speed channels ACH 1 ACH 24 Various Analog test connection DUTGNDA J1B 34 Input DUT UUT ground reference All of the Pin Electronics devices have a UUT ground reference input that can be selected to be this signal or signal ground SIG_GND Various Signal Ground reference Refer to Figure H 6 and Tables H 6 through H 8 Table H 6 J3A Connector Pinout by Pin Number DR9 Driver Receiver Board H 14 Connector Resource Pin Aor B 6 ACH35 8 ACH86 32 achas B Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Resource Aor B B B M uH HB Connector Resource Pin Aor B i a ae 32 0 4 6 8 0 4 6 8 0 4 Astronics Test Syste
2. Pin No Signal 1 SIG GND 2 CH1 3 SIG GND 4 CH2 5 SIG GND 6 CH3 7 SIG GND 8 CH4 9 SIG_GND 10 CH5 11 SIG_GND 12 CH6 13 SIG_GND 14 CH7 15 SIG_GND 16 CH8 17 SIG_GND 18 CH9 19 SIG_GND 20 CH10 21 SIG GND 22 11 23 SIG GND 24 CH12 25 SIG GND 26 CH13 27 SIG_GND 28 CH14 29 SIG_GND 30 CH15 31 SIG_GND 32 CH16 33 SIG_GND 34 AUX1A 35 SIG_GND 36 AUX2A 37 SIG_GND 38 AUX3 A DR8 Driver Receiver Board G 8 Pin No Signal 51 SIG_GND 52 CH17 53 SIG_GND 54 CH18 55 SIG_GND 56 CH19 57 SIG_GND 58 CH20 59 SIG_GND 60 21 61 SIG GND 62 CH22 63 SIG GND 64 CH23 65 SIG GND 66 CH24 67 SIG GND 68 CH25 69 SIG GND 70 CH26 71 SIG GND 72 CH27 73 SIG GND 74 CH28 75 SIG GND 76 CH29 77 SIG GND 78 CH30 79 SIG GND 80 CH31 81 SIG_GND 82 CH32 83 SIG_GND 84 AUX7 A 85 SIG_GND 86 AUX8 A 87 SIG_GND 88 AUX9 A Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal 39 SIG GND 40 AUX4A 41 SIG GND 42 AUX5 A 43 SIG GND 44 AUX6 A 45 SIG_GND 46 PBUT_A 47 PMODE_A 48 SIG_GND 49 NC 50 NC DRB 1 0 Channels J201 Table G 5 DR8 DRB I O Channels J201 Pin No Signal 89 AUX9 A 90 AUX10 A 91 AUX10 A 92 AUX11 A 93 AUX11 A 94 AUX12 A 95 AUX12 A 96 BCLK A 97 SIG_GND 98 NC 99 S
3. Astronics Test Systems Pin No Signal 29 CH14 30 CH15 31 CH15 32 CH16 33 16 34 AUX1 A 35 AUX1 A 36 AUX2 A 37 AUX2 A 38 AUX3 A 39 AUX3 A 40 AUX4 A 41 AUX4 A 42 AUX5 A 43 SIG_GND 44 AUX6 A 45 SIG_GND 46 PBUT_A 47 PMODE_A 48 SIG_GND 49 NU 50 NU Pin No Signal 79 CH30 80 CH31 81 CH31 82 CH32 83 CH32 84 AUX7 A 85 SIG_GND 86 AUX8 A 87 SIG_GND 88 AUX9 A 89 AUX9 A 90 AUX10 A 91 AUX10 A 92 AUX11 A 93 AUX11 A 94 AUX12 A 95 AUX12 A 96 BCLK A 97 SIG GND 98 NU 99 SIG GND 100 NU DR7 Driver Receiver Board F 9 Model T940 User Manual Publication No 980938 Rev K DRB 1 0 Channels J201 Table F 5 DR7 DRB Channels J201 Name Pin No Description CH33 to Various Bi directional RS 422 485 Positive High speed channels CH64 CH33 to Various Bi directional RS 422 485 Negative High speed channels CH64 SIG_GND Various Signal Ground reference AUX1 B 34 Bi directional General Purpose RS 422 485 Positive pin AUX1 B 35 Bi directional General Purpose RS 422 485 Negative AUX2 B 36 Bi directional General Purpose RS 422 485 Positive pin AUX2 B 37 Bi directional General Purpose RS 422 485 Negative pin AUX3 B 38 Bi directional General Purpose RS 422 485 Positive pin AUX3 B 39 Bi dire
4. Pei e EU send 5 120 Finishi Mode Step ii Inr ie o eee ir nrc iE evi e Lela ere ee 5 120 Rio od oro Er 5 121 CRO Type 5t et et o ttt e e et te testi 5 121 SEI 5 121 Syne N rber SEE pied c E d eda Eas pe onse 5 122 Event and Step 2 eina aerea d een reg ees A pco ua 5 122 OffSel et tnt dto bti to aat eire rec 5 122 Crit MIELE 5 123 Execute Panel Command 000 0110 00 00 na rn nnns inna 5 123 Execute ldle ied ete eee 5 123 Ute EE TRI 5 123 isti een iau et ttti 5 123 m 5 124 joe PEDE 5 124 T 5 124 Master Resets i niuis 5 124 BIN EE 5 124 Armi A E vests acc catum eee Ie ect dk 5 124 SLOP PO siegt aeter iiie deri deret 5 125 Analyze the Execution 42400200400 0 5 125 Static cant etos Kiss 5 125 Stimulus Delay ier ttti detecte beste e betta tebe 5 126 Response Delay ia cte eic copi e cot abe codon coto 5 126 TERRE ELEM 5 127 RESPONSE D 5 127 Kept BID I DP 5 127 Ries lts e e nds tum
5. 15 Signal Descriptions Figure 10 l 16 External Probe Module dae T TENA EEA Ra deal l 18 xvi Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual External Probe Module 5 iret lp e RE eod cs I 19 WRI4 GNAarACTCrISUCS eur e bh ru tu eel ph ede b t eee dates 20 B TIEIT Y GHANNELS n rte Pate e eet 1 20 PROGRAMMABLE CHANNELS 3 22 52 Ernie e tete kt tet bes EC e ELE ecu RR 1 21 Programmable AUX I O Min Max 1 23 Ben mc TT 1 24 50 suco cd Eu diss 1 24 PROBE MODULE CHARACTERISTICS sse eene nennen nnne nennen 1 24 Auxiliary l O Channels 1 26 Power Requirements e e e I 26 Environimnental z ier a eec dep 27 URT14 Signal Descriptions eot tette end e e et e dc edes 1 28 TA J1B J24A J2B J93A erred eter enter 1 29 J9 Connectors s idee ed e dede Hd dee Ui Ea ideale 1 33 eorum l 34 a a J 1 DRM Timing GChiaracterisHi6S 2
6. 5 16 Sexlde PN 5 17 esc EE 5 17 Update Group Settings 5 17 elemen EE 5 18 Delay Signals uta nte ut Et ah casa 5 18 BITE 5 18 A ETE E ENEE ETE 5 18 TTLTRG and ECLTRG Signal entente nennen 5 19 5 20 WR Properties uec ere e be ree dti eee 5 20 DUT GND 5 21 Voltage Mode 1 oce eli etd ED Gee Uode eda 5 21 geiles cm 5 22 MP SIG 5 22 Error Pulse Width di e ei RR ER e ERE RR reeled IRR ph RM REX EROS 5 23 Record Mode rcc d at e dnt 5 23 Config Data Sequencer A B sssssssssssssssesseeeeneen nennen en nentes tenens 5 24 Gonfig re Clocks rdiet gc deprecor repo PE Ia eed 5 24 Master locles i canat tte ATA deitate edi RR DT es 5 25 System Glock due itai estie re e ett ad cde n debeo 5 26 External Mode eee epe E pep ug dee ne uec Eve av uc 5 26 External Offset iiie xe ei o e ae edi ete dee c a ened 5 27 Astronics Test Systems iii Model T940 User Manual Publication No 980938 Rev K Synthesizer Freq 2 04 42 0 1000 nnne nnns nnns entente intr 5 27 Synthesizer Ref SOULE o Parere ue ptu
7. I 12 Figure 1 9 ADC Voltage and Temperature I 13 Figure 1 10 External Probe I 16 Figure 1 11 External Probe Module Flush eene 1 18 Figure l 12 External Probe Module Right 1 18 Figure l 13 External Probe Module with emen 1 19 Figure 1 14 Front Panel Connectors 1 28 Figure 1 15 UR14 J9 Calibration and Signal Connectors sse 1 33 Astronics Test Systems xxiii Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank xxiv Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 4 2 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Table 5 12 Table 5 13 Table 5 14 Table 5 15 Table 5 16 Table 5 17 Table 5 18 Table 5 19 Table 5 20 Table 5 21 Table 5 22 Table 5 23 Table 5 24 Table 5 25 Table 5 26 Table 5 27 Table 5 28 Table 5 29 List of Tables Logical Address entree nnns 2 3 VXI Interrupt 2 4 A24 A32
8. 5 156 Measure Voltage tribe ti e eid e EQ HR x EHE Re pig SR 5 156 Instrument FUriCtIonis 5 rrt teet on rp ette cate 5 156 Self Tes usines Iit ict ler 5 156 Full RAM E 7 he ttd hr mre ent me omma ed ome desi eae 5 158 Power Converter cie d sete Pared beside 5 158 Calibration Pariel rt vente eae ette e ah ge 5 159 Driver Recelvel itt stie nM 5 160 Galibrate F hction ce Ghee etuer te ee od od Bes ee ed Oe 5 160 Astronics Test Systems ix Model T940 User Manual Publication No 980938 Rev K i e EEE 5 161 Start CHAM stet e hd t e b pd une eel els a du eere ee eed 5 161 Meas Bela at aet det tati 5 161 EnA Ee EI 5 162 pr D 5 162 ia a a a Nase 5 163 Export 5 166 ip tastes 5 166 Boots ES EE EE A T ET E 5 166 Monitor Temperature 5 166 Trip Temperature iade did ende diee 5 166 xerit ed ea e td et ecu 5 169 DR3E DR9 and UR14 Voltage Monitor Panel and 5 169 22
9. 5 168 Figure 5 102 DRSE DR9 and UR14 Voltage Monitoring 5 169 Figure 5 103 DR4 Voltage Monitoring 5 171 Figure 5 104 DR3e Chip Temperature sssssssseseseseeeeeee enne enne nnns 5 173 Figure 5 105 DR9 Chip 5 174 Figure 5 106 UR14 Chip 5 174 Figure 5 107 Utility Reference 5 175 Figure 5 108 SFP Close enne intente nene 5 176 Astronics Test Systems xxi Model T940 User Manual Publication No 980938 Rev K Figure 5 109 SFP Reset Message ssssssssssssseseeeenneenen entretenir innen en 5 176 Figure 6 1 Invoke the Calibrate DRM Panel from the 6 4 Figure 6 2 T940 DR3e DR3e Connection Diagram sse 6 7 Figure 6 3 T940 DR9 DR9 or T940 UR14 Connection 6 7 Figure 6 4 T940 DR3e DR3e Connection 6 12 Figure 6 5 T940 DR9 DR9 or T940 UR14 Connection 6 12 Figure 8 1 Configure Module Panel sse nnne nennen nnne
10. F 8 Table F 5 DR7 DRB I O Channels 201 F 10 Table F 6 Calibration Settings ssessssssssssssseeeeeeee nennen entrent nsns F 10 xxviii Astronics Test Systems Publicatio n No 980938 Rev Model T940 User Manual Table G 1 DR8 4 4 00100000 nnne G 5 Table G 2 DR8 Power 2 0000000 snnt nnns G 6 Table 6 3 DR8 DRA I O Channels 200 G 7 Table G 4 DR8 Pin out by Pin Number G 8 Table G 5 DR8 DRB I O Channels 201 G 9 Table G 6 DR8 Pin out by Pin Number G 10 Table G 7 PWR 0 enne sint sen tete nnns G 11 Table G 8 Calibration Settings ssssssssssssssseseseeeeee eene nennen nennen ens G 12 Table H 1 DR9 Characteristics enne ener entr nensi nnn entente H 8 Table H 2 DR9 I O Min Max Levels Front Panel sss H 10 Table H 3 DR9 I O Min Max Levels Power Converter Type 1 or H 11 Table H 4 DR9 Power Requirements not including Power Converter power consumption H 11 Table H S DRA RESOUICES Ee oe eei ere ive Eee ide Bead etd H 14 Table H 6 J3A C
11. B 7 Table 4 DR1 Pinout by Pin Number B 8 Table B 5 DR1 DRB I O Channels J201 ssssssssssssssseeeenenneneen nennen nnne nennen B 9 Table 6 DR1 Pinout by Pin Number 0408 B 10 Table B 7 PWR Gonhnector eiecit e od ned eon Ree RE ee pd alan B 12 TTable B 8 Calibration Settings tee edt e dete t B 12 Table Gait DRZ CharacteniStiGs x ttn rr pe rrt diee Pet oar teet chr idee 5 Table C 2 DR2 Power Requirements ssssssssssssssseseeeeeen eene nennen nennt enne C 6 Table C 3 DR2 DRA I O Channels J200 ssssssssssssssseeeeene C 7 Table C 4 DR2 Pinout by Pin Number 2 4040240 000 00 enne nnne nennen C 8 Table C 5 DR2 DRB I O Channels J201 sse nennen C 10 Table C 6 DR2 Pinout by Pin Number 1 C 11 Table C 7 PWR si nnns entente nes C 13 Table C 8 Calibration 13 Table D t DR3e Characteristics 5er ettet e dee eda D 8 Table D 2 DR3e I O Min Max Levels Front Panel sssssssssseseseeeenneenen nennen D 9 Table D 3 DR3e I O Min Max Levels Power Converter Type 1 or D 10 Table D 4 VXI Power Requirements with F
12. nemen nre 5 40 Output to Input Disable 5 41 Pass Fail Basis Settings n ote ett e ee ce tette s 5 41 Pass Valid Mode Settings Rr oett inc Pet ca o Pets 5 42 Over Current Window Settings sess esee enne nennen 5 44 Drive Fault Settings dp ce eda 5 45 Probe Data Settings ade d 5 46 GRO Gapt re Settings 5 46 Probe Button Sett S a a a a a aa aaa aaau 5 47 Probe Cal Signal Settings sse 5 48 Jump Pass Fail Settings addere dee tes 5 50 Phase 3 Mode Settings ote tat ended e ien te etti Rede 5 51 Window 3 Mode Settings uen e Rr oe rte ne eta c ge Pete En o P ea 5 51 CRG epe hte tet bb tion cte testes 5 52 CRC Algorithm and Mask Settings sse 5 52 Static State Settings e ue debe PU ge UN BU ede Pee HE 5 53 Stimulus Signal 5 54 Stimulus Format 65 2 4 0 0 ener enne nnne nennen 5 55 Capture Signal Settings esia 2 exi is ehe nee RR MR Ee FR dg De 5 57 Capture Mode Settings 5 57 Static Mode Settings 4 Assis jist stati te nt d Tog fi eng it Edi 5 58 Slew Seltings z Paine adl es
13. Astronics Test Systems Functional Description 4 9 Model T940 User Manual Publication No 980938 Rev K COUPLED DRM2 DRM1 DRM6 DRM5 7 DRM4 LINKED In this example DSA and DSB on DRM1 and DRM2 are coupled to a DRS 128 channels DSA and DSB on DRM3 and DRM4 are coupled to a second DRS 128 channels DSA and DSB on DRM5 are linked and running independent of a DRS 64 channels DSA and DSB on DRM6 are not linked and running independent of a DRS two groups of 32 channels each Data Sequencer IM CONTROL DATA SEQUENCER pS ii PHASE CH DATA SIM WINDOW CH EN LTB SEQUENCE LOGIC RECADDR PATADDR PRBADDR sl PRBADDR PROBE FLAG RAM PATADDR AUX RH AUX RECADDR MPSIG SEQUENCE CONTROL Figure 4 4 Data Sequencer Block Diagram Functional Description 4 10 Astronics Test Systems Publication No 980938 Rev K Terms Used in this Section 250 MHz 500 MHz AUX DATA AUX EN AUX I O AUX RH AUX RL1 BERREN CBUS CH DATA CH EN CH IN CH IN ERR IN CH OC CH RH CH RH CONDEN CONTROL ERROR FLAGS FS HALT IM CONTROL IM IMSEQ JUMP Astronics Test Systems Model T940 User Manual 250 MHz clock derived from the 500 MHz clock 500 MHz oscillator clock AUX output data value AUX output enable value AUX output and enable signals as well as the AUX input and probe data AUX input response high comparator result AUX input response low compa
14. Source Description Channel Channel 1 through 32 AUX AUX 1 through 12 Freq Synth Frequency Synthesizer VXICLK10 10 MHz VXI backplane clock 250 MHz 500 MHz clock divided by 2 Pulse Generator Pulse Generator The relevant VXlplug amp play API function is e tat964 setCounterlnput e tat964 queryCounterlnput Astronics Test Systems Soft Front Panel Operation 5 153 Model T940 User Manual Publication No 980938 Rev K Input 1 3 Slope These controls allow the counter input slope to be selected Table 5 103 Counter Timer Input 1 3 Slope Source Description Pos Select rising edge Neg Select falling edge The relevant VXlplug amp play API function is e tat964 setCounterlnput e tat964 queryCounterlnput Aperture This control sets the gate aperture time for the frequency period and timed totalize functions Table 5 104 Counter Timer Aperture Setting Description 1us One microsecond gate time 10us Ten microsecond gate time 100us One hundred microsecond gate time 1ms One millisecond gate time 10ms Ten millisecond gate time 100ms One hundred millisecond gate time 1s One second gate time 10s Ten second gate time The relevant VXlplug amp play API function is e tat964 setCounterAperture e tat964 queryCounterAperture Trigger This pull down control programs the trigger source The selections for this pull down control are Soft Fron
15. c dad vue e eed e rede E dde Win eas G 1 Block Daira ni ie extet dt seb tar G 1 Auxiliary Driver amp Receiver 22 0000 G 2 Signal Descriptions teet tiet edd aedi a eb PR eate G 3 DR8 Driver amp Receiver I O sssssssssssssssssssseee entente enne sn terrens enne nennen nennen G 4 Signal DESCriPtlO MSs E G 4 GOntrol LOGIC cia is e nei at edt ee dite E et G 4 Signal Descriptio NS ence ict eet Pre ini er Pt ea ett pe e G 4 Firmware amp NV Data cose er En eene dede ED ette N G 5 Signal Descriptions ie cee G 5 DRE Characteristics o eee etudiant tm Sel G 5 Power Requiremaents ird bee ere ree iran ide G 6 Environmental oe ah eli b eniti G 6 DR8 Signal Description enne G 7 DRAJ O Channels J200 2 aired dee dee y e Facete se dcn e opp es G 7 DRBAI O Channels J201 che ede ee aa ena ee tide en ied G 9 PWR eee EAS G 11 GaliDratiODs zo tn ette tc iets Ate bo G 12 Astronics Test Systems Model T940 User Manual Publication No 980938 Rev K Appendix g t H 1 DR9 Driver Recelver Board re neither tue ede annus H 1 DRO F
16. Figure 5 59 Initialize Step Pattern Set Panel The relevant VXlIplug amp play API function is e tat964 initPatternSet If the Patterns control reads a number greater than zero then this command button displays the Edit Pattern Data panel see Editing the Patterns in Chapter 5 Figure 5 60 Edit Pattern Set Panel Soft Front Panel Operation 5 108 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Properties This command button displays the Sequence Step Properties panel The sequence step properties consist of the following hardware settings 1 Handshake Control Pause Resume 2 Waveform 3 Phase Trigger VXIO 2 INSTR Edit DSA Sequence Step 1 Properties Waveform 1 Waveforn2 Waveform3 Disabled W Disabled Disabled Disabled 1 Phase 1 Trigger Phase 2 Trigger Phase 3 Trigger Phase 4 Trigger System Clock System Clock w System Clock 7 System Clock w Figure 5 61 Sequence Step Properties Panel Handshake Control The handshake control allows the user to assign a signal Pause that can be either internal or external which will pause the sequencer When paused the following will stop e Phases e Windows e Waveforms For each pause signal selection there is a corresponding signal that will continue Resume sequence operation See the Pause and Halt section of Chapter 8 for additional details about the use of pause Pause Signal This pull do
17. oen 50 Middle High Glitch Signal starts between RL and RH crosses the RH two or more times and ends between RL and RH Close oen 55 High Glitch Signal starts above RH crosses the RH two or more times and ends above Close oe 88 Middle Low Signal starts between RL and RH crosses the RL once and ends below Close open Middle Glitch Low Signal starts between RL and RH Close Model T940 User Manual 36 Rising Edge Signal starts below RL and crosses the RL and RH once Close Open 51 High Glitch Middle Signal starts above RH crosses the RH three or more times and ends between RL and RH Close Open 72 Rising Edge Glitch Middle Signal starts below RL crosses RL once crosses RH two or more times and ends between RL and RH Close open Middle Low Glitch Signal starts between RL and RH crosses the RL two or more times and ends between RL and Close oe Low Glitch Signal starts below RL crosses the RL two or more times and ends below RL Close Soft Front Panel Operation 5 137 Model T940 User Manual three or more times and ends between RL and RH eed RL B4 Close Middle Rising Edge Signal starts between RL and RH crosses the RL two or mor
18. sse 5 81 Pattern Set Data View Menu sssssssssseseseeeeeeen enne enne nnns nnne nennen 5 81 Goto Pattern Pariel e ae Ra ec depu e o ae e 5 82 Patterm60dess esc amittant aet st 5 82 Probe God88 uai Ue oh dtes 5 83 Pattern Set Data File 5 86 Edit Waveforms Panel 1 5 91 Edit Waveforms Panel Waveform 5 5 91 Data Sequencer Parameters Panel sss enne 5 93 Edit Vector Bilis Panel ree e bee e e 5 95 Edit Vector Table 5 97 Sequencer Channel Test 5 98 Edit Sequence Step 5 99 Sequence Step Data Panel s sse nennen 5 100 Edit Timing Set Panel erp dede e 5 107 Initialize Step Pattern Set 5 108 Edit Pattern Set P nell eiit d prece deco at daga pae 5 108 Sequence Step Properties Panel sese 5 109 Executing a Sequence Panel sse entren 5 112 Execute State 5 113 Set Syne Panel e apa cet ate ee aa 5 122 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure 5 65 Execute DSA View Menu sssssss
19. 000 1 9 Driver Receiver Board 1 10 Model and Part Number Information 2 2 242 4 1 10 ACCOSSOLIOGS s ree ed ith 1 12 2 iere 2 1 PP ein 2 1 Initial Digital Board DB Switch Setting ssssssssseeeeeneeeenen nennen 2 2 Logical Address Sel amp ctior 2 1c epe rev Diete ae ae dea eme ee eie dac 2 3 VXI Interrupt 2 4 A24 A32 Map Selection 2 4 Other Selttlhgs nr aede bones de dened adiret RE es Be pax Ree RETE ee E 2 5 Debug Selection oct to dete n et t e tene cos 2 5 M d Selectionata 2 5 Bus Request Selections deme t a 2 6 DRS Inter Module Mode nnne nennen 2 6 Installing the Module into VXI 2 0004 0000 eene nnne nennen 2 7 Initial POWOE QI ioni esteri intu 2 10 Sottware lInstallation 3 et bea v MR t un n AR LU 2 10 VXIplug amp play Instrument Driver eee 2 10 Installi
20. ssssssssssssseeseeeeneennene 5 12 Power Converter enne 5 13 LTB Signal Pull Down Settings sess 5 14 Direction Settlngs sede tei etae tea endet b tur 5 15 Group Offset Attribute 0 5 16 Group Slew Attribute 0 2 44 nnne 5 17 Delay Signal Settings eet e te eet fen catt i cedit ls 5 18 Signal PulEDown Settlngs Et nere ttv t iae 5 19 Voltage Mode Settings Inc min tete t ta ee datas 5 21 rre i 5 22 MPSIG Source Rd daga 5 22 Error Pulse Width Settings ssssssssssseseeeeeeenen nennen nennen 5 23 Record Mode 5 24 Master Clock Source Settings sse nnne 5 25 System Clock Source Settings sssssssssssssssseseeeeee eene 5 26 External Mode Settings esssssssssessseess eee 5 26 Synthesizer Ref Source Settings sssssssssssssseeeeeeene entren 5 27 Watchdog uc erbe re b ee eo edes 5 29 Watchdog Timer Resolution 5 30 Sequence Timeout State Action sse 5 30 Trigger Seting S
21. dee ete eee eade uen LEE dede bere nde 5 169 V Voltage A peterent eire cee ee pee ee 5 170 Front Panel DUT GND edet 5 170 EXIEORGEx E ure 5 170 EXISENSEun cun Dt dL IDA 5 170 Chantel at ia ee Ert ie ep Bb pavit i Lo iat o eM eal 5 170 Monitor 5 170 Monitor Voltage tomar ba eie 5 171 DR4 Voltage Monitor Panel and enne 5 171 SIQnal s dete oi et cte ate cute Stet 5 171 Channel trt e ptc a a ee doe 5 171 Monitor Voltage 5 171 juo 5 172 POSITIVE SIG Mall student Laut or t el stein 5 172 Negative Signal reti tr Und be reris 5 172 etd acea tih n 5 172 ei bo mig bre egeta 5 172 81212 12 pe 5 172 MEI EE 5 173 Chip Temperature Panel 5 eite feu e iP eas ee i eie tn 5 173 Utility Reference 5 174 Monitor Signal atten ertet Ate Pera 5 175 SFP Close 2 244 1 1 1 0 0 aa ns aa aaa sinis innen 5 176 Chapter O cM M HP 6 1 Programmable Chann
22. 5 143 Sync Error Step cid deo Mies edu nee 5 143 Sync Error Pattern Address eem ee nera dee a a aero die 5 143 tub edo t stunt 5 144 Driver Receiver Events 5 144 aces cts tes ash see p E E 5 147 AE E E MIR ME 5 147 EVV CMM erste eh esed n DN Mn Mo 5 147 ClearEVelit eee Ete ict ede cdd 5 147 5 147 Driver Receiver Data 2 5 148 VXI Trigger Readback 5 150 Query Power Results Message ccccceeeceeeeeeeseeeeeeaeeeeaeeseaeeecaaeeeeaaeseeeeeenaeeesaeeteeeseeneee 5 150 Power Converter Condition Panel ccccccccccccsesssseseceseeecseseeaeceeeeseecsesaeaeceeeesesesesseaeeeeess 5 151 Counter Timer Panel 5 152 Un CUOr di id nie muta edi tima the 5 152 SU C6 54 ea eut ap EC 5 153 Input 1 35 SIop6 i iiem aed dep ER Hp RR 5 154 5 154 cct oto be 5 154 Initiate ote e t e oe e ea tee e t e ee eee diues 5 155 Results de t a t tdt cg 5 155 TP e 5 155 Ghiannel eot dtes en
23. Type 4 Range V4 Nominal Voltage V Nominal Voltage 12 to 12 16V 15 6V 15 to 5 9 6V 19 2V 10 to 10 16V 14 1V 5 to 7 12V 9 6V 5 to 15 19 2V 9 6V 0 to 22 28 8V 4 5V 2 to 20 26 4V 6V The type 4 power converter has a reduced voltage range and better power distribution of the VXI backplane supplies Table 4 2 Power Converter Type 004 Ranges Range V Nominal Voltage V Nominal Voltage 7 to 7 14 4V 11 7V 15 to 2 9 6V 18 9V 10 to 9 16 8V 14 1V 3 to 7 14 4V 7 2V 5 to 5 14 4V 9 6V 0 to 16 24V 4 5V 2 to 14 21 6V 6V Inter Module Control The T940 inter module configuration is determined by jumpers and the primary to terminator order is right to left The following sections describe the T940 inter module implementation Astronics Test Systems Functional Description 4 3 Model T940 User Manual Publication No 980938 Rev K LBUSC LBUSA LBUSC LBUSA LBUSC LBUSA LBUSC LBUSA INTER MODULE CONTROL INTER MODULE CONTROL INTER MODULE CONTROL INTER MODULE CONTROL INTER MODULE CONTROL Inter Module Control CONTROL IMJMPR Figure 4 3 T940 Inter Module Control Block Diagram Terms Used in this Section DRM Digital Resource Module A DRM is a single T940 module A DRM is comprised of a Digital Board DB and one or two Driver Receiver boards DRA and DRB DRS Digital Resource
24. essseeseeeeenenennenen nennen nnne nennen 8 13 Jumping and Halting on Pass Fail eene 8 14 Understanding Pass and 8 18 Additional Pipeline 8 23 Valid Pass and Capture 2 8 24 Additional Halt 8 24 Pipelined Depth GalculatlQriz ien ect Dr xt x E Fade 8 26 Pause and Halt Capabilities dn eee ee ho 8 27 IBI ise EE 8 27 Applications Em 8 27 CPU Halt Single Stepping Resume 8 27 External Halt 8 28 Halt Exambple8 5 5 ui th treu 8 29 a ene reu ite oth TES ea 8 30 Pause Op rations ii i etg f rr adeb ue eig i E Eo e Ue ded 8 30 Pause EX ANN inei ROI HAM 8 32 Pause Notes steer eth e co aee E co d e eta dtt 8 33 Sequencer ODeratlor mer este nivea v D beta pese a ite n 8 34 Introduction e HR LH MUR PH ER ep Minded 8 34 Pattern Control Instr ctiOns 8 35 Pattern Control Instruction Details 0 2 0 8 37 T964 VXI Backplane Trigger Bus sese 8
25. sese 5 151 Figure 5 84 Timer Counter Panel sess en nent enn 5 152 Fig re 5 85 PMU Panel icc tt tete eee ae be a tet ig padres 5 155 Figure 5 86 Self Test Result Message esee ener nre 5 156 Figure 5 87 Full RAM Test Results 5 158 Figure 5 88 Power Converter Test Results 5 159 Figure 5 89 Calibration Confirmation nnn 5 160 Figure 5 90 Calibration Panel ee cececeseceseceseeeeneeeeeeeeeeseeeeneeeacecanecaeeeseeseaeseaeseeeseseseenseeneeeneesaes 5 160 Figure 5 91 Confirm Calibrate Panel sse nennen nennen sene 5 162 Figure 5 92 Calibrate Warm Up 9 5 162 Figure 5 93 Calibrate Run 4 5 163 Figure 5 94 Confirm Verify 5 164 Figure 5 95 Verify Select Directory 5 164 Figure 5 96 Verify Warm up Panel 5 165 Fig re 5 97 Verity Run nite rettet eet tea e eit e EP ERA dede 5 165 Figure 5 98 DB Monitor Temperature Panel sss 5 166 Figure 5 99 DR3e Monitor Temperature 5 167 Figure 5 100 DR9 Monitor Temperature Panel sse 5 168 Figure 5 101 UR14 Monitor Temperature
26. Figure G 3 illustrates the configuration and control of the DR8 Driver amp Receiver TTL Figure G 3 DR8 Driver amp Receiver I O Block Diagram Signal Descriptions DATA Channel and auxiliary data output signals from the Data Sequencer to the TTL output drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the TTL output drivers RH Response High input signals to the Data Sequencer from the TTL input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the TTL input receivers 0 good 0 1 good 1 AUX 1 4 Four TTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 CH 1 32 These are UUT Bi directional TTL I O channels from the DR8 Drivers and Receivers VCC TTL Power 5 0V Control Logic The control logic contains the registers memory and logic that allow the digital board to interface and configure the hardware Signal Descriptions CONTROL Signals used to control isolation termination NV data and load relays DR8 Driver Receiver Board G 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digital board to the Driver Receiver board MF SIG Multi Function signal output to the PWR connector Firmware amp NV Data The Control Logic firmware is loaded via a s
27. Name Pin Description No AUX8 B 7 Bi directional General Purpose LVTTL I O pin 50 Ohm series PROBE MODE B 9 Output Probe Support Output BCLK B 11 Output Serial Clock PBUT B 13 Bi directional Probe Button Input MPSIG B 15 Output Multi purpose Signal MONITOR B 17 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time EXTFORCE B 19 Input External Force routed to all of the Pin Electronics devices used to calibrate the instrument to an external standard GND 2 20 Ground Even Calibration Driver Receiver boards are calibrated using the following settings prior to shipment 15V to 17 V Voltage Mode Power Converter 12 to 12 e 7Vto 24 V Voltage Mode Power Converter 5 to 15 DAC Basic Factory stored in EEPROM Driver channel deskew Factory stored in EEPROM ADC Monitor Field upgradable stored in EEPROM DVH DVL Field upgradable stored in EEPROM CVH CVL Field upgradable stored in EEPROM Vcom High Vcom Low Field upgradable stored in EEPROM Isource Isink Field upgradable stored in EEPROM IAL IAH Field upgradable stored in EEPROM Inter module timing deskew Static End of cable deskew Static Astronics Test Systems DR9 Driver Receiver Board H 19 Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank DR9 Driver Receiver Board H 20 Astronics
28. eee 5 102 Sequence TIMEOUTS zs oce neath taxes Ee ERE eeu Ea aa 5 102 iet EE 5 102 Sequence Flag 1 and Sequence Flag 2 sss eene 5 102 AUTOS Bor 5 102 Jump Step sioe ettet a t t e ei 5 103 J mp GonditiOn s icit ance ote e egest 5 103 Loop 5 104 Eoop GOUht6et p I Tete ities A 5 105 Mere 5 105 Pass Eall Gleat 6x ioa eit ita etui Mucagas neces arate eio 5 105 Step Record Mode tei tue at ei eI RE 5 105 use Ibit ore fe d p e REN 5 106 I atterris e c ee PNE ES DI E EE ere 5 107 sin create ei a ata edat es 5 109 Handshake Control tre e et ttai dn o ta pe teer Patent inge Pete aic de 5 109 5 cte ect deci t ceti esos 5 109 Resume Modlifier eec Mra eu desea e entail 5 110 Waveform Properties 5 111 Waveform1 Waveforma 5 111 Wavetorm it ter deeem p ve dei 5 111 Phase Trigger 0 04 0112010 nennen nnne A 5 111 Execute the 5 112 Ex cution OV6etrViIGW acest boi ntact adel ege tcp odds 5 113 Execute Panel Indicators itr pe
29. 24V power rails This tool is available upon request from Astronics Test Systems at atssales astronics com Environmental Temperature Operating 0 C to 45 Storage 40 C to 70 C 0 C to 10 C Not controlled Humidity 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 596 to 7596 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR3s Max 27 4 los 8 9 mmH 0 Typ 18 9 lps 4 5 mmH 0 Front Panel Current Requirements channels unloaded V 3 8 Amax 2 9 A typ 21 5 V V 4 3 3 4 A typ 10 5 V MTBF ground benign DR3e 131 656 hours T940 180 885 hours Power Converter 540 040 hours T940 DR3e 66 775 hours T940 DR3e DR3e 44 304 hours Dimensions 20 x 114 x 305 mm EMC Council Directive 89 336 EEC Safety Low Voltage Directive 73 23 Emission EN61326 1 2006 Class Immunity EN61326 1 2006 Table 1 Designed to Meet Testing in Progress BS EN61010 1 2010 Designed to Meet Testing in Progress Fora DRM with 2 DR3s the 1263 chassis has sufficient airflow for 25 max inlet air temperature at lt 2000 ft Astronics Test Systems DR3e Driver Receiver Board D 11 Model T940 User Manual Publication No 980938 Rev K DR3e Signal Description DRA Figure D 5 J200 and J201 Connectors DR3e Driver Receiver Board D 12 Astronics Test Systems Publication No 9
30. MPSIG Signal This control sets the source of the MPSIG All checked signals are ORed together Table 5 18 MPSIG Source Setting Description Sequence Active MPSIG goes high when sequence active is true Paused MPSIG goes high when the sequencer is paused Halt MPSIG goes high when the sequencer is halted Burst Error MPSIG goes high when burst error is true Over Current MPSIG goes high when over current is true Drive Fault MPSIG goes high when drive fault is true Watchdog Timeout MPSIG goes high when the watchdog timeout is true Sequence Timeout MPSIG goes high when the sequence timeout is true Pattern Timeout MPSIG goes high when the pattern timeout is true Sync Error MPSIG goes high when the sync error is true Soft Front Panel Operation 5 22 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API function is e tat964 setMpsigSource Error Pulse Width This pull down programs the error signal pulse width The error pulse is a DRS signal used for counting and recording errors The error pulse width is set during the DRS timing bus calibration with the Rev J driver or later and sequencer revision 0 20 or later The pulse width needs to be set the same in all coupled sequencers When the DRM is configured as a primary and not coupled to another sequencer use a setting of 2 3 1 lt If linked refer to table 5 21 below for the optima
31. Publication No 980938 Rev K Model T940 User Manual Bit Name Description 5 Over Current One or more channels generated an over current event 6 Watchdog Timeout A watchdog timeout occurred 7 Sequence Timeout A sequence timeout occurred 8 Pipeline FIFO Error Pipeline depth inadequate for the Data Rate 9 DRS Sync Error The DRS sync error flag is set The error step and error pattern address are available in the sequencer status panel 10 Phase Window Glitch A phase or window pulse less than 8 was detected 11 Window Capture An expect pattern code was programmed on a Fault channel with the capture mode set to none or the window was missing 12 Pattern Timeout A pattern timeout occurred 13 Pause A pause occurred 14 External Stop External stop signal received 15 Freq Synth Error The frequency synthesizer is selected as the master clock and is running slower than 40 kHz 16 Multiple Subroutine Attempt to jump to a subroutine when already in one 17 Return Subroutine Return encountered when not in a subroutine Error 18 Subroutine Active Sequence completed while still in a subroutine Error 19 Idle Complete Idle sequence completed 20 Sequence Complete Sequence completed 21 External TO CLK The external TO CLK is too fast or glitchy The Error edges which cause the too fast condition are ignored such that the resulta
32. cccccccsssssseeeeeeeeeeeeeseseeeeeeeeeeeeseneeeseeeeeeeeeeeeesenseeeeneeeeeeees l 1 URTA Faa e oett aot ip E 1 Block DIBgFalTi 55 e e eder dee 1 1 Auxiliary Driver and Receiver l O 1 4 Signal Descriptions Figure 1 3 1 5 Signal Descriptions Figure 1 4 nnne nennen 6 Signal Descriptions Figure 5 7 gis om 8 Signal Descriptions Figure 1 6 enne enne nennen 8 Programmable Driver and Receiver l O sssssssssssssesseseneerennene enne nennen 1 10 Signal Descriptions Figure 1 7 1 10 Open Collector Channels l O l 11 Signal Descriptions Figure 1 12 ADC Voltage and Temperature Monitoring nennen I 13 Signal Descriptions Figure 1 9 I 13 URTA Control Rp Ce bte cn A D iuge I 15 Firmware and Calibration Storage ccccccccceeececeeeeeceeeeeeeaeeeeeeeceaeeecaaeeeeaeeseeeesaeeesaeeeeaeeseaees 15 External Probe Module Block
33. sse 5 127 Table 5 93 Static Stimulus Settings niiina a iaa aaa aa a aa A 5 127 Table 5 94 Results View 08 1 22221401001 nennen tenente nnns nnne tents 5 129 Table 5 95 Probe Memory Bit nennen 5 136 Table 5 96 Sequence Enable Condition Event Bit 5 140 Table 5 97 Sequence Status Bit Descriptions 5 144 Table 5 98 Sequence Status Bit Descriptions 5 145 Table 5 99 Sequence Status Bit Descriptions 5 146 Table 5 100 Alert Bit 20 00 eene enne 5 148 Table 5 101 Counter Timer Function Settings ssssssssssssseeee enne 5 153 Table 5 102 Counter Timer Input 1 3 Source sssssssssssssseeeeeeeen nenne 5 153 Table 5 103 Counter Timer Input 1 3 Slope sse 5 154 Table 5 104 Counter Timer Aperture eene enne entente tenens 5 154 Table 5 105 Timer Counter Trigger Source ccsccceeeeeseeeeeeeeceeeeeeeaeeeeaaeeeeaeeseaeeesaeeesaeeeeneesaas 5 155 Table 5 106 Self Test Result Code Descriptions 2 44040 400 5 157 Table 5 107 Power Converter Test Thresholds 0040 0 00 5 159 Table 5 108 Calibrate Function Settings ssss
34. 5 48 Comipensatiol ds st suerte sheers KL EET 5 48 P RIDERE 5 49 hide E 5 50 Jump Pass ient iei teme iei 5 50 Phase 3 5 50 edt t e e sius 5 51 Window 9 Delay teet ete pie rc eti teta ni eee v e Beo ertet t 5 51 CBRGOG Preload nado eee Miete n deep 5 51 CRC Algorithm and Capture 5 52 Stalic Stale i ad eH Lt be io asda tae 5 52 Configuring the Channels 5 53 Selecting the Channels esses esee entente nnns 5 53 Ghannel Par meters i rd pe Be tera fe ae pde E t E ev regen 5 54 Stimulus Sighal e f eiae 5 54 Stimulus ter cotes 5 55 Capture Signal say reu perte vie tear te tradet n e ore 5 56 Capture MOde cete ndo Pre ter e edd i Pee irre ea veh kn n dn 5 57 Static Modesti eec 5 57 IEEE 5 58 Configure Channel 5 58 Driver abest eter pO mdi 5 59 Comparator Levels itii i t a edu ARE ERE EINE ce RAM PHA 5 60 Driver Slew 3 dia eed de eter etate 5 60 REDE 5 60 Over Gu rrent Alarm Levels
35. A Data Sequencer A Clocks ITE Data Sequencer B Timers plug play J Channels Triggers 40 Slot 4 Aux Outputs Pulse Generator VX10 2 INSTR DI Interrupts Settings Active Figure 5 20 Configure Data Sequencer Configure Clocks Access this panel from the menu bar Config Data Sequencer x Clocks Where x is the sequencer you wish to configure Soft Front Panel Operation 5 24 Astronics Test Systems Publication No 980938 Rev K Master Clock Model T940 User Manual pis VXIO 2 INSTR Configure DSA Clocks EIU Rising Edge External Offset 20 Figure 5 21 Configure Clocks This pull down control programs the sequencer master clock source The master clock defines the sequencer timing resolution The resolution is half of the master clock period The selections for this pull down control are Table 5 21 Master Clock Source Settings Synthesizer 1 2 FS For example if FS 100 MHz Resolution 1 2 100 000 000 Resolution 5ns Setting Description Typical Usage 500 MHz Sequencer timing resolution set to Default case 1 ns timing resolution ins is required no frequency reference Frequency Sequencer timing resolution set to 1 ns timing resolution is required an external frequency reference will be used to train the master clock or when a non standard exact data rate is required For example if a 48 MHz data rate is required the synthesizer set to 480 MHz giv
36. Ionia duc inso nena d J 1 go EDI IER J 1 External AUX Input Timing nennen J 1 External AUX Output Timing Adjustments 1 44 0 4 2 TRG Input Timing Adjustments 2 42424 4 0 0 0 0 4 2 TRG Output Timing Adjustments nnn sn terrens J 2 AUXInputto PROS esto ttd ett ts eG ned Scitis ens J 2 TRG Inputto AUX OUtpUL ered nent ett Eire eb oen n Hep ei ed J 2 DRS Timing AdJj stmoeftts ote let eee J 2 External TOCLK to TOCLK In at min delay setting ssseeenen J 2 External Halt Setup Time to SEQ J 3 External Pause to CLK J 3 External Pause Phase Resume to CLK 2 2 0 000 eee J 3 External Jump Setup Time to TOCLK 4 3 External Start Setup Time to TOCLK In J 4 External Stop Setup Time to TOCLK nennen J 4 A Channel Input to TRG Bus for a channel 1 J 4 SEQ ACT IDLE ACT Sync Pulse Seq Flag to TRG J 4 Astronics Test Systems xvii Model T940 User
37. Resolution 100 ns using a 5 MHz master clock Note Repeat pattern data is updated based on the static drive state Static Mode Type 2a Utilizes an independent static available on F W 0 20 and stimulus response path that doesn t alter earlier the Repeated pattern data of dynamic tests Static test is run in parallel with a standby Sequence Step Stimulus and Response capture timing defined by Pulse Generator assert and de assert timing set the Pulse Generator for Single Start Resolution and range based on the Pulse Generation settings Standby Sequence Step must have a period greater than the de assert timing Static Mode Type 2b Utilizes an independent static available on F W 0 21and stimulus response path that doesn t alter later the Repeated pattern data of dynamic tests Static test is not run in parallel with a standby Sequence Step Response Delay from 100ns to 6 5ms in 100ns steps Recording Mode Characteristics Recording Modes per Record errors for programmable inputs Sequence Step that have a Good 1 and Good 0 Record errors for single ended inputs that have only a Good 1 Record raw data based on NOT a Good 0 Record raw data based on a Good 1 Specifications 7 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Recording Type Un expanded Record data at the same index as the stimulus will overwrite data when looping
38. See Pin Electronic AUX Channels entry above or External Probe Module entry below Connects to PROBE for external probe compensation PROBE DETECT LVTTL input used to detect the presence of the external probe module 412V 12V Low current power for external probe support Max current 200 mA PROBE MODULE CHARACTERISTICS Table 8 Probe Module Characteristics Description Characteristics Probe Tip Characteristics Input capacitance 20 pF Input Impedance 10 MO x 196 CONTACT DETECT 5 MQ or gt 50 pF Illuminates the green LED on the Probe Handle when contact is made Contact LED will extinguish while a pattern burst is in progress ANALOG PERFORMANCE UR14 Driver Receiver Board 1 24 Input voltage detectable range 19 V to 19 V Note This input range will be attenuated by the Probe but amplified by the Probe Module to present to the D R board a signal which is 5 V max with a 50 source termination Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Description Characteristics Input voltage absolute maximum rating 200 V to 200 V Note V Protection to be provided on the Probe Module Detector voltage accuracy 50 mV 1 Detector resolution 10 mV DUT GND correction done in the Probe Module Aux 1 input GND correction is automatically disabled TIMING PERFORMAN
39. Specifying the beginning level and the bit number of subsequent transitions defines the waveform Example 1 0 5 10 15 Beginning Level 0 3 Transitions at 5 10 15 Would generate the following waveform 00000111110000011111111 Bits 1 5 low Bits 6 10 high Bits 11 15 low Bits 16 through the size of the table high Example 2 1 Beginning Level 1 Soft Front Panel Operation 5 92 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual No transitions Would generate the following waveform 111 Bits 1 through the size of the table high Waveform five and six have a maximum of two transitions The relevant VXIplug amp play API function is tat964_setWaveformData Editing Sequence Parameters The sequence parameters consist of the following entries Loop Counter Mode Pipeline Mask Strobe Vector Bit Table Selection 4 Channel Test Access this panel from the menu bar Edit gt Data Sequencer x gt Sequence Parameters Where x is the sequencer you wish to configure ceo P Loop Counter Terminal Count Action Reload Reload Reload Reload Reload LC10 1 14 1 15 Reload Reload Reload Reload Reload Reload Vector Strobe 240 Windowi Vector Tabie Set Vector Bits Figure 5 52 Data Sequencer Parameters Panel LCO LC15 These controls program the loop counter mode There are sixteen 16 bit l
40. StatChan 1 Meas Delay 0300 End Channel 36 Channel 2 1 Status Figure 5 97 Verify Run Panel The relevant VXlplug amp play API functions are e tat964 verifyChannelCalibration Astronics Test Systems Soft Front Panel Operation 5 165 Model T940 User Manual Publication No 980938 Rev K Export This command button saves the current calibration data to a comma separated file with a format that can be loaded using the File Load DRA DRB Calibration menu command The relevant VXIplug amp play API functions e tat964_saveCalibrationFile Stop This command button stops a calibration or verification run Update This command button writes the new calibration data to non volatile memory The relevant VXlplug amp play function is e tat964 updateCalibrationData Monitor Temperature Panel This panel shows the temperature of the following components within the DRM e Digital Board Sequencer FPGAs DR3e DRY and UR14 variable voltage pin electronics Trip Temperature This control programs a trip point that will disconnect the power pins from the variable voltage pin electronics and open the connect relays if the specified temperature is exceeded A Driver Receiver temperature alert event is also generated Figure 5 98 DB Monitor Temperature Panel Soft Front Panel Operation 5 166 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 03 04 05 06 CH07 08
41. cse debts re desde baba aU F 1 Block Diagram s iie ee eoe B e IRE dettes tes im LES F 1 Auxiliary Driver amp Receiver 1 F 2 Signal Descriptions c i nee agi eet F 3 DR Driver amp Receiver tei e e ot e e n LE E Re ATE EUR F 4 Signal Description Sienen 2e Eo LE D ec PH I CERE UT aeuo adc aede F 4 Control ES 5 Signal Descriptions iss dee ute p p texte Redde F 5 Firmware S NY Data iret Boia E PN EH prae Pe CREER MER F 5 Signal escriptiOlis cheeses tte CLR Amd eus Cc NE F 5 DRZ Ghi racteristiCs s ei deep ie ebd Ia Fees d P Pede e PEEL F 5 ee ioo Eh RERO F 6 Environmental 4 teet t tenete te ec e tiia tei niet die sa F 6 DR Signal Description eodd rtt eiie estende et e Re ap Pe F 7 8 7200 tto e e teet e ei e e teret teda F 7 DRBJI O Chanrnels 42049 cerise teri e oe epa ern ope tuo de nye F 10 ier leu D F 10 Appendix G 1 DRS Driver Recelver 222220202222 0222 40 G 1 sided dated teat d G 1 Front Panel Connectors
42. driver disable channel tests DRS sync check and error reporting LBUS Inter module Synchronization Interrupts An assortment from the Data Sequencers and the Driver Receiver boards see Configuring the Interrupts Sequencer Events and Driver Receiver Events in Chapter 5 Power Requirements Table 7 1 Power Requirements DB only Voltage Peak Current Dynamic Current 5V 2 9A 30 mA 5 2V 370 mA 20 mA 2V 40 mA 10 mA Specifications 7 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Voltage Peak Current Dynamic Current 412V 0 0 12V 0 0 24V 0 0 24V 0 0 Environmental Temperature Operating 0 C to 45 C Storage 40 C to 70 C Humidity non condensing 0 C to 10 C Not controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 596 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR3e 27 4 1 6 8 9 mmH 0 Typ 18 9 1 5 4 5 mmH 0 VXI Current Requirements DB only V 24 412 45 2 52 Ipeak A 0 0 29 0 04 0 37 Idyn A 0 0 03 0 01 0 02 VXI Current Requirements With 2 DR3s installed V 24 412 5 2 5 2 Ipeak 0 02 0 03 9 5 0 26 5 4 Idyn A 0 01 0 01 0 53 0 01 0 04 Front Panel PWR Current Requirements channels unloaded per DR3 V 3 8 max 2 9 A typ 21 5 V V 4 3 max 3 4 A
43. e eue pereo v Debe e n rede n e 5 61 Active Load te ceret ete cope ten cot abe odo tele eto uda cot ts 5 61 Ghaninel Gonhect a enit eet ro uri diua e ehe a e ret ER gane 5 63 Hybrid Connect nt itii Heiden Ed ee P HE Me eee eet 5 63 Comparator Delay aee t S ceti iaa de edi pact exe ede eg oae ae EE 5 63 itte ted etatem ten ESAE 5 64 Configure UR14 Channel nene 5 64 Compare Input M oit entr teer t tete t e te iae s 5 65 OG Detect A o o ae Ee Tos Fan Licet Ha 5 65 EE 5 65 Configuring the AUX Channels seen ener nnn nne 5 65 Configuring the Signals 5 68 States EE 5 69 SOUCO e deed e vae Exe doe a e P dudo xe ed dp ea eed 5 69 Astronics Test Systems V Model T940 User Manual Publication No 980938 Rev K INpUt 5 70 Gonnect Stale n cu a nh ba 5 71 Properties Programmable Logic esee ennemis 5 71 ECL Mode ECL Differential or Bipolar 5 71 Logic Mode LVTTL Bipolar ECL Logic 5 71 Gonfiguring the Interrupts lea dee Re eene eg ca 5 72 Sone LSA ck e ceri secca cx suco d
44. f ails D ND eno ND GND GND eno UR14 Driver Receiver Board 1 30 Connector Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Signal CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 NC NC NC AUX4 B AUX3 B AUX2 B AUX1 B NC NC NC NC AUX8 B AUX7 B AUX6 B AUX5 B GND Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 14 J3B Connector Pinout by Pin Number Connector Pin Signal Signal 1 GND CH24 3 GND CH23 5 GND CH22 7 GND CH21 9 GND CH20 11 GND CH19 13 GND CH18 15 GND CH17 17 GND CH16 19 GND CH15 21 GND CH14 23 GND CH13 25 GND CH12 27 GND CH11 29 GND CH10 31 GND CH9 33 GND CH8 35 GND CH7 37 GND CH6 39 GND CH5 4 GND CH4 13 GND CH3 45 GND CH2 47 GND CH1 49 GND GND Astronics Test Systems UR14 Driver Receiver Board 1 31 Model T940 User Manual Publication No 980938 Rev K Table 16 J3B Connector Pinout by Pin Number NC NC e e Nc NC NC NC NC NC NG AUX9 B AUX10 B AUX11 B UR14 Driver Receiver Board 1 32 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Connector J9 Connectors Signal AUX11 A AUX10 A AUX9 A VEXT VEXT The J9 connectors are currently used for calibration and for acces
45. reatu di t ar iei rises 5 39 Error Gount Basis 2 uae dre OR ee p 5 39 Error Address Basi eoi ipee te ee a M dinates eed anit ERE E 5 40 Biologie 5 40 Output to Input Disable 3 idet de cette AAR Aaa btts 5 41 Pass Fall Basis rte nei d a n itu e ERA din 5 41 Pass Valid Mode teca E E D T E MT Eqs 5 42 eiae TE 5 43 Channel and Global 5 43 Over Current WindOw ssssssssssesseeeeee eene entente nrt nennen nnns snnt nnns 5 43 ertet etie o inui np Miu 5 44 iom qr LEM 5 45 ERE 5 45 Orc C 5 46 Probe P It Ht iE PEE RE Et E 5 46 GRC GaptUre x iiie i giebt e ca P UE c P MESE ied n 5 46 Probe Button ER x XE 5 47 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Probe Button Level ipee beet ie bee rre er eds 5 47 Probe Input Connected het hp tee he ed 5 47 Probe Input Compare High and LOW sse 5 47 5 48 Probe Gal ae 5 48 Probe Output Connect tu dedere dig
46. 4 202 0 0 2 4 gt oue P REC ERR oda 2 5 Mode Selection i 3 tide oii BH 2 5 Bus Request Selection Let bete Ptr Paredes 2 6 ee eet Lo ebd t en cete di 3 3 Mating Connector Part 3 3 Cable Assembly Part 0 2 3 3 Power Converter Type 1 and Type Ranges sse 4 3 Power Converter Type 004 0004 00000 4 3 File Menu 4 42444 nnne nennt inneren 5 5 Config Menu 0 enne entente nsns stre 5 6 Edit Menu 4 5 7 Execute Menu Descriptions 4440 8 5 7 Instrument Menu 5 8 Help Menu Descriptions Ee vere EE ee 5 9 Inter Module 4044 4 ennt nennen nnne 5 11 Inter Module Mode Settings
47. Probe Publication No 980938 Rev K The Probe I O Block Diagram Figure 1 6 illustrates the configuration and control of the External Probe Support Signals on the UR14 The external probe connection is described in more detail in a subsequent section lt is useful to note that AUX1 A AUX2 A and AUX4 A are general purpose until they are assigned to the external probe AUX EN1A AUX DATA1A AUX RH1A AUX RL1A AUX EN2A AUX DATA2A CONTROL VO CONTROL ALL RELAYS AUX EN4A AUX DATA4A Riso AUX RH4A lt 74LVT125 T940 UR14 330 DUT GND b PROBE OUT PROBE_IN AUX1 A GNDREF PROBE CAL AUX2 A PROBE INPUT CALIBRATION PBUT PROBE DETECT PROBE COMP m3 OBE CO AUX4 A Figure 6 Probe Block Diagram Signal Descriptions Figure 1 6 AUX EN1A Channel Data Enable from the Data Sequencer to the AUX1 A output driver AUX1 A is the PROBE IN signal on the UR14 and is input only AUX DATA1A Channel Data output from the Data Sequencer to the AUX1 A output driver AUX1 A is the PROBE IN signal on the UR14 and is input only AUX RH1A Channel Response High input to the Data Sequencer from the AUX1 A PROBE IN input receiver UR14 Driver Receiver Board 1 8 Astronics Test Systems Publication No 980938 Rev K AUX RL1A AUX EN2A AUX DATA2A AUX RH2A CONTROL AUX EN4A AUX DATA4 A AUX RH4A DUT_GND PROBE OUT PROBE I
48. Publication No 980938 Rev K AUX RH 9 11 B AUX RH12B MC100ELT24 MC100ELT25 AUX DATA 9 11 B M AUX EN 9 11 B NC 24 00 IC100ELT o oVbb p NC LA AUXI9 11 B 5 2N MC100ELT24 MC100ELT25 AUX DATA12B pe MC100ELT24 AUX EN12B gt 500 CONTROL No external connection Figure 1 5 Auxiliary AUX 9 12 SE DIFF ECL I O For these Auxiliary signals pin assignment can be either SE ECL or Differential ECL Signal Descriptions Figure H 5 AUX RH 9 11 B Auxiliary Response Inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 1 1 BAuxiliary Data outputs from the Data Sequencer to the AUX EN 9 11 B AUX RH12B AUX DATA12B AUX EN12B CONTROL AUX 9 11 B AUX 9 11 B Astronics Test Systems positive side ECL output buffers Auxiliary Data outputs from the Data Sequencer to the negative side ECL output buffers Auxiliary Response Input to the Data Sequencer from the AUX12 B ECL input buffers Auxiliary Data output from the Data Sequencer to the positive side AUX12 B ECL output buffers Auxiliary Data outputs from the Data Sequencer to the negative side AUX12 B ECL output buffers Control Logic signals to control isolation termination and configuration relays Front Panel I O for the positive side of the ECL buffers Front Panel I O for the minus side of the ECL buffers UR14 Driver Receiver Board 1 7 Model T940 User Manual
49. This numeric control sets the first channel to be calibrated The valid range is from 1 CH1 to 36 AUXA This setting is used for testing and should always be set to 1 Meas Delay This numeric control sets the delay in seconds between changing a channel level and measuring the channel voltage The valid range is from 0 010 to 36 This setting is used for testing and should always be set to 0 100 Astronics Test Systems Soft Front Panel Operation 5 161 Model T940 User Manual Publication No 980938 Rev K End Channel This numeric control sets the number of channels to be calibrated starting with the Start Chan setting The valid range is from 1 to 36 This setting is used for testing and should always be set to 36 Run This command button executes the selected calibrate function The SFP will prompt the operator to confirm the action and then apply power to the Driver Receiver board BS Calibrate Run Selected Calibrate Procedure o Figure 5 91 Confirm Calibrate Panel Note Pin electronic calibration data is stored for each voltage mode 15 V to 17 V and 7 V to 24 V Calibration should be performed with the power converter setting that will be used for testing for each voltage mode Figure 5 92 Calibrate Warm up Panel The selected calibration procedures will begin when the temperature reaches 80 C or the Continue command button is pressed The unit should be calibrated at its normal application temp
50. 23 CH11 24 CH12 25 CH12 DR2 Driver Receiver Board C 8 Pin No Signal 51 SIG_GND 52 CH17 53 CH17 54 CH18 55 CH18 56 CH19 57 CH19 58 CH20 59 CH20 60 CH21 61 CH21 62 CH22 63 CH22 64 CH23 65 CH23 66 CH24 67 CH24 68 CH25 69 CH25 70 CH26 71 CH26 72 CH27 73 CH27 74 CH28 75 CH28 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal 26 CH13 27 CH13 28 CH14 29 CH14 30 CH15 31 CH15 32 CH16 33 16 34 AUX1 A 35 AUX1 A 36 AUX2 A 37 AUX2 A 38 AUX3 A 39 AUX3 A 40 AUX4 A 41 AUX4 A 42 AUX5 A 43 SIG_GND 44 AUX6 A 45 SIG_GND 46 PBUT_A 47 PMODE_A 48 SIG_GND 49 NU 50 NU Astronics Test Systems Pin No Signal 76 CH29 77 CH29 78 CH30 79 CH30 80 CH31 81 CH31 82 CH32 83 CH32 84 AUX7 A 85 SIG_GND 86 AUX8 A 87 SIG_GND 88 AUX9 A 89 AUX9 A 90 AUX10 A 91 AUX10 A 92 AUX11 A 93 AUX11 A 94 AUX12 A 95 AUX12 A 96 BCLK A 97 SIG GND 98 NU 99 SIG GND 100 NU DR2 Driver Receiver Board C 9 Model T940 User Manual Publication No 980938 Rev K DRB 1 0 Channels J201 Table C 5 DR2 DRB Channels J201 Name Pin No Description CH33 to Various Bi directiona
51. 23 SIG GND 73 SIG GND 24 CH12 74 CH28 25 SIG GND 75 SIG GND 26 CH13 76 CH29 27 SIG_GND 77 SIG GND 28 CH14 78 CH30 29 SIG GND 79 SIG GND 30 CH15 80 CH31 31 SIG_GND 81 SIG_GND 32 CH16 82 CH32 33 SIG_GND 83 SIG_GND 34 AUX1A 84 AUX7 A 35 SIG_GND 85 SIG_GND 36 AUX2A 86 AUX8 A 37 SIG_GND 87 SIG_GND 38 AUX3 A 88 AUX9 A 39 SIG_GND 89 AUX9 A 40 AUX4A 90 AUX10 A DR3e Driver Receiver Board D 14 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal Pin No Signal 41 SIG GND 91 AUX10 A 42 AUX5 A 92 AUX11 A 43 SIG_GND 93 AUX11 A 44 AUX6 A 94 AUX12 A 45 SIG_GND 95 AUX12 A 46 PBUT_A 96 BCLK A 47 PMODE_A 97 SIG_GND 48 SIG_GND 98 EXTFORCE A 49 GNDREF A 99 SIG_GND 50 MONITOR A 100 DUT_GNDA DRB 1 0 Channels J201 Table D 8 DR3e DRB I O Channels J201 Name Pin No Description CH33 CH64 Various Bi directional High speed channels DUT GND B 100 Input DUT UUT ground reference All of the Pin Electronics devices have a UUT ground reference input that can be selected to be this signal or signal ground SIG GND Various Signal Ground reference AUX1 B 34 Bi directional General Purpose pin Also used as the probe input data channel AUX2 B 36 Bi directional General Purpose pin AUXS B 38 Bi directional General Purpose p
52. 32 characters per line 34 if flag and probe data are included Each character is one of the pattern codes listed in Table 5 44 The following example lists two patterns aZOOORRRRRRRRRRRRRRRRRRRRRRRRRRRRm bCRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRn The flag code will be the first character followed by channel 1 through channel 32 and ending with probe expect In this example pattern one has e Both flags set a e Channel 1 disabled Z e Channel 2 through channel 4 driven low 0 e Channel 5 through channel 32 repeating the previous state R e Probe expect low glitch m Pattern two has BERREN flag set b e Channel 1 enabling the CRC C e Channel 2 through channel 32 repeating the previous state R e Probe expect low middle n Editing Waveforms Up to four waveforms can be defined and output during a pattern for generating UUT handshake or clock stimulus The first four waveforms are enabled per sequence step and they replace certain Phase Window signals as mapped below e Waveform 1 Mapped to Phase 4 e Waveform 2 Mapped to Window 4 e Waveform 3 Mapped to Phase 3 e Waveform 4 Mapped to Window 3 Waveforms 1 4 can be programmed to generate complex waveforms with as many transitions that can fit in the pattern period The last two waveforms Waveform 5 and Waveform 6 are not mapped to any of the phase or window signals but are limited to one or two pulses
53. 51 1 Ohm to 2 V AUX10 A 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 A 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 A 93 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 A 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 A 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT A 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output BCLK A 96 Output Reserved Table F 4 DR7 Pinout by Pin Number DRA Pin No Signal 1 SIG GND 2 CH1 3 CH1 4 2 5 2 6 CH3 7 CH3 8 CH4 9 CH4 10 CH5 11 CH5 12 CH6 13 CH6 14 CH7 15 CH7 16 CH8 17 CH8 18 CH9 19 CH9 20 CH10 21 CH10 22 CH11 23 CH11 24 CH12 25 CH12 26 CH13 27 CH13 28 CH14 DR7 Driver Receiver Board F 8 Pin No Signal 51 SIG_GND 52 CH17 53 CH17 54 CH18 55 CH18 56 CH19 57 CH19 58 CH20 59 CH20 60 CH21 61 CH21 62 CH22 63 CH22 64 CH23 65 CH23 66 CH24 67 CH24 68 CH25 69 CH25 70 CH26 71 CH26 72 CH27 73 CH27 74 CH28 75 CH28 76 CH29 77 CH29 78 CH30 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual
54. 980938 Rev K 4 Read the value of the selected ADC reference voltage 5V 5V 10 V or 10 V from the DMM and enter it into the software 5 Review the results in the Status window 6 Optional Check the measured voltage in the Value field for each reference 7 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 8 Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted the calibration factors will revert at the next power cycle Status Calibrating SN 12100791 al Calibrating ADC reference Monitor ADC The Monitor ADC calibration calculates the offset and gain of the monitor to ADC path for each channel The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current Monitor ADC calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the Monitor ADC menu item on the Calibrate Function menu Programmable Channel Calibration 6 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 2 Verify that the Monitor ADC calibrate function is now in focus Calibra
55. ARI Application Resource Interface ATLAS Abbreviated Test Language for All Systems AUX Auxiliary Bipolar Sources and sinks current single ended CAD Computer Aided Design CPP Clocks per Pattern CH Channel signal Channel Test Allows any channel of the installed Driver Receiver boards to be used as a test input TEST1 or TEST2 It can also be used with other Channel tests to form a Vector Jump Index It can even be used to start or stop a sequence Close The falling edge of a Window Comparator Compares an input signal with a voltage reference level Coupled Used to describe a DRM sequencer that is included in a DRS chain CMH Commutating Voltage High CML Commutating Voltage Low CVH Compare Voltage High CVL Compare Voltage Low DB Digital Board Astronics Test Systems Terms and Acronyms A 1 Model T940 User Manual Publication No 980938 Rev K Differential A pair of signals representing a state when one is at a high level the other is at a low level DR1 Driver Receiver Board Type 1 32 channel LVTTL I O DR2 Driver Receiver Board Type 2 32 channel LVDS I O DR3E Driver Receiver Board Type 32 channel programmable I O DR4 Driver Receiver Board Type 4 48 channel programmable 1 0 DR7 Driver Receiver Board Type 7 32 channel RS 422 485 I O DR8 Driver Receiver Board 8 32 chan
56. C 596 to 9596 5 RH 30 C to 40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR4s Max tbd lps tod mmH 0 Typ tod Ips 4 5 mmH 0 MTBF ground benign DR4 57 630 hours T940 180 885 hours T940 DR4 43 705 hours EMC Council Directive Emission EN61326 1 2006 Class A Immunity EN61326 1 2006 Table 1 89 336 EEC Designed to Meet Safety Low Voltage Directive BS EN61010 1 2010 73 23 Designed to Meet Fora DRM with 1 the 1263HPf chassis has sufficient airflow for 25 C max inlet air temperature at lt 2000 ft DR4 Driver Receiver Board E 8 Astronics Test Systems Publication No 980938 Rev K DR4 Signal Description J 2 0 0 Figure E 5 200 and J201 Connectors DRA I O Channels J200 Table E 3 DR4 DRA I O Channels J200 Model T940 User Manual Name Pin No Description CH1 CH24 Various Bi directional High speed channels AUX1A 34 Bi directional General Purpose TTL I O pin AUX2A 36 Bi directional General Purpose TTL I O pin AUX3 A 38 Bi directional General Purpose TTL I O pin AUX4A 40 Bi directional General Purpose TTL I O pin AUX5 A 42 Bi directional General Purpose TTL I O pin AUX6 A 44 Bi directional General Purpose TTL I O pin AUX7A 84 Bi directional General Purpose TTL
57. DR8 Driver Receiver Board DR8 Features e Channels 32 single ended TTL Relay Isolation on all and AUX channels e Selectable resistive input load to VCC 5 0 V ground or both e Direct or 50 100 ohm selectable output impedance e Auxiliary channels Four TTL with selectable output impedance and resistive input load Four TTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR8 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR8 Driver Receiver DRA or DRB The DR8 is comprised of four major logic sections as shown in Figure G 1 Auxiliary Driver amp Receiver I O e Channels Driver amp Receiver I O e Control Logic e Firmware amp NV Data Astronics Test Systems DR8 Driver Receiver Board G 1 Model T940 User Manual Publication No 980938 Rev K AUX DATA 5 8 AUX RH 5 8 AUXILIARY AUX DATA 9 12 goad AUX 9 12 RECEIVER 1 0 VO CONTROL AUX DATA 1 4 AUX RL1 DR8 DRIVER CH DATA 1 32 amp EN 1 32 RECEIVER A CONTROL CONTROL CONTROL us ade NV DATA Figure G 1 DR8 Driver Receiver Block Diagram Auxiliary Driver amp Receiver Figure G 2 illustrates the configuration and control of AUX5 8 TTL and AUX9 12 ECL Driver amp Receiver I O DR8 Driver Receiver Board G 2 Astronics Test Systems Publication No 980938 Rev K
58. DSB eror address memory Passed DSB timing set index memory Passed DSA pattem 1 8 memory Passed DSA pattem 9 16 memory Passed DSA pattem 17 24 memory Passed DSA pattem 25 32 memory Passed Figure 5 87 Full RAM Test Results Panel The full RAM test function saves the current memory contents and performs a full RAM test on all the internal memories The full RAM test performs multiple read write cycles to each RAM at every address location The full RAM test utilizes special hardware to test the pattern record and probe memories at speed The relevant VXI plug amp play API function is e iat964 ramTest Power Converter Test The power converter test function is accessed from the Instrument Power Converter Test menu bar selection Soft Front Panel Operation 5 158 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DRM Power Converter Test Res E Power Convert Test Setting mode to 12 to 12 Setting mode to 15 to 5 Setting mode to 10 to 10 Setting mode to 2 to 7 Setting mode to 5 to 15 Setting mode to 0 to 24 Setting mode to 2 to 22 All modes passed Figure 5 88 Power Converter Test Results Panel The power converter test saves the current power converter setting and performs a test on all the power converter modes The power converter test verifies that the positive and negative rails are within 3 of nominal The min max thresholds for each mode are listed in the followi
59. End of Pattern The stop signal causes the current sequence burst to terminate at the end of the next pattern Looping The stop signal causes the next jump to be ignored Sequence execution resumes at the step sequentially following the step with the ignored jump End of Sequence The stop signal causes the current sequence burst to terminate at the end of the sequence of a continuous or looped burst The relevant VXlplug amp play function is e tat964 setStopMode CRC Type This pull down control programs the CRC type for the next burst The selections for this pull down control are Table 5 90 CRC Type Settings Setting Description CRC16 CRCs generated in the next burst will be CRC16 polynomials CRC32 CROs generated in the next burst will be CRC32 polynomials Custom Custom CRC algorithms are only available with sequencer revisions 0 23 and later The relevant VXlplug amp play API function is e tat964 setCRCType Set Sync This command button displays the Set Sync panel so that Sync 1 and Sync 2 signals can be programmed to generate a pulse These two sync outputs can be routed to any of the AUX ECLTRG or TTLTRG Astronics Test Systems Soft Front Panel Operation 5 121 Model T940 User Manual Publication No 980938 Rev K outputs The sync parameters consist of an offset and a length Once the programmed sync event occurs the sync pulse will begin after the offset and last for length Both offset and length
60. Expanded Records data sequentially A separate Record Index Memory stores information that allows the recorded data to be re aligned with the original data Error Address Recording Separate Error Address Record Memory records where errors occurred in the Record Memory Limit 1K errors Record Offset Used to compensate for round trip driver receiver delay and also cabling delay to the UUT Can also be used to allow windows to effectively close at the end of the TOCycle Resolution 1 master clock Range 2 63 master clocks Sequencer Characteristics General Sequencers 2 per Digital Resource Module Channels 32 per sequencer Modes Static Dynamic Sequence Memory Sequence Size 1024 or 4096 Steps Sequence Loop Counters Loop Counters 16 Loop Count can be different each time or continuous Loop counters may be nested Loop counters can be optionally re loaded during a burst Only one can end on a sequence step Loop Count Range 1 64K or continuous Subroutine Characteristics Output one or more Sequence Steps with or without looping Cannot be nested Has a designated Return Step Burst Count Range 1 1M or continuous Jump Types Conditional or unconditional Jumps at the end of a sequence step Vectored 1 of 16 destinations Astronics Test Systems Specifications 7 5 Model T940 User Manual Publication No 980938 Rev Conditi
61. Expect Valid Expect Between Drive Low Expect Low Drive High Expect High Drive Low Expect High Drive High Expect Low so ow 2 t 8 1 R I L H U B 1 Figure 5 47 Pattern Codes The row labeled TEST displays the test code for each pattern There are two test flags per pattern 1 BERREN Burst Error Enable This flag allows the user to designate which patterns will be examined for Burst Error Burst Error counting and the logging of errors in the Error Address Memory 2 CONDEN Condition Enable This flag allows the user to designate which patterns will be considered for PASS FAIL jump tests Soft Front Panel Operation 5 82 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The row labeled PROBE displays the probe expect code for each pattern There are thirty four probe expect codes FE Falling Edge FEG Falling Edge Glitch b FEGH Falling Edge Glitch Middle H High HG High Glitch HM High Middle f HP High Pulse g HGH High Glitch Middle h HPL High Pulse Low i High Pulse Middle j HGFE High Glitch Falling Edge k L Low 1 LG Low Glitch nm Low Middle n LP Low Pulse o LGM Low Glitch Middle p LPH Low Pulse High q LPH Low Pulse Middle r LGRE Low Glitch Rising Edge s Middle MH Middle High u ML Middle Low v Middle Falling
62. Figure 5 29 Configure Channels Panel Selecting the Channels Before the channel parameters or properties can be programmed the channels must be selected There are two methods for selecting the channels Astronics Test Systems Soft Front Panel Operation 5 53 Model T940 User Manual Publication No 980938 Rev K 1 Left click on the desired channel in the channel list control A check mark indicates the channel has been selected Multiple channels can be selected 2 Use the pull down list box to select the desired channels and press the Select command button The choices include Channel Parameters None De selects all channels DRA Selects CH1 through CH32 DRB Selects CH33 through CH64 DRA amp DRB Selects CH1 through CH64 Group 1 Selects group 1 channels DR4 CH1 through CH16 Group 2 Selects group 2 channels DR4 CH17 through CH32 Group 3 Selects group 3 channels DR4 CH33 through CH48 The channel parameters consist of Stimulus Signal Stimulus Signal Stimulus Format Capture Signal Capture Mode Static Mode After any of the channel parameters have been changed the Update command button must be depressed in order for the new channel settings to be programmed This pull down control programs the drive phase timing for the selected channel s stimulus signal The selections for this pull down control are Table 5 55 Stimulus Signal Settings Setting Description
63. G 3 Figure G 3 DR8 Driver amp Receiver I O Block G 4 Figure G 4 J200 and J201 Connectors sssssssssssssssssseeeee nennen enne nente nnns nnne G 7 Figure G 5 Front Panel PWR nennen nnne nennen G 11 Figure H 1 DR9 Front Panel H 2 Figure H 2 DR9 Driver Receiver Block emnes H 3 Figure H 3 Auxiliary Driver amp Receiver I O Block Diagram sse H 4 Figure H 4 DR9 Driver amp Receiver I O Block H 5 Figure H 5 DR9 Control Logic Block Diagram sse enne nennen H 7 Figure H 6 DR9 1 J1B J2A J2B J3A and J3B Signal Connectors H 13 Figure URT Front Panel 1 2 Figure l 2 UR14 Driver Receiver Block eene l 3 Figure l 3 Auxiliary AUX3 A amp AUX 5 12 A LVTTL amp DIFF ECL WO eee 1 4 Figure 1 4 Auxiliary AUX 5 8 LVTTL SE 1 6 Figure 1 5 Auxiliary AUX 9 12 B SE DIFF ECL 7 Figure 1 6 Probe l O Block Diagram orte e Pete re te 1 8 Figure 1 7 Programmable Driver and Receiver l O ssssssssssseeeeeen nennen 1 10 Figure 1 8 Open Collector Channel 1
64. Good 1 level at window 4 open Good 0 level at window 4 open Good 1 level at window 4 close Good 0 level at window 4 close Positive transition at good 1 level Positive transition at good 0 level Negative transition at good 1 level 7 Negative transition at good 0 level The combination of the eight bits allows the following probe states Open 00 Close Open 05 Close Open OA Close Middle Signal remains High Signal remains above Low Signal remains below between RL and RH RH RL Soft Front Panel Operation 5 136 Astronics Test Systems Publication No 980938 Rev K Open 1 4 Middle High Signal starts between RL and RH crosses the RH once and ends above RH Close ow 41 High Middle Signal starts above RH crosses RH once and ends between RL and RH Close Open 54 Middle Glitch High Signal starts between RL and RH crosses the RH three or more times and ends above RH Close Open 76 Rising Edge Glitch Signal starts below RL crosses RL once crosses RH three or more times and ends above RH Close Open A2 Low Glitch Middle Signal starts below RL crosses the RL Close Astronics Test Systems Open 22 Low Middle Signal starts below RL crosses the RL once and ends between RL and RH Close
65. Invert None hf Figure 5 18 Set VXI Triggers DSA Panel The TTLTRG lines are open collector on the VXI backplane The chassis provides a split termination which provides a weak pull up thus there is a slow rising edge recovery time Programming an active high signal on this panel will actually drive the backplane signal low This allows multiple DRMs to actively drive the same trigger line and form a wired OR condition The DRM module receiving the signal knows to invert the incoming signal to re create an active high But non DRM VXI modules which receive triggers from a DRM or send triggers to the DRM will need to know this protocol The ECLTRG lines are more like an open emitter on the VXI backplane The chassis provides 50 ohm termination for these ECLTRG lines which results in a sharp trailing edge In this case programming an active high signal on this panel will drive the backplane signal high This also allows multiple DRMs to actively drive the same trigger line and form a wired OR condition Under certain circumstances it may be desired to form a wired AND or wired OR on the backplane such as when doing channel tests This is discussed further in the T940 VXI Backplane Trigger Bus section of Chapter 8 There is substantially more information in this section regarding the use of the TTLTRG Bus and ECLTRG Bus TTLTRG and ECLTRG Signal This pull down control programs the signal source for the specified VXI trigger The sel
66. Invert This Invert button is used to invert the associated signal The relevant VXlplug amp play function is e tat964 setlLtbTriggers Direction The direction pull down sets the signal direction Table 5 11 Direction Settings Setting Description Ato Signal sourced by sequencer A and sensed by sequencer B BtoA Signal sourced by sequencer B and sensed by sequencer A The relevant VXlplug amp play API function is e tat964 setltbTriggers Group This command button displays the group configuration panel and is only valid for group enabled front end modules like the DR4 Offset 1O Min Max Slew OC Sre OC Sink Zero HV 500 Det 65 65 Zero HV 500 500 50chm Def 65 65 Zeo HV v 500 500 NA Def 65 E Group 1 Group 2 Group 3 OFF OFF OFF Update Group Settings Figure 5 17 Configure Group Panel Group Attributes This table control programs the following group attributes Astronics Test Systems Soft Front Panel Operation 5 15 Model T940 User Manual Publication No 980938 Rev K Offset The group offset specifies the operating voltage window of the group channels The selections for this pull down control are Table 5 12 Group Offset Attribute Settings Setting Description Zero HV 15 5V to 15 5V Pos OV to 31V Neg 31V to OV Verify that the Min and Max settings are within the window before updatin
67. Multi function signal DRA DRA GND 7 Power supply signal return DRA Calibration Table C 8 Calibration Settings Inter module timing deskew Static End of cable deskew Static Astronics Test Systems DR2 Driver Receiver Board C 13 Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank DR2 Driver Receiver Board C 14 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix D DR3e Driver Receiver Board DR3e Features e Channels 32 single ended variable voltage or 16 differential channels e Voltage range 15 V to 24 V with an output swing of up to 24 V Relay Isolation on all and AUX channels e Provides full drive current on all channels simultaneously e Programmable current load with dual commutating voltages Selectable resistive input load 8 choices to a programmed voltage Selectable slew rate 0 25 V ns to 1 3 V ns e 12 50 ohm selectable output impedance e Over current detection e Over voltage detection protection e Auxiliary channels Four variable voltage FourLVTTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR3e Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR3e Driver Receiver DRA or DRB The DR3e is comprised of four major logic sections as shown in Figure D 1 e Auxiliary Driver amp
68. PG PHASE PRB DATA PRBADDR RECADDR RESUME SEQ SEQ CLK SEQ JUMP SET TO SEQ REC SEQ TRIG Functional Description 4 12 Publication No 980938 Rev K Linked Trigger Bus signals connecting DSA to DSB Master Clock Multipurpose signal output Pattern delay timers Pattern timeout timer Pattern address used by the external pattern RAM Sequence trigger used to stop the timing generator for handshaking applications Pattern code contains the input and output instructions Pulse Generator output Four output timing signals The probe expect and probe result data Probe flag address used by the external RAM Record address used by the external record RAM Sequence trigger used to resume a paused timing generator for handshaking applications Sequence Controller signals that can be assigned to the VXI or LTB Probe Button Sequence Flag 1 Sequence Flag 2 Idle Active Sequence Active Sequence Clock Signal that a valid jump event is true Sequence timeout timer Signals from the sequence controller that programs the record control logic Sequence trigger signals consisting of the following Pause Trigger 1 Pause Trigger 1 Resume Pause Trigger 2 Pause Trigger 2 Resume Phase 1 Resume Phase 2 Resume Phase 3 Resume Phase 4 Resume Execute Start Execute Stop Jump 1 Jump 2 Jump 3 Astronics Test Systems Publication No 980938 Rev K SIM START STOP SYNC 1 2 TEST CODE TO CLK VA 0 3 VXI
69. Phase 1 Use phase 1 timing signal to control output driver timing Phase 2 Use phase 2 timing signal to control output driver timing Phase 3 Use phase 3 timing signal to control output driver timing Phase 4 Use phase 4 timing signal to control output driver timing Soft Front Panel Operation 5 54 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API function is e iat964 setChannelParameters Stimulus Format This pull down control programs the stimulus data formatting for the selected channel s The selections for this pull down control are Table 5 56 Stimulus Format Settings Setting Stimulus Format Description Non Return Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory Phase Return No action Return Off Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory Phase Return Output driver disables Return Zero Return One Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory Phase Return Output driver goes to low level Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory Phase Return Output driver goes to high level Return Comp Phase Assert Output driver goes t
70. Programmable AUX I O Min Max Levels Front Panel The following table lists the min and max levels based on the power converter type 1 or 3 setting Table 5 Programmable AUX Min Max Levels Power Converter 1 or 3 Level Power Converter Setting Units 12to 12 15to 5 10to0 10 5to 7 5to 15 00 24 2 to 22 DVH max 12 5 10 7 15 24 22 V DVH min 10 13 5 8 5 4 4 1 0 5 V DVL max 8 5 2 8 5 4 5 11 6 21 18 8 V DVL min 11 6 15 10 5 5 0 2 V CVH max 9 2 6 9 5 12 2 21 8 19 4 V CVH min 12 15 10 5 5 0 2 V CVL max 9 2 6 9 5 12 2 21 8 19 4 V CVL min 12 15 10 5 5 0 2 V CMH max 9 2 6 9 5 12 2 21 8 19 4 V CMH min 12 15 10 5 5 0 2 V CML max 9 2 6 9 5 12 2 21 8 19 4 V CML min 12 15 10 5 5 0 2 V Astronics Test Systems UR14 Driver Receiver Board 1 23 Model T940 User Manual Publication No 980938 Rev K Table 6 ADC IN Characteristics PROBE SUPPORT Description Characteristics 10 V to 20 V 10 mV 0 6 Input impedance gt 1 Table 7 Probe Support Description Characteristics PROBE COMP AUX4 PROBE MODE PBUT BCLK LVTTL output used to control compensation mode LVTTL dedicated external probe module support PROBE IN AUX1 A See Pin Electronic AUX Channels entry above or External Probe Module entry below PROBE CAL AUX2 A PROBE OUT
71. Receiver channels RH Response High input signals to the Data Sequencer from the programmable input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the programmable input receivers 0 good 0 Astronics Test Systems DR9 Driver Receiver Board H 5 Model T940 User Manual V V EXTSENSE DUT_GND CONTROL CH 1 24 ACH 1 24 MONITOR GND REF EXTFORCE OVERVOLT TEMPMON Control Logic Publication No 980938 Rev K 1 good 1 Bias Power required for operation of the Pin Electronics devices Pin electronics signal used for calibration This signal comes from the UUT and can be used to offset the reference levels up to 3V Excursions of DUT GND beyond 390 mV with respect to signal ground yield GND FAULT signal Control Logic signals to control isolation relays termination pin electronics and temperature thresholds UUT Bi directional programmable channels from the DR9 Drivers and Receivers These provide a means to connect to the DR9 DIGITAL CHANNELS to ANALOG TEST resources The DIGITAL CHANNEL isolation relay is opened before the ANALOG CHANNEL relay is closed to avoid damage to the Pin Electronics Break Before Make This is an analog output signal from the Pin Electronics devices which can be used to monitor DAC levels even the Channel I O levels This signal is used with the internal ADC but a buffered version also comes out the Front Pan
72. any data channel They can be any arbitrary or repeating waveform There are up to 16 waveform tables Output resolution step size is 1 ns with the 500 MHz master clock The width high or low should not be too narrow with respect to the driver rise fall time capabilities of the Channel being used to output it Stimulus Capture Characteristics Testing Modes Dynamic Static Dynamic Mode channel Output Timing Sources per Static selection of phase 1 4 Input Timing Sources per channel Static selection of window 1 4 Data Output Formats per channel Force lo hi tri state Format NR RT RO R1 RC Complement Surround Output the Phase or its complement used to output waveforms on channels Capture Modes per channel Mask Opening edge of window Closing edge of window Window input data must match expect for the entire duration of the window Pattern Memory Pattern Stimulus Expect Data Size 256 Output H L Tristate Expect Good 1 Good 0 OK between or mask Keep last Toggle last Accumulate a CRC16 based on a Good 1 only Astronics Test Systems Specifications 7 3 Model T940 User Manual Publication No 980938 Rev K Static Mode Utilizes a Single Word Sequence Step Delay Range 1 ns to 65 us master clock 500 MHz Delay Range 100 ns to 6 5 ms master clock 5 MHz Resolution 1 ns for a 500 MHz master clock
73. are specified in pattern clocks The sync pulse will not extend past the end of the sequence In the Step event the sync pulse will not extend beyond the specified step VXIO 2 INSTR Set Sync DSA Figure 5 64 Set Sync Panel Sync Number This control selects which sync pulse signal to program either Sync 1 or Sync 2 Event and Step This pull down control programs the sync event The sync pulse event can be set to either the start of a sequence or a specific step The selections for this pull down control are Table 5 91 Finish Mode Settings Setting Description Start The sync pulse begins from the start of the sequence Step The sync pulse begins from the specified step The relevant VXlplug amp play function is e tat964 setSyncEvent Offset This control sets the offset from the sync event before the sync pulse starts The offset can be set from 0 to 1048575 patterns The relevant VXIplug amp play API function is e tat964 setSyncParameters Soft Front Panel Operation 5 122 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Length This control sets the length for the sync pulse from 0 no pulse to 4095 patterns The relevant VXIplug amp play API function is e tat964 setSyncParameters Execute Panel Command Buttons There are ten command buttons that control DRM sequence deskew and pulse generator execution Execute Idle If the Sta
74. e Channels 24 single ended variable voltage or 12 differential channels e Voltage range 15 V to 24 V with an output swing of up to 24 V Relay Isolation on all I O channels 24 Analog connection relays one per I O channel e Provides full drive current on all channels simultaneously e Programmable current load with dual commutating voltages Selectable resistive input load 8 choices to a programmed voltage Selectable slew rate 0 25 V ns to 1 5 V ns e 12 50 ohm selectable output impedance e Over current detection e Over voltage detection e Auxiliary channels Four LVTTL no relay isolation Front Panel Connectors The front panel of the DR9 Driver Receiver board is shown in Figure H 1 Note The orientations of Pin 1 in J1A and J1B are different than the orientations of the other connectors Note J9A and J9B are auxiliary channel connectors used for calibration purposes and for access to LVTTL AUX lines for test purposes or to access them for their functionality Astronics Test Systems DR9 Driver Receiver Board H 1 Model T940 User Manual Publication No 980938 Rev K T940 DR9 DR9 J3B J2B J2A Figure H 1 DR9 Front Panel Connectors DR9 Driver Receiver Board H 2 Astronics Test Systems Publication No 980938 Rev K Model T94
75. hold Astronics Test Systems its officers employees subsidiaries affiliates and distributors harmless against all claims arising out of a claim for personal injury or death associated with such unintended use FOR YOUR SAFETY Before undertaking any troubleshooting maintenance or exploratory procedure read carefully the WARNINGS and CAUTION notices This equipment contains voltage hazardous CAUTION to human life and safety and is capable of RISK OF ELECTRICAL SHOCK b inflicti ini DONOUGEEN inflicting personal injury If this instrument is to be powered from the AC line mains through an autotransformer ensure the common connector is connected to the neutral earth pole of the power supply Before operating the unit ensure the conductor green wire is connected to the ground earth conductor of the power outlet Do not use a two conductor extension cord or a three prong two prong adapter This will defeat the protective feature of the third conductor in the power cord Maintenance and calibration procedures sometimes call for operation of the unit Q with power applied and protective covers removed Read the procedures and heed warnings to avoid live circuit points SENSITIVE ELECTRONIC DEVICES AR Before operating this instrument 1 Ensure the proper fuse is in place for the power source to operate 2 Ensure all other devices connected to or in proximity to this instrument are properly grounded
76. if installed otherwise on DRA The module should settle on a temperature if the test is long enough to establish equilibrium The highest of these temperatures should be used as the calibration temperature for best accuracy in similar applications Calibration Procedures Use the following procedures to calibrate the T940 Digital Resource module Calibration is done with the covers closed and the T940 module installed in a VXI chassis The calibration procedure requires that the T940 Soft Front Panel utility program be installed and interfaced to the instrument The VISA library is required Calibration is performed from the Calibration Panel in the T940 Soft Front Panel To invoke this panel access the Calibrate menu item from the Instrument menu as shown in Figure 6 1 ES T9XX DRM File Config Edit Execute Instrument Help Self Test Astron Full RAM Test TESTS Power Converter Test Talo Update Flash Slot 4 40 VXI0 2 INSTR DEN ER E Active Voltage Monitor amice jas Chip Temperature DRA Assembly Revision A Temp Monitor DRB Power Converter Rev B 003 Chassis Type VXI 3 0 Voltage Monitor DRB Module Interconnect Seconda Chip Temperature DRB Digital Board Utility Reference Monitor Driver Receiver B Figure 6 1 Invoke the Calibrate DRM Panel from the SFP In addition be sure to select the Voltage Range mode which is required by the application as there are 7 ranges to choo
77. to align the timing skew between modules The selections for this pull down control are Table 5 14 Delay Signal Settings Setting Description Phase1 4 Phase timing signals Window 1 4 Window timing signals SEQ CLK Sequence Clock SEQ CLK D Delayed Sequence Clock TO CLK Pattern Clock Jump Jump signal The relevant VXlplug amp play API function is e tat964 setLocalBusDelay Delay This control is used to specify the delay value for the signal specified by the Delay Signal control The valid delay range is from 0 to 63 and the delay is 0 15 ns step The relevant VXIplug amp play API function is e tat964 setLocalBusDelay Note Once alignment for an Independent Linked or DRS configuration is performed these delays should not be changed VXI Triggers This command button displays the Set VXI Triggers panel so the TTLTRG and ECLTRG signals can be programmed for the selected sequencer The panel contains a pull down control and Invert button for each TTLTRG ECLTRG signal Soft Front Panel Operation 5 18 Astronics Test Systems Publication No 980938 Rev K TTLTRG2 Signal Invert TTLTRG4 Signal Invert None vi L TILTRG6 Signal Invert None zi L ECLTRGO Signal Invert 1 Model 7940 User Manual TTLTRG1 Signal Invert None TTLTRG3 Signal Invert None Ci TTLTRG5 Signal Invert None bud TTLTRG7 Signal Invert None ka ECLTRG1 Signal
78. 09 10 11 12 13 14 15 16 CH17 18 19 20 21 22 23 24 25 26 CH27 28 29 30 CH31 32 AUX1A AUX2A AUX3A AUX4A D1 Local D2 Local D3 Local DSA V4 DSB V4 DB Local S s amp 5 88 ETE Figure 5 99 DR3e Monitor Temperature Panel Astronics Test Systems Soft Front Panel Operation 5 167 Model T940 User Manual Publication No 980938 Rev K Figure 5 101 UR14 Monitor Temperature Panel Soft Front Panel Operation 5 168 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API functions are e tat964 queryTemperature e tat964 setTemperatureAlarm Voltage Monitor Panel This panel is available with the following Driver Receiver boards DR3e DR9 UR14 DR4 DR3E DR9 and UR14 Voltage Monitor Panel and Controls z ES VXI0 2 INSTR DRA Voltage V Voltage 2000 000 2000 33 00 33 00 pocesesecoccesesecossesososossosee 33 00 000 mum N 15 59 V Voltage 20 00 Channel 20 00 Front Panel DUT GND 0 009 Monitor Voltage Figure 5 102 DR3E DR9 and UR14 Voltage Monitoring Panel V Voltage This control displays the fused V bias voltage The relevant VXlplug amp play API functions are e tat964 queryAdc e tat964 queryAdcAverage Astronics Test Systems Soft Front
79. 1 Selects voltage mode 1 For any Power Converter range except for DR3e DR9 UR14 7 V to 24 V the 12V to 12V 15V to 5V and the 10 to 10V ranges on Type 1 and 3 Power Converters and except for the 15V to 2V and 10V to 9V ranges on the 4 Power Converter Refer to specific Driver Receiver board specifications for voltage range levels Astronics Test Systems Soft Front Panel Operation 5 21 Model T940 User Manual Publication No 980938 Rev K The relevant VXlplug amp play API function is e tat964 setVoltageRangeMode Note This function is inoperable for the DR1 DR2 DR4 DR7 and DR8 MFSIG Source This pull down control programs the power connector MFSIG signal function The DR3e Driver Receiver boards have an optional front panel power connector that is used to provide the rail voltages to the Pin Electronics devices In addition a signal is provided that can be programmed to generate a shutdown level to the external voltage source or to light an LED The selections for this pull down control are Table 5 17 MFSIG Settings Setting Description Shutdown High Signal goes high on voltage or temperature fault condition Shutdown Low Signal goes low on voltage or temperature fault condition Disabled Signal is not driven MPSIG Signal is assigned to the sequencer MPSIG signal The relevant VXlplug amp play API function is e tat964 setPowerSettings
80. 1 Ohm series AUX7A 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 A 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series Astronics Test Systems DR2 Driver Receiver Board C 7 Model T940 User Manual Publication No 980938 Rev K Name Pin No Description AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 A 90 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 A 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 A 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 A 93 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 A 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 A 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output BCLK A 96 Output Reserved Table C 4 DR2 Pinout by Pin Number DRA Pin No Signal 1 SIG GND 2 CH1 3 CH1 4 2 5 2 6 CH3 7 CH3 8 CH4 9 CH4 10 CH5 11 CH5 12 CH6 13 CH6 14 CH7 15 CH7 16 CH8 17 CH8 18 CH9 19 CH9 20 CH10 21 CH10 22 CH11
81. 114 x 305 mm EMC Council Directive Emission EN61326 1 2006 Class A 89 336 EEC Immunity EN61326 1 2006 Table 1 Designed to Meet Testing in Progress Safety Low Voltage Directive 73 23 EEC BS EN61010 1 2010 Designed to Meet Testing in Progress DR2 Driver Receiver Board C 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DR2 Signal Description J 2 D o DRB Figure C 4 J200 and J201 Connectors DRA I O Channels J200 Table C 3 DR2 DRA I O Channels J200 Name Pin No Description 1 to Various Bi directional LVDS Positive High speed channels CH32 CH1 to Various Bi directional LVDS Negative High speed channels CH32 SIG_GND Various Signal Ground reference AUX1 A 34 Bi directional General Purpose LVDS Positive pin AUX1 A 35 Bi directional General Purpose LVDS Negative I O pin AUX2 A 36 Bi directional General Purpose LVDS Positive I O pin AUX2 A 37 Bi directional General Purpose LVDS Negative I O pin AUX3 A 38 Bi directional General Purpose LVDS Positive I O pin AUX3 A 39 Bi directional General Purpose LVDS Negative I O pin AUX4 A 40 Bi directional General Purpose LVDS Positive I O pin AUX4 A 41 Bi directional General Purpose LVDS Negative I O pin AUX5 A 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 A 44 Bi directional General Purpose LVTTL I O pin 51
82. 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual File Config Edit Execute Instrument Help AsTRONICS company Talon Instruments T964 T940 0440 DRM Module Configuration Active Instrument Driver Revision 5 59 Serial Number 12030275 Assembly Revision A Power Converter Rev A Chassis Module Data Type Serial Number 14030383 Assembly Revision K Fimware Revision 5 9 Elapsed Time 0009 15 34 13 Calibration Revision 0 42 Calibration Revision 5 1 Calibration Date 10 14 2015 Calibration Date 03 23 2015 4 Ji File Config Edit Execute Instrument Help AsTRONICS DRM Module Configuration Active Instrument Driver Revision 5 59 Serial Number 13103717 Assembly Revision 1 0 Power Converter Rev B 003 Chassis Type VXI 3 0 Module Interconnect Not Installed Digital Board Type T940 Type UR14 Serial Number nolog Serial Number Assembly Revision Assembly Revision VXI FW Revision 5 2 Firmware Revision 1 4 Sequencer FW Revision 0 22 Elapsed Time 0010 11 48 59 Calibration Revision 0 42 Calibration Date 10 14 2015 4 Figure 5 4 Main Panel UR14 Astronics Test Systems Soft Front Panel Operation 5 3 Model T940 User Manual Publication No 980938 Rev K The following sections describe the main panel controls and indicators Company Logo Pressing this control displays the information panel Address As
83. 42 Trigger Bus descriptlon ide e shasta ea E rou e RR ew 8 42 Trigger Bus 8 42 ioco ed a edenda E teat f pA ed ect ede ERO Renate 8 43 Normal Operation Example cesis rans aeia aes aatra iaa ea snnt en 8 43 xii Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Advanced Operation Examples sss ennemis 8 43 NOLGE M 8 44 Appendix meme 1 Glossary of Terms and Acronyms A 1 om B 1 DR1 Driver Hecelver Board erento recepere rino tre ere ved eoi oue ce khu B 1 DRA FEeatures iii PHP itp irepl ines B 1 Front Panel Connectors nine n ta d dde n Edd ance B 1 Block Diagrams i meet te e teat atta B 1 Auxiliary Driver amp Receiver Ere etd e EP reb ee DE ege B 2 Signal Descriptions 1 1 Seiden ad neve a kd ceding Gatien qo B 3 DRI Driver amp Receiver N O m ened eddie c eta annee a vant versace feet B 4 Signal BI rerp oliior EU B 4 tee tubes aedi tox eor B 4 SigraliDescriptiOlis s
84. 5 and 7 had a Soft Front Panel Operation 5 102 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Jump Step Gosub to step 10 and step 13 has the Gosub Return flag set then the step number sequence starting from 1 would be 1 2 3 4 5 10 11 12 13 6 7 10 11 12 13 8 9 The selections for this pull down control are Table 5 81 Jump Type Settings Setting Description None Disable the jump logic for this step Normal After executing this step s patterns perform a normal jump if jump condition is true Gosub After executing this step s patterns perform a Gosub jump if the jump condition is true The relevant VXlplug amp play API function is e tat964 setSequenceJump This numeric control programs the Jump Step number This control is only visible if the jump type is set to Normal or Gosub If the jump condition is true then the next step number will be the value specified by the Jump Step instead of the next sequential step number The jump action takes precedence over the Last Step flag The relevant VXlplug amp play API function is e tat964 setSequenceJump Jump Condition This pull down control programs the Jump Type Mode This control is only visible if the jump type is set to Normal or Gosub Jumps can be conditional or unconditional Conditional jumps require a specified condition to be true in order for the jump to be enabled Unconditional jumps are alw
85. 5 items above are used to control the execution of the Sequence Steps Here are some examples e Unconditional Jumps o Select a Jump Always Test Condition o Designate the Jump Sequence Address e Conditional Jumps o Select a Test Condition o Designate the Jump Sequence Address Counted Loops o Seta Loop Count gt 0 this sets the CLOOP bit o Designate a loop counter to use 0 to 15 o Select a Jump Always Test Condition o Designate the Jump Sequence Address Counted Loop with Termination test o Seta Loop Count gt 0 this sets the CLOOP bit o Designate a loop counter to use 0 to 15 o Designate the Jump Sequence Address Astronics Test Systems Advanced Topics 8 35 Model T940 User Manual Publication No 980938 Rev K o Selecta Test Condition when the condition is no longer true execution advances to the next Sequence Step e Unconditional Subroutine Jump o Set SUBRT o Select a Jump Always Test Condition o Designate the Jump Sequence Address First Sequence Step of the Subroutine e Conditional Subroutine Jump o Set SUBRT o Select the Test Condition o Designate the Jump Sequence Address First Sequence Step of the Subroutine Set LSTSEQ on the last Sequence Step of the Primary Sequence Notes and Restrictions Advanced Topics 8 36 Loops can be nested but only one can end on a given Sequence Step Loop Counters can be re used when exhausted un exhausted Loop Counters will continue where they le
86. 50 O Series 002 0 8 V max 2 0 min Input Impedance Program selectable per pin 100 Q pull up to VCC 43 3 V 100 O pull down to ground Ch1 32 Aux1 4 only Skew Channel to Channel lt 3 ns drive and compare Auxiliary I O Channels per I O board LVTTL Aux 1 4 Like the channels with optional pull up and pull down LVTTL Aux 5 8 ECL Aux 9 12 Single ended or Differential AUX I O is bi directional Per channel relay isolation Data Rate max 50 MHz input and output Astronics Test Systems DR1 Driver Receiver Board B 5 Model T940 User Manual Power Requirements Publication No 980938 Rev K Table B 2 DR1 Power Requirements Voltage Peak Current Dynamic Current 5 V 4 3 A 25 mA 5 2 V 25A 1 mA 2 V 608 mA 7 4 mA 12 V 0 0 12V 0 0 24 V 0 0 24V 0 0 Environmental Temperature Operating 0 C to 45 C Storage 40 C to 70 C Humidity non condensing 0 C to 10 C Not controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 596 to 7596 5 RH 40 C to 50 C 5 to 5596 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR1s Max 4 68 los 8 9 mmH 0 Typ 4 60 lps 4 5 mmH 0 Front Panel Current Requirements NA Safety Low Voltage Directive 73 23 MTBF ground benign DR1 257 335 hours T940 180 885 hours T940 DR1 106 220 hours T940 D
87. 7 Programmable Driver and Receiver Signal Descriptions Figure 7 DATA Auxiliary data output signals from the Data Sequencer to the programmable output drivers EN Auxiliary enable output signals from the Data Sequencer to the programmable output drivers RH Response High input signals to the Data Sequencer from the programmable input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the programmable input receivers 0 good 0 1 good 1 V V Bias Power required for operation of the Pin Electronics devices EXTSENSE Pin electronics signal used for calibration UR14 Driver Receiver Board 1 10 Astronics Test Systems Publication No 980938 Rev K DUT GND CONTROL AUX1 4 B MONITOR GND REF EXTFORCE TEMPMON DSB Model T940 User Manual This signal comes from the UUT and can be used to offset the reference levels up to 3 V Excursions of DUT GND beyond 390 mV with respect to signal ground yield GND FAULT signal Control Logic signals to control isolation relays termination pin electronics and temperature thresholds Four programmable signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 This is an analog output signal from the Pin Electronics devices which can be used to monitor DAC levels even the Channel I O levels This signal is used with the internal ADC but a buffered version also comes out the Front
88. AUX EN 5 8 AUX 5 8 74LVC2G125 AUX RH 5 8 MC100ELT24 Model T940 User Manual 74LVC2G125 MC100ELT25 Figure G 2 Auxiliary Driver amp Receiver Block Diagram Signal Descriptions AUX EN 5 8 AUX 5 8 AUX RH 5 8 AUX RH 9 12 AUX DATA 9 12 AUX 9 12 CONTROL AUX 5 8 VBB AUX 9 12 AUX 9 12 Astronics Test Systems Auxiliary Enable outputs from the Data Sequencer to the TTL output buffers Auxiliary Data outputs from the Data Sequencer to the TTL output buffers Auxiliary Response High inputs to the Data Sequencer from the TTL input buffers Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers Signals used to control isolation relays and ECL bipolar differential mode Four TTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 ECL input threshold 1 3V Four negative differential signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 Four bipolar positive differential signals used to input or output test signals See Configuring the AUX Channels DR8 Driver Receiver Board G 3 Model T940 User Manual Publication No 980938 Rev K in Chapter 5 DR8 Driver amp Receiver
89. AUX1 Low Level and Pause 1 Resume was set to AUX1 High Level then the timing would stop when AUX1 is low and continue when AUX1 goes high Phase Resume Triggers If the pattern timing is paused by either the assert or return edge of a phase then this trigger is used to resume the timing Halt Trigger The halt trigger causes the sequencer to halt based on the current halt mode Astronics Test Systems Soft Front Panel Operation 5 31 Model T940 User Manual Publication No 980938 Rev K Execute Start Trigger The execute start trigger causes the selected sequence step to start Selecting a sequence step consists of arming the sequence step In a linked or DRS configuration all of the coupled sequencers need to be armed first Execute Stop Trigger The execute stop trigger causes the sequencer to stop based on the current stop mode Jump Trigger Four sequence jump triggers are available The sequence jump triggers are used for conditional jumping looping A jump loop can be based on the true false state of any of the four sequence jump triggers For example if jump trigger 1 test mode is set to Low Level then a jump if trigger 1 true would occur if the selected jump trigger 1 source is low Trigger This pull down control selects the trigger to program The selections for this pull down control are Table 5 28 Trigger Settings Setting Description Pause Trigg
90. Astronics Test Systems Soft Front Panel Operation 5 143 Model T940 User Manual Publication No 980938 Rev K error was detected Note This pattern address may be up to 5 patterns later than the first detection of a sync error Also the Sync Error Step and Pattern Address is only relevant coupled sequencers The relevant VXlplug amp play function is e tat964 querySequencerSyncError Status These LED indicators display the sequence status bits The following sequencer status bits are defined Table 5 97 Sequence Status Bit Descriptions Bit Name Description 0 PAUSED Sequencer is paused 1 ICLKOK 500 MHz Clock OK 2 IDDCM Input Delay DCM locked 3 ISPEND Internal Stop Pending 4 ESPEND External Stop Pending 5 ISTART Internal Start Pending 6 ESTART External Start Pending 7 HALT Sequencer is Halted 8 STEP Single Step Pending 9 IACT Idle Sequence Active 10 SACT Sequence Active 11 DEN Drivers Enabled 12 EHALT External Halt Pending The following sequencer status bits are defined The relevant VXlplug amp play function is e tat964 querySequencerStatus Driver Receiver Events Panel The Driver Receiver events display is accessed from the Execute DSx View Driver Receiver Events menu bar selection Where x is the sequencer you wish to query Soft Front Panel Operation 5 144 Astronics Test Systems Publication No 980938 Rev K Model T940 User Ma
91. Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 B 90 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 B 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V Astronics Test Systems DR1 Driver Receiver Board B 9 Model T940 User Manual Publication No 980938 Rev K Name Pin No Description AUX11 B 93 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 B 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT B 46 Bi directional Probe Button Input PMODE B 47 Output Probe Support Output BCLK B 96 Output Reserved Table B 6 DR1 Pinout by Pin Number DRB Pin No Signal Pin No Signal 1 SIG GND 51 SIG GND 2 CH33 52 CH49 3 SIG_GND 53 SIG GND 4 CH34 54 CH50 5 SIG GND 55 SIG GND 6 CH35 56 CH51 7 SIG GND 57 SIG GND 8 CH36 58 CH52 9 SIG GND 59 SIG GND 10 CH37 60 CH53 11 SIG GND 61 SIG GND 12 CH38 62 CH54 13 SIG GND 63 SIG GND 14 CH39 64 CH55 15 SIG GND 65 SIG GND 16 40 66 56 17 SIG GND 67 SIG GND 18 CH41 68 CH
92. CRC Sequence Sc kew ess Record Count Pattem Fail Step Fail Sequence Fail Pattem Pass Step Pass Sequence Pass Figure 8 18 Setting the Halt Mode in the Execute DSA Panel There are different types of Halt Modes The first five are typically used for single stepping e Pattern e Step e Sequence e Sync 1 e Sync2 These latter two are actually Sync Pulses set on the Execute Panel by clicking Set Sync The relevant VXlplug amp play and ARI functions are e API tat964_setSyncEvent tat964 setSyncParameters e ARI AssignPtgSyncPulse Each Sync Pulse can be set to start from the beginning of the Sequence or a specified Seq Step and then have an Offset and a Length Astronics Test Systems Advanced Topics 8 25 Model T940 User Manual Publication No 980938 Rev K To use these first five select the desired Halt Mode and then click Halt on this Execute panel PnP tat964 haltSequence ARI currently does not support the Halt command before clicking Execute Each time Halt is subsequently clicked the Halt will re occur on the next Pattern Step etc One can change the Halt Mode between clicks of Halt For example one may initially have a Sync Pulse on some desired pattern and then one could single step one pattern at a time subsequently If the Length of the Sync Pulse is N then single pattern stepping will continue until N is exhausted Note there is a max data rate
93. Control logic is used to route and terminate these signals Data Sequencer A and B Each DB contains two Data Sequencers DSA and DSB Each data sequencer can be run independently or synchronized Data Sequencer A provides the timing memory and control for the DRA board Channels 1 through 32 Data Sequencer B provides the timing memory and control for the DRB board Channels 33 through 64 The Data Sequencer logic consists of the following e Timing Data Phase Assert Phase Return Window Open Window Close e Stimulus Format Code Non Return Return to Zero etc e Pattern Data Output Levels Input Compare CRC Enable e Sequence Data Pattern Period Pattern Order Looping Conditional Testing e Result Data Error Flags Error Count CRC per Channel Record Memory Driver Receiver DR Board Driver Receiver Board A DRA The DRA board contains all the driver receiver logic relays sensors and termination circuitry for channels 1 through 32 Astronics Test Systems Introduction 1 9 Model T940 User Manual Driver Receiver Board B DRB The DRB board contains all the driver receiver logic relays sensors and termination circuitry for channels 33 through 64 Model and Part Number Information Publication No 980938 Rev K Model Description Ordering Part DR1 LVTTL 32 channels 100 source termination 405349 001 LVTTL 32 channels 50 source termination 405349 002 DR2
94. DATA EN RH RL AUX 1 4 AUX 1 4 CH 1 32 CH 1 32 DR7 Driver Receiver Board F 4 Channel and auxiliary data output signals from the Data Sequencer to the RS422 RS485 output drivers Channel and auxiliary enable output signals from the Data Sequencer to the RS422 RS485 output drivers Response High input signals to the Data Sequencer from the RS422 RS485 input receivers 1 good 1 0 good 0 Response Low input signals to the Data Sequencer from the RS422 RS485 input receivers 0 good 0 1 good 1 Four positive differential RS422 RS485 signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 Four negative differential RS422 RS485 signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 These are UUT Bi directional positive differential RS422 RS485 I O channels from the DR7 Drivers and Receivers These are UUT Bi directional negative differential RS422 RS485 I O channels from the DR7 Drivers and Receivers Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Control Logic The control logic contains the registers memory and logic that allow the digital board to interface and configure the hardware Signal Descriptions CONTROL Signals used to control isolation termination NV data and load relays MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digita
95. DR1 Driver Receiver Board B 1 Model T940 User Manual Publication No 980938 Rev K AUX DATA 5 8 AUX RH 5 8 AUXILIARY AUX DATA 9 12 DRIVER amp RECEIVER Vo 1 0 CONTROL AUX DATA 1 4 AUX RL1 DR1 CH DATA 1 32 DRIVER amp CH EN 1 32 RECEIVER Vo RL 1 32 1 0 CONTROL CONTROL CAES NV DATA Figure B 1 DR1 Driver Receiver Block Diagram Auxiliary Driver amp Receiver Figure B 2 illustrates the configuration and control of AUX5 8 LVTTL and AUX9 12 ECL Driver amp Receiver I O DR1 Driver Receiver Board B 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual AUX EN 5 8 AUX DATA 5 8 p 74LVC2G125 74LVC2G125 AUX RH 5 8 MC100ELT24 MC100ELT25 AUX DATA 9 12 MC100ELT24 Figure B 2 Auxiliary Driver amp Receiver I O Block Diagram Signal Descriptions AUX EN 5 8 Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX RH 5 8 Auxiliary Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outpu
96. DRS Linked Use DRS Linked error Qualified Use CONDEN qualified DRS Linked DRS Linked error If the Pass Fail Basis is enabled for DRS or Linked operation then the ERROR signal must be coupled between DRMs Sequencers via the TTL ECL or Linked TRG bus respectively And if used the PASS_ Valid signal must also be coupled between DRMs Sequencers via the TTL ECL or Linked TRG The ECL TRG Bus is recommended for data rates greater than 10 MHz This is discussed in more detail in the Jumping Halting Counting and Logging Errors sections in Astronics Test Systems Soft Front Panel Operation 5 41 Model T940 User Manual Publication No 980938 Rev K Chapter 8 The relevant VXlplug amp play API function is e iat964 setPassFailParameters Pass Valid Mode This pull down control programs the sequencer pass valid mode This control allows the user to define the Pass as a Valid Pass A Valid Pass is one where no channel errors were detected but there must be at least one valid pattern expect code for each pattern in the sequence step If Pass Valid is enabled for a DRS then the Pass Valid signal must be coupled between DRMs via the TTL or ECL TRG bus The ECL TRG Bus is recommended for data rates greater than 10 MHz This is discussed in more detail in the Jumping Halting Counting and Logging Errors section in Chapter 8 The selections for this pull down control are Table 5 42 Pass Valid Mode Settings Se
97. Driver Receiver Board E 1 Model T940 User Manual Publication No 980938 Rev K VD1 PROG POSITIVE REGULATOR 2V TO 34V VOLTAGE TO MUX ADC DATA 9 24 RH RL 9 24 suae FP J200 CHANNELS TO MUX ADC 16 HIGH VOLTAGE BYPASS 9 24 CHANNELS SHUTDOWN 9 24 VD1 PROG NEGATIVE REGULATOR 2V TO 34V VOLTAGE TO MUX ADC VD24 PROG POSITIVE REGULATOR 2V TO 34V ais VOLTAGE TO MUX ADC DATA 1 8 RH AL 1 8 sms gt J200 BYPASS 1 8 SHUTDOWN 1 8 HIGH VOLTAGE CHANNELS DATA 49 56 FP J201 RH RL 49 56 BYPASS 49 56 1 CHANNELS TO MUX ADC SHUTDOWN 49 56 VD2 PROG NEGATIVE REGULATOR VOLTAGE TO MUX ADC PROG POSITIVE REGULATOR 2V TO 34V VOLTAGE TO MUX ADC DATA 33 48 RH RL 33 48 CHB 33 48 FP J201 16 HIGH VOLTAGE CHANNELS BYPASS 33 48 CHANNELS TO MUX ADC SHUTDOWN 33 48 VD3 PROG NEGATIVE REGULATOR VOLTAGE TO MUX ADC I Figure 1 DR4 I O Block Diagram DR4 Driver Receiver Board 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Signal Descriptions DATA Channel data output signals from the Data Sequencer to the programmable output drivers EN Channel enable output signals from the Data Sequencer to the programmable output drivers OC Over Current detect from the programmable Driver and Receiver channels RH RL Response High input signals to the Data Sequencer fr
98. Enable Enable drive fault signal The relevant VXlplug amp play API function is e 964 setDriveFaultState This command button displays the Probe panel so the probe parameters can be programmed The probe module connects to the UR14 J1A connector uc VXIO 2 INSTR Configure DSA Probe 2 00 ns per count Probe Data Disable Y Probe Button None v Figure 5 27 Probe Panel This control initializes resets the probe resources on the UR14 module Note Disable the Probe State when not in use See the Jumping Halting Astronics Test Systems Soft Front Panel Operation 5 45 Model T940 User Manual Publication No 980938 Rev K Offset Probe Data CRC Capture Counting and Logging Errors section of Chapter 8 for a discussion on the impact of the Probe State on data rates The relevant VXlplug amp play API function is e tat964 setProbelnterfaceState The Probe offset allows the user to shift the probe record signals to accommodate system and UUT delay The relevant VXIplug amp play function is e tat964 setProbeConfiguration Note Once the Probe is calibrated for an Independent Linked or DRS configuration this offset should not be changed This sets the probe data memory setting Note Disable the Probe Data when the probe is not in use See the Jumping Halting Counting and Logging Errors section of Chapter 8 for a discussion on the impact of the Probe Data Setting on data rates The sele
99. Four LVTTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 DR9 Driver amp Receiver I O Figure H 4 illustrates the configuration and control of the DR9 Driver amp Receiver DR9 Driver Receiver Board H 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure H 4 Driver amp Receiver I O Block Diagram Note There are two important features associated with the Analog Channel and Digital Channel relay control logic First these relay connections are exclusive if the CH1 connection relay is CLOSED the ACH1 relay cannot be closed Second the control logic is implemented to provide a Break Before Make connection to protect the Pin Electronics from potential damage Analog Channel connections have voltage specifications that are far beyond the ability of the DR9 overvoltage detection and protection circuitry to reliably operate Programming an Analog Channel relay opens the associated Digital Channel relay if it is closed There is a 5 ms latency after making the Analog Channel relay connection to ensure that the Digital Channel relay has had time to open Signal Descriptions DATA Channel and auxiliary data output signals from the Data Sequencer to the programmable output drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the programmable output drivers OC Over Current detect from the programmable Driver and
100. Halt Setup Time to SEQ CLK Out AUX LVTTL to LVTTL 22 ns min Note For all master clock frequencies the master clock stops before a Phase at 0 ns will be asserted External Pause to CLK Cease There are no clocked elements in this path AUX LVTTL to CLK Stop 22 ns In addition to this there is an additional amount of time up to 1 2 the period of the master clock before the master clock appears to stop FE An internal signal External Pause Phase Resume to CLK Resume There are no clocked elements in this path AUX LVTTL to NOT CLK Stop 22 ns To addition to this there is an additional amount of time up to one full period of the master clock before the master clock actually restarts RE External Jump Setup Time to TOCLK In AUX LVTTL to Jump Test AUX LVTTL 20 ns Jump Test setup time to Jump Strobe AUX LVTTL 2 ns Jump Strobe to TOCLK In AUX LVTTL 36 ns 500 MHz master clock Jump Strobe to TOCLK In AUX LVTTL 140 ns 100 MHz master clock X 2n 36 ns x 10n 140 ns Thus 13 master clocks x 10 ns Add to x Linked or VXI Local Bus adjustments Astronics Test Systems DRM Timing Characteristics J 3 Model T940 User Manual Publication No 980938 Rev K External Start Setup Time to TOCLK In For a 10 master clock standby pattern AUX LVTTL to LVTTL 60 ns max 500 MHz master clock AUX LVTTL to LVTTL 180 ns max 100 MHz master clock 2n 60 ns x 10n 180 ns Thus n 15
101. Hz to 250 MHz 4 ns to 4 s Measurement Range Preset Aperture Windows 1 us to 10 s in decade steps Aperture Window Accuracy 0 1 50 ppm Frequency Period Measurement Resolution 24 Digits with a 1 ms Aperture 25 Digits with a 100 ms Aperture 26 Digits with a 10 s Aperture Time Interval Functions Between Inputs 1 amp 2 Positive Negative Pulse Width of Input 1 Time Interval Range 2 ns to 4 29s Time Interval Resolution 1 ns Time Interval accuracy 1 count input comparator threshold uncertainty Time Interval Reference Accuracy Totalize 2 modes 50 ppm Timed with a Preset Aperture Aperture defined by Input 3 Preset Aperture accuracy 50 ppm Max Count 2 32 1 Max Input Data Rate 250 MHz Note CH and AUX input technology may limit the max data rate that can be supported Input Trigger Specifications 7 8 Input 3 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Trigger functions for Manual Freq Period Time Interval amp External Input 3 Totalize mode 1 only Continuous Events provided Indicates when the data is ready to be read may also generate an interrupt Pulse Generator Characteristics Signal Routing System Clock VXI Triggers TTL and ECL Linked Trigger Bus Any Aux channel Counter Input Pulse Resolution 10 ns 20 ns Run Mode Continuous Continuous Start Sing
102. Input Low Level max VOH Voltage Output High Level min Terms and Acronyms A 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual VOL Voltage Output Low Level max VXI VME Extensions for Instrumentation VXI INT VXI Interrupt Signals The backplane interrupt signals WCEM Microsoft Windows CIIL Emulation Module Astronics Test Systems Terms and Acronyms A 5 Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank Terms and Acronyms A 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix B DR1 Driver Receiver Board DR1 Features e Channels 32 single ended LVTTL Relay Isolation on all and AUX channels Selectable resistive input load to VCC 3 3 V ground or both e Direct or 50 ohm selectable output impedance e Auxiliary channels Four LVTTL with selectable output impedance and resistive input load Four LVTTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR1 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR1 Driver Receiver DRA or DRB The DR1 is comprised of four major logic sections as shown in Figure B 1 e Auxiliary Driver amp Receiver I O e DH1 Driver amp Receiver e Control Logic e Firmware amp NV Data Astronics Test Systems
103. J9B ae Figure 6 5 T940 DR9 DR9 or T940 UR14 Connection Diagram Procedure 1 Press the Run button 2 Allow the T940 DRM to warm to its nominal application temperature 3 Enter the resistance readings taken by the DMM Programmable Channel Calibration 6 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 4 Optional Export the calibration to a file for later restore e g File Load DRA Calibration 5 Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted the calibration factors will revert at the next power cycle DVH DVL The DVH DVL calibration calculates the offset and gain of the output driver levels For the DR3E DR9 and UR14 a separate offset and gain is calculated for each slew rate For the DR4 a separate offset and gain is calculated for each group offset The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the DVH DVL menu item on the Calibrate Function menu Astronics Test Systems Programmable Chann
104. LVDS 32 channels 100 source termination 405350 DR3e Variable voltage 15 V to 24 V 32 Channels 408002 DR4 Variable voltage 31 V to 31 V 48 Channels 408558 DR7 RS422 RS485 32 channels 100 source 408242 101 termination DR8 TTL 32 channels 100 source termination 408241 101 TTL 32 channels 50 source termination 408241 102 DR9 Variable voltage 15V to 24V 24 Direct Analog 408254 Test Channels UR14 Utility resource 32 HV Open Collector channels 408290 probe interface auxiliary interface To understand a configured module part number for a T940 DRM use the T940 model number configurator shown in the next figure Introduction 1 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual T940 XXzz YYzz A Talon Instruments T940 Digital Resource Module Configured System Optional Application Code T940 W XXzz YYzz A Required ill a Application Code Power Converter Code A Ln DR9 Front Panel Installed CIB or Funnel DR1 2 3e 4 7 8 Front Panel To create the 2nd 3rd and 4th sections of the part for a configured T940 substitute the W XXzz YYzz and A in the part with the correct CIB Funnel Application and Power Converter Code from the table below Note that the rightmost front panel is representative of the DR1 2 3e 7 8 modules and the leftmost is for the DR9 and is similar in style to the T940 U
105. Levels Comparator Levels Driver Slew Rate Output Impedance Over Current Alarm Levels Programmable Load Channel Connect Hybrid Connect Channel Mode O m Des we dec vs These program the properties of the specific Driver Receiver boards that are installed Not every Driver Receiver board supports all nine elements If a Driver Receiver board does not support a property and you select it a Soft Front Panel Error message box similar to the following appears Click Ignore to clear the error and return to the control panel Soft Front Panel Operation 5 58 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual pO Function configChanDrEvent tat964 setChannelSenseParameters returned the error Installed front end board does not support this function tat964 setChannelSenseParameters Click Ignore to return to the current panel Exit to close the current panel Demo to switch to the demo mode Figure 5 30 Configure Channel Properties Panel Driver Levels The driver levels allow the user to set the Drive High DVH and Drive Low DVL voltage The min max levels are dependent on the installed Driver Receiver board as well as the voltage mode Note The external supply voltages will also need to be adequate for the desired drive levels when using the DR3e with external power option The relevant VXlIplug amp play function is Astronics Test Systems Soft F
106. Linked Sequencers or multiple Sequencers which are part of a DRS Similarly Errors can be logged into the EAM for Independent Sequencers Linked Sequencers or multiple Sequencers which are part of a DRS For both of these circumstances the Errors can be non qualified Errors or Qualified Errors When Non qualified Errors are chosen all of the Pattern Errors in a Sequence Step are counted if the Step Record mode calls for Errors to be counted When Qualified Errors are chosen only those patterns enabled by BERREN Burst Error Enable are counted if the Step Record mode calls for Errors to be counted This BERREN bit is set in the Pattern Memory The Pattern Data can be accessed on either the Edit Sequencer A B Patterns or Sequencer Steps panel The relevant VXlplug amp play and ARI functions are e API tat964_ setPatternTestEnable e ARI LoadPtgStepExpectedPatternBin LoadPtgStepPatternChar Astronics Test Systems Advanced Topics 8 9 Model T940 User Manual Publication No 980938 Rev K Figure 8 7 Setting the Test Bit in the Edit DSA Pattern Set Step Panel In the TEST row for each pattern column a b sets BERREN true whereas an n sets it false Thus in the example above patterns 1 3 5 amp 6 have BERREN set whereas patterns 2 amp 4 do not have BERREN set The Basis for Counting Errors is set on the CONFIG Data Sequencer A B gt Settings Panel The relevant VXIplug amp play and AR
107. Manual Publication No 980938 Rev K This page was left intentionally blank xviii Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual List of Figures Figure 1 1 Example DRM with Two Driver Receiver Boards DRA and DRB 1 7 Figure 1 2 DRM Digital Resource Module Block Diagram eene 1 8 Figure 1 3 T940 Optional Front Panel PWR Connector 1 8 Figure 2 1 T940 with Two Boards Installed 2 1 Figure 2 2 T940 with Two DR3e Boards Installed see 2 2 Figure 2 3 Digital Board DB Switch 2 3 Figure 2 4 T940 Inter Module Mode Jumper Connector 2 7 Figure 2 5 T940 Inter Module Mode Jumper Positions and 2 7 Figure 2 6 Installing the DRM into a 2 8 Figure 2 7 1263 Series VXI Chassis 1263HPf top 1263HPr bottom 2 9 Figure 3 1 T940 Front Panel Appearance 3 1 Figure 3 2 T940 Front Panel Showing Optional Front Power 3 2 3 3 PWR GOnnector i tuii eate pae aO a DER AT ba Ed 3 3 Figure 3 4 LBUS LOCKOUt Keys inet ire eer 3 4 Fig
108. NU 13 D2 Local D2 Local NU 14 CH19 CH20 CH17 CH18 NU 15 CH21 CH22 CH23 CH24 NU 16 CH5 CH6 CH20 NU 17 CH11 CH12 CH21 NU 18 CH15 CH16 CH22 NU 19 CH29 CH30 CH19 NU 20 D3 Local D3 Local NU The relevant VXlplug amp play function is e tat964 queryFrontEndAlert Driver Receiver Data Panel The Driver Receiver data display is accessed from the Execute DSx View Driver Receiver Data menu bar selection Where x is the sequencer you wish to query Soft Front Panel Operation 5 148 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 2 1 u x 1 2 Figure 5 80 Driver Receiver Data Panel This panel displays the following Driver Receiver data Channel Good 0 A 1 LED illuminated indicates that the channel is currently lower than the low comparator CVL Channel Good 1 A 1 LED illuminated indicates that the channel is currently higher than the high comparator CVH Drive Fault A 1 LED illuminated indicates that the channel has triggered a drive fault event Over Current A 1 LED illuminated indicates that the channel has triggered an over current event Capture Fault A 1 LED illuminated indicates that the channel has triggered a Capture Fault AUX A 1 LED illuminated indicates that the channel is currently higher than the high comparator The DR3e AUX1 signal is a dual comparato
109. Operation The Soft Front Panel SFP is a stand alone executable that can be used to program query and run the DRM digital resource Regardless of the user s choice of programming path VXlplug amp play instrument driver A24 A32 register based access or a combination of these the following basic 7 step process is required to implement a DRM test program 1 Open a communication link to the DRM module called a session 2 Configure global hardware parameters 3 Configure the available channels 4 Edit the Data Sequencers a Program the timing sets to govern the I O data transfers b Create the pattern sets and populate them as appropriate Create the Waveforms and define d Set sequence parameters e Edit sequence steps Execute the sequence Utilize status and post process functions to evaluate analyze results 7 Close the VXI DRM session The following sections describe the SFP operation as it pertains to the previous seven steps Additionally sections are included covering the instrument functions self test calibration and utility functions The relevant VXIplug amp play instrument driver function s for each step are also listed The program has a help menu for additional assistance SFP Basics A single T940 is referred to as a Digital Resource Module DRM A single DRM can be programmed as two separate 32 channel instruments Not Linked or as a single 64 channel instrument Linked Multiple DRMs can be
110. Panel This is the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements A buffered version also comes out the Front Panel External Force is an analog I O signal which is connected to all of the Pin Electronics devices and can be used to force a level on the output of the driver It may also be used to monitor a channel s state EXTFORCE is also used for calibration Real time temperature monitors for the pin electronics Digital Board Sequencer B Open Collector Channels The Open Collector Channel I O block diagram Figure H 8 illustrates the configuration and control of the Open Collector utility channel I O on the UR14 These channels can be used for slow LVTTL I O Four programmable input references INREF 1 4 allow testing input levels from 0 to 20V Four Over Current references OCREF 1 4 can be used to limit the sink current from 0 to 1A when a channel is used as a high voltage inductive input Astronics Test Systems UR14 Driver Receiver Board 1 11 Model T940 User Manual Publication No 980938 Rev K RH 33 64 INREF 1 4 4 input reference thresholds 1 per byte OV to 20V EN 33 64 gt e OCREF 1 4 OVER CURRENT 4 OCREF thresholds detect per pin per byte 16 selections up to 1A Figure l 8 Open Collector Channel I O Signal Descriptions Figure 1 8 RH 33 64 Sequencer B Response Data High EN 33
111. Panel Operation 5 169 Model T940 User Manual Publication No 980938 Rev K V Voltage This control displays the fused V bias voltage The relevant VXIplug amp play API functions e tat964 queryAdc e tat964 queryAdcAverage Front Panel DUT GND This control displays the GND voltage The V V power relay must be closed to activate measurement The relevant VXlplug amp play API functions are e tat964 queryAdc e tat964 queryAdcAverage EXTFORCE This control is used to connect or open the EXTFORCE signal to the specified channel The relevant VXlplug amp play API function is e iat964 setForceConnect EXTSENSE This control is used to connect or open the EXTSENSE signal to the specified channel The relevant VXlplug amp play API function is e iat964 setSenseConnect Channel This control is used to specify the channel for the EXTFORCE EXTSENSE and Monitor Signal controls The relevant VXlplug amp play function is e tat964_setMonitorSignal Monitor Signal This control is used to specify the channel and signal that will be connected to the monitor output The relevant VXI plug amp play API function is e tat964_setMonitorSignal Soft Front Panel Operation 5 170 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Monitor Voltage This control displays the selected monitor signal voltage The relevant VXlplug amp play functions are e tat964 queryAdc e tat964
112. Publication No 980938 Rev K Model T940 User Manual The figure above represents two channels with the following configuration e CH1 Output Signal Phase 1 Stimulus Format Return to One Pattern Code Drive Low e CH2 Output Signal Phase 2 Stimulus Format Non Return Pattern Code Drive High The Assert signal rising edge causes the pattern code to be loaded The Return signal falling edge causes the Stimulus Format to output Since CH2 is set to Non Return the Return signal did not affect the output level Access this panel from the menu bar Edit gt Data Sequencer x gt Timing Sets Where x is the sequencer you wish to configure Figure 5 40 Data Sequencer Timing Sets Panel To program a timing set scroll down the list until the desired timing set number is visible Timing set numbers are assigned based on the current timing mode e Per Step Multi 1024 timing sets with four phase window groups per timing set TSO is the timing for sequence step 1 TS1 is the timing for sequence step 1 timing set 1023 is the timing for sequence step 1023 e Per Step Single 4096 timing sets with one phase window group per timing set TSO is the timing for sequence step 1 TS1 is the timing for sequence step 1 timing set 4095 is the timing for sequence step 4095 Astronics Test Systems Soft Front Panel Operation 5 75 Model T940 User Manual Publication No 980938 Rev K e Indexed 256 timing set
113. Ranges 14 75 V to 14 V VMO 6 75 V to 21 V VM1 Input Threshold Resolution Input Threshold Accuracy CVH and CVL lt 5 50mV 1 of PV Skew Chan to Chan lt 3 ns drive and compare Current Source Sink Programmable Channel Commutating Voltage Vcom CMH and CML Range 0 4 mA to 20 mA usable to 24 mA Resolution lt 10 uA Accuracy 3 of PV 1200 Range same as driver Resolution 5 mV Accuracy 50mV 1 of PV Over Current Alarm IAH and IAL Range 800 mA Resolution 30 uA Accuracy 50 196 of PV Resistive Loads Selectable Channel 140 Q to 1 KO 8 selections to Vcom Accuracy 3096 PMU capability DUT_GND Reference Input per Driver Receiver board Voltage Range Resolution Accuracy same as driver Offset range 3 V Interrupt Voltage 390 mV Resistive load 100 kO Bypass Relay On or Off DR3e Driver Receiver Board D 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Description Power Input Using Optional Front Panel Power Input Connector for Pin Electronics devices Characteristics V 10 to 28 V V 4 to 19 V V to V delta lt 32 V Pin Electronics Monitoring per channel All programmed levels Output and Input levels Temperature Channel Over voltage Protection Channel Capacitance Clamped to 0 4 V beyond V or V Max current 200
114. Receiver I O e DR3e Driver amp Receiver e Control Logic e Firmware amp NV Data Astronics Test Systems DR3e Driver Receiver Board D 1 Model T940 User Manual Publication No 980938 Rev K DR3 DR3e FRO AUX DATA 5 8 Ooo AUXENSS AUXILIARY AUX 5 8 ui MEET I NE ERR AUX DATA 9 12 amp RECEIVER AUXKENSHZ vo VO CONTROL AUX DATA 1 4 PUNTA AUX RL1 CH DATA 1 32 CH RH 1 32 RECEIVER 54 CHRIUS2 RL 1 32 vO EXTFORCE OC 1 32 OVERVOLT TEMPMON VO CONTROL DUT_GND TEMPMON CONTROL oowERuer 1060 p DUT GND FP VO CONTROL FIRMWARE amp NV DATA VO CONTROL Figure D 1 DR3e Driver Receiver Block Diagram Auxiliary Driver amp Receiver Figure D 2 illustrates the configuration and control of AUX5 8 LVTTL and AUX9 12 ECL Driver amp Receiver I O DR3e Driver Receiver Board D 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual AUX 5 8 AUX DATA 5 8 p 74LVC2G125 74LVC2G125 AUX RH 5 8 MC100ELT24 MC100ELT25 AUX DATA 9 12 MC100ELT24 Figure D 2 Auxiliary Driver amp Receiver I O Block Diagram Signal Descriptions AUX EN 5 8 Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX RH 5 8 Auxiliary Response High inputs to the Data Se
115. SIG_GND 81 SIG_GND 32 CH16 82 CH32 33 SIG_GND 83 SIG_GND DR1 Driver Receiver Board B 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal Pin No Signal 34 AUX1 A 84 AUX7 A 35 SIG_GND 85 SIG_GND 36 AUX2 A 86 AUX8 A 37 SIG_GND 87 SIG_GND 38 AUX3 A 88 AUX9 A 39 SIG_GND 89 AUX9 A 40 AUX4A 90 AUX10 A 41 SIG_GND 91 AUX10 A 42 AUX5A 92 AUX11 A 43 SIG_GND 93 AUX11 A 44 AUX6 A 94 AUX12 A 45 SIG_GND 95 AUX12 A 46 PBUT_A 96 BCLK A 47 PMODE_A 97 SIG_GND 48 SIG_GND 98 NC 49 NC 99 SIG_GND 50 NC 100 NC DRB 1 0 Channels J201 Table B 5 DR1 DRB I O Channels J201 Name Pin No Description CH33 CH64 Various Bi directional High speed LVTTL channels SIG_GND Various Signal Ground reference AUX1 B 34 Bi directional General Purpose LVTTL I O pin AUX2 B 36 Bi directional General Purpose LVTTL I O pin AUX3 B 38 Bi directional General Purpose LVTTL I O pin AUX4 B 40 Bi directional General Purpose LVTTL I O pin AUX5 B 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 B 88
116. Sequencer to the LVTTL output buffers AUX DATA 5 8 Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX RH 5 8 Auxiliary Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from the Data Sequencer to the ECL output buffers CONTROL Signals used to control isolation relays and ECL bipolar differential mode AUX 5 8 Four LVTTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 VBB ECL input threshold 1 3V AUX 9 12 Four negative differential signals used to input or output test signals See Configuring the AUX Channels in Astronics Test Systems DR7 Driver Receiver Board F 3 Model T940 User Manual AUX 9 12 Publication No 980938 Rev K Chapter 5 Four bipolar positive differential signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 DR7 Driver amp Receiver Figure F 3 illustrates the configuration and control of the DR7 Driver amp Receiver RS422 RS485 Figure F 3 DR7 Driver amp Receiver Block Diagram Signal Descriptions
117. Soft Front Panel i e c and h files e MS Windows 32 bit DLL library i e tat964 32 01 and tat964 def files Microsoft 32 bit DLL import library i e tat964 lib file e Function panel file i e tat964 fp file MS Visual Basic Function Declaration text file i e tat964 bas file e Windows help file i e tat964 chm file Visit the Astronics Test Systems website at http www astronicstestsystems com support downloads to check for updated DRM driver or firmware updates Astronics Test Systems Installation 2 11 Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank Installation 2 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 3 DRM Front Panel The DRM front panel provides the hardware interface to the unit under test UUT Figures 3 1 and 3 2 illustrate the front panel and its connectors DRB Channel T940 shown with two Driver Receiver boards installed DRA and DRB DRA Channel Figure 3 1 T940 Front Panel Appearance Typical Astronics Test Systems DRM Front Panel 3 1 Model T940 User Manual Publication No 980938 Rev K DRB Channel yo J201 DRA DRB Power T940 shown with two 2 and Multi Driver Receiver boards Function Signals installed DRA and DRB 592 DRA Channel Figure 3 2 T940 Front Panel Showing Optional Front Power Connector J200 and J201 Channel The J20
118. Suite A DRS is two or more adjacent DRMs synchronized together to form a digital test system with more than 64 channels DRA Driver Receiver A DRB Driver Receiver B DSA Data Sequencer A DSB Data Sequencer B Coupled Used to describe a DRM sequencer that is included in a DRS chain Functional Description 4 4 Astronics Test Systems Publication No 980938 Rev K Description Linked Primary Secondary Terminator LBUSA LBUSC CONTROL IMA SIMA IMB SIMB IMJMPR Model T940 User Manual Used to describe two sequencers DSA and DSB on the same DRM that are synchronized together Used to describe the DRM that provides all the timing for the sequencers that are part of the DRS chain DSA is always coupled to the DRS chain and is the source of the timing and control DSB can be coupled to the new chain or run independently from the chain The primary module must be located in the right most slot position in the VXI chassis relative to the DRMs that will be coupled Used to describe the DRMs located between the primary and terminator module that pass the timing signals to the DRM in the next lower slot position Individual sequencers can be coupled to the DRS or run independently from the primary module as linked or not linked Used to describe the DRM in the left most position of the DRS chain Individual sequencers can be coupled to the DRS or run independently from the primary module as linked or not linked VX
119. Systems Soft Front Panel Operation 5 27 Model T940 User Manual Publication No 980938 Rev K Configure Timers Access this panel from the menu bar Config Data Sequencer x Timers Where x is the sequencer you wish to configure The DRM has five timers e Watchdog e Sequence Timeout e Pattern Timeout e Pattern Delay 1 e Pattern Delay 2 20ns to 42 949672970s 20 to 42 949672970s 20ns to 42 949672970s 20ns to 42 949672970s Figure 5 22 Configure Timers Watchdog The watchdog timer is a real time timer that performs specific actions if the Dynamic Test does not finish within the specified time period The Watchdog Timeout Timer starts when SEQACT begins This timer does not stop during a Pause or Halt including single stepping e Generates an event WDTO if the sequence active time exceeds the specified value e If the watchdog action is set to Disable Drivers all 32 drivers will tri state when a timeout occurs but any active load or resistive loading remains Sequence Timeout The sequence timeout timer is a real time timer intended to be used in a Sequence Step that has a conditional loop where one is waiting for a termination condition to proceed to the next Sequence Step e There is a global enable e tstarts when the first branch takes place Soft Front Panel Operation 5 28 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The timer is
120. Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix I UR14 Driver Receiver Board UR14 Features e Channels 32 Low Speed single ended Open Collector Utility Pins e Voltage range 0 to 30 V e Suitable for Inductive loads internal clamping to 42 V e 5V Pull up allowing each channel to operate as low speed TTL e Programmable input level detection per byte 0 20V e Programmable Over current detection per byte 0 1A e External Probe Support Auxiliary I O channels Six programmable Two are dedicated for the external probe when used Two LVTTL One is dedicated for the external probe when used Three ECL single ended or differential Four LVTTL or SE ECL Four LVTTL or ECL single ended or differential See Figure I 1 for a front panel illustration of the UR14 Block Diagram The top level block diagram for the UR14 Driver Receiver board is shown in Figure 2 More detailed diagrams of these blocks are featured in Figures l 3 thru l 5 Astronics Test Systems UR14 Driver Receiver Board l 1 Model T940 User Manual Publication No 980938 Rev K GL qm D o GE D T940 UR14 J3B J3A J2A J2B J1B IER ERE Figure 1 UR14 Front Panel UR14 Driver R
121. The sequence steps are used to control the flow of the patterns and assign timing Access this panel from the menu bar Edit Data Sequencer x Sequence Steps Where x is the sequencer you wish to configure 1 amp 0 100 1 SF1 10 SF2 LO STOF Figure 5 56 Edit Sequence Step Panel Up to 4096 sequence steps are available for Indexed and Per Step Single timing modes Up to 1024 sequence steps are available for Per Step Multi timing mode The Delete key will clear the step data contents de allocate any assigned pattern data and initialize the step settings A double click on any of the step number cells opens a Sequence Step Data panel for that cell The T964 Sequencer Operation Details section in Chapter 8 provides detailed information on sequencer operation The relevant VXIplug amp play API functions e tat964 selectSequenceStep e tat964 initSequenceSteps Astronics Test Systems Soft Front Panel Operation 5 99 Model T940 User Manual Publication No 980938 Rev K VXIO 2 INSTR Edit DSA Sequence Step 1 Data 1 00 ns per count Pattems Intemal TOCLK Clocks per Pattem Timing Set 32 PER gt 100 CPP 51 50 Jump Type Noe v Loop Count Loop Counter Pass Fail Clear 20 30 Defaut 7 a me Figure 5 57 Sequence Step Data Panel Internal TOCLK This control allows the user to specify the Internal TOCLK period When the system clock source is set to
122. User Manual Note Use the UH14 Current Estimator calculation tool to estimate the power converter power consumption from the 12V 24V power rails This tool is available upon request from Astronics Test Systems at atssales astronics com Environmental Table 1 11 Environmental Operating 0 C 45 C TEMPERA Storage 40 C 70 C Humidity 5 to 95 Altitude 10 000 ft Cooling Required 10 Rise 2 UR14s Max 14 4 lps 2 8 mmH 0 Typ 10 4 los 1 6 mmH 0 UR14 179 889 hours T940 180 855 hours EMC Council Directive 89 336 EEC MTBF ground kadign Power Converter 540 040 hours T940 UR14 77 279 hours Dimensions 20 x 114 x 305 mm Emission EN61326 1 2006 Class A Immunity EN61326 1 2006 Table 1 Designed to Meet Testing in Progress Safety Low Voltage Directive 73 23 BS EN61010 1 2007 Designed to Meet Testing in Progress Astronics Test Systems UR14 Driver Receiver Board 1 27 Model T940 User Manual Publication No 980938 Rev K UR14 Signal Description CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 J3B CH15 UTILITY CH14 HIGH CH13 VOLTAGE CH12 50 CH11 PINS CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 GND GND AUX3 A NC J2A PROBE OUT TIMING I O AUX 7 11 A 20 NC PINS NC AUX 6 10 A AUX 5 9 A DUT GND 12V 12V DUT_GND GND_REF BCLK PROBE I O PBUT 26 PROBE MODE PINS PROBE COMP PROB
123. Vector Bits which form the Vector Bit Index If the vector jump mode is disabled then the sequence step number to jump to is specified by the Jump Step control This control is only visible if the jump type is set to Normal or Gosub The relevant VXIplug amp play function is e tat964 setSequenceJump Pass Fail Clear This control programs the Pass Fail Clear Mode during this step The T940 pass fail flag is used for conditional jumping and indicates the results of a channel compare pattern code The pass fail flag can be set to clear at the beginning of each sequence step default or to hold the previous state mask The selections for this pull down control are Table 5 80 Step Record Mode Settings Setting Description Default Clear Pass Fail Mask Hold Previous Pass Fail Note See the Jumping on and Counting Errors section of Chapter 8 for a more in depth explanation The relevant VXlplug amp play API function is e tat964 setSequencePassFailClear Step Record Mode This control programs the Step Record Mode during this step The T940 contains three memories that store error data from a sequence Astronics Test Systems Soft Front Panel Operation 5 105 Model T940 User Manual Publication No 980938 Rev K Timing burst 1 Error Address Memory 2 Record Index Memory 3 Record Memory There is also the Error Counter which counts the number of pattern errors that occurred during the previous sequ
124. a eth re rb e P 5 27 Reference Freq MEzy o ete detta 5 27 Configure TiImers ta iiit ttt dece te ee tt t cena LU EHE E CHEER 4000 5 28 Watchdog ACHO noies Here Elie eee LEE dee ere 5 29 Watchdog Ec ccm 5 30 Sequence Timeout 5 30 Sequence Timeout 5 30 Pattern TIMEOUT PE 5 30 Pattern Delay 1 2 iere desire n a 5 31 Gonfigure Triggersx tee f aea i ecd ah t e adea n 5 31 TRIG e E LEER 5 32 NN m 5 32 Test Conditions n 5 33 edges cc 5 34 Edge Test Clear d p Pot De Pe Hia th Erde o Pe 5 34 Configure Pulse Generator essen entente nennen teneret 5 35 ELE 5 35 MOOG aceite anced ef n rf 5 35 Smp 5 36 Period someone ot eta adt tam dt dettes 5 36 Br tial 5 36 MIO s t to cette cath dito ctetu th t tete baler 5 37 Configure Data Sequencer 5 37 Error Record Basis 5 38 Raw Record 2 22 2 cei erae tee e ane ne a 5 38 8 CTS MED 5 38
125. and false would indicate the pause trigger signal is high Note The Hesume Signal selection is covered in the Configure Triggers section in Chapter 5 The relevant VXlIplug amp play API function is e tat964 setSequenceHandshake Resume Modifier This pull down control programs the Handshake Resume Modifier The resume modifier allows the handshake to resume normally None or allows for the following modifications Pattern Delay 1 or 2 Continue either on the presence of the specified resume signal or at the exhaustion of Pattern Delay timer 1 or 2 the Delay Timer started when the Pause signal was received Pattern Timeout Set the pattern timeout PTO flag if the specified resume signal is not received by the time the Pattern Timeout timer has exhausted the Pattern Timeout timer started when the Pause signal was Soft Front Panel Operation 5 110 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual received The selections for this pull down control are Table 5 83 Handshake Modifier Settings Setting Resume Modifier None No modifier resume on Resume Signal only Pattern Delay 1 Pattern Delay 1 timer Pattern Delay 2 Pattern Delay 2 timer Pattern Timeout Pattern timer PTO also set The relevant VXI plug amp play API function is e tat964 setSequenceHandshake Waveform Properties The waveform logic allows the user to enable up to six waveforms per sequence ste
126. are UUT Bi directional LVTTL I O channels from the DR1 Drivers and Receivers VCC LVTTL Power 3 3V Control Logic The control logic contains the registers memory and logic that allow the digital board to interface and configure the hardware DR1 Driver Receiver Board B 4 Astronics Test Systems Publication No 980938 Rev K Signal Descriptions Model T940 User Manual CONTROL Signals used to control isolation termination NV data and load relays MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digital board to the Driver Receiver board MF SIG Multi Function signal output to the PWR connector Firmware amp NV Data The Control Logic firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions CONTROL DR1 Characteristics Signals used to program firmware and NV DATA Table B 1 DR1 Characteristics Description Characteristics Digital Type LVTTL 74LVC2G125 Channels Output Voltage 32 single ended SE per board Per channel relay isolation 0 55 V max 2 4 V min Output Drive Current typical Source Sink 24 mA Output Impedance Program selectable per pin Input Voltage Direct or 100 O Series 001 Direct or
127. are only applicable to the master sequencer Others will vary depending on the number of DRMs in the DRS External inputs include the Auxiliary AUX and the VXI Trigger TRG inputs There are five types of AUX inputs Programmable LVTTL ECL LVDS and 422 485 The LVTTL AUX input will be used as the timing reference with adjustment values provided for the other four There are two types of VXI TRG inputs TTL and ECL The TTL input will be used as the timing reference with adjustment values provided for the ECL input Similarly the External outputs include the AUX and TRG outputs There are five types of AUX outputs Programmable LVTTL ECL LVDS and 422 485 The LVTTL AUX output will be used as the timing reference with adjustment values provided for the other three There are two types of VXI TRG outputs TTL and ECL The TTL output will be used as the timing reference with adjustment values provided for the ECL output Notes e The Programmable AUX I O is only available on the DR3e e TheLVDS AUX I O is only available on the DR2 The 422 485 AUX I O is only available on the DR7 e The Programmable AUX I O is based on LVTTL levels without any delay calibration e A DR3e Channel with LVTTL levels will have the same timing characteristics as a Programmable AUX I O when calibrated External AUX Input Timing Adjustments LVTTL timing reference ECL 1 ns faster Programmable 9 ns slower 422 485 TBD Astronics Te
128. be done on a Sequence Step or Sequence as though the Burst Count is set to 1 e With default settings Pass Fail for a Sequence Step represents the cumulative results for that Sequence Step But there are options that will be covered below e With the default settings a Sequence Step will Fail if any Pattern Error or Qualified Pattern Error occurred during the Sequence Step Similarly a Sequence will Fail if any pattern Error or Advanced Topics 8 18 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Qualified Pattern Error occurred during the Sequence simple Pass says that there were no Pattern Errors or Qualified Pattern Errors that occurred during the Sequence Step or Sequence It is logically the complement of a Step Fail or Sequence Fail e Valid Pass is one where there were no Pattern Errors or Qualified Pattern Errors but it also says that there was at least one channel for each pattern or Qualified Pattern with an expect condition in the Sequence Step or Sequence This mode on operation is enabled by Pass Valid Enable a static setting This is set on the Config gt Data Sequencer A B gt Settings panel The relevant VXIplug amp play API and ARI functions e tat964_setPassFailParameters e ARI AssignPtgPipelineParameters Ei 10 2 1 5 Configure DSA Settings 2 00 ns per acala An Eror Record Basis Raw Record Basis Eror Count Basis G
129. calibration to a file for later restore e g File Load DRA Calibration Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted the calibration factors will revert at the next power cycle Driver Receiver Calibrate Function Serial Number gra DVH DVL 71 12060853 DRB Start Chan 1 Meas Delay 0200 End Channel 2 24 Offset Gain DVH x 8566 6A8D Slew Default Status DVL 4 Channel Af 1 6AB5 Calibrating SN 12060853 Calibrating Driver Levels Channel 1 Complete Channel 2 Complete al Channel 3 Complete Channel 4 Complete sel s sd e CVH CVL The CVH CVL calibration calculates the offset and gain of the input comparator levels For the DR4 a separate offset and gain is calculated for each group offset The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the CVH CVL menu item on the Calibrate Function menu Astronics Test Systems Programmable Channel Calibration
130. capture performed on the Close edge of the window Window Channel error test and data capture performed between the Open edge and the Close edge of the window The relevant VXlplug amp play API function is e iat964 setChannelParameters Static Mode This pull down control programs static mode for the selected channel s When the Static Mode Enable is set to on the designated channel is put into the Static Mode and whatever is currently in the Static Broadside Stimulus Register will be applied to the output Channels not in Static Mode will operate in the normal dynamic mode When the channel is returned from Static to Dynamic Mode dynamic operation will resume as though it had never been put into the Static Mode The selections for this pull down control are Astronics Test Systems Soft Front Panel Operation 5 57 Model T940 User Manual Publication No 980938 Rev K Table 5 59 Static Mode Settings Setting Description Off Static Mode enabled for selected channel s On Static mode disabled for selected channel s Note The static state must be enabled before setting the static mode The relevant VXlplug amp play API function is e iat964 setStaticMode Properties This command button allows the user to configure the driver receiver properties See next section for additional information Configure Channel Properties The channel properties consist of the following nine elements Driver
131. coupled and synchronized as a Digital Resource Suite DRS Each 32 channel group in the DRM can be included in the DRS or it can be independent Up to eight DRMs can be coupled The SFP is a DRM utility that can be used to debug or check out user configurations and programming Astronics Test Systems Soft Front Panel Operation 5 1 Model T940 User Manual Publication No 980938 Rev K When started the SFP searches for all the installed DRMs in the VXI system If more than one DRM is detected a dialog box prompts the user to select the DRM to initialize Each instance of the SFP opens a VXI session with a single DRM in the system Once a single DRM is selected a dialog box prompts the user if the DRM should be reset Resetting the DRM clears any previously programmed settings Selecting No retains all the DRM structures and settings previously programmed Single DRM found at VXI Slot 4 VXI0 2 INSTR Do you want to reset NOTE Reseting will clear all defined structures Figure 5 1 Reset Screen The following warning will display if a DRM module with a type 3 power converter is installed in a VXI 3 0 chassis cTRI Warning initializing the T964 Message returned Limit output channels to avoid exceeding backplane current rating tat964 init Figure 5 2 Initialize Warning SFP Main Panel After a VXI session has opened and the reset option selected the main panel is displayed Soft Front Panel Operation 5
132. dst 5 73 XE 5 73 5 5 73 EVO sii ep p meri eed Iudei Em Iesu entre d 5 73 Editing the Data Sequencers ssssssssssssssssssssee enne enne sn nnne nnne 5 74 Editing the Timing Sets inte E tte ded iet mes 5 74 Timing Set RUES pia etre tee etr iet Pete ote restet 5 76 Advanced Timing Set 5 76 Phase Window Spanning ener nnne terrens 5 77 Idle Standby Timing iioi te Rote Pede tb Edere 5 77 Editing tlie Patterns xui ii A its 5 77 satiatus diea t o va t ck em tud Monito e ctr ut Utere 5 78 ASSO e te m teen i fe etes nevera aq Si ee 5 79 Edit Data erem 5 80 Import Export File Format mei ced m eint cei e etre 5 87 M 5 87 Data Format ineat eet beate e ext hen ate et ay 5 87 ae 5 87 BIN Aly E 5 89 ASGII M D 5 90 Editing Wavetorms iu ii nete RR S e p RE e als 5 90 able SiZe oe
133. dynamic logical address mode where the final logical address is assigned by the resource manager A switch setting of 0 while normally invalid as a selection also will place the DRM in a dynamic mode avoiding configuration conflicts with Logical Address 0 The DRM is shipped in the dynamic configuration with a switch setting of 255 Table 2 1 Logical Address Selection SW1 Position 8 7 6 5 4 3 2 1 Signal LAO LA1 LA2 LA3 LA4 LA5 LA6 LA7 Switch position 8 through 1 corresponds to bits 0 through 7 of the logical Astronics Test Systems Installation 2 3 Model T940 User Manual Publication No 980938 Rev K address The ON setting sets the corresponding bit of the logical address to a one 1 VXI Interrupt Selection The VXI backplane supports 7 levels of interrupts Using the Slot O API functions interrupt handlers can be installed and enabled for each interrupt level Switch positions 8 7 and 6 of SW2 are used to assign the DRM interrupt level A value of zero disables interrupt generation by the DRM Values between one and seven select the interrupt of the same value For example if SW2 position 7 and 6 are ON and position 1 is OFF then VXI interrupt level 6 will be used by the DRM VXI level one is set at the factory prior to shipment Table 2 2 VXI Interrupt Selection SW2 Position 8 7 6 Signal ILEVO ILEV1 ILEV2 ILEV2 ILEV1 ILE
134. e The Timer starts when the Pause begins A Pattern Delay Timer timeout will cause a resume to be generated Watchdog Action This toggle control is used to enable disable the watchdog timeout Event Only Driver Disable feature Table 5 25 Watchdog Action Setting Description Event Only Set bit in event register only when a watchdog timeout occurs Disable Drivers Set bit in event register and disable the drivers when a watchdog timeout occurs The relevant VXlplug amp play API function is Astronics Test Systems Soft Front Panel Operation 5 29 Model T940 User Manual Publication No 980938 Rev K e tat964 setWatchdogTimer Watchdog Time This numeric control is used to specify the watchdog timeout count The timeout is programmed in 20 ns steps with a range of 40 ns to 4000 s The watchdog timer set resolution adjusts based on the timeout value Table 5 26 Watchdog Timer Resolution Ranges Timer Setting Resolution Less than 10 ms 20 ns From 10ms to 10 s 100 ns From 10 s to 4000 s 1 us The relevant VXlplug amp play API function is e tat964 setWatchdogTimer Sequence Timeout State This toggle control is used to enable disable the sequence timeout feature Table 5 27 Sequence Timeout State Action Setting Description Off Disable sequence timeout bit in event register On Enable sequence timeout bit in event register The relevant VXlplug amp play API
135. e tat964 close e tat964 reset Soft Front Panel Operation 5 176 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 6 Programmable Channel Calibration This chapter provides calibration and verification information for the family of T940 Digital Resource modules which have channels with programmable driver receiver characteristics The following table lists the calibration functions and the DRM types that require the calibration Table 6 1 Calibration Functions and DRM Requirement Calibration Function DRM Types ADC Reference via EXTERNAL FORCE port DR3E DRY UR14 Monitor ADC DR3E DRY UR14 DR4 Source Sink Load via EXTERNAL FORCE port DR3E DR9 UR14 Drive High and Drive Low DR3E DRY UR14 DR4 Compare High and Compare Low DR3E UR14 DR4 Vcommutating Vcom High and Low DR3E DRY UR14 Current Source and Sink DR3E DR9 UR14 Current Alarm High and Low DR3E DRY UR14 Delete Section two only DR3E DR9 UR14 DR4 A CAUTION ALWAYS PERFORM DISASSEMBLY REPAIR AND CAUTION CLEANING AT A STATIC SAFE WORKSTATION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS Performance Verification Do not attempt to calibrate the instrument before verifying first that the instrument is in working order A complete set of specifications is listed in the Appendic
136. en 8 3 Figure 8 2 Configure Module 2 22 8 4 Figure 8 3 Configure VXI Triggers DSA 4 4400400000000 8 5 Figure 8 4 Step Record Mode Control on Edit DSA Sequence Step 8 6 Figure 8 5 Setting the Record Mode Using the Configure Module 8 7 Figure 8 6 Setting the Record Type Using the Configure DSA Settings Panel 8 8 Figure 8 7 Setting the Test Bit in the Edit DSA Pattern Set Step 8 10 Figure 8 8 Setting Error Count Basis in the Configure DSA Settings 8 11 Figure 8 9 Setting Error Address Basis in the Configure DSA Settings 8 11 Figure 8 10 Setting the Pipeline Mask in the Edit DSA Parameters Panel 8 14 Figure 8 11 Setting the Pass Fail Basis in the Configure DSA Settings Panel 8 15 Figure 8 12 Setting the Pass Fail Basis in the Configure DSA Settings Panel 8 15 Figure 8 13 Setting the Jump Condition in the Edit DSA Sequence Step Panel 8 17 Figure 8 14 Setting the Halt Mode in the Execute DSA 8 18 Figure 8 15 Setting the Halt Mode in the Execute
137. eso m eo Eder s B 5 Firmware amp NV Data ioter reote Pete boc B 5 Signal Descriptions eio Tate aL nen B 5 DR Characteristics 5 eii ete P pfe epe B 5 Power Requirements 5t tete reb P te B 6 Environmental ed tette qe ee d eb e fett Dt teg B 6 DRI Signal Description niece an ee agre er dn B 7 DRA I O Channels 200 2 0 c eee dax a Plac B 7 Channels 201 5 eene De vae aer Y e ru Dee o ae ieee B 9 PWEGOnDeCtors otn tutu ns LI E cu DIE B 11 Calibration dio tette 12 C 1 DR2 Driver Recelver Board eter rete rena nne tu tack n nnmnnn nnna C 1 BEIDE C 1 Front Panel Connectors cites dye caede dcr Ide Ee C 1 etd citer ie Wiel eed Med ey eo Sindee dee C 1 Auxilliary Driver amp Receiver N O C 2 5 065 iret rr mre t fret C 3 DR2 Driver amp Receiver V O meisie et tn bap ED n RE C 4 Signal Descriptions
138. f LC gt 0 and CA 0 load the designated Loop Counter set CA 1 and jump to JSA e If CA 1 and NOT LCD decrement the loop counter and jump to JSA f CA 1 and LCD reset CA if UCO 0 also the Seq loops or finishes e Otherwise the Seq loops or finishes 21 The Seq loops or finishes 22 e If NOT IN SUB set the IN SUB flag set the LAST flag and jump to JSA Otherwise the Seq loops or finishes also set a fault flag 23 The Seq loops or finishes 24 e lf LC 0 the Seq loops or finishes e f LC gt 0 and CA 0 NOT IN_SUB load the designated Loop Counter set CA 1 set the IN SUB flag set the LAST flag and jump to JSA e f CA 1 and NOT LCD and NOT IN SUB set the IN SUB flag set the LAST flag decrement the loop counter and jump to JSA e If CA 1 and LCD reset CA if UCO 0 also the Seq loops or finishes e Otherwise the Seq loops or finishes 25 e f IN SUB jump to the Return Seq and clear the IN SUB flag Advanced Topics 8 40 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Jump LSTSEQ RTN SUBRT CLOOP Action Comments Otherwise the Seq loops or finishes also set a fault flag 26 Jumps to JSA also set a fault flag 27 28 e f IN SUB jump to the Return Seq and clear the IN SUB flag Otherwise the Seq loops or finishes also set a fau
139. fi uiii Inti e ier fe ety eor edo y de ned ee 5 25 Configure THM OLS o th ru P tu e pf 5 28 Configure Triggers Parnel t ea rne Ee dette de es 5 31 Configure Pulse Generators tete tette trat e eee eoe TAERA 5 35 Data Sequencer Configure Settings 5 38 Over Gurrent Panel 5 43 ProbePanel saa ote eiae icai 5 45 Attribute Panels ett tidie rn tr Ser RR HR 5 50 Configure Channels 5 53 Configure Channel Properties Panel seen 5 59 Gutrent Eoad 5 5 9 duh dr d aaa ee 5 62 Resistive to VCOM Load 2 dace e tete tete 5 62 Configure UR14 Channel Properties 5 65 Configure AUX Channels Panel eene nennen 5 66 Configure AUX Channels Panel 5 66 Shared AUX UAUX Controls esssssssssseseeeeeene enne nennen enne 5 68 Configure Interr pt a e erts 5 73 Editing the Data Sequencers ssssssssssssssse eene 5 74 eii hee ee eei erent ae d Hee eee 5 74 Data Sequencer Timing Sets Panel 5 75 Edit Patterns Panel tea tea detta s 5 78 Append Data Sequencer Pattern Sets 5 79 Assign Data Sequencer Pattern Sets 5 80 Pattern Set Sequencer Data Panel
140. function is e tat964 setSequenceTimer Sequence Timeout Time This numeric control is used to specify the sequence timeout count The timeout is programmed in 10 ns steps with a range of 20 ns to 42 949672970 s The relevant VXIplug amp play function is e tat964 setSequenceTimer Pattern Timeout This numeric control is used to specify the pattern timeout count The timeout is programmed in 10 ns steps with a range of 20 ns to 42 949672970 s The relevant VXIplug amp play function is Soft Front Panel Operation 5 30 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual e lat964 setPatternTimer Pattern Delay 1 2 This numeric control is used to specify the pattern delay The pattern delay is programmed in 10 ns steps with a range of 20 ns to 42 949672970 s The relevant VXlplug amp play API function is e tat964 setPatternDelayTimer Configure Triggers Access this panel from the menu bar Config Data Sequencer x Triggers Where x is the sequencer you wish to configure E VXIO 2 INSTR Configure Figure 5 23 Configure Triggers Panel Pause Trigger and Pause Resume Trigger The pause triggers are used to stop the pattern timing during a burst The corresponding resume trigger re starts the pattern timing from where it was stopped A pause resume can be based on the true false state of any of the two pause triggers For example if Pause 1 Trigger was set to
141. fuses software non rechargeable batteries damage from battery leakage or problems arising from normal wear such as mechanical relay life or failure to follow instructions This warranty is in lieu of all other warranties expressed or implied including any implied warranty of merchantability or fitness for a particular use The remedies provided herein are buyer s sole and exclusive remedies For the specific terms of your standard warranty contact Customer Support Please have the following information available to facilitate service 1 Product serial number 2 Product model number 3 Your company and contact information You may contact Customer Support by E Mail atshelpdesk astronics com Telephone 1 800 722 3262 USA Fax 1 949 859 7139 USA RETURN OF PRODUCT Authorization is required from Astronics Test Systems before you send us your product or sub assembly for service or calibration Call or contact Customer Support at 1 800 722 3262 or 1 949 859 8999 or via fax at 1 949 859 7139 We can also be reached at atshelodesk astronics com If the original packing material is unavailable ship the product or sub assembly in an ESD shielding bag and use appropriate packing materials to surround and protect the product PROPRIETARY NOTICE This document and the technical data herein disclosed are proprietary to Astronics Test Systems and shall not without express written permission of Astronics Test Systems be use
142. good 0 Channel good 1 comparator signal Channel good 0 comparator signal Waveform 5 Waveform 5 signal Waveform 6 Waveform 6 signal Input Bus Select 1 4 Input Bus Select Signal Seq Flag 1 2 Sequence flag signal TOCLK In Test signal Pattern Clock Test signal SEQ CLK In Test signal Jump In Test signal Raw Error Test signal SEQ CLK D In Test signal TOCLK Out Test signal SEQ CLK Out Test signal Jump Out Test signal SEQ CLK D Out Test signal Pulse Generator Pulse generator signal Record Active 1 Active 0 Not Active Astronics Test Systems Soft Front Panel Operation 5 69 Model T940 User Manual Publication No 980938 Rev K Setting Description FS Reference Frequency synthesizer reference signal Frequency Synthesizer Frequency synthesizer signal Jump Strobe Test signal Int Error Test signal Ext Error Test signal HIGH Drive high PASS PASS flag FAIL FAIL flag CONDEN Condition enable flag BERREN Burst error enable flag LSR Load Sequence Register LLC Load Loop Count CA Counter Active CPPD Clocks per Pattern Done BCD Burst Count Done LCD Loop Count Done IN SUB Gosub Active C LOOP Counted Loop SUBRT Subroutine Return RTN Return Flag LSTSEQ Last Sequence Jump Test 1 4 Test signal The Channel Good 1 Channel Good 0 selections can select any of the front end channels using the tat964_setA
143. gt DSx View gt Static Data menu bar selection where x is the sequencer you wish to query Astronics Test Systems Soft Front Panel Operation 5 125 Model T940 User Manual Publication No 980938 Rev K VXIO 2 INSTR Static Data DSA Stimulus Delay N NIN NNN NON N NIN N o CB CB CO CO CO CO CO CO CD CO Figure 5 66 Static Data Panel The static data panel contains controls that program the static timing and stimulus data and displays the current static response data Prior to sequencer revision 0 21 the static timing uses the pulse generator to specify the stimulus delay and the response delay for all the static channels to within 15ns Both delays are with respect to the start of a sequence Sequencer revision 0 21 and later uses a dedicated timing source that specifies the response delay from 0 to 6 5ms Stimulus delay is no longer supported Stimulus Delay This control sets the delay from the start of a sequence execution to when the stimulus pattern will be output and is only available in sequencer revisions prior to 0 21 The delay can be set from 20ns to 40s with 10ns resolution Note The Stimulus Delay must be less than the Response Delay The relevant VXIplug amp play function is e tat964 setStaticTiming Response Delay Prior to sequencer revion 0 21 this control sets the delay from the start of a sequence execution to when the static pins will be sampled The delay be set f
144. if the pass fail flag is set to pass The relevant VXlplug amp play function is e tat964_setHaltMode Finish Mode This pull down control programs the finish mode When a sequence execution completes the sequencer will enter either the Standby or Idle state The Standby state outputs the first pattern of the specified step and pattern memory can be accessed by the user while the sequencer is in Standby The Idle state outputs the entire pattern set of the specified step and pattern memory cannot be accessed while the sequencer is idling The selections for this pull down control are Table 5 88 Finish Mode Settings Setting Description Standby Go to Standby after sequence completes ldle Go to Idle after sequence completes The relevant VXlplug amp play function is e tat964 setFinishSequence Finish Mode Step This control sets the finish mode step number The relevant VXlplug amp play API function is e tat964 setFinishSequence Soft Front Panel Operation 5 120 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Stop Mode This pull down control programs the stop mode The stop mode controls what action a CPU generated stop or a triggered stop will perform if received The selections for this pull down control are Table 5 89 Stop Mode Settings Setting Description Disable Stop signal will be ignored
145. index only visible in indexed timing mode The relevant VXlplug amp play API function is e tat964 querySequencerTimingSet Execute Panel Modes and Settings There are ten controls that set the execution mode settings Start Arm Selector This slide selects whether the Execute Idle or Execute command buttons arm or start the specified action See Execute Idle and Execute command button descriptions Astronics Test Systems Soft Front Panel Operation 5 117 Model T940 User Manual Publication No 980938 Rev K Channel Drivers This pull down control programs the channel drivers The selections for this pull down control are Table 5 86 Channel Drivers Settings Setting Description Disabled All the channel drivers are forced off disabled Enabled Channel drivers in normal mode Level and state are determined by pattern code and channel parameters and properties Note The following events can cause force the drivers to be disabled A Watch Dog Timeout if enabled to do so A local or DRS global over current event if enabled to do so A local or DRS global drive fault event if enabled to do so A channel over voltage event for Driver Heceiver modules employing this feature The relevant VXIplug amp play function is V tat964 setDriverEnable This control allows power to be applied to those D R boards which require power It also enables the isolation relays to be closed if they
146. panel 2 Data Sequencer B Enables set the Execute DSB gt View gt Sequence Events panel 3 Driver Receiver Board A Enables set in the Execute gt DSA gt View gt Driver Receiver Events panel 4 Driver Receiver Board B Enables set in the Execute gt DSB gt View gt Driver Receiver Events panel 5 Digital Board The events that can generate an interrupt depend on the specific hardware installed The Digital Board can generate these two events 1 CPU Interrupt 2 Sequencer FPGA Temperatu re Alert Access this panel from the menu bar Config Interrupts Soft Front Panel Operation 5 72 Astronics Test Systems a Publication No 980938 Rev K Model T940 User Manual Condition Event True Event False Event Es VXIO 2 INSTR Configure Inte co jm DSA DSB DRA DRB Figure 5 37 Configure Interrupt This control indicates that the interrupt condition is currently true The relevant VXI plug amp play API function is e tat964_querylnterruptCondition This control enables a VXI interrupt to be generated when any of the associated hardware groups enabled event bits goes from false to true The relevant VXlIplug amp play API function is e tat964 setlnterruptMode This control enables a VXI interrupt to be generated when any of the associated hardware groups enabled event bits goes from true to false The relevant VXlplug amp play API function is e tat964 setl
147. precondition the pipeline with NOT Pass There are two options for clearing a pipeline of depth N to NOT Pass generate an error a If the Jump Basis is not qualified use Seq Step with a jump to self for a count of For the one Pattern in this step have an expect condition which is known to Fail generate an Error Advanced Topics 8 22 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual b If the Jump Basis is qualified use a Seq Step with a jump to self for a count of N and set CONDEN high e g or for the one pattern in this step For the one Pattern in this step have an expect condition which is known to Fail generate an Error To generate an Error there must be at least one channel which has an expect which is the complement of the level that is driving that channel One can of course drive one channel and expect the complement if that won t adversely affect the UUT e g it s an unused channel But there s more to consider in this case Since we re falling through on a Pass do we want it to be a Valid Pass As described above a Valid Pass is one where there were no channel Errors but it also says that there was at least one channel with an expect condition If this additional qualification of a Pass is important then the Pass Valid Mode also needs to be enabled Non Pipelined handling of Pass Fail with default settings Since the Erro
148. provides an interface to IEEE Std 1445 formatted files that can be generated from automatic test program generators such as LASAR to seamlessly integrate with the DRM This interface provides the capability for the System to utilize the various features of IEEE Std 1445 to support guided probe Astronics Test Systems Introduction 1 3 Model T940 User Manual Publication No 980938 Rev K fault dictionary and complex patterns and timing set s Migration Tools and Translators The optional Migration Tools and Translators support many legacy test systems from a variety of manufacturers Test programs from supported systems are easily translated without extensive code rewriting Driver Receiver Board Options The DRM currently has the following Driver Receiver board types available DR1 Driver Receiver The DR1 features e Channels 32 single ended LVTTL Relay Isolation on all and AUX channels e Selectable resistive input load to VCC 3 3 V ground or both e Direct or 100 ohm selectable output impedance e Auxiliary channels Four LVTTL with selectable output impedance and resistive input load Four LVTTL Four ECL single ended or differential DR2 Driver Receiver The DR features e Channels 32 differential LVDS e Auxiliary channels FourLVDS FourLVTTL Four ECL single ended or differential DR3e Driver Receiver The DR3e features e Channels 32 single ended variable voltage or 16 differentia
149. queryAdcAverage DR4 Voltage Monitor Panel and Controls VXI0 2 INSTR DRA Voltage eel x Monitor Voltage a ga 1 Positive gt Negative Signal AD Signal CD Signal GND 5 ogr Figure 5 103 DR4 Voltage Monitoring Panel Mux Signal This control is used to program the mux tree to select the signal routed to the ADC The signal selection includes any of the channels as well as test debug signals for factory use The relevant VXlplug amp play functions are e tat964_setAdcMuxSignal Channel This control selects the channel number when the Mux Signal is set to DSA Channels or DSB Channels The relevant VXI plug amp play API functions are e tat964_setAdcMuxSignal Monitor Voltage This control displays the selected mux signal voltage Astronics Test Systems Soft Front Panel Operation 5 171 Model T940 User Manual Publication No 980938 Rev K The relevant VXlplug amp play functions e tat964 queryAdc e tat964 queryAdcAverage Mode This control sets the monitor signal mode when the Mux Signal is set to Monitor A or Monitor B The relevant VXIplug amp play functions are e tat964 setGroupMonitorSignal Positive Signal This control sets the positive monitor signal when the Mux Signal is set to Monitor A or Monitor B The relevant VXlplug amp play API functions are e tat964 setGroupMonitorSignal Negative Signal This control sets the negative monit
150. re designated to be closed by the Connect State Note The following Driver Receiver Event will automatically force the V and V power switch off or not allow it to be turned on protecting the module pin arivers V too high V too low V V Delta too great Temperature Fault detected OVP detect DR3e DRI and UR14 A ground fault or PC Error will not shut the V and V off The relevant VXI plug amp play function is Execute Idle Step e iat964 setPowerConnect This control sets the idle step number for the Idle command button operation Soft Front Panel Operation 5 118 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play function is e tat964 setldleSequence Execute Step This control sets the step number for the Execute command button operation The relevant VXlplug amp play API functions e tat964 executeSequence e tat964 armSequence Burst This control sets the burst count for the Execute command button operation The burst count determines how many times the sequence will be looped A count of 0 causes continuous looping Maximum burst count is 1048576 The relevant VXIplug amp play function is e tat964_setBurstCount Halt Mode This pull down control programs the halt mode The halt mode determines where execution will halt following either a manual halt Halt command button or an external halt trigger See the Jumping Halti
151. relevant VXlplug amp play API function is e tat964 queryChannelTemp Utility Reference Monitor This panel is available when a UR14 board is installed Soft Front Panel Operation 5 174 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 5 7100 0 Figure 5 107 Utility Reference Monitor Monitor Signal This pull down control selects the signal for the voltage monitor The selections for this pull down control are Table 5 109 UR14 Monitor Signal Settings Setting Description Front Panel Selects the front panel ADC_IN signal ADC IN VRef5 Selects the 5V reference signal Group 1 Compare Selects the CH1 CH8 comparator level Group 2 Compare Selects the CH9 CH16 comparator level Group 3 Compare Selects the CH17 CH24 comparator level Group 4 Compare Selects the CH25 CH32 comparator level The relevant VXlplug amp play API functions are e tat964 queryAdc e tat964 queryAdcAverage Astronics Test Systems Soft Front Panel Operation 5 175 Model T940 User Manual Publication No 980938 Rev K SFP Close Message This panel is used to close the soft front panel Are you sure you want to close DRM SFP VXI0 2 INSTR Figure 5 108 SFP Close Message If Yes is selected the following panel will be displayed Do you want to reset the DRM Figure 5 109 SFP Reset Message The relevant VXlplug amp play API functions
152. single ended or differential Four LVTTL or SE ECL I O Four LVTTL or ECL single ended or differential Three ECL single ended or differential I O TwoLVTTLI O Basic Elements of the DRM System As illustrated in Figure 1 1 the DRM module is comprised of the following major components front panel a Digital Board DB and selected Driver Receiver Introduction 1 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Boards named DRA and DRB for their mounted location A T940 module is shown in the photo as an example The block diagram in Figure 1 2 shows how the various components work together DRA and DRB could be any of the DR boards such as DR1 DR2 DR3e etc offered for the DRM system Power Converter Figure 1 1 Example DRM with Two Driver Receiver Boards DRA and DRB If the DRM has only one Driver Receiver board the front panel will have a blank cover panel where the front connector would have been located Note The DH9 board has a different front connector panel than the others Refer to Appendix for more information about and an illustration of the DR9 Astronics Test Systems Introduction 1 7 Model T940 User Manual Publication No 980938 Rev K POWER DIGITAL BOARD CONVERTER DB PC DRIVER RECEIVER OPTIONAL DATA SEQUENCER DRA VXI BRIDGE INTER MODULE DATA CONTROL SEQUENCER DSB DRIVER RECEIVER DRB Figure 1 2 DRM Digital Resourc
153. the inputs to the V rails Either the front panel DUT_GND signal or SIG GND Pin electronics signal used for calibration Pin electronics signal used for calibration Real time temperature monitors for the pin electronics The Control Logic firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions CONTROL Astronics Test Systems Signals used to program firmware and NV DATA DR3e Driver Receiver Board D 7 Model T940 User Manual DR3e Characteristics Publication No 980938 Rev K Table D 1 DR3e Characteristics Description Characteristics Digital Type Channels Variable Voltage 32 SE or 16 DIFF per Driver Receiver board 64 per VXI slot Per channel relay isolation Output Voltage Ranges Selectable Sequencer 15 V to 17 V VMO 7 V to 24 V VM1 Output Voltage Swing 500 mV to 24 V Output Resolution 5mV Output Accuracy DVH and DVL 50mV 196 of PV Slow Default Medium slew settings 75mV 1 of PV Fast slew setting Output Drive Current Output Impedance Selectable Channel 85 mA typical Source Sink Direct 12 or Series 50 40 Slew Rate Selectable Channel or custom 0 25 V ns 0 7 V ns 1 0 V ns or 1 3 V ns typical Input Threshold
154. the Pipeline Insert CONDEN Qual DRS Linked Errors and PV into the Pipeline Insert Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline Insert DRS Linked Errors and PV into the Pipeline Insert CONDEN Qual DRS Linked Errors and PV into the Pipeline The Pass Valid mode is described below Record Response Insert Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline Insert DRS Linked Errors and PV into the Pipeline Insert CONDEN Qual DRS Linked Errors and PV into the Pipeline Jump test conditions are programmed on the Edit gt Data Sequencer A B gt Sequence Steps panel PnP tat964 setSequenceJump ARI EndPtgStep The relevant VXIplug amp play and ARI functions are e API tat964_setSequenceJump e ARI EndPtgStep Advanced Topics 8 16 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual B VXI0 2 INSTR Edit DSA Sequence Step 1 Data 1 00 nspercount 2 Pattems intemal TOCLK ClocksperPattem Las 8 PER 2 100 Sequence Timeout Jump Type Reset vw Mma vj i Retum Always pu Count p Step Not PASS False x0 x0 Fa Step Not FAIL Sequence Flag 1 Step FAIL T cue Sequence Flag 2 Sequence FAIL SS Jump Trigger 1 True Jump Trigger 1 Not True
155. the rest of the device However this panel shows all of the Pin Electronics device temperatures at once in their relative positions on the Driver Receiver board so one can see where the hot spots are en a 2 CHi7 18 CHO3 CH04 CH19 CH05 CHOG moe pad ET sae E 100 00 r E 0005 30 00 9 30 00 30 0029 30002 30 00 98 3000 9 30 0079 3000 30 0079 3000 40 06 39 11 37 31 38 30 41 48 39 01 38 37 39 98 39 18 41 15 CH07 CHO08 CH23 24 CHO9 10 CH22 100 00 pag wt und mi 00 acl 3000 8 30002 30 00 4 30 00 30 0078 30 00 30 00 40 28 39 04 i 40 55 40 93 3974 7 28 28 CH27 CH28 CH14 CH25 CH26 CH12 Y d gel 00 pd m 00 ped 2 30 00 98 30 00 100 9 30 00 30 00 30 00 30 00 40 85 2 2975 41 99 42 34 41 33 AUX3A AUXAA CH32 AUXIA AUX2A CH29 CH30 CH15 CH16 md zd 100 00 oe pad pud s 30 0079 3000 30 00 9 30 00 30 0078 3000 30 0029 30 00 9 30 00 98 3000 39 77 39 82 40 54 40 06 41 49 39 93 39 94 38 79 40 65 40 76 Figure 5 104 DR3e Chip Temperature Astronics Test Systems Soft Front Panel Operation 5 173 Model T940 User Manual Publication No 980938 Rev K oe 100 00 30 00 9 30 00 34 26 33 50 Em 32 06 AUXIA 2 100 00 100 00 100 00 100 00 100 00 100 00 30 0079 30 00 30 0079 30 00 30 00 9 30 00 38 83 35 01 37 67 35 78 37 14 36 89 Figure 5 106 UR14 Chip Temperature The
156. to the TTL output buffers Auxiliary Data outputs from the Data Sequencer to the TTL output buffers Auxiliary Response High inputs to the Data Sequencer from the TTL input buffers Eight TTL signals used to input or output test signals DR4Driver amp Receiver I O OPTIONAL TERMINATION CONFIGURATION Power Configuration The default termination of the TTL AUX I O is a series 50 ohms The pull up and pulldown positions are unpopulated Optional termination configurations can be specified as a Special by contacting the factory The DR4 Power is supplied by VXI Backplane power Figure E 4 illustrates the distribution of power to the channel groups 24V 12V 12V 24V Positive Regulator DRIVER Negative CHANNELS Regulator X16 Positive Regulator DRIVER RECEIVER Negative CHANNELS Regulator X16 Hem pue Regulator DRIVER RECEIVER CHANNELS Regulator X16 Figure E 4 DR4 Power Configuration DR4 Driver Receiver Board E 6 Astronics Test Systems Publication No 980938 Rev K DR4 Characteristics Model T940 User Manual Table E 1 DR4 Characteristics Description Characteristics Digital Type Channels Variable Voltage 48 SE or 24 DIFF per Driver Receiver board 64 per VXI slot Per channel relay isolation Output Voltage Ranges 0Vto 31V 15 5 V to 415 5 V 31 V to 0 V Output Level Granularity Output Voltage Swing Per channel Drive High and Drive L
157. value translation Astronics Test Systems Soft Front Panel Operation 5 87 Model T940 User Manual Table 5 73 ASCII Binary Data Format Publication No 980938 Rev K Pattern Code ASCII Binary Value N 10 lt 2 15 5 6 gt Flag Code Bit15 Bit 14 Code 3 2 1 0 Probe Expect Bit 13 through Bit 8 cm 0 1 2 18 19 1A 1B 1C 1D 1E 1F 20 Soft Front Panel Operation 5 88 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Binary Probe Expect Bit 13 through Bit 8 21 g 3F The ASCII characters are in four groups of eight characters and one line per pattern A fifth column of four characters is present if flags and probe expect is included 00000002 00000000 00000000 00000000 8000 00000000 30000000 00000000 00000000 8000 The first column contains the data for channels 8 through 1 The second column contains the data for channels 16 through 9 The third column contains the data for channels 24 through 31 The fourth column contains the data for channels 32 through 25 The fifth column contains the flag and probe expect data followed by 2 trailing zeros Each column contains the pattern code for eight channels the least signifi
158. whereby one can do single stepping without corrupting the counting and or logging of Errors This limitation is defined in the Section 12 When finished doing single stepping click Resume The relevant VXlIplug amp play and ARI functions are e API tat964_resumeSequence e ARI ResumePtg The last six types of Halt Modes cover Halt Modes on various types of Pass Fail conditions In these modes set the desired condition and then click Execute The relevant VXlIplug amp play and ARI functions are e API tat964_executeSequence e ARI ExecutePtg Do not click Halt before Execute Click Resume when you want to proceed to the next conditional Halt if more are expected As before the Halt Mode be changed between Resumes To finish the Primary Sequence without any further Halts change the Halt Mode to Disable Notes 1 The Pass Fail Basis applies to conditional Halting Thus one can Halt on all Pattern Pass or Fail conditions or only those qualified with CONDEN 2 When pipelined these Halts occur the depth of the pipeline later 3 In non pipelined mode there is a max data rate where that one can do conditional Halting without corrupting the counting and or logging of Errors as shown in Section 12 Pipelined Depth Calculation Capture Delay CD is the total time from a beginning of the first pattern to when the data can be captured for Jumping or Halting on Pass Fail CD Local B
159. 0 User Manual Block Diagram This section describes the basic hardware configuration of the DR9 Driver Receiver DRA or DRB The DR9 is comprised of four major logic sections as shown in Figure H 2 Auxiliary Driver amp Receiver I O DR9 Driver amp Receiver I O Control Logic Firmware amp NV Data AUX DATA 5 8 AUXILIARY Pavey gt DRIVER AUX RH 5 8 RECEIVER CONTROL VO CH DATA 1 24 CH 1 24 ACH 1 24 MONITOR DR9 DRIVER OC 1 24 amp EXTFORCE RECEIVER VO OVERVOLT TEMPMON VO CONTROL DUT GND TEMPMON OVERVOLT Le Losie mse p FIRMWARE amp NV DATA VO CONTROL Figure H 2 DR9 Driver Receiver Block Diagram Astronics Test Systems DR9 Driver Receiver Board H 3 Model T940 User Manual Publication No 980938 Rev K Auxiliary Driver amp Receiver Figure H 3 illustrates the configuration and control of AUX5 8 LVTTL Driver amp Receiver AUX EN 5 8 AUX DATA S 8 74LVC2G125 74LVC2G125 AUX RH 5 8 CONTROL Figure H 3 Auxiliary Driver amp Receiver I O Block Diagram Signal Descriptions AUX EN 5 8 Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX RH 5 8 Auxiliary Response High inputs to the Data Sequencer from the LVTTL input buffers CONTROL Signals used to control isolation relays AUX 5 8
160. 0 and J201 connectors pinouts depend on the Driver Receiver DR boards that are installed Refer to the Appendix of the specific DR board for connector interface information PWR Connector DRA DRB Power and Signals The PWR connector is an option on the T940 which is used to supply external power to DR3e Driver Receiver boards and can be used to supply DRM Front Panel 3 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual multi function signals MFSIG and grounds to all boards Figure 3 3 PWR Connector Table 3 1 PWR Connector Pinout Connector Name Connector Name 1 DRB 5 DRB V 2 DRB MFSIG 6 DRA MFSIG 3 DRA V 7 DRA GND 4 DRB GND 8 DRA V Front Panel Connectors Table 3 2 lists the manufacturer s part numbers and the Astronics Test Systems ordering numbers for the DRM mating connectors Table 3 3 lists the part and ordering numbers for the DRM cable assemblies Table 3 2 Mating Connector Part Numbers Connector Manufacturer amp Part ATS Order Number Number J200 J201 mate 101A0 6000EC 40892 J200 J201 103A0 12R1 00 Included with 40892 flat cable backshell for the above PWR Amphenol T3505 001 408091 Table 3 3 Cable Assembly Part Numbers Description ATS Order Number T940 coaxial cable 17 positions both ends IDC terminated 602715 XXX Front Panel Signal Flat Shielded Cable 1 p
161. 0 mV min Output Drive Current typical Source Sink 8 mA Impedance Skew Channel to Channel 100 Q in parallel with 20K pull up pull down bias resistors to establish a True level if unconnected lt 3 ns drive and compare Auxiliary I O Channels per Driver Receiver board LVDS 4 Differential with 20K bias resistors LVTTL 4 Single ended ECL 4 Single ended or Differential AUX I O is bi directional Per channel relay isolation on ECL I O Data Rate max 50 MHz input and output Astronics Test Systems DR2 Driver Receiver Board C 5 Model T940 User Manual Power Requirements Publication No 980938 Rev K Table C 2 DR2 Power Requirements Voltage Peak Current Dynamic Current 5 V 500 mA 25 mA 5 2 V 355 mA 25 mA 2 V 350 mA 8 5 mA 12 V 0 0 12V 0 0 24 V 0 0 24V 0 0 Environmental Temperature Operating 0 C to 45 C Storage 40 C to 70 Humidity non condensing 0 C to 10 C Not controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 596 to 7596 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 Rise 2 DR2s Max 2 4 lps 8 9 mmH 0 Typ 2 4 lps 4 5 mmH 0 Front Panel Current Requirements NA MTBF ground benign DR2 305 905 hours T940 180 885 hours T940 DR2 113 670 hours T940 DR2 DR2 69 804 hours Dimensions 20 x
162. 0 ns steps with a range of 40 ns to 85 899345920 sec The pulse period is not required for Single Start and Single Step mode The relevant VXIplug amp play API function is e iat964 setPulsePeriod This input control is used to specify the pulse generator delay from the start of the sequence or sequence step Delay is not applicable when the Pulse Generator is in Continuous mode Soft Front Panel Operation 5 36 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Width If the resolution is 10 ns the delay is programmed in 10 ns steps with a range of 20 ns to 42 949672970 s with an uncertainty of 5 ns If the resolution is 20 ns the delay is programmed in 20 ns steps with a range of 20 ns to 85 899345920 s with an uncertainty of 5 ns The relevant VXIplug amp play API function is e tat964 setPulseDelay This input control is used to specify the pulse generator width If the resolution is 10 ns the width is programmed in 10 ns steps with a range of 0 to 42 949672950 s If the resolution is 20 ns the width is programmed in 20 ns steps with a range of 0 to 85 8993459 s If the width is equal to or greater than the period in Continuous and Continuous Start mode then the result will be a continuously true pulse If the width plus the delay is greater than the period in Continuous and Continuous Start mode then the pulse width will be reduced proportionately and vanish at some point The releva
163. 0 power converter V PC Negative bias power required for operation of the Pin Electronics devices from the T940 power converter DUT_GND FP _ This signal comes from the UUT and can be used to offset the reference levels up to 3 V Excursions of DUT GND Astronics Test Systems DR9 Driver Receiver Board H 7 Model T940 User Manual MF SIG CONTROL GND REF V V OVERVOLT DUT GND EXTFORCE EXTSENSE TEMPMON Firmware amp NV Data Publication No 980938 Rev K beyond 390 mV with respect to signal ground yields a GND FAULT signal Multi Function signal output to the PWR connector Signals used to program the features of the DR9 Driver Receiver board This is the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements Fused and switched positive bias power required for operation of the Pin Electronics devices Fused and switched negative bias power required for operation of the Pin Electronics devices Real time over voltage detector circuit monitors Driver and Receivers to protect the pin electronics Also clamps the inputs to the V rails Either the front panel DUT_GND signal or SIG GND Pin electronics signal used for calibration Pin electronics signal used for calibration Real time temperature monitors for the pin electronics The Control Logic firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field
164. 1 Select DRA or DRB if installed using the Driver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The default measurement delay is 100 ms Increase this value to give the calibration points more time to settle Programmable Channel Calibration 6 18 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature Hit the Continue button when the required temperature is reached If the DRM temperature reaches 80 the process will continue automatically If the temperature reaches 80 C the process continues automatically DRM Calibration Warmup Temperature 100 00 60 00 40 00 10 00 47 00 Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution Review the results in the Status window Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for CMH and CML in the field controls These values are not in engineering units 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the U
165. 1 2 of 10 ns The relevant VXIplug amp play function is e tat964 setSystemClockParameters SCLK Mode SCLK Offset Synthesizer Freq MHz This input control is used to specify the Frequency Synthesizer setting The valid frequency range is from 40 kHz to 500 MHz Setting the control to 0 turns off the frequency synthesizer The relevant VXIplug amp play API function is e tat964 setFreqSynth Synthesizer Ref Source This pull down control programs the frequency synthesizer reference source The selections for this pull down control are Table 5 24 Synthesizer Ref Source Settings Setting Description Internal Reference source set to internal 20 MHz AUX1 AUX12 Reference source set to front panel signal VXICLK10 Reference source set to VXI backplane 10 MHz LCLK50 Reference source set to VXI backplane LCLK100 2 VXI 4 0 slot 0 and chassis are required The relevant VXI plug amp play API function is e tat964_setFreqSynth Reference Freq MHz This input control is used to specify the external reference frequency and only appears when an external synthesizer reference source is selected In these cases the frequency synthesizer needs to be scaled so that it can produce the desired output frequency given the nominal external reference frequency The valid external reference frequency range is from 5 MHz to 80 MHz The relevant VXlIplug amp play API function is e tat964_setFreqSynth Astronics Test
166. 1 24 Table l 9 Auxiliary Channel 1 26 Table 1 10 Table 1 11 Table 1 12 Table 1 13 Table 1 14 Table 1 15 Table 1 16 Table 1 17 Table 1 18 Power Requirements including Power Converter power consumption 1 26 Environmierital 2 te Ete oett ete e Eten e ET 27 URTA ROSOUICES Nm 1 29 Connector Pinout by Pin 1 30 J3B Connector Pinout by Pin l 31 J2A Connector Pinout by Pin 1 31 J3B Connector Pinout by Pin 1 32 J1A Connector Pinout by Pin Number 1 32 J1B Connector Pinout by Pin Number 1 32 Test Systems xxix Model T940 User Manual Publication No 980938 Rev K DOCUMENT CHANGE HISTORY Revision Date Description of Change A 10 6 2009 Document Control release B 1 18 2012 EO Added T940 variant and DR3e amp DR7 boards Updated software screens and specifications C 4 17 2012 00132 Added information regarding DR9 option ECNO00901 Updated manual to add driver updates and functionality impacts ECNO02110 Updated specifications and added additional board clarifications as well as the procedure E 2 6 2013 to install a DR9 board Updated soft front panel operation to reflect
167. 1 4 FFFF w 4 FFFF Fun ves meo Update Section ors x Delete Allows the user to delete Section Two calibration data stored internally Saved calibration data can be restored using the restore feature e g File Load DRA Calibration Astronics Test Systems Programmable Channel Calibration 6 25 Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank Programmable Channel Calibration 6 26 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 7 Specifications Each Digital Resource Module DRM is comprised of a Digital Board DB and one or two Driver Receiver D R boards This section contains the specifications the Digital Board DB and its logic The specifications for each available Driver Receiver board are included in a separate appendix included in this manual Timing Characteristics Internal Data Rate using the 500 MHz master clock 15 256 kHz to 50 MHz with CPP 1 59 6 Hz Min with CPP 256 Internal I O Data Rate using the Freq synthesizer at 40 kHz as the master clock 1 22 Hz Min with CPP 1 0 048 Hz Min with CPP 256 Timing Set Options 3 256 Timing Sets with 4 phases and 4 windows and 4K sequence steps 1K Timing Sets with 4 phases and 4 windows and 1K sequence steps one for each sequence step 4K Timing Sets with 1 phase and 1 window and 4K sequence steps one f
168. 14 V e V must be lt 9 V The table below lists the recommended power converter settings for calibration for each voltage mode Table 6 2 Recommended Power Converter Settings Voltage Mode Type 1 or Type 3 4 15V to 17V 12 to 12 5 to 15 7V to 24V 10 to 9 7 to 7 Warm up Period Most equipment is subject to a small amount of drift when it is first turned on To ensure accuracy turn on the power to the T940 module and allow it to warm up to the desired operating temperature before beginning the calibration procedure Recommended Test Equipment For the DR3E DRY and UR14 the recommended equipment for adjustments is listed in Table 6 1 Test instruments other than those listed may be used only if their specifications equal or exceed the required characteristics Also listed below are accessories required for calibration Programmable Channel Calibration 6 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 6 3 Recommended Calibration Equipment Equipment Model No Manufacturer Digital Multimeter 34401 or equivalent Keysight J9A J9B funnel cal fixture DR9 UR14 408626 Astronics Test Systems J9A J9B pigtail cal fixture DR9 UR14 408626 001 Astronics Test Systems IDC 50 calibration adapter DR3e CIB 409531 050 Astronics Test Systems Basic Setup The T940 DRM should be installed in a High Pow
169. 2 2 eR qp Re EUER vb MERE code eee Naess C 4 Control Logi Cari n 4 5 5 Signal DesctiptiOlis itcm e MAILS Le C 5 2 cdi e a i I C 5 Power 2 444 4 080 ARAKEA TANPE KES CARENE ARATAT C 6 Environmental ode am cedat ed C 6 DR2 Signal Description cocer er i bee a E ET ad C 7 DRA l O Gharinels 4200 ed eei e e peti eei tens C 7 Astronics Test Systems xiii Model T940 User Manual Publication No 980938 Rev K DRB I O Channels 201 02 124 11 21 enter C 10 eite aet esee e der e Pe At dee rA Tee auae C 12 err n m IIT 13 D D 1 DR3e Driver Receiver Board nennen nnn ananas nnne nnn nnne nnns D 1 e cete Mee eet d epe re P ee OO D 1 Front Panel Co
170. 3 Level Power Converter Setting Units 12to 12 15to 5 10to 10 5to 7 5 15 Oto 24 2to 22 DVH max 12 5 10 7 15 24 22 V DVH min 10 13 5 8 5 4 4 1 0 5 V DVL max 8 5 2 8 5 4 5 11 6 21 18 8 V DVL min 11 6 15 10 5 5 0 2 V CVH max 9 2 6 9 5 12 2 21 8 19 4 V CVH min 12 15 10 5 5 0 2 V CVL max 9 2 6 9 5 12 2 21 8 19 4 V CVL min 12 15 10 5 5 0 2 V CMH max 9 2 6 9 5 12 2 21 8 19 4 V CMH min 12 15 10 5 5 0 2 V CML max 9 2 6 9 5 12 2 21 8 19 4 V CML min 12 15 10 5 5 0 2 V Power Requirements Table D 4 VXI Power Requirements with Front Panel Power Dynamic Voltage Peak Current 45V 3 3 A 330 mA 5 2 V 2 50 A 25 mA 2 V 110 mA 10 mA 12 V 21 mA 7 mA 12 V 18 1 mA 17 mA 24 V 9 9 mA 9 8 mA 24 V 0 0 Table D 5 VXI Power Requirements not including Power Converter power consumption Dynamic Voltage Peak Current Current 45V 3 3 A 330 mA 5 2 V 2 50 A 25 mA 2 V 110 mA 10 mA 12 V 21 mA 7 mA DR3e Driver Receiver Board D 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Dynamic Voltage Peak Current Current 12 V 18 1 mA 17 mA 24 V 9 9 mA 9 8 mA 24 V 0 0 Note Use the DR3e Current Estimator calculation tool to estimate the power converter power consumption from the 12V
171. 4 NC Astronics Test Systems DR4 Driver Receiver Board E 11 Model T940 User Manual Publication No 980938 Rev K Pin No Signal Pin No Signal 25 SIG GND 75 SIG GND 26 CH45 76 NC 27 SIG GND 77 SIG GND 28 46 78 29 SIG GND 79 SIG GND 30 CH47 80 NC 31 SIG_GND 81 SIG_GND 32 CH48 82 NC 33 SIG_GND 83 SIG_GND 34 AUX1 B 84 AUX7 B 35 SIG GND 85 SIG GND 36 AUX2 B 86 AUX8 B 37 SIG GND 87 SIG GND 38 AUX3 B 88 NC 39 SIG GND 89 NC 40 AUX4 B 90 NC 41 SIG GND 91 NC 42 AUX5 B 92 NC 43 SIG GND 93 NC 44 AUX6 B 94 NC 45 SIG GND 95 MPSIGB 46 PBUT B 96 BCLK 47 PMODE B 97 SIG GND 48 SIG GND 98 EXTFORCE B 49 NC 99 SIG GND 50 MONITOR B 100 NC Calibration Driver Receiver boards are calibrated for each range before shipment Field calibration can be performed using Soft Front Panel or call Table E 7 Calibration Settings ADC Monitor Factory calibrated stored in EEPROM CHANNEL Measure Factory calibrated stored in EEPROM DVH DVL Field upgradable stored in EEPROM CVH CVL Field upgradable stored in EEPROM DR4 Driver Receiver Board E 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix F DR7 Driver Receiver Board DR7 Features e Channels 32 differential RS 422 485 e Auxiliary chann
172. 4dll 10 9 2015 1 02 File fol calData 14045122 txt 10 9 2015 12 57 Text D EB tato Front Panel ico 1 13 2012 10 16 AM Icon tat964 Front Panel c 10 2 2015 7 11 C Sour E E tat964 Front Panel exe 10 8 2015 1 31 Applic 8 tat964 Front Panel h 9 9 2015 11 02 tat964 Front Panel prj 10 8 20151 31PM LabWii tat964 Front Panel uir 9 9 2015 11 02 AM LabWi tat964 c 10 8 2015 1 29PM 5 E tat964 chm 10 8 2015 1 30 Compi tat964 def 7 18 2012 716 PM Export W tat964 doc 10 8 20151 31PM Micros tat964 fo 08005 1 29PM _ e a Figure 5 95 Verify Select Directory Panel Note Pin electronic calibration data is stored for each voltage mode 15 V to 17 V and 7 V to 24 V Verification should be performed with the power converter setting that was used for calibration for each voltage mode Soft Front Panel Operation 5 164 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure 5 96 Verify Warm up Panel Verification will begin when the temperature reaches 80 C or the Continue command button is pressed The unit should be verified at its normal application temperature Refer to the Calibration Temperature section in Chapter 6 for more information Once verification has begun progress data is displayed in the Status control DRM Calibration Driver Receiver Calibrate Function Serial Number gor
173. 50 MONITOR A 100 NC DR4 Driver Receiver Board E 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DRB 1 0 Channels J201 Table E 5 DR4 DRB I O Channels J201 Name Pin No Description CH33 CH48 Various Bi directional High speed channels SIG GND Various Signal Ground reference AUX1 B 34 Bi directional General Purpose TTL I O pin AUX2 B 36 Bi directional General Purpose TTL I O pin AUX3 B 38 Bi directional General Purpose TTL I O pin AUX4 B 40 Bi directional General Purpose TTL I O pin AUX5 B 42 Bi directional General Purpose TTL I O pin AUX6 B 44 Bi directional General Purpose TTL I O pin AUX7 B 84 Bi directional General Purpose TTL I O pin AUX8 B 86 Bi directional General Purpose TTL I O pin Table E 6 DR4 Pinout by Pin Number DRB Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH33 52 CH49 3 SIG_GND 53 SIG_GND 4 CH34 54 CH50 5 SIG_GND 55 SIG_GND 6 CH35 56 CH51 7 SIG_GND 57 SIG_GND 8 CH36 58 CH52 9 SIG_GND 59 SIG_GND 10 CH37 60 CH53 11 SIG_GND 61 SIG_GND 12 CH38 62 CH54 13 SIG_GND 63 SIG_GND 14 CH39 64 CH55 15 SIG_GND 65 SIG_GND 16 CH40 66 CH56 17 SIG_GND 67 SIG_GND 18 CH41 68 NC 19 SIG_GND 69 SIG_GND 20 CH42 70 NC 21 SIG_GND 71 SIG_GND 22 CH43 72 NC 23 SIG_GND 73 SIG_GND 24 CH44 7
174. 57 19 SIG GND 69 SIG GND 20 CH42 70 CH58 21 SIG_GND 71 SIG_GND 22 CH43 72 CH59 23 SIG_GND 73 SIG_GND 24 CH44 74 CH60 25 SIG_GND 75 SIG_GND 26 CH45 76 CH61 27 SIG_GND 77 SIG GND 28 CH46 78 CH62 29 SIG_GND 79 SIG_GND 30 CH47 80 CH63 31 SIG_GND 81 SIG_GND DR1 Driver Receiver Board B 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal Pin No Signal 32 CH48 82 CH64 33 SIG_GND 83 SIG_GND 34 AUX1 B 84 AUX7 B 35 SIG GND 85 SIG GND 36 AUX2 B 86 AUX8 B 37 SIG GND 87 SIG GND 38 AUXS3 88 AUX9 B 39 SIG GND 89 AUX9 B 40 AUX4 B 90 AUX10 B 41 SIG GND 91 AUX10 B 42 AUX5 B 92 AUX11 43 SIG GND 93 AUX11 B 44 AUX6 B 94 AUX12 45 SIG GND 95 AUX12 B 46 PBUT B 96 BCLK 47 PMODE B 97 SIG GND 48 SIG GND 98 NC 49 NC 99 SIG GND 50 NC 100 NC PWR Connector When connected to an installed DR1 board the PWR connector Figure B 5 only utilizes the pins for the multi function signal MFSIG and signal ground GND The power pins are not connected to the board Figure B 5 Front Panel PWR Connector When installing the Driver Receiver Board be sure that the correctly marked PWR cable inside the module is connected to its specific board the cable marked DRA for the DRA board and marked DRB for the DRB board Incorrect installation may c
175. 6 15 Model T940 User Manual Publication No 980938 Rev K All Monitor ADC All DAC Levels DVH DVL v CVH CVL Vcom High Low ISource ISink 2 Verify that the CVH CVL calibrate function is now in focus Calibrate Function 7 Select Start and End Channels and Measurement Delay Equipment Basic Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 Use the Start and End Channel fields to select the and Auxiliary channels to be calibrated 3 The default measurement delay is 100 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hit the Continue button when the required temperature is reached If the temperature reaches 80 C the process continues automatically Programmable Channel Calibration 6 16 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution Review the results in the Status window Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for CVH and CVL in the field controls These values are not in engineering units 5 Optional Save the
176. 64 Sequencer B Channel Data Enable output from the Data Sequencer to the Open Collector Driver DATA 33 64 Sequencer B Channel Data output from the Data Sequencer to the Open Collector Driver OC 33 64 Sequencer B Channel Over Current detect signals to the Data Sequencer from Open Collector Driver over current detect comparator Depending on Sequencer B settings a detected over current can shut off just the channel or all channels CH 1 32 Data Open Collector Channels These channels be used with high voltage inductive loads The 5V pull up on each channel allows the channel to be used for low speed TTL A current sensor on each channel can programmatically limit the current on a per byte basis INREF 1 4 Programmable input reference detect thresholds There that can be programmed from OV to 20V There are four references one per byte OCREF 1 4 Programmable current detect thresholds There are seventeen levels that can be programmed from 0 to 1A There are four references one per byte UR14 Driver Receiver Board 1 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual ADC Voltage and Temperature Monitoring The ADC Voltage and Temperature Monitoring diagram Figure 1 9 illustrates the Power and Temperature amp control features for the Programmable AUX Channels as well as the voltage reference generation used for the Open Collector I O 0 20V INREF 1 4 1 per byte 4 OCREF thresh
177. 8 28 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual manner with respect to the Master Sequencer To Halt in a pattern period the halt signal must be provided 10 Master Clocks and 40 60ns before the end of the desired pattern period to be refined e Resume options o CPU Resume o CPU Single Step o Probe button o Trailing edge of an External Halt used for System Clutch see example below e Halt Edge Test Clear options static selection o The Halt Edge test flip flop is cleared just before the beginning of the Sequence option 1 o The Halt Edge test flip flop is cleared just before the beginning of the Sequence or just before the beginning of each subsequent Sequence Step option 2 o The Halt Edge test flip flop is cleared just before the beginning of the Sequence or with a CPU Resume or Single Step option 3 Halt Examples Halt on a Pattern Error o Setthe Single Step Type to Halt on Pattern Error Halt on Pattern 6 in Sequence Step 4 like a breakpoint o Setthe Single Step Type to Halt on Sync1 o Setup Sync Pulse 1 to begin a Sync Pulse on Pattern 6 in Sequence Step 4 with a duration of 1 pattern Halt at the end of the Sequence o Setthe Single Step Type to Halt on the last pattern of the Sequence o Start the Sequence Halt on an external Rising Edge signal occurring on the Aux 2 Input o Setthe Halt Source to Aux 2 o Setfor a Rising Edge Test Condition o Set
178. 8 Rev K Model T940 User Manual Setting DSA Control DSB Control DRM Type Secondary DSB Coupled DSA DRS Secondary Secondary DSA and DSB DRS DRS Secondary Coupled Terminator Not Linked DSA DSB Terminator Terminator Linked DSA DSA Terminator Terminator DSA Coupled DRS DSB Terminator Terminator DSB Coupled DSA DRS Terminator Terminator DSA and DSB DRS DRS Terminator Coupled The relevant VXI plug amp play API function is e tat964_setModulelnterconnect Power Converter This pull down control programs the power converter voltage levels so that the driver receiver boards can operate over the specified range The On Off toggle switch enables disables the power converter outputs Ranges and suggested Voltage Mode settings see D R Properties panel Table 5 9 Power Converter Ranges Type 1 and 3 Power Type 4 Power Suggested Voltage Converters Converters Mode Setting 12 to 12 7 to 7 15V to 17V 15 to 5 15 to 2 15V to 17V 10 to 10 10 to 9 15V to 17V 2 to 7 3 to 7 Either mode 5 to 15 5 to 5 Either mode 0 to 24 0 to 16 7V to 24V 2 to 22 2 to 14 7V to 24V The pull down control is disabled dimmed for DR installed power converters The relevant VXlplug amp play API functions tat964_setPowerConverter e tat964_setPowerConverterState Linked Trigger Bus The Linked Trigger Bus LTB signals are used to pass sig
179. 80938 Rev K Model T940 User Manual DRA I O Channels J200 Table D 6 DR3e Channels J200 Name Pin No Description CH1 CH32 Various Bi directional High speed channels DUT GND A 100 Input DUT UUT ground reference All of the Pin Electronics devices have a UUT ground reference input that can be selected to be this signal or signal ground SIG GND Various Signal Ground reference AUX1 A 34 Bi directional General Purpose Programmable pin Also used as the probe input data channel AUX2 A 36 Bi directional General Purpose Programmable pin AUX3 A 38 Bi directional General Purpose Programmable pin AUXA A 40 Bi directional General Purpose Programmable pin AUX5 A 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series 6 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 A 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 A 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 A 90 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX10 A 91 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX11 A 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 A 93 B
180. 80938 Rev K Model T940 User Manual E VXIO 2 1NSTR Set VXI Triggers DSA TTLTRGO Signal Invert TTLTRG1 Signal Invert Sequence Reset 7 Halted v m TTLTRG2 Signal TTLTRG3 Signal Invert DRS Sync Y Driver Disable m TTLTRGA Signal TTLTRG5 Signal Invert Master Reset v None v TTLTRG6 Signal TTLTRG7 Signal Invert None m ECLTRGO Signal Error Pass Valid Figure 8 3 Configure VXI Triggers DSA Panel Note Error and Pass Valid were placed on ECLTRGs This is necessary for high Data Rates gt 20 MHz because the TTLTRG bus has a slow recovery time Table 8 1 describes these signals and explains when they are needed Table 8 1 Summary of When Specific DRS Signals are Needed Signal When needed Error Whenever Error needs to be connected coupled to the Master Sequencer for Jumping Halting Counting or the Logging of Errors in the EAM Pass Valid Needed whenever Pass Valid Mode is enabled Error must also be connected coupled when Pass Valid is used Halted Allows connected coupled Sequencers to have their Pattern Data and Record memories accessible when halted DRS Sync Allows one to detect and create an event that says that that a connected coupled Sequencer is out of sync with the Master Sequencer Sequence Allows a Sequence Reset performed on the Master or any Reset coupled Sequencer to reset all of the Sequencers coupled together in a DRS Note on the Execute Panel this i
181. 89 AUX9 B 90 AUX10 B DR2 Driver Receiver Board C 11 Model T940 User Manual Publication No 980938 Rev K Pin No Signal Pin No Signal 41 AUX4 B 91 AUX10 B 42 AUX5 B 92 AUX11 43 SIG GND 93 AUX11 B 44 AUX6 B 94 AUX12 B 45 SIG GND 95 AUX12 B 46 PBUT B 96 BCLK 47 PMODE B 97 SIG GND 48 SIG GND 98 NU 49 NU 99 SIG GND 50 NU 100 NU PWR Connector When connected to an installed DR2 board the PWR connector Figure C 5 only utilizes the pins for the multi function signal MFSIG and signal ground GND The power pins are not connected to the board E Figure C 5 Front Panel PWR Connector When installing the Driver Receiver Board be sure that the correctly marked PWR cable inside the module is connected to its specific board the cable marked DRA for the DRA board and marked DRB for the DRB board Incorrect installation may cause you to be connected to the wrong MFSIG If the board is preinstalled by the factory the cables have already been installed Table C 7 shows the connection names pins and descriptions for the PWR connector DR2 Driver Receiver Board C 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table C 7 PWR Connector Name Pin No Description DRB MFSIG 2 Output Multi function signal DRB DRB GND 4 Power supply signal return DRB DRA MFSIG 6 Output
182. 9 Pattern Set Data File Menu The import export formats include Soft Front Panel Operation 5 86 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pattern data as ASCII Hex Pattern data as ASCII String e Pattern data as Binary e Pattern data and flags as ASCII Hex e Pattern data and flags as ASCII String e Pattern data and flags as Binary The relevant VXIplug amp play API functions are e tat964 savePatternMemory e tat964 loadPatternMemory Import Export File Format The import export file format consists of a header followed by the data The header identifies the number of patterns and the format and must be the first line of the file Header Format The format of the header is TAT964 PAT DUMP dd lt nnnnnn gt where dd is the format 00 Pattern Data ASCII Hex 01 Pattern Data Binary 02 Pattern Data ASCII String 03 Pattern Data Flags and Probe Expect ASCII Hex 04 Pattern Data Flags and Probe Expect Binary 05 Pattern Data Flags and Probe Expect ASCII String nnnnnn is the number of patterns Data Format The data format consists of three types ASCII hex Binary and ASCII string In addition each of the three data formats can include or exclude the pattern flags and probe expect ASCII Hex The ASCII hex format represents pattern data as viewable ASCII hex characters one character per channel The following table lists the pattern code to ASCII Binary
183. 94 AUX12 45 SIG GND 95 AUX12 B 46 PBUT B 96 BCLK 47 PMODE B 97 SIG GND 48 SIG GND 98 NC 49 NC 99 SIG GND 50 NC 100 NC PWR Connector When connected to an installed DR8 board the PWR connector Figure G 5 only utilizes the pins for the multi function signal MFSIG and signal ground GND The power pins are not connected to the board L Figure G 5 Front Panel PWR Connector When installing the Driver Receiver Board be sure that the correctly marked PWR cable inside the module is connected to its specific board the cable marked DRA for the DRA board and marked DRB for the DRB board Incorrect installation may cause you to be connected to the wrong MFSIG Table G 7 shows the connection names pins and descriptions for the PWR connector Table G 7 PWR Connector Name Pin No Description DRB MFSIG 2 Output Multi function signal DRB DRB GND 4 Power supply signal return DRB DRA MFSIG 6 Output Multi function signal DRA DRA GND 7 Power supply signal return DRA Astronics Test Systems DR8 Driver Receiver Board G 11 Model T940 User Manual Calibration Publication No 980938 Rev K Table G 8 Calibration Settings Inter module timing deskew Static End of cable deskew Static DR8 Driver Receiver Board G 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix H DRO9 Driver Receiver Board DR9 Features
184. 940 User Manual Accessories Model Publication No 980938 Rev K Description Ordering Part Front Panel Signal Flat Ribbon Cable 1 per Driver Receiver Board Front Panel Signal Flat Shielded Cable 1 Driver Receiver Board Coaxial Cable 22 positions Auxiliary I O from T T940 303 001 T940 master to CRB slot 408124 001 Front Panel Power Cable 1 per Digital _ Resource Module with F P power option 1940 305 xxx Single Ended Coaxial Cable 44 positions 3 408125 XXX unterminated T940 Coaxial IDC Cable 17 positions both NA ends IDC terminated 4 per 64 channel 602715 XXX module used with DR9 and DR3e modules N A A C type LBUS Lockout Key 455540 N A C type LBUS Lockout Key 455541 N A T940 Inter Module Mode Jumper 408382 N A External Probe Module Right Angle 405389 001 N A External Probe Module Flush 405389 002 N A External Probe Module Handheld Probe Kit 6139 External Probe Module Cable 3 feet 408378 036 N A External Probe Module Cable 10 feet 408378 YYY Note 1 In the above table XXX is the length in feet 2 Inthe above table YYY is the length in inches from 36 to 120 in 12 inch increments 3 For more information about Lockout Keys refer to the Front Panel LBUS Lockout Keys section in Chapter 3 Introduction 1 12 Astronics Test Systems Publication No 980938 Rev K
185. 940 power converter V PC Negative bias power required for operation of the Pin Electronics devices from the T940 power converter V FP Positive bias power required for operation of the Pin Electronics devices comes from the T964 Front Panel DR3e Driver Receiver Board D 6 Astronics Test Systems Publication No 980938 Rev K V FP DUT FP MF SIG CONTROL GND REF V y OVERVOLT DUT GND EXTFORCE EXTSENSE TEMPMON Firmware amp NV Data Model T940 User Manual PWR connector provided by external power supplies Negative bias power required for operation of the Pin Electronics devices comes from the T964 Front Panel PWR connector provided by external power supplies This signal comes from the UUT and can be used to offset the reference levels up to 3 V Excursions of DUT beyond 390 mV with respect to signal ground yields GND FAULT signal Multi Function signal output to the PWR connector Signals used to program the features of the DR3e Driver Receiver board This is the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements Fused and switched positive bias power required for operation of the Pin Electronics devices Fused and switched negative bias power required for operation of the Pin Electronics devices Real time over voltage detector circuit monitors Driver and Receivers to protect the pin electronics Also clamps
186. 980938 Rev K o Halton a Pattern o Halt on the last Pattern of the Seq Step Branches and Loops are ignored o Halt on the last Pattern of the Sequence as though there were Burst of 1 o Halton a Pattern where Sync Pulse 1 is Asserted o Halton a Pattern where Sync Pulse 2 is Asserted o Halt on Pattern Error or CONDEN qualified Pattern Error o Halton the last Pattern of the Seq Step if there was a Step Failure or CONDEN qualified Step Failure o Halton the last Pattern of the Sequence if there was a Burst Failure or CONDEN qualified Burst Failure e Timing requirements for a Halt on Pattern Error Step Failure or Burst Failure o Seethe Jumping Halting Counting and Logging on Pass Fail section for the detailed timing requirements and additional information e The CPU can also perform a Resume at any time which can allow normal operation to proceed This CPU resume can be used to o Resume after single stepping o Resume other types of Halt conditions o Resume any Pause condition External Halt Operations e External Halt Test Sources static selection o None o AnyAux Input 1 of 12 o Any TTLTRG Bus input 1 of 8 o Either ECL TRG Bus input 1 of 2 o Channel Test 1 master channel test e External Halt Test Conditions static selection o High o Low o Rising Edge o Falling Edge e External Halt Timing Considerations o The external signal used to initiate the halt must occur in a timely Advanced Topics
187. A and SIMB set to IMB IMJMPR position is a don t care Primary driver disabled The DRM is not coupled to a DRS DSA and DSB are not linked Independent Linked SIMA and SIMB set to IMA IMJMPR position is a don t care Primary driver disabled The DRM is not coupled to a DRS DSA and DSB are linked Primary DSA Coupled SIMA set to LBUSA SIMB set to IMB IMJMPR position set to primary LBUSA connected to termination Primary driver enabled The DRM is coupled to a DRS DSA is coupled to a DRS DSB is independent Primary DSA and DSB Coupled SIMA and SIMB set to LBUSA IMJMPR position set to primary LBUSA connected to termination Primary driver enabled The DRM is coupled to a DRS DSA and DSB are coupled to a DRS Secondary DRM Inter Module Modes These modes apply to a DRM that is jumpered as a Secondary Independent Not Linked SIMA set to IMA and SIMB set to IMB IMJMPR position is a don t care Primary driver disabled The DRM is not coupled to a DRS DSA and DSB are not linked Independent Linked SIMA and SIMB set to IMA IMJMPR position is a don t care Primary driver disabled The DRM is not coupled toa DRS DSA and DSB are linked Secondary Not Linked SIMA set to IMA and SIMB set to IMB IMJMPR position set to secondary LBUSA connected to LBUSC Primary driver disabled The DRM is coupled to a DRS DSA and DSB are not linked and independent Secondary Linked SIMA and SIMB set to IMA IMJMPR po
188. ASTRONICS TEST SYSTEMS Talon Instruments Model T940 64 Channel Digital Resource Module User Manual Publication No 980938 Rev K Astronics Test Systems Inc 4 Goodyear Irvine CA 92618 Tel 800 722 2528 949 859 8999 Fax 949 859 7139 atsinfo astronics com atssales astronics com atshelpdesk gastronics com _http Awww astronicstestsystems com Copyright 2009 by Astronics Test Systems Inc Printed in the United States of America All rights reserved This book or parts thereof may not be reproduced in any form without written permission of the publisher THANK YOU FOR PURCHASING THIS ASTRONICS TEST SYSTEMS PRODUCT For this product or any other Astronics Test Systems product that incorporates software drivers you may access our web site to verify and or download the latest driver versions The web address for driver downloads is http www astronicstestsystems com support downloads If you have any questions about software driver downloads or our privacy policy please contact us at atsinfo astronics com WARRANTY STATEMENT All Astronics Test Systems products are designed to exacting standards and manufactured in full compliance to our AS9100 Quality Management System processes This warranty does not apply to defects resulting from any modification s of any product or part without Astronics Test Systems express written consent or misuse of any product or part The warranty also does not apply to
189. Active Digital Board Figure 5 11 Instrument Menu Table 5 5 Instrument Menu Descriptions Menu Option Description Self Test Runs the self test Full RAM Test Runs the full RAM test Calibrate Displays the calibration panel Update Flash Displays a file select dialog to select the Flash update file Temp Monitor Displays the temperature monitor panel Voltage Monitor Displays the voltage monitor panel Chip Displays the chip temperature panel Temperature Help Menu The Help Menu is used to open the instrument driver help contents and display the SFP programming information panel B User Pubic Docume osa File Config Edit Execute Instrument Help Contents Fl AIsTRONIC About T964 SFP TEST SYSTEMS Figure 5 12 Help Menu Soft Front Panel Operation 5 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 6 Help Menu Descriptions Menu Option Description Contents Displays the VXIPNP API help file table of contents About DRM Displays revision data for the DRM Soft Front Panel executable About DRM Driver tat964 Front WIN Framework Rev 4 0 WINS5 Framwork Rev 4 0 WINNT Framework Rev 4 0 Windows CVI Revision 2010 VISA 5 1 2 T964 Assembly Rev A Figure 5 13 About DRM Driver Screen Opening a VXI DRM Session Starting the SFP initiates a search for a
190. Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table D 1 lists the min and max levels based on the power converter type 1 or 3 setting Table H 3 DR9 I O Min Max Levels Power Converter Type 1 or Level Power Converter Setting Units 12t0 12 15to 5 10to 10 5to 7 5 15 0 24 2to 22 DVH max 12 5 10 15 24 22 V DVH min 10 13 5 8 5 4 4 1 0 5 V DVL max 8 5 2 8 5 4 5 11 6 21 18 8 V DVL min 11 6 15 10 5 5 0 2 V CVH max 9 2 6 9 12 2 21 8 19 4 V CVH min 12 15 10 5 5 0 2 V CVL max 9 2 6 9 12 2 21 8 19 4 V CVL min 12 15 10 5 5 0 2 V CMH max 9 2 6 9 12 2 21 8 19 4 V CMH min 12 15 10 5 5 0 2 V CML max 9 2 6 9 12 2 21 8 19 4 V CML min 12 15 10 5 5 0 2 V Power Requirements Table H 4 DR9 Power Requirements not including Power Converter power consumption Voltage Peak Current Dynamic Current 12V 16 9 mA 15 mA 12V 18 1 mA 17 mA 5V 2200 mA 1 240 mA 2V 0 0 5 2V 0 0 24V 11 4 mA 20 mA 24V 0 0 Note Use the DR9 Current Estimator calculation tool to estimate the power converter power consumption from the 12V 24V power rails This tool is available upon request from Astronics Test Systems at atssales astronics com Astronics Test Systems DR9 Driver Receiver Board H 11 Model T940 User Manual Publication No 980938 Rev K En
191. Astronics Test Systems Soft Front Panel Operation 5 23 Model T940 User Manual Publication No 980938 Rev K Table 5 20 Record Mode Settings Setting Description Typical Usage Disabled The contents of the record memory will not Setting Record Mode to Disabled change during the next burst if Step Record insures that the record memory will not Mode is set to either None or Record be written to when Step Record Mode is Count set to either None or Record Count This means that if errors were recorded in a previous burst they will remain in memory throughout the current burst Non The contents of the record memory will be Setting Record Mode to Non Error 0 Error 0 set to 0 during the next burst if Step Record when Step Record Mode is set to either Mode is set to either None or Record None or Record Count clears the record Count memory during the next burst insuring that any previously recorded errors will not persist The relevant VXI plug amp play API function is e tat964 setSequencerRecordMode Config Data Sequencer A B The Configure Data Sequencer A B panel is used to program the clock settings sequence control signals timeout values overcurrent and record settings Access this panel from the menu bar Config Data Sequencer x Where x is the sequencer you wish to configure iad c Users Public Documents DSAwalk1 cfg File Config Edit Execute Instrument Help Module
192. C Mask A one masks the corresponding channel s capture data Bit 0 corresponds to CH1 and bit 31 corresponds to CH32 The relevant VXlplug amp play API function is e tat964 setSequencerAttribute Static State This pull down control programs the sequencer static state The static state is used to enable or disable the channel static mode setting For sequencer revisions prior to 0 21 when enabled the pulse generator is locked from user settings and is programmed to generate the output delay and response delay signals for static channels When disabled the pulse generator is unlocked and set to power up defaults and all channels are set to dynamic operation Sequencer revisions 0 21 and later have dedicated static timing and do not require the pulse generator Thus the pulse generator is available for user settings The selections for this pull down control are Soft Front Panel Operation 5 52 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 54 Static State Settings Setting Description Off Disable static operation On Enable static operation The relevant VXlplug amp play API function is e tat964_setStaticState Configuring the Channels Configuring the channels is a three step process 1 Select the channels 2 Program channel parameters 3 Configure channel properties Access this panel from the menu bar Config Channels
193. CE Absolute accuracy 5 ns With respect to Channel1 Requires field calibration PROBE CALIBRATION FACTORY Trim pot adjustment of the contact detect compare level May also be done in the field if the user has a 50 pF cap and a 5 MO resistor and can get access to the trim pot PROBE CALIBRATION FIELD Utilizes AUX A 2 provided by the D R board to provide a reference signal on the Probe Module s calibration connector which will be used for Probe Compensation Calibration and DC Timing Calibration to the Probe tip MINIMUM DETECTABLE PULSE WIDTH 10 ns BUFFERED PROBE OUTPUT Provided on the UR14 as PROBE OUT Output range Same as input from the Probe Module 5V Output Impedance Source terminated at 500hms in the Probe Module Output accuracy from Probe tip to terminated output 50 mV 1 From the Probe tip thru the Probe Module to the UR14 and out the PRBOUT connector Bandwidth from Probe tip to terminated output 50 MHz From the Probe tip thru the Probe Module to the UR14 and out the PRBOUT connector 12V 62 mA minimum 82 mA maximum max 16 5 Vp p 70 Mhz 12V 49 mA minimum 69 mA maximum max 16 5 Vp p 70 Mhz Astronics Test Systems UR14 Driver Receiver Board 1 25 Model T940 User Manual Publication No 980938 Rev K Auxiliary Channels Table l 9 Auxiliary I O Channel Characteristics Descripti
194. Collector Output Channels with Single threshold Input Comparator Output Voltage Compliance 0 to 30 V Output Data Rate Static to 5 kHz Output Data Delay 82 us from Phase to output Input Data Rate Static to 500 kHz UR14 Driver Receiver Board 1 20 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Description Characteristics Input Data Delay 220 ns with at least 2 V overdrive with respect to the programmed input reference level 2 00 ns when less than 1 V of overdrive Driver Thermal Protection If Channel FET exceeds 175 C Driver Over voltage protection Driver clamps at 42 V suitable for inductive loads Programmable OC detect 0 1 4 thresholds 4 thresholds 1 per byte OC detect levels 16 selections in Amps 0 06 0 12 0 19 0 25 0 31 0 37 0 44 0 5 0 56 0 63 0 69 0 75 0 81 0 87 0 94 1 Input Sink Current Up to 1 A per channel or 1 A max per byte On board pull up 1 to 5 V default allows each channel to be used as low speed TTL Output Impedance 520 per channel Input References 4 input references INREF 1 Channels 1 8 INREF 2 Channels 9 16 INREF 3 Channels 17 24 INREF 4 Channels 25 32 Input Compare range 0 to 20 V Input Reference resolution 5 mV steps Input Compare Accuracy 30 mV accuracy PROGRAMMABLE CHANNELS Table 3 Programmable Channel Characteristics Description Character
195. Control Bus connecting the VXI Bridge to the Data Sequencers and the Driver Receiver board s Control Logic UR14 Driver Receiver Board 17 Model T940 User Manual Publication No 980938 Rev K External Probe Module The T940 UR14 is specifically configured to support the external probe module There are two module types a Flush Mounted PCB Assembly Figure 11 and a Right Angle Assembly Figure 12 QT e MN Figure 11 External Probe Module Flush Mount K i Figure 12 External Probe Module Right Angle UR14 Driver Receiver Board 1 18 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure 13 illustrates the External Probe Module Right Angle with the 6139 Probe connected and the probe tip installed in the Probe Cal BNC Figure 13 External Probe Module with Probe External Probe Module Table 1 External Probe Module Characteristics Description Notes Interfaces to legacy panels Two types of assemblies Can mount vertically or horizontally Provides a BNC connector for the Probe with and isolation provision when mounted to the customer panel Provides a BNC connector for Compensation and DC Calibration calibrating the Probe at the Probe Tip Utilizes a cable to connect the Lengths from 36 to 120 in 12 Probe Module to the D R increments Board PN 408378 XXX PN 408378 036 36 PN 408378 120 120 As
196. Counter Timer is provided for each sequencer n agonanDE n Figure 5 84 Timer Counter Panel Function This pull down control programs the counter timer function The selections for this pull down control are Soft Front Panel Operation 5 152 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 101 Counter Timer Function Settings Setting Description Frequency Initiate command button performs a frequency measurement on input 1 Period Initiate command button performs a period measurement on input 1 Time Interval Initiate command button performs a time interval measurement from input 1 to input 2 Totalize Initiate command button counts the input 1 transitions during input 3 Timed Totalize Initiate command button counts input 1 transitions during the specified aperture time Positive Pulse Initiate command button performs a time interval measurement from the rising edge input 1 to the falling edge of input 1 Negative Pulse Initiate command button performs a time interval measurement from the falling edge input 1 to the rising edge of input 1 The relevant VXlplug amp play API function is e tat964 setCounterFunction e tat964 queryCounterFunction Input 1 3 Source These controls allow the counter input source to be selected The selections for this pull down control are Table 5 102 Counter Timer Input 1 3 Source
197. D 95 AUX12 B 46 PBUT B 96 BCLK 47 PMODE B 97 SIG GND 48 SIG GND 98 EXTFORCE B 49 GNDREF B 99 SIG GND 50 MONITOR B 100 DUT GNDB PWR Connector The PWR connector Figure D 6 supplies both positive and negative bias power as well as multi function signals to the DR3e Driver Receiver Board if the external front power option is purchased The DR3e does not require front panel power 1 22 6 f 5 Figure D 6 Front Panel Optional DR3e PWR Connector When installing the DR3e Driver Receiver Board with the front panel power option be sure that the correctly marked power cable inside the module is connected to its specific board the cable marked DRA for the DRA board and marked DRB for the DRB board Astronics Test Systems DR3e Driver Receiver Board D 17 Model T940 User Manual Publication No 980938 Rev K Table D 8 shows the connection names pins and descriptions for the power connector Table D 10 PWR Connector Name Pin No Description DRB V 1 Positive supply for the DRB Board Pin Electronics devices DRB MFSIG 2 Output Multi function signal DRB DRA V 3 Positive supply for the DRA Board Pin Electronics devices DRB GND 4 Power supply signal return DRB DRB V 5 Negative supply for the DRB Board Pin Electronics devices DRA MFSIG 6 Output Multi function signal DRA DRA GND 7 Power supply signal return DRA DRA V 8 Negative supply for the DRA Board Pin Electronics devices C
198. DRM is coupled to a DRS DSA and DSB are not linked and independent e Terminator Linked SIMA and SIMB set to IMA IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled The DRM is coupled to a DRS DSA and DSB are linked e Terminator DSA Coupled SIMA set to LBUSC and SIMB set to IMB IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled DSA is coupled to a DRS DSB is independent e Terminator DSB Coupled SIMA set to IMA and SIMB set to LBUSC IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled DSB is coupled to a DRS DSA is independent e Terminator DSA and DSB Coupled SIMA and SIMB set to LBUSC IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled DSA and DSB are coupled to a DRS Examples Each DRM in the following examples have 32 channels on DRA and 32 channels on DRB e g DR3E Individual sequencers can be run independently even if they are intermixed within a module chain One Group of 384 Channels Module T940 Inter Module Mode DRM1 Primary Linked DRM2 Secondary DSA and DSB Coupled DRMS Secondary DSA and DSB Coupled DRM4 Secondary DSA and DSB Coupled DRM5 Secondary DSA and DSB Coupled DRM6_ Terminator Linked Astronics Test Systems Functional Description 4 7 Model T940 User Manual Publication No 980938 Re
199. DSA 8 19 Figure 8 16 Setting the Pass Fail Clear Control in the Edit DSA Sequence Step Panel 8 21 Figure 8 17 Setting the Jump Pass Fail Mode in the DSA Advanced Options Panel 8 22 Figure 8 18 Setting the Halt Mode in the Execute DSA 8 25 Figure B 1 DR1 Driver Receiver Block 44 B 2 Figure B 2 Auxiliary Driver amp Receiver I O Block B 3 Figure B 3 DR1 Driver amp Receiver I O Block B 4 Figure B 4 J200 and J201 Connectors ssssssssssssssssseeeeee enne nennen nennen nennen B 7 Figure B 5 Front Panel PWR B 11 Figure C 1 DR2 Driver Receiver Block C 2 Figure C 2 Auxiliary Driver amp Receiver I O Block C 3 Figure 3 DR2 Driver amp Receiver I O Block Diagram C 4 Figure C 4 200 2201 1 8 an 7 Figure 5 Front Panel PWR Connector cccceceecceeeeeeeeeeeeeeeeceeeeceaeeesaaeeeeeeeceaeeesaeeseaaeseneeeeaas C 12 Figure D 1 DR3e Driver Receiver Block Diagram D 2 Figure D 2 Auxiliary D
200. Dat 5 3 pp 5 4 Title heated i Pis tee mead 5 4 ii Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual SFP Main Panel Menu Bar sssssssssssssseese eee entere enne 5 5 Pile MEU a dude 5 5 MENU tut euet Le ee 5 6 Edit 5 7 Execute eere de dee A epo HERES eee Le ta od eed eee 5 7 Instrument ae A teste Te tee de 5 8 tiat ccc 5 8 Opening VXI DRM 5 9 Configuring the Global Hardware Parameters sess 5 10 Configure Module nnns entree nes 5 10 Inter Module Mode 7 iiir aeterne 5 11 Power Converterin ie aai a ou ttt e tt t At e ts ead 5 13 Linked Trigger ceteri tee timeo ire Ete RN 5 13 ETBA Signal dci pedea ei aes dde cds 5 14 pc C 5 15 Bie ELE 5 15 5 15 Group ttrbutes s nc EIL M Ee eed 5 15 tere IE eie fe Ee re e tutes tee e EP TERRA 5 16 enr eer 5 16 en emp 5 16 SOW
201. E DETECT GND GND PROBE CAL PROBE IN LEGEND B Pini GND NC O Signal oe oe oe oe oe oe oe oe oe CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 NC NC NC NC AUX4 B AUX3 B AUX2 B AUX1 B NC NC NC NC AUX8 B AUX7 B AUX6 B AUX5 B GND J3A UTILIITY HIGH VOLTAGE amp USER I O 50 PINS NC NC NC NC J1B NC UR14 NC METER Pin 7 20 NC PINS NC GND VEXT VEXT AUX9A AUX10 A AUX11 A J1B AUX11 AUX11 B AUX10 B PINS AUX10 B AUX9 B AUX9 B AUX12 A AUX 8 12 UR14 FRONT PANEL yo MAPPING Figure 14 Front Panel Connectors UR14 Driver Receiver Board 1 28 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual UR14 I O J1A J1B J2A J2B J3A J3B Table 12 UR14 Resources Name Description 1 CH32 Bi directional Open Collector Channels PROBE AUX1 A Probe input channel or bi directional general purpose programmable level auxiliary I O PROBE CAL AUX2 A Probe calibration output channel or bi directional general purpose programmable level auxiliary I O AUX 1 4 B Programmable I O AUXS3 A Bi directional general purpose LVTTL AUXA A Probe support signal or bi directional general purpose LVTTL AUX 5 9 A LVTTL or ECL These channels share a pin on the A
202. EN Errors Qual Local Qual Local Qual Local Errors Errors Errors DRS Linked Don t Count Count Count Count Errors DRS Linked DRS Linked DRS Linked Errors Errors Errors Qual Don t Count Count BERREN Count BERREN Count BERREN DRS Linked Errors Qual Qual Qual DRS Linked DRS Linked DRS Linked Errors Errors Errors For logging Errors into the EAM refer to Table 8 5 Table 8 5 Cross Reference of Step Record Mode to Error Address Basis Il d Step Record Mode Error Address Record Count Record Error Record Basis Response Local Don t log any Don t log any Log Local Errors Log Local Errors Errors Errors in the EAM in the EAM Qual Local Don t log any Don t log any Log BERREN Log BERREN Errors Errors Qual Local Qual Local Errors in the Errors in the EAM EAM DRS Linked Don t log any Don t log any Log DRS Linked Log DRS Linked Errors Errors Errors in the Errors in the EAM EAM Qual Don t log any Don t log any Log BERREN Log BERREN DRS Linked Errors Errors Qual Qual DRS Linked DRS Linked Errors in the Errors in the EAM EAM Advanced Topics 8 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual In a DRS Local Errors can be counted logged in coupled sequencers while the Master sequencer is simultaneously counting logging DRS Errors In addition one could use a different BERREN when counting logging Qualified Local Errors if that is useful But there are limitations See App
203. Edge w MRE Middle Rising Edge x HGH Middle Glitch High y HGL Middle Glitch Low z MHG Middle High Glitch 8 HLG Middle Low Glitch 1 MPH Middle Pulse High 2 MPL Middle Pulse Low 3 Middle Pulse Middle 4 RE Rising Edge 5 REG Rising Edge Glitch 6 REGH Rising Edge Glitch Middle 7 v Mask off compare 8 Figure 5 48 Probe Codes Astronics Test Systems Soft Front Panel Operation 5 83 Model T940 User Manual Publication No 980938 Rev K Table 5 71 Probe Expect Codes Expect Probe Code Shortcut Description Code Signal starts above RH and crosses the FE a RH and RL once and ends below RL C9 Signal starts above RH crosses RH once crosses RL three or more times and ends FEG b below RL E9 Signal starts above RH crosses RH once crosses RL two or more times and ends FEGM between RL and RH E1 H d Signal remains above RH 05 Signal starts above RH crosses the RH HG e two or more times and ends above RH 55 Signal starts above RH crosses RH once HM f and ends between RL and RH 41 Signal starts above RH crosses RH and RL two or more times and ends above HP g RH F5 Signal starts between RL and RH crosses the RH two or more times and ends HGM h between RL and RH 51 Signal starts above RH crosses RL and RH three or more times and ends below HPL i RL F9 Signal starts above RH crosses RH three or more times RL two or more t
204. Error Address Memory The relevant VXlIplug amp play API function is e tat964 setSequenceRecordMode This command button displays the Edit Timing Set panel so the phase and window settings can be programmed for the selected sequencer step see Soft Front Panel Operation 5 106 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Editing the Timing Sets in Chapter 5 n igi VXIO 2 INSTR Edit DSA Sequence Step 0 Timing 1 00 ns pe E So Figure 5 58 Edit Timing Set Panel The relevant VXlplug amp play API function is e tat964 setSequenceTimingData Patterns If the Patterns control reads 0 then this command button displays the Initialize Step Pattern Set panel This panel allows the user to assign a block of pattern memory to the current sequence step The Number of Patterns control specifies how many patterns will be assigned and initialized to the current sequence step The Memory Offset control specifies the location of the first pattern If the offset is set to 1 the driver automatically increments the offset to the next higher multiple of 4 from the previous offset Any other number between 0 and 262140 in multiples of 4 sets the offset Click Apply to initialize the patterns or Close to cancel Astronics Test Systems Soft Front Panel Operation 5 107 Model T940 User Manual Publication No 980938 Rev K DEL Initialize Step Pattem Set
205. Event Reset to Event Replicate a System Clutch function using the Aux 8 input an active high clutch o Setthe Halt Source to Aux 8 o SetaHigh Test Condition Note A high on Aux 8 causes a halt at the end of the Pattern and a low Astronics Test Systems Advanced Topics 8 29 Model T940 User Manual Publication No 980938 Rev K resumes a Resume is not needed in this case Thus the actual duration of the Halt will most likely be longer than the duration of the System Clutch Halt Notes When Halted the CPU may access the Data Record and Probe memories A Resume will be ignored while memory access is granted An external Halt can only halt on a Pattern When the timing requirements are not met for completing the capture of the response data prior to the Halt the response data and related error counting logging will be corrupted See the Jumping Halting Counting and Logging on Pass Fail section for the detailed timing requirements and additional information Pause Operations A Pause operation is defined within a Sequence Step Thus it can be constrained to occur only at particular times during the Sequence Pause Test Condition Choices settable in each Seq Step o None o Always o Pause Test 1 True or Not True o Pause Test 2 True or Not True o Phase 1 Rising Edge RE o Phase 1 Falling Edge FE o Phase2RE o Phase2FE o Phase 3 RE o Phase 3 FE o Phase 4 RE o Phase 4 FE Pause Test 1 2 Sources
206. I Local Bus A used to connect adjacent modules VXI Local Bus C used to connect adjacent modules Control signals used to set relay driver and mux settings Inter Module signals from DSA Selected Inter Module signal used by DSA Inter Module signals from DSB Selected Inter Module signal used by DSB T940 inter module jumper This jumper sets the DRS mode as primary secondary or terminator Note Refer to DRS Inter Module Mode Control in Chapter 2 Installation for information on the Inter Module Control jumper settings The DRM utilizes the following VXI backplane resources to enable adjacent DRMs to be synchronized together to form a DRS VXI Local Bus A C LBUSA LBUSC Sequencer A on the primary module drives all twelve LBUSA signals Phases Windows Clocks and Jump Flag Both Sequencers can receive LBUSA and LBUSC signals e VXI Triggers Used for passing information between the DRS modules e g error flag synchronization flag reset signal driver disable signal channel handshake T940 Inter Module Mode Settings The VXIplug amp play API function that sets the inter module mode is tat964 setModulelnterconnect The valid settings with reference to figure 4 3 are Astronics Test Systems Functional Description 4 5 Model T940 User Manual Publication No 980938 Rev K Primary DRM Inter Module Modes These modes apply to a DRM that is jumpered as a Primary Independent Not Linked SIMA set to IM
207. I O pin AUX8 A 86 Bi directional General Purpose TTL I O pin Table E 4 Pinout by Pin Number DRA Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH1 52 CH17 3 SIG_GND 53 SIG_GND 4 CH2 54 CH18 5 SIG_GND 55 SIG_GND 6 CH3 56 CH19 7 SIG_GND 57 SIG_GND 8 CH4 58 CH20 9 SIG_GND 59 SIG_GND Astronics Test Systems DR4 Driver Receiver Board E 9 Model T940 User Manual Publication No 980938 Rev K Pin No Signal Pin No Signal 10 CH5 60 21 11 SIG GND 61 SIG GND 12 CH6 62 CH22 13 SIG GND 63 SIG GND 14 CH7 64 CH23 15 SIG GND 65 SIG GND 16 CH8 66 CH24 17 SIG GND 67 SIG GND 18 CH9 68 NC 19 SIG GND 69 SIG GND 20 CH10 70 NC 21 SIG GND 71 SIG GND 22 11 72 23 SIG GND 73 SIG GND 24 CH12 74 NC 25 SIG GND 75 SIG GND 26 CH13 76 NC 27 SIG_GND 77 SIG GND 28 CH14 78 NC 29 SIG GND 79 SIG GND 30 CH15 80 NC 31 SIG GND 81 SIG GND 32 CH16 82 NC 33 SIG GND 83 SIG GND 34 AUX1 A 84 AUX7 A 35 SIG_GND 85 SIG_GND 36 AUX2A 86 AUX8 A 37 SIG_GND 87 SIG_GND 38 AUX3 A 88 NC 39 SIG_GND 89 NC 40 AUX4A 90 NC 41 SIG_GND 91 NC 42 AUX5 A 92 NC 43 SIG_GND 93 NC 44 AUX6 A 94 NC 45 SIG_GND 95 MPSIGA 46 PBUT_A 96 BCLK A 47 PMODE_A 97 SIG_GND 48 SIG_GND 98 EXTFORCE A 49 NC 99 SIG_GND
208. I functions are e tat964_setErrorParameters e ARI AssignPatTimeGroup Advanced Topics 8 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual VX10 2 1NSTR Configure DSA Settings 2 00 ns per co 1 21 Good Local v Record Type Local Qual Local DRS Linked Output to Input Disable Qual DRS Linked Phase vl Disable 7 Figure 8 8 Setting Error Count Basis the Configure DSA Settings Panel The Basis for Logging Errors into the EAM is set on the same Panel The relevant VXlIplug amp play and ARI functions are e tat964_setErrorParameters e ARI AssignPatTimeGroup VX10 2 INSTR Configure DSA Settings 2 00 ns per co c2 S Figure 8 9 Setting Error Address Basis in the Configure DSA Settings Panel In both cases the available choices are the same e Local Astronics Test Systems Advanced Topics 8 11 Model T940 User Manual Publication No 980938 Rev K e Qual Local e DRS Linked e Qual DRS Linked But what is counted or logged varies based on the Step Record Mode For Counting Errors refer to Table 8 4 Table 8 4 Cross Reference of Step Record Mode to Error Count Basis Error Count Record Count Record Error Record Basis Response Local Don t Count Count Local Count Local Count Local Errors Errors Errors Errors Qual Local Don t Count Count BERREN Count BERREN Count BERR
209. IG_GND 100 NC Name Pin No Description CH33 CH64 Various Bi directional High speed TTL channels SIG_GND Various Signal Ground reference AUX1 B 34 Bi directional General Purpose TTL I O pin AUX2 B 36 Bi directional General Purpose TTL I O pin AUX3 B 38 Bi directional General Purpose TTL I O pin AUX4 B 40 Bi directional General Purpose TTL I O pin AUX5 B 42 Bi directional General Purpose TTL I O pin 50 Ohm series AUX6 B 44 Bi directional General Purpose TTL I O pin 50 Ohm series AUX7 B 84 Bi directional General Purpose TTL I O pin 50 Ohm series AUX8 B 86 Bi directional General Purpose TTL I O pin 50 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 B 90 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 B 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 93 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 B 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 B 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT B 46 Bi directional Probe Button Input PMODE B 47 Output Probe Support Output BCLK B 96 Output Reserved Astronics Test Systems DR8 Driv
210. Jump Trigger 2 True Jump Trigger 2 Not True Jump Trigger 3 True Jump Trigger 3 Not True Jump Trigger 4 True Jump Trigger 4 Not True Figure 8 13 Setting the Jump Condition in the Edit DSA Sequence Step Panel On this pull down you ll see that six Jump Conditions based on Pass and Fail The Halt Modes are Programmed on the Execute gt DSA DSB panel The relevant VXlplug amp play and ARI functions are e API tat964_setHaltMode e ARI AssignPtgHaltMode Astronics Test Systems Advanced Topics 8 17 Model T940 User Manual Publication No 980938 Rev K E VXIO 2 INSTR Execute x Idle Active O Pause VaN Enabed Y 1 D R Alert lt 2 v Finish Mode Step Standby Y 30 CRC Type ws Stop PG ess Record Count Pattem Fail 0 Sequence Fail Pattem Pass Step Pass Sequence Pass Figure 8 14 Setting the Halt Mode in the Execute DSA Panel Here you ll see six Halt Modes qualified either on Pass or Fail conditions What a Pass and Fail means is described in the next section called Understanding Pass and Fail Understanding Pass and Fail The following items define the uses of Pass and Fail conditions Pass and are only used for Jumping and or Halting on Pass Fail conditions e Halting on a Pass Fail condition may be done on a Pattern a Sequence Step or a Sequence as though the Burst Count is set to 1 e Jumping on a Pass Fail condition may
211. LIARY AUX DATA 9 12 DRIVER amp RECEIVER Vo 1 0 CONTROL AUX DATA 1 4 DR2 AUX 1 4 AUX RL1 DRIVER CH DATA 1 32 ks CH 1 32 RECEIVER is CH RH 1 32 RL 1 32 CONTROL p NV DATA Figure C 1 DR2 Driver Receiver Block Diagram Auxilliary Driver amp Receiver Figure C 2 illustrates the configuration and control of AUX5 8 LVTTL and AUX9 12 ECL Driver amp Receiver I O DR2 Driver Receiver Board C 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual AUX EN 5 8 AUX DATA 5 8 p 74LVC2G125 74LVC2G125 AUX RH 5 8 AUX RH 9 12 MC100ELT24 MC100ELT25 AUX DATA 9 12 MC100ELT24 Figure C 2 Auxiliary Driver amp Receiver I O Block Diagram Signal Descriptions AUX EN 5 8 Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX RH 5 8 Auxiliary Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from the Data Sequencer to the ECL output buffers CONTROL Signals used to control isolat
212. M Driver Screen rennen rennen 5 9 Figure 5 14 Opening a VXI DRM 0 2240 00000 eene nennen nnne nennen 5 10 Figure 5 15 Configure Module 5 11 Figure 5 16 Configure Linked Trigger Bus Panel sse 5 14 Figure 5 17 Configure Group Panel a 5 15 Figure 5 18 Set VXI Triggers DSA nennen nnne nennen 5 19 Figure 5 19 Configure DSn Properties 5 21 Figure 5 20 Configure Data Sequencer sssssssssssssssseeeee enne nennen nennen 5 24 Astronics Test Systems xix Model T940 User Manual Figure 5 21 Figure 5 22 Figure 5 23 Figure 5 24 Figure 5 25 Figure 5 26 Figure 5 27 Figure 5 28 Figure 5 29 Figure 5 30 Figure 5 31 Figure 5 32 Figure 5 33 Figure 5 34 Figure 5 35 Figure 5 36 Figure 5 37 Figure 5 38 Figure 5 39 Figure 5 40 Figure 5 41 Figure 5 42 Figure 5 43 Figure 5 44 Figure 5 45 Figure 5 46 Figure 5 47 Figure 5 48 Figure 5 49 Figure 5 50 Figure 5 51 Figure 5 52 Figure 5 53 Figure 5 54 Figure 5 55 Figure 5 56 Figure 5 57 Figure 5 58 Figure 5 59 Figure 5 60 Figure 5 61 Figure 5 62 Figure 5 63 Figure 5 64 Publication No 980938 Rev Gonfigure Clocks
213. M1 Fault VTM2 Fault VTM3 Fault 24 Fault 12 Fault 24 Fault 12 Fault Temp Alarm Chip Alarm I2C Fault Ww OW M M M MM Www ww amp amp ww Ww Ww Ww Ww Ww Ww Ww Ww wow Ww VTM High Current VTM Over Current Figure 5 79 DR4 Driver Receiver D R Events Panel The following DR Driver Receiver event bits are defined Table 5 99 Sequence Status Bit Descriptions Name Description Threshold Group 1 Group 1 V to V delta too large 36 0 Delta Fault Group 2 Group 2 V to V delta too large 36 0 Delta Fault Group 3 Group 3 V to V delta too large 36 0 Delta Fault VTM 1 Fault Power converter VTM1 fault set NA VTM2 Fault Power converter VTM2 fault set NA VTMS Fault Power converter VTM3 fault set NA 24V Fault The 24 V fuse reports open NA 12V Fault The 12 V fuse reports open NA 24V Fault The 24 V fuse reports open NA 12V Fault The 12 V fuse reports open NA VTM Over VTM exceeded output current gt 3 25A Current and shutdown Fault VTM High VTM High current warning gt 2 8A Current Warning Soft Front Panel Operation 5 146 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Enable Condition Event Clear Event Alert Text Name Description Threshold Temp Alarm Temp alarm set from the NA temperature monitor chip Chip Alarm Chip alarm set from the NA driver receiver chi
214. Model T940 User Manual Chapter 2 Installation The following sections discuss the installation procedure for the DRM module into a VXI chassis Before installing the DRM module ensure that the digital board DB DIP switches are set to correct settings for your setup either in the factory default mode or with specific address and mode settings to your test situation Refer to the next several sections for this setup information If you have received a small packet of extra screws with the module place these in a secure location for future use should you add a Driver Receiver board at a later date WARNING The DRM is NOT hot swappable The power to the VXI chassis must be turned off before installing a DRM Plugging the module in before the power is off may result in damage to the electronics Note The following pictures show the DRM with the cover panel removed Figure 2 1 T940 with Two DR7 Boards Installed Astronics Test Systems Installation 2 1 Model T940 User Manual Publication No 980938 Rev K Figure 2 2 T940 with Two DR3e Boards Installed Initial Digital Board DB Switch Setting WARNING Use standard ESD procedures including ground straps and static safe work surfaces whenever handling the DRM or any of its Driver Receiver boards There are three DIP switches on the Digital Board located between the VXI connectors P1 and P2 at the rear end of the board When shipped they are set to current fact
215. Module Panel The following sections describe the Configure Module panel controls Inter Module Mode This pull down control programs the control source for the DSA and DSB sequencers The T940 chain and termination are set via jumpers If a jumper is not installed the DRM can only be configured as Independent Not Linked or Independent Linked The DRM uses the VXI local bus signals to link multiple modules together The inter module configuration options consist of the types shown in Table 5 7 Table 5 7 Inter Module Types DRM Type Description Independent Independent modules do not pass the local bus chain and must not be placed between a Primary and Terminator module Two Independent modes are available 1 Independent Not Linked DSA and DSB are not linked together 2 Independent Linked DSA and DSB are linked Astronics Test Systems Soft Front Panel Operation 5 11 Model T940 User Manual Publication No 980938 Rev K DRM Type Description Primary The Primary module must be located in the rightmost slot position in the VXI chassis relative to the DRM modules that will be coupled DSA provides all the timing for the sequencers that are part of the coupled chain Two Primary modes are available 1 Primary DSA Coupled DSA coupled to DRS and DSB independent 2 Primary DSA and DSB Coupled DSA and DSB coupled to DRS chain Secondary The Secondary module s are the DRMs located between the Primar
216. N GNDREF PROBE CAL PROBE POWER PROBE MODE BCLK PBUT Model T940 User Manual Channel Response Low input to the Data Sequencer from the AUX1 A PROBE IN input receiver Channel Data Enable from the Data Sequencer to the AUX2 A output driver AUX2 A is the PROBE CAL signal on the UR14 and is output only Channel Data output from the Data Sequencer to the AUX2 A output driver AUX2 A is the PROBE CAL signal on the UR14 and is output only Channel Response High input to the Data Sequencer from the AUX2 A PROBE CAL input receiver Control Logic signals to control pin electronics isolation termination and configuration relays Channel Enable from the Data Sequencer to the AUX4 A LVTTL driver AUX4 A is the PROBE COMP signal on the UR14 and is output only Channel Data from the Data Sequencer to the AUX4 LVTTL driver AUX4 A is the PROBE COMP signal on the UR14 and is output only Channel Response High input to the Data Sequencer from the AUX4 A PROBE COMP input receiver When PROBE DETECT is true this input is inactive for the Pin Driver Logic Any GND offsets are applied to the external probe module When not used with the external probe this signal comes from the UUT and can be used to offset the reference levels up to 3 V Excursions of DUT_GND beyond 390 mV with respect to signal ground yields a GND FAULT signal DUT GND can be used to apply this offset to the probe module input Signal path tha
217. Normal Window 3 Mode Window 3 Delay CRC Preload CRC Algorithm Capture Mask Figure 8 17 Setting the Jump Pass Fail Mode in the DSA Advanced Options Panel Normal is one of the default settings included above Legacy enables Option 42 This option is typically used when one is looping a single Pattern looking for a Pass or Fail Specifically one could Jump on NOT Pass or NOT Fail and fall through on a Pass or Fail respectively Option 1 i e Pass Fail Clear Mask must be set on the Seq Step when using this option In some applications this may be known as PATC WAIT This option requires that the Pipeline be preconditioned Case 1 Jump on NOT Fail and fall through on a Fail We want to precondition the pipeline with NOT Fail There are two options for clearing a pipeline of depth N to NOT Fail not generate an Error a If the Jump Basis is not qualified use Seq Step with a jump to self for a count of For the one Pattern in this step have an expect condition which is known to NOT Fail not generate an Error b If the Jump Basis is qualified use Seq Step with a jump to self for a count of and set CONDEN low e g b or for the one pattern in this step this will fill the pipe with NOT Fail Note this case does not require the Pass Valid Mode to be used But it may be used and will have no effect Case 2 Jump on NOT Pass and fall through on a Pass We want to
218. O 10 MHz input and output Description Data Rate max Power Requirements Table F 2 DR7 Power Requirements Voltage Peak Current Dynamic Current 5 V 620 mA 25 mA 5 2 V 355 mA 25 mA 2 V 350 mA 8 5 mA 12 V 0 0 12V 0 0 24 V 0 0 24 V 0 0 Environmental Temperature Operating 0 C to 45 C Storage 40 C to 70 Humidity non condensing 0 C to 10 C Not controlled 10 C to 30 C 5 to 9596 5 RH 30 C to 40 C 596 to 7596 5 RH 40 C to 50 C 5 to 5596 5 RH Altitude 10 000 ft Cooling Required 10 Rise 1 DR7 Max 1 9 lps 1 mmH 0 Cooling Required 10 Rise 2 DR7s Max 2 4 lps 1 mmH 0 MTBF ground benign DR7 305 905 hours T940 180 885 hours T940 DR7 113 670 hours T940 DR7 DR7 69 804 hours Dimensions 20 x 114 x 305 mm EMC Council Directive Emission EN61326 1 2006 Class 89 336 EEC Immunity 61326 1 2006 Table 1 Safety Low Voltage Directive 73 23 EEC Designed to Meet Testing in Progress BS EN61010 1 2010 Designed to Meet Testing in Progress DR7 Driver Receiver Board F 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DR7 Signal Description DRB Figure F 4 J200 and J201 Connectors DRA I O Channels J200 Table F 3 DR7 DRA I O Channels J200 N
219. OETUS uite te niet ear H 1 Front Panel Connectors iiio ues redeo Rr unde pr eet H 1 Block Diagraimi 1 eet ERI IIo Ie ee ira H 3 Auxiliary Driver amp Receiver H 4 Signal Descriptions terere eed ete eti ect i H 4 DRY Driver amp RECEIVER VO 4r c rre FU E EP Eta xe E EE eddie H 4 dL tud eie ee a a E CERE Leti dee H 5 Control H 6 Signal Descriptions 2 2 eR d aerials H 7 Firmware amp NV pa e e o REP UD Ded ra qa GERARD PA H 8 SigiallDescrlptiOls H 8 DR9 Gharacteristics Pati eed eiae H 8 fea I E H 10 Power Requiremients a intet eid dite ceti et edt ceti tedio eg H 11 Environmental 3 5 2 8 dtt i eie ots H 12 DRY Signal Description tco ente edt En en Seas H 13 eee 14 DRB ReESOUICES RE H 16 PEE IEEE C M LIV LIU H 18 SLE H 19 Duns M M MH 1 1 UR14 Driver Receiver Board
220. P delay RO in ns Error Resp Delay Period 11 Master Clocks 16ns Where Advanced Topics 8 26 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual e Local BP delay Independent Linked DRS Local 14ns 16ns BP 1ns DRM 21ns Pause and Halt Capabilities Definitions e A Halt disables the System and Pattern Clocks at the end of the Pattern cycle after all Phases and Windows complete their action e Pause disables the System and Pattern Clocks and freezes the Phases and Windows e Resume generally de asserts a Pause or Halt and allows the normal operation to continue but there are exceptions Applications A Halt can be used to o Replicate the function of a System Clutch o Halt on Error o Halt on a pattern using a Sync pulse or external signal o Establish a breakpoint o Dosingle stepping o Do Probe stepping A Pause be used to o Replicate the function of a Pattern Clutch o Pause the data output when doing a handshake o Pause pattern at a Phase edge or with an external signal o Insert a fixed wait time An external Resume be used as a handshake resume CPU Halt Single Stepping Resume Operations e Single stepping is a Resume Halt combination e CPU Halt Single Step Test Condition Choices static selection o None Astronics Test Systems Advanced Topics 8 27 Model T940 User Manual Publication No
221. Q to 1 KO 8 selections to Vcom Accuracy 30 DUT_GND Reference Input Offset range 3 V Interrupt Voltage 390 mV 50 mV Resistive load 100 K 2 Bypass Relay On or Off Pin Electronics Power Input Supplied by the power converter board UR14 Channel Over voltage Protection Clamped to 0 4 V beyond V or V e Max current 200mA for 10ms Auto Shutdown e DC level within 1 V of V or V e Abys spike exceeding V or V Pin Electronics Monitoring per channel UR14 Driver Receiver Board 1 22 All programmed levels Output and Input levels Temperature Astronics Test Systems Publication No 980938 Rev Model T940 User Manual Description Characteristics Voltage Monitoring V V and Front Panel DUT Hybrid Connection This range is limited by the power converter ranges 1 700 mV at the fastest slew rate Programmable AUX I O Min Max Levels The programmable AUX I O level minimum and maximum values are Connects F P pin to any channel need to disable drive to the channel 40 series impedance 3 MHz bandwidth determined by the V an V bias voltage levels The following table lists the min and max levels based on the V and V level Level Min Max Units DVH V 5 V 3 V DVL V 4 V 7 V CVH V 2 V 7 V CVL V 2 V 7 V Vcom High CMH V 2 V 7 V Vcom Low CML V 2 V 7 V Table 4
222. R1 DR1 66 922 hours Dimensions 20 x 114 x 305 mm EMC Council Directive Emission EN61326 1 2006 Class A 89 336 EEC Immunity EN61326 1 2006 Table 1 Designed to Meet Testing in Progress BS EN61010 1 2010 Designed to Meet Testing in Progress DR1 Driver Receiver Board B 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DR1 Signal Description Figure B 4 J200 and J201 Connectors DRA I O Channels J200 Table B 3 DR1 DRA I O Channels J200 Name Pin No Description CH1 CH32 Various Bi directional High speed LVTTL channels SIG GND Various Signal Ground reference AUX1 A 34 Bi directional General Purpose pin AUX2 A 36 Bi directional General Purpose LVTTL I O pin AUXS3 A 38 Bi directional General Purpose LVTTL I O pin AUX4A 40 Bi directional General Purpose LVTTL I O pin AUX5 A 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 A 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7A 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 A 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V AUX10 A 90 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V AUX10 A 91 Bi directional General P
223. R14 front panel Code Model XXzz Application Code Description Spares Part YYzz DR1 150 LVTTL 32 Channels 50 source termination 405349 002 DR1 110 LVTTL 32 Channels 100 source termination 405349 001 DR2 210 LVDS 32 Channels 100 source termination 405350 Variable Voltage 15 V to 24 V 32 Channels DR3e 3e50 Over voltage 408002 DR7 710 RS 422 32 Channels 100 source termination 405350 101 DR8 850 TTL 32 Channels 50 source termination 405349 102 DR8 810 TTL 32 Channels 100 source termination 405349 101 Variable Voltage 15 V to 24 V DR9 950 24 Direct Analog Test Channels 408248 Utility Resource 32 HV Open Collector channels UR14 1450 probe interface auxiliary interface 408291 Code Power Converter Code Description Model Al Specity for DR3e or DR9 pates Party Type 1 1 VXI 3 0 power converter 24V 405404 001 Type 3 3 VXI 4 0 power converter 24V 405404 003 Type 4 4 VXI 3 0 or 4 0 power converter 16V 405404 004 Model A Installed CIB or Funnel Code Description Spares Part TypeF F VP90 Style Coaxial Funnel available for DR9 and DR9 408257 UR14 UR14 408258 Type F1 F1 Mini VP90 Style Signal Contact Funnel available DR3e 408257 S 2986 for DR3e and UR14 UR14 408258 S 2987 Legacy Compatible Connector CIB Module Dpew m for DR3e DRA DR8 03197 Astronics Test Systems Introduction 1 11 Model T
224. Reeve reet Pee bee 5 115 Idle BED x5 ded te de hastatus 5 115 Active LED usse nit t ueniens 5 115 Halt LED wisn ire te Heri I ee D P cec He ERE Da 5 116 CI tea a 5 116 PED 5 116 RM 5 116 Power Converter Alert in edi ipte eife nda Dt Een pae 5 116 D PUAlent zio in te et e bei eee esie 5 116 Sequence ACIIVO oae i rao depo do cod ete dan aepo EP ut Poder d e 5 117 Coat 5 117 Pattern Address ee it vete E ee PCR eed io ud ve Ee s 5 117 Record t E E He C e a e Ede be 5 117 TIMING Seti ick oa te Oe A ei ee ee A ad 5 117 Astronics Test Systems vii Model T940 User Manual Publication No 980938 Rev K Execute Panel Modes and Settings 5 117 StA Arm Sele iO creber hele etatis rh i aider 5 117 Ghahnnel DriVversisu i tec ote ote a ceterae 5 118 C 5 118 Execute Idle Step 32 ite n ee dte 5 118 Execute Step iin EE 5 119 BU tSE tates ie sae alt See rab cel eed v 5 119 Mode 2 51 51 a a 5 119
225. Results Message This display shows the external power minimum requirements based on the current level settings programmed on the Driver Receiver board The relevant VXlplug amp play API function is e tat964 queryPowerOverhead Power Converter Condition Panel The power converter conditions display is accessed from the Execute DSx View Power Converter Condition menu bar selection There is only one power converter per DRM so the DSA and DSB selection will display the same panel 2 E Figure 5 83 Power Converter Condition Panel The following power converter bits are defined VTM1 Fault Power converter VTM1 failure VTMe Fault Power converter 2 failure Astronics Test Systems Soft Front Panel Operation 5 151 Model T940 User Manual Publication No 980938 Rev K VTMS Fault Power converter VTM3 failure VTM4 Fault Power converter VTMA failure 24V Fuse The 24V level is too low 12V Fuse The 12V level is too low 24V Fuse The 24V level is too high 12V Fuse The 12V level is too high High Current Fault High current condition detected Over Current Fault Over current condition detected and shut down the power converter The relevant VXlplug amp play API function is e tat964 queryPowerConverterCondition Counter Timer Panel The Counter Timer Panel is accessed from the Execute gt DSx gt View gt Counter Timer menu bar selection where x is sequencer A or B One
226. Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The default measurement delay is 200 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hitthe Continue button when the required temperature is reached If the temperature reaches 80 the process continues automatically Astronics Test Systems Programmable Channel Calibration 6 21 Model T940 User Manual Publication No 980938 Rev K Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution Review the results in the Status window Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for Src and Snk in the field controls These values are not in engineering units 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted the calibration factors will revert at the next power cycle Driver Receiver Calibrate Function Serial Number Y DRA ISou
227. System Clutch All phases will complete their action for the current pattern Can halt based on an external signal levels or edges Can halt on error at slower data rates Can halt on a sync pulse used as a breakpoint Also used for single stepping The latter three require a CPU Resume see spec for additional clarification Halting on error is discussed in more detail in the Pause and Halt section of Chapter 8 for additional details about the use of halt Pause Pattern and Halt System Clutch Sources TTLTrgO 7 ECLTrgO 1 F P AUX I O 1 12 CH 1 32 with mask expect and Phase 1 4 for Pause External TOCycle Range lt 1 kHz to 48 MHz External TOCycle Edge Selection External TOCycle Delay Adjustment Can use either edge or both edges of a signal to define the TO Cycle period Can also divide the incoming clock by 2 A programmable delay is provided to adjust the timing relationship of the TOCycle with respect to the Ext input 2 ns resolution 0 64K ns range with the 500 MHz master clock External TOCycle Clock Source F P AUX I O 1 12 ECLTRGO Specifications 7 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Clock Waveform Outputs Up to 4 waveforms can be output during a pattern each sequencer They are provided in lieu of certain phases and windows They can be output on any AUXI O Channel two can actually be output on
228. TRIGGERS VXICLK10 WATCHDOG WINDOW Sequence Logic Model T940 User Manual Jump 4 Selected Inter Module signals Sequence trigger used to start the pattern controller Sequence trigger used to stop the pattern controller Programmable sync pulse signals Selects the jump test event Internal SEQ CLK generated by the sequence controller Vector address bits for vectored jumps TTLTRG 0 7 ECLTRG 0 1 The backplane trigger signals 10 MHz VXI backplane clock Watchdog timer Four input timing signals WINDOWA is used by the probe logic SEQUENCE LOGIC SIM PHASE 500MHz MASTER CLOCK MCLK PAUSE RESUME MCLK SEQ CLK WAVEFORM GENERATOR AUX ECLTRGO SYSTEM CLOCK SEQ CLK TO CLK SEQ CLK TO CLK SEQ JUMP PATADDR PRBADDR TEST CODE BERREN CONDEN ERROR ERROR RECADDR RECORD CONTROL SEQ JUMP TEST CODE HALT JUMP START PAT DEL 1 2 PAT TO SEQUENCE CONTROLLER SEQ REC VXI TRIGGERS LTB AUX l O CHT 1 4 CH IN AUX I O 250MHz VXICLK10 TRIGGER LOGIC COUNTER FS TIMER PULSE GENERATOR PG SEQ TRIG SEQ WATCHDOG SYNC 1 2 IMSEQ VA 0 3 PHASE TIMERS PAT DEL 1 2 Figure 4 5 Sequencer Logic Block Diagram Master Clock This block selects the master clock signal used by the timing and waveform generator Astronics Test Systems Functional Description 4 13 Model T940 Us
229. The slew attribute is updated immediately when changed The relevant VXlplug amp play API function is e tat964 setGroupAttribute OC Src This numeric entry specifies the over current source setting in mA for the selected group The over current source valid range is 10mA to 85mA The OC Src attribute is updated immediately when changed The relevant VXIplug amp play function is e tat964 setGroupAttribute OC Sink This numeric entry specifies the over current sink setting in mA for the selected group The over current sink valid range is 10mA to 85mA The OC Sink attribute is updated immediately when changed The relevant VXIplug amp play function is e tat964 setGroupAttribute Update Group Settings This command button is disabled dimmed until any of the following group attributes are modified e Offset e O Min e When enabled un dimmed this button programs the offset IO min and IO max group attributes The relevant VXlplug amp play API function is e tat964 setGroupAttribute Astronics Test Systems Soft Front Panel Operation 5 17 Model T940 User Manual Publication No 980938 Rev K Group 1 3 These toggle buttons turn the group state on or off The relevant VXlplug amp play API function is e tat964 setGroupState Delay Signal The DRM uses the VXI local bus signal to function in a multi module operation During the alignment process the local bus signals need to be delayed in order
230. UX 6 10 A connector They are a programmable selection of one AUX 7 11 A of three types LVTTL SE ECL or Differential ECL see AUXI8 12 A the next entry AUX 9 12 A Negative side of differential ECL AUX 9 12 A used when these channels are configured as differential ECL AUX 5 8 B LVTTL or ECL these channels are a programmable selection of either LVTTL or SE ECL 9 11 B SE ECL or Differential ECL bi directional general AUX 9 11 B purpose PROBE OUT Probe Support External probe module probe compensation test point This is a direct connection to PROBE IN PROBE MODE Probe Support These signals provide dedicated support PBUT for the external probe module BCLK PROBE DETECT 12V Probe Support These power pins provide low current 12V power for the external probe module The maximum current is limited with an in line poly fuse VEXT These power inputs provide a means to expand pull up options for the Open Collector channels DUT_GND DUT UUT ground reference All of the Pin Electronics devices have a UUT ground reference input that can be selected to be this signal or signal ground GND_REF Buffered selected DUT_GND for the Pin Electronics GND Signal Ground reference Refer to Figure 1 14 and Tables l 4 through 1 9 Astronics Test Systems UR14 Driver Receiver Board 1 29 Model T940 User Manual Publication No 980938 Rev K Table 13 J3A Connector Pinout by Pin Number Connector Pin 5
231. UX A PROBE_IN PROBE compensation gt l DETECT CIRCUITRY HIGHSPEED UR AMPLIFIER 10 c 1 b SES T COMPENSATION AUX1 oo gt CONNECT SWITCH CONNECT LED PROBEMODE A i Coa ml NODE DETECT CIRCUITRY SB ae PBUT lo ol CBUS E PROBE CAL AUX2 A ere 12V 12 o POWER 12V 12V PROBE DETECT 4 ETER UR14 LOGIC pomi Y Figure 10 External Probe Module Signal Descriptions Figure 1 10 UR14 Driver Receiver Board 1 16 EXTERNAL PROBE MODULE PROBE COMP PROBE OUT PROBE IN PROBE CAL PROBE POWER PROBE MODE PBUT DUT GND is the external PCB assembly that is connected to the UR14 via a cable providing a high speed buffer for probe data to the UR14 probe compensation circuitry contact detection circuitry and PROBE and CAL BNC connections AUXA A Output to the external probe module to control the contact detect relay When not used with the probe it can be used as an signal Signal path that can be used to adjust the compensation of the external probe Note that this connection is not on the probe connector Input signal from the external probe When not used wit
232. VO VXI Interrupt Level OFF OFF OFF Disabled none OFF OFF ON Level 1 Selected factory default OFF ON OFF Level 2 Selected OFF ON ON Level 3 Selected ON OFF OFF Level 4 Selected ON OFF ON Level 5 Selected ON ON OFF Level 6 Selected ON ON ON Level 7 Selected A24 A32 Map Selection In addition to the standard configuration registers assigned to the DRM in the A16 memory space 1M of extended memory space is required by the DRM The VXI resource manager assigns extended memory in either the A32 or A24 memory space Switch position 5 of SW2 is used to select A32 A24 register mapping Table 2 3 A24 A32 Map Selection SW2 Position 5 Signal A32 A24 Installation 2 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual A32 A24 Register Mapping OFF A32 factory default ON A24 ATTENTION GPIB VXI slot zero controllers do not support A32 register transfers A24 register mapping must be selected for DRM operation with these controllers Other Settings There are a few switch settings that are used for development or debug which under normal operation should not be changed The factory set default setting for normal operation is noted in each case Debug Selection This is a factory setting and must be set OFF for normal operation Switch position 4 of SW2 is used to select debug operation Table 2 4 Debug Selection SW2 Position 4 Signa
233. XIbus specification s defined minimum thickness of the lockout key and the clearance provided around the module ejector handle two LBUS lockout keys must be fitted on top of each other for each module To install lockout keys to the module 1 Set the module ejector handle to the un ejected position 2 The first key may be pushed around the ejector handle and aligned with the front panel screw holes This takes up most of the clearance under the ejector handle preventing the second lockout key from being installed To provide the necessary clearance move the first lockout key away from the module body and slide the second key underneath the first key and around the ejector handle To secure the lockout keys to the module 1 Align the lockout keys screw holes with the holes in the module front panel Astronics Test Systems DRM Front Panel 3 5 Model T940 User Manual Publication No 980938 Rev K 2 Install two screws in the holes at the top of the module front panel and tighten the screws 3 Move the ejector handle to the ejected position and install a third screw in the hole now made accessible DRM Front Panel 3 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 4 Functional Description This section describes the DRM hardware block diagrams For information about DRM address maps and register descriptions contact your local sales representative or contact Sales Support at
234. a single digital subsystem Driver Receiver module types can also be intermixed to match the signal requirements of the test system High Speed Data Sequencer The high speed data sequencer provides state of the art control over digital test patterns Each DRM contains two data sequencers that can operate Introduction 1 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual independently or linked for timing memory and control of the two Driver Receiver boards Sequencer logic supports full unit under test UUT handshaking and controls timing format pattern data looping and conditional testing The sequencer includes definable standby and idle sequences Triggering and Synchronization The DRM features extensive control over digital testing to synchronize the DRM with other test instruments and control digital test sequencing The DRM accepts triggers from the VXI TTL Trigger Bus VXI ECL Trigger Bus front panel Auxiliary inputs or from any channel and provides two sync outputs per DRM Triggers can be used to synchronize the T940 with other instruments and as a test input for test sequence control Sync outputs can be offset to the start of a test sequence or step Instrument Soft Front Panel The soft front panel software provides interactive control of the DRM The intuitive graphical interface enables setup and configuration calibration and sequencer control Channels may be set up either individuall
235. aded for in field system upgrades 2 Inter Integrated Circuit Multi master serial interface that allows communication to the temperature monitor and EEPROM Description The main purpose of the VXI Bridge is to provide a communication interface between the VXI backplane and the hardware resources Power Converter The PC converts backplane voltages into digital bias voltages V and V for front end types DR3E DR9 and UR14 Its protection circuitry can detect faults in any of the four on board power supplies status of the input fuses or a high input current or overcurrent condition There are three types of power converters each of which has seven voltage ranges Front end features of the DR3E DR9 and UR14 have headroom requirements to the and V bias voltages Refer to the specific front end appendix for Functional Description 4 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual headroom requirements and specifications for each power converter range Type 1 and Type 3 The type 1 power converter is designed for use in a VXI 3 0 chassis and the type 3 power converter is designed for a VXI 4 0 chassis and utilizes the additional power pins and can supply more current Installing a type 3 power converter in a VXI 3 0 chassis is allowed but it is up to the user to limit the number of active channels to prevent damage to the chassis Table 4 1 Power Converter Type 1 and Type 3 Ranges
236. alibration Driver Receiver boards are calibrated using the following settings prior to shipment e 15V to 17 V Voltage Mode Power Converter 12 to 12 e 7V to 24 V Voltage Mode Power Converter 5 to 15 Table D 11 Calibration Settings DAC Basic Factory stored in EEPROM Driver channel deskew Factory stored in EEPROM ADC Monitor Field upgradable stored in EEPROM DVH DVL Field upgradable stored in EEPROM CVH CVL Field upgradable stored in EEPROM Vcom High Vcom Low Field upgradable stored in EEPROM Isource Isink Field upgradable stored in EEPROM IAL IAH Field upgradable stored in EEPROM Inter module timing deskew Static End of cable deskew Static DR3e Driver Receiver Board D 18 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix E 4 Driver Receiver Board DR4 Features e Channels 48 single ended variable voltage or 24 differential channels e Voltage range 31 V to 31 V with an output swing of up to 31 V Relay Isolation on all channel I O e Selectable drive current 50 500 selectable output impedance e Over current detection e Temperature Monitoring e 16 TTL auxiliary channels Front Panel Connectors The front panel of the DR4 Driver Receiver is shown in Chapter 3 no external power connector Block Diagram The DR4 I O Block Diagram Figure E 1 describes the distribution of resources of the DR4 Astronics Test Systems DR4
237. ame Pin No Description CH1 to Various Bi directional RS 422 485 Positive High speed channels CH32 CH1 to Various Bi directional RS 422 485 Negative High speed channels CH32 SIG_GND Various Signal Ground reference AUX1 A 34 Bi directional General Purpose RS 422 485 Positive I O pin AUX1 A 35 Bi directional General Purpose RS 422 485 Negative I O pin AUX2 A 36 Bi directional General Purpose RS 422 485 Positive I O pin AUX2 A 37 Bi directional General Purpose RS 422 485 Negative I O pin AUX3 A 38 Bi directional General Purpose RS 422 485 Positive I O pin AUX3 A 39 Bi directional General Purpose RS 422 485 Negative I O pin AUX4 A 40 Bi directional General Purpose RS 422 485 Positive I O pin AUX4 A 41 Bi directional General Purpose RS 422 485 Negative I O pin AUX5 A 42 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX6 A 44 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX 7 A 84 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX8 A 86 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V Astronics Test Systems DR7 Driver Receiver Board F 7 Model T940 User Manual Publication No 980938 Rev K Name Pin No Description AUX10 A 90 Bi directional General Purpose ECL I O pin
238. ample the four vector bits VAO LSB to VA3 MSB The vector bits are only used if the vector jump bit is set during a sequence jump step The vector bits form an address into the vector table to determine the jump step and timing set if timing mode set to indexed Table 5 76 Vector Strobe Settings Setting Description Window 1 Sets the closing edge of window 1 as the vector strobe Window 2 Sets the closing edge of window 2 as the vector strobe Window 3 Sets the closing edge of window 3 as the vector strobe Soft Front Panel Operation 5 94 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Window 4 Sets the closing edge of window 4 as the vector strobe The relevant VXlplug amp play function is e tat964 setVectorJumpStrobe Set Vector Bits This command button displays the Edit Vector Bits panel so the vector bit signal selection can be programmed for the selected sequencer The four vector signals comprise an index into a vector jump table that specifies the jump address as well as the timing set indexed timing mode only The vector table signals are only used if the vector jump bit is set during a sequence jump step Configuring the vector signals consists of the following 1 Select the Source 2 Program the Input Mode VXIO 2 1NSTR Edit DSA Vector Bits jm Figure 5 53 Edit Vector Bits Panel Source This pull down control progra
239. annels Four TTL with selectable output impedance and resistive input load Four TTL Four ECL single ended or differential DR9 Driver Receiver The DRO9 features e Channels 24 single ended variable voltage or 12 differential channels and 24 analog test channels Astronics Test Systems Introduction 1 5 Model T940 User Manual Publication No 980938 Rev K Voltage range 15 V to 24 V with an output swing of up to 24 V Relay Isolation on all I O channels Provides full drive current on all channels simultaneously Programmable current load with dual commutating voltages Selectable resistive input load 8 choices to a programmed voltage Selectable slew rate 0 25 V ns to 1 3 V ns 12 50 Ohm selectable output impedance Over current detection Over voltage detection protection Auxiliary channels Four LVTTL no relay isolation Utility Resource UR Option The DRM currently has the following utility resource module type available UR14 Utility Resource The UR14 features Channels 32 Low Speed single ended open collector utility pins Voltage range 0 to 30 V Suitable for Inductive loads internal clamping to 42 V 5 V Pull up allowing each channel to operate as low speed TTL Programmable input level detection per byte 0 20 V Programmable over current detection per byte 0 1 A External probe support Auxiliary channels Six variable voltage Two are used with the external probe Four LVTTL Four ECL
240. arator inputs for DR3e DR9 and UR14 front end channels The range for Comparator Delay is from 1 bypass delay to 31 19 35ns 625ps per count Astronics Test Systems Soft Front Panel Operation 5 63 Model T940 User Manual Publication No 980938 Rev K The relevant VXlplug amp play API function is e tat964 setComparatorDelay Channel Mode This control programs the front panel channel mode setting The channel mode can be set to e Single ended e Differential with 100 differential termination e Differential no termination When set to differential adjacent odd and even channels are grouped as a single channel with the odd channel as the positive and the even channel as negative For example If the channel list is 1 2 5 6 then channel 1 and 2 are grouped and channel 5 and 6 are grouped as follows CH1 Diff CH1 CH2 Diff CH1 CH5 Diff CH3 CH6 Diff CH3 If no other differential groups are assigned then CH3 Single ended CH3 CH4 Single ended CH4 CH7 Single ended CH7 The relevant VXlplug amp play API function is e tat964_setChannelMode Configure UR14 Channel Properties The UR14 channel settings consist of a single threshold compare level and an over current detect level programmed in groups of eight channels Soft Front Panel Operation 5 64 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 2 CHitoCH8 Figure 5 33 Configure UR14 Channel Properties Panel C
241. are operation e Specifications e Acronyms and glossary of terms Driver Receiver boards technical information e Timing characteristics Overview and Features The Talon Instruments Digital Resource Module DRM provides two high speed data sequencers and up to 64 high performance digital I O channels in space saving single wide VXI module The DRM operates at data rates up to 50 MHz with 1 ns edge placement and less than 3 ns channel to channel skew Designed for High Reliability The comprehensive thermal design ensures reliability with excellent cooling monitoring and protection Each high power module is equipped with a custom designed heat sink to provide optimal cooling An on board temperature monitor protects the pin electronics devices from overheating and provides over temperature shutdown An optional Racal Instruments M 1263HP series high power VXI chassis provides an integrated power supply for DRM front panel power and additional cooling for large digital test systems See an illustration of the chassis in Chapter 2 Installation For additional information on this chassis contact your sales representative Astronics Test Systems Introduction 1 1 Model T940 User Manual Publication No 980938 Rev K Advanced Features for Modern Digital Test Development The DRM is designed for today s challenging digital test system applications through innovative design The flexible Field Programmable Gate Array FPGA des
242. atsinfo astronics com Digital Board DB CH 1 32 AUX 1 12 A VDATA PROBE BUTTON A VCTRL DRIVER PROBE MODE A INT RECEIVER GNDREFA VXI TRIGGERS DUTGNDA MONITORA MISCA CH 33 64 AUX 1 12 B PROBE BUTTON B PROBE MODE B GNDREFB DUTGNDB MONITORB MISCB DRIVER RECEIVER Figure 4 1 T940 DRM Block Diagram The following sections describe each component in detail Digital Board DB The digital board contains the digital engine of the DRM and the logic to program and group two or more as a digital subsystem Astronics Test Systems Functional Description 4 1 Model T940 User Manual Publication No 980938 Rev K VXI Bridge TEMPERATURE MONITOR 2 JTAG ADDRESS ARBITRATION TTL ECL CONTROL REGISTERS SERIAL PROM VXI INT Data Sequencer Logic Driver Receiver Logic Figure 4 2 T940 VXI Bridge Block Diagram Terms Used in this Section VADDR Address Bus The 32 bit backplane address bus VDATA VXI Data Bus The 32 bit backplane data bus VCTRL Control Bus The backplane control bus VXI INT VXI Interrupt Signals The backplane interrupt signals VXI TRIGGERS TTLTRG 0 7 ECLTRG 0 1 The backplane trigger signals CBUS An internal control bus connecting the arbitration logic to the Data Sequencers and the Driver Receiver board s Control Logic JTAG Joint Test Action Group IEEE 1149 1 Serial interface that allows the serial PROM to be relo
243. ause you to be connected to the wrong MFSIG Table B 7 shows the connection names pins and descriptions for the PWR connector Astronics Test Systems DR1 Driver Receiver Board B 11 Model T940 User Manual Publication No 980938 Rev K Table B 7 PWR Connector Name Pin No Description DRB MFSIG 2 Output Multi function signal DRB DRB GND 4 Power supply signal return DRB DRA MFSIG 6 Output Multi function signal DRA DRA GND 7 Power supply signal return DRA Calibration Table B 8 Calibration Settings Inter module timing deskew Static End of cable deskew Static DR1 Driver Receiver Board B 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix C DR2 Driver Receiver Board DR2 Features e Channels 32 differential LVDS e Auxiliary channels FourLVDS Four LVTTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR2 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR2 Driver Receiver DRA or DRB The DR2 is comprised of four major logic sections as shown in Figure C 1 e Auxiliary Driver amp Receiver I O DR2 Driver amp Receiver e Control Logic e Firmware amp NV Data Astronics Test Systems DR2 Driver Receiver Board C 1 Model T940 User Manual Publication No 980938 Rev K AUX DATA 5 8 AUX RH 5 8 AUXI
244. ays enabled The selections for this pull down control are Table 5 79 Jump Condition Settings Setting Description Always Jump always Unconditional Step Not PASS Jump if the PASS FAIL flag is NOT a PASS i e FAIL or Indeterminate Step Not FAIL Jump if the PASS FAIL flag is NOT a FAIL i e PASS or Indeterminate Astronics Test Systems Soft Front Panel Operation 5 103 Model T940 User Manual Publication No 980938 Rev K Setting Description Step FAIL Jump if the PASS FAIL flag is equal to FAIL Step PASS Jump if the PASS FAIL flag is equal to PASS Sequence FAIL Jump if Burst Error Count is not equal to zero Sequence PASS Jump if Burst Error Count is equal to zero Jump Trigger 1 Jump if Jump Trigger 1 true True Jump Trigger 1 Jump if Jump Trigger 1 not true not True Jump Trigger 2 Jump if Jump Trigger 2 true True Jump Trigger 2 Jump if Jump Trigger 2 not true not True Jump Trigger 3 Jump if Jump Trigger 3 true True Jump Trigger 3 Jump if Jump Trigger 3 not true not True Jump Trigger 4 Jump if Jump Trigger 4 true True Jump Trigger 4 Jump if Jump Trigger 4 not true not True The true false state of the jump triggers is based on the jump trigger test condition If the jump trigger test condition is set to Low Level then True would indicate the jump trigger signal is low and not True would indicate the ju
245. based on the position of the jumper Figure 2 4 shows the location of the T940 jumper The jumper is accessible through a cutout in the T940 cover To remove the jumper use the paper tab of the jumper bar to lift it off the connector Figure 2 5 shows the jumper positions for the desired setting Primary Secondary or Terminator Installation 2 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Note Jumper above is shown in the Terminator position Figure 2 4 T940 Inter Module Mode Jumper Connector Location Terminator Position Secondary Position Primary Position Note The gray areas in the figure indicate the open portions of the connector Figure 2 5 T940 Inter Module Mode Jumper Positions and Settings Installing the Module into a VXI Chassis WARNING The DRM is NOT hot swappable The power to the VXI chassis must be turned off before installing a DRM Plugging the module in before the power is off may result in damage to the electronics Astronics Test Systems Installation 2 7 Model T940 User Manual Publication No 980938 Rev K ATTENTION Be sure that the VXI chassis has sufficient power and cooling capability particularly if multiple DR3e or DR9 modules are installed into the same chassis The DRM may be installed in any VXI chassis slot except slot 0 zero whic
246. blication No 980938 Rev K o Select the Channel Test to be used 1 of 4 on the Master and or Slave Sequencer for the channels to be ORed Unmask Channel Test for these channels Set the expect level for each channel to be the level desired for a trigger Select the TRG Bus to be used and select the Channel Test signal to drive it Do a Jump Test On the Master select the same TRG bus signal and use a High or Rising Edge test condition To do a Jump Test on the AND of several Channels o Select the Channel Test to be used 1 of 4 on the Master and or Slave Sequencer for the channels to be ANDed o Unmask Channel Test for these channels o Setthe expect level for each channel to be the complement of the level desired for a trigger o Select the TRG Bus to be used and select the Channel Test signal to drive it o Onthe Master select the same TRG bus signal and use a Low or Falling Edge test condition Notes 1 Local versions of the TRG signals are used when DSA and DSB on the same module are linked Thus Channel Tests will function as above without using the backplane TRG Bus lines The TTLTRG Bus has a weak pullup thus the risetime will be quite slow As such the trailing edge of an active low signal will be delayed up to 40ns more than the leading edge Triggering on a falling edge is recommended when delay is a concern There is a way to do AND OR or OR AND channel tests between groups of channels
247. button Depress Master Reset command button also disables output drivers execute idle Execute idle sequence Enter step number and depress Execute Idle command button execute Execute sequence Enter step number and depress Execute command button Soft Front Panel Operation 5 114 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Transition Description Soft Front Panel Control last step stop idle finish mode Sequence completes step with last step flag true or stop command Finish Mode set to SetFinish Mode to Idle e Enter step number and depress Execute command button e f sequence is still active depress the Stop command button last step stop Sequence completes step e Set Finish Mode to Standby standby finish with last step flag true or e Enter step number and mode stop command Finish depress Execute command Mode set to Standby button e f sequence is still active depress the Stop command button halt Halt the active sequence e Make sure the Halt Mode is not set to Disabled e Depress the Halt command button If sequence was active Halt LED should be red halted If sequence was not running Halt LED should be green armed resume single Halt resume or single step While in HALT state step e Depress Resume command button to resume e Depress Halt co
248. calibration data for the DRB Driver Receiver Calibration board tat964 loadCalibrationFile Load DRM Loads the DRM data tat964_loadDrmFile Data Close Closes the DRM session and exits the SFP tat964 close Config Menu The Configuration Config Menu is used to configure the DRM hardware Module Data Sequencer A Data Sequencer B Channels Aux Outputs Interrupts BS _c Users Public Documents DSAwalk1 cfg File Config Edit Execute Instrument Help Ax Slot 4 VXI0 2 INSTR truments T964 T940 Active Figure 5 8 Config Menu Table 5 2 Config Menu Descriptions Menu Option Description Module Displays the panel for programming module parameters Data Sequencer A Displays the panel for programming DSA parameters Data Sequencer B Channels Displays the panel for programming DSB parameters Displays the panel for programming channel parameters Soft Front Panel Operation 5 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual AUX Outputs Displays the panel for programming auxiliary output parameters Interrupts Displays the panel for programming the interrupt parameters Edit Menu The Edit Menu is used to create program and modify timing sets pattern sets and sequences bs c Users Public Documents DSAwalkLcfg 0000 File Config Edit Execute Instrument Help Data Sequencer 4 S1 Data Se
249. calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted the calibration factors will revert at the next power cycle Driver Receiver DRA DRB Stat Chan 20 1 Channel 20 1 Status Calibrating SN 12060853 Calibrating Comparator Levels Fun ves Sor Update Section One Astronics Test Systems Programmable Channel Calibration 6 17 Model T940 User Manual Publication No 980938 Rev K Vcom High Low For DR3E DR9 and UR14 only the Vcom High Low calibration calculates the offset and gain of the current and resistive commutating voltage levels The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the CVH CVL menu item on the Calibrate Function menu 2 Verify that the Vcom High Low calibrate function is now in focus Calibrate Function Vcom High Low v Select Start and End Channels and Measurement Delay Equipment Basic Setup Procedure
250. cant channel data is the right most hex character in each column In the example above all channels are set to Z except channel 1 is set to 0 in pattern one In pattern two all channels are set to Z except channel 16 is set to 1 The binary format represents the pattern data as raw binary data The pattern data is stored in four sequential 32 bit blocks five if flags and probe expect are included The block order is listed below Table 5 74 Binary Block Format Block Number Contents Channel 8 through 1 Channel 16 through 9 Channel 24 through 17 Channel 32 through 25 Flags probe expect In blocks one through four each 32 bit value contains eight pattern codes The pattern code for each channel requires four bits The channel mapping for each block is from the lowest channel to the highest channel i e bits 0 3 are channel 1 in block 1 bits 4 7 are channel 2 in block 1 etc In block five each 32 bit value contains the flag codes and the probe expect The flag code for each pattern requires two bits Bits 15 and 14 contain the flag code and bits 13 through 8 contain the probe expect code Table 5 44 lists the binary value pattern code translation Astronics Test Systems Soft Front Panel Operation 5 89 Model T940 User Manual Publication No 980938 Rev K ASCII String The ASCII string format represents pattern data as viewable ASCII strings one character per channel
251. cer Operation Details section of Chapter 8 provides detailed information on sequence operation Timers This block contains the Watchdog Sequence Timeout Pattern Delay 2 and the Pattern Timeout Timers Probe Flag RAM The probe input code probe results and CONDEN BERREN data for each pattern is stored in this RAM Functional Description 4 14 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pattern RAM The output code as well as the input code for every channel of each pattern is stored in the Pattern RAM Record RAM This is where the individual channel results are stored The channel results are either the pattern input compare result or raw response data based on RH or RL The results can be stored in normal or indexed starting from address zero and expanded Frequency Synthesizer The Frequency Synthesizer FS may be used in lieu of the 500 MHz oscillator as the master clock The reference clock for the FS may be a built in 20 MHz oscillator VXICLK10 LCLK100 2 or any of the AUX inputs in the range of 5 to 80 MHz Sequence Control This block contains the registers and logic used to program the data sequencer Channel Control This block takes the output code from the pattern RAM formats it and outputs it according to the phase timing PHASE The resultant drive CH DATA and enable CH EN signals go to the Driver Receiver logic The response high CH RH and response low CH RL
252. cer to the programmable output drivers OC Over Current detect from the programmable Driver and Receiver channels RH Response High input signals to the Data Sequencer from the programmable input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the programmable input receivers 0 good 0 1 good 1 V V Bias Power required for operation of the Pin Electronics devices EXTSENSE Pin electronics signal used for calibration DR3e Driver Receiver Board D 4 Astronics Test Systems Publication No 980938 Rev K DUT GND CONTROL AUX 1 4 CH 1 32 MONITOR GND REF EXTFORCE OVERVOLT TEMPMON Control Logic Model T940 User Manual This signal comes from the UUT and can be used to offset the reference levels up to 3V Excursions of DUT beyond 390 mV with respect to signal ground yield GND FAULT signal Control Logic signals to control isolation relays termination pin electronics and temperature thresholds Four programmable signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 These UUT Bi directional programmable I O channels from the DR3e Drivers and Receivers This is an analog output signal from the Pin Electronics devices which can be used to monitor DAC levels even the Channel I O levels This signal is used with the internal ADC but a buffered version also comes out the Front Panel This is the gro
253. changes in software Also added UR14 board and probe features F 7 23 2013 03095 Added information regarding DR8 option ECN04897 Added additional content including attributes and static state control statis mode G 5 7 2014 comparator delay pass fail clear and static data Revised MTBF hours for boards Rebranded manual to Astronics 05018 Added information regarding new DR4 D 9 11 2012 H 6 13 2014 option including Appendix E DR4 Driver Receiver Board 06159 General update of manual to latest J 5 19 2015 software and sequencer revision addition of calibration and advanced topics chapters specification updates 06542 Updated text and soft front panel screen shots to include new reference ADC and load calibration DR4 calibration validation support current alarm high low 4 power converter control support for Sequencer 0 23 and updated slew rate specs K 10 28 2015 XXX Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 1 Introduction This manual provides information necessary to set up and operate the T940 64 Channel Digital Resource Modules DRM Throughout this manual DRM is used to refer to the T940 Separate chapters and appendices include e Overview and features of the DRM e Installation e Front panel and connector descriptions e Functional descriptions Detailed soft front panel softw
254. cks are available for triggering the timing phases to begin their programmed definition System Clock and Pattern Clock see Phase Trigger Properties in Chapter 5 If a Phase is defined to trigger on the System Clock then its span cannot exceed the System Clock period If a Phase is triggered by the Pattern Clock and the CPP gt 1 then that Phase can span the Pattern Clock period Windows are only triggered on the Pattern Clock and can span the Pattern Clock period while still observing the Timing Set Value Rules Timing Set This numeric control sets the timing set number for the sequence step This control is only visible when the sequencer timing mode is set to indexed see Timing Mode in Chapter 5 The valid values for control are from 0 to 255 The relevant VXlplug amp play function is e 964 setSequenceTimingSet Astronics Test Systems Soft Front Panel Operation 5 101 Model T940 User Manual Publication No 980938 Rev K Last Step This control allows the user to specify the Last Step flag This flag indicates whether the current step is the last step of the sequence burst True or a sub step of a multi step burst False The relevant VXIplug amp play function is e tat964 setSequencelastStep Sequence Timeout This control allows the user to specify the Sequence Timeout mode Every step in a multi step burst can be timed using the sequence timeout timer When the flag is set to Reset the timer will
255. ctional General Purpose RS 422 485 Negative pin AUX4 B 40 Bi directional General Purpose RS 422 485 Positive pin AUX4 B 41 Bi directional General Purpose RS 422 485 Negative pin AUX5 B 42 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX10 B 90 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX10 B 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 93 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 B 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 B 95 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V PBUT B 46 Bi directional Probe Button Input PMODE B 47 Output Probe Support Output BCLK B 96 Output Reserved Calibration Table F 6 Calibration Settings Inter module timing deskew Static End of cable deskew Static DR7 Driver Receiver Board 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix G
256. ctions for this pull down control are Table 5 45 Probe Data Settings Setting Description Disable The probe data memory is not written to Capture The probe data memory contains comparator and transition results Compare The probe data memory contains the results of a comparison between probe data and the probe expect data This mode is only available when the sequencer Record is set to Normal See tat964 setRecordParameters The relevant VXlplug amp play API function is e tat964 setProbeConfiguration The capture CRC mode allows the user to select the capture signal for the probe CRC The selections for this pull down control are Table 5 46 CRC Capture Settings Setting Description Disable Disable Probe CRC Capture Soft Front Panel Operation 5 46 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Setting Description Window 4 Window 4 open edge samples the Open CRC Window 4 Window 4 close edge samples the Close CRC The relevant VXlplug amp play API function is e tat964 setProbeConfiguration Probe Button This control sets the probe button action The selections for this pull down control are Table 5 47 Probe Button Settings Setting Description None Disable probe button Start Probe button starts the selected sequence Resume Probe button resumes the paused sequence Both Probe button star
257. d 108 feet 108 3 116 3 Set window to cables between 108 3 and 116 3 feet 116 6 124 6 Set window to cables between 116 6 and 124 6 feet 125 133 Set window to cables between 125 and 133 feet The relevant VXlplug amp play API function is e tat964_setOverCurrentControl Note The actual current limits for over current detection are programmed in Configuring the I O Channels below For the DR4 current limits programmed as shown in the relevant Group Attributes section Drive Fault This pull down control programs the sequencer Drive Fault mode If an output pin is enabled to also compare its state Capture mode programmed and compare levels set then a drive fault will be generated if the compare level does not match the output state Drive faults can be used with stimulus only Soft Front Panel Operation 5 44 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Probe Probe State pattern codes and can be used to detect dynamic over current conditions If enabled a drive fault will disable all channels of the specified sequencer and a drive fault event will be generated Use tat964_querySequencerEvent to query the drive fault event and tat964_querySequencerDriveFault to query which channel caused the drive fault The selections for this pull down control are Table 5 44 Drive Fault Settings Setting Description Disable Disable drive fault signal
258. d Type to Normal records into the Record Memory at the same address which corresponds to the Data Pattern Thus when looping a Step or repeating a Step at some later point during the Primary Sequence the data in the Record Memory will be over written Setting the Record Type to Indexed recording means that data will be written into the Record Memory consecutively A Record Index memory keeps track of how the data is written into the Memory so it can be reconstructed i e which data belongs to each step and or loop Advanced Topics 8 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 8 3 summarizes what gets recorded based on the selected Step Record Mode Table 8 3 Summary of the Record Memory Action for each Step Record Mode Action Normal Record Type Indexed Record Type Don t record Don t record anything into the Don t record anything into anything Record Memory at the the Indexed Record Memory address that corresponds to the Data Pattern address Thus whatever is there will not be over written Record non Write zeros into the Record Write zeros into the Errors Memory at the address that Indexed Record Memory corresponds to the Data Pattern address Note If using Indexed Recording Don t record anything is the better choice to avoid filling up the Hecord Memory unnecessarily with zeros Counting and Logging Errors Errors can be counted for Independent Sequencers
259. d in the Pattern Data as follows PnP tat964_setPatternTestEnable The relevant VXIplug amp play API and ARI functions are e tat964_setPatternTestEnable e ARI LoadPtgStepExpectedPatternBin LoadPtgStepPatternChar Figure 8 12 Setting the Pass Fail Basis in the Configure DSA Settings Panel Astronics Test Systems Advanced Topics 8 15 Model T940 User Manual Publication No 980938 Rev K The condition is programmed on the TEST row for each pattern column A c enables CONDEN Patterns 1 amp 6 have just CONDEN enabled A b means that just BERREN is enabled An for all means that both CONDEN and BERREN are enabled as on pattern 4 Unlike for the Counting and Logging of Errors Jumping and Halting is not based on the Step Record Mode The same action is taken for all Step Record Modes as shown in Table 8 6 Table 8 6 Cross Reference of Step Record Mode to Pass Fail Basis Pass Fail Basis Insert Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline Qual Local DRS Linked Qual DRS Linked Insert DRS Linked Errors and PV into the Pipeline Insert CONDEN Qual DRS Linked Errors and PV into the Pipeline f Pass Valid PV is enabled Step Record Mode Record Count Insert Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline Insert DRS Linked Errors and PV into
260. d in whole or in part to solicit quotations from a competitive source or used for manufacture by anyone other than Astronics Test Systems The information herein has been developed at private expense and may only be used for operation and maintenance reference purposes or for purposes of engineering evaluation and incorporation into technical specifications and other documents which specify procurement of products from Astronics Test Systems TRADEMARKS AND SERVICE MARKS All trademarks and service marks used in this document are the property of their respective owners Racal Instruments Talon Instruments Trig Tek Adapt A Switch N GEN and PAWS are trademarks of Astronics Test Systems in the United States DISCLAIMER Buyer acknowledges and agrees that it is responsible for the operation of the goods purchased and should ensure that they are used properly and in accordance with this document and any other instructions provided by Seller Astronics Test Systems products are not specifically designed manufactured or intended to be used as parts assemblies or components in planning construction maintenance or operation of a nuclear facility or in life support or safety critical applications in which the failure of the Astronics Test Systems product could create a situation where personal injury or death could occur Should Buyer purchase Astronics Test Systems product for such unintended application Buyer shall indemnify and
261. dle will not produce any Errors or Indeterminates Pass Fail Option 1 This option allows one to accumulate Pass Fail across consecutive Sequence Steps This is programmed on the Edit gt Data Sequencer A B gt Sequence Steps panel The relevant VXIplug amp play and ARI functions are e API tat964_setSequencePassFailClear e ARI AssignPtgPipelineParameters pia VXIO 2 INSTR Edit DSA Sequence Step 1 Data 1 00 ns per count Intemal TOCLK Clocks per Pattem CPP 1 Pass Fail Clear Defaut w v Default Mask Figure 8 16 Setting the Pass Fail Clear Control in the Edit DSA Sequence Step Panel Default is one of the default settings included above Mask means that at the end of this Sequence Step that the Pass Fail accumulator will not be cleared Pass Fail Option 2 This option disables the Step Pass Fail accumulator but not for the Sequence Pass Fail accumulator Thus the Pass Fail status on any particular pattern occurs exactly N patterns later where N is the depth of the Pipeline This is a static setting which is programmed on the Config Data Sequencer A B gt Setting panel by clicking Attributes which brings up this panel The relevant VXIplug amp play and ARI functions e API tat964_setSequencerAttribute e ARI AssignPtgSequencerAttribute Astronics Test Systems Advanced Topics 8 21 Model T940 User Manual Publication No 980938 Rev K ES VXIO 2 INSTR DS EET Phase 3 Mode v
262. ds 7 5 7 7 Counter Timer Characteristics 21221000 7 8 Pulse Generator Characteristics 44 100 eene enne nnns nennen 7 9 7 9 Front Panel tuve Bes 7 10 MAM EEE T ESE TE S E 7 10 Power 7 10 enviromental 7 11 GHapter 8 1 ed 8 1 Jumping Halting Counting and Logging on Pass Fail 8 1 Coupling Signals between Sequencers for Linking and DRS Formation 8 2 Step eu Ptr ua ntf use oto e EE ERES 8 6 Record Types tee metet ette p a e diaeta tis 8 8 Counting and Logging Errors nennen entren nennen nnne nnn snnt ns 8 9 Pipelining and non Pipelining
263. e DSx View Kept Data Astronics Test Systems Soft Front Panel Operation 5 127 Model T940 User Manual Publication No 980938 Rev K menu bar selection Where is the sequencer you wish to query Disabled Disabled Disabled Disabled Figure 5 67 Kept Data Panel The kept data represents the current pattern code that is not Invert Previous Code or Repeat Previous Code Note The Kept Data is updated at the end of a pattern so the contents of the kept data when halted or paused will contain the codes from the previous pattern The relevant VXlIplug amp play API function is e tat964 queryKeptPattern Results The Results data display is accessed from the Execute DSx View Results menu bar selection Where is the sequencer you wish to query Soft Front Panel Operation 5 128 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual E VXIO 2 1NSTR Execution Results DSA Save Results Figure 5 68 View Results Data Panel View This pull down control selects the results to view The selections for this pull down control are Table 5 94 Results View Settings Setting Description CRCs Display the CRC data from the previous sequence execution Error Address Display the error address data from the previous sequence execution Record Index Display the error address data from the previous sequence execution Record Da
264. e times crosses RH once and ends above RH Open oe D8 Middle Falling Edge Signal starts between RL and RH crosses the RH two or more times crosses RL once and ends below RL Close Close open EQ Falling Edge Glitch Signal starts above RH crosses RH once crosses RL three or more times and ends below RL Open F2 Low Pulse Middle Signal starts below RL crosses RL three or more times RH two or more times and ends between RL and RH Close Soft Front Panel Operation 5 138 crosses the RL three or more times and ends below RL B6 Open Close Low Glitch Rising Edge Signal starts below RL crosses the RL three or more times crosses RH once and ends above RH oe DQ High Glitch Falling Edge Signal starts above RH crosses the RH three or more times crosses RL once and ends below RL Close oe FO Middle Pulse Middle Signal starts between RL and RH crosses RH and RL two or more times and ends between RL and RH Close oe F4 Middle Pulse High Signal starts between RL and RH crosses RL two or more times RH three or more times and ends above RH Close Publication No 980938 Rev K Close oe CQ Falling Edge Signal starts above RH and crosses the RH and RL once and ends below RL Open E 1 Close Fa
265. e Step 3 a one pattern Sequence Step and Resume on the Rising Edge of Aux 5 o Sequence Step 3 set the Pause Test Condition Phase 4 FE o Select for Resume Phase Test 4 Aux 5 o Select for Resume Phase Test 4 Rising Edge Test Condition Replicate a Pattern Clutch function using the Aux 6 input an active high clutch o Forall Sequence Steps within the Sequence set the Pause Test Condition Pause Test 1 True o Select for Pause Test 1 Aux 6 o Select for Pause Test 1 High Note a high on Aux 6 pauses and a low resumes a Resume need not be programmed in this case Insert a 1s delay in one Pattern starting at the FE of Phase 4 Advanced Topics 8 32 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pause Notes o Isolate the Pattern one Sequence Step o I nthis Sequence Step set the Pause Test Condition Phase 4 FE o Set Delay Timer 1 for 1s o Select the option in the Seq Step which selects Delay Timer 1 for a Pattern Delay Since a Pattern can have multiple Phases using a Phase Trigger 0 and a gt 1 multiple handshakes can be performed within a pattern Since a Waveform can replace Phases 3 amp 4 there can actually be multiple irregularly spaced Handshakes within a Pattern The Phase used for a Handshake may be output as a Handshake ready signal The timing requirements for a Pause and Resume may preclude certain types of high speed hand
266. e The relevant VXlplug amp play functions are e tat964 setTtlTriggers e tat964 setEclTriggers D R Properties This command button displays the Configure DSn D R Properties panel so the configuration settings can be programmed for applicable Driver Receiver boards Soft Front Panel Operation 5 20 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DUT GND VXIO 2 INSTR Configure DSA D R DUT GND Front Panel J Sia Gna Voltage Mode 15Vto 17V w Figure 5 19 Configure DSn D R Properties Panel For the DR3e DR4 DR9 UR14 this control is used to program a relay that will connect the DUT reference for the Pin Electronics to either a front panel DUT_GND or to signal ground The former is used to correct for ground reference offsets due to cabling The relevant VXlIplug amp play function is e tat964 setPowerSettings Note This function is inoperable for the DR1 DR2 DR7 and Signal Ground is always used for these Driver Receiver boards for single ended signals Voltage Mode This pull down control programs the voltage mode for the DR3e DR9 UR14 Driver Receiver boards The selections for this pull down control are Table 5 16 Voltage Mode Settings Setting Description Recommended Usage Mode 0 Selects voltage mode 0 For any Power Converter range except for DR3e DR9 UR14 15 V to 17 the 0 to 24V and 2V to 22V V Mode
267. e 5 81 Jump SettingS 0 ccccecceceeeceseeeeeececeeeeeceaeeeeaaesseneeceaeeseaaeseeaeeseeeeesaeeeeaaesseneesaas 5 103 Table 5 79 Jump Condition Settings enne nenne 5 103 Table 5 80 Step Record Mode Settings ssssssssssssseeeenennene nnne nenne 5 105 Table 5 81 Step Record Mode Settings 22 4 0 0 0 00 5 106 Table 5 82 Handshake Pause 5 10 1 22 5 109 Table 5 83 Handshake Modifier Settings sssssssssssssseseeeeeeen nennen 5 111 Table 5 84 Execute State Description enne enne 5 113 Table 5 85 Execute State Transition Description 5 114 Table 5 86 Channel Drivers Settings ssssssssssssssseeseeneee enne nenne 5 118 Table 5 87 Halt Mode Settings ssssssssssssssssssseeeee ener entente 5 119 Table 5 88 Finish Mode Settings esee nnne nennen enne nnns 5 120 Table 5 89 Stop Mode 5 121 Table 5 90 CRC nennen nnne nnns 5 121 Table 5 91 Finish Mode 22 2 4 000 0 eene nennen nnne nenne 5 122 Table 5 92 Static Stimulus Settings
268. e Configuring the AUX Channels in Chapter 5 CH 1 32 These are UUT Bi directional positive differential LVDS I O channels from the DR2 Drivers and Receivers CH 1 32 These are UUT Bi directional negative differential LVDS channels from the DR2 Drivers and Receivers Control Logic The control logic contains the registers memory and logic that allow the DR2 Driver Receiver Board C 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual digital board to interface and configure the hardware Signal Descriptions CONTROL Signals used to control isolation ECL mode and NV data MP SIG Multi Purpose signal from the data sequencer MF SIG Multi Function signal output to the PWR connector CBUS An internal Control Bus connecting the digital board to the Driver Receiver board Firmware amp NV Data The Control Logic firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions CONTROL DR2 Characteristics Signals used to program firmware and NV DATA Table C 1 DR2 Characteristics Description Characteristics Digital Type LVDS SN65LVDM 1 76D Channels Output Voltage 32 differential per Driver Receiver board VOL 454 mV max VOH 247 mV min Differential Input Voltage 20
269. e Master must always be included in a DRS but any of the other Sequencers may be excluded Those excluded may be simply unused be independent or for a given DRM could be Linked In the latter two cases they are separate instruments from the remaining sequencers which make up the DRS Coupled A term that s only used when another sequencer is coupled to the Master in a DRS Before getting into the details of Jumping Halting Counting and Logging there are signals that may need to be connected coupled between Sequencers to support these functions in a Linked or DRS Configuration The table following the figure summarizes the applicable signals and their usage No signals need to be linked for Independent Local operation For Linked operation here are some signals that one might set up This is accomplished on the Config Configure Module panel by clicking on the Linked Trigger Bus panel The relevant VXlIplug amp play and ARI functions Advanced Topics 8 2 tat964_setLtbTriggers ARI AssignPatTimeGroup AssignPtgTrigger Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual n pepe 12to 12 7 Data Sequencer A Data Sequencer B Phase 1 5 Phase 1 32 Eror Pulse Width Record Mode Error Pulse Width Record 2 3MCLK Y Disabled Sf Figure 8 1 Configure Module Panel On this panel six signals are set up to be coupled between Sequencers A to B in the d
270. e Module Block Diagram Front Panel The DRM front panel provides the interface to the device being tested There is a Driver Receiver board connector for input and output of signals As an option the T940 can be equipped with an external power connector to power the DR3e B Figure 1 3 T940 Optional Front Panel PWR Connector Introduction 1 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Power Converter PC The PC may be optionally installed on the Digital Board when variable voltage DR boards such as the DR3e DRY or UR14 are used The PC converts backplane voltages into digital bias voltages Its protection circuitry can detect faults in any of the four on board power supplies status of the input fuses or a high input current or overcurrent condition There are three types of power converters each of which has seven voltage ranges Digital Board DB The DB contains the connectors and headers required for routing signals to from the VXI backplane as well as the DRA DRB logic DB logic is comprised of the following major components VXI Bridge The VXI Bridge maintains the VXI interface with the backplane The bridge includes the communication registers for the VXI protocol requirements The DRM functions are programmed through VXI 16 2 24 register access Inter Module Control In a multi module system the VXI Local Bus is used to synchronize the modules The Inter Module
271. e relevant VXlplug amp play function is e tat964 assignPatternSet Edit Data This control displays the view edit pattern set panel This panel allows the user to view edit the contents of the pattern set memory Double clicking on the desired pattern set can also open this panel Soft Front Panel Operation 5 80 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure 5 44 Pattern Set Sequencer Data Panel Each column contains the TEST code PROBE code and the pattern codes for all the channels The pattern codes are described in Figure 5 47 and Table 5 TTT The pattern set is displayed in pages of 32 patterns The View menu bar lists the page control shortcuts listed below Pattern Codes Next Page PgUp Previous Page PgDown First Page Home Last Page End Figure 5 45 Pattern Set Data View Menu Astronics Test Systems Soft Front Panel Operation 5 81 Model T940 User Manual Publication No 980938 Rev K To jump to a specific pattern number right click in any of the cells to display the Goto Pattern panel Figure 5 46 Goto Pattern Panel The menu bar View Pattern Codes displays a legend of all the available TEST and CH entries Bi Pattern Codes TEST Codes Both Enables True BERREN True CONDEN True Disable Pass Fail CH Codes Disable channel Collect CRC Drive Low Drive High Repeat Previous Code Invert Previous Code Expect Valid Low Expect Valid High
272. eceiver Board E 1 Biat Mg E 1 Front Panel Connectors utente eaae TE He ae aea E 1 Block Diagrams het t efe ut 1 SignialDescriptiOns 2 B eicere E 3 Channel Driver amp Receiver 1 E 4 Signal Descriptions x s 35 tee nasa aser uim dee E 4 Auxiliary Driver amp Receiver I O E 5 SIGMA SSC OTC iss 2 coste LEE ut E 6 Power sinn sententie 6 DRA GRhAaract ristiGS 7 Power Requirements 8 Environmental ti E 8 DR4 Signal Description sssini iE a eee debe adelaide E 9 200 pee edie e dc dp nde des E 9 DRB I O Channels J201 4 aa aaa s a ena E 11 eric MT E 12 xiv Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual tS F 1 DR7 Driver Recelvet Board rite oie tnn tne ennt e ta ne aa F 1 DR FORUS MEET F 1 Front Panel Connectors
273. eceiver Board 1 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual UR14 RO AUX DATA3A AUX3 A AUX DATA 5 12 A AUX 6 10 A axe sraia gt AUXIBI2 A AUX S 8 B ECL LVTTL AUX 9 11 B VO CONTROL AUX 9 11 B EE AUX DATA 1 2 4 A PROBE IN AUX EN 1 2 4 A PROBE OUT PROBE CAL PROBE MODE PROBE DETECT PROBE POWER PLED PBUT AUX RL1A MONITOR CONTROL AUX DATA 1 4 B CONTROL DATA 33 64 CH 1 32 OC 33 64 V V PC MONITOR INREF 1 4 NTROL pun ADC OVERVOLT AUXENIM B gt prc DUT GND ES C smun o 11 uma OCREF 1 4 D CONTROL TROL ovevour ExmENSE OVERVOLT EXTSENSE 1 0 CONTROL Figure 2 UR14 Driver Receiver Block Diagram e AUXILIARY DRIVER amp RECEIVER I O ECL LVTTL Block diagram illustrates the configuration and control of Auxiliary ECL amp LVTTL Driver amp Receivers on the UR14 e PROBE Block illustrates the configuration and control of the External Probe Support Signals on the UR14 e PROGRAMMABLE DRIVER amp RECEIVER I O Block diagram illustrates the major Driver amp Receiver internal and external features for the PROGRAMMABLE AUX Channels OPEN COLLECTOR CHANNEL 1 O block diagram illustrates the Astronics Test Systems UR14 Driver Receiver Board 1 3 Model T940 User Manual Publica
274. ect Start and End Channels and Measurement Delay sss 6 18 DRM Calibration 6 19 RUM Calibration 2 6 19 Source Smk Ead e ent e Pepe dete e 6 20 Select Calibrate FU rnGliObi tocco eee 6 20 Select Start and End Channels and Measurement Delay sss 6 21 DRM Calibration Warmup essen nennen nnn 6 21 Ruri Calibration re t ter 6 22 s iet et RA be AREE E Ein 6 23 Select Calibrate FuNnCUOMN iore Little ete eta a An agen ee nid ee pn nu 6 23 Select Start and End Channels and Measurement Delay sss 6 23 DRM Calibration 6 24 Run GalibratiGmn uunc chi bee tn he Ee eR nena 6 24 Chapter eee 7 1 Specifications iii en ios ee e a Ae Ln reatus 7 1 Timing Gharacteristics a ode eee ete deem tete ete tad 7 1 Astronics Test Systems xi Model T940 User Manual Publication No 980938 Rev K Stimulus Capture 44 1 1 10000 7 3 Recording Mode Characteristics amiss 0 ert e Ef e pfe a Ee Ra dd 7 4 sequencer Characteristics o Mad ee ar de ue ete o e
275. ect files are created loaded saved and renamed There are also diagnostic loads register dumps and calibration data loads A file history list permits quick reloading of recently accessed test files The SFP can also be closed from this menu Table 5 1 File Menu Descriptions Menu Option Description New Clears the DRM hardware to power up reset settings tat964 reset Open Opens a file browser for choosing a configuration file The chosen file is loaded and displayed on the title bar Astronics Test Systems Soft Front Panel Operation 5 5 Model T940 User Manual Publication No 980938 Rev K Menu Option Description and inserted in the history list tat964 loadConfiguration Save Updates the configuration file with the latest editing changes tat964 saveConfiguration Save As Creates a new configuration file with the latest editing changes It then becomes the current configuration tat964_saveConfiguration Load Hex File Low level utility routine for hardware checkout Run Command Low level utility routine for message based command Script checkout Dump DRA Saves the register contents of the DRA Pin Register Data Electronics devices to an ASCII file Dump DRB Saves the register contents of the DRB Pin Register Data Electronics devices to an ASCII file Load DRA Loads calibration data for the DRA Driver Receiver Calibration board tat964 loadCalibrationFile Load DRB Loads
276. ections for this pull down control are Table 5 15 Signal Pull Down Settings Setting Description of the VXI Trigger Source Signal None Disables the TTLTRG driver Astronics Test Systems Soft Front Panel Operation 5 19 Model T940 User Manual Invert Publication No 980938 Rev K Setting Description of the VXI Trigger Source Signal AUX1 AUX12 Selects the specified AUX input signal from the front panel Halted Used for DRS halt operation between coupled sequencers Probe Button Selects the state of the probe button Pulse Generator Sequence Flag 1 2 Selects the pulse generator signal Selects the specified sequence flag Sync 1 2 Selects the specified sync signal CHT1 4 Selects the specified channel test signal Idle Active Idle active flag Sequence Active Sequence active flag Error DRS error flag Pass Valid DRS Pass Valid signal Sequence Reset DRS sequence reset command DRS Sync DRS Sync signal Driver Disable DRS driver disable command Master Reset DRS master reset All DRS coupled sequencers must select the same TTLTRG ECLTRG for the last six listed signals if used These signals are used for DRS signaling The relevant VXlplug amp play API functions e tat964 setTtlTriggers e tat964 setEclTriggers This Invert button is used to invert the associated signal before it is driven onto the selected backplane trigger lin
277. ed bae bet ta ae aa vp bees 5 60 Active Load SettingS i125 toe tede ch tette ting 5 61 Resistive Settirigs eite tree rn 5 62 Channel Connect Settings nennen nnne nene 5 63 5 67 UR14 AUX 5 67 AUX Output State Settings 2 2 0000 5 69 AUX Source Settings t rtp da deste ad a t ide c t dade daa 5 69 Input Bus Select Source 5 70 EGLE Mode Settings dione d i edi e deoa a ede puntas 5 71 09 t eee dte eet Poeti e etes 5 72 Probe Expect a ei fe vc ERR ed 5 84 Pattern Codes ea ade ei D d 5 86 ASCII Binary Data Formati irrien iiia 5 88 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 74 Binary Block 5 89 Table 5 75 Waveform Table Size Settings sssssssssssssssseseeee eee 5 92 Table 5 76 Vector Strobe Settings 5 94 Table 5 77 Vector Bit 58 0 taana 5 96 Table 5 78 Vector Bit Input Mode Settings 5 96 Tabl
278. ee a e dee het uera Aa t aee i dee odas 5 32 Trigger Source Settings esses esee entere 5 33 Astronics Test Systems XXV Model T940 User Manual Publication No 980938 Rev K Table 5 30 Table 5 31 Table 5 32 Table 5 33 Table 5 34 Table 5 35 Table 5 36 Table 5 37 Table 5 38 Table 5 39 Table 5 40 Table 5 41 Table 5 42 Table 5 43 Table 5 44 Table 5 45 Table 5 46 Table 5 47 Table 5 48 Table 5 49 Table 5 50 Table 5 51 Table 5 52 Table 5 53 Table 5 54 Table 5 55 Table 5 56 Table 5 57 Table 5 58 Table 5 59 Table 5 60 Table 5 61 Table 5 62 Table 5 63 Table 5 64 Table 5 65 Table 5 66 Table 5 67 Table 5 68 Table 5 69 Table 5 70 Table 5 71 Table 5 72 Table 5 73 xxvi Trigger Test Condition 5 33 Trigger Input Mode Settings n i te m 5 34 Trigger Event Clear 68 5 34 Pulse Generator Mode Settings eene 5 36 Error Record Basis 5 38 Raw Record Basis Settings esses entrent nnne 5 38 Record Type Settings 5 39 Error Count Basis 0 5 39 Error Address Basis 5 40 Timing Mode
279. eesseseeeeeenneenen nennen nente nennen enne 5 125 Fig re 5 66 Static Data Panel reru turn e n head 5 126 Figure 5 67 Kept Data Pariel at ete eet reete ees 5 128 Figure 5 68 View Results Data eee ne nne 5 129 Figure 5 69 View CRC 2 220 1 0 1 5 131 Figure 5 70 View Errors Address enne 5 132 Figure 5 71 Execution Results View 5 133 Figure 5 72 View Errors Address Panel Hex sse 5 133 Figure 5 73 Record Index 8 5 134 Figure 5 74 View Record Data 5 135 5 75 Probe Data Panel eter 5 136 Figure 5 76 Sequencer Event Status 5 140 Figure 5 77 Sequencer Data DSA Panel sess 5 143 Figure 5 78 DR3E DR9 UR14 Driver Receiver D R Events 5 145 Figure 5 79 DR4 Driver Receiver D R Events 5 146 Figure 5 80 Driver Receiver Data 5 149 Figure 5 81 VXI Trigger Readback Panel 5 150 Figure 5 82 Query Power Results Message 2 444 00 5 151 Figure 5 83 Power Converter Condition Panel
280. eiver boards require calibration stop veniv Ewon Update Section Figure 5 90 Calibration Panel Driver Receiver This control selects which Driver Receiver board to calibrate Calibrate Function This pull down control selects the calibrate function Soft Front Panel Operation 5 160 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The selections for this pull down control are Table 5 108 Calibrate Function Settings Serial Number Setting Description All Selects the following calibrations e Monitor ADC e DVH DVL e CVH CVL e Vcom High Low e source Isink e Monitor ADC Selects the monitor and ADC calibration All DAC Levels DVH DVL Selects the following calibrations e DVH DVL e CVH CVL e Vcom High Low Selects the drive high and low level calibration CVH CVL Selects the compare high and low level calibration Vcom High Low Selects the commutating high and low level calibration ISource ISink Selects the source and sink current calibration IAL IAH Selects the current alarm high and low ADC Reference level calibration Selects the ADC reference voltage calibration Source Sink Load Selects the source sink load resistance calibration Delete Calibration Used to delete section two data This control displays the Driver Receiver board serial number Start Chan
281. el This is the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements A buffered version also comes out the Front Panel External Force is an analog I O signal which is connected to all of the Pin Electronics devices and can be used to force a level on the output of the driver It may also be used to monitor a channel s state EXTFORCE is also used for calibration Real time over voltage detector circuit monitors Driver and Receivers to protect the pin electronics Also clamps the inputs to the V rails Real time temperature monitors for the pin electronics The control logic contains the registers memory and logic that allow the digital board to interface and configure the hardware See Figure H 5 DR9 Driver Receiver Board H 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual CBUS INTERRUPT CONTROL MONITOR V OVERVOLT POWER MONITOR EXTFORCE REFERENCES EXTSENSE REFERENCES EXTSENSE TEMPERATURE MONITORS Figure H 5 DR9 Control Logic Block Diagram Signal Descriptions MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digital board to the Driver Receiver board INTERRUPT Real time signal generated from the power and temperature monitor data Positive bias power required for operation of the Pin Electronics devices from the T94
282. el Calibration nennen nnn 6 1 Performance Verification ee te be e a pee ena 6 1 Environmental tnr et rente nnne 6 2 Voltage MOde ta te ae e te i e etu eu et peus 6 2 V and V 4 24422422 ar nennt tenent ennt enn nene nens 6 2 Warm Up Perloq iue ordin Re E ee o o edid 6 2 Recommended Test 44444040000 0 ennt ennt 6 2 x Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual sizes Vor 6 3 Calibration Interval ditt ttr eeu exea du A 6 3 Calibration Temperature neo HE eei e cedat e idee Pr ee 6 3 Calibration 6 4 ADC Reference via EXTERNAL FORCE sse esent nennen snnt nnne enne 6 5 Select Calibrate FUhcliOn co dee e eene eg annuo dere eden en eg d his 6 5 Select Measurement Delay sse nennen enne nnne nennen nes 6 6 Rumo alora eai errare tea i ens o rix REM A 6 7 Montor x AD Q 8 6 8 Select Calibrate Funcion seeren d erras ade be Re a T
283. el Calibration 6 13 Model T940 User Manual Publication No 980938 Rev K 2 Verify that the DVH DVL calibrate function is now in focus Calibrate Function Select Start and End Channels and Measurement Delay Equipment Basic Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The minimum measurement delay is 100 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hitthe Continue button when the required temperature is reached If the temperature reaches 80 the process continues automatically DRM Calibration Warmup Temperature 100 00 60 00 40 00 10 00 47 00 Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution 2 Review the results in the Status window 3 Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for DVH and DVL in the field controls These values are not in engineering units Programmable Channel Calibration 6 14 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 5 Optional Save the
284. els Four Differential RS 422 485 Four Four ECL single ended or differential Front Panel Connectors The front panel of the DR7 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR7 Driver Receiver DRA or DRB The is comprised of four major logic sections as shown in Figure F 1 Auxiliary Driver amp Receiver I O DR7 Driver amp Receiver I O e Control Logic e Firmware amp NV Data Astronics Test Systems DR7 Driver Receiver Board F 1 Model T940 User Manual Publication No 980938 Rev K AUX DATA 5 8 AUX RH 5 8 AUXILIARY AUX DATA 9 12 DRIVER amp RECEIVER Vo 1 0 CONTROL AUX DATA 1 4 DR7 AUX 1 4 AUX RL1 DRIVER CH DATA 1 32 ks CH 1 32 RECEIVER vo CH RH 1 32 RL 1 32 CONTROL FIRMWARE NV DATA Figure F 1 DR7 Driver Receiver Block Diagram Auxiliary Driver amp Receiver Figure F 2 illustrates the configuration and control of AUX5 8 LVTTL and AUX9 12 ECL Driver amp Receiver I O DR7 Driver Receiver Board F 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual AUX EN 5 8 AUX DATA 5 8 p 74LVC2G125 74LVC2G125 AUX RH 5 8 AUX RH 9 12 MC100ELT24 MC100ELT25 AUX DATA 9 12 MC100ELT24 Figure F 2 Auxiliary Driver amp Receiver I O Block Diagram Signal Descriptions AUX EN 5 8 Auxiliary Enable outputs from the Data
285. ence AUX1A 34 Bi directional General Purpose I O pin AUX2A 36 Bi directional General Purpose TTL I O pin AUX3 A 38 Bi directional General Purpose TTL I O pin AUX4A 40 Bi directional General Purpose TTL I O pin AUX5A 42 Bi directional General Purpose TTL I O pin 50 O series AUX6 A 44 Bi directional General Purpose TTL I O pin 50 Q series AUXT7 84 Bi directional General Purpose TTL I O pin 50 Q series AUX8 A 86 Bi directional General Purpose TTL I O 50 Q series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX10 A 90 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX10 A 91 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX11 A 92 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX11 A 93 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX12 A 94 Bi directional General Purpose ECL I O pin 51 1 Q to 2V AUX12 A 95 Bi directional General Purpose ECL I O pin 51 1 Q to 2V PBUT A 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output BCLK A 96 Output Reserved Astronics Test Systems DR8 Driver Receiver Board G 7 Model T940 User Manual Publication No 980938 Rev K Table G 4 DR8 Pin out by Pin Number DRA
286. ence burst The Error Count can be queried using the tat964_queryErrorFlags function The Error Address Memory stores the sequence step address and index of each pattern that generated an error during the previous sequence burst The Error Address Memory can be queried using the tat964_queryErrorAddress function Note The Error Counter and the Error Address Memory only count log errors that are enabled with BERREN The Record Index Memory contains the data required to align the record memory contents when data is stored sequentially Record Type Indexed for the previous sequence burst The Record Memory contains either the error flag or response data for the previous sequence burst The selections for this pull down control are Table 5 81 Step Record Mode Settings Setting Description None Error counting and all three record memories are disabled Record Count Error Counting enabled Record Error Error counting and all three memories are enabled and the Record Memory is set to record error data Record Response Error counting and all three memories are enabled and the Record Memory is set to record response data For the Record Count settings the record memory can either be set to record all zeros No Error or disabled see Record Mode in Chapter 5 See the Jumping Halting Counting and Logging Errors section of Chapter 8 for more details regarding the counting and recording of errors in the
287. endet 4 10 Terms Used inthis Section o Eee eed e Re tat 4 11 SEQUENCE Eolo 4 13 Masten Glock E 4 13 System EIE 4 14 Test bogics aii 4 14 mE 4 14 Triggeribogle dete oit beoe 4 14 Counter Timer amp Pulse Generator sss eene enne nnne 4 14 Sequence Coritroller e iere ee terret cro urn itae e e cents 4 14 E S EE 4 14 Probe Flag e pete e D tee EN i ee ay 4 14 Pattern RAM n e epe 4 15 c 4 15 Frequency Synthesizer ssssssssssssssesss esee entere inttr innen enne sinis entere 4 15 SEQUENCE tte 4 15 Channel Control pate oe ke YR KE ee ERR RAEAN RAAS 4 15 AUX amp Probe Contro acii igit etd eoi i o ede eek deed ez 4 15 Driver RECCIV OR TIE 4 16 Chapter gt EE 5 1 Soft Front Panel Operations tesciscssisessccsaccastensseasscnaatienasinnsccenassbacentstanensdinaceasscnansassacieeacten 5 1 MEP BASICS e TEM 5 1 iiec eee teet ener eie end ee Pese sie edd 5 2 Company E090 c ife n te er E ek e Ae medio e Et DOG Res 5 4 Active PED RHENUM IRI P 5 4 Chassis ET 5 4 Module
288. endix A for those limitations Notes 1 The 7940 is designed to accurately count log DRS Errors in the Master at a 50MHz data rate 2 When a Sequencer is Independent the DRS Linked option will not Count or Log anything Pipelining and non Pipelining Before Jumping and Halting on various Pass Fail conditions can be presented an understanding of pipelining is required e The pipeline may be from 0 16 Patterns deep The 0 pipeline depth will hereafter be called a zero pipeline depth or non pipelined A pipeline depth of 1 16 will hereafter be called non zero pipeline depth or pipelined Azero pipeline depth is primarily used when it s desired to perform a Jump on Pass Fail in a Seq Step where the deciding Error may occur on even the last Pattern of the Seq Step This allows one to Halt immediately on Patterns that have a Fail or Pass There are performance limitations for the zero pipeline depth covered in the Performance Considerations section below e Anon zero pipeline depth means that the Error is offset delayed by the depth of the pipeline In this case a Halt on Pass or Fail will occur later by the depth of the pipeline For Jumping on a Pass or Fail there is a Jump Pass Fail attribute that affects how Jumps are handled This is detailed in Section 7 The non zero pipeline depth will handle data rates at 2 but there is a minimum pipeline depth required depending on the Data Rate T
289. eout Jump Type Reset None v Gosub Ret Loop Count Loop Counter Pass Fail Clear False NM 40 210 Defaut 7 Sequence Flag 1 Low bi ming em Record Eror Sequence Flag 2 Pattems Properties N Record Count v Record Error Record Response Figure 8 4 Step Record Mode Control on Edit DSA Sequence Step Panel As shown the choices are e None e Record Count e Record Error Advanced Topics 8 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Record Response For each Sequence Step this selection can be made Table 8 2 describes how these selections affects what s recorded in the Record Memory Table 8 2 Summary of the Record Memory Action for each Step Record Mode Step Record Mode Record Memory Action None Don t record anything Record Count Don t record anything or record non Errors Record Errors Record Errors Record Response Record Response The first choice means that nothing will be recorded in the Record Memory for any pattern in this step But this means different things based on the Record Type See the Record Type section below for more information The second entry provides two choices This is programmed on the Config Configure Module panel as shown in Figure 8 4 below The relevant VXIplug amp play and ARI functions e API tat964_setSequenceRecordMode e ARI AssignPtgRecordMode VXIO 2 INSTR Configure M
290. ep 0 Pattern Memory Free Idle Active false ast step stop standby Sequence Active false finish mode Halt flag false Paused flag false STANDBY gt Astronics Test Systems Soft Front Panel Operation 5 113 Model T940 User Manual Publication No 980938 Rev K Setting Description Entry Condition Active step User Pattern Memory Free IDLE Idle Active true Sequence Active false Halt flag false Paused flag false Active step User Pattern Memory Busy amp execute idle last step stop idle finish mode ACTIVE HALT Idle Active false Sequence Active true Halt flag false Paused flag false Active step User Pattern Memory Busy Idle Active false Sequence Active true Halt flag true Paused flag false Active step User Pattern Memory Free amp execute resume halt PAUSE Idle Active false Sequence Active true Halt flag false Paused flag true Active step User Pattern Memory Busy OA amp RDA amp amp amp WN gt D pause The following table describes the state transitions and the execute panel control to perform it Table 5 85 Execute State Transition Description Transition Description Soft Front Panel Control pon Power on NA reset Sequencer reset e Depress Reset command
291. er e tat964 setJumpTrigger e tat964_setHaltTrigger e tat964_setExecuteStartTrigger e tat964_setExecuteStopTrigger e tat964 armldleSequence e tat964 armSequence Test Condition This pull down control programs the trigger test condition The selections for this pull down control are Table 5 30 Trigger Test Condition Settings Setting Description Low Level Test for a low level High Level Test for a high level Rising Edge Test for a rising edge Falling Edge Test for a falling edge The relevant VXlplug amp play API functions are e tat964_setHandshakePauseTrigger e tat964 setHandshakeResumeTrigger Astronics Test Systems Soft Front Panel Operation 5 33 Model T940 User Manual Publication No 980938 Rev K e tat964 setPhaseResumeTrigger e tat964 setJumpTrigger e tat964 setHaltTrigger e tat964_setExecuteStartTrigger e tat964_setExecuteStopTrigger Input Mode This pull down control programs the trigger input mode The selections for this pull down control are Table 5 31 Trigger Input Mode Settings Setting Description Normal Do not modify input signal before testing Inverted Invert input signal before testing The relevant VXI plug amp play API functions are e tat964_setHandshakePauseTrigger e tat964 setHandshakeResumeTrigger e tat964 setPhaseResumeTrigger e tat964 setJumpTrigger e tat964 setHaltTrigger e tat964_setExecuteStartTrigger e tat964_setExecuteStopTrigger Edge Te
292. er 1 Select Pause Trigger 1 to edit Pause Trigger 1 Resume Select Pause Trigger 1 Resume to edit Pause Trigger 2 Select Pause Trigger 2 to edit Pause Trigger 2 Resume Select Pause Trigger 2 Resume to edit Phase 1 Resume Select Phase 1 Resume to edit Phase 2 Resume Select Phase 2 Resume to edit Phase 3 Resume Select Phase 3 Resume to edit Phase 4 Resume Select Phase 4 Resume to edit Execute Start Select Execute Start to edit Execute Stop Select Execute Stop to edit Halt Select Halt to edit Jump 1 Select Jump 1 to edit Jump 2 Select Jump 2 to edit Jump 3 Select Jump 3 to edit Jump 4 Select Jump 4 to edit Note See the Jumping Halting Counting and Logging Errors section of Chapter 8 for a more in depth explanation Source This pull down control programs the trigger source Soft Front Panel Operation 5 32 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The selections for this pull down control are Table 5 29 Trigger Source Settings Setting Description None No trigger source selected AUX1 AUX12 Trigger source set to front panel signal CHT1 Trigger source set to channel test 1 ECLTRGO 1 Trigger source set to VXI ECL trigger TTLTRGO 7 Trigger source set to VXI TTL trigger LTBO 7 Trigger source set to Linked Trigger bus signal The relevant VXlplug amp play functions are e tat964_setHandshakePauseTrigger e tat964 setHandshakeResumeTrigger e tat964 setPhaseResumeTrigg
293. er DRA or DRB 408122 XXX Front Panel Signal Flat Ribbon Cable 1 per DRA or DRB 408123 XXX Front Panel Power Cable 1 per DRM 408091 XXX Note 1 XXX denotes the length in feet 408123 006 would indicate a six foot Astronics Test Systems DRM Front Panel 3 3 Model T940 User Manual Publication No 980938 Rev K J200 J201 flat ribbon mating cable 2 DRM cable assemblies are open at one end Front Panel LBUS Lockout Keys The VXIbus defined LBUS Lockout Keys are designed to prevent adjacent VXI Modules with incompatible logic families from connecting to the Local Bus They are attached to the exterior of the module at the top of the front panel Figure 3 4 illustrates the two types of LBUS Lockout Keys used for this product Figure 3 5 shows the application of Lockout Keys for the T964 A C type C type Figure 3 4 LBUS Lockout Keys The LBUS Lockout Key is fitted to all modules The T964 requires the use of the A C type LBUS Lockout Key PN 455540 on all modules The T940 may use the C type key PN 455541 for the leftmost module as long as the jumper block for the module is NOT in the Primary position and it shouldn t be if it s the leftmost T940 DRM DRM Front Panel 3 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual LBUS LOCKOUT KEYS RESOURCE T940 MANAGER Figure 3 5 LBUS Lockout Configuration LBUS Lockout Key Installation In order to accommodate the V
294. er Manual Publication No 980938 Rev K System Clock This block selects the sequence clock signal used by the sequence controller Test Logic This block determines if a valid conditional jump is enabled or not Record Control This block generates the address for the Record RAM based on the Recording Mode This block also contains the error address memory record index memory and burst error counter Trigger Logic This block takes in Channel Test signals AUX inputs and VXI triggers and Linked Trigger bus inputs and uses them to enable jumps start stop the sequencer pause the Master Clock or halt the sequence controller Edge capture conditions that are to be cleared are also handled by this block Counter Timer amp Pulse Generator The pulse generator can be used to generate triggers system clock or as a AUX output signal The counter timer can be used to measure frequency or time interval data from any channel or AUX input Sequence Controller This block contains the Sequence RAM which defines the order in which Patterns will be output input As such this block provides the addressing to the Pattern RAM and the Record RAM The Sequence RAM also contains the TOCLK period Jump Type Jump Addresses looping controls loop counts Jump codes CPP and other control bits for Pause Code Pause Resume Options Record Capture type Waveform control and Phase Trigger Type along with 2 Sequence Flags that can be output The T940 Sequen
295. er Receiver Board G 9 Model T940 User Manual Publication No 980938 Rev K Table G 6 DR8 Pin out by Pin Number DRB Pin No Signal Pin No Signal 1 SIG GND 51 SIG GND 2 CH33 52 CH49 3 SIG_GND 53 SIG_GND 4 CH34 54 CH50 5 SIG GND 55 SIG GND 6 CH35 56 CH51 7 SIG GND 57 SIG GND 8 CH36 58 CH52 9 SIG GND 59 SIG GND 10 CH37 60 CH53 11 SIG GND 61 SIG GND 12 CH38 62 CH54 13 SIG GND 63 SIG GND 14 CH39 64 CH55 15 SIG GND 65 SIG GND 16 40 66 56 17 SIG GND 67 SIG GND 18 CH41 68 CH57 19 SIG GND 69 SIG GND 20 CH42 70 CH58 21 SIG_GND 71 SIG_GND 22 CH43 72 CH59 23 SIG_GND 73 SIG_GND 24 CH44 74 CH60 25 SIG GND 75 SIG GND 26 CH45 76 CH61 27 SIG_GND 77 SIG GND 28 CH46 78 CH62 29 SIG_GND 79 SIG_GND 30 CH47 80 CH63 31 SIG_GND 81 SIG_GND 32 CH48 82 CH64 33 SIG_GND 83 SIG_GND 34 AUX1 B 84 AUX7 B 35 SIG GND 85 SIG GND 36 AUX2 B 86 AUX8 B 37 SIG GND 87 SIG GND 38 AUX3 B 88 AUX9 B 39 SIG GND 89 AUX9 B 40 AUX4 B 90 AUX10 B DR8 Driver Receiver Board G 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal Pin No Signal 41 SIG GND 91 AUX10 B 42 AUX5 B 92 AUX11 43 SIG GND 93 AUX11 B 44 AUX6 B
296. er Requirements Voltage Peak Current Dynamic Current 45V 4 3 A 25 mA 5 2 V 25A 1 mA 2V 608 mA 7 4 mA 12 V 0 0 12V 0 0 24 V 0 0 24V 0 0 Environmental Temperature Operating 0 C to 45 C Storage 40 C to 70 Humidity non condensing 0 C to 10 C Not controlled 10 C to 30 C 596 to 9596 5 RH 30 C to 40 C 596 to 7596 5 RH 40 C to 50 C 5 to 5596 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR8s Max 4 68 los 8 9 mmH 0 Typ 4 60 lps 4 5 mmH 0 Front Panel Current Requirements NA MTBF ground benign DR8 257 335 hours T940 180 885 hours T940 DR8 106 220 hours T940 DR8 DR8 66 922 hours Safety Low Voltage Directive 73 23 Dimensions 20 x 114 x 305 mm EMC Council Directive Emission EN61326 1 2006 Class A 89 336 EEC Immunity 61326 1 2006 Table 1 Designed to Meet Testing in Progress BS EN61010 1 2010 Designed to Meet Testing in Progress DR8 Driver Receiver Board G 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual DR8 Signal Description DRB Figure G 4 J200 and J201 Connectors DRA I O Channels J200 Table G 3 DR8 DRA I O Channels J200 Name Pin No Description CH1 CH32 Various Bi directional High speed TTL channels SIG_GND Various Signal Ground refer
297. er VXI 4 0 compliant mainframe A compatible VXI slot 0 controller shall be installed and used to control software execution At its most basic level calibration is entirely internal and doesn t require any external instruments unless the references and monitor paths are being re calibrated An example configuration is shown in the diagram Cergas Calibration Interval The T940 DRM should be calibrated at a regular time interval determined by the accuracy requirements of your application A one year interval is adequate for most applications Accuracy specifications are valid only when calibration is performed at regular time intervals Accuracy specifications presented herein are not valid beyond the one year calibration interval Astronics Test Systems does not recommend extending calibration intervals beyond three years Calibration Temperature The T940 DRM should be calibrated at the nominal temperature of your application Application temperature can depend on the module type and VXI mainframe characteristics as well as the exact usage of the features of the module Using more channels simultaneously at higher selected slew rates for Astronics Test Systems Programmable Channel Calibration 6 3 Model T940 User Manual Publication No 980938 Rev K example can create a higher operating temperature For best accuracy run the Soft Front Panel during a typical test execution and monitor the programmable channel temperatures on DRB
298. eral Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 B 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT B 46 Bi directional Probe Button Input PMODE B 47 Output Probe Support Output BCLK B 96 Output Reserved DR2 Driver Receiver Board C 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table C 6 DR2 Pinout by Pin Number DRB Pin No Signal 1 SIG GND 2 CH33 3 CH33 4 CH34 5 CH34 6 CH35 7 CH35 8 CH36 9 CH36 10 CH37 11 CH37 12 CH38 13 CH38 14 CH39 15 CH39 16 CH40 17 40 18 41 19 41 20 42 21 42 22 CH43 23 CH43 24 CH44 25 CH44 26 CH45 27 CH45 28 CH46 29 CH46 30 CH47 31 CH47 32 CH48 33 CH48 34 AUX1 B 35 AUX1 B 36 AUX2 37 AUX2 B 38 AUX3 B 39 AUX3 B 40 AUX4 B Astronics Test Systems Pin No Signal 51 SIG GND 52 49 53 49 54 50 55 CH50 56 CH51 57 CH51 58 CH52 59 CH52 60 CH53 61 CH53 62 CH54 63 CH54 64 CH55 65 CH55 66 CH56 67 CH56 68 CH57 69 CH57 70 CH58 71 CH58 72 CH59 73 CH59 74 CH60 75 CH60 76 CH61 77 CH61 78 CH62 79 CH62 80 CH63 81 CH63 82 CH64 83 CH64 84 AUX7 B 85 SIG GND 86 AUX8 B 87 SIG GND 88 AUX9 B
299. erator will not work in any of its modes until armed The relevant VXlIplug amp play API function is e tat964 armPulseGenerator Soft Front Panel Operation 5 124 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Stop PG The Stop PG command button stops the pulse generator The relevant VXlplug amp play API function is e tat964 stopPulseGenerator Analyze the Execution Results After sequence execution has been performed the final step is to analyze the results to determine if the recorded input data is valid and if it matches the expected results The Burst Error LED and Errors are result indicators located on the execution panel Additional result data be accessed from the Execute gt DSx menu bar View selection Where x is the sequencer you wish to query VXIO 2 INSTR Execute DSA Static Data ion Kept Data Results Sequencer Events Sequencer Data Power Converter Alert 2 Driver Receiver Events Alet O V N Channel Drivers On Embed Driver Receiver Data VXI Trigger Readback Power Query Finish Mode Step P Power Converter Condition Standby 7 7 0 Counter Timer CRC CRC16 vi Figure 5 65 Execute DSA View Menu These panels allow the user to query the recorded memory results and status indicators from the previous sequence execution Static Data The static data display is accessed from the Execute
300. erature Refer to the Calibration Temperature section in Chapter 6 for more information Once calibration has begun progress data is displayed in the Status control The calibration run procedure creates a file calData_ lt SN gt txt and writes Soft Front Panel Operation 5 162 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual calibration data analyses data This file can be used to validate calibration results iv UO Driver Receiver Calibrate Function DRA All DRB Start Chan 1 Meas Delay 0300 End Channel Sf 36 Figure 5 93 Calibrate Run Panel The relevant VXIplug amp play API functions are e tat964 calibrateChannel e tat964 setRefOutput e tat964 setRefVoltage e tat964 setForceConnect iat964 setForceLoad e iat964 setRefLoad Verify This command button executes the selected calibrate function verify routine The SFP will prompt the operator to confirm the action and then apply power to the Driver Receiver board Astronics Test Systems Soft Front Panel Operation 5 163 Model T940 User Manual Publication No 980938 Rev K Run Calibrate Verify Ww Figure 5 94 Confirm Verify Panel The operator will be prompted to select the directory where the verification report will be created and saved iano 009007 rend C Program Files 86 1 Foundation NVISANWinNTvat964 Lock in Name Date modified J evibuild tat96
301. ere is the sequencer you wish to execute Execute Idle Step 30 i am Mode Disable Y Stop Mode Patem v CRC CRCI6 Sequence Active Step Number Pattem Address Record Count Timing Set 0 000E 0 0 0 0 0 Figure 5 62 Executing Sequence Panel The following sections describe the execution overview as well as the indicators and controls of the execute panel Soft Front Panel Operation 5 112 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Execution Overview The sequencer execution state diagram is illustrated in the following figure reset IDLE p ad m A NS p DM P 4 pec execute execute idle halt last step stop reset idle finish mode S manual resume jet single ste execute X 9 pon RESET execute idle ACTIVE Se M Ne ause execute J X manual resume or external resume reset last step stop IN standby finish mode X inc N ua STANDBY PAUSE P E reset Figure 5 63 Execute State Diagram The following table describes the six execute states of the DRM and how the state is entered Table 5 84 Execute State Description Setting Description Entry Condition RESET Idle Active false pon reset Sequence Active false Halt flag false Paused flag false Active st
302. erial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions CONTROL DR8 Characteristics Signals used to program firmware and NV DATA Table G 1 DR8 Characteristics Description Characteristics Digital Type TTL 74LVC2G125 Channels 32 single ended SE per I O board Per channel relay isolation Output Voltage Vo 0 55 V max Vou 3 8 V min Output Drive Current typical Source Sink 32 mA Output Impedance Program selectable per pin Direct or 100 O Series 101 Direct or 50 O Series 102 Input Voltage 0 8 V max Vin 2 0 V min Input Impedance Program selectable per pin Skew Channel to Channel 600 pull up to VCC 45 0 V 510 pull down to ground Ch1 32 Aux1 4 only lt 3 ns drive and compare Auxiliary Channels per I O board TTL Aux 1 4 Like the channels with optional pull up and pull down TTL Aux 5 8 ECL Aux 9 12 Single ended or Differential AUX I O is bi directional Per channel relay isolation Data Rate max 50 MHz input and output Note 1 Includes switch impedance of 90 ohms Astronics Test Systems DR8 Driver Receiver Board G 5 Model T940 User Manual Power Requirements Publication No 980938 Rev K Table G 2 DR8 Pow
303. es 1 04167 ns per count timing 20 counts gives a 20 8333 ns period or 48 MHz Using the 500 MHz clock with 21 counts yields a data rate of 47 619 MHz the closest pattern rate achievable using the 500 MHz clock The relevant VXlplug amp play API function is e tat964 setMasterClockSource Astronics Test Systems Soft Front Panel Operation 5 25 Model T940 User Manual Publication No 980938 Rev K System Clock This pull down control programs the sequencer System Clock source The System Clock signal defines the pattern period The selections for this pull down control are Table 5 22 System Clock Source Settings Setting Description Typical Usage Internal System Clock source set to the DRM or DRS where internal master clock TOCLK internal period defined by the timing is acceptable sequencer step AUX1 AUX12 System Clock source set to the Auxiliary line is assigned the function of external front panel signal external clock where AUX1 4 1 2 50 MHz when programmable threshold or load is required with the clock AUX5 8 LVTTL source 1kHz 50 MHz AUX9 12 Single ended or differential ECL source from 1 kHz to 50 MHz ECLTRGO System Clock source set to the External clock from another VXI instrument VXI ECLTRGO provided across the VXI backplane Pulse System Clock source set to the For test purposes or for when pulse width Generator internal pulse generator signal control of the system clock is req
304. es If the instrument fails to perform within the specified limits the instrument must be tested to find the source of the problem If there is a reasonable suspicion that an electrical problem exists within the T940 DRM perform a complete self test on the instrument prior to running a verification or calibration procedure Astronics Test Systems Programmable Channel Calibration 6 1 Model T940 User Manual Publication No 980938 Rev K Environmental Conditions The T940 can operate over an ambient temperature range of 0 to 45 Adjustments should be performed under laboratory conditions having an ambient temperature of 25 5 and at relative humidity of less than 80 Turn on the power to the T940 and allow it to warm up to the desired operating temperature before beginning the adjustment procedure If the instrument has been subjected to conditions outside these ranges allow additional time for the instrument to stabilize before beginning the calibration procedure Voltage Mode For the DR3E DR9 and UR14 there are two voltage mode settings available 15 to 17 and 7 to 24 Each voltage mode requires calibration and the data for both is stored in non volatile memory Be sure to select the Voltage Range mode which is required by the application prior to calibration V and V Requirements For the DRY and UR14 the V and V bias voltage level requirements for calibration are listed below e V mustbe gt
305. et eiat 5 128 neqiie ti iib E E nd diiit 5 129 SAVE Resulls e etu tta cms 5 129 CRG Save File Fottnal crie een dada ae betae ies 5 129 Error Address Save File Formart esses ener nnne nra nnns nnn 5 130 Record Index Save File Format esses ennt enne nnn nnns nn 5 130 Record Data Save File Formal er te ree ace i ed ve shies 5 130 Probe Data Save File 00100 0 0 0 5 131 8 ea eden eee 5 131 viii Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Error Address Display iot pei Ep ri eder ae eee 5 132 Record IndexsDisplay ie It er P Ee ht ede Ert Ere ue 5 133 Record Data Display E ette i die 5 134 Probe Data Memory Display etti tte cete itt e ee 5 135 Status Indicator Pariels 553 ndn I eme el 5 139 s quencer Evehls 3 on i edu die uide egre E 5 139 Enable os tse sU ELE ds CE 5 142 P 5 142 I A 5 142 Cleat Eventer PH 5 142 sequencer Data Panel reperiai maranda NEST Ye do p 5 142 Counter ACliVe 3 ces m Le Ete teh e tr e d e i d 5 143 Record Index Counties iie
306. ft off when re used Note There are 2 bits associated with each of the 16 loop counters One bit the Counter Active CA bit gets set when the loop counter is used Bit two the Use Counter Once UCO bit is programmed by the user If UCO is set the CA bit will not be reset when exiting the loop thus the counter cannot be re used once the count is exhausted If not set the CA bit is reset when the count is exhausted and the next sequence step begins Loops can be done around one or more Sequence Steps and the group of sequence steps need not be consecutive i e one or more intermediate Jumps could have occurred A Counted Loop command is ignored if the Loop Count is zero A Jump Always Jump condition is not recommended for looping group of Sequence Steps a Sequence Reset or Stop Looping command would be the only way to stop it Subroutines cannot be nested Subroutines may consist of multiple Sequence Steps which contain Loops and or Jumps The Sequence Step designated as the LSTSEQ may have Loops or Jumps to a subroutine Upon completing the Loops or returning from a Subroutine execution will proceed to the Finishing Sequence All Jumps are to the Jump Sequence Address JSA unless a Vectored Jump is requested in which case the Jump will be to the Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Sequence Address provided by the Vector Jump Address Memory Pattern Control Instructi
307. g The group state must be off to update this attribute and all group IO levels are set to OV The relevant VXlIplug amp play function is e tat964 setGroupAttribute IO Min This numeric entry specifies the minimum drive compare level that can be programmed for the selected group This level also establishes the group V voltage level The IO Min valid range is 31 V to 0 V and must be lower than IO Max The group state must be off to update this attribute and all group IO levels are set to OV The relevant VXlIplug amp play function is e tat964 setGroupMinMax IO Max This numeric entry specifies the maximum drive compare level that can be programmed for the selected group This level also establishes the group V voltage level The IO Max valid range is 0 V to 31 V and must be high than IO Min The group state must be off to update this attribute and all group IO levels are set to OV The relevant VXlplug amp play API function is e tat964 setGroupMinMax Slew The group slew specifies the slew of the group channels The selections for this pull down control are Soft Front Panel Operation 5 16 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 13 Group Slew Attribute Settings Setting Description Fast Fast recommended for low voltage swings and fast data rates Med Medium Slow Slow Def Default Low Low recommended for high voltage swings and low data rates
308. g amp play API function is e tat964 queryErrorFlags Power Converter Alert D R Alert Illuminated red indicates that one or more fault bits are set in the Power Converter Condition register Illuminated yellow indicates that the High Current bit is set in the Power Converter Condition register The relevant VXlplug amp play API function is e tat964 queryPowerConverterCondition Illuminated red indicates that one or more bits are set in the Driver Receiver event register The relevant VXlplug amp play API function is Soft Front Panel Operation 5 116 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual e tat964 queryFrontEndCondition Sequence Active This numeric indicator displays the execution time of the previous sequence burst 10 ns resolution 10 ns with an accuracy of 500 ppm up to 43 sec The relevant VXIplug amp play function is e tat964 querySequenceActive Step Number This numeric indicator displays the current sequence step address The relevant VXlplug amp play API function is e tat964 querySequencerStatus Pattern Address This numeric indicator displays the current pattern address The relevant VXlplug amp play API function is e tat964 querySequencerStatus Record Count This numeric indicator displays the current record count The relevant VXlplug amp play API function is e tat964 queryRecordCount Timing Set This numeric indicator displays the current timing set
309. gt lt line feed step offset data line feed gt Where header STEP OFFSET RECORD DATA step Step number of the error offset Pattern number data Record Memory contents Soft Front Panel Operation 5 130 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Probe Data Save File Format The Record Data results are saved in the following format header line feed step offset data line feed gt Where lt gt STEP OFFSET RECORD DATA step Step number of the error offset Pattern number data Probe Memory contents CRCs Display The CRC memory display is accessed from the Execute gt DSx gt View gt Results menu bar selection and setting the View control to CRCs Where x is the sequencer you wish to query Figure 5 69 View CRC Panel CRCs can be accumulated for all 32 channels as well as AUX1 which is dedicated for the probe channel shown at the left The relevant VXlplug amp play functions e tat964 queryCrc e tat964 queryProbeCrc Astronics Test Systems Soft Front Panel Operation 5 131 Model T940 User Manual Publication No 980938 Rev K Error Address Display The Error Address memory display is accessed from the Execute DSx View Results menu bar selection and setting the View control to Errors Address Where x is the sequencer you wish to query VXI0 2 INSTR Execu
310. h a probe AUX1 A is a programmable level I O signal Calibration output signal for the external probe Supplies compensation square wave and DC Calibration outputs When not used with a probe AUX2 A is a programmable level I O signal Supplies 12V and 12V to the external probe module This is a control signal from the Sequencer for support of external probe operations This is a Probe Button input signal to the Sequencer for support of external probe operations When PROBE DETECT is true this input is inactive Any Astronics Test Systems Publication No 980938 Rev K PROBE Model T940 User Manual DUT offsets are applied to the external probe module When not used with the external probe this signal comes from the UUT and can be used to offset the reference levels up to 3V Excursions of DUT beyond 390 mV with respect to signal ground yields a GND FAULT signal Probe Master 100 MHz probe assembly MODEL 6139 that includes a push button and LED that connect to the External Probe Module via an included cable and connector CONNECT SWITCH is a push button on the PROBE that is used to signal a CONNECT LED sequence start to the T940 Sequencer via PBUT is an LED on the PROBE that when lighted indicates contact detection PROBE DETECT this input detects the presence of an external probe CBUS Astronics Test Systems module When detected the API functions for the UR14 probe are activated An internal
311. h is reserved for the Resource Manager See Figure 2 6 Always check VXI connectors P1 and P2 for bent pins prior to installation When inserting the DRM into the chassis it should be gently rocked back and forth to seat the connectors into the backplane receptacles Figure 2 6 Installing the DRM into a Chassis Installation 2 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure 2 7 1263 Series VXI Chassis 1263HPf top 1263HPr bottom The optional Racal Instruments 1263 High Power 13 slot chassis series Figure 2 7 is recommended for multiple DRMs which are populated with multiple DR3e DR4 or DR9 modules These chassis have an integrated power supply and enhanced cooling that will support such DRMs For information on these products contact your Astronics Test Systems sales representatives Any VXI chassis will support a DRM that is populated with DR1s DR2s DR7s DR8s UR14s Astronics Test Systems Installation 2 9 Model T940 User Manual Publication No 980938 Rev K Initial Power On The DRM is normally a register based VXI module with an embedded processor to manage standard VXI communications 1 Turn off the chassis power before installing the DRM 2 Once the DRM is properly installed in a VXI chassis turn on the chassis power The SYSFAIL line will be immediately driven The DRM embedded processor will verify the processor core and VXI commu
312. he end of the pattern period e Phases and Windows are allowed to extend past the initial pattern period if multiple clocks per pattern CPP gt 1 are programmed See Clocks per Pattern later in this chapter Advanced Timing Set Features Two advanced timing set features are available 1 Phase Window Spanning Soft Front Panel Operation 5 76 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 2 Idle Standby Timing Phase Window Spanning Phase Window spanning allows the user to Assert Open the timing signal in one pattern and Return Close the signal in a different pattern The following steps describe how to span timing signals across multiple patterns 1 Disable the Return signal in the first pattern s timing set by setting the Return value equal to the pattern period 2 Disable the Assert and Return signal in any patterns between the first and the last pattern being spanned by setting the Assert Value to zero and the Return value equal to the pattern period 3 Disable the Assert signal in the last pattern by setting the Assert Value to zero For example let s assume we have three patterns and each pattern has a period of 100 We want the Phase 1 Assert at 50 of the first pattern and Return at 75 of the third pattern Pattern 1 TS1 Assert 50 Return 100 Pattern 2 TS2 Assert 0 Return 100 Pattern 3 TS3 Assert 0 Return 75 Idle Standby Timing One of the unique features of the DRM is
313. he positive side of the ECL and the LVTTL selections share a pin Changing a pin from ECL to LVTTL requires changing the Sequencer assignment of the function as well For example if External UR14 Driver Receiver Board 1 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Clock is assigned to the LVTTL AUX A 5 then subsequently changing that that pin to ECL it would require assigning the External Clock to AUX A 9 as well Signal Descriptions Figure 1 3 AUX DATAS3A AUX AUX RH3A AUX H 9 12 A Auxiliary Data output from the Data Sequencer to the LVTTL output buffer Auxiliary Enable output from the Data Sequencer to the LVTTL output buffer Auxiliary Response Input to the Data Sequencer from the LVTTL input buffer Auxiliary Response Inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 AAuxiliary Data outputs from the Data Sequencer to the AUX EN 9 12 A AUX 5 8 AUX EN 5 8 A AUX RH 5 8 A I O CONTROL AUX3 A AUX 9 12 A AUX 9 12 A AUX 5 8 Astronics Test Systems positive side ECL output buffers Auxiliary Data outputs from the Data Sequencer to the negative side ECL output buffers Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffer Auxiliary Response Input to the Data Sequencer from the LVTTL input buffers Control Logic signals to c
314. herwise proceed to the next Seq Step also set a fault flags 14 1 0 1 1 0 If NOT IN SUB set the IN SUB flag save the Return Seq addr and jump to JSA e f IN SUB jump to the Return Seq and clear the IN SUB flag also set a fault flags 15 0 0 1 1 1 e f IN SUB jump to the Return Seq and clear the IN SUB flag e Otherwise proceed to the next Seq Step also set a fault flags 16 1 0 1 1 1 e If LC 0 and IN SUB jump to the Return Seq and clear the IN SUB flag e If LC gt 0 CA 0 and NOT IN SUB load the designated Loop Counter set CA 1 set the IN SUB flag save the Return Seq addr and jump to JSA e f CA 1 and NOT LCD and NOT IN SUB set the IN SUB flag save the Return Seq addr decrement the loop counter and jump to JSA e If CA 1 and LCD reset CA if UCO 0 also if IN SUB jump to the Return Seq and clear the IN SUB flag e Otherwise if LC gt 0 CA 0 INSUB jump to the return Seq and clear the INSUB flag Astronics Test Systems Advanced Topics 8 39 Model T940 User Manual Publication No 980938 Rev K Jump LSTSEQ RTN SUBRT CLOOP Action Comments Otherwise proceed to the next Seq Step also set a fault flag 17 The Seq loops or finishes 18 Jumps to JSA 19 The Seq loops or finishes 20 O O OIO e If LC 0 the Seq loops finishes e
315. his is covered in the Pipelined Depth Calculation section below The Pipeline Depth is set on the Edit gt Data Sequencer A B Sequence Parameters panel The relevant VXlplug amp play API and ARI functions are API tat964_setConditionPipelineMask e ARI AssignPtgPipelineMask Astronics Test Systems Advanced Topics 8 13 Model T940 User Manual Publication No 980938 Rev K BR VXD 2NSTR Edit DSA Parameters aloof Loop Counter Terminal Count Action 1C2 1C3 164 1065 106 1 7 Reload Reload Reload Reload Reload Reload Reload Reload LC8 1 9 c10 2 4 5 Figure 8 10 Setting the Pipeline Mask in the Edit DSA Parameters Panel The setting for a pipeline depth of 8 is shown Jumping and Halting on Pass Fail Similar to the Counting and Logging of Errors there is a Basis for Jumping and Halting on Pass Fail conditions Jumping and Halting is programmed on the same panel as before The relevant VXlplug amp play API and ARI functions are e tat964 setPassFailParameter e ARI AssignPatTimeGroup Advanced Topics 8 14 Astronics Test Systems Publication No 980938 Rev K Step Muti w Phase v Model T940 User Manual Drive Fault Disable w Figure 8 11 Setting the Pass Fail Basis in the Configure DSA Settings Panel A qualified Pass Fail Basis in this case is based on CONDEN Condition Enable CONDEN is programme
316. i directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 A 94 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX12 A 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT A 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output GNDREF A 49 Output Ground Reference output from the Pin Electronics devices MONITOR A 50 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time BCLK A 96 Output Reserved EXTFORCEA 98 Input External Force routed to all of the Pin Electronics devices Astronics Test Systems DR3e Driver Receiver Board D 13 Model T940 User Manual Publication No 980938 Rev K Table D 7 DR3e Pinout by Pin Number DRA Pin No Signal Pin No Signal 1 SIG GND 51 SIG GND 2 CH1 52 CH17 3 SIG GND 53 SIG GND 4 CH2 54 CH18 5 SIG GND 55 SIG GND 6 CH3 56 CH19 7 SIG GND 57 SIG GND 8 CH4 58 CH20 9 SIG_GND 59 SIG_GND 10 CH5 60 21 11 SIG GND 61 SIG GND 12 CH6 62 CH22 13 SIG GND 63 SIG GND 14 CH7 64 CH23 15 SIG GND 65 SIG GND 16 CH8 66 CH24 17 SIG GND 67 SIG GND 18 CH9 68 CH25 19 SIG GND 69 SIG GND 20 CH10 70 CH26 21 SIG GND 71 SIG GND 22 11 72 27
317. ics Test Systems Driver Receiver Board E 3 Model T940 User Manual Publication No 980938 Rev K Channel Driver amp Receiver Figure E 2 illustrates Driver amp Receiver for a single channel Solid State Driver Current Setting DRIVER RECEIVER DACS DRIVER CONTROL Figure E 2 DR4 Driver Receiver Block Diagram Signal Descriptions DATA Channel data output signal from the Data Sequencer to the programmable output driver EN Channel enable output signal from the Data Sequencer to the solid state switch for tristate OC Over Current signal from the Control logic to the Digital Board Detection of an OC event will disable the channel output in the Series mode OC DETECT Over Current detect from the programmable Driver sense comparator Detection is controlled by Source Sink DAC levels Drives the OC line to the Digital board In Direct mode an OC DETECT will set SHUTDOWN for the driver two adjacent channels DVH DVL Drive High level Drive Low Level per channel CVH CVL Compare High Level Compare Low Level shared between two adjacent channels CH1 and CH2 CH3 and CH4 etc RH Response High input signals to the Data Sequencer from the programmable input receivers 1 Good 1 DR4 Driver Receiver Board E 4 Astronics Test Systems Publication No 980938 Rev K RL RELAY CNTRL CH I O TEMPMON VD VD 0 Good 0 Model T940 User Manual Response Low inpu
318. ics Test Systems Soft Front Panel Operation 5 123 Model T940 User Manual Publication No 980938 Rev K Resume Stop Reset The Resume command button terminates a pause or halt state and sequence execution continues See the Pause and Halt section in Chapter 8 for additional details about resuming a pause or halt The relevant VXIplug amp play function is e tat964 resumeSequence The Stop command button stops the sequence based on the Stop Mode selection The standby or idle state will become active based on the Finish Mode setting Pressing the Stop command button when the sequence is not active latches the stop command until the sequence is active The relevant VXlplug amp play API function is e tat964 stopSequence The Reset command button forces the sequence to the reset state Sequence Step 0 with the Channel Drivers setting unchanged The relevant VXIplug amp play API function is e tat964 resetSequence Master Reset Deskew Arm PG The Master Reset command button forces the sequence to the reset state Sequence Step 0 and also sets the Channel Drivers to Disabled The relevant VXIplug amp play function is e tat964 masterResetSequence The Deskew command button activates the end of cable deskew procedure Only closed channels will be deskewed The relevant VXlplug amp play API function is tat964 deskewDrsChannels The Arm PG command button arms the pulse generator Note The Pulse Gen
319. ign enables the DRM to meet special user and legacy requirements The high speed Data Sequencer provides control over test patterns timing and format Innovative Software Tools Speed Test Development The VXIplug amp play driver and Digital Resource Module Layer support third party test development tools to ease development and integration into popular test environments The optional Microsoft Windows CIIL Emulation Module WCEM for the Astronics Test Systems PAWS Runtime System RTS provides an interface to the DRM from the IEEE standard ATLAS test language for modern test development Application Layer System Interface Software DRS ATPG LASAR Application Resource Interface ARI Migration Probe Digital Functional VXIplu lay Driver Instrument Soft Front Panel Library DFL Debug Tools Ideal for Legacy Replacement and Preserving TPS Investments The DRM is ideal for replacing less reliable obsolete instruments With the innovative software tools the investments in digital technology can be preserved and sustained going forward on a modern platform Legacy TPS performance has been demonstrated on ARGCS RTCASS NGATS ESTS B 1B ARTS and used to replace L300 legacy systems Scalable Design Built in scalability and modular design enable configurations from 24 to 768 channels in 24 or 32 channel increments DRMs and Digital Resource Suites DRSs can operate as independent digital instruments or as
320. iled 15 DSA pattern 1 CH9 CH16 RAM test failed 16 DSA pattern 2 CH17 CH24 RAM test failed 17 DSA pattern 3 CH25 CH32 RAM test failed 18 DSA record RAM test failed 19 DSA probe flag RAM test failed 20 DSB 500 MHz clock test failed 21 DSB frequency synthesizer test failed 22 DSB VXICLK10 test failed 23 DSB pulse generator test failed 24 reserved 25 reserved 26 reserved 27 DSB sequence RAM test failed 28 DSB timing set RAM test failed 29 DSB persistence RAM test failed 30 DSB waveform RAM test failed 31 DSB record index RAM test failed 32 DSB error address RAM test failed 33 DSB pattern 0 CH1 CH8 RAM test failed 34 DSB pattern 1 CH9 CH16 RAM test failed 35 DSB pattern 2 CH17 CH24 RAM test failed 36 DSB pattern 3 CH25 CH32 RAM test failed 37 DSB record RAM test failed 38 DSB probe flag RAM test failed The relevant VXlplug amp play API function is Astronics Test Systems Soft Front Panel Operation 5 157 Model T940 User Manual Publication No 980938 Rev K e tat964 self test Full RAM Test The full RAM test function is accessed from the Instrument gt Full RAM Test menu bar selection COO DSB pattem 1 8 memory Passed DSB pattem 9 16 memory Passed DSB pattem 17 24 memory Passed DSB pattem 25 32 memory Passed DSB record memory Passed DSB probe memory Passed DSB sequence memory Passed DSB timing set memory Passed DSB persistance memory Passed DSB waveform memory Passed DSB record index memory Passed
321. imes and HPM j ends between RL and RH F1 Signal starts above RH crosses the RH three or more times crosses RL once and HGFE k ends below RL D9 L Signal remains below RL 0A Signal starts below RL crosses the RL LG m two or more times and ends below RL AA Signal starts below RL crosses the RL LM n once and ends between RL and RH 22 Signal starts below RL crosses RL and LP RH two or more times and ends below RL FA Signal starts below RL crosses the RL three or more times and ends between RL LGM p and RH A2 Signal starts below RL crosses RL and RH three or more times and ends above LPH q RH F6 Signal starts below RL crosses RL three or more times RH two or more times and LPM r ends between RL and RH F2 LGRE f B 5 Signal starts below RL crosses the RL Soft Front Panel Operation 5 84 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Expect Probe Code Shortcut Description Code three or more times crosses RH once and ends above RH M t Signal remains between RL and RH 00 Signal starts between RL and RH crosses MH the RH once and ends above RH 14 Signal starts between RL and RH crosses ML V the RL once and ends below RL 88 Signal starts between RL and RH crosses the RH two or more times crosses RL MFE w once and ends below RL D8 Signal starts between RL and RH crosses the RL two or more ti
322. in AUX4 B 40 Bi directional General Purpose pin AUX5 B 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX10 B 90 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX10 B 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 93 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX12 B 94 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX12 B 95 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V PBUT B 46 Bi directional Probe Button Input Astronics Test Systems DR3e Driver Receiver Board D 15 Model T940 User Manual Publication No 980938 Rev K Name Pin No Description PMODE B 47 Output Probe Support Output GNDREF B 49 Output Ground Reference output from driver receiver logic MONITOR B 50 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time BCLK B 96 Output Reserved EXTFORCEB 98 Input Exter
323. ing or logging of Errors in the Error Address Memory EAM Single Stepping and Record Modes will also be covered since they are interrelated This section discusses these topics using the Soft Front Panel SFP but VXIplug amp play API calls and Application Resource Interface ARI references are provided Topics to be covered in this section include e Coupling of signals between Sequencers for Linking and DRS Formation Step Record Mode e Record Type e Counting and Logging Errors e Pipelining and non Pipelining e Jumping or Halting on Pass Fail conditions e Understanding Pass Fail e Additional Pipeline Information e Valid Pass and Capture Fault e Additional Halt Information e Calibration Astronics Test Systems Advanced Topics 8 1 Model T940 User Manual Publication No 980938 Rev K Performance considerations Pipelined Depth Calculation Record Offset Limitations Two better ways to do a Wait Coupling Signals between Sequencers for Linking and DRS Formation First let s define some terms that will be used in the discussion Independent A single Sequencer A or B operating independently of all others Linked In a single DRM Sequencer B is solely linked to Sequencer A and to no other Sequencers DRS Two or more DRMs are needed to create a DRS The Primary A Sequencer is the Master Sequencer which will typically have all of the other Sequencers A amp B coupled to it But one or more may be excluded Th
324. internal TOCLK this control specifies the system clock period The period is programmed in master clock edges rising and falling i e 1 2 the master clock period For example if the master clock is set to 500 MHz then a setting of 20 would result in a system clock period of 20 ns 20 1 2 2 ns 20 ns With a master clock of 100 MHz the system clock period would be 100ns 20 1 2 10 ns 100 ns The valid values for TOCLK are from 20 to 65550 The relevant VXlplug amp play API function is e tat964 setSequenceClock Clocks per Pattern This numeric control defines the Clocks per Pattern CPP for each sequence step The CPP value determines the number of System Clocks that will be generated for each Pattern Clock When CPP 1 then Pattern Clock is equal to System Clock When CPP 2 then Pattern Clock is two times the System Clock Soft Front Panel Operation 5 100 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Example 1 CPP 1 System Clock LI LI Pattem Clock Period Sytem Clock Example 2 CPP 2 System Clock LI LI Pattem Clock E Period 2 x Sytem Clock Example 3 3 System Clock Pattem Clock Period 3x Sytem Clock The valid values for CPP are from 1 to 256 The relevant VXIplug amp play API function is e tat964 setSequenceClock CPP Phase and Window Triggering Two clo
325. ion Control Reset to Standby Sequence CPU command Run Idle Sequence CPU or external command Run Sequence CPU or external command Stop Sequence CPU or external command Single step by Pattern or Sequence Step see Halt function Burst Timeout Timer A watchdog timer that limits the maximum execution time of a dynamic pattern set independently of pauses halts and external clocks On timeout sets all outputs to tri state Can be disabled Range 40 ns to 86 seconds Resolution 20 ns Handshaking Master Clock MCLK See Pause function Internal Oscillator 500 MHz Accuracy 50 ppm Internal Synthesizer 40 KHz to 500 MHz Internal Reference 20 MHz or VXICLK10 Internal Synthesizer 4 digits typical Resolution 20 MHz Reference Accuracy 50 ppm External Front Panel Reference Range 5 MHz to 80 MHz Slow Mode Astronics Test Systems Frequency Synthesizer allows timing to be reduced by a factor of 1 to 210000 Specifications 7 7 Model T940 User Manual Counter Timer Characteristics Measurement Modes Input Source Publication No 980938 Rev K Frequency Period Time Interval Totalize Timed Totalize Positive Pulse Negative Pulse CH1 32 Uses Good 1 AUX1 12 Frequency Synthesizer VXICLK10 250 MHz Pulse Generator Input Sense Rising Pos or Falling Neg Frequency Period Input 1 Measurement Source Frequency Period 0 25
326. ion relays and ECL bipolar differential mode AUX 5 8 Four LVTTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 VBB ECL input threshold 1 3V AUX 9 12 Four negative differential signals used to input or output test signals See Configuring the AUX Channels in Astronics Test Systems DR2 Driver Receiver Board C 3 Model T940 User Manual Publication No 980938 Rev K Chapter 5 AUX 9 12 Four bipolar positive differential signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 DR2 Driver amp Receiver Figure C 3 illustrates the configuration and control of the DR2 Driver amp Receiver LVDS FRONT PANEL Figure C 3 DR2 Driver amp Receiver Block Diagram Signal Descriptions DATA Channel and auxiliary data output signals from the Data Sequencer to the LVDS output drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the LVDS output drivers RH Response High input signals to the Data Sequencer from the LVDS input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the LVDS input receivers 0 good 0 1 good 1 AUX 1 4 Four positive differential LVDS signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 AUX 1 4 Four negative differential LVDS signals used to input or output test signals Se
327. irections shown e Error e Pass Valid e DRM Sync e Driver Disable e Halted e Static Pulse These six are all of the signals that are potentially useful Those that are not needed may be excluded For example Static Pulse may be excluded if channels will not be used in Static Mode anywhere in the DRS The panel automatically handles the direction and sense of these signals thus the Direction and Invert fields are dimmed Note Sequence Reset and Master Reset are automatically handled in the S W i e a Sequence or Master Reset on either Sequencer will reset the other when they are linked Astronics Test Systems Advanced Topics 8 3 Model T940 User Manual Publication No 980938 Rev K Error Pass Valid DRM Sync Driver Disable Figure 8 2 Configure Module Panel For DRS operation there are additional signals that might need to be setup depending on how the DRS will be operated From the same Configure Module panel select VXI Triggers for the Data Sequencer A and or B depending on whether that Sequencer is included in the DRS configuration or not The relevant VXI plug amp play API and ARI functions API tat964 setTtlTriggers tat964_setEclTriggers e ARI AssignPatTimeGroup AssignPtgTrigger Additional signals required to be coupled along the backplane to form the DRS include e Sequence Reset e Master Reset Advanced Topics 8 4 Astronics Test Systems Publication No 9
328. istics Digital I O Type Variable Voltage Astronics Test Systems UR14 Driver Receiver Board 1 21 Model T940 User Manual Publication No 980938 Rev K Description Characteristics AUX Channels 6 SE Driver Receivers per VXI slot Per channel relay isolation 2 are dedicated to the External Probe when used Output Voltage Ranges Selectable Sequencer Output Voltage Swing 15 V to 17 V VMO 7 V to 24 V VM1 500 mV to 24 V Output Resolution 5mV Output Accuracy 50mV 1 of PV Slow Default Medium slew settings t 75mV 196 of PV Fast slew setting Output Drive Current Output Impedance Selectable Channel 65 mA typical Source Sink 85 mA Max Source Sink 12 0 500 40 Slew Rate Selectable Channel or custom 0 25 V ns 0 7 V ns 1 0 V ns or 1 3 V ns typical Input Threshold Ranges 14 75 V to 14 V VMO 6 75 V to 21 V VM1 Input Threshold Resolution 5mV Input Threshold Accuracy Current Source Sink Programmable Channel 50mV 1 of PV Range 0 4 mA to 20 mA usable to 24 mA Resolution lt 10 pA Accuracy 3 of PV 1200 Commutating Voltage Vcom CMH and CML Range same as driver Resolution 5 mV Accuracy 50mV 196 of PV Over Current Alarm IAH and IAL Resistive Loads Selectable Channel Range 800 mA Resolution 30 uA Accuracy 50mA 1 of PV 140
329. k disables the comparison The result of all four channel test registers can be routed to the VXI TTL trigger Astronics Test Systems Soft Front Panel Operation 5 97 Model T940 User Manual Publication No 980938 Rev K Expect Mask bus In addition channel test 1 result can also be routed to any of the sequence triggers Figure 5 55 Sequencer Channel Test Panel This allows the user to enter the expect value for the channel test signal Bit O of the expect value maps to the lowest channel of this sequencer and Bit 31 maps to the highest channel and this is the case for both A and B sequencers A one represents a valid high test and a zero represents a valid low test The relevant VXlIplug amp play API function is e tat964 setSequenceChannelTest This allows the user to enter the mask value for the channel test signal Bit of the mask value maps to the lowest channel of this sequencer and Bit 31 maps to the highest channel and this is the case for both A and B sequencers A one disables the comparison to the expect value and a zero enables the comparison The relevant VXlplug amp play API function is e tat964 setSequenceChannelTest The T940 VXI Backplane Trigger Bus section of Chapter 8 describes how to use Channel Tests to perform a logical OR and logical AND of two or more channels Soft Front Panel Operation 5 98 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Editing Sequence Steps
330. ke the final Jump decision In particular Acumulative Fail occurs if even one qualified pattern in the Seq Step has an Error e Acumulative Pass can only occur if none of the qualified patterns in the Seq Step has an Error And if the Pass Valid Mode is enabled none of the qualified patterns in the Seq Step can have a Capture Fault for Pass to occur Pipelined handling of Pass Fail with default settings Since the Error signal and Pass Valid if used are delayed by the pipeline these signals will not be aligned with the Jump Test made at the end of an individual Sequence Step or at the end of a Primary Sequence Thus to make a correct Jumping Decision e The last N patterns before the end of the Sequence Step or primary sequence will not be included in the accumulated Pass Fail decision e The last N patterns of the previous Sequence Step will be included If these are not to be included in the accumulated Pass Fail Jumping decision then they need to not produce any Errors The easiest way to not produce any Errors or Indeterminates is to employ a Qualified Pass Fail basis and disable CONDEN for these N Patterns Using this method Errors can still be Recorded Counted or Logged into the EAM if desired Note 1 A Capture Fault will generate an Error This is discussed further in Advanced Topics 8 20 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Section 9 below Note 2 Standby or I
331. l The relevant VXlplug amp play API function is e tat964 querySequencerCondition These LEDs indicate if the state of the associated signal went true The relevant VXlplug amp play API function is e tat964 querySequencerEvent This command button resets the event LEDs Sequencer Data Panel The sequence status display is accessed from the Execute gt DSx View gt Sequencer Data menu bar selection Where x is the sequencer you wish to query Soft Front Panel Operation 5 142 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Bi VXIO 2 1NSTR Sequencer Data DSA 5 Counter Active AAA 1111 diii e Figure 5 77 Sequencer Data DSA Panel Counter Active This set of LEDs indicates whether the loop counter is active or not An active counter will have its LED illuminated The relevant VXIplug amp play function is e tat964 querySequencerCounterStatus Record Index Count This indicator displays the number of valid entries in the record index memory The relevant VXlplug amp play API function is e tat964 querySequencerRecordIndex Sync Error Step This indicator displays the step number that was active when the DRS sync error occurred The relevant VXlplug amp play API function is e tat964 querySequencerSyncError Sync Error Pattern Address This indicator displays the pattern address that was active when the DRS sync
332. l LVDS Positive High speed channels CH64 CH33 to Various Bi directional LVDS Negative High speed channels CH64 SIG_GND Various Signal Ground reference AUX1 B 34 Bi directional General Purpose LVDS Positive I O pin AUX1 B 35 Bi directional General Purpose LVDS Negative pin AUX2 B 36 Bi directional General Purpose LVDS Positive pin AUX2 B 37 Bi directional General Purpose LVDS Negative I O pin AUX3 B 38 Bi directional General Purpose LVDS Positive I O pin AUX3 B 39 Bi directional General Purpose LVDS Negative I O pin AUX4 B 40 Bi directional General Purpose LVDS Positive I O pin AUX4 B 41 Bi directional General Purpose LVDS Negative I O pin AUX5 B 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 B 90 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 B 91 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX11 B 93 Bi directional General Purpose ECL I O 51 1 Ohm to 2 V AUX12 B 94 Bi directional Gen
333. l DEBUG DEBUG Debug Operation OFF Debug off Default ON Debug on Mode Selection Switch position 3 of SW2 is used to select the VXI bus protocol mode Table 2 5 Mode Selection SW2 Position 3 Signal MODE Astronics Test Systems Installation 2 5 Model T940 User Manual Publication No 980938 Rev K MODE Message Based Enabled OFF VXI Message Based ON VXI Register Based Default Bus Request Selection The VXI backplane supports 4 levels of bus request Switch positions 2 and 1 of SW2 are used to select the VXI bus request level Table 2 6 Bus Request Selection SW2 Position 2 1 Signal BRO BR1 BR1 BRO Bus Request Level OFF OFF 0 OFF ON 1 ON OFF 2 ON ON 3 Default DRS Inter Module Mode Control Note This is used when setting up a Digital Resource Suite DRS with two or more DRMs The T940 uses a jumper bar PN 408382 to define whether the DRM is the Primary Secondary or Terminator A T940 DRS is configured right to left The Primary must be installed to the right of the Terminator Secondary DRMs if any are placed between the Primary and Terminator The Inter Module Control section in Chapter 4 Functional Description describes this feature in detail The Inter Module Mode section in Chapter 5 Soft Front Panel Operation discusses the configuration of the DRMs Three settings are available
334. l board to the Driver Receiver board MF SIG Multi Function signal output to the PWR connector Firmware amp NV Data The Control Logic firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions CONTROL Signals used to program firmware and NV DATA DR7 Characteristics Table F 1 DR7 Characteristics Description Characteristics Digital Type RS 422 485 SN75ALS176 Channels 32 differential per Driver Receiver board Output Voltage VoL 3 0 V max Differential Input Voltage Vou 2 0 V min 200 mV min 6 V max Hysteresis 60 mV Output Drive Current typical Source Sink 60 mA Impedance 100 in parallel with 20K pull up pull down bias resistors to establish a True level if unconnected Output Skew Channel to Channel lt 3 ns drive and compare Input Skew Channel to Channel RS 422 485 4 Differential with 20K bias Auxiliary Channels per Driver Receiver board AUX I O is bi directional Astronics Test Systems lt 3 ns drive and compare resistors TTL 4 Single ended ECL 4 Single ended or Differential DR7 Driver Receiver Board F 5 Model T940 User Manual Publication No 980938 Rev K Characteristics Per channel relay isolation on ECL I
335. l channels e Voltage range 15 V to 24 V with an output swing of up to 24 V Relay Isolation on all and AUX channels e Full drive current on all channels simultaneously e Programmable current load with dual commutating voltages e Selectable resistive input load 8 choices to a programmed voltage e Selectable output slew rate 0 25 V ns to 1 3 V ns e 12 50 Ohm selectable output impedance e Over current detection Introduction 1 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual e Over voltage detection protection e Auxiliary channels Four variable voltage Four LVTTL Four ECL single ended or differential DR4 Driver Receiver The features e Channels 48 single ended variable voltage or 24 differential channels e Voltage range 31 V to 31 V with an output swing of up to 31 V Relay Isolation on all channel I O e Selectable current drive e 50 50 selectable output impedance e Over current detection e Temperature monitoring e 16 TTL auxiliary channels DR7 Driver Receiver The DR7 features Channels 32 differential RS 422 485 e Auxiliary channels Four RS 422 485 FourLVTTL Four ECL single ended or differential DR8 Driver Receiver The DR8 features e Channels 32 single ended TTL Relay Isolation on all and AUX channels e Selectable resistive input load to VCC 5 0 V ground or both e Direct or 100 ohm selectable output impedance e Auxiliary ch
336. l error signal pulse width Note In all cases the data period must be greater than the error pulse width 4 ns If a TTL trigger line is used to transmit the error pulse the data period will need to be approximately 2 3 times longer than the error pulse The selections for this pull down control are given along with the recommended error pulse width assuming a 500 MHz master clock Table 5 19 Error Pulse Width Settings Setting Description Typical Usage 2 8 MCLK The error pulse will be from 2 to 3 MCLK Recommended for un linked sequencers periods 3 4 MCLK The error pulse will be from 3 to 4 MCLK Recommended for a DRS of size 2 4 periods DRMs 4 5 MCLK The error pulse will be from 4 to 5 MCLK Recommended for a DRS of size 5 8 periods DRMs 5 6 MCLK The error pulse will be from 5 to 6 MCLK Recommended for a DRS of size 9 12 periods DRMs The relevant VXlplug amp play API function is e tat964_setErrorPulseWidth e tat964 calibrateDrsTimingBus Record Mode This pull down control programs the sequencer record mode The sequencer record mode selects what the sequencer does to the record memory when the sequence Step Record Mode is set to either None or Record Count see the section on Step Record Mode later in this chapter Note If Step Record Mode is set to either Record Error or Record Response then the Record Mode setting will be ignored The selections for this pull down control are
337. l have less delay but will still require a few Master Clocks which may vary depending on the placement of the Phase edge to be refined e Pause Edge Test 1 2 Clear options static selection Astronics Test Systems Advanced Topics 8 31 Model T940 User Manual Publication No 980938 Rev K o Clear both Pause Edge test flip flops just before the beginning of the Sequence option 1 o Clear both Pause Edge test flip flops just before the beginning of the Sequence and just before the beginning of each subsequent Sequence Step option 2 o Clear both Pause Edge test flip flops just before the beginning of the Sequence but only clear the selected Pause Edge Test flip flops with a CPU Resume Mated External Resume or the timeout of Pattern Delay Timer option 3 Phase Edge Test 1 4 Clear operation o Clear all 4 Phase Edge Test flip flop pairs just before the beginning of each pattern with each CPU Resume but only clear the selected Phase Edge Test flip flop pair with a Mated External Phase Resume Pause Test 1 2 Resume options o CPU Resume o Mated External Resume there s one for each Pause Test source o Pattern Delay Timer timeout Phase Test 1 4 Resume options o CPU Resume o Mated External Resume there s one for each Phase Test source o Pattern Delay Timer timeout Pause Examples A Handshake example Pause on Phase 4 FE right after the output data is formatted and before the input data is to be captured of Sequenc
338. l time Pin Electronics Overvoltage Detection circuitry with levels that indicate an Overvoltage condition OVERVOLTAGE ALARMS output from the monitoring circuitry that goes to the UR14 LOGIC VOLTAGE ALARMS Real time over voltage which monitors the PIN ELECTRONICS Driver and Receivers to protect the UR14 board DUT_GND This signal comes from the UUT and can be used to offset the Pin Driver reference levels up to 3 Comparators on the UR14 monitor excursions of DUT_GND beyond 390 mV with respect to signal ground yields to signal a GND FAULT to the UR14 LOGIC The levels of DUT GND can also be measured by the ADC MONITOR This is an analog output signal from the Pin Electronics devices which can be used to monitor DAC levels even the Channel I O levels DACVMON This signal comes from the DAC and allows monitoring of the INREF 1 4 ADC_IN This input comes from the UR14 front panel and is used to measure DC levels from 10 to 20 V PIN DRIVER TEMP Real Time Pin Driver temperature monitoring diode connections Programmable temperature thresholds allow the UR14 LOGIC to respond to OVERTEMP alarms to shut off the Pin Drivers to protect them from over temperature damage UR14 Driver Receiver Board 1 14 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual TEMP ALARMS Real time temperature monitors for the Pin Electronics Driver and Receivers to protect the UR14 board CBUS An internal Control Bus c
339. le Start Single Step Period 10 ns Resolution Min 20 ns Max 42 94967297 s 20 ns Resolution Min 40 ns Max 85 899345960 s Delay 10 ns Resolution Min 20ns Max 42 94967297 s 20 ns Resolution Min 20ns Max 85 899345960 s Width 10 ns Resolution Min Ons Max 42 94967297 s 20 ns Resolution Min Ons Max 85 899345960 s Calibration DAC Basic Factory stored in EEPROM D R channel deskew Factory stored in EEPROM Astronics Test Systems Specifications 7 9 Model T940 User Manual Publication No 980938 Rev K ADC Monitor Field upgradable stored in EEPROM DVH DVL Field upgradable stored in EEPROM CVH CVL Field upgradable stored in EEPROM Voom High Veom Low Field upgradable stored in EEPROM lsource lsink Field upgradable stored in EEPROM IAL IAH Field upgradable stored in EEPROM Inter module timing deskew Static End of cable deskew Static Pipelined operation for 0 21 F W and later Note 1 DR3e DR9 UR14 and DR4 only Note 2 DR3e DR9 and UR14 only Front Panel I O The DB is isolated from the front panel via the Driver Receiver board s Refer to the appropriate appendix for the front panel specifications for the installed Driver Receiver board VXI Interface Interfaces Supported Register based operation Data Transfers Address A16 and A24 A32 Data D16 D32 VXI Feature Usage TTLTRGO 7 ECLTRGO 1 Triggering
340. lew Rate Rate of change of an output transition typically in V ns Terminator Used to describe the DRM in the leftmost position of the DRS chain One or both sequencers can be coupled to the DRS chain Timing Set A timing set is the structure that is created that defines the stimulus response timing TO CLK System Clock TPS Test Program Set TTL TRG VXI TTL Trigger UR14 Utility Resource Board Probe and 32 channel open collector UUT Unit Under Test V Positive supply voltage provided by the Power Converter which is used to power the Pin Electronics devices In addition external power may be applied to V via an optional front panel power connector V Negative supply voltage provided by the Power Converter which is used to power the Pin Electronics devices In addition external power may be applied to V via an optional front panel power connector Valid Pass A Valid Pass is one where no channel errors were detected but there must be at least one valid pattern expect code for each pattern in the sequence step This is discussed in more detail in the Jumping Halting Counting and Logging Errors section of Chapter 8 VADDR Address Bus 32 bit backplane address bus VBB ECL Input Threshold 1 3V VCC Positive supply voltage for the TTL or LVTTL drivers receivers VCTRL VXI Control Bus The backplane control bus VDATA VXI Data Bus The 32 bit backplane data bus VIH Voltage Input High Level min VIL Voltage
341. ll DRMs using the VISA library Once all the DRMs have been identified a selector panel will display only if more than one DRM is found Selecting one of the modules opens a VXI session with that module and then displays the main panel Astronics Test Systems Soft Front Panel Operation 5 9 Model T940 User Manual Publication No 980938 Rev K VXI Slot 4 0 4 1 5 Figure 5 14 Opening VXI DRM Session Relevant VXlplug amp play API functions include tat964 init tat964_autoConnectToAll tat964_autoConnectToFirst tat964_autoConnectToLA tat964_autoConnectToSlot Configuring the Global Hardware Parameters Configuring the global hardware parameters is done from three panels Configure Module Configure Data Sequencer A and Configure Data Sequencer B Configure Module Panel Access this panel from the menu bar Config gt Module The Configure Module panel is used to program the inter module mode power converter mode state Linked Trigger bus routing signal delays VXI TRG routing driver receiver properties and record settings Soft Front Panel Operation 5 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Independent Not Linked v 12042 v T Data Sequencer A Data Sequencer B Delay Signal Delay Delay Signal Phase 1 26 Phase 1 vi Error Pulse Width Record Eror Pulse Width Record Mode Disabled mi 2 3 MCLK Disabled Sl Figure 5 15 Configure
342. lling Edge Glitch Middle Signal starts above RH crosses RH once crosses HL two or more times and ends between RL and RH Open F1 High Pulse Middle Signal starts above RH crosses RH three or more times RL two or more times and ends between RL and RH Close oe F5 High Pulse Signal starts above RH crosses RH and RL two or more times and ends above RH Close Astronics Test Systems Publication No 980938 Rev K Open F6 Close Open F8 Close Low Pulse High Signal starts Middle Pulse Low Signal below RL crosses RL and RH starts between RL and RH three or more times and ends crosses RL three or more times above RH RH two or more times and ends below RL Open F A Close Low Pulse Signal starts below RL crosses RL and RH two or more times and ends below RL The relevant VXI plug amp play API function is e tat964 queryProbeData Status Indicator Panels Model T940 User Manual Open F9 Close High Pulse Low Signal starts above RH crosses RL and RH three or more times and ends below RL The status indicator panels allow the operator to view the available status results to determine if the previous execution sequence is valid The following panels are available Sequencer Events e Sequencer Data Driver Receiver Events Driver Receiver Data e VXI Trigger Readback e Power Query e Power Co
343. lso set a fault flag Proceed to the next Seq Step e f LC 0 proceed to the next Seq Step e If LC gt 0 and CA 0 and NOT IN SUB load the designated Loop Counter set CA 1 set the IN SUB flag save the Return Seq addr and jump to JSA e If CA 1 and NOT LCD decrement the loop counter and jump to JSA e f CA 1 and LCD reset CA if UCO 0 and proceed to the next Seq Step e Otherwise proceed to the next Seq Step e f IN SUB jump to the Return Seq and clear the IN SUB flag e Otherwise proceed to the next Seq Step also set a fault flag 10 Jump to JSA also set fault flag e f IN SUB jump to the Return Seq and clear the IN SUB flag Otherwise proceed to the next Seq Step also set a fault flag e If LC 0 and IN SUB jump to the Return Seq and clear the IN SUB flag e f LC gt 0 and CA 0 load the designated Loop Counter set 1 and jump to JSA Advanced Topics 8 38 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Jump LSTSEQ RTN SUBRT CLOOP Action Comments e If CA 1 and NOT LCD decrement the loop counter and jump to JSA e lf CA 1 and LCD reset CA if UCO 0 also if IN SUB jump to the Return Seq and clear the IN SUB flag Otherwise proceed to the next Seq Step also set a fault flag 13 0 0 1 1 0 e f IN SUB jump to the Return Seq and clear the IN SUB flag e Ot
344. lt flag e If LC 0 and IN SUB jump to the Return Seq and clear the IN SUB flag e f LC gt 0 and 0 load the designated Loop Counter set 1 and jump to JSA e If CA 1 and NOT LCD decrement the loop counter and jump to JSA f CA 1 and LCD reset CA if UCO 0 also if IN SUB jump to the Return Seq and clear the IN SUB flag Otherwise the Seq loops or finishes also set a fault flag 29 e f IN SUB jump to the Return Seq and clear the IN SUB flag Otherwise the Seq loops or finishes also set a fault flag 30 f NOT IN SUB set the IN SUB flag set the LAST flag and jump to JSA e f IN SUB jump to the Return Seq and clear the IN SUB flag also set a fault flag 31 e f IN SUB jump to the Return Seq and clear the IN SUB flag Otherwise the Seq loops or finishes also set a fault flag 32 e If LC 0 and IN SUB jump to the Return Seq and clear the IN SUB flag Astronics Test Systems Advanced Topics 8 41 Model T940 User Manual Publication No 980938 Rev K Jump LSTSEQ RTN SUBRT CLOOP Action Comments e f LC gt 0 and CA 0 and NOT IN SUB load the designated Loop Counter set CA 1 set the IN SUB flag set the LAST flag and jump to JSA e If CA 1 and NOT LCD decrement the loop counter and jump to JSA e If CA 1 and LCD reset CA if UCO 0 also if IN SUB jump to the Re
345. mA for lt 10ms Auto Shutdown e DC level within 1 V of V or V e Abys spike exceeding V or V 120 pF Channel Crosstalk 250 Voltage Monitoring per Driver Receiver board V V and Front Panel DUT Hybrid Connection per Driver Receiver board Auxiliary Channels per Driver Receiver board Connects Front Panel pin to any channel via the Pin Driver electronics User must disable the drive enabled to the channel 40 series impedance 3 MHz bandwidth Programmable Level 4 LVTTL 4 ECL 4 Single Ended or Differential AUX I O is bi directional Relay isolation This range is limited by the V and V levels 1 700 mV at the fastest slew rate Min Max Levels The I O level minimum and maximum values are determined by the V an V bias voltage levels The following table lists the min and max levels based on the V and V level Table D 2 DR3e Min Max Levels Front Panel Level Min Max Units DVH V 5 V 3 V DVL V 4 V 7 V CVH V 2 V 7 V CVL V 2 V 7 V Vcom High CMH V 2 V 7 V Vcom Low CML V 2 V 7 V Astronics Test Systems DR3e Driver Receiver Board D 9 Model T940 User Manual Publication No 980938 Rev K The following table lists the min and max levels based on the power converter type 1 or 3 setting Table D 3 DR3e I O Min Max Levels Power Converter Type 1 or
346. master clocks x 30 ns n is composed of a 5 master clock intrinsic delay plus the period of the standby pattern 10 master clocks in this case A longer Standby period will lengthen this maximum If starting from Idle the setup time is with respect to the last TOCLK of the Idle step Add to x Linked or VXI Local Bus adjustments External Stop Setup Time to TOCLK In For a 10 master clock pattern period AUX LVTTL to TOCLK 70 ns max 500 MHz master clock AUX LVTTL to TOCLK 222 ns max 100 MHz master clock X 2n 70 ns x 10n 222 ns Thus n2 19 x 2 32 ns of fixed delay n is composed of a 9 master clock intrinsic delay plus the period of the pattern one is currently trying to stop in A longer pattern period will lengthen this maximum Add to x Linked or VXI Local Bus adjustments A Channel Input to TRG Bus for a channel test DR1 Channel In to TTLTRG Bus TBD DR2 Channel In to TTLTRG Bus TBD DR3 Channel In to TTLTRG Bus 29 ns SEQ ACT IDLE ACT Sync Pulse Seq Flag to TRG Bus AUX LVTTL to TTLTRG Bus 1 ns DRM Timing Characteristics J 4 Astronics Test Systems
347. mes crosses RH MRE once and ends above RH B4 Signal starts between RL and RH crosses the RH three or more times and ends MGH y above RH 54 Signal starts between RL and RH crosses the RL three or more times and ends MGL 2 below RL A8 Signal starts between RL and RH crosses the RH two or more times and ends MHG 0 between RL and RH 50 Signal starts between RL and RH crosses the RL two or more times and ends MLG 1 between RL and RH 0 Signal starts between RL and RH crosses RL two or more times RH three or more MPH 2 times and ends above RH F4 Signal starts between RL and RH crosses RL three or more times RH two or more MPL 3 times and ends below RL F8 Signal starts between RL and RH crosses RH and RL two or more times and ends MPM 4 between RL and RH FO Signal starts below RL and crosses the RE 5 RL and RH once 36 Signal starts below RL crosses RL once crosses RH three or more times and ends REG 6 above RH 76 Signal starts below RL crosses RL once crosses RH two or more times and ends REGM 7 between RL and RH 72 Signal starts below RL crosses RL once crosses RH two or more times and ends X 78 between RL and RH NA The rows labeled CH1 through CHn contain the pattern codes for the specified channels There are fourteen pattern codes The following table lists how each Astronics Test Systems Soft Front Panel Operation 5 85 Model T940 User Man
348. mmand button to single step pause Pause the primary No control to manually pause the sequence primary sequence resume Pause resume While in PAUSE state e Depress Resume command button to resume Execute Panel Indicators There are eleven indicators that display the current sequencer status These indicators are updated every 50 ms Idle LED When green indicates that the sequencer is in the IDLE state The relevant VXlplug amp play function is Active LED tat964_querySequencerStatus When green indicates that the sequencer is in the ACTIVE state Astronics Test Systems Soft Front Panel Operation 5 115 Model T940 User Manual Publication No 980938 Rev K Halt LED Pause LED The relevant VXlplug amp play API function is e tat964 querySequencerStatus When green indicates that the halt mode has been armed When red indicates that the sequencer is in the HALT state The relevant VXlplug amp play API function is e tat964 querySequencerStatus When green indicates that the sequencer is in the PAUSE state The relevant VXlplug amp play API function is e tat964 querySequencerStatus Burst Error LED Errors When red indicates that one or more burst errors have occurred in the previous sequence run The relevant VXlplug amp play API function is e tat964 queryErrorFlags This numeric indicator displays the number of pattern errors from the previous sequence burst The relevant VXlplu
349. mp trigger signal is high Note Any CONDEN enabled FAIL during the Sequence Step will prevent a PASS See the Jumping Halting Counting and Logging Errors section of Chapter 8 for a detailed explanation of Jumping based on Errors Also see the Jumping on a Step or Burst Error section of Chapter 8 The relevant VXlIplug amp play API function is e tat964 setSequenceJump Loop Count This numeric control programs the Loop Count number Jumps can be qualified by a loop counter The loop count can be set from 0 no qualification to 65536 A count qualified jump only allows the jump to occur a maximum of count times This allows single or multiple steps to be looped The relevant VXlplug amp play API function is e tat964 setSequenceJump Soft Front Panel Operation 5 104 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Loop Counter This numeric control programs the Loop Counter number Jumps can be qualified by a loop counter Sixteen loop counters are available Nested loops are supported including up to all 16 counters The relevant VXIplug amp play function is e tat964 setSequenceJump Vector Jump This control allows the user to specify the Vector Jump flag This flag indicates whether the vector jump mode is enabled true or disabled false If the vector jump mode is enabled then the sequence step number to jump to is specified in the vector jump table which is addressed by the
350. ms Driver Receiver Board H 15 Model T940 User Manual Publication No 980938 Rev K DRB Resources Table H 9 DRB Resources Name Pin No Description CH 33 CH 48 Various Bi directional High speed channels ACH 33 ACH 48 Various Analog test connection DUTGNDB J1B 34 Input DUT UUT ground reference All of the Pin Electronics devices have a UUT ground reference input that can be selected to be this signal or signal ground SIG GND Various Signal Ground reference Refer to Figure H 6 and Tables H 10 through H 12 Table H 10 J3B Connector Pinout by Pin Number Connector Connector Sionas Rore Pin Pin AorB 1 2 CH33 3 4 B 5 6 cm35 B 7 8 CH36 B 9 10 CH37 11 2 CH38 13 4 CH39 15 16 B 17 8 CH4 19 20 21 22 CH 43 B 23 24 4 B 25 26 CHM5 27 28 6 B 29 30 CH47 31 32 8 33 NC Connector Connector Resource Pin Pin Aor B GND CH 49 B DR9 Driver Receiver Board H 16 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual CH 51 CH 51 Connector Resource Pin 2 24 4 CH 23 6 CH 22 8 CH 21 10 12 14 16 18 CH 16 20 CH 15 22 CH 14 24 CH 13 26 CH 12 28 CH 11 30 CH 10 32 CH 09 34 DUTGND A amp B Astronics Test Systems DR9 Driver Receiver Board H 17 M
351. ms the vector bit source The selections for this pull down control are Astronics Test Systems Soft Front Panel Operation 5 95 Model T940 User Manual Publication No 980938 Rev K Table 5 77 Vector Bit Source Settings Setting Description None No trigger source selected AUX1 AUX12 Trigger source set to front panel signal CHT1 Trigger source set to channel test 1 1 Trigger source set to VXI ECL trigger TTLTRGO 7 Trigger source set to VXI TTL trigger LTBO 7 Trigger source set to LTB trigger The relevant VXlplug amp play API function is e tat964_setVectorJumpSignal Input Mode This pull down control programs the trigger input mode for vector jumps The selections for this pull down control are Table 5 78 Vector Bit Input Mode Settings Setting Description Normal Do not modify input signal before testing Inverted Invert input signal before testing The relevant VXI plug amp play API function is e tat964_setVectorJumpSignal Set Vector Table This command button displays the Edit Vector Table panel so the vector table settings can be programmed for the selected sequencer The vector table is indexed by the four vector signals VAO LSB to VA3 MSB Each vector table entry supplies the jump address as well as the timing set indexed timing mode only The vector table signals are only used if the vector jump bit is set true in a sequence step Configuring
352. n be from 0 to 262140 and must be a multiple of four The relevant VXlplug amp play API functions are e tat964 queryPatternSet e tat964 queryPatternSetList Append This control allows the user to append more patterns to the selected pattern set Soft Front Panel Operation 5 78 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Assign Figure 5 42 Append Data Sequencer Pattern Sets Panel Enter the Number of Patterns to append and press the Apply command button Append pattern memory will be initialized to Pattern Code R which repeats the previous code The driver allows pattern set overlaps when appending patterns If you don t want pattern sets to overlap make sure there s enough space for the appended patterns This can be facilitated by assigning the pattern offset initially see Assign function next Press the Close command button to exit the panel without any changes The relevant VXIplug amp play API function is e tat964 appendPattern This control allows the user to assign a new size and or offset to the selected pattern Astronics Test Systems Soft Front Panel Operation 5 79 Model T940 User Manual Publication No 980938 Rev K Figure 5 43 Assign Data Sequencer Pattern Sets Panel Enter the new Size and or Offset and press the Apply command button Assigned pattern memory will not be initialized Press the Close command button to exit the panel without any changes Th
353. nal Force routed to all of the Pin Electronics devices Table D 9 DR3e Pinout by Pin Number DRB DR3e Driver Receiver Board D 16 Pin No Signal Pin No Signal 1 SIG GND 51 SIG GND 2 CH33 52 CH49 3 SIG_GND 53 SIG_GND 4 CH34 54 CH50 5 SIG_GND 55 SIG_GND 6 CH35 56 CH51 7 SIG_GND 57 SIG GND 8 CH36 58 CH52 9 SIG GND 59 SIG GND 10 CH37 60 CH53 11 SIG_GND 61 SIG_GND 12 CH38 62 CH54 13 SIG_GND 63 SIG_GND 14 CH39 64 CH55 15 SIG_GND 65 SIG_GND 16 CH40 66 CH56 17 SIG_GND 67 SIG_GND 18 CH41 68 CH57 19 SIG_GND 69 SIG_GND 20 CH42 70 CH58 21 SIG_GND 71 SIG_GND 22 CH43 72 CH59 23 SIG_GND 73 SIG_GND 24 CH44 74 CH60 25 SIG_GND 75 SIG_GND 26 CH45 76 CH61 27 SIG_GND 77 SIG GND 28 46 78 62 29 SIG GND 79 SIG GND 30 CH47 80 CH63 31 SIG_GND 81 SIG_GND Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pin No Signal Pin No Signal 32 CH48 82 CH64 33 SIG_GND 83 SIG_GND 34 AUX1 B 84 AUX7 B 35 SIG_GND 85 SIG_GND 36 AUX2 B 86 AUX8 B 37 SIG_GND 87 SIG_GND 38 AUX3 B 88 AUX9 B 39 SIG_GND 89 AUX9 B 40 AUX4 B 90 AUX10 B 41 SIG GND 91 AUX10 B 42 AUX5 B 92 AUX11 B 43 SIG GND 93 AUX11 B 44 AUX6 B 94 AUX12 B 45 SIG GN
354. nals between DSA and DSB Astronics Test Systems Soft Front Panel Operation 5 13 Model T940 User Manual Publication No 980938 Rev K VXIO 2 1NSTR Configure Linked Trig n Sm Invert Direction LTBO None LTB1 None LTB2 None LTB3 None LTB4 LTB5 LTB6 O 0O Figure 5 16 Configure Linked Trigger Bus Panel LTBn Signal This pull down control programs the signal source for the specified LTB trigger The selections for this pull down control are Table 5 10 LTB Signal Pull Down Settings Setting Description None Disables the TTLTRG driver AUX1 AUX12 Selects the specified AUX input signal from the front panel Halted Used for linked halt operation between DSA and DSB Static Pulse Used for static operation between DSA and DSB Pulse Generator Selects the pulse generator signal Sequence Flag 1 2 Selects the specified sequence flag Sync 1 2 Selects the specified sync signal CHT1 4 Selects the specified channel test signal Idle Active Idle active flag Sequence Active Sequence active flag Error DRM error flag Pass Valid DRM Pass Valid signal Waveform 5 Waveform 5 DRM Sync DRM Sync signal Driver Disable DRM driver disable command Waveform 6 Waveform 6 Soft Front Panel Operation 5 14 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API function is e tat964 setltbTriggers
355. nction is e tat964_setPulseParameters Mode This pull down control programs the pulse generator mode Astronics Test Systems Soft Front Panel Operation 5 35 Model T940 User Manual Publication No 980938 Rev K Period Delay The selections for this pull down control are Table 5 33 Pulse Generator Mode Settings Setting Description Continuous The pulse generator begins continuous output when armed Continuous Start The pulse generator begins continuous output from the start of the sequence when armed Single Start The pulse generator outputs a single pulse from the start of the sequence when armed Single Step The pulse generator outputs a single pulse from the start of the specified step when armed Note if looping the sequence step or bursting the entire sequence the pulse generator will re trigger The relevant VXlplug amp play API function is e tat964 setPulseParameters This input control is used to specify the step number when the Mode is set to Single Step The Step is programmed with a range of 0 to 4095 The relevant VXlplug amp play API function is e tat964 setPulseParameters Note This setting is hidden unless the Single Step Mode is selected This input control is used to specify the pulse generator period If the resolution is 10 ns the period is programmed in 10 ns steps with a range of 20 ns to 42 949672970 s If the resolution is 20 ns the period is programmed in 2
356. ne the data level when the record mode is set to Record Response The selections for this pull down control are Table 5 35 Raw Record Basis Settings Setting Description Good 0 Use good 0 comparator levels only available on dual threshold Driver Receiver boards like the DR3e Note The Good 0 is complemented when recorded Good 1 Use good 1 comparator levels These two choices are provided for use with the DR3e Driver Receiver The relevant VXlplug amp play API function is e iat964 setRecordParameters Record Offset The record offset allows the user to shift the record signals pattern code expect and mask record offset window strobes to accommodate system and UUT Soft Front Panel Operation 5 38 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual delay See the Record Offset section in Chapter 8 for more details about using this feature The valid offset range is from 0 to 63 MCLKs The relevant VXlplug amp play function is e tat964 setRecordParameters Note Once calibrated for an Independent Linked or DRS configuration this offset should not be changed Record Type This pull down control programs the record type The selections for this pull down control are Table 5 36 Record Type Settings Settings Description Normal Data stored in the record memory will be at the same offset as the pattern set memory Indexed Data stored in the record memo
357. nel TTL I O DR9 Driver Receiver Board Type 9 24 channel programmable DRA Driver Receiver Board A DRB Driver Receiver Board B DRM Digital Resource Module DRS Digital Resource Suite A DRS is two or more adjacent DRMs synchronized together to form a digital test system with more than 64 channels DSA Digital Sequencer A DSB Digital Sequencer B DUT Device Under Test DVH Drive Voltage High DVL Drive Voltage Low ECL Emitter Coupled Logic ECL TRG VXI ECL trigger EN Enable Error A channel error is determined by comparing the channel response to the expect mask conditions of the Pattern data GND REF Ground reference output from the pin electronics devices Good 0 A signal generated when an input signal is less than CVL Good 1 A signal generated when an input signal is greater than CVH Idle An execution state that outputs the entire pattern set of a specified step after a sequence burst Pattern and record memory cannot be accessed by the user Indeterminate An indeterminate PASS FAIL condition occurs if there is neither a valid PASS nor a FAIL This is discussed in more detail in the Jumping Halting Counting and Logging Errors section in Chapter 8 Input Output Jump Used to Jump out of the normal sequential flow of Sequence Steps to another Sequence Step The jump occurs at the end of the sequence step after all of the patterns have been output Terms and Acronym
358. nelSlewRate tat964 setChannelSourceParameters This allows the user to set the termination as direct or series See specific Driver Receiver board appendix for termination values The relevant VXlplug amp play function is e tat964 setChannelSourceParameters Soft Front Panel Operation 5 60 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Over Current Alarm Levels This allows the user to set the over current high OC High mA and over current low OC Low mA alarm levels for static current limits on the DR3e DRS9 and UR14 see Drive Fault for dynamic current limiting When the driver current exceeds the level an over current signal will be generated The range for OC High is from 0 disable over current monitor to 800 The range for OC Low is from 0 disable over current monitor to 800 The relevant VXIplug amp play function is e tat964 setChannelSourceParameters Active Load Depending on the installed Driver Receiver board the user can chose one of several programmable or selectable loads The selections for this pull down control are Table 5 61 Active Load Settings Setting Description None No active load Current Programmable current load Resistive to Selectable resistive load Resistive to VCC Fixed resistive load Resistive to GND Fixed resistive load Resistive to VCC GND Fixed resistive load The programmable current load allo
359. ng Counting and Logging Errors section in Chapter 8 for additional details about the use of halt The selections for this pull down control are Table 5 87 Halt Mode Settings Setting Description Disable Halt signal ignored Pattern Halt the current sequence at the end of the next pattern Step Halt the current sequence at the end of the next step Sequence Halt the current sequence at the end of the next sequence loop Sync 1 Halt the current sequence at the end of the next pattern according to where the Sync Pulse 1 is positioned Sync 2 Halt the current sequence at the end of the next pattern according to where the Sync Pulse 2 is positioned Pattern Fail Halt the current sequence at the end of the next pattern if the pass fail flag is set to fail Astronics Test Systems Soft Front Panel Operation 5 119 Model T940 User Manual Publication No 980938 Rev K Setting Description Step Fail Halt the current sequence at the end of the next sequence step if the pass fail flag is set to fail Sequence Fail Halt the current sequence at the end of the next sequence if the pass fail flag is set to fail Pattern Pass Halt the current sequence at the end of the next pattern if the pass fail flag is set to pass Step Pass Halt the current sequence at the end of the next sequence step if the pass fail flag is set to pass Sequence Pass Halt the current sequence at the end of the next sequence
360. ng Mode Settings Setting Description Per Step Multi 1024 steps with four phase window pairs per step Per Step Single 4096 steps with one phase window pair per step Soft Front Panel Operation 5 40 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Indexed 4096 sequence steps with 256 timing sets indexed Four phase window signals per timing set The relevant VXlplug amp play API function is e tat964 setTimingMode Output to Input Disable This pull down control programs the output to input disable setting When a channel transitions from an output pattern code to an input pattern code this enable can be set to disable the output at the beginning of the pattern System Clock or on a phase assert The selections for this pull down control are Table 5 40 Output to Input Disable Settings Setting Description System Clock Disable output on System Clock Phase Disable output on Phase Assert The relevant VXlplug amp play API function is tat964_setDriverEnableControl Pass Fail Basis This pull down control programs the sequencer pass fail basis The control allows the user to select which error signal to use to determine the PASS FAIL state for jumping The selections for this pull down control are Table 5 41 Pass Fail Basis Settings Setting Description Local Use local error Qualified Local Use CONDEN qualified local error
361. ng table Table 5 107 Power Converter Test Thresholds Power V Min V Max V Min V Max Converter Mode 12to 12 15 520 16 480 16 068 15 132 15 to 5 9 312 9 888 19 776 18 624 10 to 10 15 520 16 480 14 523 13 677 2 to 7 11 640 12 360 9 888 9 312 5 to 15 18 624 19 776 9 888 9 312 0 to 24 27 936 29 664 4 635 4 365 2 to 422 25 608 27 192 6 180 5 820 The relevant VXIplug amp play API functions are tat964_setPowerConverter e tat964_setPowerConverterState e tat964 queryAdcAverage Calibration Panel The calibration function is accessed from the Instrument Calibrate menu bar selection Reference Chapter 6 Programmable Channel Calibration for field calibration procedure Calibration data is stored on the Driver Receiver board in non volatile memory Astronics Test Systems Soft Front Panel Operation 5 159 Model T940 User Manual Publication No 980938 Rev K The calibration procedure requires that the Driver Receiver boards be reset in order to load the current calibration data Any unsaved calibration data will be lost Emo ERO Calibration requires the DRM Driver Receiver boards be reset Do you want to continue Figure 5 89 Calibration Confirmation Panel Selecting Yes displays the main calibration panel If the installed Driver Receiver board requires calibration the Calibrate Function control will list the available calibration items Not all Driver Rec
362. ng the Instrument Driver 2 11 erre EET 3 1 DRM Front oit oes oet docte lends test Lees iste 3 1 J200 and J201 DRA Channel I O 3 2 PWR Connector DRA DRB Power and Signals sse 3 2 Front Panel GOnnectors uc Ei toe Ett e Eas t Ue i ere Ead 3 3 Front Panel LBUS Lockout Keys Astronics Test Systems i Model T940 User Manual Publication No 980938 Rev K LBUS Lockout Key Installation neret ens 3 5 Gliapler E IP har 4 1 FurictlonalBescripHOon i eh eee tei elec 4 1 Digital Board DB ihi rero ie e Ie Hei 4 1 MP dcigenlm EE 4 2 Terms Used in this Section tht eet tte Pet a cta 4 2 1 Emm 4 2 Power 1 tat 4 2 4 and Type 3 auae aee ene c 4 3 doch cott umen wet dun 4 3 Inter Module Gontrol ione bee tr Ra t la ee E be ER HERE ERIS 4 3 Terms Used in this 4 244 eene entente nennt intres 4 4 Descriptio ca o e eoi eeu dE 4 5 T940 Inter Module Mode 2 4 5 Examples th itle 4 7 Data Sequerncet ze t rr vet EP ei ei t a vd det
363. nication registers 3 After about five seconds if the DRM passes its internal self test the SYSFAIL line will no longer be driven by the DRM and the Ready and Passed bits in the VXI Status Register are set If the DRM fails the self test for instance the Sys Fail indicator light glows red on the Controller or the Res Man software does not see the module the SYSFAIL line will continue to be driven Should this happen turn the chassis power off make certain the DRM is properly installed in the chassis and turn the chassis power back on Should the DRM continue to fail perform the following or contact Customer Support for assistance 1 Install the instrument driver see next section 2 Run the Soft Front Panel program and select Instrument gt Self Test Should the Soft Front Panel self test continue to fail contact Customer Support for assistance Customer Support contact information is included in the front section of this manual before the Table of Contents Software Installation The DRM is shipped with a VXlIplug amp play Instrument Driver VXlplug amp play Instrument Driver The DRM instrument driver links the communication interface and an application development environment ADE It provides a higher level more abstract view of the instrument It also provides ADE specific information that supports the capabilities of the ADE such as a graphical representation Some of the ADEs that this driver supports are lis
364. nneclors creed pt E SA HR RARE EEA D 1 REPE D 1 Auxiliary Driver amp Receiver 0 44 2 0 00 enne enne nnne entente nsns nitet en D 2 D 3 DR3e6 Driver amp Receiver I O eite ierit nennen en nona inane exe Rina dou D 4 SigiallDescrlptiOns v xs etse MS cue t es MU LEE D 4 Control Logics oie ku eo a etu b ea eure eel oiii D 5 SIGNAl DSSCKPUONS em D 6 Firmware amp NV Data ea oet ette ie etit e beet D 7 Signal Description Su te P die the D 7 DR3e Characteristics ice aee eer eite eda e te Hiep D 8 cM D 9 Power aa a N D 10 2 0 c ET D 11 DR3e Signal Description sssssssssssssesees enne enne nennen entrent nsns nnns enters D 12 DRA I O Channels 200 0 0 4 1 1000 0 000 10000 enne sn nnne D 13 DRB I O Channels 201 D 15 PWR COMEC O anie ete eorr a cde batur e ddr eS rd asa ea die D 17 D 18 AppendlX E 5o erro citt tide E 1 DR4 Driver R
365. nnelSenseParameters e tat964 setChannelLoadaState Channel Connect This control allows the user to control the isolation and analog bypass relays The selections for this pull down control are Table 5 63 Channel Connect Settings Setting Description Open Isolation and Analog Bypass Relay Open Closed Isolation Closed Analog Bypass Open Analog Isolation Open Analog Bypass Closed Bypass Note DR2 DR7 Driver Receiver boards do not have relay isolation DR9 is the only Driver Receiver board with the analog bypass relay The relevant VXIplug amp play function is tat964 setChannelConnect Hybrid Connect This control allows the user to connect any of the I O channels to a pin on the front panel called EXTFORCE Note Despite being called EXTFORCE it may be used to drive or sense the channel pin When the hybrid connection is turned On the driver is forced into high impedance and the front panel EXTFORCE pin is connected to the channel There is a series resistance of 40 ohms between EXTFORCE and the Channel Note The Channel Connect relay also needs to be closed Note The bandwidth is also limited to 3 MHz When the hybrid connection is turned Off the driver is enabled and the front panel EXTFORCE pin is disconnected from the channel The relevant VXlplug amp play function is e tat964 setChannelHybridState Comparator Delay This allows the user to add delay to the comp
366. ns drive and compare Current Source Sink Programmable Channel Commutating Voltage Vcom CMH and CML Range 0 4 mA to 20 mA usable to 24 mA Resolution lt 10 pA Accuracy 3 of PV 1200 Range same as driver Resolution 5 mV Accuracy 50mV 1 of PV Over Current Alarm IAH and IAL Range 800 mA Resolution 30 uA Accuracy 50mA 1 of PV Resistive Loads Selectable Channel 140 O to 1 8 selections to Vcom Accuracy 3096 PMU capability DUT GND Reference Input per Driver Receiver board Power Input Using Optional Front Panel Power Input Conncector for Pin Electronics devices Voltage Range Resolution Accuracy same as driver Offset range 3 V Interrupt Voltage 390 mV Resistive load 100 kO Bypass Relay On or Off V 10 to 28 V V 4to 19 V V to V delta 32 V DR9 Channel Over voltage Protection Clamped to 0 4 V beyond or V e current 200mA for lt 10ms Auto Shutdown e DC level within 1 V of V or V e Abys spike exceeding V or V Channel Capacitance 120 pF Channel Crosstalk Astronics Test Systems 250 mV pk pk DR9 Driver Receiver Board H 9 Model T940 User Manual Publication No 980938 Rev K Description Characteristics Pin Electronics Monitoring per channel All programmed levels Output and Input levels Temperature Voltage Monitoring per Driver Recei
367. ns e Calibration e Firmware Updates e Temperature Monitoring e Voltage Monitoring The instrument functions are dependent on the Driver Receiver boards installed For example the DR1 Driver Receiver board does not require voltage calibration and does not contain voltage and temperature monitoring hardware Self Test The self test function is accessed from the Instrument gt Self Test menu bar selection ES DRM Self Test Res Self Test Passed Figure 5 86 Self Test Result Message The self test function resets the instrument and performs a short RAM test on all the internal memories The short RAM test tests each RAM at the major address bits locations i e 0 1 2 4 8 16 etc The self test result codes are Soft Front Panel Operation 5 156 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 106 Self Test Result Code Descriptions Code Description 0 Self Test Passed 1 DSA 500 MHz clock test failed 2 DSA frequency synthesizer test failed 3 DSA VXICLK10 test failed 4 DSA pulse generator test failed 5 reserved 6 reserved 7 reserved 8 DSA sequence RAM test failed 9 DSA timing set RAM test failed 10 DSA persistence RAM test failed 11 DSA waveform RAM test failed 12 DSA record index RAM test failed 13 DSA error address RAM test failed 14 DSA pattern 0 CH1 CH8 RAM test fa
368. nstalled The Export button can be used to save the calibration factors into a text file for examination and later restore 0 File Load Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the ADC Reference menu item on the Calibrate Function menu Astronics Test Systems Programmable Channel Calibration 6 5 Model T940 User Manual Publication No 980938 Rev K 2 Verify that the ADC Reference calibrate function is now in focus Calibrate Function Select Measurement Delay Equipment Basic Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 The default measurement delay is 200 ms Increase this value to give the calibration points more time to settle Programmable Channel Calibration 6 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Run Calibration Equipment Digital multimeter connected to DRA or DRB if installed via the EXTERNAL FORCE input EXT FORCE A Calibration Adapter Installed in J200 EXT FORCE B Calibration Adapter Installed J9A J9B E Figure 6 3 T940 DR9 DR9 T940 UR14 Connection Diagram Procedure 1 Select the ADC reference to be calibrated 2 Connect the DC Calibrator using the calibration adapter cable 3 Press the Run button Astronics Test Systems Programmable Channel Calibration 6 7 Model T940 User Manual Publication No
369. nt TO CLK period will not be allowed to be 16 Master clocks when the probe is enabled 10 Master Clocks when not OR the TO CLK is too slow period gt 65 5 us with a 500 MHz master clock or proportionately slower for a slower master clock 22 Clock Gen Fault The fault is automatically corrected but one or more patterns may have been corrupted 23 Drive Fault A Drive Fault occurred 24 Record Address Indicates that the data recorded at the last memory Overflow address may be corrupted 25 Record Index Indicates that there is more data recorded than can Overflow be reconstructed 26 ERROR Setup Fault DRS Linked Error Signal not assigned 27 PASS VALID Setup DRS Linked Pass Valid Signal not assigned Fault 28 Counter Data Ready Frequency counter data ready 29 Interval Data Ready Interval Timer data ready Astronics Test Systems Soft Front Panel Operation 5 141 Model T940 User Manual Publication No 980938 Rev K Bit Name Description 30 Probe Start Fault Probe button pushed while probe is not enabled or memory is not granted 31 External Start Fault External start signal while memory is not granted Enable Condition Event Clear Event These radio buttons enable disable the associated event from setting the sequencer interrupt event The relevant VXlplug amp play API function is e tat964_setEventEnable These LEDs indicate the current state of the associated signa
370. nt VXlIplug amp play function is e iat964 setPulseWidth Configure Data Sequencer Settings Access this panel from the menu bar Config Data Sequencer x Settings Where x is the sequencer you wish to configure VXIO 2 INSTR Configure DSA Settings 2 00 ns per s Record Type Error Address Basis 220 Normal Local v Timing Mode Output to Input Disable Pass Fail Basis Indexed m y Pass Valid Mode Disable Static State Off vi Astronics Test Systems Soft Front Panel Operation 5 37 Model T940 User Manual Publication No 980938 Rev K Figure 5 25 Data Sequencer Configure Settings Panel Error Record Basis This pull down control programs the sequencer error record basis This control allows the user to select how the response data will be evaluated for errors when the record mode is set to Record Errors The selections for this pull down control are Table 5 34 Error Record Basis Settings Setting Description Dual Use both good 1 and good 0 comparator levels Good 1 Use only the good 1 comparator Single threshold These two choices are provided for use with the DR3e Driver Receiver only The relevant VXlplug amp play API function is e tat964 setRecordParameters Raw Record Basis This pull down control programs the sequencer raw record basis This control allows the user to select which comparator will be used to determi
371. nterruptMode This control indicates that the event is currently true The relevant VXlplug amp play API function is e tat964 querylnterruptEvent Astronics Test Systems Soft Front Panel Operation 5 73 Model T940 User Manual Publication No 980938 Rev K Editing the Data Sequencers Editing the data sequencers consists of programming the following 1 Timing Sets 2 Patterns 3 Waveforms 4 Sequence Parameters 5 Sequence Steps pra cAUsersVPublidDocumentsDSAwalkLcig 000000 File Config Edit Instrument Help Data Sequencer A r A 57 Data Sequencer B gt Patterns TEST SYSTEMS Waveforms Sequence Parameters Sequence Steps Talon Instrum Figure 5 38 Editing the Data Sequencers Editing the Timing Sets The timing sets are used to control the channel drivers and receivers Each timing set has either one or four phase window groups based on the programmed timing mode Phases control the driver operation and consist of an Assert and a Return The Assert signal loads the next pattern code in to the output driver Pattern codes are discussed in the next section The Return signal is used to enable the format code in the driver The Return signal is not used for the Non Return format code See Stimulus Format earlier in this chapter CH1 2 Phase 1 Phase 2 Pattern Period Figure 5 39 Phase Timing Soft Front Panel Operation 5 74 Astronics Test Systems
372. nual VXIO 2 INSTR Driver Receiver A ww Ww wow C C C C e ww Ww Ww Ww Ww 8 Condition Event V Low V High V High V Low Delta Fault Ground Fault Temperature Alert I2C Error Over Voltage a Figure 5 78 DR3E DR9 UR14 Driver Receiver D R Events Panel The following DR3e DR9 UR14 Driver Receiver event bits are defined Table 5 98 Sequence Status Bit Descriptions Name Description DR3 DR3e DR9 UR14 Threshold Threshold V Low V too low error lt 9 65 lt 8 84 V High V too high error lt 29 00 lt 29 70 V High V too high error gt 2 80 gt 2 91 V Low V too low error lt 19 50 lt 19 8 Delta Fault The V to V delta error gt 34 00 gt 34 3 Ground DUT_GND to SIG GND gt 0 39 gt 0 39 Fault delta error greater than 390 mV even if its not being used as the DUT GND for the Pin Electronics devices Temperature One or more of the Pin NA NA Alert Electronics devices has exceeded the specified temperature 2 Error 2 communication bus has had an error in the communication protocol Over voltage One or more channels NA NA Fault had an over voltage Astronics Test Systems Soft Front Panel Operation 5 145 Model T940 User Manual C C C C C C C C C Publication No 980938 Rev K Group 2 Delta Fault Group 3 Delta Fault VT
373. nverter Condition e Counter Timer e PMU Sequencer Events The sequence events display is accessed from the Execute gt DSx gt View gt Sequencer Events menu bar selection Where x is the sequencer you wish to query Astronics Test Systems Soft Front Panel Operation 5 139 Model T940 User Manual e C E C E e e C c E E 5 e e E e e C C C E C E e e SVS See ee ee Publication No 980938 Rev Stop Freq Synth Error Multiple Subroutine Return Subroutine Error Subroutine Active Error Idle Complete Sequence Complete Extemal TO CLK Error Clock Gen Fault Drive Fault Record Address Overflow Record Index Overflow ERROR Setup Fault PASS VALID Setup Fault Counter Data Ready Interval Data Ready Probe Start Fault Extemal Start Fault Figure 5 76 Sequencer Event Status Panel The following sequencer enable condition and event bits are defined Table 5 96 Sequence Enable Condition Event Bit Descriptions Bit Name Description 0 Idle Started The idle state has been entered 1 Sequence Started The sequence active state has been entered 2 External Halt One or more external halts occurred 3 Burst Error One or more errors occurred 4 Jump One or more jumps occurred Soft Front Panel Operation 5 140 Astronics Test Systems
374. o level determined by the Pattern Code instruction in Pattern Memory Phase Return Output driver goes to complemented level determined by the Pattern Code instruction in Pattern Memory Astronics Test Systems Soft Front Panel Operation 5 55 Model T940 User Manual Publication No 980938 Rev K Setting Stimulus Format Description Comp Surround e Start of Pattern Output driver goes to complemented level determined by the Pattern Code instruction in Pattern Memory e Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory e Phase Return Output driver goes to complemented level determined by the Pattern Code instruction in Pattern Memory Note For this format to work effectively the assert must be at least 15 ns depends on the swing and slew rate programmed Force Low e Output driver goes to low level immediately after an update Force High e Output driver goes to high level immediately after an update Force Off e Output driver goes disables immediately after an update Force Phase e Phase Assert Output driver goes from high to low level e Phase Return Output driver goes from low to high level e Output driver coincides with the complement of the phase immediately after an update Force Phase e Phase Assert Output driver goes from low to high level e Phase Return Output driver goes from high to low level e Ou
375. o settle Astronics Test Systems Programmable Channel Calibration 6 23 Model T940 User Manual Publication No 980938 Rev K DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hitthe Continue button when the required temperature is reached If the temperature reaches 80 the process continues automatically Es DRM Calibration Warmup Temperature 100 00 60 00 40 00 10 00 47 00 Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution Review the results in the Status window Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for Src and Snk in the field controls These values are not in engineering units 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted the calibration factors will revert at the next power cycle Programmable Channel Calibration 6 24 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Calibrate Function Serial Number Driver Receiver gor 12060853 DRB Stat Chan 1 Meas Delay 0200 End Channel 4 24 1 4 21A
376. odel T940 User Manual Publication No 980938 Rev K J9 Connectors The J9 connectors are used for calibration and for access to the auxiliary and probe signals E PH Figure H 7 DR9 J9 Calibration and Auxiliary Connectors Table H 13 J9A Pinout Name Pin Description No AUX5A 1 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX6A 3 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX7A 5 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX8 A 7 Bi directional General Purpose LVTTL I O pin 50 Ohm series PROBE MODE A 9 Output Probe Support Output BCLK A 11 Output Serial Clock 13 Bi directional Probe Button Input MPSIG A 15 Output Multi purpose Signal MONITOR A 17 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time EXTFORCE A 19 Input External Force routed to all of the Pin Electronics devices used to calibrate the instrument to an external standard GND 2 20 Ground Even Table H 14 J9B Pinout Name Pin Description No AUX5 B 1 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX6 B 3 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX7 B 5 Bi directional General Purpose LVTTL I O pin 50 Ohm series DR9 Driver Receiver Board H 18 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual
377. odule i Inter Module Mode Power Converter Independent Not Linked v 12042 EIE Group Data Sequencer A Data Sequencer B Delay Signal Delay Delay Signal Delay Phase 1 hl 26 Phase 1 v 20 Error Pulse Width Record Mode Error Pulse Width Record Mode Figure 8 5 Setting the Record Mode Using the Configure Module Panel Setting the Record Mode to Disabled means the same as setting the Step Record Mode to None as shown above Astronics Test Systems Advanced Topics 8 7 Model T940 User Manual Publication No 980938 Rev K Setting the Record Mode to Non Error means that zeros will be written into the Record Memory for the Patterns on that Sequence Step effectively clearing the memory The last two Step Record Modes effect the Counting and Logging of Errors Each of these modes will be described in the Counting and Logging Errors section below Record Type The Record Type is programmed on the Config gt Data Sequencer gt Setting Panel The relevant VXlplug amp play API and ARI functions are e API tat964 setRecordParameter e ARI AssignPtgRecordType x VXIO 2 INSTR Configure DSA Settings 2 00 ns per co eee j Error Record Basis Raw Record Basis Error Count Basis Godd 7 Good0 Local mi Error Address Basis Local E Off Figure 8 6 Setting the Record Type Using the Configure DSA Settings Panel The two choices are e Normal e Indexed Setting the Recor
378. oiii ipi torii eia n pter ibt 5 91 a 5 92 Tane epe EH RE Te AH vespa id ed ER 5 92 Waveform PI UTI ET 5 92 Editing Sequence Parameters 5 93 Hee W 5 93 ERE ARD De 5 94 Vector Strobe isare oo c pce Ye pct dote pu eee ron e puce de 5 94 SEL Veclor BIS du rcd Urt nen dE c um rcd 5 95 felt PI EMI IE 5 95 Input Mode tte td e de tau t 5 96 Set Vector ictu eg dp t eo i pog m ei m edes s 5 96 E SE EE 5 97 Vector Jump ooi eoe cb n ete tees 5 97 ce re E a etd 5 97 Set Channel Test 32 2 piu ieee aiaa 5 97 Wu m 5 98 vi Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual MEILLEUR 5 98 Editing Sequence Steps ue eh ru tu n pte ede Rb 5 99 Internal te t eed ee 5 100 Glocks per Pattern uttter tta d rtt E e CE ERE o RE IE ER Rind 5 100 CPP Phase and Window Triggering sess 5 101 TIMING cC 5 101 Bee Yo fee Oana ree hei
379. olds 1 per byte 16 selections up to 1A MAX 5VREF EXTSENSE 10VREF 5VREF Figure 1 9 ADC Voltage and Temperature Monitoring Signal Descriptions Figure 9 BPV BPV VXI Backplane derived power from the T940 Digital board V V Bias Power required for operation of the Pin Electronics devices Astronics Test Systems UR14 Driver Receiver Board 1 13 Model T940 User Manual Publication No 980938 Rev K POWER CONTROL UR14 logic controls Pin Electronics solid state switches 10VREF 5VREF 5VREF 10VREF Precision voltage references used for calibration of UR14 Pin Drivers The UR14 Logic controls the enable and selection of these references 5VREF is used for accurate generation of the DAC INREF 1 4 references EXTSENSE This analog signal connects to the Pin Driver for internal reference calibration It is also used for calibrating the external probe AUX A 1 AUX A2 AUX B 1 4 Programmable level I O to and from the PIN Electronics OCREF 1 4 Programmable current detect thresholds for the Open Collector Channel I O There are seventeen levels that can be programmed from 0 to 1 A There are four references one per byte INREF 1 4 Programmable input reference detect thresholds for the Open Collector Channel I O There that be programmed from 0 V to 20 V There are four references one per byte OVH 1 6 OVL 1 6 Connected to the Pin Driver electronics channel I O and provide to the rea
380. om the programmable input receivers 1 good 1 0 good 0 Response Low input signals to the Data Sequencer from the programmable input receivers 0 good 0 1 good 1 CONTROL Control Logic signals to control isolation relays termination pin electronics and temperature thresholds CHA 1 24 These are Bi directional programmable I O channels from CHB 33 56 the DR4 Drivers and Receivers connected to the UUT TEMPMON Real time temperature monitors the PCB junction plane SHUTDOWN These are signals that control the driver output used in Direct Drive mode SEQUENCER A 17940 Digital Board Sequencer logic that provides the Stimulus and captures Response data SEQUENCER B 17940 Digital Board Sequencer logic that provides the Stimulus and captures Response data 48V This is the common power bus from used by the Prog Positive and Prog Negative regulators DAC Provides the reference used to generate the programmable Positive and Negative Regulator Voltages CHANNELS TO MUX ADC DC levels of the High Voltage Channels is measured using these signals for Field Calibration PROG POSITIVE NEGATIVE REGULATORS These programmable regulators provide the bias power for the High Voltage channels There are three GROUP power regulators CHANNELS TO MUX ADC DC levels of the High Voltage Channels is measured using these signals for Field Calibration The ADC can also be used to monitor other board voltages including the Power Regulators Astron
381. ompare Input V This control sets the comparator level of the selected channel group Min 0 0 Max 20 0 The relevant VXlplug amp play API function is e tat964 setUtilitySenseLevel OC Detect A This allows the user to set the over current threshold of the selected channel group The detect level can be set from 0 0 A to 1 A in increments of 62 5 mA The relevant VXIplug amp play function is e tat964 setUtilitySourceParameter All Channels Sets the compare input and OC detect levels of all four channel groups to the current panel settings The relevant VXlplug amp play functions are e tat964 setUtilitySenseLevel e tat964 setUtilitySourceParameter Configuring the AUX Channels Access this panel from the menu bar Config AUX Outputs Astronics Test Systems Soft Front Panel Operation 5 65 Model T940 User Manual Publication No 980938 Rev K ws Om Om Eia 91088 Om ZA Om 12 _ Figure 5 35 Configure AUX Channels Panel UR14 The AUX channels are a set of 12 multi purpose signals that can be used for any of the following I O resources 1 Trigger Source Input 2 Frequency Synthesizer Reference Clock Input 3 System Clock Input Soft Front Panel Operation 5 66 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Vector Jump Address Input Waveform Output Pulse Genera
382. on Characteristics General 50 MHz data rate I O Per channel relay isolation AUX 1 2 A AUXT 1 2 dedicated to the Probe when used Programmable AUXS3 A LVTTL 50 series terminated AUX4 A LVTTL dedicated to the Probe when used AUX 5 9 A LVTTL or ECL AUX 6 10 A These channels share a pin on the connector AUX 7 11 A They are a programmable selection of one of three AUX 8 12 A types LVTTL SE ECL or Differential ECL LVTTL selection is series 50 O terminated ECL is parallel terminated 50 O to 2 V AUX 9 12 A Negative side of differential ECL AUX 9 12 A used when these channels are configured as differential ECL Parallel terminated 50 O to 2 V Bi directional General purpose 1 50 MHz data rate I O Per channel relay isolation AUX 1 4 B Programmable AUX 5 8 B LVTTL or ECL These channels are a programmable selection of either LVTTL or SE ECL LVTTL selection is series 50 O terminated ECL is parallel terminated 50 O to 2 V AUX 9 11 B SE ECL or Differential ECL AUX 9 11 B Parallel terminated 500 to 2V Power Requirements Table 10 Power Requirements not including Power Converter power consumption Voltage Peak Current Dynamic Current 5 3680 330 5 2 V 800 mA 25 mA 2 V 694 mA 10 mA 12 V 710 mA 42 mA 12 V 80 mA 20 mA 24 V 3270 mA 300 mA 24 V 2980 mA 290 mA UR14 Driver Receiver Board l 26 Astronics Test Systems Publication No 980938 Rev K Model T940
383. on Details The following table describes what will happen under various conditions It s a flow chart in a tabular form The column designates that the Test Condition was True The nomenclature for the table is e JSA Jump Sequence Addr e CA Loop Counter Active e LC Loop Count from the Sequence Step e CD Loop Count Done e BCD Burst Count Done BC Burst Continuous e Use Counter Once LAST Aflag used to denote that a LSTSEQ had a jump to a SUBRT thus the Return needs to be altered The general order of precedence is e Jump e Return e Last Sequence e Next Sequence Jump LSTSEQ RTN SUBRT CLOOP Action Comments Proceed to the next Seq Step Jump to JSA Proceed to the next Seq Step e f LC 0 proceed to the next Seq Step e f LC gt 0 and CA 0 load the designated Loop Counter set 1 and jump to JSA e If CA 1 and NOT LCD decrement the loop counter and Jump to JSA o ololo o ololo o ololo a 2loo A Astronics Test Systems Advanced Topics 8 37 Model T940 User Manual Publication No 980938 Rev K Jump LSTSEQ RTN SUBRT CLOOP Action Comments e 1 and LCD reset CA if UCO 0 and proceed to the next Seq Step Proceed to the next Seq Step e If NOT IN SUB set the IN SUB flag save the Return Seq addr and jump to JSA e Otherwise proceed to the next Seq Step a
384. on different sequencers Since Aux Inputs can drive TRG Bus lines they can be ORed ANDed or even combined with Channel Test signals in various ways For example an Aux input could be a qualifier for a Channel test When a TRG Bus line is configured to drive out an ERROR a Synchronization Signal a Sequence Reset a Master Reset or Driver Disable signal the corresponding input of these signals to the Master will be automatically configured The combination of up to 4 TRG Bus signals may be used to formulate a 1 of 16 vector to the sequencers so one can do a vectored jump to 1 of 16 locations based on the state of these four signals Advanced Topics 8 44 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix A Glossary of Terms and Acronyms This appendix includes a list of many of the terms and acronyms used this manual A16 A24 A32 The VXI address is segmented into three separate areas by a group of VXI signals called the address modifiers 0 5 These three areas are called A16 A24 and A32 Every VXI module is mapped into 64 bytes of the A16 memory VXI modules in addition may request additional memory map space in the A24 or A32 space The DRM maps the Sequencers and Driver Receiver board s registers into the A24 A32 space ADE Application Development Environment ARGCS Agile Rapid Global Combat Support Assert Rising edge of a Phase
385. onal Jump Sources per seq step One of four Test Inputs Seq Step PASS Seq Step FAIL Seq Step NOT a PASS i e FAIL or indeterminate Seq Step NOT a FAIL i e PASS or indeterminate Burst PASS Burst FAIL Conditional Jump Enable CONDEN Per pattern PASS FAIL Pipeline Burst Error Enable BERREN 0 31 patterns Per pattern Test Input Sources TTLTrg0 7 ECLTrg 0 1 F P AUX I O 1 12 Chan 1 32 with mask expect Test Input Sense Rising edge Falling edge Hi state or Low state Sync Pulse Outputs Outputs per Sequencer 2 Modes Start of Sequence Start of Sequence Step Offset Range 0 1M patterns Pulse Width 1 4095 patterns AUX Outputs Sync Pulses 2 Sequence Flags 2 Sequence Idle Active TOCycle Waveforms Phases Windows A multitude of other signals Sequence Standby Characteristics A one word continuous sequence step that may be used to output standby data on power up or after a sequence reset The CPU can access pattern data in this state Idle Sequence Characteristics A continuous sequence step that may be used to output data before or after an active sequence The CPU cannot access pattern data in this state The Idle Sequence output after the active sequence may be different from the one output before Specifications 7 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Sequence Execut
386. onnecting the VXI Bridge to the Data Sequencers and the Driver Receiver board s Control Logic SBUS This bus allows the UR14 Control Logic to read and write programmable Driver and Receiver References and configuration SERIAL BUS Communication and control by the UR14 Logic of the DAC and ADC are facilitated by this bus UR14 Control Logic This control logic provides facilitates UR14 functions including access to the Pin Electronics devices Temperature Monitoring programming Voltage Over voltage and Over Temperature detection Firmware and Calibration Storage The UR14 Control Logic FPGA firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility UR14 calibration data is stored in an on board EEPROM and is loaded initialization of the T940 unit UR14 power on time is stored for reference using an on board timer External Probe Module Block Diagram The External Probe Module Figure 10 is connected to the UR14 via a cable and mounted externally It provides the interface for probe functions designed into the T940 Sequencer Logic to support probe functions Astronics Test Systems UR14 Driver Receiver Board 1 15 Model T940 User Manual Publication No 980938 Rev K T940 DB PROBE MEMORY T940 SEQA LOGIC T940 UR14 PROBE OUT DUT GND T940 EXTERNAL PROBE MODULE c gt PROBE gt A
387. onnector Pinout by Pin 2 0040204 20 4 4 1204 nennen nnns H 14 Table H 7 J2A Connector Pinout by Pin Number ssssssssseeeeeneneenneneen nnne nennen H 14 Table H 8 J1A Connector Pinout by Pin Number nnns H 15 Table H S DRB BesO0Urces s ode RR Ee ER RR e Sent RM ae enr eiit H 16 Table H 10 J3B Connector Pinout by Pin 10 H 16 Table H 11 2B Connector Pinout by Pin H 16 Table H 12 J1B Connector Pinout by Pin 0 H 17 Table Hes19 J9A inane edet a tear H 18 Table Hti J9B PinOUt irn ea en eere etse ta teet n PE e End H 18 Table 1 1 External Probe Module I 19 Table l 2 Utility Channel 1 20 Table 1 3 Programmable Channel Characteristics essen 1 21 Table l 4 Programmable AUX I O Min Max Levels Front 1 23 Table 1 5 Programmable AUX I O Min Max Levels Power Converter 1 or 23 Table 1 6 ADC Characteristics 21 00 0 1 24 Table l 7 Probe Support dr aede eed tee ova 1 24 Table 1 8 Probe Module Characteristics esses nennen
388. ontrol isolation termination and configuration relays Front Panel AUX I O Front Panel I O for the minus side of the ECL buffers for AUX I O 9A through 12 Front Panel I O for the positive side of the ECL buffers for AUX I O 9A through 12A These I O pins are connected to AUX 5 8 A 5 to 9 6 to 10 7 to 11 8 to 12 Front Panel I O for the LVTTL buffers for AUX I O 5A through 8A These I O pins are connected to AUX 9 12 A 5 to 9 6 to 10 7 to 11 8 to 12 UR14 Driver Receiver Board 1 5 Model T940 User Manual Publication No 980938 Rev K AUX RH 5 8 B MC100ELT24 MC100ELT25 74LVT125 AUX 5 8 CONTROL Figure l 4 Auxiliary AUX 5 8 B LVTTL SE ECL I O For these Auxiliary signals an pin assignment of either ECL or LVTTL requires no Sequencer assignment changes Signal Descriptions Figure 1 4 AUXRH 5 8 B Auxiliary Response Inputs to the Data Sequencer from the LVTTL or ECL input buffers AUX EN 5 8 JB Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 B Auxiliary Data outputs from the Data Sequencer to the ECL and LVTTL output buffers CONTROL Control Logic signals to control isolation termination and configuration relays AUX 5 8 B Auxiliary 5B through 8B programmable selection between SE ECL or LVTTL I O Vbb ECL Switching threshold typically 1 29 V UR14 Driver Receiver Board 1 6 Astronics Test Systems Model T940 User Manual
389. ood Good DRS Linked Record Offset Record Type Error Address Basis 210 Normal Y DRS Linked Timing Output to Input Disable Per Step Muti w Phase Drive Fault Figure 8 15 Setting the Halt Mode in the Execute DSA Panel e If there is neither a Valid Pass nor a Fail it is called Indeterminate NOT Pass is a Fail or Indeterminate NOT Fail is always the complement of a Fail A Sequence Fail is any channel Error that occurred during the Sequence as though the Burst Count is set to 1 e A Sequence Pass says that there were no channel Errors during the Sequence as though the Burst Count is set to 1 e The Pass Valid Enable option determines if it s a simple Pass or a Valid Pass Astronics Test Systems Advanced Topics 8 19 Model T940 User Manual Publication No 980938 Rev K Table 8 7 covers the above bullets Table 8 7 Truth Table Describing Pass and Fail Pass Valid Error Qualified CONDEN Pass Fail NOT Valid Pass Pass Fail Pass Fail Mode Basis X H L X H H L L X L L X H L H H H L L X H L L H H L L L X L X X X H L H L H X X H H H H H L L X L H H H L H H H L H H H L L H H L L H H L Code HzYes enabled active L No disabled inactive I2Indeterminate care As mentioned above with the default settings the cumulative results of Pass Fail are used to ma
390. oop counters Each of the sixteen loop counters can be programmed to either reload its count or disable when the terminal count is reached Astronics Test Systems Soft Front Panel Operation 5 93 Model T940 User Manual Publication No 980938 Rev K Given the following sample loop sequence Step 1 jump step 1 using LCO count 2 Step 2 jump step 1 using LC1 count 3 Example 1 If both loop counters reload on terminal count then the step order will be Ty 1 2 1 1 2 1 1 2 1 1 2 Example 2 If loop counter 0 is set to disable then the step order will be 1 1 2 1 2 1 2 1 2 The relevant VXlplug amp play API function is e tat964 setSequenceLoopMode Pipeline This control programs the pipeline depth The pipeline may be from 0 31 Patterns deep The 0 pipeline depth will hereafter be called a zero pipeline depth A pipeline depth of 1 31 will hereafter be called a non zero pipeline depth A non zero pipeline depth offsets the PASS FAIL result by the corresponding depth of the pipeline in patterns See the Jumping Halting Counting and Logging Errors section in Chapter 8 for a more in depth explanation of how pipelining affects jumping counting burst errors and the logging of errors in the error Address Memory The relevant VXlIplug amp play function is e tat964 setConditionPipelineMask Vector Strobe This control allows the user to set the vector strobe signal The closing edge of the selected window will s
391. or each sequence step TOCycle Period Range per Sequence step 20 ns to 65 5 us using the 500 MHz master clock TOCycle Timing Resolution 1 ns using the 500 MHz master clock Phase Programming Range 0 ns to 65 5 us using the 500 MHz master clock Window Programming Range Phase Window Timing Resolution 0 ns to 65 5 us using the 500 MHz master clock 1 ns using the 500 MHz master clock Minimum Phase Window Pulse Width 8 ns using the 500 MHz master clock Phase Window Reference Phases System or Pattern Clock selectable per sequence step Windows Pattern Clock only Phase Window Range 0 to Pattern Period 8 counts Window Dead Time 13 ns at the end of the Pattern period Astronics Test Systems Specifications 7 1 Model T940 User Manual Publication No 980938 Rev K Clocks per Pattern CPP 1 to 256 selectable per sequence step Pause Pattern Clutch Phases and Windows are frozen when asserted Can pause based on an external signal levels or edges Can pause based on a phase edge Can resume based on an external signal levels or edges or CPU Resume Can resume after a programmed delay 2 timers available Useful to implement a Wait Pattern timeout can be programmed to generate an event if a pattern is paused too long See the Pause and Halt section of Chapter 8 for additional details about the use of pause Halt
392. or connected to the protective third wire earth ground If the instrument fails to operate satisfactorily shows visible damage has been stored under unfavorable conditions has sustained stress Do not operate until performance is checked by qualified personnel Publication No 980938 Rev K Model T940 User Manual Table of Contents GEOR mS 1 1 1 Ree es 1 1 Overview and Features ies ote uet er Hia eed privet nette Ee eds 1 1 Driver Receiver Board Options esssssssssssseseeeeee eene tenen nnne nnne 1 4 Utility Resource UR 4 0 240 idadi i nnns trennen nensis nnn i 1 6 Basic Elements of the DRM System ssssssssssssssseseesee eene tentent nnns 1 6 Front Panel Rea tede Se Prades 1 8 Power Converter PC entente nnns nnns 1 9 Digital Board DB ed m dE dee E ERE PUR 1 9 ec EIE EENT AE E E EAE LEO 1 9 Inter Module 1 9 Data Sequencer 4 1 9 Driver Receiver DR 242244 0 essent nnne 1 9 Driver Receiver Board
393. or one or more patterns an error will be registered If an error is not registered it means that the channel for this pattern was not only as expected but also that there was a valid capture If an error is registered it could mean that the channel for this pattern was either not as expected or there was a capture fault Capture faults are registered separately so that one can determine if there was a capture fault for this channel on one or more patterns If so one can look for programming faults and fix them first Once the capture faults are taken care of any remaining errors will now be bona fide errors channel data not as expected See the following Sequence Events and Driver Receiver Data Panel sections for more information about capture faults The relevant VXIplug amp play function is e tat964 queryRecoraData Probe Data Memory Display The probe data memory display is accessed from the Execute DSx View Results menu bar selection and setting the View control to Probe Data Where x is the sequencer you wish to query Astronics Test Systems Soft Front Panel Operation 5 135 Model T940 User Manual Publication No 980938 Rev K Es VXI0 2 INSTR Execution Results DSA e 1 2 3 4 gt Din la Figure 5 75 Probe Data Panel The probe memory stores eight bits of data from the 1 input for every pattern Table 5 95 Probe Memory Bit Descriptions Bit Description
394. or signal when the Mux Signal is set to Monitor A or Monitor B The relevant VXIplug amp play functions are e tat964 setGroupMonitorSignal AD Signal This control sets the analog diagnostic signal when the Mux Signal is set to Monitor A or Monitor B and the Positive Signal is set to AD The relevant VXlIplug amp play API functions e tat964 setGroupMonitorSignal CD Signal or E S Signal This control selects the analog diagnostic signal when the Mux Signal is set to Monitor A or Monitor B and the Positive Signal is set to AD and the AD Signal is set to Central Diag CD Signal or E S E S Signal The relevant VXlIplug amp play functions e tat964 setGroupMonitorSignal Register This control is used to select one of the thirty two DAC registers to query for factory test The relevant VXlplug amp play API function is Soft Front Panel Operation 5 172 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Value This control is used to display the selected DAC register value for factory test The relevant VXIplug amp play function is NA Chip Temperature Panel This panel is available with the following Driver Receiver boards DR3e DR9 e UR14 The temperatures on this panel will usually be less than what s shown on the Monitor Temperature panel The Monitor Temperature panel monitors the temperature near the output drivers which are usually hotter than
395. ory default settings However SW1 and SW can be set to modify several selections including e Logical Address Selection e Interrupt Level Selection A24 A32 Map Selection If you are using two or more T940 boards in a system there is also a jumper that needs to be set depending how it is configured for instance Primary Secondary or Terminator See the following sections for more information Installation 2 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual nmi hn Nh SW1 SW2 VXI Connector VXI Connector Figure 2 3 Digital Board DB Switch Locations CAUTION Switch settings shown in Figure 2 2 are for example only and are not particularly what your board should be set to Refer to the text for proper switch settings Logical Address Selection The VXI chassis Resource Manager identifies units in the system by the unit s logical address The VXI logical address can range from 0 to 255 The exceptions are addresses 0 and 255 Address 0 is reserved for the Resource Manager Address 255 is used for dynamic configuration The logical address of the DRM can be statically or dynamically configured SW1 an eight position DIP switch located on the DB Figure 2 3 is used to assign the logical address Refer to Table 2 1 A switch setting between 1 and 254 will establish a static logical address of the binary encoded value A switch setting of 255 will place the DRM in a
396. ow 31 V max Output Resolution lt 10mV Output Accuracy lt 2 100 mV Output Drive Current Output Impedance Selectable Channel 31V range 50 mA typical Source Sink 20V range 65 mA typical Source Sink 5 Q 50 20 Programmable Drive Current Programmable per group 16 Channel Input Threshold Ranges Input Threshold levels OVto 31V 15 5 V to 415 5 V 31V to0V Dual Threshold Input Threshold granularity Per 2 channels CVH and CVL shared Input Threshold Resolution lt 20 mV Input Threshold Accuracy lt 2 200 mV Skew Chan to Chan lt 5ns Pin Electronics Monitoring per channel Temperature Monitoring All programmed levels Output and Input levels Per 16 channel group junction plane monitors Voltage Monitoring Real time alarms for driver voltages Internal voltage measurements using internal ADC Auxiliary Channels 16 TTL Astronics Test Systems DR4 Driver Receiver Board E 7 Model T940 User Manual Publication No 980938 Rev K Power Requirements Table E 2 VXI Power Requirements Dynamic Voltage Peak Current 45V tbd tbd 5 2 V tbd tbd 2 V tbd tbd 12 V tbd tbd 12V tbd tbd 24 V tbd tbd 24 V tbd tbd Environmental Temperature Operating 0 C to 45 Storage 40 C to 70 0 C to 10 C Not controlled Humidity 10 C to 30
397. p 2 Error The 2 communication bus has NA had an error in the communication protocol These radio buttons enable disables the associated event from setting the Driver Receiver interrupt event The relevant VXIplug amp play API function is e iat964 setEventEnable These LEDs indicate the current state of the associated signal The relevant VXIplug amp play API function is e tat964 queryFrontEndCondition These LEDs indicate if the state of the associated signal went true The relevant VXIplug amp play API function is e tat964 queryFrontEndEvent This command button resets the event LEDs Note Any one of these faults except for Ground Fault or I2C Error will open the power relays This indicator displays the channel that generated the temperature alert event The alert is returned as a 32 bit number and then converted to text by the soft front panel Astronics Test Systems Soft Front Panel Operation 5 147 Model T940 User Manual Publication No 980938 Rev K Table 5 100 Alert Bit Descriptions Bit DR3e DR9 UR14 Channel Channel Channel 0 CH9 10 CH1 CH2 AUX3 B 1 CH3 CH4 CH7 CH8 AUX4B 2 CH25 CH26 CH4 AUX1A 3 CH13 CH14 CH5 AUX2A 4 AUX1 AUX2 CH6 AUX1B 5 CH23 CH24 CH3 AUX2 B 6 Local D1 Local D1 Local D1 7 CH17 CH18 CH9 CH10 NU 8 CH1 CH2 CH15 CH16 NU 9 CH7 CH8 CH12 NU 10 CH31 CH32 CH13 NU 11 CH27 CH28 CH14 NU 12 AUX3 AUX4 CH11
398. p see Editing Waveforms in Chapter 5 Waveform 1 through Waveform 4 have to be enabled per sequence step to replace the timing signals they are paired with Waveforms 5 and 6 are dedicated and do not need to be enabled Waveform1 Waveform4 This control allows the user to enable disable the specific waveform number The relevant VXlIplug amp play API function is e tat964 setSequenceWaveform Waveform Table This numeric control allows the user to program the waveform table for the sequence step Numeric values can range from Waveform Tables 1 through 16 The relevant VXIplug amp play API function is e tat964 setSequenceWaveform Phase Trigger Properties The phase trigger logic allows the user to select the phase trigger signal source for the four phases between the System Clock and the Pattern Clock PCLK In System Clock mode another Phase is output for each System Clock In Pattern Clock mode another Phase is output for each Pattern Clock which results in the Phase output rate being at a multiple of the System Clock period if gt 1 PERscik CPP The relevant VXlIplug amp play API function is e tat964_setSequencePhaseTrigger Astronics Test Systems Soft Front Panel Operation 5 111 Model T940 User Manual Publication No 980938 Rev K Execute the Sequence Sequence execution and control is performed from the Execute panel Access this panel from the menu bar Execute gt DSx Wh
399. p play API function is e lat964 setErrorParameters Error Address Basis This pull down control programs the sequencer error address basis This control allows the user to select which error signal causes an error to be recorded in the Error Address Memory The selections for this pull down control are Table 5 38 Error Address Basis Settings Setting Description Typical Usage Local Use local error Error recording is globally enabled Qualified Local Use BERREN qualified Error recording is enabled per local error pattern by the BERREN bit qualifier DRS Linked Use DRS Linked error DRS Linked error recording is globally enabled Qualified Use BERREN qualified DRS Linked error recording is DRS Linked DRS Linked error enabled per pattern by the BERREN bit qualifier If the Error Address Basis is enabled for DRS or Linked operation then the ERROR signal must be coupled between DRMs Sequencers via the TTL ECL or Linked TRG bus respectively The ECL TRG Bus is recommended for data rates greater than 10 MHz This is discussed in more detail in the Jumping Halting Counting and Logging Errors section in Chapter 8 including data rate limitations The relevant VXIplug amp play function is e tat964_setErrorParameters Timing Mode This pull down control programs the timing mode which selects one of three available timing set organization methods The selections for this pull down control are Table 5 39 Timi
400. p play API function is e tat964 setSequencerAttribute Window 3 Delay This control is used to delay the window 3 signal and is used when the Window 3 attribute is set to Jump 2 Typically Window 3 Mode can be used with an external response clock connected as the source of Jump Trigger 2 Window 3 Delay can be used to align an external response clock with the incoming response data The valid delay range is from 0 to 15 with 2ns resolution The relevant VXIplug amp play function is e tat964 setSequencerAttribute CRC Preload This control sets the seed number for the CRC preload and are available in sequencer revision 0 23 and later Astronics Test Systems Soft Front Panel Operation 5 51 Model T940 User Manual Publication No 980938 Rev K The selections for this pull down control are Table 5 52 CRC Preload Settings Setting Description Zeros Preload 0 s Ones Preload 1 s Masked Mask Preload The relevant VXI plug amp play API function is e tat964 setSequencerAttribute CRC Algorithm and Capture Mask These numeric controls set the number for the CRC algorithm and for the CRC capture mask settings and are available in sequencer revision 0 23 and later Table 5 53 CRC Algorithm and Mask Settings Setting Description CRC Algorithm A one in a bit position enables the corresponding CRC register bit feedback path Bit 0 corresponds to CH1 and bit 31 corresponds to CH32 CR
401. pdate button If this step is omitted the calibration factors will revert at the next power cycle Astronics Test Systems Programmable Channel Calibration 6 19 Model T940 User Manual Publication No 980938 Rev K ORM Calibration 00000 Driver Receiver Calibrate Function Serial Number 4 Vcom High Low 12060853 DRB Stat 20 1 Meas Delay 0300 End Channel 2 24 Channel 1 Offset cMH 2 82 d so A a ves Eme uem D Source Sink Load For DR3E DR9 and UR14 only the Source Sink Load calibration calculates the offset and gain of the current load levels The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the ISource ISink menu item on the Calibrate Function menu Programmable Channel Calibration 6 20 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual 2 Verify that the ISource ISink calibrate function is now in focus Calibrate Function Select Start and End Channels and Measurement Delay Equipment Basic
402. pdate the EEPROM ES Probe Calibration Update EEPROM The relevant VXlplug amp play function is Astronics Test Systems Soft Front Panel Operation 5 49 Model T940 User Manual Publication No 980938 Rev K e tat964 probeCalibration Attributes This command button on the Configure DSA Settings panel displays the Attribute panel so that the sequencer attributes can be programmed Jump Pass Fail 1 Phase 3 Mode Normal v Window 3 Mode Normal v Window 3 Delay CRC Preload Zeros 71 CRC Algorithm 00000000 Capture Mask 00000000 MI Figure 5 28 Attribute Panel Jump Pass Fail This control sets the sequencer step pass fail accumulator mode The selections for this pull down control are Table 5 49 Jump Pass Fail Settings Setting Description Normal Enable the sequence step pass fail accumulator Default Legacy Disable the sequence step pass fail accumulator Note See the Jumping on and Counting Errors section in Chapter 8 for details on Jump Pass Fail The relevant VXlplug amp play function is e tat964 setSequencerAttribute Phase 3 Mode This control sets the phase 3 signal mode that selects internal or external operation Internal phase 3 mode uses the normal phase generator to generate phase 3 External phase 3 mode uses the Jump 1 trigger to generate the phase 3 signal Phase 3 is typically set to Jump 1 to perform a Phase Replacement during a Pause and Resume ope
403. per pattern The waveform output repeats for every pattern in the sequence step All waveforms can be output on any AUX I O Channel Waveform 1 and Waveform 3 can also be output on any channel Access this panel from the menu bar Edit gt Data Sequencer x gt Waveforms Soft Front Panel Operation 5 90 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Where x is the sequencer you wish to configure 16x 1K Waveform Definition 0 10 20 Waveform Definition 10 20 100 200 Figure 5 51 Edit Waveforms Panel Waveform 5 Table Size This pull down control programs the waveform table size for waveforms 1 4 Astronics Test Systems Soft Front Panel Operation 5 91 Model T940 User Manual Publication No 980938 Rev K Waveforms 5 and 6 are fixed at 65536 The selections for this pull down control are Table 5 75 Waveform Table Size Settings Setting Description 16x1K 16 tables each with 1024 bits 8x2K 8 tables each with 2048 bits 4 x AK 4 tables each with 4096 bits 2x 8K 2 tables each with 8192 bits 1x 16K 1 table with 16384 bits The relevant VXI plug amp play API function is e tat964_setWaveformTableSize Waveform This pull down control selects the waveform to view edit Table Number This control selects the table number to view edit Waveforms five and six only have one table Waveform Definition This control allows the user to define the waveform
404. pter for control descriptions for this panel The relevant VXIplug amp play API functions e tat964 setAuxSourceLevels e tat964 setAuxSourceParameters tat964_setAuxSlewRate e tat964_setAuxSenseLevels e tat964 setAuxSenseParameters e iat964 setAuxLoadState ECL Mode ECL Differential or Bipolar Logic This control allows the user to select the ECL mode Table 5 69 ECL Mode Settings Setting Description Bipolar AUX configured as bipolar ECL Differential AUX configured as differential ECL The relevant VXlplug amp play API function is tat964_setAuxEclMode Logic Mode LVTTL Bipolar ECL Logic This control allows the user to select the LVTTL ECL mode Astronics Test Systems Soft Front Panel Operation 5 71 Model T940 User Manual Table 5 70 Logic Mode Settings Publication No 980938 Rev K Setting Description LVTTL AUX configured as LVTTL ECL Bipolar ECL AUX configured as differential ECL The relevant VXIplug amp play API funct e tat964 setAuxLogicMode Configuring the Interrupts ion is There are five hardware groups on the T940 that are capable of generating VXI interrupt VXI interrupts are generated from events in the hardware Each event has an enable that allows it to pass the event to the interrupt logic on the digital board The five hardware groups are 1 Data Sequencer A Enables set in the Execute gt DSA gt View gt Sequence Events
405. q Active A Channel Test Normal Operation e For inter module communication the active high and active low state of the backplane bus is handled automatically e For communications with other instruments the active high or active low state of the bus must be considered when o Receiving a signal from another instrument o Providing a signal to another instrument e The signals driving out onto these buses or coming in from these buses can be inverted Normal Operation Example e Todo a Jump Test on an Aux Input located on a Slave Sequencer o Select the TRG Bus to be used and select the Aux signal to drive it o Invert the output if the Aux signal is active low o Onthe Master select the same TRG Bus signal and use a High or Rising Edge test condition e Todo a Jump Test an input Channel Channel Test o Select the Channel Test to be used 1 of 4 on the Master or Slave Sequencer which covers that channel Pick the desired channel and unmask the channel test for that channel Set the expect level for the channel to be the level desired for a trigger Select the TRG Bus to be used and select the Channel Test signal to drive it On the Master select the same TRG Bus signal and use a High or Rising Edge test condition Advanced Operation Examples e Todoa Jump Test on the OR of several Channels Astronics Test Systems Advanced Topics 8 43 Model T940 User Manual Pu
406. quencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from the Data Sequencer to the ECL output buffers CONTROL Signals used to control isolation relays and ECL bipolar differential mode AUX 5 8 Four LVTTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 VBB ECL input threshold 1 3V AUX 9 12 Four negative differential signals used to input or output test signals See Configuring the AUX Channels in Astronics Test Systems DR3e Driver Receiver Board D 3 Model T940 User Manual Publication No 980938 Rev K Chapter 5 AUX 9 12 Four bipolar positive differential signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 DR3e Driver amp Receiver Figure D 3 illustrates the configuration and control of the DR3e Driver amp Receiver TEMPMON VO CONTROL Figure D 3 DR3e Driver amp Receiver Block Diagram Signal Descriptions DATA Channel and auxiliary data output signals from the Data Sequencer to the programmable output drivers EN Channel and auxiliary enable output signals from the Data Sequen
407. quencer B TEST SYSTEMS Figure 5 9 Edit Menu Table 5 3 Edit Menu Descriptions Menu Option Description Data Sequencer A Displays the panels for programming DSA timing sets patterns sequence parameters and sequence steps Data Sequencer B Displays the panels for programming DSB timing sets patterns sequence parameters and sequence steps Execute Menu The Execute Menu is used to program the run option and run the sequences TEST SYSTEMS Figure 5 10 Execute Menu Table 5 4 Execute Menu Descriptions Menu Option Description DSA Displays the execution panel for DSA DSB Displays the execution panel for DSB Astronics Test Systems Soft Front Panel Operation 5 7 Model T940 User Manual Publication No 980938 Rev K Instrument Menu The Instrument Menu is used to run self test calibration and monitor routines on the DRM hardware E auena oaa File Config Edit Execute Instrument Self Test m Astron fl aN Te Sal rests Power Converter Test Calibrate Talo Flash DRM Module Configuratio Temp Monitor DRA Voltage Monitor DRA Instrument Driver Revision 5 5 Serial Number 12030275 Chip Temperature DRA Assembly Revision A Temp Monitor DRB Power Converter Rev A Chassis Type VXI 3 0 Voltage Monitor DRB Module Interconnect Not Instal Chip Temperature DRB Utility Reference Monitor Slot 4 40 0 2 1 5
408. r AUX1L indicates the low comparator and AUX1H indicates the high comparator The relevant VXlIplug amp play functions e tat964 querySequencerChannels e tat964 querySequencerAux Astronics Test Systems Soft Front Panel Operation 5 149 Model T940 User Manual Publication No 980938 Rev K e tat964 querySequencerDriveFault e tat964 querySequencerOverCurrent e tat964 queryCaptureFault VXI Trigger Readback Panel The VXI trigger readback display is accessed from the Execute gt DSx gt View gt VXI Trigger Readback menu bar selection Where x is the sequencer you wish to query TTLTRIGO TTLTRIG2 TTLTRIG3 TTLTRIG4 TTLTRIGS TTLTRIG6 TTLTRIG7 ECLTRIGO ECLTRIG1 2 2 Figure 5 81 VXI Trigger Readback Panel This panel displays the current level of the eight TTL and two ECL VXI backplane triggers The LED illuminated indicates a high state Note A high TTLTRG signal is active low on the backplane The relevant VXIplug amp play API function is e tat964 queryVxiTrigger Query Power Results Message The query power results display is accessed from the Execute gt DSx gt View gt Power Query menu bar selection Where x is the sequencer you wish to query Soft Front Panel Operation 5 150 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Minimum front panel power V A 10 000000 V A 3 000000 Figure 5 82 Query Power
409. r Ya eo gara aaa eve 6 8 Select Start and End Channels and Measurement Delay sse 6 9 DRM Calibration Warmup z dte e e te ed ae i i t dte 6 9 RUM Calibration ico eu Nueva 6 10 Source Sink EOAd 2 e aa OM ates doen xe da OT qe de LT AE bee RR dde 6 11 Select Calibrate FUNCUON iiic tanen enero art at die dne enean atat der n drea nera dg 6 11 o Evae 6 11 tii 6 13 Select Calibrate F rcliOm tee an 6 13 Select Start and End Channels and Measurement Delay sss 6 14 DRM Calibration Warmup sssssseseseseeenenennnenene enne ennt sn nennen nnns nennen nenn 6 14 Run Calibration wen c teer alae eed e d e 6 14 iiie 6 15 Select Calibrate F nctiOm cene tc rn een 6 15 Select Start and End Channels and Measurement Delay sss 6 16 DRM Calibration essent sn 6 16 EE 6 17 Vcom High EOW sis 3 Eno tei End ib te tides 6 18 Select Calibrate Function sa as iners cite tie ct sand de oor no 6 18 Sel
410. r signal and Pass Valid if used are not delayed by the pipeline these signals will be aligned with the Jump Test made at the end of an individual Sequence Step or at the end of a Sequence Thus all the patterns in the Sequence Step or Sequence will be accumulated and none outside of the Sequence Step will be included But there is one option as follows Pass Fail Option 1 This option allows one to accumulate Pass Fail across consecutive Sequence Steps Pass Fail Option 2 Not useful in the non pipelined case Additional Pipeline Information e With a zero pipeline depth Raw Error is used for Error Raw Error comes directly from the channel in logic An Error is initially generated at the beginning of a pattern and then reflects the actual Error non Error after the final decision point Foranon zero pipeline Error is captured at the end of the Pattern period and then propagated as a pulse By using a pulse higher data rates can be accommodated For F W 0 21 and later the Pulse Width is set by the S W drivers for optimal operation For 0 20 F W and earlier the Pulse Width is set by the user PnP tat964 setErrorPulseWidth ARI AssignPatTimeGroup e Error and Raw Error can be examined Aux outputs e The pipeline depth needs to be set in the same in the Master and all coupled sequencers Astronics Test Systems Advanced Topics 8 23 Model T940 User Manual Publication No 980938 Rev K Valid Pass and Capture Fa
411. ration The selections for this pull down control are Soft Front Panel Operation 5 50 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 50 Phase 3 Mode Settings Setting Description Typical Usage Normal Phase 3 is sourced from the internal Internally programmed timing for drive phase generator Default phases Jump 1 Phase 315 sourced form the Jump 1 Externally programmed timing trigger signal controlled by an external stimulus clock tied to the Jump 1 Trigger source The relevant VXlplug amp play API function is e tat964 setSequencerAttribute Window 3 Mode This control sets the window 3 signal mode that selects internal or external operation Internal window 3 mode uses the normal window generator to generate window 3 External window 3 mode uses the Jump 2 trigger to generate the window 3 signal Window 3 is typically set to Jump 2 to perform a Window Replacement during a Pause and Resume operation The selections for this pull down control are Table 5 51 Window 3 Mode Settings Setting Description Typical Usage Normal Window 3 is sourced from the Internally programmed timing for internal window generator Default response windows Jump 2 Window is sourced from the Jump Externally programmed timing 2 trigger signal controlled by an external response clock tied to the Jump 2 Trigger source The relevant VXlplug am
412. rator result Burst Error Enable This flag allows the user to designate which patterns will be examined for Burst Error Burst Error counting and the logging of errors in the Error Address Memory BERREN is a qualifier for the burst error and burst error count An internal control bus connecting the arbitration and trigger logic on the VXI Bridge to the Data Sequencer Channel output data value Channel output enable value Channel input data which is the response data Channel input data which is either the response data or the input pattern code test result Channel output over current flag Channel input response high comparator result Channel input response low comparator result Condition Enable A qualifier for conditional jumping on error Control signals and registers to program the data sequence settings memory Signal that indicates an input pattern code failed BERREN and CONDEN flags Frequency Synthesizer Clock Sequence trigger used to stop the sequence controller for single stepping applications Signals used to set relay driver and mux settings Inter Module signals Inter module sequence Controller signals that can be assigned to the VXI or LTB for DRS coupling Error Pass Valid Sequence Reset DRS Sync Driver Disable Master Reset Sequence trigger used conditional jumping Functional Description 4 11 Model T940 User Manual LTB MCLK MPSIG DEI 1 2 PAT TO PATADDR PAUSE PCODE
413. rce ISink 4 112060853 DRB Offset Sre 4 7853 Snk 4 Calibrating SN 12060853 Calibrating Load Source and Sink Levels ves Exon ume secon Om Programmable Channel Calibration 6 22 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual IAL IAH For DRSE DR9 and UR14 only the IAL IAH calibration calculates the offset and gain of the over current alarm levels The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the IAL IAH menu item on the Calibrate Function menu M 2 Verify that the ISource ISink calibrate function is now in focus Calibrate Function Select Start and End Channels and Measurement Delay Equipment Basic Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The default measurement delay is 100 ms Increase this value to give the calibration points more time t
414. re start at the beginning of this step If this flag is set to Continue then the timer will not reset The relevant VXIplug amp play function is e tat964 setSequenceTimeoutContinue Gosub Return This control allows the user to specify the Gosub Return flag The Gosub Return flag is used to signal the last step of a subroutine The relevant VXlplug amp play API function is e tat964 setSequenceGosubReturn Sequence Flag 1 and Sequence Flag 2 This control allows the user to specify the level of Sequence Flag 1 and Sequence Flag 2 during this step These general purpose outputs can be routed any of the AUX outputs as well as the VXI TTLTRG and ECLTRG outputs The relevant VXlplug amp play API function is e tat964 setSequenceFlags Jump Type This pull down control programs the Jump Type Mode Normal sequence step execution proceeds sequentially until the step with the Last Step flag is set true Conditional and unconditional jumps and Gosubs can be added to allow the user to modify sequence step execution order Two jump types can be set Normal and Gosub e Normal jumps force the next sequence step number to be replaced by the specified jump step number e Gosub jumps save the current step number and forces the next sequence step number to be replaced by the specified step number The Gosub Return flag set true will force the sequence step number to be one more than the saved step number For example if step number
415. reset at the beginning of every step unless the sequence timeout continue flag is set in the Edit Sequence Step panel e Cannot be nested Does not stop during a Pause or Halt including single stepping e Atimeout will generate an event and the occurrence of this particular event can be enabled to generate an interrupt so the S W can query the events to see which one occurred e The continuous conditional loop will continue to branch unless the termination condition is subsequently met whereby execution will advance to the next Sequence Step as usual If it doesn t the user can manually halt or stop the Sequence e The sequence timeout can be used to generate an event to indicate that a sequence step or steps has taken too long to complete Pattern Timeout The pattern timeout timer is a real time timer which can be used in a sequence step that has a Pause e Inthe Sequence Step the Handshake Modifier can be set to the Pattern Timeout The Timer starts when the Pause begins The Pattern Timeout Timer will generate an event when the timer times out The Pause will continue unless the termination condition is subsequently met whereby execution will resume If it doesn t the user can manually resume or stop the Sequence Pattern Delay The two pattern delay timers are real time timers which can be used in a sequence step that has a Pause e Inthe Sequence Step the Handshake Modifier can be set to Pattern Delay 1 or 2
416. river amp Receiver I O Block D 3 Figure D 3 DR3e Driver amp Receiver I O Block nen D 4 Figure D 4 DR3e Control Logic Block Diagram sse D 6 Figure D 5 J200 and J201 Connectors cccceecceceeeeeeeeeeeeeeeeeeeeeceeeeeceaeeeeaaeeeeeeeseaeeesaeeteaeseeeeeeaas D 12 Figure D 6 Front Panel Optional DR3e PWR Connector sse D 17 Figure E 1 DR4 I O Block Diagram ienei aaae aaaea aaen iaaa entente sinis sinet E 2 Figure E 2 DR4 Driver Receiver Block 2 44 44 0 E 4 Figure E 3 Auxiliary Driver amp Receiver I O Block E 5 Figure 4 DR4 Power Configuration E 6 xxii Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure E 5 J200 and J201 E 9 Figure F 1 DR7 Driver Receiver Block emen F 2 Figure F 2 Auxiliary Driver amp Receiver I O Block F 3 Figure F 3 DR7 Driver 4 Receiver I O Block F 4 Figure 4 J200 and J201 F 7 Figure G 1 DR8 Driver Receiver Block 2 4 010000000000 G 2 Figure G 2 Auxiliary Driver amp Receiver I O Block
417. rom Stimulus Delay 10ns to Stimulus Delay 40s with 10ns resolution Note The Response Delay must be greater than the Stimulus Delay Soft Front Panel Operation 5 126 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Stimulus Response Kept Data For sequencer revision 0 21 and later this control sets the delay when the static input pins will be sampled from 0 to 6 5ms with 100ns resolution The delay is from the execution of the 1964 executeStaticPattern The relevant VXlplug amp play API function is e tat964 setStaticTiming e iat964 executeStaticPattern This table column contains pull down selections that sets the stimulus output state The selections for the table column pull down control are Table 5 92 Static Stimulus Settings Setting Description Z Disable the channel 0 Drive to low level 1 Drive to high level X Uninstalled channel The relevant VXlplug amp play API function is e lat964 setStaticData This table column contains the stimulus input state of the previous static execution The selections for the table column pull down control are Table 5 93 Static Stimulus Settings Code Description B Response between high and low L Response low level H Response high level Unknown The relevant VXlplug amp play API function is e tat964 queryStaticResponse The kept data display is accessed from the Execut
418. ront Panel Operation 5 59 Model T940 User Manual Publication No 980938 Rev K e tat964 setChannelSourceLevels Comparator Levels Driver Slew Termination The comparator levels allow the user to set the Compare High CVH and Compare Low CVL voltage The min max levels are dependent on the installed Driver Receiver board as well as the voltage mode Note The external supply voltages will also need to be adequate for the desired drive levels when using the DR3e external power option The relevant VXIplug amp play function is tat964 setChannelSenseLevels The driver slew allows the user to set the output Slew Rate The selections for this pull down control are Table 5 60 Slew Settings Setting Description Fast Sets the DR3e DR9 UR14 slew rate to 1 3 V ns Medium Sets the DR3e DR9 UR14 slew rate to 1 0 V ns Default Sets the DR3e DR9 UR14 slew rate to 0 7 V ns Slow Sets the DR3e DR9 UR14 slew rate to 0 25 V ns Low Power Sets the DR3e DR9 UR14 slew rate to 0 1 V ns Depressing the Custom command button allows the user to specify the DR3e DR9 UR14 Slew Rate Slew Rate and Bias The range for the Slew Rate and Slew Rate is from 3 slowest to 31 fastest The range for the Bias is slowest to fastest 4 5 6 7 0 1 2 and 3 The fastest slew rate would be with a value of 31 and a bias of 3 The relevant VXlIplug amp play functions e tat964 setChan
419. ront Panel Power D 10 Table D 5 VXI Power Requirements not including Power Converter power consumption D 10 Table D 6 DR3e DRA I O Channels 200 D 13 Table 0 7 DR3e Pinout by Pin Number D 14 Table D 8 DR3e DRB I O Channels 201 D 15 Table D 9 DR3e Pinout by Pin Number DRB essen ene D 16 Table 0 10 PWR Connector D 18 Table DAt Calibration Settings rr n Peta i ern endete D 18 Table E 1 DR4 Characteristics ette cet etit e de deed greed E 7 Table 2 VXI Power 00 8 Table E 3 DR4 DRA I O Channels 200 2 404444 0 0 0 0000 E 9 Table E 4 Pinout by Pin Number E 9 Table E 5 DR4 DRB I O Channels 7201 E 11 Table E 6 Pinout by Pin Number 4 4 E 11 Table E 7 Calibration E 12 Table F 1 DR7 2 2 0000 0 entente F 5 Table F 2 DR7 Power F 6 Table F 3 DR7 DRA I O Channels J200 sse eene nennen nnne nennen F 7 Table 4 DR7 Pinout by Pin Number
420. rovides all the timing for the sequencers that are part of the DRS chain Sequencer B can be coupled to the new chain terminate the previous chain Primary Terminator or run independently from the chain The primary module must be located in the rightmost slot position in the VXI chassis relative to the DRMs that will be coupled PWR Front panel connector for optional external power on the DR3e Reference A programmable DC voltage Return Falling edge of a Phase RTCASS Reconfigurable Transportable Consolidated Automated Support System Standby An execution state that outputs the first pattern of a specified Astronics Test Systems step after a sequence burst Pattern and record memory can be accessed by the user Terms and Acronyms A 3 Model T940 User Manual Publication No 980938 Rev K Secondary Used to describe the DRMs located between the primary and terminating modules that pass the timing signals to the DRM in the next higher slot position Individual sequencers can either be coupled or run independently from the primary module Sequence A sequence is an ordered list of stimulus response actions consisting of one or more sequence steps Sequence An execution of one or more patterns Burst Sequence A sequence step is a single element of a sequence A Step sequence step selects a timing set pattern set loop count jump condition and control flags S
421. rt Arm control is set to Start this command button starts the Idle sequence at the sequence step specified in the Execute Idle Step control If the Start Arm control is set to Arm this command button arms the Idle sequence at the sequence step specified in the Execute Idle Step control Arming the idle sequence would be used in conjunction with an external start trigger It is also used if this is not the Primary Sequencer in a DRS The relevant VXlplug amp play functions e tat964 executeldleSequence e tat964 armldleSequence Execute If the Start Arm control is set to Start this command button starts the sequence at the sequence step specified in the Execute Step control If the Start Arm control is set to Arm this command button arms the sequence at the step specified in the Execute Step control Arming the sequence would be used in conjunction with an external start trigger It is also used if this is not the Primary Sequencer in a DRS The relevant VXIplug amp play API functions e tat964 executeSequence e tat964 armSequence Halt The Halt command button halts the sequence based on the Halt Mode selection Once halted indicated by a red Halt LED another push of the Halt command button resumes the sequence and then halts it again single step See the Pause and Halt section in Chapter 8 for additional details about the use of halt The relevant VXIplug amp play function is e tat964 haltSequence Astron
422. ry will begin at offset 0 The record index memory contains the information needed to realign the record memory with the sequence step data The relevant VXlplug amp play API function is tat964 setRecordParameters Error Count Basis This pull down control programs the sequencer error count basis This control allows the user to select which error signal to use to determine the error count The selections for this pull down control are Table 5 37 Error Count Basis Settings Setting Description Typical Usage Local Use local error Error counting is globally enabled Qualified Local Use BERREN qualified local Error counting is enabled per pattern by the error BERREN bit qualifier DRS Linked Use DRS Linked error DRS Linked error counting is globally enabled Qualified Use BERREN qualified DRS Linked error counting is enabled per DRS Linked DRS Linked error pattern by the BERREN bit qualifier If the Error Count Basis is enabled for DRS or Linked operation then the ERROR signal must be coupled between DRMs Sequencers via the TTL ECL or Linked TRG bus respectively The ECL TRG Bus is recommended for data rates greater than 10 MHz This is discussed in more detail in the Jumping Halting Astronics Test Systems Soft Front Panel Operation 5 39 Model T940 User Manual Publication No 980938 Rev K Counting and Logging Errors section in Chapter 8 including data rate limitations The relevant VXlplug am
423. s simply called Reset Master Reset Allows a Master Reset performed on the Master or any coupled Sequencer to reset all of the Sequencers coupled together in a DRS Note a Master Reset disables all of the channel drivers among other things Astronics Test Systems Advanced Topics 8 5 Model T940 User Manual Publication No 980938 Rev K Signal When needed Driver If programmed to do so on each Sequencer a channel fault Disable which occurs on the Master or any connected coupled Sequencer will disable all of the channel drivers Static Pulse Couples the Static Stimulus Response Pulse from the Master to all connected coupled sequencers It is only needed if Static Mode is being used The signals above which are desired for a DRS configuration must be setup on the same TRG buses on the Master and each coupled Sequencer Warning Do not program the same TRG Bus for Sequencers which are not a part of the DRS Step Record Mode Step Record Mode is programmed in each Sequencer Step On the SFP it is set on the Edit gt Data Sequencer A B gt Sequence Steps panel The relevant VXlplug amp play and ARI functions are API tat964_setSequenceRecordMode e ARI AssignPtgResponseMode uc VXIO 2 INSTR Edit DSA Sequence Step 1 Data 1 00 ns per count s Pattems intemal TOCLK Clocks per Pattem M True T 0 2100 CPP 21 Sequence Tim
424. s A 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual JTAG Joint Test Action Group IEEE 1149 1 serial interface that allows the serial PROM to be reloaded for in field system upgrades CBUS An internal Control Bus connecting the VXI Bridge to the Data Sequencers and the Driver Receiver board s Control Logic 5 Liters per second flow rate measurement LED Light Emitting Diode Linked Mode DSA and DSB operating synchronously within a DRM LVDS Low Voltage Differential Signaling LVTTL Low Voltage TTL MCLK Master Clock Open The rising edge of a Window PAT CLK Pattern Clock Pass Valid A signal which conveys a Pass Valid Mode setting If Pass Valid is enabled for a DRS then the Pass Valid signal must be coupled between DRMs via the TTL or ECL TRG bus The ECL TRG Bus is recommended for data rates greater than 10 MHz This is discussed in more detail in the Jumping Halting Counting and Logging Errors section of Chapter 8 See also Valid Pass below Pattern One stimulus applied to and or one response received from the UUT Sometimes called a Word or Vector Pattern Set A Pattern Set is one or more consecutive channel patterns PBUT Probe button input signal to the Sequencer for support of remote probe operations PMODE Control signal from the Sequencer for support of remote probe operations Primary Used to describe sequencer A on the DRM that p
425. s to the auxiliary and probe signals Figure I 15 UR14 J9 Calibration and Signal Connectors Table I 19 J9A Pinout Name Pin Description No AUX5A 1 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX6 A 3 Bi directional General Purpose LVTTL I O 50 Ohm series AUX7A 5 Bi directional General Purpose LVTTL I O 50 Ohm series AUX8 A 7 Bi directional General Purpose LVTTL I O 50 Ohm series PROBE MODE A 9 Output Probe Support Output BCLK A 11 Output Serial Clock PBUT A 13 Bi directional Probe Button Input MPSIG A 15 Output Multi purpose Signal MONITOR 17 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time EXTFORCE A 19 Input External Force routed to all of the Pin Electronics devices GND 2 20 Ground Even Astronics Test Systems UR14 Driver Receiver Board 1 33 Model T940 User Manual Publication No 980938 Rev K Table 1 20 J9B Pinout Name Pin Description No AUX5 B 1 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 3 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 5 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 B 7 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series PROBE MODE B 9 Output Probe Support Output BCLK B 11 Output Serial Clock PBUT B 13 Bi direc
426. s with four phase window groups per timing set and 4096 sequence steps where each sequence step points to one of the 256 timing sets Double click on one of the available Assert Return Open Close cells Enter the desired value using the numeric keys or the up down arrows followed by the Enter key The timing value resolution is displayed in the title bar area of the panel Timing resolution is controlled by the Master Clock setting Use tat964 setMasterClockSource and tat964_setFreqSynth API functions to change the timing resolution The user can disable the timing set phases windows by setting Assert Return and Open Close values to zero For example Phase 1 and Window 1 are disabled during TS2 in the configuration shown below Edit DSA Timing Sets 1 00 ns per count NI Phase1 en Retum The relevant VXlplug amp play API function is e tat964 setTimingSetData Timing Set Value Rules For valid timing signal operation the following rules must be followed Phase pulse width must be greater than seven i e the Return value must be at least eight more than the Assert value e Window pulse width must be greater than seven i e the Close value must be at least eight more than the Open value e End of pattern dead time Phase Return and Window Close values must occur eight counts or more before the end of the pattern Additionally a Window Close must occur 13 ns prior to t
427. se from and two voltage modes Calibrating in a Voltage Mode range that is different from the range used in the application can cause a reduction in measurement accuracy Note Calibration procedures must be performed in the order shown below Changing the order of calibration from that which is shown in the procedure can invalidate the results The Calibrate panel before opening will inform the user that calibration mode requires the instrument to be automatically reset to its power on defaults If the instrument settings need to be saved prior to calibration or if the instrument is Programmable Channel Calibration 6 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual running a critical test now is the time to exit Select Yes if it is OK to continue or No if DRM calibration mode should be exited ina O Calibration requires the DRM Driver Receiver boards be reset Do you want to continue Access the Calibrate Function to be performed using the Calibrate Function drop down list From this list select the function on the T940 DRM to be calibrated The sections to follow describe the individual procedures in detail al Section ADC Reference via EXTERNAL FORCE For DR3E DR9 and UR14 only the ADC Reference calibration is used to measure the reference voltages used to calibrate the ADC Monitor path Connect the DC calibrator to the EXTERNAL FORCE input on either DRA or DRB if i
428. ser Manual Publication No 980938 Rev K Sequencer Operation Introduction The Pattern data describes both the Stimulus to be applied to the UUT and how the response from the UUT is to be examined includes expect data if applicable for each channel The Sequencer is a Mealy state machine that controls the flow of patterns The Sequencer is always running unless Paused or Halted these terms are similar to Pattern and System Clutch although they have broader application The sequencer memory contains one or more of the following A Primary Sequence is composed of one or more Sequence Steps and describes in total how all the Patterns will be applied to a UUT for a dynamic Stimulus Response test A Standby Sequence is a special Seq Step which defines the power up reset state of the sequencer It runs continuously and may output one pattern but response data is ignored An Idle Sequence is a special Seq Step that may be run before and or after the Primary Sequence The Idle Sequence run after a Primary Sequence may be different than the one run before a Primary Sequence An Idle Sequence always runs continuously and may output one or more Patterns but response data is ignored A Finishing Sequence is the Seq Step that is run after the Primary Sequence It may be an Idle Sequence or a Standby Sequence A Sequence Step defines a subset of the total number of Patterns to be applied to the UUT and defines
429. setOverCurrentControl Over Current Window An over current window can be programmed to wait for current transients to subside These transients are primarily due to cable length The over current test window is triggered on the assert or return edge of the selected phase and prevents an over current event from occurring until after the transient has subsided The selections for the over current window pull down controls are Astronics Test Systems Soft Front Panel Operation 5 43 Model T940 User Manual Publication No 980938 Rev K Table 5 43 Over Current Window Settings Setting Description 4 8 Set window to cables between 4 and 8 feet 8 3 16 3 Set window to cables between 8 3 and 16 3 feet 16 6 24 6 Set window to cables between 16 6 and 24 6 feet 25 33 Set window to cables between 25 and 33 feet 33 3 41 3 Set window to cables between 33 3 and 41 3 feet 41 6 49 6 Set window to cables between 41 6 and 49 6 feet 50 58 Set window to cables between 50 and 58 feet 58 3 66 3 Set window to cables between 58 3 and 66 3 feet 66 6 74 6 Set window to cables between 66 6 and 74 6 feet 75 83 Set window to cables between 75 and 83 feet 83 3 91 3 Set window to cables between 83 3 and 91 3 feet 91 6 99 6 Set window to cables between 91 6 and 99 6 feet 100 108 Set window to cables between 100 an
430. shaking The mated edge flip flops used for Pause Test 1 2 Resume and Phase Test 1 4 Resume are automatically cleared when not paused If the mated Resume is already satisfied like with a level the Pause will not occur When Paused the CPU cannot access the Pattern Record or Probe memories For 0 23 F W a Pause based on a level can only be cleared by removing the level causing the Pause Changing the Pause Test Condition will not clear a Pause nor will a CPU Resume a Pattern Delay Timeout or a Sequence Reset For 0 23 F W the Phase Pause edge may occur as early as Ons TO but not later than 16ns before the end of the period using a 500MHz Master Clock For 0 23 F W it is possible to record the correct results even when pausing To do so the observed Window decision edge must occur no later than 6ns after the Pause decision edge Aux outputs may be used to examine the timing relationship of the active Windows with respect to the Phase edge or external signal used to trigger a pause For 0 23 the Window decision edge in pattern n must occur before any pause in pattern n 1 by at least the amount of record offset in ns in order to capture results correctly For 0 23 the delay from a TTL Aux Pause 1 2 Trigger Input or a Phase 1 2 3 4 Pause to an actual pause 6 7ns Likewise the delay from Pause 1 2 Trigger Resume or a Phase 1 2 3 4 Resume is 6 7ns Astronics Test Systems Advanced Topics 8 33 Model T940 U
431. signals from the Receivers are examined and then based on the window timing WINDOW the response is analyzed with respect to the input code The channel results are routed to the Record RAM The cumulative Error signal goes to the Sequence Logic block so it can be used for Jumping Halting and the Counting of Errors Individual over current OC signals from the Channel Drivers can also be processed by this block to disable the channel drivers if desired AUX amp Probe Control AUX control allows user and diagnostic signals to be input or output the AUX pins The inputs go to the Sequence Logic block described above There is also a Multi purpose signal MPSIG which can be combined with other signals on the Driver Receiver board and provided to the user on the power connector Probe expect data is received from the Probe Flag RAM and result data is generated that is stored back into the Probe Flag RAM Astronics Test Systems Functional Description 4 15 Model T940 User Manual Publication No 980938 Rev K Driver Receiver The DRM can accommodate two Driver Receiver boards named DRA or DRB for their mounted location Each Driver Receiver board contains unique driver receiver circuitry and front panel connector pinouts that are described in an appendix dedicated to each specific Driver Receiver type Functional Description 4 16 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 5 Soft Front Panel
432. sition set to secondary LBUSA connected to LBUSC Primary driver disabled DRM is coupled to a DRS DSA and DSB are linked and independent Secondary DSA Coupled SIMA set to LBUSC and SIMB set to IMB IMJMPR position set to secondary LBUSA connected to LBUSC Primary driver disabled DSA is coupled to a DRS DSB is independent Secondary DSB Coupled SIMA set to IMA and SIMB set to LBUSC IMJMPR position set to secondary LBUSA connected to LBUSC Primary driver disabled DSB is coupled to a DRS DSA is independent Secondary DSA and DSB Coupled SIMA and SIMB set to LBUSC IMJMPR position set to secondary LBUSA connected to LBUSC Primary driver disabled DSA and DSB are coupled to a DRS Terminator DRM Inter Module Modes The following modes apply to a DRM that is jumpered as a Terminator Independent Not Linked SIMA set to IMA and SIMB set to IMB IMJMPR Functional Description 4 6 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual position is a don t care Primary driver disabled The DRM is not coupled to a DRS DSA and DSB are not linked e Independent Linked SIMA and SIMB set to IMA IMJMPR position is don t care Primary driver disabled The DRM is not coupled to a DRS DSA and DSB are linked and independent e Terminator Not Linked SIMA set to IMA and SIMB set to IMB IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled The
433. ssssssssseeeeeeee enne 5 161 Table 5 109 UR14 Monitor Signal Settings sese 5 175 Table 6 1 Calibration Functions and DRM 6 1 Table 6 2 Recommended Power Converter Settings 6 2 Table 6 3 Recommended Calibration Equipment ssssssseseseeeeeeeen nene 6 3 Table 7 1 Power Requirements DB 7 10 Table 8 1 Summary of When Specific DRS Signals are 8 5 Table 8 2 Summary of the Record Memory Action for each Step Record Mode 8 7 Table 8 3 Summary of the Record Memory Action for each Step Record Mode 8 9 Astronics Test Systems xxvii Model T940 User Manual Publication No 980938 Rev K Table 8 4 Cross Reference of Step Record Mode to Error Count 8 12 Table 8 5 Cross Reference of Step Record Mode to Error Address Basis 8 12 Table 8 6 Cross Reference of Step Record Mode to Pass Fail 8 16 Table 8 7 Truth Table Describing Pass and 8 20 Table B 1 DR1 Characteristics sess enne nnne B 5 Table 2 DR1 Power 6 Table B 3 DR1 DRA I O Channels 200 404444401 0 0 0 00
434. st Clear This pull down control programs the trigger event clear The event clear allows the user to program when the rising falling edge flip flops are cleared during operation for the following triggers e Pause 1 2 e e Jump 1 4 The selections for this pull down control are Table 5 32 Trigger Event Clear Settings Setting Description Start Clear flip flops at start of burst Step Clear flip flops at start of every sequence step Event True Clear flip flops when trigger event tests true Soft Front Panel Operation 5 34 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API functions e tat964 setPauseTriggerReset e tat964 setHaltTriggerReset e tat964 setJumpTriggerReset Configure Pulse Generator Access this panel from the menu bar Config Data Sequencer x Pulse Generator where is the sequencer you wish to configure Period 40 000000000 9 40ns to 85 899345960 Delay 3 20 000000000 9 20 to 85 899345960s Width 2 0 000000000E 0 Oto 85 899345960s Figure 5 24 Configure Pulse Generator Each data sequencer has a programmable pulse generator that can be routed to the following signals e Data sequencer System Clock e VXI TTLTRG e VXI ECLTRG e Front panel AUX Resolution This toggle control is used to program the pulse generator resolution to either 10 ns or 20 ns The relevant VXI plug amp play API fu
435. st Systems DRM Timing Characteristics J 1 Model T940 User Manual Publication No 980938 Rev K External AUX Output Timing Adjustments LVTTL timing reference ECL 0 ns same as LVTTL Programmable 8 ns slower 422 485 TBD TRG Input Timing Adjustments TTLTRG Bus timing reference based on the leading edge ECLTRG Bus 5 ns slower Note The TTLTRG Bus open collector recovery time is 17 ns min and increases 4 ns for each DRM installed Other VXI modules installed in the same chassis may further aggravate the recovery time leading edge for the TTLTRG Bus is a falling edge TRG Output Timing Adjustments TTLTRG Bus timing reference to the leading edge ECLTRG Bus 1 ns faster AUX Input to TRG AUX LVTTL to TTLTRG Bus 16 ns TRG Input to AUX Output TTLTRG to AUX LVTTL 15 ns LE DRS Timing Adjustments Independent timing reference Linked 1 ns VXI Local Bus 1 5 ns DRM TTLTRG Bus 1 ns DRM ECLTRG Bus 1 ns DRM External TOCLK to TOCLK In at min delay setting Independent AUX LVTTL to LVTTL 86 ns 500 MHz master clock AUX LVTTL to LVTTL 140 ns 250 MHz master clock DRM Timing Characteristics J 2 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual X 2n 86 ns X 4n 140 ns Thus n 27 master clocks x 32 ns of fixed delay Add to x Linked or VXI Local Bus adjustments Note The programmable delay can correct for this input offset External
436. static selection o None o Any Aux Input 1 of 12 Any TTLTRG Bus input 1 of 8 o Either ECL TRG Bus input 1 of 2 o Channel Test 1 master channel test Pause Test 1 2 Conditions static selection Advanced Topics 8 30 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual o High o Low o Rising Edge o Falling Edge Pause Test 1 2 Resume Sources static selection o AnyAux Input 1 of 12 o Any TTLTRG Bus input 1 of 8 o Either ECL TRG Bus input 1 of 2 o Channel Test 1 master channel test e Phase Test 1 4 Resume Sources static selection o Any Aux Input 1 of 12 o Any TTLTRG Bus input 1 of 8 o Either ECL TRG Bus input 1 of 2 o Channel Test 1 master channel test Pause Test 1 2 or Phase Test 1 4 Resume Conditions static selection o High o Low o Rising Edge o Falling Edge e Pause Resume Options settable in each Seq Step o None o Pattern Delay Timer 1 used to Resume after a fixed delay o Pattern Delay Timer 2 used to Resume after a fixed delay o Pattern Timeout Timer Pattern Delay Timeout Timer static settings o Range 20 ns to 43s o Resolution 10ns e Pause Timing Considerations o external signal used to initiate the pause must occur in a timely manner with respect to the Primary Sequencer The pause signal must be provided 10 Master Clocks and 40 60ns before the desired pausing point to be refined o Using a Phase edge to pause wil
437. t Panel Operation 5 154 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 105 Timer Counter Trigger Source Source Description None Disables the timer counter External Sets input 3 as the trigger source Internal Continuous Enables Continuous Measurements Internal Single Performs one measurement with initiate The relevant VXlplug amp play API function is e 1964 setCounterTrigger e tat964 queryCounterTrigger Initiate Generates an immediate trigger to the timer counter The relevant VXIplug amp play API function is e tat964 CounterlnitiateTrigger Results Retrieve the results of the selected counter timer function The relevant VXIplug amp play API function is e tat964 measureCounterResults PMU Panel The PMU display is accessed from the Execute gt DSx gt View gt PMU menu bar selection Es VXIO 2 INSTR PMU DSA Figure 5 85 PMU Panel Astronics Test Systems Soft Front Panel Operation 5 155 Model T940 User Manual Publication No 980938 Rev K Channel This control sets the channel number to measure The relevant VXIplug amp play API functions are e tat964 pmuMeasureVoltage Measure Voltage This control initiates a voltage measurement The relevant VXlplug amp play API function is e tat964 pmuMeasureVoltage Instrument Functions The Instrument menu bar selections allow the user to perform the following e Self test functio
438. t can be used to adjust the compensation of the external probe Note that this connection is not on the probe connector Input signal from the external probe When not used with a probe AUX1 A is a programmable level I O signal This is the buffered DUT GND and is currently not used for the external probe module Calibration output signal for the external probe Supplies compensation square wave and DC Calibration outputs When not used with a probe AUX2 A is a programmable level I O signal Supplies 12 V and 12 V to the external probe module This is a control signal from the Sequencer for support of external probe operations This is a reserved output signal that can be used for further expansion of the external probe functions This is a Probe Button input signal to the Sequencer for support of external probe operations PROBE DETECT Detects the presence of an external probe module When Astronics Test Systems UR14 Driver Receiver Board I 9 Model T940 User Manual Publication No 980938 Rev K detected the API functions for the UR14 probe are activated PROBE COMP _ Signal used to enable the probe module compensation calibration logic When not used with a probe AUX4 A is a LVTTL level 1 0 signal Programmable Driver and Receiver I O The Programmable Driver and Receiver I O Block diagram Figure H 7 illustrates Pin Electronics Driver amp Receiver features for the Programmable AUX Channels VO CONTROL Figure
439. t signals to the Data Sequencer from the programmable input receivers 0 Good 1 1 Good 0 Controls isolation relays This is the Bi directional programmable I O channel from the DR4 Drivers and Receivers to the UUT Real time temperature monitors the PCB junction plane Driver Bias Power from the Programmable Regulators Auxiliary Driver amp Receiver I O Figure E 3 illustrates the configuration and control of the AUXA 1 8 and the AUXB 1 8 Driver amp Receiver I Os AUXA EN 1 8 AUXA DATA 1 8 ps 74 125 AUXA RH 1 8 74LVT125 74 125 R not installed R not installed R not installed R not installed Optional Termination Configuration 0603 pads AUXA 1 8 Optional Termination Configuration 0603 pads AUXB 1 8 Figure E 3 Auxiliary Driver amp Receiver Block Diagram Astronics Test Systems DR4 Driver Receiver Board E 5 Model T940 User Manual Signal Descriptions AUXA EN 5 8 AUXA DATA 1 8 AUXA RH 1 8 AUXA 1 8 AUXB EN 1 8 AUXB DATA 1 8 AUXB RH 1 8 AUXB 1 8 Publication No 980938 Rev K Auxiliary Enable outputs from the Data Sequencer to the TTL output buffers Auxiliary Data outputs from the Data Sequencer to the TTL output buffers Auxiliary Response High inputs to the Data Sequencer from the TTL input buffers Eight TTL signals used to input or output test signals Auxiliary Enable outputs from the Data Sequencer
440. ta Display the error address data from the previous sequence execution Probe Data Display the error address data from the previous sequence execution Save Results This command button will display a file save panel that allows the user to select and existing file or create a file to store the result data as a comma separated list csv All numeric values are displayed as decimal CRC Save File Format The CRC results are saved in the following format Astronics Test Systems Soft Front Panel Operation 5 129 Model T940 User Manual Publication No 980938 Rev K lt id gt lt crc gt lt lf gt Where lt id gt 01 through CH32 PGO and PG1 crc The CRC value Error Address Save File Format The Error Address results are saved in the following format header line feed step offset pma data gt lt line feed Where header STEP OFFSET PMA RECORD DATA step Step number of the error offset Pattern number pma Pattern Memory Address data Record memory Record Index Save File Format The Record Index results are saved in the following format lt header gt lt line feed lt step gt lt offset gt lt line feed Where lt gt STEP OFFSET step Step number of the error offset Record memory offset where the results are saved Record Data Save File Format The Record Data results are saved in the following format lt header
441. te Function Select Start and End Channels and Measurement Delay Equipment Basic Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 Use the Start and End Channel fields to select the and Auxiliary channels to be calibrated 3 The minimum measurement delay for this calibration is 200 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hit the Continue button when the required temperature is reached If the temperature reaches 80 C the process continues automatically Astronics Test Systems Programmable Channel Calibration 6 9 Model T940 User Manual Publication No 980938 Rev K Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution 2 Review the results in the Status window 3 Optional Verify the results using the Verify button Ensure that all channels pass verification 4 Optional Check the individual gain and offset values in the field controls Verify that all offsets are near zero and that all gains are near unity 1 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the Update button If this step is omitted
442. ted below e Agilent Technologies Agilent VEE e Astronics Test Systems PAWS e Microsoft Visual Studio Visual Basic C Visual C Visual C National Instruments LabVIEW e National Instruments LabWindows CVI Installation 2 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Included with the instrument driver is the Soft Front Panel SFP software The soft front panel is a graphical user interface for the DRM It can be used to verify communications and to debug applications during development and integration The DRM VXlplug amp play Instrument Driver uses the VISA communication library to operate the instrument The VISA library is typically provided by the manufacturer of the VXI Slot 0 device Contact your Slot 0 device manufacturer if you do not have the VISA library installed on your system Installing the Instrument Driver 1 Insert the included documentation CD into your computer s CD DVD drive 2 There are two versions of the driver installer on the CD one with the Run Time Engine RTE and one without e The installer with the RTE is in the Driver with RTE folder e The installer without the RTE is in the Driver without RTE folder 3 Double click the setup exe file 4 Follow the setup directions After the instrument driver is installed the DRM soft front panel will be launched The following files are installed from the CD e ANSI C source code for the Instrument Driver and
443. the Idle Standby state After the execution of a sequence burst the sequencer will enter the Idle Standby state The user can define the Idle Standby state timing and pattern such that UUT stimulus can be maintained between pattern bursts A single pattern can be specified so that the pattern memory can be updated Standby or a group of patterns can be specified Idle during this state The user can disable the timing set phases windows during the Idle Standby state by setting Assert Return and Open Close values to zero Editing the Patterns Patterns are the memory element that contains the instructions for each channel during a sequence burst These instructions called pattern codes define whether a channel will drive high drive low test high etc Once a sequence step has been initialized a pattern set is assigned to the step A Pattern Set is one or more patterns A Pattern is the pattern codes for all the channels that will be applied at the same time See Patterns in Chapter 5 Access this panel from the menu bar Edit Data Sequencer x Patterns Where is the sequencer you wish to configure Astronics Test Systems Soft Front Panel Operation 5 77 Model T940 User Manual Publication No 980938 Rev K Figure 5 41 Edit Patterns Panel This panel lists all the defined pattern sets The associated step number size and offset are displayed The size of a pattern set can be from 1 to 262144 The offset ca
444. the calibration factors will revert at the next power cycle Goce TET Driver Receiver Calibrate Function Serial Number DRA Monitor ADC 12060853 7 DRB Stat Chan 2 1 Meas Delay 0 200 End Channel 24 Channel 21 Offset ae 4 0 00706 4 0 99616 me se ver Sort Update section Ore Programmable Channel Calibration 6 10 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Source Sink Load For DR3E DRY and UR14 only the Source Sink Load calibration is used to measure the reference resistor used to calibrate the Isource Isink and IAL IAH levels The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the Source Sink Load menu item on the Calibrate Function menu 2 Verify that the Source Sink Load calibrate function is now in focus Calibrate Function Run Calibration Equipment Digital multimeter connected to DRA or DRB if installed via the EXTERNAL FORCE input Astronics Test Systems Programmable Channel Calibration 6 11 Model T940 User Manual Publication No 980938 Rev K EXT FORCE A Calibration Adapter Installed in J200 Figure 6 4 T940 DR3e DR3e Connection Diagram Xt QJ EXT FORCE B Calibration Adapter Installed JBA
445. the following properties The location of the Data to be output and the number of Patterns to be output The timing to be used for the Stim Resp Data TOCLK period phase and window timing The Clocks per Pattern CPP to be used for each Pattern in this Sequence Step the Clocks per Pattern may be from 1 to 256 Waveform selection control 4 bits and Waveform Table to use 1 of 256 The Phase Trigger Type for each Phase Pattern or System Clock 4 bits This is applicable when CPP is greater than 1 Sequence Flag state 2 Pattern Control Instructions One or more Sequence Steps may be designated as a Subroutine The Pattern Control Instructions handle looping branching etc Advanced Topics 8 34 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Pattern Control Instructions The Pattern Controller defines the following e Jump Test conditions 4 bits e Jump Sequence Address 12 bits e Loop count 16 bits e Loop counter to use 4 b e Control bits 1 bit each o LSTSEQ Last Seq Step in the Primary Seq o 1 Counted Loop SUBRT Subroutine Jump its o RTN Return used on the last Seq Step of a Subroutine o VJ Vector Jump o Continue accumulating Seq Timeout Time e Pause Test Conditions used for Handshaking and other purposes 4 bits e Pause Resume Options used for Pattern Delay and Pattern Timeout 2bits e Record Capture Type 2 bits The first
446. the vector table signal consists of the following 1 Select the Vector Bit Index 2 Select the Vector Jump Step 3 Program the Timing Set only used in the indexed timing mode Soft Front Panel Operation 5 96 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual VXIO 2 INSTR Edit DSA V EHI Vector Bit Index Vector Jump Step Figure 5 54 Edit Vector Table Panel Vector Bit Index This allows the user to enter the index to program There are 16 indexes that can be set 0 to 15 The index is the binary value of the vector bits VAO through VA3 The relevant VXlplug amp play API function is e tat964 setVectorJumpTable Vector Jump Step This allows the user to enter the jump step number for the current vector jump index The relevant VXlplug amp play API function is e tat964 setVectorJumpTable Timing Set When the timing mode is set to indexed this control allows the user to specify the timing set for the current vector jump index The relevant VXIplug amp play function is e tat964 setVectorJumpTable Set Channel Test This command button displays the Edit Channel Test panel so the channel test settings can be programmed for the selected sequencer Configuring the sequence channel test registers consists of the following 1 Program the expect value 2 Program the mask value The expect value is compared to the response high Good 1 of the input channel A high in the mas
447. tion No 980938 Rev K configuration and control of the OPEN COLLECTOR utility channel I O on the UR14 e ADC VOLTAGE amp TEMPERATURE MONITORING block diagram illustrates the Power and Temperature amp control features for the PROGRAMMABLE AUX Channels as well as the voltage reference generation used for the OPEN COLLECTOR I O e CONTROL LOGIC This control logic provides facilitates UR14 functions including access to the Pin Electronics devices Temperature Monitoring programming Voltage Over voltage and Over Temperature detection e FIRMWARE amp NV DATA The UR14 Control Logic FPGA firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility UR14 calibration data is stored in an on board EEPROM and is loaded initialization of the T940 unit UR14 power on time is stored for reference using an on board timer Auxiliary Driver and Receiver ECL LVTTL The Auxiliary Driver and Receiver ECL LVTTL block diagram Figure H 3 illustrates the configuration and control of Auxiliary ECL amp LVTTL Driver amp Receivers on the UR14 AUX AUX DATA3A 74LVT125 AUX RH3A AUX RH 9 12 A MC100ELT2 AUX DATA 9 12 A gt AUX 9 12 AUX 5 8 AUX 5 8 gt B 7ALVT125 7ALVT125 AUX RH 5 8 A CONTROL Figure 1 3 Auxiliary AUX3 A amp AUX 5 12 A LVTTL amp DIFF ECL I O It is important to note that t
448. tion Results DSA L ul View Errors Addres Figure 5 70 View Errors Address Panel The error address memory records the sequence step and pattern address of the first 1024 errors of a sequence execution and is displayed in the Step and Addr columns The Pattern column is calculated based on the Record Type setting and Record column is read from the record memory The relevant VXlplug amp play function for Step and Addr data is e tat964 queryErrorAddress The relevant VXlIplug amp play function for Record data is e tat964 queryRecoraData The relevant VXlIplug amp play function for Pattern data is e tat964 queryPatternSet if Record Type set to Normal e tat964 if Record Type set to Indexed The View menu selection allows the address column of the error address panel to toggle between decimal and hexadecimal Soft Front Panel Operation 5 132 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Figure 5 72 View Errors Address Panel Hex Record Index Display The record index memory display is accessed from the Execute gt DSx View gt Results menu bar selection and setting the View control to Record Index Where x is the sequencer you wish to query The record index memory stores the sequence step and pattern index of the first 1024 steps of a sequence execution When the record type is set to indexed the sequence res
449. tional Probe Button Input MPSIG B 15 Output Multi purpose Signal MONITOR B 17 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time EXTFORCE B 19 Input External Force routed to all of the Pin Electronics devices GND 2 20 Ground Even Calibration Driver Receiver boards are calibrated using the following settings prior to shipment 15V to 17 V Voltage Mode Power Converter 12 to 12 e 7 V to 24 V Voltage Mode Power Converter 5 to 15 DAC Basic Factory stored in EEPROM Driver channel deskew Factory stored in EEPROM ADC Monitor Field upgradable stored in EEPROM DVH DVL Field upgradable stored in EEPROM CVH CVL Field upgradable stored in EEPROM Vcom High Vcom Low Field upgradable stored in EEPROM Isource Isink Field upgradable stored in EEPROM IAL IAH Field upgradable stored in EEPROM Inter module timing deskew Static End of cable deskew Static UR14 Driver Receiver Board 1 34 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Appendix J DRM Timing Characteristics Introduction The timing characteristics of the DRM are important when external input signals are used to alter normal internal operation of the Sequencer Similarly the Sequencer can also output signals for use by other instruments The timing of these outputs may be important to the user Some of these timing characteristics
450. tor Output Sync Output Frequency Synthesizer Output Gro ore Timing Set Output Signals a Phase b Window c TO CLK d Pattern Clock 10 Sequencer Status Outputs a ldle Active b Sequence Active c Sequence Flag d Pass Fail e Error 11 Numerous Factory Test Outputs Table 5 64 DRn AUX Configuration Driver Receiver AUX1 AUX4 AUX5 AUX9 Board AUX8 AUX12 DR1 LVTTL LVTTL ECL DR2 LVDS LVTTL ECL DR3E Programmable LVTTL ECL DR4 TTL TTL Not Installed DR7 RS422 485 LVTTL ECL DR8 TTL TTL ECL DR9 Not installed LVTTL Not Installed Table 5 65 UR14 AUX Configuration Signal Logic Special Use AUX1 A AUX2 A Programmable Used for probe input AUX1 and probe cal AUX2 AUX3 A AUXA A LVTTL AUXA used for probe compensation AUX5 A LVTTL Shares front panel pin with AUX9 A Astronics Test Systems Soft Front Panel Operation 5 67 Model T940 User Manual Publication No 980938 Rev K Signal Logic Special Use AUX6 A LVTTL Shares front panel pin with AUX10 A AUX7 A LVTTL Shares front panel pin with AUX11 A AUX8 A LVTTL Shares front panel pin with AUX12 A AUX9 A ECL differential or bipolar Shares front panel pin with AUX5 A AUX10A ECL differential or bipolar Shares front panel pin with AUX6 A AUX11A ECL differential or bipolar Shares front panel pin with AUX7 A AUX12A ECL differential or bipolar Shares front panel pin
451. tput driver coincides with the phase immediately after an update Note The last five settings above will only go to the new output state if the Channels drivers are enabled and power is applied See Channel Driver and V V in the Execute Panel Modes and Settings section of this chapter The relevant VXI plug amp play API function is e tat964_setChannelParameters Capture Signal This pull down control programs the selected channel s capture signal The selections for this pull down control are Soft Front Panel Operation 5 56 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Table 5 57 Capture Signal Settings Setting Description Window 1 Use Window 1 timing signal to control input comparator timing Window 2 Use Window 2 timing signal to control input comparator timing Window 3 Use Window 3 timing signal to control input comparator timing Window 4 Use Window 4 timing signal to control input comparator timing The relevant VXlplug amp play API function is e iat964 setChannelParameters Capture Mode This pull down control programs the selected channel s capture mode The selections for this pull down control are Table 5 58 Capture Mode Settings Setting Description Masked Disables the channel error test Open Edge Channel error test and data capture performed on the Open edge of the window Close Edge Channel error test and data
452. tronics Test Systems Inc 4 Goodyear St Irvine CA 92618 Phone Numbers Voice 800 722 2528 Fax 949 859 7139 Electronic Mail Figure 5 5 Company Information Panel Active LED The Active LED indicates whether a VXI session has been established successfully Chassis Data The chassis data control indicates the slot position and logical address of the DRM that the SFP is connected to Module Data The module data is displayed in four separate controls The module data is stored in non volatile memory Title Bar The title bar will display the current project file Soft Front Panel Operation 5 4 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual SFP Main Panel Menu Bar The SFP main panel menu bar provides access to select program and save the DRM hardware Relevant VXIplug amp play API functions are included with the menu options Bis TOXX DRM File Config Edit Execute Instrument Help Figure 5 6 Menu Bar File Menu File Config Edit Execute Instrument Help New Open Save Ctrl N Ctrl O Ctrl S Save As Load Hex File 964 T940 LAUR Run Command Script Active Dump DRA Register Data Dump DRB Register Data Load DRA Calibration Load DRB Calibration Load DRM Data 1 c Users Public Documents DSAwalk1 cfg Close Figure 5 7 File Menu The File Menu is used to manage the loading and saving of test files With this menu DRM SFP proj
453. tronics Test Systems UR14 Driver Receiver Board 1 19 Model T940 User Manual Publication No 980938 Rev K Description Notes AUX1 A and AUX2 A are 50 ohm coax Probe When used with the external probe module these are dedicated I O ProbeMaster PN 853 068 00 100 MHz probe PM6139 Probe Module Interfaces to the UR14 J1A 26 Pin connector Secures power 12 from the UR14 PolyFuse current limited Provides contact detect through the probe tip Details below Supports Probe Handle pushbutton and Footswitch signaling through the D R board to the Digital Board to initiate or resume a burst and deactivate the contact detect circuitry The Sequencer handles the sequencing once the pushbutton signal is received Footswitch signaling simply requires tapping into the Probe Aux connector Supports dual threshold detection Via the UR14 AUX1 A input Utilizes Window 4 for Probe Data capturing Detectable states 34 Implemented in the T940 DB Sequencer see relevant manual section Provided in the T940 DB Sequencer Provides Capture Learn and Expect Compare of Probe input Provided in the T940 DB Sequencer Provides dual level CRC CRC16 and pre load of 1 s Provided in the T940 DB Sequencer UR14 Characteristics UTILITY CHANNELS Table 1 2 Utility Channel Characteristics Description Characteristics Digital I O Type Bi directional 32 Open
454. ts and resumes the sequence The relevant VXlplug amp play API function is e tat964 setProbeConfiguration Probe Button Level This control sets the active level of the probe button Setting options e Active Low e Active High The relevant VXIplug amp play API function is e tat964 setProbeConfiguration Probe Input Connect This control opens and closes the probe input channel connect relay The probe input is routed through AUX1 A on the UR14 Driver Receiver board The relevant VXlplug amp play function is e iat964 setProbeConnect Probe Input Compare High and Low These two controls set the probe input high and low comparator levels The Astronics Test Systems Soft Front Panel Operation 5 47 Model T940 User Manual Publication No 980938 Rev K probe input is routed through AUX1 A on the UR14 Driver Receiver board The relevant VXlIplug amp play function is e tat964_setProbeLevels Probe Cal Connect This control opens and closes the probe calibration channel connect relay The probe calibration is routed through AUX2 A on the UR14 Driver Receiver board The relevant VXlIplug amp play API function is iat964 setProbeConnect Probe Cal Signal This pull down control programs the probe calibration signal source The selections for this pull down control are Table 5 48 Probe Cal Signal Settings Setting Description AUX2 Calibration signal sourced by AUX2 programmable dri
455. ts from the Data Sequencer to the ECL output buffers CONTROL Signals used to control isolation relays and ECL bipolar differential mode AUX 5 8 Four LVTTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 VBB ECL input threshold 1 3V AUX 9 12 Four negative differential signals used to input or output test signals See Configuring the AUX Channels in Astronics Test Systems DR1 Driver Receiver Board B 3 Model T940 User Manual Publication No 980938 Rev K Chapter 5 AUX 9 12 Four bipolar positive differential signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 DR1 Driver amp Receiver Figure B 3 illustrates the configuration and control of the DR1 Driver amp Receiver LVTTL Figure B 3 DR1 Driver amp Receiver Block Diagram Signal Descriptions DATA Channel and auxiliary data output signals from the Data Sequencer to the LVTTL output drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the LVTTL output drivers RH Response High input signals to the Data Sequencer from the LVTTL input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the LVTTL input receivers 0 good 0 1 good 1 AUX 1 4 Four LVTTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 CH 1 32 These
456. tting Description Disable Do not use pass valid signal Enable Use pass valid signal The relevant VXlplug amp play API function is e iat964 setPassFailParameters Soft Front Panel Operation 5 42 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Over Current This command button displays the Over Current panel so the over current parameters can be programmed for the selected sequencer The over current mode should be used for channels configured in the static mode only It should not be used for channels configured in dynamic mode because of the long recovery delay from over current transients due to data transitions Use Drive Fault to detect an over current for channels configured as dynamic Figure 5 26 Over Current Panel Channel and Global Disable The DR3e DR4 DRY and UR14 programmable drivers generate an over current signal that is monitored Setting the Channel Disable control to On will cause the channel or channels which have an over current event to be disabled Setting the Global Disable control to On causes all of the channels on the Driver Receiver board to be disabled whenever any channel has an over current event If Driver Disable is coupled between DRMs via the TTL or ECL Trigger bus or coupled between sequencers on the Linked Trigger Bus then all the channels in the DRS and or Linked sequencers will be disabled The relevant VXIplug amp play API functions is iat964
457. turn Seq and clear the IN SUB flag Otherwise if LC gt 0 0 and INSUB jump to the return Seq and clear the INSUB flag Otherwise the Seq loops or finishes also set a fault flag T964 VXI Backplane Trigger Bus Trigger Bus description Trigger Bus Applications TTLTRG Bus 8 VXI backplane signals normally active low ECLTRG Bus 2 VXI backplane signals normally active high Inter module communications for Sequencers configured in Master Slave configuration Communicating a Trigger for a Conditional Jump Error with or w o Pass Valid Channel Test Communicating a Synchronization Signal from the Primary Sequencer that all the coupled Synchronizers can check themselves against Communicating a Sequence Reset to all coupled sequencers primarily used for re synchronizing coupled Sequencers Communicating a Master Reset to all coupled sequencers Communicating a Driver Disable to all coupled sequencers that can disable all the channel drivers at once Advanced Topics 8 42 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual e Receive a signal from another instrument in the VXI chassis needs to go to the T940 Primary Sequencer o External Start and or Stop o External Jump o External Halt Pause or Resume e Trigger another instrument in the VXI chassis Possible signal choices within the T940 are A sync pulse A Seq Flag An Aux Input Idle Active Se
458. typ 10 5 V MTBF ground benign T940 180 885 hours Dimensions Single slot size VXI module 30 x 260 x 350 mm EMC Council Directive 89 336 EEC Emission EN61326 1 2006 Class A Immunity EN61326 1 2006 Table 1 Designed to Meet Testing in Progress Safety Low Voltage Directive 73 23 EEC BS EN61010 1 2010 Designed to Meet Testing in Progress Fora DRM with 2 DR3e modules the 1263 chassis only has sufficient airflow for 25 C max inlet air temperature at lt 2000 ft Astronics Test Systems Specifications 7 11 Model T940 User Manual Publication No 980938 Rev K This page was left intentionally blank Specifications 7 12 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Chapter 8 Advanced Topics This section describes advanced topics of the T940 giving more details than what were provided in previous chapters Because references are made to DRS configurations relevant API and ARI calls are both provided here The topics covered include e Jumping Halting Counting and Logging on Pass Fail e Understanding Record Offset e Pause and Halt e Sequencer Operation Details e VXI Backplane Trigger Bus Jumping Halting Counting and Logging on Pass Fail Conditions The T940 has extensive capability when it comes to Jumping or Halting on various Pass Fail conditions in both Pipelined and non Pipelined modes The count
459. ual Publication No 980938 Rev K pattern code affects the driver comparator Table 5 72 Pattern Codes Pattern Code Driver Comparator Invert Code Expect Mode Level Disable Channel Z Off X None Disable Channel z Collect CRC C Off X Enable CRC Collect CRC C Drive High 1 On DVH None Drive Low 0 Drive Low 0 On DVL None Drive High 1 Repeat Previous Code Repeats the last non repeat invert code R Invert Previous Code l Inverts the last non repeat invert code Refer to Invert Code _ Lt l COlmnofthistabe Expect Valid Low L Off X CVL Expect Valid High H Expect Valid High H Off X CVH Expect Valid Low Expect Valid V Off X CVL or CVH Expect Between B Expect Between B Off X gt CVL and lt CVH Expect Valid V Drive Low Expect Low On DVL lt CVL Drive High Expect T High h Drive High Expect High On DVH gt CVH Drive Low Expect h Low 7 Drive Low Expect High On DVL CVH Drive High Expect T Low V Drive High Expect Low On DVH CVL Drive Low Expect y High The relevant VXIplug amp play API functions are tat964_setPatternData e tat964 setPatternTestEnable e tat964 setProbeExpectData The pattern data can be imported exported using the File menu bar selection Bi VXIO 2 1NSTR Edit DSA Pattern Set Step 1 D arms Import File Export File Figure 5 4
460. uired Frequency System Clock source set the to For the purpose of having a self test Synthesizer the internal frequency synthesizer signal The relevant VXlplug amp play API function is e tat964 setSystemClockSource External Mode This pull down control selects the clock edge mode when the System Clock source is set to any non TOCLK selection The selections for this pull down control are Table 5 23 External Mode Settings Setting Description Rising Edge Use the rising edge of the external signal as the active edge Falling Edge Use the falling edge of the external signal as the active edge Both Edges Use the rising and falling edge of the external signal as the active edge Divide by2 Divide the external signal by two and use the rising edge as the active Rising Edge edge Divide by2 Divide the external signal by two and use the falling edge as the active Falling Edge edge Soft Front Panel Operation 5 26 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API function is e tat964 setSystemClockParameters External Offset This control is used to specify the external System Clock offset in order to align the clock data relationship The valid offset range is from 0 to 65534 even numbers only and the resolution is 1 2 the MCLK period For example if the MCLK is set to 100 MHz then the resolution is 5 ns
461. ult A Valid Pass for a given pattern occurs if there is at least one channel with an Expect and a Window Capture Mode an Open Edge Close Edge or Window but it does not verify that there is an appropriate window programmed to occur during the period A Capture Fault Event occurs if there was an Expect without an appropriate Capture Mode i e a Capture Mode of none or an Expect and a Capture Mode but without appropriate Window edges within the Pattern period Capture Faults automatically generate an Error for that Pattern The channel s with a Capture Fault can be queried which may help narrow down where the Capture Fault occurred Note Whereas a Valid Pass only requires one channel with an Expect and Capture Mode a Capture Fault is generated for every channel that has an Expect with neither a Capture Mode nor an appropriate Window edge s Additional Halt Information Halt modes are shown on the Execute panel The relevant VXIplug amp play and ARI functions e API tat964 setHaltMode e ARI AssignPtgHaltMode Advanced Topics 8 24 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual E vazas c a Ide 2 Active Halt Pause VaN Start Burst Error Errors Channel Drivers On RUE 3 0 Enabled Y Power Converter Alert 2 Execute Idle Step 30 gt D R Alet Q Burst v 1 Disable v Finish Mode Step Disable Standby Y 0 Pattem Step
462. ults are stored sequentially in the record memory starting at offset 0 The record index memory allows the user to determine sequence step order that filled the record memory Astronics Test Systems Soft Front Panel Operation 5 133 Model T940 User Manual Publication No 980938 Rev K Figure 5 73 Record Index Panel The relevant VXlIplug amp play API function is e tat964 queryRecordlndex Record Data Display The record memory display is accessed from the Execute gt DSx gt View gt Results menu bar selection and setting the View control to Record Data Where x is the sequencer you wish to query Soft Front Panel Operation 5 134 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual pad VXIO 2 INSTR Execution Results DSA Figure 5 74 View Record Data Panel The Record Data contains either the error or response results from the previous sequence burst see Step Record Mode in Chapter 5 The least significant bit of the record data in hex represents the error response for channel 1 and the most significant bit represents channel 32 Error data stores a 1 to indicate a channel did not match its programmed expect value and a 0 indicates no error Response data stores a 1 to indicate a high level and a 0 to indicate a low level The compare level used for recoding response data is set by the Raw Record Basis see Raw Record Basis in Chapter 5 Note If there is a Capture Fault on a channel f
463. und reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements A buffered version also comes out the Front Panel External Force is an analog I O signal which is connected to all of the Pin Electronics devices and can be used to force a level on the output of the driver It may also be used to monitor a channel s state EXTFORCE is also used for calibration Real time over voltage detector circuit monitors Driver and Receivers to protect the pin electronics Also clamps the inputs to the V rails DR3e only Real time temperature monitors for the pin electronics The control logic contains the registers memory and logic that allow the digital board to interface and configure the hardware See Figure D 4 Astronics Test Systems DR3e Driver Receiver Board D 5 Model T940 User Manual Publication No 980938 Rev K CBUS ER INTERRUPT CONTROL MONITOR V OVERVOLT POWER MONITOR EXTFORCE REFERENCES ____ EXTSENSE REFERENCES EXTSENSE TEMPERATURE MONITORS Figure D 4 DR3e Control Logic Block Diagram Signal Descriptions MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digital board to the Driver Receiver board INTERRUPT Real time signal generated from the power and temperature monitor data Positive bias power required for operation of the Pin Electronics devices from the T
464. upgradeable using our supplied loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions CONTROL DR9 Characteristics Signals used to program firmware and NV DATA Table H 1 DR9 Characteristics Description Characteristics Digital I O Type Variable Voltage Digital Channels Analog Channels 24 SE or 12 DIFF per Driver Receiver board 48 per VXI slot Per channel relay isolation 24 Analog Connections per Driver Receiver Board 48 per VXI slot Output Voltage Ranges 15 V to 417 V VMO Selectable Sequencer 7 V to 24 V VM1 Output Voltage Swing 500 mV 1 to 24 V DRO9 Driver Receiver Board H 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Description Characteristics Output Resolution 5mV Output Accuracy DVH and DVL 50mV 1 of PV Slow Default Medium slew settings t 75mV 196 of PV Fast slew setting Output Drive Current Output Impedance Selectable Channel 85 mA typical Source Sink Direct 12 or Series 50 x4 Q Slew Rate Selectable Channel or custom 0 25 V ns 0 7 V ns 1 0 V ns or 1 3 V ns typical Input Threshold Ranges 14 75 V to 14 V VMO 6 75 V to 21 V VM1 Input Threshold Resolution Input Threshold Accuracy CVH and CVL 5mV 50mV 1 of PV Skew Chan to Chan 3
465. ure 3 5 LBUS Lockout Configuration essere rennen 3 5 Figure 4 1 T940 DRM Block 4 1 Figure 4 2 T940 VXI Bridge Block 4 2 Figure 4 3 T940 Inter Module Control Block 4 4 Figure 4 4 Data Sequencer Block 4 10 Figure 4 5 Sequencer Logic Block Diagram eese 4 13 Fig re 5 1 Reset Screen onec eere ehe pb ea da haath esu Re doe bene dte dede 5 2 Figure 5 2 I nitlalize Warning ite oe t ean dta b Ra taux 5 2 Figure 5 3 Mairi Panel etti baee ERA eue eu Praese 5 3 Fig re 5 4 Main Panel URT4 ee nte ite 5 3 Figure 5 5 Company Information Panel sss ener nnne 5 4 Figure 5 6 Men Bar oto diat dod o e sed aie Red ds dba fibra ecd 5 5 Figure 5 7 File Men iiss isis atest err et em redde en 5 5 igure 5 8 Conflg Men s e a e ER err 5 6 Figure 5 9 Edit Menu pida eet RUE dee ke Reed Pug E Ro n t E Ru deed 5 7 Figure 5 10 Execute Mentoren eene eec e edente e done iia a dogs 5 7 Figure 5 11 Instrument 5 8 Figure 5 12 FHelp Menu ient tatit ni te tie RH hoe nette a rude 5 8 Figure 5 13 About DR
466. urpose ECL I O pin 51 1 Ohm to 2V AUX11 A 92 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V AUX11 A 93 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V AUX12 A 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V Astronics Test Systems DR1 Driver Receiver Board B 7 Model T940 User Manual Publication No 980938 Rev K Name Pin No Description AUX12 A 95 Bi directional General Purpose ECL I O 51 1 Ohm to 2V 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output BCLK A 96 Output Reserved Table B 4 DR1 Pinout by Pin Number DRA Pin No Signal Pin No Signal 1 SIG GND 51 SIG GND 2 CH1 52 CH17 3 SIG GND 53 SIG_GND 4 CH2 54 CH18 5 SIG_GND 55 SIG_GND 6 CH3 56 CH19 7 SIG_GND 57 SIG_GND 8 CH4 58 CH20 9 SIG_GND 59 SIG_GND 10 CH5 60 21 11 SIG GND 61 SIG GND 12 CH6 62 CH22 13 SIG GND 63 SIG GND 14 CH7 64 CH23 15 SIG GND 65 SIG GND 16 CH8 66 CH24 17 SIG GND 67 SIG GND 18 CH9 68 CH25 19 SIG GND 69 SIG GND 20 CH10 70 CH26 21 SIG GND 71 SIG GND 22 11 72 27 23 SIG GND 73 SIG GND 24 CH12 74 CH28 25 SIG GND 75 SIG GND 26 CH13 76 CH29 27 SIG_GND 77 SIG GND 28 CH14 78 CH30 29 SIG GND 79 SIG GND 30 CH15 80 CH31 31
467. uxChannelSelect API Input Bus Select selections can select any of the AUX TTL or ECL trigger Local Trigger Bus or Channel Test 1 using the tat964 setAuxInputBusSelect API The relevant VXlIplug amp play API function is e tat964 setAuxOutputSignal Input Bus Source This control is visible when the Source control is set to one of the four Input Bus Select signals It selects the source for the seleced input bus select Table 5 68 Input Bus Select Source Settings Setting Description AUX1 Good 0 Source set to AUX1 Good zero signal AUX1 12 Good 1 Source set to AUXn Good one signal CHT1 Source set to channel test 1 Soft Front Panel Operation 5 70 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Setting Description ECLTRGO 1 Source set to VXI ECL trigger TTLTRGO 7 Source set to VXI TTL trigger LTBO 7 Source set to Linked Trigger bus signal Connect State This control allows the user to open or close the isolation relay DR2 DR7 Driver Receiver boards do not have isolation relays The relevant VXlIplug amp play function is iat964 setAuxConnect Note DR2 and DR7 Driver Receiver boards do not have relay isolation Properties Programmable Logic This command button displays the panel to allow the user to configure the Programmable AUX Driver Receiver settings Refer to Configure Channel Properties earlier in this cha
468. v K COUPLED pettosocscscscsosccccoscccscccoccccoscsesososccocoocccsccosccccosccocccocccccosceccecocooo gee E P Ee ed YE a ON DRM1 PRI 3 DSB LINKED DSA D e DRM2 SEC DSB DSA 193 256 129 192 CH 65 128 1 64 In this example all 12 sequencers DSA and DSB on DRM1 through DRM6 are coupled to a single DRS 368 channels Three Groups of 128 Channels Module T940 Configuration M1 Primary Linked M2 Terminator DSA and DSB Coupled M3 Primary Linked M4 Terminator DSA and DSB Coupled M5 Primary Linked M6 Terminator DSA and DSB Coupled Functional Description 4 8 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual COUPLED escsceocccccccccccccoceoo DRM3 E 4 DRM2 DRM1 eH 321 384 CH257 320 icH 193 256 CH 129 192 E t CH 65 128 CH 1 64 In this example DSA and DSB on DRM1 and DRM2 are coupled to DRS 128 channels DSA and DSB on DRM3 and DRM4 are coupled to a second DRS 128 channels DSA and DSB on DRM5 and DRM6 are coupled to a third DRS 128 channels Two Groups of 128 Channels One Group of 64 Channels and Two Groups of 32 Channels Module T940 Configuration M1 Primary Linked M2 Terminator DSA and DSB Coupled M3 Primary Linked M4 Terminator DSA and DSB Coupled M5 Secondary Linked M6 Terminator Not Linked
469. ver 10V Calibration signal sourced from internal 10V reference 5V Calibration signal sourced from internal 5V reference GND Calibration signal tied to ground 5V Calibration signal sourced from internal 5V reference 10V Calibration signal sourced from internal 10V reference The relevant VXI plug amp play API function is e tat964 setProbeCalSignal Probe Output Connect This control opens and closes the probe output channel connect relay The probe output is routed through PROBE OUT signal on the UR14 Driver Receiver board The relevant VXIplug amp play function is iat964 setProbeConnect Compensation This control initiates a compensation calibration The user is prompted to connect the probe to the calibration BNC Soft Front Panel Operation 5 48 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual Connect probe to calibration BNC L The user is then prompted to adjust the probe compensation screw until the probe module LED labeled D1 illuminates 59 Adjust probe compensation screw on probe until LED on probe module D1 illuminates The relevant VXIplug amp play function is e tat964 probeCalibration DC Cal This control initiates a DC level calibration The user is prompted to connect the probe to the calibration BNC BS Probe Calibration n Connect probe to calibration BNC After calibration has been perfomed the user is prompted to u
470. ver board V V and Front Panel DUT Hybrid Connection per Driver Receiver board Connects Front Panel pin to any channel via the Pin Driver electronics User must disable the drive enabled to the channel 40 series impedance 3 MHz bandwidth per channel Hybrid Channel Relay Connection Connects pin to the Hybrid channel pin 5 ms connection latency for Break Before Make operation per channel Hybrid Channel Relay Isolation Hybrid Channel Relay Connection 200 V Adjacent Channels must be gt 0 V for 200 V or lt 0 V or below for 200 V 32 db 200 MHz 29 db 100 MHz Hybrid Channel Relay Insertion Loss Insertion loss 0 40 db 200 MHz Insertion loss 0 15 db 100 MHz Auxiliary Channels per Driver Receiver board LVTTL 4 fixed 50 series terminations for calibration support This range is limited by the Power Converter range selected 1 700 mV at the fastest slew rate O Min Max Levels The I O level minimum and maximum values are determined by the V and V bias voltage levels The following table lists the min and max levels based on the V and V level Table H 2 DR9 I O Min Max Levels Front Panel Level Min Max Units DVH V 5 V 3 V DVL V 4 V 7 V CVH V 2 V 7 V CVL V 2 V 7 V Vcom High CMH V 2 V 7 V Vcom Low CML V 2 V 7 V DR9 Driver Receiver Board H 10
471. vironmental Teniparature Operating 0 C to 45 C Storage 40 C to 70 0 C to 10 C Not controlled Humidity 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 596 to 7596 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 Rise 1 DR9 Cooling Required 10 C Rise 2 DR9s Typ 8 0 lps 1 1 mmH 0 Max 10 3 Ips 1 5 mmH 0 Max 19 5 los 4 6 mmH 0 Typ 13 lps 2 2 mmH 0 Front Panel Current Requirements channels unloaded per DR3 V 3 8 A max 2 9 A typ 21 5 V V 4 3 3 4 A typ 10 5 V DR9 145 933 hours T940 180 885 hours MTBF ground benign Power Converter 540 040 hours T940 DR9 70 261 hours T940 DR9 DR9 47 427 hours Dimensions 23 x 114 x 294 mm EMC Council Directive 89 336 EEC Emission EN61326 1 2006 Class A Immunity EN61326 1 2006 Table 1 Designed to Meet Testing in Progress 73 23 DR9 Driver Receiver Board H 12 Safety Low Voltage Directive Designed to Meet Testing in Progress BS EN61010 1 2010 Astronics Test Systems Publication No 980938 Rev K DR9 Signal Description J3B J3A n oo J2B 2
472. with AUX8 A AUX1 B AUX4 B Programmable General purpose AUX5 B AUX8 B LVTTL Bipolar ECL General purpose selectable AUX9 B AUX12 B ECL differential or bipolar General purpose Configuring the AUX UAUX Signals Configuring the AUX UAUX signal is done by double clicking the left mouse button on the signal name corresponding to the desired AUX number Refer to the specific Driver Receiver board appendix for AUX capabilities All AUX and UAUX signals share the controls listed in the following figure Figure 5 36 Shared AUX UAUX Controls Soft Front Panel Operation 5 68 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual State This control allows the user to set the output state for the selected AUX signal Table 5 66 AUX Output State Settings Setting Description Off Disable the AUX output On Enable the AUX output Inv Enable and invert the AUX output The relevant VXlplug amp play API function is e tat964 setAuxOutputSignal Source This control is visible when the state is set to On or Inv and allows the user to set the output source for the selected AUX signal Table 5 67 AUX Source Settings Setting Description Phase 1 4 Phase timing signal Window 1 4 Window timing signal Waveform 1 4 Waveform signal Sync 1 2 Sync signal Idle Active 1 Active 0 Not Active Sequence Active 1 Active 0 Not Active Channel good 1 Channel
473. wn control programs the Handshake Pause signal The selections for this pull down control are Table 5 82 Handshake Pause Signal Setting Pause Signal Resume Signal None Handshake mode NA disabled Astronics Test Systems Soft Front Panel Operation 5 109 Model T940 User Manual Publication No 980938 Rev K Setting Pause Signal Resume Signal Pause Trigger 1 True Pause Trigger 1 signal Pause Trigger 1 Resume true Pause Trigger 1 Not Pause Trigger 1 signal Pause Trigger 1 Resume True not true Pause Trigger 2 True Pause Trigger 2 signal Pause Trigger 2 Resume true Pause Trigger 2 Not Pause Trigger 2 signal Pause Trigger 2 Resume True not true Phase 1 Assert Phase 1 Assert edge Phase 1 Resume Trigger occurs Phase 1 Return Phase 1 Return edge Phase 1 Resume Trigger occurs Phase 2 Assert Phase 2 Assert edge Phase 2 Resume Trigger occurs Phase 2 Return Phase 2 Return edge Phase 2 Resume Trigger occurs Phase 3 Assert Phase 3 Assert edge Phase 3 Resume Trigger occurs Phase 3 Return Phase 3 Return edge Phase 3 Resume Trigger occurs Phase 4 Assert Phase 4 Assert edge Phase 4 Resume Trigger occurs Phase 4 Return Phase 4 Return edge Phase 4 Resume Trigger occurs The true false state of the pause triggers is based on the pause trigger test condition If the pause trigger test condition is set to Low Level then true would indicate the pause trigger signal is low
474. ws the user to specify a source and sink current load and a commutating voltage VCOM Note VCC 3 3V for the DR1 VCOM High Sink Current mA 549 59 ou Load State VCOM Low Source Current mA On 2 00 2 100 jor Mode Astronics Test Systems Soft Front Panel Operation 5 61 Model T940 User Manual Publication No 980938 Rev K Source VCOM Low VCOM High Load State Sink Figure 5 31 Current Load When the channel voltage is greater than the VCOM High level the Sink current becomes active When the channel voltage is less than the VCOM Low level the Source current becomes active The resistive load to VCOM allows the user to select resistance to the High level VCOM High Resistance Ohms 4 5 w v Load State On Jor Mode Resistor P id VCOM High Network Load State Figure 5 32 Resistive to VCOM Load The selections for this pull down control are Table 5 62 Resistive Settings Setting Description 140 Resistive load set to 140 Q 151 Resistive load set to 151 Q 165 Resistive load set to 165 Q 207 Resistive load set to 207 Q 240 Resistive load set to 240 Q 290 Resistive load set to 290 Q 540 Resistive load set to 540 Q 1040 Resistive load set to 1040 Q Soft Front Panel Operation 5 62 Astronics Test Systems Publication No 980938 Rev K Model T940 User Manual The relevant VXlplug amp play API functions are e iat964 setCha
475. y and Terminator modules Five Secondary modes exist 1 Secondary Not Linked DSA and DSB not linked and are independent 2 Secondary Linked DSA and DSB linked and independent 3 Secondary DSA Coupled DSA coupled to DRS and DSB independent 4 Secondary DSB Coupled DSB coupled to DRS and DSA independent 5 Secondary DSA and DSB Coupled Both DSA and DSB coupled to the DRS Terminator The Terminator module is the DRM leftmost slot Five Terminator modes exist 1 Terminator Not Linked DSA and DSB not linked and are independent 2 Terminator Linked DSA and DSB linked and independent 3 Terminator DSA Coupled DSA coupled to DRS and DSB independent 4 Terminator DSB Coupled DSB coupled to DRS and DSA independent 5 Terminator DSA and DSB Coupled Both DSA and DSB coupled to the DRS All the selections for the Inter Module Mode pull down control are listed below Only valid selections are displayed based on the jumper setting Table 5 8 Inter Module Mode Settings Setting DSA Control DSB Control DRM Type Independent Not Linked DSA DSB Independent Independent Linked DSA DSA Independent Primary DSA Coupled DRS DSB Primary Primary DSA and DSB Coupled DRS DRS Primary Secondary Not Linked DSA DSB Secondary Secondary Linked DSA DSA Secondary Secondary DSA Coupled DRS DSB Secondary Soft Front Panel Operation 5 12 Astronics Test Systems Publication No 98093
476. y or in user defined groups WCEM for Astronics Test Systems PAWS The optional WCEM for the PAWS Runtime system provides an interface to the DRM from the IEEE standard ATLAS test language This interface provides the capability for the DRM to support both legacy and modern system implementations that take advantage of the higher order signal oriented features of IEEE ATLAS The interface utilizes the PAWS system the popular independent implementation of the ATLAS language The user does not need to know the nuances of the DRM as the ATLAS language provides the higher order interface to the hardware Application Resource Interface ARI The optional Application Resource Interface ARI provides C callable functions and services to the standard DRM driver providing the capability for users to configure and execute multiple DRMs as a DRS This interface provides the capability to emulate the legacy system characteristics without changes to the underlying C program that executes the digital test Digital Function Library DFL The optional Digital Function Library DFL provides an interface to Legacy Applications that can be adapted as needed to implementations to seamlessly support legacy investments This interface provides the capability for the system to emulate the legacy software characteristics without changes to the underlying C program that executes the digital test Automatic Test Program Generation ATPG The optional ATPG

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