TB-6V-LX760-LSI Hardware User Manual
Contents
1. a gt lt ao ma a enn MI gt UNIT MN gt BU km MT29F4G16 95 BABWP MicroSD 15 MicroSI z TET rf z osc 9 85 8g DDR 2908 05WB MG 83 83 15 3 8 i XC3S700AN C FG484 E DOR 23 23 as 3 5 8 XC6VSX760T 1 22 ans F1760 28 RA 05 42 5X42 5 Be a 8 DDR 88 o 3 z iD 8s 15 gt gt EP 2 DDR 3 8 Lr ne SN74GBS z DES 5 73245000 O oo pe 83 81 E m E lt p 82 M FR ES ET 1 uk 08 4 gt 3 C 3474988 ci da 1324 v De al kaj H mm m MS LED OUT y um no le 2 x TIE gt lt iss VV Vea lt Sv 00 gt lt 002 gt lt 177 gt C gt sez gt l 2 695 Figure6 1 Layout of TB 6V LX760 LSI Board Components TOKYO ELECTRON DEVICE LIMITED Rev 3 00 TB 6V LX760 LSI Hardware User Manual inreviun E 6 5 Layout of the TB FMCH STACK Board Components The following figure shows the dimensions of the TB FMCH STACK board and locations of its connectors Carrier Card Connector 1 SESESEISIOESS SS Siena TMN NTI NINE2. Bank No Pin No H Pin No Bank No 1 5 VREF A M2C 15 V38 SNT 2 L AB42 14 15 U38 3 GND 4 AB37 14 5 AA37 14 14 AC38 6 14 AC39 AB39 14 8 AB38 14 14 AA39 9 14 Y39 AD42 14 11 AC41 14 15 U42 12 15 T42 13 AA36 14 14 AA35 14 15 T40 15 T39 16 AC34 14 17 AC35 14 15 Y32 18 15 Y33 41 15 20 42 15 14 AA32 21 14 AB33 V35 15 23 V34 15 15 W32 24 15 W33 R37 15 26 T36 15 14 AA41 27 14 Y42 V36 15 29 U36 15 15 N41 30 15 N40 W41 14 32 W42 14 15 W35 33 15 W36 U34 15 35 V33 15 15 M42 36 GND 15 Mai R39 15 GND R38 15 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 28 inreviun 8 8 3 4 FMC4 LPC MC CC Connector FMC connector 46 70 is interfaced to the FPGA over 36 pairs of signal pins Of them 2 pairs are assigned to the MRCC pins of the FPGA The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 4 FMC4 Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M C2M 2 GND C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 GBTCLKO 2 M2C 6 GND 2 7 GND GND 8 LA01_P CC AV40 12 GND
3. 05C V6_CLK266M_P_ 1 1 W Sparten3AN OSC 50MHz E kuri P GC CCLK VOLGOLK XC3S700AN ESM KC3225A50 css 000003 psum gt GC FG484 MRCC V6_USB_IFCLK PHY ve USB CY7C68013 24MHz lt 56 T m m V6 DDR3A CK 10 gt DDR3 SDRAM gt 580 Ve SYSCUK l oc PO DDR9A Group A PLE 6 SYSCLK gt ac ICS8430AY1 61 Frequency V6_DDR3B_CK INI2 0 20 88 500MHz fo gt DDR3 SDRAM _ V6_DDR3B_XCK Group B Frequency FMC1_CLK_M2C_P 1 0 14 27MHz GC MRCG gt FMC c FMC 1 FMC1_CLK_M2C_N 1 0 Connector 1 85C GOMROG ya SR A LPC CC LPC MC 16MHz FMC2_CLK_M2C_P 1 0 SG 8002DC m 11 0 2 M2C_N 1 0 Connector 2 Connector 2 py s s 1 LPC CC LPC MC MMCX BNC CN FMC3_CLK_M2C_P 1 0 FMC FMC MMCX J P H ST TH1 NRC ass ZE V6 MMCX P FMC3 CLK M2C NI1 0 onnector 3 Connector 3 Pa e S_MMOXP _ gt ac MRCOG LPC CC LPC MC FMC4_CLK_M2C_P 1 0 I Y6_MMOXN _ gt ac MACO Mm FMC FMC FMC4 CLK N 1 0 Connector 4 Connector 4 PC CC PC MC FPGA _ _ XC6VLX760 FFG1760C EMOS CUR M20 1 0 MA O ieee ome Sx FI 3 Connector 5 Connector 5 FMC5 CLK 2 N 1 0 MRCC 4 d LPC CC LPC MC
4. Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M C2M 2 GND C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 GBTCLKO 2 M2C 6 GND 2 7 GND GND 8 LAO1 P CC Y38 14 GND 9 LA01 N CC Y37 14 15 U37 LA06_P 10 GND 15 T37 LAO6_N 11 LAO5 U41 15 GND 12 LAOS V40 15 GND 13 GND 14 Y35 LA10 P 14 LA09 P AD33 14 14 Y34 LA10 N 15 LAO9 N AD32 14 GND 16 GND GND 17 LA13 P AC33 14 15 R40 LA14 P 18 LA13_N AB32 14 15 P40 LA14 N 19 GND GND 20 LA17 AB34 14 GND 21 LA17 AA34 14 14 VAI LA18 22 GND 14 W40 18 CC 23 LA23 AB41 14 GND 24 LA23_N AC40 14 GND 25 GND 14 AA40 LA27 26 LA26 W38 15 14 Y40 LA27_N 4 LA26 W37 15 GND GND GND 3 TOK 1 SCL 3 TDI 1 SDA 3 TDO GND 7 3P3VAUX GND WO 3 TMS 2 wo gt TRST_L 7 12POV 2 GAI GND 7 3P3V 7 12POV N GND GND 7 3P3V 7 C2 GND GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 27 inreviun 8
5. Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M C2M 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 GBTCLKO M2C M2C 6 GND M2C 7 GND GND 8 LAO1 P CC E9 36 GND 9 LAO1 CC E10 36 36 E8 06 P 10 GND 36 D8 06 11 LAO5 P C6 36 GND 12 LA05 N B6 36 GND 13 GND 36 B12 LA10 14 09 F10 35 36 B11 LA10 N 15 LAO9 N F9 35 GND 16 GND GND 17 LA13 P D10 36 36 G11 LA14_P 18 LA13_N D11 36 36 G12 LA14 N 19 GND GND 20 LA17 G6 35 GND 21 LA17 F6 35 35 J8 LA18 22 GND 35 H8 18 CC 23 LA23 H11 35 GND 24 LA23 H10 35 GND 25 GND 35 J10 LA27 26 LA26 N14 35 35 11 27 27 LA26 N N15 35 GND GND GND 3 TCK N c 1 SCL 3 TDI 1 SDA TDO GND C2 N 7 3P3VAUX GND 3 TMS 2 TRST_L wo gt 712 0 2 GAI GND 7 3P3V 7 12POV GND 51 GND 7 3P3V 7 3P3V GND GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 37 inreviun 8
6. pH 8 5 6 5 0 20 6 o eo o The following table shows the function corresponding to the N value Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 46 inreviun 8 Table9 2 PLL s N Divide Setting Table N Divider Value Output Frequency MHz Minimum Maximum 250 500 166 66 333 33 125 250 83 33 166 66 62 5 125 41 66 83 33 31 25 62 5 0 0 0 0 1 1 1 1 Rev 3 00 OO CO o o O C2 OO 20 83 TOKYO ELECTRON DEVICE LIMITED 41 66 47 inreviun 10 Power Supply System 10 1 Power Consumption Estimation The following is the power consumption estimation of the main components XC6VLX760 2FFG1760C Vccint 1 0V 29 5W Vccaux 2 5V 7 5W Vcco2 5 2 5V 10 5W 1 5 1 5V 2 5W XC3S700AN 4FGG484C Vccint 1 2V 0 6W Vccaux 3 3V 0 66W 2 5 2 5V 0 75W DDR8 Micron 1 Gbit x 4 VDD 1 5V 4W Vtt 0 75V 1W Note 0 75V 50ohm x 60pin 1A SPI Flash Numonyx M25P64 x 1 VDD 3 3V 0 5W USB Cypress CY7C68013A x 1 VDD VDDQ 3 3V 0 5W Option I O x20 to FMC 2 5V 20W 3 3V 26 4W 5 0V 20W 12V 24W
7. 35 Table8 8 FMC8 Connector Pinouts on Component and Solder 5 37 Table8 9 FMC9 Connector Pinouts on Component and Solder SideS 2 39 Table8 10 FMC10 Connector Pinouts on Component Solder 5 41 Table9 1 PLL s M Divide Setting Table L 46 Table9 2 PLL s N Divide Setting Table i 47 Table tite LED IUe 52 I FUNCtHONS UU A VO iii 53 Table11 3 Jumper Functions ii 54 Table11 4 Pin assign of Pin 55 Table12 1 Initial Settings ni iaia 57 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 5 inreviun 8 Introduction Thank you for purchasing the TB 6V LX760 LSI board Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual and then always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you other personnel or damage to property Before using the product read these safety precautions carefully to assure safe use These precautions contain serious safety instructions that must be observed After reading through this manual be sure to always keep it handy The following conventions are u
8. Bank No Pin No H Pin No Bank No 1 5 VREF M2C 35 K8 2 L M13 35 35 J7 3 GND 4 J15 36 5 J16 36 36 11 6 36 12 12 36 8 12 36 36 7 9 36 7 D6 35 11 D7 35 36 A9 12 36 A10 B8 36 14 89 36 36 C11 36 C10 _16 F7 35 17 E7 35 36 G13 18 36 H13 11 36 20 12 36 35 H9 21 35 G9 G7 35 23 G8 35 35 K10 24 35 L11 M16 35 26 L15 35 35 L10 27 35 K9 M16 35 29 L15 35 35 K13 30 35 J12 31 N16 35 32 P16 35 35 R15 33 35 P15 J13 36 35 K14 36 35 H14 36 GND 35 G14 L16 36 GND K15 36 7 GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 38 inreviun 8 3 9 FMC9 LPC MC CC Connector The FMC connector J51 J75 is interfaced to the FPGA over 36 pairs of signal pins Of them 2 pairs are assigned to the MRCC pins of the FPGA The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 9 FMC9 Connector Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M C2M 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 GBTCLKO M2C M2C 6 GND M2C 7 GND GND 8 LAO1 P CC N1 45 GND 9 LAO1 N CC M1 45 44 LA06_P 10 GND 44 Y2 LA06_N 11 LA05_P T6 45 GND 12 LA05 N T7 45 GND 13 GND 45 U11 LA10 14 09 W8 45 45 V11 LA10 N 15 LAO9 N W7 45 GN
9. 51 10 5 Power S pply for Fan 51 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 3 inreviun 8 11 gt _ lt _ 52 TES BED n1 niece emis II M 52 53 cw 54 11 4 Pin Header ie rina anice 55 12 kp m e e ee 56 Figure4 1 Block _ V 11 Figure5 1 Component 5 12 Figure5 3 External view of the TB FMCH STACK and TB FMCH CONNECTOR 13 Figure6 1 Layout of TB 6V LX760 LSI Board 16 Figure6 2 Layout of the TB FMCH STACK Board 17 Figure6 3 Layout of the TB FMCH CONNECTER Board Components 17 Figure7 1 DDR3 Peripheral 18 Figure7 2 SPI Flash Peripheral Connections 19 Figure 7 3 BPI Flash Peripheral Connections i 19 Figure7 4 CONFIG Peripheral Connections ii 20 Figure 7 5 STAG u aaa 20 Figure8 1 USB and 12C Peripheral Connections 21 Figure8 2 FMC Connector Peripheral Connections 22 Figure8 3 Low Pin Count Pinouts ii 22 Figure8 4 SDA SCL GA1 0 TDI TDO
10. 43 Figure8 5 PG C2M Circuit ETT TTT TTT Ria 43 Figure8 6 VREF A M2C 43 Figure8 7 FMC_VREF Select Circuit iii 44 Figure8 8 VA DANOJ OE ET 44 Figure9 1 Clock System Diagram 45 Figure10 1 Power Supply System Diagram i 49 Figure10 2 Power Supply Monitor ii 50 Figure10 3 Power Supply Arrangement for FPGA 51 Figure10 4 Fan Connector Peripheral Circuit eee 51 Figure12 1 Default Settings component side nens 56 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 4 inreviun 8 List of Tables Table6 1 TB 6V LX760 LSI Board Structure 14 Table6 2 TB FMCH STACK Board Structure 14 Table6 3 TB FMCH CONNECTER Board Structure 15 Table8 1 FMC1 Connector Pinouts on Component and Solder Sides 23 Table8 2 FMC2 Connector Pinouts on Component and Solder Sides 25 Table8 3 FMC3 Connector Pinouts on Component and Solder Sides 27 Table8 4 FMC4 Pinouts on Component and Solder Sides 29 Table8 5 FMC5 Pinouts on Component and Solder 31 Table8 6 FMC6 Connector Pinouts on Component and Solder Sides 33 Table8 7 FMC7 Connector Pinouts on Component and Solder Sides
11. GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 35 inreviun 8 Bank No Pin No Pin No Bank No 1 5 A 37 G16 2 6 PRSNT B18 38 37 F16 3 GND 4 D17 38 5 D18 38 38 D21 6 38 C21 20 38 8 D20 38 38 F19 9 38 E18 A16 38 11 17 38 38 F21 12 38 E20 C18 38 14 C19 38 38 B16 15 38 B17 16 E17 38 17 F17 38 38 G19 18 38 H20 J22 38 20 J21 38 37 B13 21 37 B14 H15 37 23 H16 37 37 17 24 37 J17 K18 37 26 J18 37 38 121 27 38 120 18 37 29 19 37 37 17 30 97 N18 E14 37 32 E15 37 37 817 33 37 P18 34 37 35 N20 37 37 M17 36 97 P20 AN D13 37 GND E13 37 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 36 inreviun 8 8 3 8 FMC8 LPC MC CC Connector The FMC connector J50 J74 is interfaced to the FPGA over 36 pairs of signal pins Of them 1 pair is assigned to the GCLK pins and 1 pair is assigned to the MRCC pin of FPGA The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 8 FMC8 Connector Pinouts on Component and Solder Sides
12. The following is the current value to the power consumption of the main components Vccint Vccaux Vcco 1 0V 29 5W 29 5 1 2V 0 6 0 50 2 5V 18 8W 7 52 3 3V 2 5W 0 75 1 5V 6 5W 4 3 0 75 1 0W 1 33 Option Power 2 5V 20 0W 3 20 3 3V 26 4W 3 55A 5 0V 20 0W 7 22 12 24W 2A The board is designed assuming that the power consumption and the current value for 12V input power is 149 30W and 12 44A respectively Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 48 TB 6V LX760 LSI Hardware User Manual 10 2 Power Supply System Diagram Power Supply ATX12V Power Supply Connector Molex 39 29 1048 or 39 30 0060 connector The following figure shows the power supply system diagram inreviun ATX CN 39 30 0060 414 SA a gt gt gt 7 S6A MAX To Vint of Virtex6 FPGA 5 g g FUS LTM4601A Use rate 81 94 V6_VINT is about 29 5A 6 3 12 0V gt 1 0V KE MASTER ATXCN 39 29 1048 DC DC 1 3 LTM4601A 1 A KI 12 0V 1 0 NON SLAVE DC DC LTM4601A 1 12 0V gt 1 0V SLAVE 6A MAX To Vccaux of Virtex6 FPGA DC DC Use rate 50 6 VAUX is about LTM4606 12 0V gt 2 5V DC DC SAMAJ To Vcco of Virtex6 FPGA uu Use rate 67 1 5V is about 4 02A
13. ua 69 0 Component i Component side 184 side 2 0 L 2 40 LAS Solder side Hole for HPS MC Unit mm Module Connector Figure6 2 Layout of the TB FMCH STACK Board Components 6 6 Layout of the TB FMCH CONNECTER Board Components The following figure shows the dimensions of the TB FMCH CONNECTER board and locations of its connectors 8 mm Component side Solder side FMC HPC Module Back Side lt 39 31 5 880 31 5 3 0 Figure6 3 Layout of the TB FMCH CONNECTER Board Components Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 17 inreviun 8 7 Description of Components 7 1 DDR3 SDRAM The TB 6V LX760 LSI board has four DDR3 SDRAM chips Device MT41J64M16LA 15E B Micron 1 Gbit BMeg x 16bit x 8Bank x 4 or equivalents The DDR3 memory device can be divided into two groups as shown in following figure GroupA A 13 0 BA 2 0 CK DDR3 SDRAM XCK CKE XCS 1Gbit ODT XWE XRAS MT41J64M16LA 15 DQI31 16 DQS 3 2 XDQS 3 2 DDR3 SDRAM 1Gbit MT41J64M16LA 15 DQ 15 0 DOS 1 0 XDQSI1 0 FPGA __ XC6VLX760 FFG1760C A 13 0 BA 2 0 CK XCK CKE XCS ODT XWE XRAS XCAS XRESET MT41J64M16LA 15 DQ 31 16 DQS 3 2 XDQS 3 2 DDR3 SDRAM 1Gbit DQ 1
14. Connector Module High Pin Figure5 3 External view of the TB FMCH STACK and TB FMCH CONNECTOR Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 13 inreviun 8 6 Board Specifications 6 1 TB 6V LX760 LSI Board Structure The following table shows the board structure and the specifications For details about connector locations refer to the board layout drawing For details about clock structure and operational frequency refer to the clock system diagram Table6 1 TB 6V LX760 LSI Board Structure Category l Category Il Specification Remarks Number of Layers 16 Dimensions 369mm x 225mm Thickness Resist Color Red Material FR 4 13 0mm without FAN and power connector 7 1mm 50 Ohm 90 Ohm 100 Ohm RoHS lead free solder Gold plating Board Structure Component Side Height Solder Side Single Signal Differential Signal RoHS Pbfree RoHS Pbfree Surface Coating Impedance Control 6 2 TB FMCH STACK Board Structure The following table shows the board structure and the specifications For details about connector locations refer to the board layout drawing Table6 2 TB FMCH STACK Board Structure Category l Category Il Specification Remarks Board Structure Number of Layers 16 Dimensions 69mm x 40mm Thickness smm Resist Color Red Material FR 4 Height Component Side 6 5 Solder
15. adenine 18 d sas 19 7 32 BPIFLASH calli 19 7 4 MicroSD NAND FLASH these are only for Virtex 6 configuration 20 85 Interfaces iii 21 8 1 ati CE rari 21 82 Method of Rewriting an EEPROM for USB 21 8 3 PMG Comme 22 8 3 1 FMC1 LPC CC Connector ue 23 8 3 2 FMC2 LPC CC Connector ie 25 8 3 3 FMC3 LPC MC CC Connector ii 27 8 3 4 FMC4 LPC MC CC Connector 29 8 3 5 FMC5 LPC CC 31 8 3 6 FMC6 LPC CC 33 8 3 7 FMC7 LPG MC 35 8 3 8 FMC8 LPC Connector 37 8 3 9 9 LPC CC Connector 39 8 3 10 FMC10 LPC MC Connector iii 41 9 Clock System Diagrami aaa 45 9 1 46 10 Power Supply SySteltiuma 48 10 1 Power Consumption Estimation 48 10 2 Power Supply System Diagram i 49 10 3 Power Supply Monitor _ ___ _ _ _ _ _ 50 10 4 Power Supply Arrangement for FPGA
16. 1 SCL 3 TDI 1 SDA GND 7 3P3VAUX GND 3 TMS 09 2 GAO TRST_L gt 7 12POV 2 GAI GND 7 7 12POV GND N GND 7 3P3V 7 3P3V GND c GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 31 inreviun 8 Bank No Pin No H Pin No Bank No 1 5 VREF A M2C 22 AW32 SNT L AN28 22 22 AW33 3 GND 4 AU36 23 5 AU37 23 23 AW36 6 23 AV35 AV33 22 8 AU32 22 22 AV34 9 22 AU34 BA34 22 11 5 22 23 9 12 23 AY39 13 BB36 23 14 BA36 23 23 AV38 23 AU38 16 1 22 17 AP30 22 23 AU39 18 23 AV39 AY40 23 20 AW40 23 22 AY33 21 22 AY34 AV31 22 23 AU31 22 22 AT30 24 22 AR29 AR28 22 26 AT29 22 22 AN30 27 22 AN31 AM29 22 29 AN29 22 23 AP32 30 23 AR32 31 1 23 32 AM32 23 22 AL27 33 22 AM28 AL26 22 35 AM27 22 22 AJ28 36 GND 22 AK28 AK27 22 GND 27 22 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 32 inreviun 8 8 3 6 FMC6 LPC MC CC Connector
17. A B 5 V6 OPVREF A B FP OP gt VREFA B V6 OPVREF A B FP OP A FP OP B V6 OPVREF A VREFA J23 TMM 102 06 L D SM Figure8 7 FMC VREF Select Circuit 6 PRSNT M2C L This connects the H2 pin of the FMC connector to the FPGA 7 Power Supply The board provides 12V to the 12POV pin and 3 3V to the 3P3V and 3P3VAUX pins The following circuit also allows the selection of 5V 3 3V and 2 5V for the VADJ pins including E39 F40 G39 and H40 The voltage can be supplied by short circuiting one of the jumpers JP7 16 and JP27 36 respectively The supply voltage can be monitored with a neighboring LED Caution Do not short circuit two or more positions of each JP7 16 and JP27 36 Short circuit the same position of each JP7 16 and JP27 36 RS 100 077 5 310 77 y 2 CA VADI SV LEDO VA 854 1 c FUGE VAD LL J SWLTOCITES r 078 LEDIG VADIO RSSG 5 E 807 400 POS VADI x V LEOR VADUX 8 AN omn DO pa DTD1 3ZU EET T 02 33V 8 0 Figure8 8 VADJ Circuit Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 44 TB 6V LX760 LSI Hardware User Manual inreviun E 9 Clock System Diagram The following figure shows the clock system diagram of the TB 6V LX760 LSI board
18. FMC6 LI 2 MII M2C FMC FMC Connector6 Connector 6 OME VIII FMC1_FRSNT_M2C P FMC FMCA_CLKM2C_PINI O ConnectorA FMC Connector 1 LPC MC CC LPC CC LPC MC FMC6 LA P N 33 0 FMC1 LA P N 33 0 FMC7 PI 8NT M2C FMC2 PI SNT M2C iM Connector 7 Connector 7 l FEZ VIII CERO ROKA COJ Connector2 Connector 2 LPC MC CC CC LPC MC FMC7 LA P N 33 0 FMC2 LA P N 33 0 FME8_FRSNT_M2C Bk FMC3 FRSNT M2C di is 8 Connector 8 AC6VLX760 FMCS CLM Msc Connector 3 Connector LPC MC LC CC 2FFG1760C LPC CC LPC Mc LA P N 33 0 LA P N 33 0 FMiC9 FRSNT M2C FRSNT M2C ela Connector9 Connector 9 Meet 00000 Connector4 Connector 4 LPC MC LC CC LC CC LPC MC 9 LA P N 33 0 LA P N 33 0 FMC10_PRENT_M2C FMC5 PR amp NT M2C ole Connector 10 Connector 10 l EMETO ELK ENTON Connector 5 Connector 5 LPC MC LPC CC LPC CC LPC MC LA P N 33 0 FMC5 LA P N 33 0 Figure8 2 FMC Connector Peripheral Connections The following figure shows the FMC connector pinout Note that not all LPC Cow Pin Count are canneries to the FPGA D 1 eee _ EA P LPC Connector LPC Connector PC Con
19. CLK 1 0 FMC FMC an mu Laem Lisa Connector 6 Connector 6 MRCC FMO6_CLK_M2C_N 1 0 LPC CC LPC MC ILE MO7 20 1 0 MRCC c7 CIK moc Connector 7 Connector 7 M2C 1 0 em TIT LPC MC FMC8_CLK_M2C_P 1 0 GOMACG S FMC FMC FMC8 CLK M2C N 1 0 Connector 8 Connector 8 a 1 0 FMC FMC MR pu gu id FMC9 N 1 0 n 3 MC 3 Differential clock FMC10_CLK_M2C_P 1 0 Single end clock EMC10 CLK M2C_N 1 0 Connector 10 Connector 10 Figure9 1 Clock System Diagram Rev 3 00 ELECTRON DEVICE LIMITED TB 6V LX760 LSI Hardware User Manual inreviun E 9 1 PLL Setting The output clock frequency of an onboard PLL can be calculated using the following formula Fout is the output clock frequency in the range of 20 83MHz 500MHz and is the input clock frequency in the range of 14MHz 27 MHz M N 16 N Fvco 16 x M must be set within the range of 250 500MHz Fout Fxtal 16 x M N Fout In case of outputting 125MHz Condition Fxtal input clock 16MHz M 8 0 0 1 1 1 1 1 0 1 0 x 250 N 2 0 0 1 0 divide by 2 The following table shows the mapping table between M value and DIP SW Table9 1 PLL s M Divide Setting Table
20. USB WUP V6 USB RP T1 0 USB RDYT1 0 24M ACOVLA760 FFG1760C V6 USB XRST BUF Figure8 1 USB and I2C Peripheral Connections 8 2 Method of Rewriting an EEPROM for USB PHY Free software EzMr exe is available from Cypress Semiconductor Corporation for rewriting the CY7C68013 EEPROM The following procedure describes how to rewrite an EEPROM Contact Cypress Semiconductor for more information if necessary 1 Remove the J53 jumper 2 Connect the board to a PC using a USB cable 3 Run EzMr exe 4 Reinstall jumper J53 5 Onthe EzMr exe panel select the EEPROM Erase File hex to erase the EEPROM data 6 After completion of downloading disconnect the USB cable 7 Connectit again to get the PC to recognize the board once more 8 Onthe EzMr exe panel select the target firm binary data iic and download it 9 Again disconnect and reconnect the USB cable to get the PC recognize it 10 That s all Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 21 TB 6V LX760 LSI Hardware User Manual inreviun 8 3 FMC Connector The TB 6V LX760 LSI board has 10 FMC LPC connectors Carrier type on its component side and 10 FMC LPC connectors Module type on its solder side The following figure shows the FPGA to FMC connections For details about FPGA pinouts refer to the board circuit diagram A Microsoft Excel spreadsheet document defining the pinouts is also available as a published reference
21. GND 7 7 3P3V GND GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 25 inreviun 8 Bank No Pin No Pin No Bank No 1 5 VREF A_M2C 16 M38 2 6 PRSNT I D40 17 16 M37 3 GND 4 J38 17 5 J37 17 16 M36 6 16 N35 L40 16 8 K40 16 16 U33 9 16 T34 K38 16 11 137 16 17 K37 12 17 L36 R33 16 14 R32 16 17 L35 15 17 M34 16 M33 17 17 L34 17 17 K34 18 17 J35 41 17 20 40 17 16 K42 21 16 J41 F40 17 23 F39 17 16 G42 24 16 F42 P38 16 26 P37 16 16 H40 27 16 041 834 16 29 P35 16 17 41 30 17 B42 P36 16 32 N36 16 17 E39 33 17 E38 34 T35 16 35 R35 16 16 U31 36 16 M39 N B39 17 GND C39 17 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 26 inreviun 8 8 3 3 CC Connector The FMC connector J45 J69 is interfaced to the FPGA over 36 pairs of signal pins Of them 2 pairs are assigned to the MRCC pins of the FPGA The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 3 FMC3 Connector Pinouts on Component and Solder Sides
22. So LA33_P N cannot use for differential signal interface The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 7 FMC7 Connector Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M 2 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 2 M2C 6 GND M2C 7 GND GND 8 LAO1 P F20 38 GND 9 LAO1 CC E19 38 38 B21 06 P 10 GND 38 A21 LAO6 N 11 LAO5 A19 38 GND 12 LA05 N A20 38 GND 13 GND 38 K22 LA10 14 LA09 P 16 37 38 122 LA10 N 15 LAO9 N D16 37 GND 16 GND GND 17 LA13 P G21 38 38 K20 LA14 P 18 LA13 N H21 38 38 J20 LA14 N 19 GND GND 20 LA17 14 37 GND 21 LA17 15 37 37 H18 LA18 22 GND 37 G17 LA18 N CC 23 LA23 P C15 37 GND gt LA23_N D15 37 GND N GND 37 F15 LA27 N 26 K19 28 37 F14 LA27 N N LA26_N L19 37 GND GND GND N 3 TOK 1 SCL 3 TDI 1 SDA TDO GND 7 3P3VAUX GND 3 TMS 2 wo gt TRST_L 7 12POV 2 GAI GND 7 3P3V 7 12POV N GND GND 7 7 3P3V GND
23. c 3 TCK 1 SCL 3 TDI 1 SDA TDO GND C2 N 7 3P3VAUX GND 3 TMS 2 wo gt TRST_L 7 12POV 2 GAI GND 7 3P3V 7 12POV 51 GND GND 7 3P3V 7 3P3V GND GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 41 inreviun 8 Bank No Pin No H Pin No Bank No 1 5 VREF A M2C 42 AL5 2 L AH10 42 42 AK5 3 GND 4 AH4 43 5 AG4 43 43 ADE 6 43 ADS AGI 43 8 AF1 43 43 AG2 9 43 AF2 AF5 43 11 AE5 43 42 AH8 12 42 AJ7 AJ6 42 14 AJ5 42 43 AF7 43 AF6 16 AG7 43 17 AG6 43 42 AL2 18 42 AK3 AH6 42 20 AH5 42 42 AR2 21 42 AP2 AG9 42 23 AG8 42 42 AR4 24 42 AR3 AF10 43 26 AF9 43 43 AJ3 27 43 AJ2 AP3 42 29 AN3 42 43 AD10 30 43 AD11 31 AE10 43 32 AE9 43 42 AV1 33 42 AU1 AC10 43 35 11 43 43 12 36 43 AF11 AG12 43 AGHI 43 39 GND 40 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 42 TB 6V LX760 LSI Hardware User Manual inreviun E 1 SCL SDA This has a test pad to perform the
24. 13 AH41 27 13 41 AG42 13 29 AF41 13 13 AF39 30 13 AE39 31 AD37 13 32 AD38 13 13 AF42 33 13 AE42 AD40 13 35 AD41 13 12 AH33 36 GND 12 AH34 AD36 13 GND AD35 13 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 30 inreviun 8 8 3 5 FMC5 LPC MC CC Connector The FMC connector J47 J71 is interfaced to the FPGA over 36 pairs of signals pins Of them 2 pairs are assigned to the MRCC pins of the FPGA The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 5 FMC5 Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M C2M P 2 GND DPO C2M N 3 GND GND 4 GBTCLKO M2C P GND 5 C8ICLM0 2 M2C 6 GND M2C 7 GND GND 8 LAO1 P AV30 22 GND 9 01 CC AW31 22 22 BB33 LAO6 10 GND 22 BB34 LAO6_N 11 LAO5 AP33 23 GND 12 LAOS AN33 23 GND 13 GND 23 BA40 LA10 P 14 LA09 P BB37 23 23 BB39 LA10 N 15 LAO9 N BB38 23 GND 16 GND GND 17 LA13 BA42 23 23 AY38 LA14 P 18 LA13 N AY42 23 23 AW38 LA14 N 19 GND GND 20 LA17 BA41 23 GND 21 LA17 N CC BB41 23 22 AY35 LA18 22 GND 22 35 18 CC 23 LA23 AV36 23 GND 24 LA23 N AW37 23 GND 25 GND 23 AT35 L 27 26 LA26_P AR30 22 23 AR34 LA27_N N LA26_N AT31 22 GND GND N GND 3 N
25. AC9 44 29 AC8 44 44 AD1 30 44 AC1 31 44 32 44 44 Y10 33 44 11 V9 45 35 V10 45 45 Wii 36 GND 45 W10 AA10 44 GND 11 44 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 40 inreviun 8 8 3 10 FMC10 LPC CC Connector FMC connector 452 76 is interfaced to the FPGA over 36 pairs of signal pins Of them 2 pairs are assigned to the MRCC pins of the FPGA Following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 10 FMC10 Connector Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M C2M 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 GBTCLKO M2C M2C 6 GND M2C 7 GND GND 8 LAO1 P CC AE7 43 GND 9 LAO1 N CC AD7 43 43 AD8 LAO6 10 GND 43 AE8 LAO6 N 11 L 05 AH1 43 GND 12 LA05 N AJ1 43 GND 13 GND 42 AL1 LA10 P 14 09 AJ8 42 42 AK2 LA10 N 15 LAO9 N 7 42 GND 16 GND GND 17 LA13 P AP1 42 42 AL4 LA14 P 18 LA13_N ANI 42 42 AK4 LA14 N 19 GND GND 20 LA17 AM6 42 GND 21 LA17 AL6 42 42 AN4 LA18 22 GND 42 ANS LA18 N CC N LA23 P 1 42 GND gt LA23 N AM2 42 GND N GND 42 AM4 LA27_P N 26 AU3 42 42 AM3 LA27_N N LA26_N AU2 42 GND GND GND N
26. FMC OP POWER is about 2A 49 TB 6V LX760 LSI Hardware User Manual inreviun E 10 3 Power Supply Monitor The board has a Linear Technology s LTC2978CUP to monitor the onboard power sources such as Core voltage AUX voltage and VCCO 2 5V 1 5V that use Virtex 6 The monitor information can be displayed on your PC through the onboard CN29 connector and the Linear Technology s USB conversion board You can set various parameters for monitoring using dedicated application software The following figure shows the connection diagram TB 6V LX760 LSI These devices are watched by LTC2978 These devices are not watched FP OP A OP 5V T mE DCDC 7 DC DC gt Module x 2 FP OP B Module x 2 OP SV B LTM4606 gt lt 7 LTM8025 7 OP 33V V6 VAUX DC DC DC DC VCC 33V gt Module OP 25V T Module gt USE interface exchange board LTM4619 7 LTM8025 p Linear Technology OP 33V S3 VINT USB V6 VCCO25 DC DC DC DC gt Module OP 25V B Regulator vcco25 14 LTM4619 LTC3417 CN29 VCC 1 5V h lt Figure10 2 Power Supply Monitor For more information please contact Linear Technology Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 50 TB 6V LX760 LSI Hardware User Manual inreviun E 10 4 Power Supply Arrangement for FPGA Banks Figure 6 3 shows the arrangement of the pow
27. FPGA 2 FMC VREFB 3 4 FP OP B J12 J32 VADJ power supply selection for FMC1 LPC CC MC 1 2 5V J11 J31 VADJ power supply selection for FMC2 LPC CC MC 3 3 3 914 J34 VADJ power supply selection for FMC3 LPC 5 5V J13 J33 VADJ power supply selection for FMC4 LPC CC MC 2 4 6 VADJ J7 J27 VADJ power supply selection for FMC5 LPC CC MC 8 428 VADJ power supply selection for FMC6 LPC CC MC J10 930 VADJ power supply selection for FMC7 LPC CC MC 49 429 VADJ power supply selection for FMC8 LPC CC MC 916 J36 VADJ power supply selection for FMC9 LPC CC MC J15 935 VADJ power supply selection for FMC10 LPC CC MC Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 54 inreviun 8 11 4 Pin Header This pin header is used for general purpose The connector is HIROSE A1 34PA 2 54DSA Table11 4 Pin assign of Pin header Pin Number Pin Name Pin Number Pin Name 1 2 5V 2 5V V6_TPO V6_TP15 V6_TP1 V6_TP16 V6_TP2 V6_TP17 V6_TP3 V6_TP18 V6_TP4 V6_TP19 V6_TP5 V6_TP20 V6_TP6 V6_TP21 V6_TP7 V6_TP22 V6_TP8 V6_TP23 V6_TP9 V6_TP24 V6_TP10 V6_TP25 V6_TP11 V6_TP26 V6_TP12 V6_TP27 V6_TP13 V6_TP28 V6_TP14 V6_TP29 GND GND Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 55 TB 6V LX760 LSI Hardware User Manual 12 Initial Settings The following figure shows the Initial switch settings Look at the switches surrounded by a blue box
28. FPGA Configuration 64MBit x 1 for MicroBlaze 256MBit x 1 for test Connectors for component side x 10 Connectors for solder side x 10 Type B Hi speed USB target MicroSD It is only for Virtex 6 Configuration x 1 30 bit connecting to XC6VLX760 Onboard power source monitor OSC 24MHz for USB mounted 50MHz for 35700 mounted 266MHz for DDR3 mounted 16MHz for PLL mounted 4 Header Header connecting to XC3S700AN Green color LED for XC6VLX760 configuration DONE 14 general purpose green color LEDs connecting to XC6VLX760 2 general purpose red LEDs connecting to XC6VLX760 Green color LED for XC3S700AN configuration DONE 3 general purpose red LEDs connected to XC3S700AN Pushbutton switch to initiate configuration General purpose 16 bit DIP switch connected to XC6VLX760 General purpose 4 bit pushbutton switch connected to XC6VLX760 2 switches connected to XC3S700AN TOKYO ELECTRON DEVICE LIMITED inreviun 8 Power Supply The 12 volt power supply can be derived either from the Molex 39 29 1048 connector or from the 39 30 0060 A dedicated power supply is attached Onboard power supply module Various Linear modules LTM4601A LTM4606 LTM8025 etc Holes for fixing an FPGA radiator dedicated heat sink and FAN Spacers and screws for attaching option boards 5 TB FMCH STACK boards and 3 TB FMCH CONNECTERs Warning Virtex 6 FPGA does not support 3 3V IO Rev 3 00 TOKYO ELECTRON DEVICE LIMITE
29. Modified Table 8 7 CLK1 M2C P N and CLKO M2C P N Modified Table 8 8 CLK1_M2C_P N and CLKO 2 P N Modified Table 8 9 CLK1 M2C P N and CLKO M2C P N Modified Table 8 10 CLK1 M2C P N and CLKO P N Modified Figure 1 3 Power Supply Arrangement for FPGA Banks Modified Spec of FAN Added 11 4 Pin header and Table 11 4 pin assign of pin header Modified Figure 12 1 Default settings Modified Table 12 1 Initial Settings removed J66 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 2 inreviun 8 Table of Contents 1 Related Documents and Accessories 9 MEOS 9 ud FEAE an 9 4 Block Diagram aaa area aa 11 5 External View Of the Board ee ale 12 bi TB 6V LXZ60 LSl 12 5 2 TB FMCH STACK and 13 6 Board Specifications reete iaia 14 6 1 TB 6V LX760 LSI Board Structure ii 14 6 2 TB FMCH STACK Board 14 6 3 TB FMCH CONNECTER Board Structure i 15 6 4 Layout of TB 6V LX760 LSI Board 16 6 5 Layout of the TB FMCH STACK Board Components i 17 6 6 Layout of the TB FMCH CONNECTER Board Components 17 7 Description of Components 18 71 DDRS SDRAM
30. SDA TDO GND 7 3P3VAUX GND 3 TMS WO 2 TRST_L wo gt 7 12POV 2 GAI GND 7 3P3V 7 12POV GND N GND 7 3P3V 7 GND C2 GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 23 inreviun 8 Bank No Pin No Pin No Bank No 25 N31 2 G31 26 25 M32 3 GND 4 D33 26 5 E33 26 25 N30 6 25 P31 M31 25 8 L32 25 25 G36 25 36 34 25 11 F35 25 25 B37 12 25 A37 F37 25 14 E37 25 26 B33 15 26 C34 16 C36 25 17 D37 25 25 P30 18 25 N29 19 K32 25 20 J32 25 26 E32 21 26 F32 H29 26 23 H30 26 26 M28 24 26 L29 28 26 26 J28 26 26 L27 27 26 M27 A35 26 29 A34 26 25 R28 30 25 P28 P26 26 32 N26 26 26 P27 33 26 R27 34 A32 26 35 B32 26 25 K33 36 25 131 1 26 F30 26 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 24 inreviun 8 8 3 2 FMC2 LPC MC CC Connector The FMC connector J44 J68 is interfaced to the FPGA over 36 pairs of signal pins Of them 2 pairs are assigned to the MRC
31. Side 7 1mm Impedance Control Single Signal 50 Ohm Differential Signal 100 Ohm RoHS Pbfree RoHS Pbfree RoHS lead free solder Surface Coating Rev 3 00 Gold plating TOKYO ELECTRON DEVICE LIMITED 14 inreviun 8 6 3 TB FMCH CONNECTER Board Structure The following table shows the board structure and the specifications For details about connector locations refer to the board layout drawing Table6 3 TB FMCH CONNECTER Board Structure Category l Category Il Specification Remarks Board Structure Number of Layers 16 Dimensions 69mm x 80mm Thickness Resist Color Red Material FR 4 Height Component Side 2mm Solder Side 7 1mm Impedance Control Single Signal 50 Ohm Differential Signal 100 Ohm RoHS Pbfree RoHS Pbfree RoHS lead free solder Rev 3 00 Surface Coating Gold plating TOKYO ELECTRON DEVICE LIMITED 15 225 16 TB 6V LX760 LSI Hardware User Manual Layout of TB 6V LX760 LSI Board Components The following figure shows the dimensions of the TB 6V LX760 LSI 6 4
32. 12 0V gt 2 5V p To Veco of Virtex6 FPGA pia SE raie 39 V6_OP_A is about 6A E gt 1 2 1 5 1 8V A MAX DC DC To Vcco of Virtex6 FPGA LTM4606 V6 OP Bis about 12 0V gt 1 2 1 5 1 8V 6A MAX To Vcco VRP VRN Virtex6 DC DC FPGA and VDD VDDQ of DDR3 LTM4608 Use rate 72 17 1 5V is about 4 33A pN m To Vref of Virtex6 FPGA and i LTC3413 Use rate 44 33 of DDRS ka 12 0V gt 1 5V VTT_0 75V is about 1 33A 3A MAX To Vccaux of Spartan3 FPGA DC DG Use rate 25 other devices LTM8025 VCC_3 3V is about 0 75A 12 0V gt 3 3V DC DG 1 5A MAX To Vecint of Spartan3 LTC3417 Use rate 33 34 S3 VINT is about 0 5A 3 3V 1 2V 1 0A MAX To Vcco of Spartan3 FPGA 3 3 2 5V Use rate 70 53 VCCO25 is about 0 3A LT1763CS8 1 8 0 5A MAX Vcc of BPI flash memory 3 3V gt 1 8V Use rate 100 VCC_1 8V is about 0 051A DC DC LTM4619 4A MAX To LPC FMC 12 0V gt 2 5V Use rate 80 2 5 is about 3 2A 12 0V gt 3 3V 4A MAX To LPC FMC Use rate 88 75 3 3V Tis about 3 55A DC DC 3A MAX To LPC FMC nr a rato gt 5 is about 4A DC DC LTM4619 4A MAX To LPC FMC 12 0V gt 2 5V Use rate 80 2 5V Bis about 3 2A 12 0V gt 3 3V 4 To LPC Use rate 88 75 3 3V Bis about 3 55A DC DC 3A MAX To LPC FMC Use mee OP_SV_B is about 4A Figure10 1 Power Supply System Diagram Rev 3 00 TOKYO ELECTRON DEVICE LIMITED To LPC
33. 5 MT41J64M16LA 15 cu a Figure7 1 DDR3 Peripheral Connections Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 18 inreviun 8 7 2 SPI FLASH The TB 6V LX760 LSI board has one SPI Flash memory device Device M25P64 VMF6TP Numonyx 64 MBit Level FPGA Shifter E XC6VLX760 FFG1760C Figure7 2 SPI Flash Peripheral Connections 7 3 BPI FLASH The TB 6V LX760 LSI board has one BPI Flash memory device Device JS28F256P30TF Numonyx 256 MBit 24 1 JS28F256P30TF XOE XWE XRST xC6VLX760 FFG1760C 2 5V lt Figure7 3 BPI Flash Peripheral Connections Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 19 TB 6V LX760 LSI Hardware User Manual inreviun E 7 4 MicroSD NAND FLASH these are only for Virtex 6 configuration The TB 6V LX760 LSI board has one NAND Flash for storing Virtex 6 configuration files and one MicroSD socket The Spartan 3AN reads the data stored in the Micro SD NAND Flash memory device to configure the Virtex 6 device Device NAND Flash MT29F4G16BABWP Micron 4 G 16 bit For more information refer to the related document Configuration Method Using SD and XC3S700AN uSD CONF UserManual V6LSI x xxe pdf JTAG connector 87832 1420 VOC 3 3V SP3 FRIC SP3 SP3 Mi 3 2 P SP3 V52 SP3_VSI TOLTMS TCK CONF LI15 0 V6 DIN V6_ROWR_B V6_CSI_B V6_CCLK V6 MI2 11V6 DONE V6 INI T BV6 DOU
34. 9 LA01_N_CC AW41 12 12 AW42 LA06_P 10 GND 12 AV41 LAO6_N 11 LAO5 AT40 12 GND 12 LAOS AR40 12 GND 13 GND 12 AT42 LA10 P 14 LA09 P AR42 12 12 AU42 LA10 N 15 LAO9 N AP42 12 GND 16 GND GND 17 LA13 P AP41 12 13 AJ40 LA14 P 18 LA13_N AN40 12 13 AH40 LA14 N 19 GND GND 20 LA17 AG36 13 GND 21 LA17 CC AG37 13 13 AL42 LA18 22 GND 13 AK42 18 CC 23 LA23 AF34 13 GND 24 LA23_N AF35 13 GND 25 GND 13 AJ41 LA27 26 LA26_P AE40 13 13 AJ42 LA27 N 27 LA26 N AF40 13 GND 28 GND GND 29 3 TCK 1 SCL 30 3 TDI 1 SDA 31 3 TDO GND 32 7 3P3VAUX GND 33 3 TMS 2 34 3 12POV 35 2 GAI GND 36 7 3P3V 12POV 37 GND GND 38 7 3P3V 7 39 GND GND 40 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 29 inreviun 8 Bank No Pin No H Pin No Bank No 1 5 VREF A M2C 12 AK37 SNT L AU41 12 12 AJ36 3 GND 4 AF36 13 5 AF37 13 12 AG32 6 12 AG37 AN39 12 8 AP40 12 12 AE33 9 12 AE32 AM39 12 11 AL39 12 12 AG34 12 12 AG33 13 AK35 12 14 AJ35 12 12 AH36 12 AH35 16 AK38 12 17 AJ37 12 13 AH38 18 13 AH39 AN41 12 20 AM41 12 13 AM42 21 13 AL41 AK39 12 23 AJ38 12 13 AE37 24 13 AE38 AG38 13 26 AG39 13
35. ANDFlash 1 FUN FAN Power I Flash MM T aie j MMOX GLK 12C lt E E f INX 1 si Input FMES Power Power Power FMG2 Power Gennector5 Connector Connectors Conneetor2 Gennector1 Carrier Low Pin Carrier Low Pin Carrier Low Pin Carrier Low Pin Carrier Low Pin FMC1 Power Figure5 1 Component Side FMC Connector6 FMC Connector7 FMC Connector8 FMC Connector9 FMC Connector10 Module Low Ping LI Module Low Ping LI Module Low Pin Module Low Pin Module Low Ping i p Tu serea DT yini imas OST SALI vo 28 e 5 SEES 2 T Connector1 Connector2 Connector3 Connector4 Connector5 LI Module Low Ping 0 Module Low Ping LI Module Low Ping LI Module Low Ping LI Module Low Ping Figure5 2 Solder Side Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 12 TB 6V LX760 LSI Hardware User Manual inreviun E 5 2 TB FMCH STACK and TB FMCH CONNECTOR The TB FMCH STACK and the TB FMCH CONNECTOR permit the interconnection of multiple TB 6V LX760T LSI boards in either a horizontal or vertical configuration FMG Connector Module High Pin TB FMCH Connector Solder side FMO Connector arrire High Pin 1 1 5 VIUT A TOKYO ELECTRON DEVICE LIMITED STACK Rev 2
36. C pins of the FPGA Also LA33_P and LA33_N is not FPGA deferential signal pair pin So LA33_P N cannot use for differential signal interface The following table shows the pin mapping assignments between the FPC connector and the FPGA Table8 2 FMC2 Connector Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M 2 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 2 M2C 6 GND M2C 7 GND GND 8 LAO1 P T31 16 GND 9 LA01_N_CC T32 16 16 J40 LA06_P 10 GND 16 K39 LAO6 N 11 LAO5 N33 17 GND 12 LA05 N P32 17 GND 13 GND 17 G37 LA10 14 LA09 P P33 17 17 H36 LA10 N 15 LAO9 N N34 17 GND 16 GND GND 17 LA13 P J36 17 17 H39 LA14 P 18 LA13 N K35 17 17 G39 LA14 N 19 GND GND 20 LA17 942 16 GND 21 LA17 H41 16 16 L42 LA18 P CC 22 GND 16 L41 LA18 N CC 23 LA23 P F41 17 GND gt LA23 N E42 17 GND N GND 17 41 LA27 N 26 D42 17 17 C40 LA27_N N LA26_N D41 17 GND GND GND N 3 TOK 1 SCL 3 TDI 1 SDA TDO GND 7 3P3VAUX GND 3 TMS 2 wo gt TRST_L 7 12POV 2 GAI GND 7 3P3V 7 12POV N GND
37. D 10 TB 6V LX760 LSI Hardware User Manual inreviun 4 Block Diagram The following figure represents the block diagram of the TB 6V LX760 LSI and illustrates the assignment of various blocks and connectors to IO banks on the FPGA O O o O Virtex6 5 XC6VLX760 2 FGG1760 e 71 n O O Do Do a coc 8 9 48 I I I I 7 QIO QIO gt gt gt gt 9 S28 n di n SLX MSdIO T Figure4 1 Block Diagram Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 11 TB 6V LX760 LSI Hardware User Manual 5 External View of the Board 5 1 TB 6V LX760 LSI Gonnector10 Gonnector9 FMG Gonnector8 Gonnector7 Gonnector6 Carrier Low Pin Carrier Low Pin Garrier Low Pin Carrier Low Din Carrier Low Pin FMG10 Power FMG9 Power FMG8 Power FMG7 Power FMO6 Power DIP sw Push SW PLL OLKIN JTAG 7 PIO USE _ Sere gt EPI Flash Part PLL DDR3 I Power GroupA8B 8 3 nia FPGA Virtex6 Config Mode ie Power2 Config Area VREF B Setting B Setting GOO Setting VREF_A Setting yetem Monitor DSG 266 67M Config FPGA Config MicroSD Cordig gl I 3 ORI LED Config N
38. D 16 GND GND 17 LA13 P V1 45 45 V8 LA14 P 18 LA13 N U1 45 45 U7 LA14 N 19 GND GND 20 LA17 Y5 44 GND 21 LA17 CC Y4 44 44 AA1 LA18 22 GND 44 AA2 18 23 LA23 Y7 44 GND 24 LA23 N Y8 44 GND 25 GND 44 AC3 LA27 26 LA26 ABI 44 44 AB3 27 27 LA26 N AB2 44 GND GND GND N c 3 TCK 1 SCL 3 TDI 1 SDA TDO GND C2 N 7 3P3VAUX GND 3 TMS 2 wo gt TRST_L 7 12POV 2 GAI GND 7 3P3V 7 12POV 51 GND GND 7 3P3V 7 3P3V GND GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 39 inreviun 8 Bank No Pin No H Pin No Bank No 1 5 VREF M2C 44 ACA SNT M2C L AD3 44 44 ABA 3 GND 4 V5 45 5 V6 45 45 R4 6 45 R5 U6 45 8 T5 45 45 Ti 9 45 T2 W6 45 11 W5 45 44 AA6 12 44 AA7 13 P2 45 14 P4 45 45 P1 45 E2 16 R3 45 17 T4 45 44 AB7 18 44 AB6 W3 45 20 45 44 Wi 21 44 W2 AA4 44 23 AA5 44 44 AA9 24 44 Y9 U8 45 26 U9 45 44 AB9 27 44 AB8
39. Figure12 1 Default Settings component side Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 56 inreviun 8 The following table shows the initial settings Table12 1 Initial Settings Silk No Sod Function Setting J41 J42 Address setting for voltage monitoring J53 Use for rewriting to EEPROM of USB Chip J54 VCCO setting for Virtex6 Bank16 17 25 26 2 5V A None J55 VCCO setting for Virtex6 Bank27 28 37 38 2 5V FP_OP_B None VREF setting for Virtex6 Bank16 17 25 26 1 8V FMC_VREFA None VREF setting for Virtex6 Bank27 28 37 38 1 8V FMC_VREFB None setting for FMC1 LPC 2 5V 3 3V None VADJ setting for FMC2 LPC CC MC 2 5 3 3V 5V None VADJ setting for FMC3 LPC CC MC 2 5V 3 3V None VADJ setting for FMC4 LPC CC MC 2 5V 3 3V 5V None VADJ setting for FMC5 LPC CC MC 2 5V 3 3V 5 None J23 424 J12 432 J11 J31 J14 J34 J13 J33 J7 J27 J8 J28 J10 J30 J9 J29 J16 J36 J15 J35 VADJ setting for FMC6 LPC CC MC 2 5V 3 3V 5V None VADJ setting for FMC7 LPC CC MC 2 5V 3 3V 5V None VADJ setting for FMC8 LPC CC MC 2 5V 3 3V 5V None VADJ setting for FMC9 LPC CC MC 2 5V 3 3V None VADJ setting for FMC10 LPC CC MC 2 5V 3 3V 5V None FPGA Configuration Slave Select Map Mode setting FAN Alarm OFF SW5 1 User Rotary Switch SW6 0 User Rotary Switch SW8 14 15 16 User Slide
40. I2C communication with the FMC mezzanine card 2 GA 1 0 This has a test pad to perform the ID notification function to the FMC mezzanine card 3 TDI TDO TCK TMS TRST_L These have an onboard loopback function to enable JTAG communication from the FMC mezzanine card TCK TMS and TRST L are for test points only By default the loopback connection is not enabled since a 0 ohm resistor is not mounted FMUT LA NZ D28 END FI PAD86 FADO 1 F1 D29 me SCL 8499 i x F1 TDI 030 TOL PAD73 PAD O_N FI_IDO D31 TDO PAD74 PAD 2 ap FI SDA FI TMS PAD7Z5PAD 1 F1 TMS e FI TRST PAD77 PAD F1 TRST FI GAl PAD81 PAD 1 FI_GAI OP_3 3V 39 3C3V OP_33V_T ASP 134603 01 DGND Figure8 4 SDA SCL GA1 0 TDI TDO Circuit 4 PG_C2M This has a test point and a pull up function to enable level output to the FMC mezzanine card OP_3 3V_T F1 PG C2M PAD84 PAD Figure8 5 PG_C2M Circuit 5 VREF_A_M2C This has a test pad to monitor the H1 pin of each FMC3 4 5 8 9 and 10 connector F9 VREF M2C la PAD105 PAD F9 VREF VREF A M2C PRSNT M2C L Figure8 6 VREF A M2C Circuit Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 43 inreviun 8 This connects the H1 pin of the FMC1 and 2 connectors to the FMC_VREFA and the H1 pin of the FMC6 7 connectors to the FMC_VREFB The following VREF circuit is enabled with J23 and J24 settings FMC_VREFA B gt V6_OPVREF_A B
41. Lights when Virtex6_ VAUX 2 5V is OK Lights when Virtexe VCCO25 2 5V is OK Lights when VCC_1 5V 1 5V is OK Lights when VCC_3 3V 3 3V is OK Lights when Spartan3_VINT 1 2V 53 25 2 5V is OK Lights when VTT_0 75V 0 75V is OK Lights when OP_3 3V_T 3 3V and OP_2 5V_T 2 5V is OK Lights when OP_3 3V_B 3 3V and OP_2 5V_B 2 5V is OK Lights when FP_OP_A 1 2V 1 5V 1 8V is OK Lights when FP_OP_B 1 2V 1 5V 1 8V is OK Lights when OP_5V_T 5V is OK Lights when OP_5V_B 5V is OK Lights when Power Monitor is in an Alert state D34 Green Lights when Power Monitor is OK D32 Green Lights when Sparten3 Config is completed D33 Green Lights when Virtex6 Config is completed 5V_VADJ1 10 Red Lights when FMC VAD is 5V 3 3V_VADJ1 10 Green Lights when FMC VADJ is 3 3V 2 5V_VADJ1 10 Yellow Lights when FMC VADJ is 2 5V D 31 29 Red Connects to Spartan3 for test D 60 57 Green D 98 91 Green D 102 101 Green Connects to Virtex6 for test D 100 99 Red Rev 3 00 Connects to Virtex6 for test TOKYO ELECTRON DEVICE LIMITED 52 TB 6V LX760 LSI Hardware User Manual inreviun E 11 2 Switch The following table shows the destination of the onboard switch to be connected and its function Table11 2 Switch Functions Switch Name Functi
42. Switch SW17 18 19 PLL Slide Switch The bold red characters in the Function field indicate a default setting m SW7 AII Off Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 57 TB 6V LX760 LSI Hardware User Manual INFEVIUTI NE TOKYO ELECTRON DEVICE PLD Solution Dept PLD Division URL http solutions inrevium com E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4016 FAX 81 45 443 4058 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 58
43. T EUSY XCeVLX760 FFG1760C Sparten3AN XC3S7 00AN FG484 SD card connector 2808 05WB MCG D 15 0 RXBXRE XCE CLE ALE XWE MAT NAND FLASH MT29F4G16BAEW Figure7 4 CONFIG Peripheral Connections The following figure shows the JTAG chain of Virtex 6 and Spartan 3AN The Spartan 3AN comes with burned ROM data for configuration No need to change it if itis used in an ordinary way lO CN12 2908 05WB MG d DATO VO eta Ve vacas DAT3 V0 87832 1420 DAT2 Spartan 3AN MicroSD TMS Pind CLK DATI 4 TEK EnS TDO Pin8 TDI Pinto co wo Figure7 5 JTAG Chain Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 20 TB 6V LX760 LSI Hardware User Manual inreviun E 8 Interfaces 8 1 USB and 2 USB Connector Type B 67068 8000 USB PHY CY7C68013A 56PVXC 12C Connector Pin Header A2 2PA 2 54DSA V6 USB PA 7O USB Usgen V6 USB PE 7O USB_PE 7 0 EUS 67088 8000 V6 USB PD 7 0 USB PD 7 O Ve USB ILO BUF USE C ILI2 0 PHY 453 V6_USE_XRST USB XRST CY7C88013 SDA y 12C V6 USB IFCLK USB IFCLK A 56PVXC 2 0811 V6_USB_CLK USB CLK 5CL 4 EE V6 USB
44. The FMC connector J48 J72 is interfaced to the FPGA over 38 pairs of signal pins Of them 2 pairs are assigned to the MRCC pins of the FPGA Also LA33_P and LA33_N is not FPGA deferential signal pair pin So LA33_P N cannot use for differential signal interface The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 6 FMC6 Connector Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M 2 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 2 M2C 6 GND M2C 7 GND GND 8 LAO1 P A31 27 GND 9 LAO1 N CC 831 27 27 H28 LA06_P 10 GND 27 J27 LA06_N 11 LA05_P B28 27 GND 12 LA05 N B29 27 GND 13 GND 27 D30 LA10 14 LA09 P L25 27 27 E29 LA10 N 15 LAO9 N M24 27 GND 16 GND GND 17 LA13 P G27 27 27 H26 LA14 P 18 LA13 N G26 27 27 J26 LA14 N 19 GND GND 20 LA17 K23 28 GND 21 LA17 923 28 28 026 LA18 22 GND 28 D25 LA18 CC 23 LA23 P A25 28 GND gt LA23_N A24 28 GND N GND 28 E24 LA27 P N 26 24 28 28 25 27 N LA26_N H25 28 GND GND GND N 3 TOK 1 SCL 3 TDI 1 SDA TDO GND 7 3P3VAUX GND 3 TMS 2 w
45. developed for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within 2 two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 8 inreviun 8 1 Related Documents and Accessories Related documents All documents relating to this board can be downloaded from our website Please see attached Welcome latter on the products Board accessories FMC spacer set 2 Overview This document describes the design specification of the TB 6V LX760 LSI board The design covers the TB 6V LX760 LSI board and two FMC option boards TB FMCH STACK and TB FMCH CONNECTOR 3 Feature FPGA Devices Memory DDR3 SDRAM DDR3 SDRAM CH2 NAND FLASH SPI Flash BPI Flash Interface FMC LPC FMC LPC USB SD CARD Expansion Connector Others LTC2978CUP Clock 2 LED SW Rotary SW Rev 3 00 XC6VLX760 2FFG1760 XC3S700AN 4FGG484C It is only for Virtex 6 Configuration 1Gbit 8Meg x 16bit x 8Bank x 2 1Gbit 8Meg x 16bit x 8Bank x 2 4G 16bit x 1 for
46. er supplies for Virtex V6 FPGA Banks that are mounted on the TB 6V LX760 LSI board NCCO VccoVar XEL2V or HL5V or 1 m Vecovaror 42 5V E E gt Var o 2 5V 8 8 8 R 4 L5V gt L5V 8 8 gt 2 8 a Sne gt MI 1 5 Var o 2 5V VREF A M2C VccoVar or 42 5V VrefVar E 40 75V or 409V Vref Fixed 40 75V gt L5V wc E Figure10 3 Power Supply Arrangement for FPGA Banks 10 5 Power Supply for Fan FAN Pin Header MOLEX s 5045 03A 50PS mounted FAN Specification draft Rotation speed 3800 min rated current 0 11A and rated voltage 12V The following figure shows the FAN pin header connection IW VIN 12V R amp 35 tk Sparten3A XC3S700AN FG484 IO an A OPS FB5S24CS30 DGND Figure10 4 Fan Connector Peripheral Circuit Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 51 TB 6V LX760 LSI Hardware User Manual 11 LED SW JUMPER 11 1 LED The following table describes the function of the onboard LEDs LED Name Table11 1 LED Functions Function inreviun Remarks D1 Green Lights when 12V input power is ON Lights when Virtex6_VINT 1 0V is OK
47. inreviun 8 Rev 3 00 TB 6V LX760 LSI Hardware User Manual Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History Version Date Description Publisher Rev 1 xx 2009 xx xx Preliminary Rev 2 00 2010 05 06 Initial release Sen Odajima Rev 2 01 2010 06 25 Added J66 J53 to figure 12 1 Yoshioka Modified table 12 1 Added J66 J53 Separate SW5 SW6 Changed initial settings No1 6 7 18 20 21 Rev 2 02 2010 07 07 Modified table 6 1 table 6 2 table 6 3 Yoshioka Modified figure 6 1 figure 7 3 Delete wrong information on 8 3 FMC connector Modified explaining of clock signal of each FMC connectors Modified figure 9 1 Add DIP SW pin number on table 9 1 and 9 2 Changed connector for FAN on 6 5 Power supply for FAN Rev 2 03 2012 04 24 Modified Q ty of TB FMCH STACK and Yoshioka Q ty of TB FMCH CONNECTRO Rev 3 00 2012 07 17 Modified revision of pin assign table Yoshioka Modified PCB dimension and surface coating Modified External view Modified Table 8 1 LAO6_P N LA33_P N CLK1_M2C_P N and CLKO M2C P N Add comment to Table 8 1 8 2 8 6 8 7 LA33_P N these are not differential pair Modified Table 8 2 LA15_P N LA19 P N LA33_P N CLK1_M2C_P N and CLKO_M2C_P N Modified Table 8 4 CLK1_M2C_P N and CLKO_M2C_P N Modified Table 8 5 CLK1_M2C_P N and CLKO_M2C_P N Modified Table 8 6 LA11_P N LA33_P N CLK1_M2C_P N and CLKO M2C P N
48. nector LPC Connector Figure8 3 Low Pin Count Pinouts 22 Rev 3 00 O ELECTRON DEVICE LIMITED inreviun 8 8 3 1 FMC1 LPC MC CC Connector The FMC connector J43 J67 is interfaced to the FPGA over 36 pairs of signal pins Of them 1 pair is assigned to the GC pin and 1 pair is assigned to the MRCC pins of the FPGA Also LA33_P and LA33_N is not FPGA deferential signal pair pin So LA33_P N cannot use for differential signal interface The following table shows the pin mapping assignments between the FMC connector and the FPGA Table8 1 FMC1 Connector Pinouts on Component and Solder Sides Bank No Pin No D PinNo Bank No GND 1 4 PG_C2M DPO C2M 2 GND DPO C2M N 3 GND GND 4 GBTCLK0 M2C GND 5 GBTCLKO M2C N DPO M2C P 6 GND DPO M2C N 7 GND GND 8 LAO1 P CC A39 26 GND 9 LAO1 CC B38 26 26 P25 06 10 GND 26 R25 LAO6 11 LAO5 H35 26 GND 12 LA05 N H34 26 GND 13 GND 25 D38 LA10 P 14 LA09 P D35 25 25 C38 LATO 15 LAO9 N E34 25 GND 16 GND GND 17 LA13 P C35 25 25 G34 LA14 P 18 LA13_N B34 25 25 H33 LA14 N 19 GND GND 20 LA17 P M29 26 GND 21 LA17 N CC N28 26 26 K30 LA18 22 GND 26 J31 LA18 N_CC 23 LA23 P C33 25 GND 24 LA23 N D32 25 GND 25 GND 26 G33 LA27 26 LA26_P A36 25 26 G32 LA27_N 4 LA26_N B36 25 GND GND GND 3 TCK 1 SCL 3 TDI 1
49. o gt TRST_L 7 12POV 2 GAI GND 7 3P3V 7 12POV N GND GND 7 7 3P3V GND GND gt 7 3P3V Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 33 inreviun 8 Bank No Pin No Pin No Bank No 28 F26 2 C31 27 28 F25 3 GND 4 D28 27 5 E28 27 27 D31 6 27 E30 G29 28 8 F29 28 27 A30 9 27 A29 23 27 11 N24 27 27 N25 12 27 M26 29 27 14 28 27 27 G28 15 27 F27 16 L26 27 17 K27 27 28 E27 18 28 D27 19 K24 28 20 J25 28 28 A27 21 28 A26 G23 28 23 H23 28 28 F22 24 28 G22 C23 28 26 B23 28 27 M22 27 27 M21 B22 28 29 A22 28 28 B24 30 28 624 C23 28 32 023 28 28 24 28 F24 34 N21 27 35 22 27 28 27 36 28 124 22 28 GND D22 28 7 VADJ GND GND 7 VADJ Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 34 inreviun 8 8 3 7 FMC7 LPC MC CC Connector The FMC connector J49 J73 is interfaced to the FPGA over 36 pairs of signal pins Of them 2 pairs are assigned to the MRCC pins of the FPGA Also LA33_P and LA33_N is not FPGA deferential signal pair pin
50. on DIP_SW Destination RN m Pin Order Function 1 V6 MO Slide Switch for 2 V6 M1 SP3AN FPGA Configuration 3 V6 M2 4 V6 FPGA V6 PROG B Rotary Switch for Test SP3AN FPGA MODE 3 0 Rotary Switch for Test SP3AN FPGA AREA 3 0 Slide Switch for Test V6 FPGA V6 DIPSW 3 0 Slide Switch for Test V6 FPGA V6 DIPSW 7 4 Slide Switch for Test V6 FPGA V6 DIPSWT 1 1 8 Slide Switch for Test V6 FPGA V6 DIPSW 15 12 Push Switch for Test V6 FPGA V6 PUSHSWO Push Switch for Test V6 FPGA V6 PUSHSW1 Push Switch for Test V6 FPGA V6 PUSHSW2 Push Switch for Test V6 FPGA V6 PUSHSW3 Slide Switch for PLL Setting ICS8430AYI M 3 0 Slide Switch for PLL Setting ICS8430AY M 7 4 Slide Switch for PLL Setting ICS8430AY N 2 0 M8 Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 53 TB 6V LX760 LSI Hardware User Manual inreviun E 11 3 JUMPER The following figure shows the onboard jumper functions Table11 3 Jumper Functions Jumper Name Function Remarks 1 Pull up J41 J42 NC pull up pull down setting for Monitor ASEL 1 0 pin 2 ASELO 1 3 Pull down 1 2 FP OP A VCCO A power supply selection for Virtex 6 FPGA 3 4 V6 VCCO A 5 6 2 5V 1 2 FP OP B VCCO B power supply selection for Virtex 6 FPGA 3 4 V6 VCCO B 5 6 2 5V 1 V6 OPVREF A V6 OPVREF A power supply selection for Virtex 6 FPGA 2 FMC VREFA 3 4 FP OP A 1 V6 OPVREF B J24 V6 OPVREF B power supply selection for Virtex 6
51. ot touch a cooling fan As a cooling fan rotates at high speed do not put your hand close to it or touch it Otherwise it may cause injury Do not place the product in an unstable position Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash on it Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may be damaged and break down or it may cause a fire or electric shock 00000 X Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 7 TB 6V LX760 LSI Hardware User Manual inreviun B A Caution Do not use or place the product in the following locations e Humid and dusty locations e Airless locations such as closet or bookshelf e Locations which receive oily smoke or steam e Locations exposed to direct sunlight e Locations close to heating equipment e Clo
52. sed inside of a car where the temperature becomes high e Static locations e Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the product may be damaged B Disclaimer This product is a Xilinx Virtex6 FPGA evaluation board Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been
53. sed to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled Danger incorrectly Indicates the possibility of serious injury or death if the product is handled N warning incorrectly the product is handled incorrectly Indicates the possibility of injury or physical damage in connection with property if A Caution The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch KG M Do not disassemble the product Do attempt this Rev 3 00 TOKYO ELECTRON DEVICE LIMITED 6 inreviun 8 A Warning In the event of a failure disconnect the power supply Ifthe product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact technical support If an unpleasant smell or smoking occurs disconnect the power supply Ifthe product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation inspection modification or repair contact our sales personnel Do n
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