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F2MC-8FX MB95130/MB Series HARDWARE MANUAL

1. eet Oe st 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SWT2 SWTO Number o Cycles EM k About 1 00s About 0 5s About 0 25s About 0 125s About 62 44ms 2 2 Fo About 31 19ms 2 2 Fc About 15 56ms 2 2 Fc About 7 75ms 27 2 Fc About 3 85ms 28 2 About 1 89ms 25 2 Fe About 915 5 us 2 2 Fc About 427 2 us 23 2 Fc About 183 1 us 2 2 Fc About 61 0 us 2 2 Fe 0 0 ps 21 2 Fo 0 0 us OoojoLj 2j ojoooou OoL jooji ojoL L1 IJjoo2 O o0230 oj 0 o0 Jilo o R W Readable writable Read value is the same as write value Initial value For mask ROM products initial oscillation stabilization time depends on the option setting when ordering mask ROM CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 59 CHAPTER 6 CLOCK CONTROLLER 6 5 Oscillation Stabilization Wait Time Setting Register WATR MB95130 MB Series Table 6 5 1 Functions of Bits in Oscillation Stabilization Wait Time Setting Register WATR 1 2 Bit name Function SWT3 SWT2 SWTI SWTO Sub Clock Oscillation stabilization wait time select bits 60 Set the sub clock oscillation stabilization wait time SWT
2. External interrupt control register EIC Address bit7 bit5 bit4 bit3 bit2 bit bito Initial value 0048 EICOO ElR1 SL11 SL10 EIE EIRO 5101 SLOO EIEO 00000000 R RMI W R W R W RW RRM W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bito Initial value 00494 EIC10 ElR1 5111 SL10 EIE1 EIRO SLO1 SLOO EIEO 00000000 R RMIJW R W R W R W RRMDW R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 004A EIC20 ElR1 5111 SL10 EIE1 EIRO SLO1 SLOO EIEO 00000000 R RMI W RW R W RW RRM W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 004 EIC30 SL11 SL10 EIE EIRO 5101 SLOO EIEO 00000000 R RM1 W R W R W RW RRM W R W R W R W R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction 292 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT MB95130 MB Series 18 5 Registers of External Interrupt Circuit 18 5 1 External Interrupt Control Register EICOO The external interrupt control register EICOO is used to select the edge polarity for the external interrupt input and control interrupts B External Interrupt Control Register EICOO Figure 18 5 2 External Interrupt Control Regi
3. Hysteresis ERES HN D el 0 Peripheral function input je Peripheral function input enable H Peripheral function output enable f Only 1 C T 1 Peripheral function output j A 9 i a i a Automotive s Pull up A 0 cmos He Ld 4 P ch PDR read 1 4 gt 4 Pin gt PDR 0 t PDR write In bit operation instruction A DR read o 7 2 E o 2 Stop Watch SPL 1 Internal bus Only P04 is selectable ILSR2 read ILSR2 ILSR2 write A MSAN CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 111 CHAPTER 9 I O PORT MB95130 MB Series 9 2 1 Port 0 Registers This section describes the port 0 registers E Port 0 Register Function Table 9 2 2 lists the port 0 register functions Table 9 2 2 Port 0 Register Function Register name Read read modify write PDRO Pin state is L level PDR register value is 0 As output port outputs L level Pin state is H level PDR register value is 1 As output port outputs H level Port input enabled DDRO Port output enabled Pull up disabled Pull up enabled PULO Analog input enabled AIDRL Port input enabled Hysteresis input level selection ILSR
4. 1 Receiving side of serial clock external serial clock reception LIN synch break generation bit mode 3 Write Read No effect 1 LIN synch break generation 0 is always read R W Readable writable Read value is the same as write value R WX Read only Readable writing has no effect on operation RO W Write only Writable 0 is read RX WO Reserved bit Write value is always 0 read value is undefined X Indeterminate Initial value Unused when SSM 0 in operation mode 2 Reserved bit The read value is indeterminate 0 is always set 376 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 4 Registers of LIN UART Table 22 4 5 Functions of Each Bit in LIN UART Extended Communication Control Register ECCR Bit name Function The read value is indeterminate Reserved bit o 0 is always set Setting this bit to 1 in mode 3 generates a LIN synch break which has the length specified by LBLO 1 in the ESCR This bit should be 0 in mode 0 1 and 2 Select sending side receiving side of serial clock in mode 2 When sending side 0 is selected generate a synchronous clock When receiving side 1 is selected receive an external serial clock This bit is fixed to 0 in modes 0 1 and 3 Modify this bit only when the SCR TXE bit is 0 Note When receiving side of serial clock is
5. 223 Operation of Interval Timer Function One shot Mode 219 Operation of PWC Timer Function 229 Operation of PWM Timer Function Fixed cycle Mode 225 Operation of PWM Timer Function Variable cycle Mode 227 Port 0 Register Function uuusse 112 Port 1 Register 117 Port F Register Function esses 122 Port G Register Function eese 127 PWC Timer Function esee 197 PWM Timer Function Fixed cycle Mode 196 PWM Timer Function Variable cycle Mode 196 When Interval Timer Input Capture or PWC Function Has Been Selected 234 G General purpose Register Configuration of General purpose Registers 41 Features of General purpose Registers 42 H Hardware Hardware Connection Example 194 Hardware sequence flag Hardware sequence flag 472 Hardware Trigger Hardware Trigger eines 281 Circuit VO Circuit iter ete 16 Map WO Maps M 494 Ports Overview of I O Ports eeeeeeeeeseess 108 ILR Interrupt Level Setting Registers ILRO to ILR5 Configuration 98 Input In
6. 271 17 5 8 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 272 17 5 4 16 bit PPG Status Control Register Upper Lower PCNTHO PCNTLO 273 17 6 Interrupts of 16 bit PPG Time aurae nadine erected ee ean te ue doc eue dan 277 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example 278 17 8 Notes on Using 16 bit PPG Timer sse nennen tenere sitne nennen 282 17 9 Sample Programs for 16 bit PPG 283 vi CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT eere 287 18 1 Overview of External Interrupt Circuit 288 18 2 Configuration of External Interrupt Circuit essssssssssessseneeeee eene ene 289 18 3 Channels of External Interrupt Circuit 290 18 4 Pins of External Interrupt Circuit essent nennen 291 18 5 Registers of External Interrupt Circuit essssssessessseeeenenneneeen eene enne nnne 292 18 5 1 External Interrupt Control Register EICOO ssssssssseseseeeeenenenn nennen 293 18 6 Interrupts of External Interrupt Circuit nnne nenas 295 18 7 Explanation of External Interrupt Circuit Operations and Setup Proced
7. O Used bit X Unused bit A Only ECCR SSM 1 available Reception interrupt Each flag bit in the LIN UART serial status register SSR is set to 1 when any of following operation occurs in reception mode Data reception completed When the reception data is transferred from the serial input shift register to the LIN UART reception data register RDR RDRF 1 Overrun error When the following serial data is received when RDRF 1 and the RDR is not read by the CPU ORE 1 Framing error When the stop bit reception error occurs FRE 1 Parity error When the parity detection error occurs PE 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 379 CHAPTER 22 LIN UART 22 5 Interrupt of LIN UART MB95130 MB Series A reception interrupt request is generated if the reception interrupt is enabled SSR RIE 1 when any of the above flag bits is 1 flag is automatically cleared to 0 by reading the LIN UART reception data register RDR All of error flags are cleared to 0 by writing 1 to the reception error flag clear bit CRE in the LIN UART serial control register SCR Note For the CRE bit disable the reception operation RXE 0 first and then clear the reception error flags If an error flag is cleared before the reception operation is disabled the reception will be aborted at that time and resume later This may result in a data reception error LIN synch break i
8. TMCRO TO1 TOO IIS MOD FE11 FE10 FEO1 FEOO TOODR TO1DR Sets interval time counter compare value O Used bit x Unused bit 1 Set 1 0 Set 0 In interval timer function free run mode enabling timer operation TOOCRO TOOCR1 STA 1 causes the counter to start counting from 00g at the rising edge of a selected count clock signal When the counter value matches the value in the 8 16 bit compound timer 00 01 data register TOODR TOIDR the timer output bit TMCRO TOO TO1 is inverted and the interrupt flag TOOCR1 TO1CRI IF is set to 1 The counter continues to count and when the count value reaches it restarts counting at 00g to continue The timer outputs a square wave as a result of this continuous operation The value of the 8 16 bit compound timer 00 01 data register TOODR TOIDR is transferred to the temporary storage latch comparison data storage latch in the comparator either when the counter starts counting or when a counter value comparison match is detected Writing 00g to the 8 16 bit compound timer 00 01 data register is prohibited When the timer stops operation the timer output bit TMCRO TOO TO1 holds the last value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 223 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 9 Operating Description of Interval Timer Function Free run Mode MB951 30 MB Series Figure 15 9 2 Operating Diagram of Interval Timer Funct
9. sssssssssssseseeeenee eene nnne 234 15 16 Notes on Using 8 16 bit Compound Timer 236 CHAPTER 16 8 16 BIT PPG ce usc cU re hus 3 yu Ru E oras season ia aa 237 16 1 Overview of 8 16 bit PPG a a a inni iaaa tia diaaa aae 238 16 2 Configuration of 8 16 bit PPG 239 16 3 Channels of 8 16 bit PP Gis yiia a iniaa ete eet cte to Ed PEL th athe ede eee ege dde 241 16 4 Pins of 8 16 Dit PPG iue o itte tee teret ee etenim det ita 242 16 5 Registers of 8 16 bit nens intente rrr s enn a Aaa R NEAS ieai nennen 243 16 5 1 8 16 bit PPG Timer 01 Control Register Ch 0 PCO1 244 16 5 2 8 16 bit PPG Timer 00 Control Register ch 0 PCOO 246 16 5 8 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register PPSO1 PPSOO 248 16 5 4 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register PDSO1 PDSO00 249 16 5 5 8 16 bit PPG Start Register 2 3 250 16 5 6 28 16 bit PPG Output Inversion Register REVO 251 16 6 Interrupts of 8 16 bit PPG sssssssssssss
10. esses 328 Pins Related to UART SIO 316 Registers and Vector Table Related to UART SIO 327 Registers Related to UART SIO 318 Sample Programs for UART SIO 342 UART SIO Dedicated Baud Rate Generator Block Diagram of UART SIO Dedicated Baud Rate GONE ALOR ec ia ecu eun nie 348 Channels of UART SIO Dedicated Baud Rate Generator ies 349 Registers Related to UART SIO Dedicated Baud Rate Generator 350 UART SIO Serial Input Data Register UART SIO Serial Input Data Register UART SIO Serial Mode Control Register UART SIO Serial Mode Control Register 1 SMC10 nir dL DR ed AM cate Ud Et 319 UART SIO Serial Mode Control Register 2 SMC20 UICE 321 UART SIO Serial Output Data Register UART SIO Serial Output Data Register e aes 326 UART SIO serial status and data Registers UART SIO serial status and data register SSRO sessesssse 323 V Variable cycle Mode Operation of PWM Timer Function Variable cycle Mode 227 PWM Timer Function Variable cycle Mode 196 Vector Table Register and Vector Table for Interrupts of Time base etat 139 Register and Vector Table Related to 8 10 bit A D Converter Interrupts ss 439 Register and Vector
11. sess 71 Table of Interrupt Causes eese 498 Timer 00 Interrupt eene 217 Timer 01 Interrupt eee 217 Transmit interrupt eeeeeeeeeeees 327 380 Transmit Interrupt Generation and Flag Set Timing E 385 Transmit Interrupt Request Generation Timing 386 Interrupt level setting register Interrupt Level Setting Registers ILRO to ILR5 Configuration eeeeeseeeeeeeeee 98 Interrupt Pin Selection Circuit Block Diagram of Interrupt Pin Selection Circuit 303 Interrupt Pin Selection Circuit 302 Operation of Interrupt Pin Selection Circuit 309 Pins Related to Interrupt Pin Selection Circuit 304 Registers Related to Interrupt Pin Selection Circuit a 305 Interrupt pin selection circuit control register Interrupt pin selection circuit control register Interrupt request An Interrupt Request may Suppress Transition to Standby 71 Interrupt Requests from Peripheral Resources 96 Interval Interrupt when Interval Function is in Operation 138 Interval Timer Interrupt when Interval Timer Function is in Operation Watch Interrupts esses 162 Interval Timer Function 132 156 Interval Timer Function Continuous Mode 196 Interval Timer Function Free ru
12. 332 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 7 Explanation of UART SIO Operations and Setup Procedure Example Q Start bit detection and confirmation of receive data during reception The start bit is detected by a falling of the serial input followed by a succession of three L levels after the serial data input is sampled according to the clock BRCLK signal provided by the dedicated baud rate generator with the reception operation enable bit RXE set to 1 When the first H L L L train is detected in a BRCLK sample therefore the current bit is regarded as the start bit The frequency quartered circuit is activated upon detection of the start bit and serial data is inputted to the reception shift register at intervals of four periods of BRCLK When data is received sampling is performed at three points of the baud rate clock BRCLK and data sampling clock DSCLK and received data is confirmed on a majority basis when two bits out of three match Figure 20 7 5 Start Bit Detection and Serial Data Input RXE Serial data input 010 Start bit C Start bit detection A Counter divided by 4 x Y Y i 5 X 3 Xo X i Y 8 X UUSES A AAA AAA AAA A Sampling at three points to determine 0 or 1 on a majority basis when two bits out of three match Reception shift register X y DO X D1 X
13. 250 8 16 bit PPG Timer 00 Control Register ch 0 PCO0 ctt te beet ees 246 534 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register 501 500 248 8 16 bit Timer 00 01 Duty Setup Buffer Register 801 00 249 8 16 bit PPG Timer 01 Control Register ch 0 244 External Interrupt Control Register EICOO 293 List of Registers of External Interrupt Circuit orie aie cte a a neues 292 One shot Mode MDSE of PCNTHO Register bit 521 itte be iid docs 280 Port 0 Register Function uus 112 Port 1 Register Function ssessseses 117 Port F Register Function eeesesesssss 122 Port G Register Function 127 PWM Mode MDSE of PCNTH Register bit 320 nene dedere e rine 278 Registers and Vector Table Related to Interrupts of 16 bit PPG 277 Registers and Vector Table Related to Interrupts of 8 16 bit 252 Registers and Vector Table Related to Interrupts of External Interrupt Circuit 295 Registers and Vector Tables Related to Interrupts of 8 16 bit Compound 218 Registers of 16 bit PPG Timer 269 Registers of 8 16 bit PPG 243 Registers Related to
14. 410 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART 22 7 6 X Master slave Mode Communication Function Multi processor Mode Operation mode 1 allows communication between multiple CPUs connected in master slave mode It can be used as a master or slave B Master Slave Mode Communication Function To operate the LIN UART in multiprocessor mode operation mode 1 the settings shown in Figure 22 7 13 are required Figure 22 7 13 Settings of LIN UART Operation Mode 1 bit15 biti4 bit13 bit 2 bit bitiO bit9 bits bit7 bit6 bits bits bit2 bit bito SCR SMR PEN P SBL CL AD CRE RXE TXE MD1 MDO EXT REST UPCL SCKE SOE Mode 1 gt x 0 0 1 0 0 0 SSR Set conversion data during writing RDR TDR ORE ERE DRE PARE abs HE Retain reception data during reading Mode 1 gt X ESCR ECCR LBIE LBD LBL1 LBLO SOPE SIOP CCO scEs Peser LBR MS SCDE ssm Reser RBI TBI Mode 1 gt X X X x 0 0 0 x X X x 0 Used bit Unused bit Set to 1 Set to 0 Bit correctly set automatically Inter CPU Connection For master slave mode communication a communication system is configured by connecting between one
15. f D IRQ13 PPG timer 01 Y n LOAD pee gt CLK xp 0 8 bit down counter _ stop PPG timer 01 1 m PENO1 j PPGO1 Edge detection gt BORROW PIE1 PUF1 POENI Lo D IRQ12 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 239 CHAPTER 16 8 16 BIT PPG 16 2 Configuration of 8 16 bit PPG MB951 30 MB Series Counter clock selector The clock for the countdown of 8 bit down counter is selected from eight types of internal count clocks 8 bit down counter It counts down with the count clock selected with the count clock selector Comparator circuit The output is kept H level until the value of 8 bit down counter is corresponding to the value of 8 16 bit PPG duty setup buffer register from the value of 8 16 bit set buffer register of PPG cycle Afterwards after keep L level the output until the counter value is corresponding to 1 it keeps counting 8 bit down counter from the value of 8 16 bit PPG cycle setup buffer register 8 16 bit PPG timer 01 control register PCO1 The operation condition on the PPG timer 01 side of 8 16 bit PPG timer is set 8 16 bit PPG timer 00 control register PC00 The operation mode of 8 16 bit PPG timer and the operation condition on the PPG timer 00 side are set 8 16 bit PPG timer 01 00 cycle setup buffer register ch 0 PPS01 ch O PPSO00 The compare value for the cycle of 8 16 bit PPG timer
16. Has the main clock oscillation started Reset state 1 oscillation stabilization wait YES Oscillation Main clock restarts operation CR clock Oscillation operation halted CSV reset generated Reset is cleared CR clock operation External reset generated CSV Clock supervisor 1 After the power is turned on the main clock operation starts after the oscillation stabilization wait time generated by the main clock oscillation has elapsed 2 If the main clock halts at power on the device remains in the reset state oscillation stabilization wait state The operation changes to the main clock after the oscillation restarts and the oscillation stabilization wait time elapsed 3 If an oscillation halt is detected during main clock operation the operating clock is switched to the CR clock and a reset is generated 4 If the main oscillation continues oscillation does not halt the device continues to run using the main clock 5 If an external reset occurs during the CR clock operation operation changes to the main clock However if the oscillation is halted at this time another CSV reset is generated and the device returns to CR clock operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 461 CHAPTER 25 CLOCK SUPERVISOR 25 4 Operations of Clock Supervisor MB95130 MB Series E Example Startup Flowchart when using the Clock Supervisor Inserting checking proc
17. Initial value 000010008 TIE Transmit interrupt request enable bit 0 Disable transmit interrupts 1 Enable transmit interrupts RIE Reception interrupt request enable bit 0 Disable reception interrupts 1 Enable reception interrupts BDS Transfer direction selection bit 0 1 LSB first transfer from the least significant bit MSB first transfer from the most significant bit TDRE Transmit data empty flag bit Transmit data register TDR has data Transmit data register TDR is empty Reception data register RDR is empty Reception data register RDR has data FRE Framing error flag bit 0 No framing error 1 Framing error exists ORE Overrun error flag bit 0 No overrun error 1 Overrun error exists PE Parity error flag bit 1 0 Not parity error Parity error exists R W Readable writable Read value is the same as write value R WX Read only Readable writing has no effect on operation 370 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series Table 22 4 3 Functions of Each Bit in serial status register SSR Bit name Function PE Parity error flag bit Detect a parity error in received data This bit is set to 1 when a parity error occurs during reception with PEN 1 and cleared by writing 1 to the CRE bit in the LIN UART serial control register SCR Output
18. Note Figure 22 5 4 does not show all transmissions in mode 0 It only shows 8P1 P even parity or odd parity No parity bit is transmitted in mode 3 or in mode 2 with SSM 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 385 CHAPTER 22 LIN UART 22 5 Interrupt of LIN UART MB95130 MB Series E Transmit Interrupt Request Generation Timing When TDRE flag is set to 1 if the transmit interrupt is enabled SSR TIE 1 a transmit interrupt is generated Note Since the TDRE bit is initially set to 1 a transmit interrupt is generated immediately after the transmit interrupt is enabled SSR TIE 1 Be careful with the timing for enabling the transmit interrupt since the TDRE bit can be cleared only by writing new data to the LIN UART transmit data register TDR Refer to APPENDIX B Table of Interrupt Causes for the interrupt request numbers and vector tables of all peripheral functions 386 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 6 LIN UART Baud Rate 22 6 LIN UART Baud Rate One of the following can be selected for the LIN UART input clock send receive clock source e Input a machine clock into a baud rate generator reload counter Input an external clock into a baud rate generator reload counter Use the external clock SCK pin input clock directly E LIN UART Baud Rate Selection You can select one of the following three diffe
19. 0 505020 0 100 10 020 008 004 004 0 60 0 15 Stand off 024 006 Dimensions in mm inches Note The values in parentheses are reference values Please confirm the latest Package dimension by following URL http edevice fujitsu com package en search CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED CHAPTER 1 DESCRIPTION 1 7 Pin Description 1 7 Pin Description MB95130 MB Series Table 1 7 1 shows pin description The alphabet in the I O Circuit Type column of Table 1 7 1 corresponds to the one in the Type column of Table 1 8 1 E Pin Description Table 1 7 1 Pin Description 1 2 Pin name circuit type Function General purpose I O port General purpose I O port for large current Operating mode designation pin Main clock oscillation input pin Main clock oscillation input output pin Power supply pin GND Power supply pin SIn I AD nm nu IAJ nm Capacity connection pin 2 1 PG1 X0A Single clock product is general purpose port PG2 Dual clock product is sub clock input output oscillation pin 32 kHz Single clock product is general purpose port PG1 Dual clock product is sub clock input oscillation pin 32 kHz RST Reset pin AVcc A D converter power supply pin A D converter powe
20. CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 333 CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example Q Transmission in asynchronous clock mode Use UART SIO serial mode control register 1 SMC10 to select the serial data direction endian parity non parity parity polarity stop bit length character bit length and clock The following two procedures can be used to initiate the transmission process Set the transmission operation enable bit TXE to 1 and then write transmit data to the serial output data register to start transmission Write transmit data to the serial output data register and then set the transmission operation enable bit TXE to 1 to start transmission Transmit data is written to the UART SIO serial output data register TDRO after it is checked that the transmit data register empty TDRE bit is set to 1 When the transmit data is written to the UART SIO serial output data register TDRO the transmit data register empty TDRE bit is cleared to 0 The transmit data is transferred from the UART SIO serial output data register TDRO to the transmission shift register and the transmit data register empty TDRE is set to 1 When the transmission interrupt enable bit TIE contains 1 a transmission interrupt occurs if the transmit data register empty TDRE bit is set to 1 This allows the next piece of transmit data to
21. Reload counter This block is a 15 bit reload counter serving as a dedicated baud rate generator The block consists of a 15 bit register for reload values it generates the transmit reception clock from the external or internal clock The count value in the transmit reload counter is read from the baud rate generator 1 0 BGR1 BGRO CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 359 CHAPTER 22 LIN UART 22 2 Configuration of LIN UART MB95130 MB Series 360 Q Reception control circuit This block consists of a reception bit counter a start bit detection circuit and a reception parity counter The reception bit counter counts the reception data bits and sets a flag in the LIN UART reception data register when one data reception is completed according to the specified data length If the reception interrupt is enabled at this time a reception interrupt request is generated The start bit detection circuit detects a start bit in a serial input signal When a start bit is detected the circuit sends a signal to the reload counter in synchronization with the start bit falling edge The reception parity counter calculates the parity of the received data Q Reception shift register The circuit inputs received data from the SIN pin while bit shifting and transfers it to the RDR register upon completion of reception LIN UART Reception Data Register RDR This register retains the received data Serial input data is converted and s
22. SOE LIN UART serial data output enable bit 0 General purpose I O port 1 LIN UART serial data output pin SCKE LIN UART serial clock output enable bit General purpose I O port or LIN UART clock input pin LIN UART serial clock output pin LIN UART programmable clear bit Write Read No effect 0 is always LIN UART reset read Reload counter restart bit Write Read No effect 0 is always Restart the reload counter read External serial clock source selection bit Use the baud rate generator reload counter Use the external serial clock source One to one external clock input enable bit Use the baud rate generator reload counter Use the external clock directly Operation mode selection bits R W Readable writable Mode 0 asynchronous normal Read value is the same as write value Mode 1 asynchronous multiprocessor RO W Write only Writable 0 is read Mode 2 synchronous Initial value Mode 3 asynchronous LIN 368 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 4 Registers of LIN UART Table 22 4 2 Functions of Each Bit in LIN UART Serial Mode Register SMR Bit name Function Set the operation mode Note If the mode is changed during communication the transmission reception of LIN UART halts and waits for starting the next communication MDI Operation mode select
23. ees 395 LIN UART Pin Direct Access 408 LIN UART Reception Data Register RDR 372 LIN UART Reception Data Register RPR TPR 372 LIN UART serial control register SCR 366 LIN UART serial status register 558 E 370 LIN UART Transmit Data Register TDR 373 Notes on Using 417 Pins related to 11 363 Register and Vector Table Related to LIN UART Interr pt 382 Register List of LIN UART 365 Sample Programs of LIN UART 422 LIN UART Baud Rate Generator Register 1 0 Bit Configuration of LIN UART Baud Rate Generator Register 1 BGR1 BGRO 378 LIN UART extended communication control register Bit Configuration of LIN UART Extended Communication Control Register ECCR LIN UART extended status control register Bit Configuration of LIN UART Extended Status Control Register ESCR 374 LIN UART Reception Data Register LIN UART Reception Data Register RDR 372 LIN UART Reception Data Register RDRITDB teh nen 372 LIN UART serial mode register LIN UART serial mode register LIN UART serial status register LIN UART serial status register SSR sis cinta 370 LIN UART Transmit Data Register LIN UART Transmit Data Register TDR 373 List List
24. selectable n bit operation instruction E REI DDR read DDR J pon A Stop Watch SPL 1 M PUL read d PUL 4 o E PUL write ILSR read 1 1 1 L4 ILSR ILSR write Only P10 is selectable ILSR2 read gt ILSR2 ILSR2 write we 116 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 3 Port 1 9 3 1 Port 1 Registers This section describes the port 1 registers E Port 1 Register Function Table 9 3 2 lists the port 1 register functions Table 9 3 2 Port 1 Register Function Register name Read read modify write PDRI Pin state is L level PDR register value is 0 As output port outputs L level Pin state is H level PDR register value is 1 As output port outputs H level Port input enabled DDRI Port output enabled Pull up disabled Pull up enabled PULI Hysteresis input level selection ILSR 7 CMOS input level selection Hysteresis input level selection ILSR2 O Ol 0l Ol Automotive input level selection Only for 5V products it is an effective register Table 9 3 3 lists the correspondence between port 1 pins and each register bit Table 9 3 3 Correspondence between Registers and Pins for Port 1 Correspondence between related register bits and pins Pin name P16 P15 P14 P13
25. 8 16 bit compound timer 00 01 control status register 0 TO0CRO TO1CRO Address bit7 bit6 bit5 bit4 bit3 bit2 bito bito OF92 TO1CRO IFE C2 C1 CO F3 F2 F1 FO OF93 TOOCRO RW RW RW RW RW RW RW RW 8 16 bit compound timer 00 01 control status register 1 TOOCR1 TO1CR1 Address bit7 bit6 bit5 bit4 bit3 bit2 bito bito 00364 TO1CR1 STA HO IE IR BF IF SO OE 0037 TOOCR1 RW R W R W R WX RRM wW RW R W 8 16 bit compound timer 00 01 data register TOODR TO1DR Address bit7 bit6 bit5 bit4 bit3 bit2 bito bito OF944 TO1DR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDRO OF95 TOODR RW RW RW RW RW RW RW RW 8 16 bit compound timer 00 01 timer mode control register TMCRO Address bit7 bit6 bit5 bit4 bit3 bit2 bito bito OF96 TMCRO TO1 TOO IIS MOD FE11 FE10 FEO1 FEO0 R WX R WX RW RW RW RW RW RW R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction R WX Read only Readable writing has no effect on operation RW Readable writable Read value is different from write value Initial value 00000000p Initial value 00000000p Initial value 00000000g Initial value 00000000p 204 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15
26. Figure 15 4 2 Block Diagram of pin ECO related to 8 16 bit Compound Timer Hysteresis Only P10 is Peripheral function input Peripheral function input enable selectable 1 I Peripheral function output enable e gt e Peripheral function output __ __ SEEMS breiter e P If On Automotive SESSA L m 0 14 Pull up IM oM 1 i gt V He PDR read if pL Pen 1 P t 4 LT P Only P10 P12 PDR write and P13 are Inbit selectable n bit operation instruction DDR read DDR Pon wae Stop Watch SPL 1 PUL read Internal bus Uu c PUL write ILSR E 1 1 ILSR read 1 i 1 ILSR write Only P10 is selectable ILSR2 read p ILSR2 ILSR2 write CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 203 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer 15 5 Registers of 8 16 bit Compound Timer MB95130 MB Series This section describes the registers related to the 8 16 bit compound timer E Registers Related to 8 16 bit Compound Timer Figure 15 5 1 Registers Related to 8 16 bit Compound Timer
27. gt 27A5u 12H 27A6H 34H A 1234n General purpose register addressing This is used when accessing the register bank in general purpose register area with the addressing shown Ri in instruction table In this addressing fix one high rank byte of the address to 01 and create one subordinate position byte from the contents of RP register bank pointer and three subordinate bits of the operation code to access to this address Figure E 1 6 shows an example CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 507 APPENDIX APPENDIX E Instruction Overview MB951 30 MB Series Figure E 1 6 Example of General purpose Register Addressing MOV A R6 RP 010105 01564 ABH 5 a ABH Immediate addressing This is used when immediate data is needed in addressing shown d8 in the instruction table In this addressing the operand becomes immediate data as it is The specification of byte word depends on the operation code Figure E 1 7 shows an example Figure E 1 7 Example of Immediate Addressing MOV A 56H Vector addressing This is used when branching to the subroutine address registered in the table with the addressing shown vct in the instruction table In this addressing information on vct is contained in the operation code and the address of the table is created using the combinations shown
28. Operation in stop mode and watch mode Ifthe pin state specification bit in the standby control register STBC SPL is set to 1 when the device switches to stop or watch mode the pin is set forcibly to the high impedance state regardless of the DDR register value Note that the input is locked to L level and blocked in order to prevent leaks due CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 113 CHAPTER 9 I O PORT 9 2 Port 0 MB95130 MB Series to freed input However if the interrupt input is enabled for the external interrupt control register EIC of the external interrupt circuit and the interrupt pin selection circuit control register WICR of the external interrupt selection circuit the input is enabled and not blocked e If the pin state specification bit is 0 the state remains in port I O or peripheral function I O and the output is maintained Operation as an analog input Set the DDR register bit which is corresponding to the analog input pin to 0 and set the AIDRL register bit to 0 Set the corresponding PUL register bit to 0 Operation of the external interrupt input pin Set the DDR register bit which is corresponding to the external interrupt input pin to 0 Pin values are continuously input to the external interrupt circuit When using the pin for a function other than an interrupt you must disable the corresponding external interrupt Operation of the pull up control register
29. TOODR Sets L pulse width compare value TO1DR Sets the cycle of PWM waveform compare value O Used bit x Unused bit 1 Set 1 0 Set 0 In PWM timer function variable cycle mode both timers 00 and 01 are used when the cycle is specified by the 8 16 bit compound timer 01 data register TOI DR and the L pulse width is specified by the 8 16 bit compound timer 00 data register TOODR any cycle and duty PWM signal is generated from the timer output bit TOOO For this function the compound timer cannot serve as a 16 bit counter as the two 8 bit counters are used Enabling timer operation by setting either TOOCRI STA 1 or TOICRI STA 1 sets the mode bit TMCRO MOD to 0 As the first cycle always begins with L pulse output the timer initial value setting bit TOOCR1 TO1CR1 SO is meaningless The interrupt flag TOOCR1 TOICRI IF is set when each 8 bit counter matches the value in the corresponding 8 16 bit compound timer 00 01 data register TOODR TOIDR The 8 16 bit compound timer 00 01 data register value is transferred to the temporary storage latch comparison data storage latch in the comparator either when the counter starts counting or when a comparison match with each counter value is detected is not outputted when the L pulse width setting value is greater than the cycle setting value The count clock must be selected for both of timers 00 and 01 Selecting different count clocks howeve
30. oOo AN UART prescaler selection register PSSRO x UART baud rate setting register BRSRO 1 256 Baud Rate Setting BRS7 to BRSO bps Serial clock The serial clock signal is outputted under control of the output for transmit data When only reception is performed therefore set transmission control TXE 1 to write dummy transmit data to the UART SIO serial output register Refer to the data sheet for the UCKO clock value Reception in UART SIO operation mode 1 For reception in operation mode 1 each register is used as follows Figure 20 7 11 Registers Used for Reception in Operation Mode 1 SMC10 UART SIO Serial Mode Control Register 1 bit7 bit6 bit5 bit4 bit3 bit2 bit bito BDS PEN TDP SBL CBL1 CBLO CKS MD x x 1 SMC20 UART SIO Serial Mode Control Register 2 bit7 bit6 bit5 bit4 bit3 bit2 bit bito SCKE TXOE RERC RXE TXE RIE TCIE TEIE 0 x SSRO UART SIO serial status and data register bit7 bit6 bit5 bit4 bit3 bit2 bit bito PER OVE FER RDRF TCPL TDRE x x x X X x TDRO UART SIO serial output data register bit7 bit6 bit5 bit4 bit3 bit2 bit bito TD7 TD6 TD5 TD4 TD3 TD2 TD1 TDO x x x x x x x x RDRO UART SIO serial input data register bit7 bit6 bit5
31. Index register IX The index register is a 16 bit register used to hold the index address The index register is used with a single byte offset 128 to 127 The offset value is added to the index address to generate the memory address for data access The initial value after a reset is 0000g Extra pointer EP The extra pointer is a 16 bit register which contains the value indicating the memory address for data access The initial value after a reset is 00004 Stack pointer SP The stack pointer is a 16 bit register which holds the address referenced when an interrupt or subroutine call occurs and by the stack push and pop instructions During program execution the value of the stack pointer indicates the address of the most recent data pushed onto the stack The initial value after a reset is 0000p Program status PS The program status is a 16 bit control register The upper eight bits make up the register bank pointer RP and direct bank pointer DP the lower eight bits make up the condition code register CCR In the upper eight bits the upper five bits make up the register bank pointer used to contain the address of the general purpose register bank The lower three bits make up the direct bank pointer which locates the area to be accessed at high speed by direct addressing The lower eight bits make up the condition code register CCR which consists of flags that represent the state of the CPU The inst
32. NV AOIN 28ns J3qqv dW AOIN dS V 91 45 erc Tp Spi p 8P 1p y py 1 y apy n y 1p y pv MHOX MAOW MAOW MAOW STI dO AOW JO NV AON 28ns AOIN Od V 9IPH V V ne ert SPH V 8PH V 8P V 8PH V SPH V SPE V SPH MHOX MAOIN MAOIN MAOW eI svd vya HO NV Oans 2 dW AOW dd v Vd dd dd 1 va v L v LY V V MAON MAOW MOA MONI MAOIN MUO MHOX MOSS MAAV MdIND DAOA XI V Vv XI XI XI ert v L va V LY V V MAON MAOIN M23d MONI AOW AOW NV HOX 0915 Oddy dW X IO3 dS Vds ds 45 1 V Sd V axo XI XI 9 Ippe 9 Ippe V MAON MAON M28d MONI OLAS OYTO MAOW AOW MdOd MHSNd TIVO dt NTAN Od V V V 810 1 np Sd V MAOW df MOC MONI 195 ge MAOW AOW MdOd MHSNd Iau Lau dVMS dON CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 518 APPENDIX APPENDIX F Mask Option MB95130 MB Series APPENDIX F Mask Option The mask option list of the MB95130 MB series is shown in Table F 1 B Mask Option List Table F 1 Mask Option List Part number MB95136MB MB95F133MBS F133NBS F133JBS MB95F134MBS F134NBS F134JBS MB95F136MBS F136NBS F136JBS MB95F133MBW F133NBW F133JBW MB95F134MBW F134NBW F134JBW MB95F136MBW F136NBW F136JBW MB95FV100D 103 Specifying procedure
33. PFI PF1 general purpose I O Not shared Hysteresis Automotive CMOS OD Open drain PU Pull up For5V products the hysteresis input can be switched to the automotive input It becomes hysteresis input besides 120 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series E Block Diagram of Port F Figure 9 4 1 Block Diagram of Port F CHAPTER 9 I O PORT 9 4 Port F Internal bus Hysteresis Z 0 D o PDR Y s PDR write In bit operation instruc ion A 2 Ei o o DDR V 2 Stop Watch SPL 1 Z ILSR2 ILSR2 write CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 121 CHAPTER 9 I O PORT 9 4 Port F MB95130 MB Series 9 4 1 Port F Registers This section describes the port F registers E Port F Register Function Table 9 4 2 lists the port F register functions Table 9 4 2 Port F Register Function Register name Read read modify write PDRF Pin state is L level PDR register value is 0 As output port outputs L level Pin state is H level PDR register value is 1 As output port outputs H level Port input enabled DDRF Port output enabled Hysteresis input level selection ILSR2 Automotive input level selectio
34. This chapter describes the functions and operations of the I O ports 9 1 Overview of I O Ports 9 2 Port 0 9 3 Port 1 9 4 Port F 9 5 Port G CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 107 CHAPTER 9 I O PORT 9 1 Overview of I O Ports MB951 30 MB Series 9 1 Overview of I O Ports I O ports are used to control general purpose I O pins Bl Overview of I O Ports The I O port has functions to output data from the CPU and load inputted signals into the CPU via the port data register PDR It is also possible to set the input output direction of the I O pins as desired at the bit level via the port direction register DDR Table 9 1 1 lists the registers for each port Table 9 1 1 Each Port Registers Register name Read Write Initial value Port 0 data register PDRO 00000000 Port 0 direction register DDRO 00000000 Port 1 data register 00000000 Port 1 direction register DDR1 00000000 Port F data register PDRF 00000000 Port F direction register DDRF 00000000 Port G data register PDRG 00000000 Port G direction register DDRG 000000005 Port 0 pull up register PULO 00000000 Port 1 pull up register PUL1 00000000 Port G pull up register PULG 00000000 A D input disable register lower AIDRL 00000000 Input level selection register ILSR 00000000 Input level selection register 2 ILSR2 00000000 R W Readable writable Read v
35. x REVC REVO01 REVOO x G Used bit 0 Set 1 Set 1 x Setting nullified The bit status changes depending on the number of channels implemented 258 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 7 Operating Description of 8 16 bit PPG il Operation of 16 bit PPG Mode This mode is selected by setting the operation mode select bits MD1 MDO of the PPG timer 00 control register to 10g or 11g When the PPG operation enable bit PENOO is set to 1 in 16 bit PPG mode the 8 bit down counters PPG timer 00 and 8 bit down counter PPG timer 01 load the values in the 8 16 bit PPG timer 00 01 cycle setup buffer registers PPSO1 for PPG timer 01 and PPSOO for PPG timer 00 and start down count operation When the count value reaches 1 the values in the cycle setup register are reloaded and the counters repeat the counting When the values of the down counters match the values in the 8 16 bit PPG timer duty setup buffer registers both the value in PDSOI for PPG timer 01 and the value in PDSOO for PPG timer 00 the pin is set to synchronizing with the count clock After H which is the value of duty setting is output the PPGOO pin is set to L If the output inversion signal REVOO is 0 the signal will be outputted to the PPGOO with the polarity unchanged If it is set to 1 the polarity will be inv
36. B Interrupts During 8 10 bit A D Converter Operation When A D conversion is completed the interrupt request flag bit ADC1 ADI is set to 1 Then if the interrupt request enable bit is enabled ADC2 ADIE 1 an interrupt request is issued to the interrupt controller Write 0 to the ADI bit using the interrupt service routine to clear the interrupt request The ADI bit is set when A D conversion is completed irrespective of the value of the ADIE bit The CPU cannot return from interrupt processing if the interrupt request flag bit ADC1 ADI is 1 with interrupt requests enabled ADC2 ADIE 1 Be sure to clear the ADI bit within the interrupt service routine E Register and Vector Table Related to 8 10 bit A D Converter Interrupts Table 23 5 1 Register and Vector Table Related to 8 10 bit A D Converter Interrupts Interrupt Interrupt level setting register Vector table address Interrupt source request number Registers Setting bit 8 10 bit A D IRQ18 ILR4 FFD6g FFD7g Refer to APPENDIX B Table of Interrupt Causes for the interrupt request numbers and vector tables of all peripheral functions CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 439 CHAPTER 23 8 10 BIT A D CONVERTER 23 6 Operations of 8 10 bit A D Converter and Its Setup Procedure Examples Procedure Examples MB95130 MB Series 23 6 Operations of 8 10 bit A D Converter and Its Setup The EXT bit in the ADC1 register can be used to select the
37. CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 167 CHAPTER 12 WATCH PRESCALER 12 7 Sample Programs for Watch Prescaler MB951 30 MB Series 168 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 13 WATCH COUNTER This chapter describes the functions and operations of the watch counter 13 1 Overview of Watch Counter 13 2 Configuration of Watch Counter 13 3 Registers of Watch Counter 13 4 Interrupts of Watch Counter 13 5 Explanation of Watch Counter Operations and Setup Procedure Example 13 6 Notes on Using Watch Counter 13 7 Sample Programs for Watch Counter Code CM26 00108 2E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 169 CHAPTER 13 WATCH COUNTER 13 1 Overview of Watch Counter MB95130 MB Series 13 1 Overview of Watch Counter The watch counter can generate interrupt requests ranging from min 125ms to max 63s intervals E Watch Counter The watch counter performs counting for the number of times specified in the register by using the selected count clock and generates an interrupt request The count clock can be selected from the four types shown in Table 13 1 1 The count value can be set to any number from 0 to 63 When 0 is selected no interrupt is generated When the count cycle is set to 1s and the count value is set to 60 an interrupt is generated every one minute Table 13 1 1 Count Clock Types Count clock Count cycle when Fg operates at 32 768kHz
38. The UART SIO dedicated baud rate generator serves as the baud rate generator for asynchronous clock mode E Baud Rate Setting The SMC10 register CKS bit of the UART SIO is used to select the serial clock This selects the UART SIO dedicated baud rate generator In asynchronous CLK mode the shift clock that is selected by the CKS bit and divided by four is used and transfers can be performed within the range from 2 to 2 The baud rate calculation formula for the UART SIO dedicated baud rate generator is shown below CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 353 CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR 21 4 Operating Description of UART SIO Dedicated Baud Rate MB95130 MB Series Generator Figure 21 4 1 Baud Rate Calculation Formula when UART SIO Dedicated Baud Rate Generator Is Used Machine clock MCLK Baud rate bps 1 2 4x 2 4 255 8 UART baud rate setting register BRSRO UART prescaler selection register PSSRO Baud Rate Setting Prescaler selection BRS7 to BRSO PSS1 PSSO Table 21 4 1 Sample Asynchronous Transfer Rates by Baud Rate Generator Machine Clock 10MHz 16MHz 16 25MHz Settings of UART SIO dedicated baud Baudrate Baudrate Baud rate rate generator UART Total division ratio 10MHz 16MHz 16 25MHz Internal PSS x BRS 4 Total Total Total division division division Prescaler selection Baud rate A counter setting d
39. We provide sample programs that can be used to operate the watch prescaler il Sample Programs for Watch Prescaler For information about sample programs for the watch prescaler refer to Sample Programs in Preface E Setting Methods not Covered by Sample Programs Q How to initialize the watch prescaler The watch timer initialization bit WPCR WCLR is used Control item Watch timer initialization bit WCLR When initializing watch prescaler Set the bit to 1 How to select the interval time The watch interrupt interval time select bits WPCR WTCI WTCO are used to select the interval time Interrupt related register The interrupt level is set using the interrupt level register shown in the following table Interrupt source source Interrupt level setting register Interrupt level setting register setting register Interrupt vector Interrupt vector Watch 1 Interrupt level register ILR5 presea er Address 0007 TONG How to enable disable clear interrupts The interrupt request enable bit WPCR WTIE is used to enable interrupts Control item Interrupt request enable bit WTIE To disable interrupt requests Set the bit to 0 To enable interrupt requests Set the bit to 1 The watch interrupt request flag WPCR WTIF is used to clear interrupt requests Control item Watch interrupt request flag WTIF To clear an interrupt request Set the bit to 0
40. When enabling PPG operation Set the bit to 1 PPG operation must be enabled before the PPG is activated How to set the PPG operation mode The operation mode select bits PCO0 MD 1 0 are used Q How to select the operating clock ch 0 is selected by the operating clock select bits PC00 CKS02 CKS01 CKS00 How to enable disable the PPG output pin The output enable bit PC00 POENO is used When enabling PPG output Set the bit to 1 When disabling PPG output Set the bit to 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 261 CHAPTER 16 8 16 BIT PPG 16 9 Sample Programs for 8 16 bit PPG Timer MB95130 MB Series How to invert the PPG output The output level inversion bit REVC REV00 or REV10 is used for PPGOO 262 Output level inversion bit REVOO or REV10 When inverting PPG output Set the bit to 1 The output level inversion bit REVC REVOI or REV11 is used for PPGOI Output level inversion bit REVO1 or REV11 When inverting PPG output Set the bit to 1 Interrupt related register The interrupt level is set by the interrupt setup register shown in the following table Interrupt source ch 1 lower Interrupt level setup register Interrupt level register ILR2 Address 0007Bg Interrupt vector 09 Address 0FFE8y ch 1 upper Interrupt level register ILR2 Address 0007Bg 10 Address 0FFE6y ch 0 lower Interrupt level register ILR
41. sssssssssseseeeeeeeeen n 448 24 2 Configuration of Low voltage Detection Reset Circuit seeseeee 449 24 3 Pins of Low voltage Detection Reset 1 450 24 4 Operations of Low voltage Detection Reset Circuit sssseeeme 451 CHAPTER 25 CLOCK SUPERVISOR edid uod cda md s Dow Ur cx Res 453 25 1 Overview of Clock Supervisor ssssssssssssssssssesee eene en nennt s nnne tnn snnt en 454 25 2 Configuration of Clock Supervisor sss eene ener senes nennen 455 25 3 Register of Clock SupervisOEl co ede th e n td e gig b D Edda 457 25 3 1 Clock Supervisor Control Register CSVCR nenne 458 25 4 Operations of Clock Supervisor ssssssssssssssseesese enne nennen nnne 460 25 5 Notes on Using Clock Supervisor sssssssssssssssseee eene eren 463 CHAPTER 26 256 Kbit FLASH MEMORY nennen nnn nnn 465 26 1 Overview of 256 Kbit Flash Memory 2 466 26 2 Sector Configuration of Flash Memory 2 enne nnne enters nnn nennen 467 26 3 Register of Flash Memory sssssssseesesneeeeeene eee nnne 468 26 3 1 Flash Memory Status Register FSR sse nennen 469 26 4 Starting the Flash M
42. 208 STBC Standby Control Register STBC 62 Stop mode Operation at the Main Clock Stop Mode 179 Operation in Sub Clock Stop Mode 179 Operations in Stop 76 Sub Clock Operation in Sub Clock Stop Mode 179 Sub clock mode Operations in Sub Clock Mode Dual clock product 65 Sub PLL clock mode Operations in Sub PLL Clock Mode Dual clock product 65 SYCC Configuration of System Clock Control Register rH p TP 54 Synchronous method Synchronous method eeeeeeeesesss 396 Synchronous Mode Operation of Synchronous Mode Operation Mode 2 cp E DDR 401 System clock control register Configuration of System Clock Control Register SY CO c ase iita tke eun 54 T TOOCRO TO1CRO 8 16 bit Compound Timer 00 01 Control Status Register 0 205 TOOCR1 T01CR1 8 16 bit Compound Timer 00 01 Control Status 536 Register 1 TOOCRl TOICRI 208 TOODR TO1DR 8 16 bit Compound Timer 00 01 Data Register TOODR TOIDR 214 Table Explanation of Item in Instruction Table 505 Registers and Vector Table Related to Interrupts of 16 bit PPG 277 Registers and Vector Table Related to Interrupts of 8 1
43. BC BLO at no branch BNC BHS at branch OthenPCc PC rel BNC BHS rel at no branch BN at branch ifN IthenPCc PC rel BN at no branch at branch ifN OthenPC lt PC rel at no branch at branch IthenPC lt PC rel at no branch at branch ifVVN OthenPC lt PC rel at no branch dir b rel MO Mme BY dy BY de AINI BY po AINI SAIN AIN Se if dir b OthenPC lt PC rel dir b rel if dir b 1thenPC lt PC rel lt A lt ext vectorcall subroutinecall lt lt 1 returnfromsubroutine E Other Instructions Table E 4 4 Other Instructions returnfrominterrupt SP lt A SP SP 2 restore A SP SP SP 2 SP 0X SP SP 2 IX SP SP SP 2 No operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 517 MB95130 MB Series Map ion Table E 5 1 Instruction Map of 2 8 Instruct APPENDIX E Instruction Overview Table E 5 1 shows the instruction map of F2MC 8FX E 5 E Instruction Map APPENDIX Lt LA LA er Tp 8PH SPH LA LA Y LAY Vid LIV
44. CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR MB95130 MB Series 21 3 Registers of UART SIO Dedicated Baud Rate Generator 21 3 1 UART SIO Dedicated Baud Rate Generator Prescaler Selection Register PSSRO The UART SIO dedicated baud rate generator prescaler register PSSRO controls the output of the baud rate clock and the prescaler UART SIO Dedicated Baud Rate Generator Prescaler Selection Register PSSRO Figure 21 3 2 UART SIO Dedicated Baud Rate Generator Prescaler Selection Register PSSRO bit bit6 bits bit4 bit3 bit2 biti Initial value Address me pue Rs RO WX RO WX RO WX RO WX Ro WX R W R W R W PSS1 PSSO Prescaler selection bits 0 0 1 1 0 1 1 2 1 0 1 4 1 1 1 8 BRGE Baud rate clock output enable bit 0 Disables baud rate output 1 Enable baud rate output R W Readable writable Read value is the same as write value RO WX Undefined bit Read value is 0 writing has no effect on operation Initial value Table 21 3 1 UART SIO Dedicated Baud Rate Generator Prescaler Selection Register PSSRO Bit name Function bit7 to bit3 Undefined bits These bits are undefined Reading the bits always returns 0 This bit enables the output of the baud rate clock BRCLK When set to 1 loads BRS 7 0 to the 8 bit down counter and outputs BRCLK which is supplied to the UART SIO When set to 0 stops the output of B
45. FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series 5 1 2 Direct Bank Pointer DP CHAPTER 5 CPU 5 1 Dedicated Registers The direct bank pointer DP in bits 10 to 8 of the program status PS register specifies the area to be accessed by direct addressing E Configuration of Direct Bank Pointer DP Figure 5 1 4 shows the configuration of the direct bank pointer Figure 5 1 4 Configuration of Direct Bank Pointer RP DP PS R3 R2 RO DP2 DP1 bit15 bit14 bit13 bit12 6 11 bitlO bit9 bits bit bit6 bits bit4 bits bit2 biti bitO CCR DP Initial value DPO H ui mo N z vic 000g The areas from 0000y to 007Fy and 0080y to 047Fy can be accessed by direct addressing Access to 0000g to 007Fg is specified with an operand regardless of the value in the direct bank pointer Access to 0080y to 047Fy is specified with the value in the value of the direct bank pointer and the operand Table 5 1 1 shows the relationship between direct bank pointer DP and access area Table 5 1 2 lists the direct addressing instructions Table 5 1 1 Direct Access Pointer and Access Area Direct bank pointer DP 2 0 Operand specified dir XXX y It does not affect the mapping 0000y to 007Fg Access area 0000 to 007F yy 000g Initial value 001g 010g 0llg 00805 to OOFFyy 100g 101g 110g CM26 10118 3E
46. STBC register top 1 i Sleep cancelled by i lt gt 1 watch interrupt WIRQi 3 STP bit i STBC register Stop cancelled by external interrupt When setting interval time select bits in the watch prescaler control register WPCR WTC1 to 11g 214 2 Fa WPCR WTC1 WTCO Interval time select bits in watch prescaler control register WPCR WCLR Watch timer initialization bit in watch prescaler control register WPCR WTIF Watch interrupt request flag bit in watch prescaler control register WPCR WTIE Watch interrupt request enable bit in watch prescaler control register STBC SLP Sleep bit in standby control register STBC STP Stop bit in standby control register WATR SWTS to SWTO Sub clock oscillation stabilization wait time select bit in oscillation stabilization wait time setup register E Setup Procedure Example The watch prescaler is set up in the following procedure Initial setting 1 Set the interrupt level ILR5 2 Set the interval time WPCR WTCI WTCO 3 Enable interrupts WPCR WTIE 1 4 Clear the counter WPCR WCLR 1 Interrupt processing 1 Clear the interrupt request flag WPCR WTIF 0 2 Arbitrary processing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 165 CHAPTER 12 WATCH PRESCALER 12 6 Notes on Using Watch Prescaler MB95130 MB Series 12 6 Notes on Using Watch Prescaler Shown below are the precautions that mu
47. When the timer stops operation in PWM timer function fixed cycle mode this bit holds the last value When the timer operation mode select bit TOOCRO TO1CRO F2 F1 is changed with the timer being stopped the bit indicates the last value of timer operation if the same timer operation has ever been performed or otherwise contains 0 This bit indicates the output value of timer 00 When the timer starts operation TOOCR1 TOICRL STA 1 the value in the bit changes depending on the selected timer function Writing to this bit has no effect on the operation The value in the bit remains indeterminate when the input capture function has been selected e When the timer stops operation TOOCR1 TOICRI STA 0 in interval timer PWM timer variable cycle mode or PWC timer function this bit holds the last value When the timer stops operation in PWM timer function fixed cycle mode this bit holds the last value When the timer operation mode select bit TOOCRO TO1CRO F2 F1 is changed with the timer being stopped the bit indicates the last value of timer operation if the same timer operation has ever been performed or otherwise contains 0 TOO Timer 00 output bit This bit selects the signal input to timer 00 when the PWC timer or input capture function has been selected Writing 0 selects the external signal ECOO as the signal input for timer 00 Writing 1 selects the intern
48. Bit name Function EIRI External interrupt request flag bit 1 This flag is set to 1 when the edge selected by the edge polarity select bits SL11 SL10 is inputted to the external interrupt pin INTOI When this bit and the interrupt request enable bit 1 EIE1 are set to 1 an interrupt request is outputted e Writing 0 clears the bit Writing 1 has no effect is read in read modify write RMW instructions SL11 SL10 Edge polarity select bits 1 These bits select the polarity of the interrupt source edge of the pulse inputted to the external interrupt pin INTOI Edge detection is not performed and no interrupt is generated when these bits are set to 00g Rising edges are detected when these bits are 01g falling edges when 10g and both edges when 11g EIE1 Interrupt request enable bit 1 This bit is used to enable and disable output of interrupt requests to the interrupt controller When this bit and the external interrupt request flag bit 1 EIR1 are 1 an interrupt request is outputted When using an external interrupt pin write 0 to the corresponding bit in the port direction register DDR to set the pin as an input The status of the external interrupt pin can be read directly from the port data register regardless of the status of the interrupt request enable bit EIRO External interrupt request flag bit 0 This flag is set to 1 when the edge selected by t
49. CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 175 CHAPTER 13 WATCH COUNTER 13 3 Registers of Watch Counter MB95130 MB Series Table 13 3 2 1 Functional Description of Each Bit of Watch Counter Status Register WCSR Bit name Function This bit activates the watch counter and selects whether to enable interrupts of the watch counter or those of the watch prescaler When set to 0 watch counter is cleared and stopped Moreover interrupt requests of the watch counter are disabled while interrupt requests of the watch prescaler are enabled ISEL When set to 1 The interrupt request output of the watch counter is enabled Watch counter and the counter starts operation On the other hand interrupt start amp interrupt requests of the watch prescaler are disabled request enable bit Always disable interrupts of the watch prescaler before setting this bit to 1 to select interrupts of the watch counter The watch counter performs counting using an asynchronous clock from the watch prescaler For this reason an error of up to one count clock may occur at the beginning of a count cycle depending on the timing for setting ISEL bit to 1 This bit is set to 1 when the counter underflows When this bit and the ISEL bit are both set to 1 a watch counter interrupt is generated Writing 0 clears the bit Writing I to this bit has no effects on the operation is always read in read modify write RMW in
50. CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 187 CHAPTER 14 WILD REGISTER 14 3 Registers of Wild Register MB95130 MB Series Wild Register Number Each wild register address setup register WRAR and wild register data setup register WRDR has its corresponding wild register number Table 14 3 1 Wild Register Numbers Corresponding to Wild Register Address Setup Registers and Wild Register Data Setup Registers Wild registers Wild registers address setup register WRAR data setup register WRDR Wild register number 188 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 14 WILD REGISTER MB95130 MB Series 14 3 Registers of Wild Register 14 31 Wild Register Data Setup Registers WRDRO to WRDR2 The wild register data setup registers WRDRO to WRDR2 use the wild register function to specify the data to be amended B Wild Register Data Setup Registers WRDRO to WRDR2 Figure 14 3 2 Wild Register Data Setup Registers WRDRO to WRDR2 WRDRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OF824 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO 000000008 RW RW RW RW RW RW RW RW WRDR1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OF85y RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO 00000000pg RW RW RW RW RW RW RW RW WRDR2 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial val
51. CMOS input level selection Hysteresis input level selection ILSR2 O Ol 0l ol Oj Automotive input level selection Only for 5V products it is an effective register Table 9 2 3 lists the correspondence between port 0 pins and each register bit Table 9 2 3 Correspondence between Registers and Pins for Port 0 Correspondence between related register bits and pins Pin name P06 P05 P04 P02 P01 PDRO DDRO PULO bit7 bit6 bit5 bit4 bit3 bit2 bitl bitO AIDRL ILSR bit2 ILSR2 bitO Only for 5V products it is an effective register 112 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 2 Port 0 9 2 2 Operations of Port 0 This section describes the operations of port 0 E Operations of Port 0 Operation as an output port Setting the corresponding DDR register bit to 1 sets a pin as an output port e When a pin is set as an output port it outputs the value of PDR register to pins e If data is written to the PDR register the value is stored in the output latch and output to the pin as it is Reading the PDR register returns the PDR register value Operation as an input port Setting the corresponding DDR register bit to 0 sets a pin as an input port When using the analog input shared pin as an input port set the corresponding bits in the A D i
52. Interrupt requests are cleared by the interrupt request bit EICOO EIRO or EIR1 Interrupt request bit EIRO or EIR1 300 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT This chapter describes the functions and operations of the interrupt pin selection circuit 19 1 Overview of Interrupt Pin Selection Circuit 19 2 Configuration of Interrupt Pin Selection Circuit 19 3 Pins of Interrupt Pin Selection Circuit 19 4 Registers of Interrupt Pin Selection Circuit 19 5 Operating Description of Interrupt Pin Selection Circuit 19 6 Notes on Using Interrupt Pin Selection Circuit Code CM26 001 10 2E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 301 CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT 19 1 Overview of Interrupt Pin Selection Circuit MB95130 MB Series 19 1 Overview of Interrupt Pin Selection Circuit The interrupt pin selection circuit selects pins to be used as interrupt input pins from among various peripheral input pins B Interrupt Pin Selection Circuit The interrupt pin selection circuit is used to select interrupt input pins from amongst various peripheral inputs TRGO ADTG UIO SCK SIN The input signal from each peripheral function pin is selected by this circuit and the signal is used as the INTOO channel 0 input of external interrupt This enables the input signals to the peripheral function pins to also serve as e
53. STBC register Wake up from stop mode by external interrupt 1 Wake up from sleep mode by interrupt 1 gt SIPbi STBC register i Stop mode 234 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 15 States in Each Mode during Operation Figure 15 15 2 Operations of Counter in Standby Mode or in Pause Serving as PWM Timer Counter value BE 9 FFH gt 14 1 1 Delay of oscillation stabilization wait time Time 1 LI 1 1 TOODR TO1DR value FFH STA bit E i x 1 lt gt gt 1 1 1 11 PWM timer output pin 4 oo 4 Sleep mode intaj i Maintains the level prior to hold SLP bit 4 Maintains the level prior to Stop 1 it STBC register T d Wake up from sleep mode by interrupt 1 1 1 1 1 STP bit i STBC register 1 1 HO bit TERS o ES The PWM timer output maintains the value held before it enters the stop mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 235 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 16 Notes on Using 8 16 bit Compound Timer MB951 30 MB Series 15 16 Notes on Using 8 16 bit Compound Timer This section explains the precautions to be taken when using the 8 16 bit compound timer Notes on Using 8 16 bit Compound Timer 236 When changing the timer function by using
54. Setting 1 to the PUL register connects the pull up resistor to the pin However when the general purpose I O port or shared peripheral resource outputs L level the pull up resistor is disconnected regardless of the PUL register value Operation of the input level selection register Setting 1 to the bit2 of ILSR register changes only P04 from the hysteresis input level to the CMOS input level When the bit2 of ILSR register is 0 it should be the hysteresis input level e For pins other than P04 the CMOS input level cannot be selected however only the hysteresis input level or the automotive input level can e Make sure that the input level for P04 is changed during the peripheral function UART SIO stopped Operation of the input level selection register 2 The ILSR2 register is a valid register only for 5V models e Setting bitO of the ILSR2 register to 1 changes the port 0 input level from the hysteresis input level to the automotive input level The hysteresis input level is used when bitO of the ILSR2 register is 0 Only modify the port 0 input level setting when the peripheral functions input are halted Table 9 2 4 shows the pin states of the port Table 9 2 4 Pin State of Port 0 Normal operation Operating Sleep Stop SPL 1 state Stop SPL 0 Watch SPL 1 Watch SPL 0 At reset Hi Z the pull up setting is enabled Input cutoff If external interrupts are enabled the external int
55. Synch field is transmitted as byte data 55y following the LIN break To prevent generation of a transmit interrupt 55 can be written to the TDR after the LBR bit in ECCR is set to 1 even if the flag is 0 Operation as LIN slave In LIN slave mode the LIN UART must synchronize to the baud rate for the master The LIN UART generates a reception interrupt when LIN break interrupt is enabled LBIE 1 even though reception is disabled RXE 0 The LBD bit in the ESCR is set to 1 at this time Writing 0 to the LBD bit clears the reception interrupt request flag For calculation of the baud rate the following example shows the operation of the LIN UART When the LIN UART detects the first falling edge of Synch field set an internal signal which is input to the 8 16 bit compound timer to and then start the timer The internal signal should be L at the fifth falling edge The 8 16 bit compound timer must be set to the input capture mode Also the 8 16 bit compound timer interrupts must be enabled and set for the detection at both edges The time for which the input signal to the 8 16 bit compound timer is 1 becomes the value obtained by multiplying the baud rate by 8 The baud rate setting value is calculated by the following expressions When the counter of the 8 16 bit compound timer is not overflowing BGR value b ay8 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 405 CHAPTER 22 LIN UART 22 7 Op
56. eene 248 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register 801 900 249 Setup Methods without Sample Program ns 261 283 299 Setup Procedure Example 258 281 297 Setup Procedure Example Setup Procedure Example D 142 153 165 179 328 396 442 Signaling Signaling ie eed tete edu 396 Single chip Mode Single chip 32 Slave LIN Master Slave Mode Communication Function ME ERES BIER 414 Master slave mode communication function 411 Slave Device LIN Slave Device eese 416 Sleep mode Operations in Sleep Mode 75 SMC UART SIO Serial Mode Control Register 1 SMC10 EE 319 UART SIO Serial Mode Control Register 2 SMC20 eU ETE 321 SMR LIN UART serial mode register CSMR ccena rese idees ve vede 368 Special Instruction Special Instruction eseseeeeeeeeeeeee 510 SSR LIN UART serial status register SSR endi fici dt estos E 370 UART SIO serial status and data tegister SSR wees iiec ttn 323 Stack Interrupt Processing Stack Area 105 Stack Operation at Start of Interrupt Processing 104 Stack Operation upon Returning from Interrupt 104 Standby control register Standby Control Register STBC 62 Standby Mode An Interrupt Request may Suppress Transition to Standby Mode
57. 0 Each error flag is set when a reception is completed SSR RDRF 1 or when a reception error occurs SSR PE ORE FRE 1 If the reception interrupt is enabled SSR RIE 1 at this time a reception interrupt is generated Note When a reception error occurs in each mode the data in the LIN UART reception data register RDR is invalid Figure 22 5 2 shows the timing of reception and flag set Figure 22 5 2 Timing of Reception and Flag Set Reception data Mode 0 3 Reception data Mode 1 Reception data Mode 2 PE FRE RDRF ORE RDRF 1 Reception 1 PEflagis always 0 in modes 1 and 3 2 Anoverrun error is generated if the next data is transferred before a received data is read RDRF 1 ST Start bit SP Stop bit AD Mode 1 multiprocessor address data select bit Note Figure 22 5 2 does not show all receptions in mode 0 It only shows examples for 7 bit data parity even parity or odd parity 1 stop bit and 8 bit data no parity 1 stop bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 383 CHAPTER 22 LIN UART 22 5 Interrupt of LIN UART MB95130 MB Series Figure 22 5 3 ORE Flag Set Timing Reception data NST O X 1X2 X 3 4 5X6X 7 SNST OX 1X 2Y 3X AN 5X 6Y 7 SR RDRF ou 0o 0 ORE 384 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 5 Interrupt of LIN UART 22 5 2 Tra
58. 1 Main clock halt detected Reserved bit Be sure to set this bit to 0 458 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 25 CLOCK SUPERVISOR MB95130 MB Series 25 3 Register of Clock Supervisor Table 25 3 1 Functions of Bits in Clock Supervisor Control Register CSVCR Bit name Function This bit is reserved Reserved bit Write 0 to this bit The read value is always 0 This bit is read only and this bit indicates that a main clock oscillation halt has been detected When set to 0 The bit indicates that no main clock oscillation halt has been detected When set to 1 The bit indicates that main clock oscillation halt has been detected Writing 1 to this bit does not affect the operation MM Main clock halt detection bit This bit is read only and this bit indicates that a sub clock oscillation halt has been detected When set to 0 The bit indicates that no sub clock oscillation halt has been detected When set to 1 The bit indicates that sub clock oscillation halt has been detected Writing 1 to this bit does not affect the operation This bit enables CR oscillation When set to 0 The bit disables oscillation When set to 1 The bit enables oscillation initial value Before writing 0 to this bit make sure that the clock monitor function has been disabled with the MM and SM bits set to 0 SM Sub clock halt detection bit RCE CR clock oscillatio
59. 11 FUJITSU MICROELECTRONICS LIMITED 0080y to OOFFyy 01004 to 17 0180 to 01FFgj 0200 to 027 02804 to O2FFy 0300 to 037 0380 to 03FFy 0400 to 047 37 CHAPTER 5 CPU 5 1 Dedicated Registers MB95130 MB Series Table 5 1 2 Direct Address Instruction List Applicable Instruction CLRB dir bit SETB dir bit BBC dir bit rel BBS dir bit rel MOV A dir ADDC SUBC A dir MOV dir A XOR A dir AND A dir OR A dir MOV dir imm CMP dir imm MOVW A dir MOVW dir A 38 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 5 CPU MB951 30 MB Series 5 1 Dedicated Registers 5 1 3 Condition Code Register CCR The condition code register CCR in the lower eight bits of the program status PS register consists of the bits H N Z V and C containing information about the arithmetic result or transfer data and the bits I IL1 and ILO used to control the acceptance of interrupt requests E Configuration of Condition Code Register CCR Figure 5 1 5 Configuration of Condition Code Register RP DP CCR bit15 0114 biti3 bit12 bitii bit1O bit9 bits bit7 bits bit4 bits bit2 biti bitO ee PS R4 R3 R2 R1 RO DP2 DP1 DPO H IL1 ILO N Z V C 00110000 Half carry flag Interrupt enable flag Interrupt level
60. 498 APPENDIX C Memo Map iecit ente he e cei rg dat reed estote De bd ene Pe ung abere retenta 499 APPENDIX D Pin Status of MB95130 MB series 501 APPENDIX E Instruction Overview ns intret ensi nnns 5038 APPENDIX F Mask ODON tU rade cn ri ener ER ie REED tange 519 APPENDIX G Writing to Flash Microcontroller Using Parallel Writer ss 521 yp M 523 Register NdexX 539 Pin F nction Index i n ca nob WF dS CR 541 Interrupt Vector Index CHAPTER 2 HANDLING DEVICES 2 1 Device Handling Precautions E Device Handling Precautions Main changes in this edition Page Changes For details refer to main body Added 6 Serial Communication Bi Pin Connection Added C pin CHAPTER 7 RESET 7 2 Reset Source Register RSRR E Configuration of Reset Source Register RSRR Figure 7 2 1 Write access to this bit sets it to gt Writing sets the bit to 0 Table 7 2 1 Corrected description of bit5 This bit varies only with the models equipped with the clock supervi sor 25 Read or write access 0 or 1 to this bit sets it to 0 Corrected the following descriptions of bit4 to bit e Read w
61. Accumulator A The accumulator is a 16 bit register for arithmetic operation It is used for a variety of arithmetic and transfer operations of data in memory or data in other registers such as the temporary accumulator T The data in the accumulator can be handled either as word 16 bit data or byte 8 bit data For byte length arithmetic and transfer operations only the lower eight bits AL of the accumulator are used with the upper eight bits AH left unchanged The initial value after a reset is 00004 34 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 5 CPU MB951 30 MB Series 5 1 Dedicated Registers Temporary accumulator T The temporary accumulator is an auxiliary 16 bit register for arithmetic operation It is used to perform arithmetic operations with the data in the accumulator A The data in the temporary accumulator is handled as word data for word length 16 bit operations with the accumulator A and as byte data for byte length 8 bit operations For byte length operations only the lower eight bits TL of the temporary accumulator are used and the upper eight bits TH are not used When a MOV instruction is used to transfer data to the accumulator A the previous contents of the accumulator are automatically transferred to the temporary accumulator When transferring byte length data the upper eight bits TH of the temporary accumulator remain unchanged The initial value after a reset is 00004
62. Clock mode select e Single system clock mode Dual system clock mode Specify when ordering MASK selectable Setting disabled Single system clock mode Setting disabled Dual system clock mode Setting disabled Changing by the switch on MCU board Low voltage detection reset With low voltage detection reset Without low voltage detection reset Specify when ordering MASK Specified by part number Specified by part number Changing by the switch on MCU board Clock supervisor With clock supervisor Without clock supervisor Specify when ordering MASK Specified by part number Specified by part number Changing by the switch on MCU board Reset output With reset output Without reset output Specify when ordering MASK Specified by part number Specified by part number MCU board switch set as following With supervisor Without reset output Without supervisor With reset output Oscillation stabilization wait time Fixed to oscillation stabilization wait time of 21 2 Foy Fixed to oscillation stabilization wait time of 2 4 2 Foy Fixed to oscillation stabilization wait time of 214 2 Foy Fixed to oscillation stabilization wait time of 21 2 Foy Foy Main clock Refer to table below about clock mode select low voltage detection reset clock supervisor select and reset output CM
63. IX SP A lt PC CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 515 APPENDIX APPENDIX E Instruction Overview MB951 30 MB Series Note In automatic transfer to T during byte transfer to A AL is transferred to TL If an instruction has plural operands they are saved in the order indicated by MNEMONIC Arithmetic Operation Instructions Table E 4 2 Arithmetic Operation Instruction 1 2 MNEMONIC Operation OPCODE A Ri A lt A 48 lt 48 A dir lt A dir A IX off lt A off A EP lt A EP C A D 4 C AL lt AD TD lt A Ri C A lt A d8 C A lt dir C A GIX off A A UX off C A EP lt A EP C C AL lt TL AD C RD RD 1 lt EP 1 IX lt IX 1 A lt A 1 Ri lt Ri 1 lt EP 1 IX lt IX 1 lt A I lt AL x TL lt MOD T lt A D A lt A v T A lt A v T TL AL T A A 48 A dir A dir A EP A EP A GIX off A off A Ri decimaladjustforaddi
64. Operation Example operation Read replacement data from outside The built in ROM code to be modified is in the address through its specific communication FOl11g and the data to be modified is B5g Three built method in ROM codes can be modified Write the replacement address unto Mie Set Wild register address setup registers wild register address setup register WRARO F011 WRARI WRAR2 WRARO to WRAR2 Hm Ue e Write a new ROM code replacement for the built in ROM code to the wild Set Wild register data setup registers register data setup register WRDRO to WRDRO B5y WRDRI WRDR2 WRDR2 Setting bitO of the address compare enable register WREN to 1 enables the wild register function for the wild register number 0 If the address matches the value set in the address setup register WRAR the value of the data setup register WRDR will replace the built in ROM code When replacing more than one built in ROM code enable the corresponding bits of the address compare enable register WREN Enable the corresponding bits in the wild register address compare enable register WREN B Wild Register Applicable Addresses The wild register is applicable to all addresses in the address space except 00784 As address 00784 is used as a mirror address for the register bank pointer and direct bank pointer this address cannot be patched CM26 10118 3E FUJITSU MICROELECTRONICS
65. Readable writable Read value is the same as write value This register is used to set the duty of the PPG output H pulse width when normal polarity CM26 10118 3E In 16 bit PPG mode PDSOI serves as the upper 8 bits while PDSOO serves as the lower 8 bits In 16 bit PPG mode write the upper bits before the lower bits When only the upper bits are written the previously written value is reused in the next load By writing to PDS00 PDSOI is updated Initialized at reset To set the duty to 0 select 00g To set the duty to 100 set it to the same value as the 8 16 bit PPG timer 00 01 cycle setup register PPS When the 8 16 bit PPG timer 00 01 duty setup register PDS is set to a larger value than the setting value of the 8 16 bit PPG cycle setup buffer register PPS the PPG output becomes L output in the normal polarity when the output level inversion bit of 8 16 bit PPG output inversion register 15 0 If the duty settings are modified during operation the modified value will be effective from the next PPG cycle FUJITSU MICROELECTRONICS LIMITED 249 CHAPTER 16 8 16 BIT PPG 16 5 Registers of 8 16 bit PPG 16 5 5 8 16 bit PPG Start Register PPGS MB95130 MB Series The 8 16 bit PPG start register PPGS starts or stops the down counter The operation enable bit of each channel is assigned to the PPGS register allowing simultaneous
66. TOODR TO1DR Sets H pulse width compare value O Used bit x Unused bit 1 Set 1 0 Set 0 In PWM timer function fixed cycle mode a fixed cycle PWM signal in a variable H pulse width is outputted from the timer output pin TOOO TOOI The cycle is fixed to FFy in 8 bit operation or FFFFgq in 16 bit operation The time is determined by the count clock selected The pulse width is specified by the value in the 8 16 bit compound timer 00 01 data register TOODR TOIDR This function has no effect on the interrupt flag TOOCR1 TOICRI IF As each cycle always starts with pulse output the timer output initial value setting bit TOOCR1 TO1CR1 SO is meaningless The value of the 8 16 bit compound timer 00 01 data register TOODR TOIDR is transferred to the temporary storage latch comparison data storage latch in the comparator either when the counter starts counting or when a counter value comparison match is detected When the timer stops operation the timer output bit TMCRO TOO TO1 holds the last value The H pulse is one count clock shorter than the setting value in the output waveform immediately after activation of the timer write 1 to the STA bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 225 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 10 Operating Description of PWM Timer Function Fixed cycle mode MB951 30 MB Series Figure 15 10 2 Operating Diagram of PWM Timer Function Fixed cycle Mode
67. TOODR TO1DR register value 00 duty ratio 0 Counter value 00H FFy 004 gt H PWM waveform Lh TOODR TO1DR register value 804 duty ratio 50 Counter value 004 0 80 m FFy 004 H PWM waveform TOODR TO1DR register value FF duty ratio 99 6 Counter value 00 M9 005 59 1 1 PWM waveform One count width Note When the PWM function has been selected the timer output pin holds the level used when the counter stops TOOCRO TO1CRO STA 0 226 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 11 Operating Description of PWM Timer Function Variable cycle Mode 15 11 Operating Description of PWM Timer Function Variable cycle Mode This section describes the operations of the PWM timer function variable cycle mode for the 8 16 bit compound timer E Operation of PWM Timer Function Variable cycle Mode The compound timer requires the settings shown in Figure 15 11 1 to serve as the PWM timer function variable cycle mode Figure 15 11 1 Settings for PWM Timer Function Variable cycle Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO 0 1 0 0 TOOCR1 T01CR1 STA HO IE IR BF IF SO OE 1 TMCRO TO1 TOO IIS MOD FE11 FE10 FEO1 FEOO
68. To set the clock source select the external clock and its direct use SMR EXT 1 OTO 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 387 CHAPTER 22 LIN UART 22 6 LIN UART Baud Rate MB95130 MB Series Figure 22 6 1 LIN UART Baud Rate Selection Circuit GUT Reload value V falling edge detection of a start bit Reception Rxc 0 1 Reception clock 15 bit reload counter Reload Reload value V Transmission MCL 15 bit reload counter Machine clock SCK External clock input Counter value Txc Transmission clock Internal data bus ll BGR7 T nas a EXT Register REST BaRa 99 OTO BGR2 BGRO 388 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 6 LIN UART Baud Rate 22 6 1 Baud Rate Setting This section shows baud rate settings and the calculation result of serial clock frequencies E Baud Rate Calculation The two 15 bit reload counters are set by the baud rate generator register 1 0 BGR1 BGRO The expressions for the baud rate are as follows Reload value v Reload value b Baud rate MCLK Machine clock or external clock frequency Calculation example Assuming that the machine clock is 10MHZ the internal clock is used and the baud rate is set to 19200 bps Reload value 6 Rus ME ME NET 19200 Thus the actual baud rate can be calculated as follows M
69. Upper 4 bits same as RA PA and SA gt U Upper 4 bits same as RA and PA xiii Changes For details refer to main body 26 5 Checking the Automatic Algorithm Execution Status E Hardware Sequence Flag Overview of hardware sequence flag Changed description consists of the following 4 bit outputs gt consists of the following 3 bit outputs Deleted Toggle bit 2 flag DQ2 Deleted Note however that hardware sequence flags are output only for the bank on a command issued side Table 26 5 1 Changed bit 2 DQ22 Table 26 5 2 26 5 4 Toggle Bit 2 Flag DQ2 Deleted column of DQ2 Deleted Note at the bottom of the table Deleted whole section of 26 5 4 APPENDIX APPENDIX A I O Map 1 0 Map Changed the column of 0073y 00744 0075y to Prohibited APPENDIX B Table of Interrupt Causes Table of Interrupt Causes Changed the column Address of vector table Upper Mode data in Table B 1 FFFCy gt The vertical lines marked in the left side of the page show the changes xiv CHAPTER 1 DESCRIPTION This chapter explains a feature and a basic specification of the MB95130 MB series 1 1 Feature of MB95130 MB Series 1 2 Product Lineup of MB95130 MB Series 1 8 Difference Points among Products and Notes on Selecting a Product 1 4 Block Diagram of MB95130 MB Series 1 5 Pin Assignment 1 6 Package Dimension 1 7 Pin Description 1 8 I O Circuit Ty
70. _ RDR read by CPU CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 407 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series 22 7 4 Serial Pin Direct Access Transmission pin SOT or reception pin SIN can be accessed directly E LIN UART Pin Direct Access The LIN UART allows the programmer to directly access the serial I O pins The status of the serial input pin SIN can be read by using the serial I O pin direct access bit ESCR SIOP You can set the value of the serial output pin SOT arbitrarily when the serial output is enabled SMR SOE 1 after direct write to the serial output pin SOT is enabled ESCR SOPE 1 and then 0 or 1 is written to the serial I O pin direct access bit ESCR SIOP In LIN mode this feature is used for reading transmitted data or for error handling when a LIN bus line signal is physically incorrect Note Direct access is allowed only when transmission is not in progress the transmission shift register is empty Before enabling transmission SMR SOE 1 write a value to the serial output pin direct access bit ESCR SIOP This prevents a signal of an unexpected level from being output since the SIOP bit holds a previous value While the value of the SIN pin is read by normal read the value of the SOT pin is read for the SIOP bit by the read modify write RMW instructions 408 FUJITSU MICROELECTRONICS LI
71. a N A DO X D1 X D2 X D3 X TDRE ks Transmission interrupt po B M MN A ce ME eee wie ee eee E EE eee ease ease ue E qc EE Figure 20 7 8 Setting Timing 2 for Transmit Data Register Empty Flag TDRE When TXE Is Switched from 0 to 1 Writing of transmit data uoo L w X X XX m X TDRE Transmission interrupt Concurrent transmission and reception In asynchronous clock mode UART transmission and reception can be performed independently Therefore transmission and reception can be performed at the same time or even with transmitting and receiving frames overlapping each other in shifted phases CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 335 CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example 20 7 2 Operating Description of Operation Mode 1 Operation mode 1 operates in synchronous clock mode E Operating Description of UART SIO Operation Mode 1 Setting the MD bit in UART SIO serial mode control register 1 SMCIO to 1 selects synchronous clock mode SIO The character bit length in synchronous clock mode SIO is variable between 5 bits and 8 bits Note however that parity is disabled and no stop bit is used The serial clock is selected by the CKS bit in the SMCIO register Select the dedicated baud rate generator or external clock The SIO p
72. x ADC2 AD8 TIM1 TIMO ADCK ADIE EXT CKDIV1 CKDIVO 1 9 ADDH A D converted value retained Used bit x Unused bit 1 Setto 1 When continuous activation is enabled A D conversion is activated at the rising edge of the selected input clock to start the A D conversion function Continuous activation is stopped by disabling it ADC2 EXT 0 E Operations of A D Conversion Function This section details the operations of the 8 10 bit A D converter 1 When A D conversion is started the conversion flag bit is set ADC1 ADMV 1 and the selected analog input pin is connected to the sample and hold circuit 2 The voltage at the analog input pin is loaded into the sample and hold capacitor in the sample and hold circuit during the sampling cycle This voltage is held until A D conversion has been completed 3 The comparator in the control circuit compares the voltage loaded into the sample and hold capacitor with the A D conversion reference voltage from the most significant bit MSB to the least significant bit LSB and then sends the results to the ADDH and ADDL registers After the results have been completely transferred the conversion flag bit is cleared ADCI ADMV 0 and the interrupt request flag bit is set ADC1 ADI 1 Notes When the A D conversion function is used the contents of the ADDH and ADDL registers are retai
73. 1 1 1 1 1 1 1 f T Count clock cycle m PPS register value n PDS register value The value changes depending on the count clock selected and the start timing Example for setting the duty to 5096 When PDS is set to 024 with PPS set to 041 the PPG output is set at a duty ratio of 50 PPS setting value 2 set to PDS CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 255 CHAPTER 16 8 16 BIT PPG 16 7 Operating Description of 8 16 bit PPG MB951 30 MB Series 16 7 2 8 bit Prescaler 8 bit PPG Mode In this mode the rising and falling edge detection pulses from the PPG timer 01 output can be used as the count clock of the PPG timer 00 down counter to allow variable cycle 8 bit PPG output from PPG timer 00 E Setting 8 bit Prescaler 8 bit PPG Mode The unit requires the register settings shown in Figure 16 7 3 to operate in 8 bit prescaler 8 bit PPG mode Figure 16 7 3 Setting 8 bit Prescaler 8 bit PPG Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito PCO1 PIE1 PUF1 POEN1 CKS12 CKS11 CKS10 PCOO MD1 MDO PIEO PUFO POENO 502 CKS01 CKS00 0 1 x x x PPS01 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PHO N Set PPG output cycle for PPG timer 01 PPSOO PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO Set PPG output cycle for PPG timer 00
74. BGR1 Q Start counting Writing a reload value to the LIN UART baud rate generator registers 1 0 BGR1 BGRO causes the reload counter to start counting Restart The reload counter restarts in the following conditions For both transmit reception reload counter e LIN UART programmable reset SMR UPCL bit Programmable restart SMR REST bit For reception reload counter Start bit falling edge detection in asynchronous mode Simple timer function Two reload counters restart at the next clock cycle when the REST bit in the LIN UART serial mode register SMR is set to 1 This function enables the transmit reload counter to be used as a simple timer Figure 22 6 3 shows an example of using a simple timer by restarting the reload timer when reload value is 100 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 393 CHAPTER 22 LIN UART 22 6 LIN UART Baud Rate MB95130 MB Series Figure 22 6 3 Example of Using a Simple Timer by Restarting the Reload Timer Write SMR register REST bit ite write signa Reload Reload counter X 37 X 36 X 35 1001 99 X 98 X 97 X 96 X 95 X 94 X 93 X 92X 91 X 90 X 89 X 88 X 87 BGRO BGR1 register read signal ile The number of machine cycles after restart in this example is obtained by the following expression cyc v c 1 100 90 1 11 v Reload value c Reload counter value Note The re
75. CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series 22 4 6 LIN UART Extended Communication Control Register ECCR The LIN UART extended communication control register ECCR is used for the bus idle detection the synchronous clock setting and the LIN Synch break generation E Bit Configuration of LIN UART Extended Communication Control Register ECCR Figure 22 4 7 shows the bit configuration of the LIN UART extended communication control register ECCR Table 22 4 5 lists the function of each bit in the LIN UART extended communication control register ECCR Figure 22 4 7 Bit Configuration of LIN UART Extended Communication Control Register ECCR Address bit bit6 bits bit4 bit3 bit2 biti bitO Initial value 00994 LAR MS scoe ssm TBI 000000XXe RX WORO W R W R W R WRX WOR WX R WX TBI Transmit bus idle detection flag bit 0 In transmission 1 No transmission RBI Reception bus idle detection flag bit 0 In reception 1 No reception Reserved bit The read value is indeterminate 0 is always set SSM Start stop enable bit mode 2 0 No start stop bit 1 With start stop bit SCDE Serial clock delay enable bit mode 2 0 Disable clock delay 1 Enable clock dela MS Sending side receiving side of serial clock selection bit mode 2 0 Sending side of serial clock serial clock generation
76. Conversion completed with no effect on others Analog input channel select bits ANOO pin ANO1 pin ANO2 pin ANOS pin 4 pin ANO5 pin ANO6 pin R W Readable writable Read value is the same as write value R WX Read only Readable writing has no effect on operation RO W Write only Writable 0 is read R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction Initial value Do not select the unusable channel for this series by analog input channel select bits ANS3 to ANSO 434 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 4 Registers of 8 10 bit A D Converter Table 23 4 1 Functions of Bits in 8 10 bit A D Converter Control Register 1 ADC1 Bit name Function Select the analog input pin to be used from among ANOO to ANOT ANS3 ANS2 Note that the number of analog input pins differs depending on the series ANSI ANSO When A D conversion is activated AD 1 via software ADC2 EXT 0 these bits can be Analog input updated at the same time channel select bits Note When the ADMV bit is 1 do not update these bits The pins not used as analog input pins can be used as general purpose ports Detects the termination of A D conversion When the A D conversion function is used the bit is set 1 upon terminatio
77. Count clock selector The clock for the countdown of 16 bit down counter is selected from eight types of internal count clocks 16 bit down counter It counts down with the count clock selected with the count clock selector CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 265 CHAPTER 17 16 BIT PPG TIMER 17 2 Configuration of 16 bit PPG Timer MB951 30 MB Series Comparator circuit The output is kept H until the value of 16 bit down counter is corresponding to the value of 8 16 bit PPG duty setting buffer register from the value of 16 bit PPG cycle setting buffer register Afterwards after keep L the output until the counter value is corresponding to 1 it keeps counting 8 bit down counter from the value of 16 bit PPG cycle setting buffer register 16 bit PPG down counter register upper lower PDCRHO PDCRLO The value of 16 bit down counter of 16 bit PPG timer is read 16 bit PPG cycle setting buffer register upper lower PCSRHO PCSRLO The compare value for the cycle of 16 bit PPG timer is set 16 bit PPG duty setting buffer register upper lower PDUTHO PDUTLO The compare value for width of 16 bit PPG timer is set 16 bit PPG status control register upper lower PCNTHO PCNTLO The operation mode and the operation condition of 16 bit PPG timer are set B Input Clock The 16 bit PPG timer uses the output clock from the prescaler as its input clock count clock 266 FUJITSU MICROELECTRONIC
78. Disables transmission data register empty interrupt 1 Enables transmission data register empty interrupt TCIE Transmission completion interrupt enable bit 0 Disables transmission completion interrupt 1 Enables transmission completion interrupt Reception interrupt enable bit 0 1 Disables reception interrupt E nables reception interrupt 0 Disables transmission operation 1 Enables reception operation Reception error flag clear bit 0 1 lears each error flag No effect on the operation Serial data output enable bit 0 Disables serial data output usable as port 1 Enables serial data output Serial clock output enable bit O Disables serial clock output usable as port 1 Enables serial clock output R W Readable writable Read value is the same as write value R1 W Readable writable Read value is always 1 Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 321 CHAPTER 20 UART SIO 20 5 Registers of UART SIO MB95130 MB Series Table 20 5 2 Functional Description of Each Bit of UART SIO Serial Mode Control Register 2 SMC20 Bit name Function SCKE Serial clock output enable bit This bit controls the input output of the serial clock UCKO pin in clock synchronous mode Setting the bit to 0 allows the pin to be used as a general purpose port Setting the
79. For information about the sample programs for UART SIO refer to I Sample Programs in Preface E Setting Methods not Covered by Sample Programs How to select the operation mode The operation mode select bit SMC10 MD is used Operation mode Operation mode selection MD Asynchronous clock mode UART Set the bit to 0 Synchronous clock mode SIO Set the bit to 1 Operation clock types and how to select it The clock select bit SMC10 CKS is used Clock input Clock selection CKS To select a dedicated baud rate generator Set the bit to 0 To select an external clock Set the bit to 1 How to use UCKO UIO and UOO pin Uses the following setting DDRI P12 0 To set the UCKO pin as input SMC20 SCKE 0 To set the UCKO pin as output SMC20 SCKE 1 When using UIO pin DDR1 P10 0 When using pin SMC20 TXOE 1 342 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 8 Sample Programs for UART SIO Q How to enable stop UART operation The reception operation enable bit SMC20 RXE is used Control item Reception interrupt enable bit RXE Disabling stopping reception Set the bit to 0 Enabling reception Set the bit to 1 The transmission operation control bit SMC20 TXE is used Control item Transmission operation enable bit TXE Disabling stopping transmission Set the bit to 0 Enabling tran
80. Internal count clock cycle Interval time 210 X 2 Foy 512 0 us 212 X 2 Foy 2 05ms 2 Fcg 0 5 us 214 X 2 Foy 8 19ms 216 X 2 Foy 32 77ms Foy Main clock The values in parentheses represent the values used when the main clock operates at 4MHz FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 10 TIME BASE TIMER MB951 30 MB Series 10 2 Configuration of Time base Timer 10 2 Configuration of Time base Timer The time base timer consists of the following blocks e Time base timer counter Counter clear circuit Interval timer selector e Time base Timer Control Register TBTC E Block Diagram of Time base Timer Figure 10 2 1 Block Diagram of Time base Timer Time base timer counter To prescaler To watchdog timer To clock control block Main PLL oscillation stabilization wait iy x 2 x 2 211 2x 2 25x 216 217x 28x 2x 220 Dell 22 divide by 2 Counter clear 214 2 1 2 2 Fcn To clock control block oscillation stabilization wait time selector Watchdog timer clear Counter Interval timer Resets stops Main clock claeir citi selector Time base timer interrupt sF THE r amp co Time base timer control register TBTC Feu Main clock CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 133 CHAPTER 10 TIME BASE TIMER 10 2 Configuration of Time base Timer MB951 30 MB Series
81. Interrupt During Operation of External Interrupt Lice ce ee ettet 295 List of Registers of External Interrupt Gic 292 Notes on Using External Interrupt eire 298 Operation of External Interrupt Circuit 296 Pins Related to External Interrupt Circuit 291 Registers and Vector Table Related to Interrupts of External Interrupt Circuit 295 Sample Programs for External Interrupt 299 External Interrupt Control Register External Interrupt Control Register EICOO 293 F F MC 8FX Instruction Overview of F7MC 8FX 503 Feature Feature of MB95130 MB 2 Fixed cycle Mode Operation of PWM Timer Function Fixed cycle Mode 225 PWM Timer Function Fixed cycle Mode 196 Flag Set Reception Interrupt Generation and Flag Set Timing 383 Transmit Interrupt Generation and Flag Set Timing 385 Flash memory Details of Programming Erasing Flash Memory 476 Erasing AII Data from Flash Memory Chip Erase iier nn 480 Features of 256 Kbit Flash Memory 466 Flash Memory Programming Procedure 478 Flash Memory Programming BT SIBg e ewes cies Snes Save de 466 Overview of 256 Kbit Flash Memory 466 Placing Flash Memory in the Read Reset State 477 Programming Data into Flash Memory Re
82. MB95130 MB Series 15 12 Operating Description of PWC Timer Function 15 12 Operating Description of PWC Timer Function This section describes the operations of the PWC timer function for the 8 16 bit compound timer E Operation of PWC Timer Function The compound timer requires the settings shown in Figure 15 12 1 to serve as the PWC timer function Figure 15 12 1 Settings for PWC Timer Function bit7 bit6 bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO TOOCR1 T01CR1 STA HO IE IR BF IF SO OE 1 TMCRO TO1 TOO IIS MOD FE11 FE10 FEO1 FEOO O O O TOODR TO1DR Holds pulse width measurement value O Used bit x Unused bit 1 Set 1 When the PWC timer function is selected the width and cycle of an external input pulse can be measured The edges to start and end counting are selected by timer operation mode setting TOOCRO TO1CRO F3 F2 F1 F0 In this operation mode the counter starts counting from 00 upon detection of the specified count start edge of an external input signal Upon detection of the specified count end edge the count value is transferred to the 8 16 bit compound timer 00 01 data register TOODR TOIDR and the interrupt flag TOOCR1 TO1CR1 IR and buffer full flag TOOCR1 TOICR1 BF are set to 1 The buffer full flag is set to when the 8 16 bit compound timer 00 01 dat
83. Machine Clock 10MHz 16MHz 16 25MHz Dedicated baud rate generator setting Baud rate Baud rate Baud rate Bae UART Total division ratio 10MHz 16MHz 16 25MHz aud rate Internal PSS x BRS x 4 Total Total Total counter setting division division division division Prescaler selection PSS 1 0 BRS 7 0 ratio ratio ratio 1 Setting value 0 0 125000 200000 203125 1 Setting value 0 0 113636 181818 184659 1 Setting value 0 0 56818 90909 92330 1 Setting value 0 0 28736 45977 46695 1 Setting value 0 0 19231 30769 31250 2 Setting value 0 1 9615 15385 15625 4 Setting value 1 0 4808 7692 7813 8 Setting value 1 1 2404 3846 3906 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 329 CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example The baud rate in clock asynchronous mode can be set in the following range Table 20 7 3 Baud Rate Setting Range in Clock Asynchronous Mode 00g to 11g 024 2 to 255 Transfer data format UART can treat data only in NRZ Non Return to Zero format Figure 20 7 2 shows the transfer data format The character bit length can be selected from among 5 to 8 bits depending on the CBL1 and CBLO settings The stop bit length can be set to 1 or 2 bits depending on the SBL setting PEN and TDP can be used to enable disable parity and to select parity polarity As
84. Only for 5V products it is an effective register 2 For the 5V product the C pin is used CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 127 CHAPTER 9 I O PORT 95130 9 5 2 Operations of Port G This section describes the operations of port G E Operations of Port G Operation as an output port Setting the corresponding DDR register bit to 1 sets a pin as an output port e When a pin is set as an output port it outputs the value of PDR register to pins If data is written to the PDR register the value is stored in the output latch and output to the pin as it is Reading the PDR register returns the PDR register value Operation as an input port Setting the corresponding DDR register bit to 0 sets a pin as an input port e If data is written to the PDR register the value is stored in the output latch but not output to the pin Reading the PDR register returns the pin value However the read modify write command returns the PDR register value Operation at reset Resetting the CPU initializes the DDR register values to 0 and sets the port input enabled Operation in stop mode and watch mode fthe pin state specification bit in the standby control register STBC SPL is set to 1 when the device switches to stop or watch mode the pin is set forcibly to the high impedance state regardless of the DDR register value Note that the input is locked to
85. PDSO1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit0 Reset value OF9E PDSO1 DH7 DH6 DH5 DH4 DH3 DH2 DH1 DHO 111111116 R W R W R W R W R W R W R W R W 8 16 bit PPG timer 00 duty setup buffer register PDSOO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit Reset value OF9F PDSOO DL7 DL6 DL5 DL4 DL3 DL2 DL1 DLO 11111111 R W R W R W R W R W R W R W R W 8 16 bit PPG start register PPGS Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OFA4y PENO1 PENOO 000000008 RO WX RO WX RO WX RO WX RO WX RO WX RW R W 8 16 bit PPG output inversion register REVC Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OFA5y REVO1 REVOO 00000000 RO WX RO WX RO WX RO WX RO WX RO WX R W R W R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction RO WX Undefined bit Read value is 0 writing has no effect on operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 243 CHAPTER 16 8 16 BIT PPG 16 5 Registers of 8 16 bit PPG MB951 30 MB Series 16 5 1 8 16 bit PPG Timer 01 Control Register ch 0 PCO1 The 8 16 bit
86. Readable writable Read value is the same as write value MCLK Machine clock 1 value 436 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 4 Registers of 8 10 bit A D Converter Table 23 4 2 Functions of Bits in 8 10 bit A D Converter Control Register 2 ADC2 Bit name Function This bit selects the resolution of A D conversion When set to 0 The bit selects 10 bit precision ADS When set to 1 The bit selects 8 bit precision in which case eight bits of data can be read Precision select bit from the ADDL register Note The data bits used are different depending on the resolution Update this bit only with A D operation stopped before starting conversion Set the sampling time TIMI TIMO Change this sampling time setting depending on the operating conditions voltage and Sampling time frequency select bits The CKIN value is determined by the clock select bits ADC2 CKDIV 1 DKDIVO Note Update this bit only with A D operation stopped ADCK External start Selects the start signal for external start ADC2 EXT 1 signal select bit ADIE Enables or disables output of interrupts to the interrupt controller Interrupt request Interrupt requests are output with both of this bit and the interrupt request flag bit ADC1 ADI enable bit set to 1 EXT Continuous Selects whether to activate the A D conversion function via software
87. SCR LIN UART serial control register 000000005 SMR LIN UART serial mode register 000000005 SSR LIN UART serial status register 00001000 RDR TDR LIN UART reception transmission data register 000000005 ESCR LIN UART extended status control register 00000100 ECCR LIN UART extended communication control register 000000 SMCIO UART SIO serial mode control register 1 ch 0 000000005 SMC20 UART SIO serial mode control register 2 ch 0 001000005 SSRO UART SIO serial status register ch 0 00000001 TDRO UART SIO serial output data register ch 0 000000005 RDRO UART SIO serial input data register ch 0 000000005 Prohibited A D converter control register 1 000000005 A D converter control register 2 000000005 A D data register upper 000000005 A D data register lower 000000005 Watch counter control register 00000000 Prohibited Flash memory status register 000x0000 Prohibited Wild register address compare enable register CM26 10118 3E Wild register data test setting register FUJITSU MICROELECTRONICS LIMITED 495 APPENDIX APPENDIX A I O Map MB95130 MB Series Table A 1 MB95130 MB Series 3 4 Address Register abbreviation Register name Register bank pointer RP Mirror of direct bank register DP Initial val
88. Table E 3 1 Bus Operation for Bit Manipulation Instructions MNEMONIC Address bus Data bus AO to A7 CLRB dir b N42 Next instruction dir address Data A8 to AF SETB dir b dir address Data N 3 Instruction after next E Read Destination on the Execution of Bit Manipulation Instructions For some I O ports and the interrupt request flag bits the read destination differs between a normal read operation and a read modify write operation V O ports during a bit manipulation From some I O ports an I O pin value is read during a normal read operation while a port data register value is read during a bit manipulation This prevents the other port data register bits from being changed accidentally regardless of the I O directions and states of the pins Interrupt request flag bits during a bit manipulation An interrupt request flag bit functions as a flag bit indicating whether an interrupt request exists during a normal read operation however 1 is always read from this bit during a bit manipulation This prevents the flag from being cleared accidentally by writing the value 0 to the interrupt request flag bit when manipulating another bit 514 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX E Instruction Overview E 4 F MC 8FX Instructions Table E 4 1 to Table E 4 4 show the instructions used by the F MC 8FX E Transfer Instructions Table E 4 1 Trans
89. WDTC activates or clears the watchdog timer Watchdog Timer Control Register WDTC Figure 11 3 2 Watchdog Timer Control Register WDTC Address pit7 bite bits bit bitO Initial value CS1 CS0 wTe2 WTE1 WTEO 000000008 R W R W RO WX RO WX ROW ROW ROW ROW LS wrESWTEZIWTET WTEG Watchdog Activate watchdog timer in first write after reset Clear watchdog timer in second or succeeding write after reset No effect on operation Count clock switch bits Output cycle of time base timer 221 Output cycle of time base timer 220 Output cycle of watch prescaler 214 Fct Output cycle of watch prescaler 213 FoL R W Readable writable Read value is the same as write value RO W Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined Initial value Fen Main clock Fe Sub clock 150 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 11 WATCHDOG TIMER MB951 30 MB Series 11 3 Register of The Watchdog Timer Table 11 3 1 Functional Description of Each Bit of Watchdog Timer Control Register WDTC Bit name Function These bits select the count clock of the watchdog timer Count clock switch bits Output cycle of time base timer 221 Output cycle of time base timer 220 CS1 CSO Outpu
90. When the clock mode is sub PLL clock mode the device waits for the sub PLL clock oscillation stabilization wait time to elapse If the sub PLL oscillation enable bit in the PLL control register PLLC SPEN contains 1 however the device does not wait for that time to elapse even when the clock mode is sub PLL clock mode FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 8 Operations in Low power Consumption Modes Standby Modes 6 8 2 Sleep Mode Sleep mode stops the operations of the CPU and watchdog timer E Operations in Sleep Mode Sleep mode stops the operating clock for the CPU and watchdog timer In this mode the CPU stops while retaining the contents of registers and RAM that exist immediately before the transition to sleep mode but the peripheral resources except the watchdog timer continue operating Q Transition to sleep mode Writing 1 to the sleep bit in the standby control register STBC SLP causes the device to enter sleep mode Cancellation of sleep mode A reset or an interrupt from a peripheral resource releases the device from sleep mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 75 CHAPTER 6 CLOCK CONTROLLER 6 8 Operations in Low power Consumption Modes Standby MB95130 MB Series Modes 6 8 3 Stop Mode Stop mode stops the main clock E Operations in Stop Mode Stop mode stops the main clock In this mode the device stops all
91. activation of the PPG channels E 8 16 bit PPG Start Register PPGS Figure 16 5 6 8 16 bit PPG Start Register PPGS bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value Address eT O O Pen sumus RO WX RO WX RO WX RO WX RO WX RO WX R W PENOO PPG timer 00 ch 0 down counter operation enable bit 0 Stops operation 1 Enables operation PENO1 PPG timer 01 ch 0 down counter operation enable bit 0 Stops operation 1 Enables operation RO WX Undefined bit Read value is 0 writing has no effect on operation RAW Readable writable Read value is the same as write value Initial value 250 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 5 Registers of 8 16 bit PPG 16 5 6 8 16 bit PPG Output Inversion Register REVC The 8 16 bit PPG output inversion register REVC inverts the PPG output including the initial level E 8 16 bit PPG Output Inversion Register REVC Figure 16 5 7 8 16 bit PPG Output Inversion Register REVC bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value Aes J OFASH RO WX RO WX RO WX RO WX RO WX RO WX R W R W REVOO PPG timer 00 ch 0 output level inversion bit 0 Normal 1 Inversion REVO1 PPG timer 01 ch 0 output level inversion bit 0 Normal 1 Inversion RO WX Undefined bit Read value is 0 writing
92. detection in input capture function Excluded during 16 bit operation Interrupt flag TOICRI IF TOICRI IF TOICRI1 IR Interrupt enable CM26 10118 3E TOICRI IE and TO1CRO IFE TOICRI IE and TOICRO IFE FUJITSU MICROELECTRONICS LIMITED TOICRI IE 217 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 6 Interrupts of 8 16 bit Compound Timer MB951 30 MB Series E Registers and Vector Tables Related to Interrupts of 8 16 bit Compound Timer Table 15 6 3 Registers and Vector Tables Related to Interrupts of 8 16 bit Compound Timer Interrupt Interrupt Interrupt level setup register Vector table address source request No Register Setting bit Upper Lower Timer 00 Timer 01 The request numbers and vector tables of all peripheral functions are listed in APPENDIX B Table of Interrupt Causes 218 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 7 Operating Description of Interval Timer Function One shot Mode 15 7 Operating Description of Interval Timer Function One shot Mode This section describes the operations of the interval timer function one shot mode for the 8 16 bit compound timer E Operation of Interval Timer Function One shot Mode The compound timer requires the register settings shown in Figure 15 7 1 to serve as the interval timer function Figure 15
93. instruction use a 16 bit access instruction to write to the PCSRHO register address Use the MOV instruction and write to PCSRHO first and PCSRLO second If a down counter load occurs after writing data to PCSRHO but before writing data to PCSRLO the previous valid PCSRHO PCSRLO value will be loaded to the down counter If the PCSRHO PCSRLO value is modified during counting the modified value will become effective from the next load of the down counter Do not set PCSRHO and PCSRLO to 00g or PCSRHO to 01g and PCSRLO to Olp Note If the down counter load occurs after the MOV instruction is used to write data to PCSRLO before PCSRHO the previous valid PCSRHO value and newly written PCSRLO value are loaded to the down counter It should be noted that as a result the correct period cannot be set CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 271 CHAPTER 17 16 BIT PPG TIMER 17 5 Registers of 16 bit PPG Timer MB951 30 MB Series 17 5 3 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO The 16 bit PPG duty setting buffer registers control the duty ratio for the output pulses generated by the PPG E 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO Figure 17 5 4 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 16 bit PPG duty setting buffer register upper PDUTHO Address bitlb biti4 bit13 biti2 bitii bittO bit9 bit8 Initial value OFAE PD
94. ssssssssseseeseeeeeneneeeneennen nene nnne nennen 143 CHAPTER 11 WATCHDOG TIMER rina anna kia aa ir s ccr ara nana 145 11 1 Overview of Watchdog Timer sssssssssssssesesssseeeneeen nennen sn trnre enr sinn nrn nennt enne 146 11 2 Configuration of Watchdog Timer sssssssssssssesseneeeeneeenne entente nens nnns enne 147 11 3 Register of The Watchdog Timer NALEAN enn 149 11 3 1 Watchdog Timer Control Register WDTO 150 11 4 Explanation of Watchdog Timer Operations and Setup Procedure Example 152 11 5 Notes on Using Watchdog Timer ssssssssesssseeneeneeeneen nennen nennen enne en nnne 154 CHAPTER 12 WATCH PRESCALER 155 12 1 Overview of Watch Prescaler 156 12 2 Configuration of Watch Prescaler sssssssssssessseeeenee eene 157 12 3 Registers of the Watch Prescaler sss ennemi nennen enn 159 12 3 1 Watch Prescaler Control Register WPCR 160 12 4 Interrupts of Watch Prescaler 162 12 5 Explanation of Watch Prescaler Operations and Setup Procedure Example 164 12 6 Notes on Using Watch Prescaler ossessio
95. the counter starts to count down from 7FFFg Once 00004 is reached the counter returns to 7FFFq to continue the count When the time set by the interrupt interval time select bits is reached during down counting the watch interrupt request flag bit WPCR WTIF is set to 1 in any mode other than the main clock stop mode In other words a watch interrupt request is generated at each selected interval time based on the time when the counter was last cleared E Clearing Watch Prescaler If the watch prescaler is cleared when the output of the watch prescaler is used in other peripheral functions this will affect the operation by changing the count time or in other manners When clearing the counter by using the watch prescaler initialization bit WPCR WCLR perform setup so that this does not have unexpected effects on other peripheral functions When the output of the watch prescaler is selected as the count clock clearing the watch prescaler also clears the watchdog timer The watch prescaler is cleared not only by the watch prescaler initialization bit WPCR WCLR but also when the sub clock is stopped and a count is required for the oscillation stabilization wait time When moving from the sub clock mode or sub PLL clock mode to the stop mode When the sub clock oscillation stop bit in the system clock control register SYCC SUBS is set to 1 in the main clock mode or main PLL clock mode In addition the counter of the watc
96. v Falling edge detection Receive new frame CRE bit timing out of 1 2 bit time of stop bit Last data bit Stop bit Start bit SIN 1 2 bit time Error flag 1 Falling edge detection Receive new frame Reception state machine is reset start bit condition is reset reception is desynchronized CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 419 CHAPTER 22 LIN UART 22 8 Notes on Using LIN UART MB95130 MB Series Figure 22 8 2 Example of desynchronization RX read LU i Next falling edge is used as I I I 1 I start bit 1 1 we Or we e 1stFrame 2 i First asynchronous i 1 Start of second frame 1 asynchronous l frame a lt Lost bit Lost bit 420 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 8 Notes on Using LIN UART Figure 22 8 3 UART dominant bus operation When reception is always enabled RXE 1 L N FRE LLIN LLL TLD CRE AL E y Framing error Error is Reception is ongoing Next framing Falling edge is occurs cleared regardress of no falling error occurs next start bit edge edge When reception is temporarily disabled RXE 1 0 gt 1 y 555 p q Reception is reset Error is cleared Waitng for falling edge Falling edge is Framing err
97. 0 first and then clear the reception error flags If an error flag is cleared before the reception operation is disabled the reception will be aborted at that time and resume later This may result in a data reception error RXE Reception operation enable bit Enable or disable the reception of LIN UART 0 Disable data frame reception 1 Enable data frame reception The LIN synch break detection in mode 3 is not affected Note When the reception is disabled RXE 0 during reception the reception halts immediately In that case the data is not guaranteed TXE Transmit operation enable bit CM26 10118 3E Enable or disable the transmission of LIN UART 0 Disable data frame transmission 1 Enable data frame transmission Note When the transmission is disabled TXE 0 during transmission the transmission halts immediately In that case the data is not guaranteed FUJITSU MICROELECTRONICS LIMITED 367 CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series 22 4 2 LIN UART Serial Mode Register SMR The LIN UART serial mode register SMR is used to select the operation mode specify the baud rate clock and enable disable output to the serial data and clock pins Bi LIN UART Serial Mode Register SMR Figure 22 4 3 LIN UART Serial Mode Register SMR Address bit7 bit6 bits bit4 bit3 bit bit bitO Initial value did 000000008 R W R W R W R W RO W RO W R W R W
98. 0 d 1 LSB MSB Data Clock inversion When the SCES bit in the LIN UART extended status register ESCR is 1 the LIN UART clock is inverted and received data is sampled at the falling edge of the clock At this time the value of the serial data must be enabled at the timing of the clock falling edge 402 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART Continuous clock supply When the CCO bit in the ESCR is 1 the serial clock output from the SCK pin is supplied in the sending side of serial clock continuously In this mode add the start stop bit to the data format SSM 1 in order to identify the beginning and end of the data frame Figure 22 7 6 shows the continuous clock supply mode 2 Figure 22 7 6 Continuous Clock Supply Mode 2 Transmit reception clock SCES 0 1 Transmit reception clock SCES 1 1 Data stream SSM 1 ST SP No parity 1 stop bit Data frame Error detection When the start stop bits are disabled ECCR SSM 0 only overrun errors are detected Communication settings for synchronous mode To communicate in synchronous mode the following settings are required e LIN UART baud rate generator register 1 0 BGRO BGR1 Set the dedicated baud rate reload counter to a required value e LIN UART serial mode register SMR MD1
99. 1 imer operable Readable writable Read value is the same as write value Read only Readable writing has no effect on operation Initial value e value 1 is read by read modify write RMW instruction 208 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series 1 1 2 STA Timer operation enable bit CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer Table 15 5 2 Functional Description of Each Bit of 8 16 bit Compound Timer 00 01 Control Status Register Bit name Function This bit enables or stops timer operation Writing 0 stops the timer operation and sets the count value to 00g When the PWM timer function variable cycle mode has been selected TOOCRO TO1CRO F2 Fl FO 0100p the STA bit can be used to enable or disable timer operation from within either the TOOCR1 timer 00 or TO1CR1 timer 01 register In this case the STA bit in the other register is set to the same value automatically During 16 bit operation TMCRO MOD 1 use the STA bit in the TOOCRI timer 00 register to enable or disable timer operation In this case the STA bit in the other register is set to the same value automatically Writing 1 allows timer operation to start from count value 00g e Set this bit to 1 after setting the count clock select bits 2 CO timer operation select bits TOOCRO TOI1CRO F3 F2 F1
100. 1 In order to avoid desynchronization of the data stream it is necessary to set the CRE bit within a half bit time immediately after an error is received as shown in Figure 22 8 2 or to wait for the application dependent time while SINn is idling after an error is received 2 If a framing error occurs stop bit SINn 0 and the next start bit SINn 0 immediately follows it this start bit is recognized regardless of a falling edge for the start bit and reception is started This sequence is used for detecting the continuous L state of the serial data input SINn when the next framing error is detected while the data stream is synchronized See When reception is always enabled RXE 1 in Figure 22 8 3 If this operation is not necessary disable data reception temporarily after receiving a framing error RXE 1 0 1 Therefore the falling edge of the serial data input SINn is detected the start bit is recognized when L is detected at the reception sampling point and the reception is started See When reception is temporarily disabled RXEz1 0 1 in Figure 22 8 3 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 8 Notes on Using LIN UART Figure 22 8 1 CRE bit timing CRE bit timing within 1 2 bit time of stop bit Last data bit Stop bit Start bit s MENT SIN I I Error flag I i CRE v Reception state machine is reset
101. 1 6 shows how the carry flag is updated by a shift instruction Figure 5 1 6 Carry Flag Updated by Shift Instruction Left shift ROLC Right shift RORC bit7 bit7 gt bitO C lt aa E Interrupt Acceptance Control Bits 40 Interrupt enable flag 1 When this flag is set to 1 interrupts are enabled and accepted by the CPU When this flag is set to 0 interrupts are disabled and rejected by the CPU The initial value after a reset is 0 The SETI and CLRI instructions set and clear the flag to 1 and 0 respectively Interrupt level bits IL1 ILO These bits indicate the level of the interrupt currently accepted by the CPU The interrupt level is compared with the value of the interrupt level setting register ILRO to ILR5 that corresponds to the interrupt request IRQO to IRQ23 of each peripheral resource The CPU services an interrupt request only when its interrupt level is smaller than the value of these bits with the interrupt enable flag set CCR I 1 Table 5 1 3 lists interrupt level priorities The initial value after a reset is 11g Table 5 1 3 Interrupt Levels Interrupt Level Priority Low No interrupt The interrupt level bits IL1 ILO are usually 11g with the CPU not servicing an interrupt with the main program running For details on i
102. 1 Pins of External Interrupt Circuit Pin name Pin function External interrupt input ch 0 External interrupt input ch 1 External interrupt input ch 2 External interrupt input ch 3 External interrupt input ch 4 External interrupt input ch 5 External interrupt input ch 6 External interrupt input ch 7 Table 18 3 2 Registers of External Interrupt Circuit Register name Corresponding register Name in this manual EIC External Interrupt Control register The following sections only describe the unit 0 side of the external interrupt circuit The other units are the same as the unit 0 side of the external interrupt circuit 290 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT MB95130 MB Series 18 4 Pins of External Interrupt Circuit 18 4 Pins of External Interrupt Circuit This section shows the pins related to the external interrupt circuit and the block diagram of such pins B Pins Related to External Interrupt Circuit The pins related to the external interrupt circuit are the INTOO to INTO pins INTOO to INTO7 pins These pins serve both as external interrupt inputs and as general purpose I O ports INTOO to INTO7 When the corresponding pin of the INTOO to INTO7 pins is set as an input port by the port direction register DDR and the corresponding external interrupt input is enabled by the external interrupt control
103. 100V to 220V power adapter Writer dedicated RS232C cable for PC AT Standard target probe a Length 1 Fujitsu control module for F2MC 16LX flash microcontroller Remote controller 2Mbytes PC Card Option Flash memory capacity up to 128 Kbytes 4Mbytes PC Card Option Flash memory capacity up to 512 Kbytes Contact Yokogawa Digital Computer Co Ltd Tell 81 042 333 6222 Note Although the AF200 flash microcontroller programmer is an old model this can be handled using the FF201 control module The connection examples shown in the next chapter can also be used as example connections for serial writing 486 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION MB95130 MB Series 27 2 Example of Serial Programming Connection 27 2 Example of Serial Programming Connection Inputting MOD H from TAUX3 on the AF220 AF210 AF120 or AF110 to the mode pin which is set to MOD L by the user system sets the mode to serial write mode serial write mode MOD H P12 H P13 L E Example of Serial Programming Connection Figure 27 2 1 shows an example connection for serial writing The TTXD pin on the flash microcontroller programmer is connected to P10 UIO and outputs low until data transfer starts Setting in this way specifies that serial write mode uses clock synchronous communications Note that a user power s
104. 10118 3E FUJITSU MICROELECTRONICS LIMITED 477 CHAPTER 26 256 Kbit FLASH MEMORY 26 6 Flash Memory Program Erase MB95130 MB Series 26 6 2 Programming Data into Flash Memory This section explains the procedure for entering the write program command to program data into flash memory E Programming Data into Flash Memory To start the automatic algorithm for programming data into flash memory send the program command in the command sequence table continuously from the CPU to flash memory Upon completion of data programming to a target address in the fourth cycle the automatic algorithm starts automatic programming How to specify addresses Programming writing can be performed even in any order of addresses or across a sector boundary Data written by a single program command is only one byte Notes on programming data Bit data cannot be returned from O to 1 by programming When bit data I is programmed to bit data 0 the data polling function DQ7 or toggle operation DQ6 is not terminated the flash memory element is determined to be defective and the execution time out flag DQ5 detects an error to indicate that the specified programming time has been exceeded When data is read in the read reset state the bit data remains 0 To return the bit data from O to 1 erase flash memory All commands are ignored during automatic programming e Ifa hardware reset occurs during programming the d
105. 16 bit PPG duty setting buffer register lower PDUTL Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OFAF4 PDUTLO DUO7 DUO6 0005 DU04 DUO3 DU02 DUO1 DUOO 111111118 RW RW RW RW RW RW RW RW 16 bit PPG status control register upper PCNTH Address biti4 biti2 bitii bitiO bit9 bit8 Initial value 00424 PONTHO CNTE STRG MDSE RTRG CKS2 CKS1 CKSO PGMS 000000008 RW RO W RW RW RW RW RW RW 16 bit PPG status control register lower PCNTL Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit Initial value 00434 PCNTLO EGS1 EGSO IREN IRQF IRS1 IRSO POEN OSEL 000000008 RW RW RW RPM W RW RW RAN RW R W Readable writable Read value is the same as write value R WX Read only Readable writing has no effect on operation R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction RO W Write only Read value is 1 writing has no effect on operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 269 CHAPTER 17 16 BIT PPG TIMER 17 5 Registers of 16 bit PPG Timer MB951 30 MB Series 17 5 4 16 bit PPG Down Counter Registers Upper Lower PDCRHO PDCRLO The 16 bit PPG down counter registers upper lower PDCRHO PDCRLO form a 16 bit register which is used to read the count value from the 16 bit PPG
106. 16 bit PPGO ch 1 output Hysteresis Analog Automotive ANO2 analog input 2 2 ANO2 SCK P02 general purpose I O INTO2 external interrupt input LIN UART clock I O Hysteresis Analog Automotive ANO3 analog input P03 INTO3 ANO3 SOT general purpose I O INTO3 external interrupt input LIN UART data output Hysteresis Analog Automotive ANO04 analog input A el INTO4 external interrupt input ANOA SIN P04 g purpose I O LIN UART data input Hysteresis Analog CMOS Automotive ANOS analog input 5 5 POS INTOS external interrupt input ANO05 TOO00 8 16 bit compound timerO ch 0 output Hysteresis Analog Automotive ANO6 analog input PO6 INT06 P06 pexeral p rpose LO INT06 external interrupt input AN06 TOO1 8 16 bit compound timerO ch 1 output Hysteresis Analog Automotive ANO7 analog input POr TITON P07 general purpose I O ANO7 INTO7 external interrupt input OD Open drain PU Pull up For 5V products the hysteresis input can be switched to an automotive input It becomes a hysteresis input besides 110 FUJITSU MICROELECTRONICS LIMITED Hysteresis Analog Automotive CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 2 Port 0 E Block Diagram of Port 0 Figure 9 2 1 Block Diagram of Port 0
107. 1666 0 02 1692 0 02 7200 1110 lt 0 01 1388 lt 0 01 2221 lt 0 01 2256 lt 0 01 4800 1666 0 02 2082 0 02 3332 lt 0 01 3384 lt 0 01 2400 3332 lt 0 01 4166 lt 0 01 6666 lt 0 01 6770 lt 0 01 1200 6666 lt 0 01 8334 lt 0 01 13332 lt 0 01 13541 lt 0 01 600 13332 lt 0 01 16666 lt 0 01 26666 0 01 27082 0 01 300 26666 0 01 53332 0 01 54166 0 01 The unit of frequency deviation dev is 70 MCLK indicates the machine clock 390 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 6 LIN UART Baud Rate B External Clock The external clock is selected by writing 1 to the EXT bit in the LIN UART serial mode register SMR In the baud rate generator the external clock can be used in the same way as the internal clock When slave operation is used in synchronous mode 2 select the one to one external clock input mode SMR OTO 1 In this mode the external clock input to SCK is input directly to the LIN UART serial clock Note The external clock signal is synchronized with the internal clock MCLK machine clock in the LIN UART Therefore the signal is unstable because the external clock cannot be divided if its cycle is faster than half cycle of the internal clock Be sure not to set the cycle of the external clock is faster than half cycle of the internal clock For the value of the SCK clock see Data Sheet CM26 10118 3
108. 23 4 Registers of 8 10 bit A D Converter 23 4 Registers of 8 10 bit A D Converter The 8 10 bit A D converter has four registers A D converter control register 1 ADC1 A D converter control register 2 ADC2 A D converter data register upper ADDH and A D converter data register lower ADDL List of 8 10 bit A D Converter Registers Figure 23 4 1 lists the registers of the 8 10 bit A D converter Figure 23 4 1 Registers of 8 10 bit A D Converter 8 10 bit A D converter control register 1 ADC1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito 006 ANS3 ANS2 ANS1 ANSO ADI ADMV ADMVX AD RAN R W R W RAW R RM1 w R WX R W ROW 8 10 bit A D converter control register 2 ADC2 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito 006Du AD8 TIM1 TIMO ADCK ADIE EXT CKDIV1 CKDIVO R W R W R W R W R W R W R W R W 8 10 bit A D converter data register upper ADDH Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito 006E SAR9 SAR8 RO WX RO WX RO WX RO WX RO WX RO WX R WX R WX 8 10 bit A D converter data register lower ADDL Address bit7 bite bit5 bit4 bit3 bit2 bit1 bitO 006 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SARO R WX RWX RWX RWX RWX R W Readable writable Read value is the same as write value RMW instruction R WX R
109. 250ms 2 61 0 us 21 X 2 Fc 500ms 21 X 2 Fc 1 008 sub clock The values in parentheses represent the values achieved when the sub clock operates at 32 768kHz Note The watch prescaler cannot be used in single clock product 156 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER MB95130 MB Series 12 2 Configuration of Watch Prescaler 12 2 Configuration of Watch Prescaler The watch prescaler consists of the following blocks e Watch prescaler counter Counter clear circuit Interval timer selector e Watch Prescaler Control Register WPCR E Block Diagram of Watch Prescaler Figure 12 2 1 Block Diagram of Watch Prescaler To oscillation stabilization wait timer of sub clock Watch prescaler counter counter watchdog timer watch counter Counter clear 2 5 2 Fa to 21 2 Fc To clock control oscillation stabilization Watchdog timer clear mh wait time selector Resets stops Counter clear Interval timer Sub clock circuit selector Interrupt of watch prescaler To the selector of watch counter wmr wre Wret wrco WCLR Watch prescaler control register WPCR Fc Sub clock CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 157 CHAPTER 12 WATCH PRESCALER 12 2 Configuration of Watch Prescaler MB951 30 MB Series Watch prescaler counter counter This is a 15 bit down counter that us
110. 6 Bit Configuration of LIN UART Extended Status Control Register ESCR Address bit7 bit6 bitS bit4 bit2 biti bito Initial value R W R RMi w R W R W R W RW R W L SCES Sampling clock edge selection bit mode 2 0 Sampling with rising clock edge normal Sampling with falling clock edge inverted clock CCO Continuous clock output enable bit mode 2 0 Disable continuous clock output 1 Enable continuous clock output Serial I O pin direct access bit Write SOPE 1 Read Fix SOT pin to 0 p Read the value of SIN pin Fix SOT pin to 1 SOPE Serial output pin direct access enable bit 0 Disable serial output pin direct access 1 Enable serial output pin direct access 13 bits 14 bits 15 bits 16 bits LIN synch break detection flag bit Write Read LIN synch break detection No LIN synch break flag clear detection No effect With LIN synch break detection R W Readable writable Read value is the same as write value R RM1 W Readable writable LBIE LIN synch break detection interrupt enable bit value is different from write value 0 Disable LIN synch break detection interrupt is read by read modify write RMW instruction 1 Enable LIN synch break detection interrupt Initial value 374 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130
111. 7 431 A D converter power supply pin 431 A D converter ground pin 431 8 16 bit compound timer 00 01 clock input pin chis uii eo pee enn 202 External interrupt input pin ch O 291 INTO1 INTO2 INTO3 INTO4 INTO5 INTOG INTO7 PPGO PPGOO PPGO1 TOOO TOO1 TRGO External interrupt input pin ch 1 291 External interrupt input pin ch 2 291 External interrupt input pin ch 3 291 External interrupt input pin ch 4 291 External interrupt input pin ch 5 291 External interrupt input pin ch 6 291 External interrupt input pin ch 7 291 16 bit PPG output pin ch O 268 8 16 bit PPG timer 00 output pin ch 0 242 8 16 bit PPG timer 01 output pin ch 0 242 8 16 bit compound timer 00 output pin ch 0 DEUDA DR 202 8 16 bit compound timer 01 output pin ch 0 TEN 202 16 bit PPG trigger input pin ch 0 268 541 Interrupt Vector Index IRQO IRQO IRQ1 IRQ1 IRQ2 IRQ2 IRQ3 IRQ3 IRQ5 IRQ6 IRQ12 IRQ13 IRQ15 542 External interrupt ch O 295 External interrupt 4 295 External interrupt 1 295 External interrupt ch 5 295 External interrupt 2 295 External interrupt ch 6 295 Externa
112. 7 1 Settings of Interval Timer Function bit7 bite bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO 0 0 0 0 TOOCR1 T01CR1 STA HO IE IR BF IF SO OE 1 TMCRO IIS MOD FE11 FE10 FEO1 FEOO TOODR TO1DR Sets interval timer counter compare value O Used bit x Unused bit 1 Set 1 0 Set 0 In interval timer function one shot mode enabling timer operation TOOCRO TOOCRI STA 1 causes the counter to start counting from 00g at the rising edge of a selected count clock signal When the counter value matches the value of the 8 16 bit compound timer 00 01 data register TOODR TOIDR the timer output TMCRO TOO TOI is inverted the interrupt flag TOOCR1 TO1CRI1 IF is set to 1 and the start bit 1 STA is set to 0 and then the count operation stops The value of the 8 16 bit compound timer 00 01 data register TOODR TOIDR is transferred to the temporary storage latch comparison data storage latch in the comparator when the counter starts counting Writing 00g to the 8 16 bit compound timer 00 01 data register is prohibited Figure 15 7 2 shows the operation of the interval timer function in the 8 bit operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 219 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 7 Operating Description of Interval Timer Function One shot Mode MB951 30 MB Series Figure 15 7 2 Operation o
113. 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 5 Registers of 8 16 bit Compound Timer 15 5 1 8 16 bit Compound Timer 00 01 Control Status Register 0 TOOCRO T01CRO The 8 16 bit compound timer 00 01 control status register 0 TOOCRO TO1CRO selects the timer operation mode selects the count clock and enables or disables IF flag interrupts The TOOCRO and TO1CRO registers correspond to timers 00 and 01 respectively E 8 16 bit Compound Timer 00 01 Control Status Register 0 TOOCRO TO1CRO Figure 15 5 2 8 16 bit Compound Timer 00 01 Control Status Register 0 TOOCRO TO1CRO Address bit bit2 bit Initial value OFS2HTO1CRO IFE C2 C1 CO Fs F2 Fi Fo 00000000 QF9S3HTOOCRO RW Rw RW RW RW RW RW RW Timer operation mode select bits Interval timer one shot mode Interval timer continuous mode Interval timer free run mode PWM timer fixed cycle mode PWM timer variable cycle mode PWC timer H pulse rising to falling PWC timer L pulse falling to rising PWC timer cycle rising to rising PWC timer cycle falling to falling PWC timer H pulse rising to falling Cycle rising to rising Input capture rising free run counter Input capture falling free run counter Input capture both edges free run counter Input capture rising counter clear I
114. 8 16 bit 239 Block Diagram of Pins Related to 8 16 bit PPG eee 242 Block Diagrams of Pins Related to 16 bit 268 Channels of 16 bit PPG 267 Channels of 8 16 bit PPG 241 Interrupts of 16 bit PPG 277 Interrupts of 8 16 bit PPG 0 ee 252 Notes on Using 16 bit PPG Timer 282 Notes on Using 8 16 bit PPG 260 Operation of 16 bit PPG Mode 259 Operation of 8 bit PPG Independent Mode 254 Operation of 8 bit Prescaler 8 bit PPG 256 Overview of 8 16 bit 238 Pins of 16 bit PPG 268 Pins of 8 16 bit 242 Registers and Vector Table Related to Interrupts of 16 bit PPG 277 Registers and Vector Table Related to Interrupts of 8 16 bit PPG eese 252 Registers of 16 bit PPG 269 Registers of 8 16 bit PPG 243 Sample Programs for 16 bit PPG Timer 283 Sample Programs for 8 16 bit PPG Timer 261 Setting 16 bit PPG 258 Setting 8 bit Prescale
115. As this halts the internal clock it may result in deadlock Initializing the main clock halt detection bit The main clock halt detection bit CSVCR MM is initialized by a power on reset or external reset only The bit is not initialized by the watchdog timer reset software reset CSV reset Accordingly the device remains in CR clock mode if one of these resets occurs during CR clock mode FUJITSU MICROELECTRONICS LIMITED 463 CHAPTER 25 CLOCK SUPERVISOR 25 5 Notes on Using Clock Supervisor MB95130 MB Series 464 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY This chapter describes the functions and operations of 256 Kbit flash memory 26 1 Overview of 256 Kbit Flash Memory 26 2 Sector Configuration of Flash Memory 26 3 Register of Flash Memory 26 4 Starting the Flash Memory Automatic Algorithm 26 5 Checking the Automatic Algorithm Execution Status 26 6 Flash Memory Program Erase 26 7 Flash Security Code CM26 00115 3E Page 465 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 465 CHAPTER 26 256 Kbit FLASH MEMORY 26 1 Overview of 256 Kbit Flash Memory MB95130 MB Series 26 1 Overview of 256 Kbit Flash Memory 256 Kbit flash memory is located from 8000 to FFFF on the CPU memory map The function of the flash memory interface circuit provides read access and program access from the CPU to flash memory ll Overview of 256 Kbit Flash Memory The following methods can b
116. Asynchronous Mode Asynchronous Mode Operation 397 B Baud rate Baud Rate 389 Baud Rate Setting cee 353 LIN UART Baud Rate Selection 387 Reload Value and Baud Rate of Each Clock Speed witha tea du Guns eden rad 390 Baud Rate Generator Block Diagram of UART SIO Dedicated Baud Rate Gienerator iiec e des a aah 348 Channels of UART SIO Dedicated Baud Rate Generator niii 349 Registers Related to UART SIO Dedicated Baud Rate Generator 350 BGR Bit Configuration of LIN UART Baud Rate Generator Register 1 0 BGRI BGRO 378 Bi directional Communication Bi directional Communication Function 409 Bit Manipulation Instructions Read Destination on the Execution of Bit Manipulation Instructions 514 Bits Result Bits Result Information Bits 39 Block Diagram Block Diagram of 16 bit PPG Timer 265 Block Diagram of 8 10 bit A D Converter 429 Block Diagram of 8 16 bit Compound gb 199 Block Diagram of 8 16 bit PPG 239 Block Diagram of All MB95130 MB Series 9 Block Diagram of Clock Supervisor 455 Block Diagram of External Interrupt aee iere eee eee m 289 Block Diagram of Interrup
117. Automotive input control CMOS output Hysteresis input Pull up control available Automotive input Digital output Digital output xL N ch d3 Hysteresis input Standby 1 432 Automotive input control CMOS output Hysteresis input Automotive input CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED CHAPTER 1 DESCRIPTION 1 8 Circuit Type MB95130 MB Series 18 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 2 HANDLING DEVICES This chapter gives notes on using this series 2 1 Device Handling Precautions Code CM26 00101 3E Page 23 24 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 19 CHAPTER 2 HANDLING DEVICES 2 1 Device Handling Precautions MB95130 MB Series 2 1 Device Handling Precautions This section describes the precautions common to all devices including the device s power supply voltage and pin treatment Note that available functions differ depending on the series E Device Handling Precautions 20 Preventing Latch up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used Latch up may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to input and output pins other than medium and high withstand voltage pins or if higher than the rating voltage is applied between Vcc pin and Vss pin When latch up occurs power supply current increa
118. CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT 24 3 Pins of Low voltage Detection Reset Circuit MB951 30 MB Series 24 3 Pins of Low voltage Detection Reset Circuit This section explains the pins of the low voltage detection reset circuit E Pins Related to Low voltage Detection Reset Circuit Vcc pin The low voltage detection reset circuit monitors the voltage at this pin Q vss pin This pin is a GND pin serving as the reference for voltage detection RST pin The low voltage detection reset signal is output inside the microcontroller and to this pin However for the model equipped with the clock supervisor function see 1 2 Product Lineup of MB95130 MB Series for details the low voltage detection reset signal is generated only in the microcontroller and not output to this pin 450 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT MB95130 MB Series 24 4 Operations of Low voltage Detection Reset Circuit 24 4 Operations of Low voltage Detection Reset Circuit The low voltage detection reset circuit generates a reset signal if the power supply voltage falls below the detection voltage E Operations of Low voltage Detection Reset Circuit The low voltage detection reset circuit generates a reset signal if the power supply voltage falls below the detection voltage If the voltage is subsequently detected to have recovered the circuit outputs a reset signal for the duration of t
119. Code and Instruction Map 0 to 2 bytes are given depending on instructions SS Instruction map 1 byte instruction Instruction code Higher 4 bits Sq p 18M07 The instruction is classified into following four types forwarding system operation system branch system and others There are various methods of addressing and ten kinds of addressing can be selected by the selection and the operand specification of the instruction This provides with the bit operation instruction and can operate the read modification write There is an instruction that directs special operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 503 APPENDIX APPENDIX E Instruction Overview MB951 30 MB Series E Explanation of Display Sign of Instruction Table E 1 shows the explanation of the sign used by explaining the instruction code of this APPENDIX E Table E 1 Explanation of Sign in Instruction Table Signification i Direct address 8 bit length Offset 8 bit length Extended address 16 bit length Vector table number 3 bit length Immediate data 8 bit length Immediate data 16 bit length Bit direct address 8 bit length 3 bit length Branch relative address 8 bit length Register indirect Example 9 A 9 TX 9 EP Accumulator Whether 8 bit length or 16 bit length is decided by the instruction used Upper 8 bit of accumulator 8 bit
120. FO timer output initial value bit TOOCR1 TO1CRI SO 16 bit mode enable bit TMCRO MOD and filter function select bits TMCRO FE11 FE10 FEO1 FE00 HO Timer suspend bit This bit suspends or resumes timer operation Writing 1 to this bit during timer operation suspends the timer operation e Writing 0 to the bit when timer operation has been enabled TOOCR1 TOICRI STA 1 resumes the timer operation When the PWM timer function variable cycle mode has been selected TOOCRO TO1CRO F2 F1 FO 0100 the HO bit can be used to suspend or resume timer operation from within either the TOOCR1 timer 00 or TOICRI timer 01 register In this case the HO bit in the other register is set to the same value automatically During 16 bit operation TMCRO MOD 1 use the HO bit in the TOOCRI timer 00 register to suspend or resume timer operation In this case the STA bit in the other register is set to the same value automatically IE Interrupt request enable bit This bit enables or disables the output of interrupt requests Writing 0 disables interrupt request Writing 1 outputs an interrupt request when the pulse width measurement completion edge detection flag TOOCRI TOICRI IR or timer reload overflow flag TOOCR1 TOICR LIF is 1 Note however that an interrupt request from the timer reload overflow flag TOOCR1 TO1CR1 IF is not outputted unless the IF flag interrupt enable TOOCRO TO1CRO
121. FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series 15 6 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 6 Interrupts of 8 16 bit Compound Timer Interrupts of 8 16 bit Compound Timer The 8 16 bit compound timer generates the following types of interrupts to each of which an interrupt number and interrupt vector are assigned Timer 00 interrupt Timer 01 interrupt E Timer 00 Interrupt Table 15 6 1 explains the timer 00 interrupt and its source Table 15 6 1 Timer 00 Interrupt Item Description Interrupt generating condition Comparison match in interval timer function or PWM timer function variable cycle mode has been selected Overflow in PWC timer function or input capture function Completion of measurement in PWC timer function or edge detection in input capture function Interrupt flag TOOCR1 IF TOOCR1 IF TOOCR1 IR Interrupt enable E Timer 01 Interrupt TOOCR1 IE and TOOCRO IFE TOOCRI IE and TOOCRO IFE Table 15 6 2 explains the timer 01 interrupt and its cause Table 15 6 2 Timer 01 Interrupt Item Description Interrupt generating condition Comparison match in interval timer function or PWM timer function variable cycle mode has been selected Excluded during 16 bit operation Overflow in PWC timer function or input capture function Excluded during 16 bit operation TOOCR1 IE Completion of measurement in PWC timer function or edge
122. HO 1 request is issued during operation E When Interval Timer Input Capture or PWC Function Has Been Selected Figure 15 15 1 shows how the counter value changes when transition to watch mode or stop mode or a suspend request occurs during operation of the 8 16 bit compound timer The counter stops operation while holding the value when transition to stop mode or watch mode occurs When the stop mode or watch mode is canceled by an interrupt the counter resumes operation with the last value held So the first interval time and external clock count are incorrect After releasing from stop mode or watch mode be sure to initialize the counter value Figure 15 15 1 Operations of Counter in Standby Mode or in Pause Not Serving as PWM Timer TOODR TO1DR data register value FFH Counter value FFH A HIE GP LIE mcd ap CE MID 80H 00H 1 ot 1 HO rehuest Request ends 1 1 1 Dn 1 HO request ends 1 1 1 1 1 1 1 1 1Delay of oscillation stabilizationiwait time 1 1 1 1 1 Interval time after wake up 1 from stop mode indeterminate 1 11 IF bit 1 T 1 Cleared by progrant 4 Operatio halts 1 1 1 1 1 1 1 STA bit ju history 1 1 1 1 1 1 t 1 1 1 Operation reactivated HO bit 1 1 1 1 1 i 1 i 1 1 1 Sleep mode IE bit i 1 2 SLP bit
123. IFE bit is also set to 1 IR Pulse width measurement completion edge detection flag CM26 10118 3E This bit shows the completion of pulse width measurement or the detection of an edge The bit is set to 1 upon completion of pulse width measurement when the PWC timer function has been selected The bit is set to 1 upon detection of an edge when the input capture function has been selected The bit is 0 when any timer function other than the PWC timer and input capture functions has been selected This bit always returns 1 to a read modify write RMW instruction The IR bit in TOICRI timer 01 register is set to 0 during 16 bit operation Writing 0 to the bit sets it to O An attempt to write 1 to the bit is ignored FUJITSU MICROELECTRONICS LIMITED 209 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer MB951 30 MB Series Table 15 5 2 Functional Description of Each Bit of 8 16 bit Compound Timer 00 01 Control Status Register 1 2 2 Bit name Function This bit is set to 1 when a count value is stored in the 8 16 bit compound timer 00 01 data register TOODR TO1DR upon completion of pulse width measurement in PWC timer function This bit is set to 0 when the 8 16 bit compound timer 00 01 data register TOODR TOIDR is read during 8 bit operation The 8 16 bit compound timer 00 01 data register TOODR TOIDR holds data with this bit containing 1
124. LIMITED 57 CHAPTER 6 CLOCK CONTROLLER 6 4 PLL Control Register PLLC MB95130 MB Series Table 6 4 1 Functions of Bits in PLL Control Register PLLC 2 2 Bit name Function Set the multiplier for the Sub PLL clock SPMC1 SPMCO Sub PLL Clock Multiplier Setting Bits 0 0 Setting prohibited Be sure to write any other value before using the PLL 0 1 Sub clock x 2 1 0 Sub clock x 3 1 1 Sub clock x 4 SPMCI SPMCO Sub PLL clock On single clock product the value of the bit has no effect on the operation multiplier setting bits Notes Dual clock product only Although the initial value of these bits is 00g the PLL does not operate normally with this setting Be sure to set the bits to any value other than 00 either before setting the sub PLL clock oscillation enable bit SPEN to 1 or before setting the clock mode selection bits in the system clock control register SYCC SCS1 SCSO to 01g These bits can be updated only when the sub PLL clock is stopped Consequently you should not update the bits either with the sub PLL clock oscillation enable bit SPEN set to or with the system clock select bits in the system clock control register SYCC SCS1 SCSO set to 01g It is however possible to set these bits at the same time as setting SPEN to 1 Indicates whether sub PLL clock oscillation has become stable SPRDY When set to 1 the SPRDY bit indicates that the oscillation stabilization wait time f
125. LIMITED CM26 10118 3E MB95130 MB Series CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART Figure 22 7 15 Master Slave Mode Communication Flowchart Master CPU Set to operation mode 1 Set SIN pin for serial data input Set SOT pin for serial data output Set 7 or 8 data bits Set 1 or 2 stop bits Set 1 to AD bit Enable transmission reception Transmit address to slave Set 0 to AD bit Communicate with slave CPU Terminate communication Disable transmission reception Slave CPU Set to operation mode 1 Set SIN pin for serial data input Set SOT pin for serial data output Set 7 or 8 data bits Set 1 or 2 stop bits Enable transmission reception Receive bytes Slave address matched YES Communicate with master Terminate communication CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 413 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series 22 7 7 LIN Communication Function For LIN UART communication a LIN device can be used in the LIN master system or the LIN slave system B LIN Master Slave Mode Communication Function Figure 22 7 16 shows the required settings for the LIN communication mode of LIN UART operation mode 3
126. MB Series 7 2 Reset Source Register RSRR Table 7 2 1 Functions of Bits in Reset Source Register RSRR Bit name Function Undefined bits The read value is always 0 These bits are read only Writing has no effect on operation CSVR Clock supervisor reset flag bit This bit is set to 1 to indicate that a clock supervisor reset has occurred Otherwise the bit retains the value existing before the clock supervisor reset occurred Read or write access 0 or 1 to this bit sets it to 0 The bit value is always 0 in product types that do not have the clock supervisor function Writing has no effect on the operation EXTS External reset flag bit This bit is set to 1 to indicate that an external reset has occurred Otherwise the bit retains the value existing before the reset occurred Read or write access 0 or 1 to this bit sets it to 0 WDTR watchdog reset flag bit This bit is set to 1 to indicate that an watchdog reset has occurred Otherwise the bit retains the value existing before the reset occurred e Read or write access or 1 to this bit sets it to 0 PONR Power on reset flag bit This bit is set to 1 to indicate that a power on reset or low voltage detection reset option has occurred Otherwise the bit retains the value existing before the reset occurred The low voltage detection reset function is provided for specific models Read or write access 0 or 1
127. Once flash memory has been protected the function cannot be unlocked until the chip erase command is executed Note that only addresses 55544 and 2AAA can be read as exceptions It is advisable to code the protection code at the end of flash programming This is to avoid unnecessary protection during programming Once flash memory has been protected the chip erase operation is required before it can be reprogrammed CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 481 CHAPTER 26 256 Kbit FLASH MEMORY 26 7 Flash Security MB95130 MB Series 482 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION This chapter describes the example of a serial programming connection 27 1 Basic Configuration of Serial Programming Connection for Flash Memory Products 27 2 Example of Serial Programming Connection 27 3 Example of Minimum Connection to Flash Microcontroller Programmer Code CM26 00124 1E Page 484 485 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 483 CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 27 1 Basic Configuration of Serial Programming Connection for MB95130 MB Series Flash Memory Products 27 1 Basic Configuration of Serial Programming Connection for Flash Memory Products The MB95F133MBS NBS JBS MBW NBW JBW MB95F134MBS NBS JBS MBW NBW JBW MB95F136MBS NBS JBS MBW NBW JBW supports flash ROM serial onboard programming Fujitsu standar
128. Operations of Port 123 Port F Configuration eseeeeeeeeeeeee 120 Port E PIs cise e ete Tenet Line ern 120 Port F Register Function esesesesssss 122 Port G Block Diagram of Port 126 Operations of Port 128 Port G Configuration 125 Port Gi PINS 125 Port G Register Function 0000 cee 127 PPG 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO 271 16 bit PPG Down Counter Registers Upper Lower PDCRLO 270 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 272 16 bit PPG Status Control Register Lower PCN FEO srine nt rei unire 275 16 bit PPG Status Control Register Upper PCNTEO 273 16 bit PPG Timer eee 264 8 16 bit PPG Output Inversion Register iiid iei e dre tinere 251 8 16 bit PPG Start Register PPGS 250 8 16 bit PPG Timer 00 Control Register ch 0 eren 246 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register 01 00 248 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register 801 900 249 8 16 bit Timer 01 Control Register 0 244 Block Diagram of 16 bit PPG 265 Block Diagram of
129. P12 PDRI DDRI bit6 bit5 bit4 bit3 bit2 bitl bitO PULI ILSR bitO ILSR2 bitl Only for 5V products it is an effective register CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 117 CHAPTER 9 I O PORT RE MB95130 MB Series 9 3 2 Operations of Port 1 This section describes the operations of port 1 il Operations of Port 1 Operation as an output port Setting the corresponding DDR register bit to 1 sets a pin as an output port Fora peripheral function sharing pins disable its output e When a pin is set as an output port it outputs the value of the PDR register to pins fdatais written to the PDR register the value is stored in the output latch and output to the pin as it is Reading the PDR register returns the PDR register value Operation as an input port Setting the corresponding DDR register bit to 0 sets a pin as an input port Fora peripheral function sharing pins disable its output e If data is written to the PDR register the value is stored in the output latch but not output to the pin Reading the PDR register returns the pin value However the read modify write command returns the PDR register value Operation as a peripheral function output Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register eve
130. PPG timer 01 control register ch 0 PCO1 sets the operating conditions for PPG timer 01 E 8 16 bit PPG Timer 01 Control Register ch 0 PC01 Figure 16 5 2 8 16 bit PPG Timer 01 Control Register ch 0 PCO1 bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value Address 003AH PCO1 1 PUF1 POEN1 CKS12 CKS11 CKS10 000000008 Ro WX RO WX R W R RM1 W RW R W RW RW CKS12 CKS11 CKS10 Operating clock select bits 0 0 0 1 MCLK POEN1 Output enable bit 0 Output disabled general purpose port 1 Output enabled Counter borrow detection flag bit for PPG cycle down counter Read Write Counter borrow undetected Flag cleared Counter borrow detected No effect on operation PIE1 Interrupt request enable bit 0 Interrupt disabled 1 Interrupt enabled MCLK Machine clock frequency FCH Main clock oscillation frequency R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction RO WX Undefined bit Read value is 0 writing has no effect on operation Initial value 244 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series CHAPTER 16 8 16 BIT PPG 16 5 Registers of 8 16 bit PPG Table 16 5 1 8 16 bit PPG Timer 01 Control Register PCO1 Bit name Function Undefined bits These
131. PPGO A PPG waveform is outputted to these pins The PPG waveform can be outputted by using the 16 bit PPG status control register to enable output PCNTLO POEN 1 TRGO pin TRGO Used to start 16 bit PPG timer by hardware trigger E Block Diagrams of Pins Related to 16 bit PPG Figure 17 4 1 Block Diagram of Pin Related to 16 bit PPG PPGO TRGO Hysteresis pc me 078 OnyPi0is 0 1 Peripheral function input selectable Peripheral function input enable pesce 1 KC EH Peripheral function output enable Automotive Peripheral function output 1 5 Wow DER E d ee eee Pull up lt 1 1 PDR read Y 1 1 ____ cmos HE Peh 1 Pin PDR 0 LT PDR write n bit operation instruction i Only P10 P12 DDR read and P13 are selectable DDR ODRwrite Stop Watch SPL 1 PUL read PUL 4 PUL write i f I i 1 ILSR read 1 1 1 ILSR i 1 1 5 _ ______________ 1 Only P10 is selectable ILSR2 read ILSR2 ILSR2 write 268 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB951 30 MB Series 17 5 Registers of 16 bit PPG Timer 17 5 Registers of 16 bit PPG Timer This section d
132. Pointer addressing General purpose register addressing Immediate addressing Vector addressing Relative addressing Inherent addressing E Explanation of Addressing Direct addressing This is used when accessing the direct area of 00004 to 047Fy with addressing indicated dir in instruction table In this addressing when the operand address is 00g to 7Fy it is accessed into 00004 to 007Fg Moreover when the operand address is 80g to FFy the access can be mapped in 0080p to 047Fg by setting of direct bank pointer DP Figure E 1 1 shows an example Figure E 1 1 Example of Direct Addressing MOV 92H A DP 0018 0112u 4 5H k A 454 Extended addressing This is used when the area of the entire 64 K bytes is accessed by addressing shown ext in the instruction table In this addressing the first operand specifies one high rank byte of the address and the second operand specifies one subordinate position byte of the address Figure E 1 2 shows an example Figure E 1 2 Example of Extended Addressing MOVW A 1234H gt 123 4H 1235H 5 6H 7 8H 567 8H 506 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX E Instruction Overview Q Bit direct addressing This is used when accessing the direct area of 00004 to 047 in bit unit wi
133. Programmer 27 3 Example of Minimum Connection to Flash Microcontroller Programmer The connection between MOD and the flash microcontroller programmer is not required if the pins are set as shown in Figure 27 3 1 during serial writing serial write mode MODz H P12 H P13z L E Example of Minimum Connection to Flash Microcontroller Programmer Figure 27 3 1 shows an example of the minimum connection between the flash memory products and flash microcontroller programmer The TTXD pin on the flash microcontroller programmer is connected to P10 UIO and outputs low until data transfer starts Setting P10 UI0 Low in this way specifies that serial write mode uses clock synchronous communications Note that a user power supply is required for serial writing 490 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION MB95130 MB Series 27 3 Example of Minimum Connection to Flash Microcontroller Programmer Figure 27 3 1 Example of Minimum Connection between Flash Memory Products and Flash Microcontroller Programmer AF220 AF210 AF120 AF110 flash microcontroller programmer User system Flash memory products P13 fena At serial 4 7kQ reprogramming H MOD M Lo xi AT i Connector i DX10 28S i TRES 6 Arka RST TTXD i 13 P10 UIO TRXD 27 P11 UOO TCK 6 P12 UCKO TVcc
134. Q Time base timer counter 22 bit down counter that uses the main clock divided by two as the count clock Counter clear circuit This circuit controls clearing of the time base counter Interval timer selector This circuit selects the one bit from four bits in the 22 bits that make up the time base timer counter to use the interval timer Q Time base timer control register TBTC This register selects the interval time clears the counter controls interrupts and checks the status B Input Clock The time base timer uses the main clock divided by two as its input clock count clock Bi Output Clock The time base timer supplies clocks to the main clock oscillation stabilization wait time timer the watchdog timer and the prescaler 134 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 10 TIME BASE TIMER MB95130 MB Series 10 3 Registers of the Time base Timer 10 3 Registers of the Time base Timer Figure 10 3 1 shows the register of the Time base Timer E Registers of the Time base Timer Figure 10 3 1 Register of the Time base Timer Time base timer control register TBTC R W Readable writable Read value is the same as write value RMW instruction Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito 000A TBIF TBIE TBC1 TBCO TCLR R RM1 W R W RO WX RO WX RO WX R W R W RO W Initial value 000000005 R RM1 W Readable writable Read value
135. REVOI is 0 bit2 to bitO CKS12 CKS11 CKS 10 Operating clock select bits CM26 10118 3E These bits select the operating clock for 8 bit down counter of the PPG timer 01 The operating clock is generated from the prescaler Refer to CHAPTER 6 CLOCK CONTROLLER In 16 bit PPG operation mode the setting of this bit has no effect on the operation 0005 I MCLK 001g 2 MCLK 010g 4 MCLK 011g 8 MCLK 100g 16 MCLK 101g 32 MCLK 1106 27 F 111g 2 Foy Note Use of a sub clock in dual clock product stops the time base timer operation Therefore selecting 110g or 111g is prohibited FUJITSU MICROELECTRONICS LIMITED 245 CHAPTER 16 8 16 BIT PPG 16 5 Registers of 8 16 bit PPG MB951 30 MB Series 16 5 2 8 16 bit PPG Timer 00 Control Register ch 0 PCOO The 8 16 bit PPG timer 00 control register ch 0 PCOO sets the operating conditions and the operation mode for PPG timer 00 E 8 16 bit PPG Timer 00 Control Register ch 0 PCOO Figure 16 5 3 8 16 bit PPG Timer 00 Control Register ch 0 PCOO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value Address 003BH MD1 MDO PIEO PUFO 02 CKS01 CKS00 000000008 RAN RA R W R RM1 W RW RW RW RW CKS02 CKS01 CKS00 Operating clock select bits 0 1 MCLK 2 MCLK 4 MCLK 8 MCLK 16 MCLK 32 MCLK 2 FcH 28 POENO Output enable bit 0 Output disabled gene
136. Series E Features of General purpose Registers There are the following features in the general purpose registers High speed access to RAM using short instructions general purpose register addressing Blocks of register banks facilitating data backup and division by function unit General purpose register banks can be allocated exclusively for specific interrupt service routines or vector call CALLV 0 to 7 processing routines An example is always using the fourth register bank for the second interrupt Only specifying a dedicated register bank at the beginning of an interrupt service routine automatically saves the general purpose registers before the interrupt This eliminates the need for pushing general purpose register data onto the stack allowing the CPU to accept interrupts at high speed Notes When coding an interrupt service routine be careful not to change the value of the interrupt level bits CCR IL1 ILO in the condition code register when specifying the register bank by updating the register bank pointer RP in that routine Perform the programming by using either of them Read the interrupt level bits and save their value before writing to the RP Directly write to the RP mirror address 00784 to update the RP 42 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 5 CPU MB95130 MB Series 5 3 Placement of 16 bit Data in Memory 5 3 Placement of 16 bit Data in Memory This section de
137. TDRE bit are 1 FUJITSU MICROELECTRONICS LIMITED 371 CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series 22 4 4 LIN UART Reception Data Register LIN UART Transmit Data Register RDR TDR The LIN UART reception and LIN UART transmit data registers are located at the same address If read they work as the reception data register if written they work as the transmit data register il LIN UART Reception Data Register RDR TDR Figure 22 4 5 shows the LIN UART reception data register LIN UART transmit data register Figure 22 4 5 LIN UART Reception Data Register LIN UART Transmit Data Register RDR TDR Address bt 7 6 5 4 3 2 1 0 Initial value R W R W R W R W R W R W R W R W R W Data register Read Read from the LIN UART reception data register Write Write to the LIN UART transmit data register R W Readable writable Read value is the same as write value E LIN UART Reception Data Register RDR The LIN UART reception data register RDR is the data buffer register for the serial data reception Serial data signal transmitted to the serial input pin SIN pin is converted via a shift register and stored in the LIN UART reception data register RDR If the data length is 7 bits the upper 1 bit RDR D7 is 0 The reception data full flag bit SSR RDRF is set to 1 when received data is stored into the LIN UART reception dat
138. TO1CR1 controls the interrupt flag timer output and timer operations TOOCR1 and TO1CR1 registers correspond to timers 00 and 01 respectively E 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCR1 TO1CR1 Figure 15 5 3 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCR1 TO1CR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value Address 0036H TOTCR1 STA HO IE IR BF IF SO OE 0037H TOOCR1 RW R W R RM1 W R WX R RM1 W R W 000000005 R W gt Timer output disabled Timer output enabled SO Timer output initial value bit 0 Timer initial value 0 OE Timer output enable bit 0 1 Timer initial value 1 Timer reload overflow flag Read Write No reload or overflow Flag clear 1 Reload and overflow BF Data register full flag 0 Measurement data absent in data register 1 Measurement data present in data register Pulse width measurement complete and edge detection flag Read Write No effect on operation 0 Measurement complete edge undetected Flag clear Measurement complete edge detected No effect on operation 1 IE Interrupt request bit 0 Interrupt disabled 1 Interrupt enabled HO Timer pause bit 1 0 imer operable imer paused STA Timer operation enable bit R W R WX R RM1 W Readable writable Read value is different from wri 0 Timer stopped
139. Table Related to Interrupts of Watch Counter eeeeeeeeeeee 177 Register and Vector Table Related to Interrupts of Watch Prescaler suse 163 Register and Vector Table Related to LIN UART Interrupt eere tene 382 Registers and Vector Table Related to Interrupts of 16 bit PPG Timer 277 Registers and Vector Table Related to Interrupts of 8 16 bit eese 252 Registers and Vector Table Related to Interrupts of External Interrupt Circuit 295 Registers and Vector Table Related to UART SIO Int rr pts ettet teme 327 Registers and Vector Tables Related to Interrupts of 8 16 bit Compound Timer 218 Vector table area Addresses FFCOg to FFFFyy 28 Watch counter Block Diagram of Watch Counter 171 Interrupts of Watch Counter 177 Register and Vector Table Related to Interrupts of Watch Counter eese 177 Registers of Watch Counter sus 173 Sample Programs for Watch Counter 181 Setup Procedure of Watch Counter 178 Watch courier etre 170 Watch counter control register Watch Counter Control Register WCSR 175 Watch Interrupts Interrupt when Interval Timer Function is in Operation Watch 162 Watch mo
140. Watch prescaler control register R W 00000000 000Cy WDTC Watchdog timer control register R W 00000000 0000 to Prohibited 00274 00284 PDRF Port F data register R W 000000005 00294 DDRF Port F direction register R W 00000000 002A 1 PDRG Port G data register R W 00000000g 002Bg DDRG Port G direction register R W 00000000 002Cy PULO Port 0 pull up register R W 00000000g 002Dg PULI Port 1 pull up register R W 00000000g 002 to Prohibited 00344 00354 PULG Port G pull up register R W 000000005 00364 TOICRI 8 16 bit compound timer 01 control status register 1 ch 0 R W 00000000 00374 TOOCR1 8 16 bit compound timer 00 control status register 1 ch 0 R W 000000008 00384 0039 Prohibited 003Ayq 1 8 16 bit PPGI control register ch 0 R W 000000005 003By PCOO 8 16 bit PPGO control register ch 0 R W 00000000 494 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series Table A 1 MB95130 MB Series 2 4 Address Register abbreviation Prohibited APPENDIX APPENDIX A I O Map value PCNTHO 16 bit PPG status control register upper ch 0 PCNTLO 16 bit PPG status control register lower ch 0 Prohibited External interrupt circuit control register ch 0 ch 1 External interrupt circuit control register ch 2 ch 3 External interrupt circuit control register ch 4 ch 5 External interrupt circuit control register ch 6 ch 7 Prohibited
141. a reception interrupt request when both PE bit and RIE bit are 1 When this flag is set the data in the reception data register RDR is invalid ORE Overrun error flag bit Detect an overrun error in received data This bit is set to 1 when an overrun occurs during reception and cleared by writing to the CRE bit in the LIN UART serial control register SCR Output a reception interrupt request when both ORE bit and RIE bit are 1 When this flag is set the data in the reception data register RDR is invalid FRE Framing error flag bit Detect a framing error in received data This bit is set to 1 when a framing error occurs during reception and cleared by writing 1 to the CRE bit in the LIN UART serial control register SCR Output a reception interrupt request when both FRE bit and RIE bit are 1 When this flag is set the data in the reception data register RDR is invalid RDRF Reception data full flag bit This flag shows the status of the reception data register RDR This bit is set to 1 when received data is loaded into the reception data register RDR and cleared to 0 by reading RDR Output a reception interrupt request when both RDRF bit and RIE bit are 1 TDRE Transmit data empty flag bit This flag shows the status of the transmit data register TDR This bit is set to 0 by writing the transmit data to TDR and indicates that the TDR has valid
142. available only to MASK ROM product Hysteresis input only for MASK ROM product Mo Reset input Reset output Reset output N ch 777 CMOS output Hysteresis input Pull up control Analog input Pull up control available P ch t UAE Digital output e Automotive input Digital output 5 N ch me t P Analog input E Automotive input A D control Standby control 4 External interrupt control Hysteresis input 16 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series Table 1 8 1 I O Circuit Type 2 2 Circuit E Pull up control hc Digital output Digital output N ch Analog input CMOS input Hysteresis input A D control Automotive input Standby control TD External interrupt control CHAPTER 1 DESCRIPTION 1 8 I O Circuit Type Remarks CMOS output CMOS input Hysteresis input Analog input Pull up control available Automotive input Pull up control Digital output Digital output CMOS input Hysteresis input Standby Automotive input control CMOS output CMOS input Hysteresis input Pull up control available Automotive input Pull up control Digital output Digital output ale N ch d 2 Hysteresis input Standby 7 jx
143. baud rate for the UART SIO The generator consists of the UART SIO dedicated baud rate generator prescaler selection register PSSRO and UART SIO dedicated baud rate generator baud rate setting register BRSRO E Block Diagram of UART SIO Dedicated Baud Rate Generator Figure 21 1 1 Block Diagram of UART SIO Dedicated Baud Rate Generator Baud rate generator UART SIO PSS1 PSS0 BRS7 to BRSO MCLK Machine clock 8 bit BRCLK down counter Prescaler B Input Clock The UART SIO dedicated baud rate generator uses the output clock from the prescaler or the machine clock as its input clock Bi Output Clock The UART SIO dedicated baud rate generator supplies its clock to the UART SIO 348 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR MB951 30 MB Series 21 2 Channels of UART SIO Dedicated Baud Rate Generator 21 2 Channels of UART SIO Dedicated Baud Rate Generator This section describes the channels of the UART SIO dedicated baud rate generator Channels of UART SIO Dedicated Baud Rate Generator This series contains one channel of the UART SIO dedicated baud rate generator Table 21 2 1 shows the registers of the UART SIO dedicated baud rate generator Table 21 2 1 Registers of UART SIO Dedicated Baud Rate Generator Channel Register name Corresponding register Representation in this manual UART SIO dedicated baud rate generator pres
144. be written to the UART SIO serial output data register TDRO by interrupt handling To detect the completion of serial transmission by transmission interrupt set the transmission completion interrupt enable bits as follows TEIE 0 TCIE 1 Upon completion of transmission the transmission completion flag TCPL is set to 1 and a transmission interrupt Occurs Both the transmission completion flag TCPL and the transmission data register empty flag TDRE when transmitting data consecutively are set at the position which the transmission of the last bit was completed it varies depending on the data length parity enable or stop bit length setting as shown in Figure 20 7 6 below Note that modifying UART SIO serial mode control register 1 SMC10 during transmission may result in unpredictable operation Figure 20 7 6 Transmission in Asynchronous Clock Mode UART Uoo TCPL TDRE X D5 X D6 X D7 X P X SP SP Transmission interrupt 334 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 7 Explanation of UART SIO Operations and Setup Procedure Example The TDRE flag is set at the point indicated in the following figure if the preceding piece of transmit data does not exist in the transmission shift register Figure 20 7 7 Setting Timing 1 for Transmit Data Register Empty Flag TDRE When TXE is 4 TXE Writing of transmit data
145. bit TCIE TEIE To disable interrupt requests Set to 0 To enable interrupt requests Set to 1 The following setting is used to clear interrupt requests px UART reception UART transmission Read from serial input register RDR 0 to The transmit data register empty TDRE is set to 0 To clear reception data register full bit RDRF clear interrupt requests Write 0 to error flag clear bit RERC to bY Writing data to the serial clear error flags PER OVE FER to 0 output data register TDRO CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 345 CHAPTER 20 UART SIO 20 8 Sample Programs for UART SIO MB951 30 MB Series 346 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOH This chapter describes the functions and operations of the dedicated baud rate generator of UART SIO 21 1 Overview of UART SIO Dedicated Baud Rate Generator 21 2 Channels of UART SIO Dedicated Baud Rate Generator 21 3 Registers of UART SIO Dedicated Baud Rate Generator 21 4 Operating Description of UART SIO Dedicated Baud Rate Generator Code CM26 00121 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 347 CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR 21 1 Overview of UART SIO Dedicated Baud Rate Generator MB951 30 MB Series 21 1 Overview of UART SIO Dedicated Baud Rate Generator The UART SIO dedicated baud rate generator generates the
146. bit A D converter uses the output clock from the prescaler as the input clock operation clock 430 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 3 Pins of 8 10 bit A D Converter 23 3 Pins of 8 10 bit A D Converter This section describes the pins of the 8 10 bit A D converter E Pins of 8 10 bit A D Converter MB95130 MB series has 8 channels of analog input pin Analog input pins also serve as general purpose I O ports ANO07 to ANOO Pins to ANOO ADTG Pin ADTG AVcc pin AVcc e AVss pin AV gs CM26 10118 3E When using the A D conversion function input the analog voltage you wish to convert to one of these pins Each of the pins serves as an analog input pin by selecting it using the analog input channel select bits ADC1 ANSO to ANS3 with the corresponding bit in the port direction register DDR set to 0 Even when the 8 10 bit A D converter is used the pins not used for analog input can be used as general purpose I O ports Note that the number of analog input pins differs depending on the series This is a pin used to activate A D conversion function by external trigger This is a 8 10 bit A D converter power supply pin Use this at the same potential as Vcc If A D conversion precision is demanded you should take measures to ensure that Vcc noise does not enter AVcc or use a separate power source You should connect this
147. bit PPG Timer Shown below are the precautions that must be followed when using the 16 bit PPG timer E Notes on Using 16 bit PPG Timer 282 Precautions when setting the program Do not use the retrigger if the same values are set for the cycle and duty If used the PPG output will go to the L level for one count clock cycle after the retrigger and then go back to the H level when normal polarity has been selected If the microcontroller enters a standby mode the TRGO pin setting may change and cause the device to malfunction Therefore disable the timer enable bit PCNTHO CNTE 0 or disable the hardware trigger enable bit PCNTLO EGS1 EGSO 005 When the cycle and duty are set to the same value an interrupt is generated only once by duty match Moreover if the duty is set to a value greater than the value of the period no interrupt will be generated by duty match Do not disable the timer enable bit PCNTHO CNTE 0 and software trigger PCNTHO STRG 1 at the same time when retrigger by the software is enabled PCNTHO RTRG 1 and the retrigger is selected as an interrupt type PCNTLO IRS1 IRSO 005 during count operation If it occurs interrupt flag bit may set by retrigger although timer stops FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 9 Sample Programs for 16 bit PPG Timer 17 9 Sample Programs for 16 bit PPG Timer We provide sample
148. bit PPG Timer 17 6 Interrupts of 16 bit PPG Timer The 16 bit PPG timer can generate interrupt requests in the following cases When a trigger or counter borrow occurs When a rising edge of PPG is generated in normal polarity When a falling edge of PPG is generated in inverted polarity The interrupt operation is controlled by IRS1 bit 3 and IRSO bit2 in the PCNTL register B Interrupts of 16 bit PPG Timer Table 17 6 1 shows interrupt control bits and interrupt sources of the 16 bit PPG timer Table 17 6 1 Interrupt Control Bits and Interrupt Sources of 16 bit PPG Timer Item Description Interrupt flag bit PCNTLO IRQF Interrupt request enable bit PCNTLO IREN Interrupt type select bits PCNTLO IRS1 IRSO PCNTLO IRS1 IRSO 00 Hardware trigger by TRGO Pin input of 16 bit down counter software trigger and retrigger PCNTLO IRS1 IRSO 01 Counter borrow of 16 bit down counter Interrupt sources PCNTLO IRS1 IRS0 10p Rising edge of PPGO output in normal polarity or falling edge of PPGO output in inverted polarity PCNTLO IRS1 IRSO 11 Counter borrow of 16 bit down counter rising edge of PPGO output in normal polarity or falling edge of PPGO output in inverted polarity When IRQF bit 4 in the 16 bit PPG status control register PCNTLO is set to 1 and interrupt requests are enabled PCNTLO IREN bit 5 1 in the 16 bit PPG timer an interrupt request is generated and outputt
149. bit of the watch counter is disabled WCSR ISEL 0 an interrupt request IRQ20 occurs from watch prescaler to an interrupt controller Regardless of the value in the WTIE bit the WTIF bit is set to 1 when the time set by the watch interrupt interval time select bits has been reached When the WTIF bit is set to 1 changing the WTIE bit from the disable state to the enable state WPCR WTIE 0 1 immediately generates an interrupt request The WTIF bit cannot be set when the counter is cleared WPCR WCLR 1 at the same time as the selected bit overflows Write 0 to the WTIF bit in the interrupt processing routine to clear an interrupt request to 0 Note When enabling the output of interrupt requests WPCR WTIE 1 after canceling a reset always clear the WTIF bit at the same time WPCR WTIF 0 Interrupts of Watch Prescaler Table 12 4 1 Interrupts of Watch Prescaler Description Interrupt condition Interval time set by WPCR WTCI and WTCO has elapsed Interrupt flag WPCR WTIF Interrupt enable WPCR WTIE 162 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER MB95130 MB Series 12 4 Interrupts of Watch Prescaler E Register and Vector Table Related to Interrupts of Watch Prescaler Table 12 4 2 Register and Vector Table Related to Interrupts of Watch Prescaler Interrupt Interrupt level setting request register number Registers Setting bit Interrupt Vect
150. bits Negative flag Zero flag Overflow flag Carry flag The condition code register is a part of the program status PS register and therefore cannot be accessed independently B Bits Result Information Bits Half carry flag This flag is set to 1 when a carry from bit3 to bit4 or a borrow from bit4 to bit3 occurs as the result of an operation Otherwise the flag is set to 0 Do not use this flag for any operation other than addition and subtraction as the flag is intended for decimal adjusted instructions Negative flag N This flag is set to 1 when the value of the most significant bit is 1 as the result of an operation and set to 0 if the value is 0 Zero flag Z This flag is set to 1 when the result of an operation is 0 and set to 0 otherwise Overflow flag V This flag indicates whether an operation has resulted in an overflow assuming the operand used for the operation as an integer represented by a two s complement The flag is set to 1 when an overflow occurs and set to 0 otherwise CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 39 CHAPTER 5 CPU 5 1 Dedicated Registers MB95130 MB Series Carry flag C This flag is set to 1 when a carry from bit7 or a borrow to bit7 occurs as the result of an operation Otherwise the flag is set to 0 When a shift instruction is executed the flag is set to the shift out value Figure 5
151. bits are compared with the interrupt level bits in the condition code register CCR IL 1 ILO When interrupt level 3 is set for an interrupt request the CPU ignores the interrupt request Table 8 1 2 shows the relationships between interrupt level setting bits and interrupt levels Table 8 1 2 Relationships Between Interrupt Level Setting Bits and Interrupt Levels LXX 1 0 Interrupt Level Priority Low No interrupt XX 00 to 23 Corresponding interrupt number During execution of a main program the interrupt level bits in the condition code register CCR IL1 ILO are usually 115 98 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 8 INTERRUPTS MB95130 MB Series 8 1 Interrupts 8 1 2 Interrupt Processing Steps When an interrupt request is generated by a peripheral resource the interrupt controller passes the interrupt level to the CPU When the CPU is ready to accept interrupts it temporarily halts the program currently being executed and executes an interrupt service routine E Interrupt Processing The procedure of processing an interrupt takes the following steps the generation of an interrupt resource in a peripheral resource the execution of the main program the setting of the interrupt request flag bit the evaluation of the interrupt request enable bit the evaluation of interrupt level ILRO to ILR5 and 1 ILO the checking for any equal level interrupt request and the ev
152. ch 0 operation is enabled in the external interrupt circuit ECO ECO interrupt pin select bits This bit is used to determine whether to select the ECO pin as an interrupt input pin Setting the bit to 0 Deselects the ECO pin as an interrupt input pin and the circuit treats the ECO pin input as being fixed at 0 Setting the bit to 1 Selects the ECO pin as an interrupt input pin and the circuit passes the ECO pin input to INTOOO ch 0 of the external interrupt circuit In this case the input signal to the ECO pin can generate an external interrupt if INTOO ch 0 operation is enabled in the external interrupt circuit bitl UIO UIO interrupt pin select bits UCKO UCKO interrupt pin select bit This bit is used to determine whether to select the UIO pin as an interrupt input pin Setting the bit to 0 Deselects theUIO pin as an interrupt input pin and the circuit treats the UIO pin input as being fixed at 0 Setting the bit to 1 Selects the UIO pin as an interrupt input pin and the circuit passes the UIO pin input to INTOO ch 0 of the external interrupt circuit In this case the input signal to the UIO pin can generate an external interrupt if INTOO ch 0 operation is enabled in the external interrupt circuit This bit is used to determine whether to select the UCKO pin as an interrupt input pin Setting the bit to 0 Deselects the UCKO pin as an interrupt input pin and the circuit treats th
153. conjunction with an external circuit Output inversion mode This mode can invert the PPG output value 238 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 2 Configuration of 8 16 bit PPG 16 2 Configuration of 8 16 bit PPG This section shows the block diagram of 8 16 bit PPG E Block Diagram of 8 16 bit PPG Figure 16 2 1 shows the block diagram of the 8 16 bit PPG Figure 16 2 1 Block Diagram of 8 16 bit PPG Used as the select signal of each selector Cycle setup register Duty setup register 512 CKS11 CKS10 Y Cycle setup Duty register buffer buffer register cycle setup ckso2 cksoi cksoo Duy setup register Cycle setup register Duty setup buffer register 1 MCLK 2 MCLK 4 MCLK 8 MCLK 01 Compa PPG timer 00 Prescaler gt CLK LOAD rator 32 MCLK 00 circuit 27 F ou sl 40 a ee 2 F i 11 8 bit down counter REVO0O PPG timer 00 1 0 t gt STOP 1 Q Pin E PPGOO Edge on T IH gt START BORROW 0 1 t PIEO PUFO Poeno I POENO
154. continuous mode or PWM timer function variable cycle mode The bit is set to 1 when a counter overflow occurs during PWC or input capture function This bit always returns 1 to a read modify write RMW instruction e Writing 0 to the bit sets it to 0 Writing 1 to this bit has no effects on the operation The bit is 0 when the PWM function variable cycle mode has been selected The IF bit in the TOICRI timer 01 register is 0 during 16 bit operation Writing to this bit sets the timer output TMCRO TO1 TOO initial value The value in this bit is reflected in the timer output when the timer operation enable bit TOOCR1 TOICRI STA changes from 0 to 1 During 16 bit operation TMCRO MOD 1 use the SO bit in the TOOCRI timer 00 register to SO set the timer output initial value In this case the value of the S bit in the other register is Timer output initial meaningless value bit An attempt to write to this bit is nullified during timer operation TOOCRI TOICRI STA 1 During 16 bit operation however a value can be written to the SO bit in the TOICRI timer 01 register even during timer operation but it has no direct effect on the timer output The value of this bit is meaningless when the PWM timer function either fixed cycle or variable cycle mode or input capture function has been selected IF Timer reload overflow flag This bit enables or disabled timer output OE
155. data access by CPU and by the parallel programmer e MB95F136MBS F136NBS F136MBW F 1 36eNBW F136JBS F136JBW 32 Kbytes Flash memory CPU address Programmer address 8000 180004 32 Kbytes FFFFy 1FFFF Programmer addresses are corresponding to CPU addresses used when the parallel programmer programs data into Flash memory These programmer addresses are used for the parallel programmer to program or erase data in Flash memory CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 521 APPENDIX APPENDIX G Writing to Flash Microcontroller Using Parallel Writer MB951 30 MB Series Programming method 1 Set the type code of the parallel programmer to 17237 2 Load program data to programmer addresses 180005 to 1FFFF 3 Write data with the parallel programmer e MB95F134MBS F134NBS F134JBS F134MBW F134NBW F134JBW 16 Kbytes Flash memory CPU address Programmer address C0004 1C000 16 Kbytes FFFFy 1FFFFj Programmer addresses are corresponding to CPU addresses used when the parallel programmer programs data into Flash memory These programmer addresses are used for the parallel programmer to program or erase data in Flash memory Programming method 1 Set the type code of the parallel programmer to 17237 2 Load program data to programmer addresses 1C000g to 1FFFFg 3 Write data with the parallel programmer e MB95F133MBS F133NBS F133JBS F13
156. data sets the TDRE flag to 0 If transmission is enabled SCR TXE 1 at this time the data is written to the transmit shift register and the transmission is started sequentially from the start bit in the next serial clock cycle If the transmit interrupt is enabled TIE 1 the transmit data is transferred from the LIN UART transmit data register TDR to transmit shift register the TDRE flag is set to 1 and an interrupt occurs When the data length is set to 7 bit CL 0 the bit7 in the TDR register is an unused bit regardless of the transfer direction select bit BDS setting LSB first or MSB first Note Since the initial value of transmit data empty flag bit SSR TDRE is 1 an interrupt is generated immediately when transmit interrupts are enabled SSR TIE 1 Reception The reception is performed when reception is enabled SCR RXE 1 When the start bit is detected one frame data is received according to the data format defined in the LIN UART serial control register SCR If an error occurs the error flag SSR PE ORE FRE is set After the reception of the one frame data is completed the received data is transferred from the reception shift register to the LIN UART reception data register RDR and the reception data register full flag bit SSR RDRF is set to 1 If the reception interrupt request is enabled SSR RIE 1 at this time a reception interrupt request is output To read the received data c
157. detector x 2 channels Noise filter x 2 channels 198 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 2 Configuration of 8 16 bit Compound Timer E Block Diagram of 8 16 bit Compound Timer Figure 15 2 1 Block Diagram of 8 16 bit Compound Timer TOOCRO CEJ CO Timer 00 8 bit counter CKOO gt Clocks from prescaler 0 Count Timer output Time Base Timer CK06 clock a selector 5 8 bit comparator Output CK07 5 controller ENOO o 8 bit data register aa fet ez ter detector TIO 1 STAJHO IE IR BF IF SO oE ien TOOCR1 EE erea Yona avo TO1CRO Timer 01 ERO 16 bit mode clock 8 bit counter Clocks from 0 Count prescaler Timer output 1 Ti B clock 8 TOO S ase 16 selector 6 bit 1 Output CK17 o 5 Oo m 8 bit data register Lr Noise Edge filter detector ECO1 TO1CR1 STAJHO IE IR BF IF SOJOE CEEI 1 1 I 1 I 1 I I 1 ENO1 1 I 1 I 1 I 1 I I I 1 I Register shared by timer 00 and timer 01 8 bit counter This counter serves as the basis for various timer operations It can be used either as two 8 bit counters or as a 16 bit counter 8 bit comparator The comparator compares the values in the 8 16 bit compound tim
158. down counter 16 bit PPG Down Counter Registers Upper Lower PDCRHO PDCRLO Figure 17 5 2 16 bit PPG Down Counter Registers Upper Lower PDCRHO PDCRLO 16 bit PPG down counter register upper PDCRHO Address bit7 bit5 bit4 bit3 bit2 bit bito Initial value PDCRHO DC15 DC14 DC13 DC12 DC11 DC10 DCO8 000000008 R WX R WX R WX R WX R WX R WX R WX R WX 16 bit PPG down counter register lower PDCRLO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value OFAB PDCRLO DCO7 DC06 5 DC04 DCO2 DCO1 00000000 R WX R WX R WX HR WX R WX Read only Readable writing has no effect on operation These registers form a 16 bit register which is used to read the count value from the 16 bit down counter The initial values of the register are all 0 Always use one of the following procedures to read from this register Use the MOVW instruction use a 16 bit access instruction to read the PDCRHO register address Use the MOV instruction and read PDCRHO first and PDCRLO second reading PDCRHO automatically copies the lower 8 bits of the down counter to PDCRLO These registers are read only and writing has no effect on the operation Note If you use the MOV instruction and read PDCRLO before PDCRHO PDCRLO will return the value from the previ
159. for 8 16 bit PPG Timer 261 Sample Programs for External Interrupt m 299 Setup Methods without Sample Program sese 261 283 299 Sample Program Setup Methods without Sample Program sese 261 283 299 Sample Programs Sample Programs for 8 10 bit A D Converter 444 Sample Programs for UART SIO 342 Sample Programs for Watch Counter 181 Sample Programs for Watch Prescaler 167 Sample Programs of LIN UART 422 SCR LIN UART serial control register SCR 366 Sector Sector Configuration of 256 Kbit Flash Memory 467 Selecting Difference Points among Products and Notes on Selecting a 7 Sequence Command Sequence Table 471 Serial Programming Basic Configuration of Serial Programming Connection for Flash Memory Products 484 Example of Serial Programming Connection 487 Setting 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO 271 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 272 Setting 16 bit PPG 258 Setting 8 bit Independent Mode 254 Setting 8 bit Prescaler 8 bit PPG Mode 256 Setup 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register PPSOT PPSOO
160. for the oscillation stabilization wait time External resets and resets are also affected by the RAM access protection function and main clock oscillation stabilization wait time In the case of a power on reset or low voltage detection reset the reset continues during the oscillation stabilization wait time E Reset Output The RST pin of 5 V products with the reset For details see Table 1 2 1 outputs L level during reset time However a reset pin does not output L level in the case of an external reset The RST pin of 3 V products and 5 V products without the reset outputs do not have an output function CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 87 CHAPTER 7 RESET 7 1 Reset Operation MB95130 MB Series ll Overview of Reset Operation Figure 7 1 1 Reset Operation Flow Power on reset Software reset aca d low voltage detection Watchdog reset reset Suppress resets during RAM access Suppress resets during RAM access During reset In sub clock mode sub PLL clock mode or stop mode Sub clock mode During operation in sub PLL clock mode Main clock oscillation Main clock oscillation stabilization wait time stabilization wait time E Reset state Reset state Main clock oscillation stabilization wait time Reset state Released from extemal reset Capture mode data Address FFFDy Capture reset vector Address FFFF Mode fetch Capture instr
161. i 2 Vcc 78 14 15 User power supply GND 1 22 Vss d 1 28 Pin 14 Pin 1 Pins 3 4 9 10 11 12 16 17 18 X 19 20 23 24 25 26 are Open 0 10 285 28 15 DX10 28S Right angle type Connector manufactured by Hirose Electric Co Ltd pin alignment As the UIO UOO and UCKO pins are also used by the user system you need to provide a control circuit as shown below if you want to disconnect from the user circuit during serial writing The TICS signal of the flash microcontroller programmer can be used to disconnect from the user circuit during serial writing See the connection example in Figure 27 2 1 for details Figure 27 3 2 Control Circuit AF220 AF210 AF120 AF110 programming control pin Flash memory products programming 24 7kQ AF220 AF210 AF120 AF110 control pin TICS pin User circuit Only connect to the AF220 AF210 AF120 or AF110 while the user power supply is turned off CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 491 CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 27 3 Example of Minimum Connection to Flash Microcontroller MB951 30 MB Series Programmer Note The pull up and pull down resistances in the above example connection are examples only and may be adjusted to suit your system If variation in the input level to the MOD pin is possible due to noise or other factors it is also recommended that you use a capacitor or other method to minimiz
162. input pin 1 This pin works as the serial clock output pin and outputs the clock in operation mode 2 synchronous Note When the SCK pin is used as a serial clock input SCKE 0 set the corresponding DDR bits in the general purpose I O port as an input port Also select the external clock EXT 1 by using the clock select bit When the SCK pin is set as a serial clock output SCKE 1 this pin works as a serial clock output pin regardless of the state of the general purpose I O port SCKE LIN UART serial clock output enable bit Enable or disable output of serial data 0 The SOT pin works as a general purpose I O port 1 The SOT pin works as a serial data output pin SOT When set as a serial data output SOE 1 the SOT pin works as a SOT pin regardless of a general purpose I O port SOE LIN UART serial data output enable bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 369 CHAPTER 22 LIN UART 22 4 Registers of LIN UART 22 4 3 MB95130 MB Series LIN UART Serial Status Register SSR The LIN UART serial status register SSR i S used to check the status of transmission reception or error and to enable disable interrupts LIN UART Serial Status Register SSR Figure 22 4 4 LIN UART serial status register SSR bit bit6 bits bit4 bit3 bit2 biti bitO R IWXR WX R WX R WX R W R W R W Address 0052H Initial value
163. interrupt is accepted a branch to the interrupt service routine takes place with the content of the interrupt vector table address corresponding to the interrupt request as the address of the branch destination The priority for each interrupt request can be set to one of four levels using the interrupt level setting registers ILRO to ILR5 If another interrupt request with the same or lower level occurs during execution of the interrupt service routine the interrupt is processed after the current interrupt handler routine completes If interrupt requests of the same level occur at the same time IRQO is assigned the highest priority FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 8 INTERRUPTS MB95130 MB Series 8 1 Interrupts Table 8 1 1 Interrupt Requests and Interrupt Vectors Vector table address Priority for equal level Bit name of interrupt level Interrupt requests Upper Lower setting register generated simultaneously Interrupt request Reset vector Mode data IRQO 100 1 0 IRQI L01 1 0 IRQ2 L02 1 0 IRQ3 L03 1 0 IRQ4 L04 1 0 IRQS 105 1 0 IRQ6 L06 1 0 IRQ7 L07 1 0 IRQS 108 1 0 IRQ9 109 1 0 IRQ1O L10 1 0 IRQII L11 1 0 IRQ12 L12 1 0 IRQ13 L13 1 0 IRQ14 L14 1 0 IRQI15 L15 1 0 IRQ16 L16 1 0 IRQ17 L17 1 0 IRQ18 L18 1 0 IRQ19 L19 1 0 IRQ20 L20 1 0 IRQ21 L21 1 0 IRQ22 L22 1 0 IRQ23 L23 1 0 For interrupt sources see APPENDIX B Table of Interrup
164. interrupt sources for the external interrupt circuit include detection of the specified edge of the signal inputted to an external interrupt pin B interrupt During Operation of External Interrupt Circuit When the specified edge of external interrupt input is detected the corresponding external interrupt request flag bit EIC EIRO EIR1 is set to 1 In this case an interrupt request will be generated to the interrupt controller if the corresponding interrupt request enable bit is enabled EIC EIEO EIE1 1 Write 0 to the corresponding external interrupt request flag big to clear the interrupt request in the interrupt process routine E Registers and Vector Table Related to Interrupts of External Interrupt Circuit Table 18 6 1 Registers and Vector Table Related to Interrupts of External Interrupt Circuit Interrupt Interrupt Interrupt level setting register Vector table address request No Register Setting bit Upper Lower ch Channel Refer to APPENDIX B Table of Interrupt Causes for the interrupt request numbers and vector tables of all peripheral functions CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 295 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 7 Explanation of External Interrupt Circuit Operations and Setup MB95130 MB Series Procedure Example 18 7 Explanation of External Interrupt Circuit Operations and Setup Procedure Example This section describes the operation of the e
165. is recommended 124 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 5 Port G 9 5 Port G Port G is a general purpose I O port This section focuses on functions as a general purpose 1 0 port E Port G Configuration Port G is made up of the following elements General purpose I O pins Port G data register PDRG e Port G direction register DDRG e Port G pull up control register PULG Input level selection register 2 ILSR2 E Port Pins Port G has three I O pins Table 9 5 1 lists the port G pins Table 9 5 1 Port G Pins I O type Pin name Function Shared peripheral functions Input Output PGO PGO general purpose I O Not shared Hysteresis Automotive 2 PG1 general purpose I O Not shared Hysteresis Automotive PG2 X1A PG2 general purpose I O Not shared Hysteresis Automotive OD Open drain PU Pull up For the 5V product the C pin is used 2 For the single system product the general purpose port is used for the dual system the sub clock oscillation pin is used 3 For 5V products the hysteresis input can be switched to an automotive input It becomes a hysteresis input besides CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 125 CHAPTER 9 I O PORT 9 5 Port G E Block Diagram of Port G Figure 9 5 1 Block Diagram of Port G MB95130 MB Series Hysteresis D5 0 N PDR rea
166. is different from write value 1 is read by read modify write ROW Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 135 CHAPTER 10 TIME BASE TIMER 10 3 Registers of the Time base Timer MB951 30 MB Series 10 3 1 Timer Control Register TBTC The time base timer control register TBTC selects the interval time clears the counter controls interrupts and checks the status E Time base Timer Control Register TBTC Figure 10 3 2 Time base Timer Control Register TBTC Address bits bit4 bit3 bit bito Initial value 000 TBIF TRIE 1 000000008 R RM1 W RAW RO WX_ RO WX RO WX R W R W RO W Time base timer initialization bit Read Write No change No effect on operation Clears the counter of time base timer 0 is always read Interval time select bit Main clock 4MHz 219 2 512 0 us 2 2x 2 Fcu 2 05ms 214 2 8 19ms 218 2 32 77ms Disables output of interrupt request Enables output of interrupt request Time base timer interrupt request flag bit Read Write Interval time has not elapsed Interval time has No change elapsed No effect on operation Clears bit R W Readable writable Read value is the same as w
167. is set 8 16 bit PPG timer 01 00 duty setup buffer register ch 0 PDS01 ch 0 PDS00 The compare value for H width of 8 16 bit PPG timer is set 8 16 bit PPG start register The start or the stop of 8 16 bit PPG timer is set 8 16 bit PPG output inversion register An initial level also includes the output of 8 16 bit PPG timer and it is reversed B Input Clock The 8 16 bit PPG uses the output clock from the prescaler as its input clock count clock 240 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 3 Channels of 8 16 bit PPG 16 3 Channels of 8 16 bit PPG This section describes the channels of the 8 16 bit PPG E Channels of 8 16 bit PPG MB95130 MB series has 1 channel of the 8 16 bit PPG There are 8 bit PPG timer 00 and 8 bit PPG timer 01 in 1 channel They can be used respectively as two 8 bit PPGs Also they can be used as a 16 bit PPG Table 16 3 1 and Table 16 3 2 show the channels and their corresponding pins and registers Table 16 3 1 Pins of 8 16 bit PPG PPGOO PPG timer 00 8 bit PPG 00 16 bit PPG PPGO01 PPG timer 01 8 bit PPG 01 8 bit prescaler Table 16 3 2 Registers of 8 16 bit PPG Channel Register name Corresponding register as written in this manual 1 8 16 bit PPG timer 01 control register 8 16 bit PPG timer 00 control register 0 501 8 16 bit PPG timer 01 cycle setup buffe
168. is shown in Figure 20 7 2 the transfer data always starts from the start bit L level and ends with the stop bit H level by performing the specified data bit length transfer with MSB first or LSB first LSB first or MSB first can be selected by the BDS bit It becomes H level at the idle state Figure 20 7 2 Transfer Data Format Y ps Y D4 Y sP Without j st 00 Y D1 Y oz Y Ds Y Da Y sP 5 J A 00 X X gt 5 bit data D X D2 X 03 X D4 X P Y SP B V With P D X D2 X 03 X D4 X P Y SP SP J J 6 bit and 8 bit data are also the same X D1 X o2 X ns X D4 X Ds X X D7 Y se D Koo X D2 X b4 X ps X pe X D7 Y sp 5 J VOCEA sT X S S P gt 8 bit data 1 X D2 X ps X D4 X ps X De X D7 X P Y SP J 7 T Start bit P Stop bit Parity bit DO to D7 Data The sequence can be selected from LSB first MSB first by the direction control register BDS bit 330 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 7 Explanation of UART SIO Operations and Setup Procedure Example Receiving operation in asynchronous clock mode UART Use UART SIO serial mode control register 1 SMC10 to select the serial data direction endian parity non parity parity polarity stop bit length character bit length an
169. it can be set to 5 bits to 8 bits when no parity is used or to 6 bits to 9 bits when parity is used Refer to Table 20 1 1 The serial data direction endian can be selected The data transfer format is NRZ Non Return to Zero Two operation modes operation modes 0 and 1 are available Operation mode 0 operates as asynchronous clock mode UART Operation mode 1 operates as clock synchronous mode SIO Operation Data length mode No parity With parity co I DA Mm co rl a Synchronous mode Asynchronous Synchronous FUJITSU MICROELECTRONICS LIMITED Stop bit length 1 bit or 2 bits CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 2 Configuration of UART SIO 20 2 Configuration of UART SIO The UART SIO consists of the following blocks e UART SIO serial mode control register 1 SMC10 e UART SIO serial mode control register 2 SMC20 e UART SIO serial status and data register SSRO e UART SIO serial input data register RDRO UART SIO serial output data register TDRO E Block Diagram of UART SIO Figure 20 2 1 Block Diagram of UART SIO PER Reception OVE State from state each block decision FER circuit Reception eee interrupt Dedicated baud rate generator TDRE 4 State from Transmission each block state TEIE D gt Transmission xternal clock inpu n decision i Pin ot interrupt UCKO
170. machine clock divided signal and time base timer output Edge detector The edge detector selects the edge of an external input signal to be used as an event for PWC timer operation or input capture operation Noise filter This filter serves as a noise filter for external input signals H pulse noise L pulse noise or H L pulse noise elimination can be selected as the filter function TIIO internal pin internally connected to the LIN UART available only in channel 0 The TIIO pin serves as the signal input pin for timer 00 it is connected to the LIN UART inside the chip For information about how to use the pin refer to CHAPTER 22 LIN UART Note that the TIO pin in channel is internally fixed to 0 B Input Clock The 8 16 bit compound timer uses the output clock from the prescaler as its input clock count clock 200 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 3 Channels of 8 16 bit Compound Timer 15 3 Channels of 8 16 bit Compound Timer This section describes the channels of 8 16 bit compound timer E Channels of 8 16 bit Compound Timer MB95130 MB series contains one channel of 8 16 bit compound timer In one channel there are two 8 bit counters Each counter can be used as two 8 bit timers or one 16 bit timer The following table lists the external pins and registers corresponding to each channel Table 15 3 1 8 16 bit Compound Timer Ch
171. mode The device enters stop mode when 1 is written to the stop bit in the standby control register STBC STP In response to an external interrupt the device returns to the RUN state after waiting for the oscillation stabilization wait time required for each clock mode When the device waits for a PLL oscillation stabilization wait time it waits for the relevant oscillation stabilization wait time or PLL oscillation stabilization wait time to elapse whichever is longer Time base timer mode The device enters time base timer mode when 1 is written to the watch bit in the standby control register STBC TMD in main clock mode or main PLL clock mode The device returns to the RUN state in response to a time base timer interrupt watch prescaler watch counter interrupt or external interrupt When the clock mode is main PLL clock mode the device waits for the main PLL clock oscillation stabilization wait time to elapse If the main PLL oscillation enable bit in the PLL control register PLLC MPEN contains 1 however the device does not wait for that time to elapse even when the clock mode is main PLL clock mode 74 Watch mode The device enters watch mode when 1 is written to the watch bit in the standby control register STBC TMD in sub clock mode or sub PLL clock mode The device returns to the normal operating state in response to a watch prescaler watch counter interrupt or external interrupt
172. or disables the programming erasing of data into from the flash memory area Set the WRE bit before invoking a flash memory program erase command Setting the bit to 0 Prevents a program erase signal from being generated even when a program erase command is input Setting the bit to 1 Allows flash memory programming erasing to be performed after program erase command is input When flash memory is not to be programmed or erased set the WRE bit to 0 to prevent it from being accidentally programmed or erased Reserved Reserved bit Be sure to set this bit to 0 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 4 Starting the Flash Memory Automatic Algorithm 26 4 Starting the Flash Memory Automatic Algorithm There are three types of commands that invoke the flash memory automatic algorithm read reset write program and chip erase il Command Sequence Table Table 26 4 1 shows commands used for programming erasing data on flash memory Table 26 4 1 Command Sequence Table 1st bus 2nd bus 3rd bus 4th bus 5th bus 6th bus Command write cycle write cycle write cycle write cycle write cycle write cycle sequence Address Data Address Data Address Data Address Data Address Data Address Data Read reset Programming Chip erasing RA Read address PA Write program address RD Read data PD Wr
173. peripheral resources listed in the table below are not affected by the clock mode division and PLL multiplier settings Table 6 1 2 lists the peripheral resources not affected by the clock mode Table 6 1 2 Peripheral Resources Not Affected by Clock Mode Peripheral Function Operating Clock Time base timer Main clock 21 main clock divided by 2 Main clock with time base timer output selected Sub clock with watch prescaler output selected dual clock product only Watch prescaler Dual clock product only Sub clock 2 F oy sub clock divided by 2 Watch counter Dual clock product only Sub clock watch prescaler output For some peripheral resources other than those listed above it may be possible to select the time base timer or watch prescaler output as a count clock Check the description of each peripheral resource for details CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 49 CHAPTER 6 CLOCK CONTROLLER 6 1 Overview of Clock Controller MB951 30 MB Series il Standby Modes The clock controller selects whether to enable or disable clock oscillation and clock supply to internal circuitry depending on each standby mode With the exception of time base timer mode and watch mode the standby mode can be set independently of the clock mode Table 6 1 3 shows the relationships between standby modes and clock supply states Table 6 1 3 Standby Modes and Clock Supply States Standby Mode C
174. port 1 input level setting when the peripheral functions UART SIO are halted Table 9 3 4 shows the pin states of the port Table 9 3 4 Pin State of Port 1 Normal operation Operating Sleep Stop SPL 1 state Stop SPL 0 Watch SPL 1 Watch SPL 0 At reset Hi Z Hi Z the pull up setting is enabled Input enabled Input cutoff Not functional I O port peripheral function I O Pin state SPL Pin state specification bit in standby control register STBC SPL Hi Z High impedance Input enabled means that the input function is in the enabled state After reset setting for internal pullup or output pin is recommended CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 119 CHAPTER 9 I O PORT 9 4 Port F MB95130 MB Series 9 4 Port F Port F is a general purpose I O port This section focuses on functions as a general purpose 1 0 port See the chapters on each peripheral function for details about peripheral functions E Port F Configuration Port F is made up of the following elements e General purpose I O pins peripheral function I O pins Port F data register PDRF Port F direction register DDRF Input level selection register 2 ILSR2 E Port F Pins Port F has two I O pins Table 9 4 1 lists the port F pins Table 9 4 1 Port F Pins I O type Pin name Function Shared peripheral functions Input Output PFO PFO general purpose I O Not shared Hysteresis Automotive CMOS
175. programs that can be used to operate the 16 bit PPG timer E Sample Programs for 16 bit PPG Timer For information about the sample programs for the 16 bit PPG timer refer to Sample Programs in Preface E Setup Methods without Sample Program How to set the PPG operation mode The operation mode select bit PCNTHO MDSE is used Operation mode Operation mode select bit MDSE PWM mode Set the bit to 0 One shot mode Set the bit to 1 Q How to select the operating clock The operating clock select bits PCNTHO CKS2 CKS 1 CKSO are used to select the clock How to enable disable the PPG output pin The output enable bit PCNTLO POEN is used When enabling PPG output Set the bit to 1 When disabling PPG output Set the bit to 0 Q How to enable disable PPG operation The timer enable bit PCNTHO CNTE is used When disabling PPG operation Set the bit to 0 When enabling PPG operation Set the bit to 1 Enable PPG operation before starting the PPG CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 283 CHAPTER 17 16 BIT PPG TIMER 17 9 Sample Programs for 16 bit PPG Timer MB951 30 MB Series Q How to start PPG operation by software The software trigger bit PCNTHO0 STRG is used When starting PPG operation by software Set the bit to 1 How to enable disable the retrigger function of the software trigger The retrigger enable bit PCNTHO RTRG is used When enabling
176. register 108 PUL1 Port 1 pull up control register 108 PULG Port G pull up control register 108 R REVC 8 16 bit PPG output inversion register 251 539 T TOOCRO TOOCR1 TOODR TO1CRO TO1CR1 TO1DR TMCRO TMCR1 540 8 16 bit compound timer 00 control status register 0 205 8 16 bit compound timer 00 control status register 1 eh Ounneri nne 208 8 16 bit compound timer 00 data register E T E EET A 214 8 16 bit compound timer 01 control status register 0 0 205 8 16 bit compound timer 01 control status register 1 0 208 8 16 bit compound timer 01 data register China pie voee aree Ene 214 8 16 bit compound timer 00 01 timer mode control register ch O 211 8 16 bit compound timer 00 01 timer mode control register ch 1 211 Pin Function Index ANOO ANO1 ANO2 ANO3 ANO4 5 ANO6 ANO7 AVcc AVss ECO INTOO A D converter analog input pin ch 0 431 A D converter analog input pin ch 1 431 A D converter analog input pin ch 2 431 A D converter analog input pin ch 3 431 A D converter analog input pin ch 4 431 A D converter analog input pin ch 5 431 A D converter analog input pin ch 6 431 A D converter analog input pin ch
177. reset The main clock monitoring enable bit CSVCR MSVE of clock supervisor is initialized only by power on reset The oscillation stabilization wait time setting register WATR of clock control block is initialized only by power on reset CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 93 CHAPTER 7 RESET 7 3 Notes on Using Reset MB95130 MB Series 94 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 8 INTERRUPTS This section explains the interrupts 8 1 Interrupts Code CM26 00105 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 95 CHAPTER 8 INTERRUPTS 8 1 Interrupts MB95130 MB Series 8 1 Interrupts This section explains the interrupts Overview of Interrupts The F MC 8FX family has 24 interrupt request input lines corresponding to peripheral resources for each of which an interrupt level can be set independently When a peripheral resource generates an interrupt request the interrupt request is output to the interrupt controller The interrupt controller checks the interrupt level of that interrupt request and then passes the occurrence of the interrupt to the CPU The CPU services the interrupt according to the interrupt acceptance status Interrupt requests also release the device from standby mode to resume instruction execution E Interrupt Requests from Peripheral Resources 96 Table 8 1 1 shows the interrupt requests corresponding to the peripheral resources When an
178. selected the clock source must be set as an external clock and the external clock input must be enabled SMR SCKE 0 EXT 1 OTO 1 Setting the SCDE bit to 1 at sending side of serial clock in mode 2 SCDE outputs a delayed serial clock as shown in Figure 22 7 5 This bit is Serial clock delay enable bit effective in serial peripheral interface This bit is fixed to 0 in modes 0 1 and 3 Add the start stop bit to the synchronous data format when this bit is set to in mode 2 This bit is fixed to 0 in modes 0 1 and 3 The read value is indeterminate 0 is always set LBR LIN Synch break generation bit MS Sending side receiving side of serial clock select bit SSM Start stop bit mode enable bit Reserved bit RBI Reception bus idle detection flag bit TBI Transmit bus idle detection flag bit When the SIN pin is H level and reception is not performed this bit is Do not use this bit when SSM z 0 in operation mode 2 This bit is 1 when there is no transmission on the SOT pin Do not use this bit when SSM 0 in operation mode 2 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 377 CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series 2247 LIN UART Baud Rate Generator Register 1 0 1 0 BGR1 BGRO The LIN UART baud rate generator register 1 0 BGR1 BGRO sets the division ratio of the serial clock Also the count value in the transmi
179. the L level will always be outputted if inverted polarity is set When the duty setting registers are set to 005 the L level will always be outputted if normal polarity is set or the H level will always be outputted if inverted polarity is set When the value set in the duty setting registers is greater than the value in the 16 bit PPG cycle setting buffer registers the L level will always be outputted if normal polarity is set and the H level will always be outputted if inverted polarity is set 272 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 5 Registers of 16 bit PPG Timer 17 5 4 16 bit PPG Status Control Register Upper Lower PCNTHO PCNTLO The 16 bit PPG status control register is used to enable and disable the 16 bit PPG timer and also to set the operating status for the software trigger retrigger control interrupt and output polarity This register can also check the operation status 16 bit PPG Status Control Register Upper PCNTHO Figure 17 5 5 16 bit PPG Status Control Register Upper PCNTHO bi7 06 bib bito Initial value A soa cNTuo CNTE STRG MDSE RTRG CKs2 cKs1 ckso PGMs 90000000 RW ROW RW RW RW RW RW RW PGMS PPG output mask enable bit 0 Disables PPG output mask 1 Enables PPG output mask gt CKS2 CKS
180. the PPG timer Reading this bit always returns 0 STRG Software trigger bit This bit is used to set the PPG operation mode MDSE When the bit is set to 0 the PPG operates in PWM mode Mode select bit When the bit is set to 1 the PPG operates in one shot mode Note Modifying this bit is prohibited during operation RTRG This bit is used to enable or disable the software retrigger function of the PPG during operation Software retrigger When the bit is set to 0 the software retrigger function is disabled enable bit When the bit is set to 1 the software retrigger function is enabled These bits select the operating clock for the 16 bit PPG timer The count clock signal is generated by the prescaler Refer to 6 12 Operating Explanation of CKS2 to CKSO Prescaler Count clock select bits Note As the time base timer TBT is halted in sub clock mode Foy 2 and Foy 2 cannot be selected in this case This bit is used to mask the PPG output to a specific level regardless of the mode setting MDSE bit5 period setting PCSRHO PCSRLO and duty setting PDUTHO PDUTLO PGMS When the bit is set to 0 the PPG output mask function is disabled PPG output mask When the bit is set to 1 the PPG output mask function is enabled When the PPG output polarity enable bit setting is set to normal OSEL bit in PCNTLO register 0 the output is always masked to L When the polarity setting is se
181. the first cycle of the PPG output immediately after the activation The error varies depending on the count clock selected The output however is performed properly in the succeeding cycles Precaution regarding interrupts A PPG interrupt is generated when the interrupt enable bit PIEI PIEO is set to 1 and the interrupt request flag bit PUF1 PUFO in the 8 16 bit PPG timer 01 00 control register is also set to 1 Always clear the interrupt request flag bit PUF1 PUFO to 0 in the interrupt routine 260 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 9 Sample Programs for 8 16 bit PPG Timer 16 9 Sample Programs for 8 16 bit PPG Timer We provide sample programs that can be used to operate the 8 16 bit PPG timer il Sample Programs for 8 16 bit PPG Timer For information about the sample programs for the 8 16 bit PPG timer refer to Sample Programs in Preface E Setup Methods without Sample Program How to enable stop PPG operation The PPG operation enable bit PPGS PENOO is used for PPG timer 00 PPG operation enable bit PENOO When stopping PPG operation Set the bit to 0 When enabling PPG operation Set the bit to 1 PPG operation must be enabled before the PPG is activated The PPG operation enable bit PPGS PENO1 is used for PPG timer 01 PPG operation enable bit PENO1 When stopping PPG operation Set the bit to 0
182. the overflow flag for a timer counter is set during a CPU break and the interrupt is enabled the interrupt routine will run immediately when execution restarts after the break 2 Clearing the overflow flag for a timer counter via the memory window or similar during a CPU break will not appear to work as the flag will quickly be reset again Prohibited Access to Undefined I O Addresses The debugger for the F MC 8FX family uses the same evaluation device for debugging all models This evaluation device includes all peripheral functions that may be used during debugging Accessing a register that does not exist on your target production device may invoke a peripheral function that should not exist and may result in abnormal operation Accordingly please do not access undefined address areas FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 2 HANDLING DEVICES MB95130 MB Series 2 1 Device Handling Precautions E Pin Connection Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch up leaving to permanent damage Unused input pins should always be pulled up or down through resistance of at least 2 kQ Any unused input output pins may be set to output mode and left open or set to input mode and treated the same as unused input pins If there is unused output pin make it open Treatment of Power Supply Pins on A D Converter Connect to be AV cc Vcc and AV gg Vss even if the A D
183. to 1 enable the operation of the wild register function CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 191 CHAPTER 14 WILD REGISTER 14 3 Registers of Wild Register MB95130 MB Series 14 3 4 Wild Register Data Test Setup Register WROR The wild register data test setup register WROR enables disables reading from the corresponding wild register data setup register WRDRO to WRDR2 Bi Wild Register Data Test Setup Register WROR Figure 14 3 5 Wild Register Data Test Setup Register WROR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 00774 Reser Reser Reser DRR2 DRR1 DRRO 00000000g ved ved ved RO WX RO WO RO WO RO WO R W R W R W R W Readable writable Read value is the same as write value RO WO Reserved bit Write value is 0 read value is 0 RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined Table 14 3 5 Functional Description of Wild Register Data Test Setup Register WROR Bit name Function These bits are undefined Undefined bits The read value is 0 Writing has no effect on the operation These bits are reserved Reserved bits The read value is 0 Always set 0 These bits enable disable the normal reading from the corresponding data setup register of the wild register DRRO enables disables reading from the wild register data setup register
184. up to one count clock may occur at the beginning of a count cycle depending on the timing for setting the ISEL bit to 1 3 When the counter underflows the WCFLG bit of the WCSR register is set to 1 generating an interrupt 4 Write 0 to the WCFLG bit to clear it 5 If RCTRS to RCTRO bits are modified during counting the reload value will be updated during a reload after the counter is set to 1 6 When writing 0 to the ISEL bit the counter becomes 0 and stops operation Figure 13 5 1 Descriptive Diagram of Watch Counter Operation ISEL 2 6 countet M UUU U UU UU UU UNUT caie aa 11e 1 RCTRS5 to RCTRO crrstoctro_o 7 6 5 4 2 7 5 4 WCFLG 3 4 Note When the operation is reactivated by WCSR ISEL 0 after counter stop please reactivate after confirming reading WCSR CTR 5 0 twice and clearing to CTR 5 0 2000000g 178 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 13 WATCH COUNTER MB951 30 MB Series 13 5 Explanation of Watch Counter Operations and Setup Procedure Example il Operation in Sub Clock Stop Mode When the device enters the sub clock stop mode the watch counter stops the count operation and the watch prescaler is also cleared Therefore the watch counter cannot count the correct value after the sub clock stop mode is cancelled After the sub clock stop mode is cancelled the ISEL bit must always be set to 0 to clear the c
185. way CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 43 CHAPTER 5 CPU 5 3 Placement of 16 bit Data in Memory MB951 30 MB Series 44 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER This chapter describes the functions and operations of the clock controller 6 1 Overview of Clock Controller 6 2 Oscillation Stabilization Wait Time 6 3 System Clock Control Register SYCC 6 4 PLL Control Register PLLC 6 5 Oscillation Stabilization Wait Time Setting Register WATR 6 6 Standby Control Register STBC 6 7 Clock Mode 6 8 Operations in Low power Consumption Modes Standby Modes 6 9 Clock Oscillator Circuits 6 10 Overview of Prescaler 6 11 Configuration of Prescaler 6 12 Operating Explanation of Prescaler 6 13 Notes on Use of Prescaler Code CM26 00123 1E Page 78 81 82 84 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 45 CHAPTER 6 CLOCK CONTROLLER 6 1 Overview of Clock Controller MB951 30 MB Series 6 1 Overview of Clock Controller The F MC 8FX family has a built in clock controller that optimizes its power consumption It includes dual clock product supporting both of the main clock and sub clock and single clock product supporting only the main clock The clock controller enables disables clock oscillation enables disables clock supply to the internal circuitry selects the clock source and controls the PLL and frequency divider circuits E Overview of Clock Con
186. writing 1 to this bit during A D conversion with EXT 0 AD A D conversion startup bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 435 CHAPTER 23 8 10 BIT A D CONVERTER 23 4 Registers of 8 10 bit A D Converter 23 4 2 MB95130 MB Series 8 10 bit A D Converter Control Register 2 ADC2 8 10 bit A D converter control register 2 ADC2 selects the 8 10 bit A D converter function selects the input clock and performs interrupt and status checking E 8 10 bit A D Converter Control Register 2 ADC2 Figure 23 4 3 8 10 bit A D Converter Control Register 2 ADC2 Address bit7 R W 006DH TIM1 TIMO ADCK ADIE 000000008 W bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value R W RW RW RW RW RW R 1 CKDIV1 CKDIVO 0 0 Clock CKIN select bits Continuous activation enable bit Start using the AD bit in the ADC1 register Continuous activation with the clock selected by the ADCK bit in the ADC2 register ADIE Interrupt request enable bit Disables interrupt request output Enable interrupt request output External start signal select bit Start via ADTG input pin 1 Start via 8 16 bit compound timer TOOO output TIM1 TIMO Sampling time select bits Co 0 CKIN x 4 0 1 CKIN x 7 1 0 CKIN x 10 CKIN x 16 AD8 Precision select bit 0 10 bit precision 1 8 bit precision R W
187. you write 1 simultaneously to two or more of the stop bit STP sleep bit SLP software reset bit SRST and watch bit TMD priority is given to them in the following order 1 Software reset bit SRST 2 Stop bit STP 3 Watch bit TMD 4 Sleep bit SLP When released from the standby mode the device returns to the normal operating status 64 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 7 Clock Mode 6 7 Clock Mode The clock modes available are main clock mode sub clock mode main PLL clock mode and sub PLL clock mode Mode switching takes place according to the settings in the system clock control register SYCC Sub clock mode and sub PLL clock mode are not supported by single clock product il Operations in Main Clock Mode Main clock mode uses the main clock as the machine clock for the CPU and peripheral resources The time base timer operates with the main clock The watch prescaler and watch counter operate with the sub clock on dual clock product If you set standby mode during operation in main clock mode the device can enter sleep mode stop mode or time base timer mode After a reset main clock mode is always set regardless of the clock mode used before the reset E Operations in Sub Clock Mode on Dual Clock Product Sub clock mode uses the sub clock as the machine clock for the CPU and peripheral resources with main clock oscilla
188. 0 5 3 UART SIO Serial Status and Data Register SSRO The UART SIO serial status and data register SSRO indicates the transmission reception status and error status of the UART SIO UART SIO Serial Status and Data Register SSRO Figure 20 5 4 UART SIO Serial Status and Data Register SSRO Address bit bit6 bits bit4 bits bit2 biti Initial value SSRO 0058H PER OVE FERRDRF TCPLTDRE 000000015 RO WX RO WX R WX R WX R WX R WXR RMI WR WX R WX RO WX Transmission data register empty flag 0 Transmit data present 1 Transmit data absent TCPL Transmission completion flag 0 Cleared by writing 1 Serial transmission complete RDRF Reception data register full flag 0 Receive data absent 1 Receive data present Framing error flag 0 Framing error absent 1 Framing error present Overrun error flag 0 Overrun error absent 1 Overrun error present Parity error flag 0 Parity error absent 1 Parity error present R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction Read only Readable writing has no ef fect on operation Undefined bit Read value is 0 writing has no effect on operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 323 CHAPTER 20 UART SIO 20 5 Registers of UART SIO MB95130 MB Series Table 20 5 3 Functional De
189. 0 bit A D converter Use the clock select bits ADC2 CKDIV 1 CKDIV0 to select the operating clock Selecting the sampling time of the 8 10 bit A D converter Use the sampling time select bits ADC2 TIMI TIMO to select the sampling time Controlling the analog switch for internal reference power shutdown of the 8 10 bit A D converter Use the analog switch control bit ADC1 ADMV X to control the internal reference power shutdown analog switch Control item Analog switch control bit ADMVX To turn off internal reference power supply Set the bit to 0 To turn on internal reference power supply Set the bit to 1 Q Selecting the 8 10 bit A D converter activation method Use the continuous activation enable bit ADC2 EXT to select the startup trigger A D startup factor Continuous activation enable bit EXT To select the software trigger Set the bit to 0 To select the input clock rising signal Set the bit to 1 Generating a software trigger Use the A D conversion start bit ADC1 AD to generate a software trigger To generate a software trigger Set the bit to 1 444 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 8 Sample Programs for 8 10 bit A D Converter e Activation using the input clock A startup trigger is generated at the rise of the input clock signal To select the input clock use the external start signal select bit ADC2 A
190. 00 0 eee 71 Check That Clock mode Transition has been Completed before Setting Standby Mode 71 Combinations of Clock Mode and Standby Mode 51 Operations in Standby Mode 451 Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition 53 Overview of Transitions to and from Standby Mode LIE 70 Pin States in Standby Mode 70 Place at Least Three NOP Instructions Immediately Following a Standby Mode Setting Instruction 71 Standby Mode 50 Standby Mode is Also Canceled when the CPU Rejects Interrupts sess 71 Standby Mode State Transition Diagram 72 Start 8 16 bit PPG Start Register PPGS 250 Startup Example Startup Flowchart when using the Clock Nulvsasri de ER 462 State Transition Diagram Clock Mode State Transition Diagram 66 Standby Mode State Transition Diagram 72 Status 16 bit PPG Status Control Register Lower PCNTLEO niet eben thd 275 16 bit PPG Status Control Register Upper uino 273 8 16 bit Compound Timer 00 01 Control Status Register 0 205 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCRI TOI1CR1 208 Status Register 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCRI TOICR1
191. 0D 103 MB95F133MBW F133NBW F 133JBW MB95F134MBW F134NBW F134JBW MB95F136MBW F136NBW F136JBW 00001 0000 00001 00804 00804 00804 RAM 3 75K bytes RAM 1K bytes RAM 01004 Registers 01004 Registers 01004 Registers 02004 77777 02004 77777 0200 7777 0480 Address 1 Access prohibited Access prohibited OF80 OF80 OF80 Extended I O Extended I O Extended I O 1000 10004 10004 Access prohibited Access prohibited Flash 60K bytes 80004 Address 2 ROM 32K bytes Flash memory FFFFy FFFFy FFFFY Flash Flash memory ROM Mask ROM CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 29 CHAPTER 3 MEMORY SPACE 3 2 Memory Map MB95F133MBS F133NBS F133JBS MB95F133MBW F133NBW F133JBW Flash memory 8 Kbytes 256 bytes MB95130 MB Series Address 1 Address 2 MB95F134MBS F134NBS F134JBS MB95F134MBW F134NBW F134JBW 16 Kbytes 512 bytes MB95F136MBS F136NBS F136JBS MB95F136MBW F136NBW F136JBW 32 Kbytes 1 Kbytes 30 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 4 MEMORY ACCESS MODE This chapter describes the memory access mode 4 1 Memory Access Mode Code CM26 00102 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 31 CHAPTER 4 MEMORY ACCESS MODE 4 1 Memory Access Mode MB95130 MB Series 4 1 Memory Access Mode The memory access mode supported by this series is only single chip mode E Single chip Mod
192. 1 is set to 1 The interrupt service routine can therefore be used to count the number of times the overflow occurs The capture value in the 8 16 bit compound timer 00 01 data register TOODR TO1DR must be nullified if an interrupt occurs before the timer is activated before 1 is written to the STA bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 231 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 13 Operating Description of Input Capture Function MB951 30 MB Series When the timing at which the 8 16 bit compound timer captures a counter value is the detection of either edge of the external input signal TOOCRO TO1CRO F3 F0 11005 or 11115 the operations in falling edge detection vary according to the level of the external input signal as explained below External input signal level H In both free run mode and clear mode the first falling edge is ignored no counter value is transferred to the data register TOODR TO1DR and the pulse width measurement completion edge detection flag TOOCR1 TOI CR 1 16 is not set In addition in clear mode the counter is not cleared either External input signal level L The 8 16 bit compound timer starts edge detection from the first rising edge Figure 15 13 2 Operating Diagram of Input Capture Function Capture value in TOODR TO1DR Falling edge of capture Rising edge of capture Rising edge of Falling edge of External input capture i a Caunterci
193. 1 CKSO Counter clock select bit 0 0 0 MCLK A 0 0 1 MCLK 2 0 1 0 MCLK 4 0 1 1 MCLK 8 1 0 0 MCLK 16 1 0 1 MCLK 32 1 1 0 Fcu 27 1 1 1 Fcu 2 MCLK Machine clock Main clock RTRG Software retrigger enable bit 0 Disables software retrigger 1 Enables software retrigger MDSE Mode select bit 0 PWM mode 1 One shot mode Software trigger bit Write Read 0 No effect on operation 1 Generates software trigger CNTE Timer enable bit 0 Stops PPG timer 1 Always reads 0 R W Readable writable Read value is the same as write value RO W Write only Read value is 0 writing has no effect on operation Initial value Enables PPG timer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 273 CHAPTER 17 16 BIT PPG TIMER 17 5 Registers of 16 bit PPG Timer MB951 30 MB Series Table 17 5 1 16 bit PPG Status Control Register Upper PCNTHO Bit name Function This bit is used to enable stop PPG timer operation When the bit is set to 0 the PPG operation halts immediately and the PPG output goes to the initial level L output if OSEL is 0 H output if OSEL is 1 When the bit is set to 1 PPG operation is enabled and the PPG goes to standby to wait for a trigger CNTE Timer enable bit This bit is used to start the PPG timer by software When the bit is set to 1 setting the CNTE bit to 1 starts
194. 1 PPG Mode 256 524 A A D Conversion A D Conversion Functions eeeeees 428 Operations of A D Conversion Function 441 A D Converter Block Diagram of 8 10 bit A D Converter 429 Block Diagram of Pins Related to 8 10 bit A D Converter Block Diagram 432 Interrupts During 8 10 bit A D Converter Operation A 439 List of 8 10 bit A D Converter Registers 433 Notes on Use of 8 10 bit A D Converter 443 Operations of 8 10 bit A D Converter s Conversion Function ttti ente 440 Pins of 8 10 bit A D Converter 431 Register and Vector Table Related to 8 10 bit A D Converter Interrupts 439 Sample Programs for 8 10 bit A D Converter 444 ADC 8 10 bit A D Converter Control Register 1 ADC1 D 434 8 10 bit A D Converter Control Register 2 ADC2 436 ADDH 8 10 bit A D Converter Data Registers Upper Lower ADDH 438 ADDL 8 10 bit A D Converter Data Registers Upper Lower ADDH ADDL enn 438 Addressing Explanation of Addressing 506 Applicable Addresses Wild Register Applicable Addresses 193 Arithmetic Operation Arithmetic Operation Instructions 516 Asynchronous LIN Mode Asynchronous LIN Mode Operation 405
195. 110 TICS pin User circuit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 485 CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 27 1 Basic Configuration of Serial Programming Connection for MB95130 MB Series Flash Memory Products Oscillation Clock Frequency and Serial Clock Input Frequency The permitted frequency for the input serial clock on the flash memory products is calculated from the following formula Accordingly modify the serial clock input frequency by setting the flash microcontroller programmer according to the oscillation clock frequency used Permitted frequency for the input serial clock 0 125 X Oscillation clock frequency Example Maximum serial clock Maximum serial clock Maximum serial clock frequency that can be frequency that can be set frequency input to the on the AF220 AF210 AF120 thatcan be set on the microcontroller and AF110 AF200 Oscillation clock frequency at AMHz 500kHz 500kHz 500kHz at 8MHz 1MHz 850kHz 500kHz at LOMHz 1 25MHz 1 25MHz 500kHz Table 27 1 2 System Configuration of the Flash Microcontroller Program Yokogawa Digital Computer Co Ltd Product type Function AF220 ACAP Model with built in Ethernet interface 100V to 220V power adapter AF210 ACAP Standard model 100V to 220V power adapter Main unit AF120 AC4P Single key model with built in Ethernet interface 100 to 220V power adapter AF110 ACAP Single key model
196. 134JBW MB95F136MBW F136NBW F136JBW 0000 0000 0000 VO 00804 00804 00804 RAM 3 75K bytes RAM 1K byte RAM 01004 Registers 01904 Registers 01004 Registers 02000 77777 02004 7777 0200 7777 04804 Address 1 Access prohibited Access prohibited OF80 OF804 OF80 Extended I O Extended I O Extended I O 1000 1000 1000 Access prohibited Access prohibited Flash 60K bytes 80004 Address 2 ROM 32K bytes Flash memory FFFFY Flash Flash memory ROM Mask ROM CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 499 APPENDIX APPENDIX Memory Map MB95130 MB Series Flash memory Address 1 Address 2 MB95F133MBS F133NBS F133JBS MB95F133MBW F133NBW 8 Kbytes 256 bytes F133JBW MB95F134MBS F134NBS F134JBS MB95F134MBW F134NBW 16 Kbytes 512 bytes F134JBW MB95F136MBS F136NBS F136JBS MB95F136MBW F136NBW 32 Kbytes F136JBW 500 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series APPENDIX D Pin Status of MB95130 MB series APPENDIX APPENDIX D Pin Status of MB95130 MB series The state of the pin of the MB95130 MB series in each mode is shown in Table D 1 E Pin Status in Each Mode Table D 1 Pin Status in Each Mode 1 2 Pin name Normal operation Oscillation circuit input Sleep mode Oscillation circuit input Stop mode Watch mode SPL 0 Hi Z SPL 1 Hi Z SPL 0 Hi Z SPL 1 Hi Z While r
197. 2 Configuration of Watchdog Timer The watchdog timer consists of the following blocks Count clock selector e Watchdog timer counter e Reset control circuit e Watchdog timer clear selector Counter clear control circuit e Watchdog Timer Control Register WDTC E Block Diagram of Watchdog Timer Figure 11 2 1 Block Diagram of Watchdog Timer Watchdog timer control register WDTC CS1 50 WTE3SWTE2WTE1 WTEO Watchdog timer 221x 2 2x 2 Time base timer output B Count clock 214 2 Fc 218 2 FcL selector Clearing Watch prescaler output activated Reset Watchdog control Reset signal timer counter circuit Clear signal from time base timer Watchdog timer Overflow clear selector Clear signal from watch prescaler Sleep mode starts Stop mode starts Counter clear Time base timer control circuit watch mode starts Main clock Fo Sub clock CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 147 CHAPTER 11 WATCHDOG TIMER 11 2 Configuration of Watchdog Timer MB95130 MB Series Count clock selector This selector selects the count clock of the watchdog timer counter Watchdog timer counter This is a 1 bit counter that uses the output of either the time base timer or watch prescaler as the count clock Reset control circuit This circuit generates a reset signal when the watchdog timer counter overflows Watchdog timer clear selector
198. 26 10118 3E FUJITSU MICROELECTRONICS LIMITED 415 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART E LIN Slave Device MB95130 MB Series Figure 22 7 19 LIN Slave Flowchart Initial setting Set to operation mode 3 Enable serial data output 1 TIE 0 RXE 0 RIE 1 Connect LIN UART with 8 16 bit compound timer Disable reception Enable 8 16 bit compound timer interrupts Enable Synch break interrupts LBD 1 Synch break interrupts Clear Synch break detection ESCR LBD 0 Disable Synch break interrupts TIIO interrupt Read 8 16 bit compound timer data Clear 8 16 bit compound timer interrupt flag TIIO interrupt Read 8 16 bit compound timer data Adjust baud rate Enable reception Clear 8 16 bit compound timer interrupt flag Disable 8 16 bit compound timer interrupts RDRF 1 Reception interrupt Receive Identify field Reception yes Receive Data 1 RDRF 1 Reception interrupt Receive Data N Disable reception Wake up received Wake up transmitted Data Field Reception Reception interr pt no Transmission Set transmit data 1 TDR Data 1 Enable transmit interrupts 1 Transmit interrupt Set transmit data N TDR Data N Disable transmit interrup
199. 26 10118 3E FUJITSU MICROELECTRONICS LIMITED 519 APPENDIX APPENDIX F Mask Option MB95130 MB Series Low voltage Product Name Clock mode select detection reset Clock supervisor Reset output Single system MB95136MB Dual system MB95F133MBS MB95F133NBS MB95F133JBS MB95F134MBS MB95F134NBS Single system MB95F134JBS MB95F136MBS MB95F136NBS MB95F136JBS MB95F133MBW MB95F133NBW MB95F133JBW MB95F134MBW MB95F134NBW Dual system MB95F134JBW MB95F136MBW MB95F136NBW MB95F136JBW Single system MB95FV 100D 103 Dual system 520 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX G Writing to Flash Microcontroller Using Parallel Writer APPENDIX Writing to Flash Microcontroller Using Parallel Writer This section describes writing to flash microcontroller using parallel writer E Writing to Flash Microcontroller Using Parallel Writer Table G 1 Parallel Writer and Adaptor Package Conformable adaptor model Parallel writer FPT 28P M17 TEF110 95F136HSPF AF9708 Ver 02 43E higher AF9709 B Ver 02 43E higher FPT 30P M02 TEF110 95F136MB Inquiry Flash Support Group Inc Tel 8 1 53 428 8380 Q Sector configuration The following table shows sector specific addresses for
200. 3 n0 PDSOO register value The value changes depending on the 3 1 m1 01 register value PPGO1 output ch 1 waveform and the 4 1 x mo PDSO register value PENOO start timing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 257 CHAPTER 16 8 16 BIT PPG 16 7 Operating Description of 8 16 bit PPG MB951 30 MB Series 16 7 3 16 bit PPG Mode In this mode the unit can operate as a 16 bit PPG when PPG timer 01 and PPG timer 00 are assigned to the upper and lower bits respectively Setting 16 bit PPG Mode The unit requires the register settings shown in Figure 16 7 5 to operate in 16 bit PPG mode Figure 16 7 5 Setting 16 bit PPG Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bit PCO1 5 PIE1 PUF1 POEN1 CKS12 CKS11 CKS10 PCoo MD1 MDO PIEO PUFO POENO CKSO2 CKSO01 CKS00 0 0 1 PPSO1 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PHO Set PPG output cycle Upper 8 bits for PPG timer 01 PPSOO PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO Set PPG output cycle Lower 8 bits for PPG timer 00 PDSO1 DH7 DH6 DH5 DH4 DH3 DH2 DH1 N Set PPG output duty Upper 8 bits for PPG timer 01 PDSOO DL7 DL6 DL5 DL4 DL3 DL2 DL1 DLO Set PPG output duty Lower 8 bits for PPG timer 00 PPGS PENO1 PENOO
201. 3 Address 0007Cy 12 Address 0FFE2q ch 0 upper Interrupt level register ILR3 Address 0007Cy How to enable disable clear interrupts Interrupt request enable flag Interrupt request flag 13 Address 0FFEOy The interrupt request enable bit PCOO PIEO or PCO1 PIE1 is used to enable or disable interrupts When disabling interrupt requests Interrupt request enable bit PIEO or PIE1 Set the bit to 0 When enabling interrupt requests Set the bit to 1 The interrupt request flag PC00 PUFO or PCO1 PUF1 is used to clear interrupt requests Interrupt request flag PUFO or PUF1 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER This chapter describes the functions and operations of the 16 bit PPG timer 17 1 Overview of 16 bit PPG Timer 17 2 Configuration of 16 bit PPG Timer 17 3 Channels of 16 bit PPG Timer 17 4 Pins of 16 bit PPG Timer 17 5 Registers of 16 bit PPG Timer 17 6 Interrupts of 16 bit PPG Timer 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example 17 8 Notes on Using 16 bit PPG Timer 17 9 Sample Programs for 16 bit PPG Timer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 263 CHAPTER 17 16 BIT PPG TIMER 17 1 Overview of 16 bit PPG Timer MB95130 MB Series 17 1 Overview of 16 bit PPG Timer The 16 bit PPG timer can generate a PWM Pulse Width Modulation output or one shot square wave output and t
202. 3 SWT2 SWT1 SWTO it 1110 11015 11005 1011g 1010p 10015 10006 0111 0110p 0101p 0100p 0011 00105 0001p 0000p Number of Cycles 215 5 2142 213 2 2122 212 Sub Clock 32 768kHz 215 2 Foy About 1 05 214 2 Fce About 0 5 s 213 2 Fc About 0 25 s 212 2 About 0 125 s 211 2 Fe About 62 44 ms 219 2 IF About 31 19 ms 29 2 About 15 56 ms 28 2 Fa About 7 75 ms 27 2 Fey About 3 85 ms 26 2 About 1 89 ms 25 2 Fe About 9 15 545 24 2 About 4 27 245 23 2 About 183 1 us 22 2 Fe About 61 0 us 21 2 Fay 0 0 us 0 0 us 21 2 On single clock product the value of these bits is meaningless Number of cycles in the above table is for a minimum value Add 1 to the number of cycle in the above table for a maximum value Note Do not update these bits during sub clock oscillation stabilization wait time You should update them either with the sub clock oscillation stability bit in the system clock control register SYCC SRDY set to 1 or in sub clock mode or sub PLL clock mode You can also update them while the sub clock is stopped with the sub clock oscillation stop bit in the system clock control register SYCC SUBS set to 1 in main clock mode or main PLL clock mode FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 5 Oscillation Stabiliza
203. 3MBW F 1833NBW F 133JBW 8 Kbytes Flash memory CPU address Programmer address E000 1E0004 8 Kbytes FFFF 1FFFFY Programmer addresses are corresponding to CPU addresses used when the parallel programmer programs data into Flash memory These programmer addresses are used for the parallel programmer to program or erase data in Flash memory Programming method 1 Set the type code of the parallel programmer to 17237 2 Load program data to programmer addresses 1E000g to 1FFFFg 3 Write data with the parallel programmer 522 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E Index Numerics 16 bits Placement of 16 bit Data in Memory 43 16 bit PPG Cycle Setting Buffer Registers 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO 271 16 bit PPG Down Counter Registers 16 bit PPG Down Counter Registers Upper Lower PDCRLO 270 16 bit PPG Duty Setting Buffer Registers 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 272 16 bit PPG Mode Operation of 16 bit PPG Mode 259 Setting 16 bit PPG 258 16 bit PPG Status Control Register 16 bit PPG Status Control Register Lower PCNTEO npe eenaa a 275 16 bit PPG Status Control Register Upper eee ene repetere 273 16 bit PPG Timer 16 bit PPG 264 Block Di
204. 4 1 shows the block diagram of all MB95130 MB series E Block Diagram of All MB95130 MB Series Figure 1 4 1 Block Diagram of All MB95130 MB Series F 2MC 8FX CPU RST Reset control ROM X0 X1 RAM Clock control PG2 X1A een gt Interrupt control PG1 X0A XOA Watch counter Wild register Watch prescaler POO INTOO to PO7 INTO7 External interrupt P00 PPG00 bi s P01 PPG01 P10 UIO P11 UO0 ES UART SIO S PO2 SCK P12 UCKO LIN UART P03 SOT PO4 SIN P13 TRGO ADTG 16 bit 14 PO5 TOO0 15 16 8 16 bit PO6 TOO1 compound timer POO ANOO to PO7 ANO7 P12 ECO 8 10 bit AN GG ed A D converter PFO PF1 AVss Other pins 1 These pins are the oscillation terminals for general purpose port in single system clock product and MOD Vcc Vss the oscillation terminals for sub clock in dual clock product 2 5 V product is C terminal CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 9 CHAPTER 1 DESCRIPTION 1 5 Pin Assignment MB95130 MB Series 1 5 Pin Assignment Figure 1 5 1 and Figure 1 5 2 shows the pin assignment of the MB95130 MB series E Pin Assignment of MB95130 MB Series Figure 1 5 1 Pin Assignment of FPT 28P M17 TOP VIEW P16 1 P15 PFo 2 P14 PPGO PF1 P13 TRGO ADTG MOD _ 4 P12 UCKO ECO 5 P11 UOO x1 6 P10 UIO Vss
205. 6 bit PPG eese 252 Registers and Vector Table Related to Interrupts of External Interrupt Circuit 295 Table of Interrupt 498 TBTC Time base Timer Control Register TBTC 136 TDR LIN UART Reception Data Register RDR TDB ether 372 LIN UART Transmit Data Register TDR 373 UART SIO Serial Output Data Register FEDRO 326 Time counter data register Watch Counter Data Register WCDR 174 Time base timer Block Diagram of Time base Timer 133 Clearing Time base Timer 141 Notes on Using Time base Timer 143 Operating Examples of Time base Timer 141 Operations of Time base Timer 140 Register and Vector Table for Interrupts of Time base THE a aee 139 Registers of the Time base Timer 135 Time base timer control register Time base Timer Control Register TBTC 136 Time base timer mode Operations in Time base Timer Mode 77 Timer 00 Timer 00 Interrupt eee 217 Timer 01 Timer 01 Interrupt ee 217 Timing Reception Interrupt Generation and Flag Set Timing tede do ane a 383 Transmit Interrupt Generation and Flag Set Timing 385 Transmit Interrupt Request Generation Timi
206. 6 bit PPG Counter operation clock Available from eight selectable clock sources Watch counter Count clock Available from four selectable clock sources 125 ms 250 ms 500 ms or 1 s Counter value can be set within the range of 0 to 63 When one second is selected as for the clock source and the counter value is set to 60 it is possible to count for one minute Note At selecting the dual clock product Watch prescaler Available from four selectable interval times 125 ms 250 ms 500 ms 1 s Note At selecting the dual clock product External interrupt 8ch Interrupt by edge detection Select from rising edge falling edge or both edges Can be used to recover from standby modes Flash memory Supports automatic programming Embedded Algorithm Write Erase Erase Suspend Resume commands A flag indicating completion of the algorithm Number of write erase cycles 10000 times Data retention time 20 years Erase can be performed on each block Block protection with external programming voltage Flash Memory Security feature Standby Mode FUJITSU MICROELECTRONICS LIMITED Sleep stop watch Only for dual clock product and time base timer CM26 10118 3E CHAPTER 1 DESCRIPTION MB95130 MB Series 1 8 Difference Points among Products and Notes on Selecting a Product 1 3 Difference Points among Products and Notes on Selecting a Product The following describes differences among MB95130 MB series p
207. 7 P07 INTO7 ANO7 8 PO6 INTOG ANOG TOO1 cL 9 PO5 INTO5 ANO5 TOO0 PG2 X1A _ 10 P04 INT04 ANO4 SIN PG1 XOA _ 11 P03 INT03 AN03 SOT RST 12 PO2 INTO2 AN02 SCK AVcc _ 13 PO1 INTO1 ANO1 PPGO1 AVss 14 PO0 INTOO ANOO PPGOO FPT 28P M17 General purpose port for the single clock product and oscillation pin for sub clock for the dual clock product 10 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 1 DESCRIPTION MB95130 MB Series 1 5 Pin Assignment Figure 1 5 2 Pin Assignment of FPT 30P M02 TOP VIEW Piel 1 P15 2 14 PF1 3 P13 TRGO ADTG MOD 4 P12 UCKO ECO xo 5 NC 6 P11 UO0 55 7 P10 UIO vec 8 PO7 INTO7 ANO7 cl PO6 INTOG ANO6 TOO1 PG2 X1A PO05 INTO5 ANO5 TOOO PG1 XOA PO4 INTO4 ANOA SIN RST E NC AVcc PO3 INTO3 ANO3 SOT AVss C PO2 INTO2 ANO2 SCK POO INTOO ANOO PPGOO P0O1 INTO1 ANO1 PPGO01 FP T 30P M02 General purpose port for the single clock product and oscillation pin for sub clock for the dual clock product CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 11 CHAPTER 1 DESCRIPTION 1 6 Package Dimension 1 6 Package Dimension MB95130 MB Series MB95130 MB series is available in 2 types of package E Package Dimension of FPT 28P M17 Figure 1 6 1 Package Dimension of FPT 28P M17 28 pin plastic SOP Lead pitch 1 27 mm Package width x 8 6x 17 75 mm package leng
208. 8 16 bit Compound TIGER ree degens 204 Register Bank Pointer Configuration of Register Bank Pointer RP 36 Register Bank Pointer Direct Bank Pointer Mirror Address 36 Reload Counter Function of Reload Counter 393 Operation of Dedicated Baud Rate Generator Reload aru 392 Reload value Reload Value and Baud Rate of Each Clock Speed 390 Reset Block Diagram of Low voltage Detection Reset Circuit Em 449 Effect of Reset on RAM Contents 88 Low voltage Detection Reset Circuit 448 Notes on Using Reset eseeeeeeeeeeeess 93 Overview of Reset Operation 88 Pin State During a 89 Placing Flash Memory in the Read Reset State 477 Reset output nempe 87 Reset 86 Reset iiie iei 87 Reset cause register Configuration of Reset Source Register RSRR 90 Status of Reset Source Register RSRR 92 REVC 8 16 bit PPG Output Inversion Register RP Configuration of Register Bank Pointer RP 36 RSRR Configuration of Reset Source Register RSRR 90 Status of Reset Source Register RSRR 92 S Sample Sample Programs for 16 bit PPG Timer 283 Sample Programs
209. 82 6 12 Operating Explanation of Prescaler ssssssssssssssssseseeeee eene nnne nennen snnt nennen 83 6 13 Notes on Use of Prescaler 84 CHAPTER 7 RESET siccitas cedo aa anc Ga Fa ka ip een dE RE EE 85 7 1 Reset Operati EUER EE 86 7 2 Reset Source Register RSRR sssssssssssssssessseess nsns 90 7 3 INotes on Using Resets ie eter ed Pet eie ete RE ei eph erred eee 93 CHAPTER S INTERRUPTS irren antiena naaa np 28S eoa cue Fe cH 95 8 1 Interr pts dun Lee e io e te a EH es 96 8 1 1 Interrupt Level Setting Registers ILRO to 98 8 1 2 Interrupt Processing Steps ssssssssssssssssssseseeee nennen nnne entes intrent nennen 99 8 1 3 Nested Interrupts 22 tetur UM ERR M Ere RE REPE CARE CHEER REM EROR MR eta Run 102 8 1 4 Interrupt Processing TiImoe ene ere e ehe at eh ehe ete s 103 8 1 5 Stack Operations During Interrupt Processing sse 104 8 1 6 Interrupt Processing Stack Area 2 105 9 J O PORT e verona dnx Fe aux ous ver occa daa 107 9 1 Overview Of I O Ports si scii oc eiecti tp te eo ret tdt T 108 9 2 ETE 109 9 2 1 Port O Registers EE 112 9 2 2 Opera
210. ASE TIMER 10 5 Explanation of Time base Timer Operations and Setup Procedure Example MB95130 MB Series Figure 10 5 2 Operations of Time base Timer Counter value count down SFFFFF Count value detected in WATR MWTS MWT2 MWT1 MWTO Count value detected in TBTC TBC1 0 le Interval cycle TBTC TBC1 TBC0 1 18 D H iClear by transferring ito stop mode 000000 Oscillation 4 Counter cl i Oscillation stabilization wait time OUrter C Gar ilizati it ti 1 TBTC TCLR 1 stabilization wait time 1 Power on reset Clear at interval Clear in interrupt setup processing routine 1 Y iv TBIF bit ET TBIE bit Sleep 2 SLP bit STBC register Sleep cancelled by timebase lt gt i timer interrupt TIRQ 3 STP bit STBC register i Stop cancelled by external interrupt When setting 11 to interval time select bits of time base timer control register TBTC TBC1 TBCO 2 x 2 TBTC TBC1 TBCO Interval time select bits of time base timer control register TBTC TCLR Time base timer initialization bit of time base timer control register TBTC TBIF Time base timer interrupt request flag bit of time base timer control register TBTC TBIE Time base timer interrupt request enable bit of time base timer control register STBC SLP Sleep bit of standby cont
211. BIT COMPOUND TIMER 15 12 Operating Description of PWC Timer Function MB951 30 MB Series When the timer stops operation the timer output bit TMCRO TO1 TOO holds the last value The value of the 8 16 bit compound timer 00 01 data register TOODR TOIDR must be nullified if an interrupt occurs before the timer is activated before 1 is written to the STA bit Figure 15 12 2 Operating Diagram of PWC Timer Example of H pulse Width Measurement width Pulse input Input waveform to PWC pin Counter value rp Time X 9 STA bit Counter f Cleared by program operation 4 d L BF bit 8 8_ _ Data transferred from counter to TOODR TO1DR TOODR TO1DR data register read 230 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 13 Operating Description of Input Capture Function 15 13 Operating Description of Input Capture Function This section describes the operations of the input capture function for the 8 16 bit compound timer E Operation of Input Capture Function The compound timer requires the settings shown in Figure 15 13 1 to serve as the input capture function Figure 15 13 1 Settings for Input Capture Function bit7 bit6 bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO TOOCR1 T01CR1 STA HO IE IR BF IF S
212. CLK 10 x 10 b 19193 8579 1 521 Note The reload counter halts if the reload value is set to 0 Therefore the least reload value should be 1 For transmission reception in asynchronous mode the reload value must be at least 4 in order to determine the reception value by oversampling on five times CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 389 CHAPTER 22 LIN UART 22 6 LIN UART Baud Rate MB95130 MB Series E Reload Value and Baud Rate of Each Clock Speed Table 22 6 1 shows the reload value and baud rate Table 22 6 1 Reload Value and Baud Rate 8MHz MCLK 10MHz MCLK 16MHz MCLK 16 25MHz MCLK Baud rate bps Reload Frequency Reload Frequency Reload Frequency Reload Frequency value deviation value deviation value deviation value deviation 2M 4 0 7 0 1M 7 0 9 0 15 0 500000 15 0 19 0 31 0 400800 z z 250000 31 0 39 0 63 0 64 0 230400 68 0 64 153600 51 0 16 64 0 16 103 0 16 105 0 19 125000 63 0 79 0 127 0 129 0 115200 68 0 64 86 0 22 138 0 08 140 0 04 76800 103 0 16 129 0 16 207 0 16 211 0 19 57600 138 0 08 173 0 22 277 0 08 281 0 04 38400 207 0 16 259 0 16 416 0 08 422 0 04 28800 277 0 08 346 0 06 555 0 08 563 0 04 19200 416 0 08 520 0 03 832 0 04 845 0 04 10417 767 lt 0 01 959 lt 0 01 1535 lt 0 01 1559 lt 0 01 9600 832 0 04 1041 0 03
213. CM26 10118 3E CHAPTER 13 WATCH COUNTER MB95130 MB Series 13 3 2 Watch Counter Control Register WCSR 13 3 Registers of Watch Counter The watch counter control register WCSR is used to control the operation and interrupts of the watch counter It can also read the count value Bi Watch Counter Control Register WCSR Figure 13 3 2 1 Watch Counter Control Register WCSR bit bit6 bits bit4 bits bit2 biti bitO Address Initial value 0070 ISEL WCFLG CTR5 CTR2 CTR1 000000008 R WrRRM1 wW R WX R WX R WX R WX Counter read bit CTR5 to CTRO These bits can read the counter value Interrupt request flag bit Write Read Clears this bit No change no effect on operation No interrupt request generated An interrupt request generated Watch counter start amp interrupt enable bit 0 Stops watch counter and disables interrupt request of watch counter Enables interrupt request of watch prescaler 1 Activates watch counter and enables interrupt request of watch counter Disables interrupt request of watch prescaler R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction R WX Read only Readable writing has no effect on operation Initial value
214. CROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 7 Explanation of UART SIO Operations and Setup Procedure Example 20 7 4 Operating Description of Operation Mode 0 Operation mode 0 operates as clock asynchronous mode UART E Operating Description of UART SIO Operation Mode 0 Clock asynchronous mode UART is selected when the MD bit in the UART SIO serial mode control register 1 SMCIO is set to 0 Baud rate The serial clock is selected by the CKS bit in the SMC1O register Be sure to select the dedicated baud rate generator at this time The baud rate is equivalent to the output clock frequency of the dedicated baud rate generator divided by four The UART can perform communication within the range from 2 to 2 of the selected baud rate The baud rate generated by the dedicated baud rate generator is obtained from the equation ilustrated below For information about the dedicated baud rate generator refer to CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR Figure 20 7 1 Baud Rate Calculation when Using Dedicated Baud Rate Generator Machine clock MCLK Baud rate bps 1 2 4x 2 4 255 8 UART baud rate setting register BRSRO UART prescaler selection register PSSRO Baud rate setting Prescaler selection BRS7 to BRSO PSS1 PSSO Table 20 7 2 Sample Asynchronous Transfer Rates Based on Dedicated Baud Rate Generator
215. CROELECTRONICS LIMITED 195 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 1 Overview of 8 16 bit Compound Timer MB951 30 MB Series 15 1 Overview of 8 16 bit Compound Timer The 8 16 bit compound timer consists of two 8 bit counters and can be used as two 8 bit timers or one 16 bit timer if they are connected in cascade The 8 16 bit compound timer has the following functions Interval timer function PWM timer function PWC timer function pulse width measurement Input capture function E Interval Timer Function One shot Mode When the interval timer function one shot mode is selected the counter starts counting from 00g as the timer is started When the counter value matches the register setting value the timer output is inverted the interrupt request occurs and the count operation is stopped E Interval Timer Function Continuous Mode When the interval timer function continuous mode is selected the counter starts counting from 00g as the timer is started When the counter value matches the register setting value the timer output is inverted the interrupt request occurs and the count operation is continued from 00g again The timer output a square wave as a result of this repeated operation E Interval Timer Function Free run Mode When the interval timer function free run mode is selected the counter starts counting from 00g When the counter value matches the register setting value the tim
216. D conversion completed with no interrupt request A D conversion completed with interrupt request The value read is 1 generated Checking with the conversion flag bit ADCI ADMV Conversion flag bit ADMV Setting The value read is 0 A D conversion completed suspended The value read is 1 A D conversion in progress Interrupt related register Use the following interrupt level setting register to set the interrupt level Interrupt source source Interrupt level setting register Interrupt level setting register setting register o Interrupt vector o Interrupt vector 8 10 bit Interrupt level register ILR4 18 A D converter Address 0007Dg Address OFFD6g Enabling disabling and clearing interrupts To enable interrupts use the interrupt request enable bit ADC2 ADIE Control item Interrupt request enable bit ADIE To disable interrupt requests Set the bit to 0 To enable interrupt requests Set the bit to 1 To clear interrupt requests use the interrupt request bit ADC1 ADI Control item Interrupt request bit ADI To clear an interrupt request SET the Dit pt req Or activate A D 446 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 24 LOW VOL TAGE DETECTION RESET CIRCUIT This chapter describes the functions and operations of the low voltage detection reset circuit 24 1 Overview of Low voltage Detection Reset Circuit 24 2 C
217. DCK External start signal select bit ADCK Input clock To select the ADTG input pin Set the bit to 0 To select the 8 16 bit compound timer TOO0 Set the bit to 1 Q Selecting the A D conversion precision To select the precision of conversion results use the precision select bit ADC2 ADS Operation mode Precision select bit AD8 To select 10 bit precision Set the bit to 0 To select 8 bit precision Set the bit to 1 Using analog input pins To select an analog input pin use the analog input channel select bits ADC1 ANS3 to ANSO Operation Analog input channel select bits ANS3 to ANSO To use the ANOO pin Set the pins to 00005 To use the ANOI pin Set the pins to 00015 To use the ANO2 pin Set the pins to 0010 To use the ANO3 pin Set the pins to 0011 To use the AN04 pin Set the pins to 0100 To use the ANOS pin Set the pins to 01015 To use the ANO6 pin Set the pins to 01105 To use the ANO7 pin Set the pins to 01115 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 445 CHAPTER 23 8 10 BIT A D CONVERTER 23 8 Sample Programs for 8 10 bit A D Converter MB951 30 MB Series Checking the completion of conversion The following two methods can be used to check whether conversion has been completed Checking with the interrupt request flag bit ADCI ADI Interrupt request flag bit ADI Meaning The value read is 0 A
218. Diagram of 16 bit PPG Timer When upper 8 bits of setting register are written but lower 8 bits are not 7 ioe he value is 4 16 bit PPG cycle 16 bit PPG cycle written the value is 1 setting buffer register setting buffer register 16 bit PPG duty 16 bit PPG duty otherwise it is 0 1 upper 8 bits lower 8 bits setting buffer register setting buffer register PEE goes m munem oe eee upper 8 bits lower 8 bits Y 16 EN it 16 bit t uty DI 16 bit PPG cycle setting buffer register setting buffer register ckse T CKSO DEBE DI roster for upper 8 bits buffer for lower 8 bits buffer 0 ET MCLK 1 MCLK 2 Y Y Comparator MCLK 4 circuit MCLK 8 LORD Prescaler MCLK 16 16 bit MCLK 32 down counter 27 LL MDSE PGMS OSEL POEN 2 28 gt STOP p START BORROW Ls POEN S E Mz Pin D E E 2 m PPGO 8 21 5 3 8 4 4 n n 5 Interrupt Interrupt selection of 16 bit PPG Edge detection IRS1 1850 IRQF IREN alle 7 n Pin TRGO 981 ecso stra RrRG
219. E FUJITSU MICROELECTRONICS LIMITED 391 CHAPTER 22 LIN UART 22 6 LIN UART Baud Rate MB95130 MB Series E Operation of Dedicated Baud Rate Generator Reload Counter Figure 22 6 2 shows the operation of dedicated baud rate generator reload counter Figure 22 6 2 Operation of Dedicated Baud Rate Generator Reload Counter Transmit reception clock Falling at V 1 2 Reload counter oo2 oot 831 829 828 Jat are ais Jana ero par X LA Reload counter value Note The falling edge of the serial clock signal is generated after the reload value divided by 2 v 1 2 is counted 392 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 6 LIN UART Baud Rate 22 6 2 Reload Counter This block is a 15 bit reload counter serving as a dedicated baud rate generator It generates the transmit reception clock from the external or internal clock The count value in the transmit reload counter is read from the LIN UART baud rate generator registers 1 0 BGR1 BGRO E Function of Reload Counter There are two kinds of reload counters transmit and reception They work as the dedicated baud rate generator The block consists of a 15 bit register for reload values it generates the transmit reception clock from the external or internal clock The count value in the transmit reload counter is read from the LIN UART baud rate generator registers 1 0
220. E of PCNTH Register Dit O Rm 278 Memory Memory Map tm te t eee taedet 499 Placement of 16 bit Data in Memory 43 Memory Map Memory Map seen 27 29 499 Memory Space Configuration of Memory 26 Mirror Address Register Bank Pointer Direct Bank Pointer Mirror Address 36 Mode 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 211 An Interrupt Request may Suppress Transition to Standby Mode 71 Asynchronous LIN Mode Operation 405 Asynchronous Mode Operation 397 Check That Clock mode Transition has been Completed before Setting Standby Mode 71 clock mode eiiis ee tnn 49 Clock Mode State Transition Diagram 66 Combinations of Clock Mode and Standby Mode 51 Interval Timer Function Continuous Mode 196 Interval Timer Function Free run Mode 196 Interval Timer Function One shot Mode 196 One shot Mode MDSE of PCNTHO Register bit S ae dees 280 Operating Description of UART SIO Operation Mode Dre dus dedo 329 Operating Description of UART SIO Operation Mode edere qi d divin eae 336 Operation at the Main Clock Stop Mode 179 Operation in Sub Clock Stop Mode 179 Operation of 16 b
221. Even when the next edge is detected with this bit containing 1 the count value is not transferred to the 8 16 bit compound timer 00 01 data register TOODR TO1DR and thus the next measurement result is lost However as the exception when the H pulse and cycle measurement TOOCRO TO1CRO F2 F1 FO 1001 is selected the H pulse measurement result is transferred to the 8 16 bit compound timer 00 01 data register TOODR TO1DR with this bit set to 1 The cycle measurement result is not transferred to the 8 16 bit compound timer 00 01 data register with the bit set to 1 For cycle measurement therefore the H pulse measurement result must be read before the cycle is completed Note also that the result of H pulse measurement or cycle measurement is lost unless read before the completion of the next pulse The BF bit in the TOOCRI timer 00 register is set to 0 when the TOIDR timer 01 register is read during 16 bit operation The BF bit in TOICRI timer 01 register is set to 0 during 16 bit operation This bit is 0 when any timer function other than the PWC timer function has been selected Writing to this bit has no effects on the operation BF Data register full flag This bit detects a match with a count value or a counter overflow The bit is set to 1 when the 8 16 bit compound timer 00 01 data register TOODR T01DR value matches the count value during interval timer function both one shot and
222. External Interrupt Circuit 296 Overview of Interrupts 96 Pins Related to External Interrupt Circuit 291 Reception interrupt eeeeeesesee 327 379 Reception Interrupt Generation and Flag Set Timing 383 Register and Vector Table for Interrupts of Time base a c EE 139 Register and Vector Table Related to 8 10 bit A D Converter Interrupts 439 Register and Vector Table Related to Interrupts of Watch Counter 177 Register and Vector Table Related to Interrupts of Watch 163 Register and Vector Table Related to LIN UART Interr pt eee et 382 Registers and Vector Table Related to Interrupts of 16 bit PPG Timer sess 277 Registers and Vector Table Related to Interrupts of 8 16 bit PPG eee 252 Registers and Vector Table Related to Interrupts of External Interrupt Circuit 295 Registers and Vector Table Related to UART SIO Initerr pts nente tnit 327 Registers and Vector Tables Related to Interrupts of 8 16 bit Compound Timer 218 Sample Programs for External Interrupt C oos ces ee a 299 Stack Operation at Start of Interrupt Processing 104 Stack Operation upon Returning from Interrupt 104 Standby Mode is Also Canceled when the CPU Rejects Interrupts
223. FE10 FEO1 FEOO TOODR TO1DR Sets interval time counter compare value O Used bit x Unused bit 1 Set 1 0 Set 0 In interval timer function continuous mode enabling timer operation TOOCRO TOOCRI STA 1 causes the counter to start counting from 00g at the rising edge of a selected count clock signal When the counter value matches the value in the 8 16 bit compound timer 00 01 data register TOODR TOIDR the timer output bit TMCRO TOO TOI is inverted the interrupt flag TOOCR1 TO1CR1 IF is set to 1 and the counter continues to count by restarting at 00g The timer outputs a square wave as a result of this continuous operation The value of the 8 16 bit compound timer 00 01 data register TOODR TOIDR is transferred to the temporary storage latch comparison data storage latch in the comparator either when the counter starts counting or when a counter value comparison match is detected Writing 00g to the 8 16 bit compound timer 00 01 data register is disabled during the count operation When the timer stops operation the timer output bit TMCRO TOO TO1 holds the last value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 221 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 8 Operating Description of Interval Timer Function Continuous Mode MB951 30 MB Series Figure 15 8 2 Operating Diagram of Interval Timer Function Continuous Mode Compare value Compare value Compare value 1 EO
224. FF This area contains the auxiliary registers used for 8 bit arithmetic or transfer operations Asthe area is allocated as part of the RAM area it can also be used as ordinary RAM When the area is used as general purpose registers general purpose register addressing enables higher speed access using short instructions For details see Section 5 1 1 Register Bank Pointer RP and Section 5 2 General purpose Registers E Vector Table Area Addresses FFCO to FFFF e This area is used as the vector table for vector call instructions CALL V interrupts and resets The vector table area is allocated at the top of the ROM area At the individual addresses in the vector table the start addresses of their respective service routines are set as data Table 8 1 1 lists the vector table addresses to be referenced for vector call instructions interrupts and for resets For details see CHAPTER 8 INTERRUPTS CHAPTER 7 RESET and BiSpecial Instruction 6CALLV vct in Appendix E 2 Special Instruction 28 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series 3 2 Memory Map CHAPTER 3 MEMORY SPACE 3 2 Memory Map This section gives a memory map of this series E Memory Map Figure 3 2 1 Memory map MB95F133MBS F133NBS F133JBS MB95F134MBS F134NBS F134JBS MB95FV100D 101 MB95136MB MB95F136MBS F136NBS F136JBS MB95FV10
225. FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM26 10118 3E F MC 8FX 8 BIT MICROCONTROLLER MB95130 MB Series HARDWARE MANUAL FUJITSU F MC 8FX 8 BIT MICROCONTROLLER MB95130 MB Series HARDWARE MANUAL For the information for microcontroller supports see the following web site This web site includes the Customer Design Review Supplement which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development http edevice fujitsu com micom en support FUJITSU MICROELECTRONICS LIMITED PREFACE E The Purpose and Intended Readership of This Manual Thank you very much for your continued special support for Fujitsu semiconductor products The MB95130 MB series is a line of products developed as general purpose products in the F MC 8FX family of proprietary 8 bit single chip microcontrollers applicable as application specific integrated circuits ASICs The MB95130 MB series can be used for a wide range of applications from consumer products including portable devices to industrial equipment Intended for engineers who actually develop products using the MB95130 MB series of microcontrollers this manual describes its functions features and operations You should read through the manual For details on individual instructions refer to the FMC 8FX Programming Manual Note F MC is the abbreviation of FUJITSU Flexible Microco
226. Figure 22 7 16 Settings of LIN UART Operation Mode 3 LIN biti5 bit14 bit13 bit12 bitl1 bit1O bit9 bits bit7 bit6 bits bit4 bits bit2 biti bitO SCR SMR PEN SBL CL AD CRE RXE MD1 EXT REST UPCL SCKE SOE Mode 3 x x 0 1 1 0 0 0 SSR Set conversion data during writing RDR TDR PE EISE PRE ela BDS RIE CTIE Retain reception data during reading Mode 3 gt X ESCR ECCR LBIE LBD LBL1 LBLO SOPE SIOP CCO SCES BR LBR MS SCDE SSM Ed RBI TBI Mode3J 5 0 O0 0 Go X X X 0 Used bit Unused bit Set to 1 Set to 0 Bit correctly set automatically OoO xX LIN device connection Figure 22 7 17 shows an example of the LIN bus system communication The LIN UART can serve as the LIN master or LIN slave Figure 22 7 17 Example of LIN Bus System Communication LIN master Transceiver Transceiver LIN slave 414 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART 22 7 8 Example of LIN UART LIN Communication Flowchart Operation Mode 3 This section shows examples of LIN UART LIN communication flowchart BB LIN Master Device Figure 22 7 18 LIN Master Flowcha
227. Figure E 1 10 Example of Inherent Addressing NOP Old PC 9ABCH New PC 9A B DH CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 509 APPENDIX APPENDIX E Instruction Overview MB951 30 MB Series E 2 Special Instruction This section explains special instructions other than the addressings E Special Instruction JMP 9A This instruction is to branch the content of A accumulator to PC program counter as an address N pieces of the jump destination is arranged on the table and one of the contents is selected and transferred to A N branch processing can be done by executing this instruction Figure E 2 1 shows a summary of the instruction Figure E 2 1 JMP A Before executing After executing A 123 4H N 1234 Old PC X X X XH gt New PC 123 4 MOVW A PC This instruction works as the opposite of JMP A That is it stores the content of PC to A When you have executed this instruction in the main routine and set it to call a specific subroutine you can make sure that the content of A is the specified value in the subroutine Also you can identify that the branch is not from the part that cannot be expected and use it for the reckless driving judgment Figure E 2 2 shows a summary of the instruction Figure E 2 2 MOVW A PC Before executing After executin
228. Generation and Flag Set Timing ssssssseen 383 22 5 2 Transmit Interrupt Generation and Flag Set Timing sse 385 22 6 EINE ART B atid Rale eee esee coat d ee i EN esie 387 22 6 1 Baud Rate Seting e mairinas nenti el eae cu ee qi ee eo ie 389 22 6 2 Reload Counter be etie eee Wet atit eR d debate 393 22 7 Operations and Setup Procedure Example of LIN UART 395 22 7 1 Operation of Asynchronous Mode Operation Mode 0 1 397 22 7 2 Operation of Synchronous Mode Operation Mode 2 401 22 7 8 Operation of LIN function Operation Mode 3 405 22 7 4 Serial Pin Direct ACCESS e ne eet ee e tases 408 22 7 5 Bi directional Communication Function Normal Mode sse 409 22 7 6 Master slave Mode Communication Function Multi processor Mode 411 22 7 7 LIN Communication Function nnn sitne nnn nnne en 414 22 7 8 Example of LIN UART LIN Communication Flowchart Operation Mode 3 415 22 8 Notes on Using LIN UART AN A EA EEEE AER 417 22 9 Sample Programs of LIN UART sss nennen nnns 422 C
229. H FFH Compare value 80H 00H 1 TOODR TO1DR value modified FFH 80H 1 1 Time 1 Cleared by program TOODR TO1DR value 0 IF bi bit r r i i 1 1 1 1 STA bit 1Activated Matched 1Matched 1 Matched Matched Matched 1 Counter clear 2 LL ff n dL iL 1 Timer output pin _ LLL L L 1 1 If the TOODR TO1DR data register value is modified during operation the new value is used from the next active cycle 2 The counter is cleared and the data register settings are loaded into the comparison data latch when a match is detected at each point during activation 222 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 9 Operating Description of Interval Timer Function Free run Mode 15 9 Operating Description of Interval Timer Function Free run Mode This section describes the operation of the interval timer function free run mode for the 8 16 bit compound timer E Operation of Interval Timer Function Free run Mode The compound timer requires the settings shown in Figure 15 9 1 to serve as the interval timer function free run mode Figure 15 9 1 Settings for Interval Timer Function Free run Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO 0 0 1 0 TOOCR1 T01CR1 STA HO IE IR BF IF SO OE 1
230. HAPTER 23 8 10 BIT A D CONVERTER nnn nnn nnn nnn nnn 427 23 1 Overview of 8 10 bit A D Converter sssssssssssssessseeeeee eene enne 428 23 2 Configuration of 8 10 bit A D Converter 429 23 3 Pins of 8 10 bit A D Converter innin i nennen entrent 431 23 4 Registers of 8 10 bit A D Converter ssssssssssssssssseeee eene nnne inse nennen 433 23 4 1 8 10 bit A D Converter Control Register 1 ADC1 ssssssssssseeeeneeeeenen nenne 434 23 4 2 8 10 bit A D Converter Control Register 2 ADC2 436 23 4 3 8 10 A D Converter Data Registers Upper Lower ADDL 438 23 5 Interrupts of 8 10 bit A D Converter eene nennen intrent nnne nennen 439 23 6 Operations of 8 10 bit A D Converter and Its Setup Procedure Examples 440 23 7 Notes on Use of 8 10 bit A D Converter ssssssssssssseseseee eene enne nennen entree 443 23 8 Sample Programs for 8 10 bit A D Converter sssssssssssssssee eene eene nennen nennen 444 CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT 447 24 1 Overview of Low voltage Detection Reset Circuit
231. I TO1CR1 208 8 16 bit Compound Timer 00 01 Data Register 214 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCR0O 211 Block Diagram of 8 16 bit Compound Timer 199 Block Diagram of Pins Related to 8 16 bit Compound ybi ERR 203 Channels of 8 16 bit Compound Timer 201 Notes on Using 8 16 bit Compound 236 Pins Related to 8 16 bit Compound Timer 202 Registers and Vector Tables Related to Interrupts of 8 16 bit Compound Timer 218 Registers Related to 8 16 bit Compound ybi EROR 204 Compound Timer Interrupt LIN Synch Field Edge Detection Interrupt 8 16 bit Compound Timer Interrupt 381 Condition Code Register Condition Code Register CCR Configuration sese 39 Configuration Configuration of Direct Bank Pointer DP 37 Port 0 Configuration 109 Port 1 Configuration 115 Port F 120 Port G Configuration ess 125 Register Bank Pointer Direct Bank Pointer Mirror Address 36 Continuous Mode Interval Timer Function Continuous Mode 196 Operation of Interval Timer Function Continuous Mode 221 Counter 16 bit PPG Down Counter R
232. ICS LIMITED CM26 10118 3E MB95130 MB Series 22 4 Registers of LIN UART CHAPTER 22 LIN UART 22 4 Registers of LIN UART This section lists the registers of LIN UART E Register List of LIN UART Figure 22 4 1 Register List of LIN UART LIN UART serial control register SCR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito 00504 PEN P SBL CL AD CRE RXE TXE R W HW RW HW HW ROW HW RW LIN UART serial mode register SMR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito 00514 MD1 MDO EXT REST UPCL SCKE SOE R W HW HW HW ROW ROW HW RW LIN UART serial status register SSR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit 00524 PE ORE FRE RDRF TDRE BDS RIE TIE H WX R WX RWX RWX RWX RW HW RW LIN UART reception data register LIN UART transmit data register RDR TDR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit 0053 D7 D6 D5 D4 D3 D2 D1 DO R W HW RW HW HW HW HW RW LIN UART extended status control register ESCR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito 00544 LBIE LBD LBL1 LBLO SOPE SIOP CCO SCES R W R W R W R W R W R W LIN UART extended communication control register ECCR Address bit7 bit6 bit5 bit4 bit3 bit2 bit b
233. ITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 11 WATCHDOG TIMER MB951 30 MB Series 11 4 Explanation of Watchdog Timer Operations and Setup Procedure Example Interval time The interval time varies depending on the timing for clearing the watchdog timer Figure 11 4 1 shows the correlation between the clearing timing of the watchdog timer and the interval time Figure 11 4 1 Clearing Timing and Interval Time of Watchdog Timer Main clock 4MHz WDTC CS1 CS0z00g Minimum time 524ms Time base timer l count clock output Watchdog clear Overflow Watchdog 1 bit counter Watchdog reset Maximum time k 1 05s gt Time base timer l count clock output i Watchdog clear Overflow Watchdog 1 bit counter _ Ti T Watchdog reset l Operation in the sub clock mode When a watchdog reset is generated in the sub clock mode the timer starts operating in the main clock mode after the oscillation stabilization wait time has elapsed The reset signal is outputted during this oscillation stabilization wait time E Setup Procedure Example The watchdog timer is set up in the following procedure 1 Select the count clock WDTC CS1 CS0 2 Activate the watchdog timer WDTC WTE3 to WTEO 0101 3 Clear the watchdog timer WDTC WTE3 to WTEO 0101p CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 153 CHAPTER 11 WATCHDOG TIMER 11 5 Notes on Using Watchdog Timer MB95130 MB Serie
234. ITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER This chapter describes the functions and operations of the watch prescaler 12 1 Overview of Watch Prescaler 12 2 Configuration of Watch Prescaler 12 3 Registers of the Watch Prescaler 12 4 Interrupts of Watch Prescaler 12 5 Explanation of Watch Prescaler Operations and Setup Procedure Example 12 6 Notes on Using Watch Prescaler 12 7 Sample Programs for Watch Prescaler Code CM26 00107 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 155 CHAPTER 12 WATCH PRESCALER 12 1 Overview of Watch Prescaler MB95130 MB Series 12 1 Overview of Watch Prescaler The watch prescaler is a 15 bit down counting free run counter which is synchronized with the sub clock divided by two It has an interval timer function that continuously generates interrupt requests at regular intervals Bi Interval Timer Function The interval timer function continuously generates interrupt requests at regular intervals using the sub clock divided by two as its count clock The counter of the watch prescaler counts down and an interrupt request is generated every time the selected interval time has elapsed The interval time can be selected from the following four types Table 12 1 1 shows the interval times of the watch prescaler Table 12 1 1 Interval Times of Watch Prescaler Internal count clock cycle Interval time 21 X 2 Fc 125ms 212 X 2 Fc
235. Interrupts Table 20 6 2 Registers and Vector Table Related to UART SIO Interrupts Interrupt Interrupt level setting Vector table address request register Interrupt source number Registers Setting bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 327 CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure Example Procedure Example MB95130 MB Series 20 7 Explanation of UART SIO Operations and Setup The UART SIO has a serial communication function operation modes 0 1 E Operation of UART SIO Operation mode Two operation modes are available in the UART SIO Clock synchronous mode SIO or clock asynchronous mode UART can be selected see Table 20 7 1 Table 20 7 1 Operation Modes of UART SIO Operation Data length mode No parity With parity Synchronous Mode Asynchronous Stop bit length 1 bit or 2 bits E Setup Procedure Example The UART SIO is set up in the following procedure Initial setting 1 Set the port for input DDR1 2 Set the interrupt level ILR1 3 Set the prescaler PSSRO 4 Set the baud rate BRSRO 5 Select the clock SMC10 CKS 6 Set the operation mode SMC10 MD 7 Enable disable the serial clock output SMC20 SCKE 8 Enable reception SMC20 RXE 1 9 Enable interrupts SMC20 RIE 1 Interrupt processing Read receive data RDRO Synchronous 328 FUJITSU MI
236. K CONTROLLER inihi noa in arra nani tuc nnne 45 6 1 Overview of Clock Controller sss enne enne nennen nennen 46 6 2 Oscillation Stabilization Wait Time esssessssssesesseseseeee entente enn snnt nensi nnns 52 6 3 System Clock Control Register SYCO 54 6 4 PLLE Gontrol Register PELC 56 6 5 Oscillation Stabilization Wait Time Setting Register WATR sss 59 6 6 Standby Control Register nnne eese ns 62 6 7 Glock MOde tmo bs tn a eatis e 65 6 8 Operations in Low power Consumption Modes Standby Modes 70 6 8 1 Notes on Using Standby Mode sssssssssssssssssseseeeee eene nnne nnns enne nnn nennen 71 6 8 2 Sleep MOodG ic 55 eL SD LR SS I USER UG LO Sus 75 6 8 3 Stop Mode ne Rp e o HER de EOD ie 76 6 8 4 Time base Timer MOdGe 5 rcr ette SEE HL i rU Ede Edere ede See ety 77 6 8 5 WatclrMode a a ete i e tet bei ote es ilte Cost eee tee 78 6 9 Clock Oscillator Circuits enne a 79 6 10 Overview of Prescaler irruere beate erbe sire Ee a epe ib t 81 6 11 Configuration of Prescaler ssssssssssssssssseeeeenne ene neeen nensis ss nnne rennes
237. L level and blocked in order to prevent leaks due to freed input Ifthe pin state specification bit is 0 the state remains in port I O and the output is maintained Operation of the pull up control register Setting 1 to the PUL register connects the pull up resistor to the pin However when the general purpose I O port or shared peripheral resource outputs L level the pull up resistor is disconnected regardless of the PUL register value Operation of the input level selection register 2 The ILSR2 register is a valid register only for 5V models Setting bit6 of the ILSR2 register to 1 changes the port G input level from the hysteresis input level to the automotive input level The hysteresis input level is used when bit6 of the ILSR2 register is 0 128 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 5 Port G Table 9 5 4 shows the pin states of the port Table 9 5 4 Pin State of Port G Normal operation Operating Sleep Stop SPL 1 state Stop SPL 0 Watch SPLz1 Watch SPL 0 At reset Hi Z Input enabled Not functional Hi Z Input cutoff Pin state I O port SPL Pin state specification bit in standby control register STBC SPL Hi Z High impedance Input enabled means that the input function is in the enabled state After reset setting for internal pullup or output pin is recommended CM26 10118 3E FUJITSU MICROELECTRONIC
238. LIMITED 193 CHAPTER 14 WILD REGISTER 14 5 Typical Hardware Connection Example MB951 30 MB Series 14 5 Typical Hardware Connection Example Shown below is a typical hardware connection example applied when using the wild register function E Hardware Connection Example Figure 14 5 1 Typical Hardware Connection Example E PROM Stores correction program MB95XXX series 194 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER This chapter describes the functions and operations of the 8 16 bit compound timer 15 1 Overview of 8 16 bit Compound Timer 15 2 Configuration of 8 16 bit Compound Timer 15 3 Channels of 8 16 bit Compound Timer 15 4 Pins of 8 16 bit Compound Timer 15 5 Registers of 8 16 bit Compound Timer 15 6 Interrupts of 8 16 bit Compound Timer 15 7 Operating Description of Interval Timer Function One shot Mode 15 8 Operating Description of Interval Timer Function Continuous Mode 15 9 Operating Description of Interval Timer Function Free run Mode 15 10 Operating Description of PWM Timer Function Fixed cycle mode 15 11 Operating Description of PWM Timer Function Variable cycle Mode 15 12 Operating Description of PWC Timer Function 15 13 Operating Description of Input Capture Function 15 14 Operating Description of Noise Filter 15 15 States in Each Mode during Operation 15 16 Notes on Using 8 16 bit Compound Timer CM26 10118 3E FUJITSU MI
239. LIN UART Reception Data Register RDR 372 LIN UART Reception Data Register RDR EDB 372 UART SIO Serial Input Data Register ipeo une 325 Read Placing Flash Memory in the Read Reset State 477 Read Destination on the Execution of Bit Manipulation Instructions 514 Read modify write Read modify write Operation 514 Reception Reception 327 379 Reception Interrupt Generation and Flag Set Timing 383 Register 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO 271 16 bit PPG Down Counter Registers Upper Lower PDCRHO PDCRLO 270 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 272 16 bit PPG Status Control Register Lower PCNTLO siiis iiinis 275 16 bit PPG Status Control Register Upper PCNTHOQ inhians 2738 8 16 bit Compound Timer 00 01 Control Status Register 0 205 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCRI TO1CR1 208 8 16 bit Compound Timer 00 01 Data Register 214 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 211 8 16 bit PPG Output Inversion Register REWVQ iaiieeisenuieieiceisetene 251 8 16 bit PPG Start Register PPGS
240. Lav Lav LV IT8 NATIVO 28d ON 9195 AOW JO NV AOW Oans 23qqv AOIN OH 9d oI 219 8PH OY SPH OY nV 9 9 Vou 9 V 9A 9 9 V 494 ATIVO 28d ONI 9195 dW AOW HO NV AOIN 0915 ady dW AOW ar SH RI ca e1 g 1 8PH SY SPH SA ev eu v ev ev ev Za NATIVO 28d N 9195 diND AOW uo NV MOX AOW 28ns dW AOW 3I TE va er T SPH PA SPH PA rv vH rv ZN8 ATIVO 28d ON 9195 dO AOW CNV MOX AOIN 28ns AOIN ar e u ed ert np 8 EA SPH EA ev ev ev fav ev ev ev Ng NATIVO 28d ON 9195 dWO AOW NV OX AOIN 2915 AOIN ca ca erc Uum SPH TA SPH TA OV Cuv Ov 49 ATIYO oad ON 9195 dWO AOW JO NV AOW Oans AOIN E TA TA a I 8PH TA 8PH TA nv DV Rv vid lv nv Rv hav 28 ATIVO 28d N 9195 AOIN AOIN 2915 al 0 ou ou e1 0 1 8P ON 8 OA ou Y O ou Y VoU oU Y 0 ouv Ou NATIVO 28d 9195 dO AOW uo NV MOX AOW 28ns dW AOW da Y 91 da V 499 499 er i Sp ddO 8P daO 40 V dd v dido V V dd dH Y ddo v 499 V dd V MHOX MAOW MAOW MAOW dO AOW OX AOIN 28ns AOIN XIV 91P XI VPHXIO PXIO 19 1 8P P XIO 8P P XI PHXIO V P XIO V P XIO V V P XIO P XIO P XIO V P XIO V P XIO V MHOX MAOIN MAOW MAOW dO AOW
241. MB Series Table 22 4 4 Functions of Each Bit in LIN UART Extended Status Control Register ESCR Bit name Function LBIE LIN synch break detection interrupt enable bit This bit enables or disables LIN synch break detection interrupts An interrupt is generated when the LIN synch break detection flag LBD is 1 and the interrupt is enabled LBIE 1 This bit is fixed to 0 in mode 1 and mode 2 LBD LIN synch break detection flag bit Detect LIN synch break This bit is set to 1 when the LIN synch break is detected in operation mode 3 the serial input is 0 when bit width is 11 bits or more Also writing 0 clears the LBD bit and the interrupt Although the bit is always read as 1 when the read modify write RMW instruction is executed this does not indicate that a LIN synch break detected Note To detect a LIN synch break enable the LIN synch break detection interrupt LBIE 1 and then disable the reception SCR RXE 0 LBLI LBLO LIN synch break length selection bits These bits specify the bit length for the LIN synch break generation time The LIN synch break length for reception is always 11 bits SOPE Serial output pin direct access enable bit Enable or disable direct writing to the SOT pin Setting this bit to 1 when serial data output is enabled SMR SOE 1 enables direct writing to the SOT pin SIOP Serial I O pin direct access bit Control direct access t
242. MDO 10 Mode 2 SCKE 1 Use the dedicated baud rate reload counter 0 Input external clock SOE 1 Enable transmission reception 0 Enable reception only e LIN UART serial control register SCR RXE Set either bit to 1 AD The value of this bit is disabled so that the address data selection function cannot be used CL This bit is set to 8 bits length automatically and its value is disabled CRE 1 Since the error flag is cleared transmission reception is stopped For SSM 0 PEN P SBL Since not used parity bit and stop bit are disabled For SSM 1 PEN 1 Add detect parity bit 0 Not use parity bit P 1 Odd parity 0 Even parity SBL 1 Stop bit length 2 0 Stop bit length 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 403 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series e LIN UART serial status register SSR BDS 0 LSB first 1 MSB first RIE 1 Enable reception interrupt 0 Disable reception interrupt TIE 1 Enable transmit interrupt 0 Disable transmit interrupt e LIN UART extended communication control register SSM 0 Not use start stop bit normal 1 Use start stop bit extended function MS 0 Sending side of serial clock serial clock output Receiving side of serial clock input serial clock from sending side of serial clock Note To start communication w
243. MITED CM26 10118 3E CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB95130 MB Series 22 7 5 Bi directional Communication Function Normal Mode Normal serial bi directional communication can be performed in operation mode 0 or 2 Asynchronous mode and synchronous mode can be selected in operation modes 0 and 2 respectively E Bi directional Communication Function To operate the LIN UART in normal mode operation mode 0 or 2 the settings shown in Figure 22 7 10 are required Figure 22 7 10 Settings of LIN UART Operation Modes 0 and 2 bit15 bit14 bit13 bit12 bitii bit10 bit9 bit8 bit7 bit6 bits bit4 bits bit2 biti bitO SCR SMR P SBL CL AD CRE RXE TXE MD1 MDO OTO EXT REST UPCLI SCKE SOE Mode0 X 0 0 0 0 0 0 2 H x 0 1 0 0 0 SSR Set comparison data during writing RDR TDR ORE PHEIBONE TORE BDS RIE TIE Retain reception data during reading Mode 0 gt Mode2 m m ESCR ECCR LBIE LBD LBL1 LBLO SOPE SIOP CCO SCES Rosor LBR MS SCDE SSM RBI TBI Mode 0 X X X
244. MITED CM26 10118 3E MB95130 MB Series CHAPTER 16 8 16 BIT PPG 16 7 Operating Description of 8 16 bit PPG When the PPG operation enable bit PENOO is set to 1 the 8 bit PPG PPG timer 00 loads the value in the 8 16 bit PPG timer 00 cycle setup buffer register 500 and starts down count operation count clock rising and falling edge detection pulses of PPGO1 output after PPG timer 01 operation is enabled When the count value reaches 1 the value in the 8 16 bit PPG timer 00 cycle setup buffer register is reloaded to repeat the counting When the value of the down counter matches the value in the 8 16 bit PPG timer 00 duty setup buffer register 500 the PPGOO output is set to H synchronizing with the count clock After H which is the value of duty setting is output the PPGOO output is reset to L If the output inversion signal REVOO is 0 the polarity will remain the same If it is 1 the polarity will be inverted and the signal will be outputted to the PPGOO pin Set that the duty of the 8 bit prescaler PPG timer 01 output to 50 When PPG timer 00 is started with the 8 bit prescaler PPG timer 01 being stopped PPG timer 00 does not count When the duty of the 8 bit prescaler PPG timer 01 is set to 0 or 100 PPG timer 00 does not perform counting as the 8 bit prescaler PPG timer 01 output does not toggle Figure 16 7 4 shows the operation of 8 bit prescaler 8 bit PPG mode Figure 16 7 4 Op
245. Machine Clock divide ratio select bits CM26 10118 3E These bits select the machine clock divide ratio to the source clock The machine clock is generated from the source clock according to the divide ratio set by the bits Machine Clock Divide Ratio Selection Bits SCM1 SCMO 10g Source clock No division Main clock divided by 2 Main clock divided by 8 Main clock divided by 16 Main clock divided by 32 Source clock 4 Source clock 8 Source clock 16 FUJITSU MICROELECTRONICS LIMITED 55 CHAPTER 6 CLOCK CONTROLLER 6 4 PLL Control Register PLLC MB951 30 MB Series 6 4 PLL Control Register PLLC The PLL control register PLLC controls the main PLL clock and sub PLL clock E Configuration of PLL Control Register PLLC Figure 6 4 1 Configuration of PLL Control Register PLLC Address bit bits bit4 bit3 bit2 biti bito Initial value 0006 000000008 R W R W R W RWX R W R W R W R WX SPRDY Sub PLL clock oscillation stability bit Indicates the sub PLL clock oscillation stabilization wait state or sub PLL clock oscillation being stopped Indicates sub PLL clock oscillation being stable Setting prohibited Sub clock x 2 Sub clock x 3 Sub clock x4 SPEN Sub PLL clock oscillation enable bit 0 Disables sub PLL clock oscillation 1 Enables sub PLL clock oscillation Main PLL clock oscillation stability bit Indicates the main PLL clock oscil
246. O OE 1 TMCRO TO1 IIS MOD FE11 FE10 FEO1 FEOO x x TOODR TO1DR Holds pulse width measurement value O Used bit x Unused bit 1 Set 1 When the input capture function is selected the counter value is stored to the 8 16 bit compound timer 00 01 data register TOODR TO1DR upon detection of an edge of the external signal input The edge to be detected is selected by timer operation mode setting TOOCRO TO1CRO F3 F2 FO This function is available in either free run mode or clear mode which can be selected by timer operation mode setting In clear mode the counter starts counting from 00g When the edge is detected the counter value is transferred to the 8 16 bit compound timer 00 01 data register TOODR TOIDR the interrupt flag TOOCR1 TO1CR1 IR is set to 1 and the counter continues to count by restarting at 00g When the edge is detected in free run mode the counter value is transferred to the 8 16 bit compound timer 00 01 data register TOODR TOI DR and the interrupt flag TOOCR1 TO1CR1 IR is set to 1 In this case the counter continues to count without being cleared This function has no effect on the buffer full flag To measure the time exceeding the length of the counter software can be used to count the number of occurrences of a counter overflow When the counter causes an overflow the interrupt flag TOOCR1 1
247. O as interrupt input pin UIO UIO interrupt pin select bit 0 Deselects as interrupt input pin 1 Selects UIO as interrupt input pin ECO ECO interrupt pin select bit 0 Deselects ECO as interrupt input pin 1 Selects ECO as interrupt input pin SCK SCK interrupt pin select bit 0 Deselects SCK as interrupt input pin 1 Selects SCK as interrupt input pin SIN SIN interrupt pin select bit 0 Deselects SIN as interrupt input pin 1 Selects SIN as interrupt input pin INTOO INTOO interrupt pin select bit O Deselects INTOO as interrupt input pin 1 Selects INTOO as interrupt input pin R W Readable writable Read value is the same as write value RO WX Undefined bit Read value is 0 writing has no effect on operation Initial value 306 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT 19 4 Registers of Interrupt Pin Selection Circuit Table 19 4 1 Functional Description of Each Bit of Interrupt Pin Selection Circuit Control Register WICR 1 2 Bit name Function Undefined bit This bit is undefined The read value is always 0 Writing has no effect on the operation INTOO IINTOO interrupt pin select bit This bit is used to determine whether to select the INTOO pin as an interrupt input pin Setting the bit to 0 Deselects the INTOO pin as an interrupt input pin and the circui
248. O serves as the lower 8 bits In 16 bit PPG mode write the upper bits before the lower bits When only the upper bits are written the previously written value is reused in the next load 8 bit mode Cycle max 255 FFy x Input clock cycle 16 bit mode Cycle max 65535 x Input clock cycle Initialized at reset Do not set the cycle to 00g or Oly when using the unit in 8 bit PPG independent mode or in 8 bit prescaler mode 8 bit PPG mode Do not set the cycle to 0000 or 00014 when using the unit in 16 bit PPG mode If the cycle settings are modified during the operation the modified settings will be effective from the next PPG cycle FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 5 Registers of 8 16 bit PPG 16 5 4 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register PDSO01 PDSO0 The 8 16 bit PPG timer 00 01 duty setup buffer register PDS01 PDSO0 sets the duty of the PPG output E 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register PDSO1 PDSO0 Figure 16 5 5 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register PDS01 PDS00 PDSO1 bit7 bit5 bit4 bit3 bit2 bit bito Initial value Address DH7 DH6 DHS DH4 DH3 DH2 DHO 111111116 OF9E PDSO1 RW RW RW RW RW RW RW RW PDS00 bit7 bit5 bit4 bit3 bit2 bit bito Initial value Address DL7 DL6 DL5 DL4 DL3 DL2 DL1 DLO 111111116 OF9F PDSOO RW RW RW RW RW RW RW RW R W
249. O7 ANO7 General purpose I O port Pe Shared with UART SIO ch 0 data input UIO General purpose I O port Beye Shared with UART SIO ch 0 data output UOO General purpose I O port P12 UCKO ECO Shared with UART SIO ch 0 clock I O UCKO and 8 16 bit compound timer ch 0 clock input ECO General purpose I O port Shared with 16 bit PPG ch 0 trigger input TRGO and A D converter trigger input ADTG P13 TRG0 ADTG General purpose I O port Shared with 16 bit PPG ch 0 output PPGO P15 General purpose I O port Internal connection pin Ne Make sure to be open 1 FPT 30P M02 2 FPT 28P M17 3 Refer to section 1 8 I O Circuit Type about the I O circuit types CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 15 CHAPTER 1 DESCRIPTION 1 8 W O Circuit Type MB95130 MB Series 1 8 Circuit Type Table 1 8 1 lists the I O circuit types Also the alphabet in the Type column of Table 1 8 1 corresponds to the one in the I O Circuit Type column of Table 1 7 1 Bi 1 O Circuit Type Table 1 8 1 I O Circuit Type 1 2 Circuit Remarks Oscillation circuit R gt High speed side NI Clock Feedback resistance approx 1 MQ T Oo input Low speed side XOXOA mo t Len Feedback resistance approx 10 MQ Standby control Only for input Mode input Hysteresis input only for MASK ROM product H R Pull down resistor
250. PDSO1 DH7 DH6 DH5 DH4 DH3 DH2 DH1 DHO N Set PPG output duty for PPG timer 01 4 PDSOO DL7 DL6 DL5 DL4 DL3 DL2 DL1 DLO Set PPG output duty for PPG timer 00 7 PPGS F PENO 1 PENOO REVC REVO1 REVOO Used bit 0 Set 0 1 Set 1 x Setting nullified The bit status varies depending of the number of channels implemented il Operation of 8 bit Prescaler 8 bit PPG Mode e This mode is selected by setting the operation mode select bits MD1 MDO of the 8 16 bit PPG timer 00 control register PC00 to 01g This allows PPG timer 01 to be used as an 8 bit prescaler and PPG timer 00 to be used as an 8 bit PPG When the PPG timer 01 ch 0 down counter operation enable bit PENOI is set to 1 the 8 bit prescaler PPG timer 01 loads the value in the 8 16 bit PPG timer 01 cycle setup buffer register PPSO1 and starts down count operation When the value of the down counter matches the value in the 8 16 bit PPG timer 01 duty setup buffer register PDSOI the PPGO1 output is set to synchronizing with the count clock After H which is the value of duty setting is output the PPGOI output is set to L If the output inversion signal REVOI is 0 the polarity will remain the same If it is 1 the polarity will be inverted and the signal will be outputted to the PPG pin 256 FUJITSU MICROELECTRONICS LI
251. PLL clock mode Clock mode monitor bits Sub clock mode Sub PLL clock mode Main clock mode Main PLL clock mode R W Readable writable Read value is the same as write value R WX Read only Readable writing has no effect on operation X Indeterminate Initial value 54 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER 6 3 System Clock Control Register SYCC MB95130 MB Series Table 6 3 1 Functions of Bits in System Clock Control Register SYCC Bit name Function SCMI SCMO clock mode monitor bit Indicate the current clock mode When set to 00g the bits indicate sub clock mode When set to 015g the bits indicate sub PLL clock mode When set to 10g the bits indicate main clock mode When set to 11g the bits indicate main PLL clock mode These bits are read only Writing has no effect on operation SCSI SCSO clock mode select bits Specify the clock mode When set to 005 the bits specify transition to sub clock mode Dual clock product only When set to 015 the bits specify transition to sub PLL clock mode Dual clock product only When set to 10g the bits specify transition to main clock mode When set to 11g the bits specify transition to main PLL clock mode Once a clock mode has been selected in the SCS1 and SCSO bits any attempt to write to them is ignored until the transition to that clock mode is completed On s
252. PSSR0O 351 21 3 2 UART SIO Dedicated Baud Rate Generator Baud Rate Setting Register BRSRO 352 21 4 Operating Description of UART SIO Dedicated Baud Rate Generator 353 vii CHAPTER 22 LIN UART scd pe chanel aeri arce in eia uiii s anid enda 355 22 1 Overview of LIN UART 356 22 2 Configuration of LIN UART deae aene 358 22 9 Pins o UN UAR T Asks itti eui me qe RR gm Lx 363 22 4 Registers oPLIN UART eerie ee edd cete eed idee dete poke dE eg ene 365 22 4 4 LIN UART Serial Control Register SCR sse nnn 366 22 4 LIN UART Serial Mode Register SMR ssssssssssssseseeeeeeneen nennen nnne 368 22 4 8 LIN UART Serial Status Register SSR 370 22 4 4 LIN UART Reception Data Register LIN UART Transmit Data Register RDR TDR 372 22 4 5 LIN UART Extended Status Control Register ESCR sse 374 22 4 6 LIN UART Extended Communication Control Register ECCR 376 22 4 7 LIN UART Baud Rate Generator Register 1 01 0 BGR1 BGRO 378 22 5 Interrupt oP LIN UART niti tedio titt kei eti o Pee get Ee gea ERASATEN EAER 379 22 5 1 Reception Interrupt
253. R2 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value WRDRO OF82 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO 00000000 WRDR1 OF85y RW RW RW RW RW RW RW RW WRDR2 OF88 y Wild register address setup registers WRARO to WRAR2 Address bitlb biti4 bit13 biti2 bitii bit8 Initial value WRARO OF80y OF81u RA15 RA14 RA13 RA12 RA11 RA10 RAQ 000000006 WRAR1 OF83y 0F844 RW RW RW RW RW RW RW RW WRAR2 0F86 0F87 bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value RA7 RA6 RAS RA4 RA2 RAM RAO 00000000 RW RW RW RW RW RW RW RW Wild register address compare enable register WREN Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value WREN 00764 Reserved Reserved Reserved EN2 EN1 ENO 000000006 RO WX RO WX RO WO RO WO RO WO R W RAN R W Wild register data test setup register WROR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value WROR 0077 Reserved Reserved Reserved DRR2 DRR1 DRRO 00000000g RO WX RO WX RO WO RO WO RO WO R W RAN R W R W Readable writable Read value is the same as write value RO WO Reserved bit Write value is 0 read value is 0 RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined
254. RCLK BRGE Baud rate clock output enable bit Prescaler selection PSS1 PSSO bitl bitO Prescaler selection bits CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 351 CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR 21 3 Registers of UART SIO Dedicated Baud Rate Generator MB95130 MB Series 21 3 2 UART SIO Dedicated Baud Rate Generator Baud Rate Setting Register BRSRO The UART SIO dedicated baud rate generator baud rate setting register BRSRO controls the baud rate settings il UART SIO Dedicated Baud Rate Generator Baud Rate Setting Register BRSRO Figure 21 3 3 UART SIO Dedicated Baud Rate Generator Baud Rate Setting Register BRSRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value BRSRO OFBF BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRS0 000000008 RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value This register sets the cycle of the 8 bit down counter This register can be used to set any baud rate clock Write to the register when the UART is stopped Do not set BRS 7 0 to 004 or Oly in clock asynchronous mode 352 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR MB951 30 MB Series 21 4 Operating Description of UART SIO Dedicated Baud Rate Generator 21 4 Operating Description of UART SIO Dedicated Baud Rate Generator
255. RO P05 Set the register to 0 Using INTOG pin for external interrupt DDRO P06 Set the register to 0 Using INTO7 pin for external interrupt DDRO P07 Set the register to 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 299 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 9 Sample Programs for External Interrupt Circuit Interrupt related registers MB95130 MB Series The interrupt level is set by the interrupt level setting registers shown in the following table Channel Interrupt level setting register Interrupt level register ILRO Address 000794 Interrupt vector 0 Address OFFFAy Interrupt level register ILRO Address 000794 1 Address OFFF8y Interrupt level register ILRO Address 000794 2 Address OFFF6y Interrupt level register ILRO Address 000794 3 Address OFFFAq Interrupt level register ILRO Address 000794 0 Address OFFFAq Interrupt level register ILRO Address 000794 1 Address 8 Interrupt level register ILRO Address 000794 2 Address OFFF6 Interrupt level register ILRO Address 000794 How to enable disable clear interrupts Interrupts are enabled by the interrupt enable bit EICOO ETEO or EIE1 When disabling interrupt request 3 Address OFFFAq Interrupt enable bit EIEO or EIE1 Set the bit to 0 When enabling interrupt request Set the bit to 1
256. Reset Circuit TET 450 Pins Related to UART SIO 316 Port 0 eee jene ee te Pee Cun 110 POLS PINS P teri Dee 115 Port F Pins Reeve iiini 120 Port G 125 Pin Assignment Pin Assignment of MB95130 MB Series 10 Pin Description Pin Description cccecceeeeeeeeeeeeeeeeeeeeaeaeaeaeneaes 14 LIN UART Pin Direct Access LIN UART Pin Direct 408 Pin Status Pin Status in Each 501 Placement Placement of 16 bit Data in Memory 43 PLL Clock PLL Clock Oscillation Stabilization Wait Time 53 PLL control register Configuration of PLL Control Register PLLC 56 PLLC Configuration of PLL Control Register PLLC 56 Port 0 Block Diagram of Port 0 111 Operations of Port 0 113 Port 0 Configuration seseeeeeeeeeeee 109 Port O Pins eei nere tende trei 110 Port 0 Register Function 6 112 Port 1 Block Diagram of Port 1 116 Operations of Port 1 118 Port 1 Configuration seseeeeeeeeeeee 115 Port 115 Port 1 Register Function eene 117 Port F Block Diagram of Port 121
257. S LIMITED 129 CHAPTER 9 I O PORT 9 5 Port G MB95130 MB Series 130 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 10 TIME BASE TIMER This chapter describes the functions and operations of the time base timer 10 1 Overview of Time base Timer 10 2 Configuration of Time base Timer 10 3 Registers of the Time base Timer 10 4 Interrupts of Time base Timer 10 5 Explanation of Time base Timer Operations and Setup Procedure Example 10 6 Notes on Using Time base Timer Code CM26 00122 2E Page 134 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 131 CHAPTER 10 TIME BASE TIMER 10 1 Overview of Time base Timer MB95130 MB Series 10 1 Overview of Time base Timer The time base timer is a 22 bit free run down counting counter which is synchronized with the main clock divided by two The time base timer has an interval timer function which can repeatedly generate interrupt requests at regular intervals Interval Timer Function 132 The interval timer function repeatedly generates interrupt requests at regular intervals by using the main clock divided by two as the count clock The counter of the time base timer counts down so that an interrupt request is generated every time the selected interval time elapses The interval time can be selected from the following four types Table 10 1 1 shows the interval times available to the time base timer Table 10 1 1 Interval Times of Time base Timer
258. S LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 3 Channels of 16 bit PPG Timer 17 3 Channels of 16 bit PPG Timer This section describes the channels of the 16 bit PPG timer Channels of 16 bit PPG Timer MB95130 MB series has onel6 bit PPG timer Table 17 3 1 and Table 17 3 2 show the correspondence among the channel pin and register Table 17 3 1 Pins of 16 bit PPG Timer PPGO PPGO output j TRGO Trigger 0 input Table 17 3 2 Registers of 16 bit PPG Timer Channel Register name Corresponding register name in this manual PDCRHO 16 bit PPG down counter register upper PDCRLO 16 bit PPG down counter register lower PCSRHO 16 bit PPG cycle setting buffer register upper PCSRLO 16 bit PPG cycle setting buffer register lower PDUTHO 16 bit PPG duty setting buffer register upper PDUTLO 16 bit PPG duty setting buffer register lower PCNTHO 16 bit PPG status control register upper PCNTLO 16 bit PPG status control register lower CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 267 CHAPTER 17 16 BIT PPG TIMER 17 4 Pins of 16 bit PPG Timer MB951 30 MB Series 17 4 Pins of 16 bit PPG Timer This section describes the pins of the 16 bit PPG timer E Pins of 16 bit PPG Timer The pin related to the 16 bit PPG timer is namely the PPGO pin and TRGO pin PPGO pin Each pin serves as a general purpose I O port as well as a 16 bit PPG timer output
259. Supervisor This section describes the operations of the clock supervisor il Operations of Clock Supervisor The clock supervisor monitors the main clock and sub clock oscillations If main clock and sub clock oscillations have halted the device switches to an CR clock and generates a reset The following describes the operation in each clock mode Main clock oscillation halt in main clock mode The clock supervisor detect that main clock oscillation has halted if no rising edge is detected on the main clock for 4 CR clock cycles in main clock mode If a main clock halt is detected a reset is generated and the main clock switches to the CR clock The clock supervisor may detect incorrectly if main clock is a low speed longer than 4 CR clock cycles It results from using the CR clock for detecting that main clock oscillation have halted The clock supervisor does not detect the main clock during stop mode Sub clock oscillation halt in main clock mode only on dual clock products In main clock mode the condition used to detect the sub clock oscillation as having halted is that no rising edge is detected on the sub clock for 32 CR clock cycles Although no reset is generated immediately if a sub clock halt is detected in main clock mode the sub clock switches to CR clock divided by two A reset can be generated when the device switches from main clock mode to sub clock mode with a sub clock oscillation halt detecte
260. TSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 13 WATCH COUNTER MB951 30 MB Series 13 3 Registers of Watch Counter 13 3 Registers of Watch Counter Figure 13 3 1 shows the registers of the watch counter E Registers of Watch Counter Figure 13 3 1 Registers Related to Watch Counter Watch counter data register WCDR Address bit7 bit5 bit4 bit3 bit2 bit bitO Initial value OFE3 CS1 CSO RCTR5 RCTR4 RCTR3 RCTR2 RCTR1 RCTRO 001111116 R W R W R W R W R W R W R W R W Watch counter control register WCSR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value 00704 ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1 00000000g R W R RM1 W R WX R WX R WX R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction R WX Read only Readable writing has no effect on operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 173 CHAPTER 13 WATCH COUNTER 13 3 Registers of Watch Counter MB951 30 MB Series 13 3 1 Watch Counter Data Register WCDR The watch counter data register WCDR is used to select the count clock and set the counter reload value E Watch Counter Data Register WCDR Figure 13 3 1 1 Watch Counter Data Register WCDR bit bitG bits
261. This bit is set to 1 to indicate that an external reset has occurred This bit is set to 1 to indicate that a watchdog reset has occurred This bit is set to 1 to indicate that a power on reset or low voltage detection reset option has occurred The bit value 1 indicates that a reset source occurs from either CSVR EXTS WDTR or PONR This bit is set to 1 to indicate that a software reset has occurred FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 7 RESET MB95130 MB Series 7 3 Notes on Using Reset 7 3 Notes on Using Reset This section explains the notes on using Reset E Notes on Using Reset Initialization of the main clock stop detection bit of clock supervisor The main clock stop detection bit CSVCR MM of clock supervisor is initialized only by power on reset and external reset The bit is not initialized by the watchdog timer reset software reset clock supervisor reset Therefore if one of these resets is issued the CR clock mode continues Initialization of register and bit by reset source Some registers and bits are not initialized by reset source For the reset source register RSRR which of the bit is initialized depends on the reset source The main clock stop detection bit CSVCR MM of clock supervisor is initialized only by power on reset and external reset e The CR oscillation enable bit CSVCR RCE of clock supervisor is initialized only by power on reset external
262. This selector selects the watchdog timer clear signal Counter clear control circuit This circuit controls the clearing and stopping of the watchdog timer counter Watchdog timer control register WDTC This register performs setup for activating clearing the watchdog timer counter as well as for selecting the count clock B Input Clock 148 The watchdog timer uses the output clock from either the time base timer or watch prescaler as the input clock count clock FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 11 WATCHDOG TIMER MB951 30 MB Series 11 3 Register of The Watchdog Timer 11 3 Register of The Watchdog Timer Figure 11 3 1 shows the register of the watchdog timer E Register of The Watchdog Timer Figure 11 3 1 Register of The Watchdog Timer Watchdog timer control register WDTC Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value 000Cy CS1 50 WTES3 WTE2 WTE1 WTEO 000000006 R W R W RO WX RO WX ROW ROW ROW RO W R W Readable writable Read value is the same as write value RO W Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 149 CHAPTER 11 WATCHDOG TIMER 11 3 Register of The Watchdog Timer MB95130 MB Series 11 3 1 Watchdog Timer Control Register WDTC The watchdog timer control register
263. UPT CIRCUIT 18 9 Sample Programs for External Interrupt Circuit 18 9 Sample Programs for External Interrupt Circuit We provide sample programs that can be used to operate the external interrupt circuit il Sample Programs for External Interrupt Circuit For information about the sample programs for the external interrupt circuit refer to Bl Sample Programs in Preface E Setup Methods without Sample Program Detection levels and setup methods Four detection levels are available no edge detection rising edge falling edge both edges The detection level bits EIC SLO1 SLOO or EIC SL11 SL10 are used Operation mode No edge detection Select 005 Detection level bits 5101 5100 Detecting rising edges Select 01 Detecting falling edges Select 105 Detecting both edges Select 11 Q How to use the external interrupt pin Set the corresponding data direction register DDRO to 0 Operation Using INTOO pin for external interrupt Direction bit POO to P07 Setting DDRO P00 Set the register to 0 Using INTO1 pin for external interrupt DDRO P01 Set the register to 0 Using INTO2 pin for external interrupt DDRO P02 Set the register to 0 Using INTO3 pin for external interrupt DDRO P03 Set the register to 0 Using INTO04 pin for external interrupt DDRO P04 Set the register to 0 Using INTOS pin for external interrupt DD
264. UTHO DU15 DU14 DU13 DU12 DU11 DU10 DUO9 DUO8 111111116 RW RW RW RW RW RW RW RW 16 bit PPG duty setting buffer register lower PDUTLO Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value OFAF PDUTLO DU07 DUO6 DU05 DU04 DUOS DUO2 DUO1 DUOO 111111116 RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value These registers form a 16 bit register which controls the duty ratio for the output pulses generated by the PPG Transfer of the data from the 16 bit PPG duty setting buffer registers to the duty setting registers is performed at the same timing as the down counter read When writing to these registers always use one of the following procedures e Use the MOVW instruction use a 16 bit access instruction to write to the PDUTHO register address Use the MOV instruction and write to PDUTHO first and PDUTLO second If a down counter load occurs after writing data to PDUTHO but before writing data to PDUTLO the value of the 16 bit PPG duty setting buffer registers is not transferred to the duty setting registers The relation between the value of the 16 bit PPG duty setting registers and output pulse is as follows When the same value is set in both the 16 bit PPG cycle setting buffer registers and duty setting registers the H level will always be outputted if normal polarity is set or
265. W R W R W R W Readable writable R Read only CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 457 CHAPTER 25 CLOCK SUPERVISOR 25 3 Register of Clock Supervisor 25 3 1 MB95130 MB Series Clock Supervisor Control Register CSVCR The clock supervisor control register CSVCR is used to enable the various functions and to check the status Clock Supervisor Control Register CSVCR Figure 25 3 2 Clock Supervisor Control Register CSVCR bit 7 6 5 4 3 2 1 0 Address Initial value R W R R RW RW RW RW RW Reserved Reserved bit Be sure to set this bit to 0 SRST Reset generation enable bit 0 Disables reset generation 1 Enables reset generation Assuming that a sub clock halt has been already detected at transition from main clock mode to sub clock mode SSVE Sub clock monitoring enable bit 0 Disables sub clock monitoring 1 Enables sub clock monitoring MSVE Main clock monitoring enable bit Reserved R W Readable writable R Readonly Reserved Reserved bit Initial value 0 Disables main clock monitoring 1 Enables main clock monitoring RCE CR clock oscillation enable bit 0 Disables CR clock oscillation 1 Enables CR clock oscillation SM Sub clock halt detection bit Sub clock halt not detected 1 Sub clock halt detected MM Main clock halt detection bit o Mainclock halt not detected
266. WCSR CTR 5 0 twice and clearing to CTR 5 0 20000005 180 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 13 WATCH COUNTER MB951 30 MB Series 13 7 Sample Programs for Watch Counter 13 7 Sample Programs for Watch Counter We provide sample programs that can be used to operate the watch counter il Sample Programs for Watch Counter For information about sample programs for the watch counter refer to Bl Sample Programs in Preface E Setting Methods not Covered by Sample Programs How to enable stop the watch counter Use the interrupt request enable bit WCSR ISEL Control item Watch timer initialization bit ISEL When enabling watch counter Set the bit to 1 When stopping watch counter Set the bit to 0 How to select the count clock The count clock select bits WCDR CS1 CSO are used to select the clock Interrupt related register The interrupt level is set in the interrupt level register shown in the following table Interrupt source source Interrupt level setting register Interrupt level setting register setting register Interrupt vector Interrupt vector Watch Interrupt level register ILR5 alca Counter Address 0007 55 How to enable disable clear interrupts The interrupt request enable bit WCSR ISEL is used to enable interrupts Control item Interrupt request enable bit ISEL To disable interrupt requests Set the bit to 0 To enable inte
267. WRDRO DRRI enables disables reading from the wild register data setup register WRDRI DRR2 DRRI DRRO Wild registers data test setup bits DRR2 enables disables reading from the wild register data setup register WRDR2 When set to 0 disable reading When set to 1 enable reading 192 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 14 WILD REGISTER MB95130 MB Series 14 4 Operating Description of Wild Register 14 4 Operating Description of Wild Register This section describes the setup procedure for the wild register E Setup Procedure for Wild Register Prepare a special program that can read the value to be set in the wild register from external memory e g E PROM or FRAM in the user program before executing the program The setup method for the wild register is shown below It should be noted that this section does not explain how to communicate between the external memory and the device Write the address of the built in ROM code that will be modified to the wild register address setup register WRARO to WRAR2 Write a new code into the corresponding wild register data setup register WRDRO to WRDR2 Write the corresponding bits to the wild register address compare enable register WREN to enable the wild register function Table 14 4 1 shows the register setup procedure for the wild register Table 14 4 1 Register Setup Procedure for Wild Register Operating step
268. Write value is O read value is the same as write value Undefined bit Read value is 0 writing has no effect on operation Indeterminate 468 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 3 Register of Flash Memory 26 3 1 Flash Memory Status Register FSR Figure 26 3 2 lists the functions of the flash memory status register FSR B Flash Memory Status Register FSR Figure 26 3 2 Flash Memory Status Register FSR Address bit7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O Initial value T pee eene RO WX RO WXR RM1 W R WX R W R W Re Reserved bit served Be sure to set the bit to 0 Flash memory program erase enable bit Disables flash memory area programming erasing Enables flash memory area programming erasing IRQEN Flash memory program erase interrupt enable bit 0 Disables interrupts upon completion of programming erasing 1 Enables interrupts upon completion of programming erasing Boned Reserved bit 0 Be sure to set the bit to 0 Flash memory program erase status bit Data is being programmed erased not ready to program erase next data Data has been programmed erased ready to program erase next data J Flash memory operation flag bit gt IRDYIRQ Read Write Programming erasing is being performed Clears this bit Programming e
269. Writing 0 prevents the timer output from being supplied to the external pin In this case the Timer output enable bit external pin serves as a general purpose port Writing 1 supplies timer output TMCRO TOI TOO to the external pin 210 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 5 Registers of 8 16 bit Compound Timer 15 5 3 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO The 8 16 bit compound timer 00 01 timer mode control register ch 0 TMCRO selects the filter function 8 bit or 16 bit operation mode and signal input to timer 00 and to indicate the timer output value This register serves for both of timers 00 and 01 E 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO Figure 15 5 4 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO TMCRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value OF96H TO1 TOO IIS FE11 FE10 FEO1 FEO0 00000000 R WX RWX RW RW RW RW RW R W Timer 00 filter function select bits No filtering Removing H pulse noise Removing L pulse noise Removing H L pulse noise Timer 01 filter function select bits No filtering Removing H pulse noise Removing L pulse noise Removing H L pulse noise MOD 8 bit 16 bit operation mode select
270. X R WX R WX R WX R WX R WX Read only Readable writing has no effect on operation RO WX Undefined bit Read value is 0 writing has no effect on operation The upper two bits of 10 bit A D data correspond to 011 and 0 in the ADDH register the lower eight bits correspond to bit15 to bit8 in the ADDL register Set the ADS bit in the ADC2 register to 1 to select 8 bit precision mode so that 8 bit data can be read from the ADDL register These registers are read only Writing has no effect on the operation During 8 bit conversion SAR8 and SAR9 hold 0 A D Conversion Functions When A D conversion is started the results of conversion are finalized and stored in these registers after the conversion time according to the register settings has passed After A D conversion finishes therefore read the A D data registers conversion results write 0 to the ADI bit bit3 in the ADCI register before the next A D conversion terminates then after A D conversion finishes clear the flag During A D conversion the registers contain the values resulting from the last conversion performed 438 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 5 Interrupts of 8 10 bit A D Converter 23 5 Interrupts of 8 10 bit A D Converter An interrupt source of the 8 10 bit A D converter is Completion of conversion when A D conversion functions are operating
271. a register RDR If the reception interrupt is enabled SSR RIE 1 a reception interrupt request is generated The LIN UART reception data register RDR should be read when the reception data full flag bit SSR RDRF is 1 The reception data full flag bit SSR RDRF is automatically cleared to 0 by reading the LIN UART reception data register RDR Also the reception interrupt is cleared when the reception interrupt is enabled and no error occurs When the reception error occurs any of SSR PE ORE or FRE is 1 the data in the LIN UART reception data register RDR is invalid 372 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 4 Registers of LIN UART Bi LIN UART Transmit Data Register TDR The LIN UART transmit data register TDR is the data buffer register for the serial data transmission If the data to be transmitted is written to the LIN UART transmit data register TDR when transmission is enabled SCR TXE 1 the transmit data is transferred to the transmission shift register converted to serial data and output from the serial data output pin SOT pin If the data length is 7 bits the data in the upper 1 bit TDR D7 is invalid The transmit data empty flag SSR TDRE is cleared to 0 when a transmit data is written to the LIN UART transmit data register TDR The transmit data empty flag SSR TDRE is set to 1 after the data is transferred to the transmission shi
272. a register TOODR T01DR is read from The 8 16 bit compound timer 00 01 data register holds data with the buffer full flag set to 1 Even when the next edge is detected at this time the next measurement result is lost as the count value is not transferred to the 8 16 bit compound timer 00 01 data register As the exception when the H pulse and cycle measurement TOOCRO TO1CRO F3 F2 F1 FO 10015 is selected the H pulse measurement result is transferred to the 8 16 bit compound timer 00 01 data register with the BF bit set to 1 but the cycle measurement result is not transferred to the 8 16 bit compound timer 00 01 data register with the BF bit set to 1 For cycle measurement therefore the H pulse measurement result must be read before the cycle is completed Note also that the result of H pulse measurement or cycle measurement is lost unless read before the completion of the next H pulse To measure the time exceeding the length of the counter you can use software to count the number of occurrences of a counter overflow When the counter causes an overflow the interrupt flag TOOCR1 1 1 is set to 1 The interrupt service routine can therefore be used to count the number of times the overflow occurs Note also that an overflow toggles the timer output The timer output initial value can be set by the timer output initial value bit TOOCRI TO1CR1 SO CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 229 CHAPTER 15 8 16
273. agram of 16 bit PPG Timer 265 Block Diagrams of Pins Related to 16 bit PPG tnt 268 Channels of 16 bit PPG Timer 267 Interrupts of 16 bit PPG Timer 277 Notes on Using 16 bit PPG Timer 282 Pins of 16 bit PPG 268 Registers and Vector Table Related to Interrupts of 16 bit PPG 277 Registers of 16 bit PPG Timer 269 Sample Programs for 16 bit PPG Timer 283 256 Kbit Features of 256 Kbit Flash Memory 466 Overview of 256 Kbit Flash Memory 466 Sector Configuration of 256 Kbit Flash Memory 467 8 10 bit Block Diagram of 8 10 bit A D Converter 429 Block Diagram of Pins Related to 8 10 bit A D CODV6eIer iius iie cea eia oie 432 Interrupts During 8 10 bit A D Converter Operation 439 List of 8 10 bit A D Converter Registers 433 Notes on Use of 8 10 bit A D Converter 443 Operations of 8 10 bit A D Converter s Conversion PUNCHON uii ttt erret 440 Pins of 8 10 bit A D 431 Register and Vector Table Related to 8 10 bit A D Converter Interrupts 439 Sample Programs for 8 10 bit A D Converter 444 8 10 bit A D Converter Control Register 8 10 bit A D Converter Control Regis
274. al signal as the signal input for timer 00 IIS Timer 00 internal signal select bit This bit selects 8 bit or 16 bit operation mode Writing 0 allows timers 00 and 01 to operate as separate 8 bit timers MOD Writing 1 allows timers 00 and 01 to operate as a 16 bit timer 16 bit mode enable bit This bit is set to 0 automatically when the timer starts operation TOOCRI TOICRI STA 1 in PWM timer mode variable cycle mode e Write access to this bit is nullified during timer operation TOOCR1 STA 1 or TOICRI STA 1 These bits select the filter function for the external signal ECO1 to timer 01 when the PWC timer or input capture function has been selected Timer 01 filter No filtering FE11 FE10 Timer 01 filter function select bits Removing L pulse noise Removing H pulse noise Removing H L pulse noise e Write access to these bits is nullified during timer operation TOICRI STA 1 The settings of the bits have no effect on operation when the interval timer or PWM timer function has been selected filter function does not operate 212 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB951 30 MB Series 15 5 Registers of 8 16 bit Compound Timer Table 15 5 3 Functional Description of Each Bit of 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 2 2 Bit name Function FEO1 FEOO Timer 00 fi
275. aluation of the interrupt enable flag CCR I Figure 8 1 2 illustrates the steps to take for interrupt processing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 99 CHAPTER 8 INTERRUPTS 8 1 Interrupts MB95130 MB Series Figure 8 1 2 Interrupt Processing Steps Condition code register CCR Release from stop mode Release from sleep START a Internal data bus Interrupt from peripheral resource Compare interrupt level with IL bitin PS YES Interrupt level higher than IL value Save PC and PS onto stack PC interrupt vector Update IL in PS Execute interrupt processing RETI 100 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 8 INTERRUPTS MB95130 MB Series 8 1 Interrupts 1 Any interrupt request is disabled immediately after a reset In the peripheral resource initialization program initialize those peripheral resources which generate interrupts and set their interrupt levels in their respective interrupt level setting registers ILRO to ILR5 before starting operating the peripheral resources The interrupt level can be set to 0 1 2 or 3 Level 0 is given the highest priority and level 1 the second highest Setting level 3 for a peripheral resource disables interrupts from that resource 2 Execute the main program or the interrupt processing routine for nested interrupts 3 When an interrupt is triggered in a peripheral resource the in
276. alue is the same as the write value R RM W Readable writable Read value is different from write value write value is read by read modify write instruction Only for 5V products it is an effective register 108 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 2 Port 0 9 2 Port 0 Port 0 is a general purpose I O port This section focuses on functions as a general purpose 1 0 port See the chapters on each peripheral function for details about peripheral functions E Port 0 Configuration Port 0 is made up of the following elements CM26 10118 3E General purpose I O pins peripheral function I O pins Port 0 data register PDRO Port 0 direction register DDRO Port 0 pull up register PULO A D input disable register lower AIDRL Input level selection register ILSR Input level selection register 2 ILSR2 FUJITSU MICROELECTRONICS LIMITED 109 CHAPTER 9 I O PORT 9 2 Port 0 E Port 0 Pins Port 0 has eight I O pins Table 9 2 1 lists the port 0 pins Table 9 2 1 Port 0 Pins Pin name Function Shared peripheral functions MB95 130 MB Series I O type ANOO analog input POO INTOO POO general purpose I O INTOO external interrupt input 8 16 bit PPGO ch 0 output Input Hysteresis Analog Automotive Output ANOI analog input PO1 INTO1 ANOI PPGOI P01 general purpose INTO1 external interrupt input 8
277. an parity and its polarity stop bit length operation mode synchronous asynchronous data length and serial clock UART SIO Serial Mode Control Register 1 SMC10 Figure 20 5 2 UART SIO Serial Mode Control Register 1 SMC10 Address bit7 bit6 bit5 bit4 bit3 bit bit bito Initial value RAN R W R W R W RAN R W RAW R W ae Operation mode selection bit 0 Clock asynchronous mode UART 1 Clock synchronous mode SIO CKS Clock selection bit 0 Dedicated baud rate generator 1 External clock cannot be used in clock asynchronous mode CBL1 CBLO Character bit length control bits 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits SBL Stop bit length control bit 0 1 bit length 1 2 bit length T Parity polarity bit Odd parity DP O Even parity 1 EN P Parity control bit 0 No parity 1 With parity Serial data direction control bit 0 Transmit receive data from LSB side sequentially 1 Transmit receive data from MSB side sequentially R W Readable writable Read value is the same as write value Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 319 CHAPTER 20 UART SIO 20 5 Registers of UART SIO MB95130 MB Series Table 20 5 1 Functional Description of Each Bit of UART SIO Serial Mode Control Register 1 SMC10 Bit name Function BDS Serial data direc
278. an also release the device from time base timer mode using an interrupt by the watch prescaler or watch counter Note When time base timer mode is canceled via an interrupt peripheral resources placed into time base timer mode during an action resume that action Therefore the initial interval time of the interval timer and other similar settings are rendered indeterminate After recovery from time base timer mode initialize each peripheral resource as necessary CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 77 CHAPTER 6 CLOCK CONTROLLER 6 8 Operations in Low power Consumption Modes Standby MB95130 MB Series Modes 6 8 5 Watch Mode In watch mode the operating clock for the CPU and peripheral resources is stopped The device stops all the functions except the watch prescaler watch counter external interrupt and low voltage detection reset while retaining the contents of registers and RAM that exist immediately before the transition to watch mode il Operations in Watch Mode In watch mode the operating clock for the CPU and peripheral resources is stopped The device stops all the functions except the watch prescaler watch counter external interrupt and low voltage detection reset while retaining the contents of registers and RAM that exist immediately before the transition to watch mode Transition to watch mode Writing 1 to the watch bit in the standby control register STBC TMD causes the de
279. annels and Corresponding External Pins Channel Pin name Pin function Timer 00 output Timer 01 output Timer 00 input and timer 01 input Table 15 3 2 8 16 bit Compound Timer Channels and Corresponding Registers Channel Register name Registers TOOCRO Timer 00 control status register 0 TO1CRO Timer 01 control status register 0 TOOCR1 Timer 00 control status register 1 TOICRI Timer 01 control status register 1 TOODR Timer 00 data register TOIDR Timer 01 data register TMCRO Timer 00 01 timer mode control register The 2 digit number in the pin names and register names corresponds to channel and timer The upper number corresponds to channel and the lower number corresponds to timer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 201 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 4 Pins of 8 16 bit Compound Timer MB951 30 MB Series 15 4 Pins of 8 16 bit Compound Timer This section describes the pins related to the 8 16 bit compound timer E Pins Related to 8 16 bit Compound Timer 202 The external pins related to the 8 16 bit compound timer are TO00 TOO1 and ECO is for internal chip connection 1000 pins TOOO This pin serves as the timer output pin for timer 00 during 8 bit operation or for timers 00 and 01 during 16 bit operation When the output is enabled TOOCR1 OE 1 in interval timer PWM timer or PWC timer function the pin is set for output autom
280. are trigger or retrigger Set the bits to 005 Counter borrow Set the bits to 01g Rising edge of PPG output in normal polarity or falling edge of 75 Set the bits to 10g PPG output in inverted polarity Counter borrow rising edge of PPG output in normal polarity or Set the bits to 11g falling edge of PPG output in inverted polarity Interrupt related registers The interrupt level is set by the level setting registers shown in the following table Interrupt source source Interrupt level setting register Interrupt vector Interrupt level register ILR3 15 Address 0007Cy Address OFFDCq How to enable disable clear interrupts The interrupt request enable bit PCNTLO IREN is used to enable interrupts When disabling interrupt request Set the bit to 0 When enabling interrupt request Set the bit to 1 The interrupt request flag PCNTLO IRQF is used to clear interrupt requests When clearing interrupt request Write 0 to the bit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 285 CHAPTER 17 16 BIT PPG TIMER 17 9 Sample Programs for 16 bit PPG Timer MB951 30 MB Series 286 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT This chapter describes the functions and operations of the external interrupt circuit 18 1 Overview of External Interrupt Circuit 18 2 Configuration of External Interrupt Circuit 18 3 Channels of Ex
281. ata being programmed to the current address is not guaranteed Retry from the chip erase command E Flash Memory Programming Procedure Figure 26 6 1 shows the sample procedure for programming into flash memory The hardware sequence flags can be used to check the operating state of the automatic algorithm in flash memory The data polling flag DQ7 is used for checking the completion of programming into flash memory in this example Flag check data should be read from the address where data was last written Because the data polling flag DQ7 and execution time out flag DQ5 are updated at the same time the data polling flag DQ7 must be checked even when the execution time out flag DQ5 is 1 Similarly the toggle bit flag DQ6 must be checked as it stops toggling at the same time as when the execution time out flag DQ5 changes to 1 478 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 6 Flash Memory Program Erase Figure 26 6 1 Sample Procedure for Programming into Flash Memory FSR WRE bit1 Write enable flash memory Programming command sequence 1 lt AAH 2 U554u lt 55H 3 UAAAH A0H 4 Write address Write data Read internal address Next address Data polling DQ7 Timing limit DQ5 Data polling DQ7 NO Last address Write error FSR WRE bit1 Write disable f
282. ata input pin UIO UCKO Clock input output pin for UART SIO When the clock output is enabled SMC20 SCKE 1 it serves as a UART SIO clock output pin UCKO regardless of the value of the corresponding port direction register At this time do not select the external clock set SMC10 CKS 0 When it is to be used as a UART SIO clock input pin disable the clock output SMC20 SCKE 0 and make sure that it is set as input port by the corresponding port direction register At this time be sure to select the external clock set SMC10 CKS 0 UOO Serial data output pin for UART SIO When the serial data output is enabled SMC20 TXOE 1 it serves as a UART SIO serial data output pin UOO regardless of the value of the corresponding port direction register UIO Serial data input pin for UART SIO When it is to be used as a UART SIO serial data input pin make sure that it is set as input port by the corresponding port direction register 316 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 4 Pins of UART SIO E Block Diagram of Pins Related to UART SIO Figure 20 4 1 Block Diagram of Pins Related to UART SIO UIO UOO UCKO PDR read Hysteresis 1 Only P10 is Peripheral function input selectable Peripheral function output Peripheral function output enable 1 9 Peripheral function input enable Automotive e L 0 AL 1 Pull up lt
283. atically regardless of the port direction register DDRO bit5 to serve as the timer output TOOO pin The output remains indeterminate when the input capture function has been selected enabling output 1001 pins TOO1 This pin serves as the timer output pin for timer 01 during 8 bit operation When the output is enabled 1 in interval timer PWM timer fixed cycle mode or PWC timer function the pin is set for output automatically regardless of the port direction register DDRO bit6 to serve as the timer output TOO pin The output remains indeterminate during 16 bit operation when the PWM timer function variable cycle mode or input capture function has been selected enabling output ECO pins The ECO pin is connected to the ECOO and ECOI internal pins ECOO internal pin This pin serves as the external count clock input pin for timer 00 when the interval timer or PWM timer function has been selected or as the signal input pin for timer 00 when the PWC timer or input capture function has been selected The pin cannot be set as the external count clock input pin when the PWC timer or input capture function has been selected To use this input feature set the port direction register DDRO bit2 to 0 to set the pin as an input port 1 internal pin This pin serves as the external count clock input pin for timer 01 when the interval timer or PWM timer function has been selected or the signal input pi
284. atus PS values saved in a stack and resumes the processing of the interrupted program Restoring the program status PS also restores the condition code register CCR to its value existing prior to the interrupt 102 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 8 INTERRUPTS MB95130 MB Series 8 1 Interrupts 8 1 4 Interrupt Processing Time The time between an interrupt request being generated and control being passed to the interrupt processing routine is equal to the sum of the time until the currently executing instruction completes and the interrupt handling time time required to initiate interrupt processing This time consists of a maximum of 26 machine clock cycles B Interrupt Processing Time The interrupt request sampling wait time and interrupt handling time intervene between the occurrence and acceptance of an interrupt request and the execution of the relevant interrupt service routine Interrupt request sampling wait time Whether an interrupt request has occurred is determined through the sampling of the interrupt request during the last cycle of each instruction The CPU cannot therefore recognize interrupt requests during the execution of each instruction The maximum length of this delay occurs if the interrupt request is generated immediately after the DIVU instruction requiring the longest instruction cycle 17 machine clock cycles starts executing Interrupt handling time After receiving an inter
285. bit 0 8 bit operation 1 16 bit operation Timer 00 internal signal select bit 0 Selecting external signal ECO00 as timer 00 input 1 Selecting internal signal TIIO as timer 00 input TOO Timer 00 output bit Output value of timer 00 TO1 Timer 01 output bit Output value of timer 01 R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction R WX Read only Readable writing has no effect on operation Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 211 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer MB951 30 MB Series Table 15 5 3 Functional Description of Each Bit of 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 1 2 Bit name Function This bit indicates the output value of timer 01 When the timer starts operation TOOCR1 TOICRL STA 1 the value in the bit changes depending on the selected timer function Writing to this bit has no effect on the operation The value in the bit remains indeterminate during 16 bit operation when the PWM timer function variable cycle mode or input capture function has been selected TOI e When the timer stops operation TOOCRI TOICRI STA 0 in interval timer or PWC timer Timer 01 output bit function this bit holds the last value
286. bit has been set LIN synch break Synch Field detection circuit This circuit detects a LIN synch break when the LIN master node transmits a message header The LBD flag is set when the LIN synch break is detected An internal signal is output to 8 16 bit compound timer in order to detect the first and fifth falling edges of the LIN synch Field and to measure the actual serial clock synchronization transmitted by the master node FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 2 Configuration of LIN UART LIN synch break generation circuit This circuit generates a LIN synch break with the specified length Bus idle detection circuit This circuit detects that no transmission or reception is in progress and generates the TBI and RBI flag bits LIN UART serial control register SCR Operating functions are as follows Sets parity bit existence Parity bit selection Sets stop bit length Sets data length Selects the frame data format in mode 1 Clears error flag Enables disables transmission Enables disables reception LIN UART serial mode register SMR Operating functions are as follows Selects the LIN UART operation mode Selects a clock input source Selects between one to one connection or reload counter connection for the external clock Resets a dedicated reload timer LIN UART software reset maintains register settings Enables disables output to the serial da
287. bit to 1 enables clock output Note When CKS is 1 the internal clock signal is not outputted even with this bit set to ES If this bit is set to 1 with SMC10 MD set to 0 asynchronous mode the output from the port will always be H TXOE Serial data output enable bit This bit controls the output of the serial data UOO pin Setting the bit to 0 allows the pin to be used as a general purpose port Setting the bit to 1 enables serial data output RERC Receive error flag clear bit Setting the bit to 0 clears the error flags PER OVE FER of the SSRO register Setting the bit to 1 has no effect on operation Reading this bit always returns 1 RXE Reception operation enable bit Setting the bit to 0 disables the reception of serial data Setting the bit to 1 enables the reception of serial data If this bit is set to 0 during reception the reception operation will be immediately disabled and initialization will be performed The data received up to that point will not be transferred to the serial input data register Note Setting this bit to 0 initializes reception operation It has no effect on the receive data register full RDRF bit or an error flag PER OVE FER TXE Transmission operation enable bit Setting the bit to 0 disables the transmission of serial data Setting the bit to 1 enables the transmission of serial data If this bit is set to 0 durin
288. bit4 bit3 bit2 biti bitO Initial value Aces CS1 CSO RCTRS RCTRARCTR RCTRZRCTR RCTRO 00111111 R W RW RW RAW RAW RW R W R W RCTRS to Counter reload value setting bit RCTRO Initial value Count clock select bits FCL 32 768kHz 2 FcL 125ms 2 FcL 250ms 2 500ms 2 18 R W Readable writable Read value is the same as write value Initial value FcL Sub clock Table 13 3 1 1 Functional Description of Each Bit of Watch Counter Data Register WCDR Bit name Function These bits select the clock for the watch counter 00g 2 1 01g 2P Fa 10g 2 4 1 11g 2 7 1 sub clock These bits should be modified when the WCSR ISEL bit is 0 These bits set the counter reload value If the value is modified during counting the modified value will become effective upon a reload after the counter underflows When set to 0 No interrupt requests will be generated If the reload value RCTR5 to RCTRO is modified at the same time as an interrupt is generated WCSR WCFLG 1 the correct value will not be reloaded Therefore the reload value must be modified before an interrupt is generated such as when the watch counter is stopped WCSR ISEL 0 during the interrupt routine CS1 CSO Count clock select bits RCTRS to RCTRO Counter reload value setting bits 174 FUJITSU MICROELECTRONICS LIMITED
289. bit4 bit3 bit2 bit bito RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO Used bit X Unused bit 0 Set 0 1 Set 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 337 CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example The reception depends on whether the serial clock has been set to external or internal clock When external clock is enabled gt When the reception operation enable bit RXE contains 1 serial data is received always at the rising edge of the external clock signal lt When internal clock is enabled gt The serial clock signal is outputted in accordance with transmission Therefore transmission must be performed even when only performing reception The following two procedures can be used Set the transmission operation enable bit TXE to 1 then write transmit data to the UART SIO serial output data register to generate the serial clock signal and start reception Write transmit data to the UART SIO serial output data register then set the transmission operation enable bit TXE to 1 to generate the serial clock signal and start reception When 5 bit to 8 bit serial data is received by the reception shift register the received data is transferred to the UART SIO serial input data register RDRO and the next piece of serial data can be received When the UART SIO serial input data register stores data the receive data reg
290. bits Asynchronous Normal mode Asynchronous Multiprocessor mode Synchronous Normal mode Asynchronous LIN mode OTO One to one external clock input enable bit EXT External serial clock source select bit 1 Enable the external clock to be used directly as the LIN UART serial clock Used for reception side of serial clock ECCR MS 1 in operation mode 2 synchronous When EXT 0 the OTO bit is fixed to 0 Select a clock input 0 Select the clock of the internal baud rate generator reload counter 1 Select the external serial clock source Restart the reload counter 0 No effect 1 Restart the reload counter Reading this bit always returns 0 REST Reload counter restart bit UPCL LIN UART programmable clear bit Reset the LIN UART software reset Reset the LIN UART 0 No effect 1 Reset the LIN UART immediately LIN UART software reset However the register settings are maintained At that time transmission and reception are halted All of the transmit reception interrupt factors TDRE RDRF LBD PE ORE FRE are reset Reset the LIN UART after the interrupt and transmission are disabled Also the reception data register is cleared RDR 00 and the reload counter is restarted Reading this bit always returns 0 Control the serial clock I O port 0 The SCK pin works as a general purpose I O port or a serial clock
291. bits are undefined Writing to the bits is meaningless Read always returns 0 PIEI Interrupt request enable bit This bit controls interrupts of PPG timer 01 Setting the bit to 0 disables interrupts of PPG timer 01 Setting the bit to 1 enables interrupts of PPG timer 01 The bit outputs an interrupt request IRQ when the counter borrow detection bit PUF1 and the PIEI bit are both set to 1 PUFI Counter borrow detection flag bit for PPG cycle down counter This bit serves as the counter borrow detection flag for the PPG cycle down counter of the PPG timer 01 This bit is set to 1 when a counter borrow occurs during 8 bit PPG mode or 8 bit prescaler mode n 16 bit PPG mode this bit is not set to I even when a counter borrow occurs Writing 1 to the bit is meaningless Writing 0 clears the bit e is read in read modify write RMW instruction When the bit is set to 0 a counter borrow is undetected When the bit is set to 1 a counter borrow is detected POENI Output enable bit This bit enables or disables the output of PPG timer 01 pin When the bit is set to 0 the PPG timer 01 pin is used as a general purpose port When the bit is set to 1 the PPG timer 01 pin is used as the PPG output pin Setting this bit to 1 during 16 bit PPG operation mode sets the PPG timer 01 pin as an output The setting value of REVOI is outputted L output is supplied when
292. by read modify write ROW Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 159 CHAPTER 12 WATCH PRESCALER 12 3 Registers of the Watch Prescaler MB95130 MB Series 12 3 1 Watch Prescaler Control Register WPCR The watch prescaler control register WPCR is a register used to select the interval time clear the counter control interrupts and check the status Bi Watch Prescaler Control Register WPCR Figure 12 3 2 Watch Prescaler Control Register WPCR Address pit7 bit bitb bit bit Initial value oooBy wrr wre wrct wrco weir 000000008 R RM1 W R W RO WX RO WX RO WX R W R W RO W Watch timer initialization bit Read Write 0 is always read No change No effect on operation Clears watch prescaler counter Watch interrupt interval timer time select bit Sub clock Fc 32 768kHz 211 x 2 Fa 125ms 21 x 2 Fa 250ms 213 x 2 Fc 500ms 214 x 2 1 005 WTIE Interrupt request enable bit 0 Disables interrupt request output 1 Enables interrupt request output Watch interrupt request flag bit Read Write Interval time has not elapsed Clears the bit Interval time has No change elapsed No effect on operation R W Readable writable Read val
293. caler selection register UART SIO dedicated baud rate generator baud rate setting register CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 349 CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR 21 3 Registers of UART SIO Dedicated Baud Rate Generator MB95130 MB Series 21 3 Registers of UART SIO Dedicated Baud Rate Generator The registers related to the UART SIO dedicated baud rate generator are namely the UART SIO dedicated baud rate generator prescaler selection register PSSRO and UART SIO dedicated baud rate generator baud rate setting register BRSRO E Registers Related to UART SIO Dedicated Baud Rate Generator Figure 21 3 1 Registers Related to UART SIO Dedicated Baud Rate Generator UART SIO dedicated baud rate generator prescaler selection register PSSRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value PSSRO OFBE BRGE PSS1 PSS0 00000000g RO WX RO WX RO WX RO WX RO WX R W RAN RAN UART SIO dedicated baud rate generator baud rate setting register BRSRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value BRSRO OFBF BRS7 BRS6 BRS5 BRS4 BRS3 BRS2 BRS1 BRSO 00000000 RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value RO WX Undefined bit Read value is 0 writing has no effect on operation 350 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E
294. character bit length CBL1 CBLO is set to shorter than 8 bits the excess upper bits beyond the set bit length are ignored Note The data in this register cannot be updated when TDRE in UART SIO serial status and data register is 0 When this register is updated at writing complete the transmission data and TDRE 0 without depending on of serial mode control register 2 is 1 or 0 the transmission operation is initialized by writing to TDRE becomes 1 and the update of this register becomes possible Moreover when 0 is written in TXE without the starting transmission when the transmission data is written in TDRO and it has not transmitted TXE to 1 yet TCPL is not set in 1 And to change data please write it after making TDRE 1 once by writing TXE 0 326 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 6 Interrupts of UART SIO 20 6 Interrupts of UART SIO The UART SIO has six interrupt related bits error flag bits PER OVE FER receive data register full bit RDRF transmission data register empty bit TDRE and transmission completion flag TCPL E Interrupts of UART SIO Table 20 6 1 lists the UART SIO interrupt control bits and interrupt sources Table 20 6 1 UART SIO Interrupt Control Bits and Interrupt Sources Item Description Le SSRO TDRE SSRO TCPL SSRO RDRE SSRO PER SSRO OVE SSRO FER Interrupt request
295. circuit Serial clock output lt Serial status and data register Shift register for reception Serial data input Pi ulo Serial input data register n Data sample clock input Internal bus Serial output data register Serial data output Serial mode Port control i control registers Set to 1 2 each block CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 313 CHAPTER 20 UART SIO 20 2 Configuration of UART SIO MB95130 MB Series UART SIO serial mode control register 1 SMC10 This register controls UART SIO operation mode The register is used to set the serial data direction endian parity and its polarity stop bit length operation mode synchronous asynchronous data length and serial clock UART SIO serial mode control register 2 SMC20 This register controls UART SIO operation mode It is used to enable disable serial clock output serial data output transmission reception and interrupts and to clear the reception error flag UART SIO serial status and data register SSRO This register indicates the transmission reception status and error status of UART SIO UART SIO serial input data register RDRO This register holds the receive data The serial input is converted and then stored in this register UART SIO serial output data register TDRO This register sets the trans
296. circuit Dual clock product This block is the oscillator circuit for the sub PLL clock System clock selector This block selects one of the four different source clocks for main clock sub clock main PLL clock and sub PLL clock depending on the clock mode The prescaler frequency divides the selected source clock into the machine clock It is supplied to the clock control circuit Clock control circuit This block controls the supply of the machine clock to the CPU and each peripheral resource according to the standby mode or oscillation stabilization wait time Oscillation stabilization wait circuit This block outputs the oscillation stabilization wait time signal for each clock from 14 types of main clock oscillation stabilization signals created by the time base timer and 15 types of sub clock oscillation stabilization signals created by the watch prescaler System clock control register SYCC This register is used to control current clock mode display clock mode selection machine clock divide ratio selection and sub clock oscillation in main clock mode and main PLL clock mode Standby control register STBC This register is used to control the transition from RUN state to standby mode the setting of pin states in stop mode time base timer mode or watch mode and the generation of software resets PLL control register PLLC This register is used to enable disable the oscillation of the main PLL and sub PLL clock
297. cmos 0 2 P10 P12 P13 are selectable In bit operation instruction A o m w a V o m o a Stop Watch SPL 1 c a Internal bus 0 c E c imd aN ILSR V E E n D 3 g SR write Only P10 is selectable gt ILSR2 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 317 CHAPTER 20 UART SIO 20 5 Registers of UART SIO MB95130 MB Series 20 5 Registers of UART SIO The registers related to UART SIO are UART SIO serial mode control register 1 SMC10 UART SIO serial mode control register 2 SMC20 UART SIO serial status and data register SSRO UART SIO serial output data register TDRO and UART SIO serial input data register RDRO E Registers Related to UART SIO Figure 20 5 1 Registers Related to UART SIO UART SIO serial mode control register 1 SMC10 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito 0056 BDS PEN TDP SBL CBL1 CBLO CKS MD RW RW RW RW RW RW RW RW UART SIO serial mode control register 2 SMC20 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito 00574 SCKE TXOE RERC RXE TXE RIE TCIE TEIE RW RW RW RW RW RW RW UART SIO serial status and data register SSRO Address bit7 bit6 b
298. connection to TICS and circuit 1 are not required See the connection example in Figure 27 3 1 The UIO and UOO pins are also used by the user system and the control circuit shown below like that used for the UCKO pin is required if you want to disconnect from the user circuit during serial programming The TICS signal of the flash microcontroller programmer can be used to disconnect from the user circuit during serial writing See the connection example in Figure 27 2 1 for details FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION MB95130 MB Series 27 2 Example of Serial Programming Connection Figure 27 2 2 Control Circuit AF220 AF210 AF120 AF110 programming control pin Flash memory products programming 2 4 7kQ control pin AF220 AF210 AF120 AF110 TICS pin User circuit Only connect to the AF220 AF210 AF120 or AF110 while the user power supply is turned off Note The pull up and pull down resistances in the above example connection are examples only and may be adjusted to suit your system If variation in the input level to the MOD is possible due to noise or other factors it is also recommended that you use a capacitor or other method to minimize noise CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 489 CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 27 3 Example of Minimum Connection to Flash Microcontroller MB951 30 MB Series
299. converter is not in use Noise riding on the AVcc pin may cause accuracy degradation Therefore it is recommended to connect approx 0 1 uF ceramic capacitor as a bypass capacitor between and AVgg pins in the vicinity of this device Power Supply Pins In products with multiple or Veg pins the pins of the same potential are internally connected in the device to avoid abnormal operations including latch up However you must connect the pins to external power supply and a ground line to lower the electro magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating Moreover connect the current supply source with the Vcc and pins of this device at the low impedance It is also advisable to connect a ceramic bypass capacitor of approximately 0 1 uF between Vcc and pins near this device Mode Pin MOD Connect the mode pin directly to Vec or Vss To prevent the device unintentionally entering test mode due to noise lay out the printed circuit board so as to minimize the distance from the mode pins to or Vss and to provide a low impedance connection C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics A bypass capacitor of Vcc pin must have a capacitance value higher than Cg For connection of smoothing capacitor Cs see Figure 2 1 1 Figure 2 1 1 C pin conne
300. ction can be selected as an option on 5 V products only Note Refer to the data sheet for the period and other details about the CR clock 454 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 25 CLOCK SUPERVISOR MB95130 MB Series 25 2 Configuration of Clock Supervisor 25 2 Configuration of Clock Supervisor The clock supervisor consists of the following blocks Control circuit e CR oscillator circuit e Main clock monitor e Sub clock monitor e Main clock selector e Sub clock selector e CSV control register CSVCR E Block Diagram of Clock Supervisor Figure 25 2 1 shows a block diagram of the clock supervisor Figure 25 2 1 Block Diagram of Clock Supervisor Internal bus N CSS CSV control register CSVCR Control circuit __ Internal reset Enable CR oscillator circuit Enable Detect Enable Detect Select Select sub clock main clock Main clock Sub clock monitor monitor A Internal CR clock PLL main clock Main clock Kl circuit From X0 X1 Selector Y gt 1 2 ISub clock Internal Sub clock selector sub clock From X0A X1A CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 455 CHAPTER 25 CLOCK SUPERVISOR 25 2 Configuration of Clock Supervisor MB95130 MB Series 456 Control circuit This block contr
301. ction diagram Os CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 23 CHAPTER 2 HANDLING DEVICES 2 1 Device Handling Precautions MB95130 MB Series NC Pins Any pins marked NC must be left open Analog Power Supply Always set the same potential to AVcc and When gt AVcc the current may flow through analog input pins AN 24 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 3 MEMORY SPACE This chapter describes memory space 3 1 Memory Space 3 2 Memory Map Code CM26 00126 1E Page 29 30 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 25 CHAPTER 3 MEMORY SPACE 3 1 Memory Space MB95130 MB Series 3 1 Memory Space The memory space on the F2MC 8FX family is 64 K bytes divided into I O extended I O data and program areas The memory space includes special purpose areas such as the general purpose registers and vector table E Configuration of Memory Space area addresses 0000 to 007F This area contains the control registers and data registers for on chip peripheral resources As the I O area is allocated as part of memory space it can be accessed in the same way as for memory It can also be accessed at higher speed by using direct addressing instructions Extended I O area addresses OF80 to OFFFy This area contains the control registers and data registers for on chip peripheral resources As the extended I O area is a
302. ctor This block selects the A D conversion clock with continuous activation enabled ADC2 EXT 1 Analog channel selector This circuit selects one of multiple analog input pins Sample and hold circuit This circuit holds the input voltage selected by the analog channel selector This enables A D conversion to be performed without being affected by variation in input voltage during conversion comparison by sampling and holding the input voltage immediately after starting A D conversion Control circuit The A D conversion function determines the values in the 10 bit A D converter data register sequentially from MSB to LSB based on the signals from the comparator When conversion is completed the A D conversion function sets the interrupt request flag bit ADC1 ADI Q A D converter data registers ADDH ADDL The high order two bits of 10 bit A D data are stored in the ADDH register the low order eight bits are stored in the ADDL register Setting the A D conversion precision bit ADC2 ADS to 1 provides 8 bit precision storing the upper eight bits of the 10 bit A D data in the ADDL register A D converter control register 1 ADC1 This register is used to enable and disable functions select an analog input pin check statuses and control interrupts Q A D converter control register 2 ADC2 This register is used to select an input clock enable and disable interrupts and select functions B Input Clock The 8 10
303. d E 1 pe Automotive PDR write In bit operation instruction N DDR read Internal bus DDR DDR write Stop Watch SPL 1 N PUL read y PUL PUL write ILSR2 read ILSR2 La ILSR2 write 126 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 5 Port G 9 5 1 Port G Registers This section describes the port G registers E Port G Register Function Table 9 5 2 lists the port G register functions Table 9 5 2 Port G Register Function Register name Read read modify write PDRG Pin state is L level PDR register value is 0 As output port outputs L level Pin state is H level PDR register value is 1 As output port outputs H level Port input enabled DDRG Port output enabled Pull up disabled Pull up enabled PULG Hysteresis input level selection ILSR2 Automotive input level selection Only for 5V products it is an effective register Table 9 5 3 lists the correspondence between port G pins and each register bit Table 9 5 3 Correspondence between Registers and Pins for Port G Correspondence between related register bits and pins Pin name PG2 PG1 PULG ILSR2
304. d This section describes the specifications Basic Configuration of Serial Programming Connection for Flash Memory Products Flash microcontroller programmer manufactured by Yokogawa Digital Computer Co Ltd is used for Fujitsu standard serial onboard programming Figure 27 1 1 shows the basic configuration of serial programming connection for flash memory products Figure 27 1 1 Basic Configuration of Serial Programming Connection for Flash Memory Products Host interface cable AZ221 General purpose common cable AZ210 microcontroller CLK synchronous n PEISA programmer serial Flash memory products user system memory card sA Operable in stand alone mode Note For the function and operation method of the AF220 AF210 AF120 AF110 flash microcontroller programmer and the general purpose common cable AZ210 for connection and connector contact Yokogawa Digital Computer Co Ltd 484 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION MB95130 MB Series 27 1 Basic Configuration of Serial Programming Connection for Flash Memory Products Table 27 1 1 Pins Used for Fujitsu Standard Serial Onboard Programming Function Description MOD P13 Mode pin Setting MOD High and P13 Low sets serial write mode The CPU s internal operating clock during serial write mode is the oscillator frequenc
305. d by setting the SRST bit in the clock supervisor control register CSVCR As the CR clock is used to detect whether the sub clock has halted a sub clock halt may be detected if the sub clock is set to a low speed period longer than 32 CR clock cycles The clock supervisor does not detect the sub clock during the stop mode Sub clock oscillation halt in sub clock mode only on dual clock products In sub clock mode the condition used to detect the sub clock oscillation as having halted is that no rising edge is detected on the sub clock for 34 CR clock cycles If a sub clock halt is detected a reset is generated and the device enters main clock mode In this case the sub clock switches to CR clock divided by two As the CR clock is used to detect whether the sub clock has halted a sub clock halt may be detected if the sub clock is set to a low speed period longer than 32 CR clock cycles The clock supervisor does not detect the sub clock during the stop mode Main clock oscillation halt in sub clock mode only on dual clock products In sub clock mode the main clock oscillation remains halted and is therefore not detected by the clock supervisor 460 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 25 CLOCK SUPERVISOR MB95130 MB Series 25 4 Operations of Clock Supervisor E Example Operation Flowchart for the Clock Supervisor Figure 25 4 1 Example Operation Flowchart for the Clock Supervisor Power on
306. d clock Reception remains performed as long as the reception operation enable bit RXE contains 1 Upon detection of a start bit in receive data with the reception operation enable bit RXE set to 1 one frame of data is received according to the data format set in UART SIO serial control register 1 SMC10 When the reception of one frame of data has been completed the received data is transferred to the UART SIO serial input data register RDRO and the next frame of serial data can be received When the UART SIO serial input data register RDRO stores data the receive data register full RDRF bit is set to 1 A reception interrupt occurs the moment the receive data register full RDRF bit is set to 1 when the reception interrupt enable bit RIE contains 1 Received data is read from the UART SIO serial input data register RDRO after each error flag PER OVE FER in the UART SIO serial status and data register is checked When received data is read from the UART SIO serial input data register RDRO the receive data register full RDRF bit is cleared to 0 Note that modifying UART SIO serial mode control register 1 SMC10 during reception may result in unpredictable operation If the RXE bit is set to 0 during reception the reception is immediately disabled and initialization will be performed The data received up to that point will not be transferred to the serial input data register Figure 20 7 3 Receiving Ope
307. data This bit is set to 1 when data is loaded into the transmit shift register and the transmission starts and indicates that the TDR does not have effective data Output a transmit interrupt request when both TDRE bit and TIE bit are 1 When the TDRE bit is 1 setting the LBR bit in the extended communication control register ECCR to 1 changes the TDRE bit to 0 Then the TDRE bit goes back to after LIN sync break is generated Note The initial state is TDRE 1 BDS Transfer direction selection bit Specify whether the transfer serial data is transfer from the least significant bit LSB first BDS 0 or from the most significant bit MSB first BDS 1 Note Since data values are exchanged between the upper and lower when the data is read written to the serial data register changing BDS bit after writing data to the RDR register invalidates the written data The BDS bit is fixed to 0 in mode 3 LIN RIE Reception interrupt request enable bit Enable or disable the reception interrupt request output to the interrupt controller Output a reception interrupt request when both the RIE bit and the reception data flag bit RDRF are 1 or when one or more error flag bits PE ORE FRE is 1 TIE Transmit interrupt request enable bit CM26 10118 3E Enable or disable the transmit interrupt request output to the interrupt controller Output a transmit interrupt request when both TIE bit and
308. data format selection bit Be sure to note the followings when using the AD bit The AD bit is used to select the address data for transmission when it is written and to read the AD bit received last when it reads Internally the AD bit values for transmission and reception are stored in separate registers The transmit AD bit value is read when read modify write RMW instructions are used Therefore an incorrect value may be written to the AD bit when another bit in the SCR is bit accessed For the above reason the AD bit must be set at the last access to the SCR before transmission Or the above problem can be prevented by byte accessing whenever the SCR is written LIN UART software reset Execute the LIN UART software reset SMR UPCL 1 when the TXE bit in the LIN UART serial control register SCR is Synch break detection In mode 3 LIN mode when serial input has 11 bits width or more and becomes L the LBD bit in the extended status control register ESCR is set to 1 Synch break detection and the LIN UART waits for the Synch field As a result when serial input has more than 11 bits of 0 except Synch break the LIN UART recognizes that the Synch break is input LBD 1 and then waits for the Synch field In this case execute the LIN UART reset SMR UPCL 1 Handling framing errors 1 CRE resets reception state machine and next falling edge at SINn starts reception of new byte Figure 22 8
309. dd at transmission and detect at reception a parity bit Note The parity bit is added only in operation mode 0 or in operation mode 2 with the settings that start stop is set ECCR SSM 1 This bit is fixed to 0 in mode 3 LIN P Parity selection bit Set either odd parity 1 or even parity 0 if the parity bit has been selected SCR PEN 1 SBL Stop bit length selection bit Set the bit length of the stop bit frame end mark in transmit data in operation mode 0 1 asynchronous or in operation mode 2 synchronous with the settings that start stop bit is set ECCR SSM 1 This bit is fixed to 0 in mode 3 LIN CL Data length selection bit Specify the data length to be transmitted and received This bit is fixed to 1 in mode 2 and mode 3 AD Address Data format selection bit Specify the data format for the frame to be transmitted and received in multiprocessor mode mode 1 Write to this bit in master mode read this bit in slave The operation in master mode is as follows 0 Set to data frame 1 Set to address data frame The value of last received data format is read Note See Section 22 8 Notes on Using LIN UART for using this bit CRE Reception error flag clear bit This bit is to clear FRE ORE and PE flags in serial status register SSR 0 No effect 1 Clear the error flag Reading this bit always returns 0 Note Disable the reception operation RXE
310. de Operations in Watch Mode sss 78 Watch prescaler Block Diagram of Watch Prescaler 157 Clearing Watch Prescaler 164 Interrupts of Watch Prescaler 162 Notes on Using Watch Prescaler 166 Operating Examples of Watch Prescaler 164 Operation of Interval Timer Function Watch 164 Register and Vector Table Related to Interrupts of Watch Prescaler 163 Register of the Watch 159 Sample Programs for Watch Prescaler 167 Watch prescaler control register Watch Prescaler Control Register WPCR 160 Watchdog timer Block Diagram of Watchdog Timer 147 Notes on Using Watchdog Timer 154 Operations of Watchdog 152 Register of The Watchdog Timer 149 Watchdog Timer Function 146 Watchdog timer control register Watchdog timer control register atnda 150 WATR Configuration of Oscillation Stabilization Wait Time Setting Register WATR 59 WCDR Watch Counter Data Register WCDR 174 WCSR Watch Counter Control Register WCSR 175 WDTC Watchdog t
311. de during instruction execution which is resumed after the device is released from the standby mode increasing the number of instruction execution cycles E Check That Clock mode Transition has been Completed before Setting Standby Mode Before setting standby mode make sure that clock mode transition has been completed by comparing the values of the clock mode monitor bit SYCC SCM1 SCMO and clock mode setting bit SYCC SCSI1 SCSO in the system clock control register E An Interrupt Request may Suppress Transition to Standby Mode If an attempt is made to set a standby mode while an interrupt request with an interrupt level higher than 11g has been issued the device ignores the attempt to write to the standby control register and continues instruction execution without entering the standby mode The device does not enter the standby mode even after having serviced the interrupt This behavior is the same as when interrupts are disabled by the interrupt enable flag CCR T and interrupt level bits in the condition code register CCR IL1 ILO of the CPU E Standby Mode is Also Canceled when the CPU Rejects Interrupts When an interrupt request with an interrupt level higher than 11 is issued in standby mode the device is released from the standby mode regardless of the settings of the interrupt enable flag CCR I and interrupt level bits CCR IL1 ILO of the condition code register of the CPU After being released from standby mode t
312. e Single chip mode uses only internal RAM and ROM External bus access is not used Mode data Mode data is used to determine the memory access mode of the CPU The mode data address is fixed as FFFDy the value of FFFCy can be any value Be sure to set the mode data of internal ROM to 00g to select single chip mode Figure 4 1 1 Mode Data Settings Address bit bit6 bit5 bit bito FFFDy 00 Select single chip mode Other than 00 Reserved Do not make any setting 32 After a reset the CPU fetches mode data first The CPU then fetches the reset vector after the mode data The instruction is performed from the address set by reset vector Mode pin MOD Be sure to set the mode pin MOD to Vss FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 5 CPU This chapter describes functions and operations of the CPU 5 1 Dedicated Registers 5 2 General purpose Registers 5 3 Placement of 16 bit Data in Memory Code CM26 00103 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 33 CHAPTER 5 CPU 5 1 Dedicated Registers MB95130 MB Series 5 1 Dedicated Registers The CPU has its dedicated registers the program counter PC two arithmetic registers A and T three address pointers IX EP and SP and the program status PS register Each of the registers is 16 bits long The PS register consists of the register bank po
313. e writing has no effect on operation This register stores received data The serial data signals sent to the serial data input pin UIO pin is converted by the shift register and stored in this register When received data is set correctly in this register the receive data register full RDRF bit is set to 1 At this time an interrupt occurs if reception interrupt requests have been enabled If an RDRF bit check by the program or using an interruption shows that received data is stored in this register the reading of the content for this register clears the RDRF flag to 0 When the character bit length CBL1 CBLO is set to shorter than 8 bits the excess upper bits beyond the set bit length are set to 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 325 CHAPTER 20 UART SIO 20 5 Registers of UART SIO MB95130 MB Series 20 5 5 UART SIO Serial Output Data Register TDRO The UART SIO serial output data register TDRO is used to output transmit serial data E UART SIO Serial Output Data Register Figure 20 5 6 shows the bit configuration of the UART SIO serial output data register TDRO Figure 20 5 6 UART SIO Serial Output Data Register TDRO Address bit7 bite bit5 bit4 bit3 bit2 bit bito Initial value TDRO 0059 TD7 TD6 TDS TD4 TDS TD2 TD1 TDO 00000000 RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as wr
314. e ADCI register Continuous activation using the external pin ADTG Continuous activation using the 8 16 bit compound timer output TOOO 428 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 2 Configuration of 8 10 bit A D Converter 23 2 Configuration of 8 10 bit A D Converter The 8 10 bit A D converter consists of the following blocks Clock selector input clock selector for starting A D conversion Analog channel selector e Sample and hold circuit e Control circuit A D converter data registers ADDH ADDL A D converter control register 1 ADC1 A D converter control register 2 ADC2 E Block Diagram of 8 10 bit A D Converter Figure 23 2 1 shows a block diagram of the 8 10 bit A D converter Figure 23 2 1 Block Diagram of 8 10 bit A D Converter A D converter control register 2 ADC2 dumb 4 ADTG 8 16bit compound timer TO00 output W Sample Analo ANOO to ANO7 Pip and hold Control circuit selector circuit ADDL Internal data bus AVcc gt AVss gt ANSS ANS2 ANSO ADI ADMV ADMVX aD K X A D converter control register 1 ADC1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 429 CHAPTER 23 8 10 BIT A D CONVERTER 23 2 Configuration of 8 10 bit A D Converter MB951 30 MB Series Clock sele
315. e UCKO pin input as being fixed at 0 Setting the bit to 1 Selects the UCKO pin as an interrupt input pin and the circuit passes the UCKO pin input to INTOO ch 0 of the external interrupt circuit In this case the input signal to the UCKO pin can generate an external interrupt if INTOO ch 0 operation is enabled in the external interrupt circuit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 307 CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT 19 4 Registers of Interrupt Pin Selection Circuit MB951 30 MB Series Table 19 4 1 Functional Description of Each Bit of Interrupt Pin Selection Circuit Control Register WICR 2 2 Bit name Function This bit is used to determine whether to select the TRGO pin as an interrupt input pin Setting the bit to 0 Deselects the TRGO pin as an interrupt input pin and the circuit treats the TRGO pin input as being fixed at 0 Setting the bit to 1 Selects the TRGO pin as an interrupt input pin and the circuit passes the TRGO pin input to INTOO ch 0 of the external interrupt circuit In this case the input signal to the SCK pin can generate an external interrupt if INTOO ch 0 operation is enabled in the external interrupt circuit TRGO0 TRGO interrupt pin select bit When these bits are set to 1 and the operation of INTOO ch 0 of the external interrupt circuit is enabled in MCU standby mode the selected pins are enabled to perform input operation The MCU wakes up
316. e affects the following resources e UART SIO e 8 16 bit compound timer e 8 16 bit PPG 16 bit PPG e 8 10 bit A D converter 84 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 7 RESET This section describes the reset operation 7 1 Reset Operation 7 2 Reset Source Register RSRR 7 3 Notes on Using Reset Code CM26 00104 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 85 CHAPTER 7 RESET 7 1 Reset Operation MB95130 MB Series 7 1 Reset Operation When a reset factor occurs the CPU stops the current execution immediately and enters the reset release wait state When the device is released from the reset the CPU reads mode data and the reset vector from internal ROM mode fetch When the power is turned on or when the device is released from a reset in sub clock mode sub PLL clock mode or stop mode the CPU performs mode fetch after the oscillation stabilization wait time has passed E Reset Factors Resets are classified into five reset factors Table 7 1 1 Reset Sources Reset Sources Reset Condition External reset L level input to the external reset pin Software reset is written to the software reset bit STBC SRST in the standby control register Watchdog reset The watchdog timer causes an overflow Power on reset The power is turned on or the supply voltage falls below the detected voltage low voltage detection reset Option Clock supervisor reset Abno
317. e clock MB95F136JBS MB95F136MBW MB95F136NBW Dual clock MB95F136JBW 8KB 256B 16KB 512B 5V products 32KB 1KB Single clock Mask ROM MB95136MB 32KB 1KB products Dual clock 4 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 1 DESCRIPTION MB95130 MB Series 1 2 Product Lineup of MB95130 MB Series LVD Low voltage detection reset CSV Clock Supervisor For evaluation products use the switch on MCU board to enable disable LVD CSV and the 1 2 system LVD cannot be disabled while CSV is enabled 2 For the mask ROM products enable disable LVD CSV and the 1 2 system when ordering the mask ROM LVD cannot be disabled while CSV is enabled CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 5 CHAPTER 1 DESCRIPTION 1 2 Product Lineup of MB95130 MB Series MB95130 MB Series Table 1 2 2 CPU and Peripheral Function of MB95130 MB Series Item Specification CPU function Number of basic instructions 136 instructions Instruction bit length 8 bits Instruction length 1 to 3 bytes Data bit length 1 8 and 16 bits Minimum instruction execution time 61 5 ns at machine clock 16 25 MHz Interrupt processing time 0 6 us at machine clock 16 25 MHz Peripheral function Port General purpose I O ports CMOS 20 Max Time base ti
318. e falling edge of TRGO EGS1 Hardware trigger enable bit1 0 The rising edge of TRGO has no effect on operation 1 The operation is started by the rising edge of TRGO R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 275 CHAPTER 17 16 BIT PPG TIMER 17 5 Registers of 16 bit PPG Timer MB95130 MB Series Table 17 5 2 16 bit PPG Status Control Register Lower PCNTLO Bit name Function EGS1 Hardware trigger enable bit1 This bit determines whether to allow or disallow the falling edge of TRGO input to stop operation When the bit is set to 0 the falling edge of TRGO has no effect on operation When the bit is set to 1 the operation is stopped by the falling edge of TRGO EGSO Hardware trigger enable bit0 This bit determines whether to allow or disallow the rising edge of TRGO input to start operation When the bit is set to 0 the rising edge of TRGO has no effect on operation When the bit is set to 1 the operation is started by the rising edge of TRGO TREN PPG interrupt request enable bit This bit enables or disables PPG interrupt request to the interrupt controller When the bit is set to 0 an interrupt request is disabled When the bit is set to 1 an interrupt r
319. e instruction that follows the instruction executed prior to the interrupt Note The interrupt request flag bits of peripheral resources are not automatically cleared to after an interrupt request is accepted The bits must therefore be cleared to 0 by a program by writing O to the interrupt request flag bit in the interrupt processing routine An interrupt causes the device to recover from standby mode low power consumption mode For details see Section 6 8 Operations in Low power Consumption Modes Standby Modes CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 101 CHAPTER 8 INTERRUPTS 8 1 Interrupts MB95130 MB Series 8 1 3 Nested Interrupts You can set different interrupt levels for two or more interrupt requests from peripheral resources in the interrupt level setting registers ILRO to ILR5 to process the nested interrupts E Nested Interrupts If an interrupt request of higher priority interrupt level occurs while an interrupt service routine is being executed the CPU halts processing of the current interrupt and accepts the higher priority interrupt request The interrupt level can be set to 0 to 3 If it is set to 3 the CPU will accept no interrupt request Example Nested interrupts To assign higher priority to external interrupts over timer interrupts as an example of processing nested interrupts set the timer interrupt and external interrupt levels to 2 and 1 respectively If an external
320. e noise 492 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX This appendix explains I O map interrupt list memory map pin status instruction overview mask option and writing to Flash microcontroller using parallel writer APPENDIX A I O Map APPENDIX B Table of Interrupt Causes APPENDIX C Memory Map APPENDIX D Pin Status of MB95130 MB series APPENDIX E Instruction Overview APPENDIX F Mask Option APPENDIX G Writing to Flash Microcontroller Using Parallel Writer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 493 APPENDIX APPENDIX A Map MB95130 MB Series APPENDIX A I O Map This section explains I O map that is used on MB95130 MB series B I O Map Table A 1 MB95130 MB Series 1 4 Address Register name an 00004 PDRO Port 0 data register R W 00000000 00014 DDRO Port 0 direction register R W 00000000g 00024 PDR1 Port 1 data register R W 00000000 00034 DDR1 Port 1 direction register R W 00000000 00044 Prohibited 00054 WATR Oscillation stabilization wait time setting register R W 11111111g 00064 PLLC PLL control register R W 000000005 00074 SYCC System clock control register R W 1010x011g 00084 STBC Standby control register R W 00000000g 00094 RSRR Reset source register R W XXXXXXXXp 000A hH TBTC Time base timer control register R W 00000000g 000B4 WPCR
321. e or main clock oscillation PLL Clock stabilization wait time to elapse whichever is longer When the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 10g the device enters main clock mode after waiting for the main clock oscillation stabilization wait time CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 69 CHAPTER 6 CLOCK CONTROLLER 6 8 Operations in Low power Consumption Modes Standby MB95130 MB Series Modes 6 8 Operations in Low power Consumption Modes Standby Modes The standby modes available are sleep mode stop mode time base timer mode and watch mode E Overview of Transitions to and from Standby Mode The standby modes available are sleep mode stop mode time base timer mode and watch mode The device enters standby mode according to the settings in the standby control register STBC The device is released from standby mode in response to an interrupt or reset Before transition to normal operation the device waits for the oscillation stabilization wait time to elapse as required When released from standby mode by a reset the device returns to main clock mode When released from standby mode by an interrupt the device enters the clock mode in which the device was before entering the standby mode E Pin States in Standby Mode 70 The pin state setting bit STBC SPL of the standby control register can be used to set the I O port per
322. e timer set for 16 bit operation TMCRO MOD 1 starts operation TOOCR1 TOICRI STA 1 in the PWM timer function variable cycle mode Write access to these bits is nullified during timer operation TOOCR1 TOICRI STA 1 Timer operation mode select bits Interval timer one shot mode Interval timer continuous mode Interval timer free run mode PWM timer fixed cycle mode PWM timer variable cycle mode PWC timer H pulse rising to falling F3 F2 Fl FO PWC timer L pulse falling to rising Timer operation mode select bits PWC timer cycle rising to rising j O O O O Oo CO CO oj o O O gt j O O O PWC timer cycle falling to falling PWC timer H pulse rising to falling Cycle rising to rising Input capture rising free run counter Input capture falling free run counter Input capture both edges free run counter Input capture rising counter clear Input capture falling counter clear Input capture both edges counter clear CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 207 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer 15 5 2 TOOCR1 TO1CR1 MB95130 MB Series 8 16 bit Compound Timer 00 01 Control Status Register 1 8 16 bit compound timer 00 01 control status register 1 TOOCR1
323. e used to program write and erase data into from flash memory Programming erasing using a parallel writer Programming erasing using a dedicated serial writer Programming erasing by program execution As flash memory by program execution can be programmed and erased by the instructions from the CPU via the flash memory interface circuit you can efficiently reprogram update program code and data in flash memory with the device mounted on a circuit board E Features of 256 Kbit Flash Memory 32K bytes x 8 bits sector configuration Automatic program algorithm Embedded Algorithm Detection of completion of programming erasing using the data polling or toggle bit function Detection of completion of programming erasing by CPU interrupts Compatible with JEDEC standard commands Programming erase count minimum 10 000 times E Programming and Erasing Flash Memory 466 It is not possible to write to and read from flash memory at the same time To program erase data into from flash memory first copy the program on the flash memory to RAM and then execute the copied program on RAM so that writing to the flash memory can be performed FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 2 Sector Configuration of Flash Memory 26 2 Sector Configuration of Flash Memory This section explains the sector configuration of flash memory Sector Configuration of 256 Kbit F
324. ead only Readable writing has no effect on operation RO W Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Initial value 00000000 Initial value 000000006 Initial value 00000000pg Initial value 000000008 R RM1 W Readable writable Read value is different from write value 1 is read by read modify write CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 433 CHAPTER 23 8 10 BIT A D CONVERTER 23 4 Registers of 8 10 bit A D Converter MB951 30 MB Series 23 4 1 8 10 bit A D Converter Control Register 1 ADC1 8 10 bit A D converter control register 1 ADC1 is used to enable and disable individual functions of the 8 10 bit A D converter select an analog input pin and to check the states E 8 10 bit A D Converter Control Register 1 ADC1 Figure 23 4 2 8 10 bit A D Converter Control Register 1 ADC1 Address _ bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value 006CH ANS3 ANS2 ANS1 ANSO ADI ADMV aowvx AD 000000008 R W RAN R W R W R RM1 W RWX RW ROW AD A D conversion start bit 0 Do not start A D conversion 1 Start A D conversion ADMVX Current cut off analog switch control bit 0 Turn on analog switch only during conversion 1 Maintain analog switch on Interrupt request flag bit Read Write Conversion not completed Clear this bit Make no changes to the bit
325. eak detected Transmit interrupts send data empty Interrupt requests to TIIO LIN synch field detected LSYN Master slave mode communication function Multiprocessor mode Capable of 1 master to n slaves communication support both the master and slave system Synchronous Mode Send side receive side of serial clock Pin access Serial I O pin states can be read directly LIN bus option Master device operation Slave device operation LIN synch break detection LIN Synch break generation Detection of LIN synch field start stop edges connected to the 8 16 bit compound timer Synchronous serial clock Continuous output to the SCK pin is possible for synchronous communication using the start stop bits Clock delay option 356 Special synchronous clock mode for delaying the clock used for serial peripheral interface SPI FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 1 Overview of LIN UART The LIN UART has four operation modes The operation mode is selected by the MDO and MDI bits in the LIN UART serial mode register SMR Mode 0 and mode 2 are used for bi directional serial communication mode 1 for master slave communication and mode 3 for LIN master slave communication Table 22 1 2 LIN UART Operation Modes Data length Synchronous Stop Data bit Operation mode With parity method bit length format No parit
326. easurement is begun 52 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB951 30 MB Series 6 2 Oscillation Stabilization Wait Time B PLL Clock Oscillation Stabilization Wait Time As with the oscillation stabilization wait time of the oscillator the clock controller automatically waits for the PLL oscillation stabilization wait time to elapse after a request for state transition from PLL oscillation stopped state to oscillation start is generated via an interrupt in standby mode or a change of clock mode by software Note that the PLL clock oscillation stabilization wait time changes according to the PLL startup timing Table 6 2 2 shows the PLL oscillation stabilization wait time Table 6 2 2 PLL Oscillation Stabilization Wait Time PLL Oscillation Stabilization Wait Time Remarks Minimum Maximum time time Oscillation stabilization wait time is taken while 2 Roy is Main PLL clock 2 Roy X 2 counted twice minimum or three times maximum Foy represents the main clock frequency Oscillation stabilization wait time is taken while 2 Fo is Sub PLL clock Dual clock product 2 2 counted twice minimum or three times maximum Fc represents the sub clock frequency E Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition The clock controller automatically waits for the oscillation stabilization wait time to elapse as needed when the operatin
327. ection control BDS When selecting LSB first transfer from least significant bit Set the bit to 0 When selecting MSB first transfer from most significant bit Set the bit to 1 How to clear the reception completion flag Uses the following setting Control item Method To clear the reception completion flag Read the RDRO register The first RDRO register read is the reception initiation Q How to clear the transmit buffer empty flag Uses the following setting Control item Method To clear the transmit buffer empty flag Write to TDRO register The first TDRO register write is the transmit initiation How to set the baud rate See Section 20 7 1 Operating Description of Operation Mode 0 344 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 8 Sample Programs for UART SIO Interrupt related register Use the following interrupt level setting register to set the interrupt level Interrupt level setting register Interrupt vector Interrupt level register ILR1 4 a Address 0007 Address OFFF2g Enabling disabling and clearing interrupts The interrupt request enable bits SMC20 RIE SMC20 TCIE SMC20 TEIE are used to enable interrupts UART reception UART transmission Transmission Transmission data Reception completion register empty interrupt enable bit RIE interrupt interrupt enable bit enable
328. ectional communication function normal mode and master slave communication function multiprocessor mode supports both master and slave operation the LIN UART also supports the special functions used by the LIN bus E Functions of LIN UART The LIN UART is a general purpose serial data communication interface for transmitting serial data to and receiving data from other CPUs and peripheral devices Table 22 1 1 lists the functions of the LIN UART Table 22 1 1 Functions of LIN UART Data buffer Full duplex double buffer Serial input The LIN UART oversamples received data for five times to determine the received value by majority only asynchronous mode Transfer mode Clock synchronization Select start stop synchronization or start stop bit Clock asynchronous Start stop bits available Baud rate Dedicated baud rate generator provided made of a 15 bit reload counter The external clock can be inputted The reload counter can also be used to adjust the external clock Data length 7 bits not in synchronous or LIN mode 8 bits Signaling NRZ Non Return to Zero Start bit timing Synchronization with the start bit falling edge in asynchronous mode Reception error detection Framing error Overrun error Parity error Not supported in operation mode 1 Interrupt request Reception interrupts reception completed reception error detected LIN synch br
329. ed to the controller E Registers and Vector Table Related to Interrupts of 16 bit PPG Timer Table 17 6 2 Registers and Vector Table Related to Interrupts of 16 bit PPG Timer Interrupt Interrupt Interrupt level setting register Vector table address Source request No Register Setting bit ch Channel Refer to APPENDIX B Table of Interrupt Causes for the interrupt request numbers and vector tables of all peripheral functions CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 277 CHAPTER 17 16 BIT PPG TIMER 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example MB951 30 MB Series 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example The 16 bit PPG timer can operate in PWM mode or one shot mode In addition a retrigger function can be used in the 16 bit PPG timer E PWM MDSE of PCNTH Register bit 5 0 In PWM operation mode the 16 bit PPG cycle setting buffer register PCSRHO PCSRLO values are loaded and the 16 bit down counter starts down count operation when a software trigger is inputted or a hardware trigger by TRGO pin input is inputted When the count value reaches 1 the 16 bit PPG cycle setting buffer register PCSRHO PCSRLO values are reloaded to repeat the down count operation The initial state of the PPGO output is L When the 16 bit down counter value matches the value set in the duty setting registers the output changes to H synchronizing
330. eeeeeeeeeeeseeeeneaees 517 Output 8 16 bit PPG Output Inversion Register uiuis timete cetus ien tust 251 Output Clock Output Clock 82 134 158 348 Overview Instruction Overview of 2 8 503 Overview of 8 16 bit PPG 238 Overview of I O Ports esee 108 531 P Package and Its Corresponding Product Package Its Corresponding Product 8 Package Dimension Package Dimension of FPT 28P M17 12 Package Dimension of FPT 30P M02 13 Parallel Writer Writing to Flash Microcontroller Using Parallel Writer 521 PC 8 16 bit PPG Timer 00 Control Register ch 0 oo cuente ete ce eatem ces 246 8 16 bit PPG Timer 01 Control Register ch 0 PCO 3 iei ien ecran ip fe 244 PCNTH 16 bit PPG Status Control Register Upper RENT wes iie cana teat enata yen 2738 One shot Mode MDSE of PCNTHO Register codem hen ed 280 PWM Mode MDSE of PCNTH Register bit 530 terti pe focii itte 278 PCNTL 16 bit PPG Status Control Register Lower PENT EO iyo teint dieere teuer omues 275 PCSRHO PCSRLO 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO 271 PDCRHO PDCRLO 16 bit PPG Down Counter Registers Upper Lower PDCRHO PDCRLO 270 PDS 8 16 bit PPG Timer 00 01 Duty Setup Buf
331. egisters Upper Lower PDCRLO 270 526 Function of Reload Counter 393 Watch counter 170 Inter CPU Connection Method 396 Standby Mode is Also Canceled when the CPU Rejects Interrupts 71 CSVCR Clock supervisor control register delere eee 458 D Data Polling Flag Data Polling Flag 473 Debug Precautions for Debug 21 Dedicated Baud Rate Generator Operation of Dedicated Baud Rate Generator Reload COUntert coprire naaa a dek 392 Dedicated Registers Configuration of Dedicated Registers 34 Functions of Dedicated Registers 34 Description Pin Descriptlon ise itte eee anaE 14 Device Handling Devices eeeeeeeeeeeeeee 20 Difference Points among Products Difference Points among Products and Notes on Selecting a 7 Display Sign Explanation of Display Sign of Instruction 504 DP Configuration of Direct Bank Pointer DP 37 DQ5 Timing Limit Elapsed Flag Hl ek 475 DQ6 Toggle Bit Flag DQ6 474 DQ7 Data Polling Flag DOT cet eerte eeu 473 Dual Clock Product Operations in Sub Clock M
332. el it becomes OR of the signals inputted to the selected pins 310 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO This chapter describes the functions and operations of UART SIO 20 1 Overview of UART SIO 20 2 Configuration of UART SIO 20 3 Channels of UART SIO 20 4 Pins of UART SIO 20 5 Registers of UART SIO 20 6 Interrupts of UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure Example 20 8 Sample Programs for UART SIO Code CM26 00120 2E Page 317 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 311 CHAPTER 20 UART SIO 20 1 Overview of UART SIO 20 1 Overview of UART SIO MB95130 MB Series The UART SIO is a general purpose serial data communication interface Serial data transfers of variable length data can be made with a synchronous or asynchronous clock The transfer format is NRZ The transfer rate can be set with the dedicated baud rate generator or external clock in clock synchronous mode E Functions of UART SIO The UART SIO is capable of serial data transmission reception serial input output to and from another CPU or peripheral device Table 20 1 1 Operation Modes of UART SIO 312 Equipped with a full duplex double buffer that allows 2 way full duplex communication The synchronous or asynchronous transfer mode can be selected The optimum baud rate can be selected with the dedicated baud rate generator The data length is variable
333. elect the interval time Interval time select bits Main clock Foy 4MHz TBCI TBCO 210 X 2 512 0 us Interval time select bits 212 X 2 Fcy 2 05ms 214 X 2 Foy 8 19ms 216 X 2 Foy 32 77ms This bit clears the time base timer counter Writing 0 ignored and has no effect on the operation TCLR Writing 1 initializes all counter bits to 1 Time base timer The read value is always 0 initialization bit Note When the output of the time base timer is selected as the count clock for the watchdog timer using this bit to clear the time base timer also clears the watchdog timer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 137 CHAPTER 10 TIME BASE TIMER 10 4 Interrupts of Time base Timer MB951 30 MB Series 10 4 Interrupts of Time base Timer An interrupt request is triggered when the interval time selected by the time base timer elapses interval timer function E Interrupt when Interval Function is in Operation When the time base timer counter counts down using the internal count clock and the selected time base timer counter underflows the time base timer interrupt request flag bit TBTC TBIF is set to 1 If the time base timer interrupt request enable bit is enabled TBTC TBIE 1 an interrupt request IRQ19 will be generated to interrupt controller Regardless of the value of TBIE bit TBIF bit is set to 1 when the selected bit underflows When TBIF bit
334. els will be reversed if OSEL is set to 1 invalidating the retrigger RTRG of PCNTHO register bit 4 0 Figure 17 7 3 When Retrigger Is Invalid in One shot Mode Counter value NE ibo Mu c 0 Time Rising edge detected i Trigger ignored Software trigger 1 PPG m Normal polarity PPG Inverted polarity PEUT 0 T Count clock cycle 1 n x T ns m PCSRHO amp PCSRLO register value 2 m x T ns n PDUTHO amp PDUTLO register value Validating the retrigger RTRG of PCNTHO register bit 4 1 Figure 17 7 4 When Retrigger Is Valid in One shot Mode Counter value T EN cee eee ME TN NE iR ES Seer estie dk 0 Time Rising edge detected Software trigger PPG Normal polarity PPG Inverted polarity 2 1 n x T ns 2 T Count clock cycle 2 T m PCSRHO amp PCSRLO register value 2 m x T ns n PDUTHO amp PDUTLO register value 280 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example E Hardware Trigger Hardware trigger refers to PPG activation by signal input to the TRGO input pin When EGS1 and EGSO are set to 11g and the hardware trigger is used with TRGO input PPG starts operation on a rising edge and ha
335. emory Automatic Algorithm 471 26 5 Checking the Automatic Algorithm Execution Status sssssssssssssseeeeeenn 472 26 5 1 Data Polling Flag DQ7 niin i e etn te e eh retos 473 26 5 2 Toggle Bit Flag iren petebat ede eo 474 26 5 3 Execution Time out Flag DQ5 sssssssessssssseseseenennne nnne en tenent senten nenne nennen en 475 26 6 Flash Memory 476 26 6 1 Placing Flash Memory in the Read Reset State sse 477 26 6 2 Programming Data into Flash Memory sse enne en ETKA nnne nnns 478 26 6 3 Erasing All Data from Flash Memory Chip Erase 480 26 7 Flash SeCurity th ith ae ate Met uite 481 CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 483 27 1 Basic Configuration of Serial Programming Connection for Flash Memory Products 484 27 2 Example of Serial Programming Connection nennen 487 27 8 Example of Minimum Connection to Flash Microcontroller Programmer 490 PRP PEIN DM Ge 493 APPENDDCA I OMap o iiia etit ette emnt ee rota etie diede reo ede de 494 APPENDIX B Table of Interrupt Causes sse
336. en the start stop bit is included ECCR SSM 1 you can select whether or not to include the parity bit SCR PEN Figure 22 7 3 shows the transmit reception data format operation mode 2 Figure 22 7 3 Transmit Reception Data Format Operation Mode 2 Transmit reception data ECCR SSM 0 SCR PEN 0 bey bey b Dsy b 07 Transmit reception data E ECCR SSM 1 SCR PEN 0 ST gt f Ds De o7 SP SP Transmit reception data ECCR SSM 1 SCR PEN 1 Ver bo ox foafos osyos pef P sP se When two stop bits are set SCR SBL 1 ST Start bit SP Stop bit P Parity bit LSB first Clock inversion function When the SCES bit in the LIN UART extended status control register ESCR is 1 the serial clock is inverted In receiving side of serial clock the LIN UART samples data at the falling edge of the received serial clock Note that in sending side of serial clock the mark level is set to 0 when the SCES bit is 1 Figure 22 7 4 Transmission Data Format During Clock Inverted Transmit reception clock Mark level SCES 0 CCO 0 Transmit reception clock SCES 266020 PULL LLL LU D Eo uec Data stream SSM 1 No parity 1 stop bit 1 lt Data frame g CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 401 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series Q Start stop bit W
337. enable bit SMC20 TEIE SMC20 TCIE SMC20 RIE SMC20 RIE SMC20 RIE SMC20 RIE Transmission Interrupt source data register empty Transmission Reception data Parity Overrun completion register full error error Framing error E Transmit Interrupts When transmit data is written to the serial output data register TDRO the data is transferred to the transmission shift register When the next piece of data can be written the TDRE bit is set to 1 At this time an interrupt request to the interrupt controller occurs when transmit data register empty interrupt enable bit has been enabled SMC20 TEIE 1 The TCPL bit is set to upon completion of transmission of all pieces of transmit data At this time an interrupt request to the interrupt controller occurs when transmission completion interrupt enable bit has been enabled SMC20 TCIE 1 E Reception Interrupt If the data is inputted successfully up to the stop bit the RDRF bit is set to 1 If an overrun parity or framing error occurs the corresponding error flag bit PER OVE or FER is set to SE These bits are set when a stop bit is detected If reception interrupt enable bit has been enabled SMC20 RIE 1 an interrupt request to the interrupt controller will be generated Refer to CHAPTER 8 INTERRUPTS for the interrupt request numbers and vector tables of all peripheral functions Registers and Vector Table Related to UART SIO
338. enabled and not blocked e f the pin state specification bit is 0 the state remains in port I O or peripheral function I O and the output is maintained Operation of the pull up control register Setting 1 to the PUL register connects the pull up resistor to the pin However when the general purpose I O port or shared peripheral resource outputs L level the pull up resistor is disconnected regardless of the PUL register value Operation of the input level selection register e Setting 1 to the bitO of ILSR register changes only P10 from the hysteresis input level to the CMOS input level When the bitO of ILSR register is 0 it should be the hysteresis input level For pins other than P10 the CMOS input level cannot be selected however only the hysteresis input level or the automotive input level can Make sure that the input level for P10 is changed during the peripheral function UART SIO stopped Operation of the input level selection register 2 The ILSR2 register is a valid register only for 5V models e Setting bitl of the ILSR2 register to 1 changes the port 1 input level from the hysteresis input level to the automotive input level The hysteresis input level is used when bit of the ILSR2 register is 0 e P10 only uses the automotive input level when bit 0 of the ILSR register is 0 In the case of P10 only setting 1 to bitO of the ILSR register has priority over ILSR2 Only modify the
339. equest is enabled IRQF PPG interrupt flag bit This bit is set to 1 when a PPG interrupt occurs When the bit is set to 0 clears the bit When the bit is set to 1 has no effect on operation is always read in read modify write RMW instruction IRS1 IRSO Interrupt type select bits These bits select the interrupt type for the PPG timer Type of interrupt Trigger by TRGO input software trigger or retrigger Counter borrow Rising edge of PPGO output in normal polarity or falling edge of PPGO output in inverted polarity Counter borrow rising edge of PPGO output in normal polarity or falling edge of PPGO output in inverted polarity POEN Output enable bit This bit enables or disables output from the PPGO output pin When the bit is set to 0 the pin serves as a general purpose port When the bit is set to 1 the pin serves as the PPG timer output pin OSEL Output inversion bit This bit selects the polarity of PPGO output pin When the bit is set to 0 the PPGO output goes to when L is output in the internal start and the 16 bit down counter value matches the duty setting register value and goes to L when a down counter borrow occurs Normal polarity When the bit is set to 1 the PPGO output is inverted Inverted polarity FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB951 30 MB Series 17 6 Interrupts of 16
340. er 23 1 Overview of 8 10 bit A D Converter 23 2 Configuration of 8 10 bit A D Converter 23 3 Pins of 8 10 bit A D Converter 23 4 Registers of 8 10 bit A D Converter 23 5 Interrupts of 8 10 bit A D Converter 23 6 Operations of 8 10 bit A D Converter and Its Setup Procedure Examples 23 7 Notes on Use of 8 10 bit A D Converter 23 8 Sample Programs for 8 10 bit A D Converter Code CM26 00125 2E Page 429 431 432 434 435 442 443 445 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 427 CHAPTER 23 8 10 BIT A D CONVERTER 23 1 Overview of 8 10 bit A D Converter MB951 30 MB Series 23 1 Overview of 8 10 bit A D Converter The 8 10 bit A D converter is a 10 bit successive approximation type of 8 10 bit A D converter It can be started via software external trigger and internal clock with one input signal selected from among multiple analog input pins E A D Conversion Functions The A D converter converts analog voltages input voltages input to an analog input pin to 10 bit digital values Oneof multiple analog input pins can be selected The conversion speed is programmable to be configured selected according to the operating voltage and frequency Aninterrupt is generated when A D conversion completes The completion of conversion can also be checked with the ADI bit in the ADCI register To activate A D conversion functions follow one of the methods given below e Activation using the AD bit in th
341. er Table 13 4 2 Register and Vector Table Related to Interrupts of Watch Counter Interrupt Interrupt level setting register Vector table address Interrupt source request number Register Setting bit IRQ20 ILRS FFD2 FFD3g The watch counter shares the same interrupt request number and vector table as the watch prescaler Refer to CHAPTER 8 INTERRUPTS for the interrupt request numbers and vector tables of all peripheral functions CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 177 CHAPTER 13 WATCH COUNTER 18 5 Explanation of Watch Counter Operations and Setup MB95130 MB Series Procedure Example 13 5 Explanation of Watch Counter Operations and Setup Procedure Example The watch counter counts down for the number of times specified in the count value by RCTR5 to RCTRO bits using the count clock selected by CS1 and CSO bits when the ISEL bit is set to 1 Once the counter underflows WCFLG bit of the WCSR register is set to 1 generating an interrupt Setup Procedure of Watch Counter The setup procedure of the watch counter is described below 1 Select the count clock CS1 and CSO bits and set the counter reload value RCTRS5 to RCTRO bits 2 Set the ISEL bit of the register to 1 to start a down count and enable interrupts Also disable interrupts of the watch prescaler The watch counter performs counting by using a divided clock asynchronous from the watch prescaler An error of
342. er SMR LIN UART serial status register SSR LIN UART extended status control register ESCR LIN UART extended communication control register ECCR 358 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 2 Configuration of LIN UART LIN UART Block Diagram Figure 22 2 1 LIN UART Block Diagram OTO EXT ORE FRE REST TIE Transmit clock Reload Reception clock counter Reception contro control circuit circuit 3 circuit Y Y us E RBI i 1 bcd Transmit irit start circuit lt Reception 1 f f 1 IRQ i Reception i Transmit Transmission reload counter bit counter bit counter 7 IRQ i SOT sampling gt e i ta gt Pin circuit lt Parity counter parity counter E om 077777 7 RDRF SOT Internal signal SIN to 8 16 bit compound timer LiINbrea c4 h Fiel rni i Reception Transmit LIN break circuit shift register shift register generation i Start CT transmis ww Error i detection TDR ion s Bus idle LBR detection LBL1 i LBLO PE ir ERES S apes Internal data bus DES af as PE MD1 ORE MDO Pa Roar e SSR 41 SMR SUR ESCR sope ECCR ister i register register i regis REST register SSM register BDS UPCL RIE SCKE M TIE SOE
343. er 00 01 data register and counter It incorporates a latch to temporarily store the 8 16 bit compound timer 00 01 data register value 8 16 bit compound timer 00 01 data register The 8 16 bit compound timer 00 01 data register is used to write the maximum value counted during interval timer or PWM timer operation and to read the count value during PWC timer or input capture operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 199 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 2 Configuration of 8 16 bit Compound Timer MB951 30 MB Series 8 16 bit compound timer 00 01 control status registers 0 TOOCRO TO1CRO These registers are used to select the timer operation mode select the count clock and to enable or disable IF flag interrupts 8 16 bit compound timer 00 01 control status registers 1 TOOCR1 TO1CR1 These registers are used to control interrupt flags timer output and timer operation 8 16 bit compound timer 00 01 timer mode control register TMCRO This register is used to select the noise filter function 8 bit or16 bit operation mode and signal input to timer 00 and to indicate the timer output value Output controller The output controller controls timer output The timer output is supplied to the external pin when the pin output has been enabled Q Control logic The control logic controls timer operation Count clock selector The selector selects the counter operation clock signal from among prescaler outputs
344. er output is inverted and the interrupt request occurs When the counter continues to count until reaching FFy it restarts counting from 00g to continue the counting operation The timer outputs a square wave as a result of this repeated operation E PWM Timer Function Fixed cycle Mode When the PWM timer function fixed cycle mode is selected a PWM signal with a variable H pulse width is generated in fixed cycles The cycle is fixed to FFy during 8 bit operation or FFFFg during 16 bit operation The time is determined by the count clock selected The H pulse width is specified by setting a register PWM Timer Function Variable cycle Mode 196 When the PWM timer function variable cycle mode is selected two 8 bit counters are used to generate an 8 bit PWM signal in any cycles and duty depending on the cycle and L pulse width specified by registers In this operation mode the compound timer cannot serve as a 16 bit counter as two 8 bit counters are used FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 1 Overview of 8 16 bit Compound Timer PWC Timer Function When the PWC timer function is selected the width and cycle of an external input pulse can be measured In this operation mode the counter starts counting from 00g upon detection of a count start edge of an external input signal and transfers the count value to a register to generate an interrupt
345. eration TOOCR1 TO1CRI STA 1 The clock selection of TO1CRO timer 01 is nullified during 16 bit operation These bits cannot be set to 111g when the PWC or input capture function is used An attempt to write 111g with the PWC or input capture function in use resets the bits to 0005 The bits are also reset to 0005 if the timer enters the input capture operation mode with the bits set to 111g Count clock 1 x MCLK machine clock 1 2 x MCLK machine clock 1 4 x MCLK machine clock 1 8 x MCLK machine clock 1 16 x MCLK machine clock 1 32 x MCLK machine clock 1 2 x Foy External clock C2 CO Count clock select bits ojl ol ol o ol ool o ojl ol 5 206 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 5 Registers of 8 16 bit Compound Timer Table 15 5 1 Functional Description of Each Bit of 8 16 bit Compound Timer 00 01 Control Status Register 0 TOOCRO TO1CR0O 2 2 Bit name Function These bits select the timer operation mode The PWM timer function variable cycle mode F2 Fl FO 01005 is set by either the TOOCRO timer 00 register or TO1CRO timer 01 register In this case the other register is set to F2 F1 FO 0100g automatically when the timer starts operation TOOCR1 TOICRI STA 1 The MOD bit is set to 0 automatically when th
346. eration code of XCHW A PC is stored This is why 12354 is stored instead of 12344 Figure E 2 6 shows an assembler language example CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 511 APPENDIX APPENDIX E Instruction Overview MB95130 MB Series Figure E 2 6 Example of Using XCHW A PC Main routine Subroutine MOVW A PRUTSUB eser o PUTSUB XCHW A EP XCHW A PC PUSHW A DB PUT OUT DATA EOL PTS1 MOV A EP MOVW A 1234H INCW EP MOV IO A Output table data here CMP A EOL BNE PTS1 POPW A XCHW A EP JMP A CALLV vct This instruction is used to branch to a subroutine address stored in the vector table The instruction saves the return address contents of PC in the location at the address contained in SP stack pointer and uses vector addressing to cause a branch to the address stored in the vector table Because CALLV vct is a 1 byte instruction the use of this instruction for frequently used subroutines can reduce the entire program size Figure E 2 7 shows a summary of the instruction Figure E 2 7 Example of Executing CALLV 3 Before executing After executing 5678H FED SP 1234 r 2 SP 1232 1232H 1232H 56 1233H 1233H 79H FFC6H FEH FFC6H FEH FFC7H DCH FFC7H DCH After the CALLV vct instruction is executed the conten
347. eration of 8 bit Prescaler 8 bit PPG Mode Count clock A A k k k k k k k ae ae ae Oe ae Cycle T PENO1 1 Cycle setting 501 1 4 Duty setting 1 2 PDS01 1 timer 01 Xe X 2X 1X 4X 3X 2X 1X 4X 3 X 2X 1X 4X 3X 2X 1X 4 X counter value Down counter value matches matches duty r setting value Counter borrow PPG output source Normal polarity Lo T Synchronizing with machine clock Inversion polarity 1 1 i q4 1 1 1 gt 2 Cycle setting t PPsoo mo 3 Duty setting 1 PDsoo 9 2 i PPG timer 00 T n counter value X 2 X 1 X B X 2 X 1 X 3 X Down counter value iJ matches matches duty setting value Counter borrow t Do 1 1 PPG output source i i Synchronizing with machine clock 1 1 Normal polarity 1 i Inversion polarity i i 1 gt 3 M m 4 1 1 x T T Count clock cycle The value changes depending on the count 2 m1xT m0 PPSOO register value clock selected and the PENO 1 start timing
348. erations and Setup Procedure Example of LIN UART MB951 30 MB Series When the counter of the 8 16 bit compound timer is overflowing BGR value max b a 8 1 max Maximum value of free run timer a TIIO data register value after the first interrupt b TIIO data register value after the second interrupt Note Do not set the baud rate if the new BGR value calculated based on Synch field as above in LIN slave mode involves an error over 15 For the operations of the input capture function on the 8 16 bit compound timer see Section 15 13 Operating Description of Input Capture Function LIN synch break detection interrupt and flag The LIN break detection LBD flag in ESCR is set to 1 when the LIN synch break is detected in slave mode When the LIN break interrupt is enabled LBIE 1 an interrupt is generated Figure 22 7 7 Timing of LIN Synch Break Detection and Flag Set Serial clock I Serial input LIN bus Bn clear by CPU LBD l LSYN SYN Synch break for 14 bits setting Synch field 4 gt TIIO input The above diagram shows the timing of the LIN synch break detection and flag Since the data framing error FRE flag bit in SSR generates a reception interrupt two bits earlier than a LIN break interrupt for communication format is 8 bit data no parity 1 stop bit set the RXE to 0 when a LIN break is
349. erforms shift operation using the selected serial clock as a shift clock To input the external clock signal set the SCKE bit to 0 To output the dedicated baud rate generator output as a shift clock signal set the SCKE bit to The serial clock signal is obtained by dividing clock by two which is supplied by the dedicated baud rate generator The baud rate in the SIO mode can be set in the following range For more information about the dedicated baud rate generator also refer to CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR Table 20 7 4 Baud Rate Setting Range in SIO Mode 01401 to FFy 255 004 256 00g to 11g The highest and lowest baud rate settings are Oly and 00y respectively The baud rate applied when the external clock or dedicated baud rate generator is used is obtained from the corresponding equation illustrated below Figure 20 7 9 Figure 20 7 10 Figure 20 7 9 Calculating Baud Rate Based on External Clock 1 Baud rate bps External Clock More than 4 machine clock External Clock lt lt More than 4 machine clock 336 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example Figure 20 7 10 Baud Rate Calculation Formula for Using Dedicated Baud Rate Generator Machine clock MCLK Baud rate 2X Prescaler selection PSS1 PSSO
350. eries for details about the states of all pins during a reset CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 89 CHAPTER 7 RESET 7 2 Reset Source Register RSRR MB95130 MB Series 7 2 Reset Source Register RSRR The reset source register indicates the source or factor causing a reset that has been generated E Configuration of Reset Source Register Figure 7 2 1 Reset Source Register RSRR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value 009 csvr EXTS WDTH PONR HWR SWR XXXXXXXXe RO WX RO WX RW RW RW RW RW RW SWR Software reset flag bit Read Write 0 Writing sets the bit to O 1 Factor is software reset Hardware reset flag bit Read Write Writing sets the bit to 0 Factor is hardware reset Power on reset flag bit PONR Read Write 0 Writing sets the bit to 0 1 Factor is power on reset Watchdog reset flag bit Read Write Writing sets the bit to 0 Factor is watchdog reset External reset flag bit Read Write Writing sets the bit to 0 Factor is external reset Clock supervisor reset flag bit Read Write Factor is clock supervisor Writing sets the bit to 0 reset R W Readable writable RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined X Indeterminate 90 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 7 RESET MB95130
351. ernal interrupt pins Note If more than one interrupt pin are selected in WICR interrupt pin selection circuit control register simultaneously an input to INTOO ch 0 of the external interrupt circuit is treated as H if any of the selected input signals is H It becomes OR of the signals inputted to the selected pins CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 309 CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT 19 6 Notes on Using Interrupt Pin Selection Circuit MB951 30 MB Series 19 6 Notes on Using Interrupt Pin Selection Circuit This section explains the precautions to be taken when using the interrupt pin selection circuit E Notes on Using Interrupt Pin Selection Circuit If more than one interrupt pin are selected in WICR interrupt pin selection circuit control register simultaneously and the operation of INTOO ch 0 of the external interrupt circuit is enabled the values other than 00g are set to SLO1 SLOO bits in EICOO register of external interrupt circuit and the interrupt is enabled by writing 1 to the EIEO bit when selecting the valid edge the selected pins will remain enabled to perform input so as to accept interrupts even in a standby mode If more than one interrupt pin are selected in WICR interrupt pin selection circuit control register simultaneously an input to INTOO ch 0 of the external interrupt circuit is treated as H level if any of the selected input signals is H lev
352. errupt can be input SPL Pin state specification bit in standby control register STBC SPL I O port peripheral function I O Hi Z Pin state Input disabled Hi Z High impedance Input disabled means the state that the operation of the input gate close to the pin is disabled 114 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series 9 3 Port 1 CHAPTER 9 I O PORT 9 3 Port 1 Port 1 is a general purpose I O port This section focuses on functions as a general purpose 1 0 port See the chapters on each peripheral function for details about peripheral functions E Port 1 Configuration Port 1 is made up of the following elements e General purpose I O pins peripheral function I O pins e Port 1 data register PDR1 Port 1 direction register DDR1 Port 1 pull up control register PUL1 Input level selection register ILSR Input level selection register 2 ILSR2 E Port 1 Pins Port 1 has seven I O pins Table 9 3 1 lists the port 1 pins Table 9 3 1 Port 1 Pins I O type Pin name Function Shared peripheral functions Input Output PIO UIO P10 general purpose 010 UART SIO ch 0 data input t MOS GRIOS Automotive P11 UOO P11 general purpose I O UOO UART SIO ch 0 data output Hysteresis Automotive CMOS p12 UART SIO ch 0 clock I O UCKO ECO P12 general purpose I O ECO 8 16 bit compound time
353. errupt causes used in MB95130 MB series E Table of Interrupt Causes Refer to CHAPTER 5 CPU for interrupt operation Table B 1 MB95130 MB Series Interrupt Address Bit name of The same level Interrupt causes request of vector table interrupt level priority number Upper Lower setting register Concurrence External interrupt ch 0 External interrupt ch 4 External interrupt ch 1 External interrupt ch 5 External interrupt ch 2 External interrupt ch 6 External interrupt ch 3 External interrupt ch 7 UART SIO ch 0 8 16 bit compound timer ch 0 lower 8 16 bit compound timer ch 0 upper LIN UART reception LIN UART transmission Not used Not used Not used 8 16 bit PPG ch 0 lower 16 bit PPG ch 0 Not used Not used 10 bit A D Time base timer Watch prescaler counter Not used Not used Flash memory 498 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX C Memory Map APPENDIX C Memory Map This section shows the memory map of MB95130 MB series E Memory Map Figure C 1 Memory Map MB95F133MBS F133NBS F133JBS MB95F134MBS F134NBS F134JBS MB95FV100D 101 MB95136MB MB95F136MBS F136NBS F136JBS MB95FV100D 103 MB95F133MBW F133NBW F133JBW MB95F134MBW F134NBW F
354. ers Data of up to three different addresses can be modified The wild register function can be used to debug the program after creating the mask and patch bugs in the program 184 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 14 WILD REGISTER MB95130 MB Series 14 2 Configuration of Wild Register 14 2 Configuration of Wild Register The block diagram of the wild register is shown below The wild register consists of the following blocks e Memory area block Wild register data setup register WRDRO to WRDR2 Wild register address setup register RARO to WRAR2 Wild register address compare enable register WREN Wild register data test setup register WROR Control circuit block E Block Diagram of Wild Register Function Figure 14 2 1 Block Diagram of Wild Register Function Wild register function Decoder and logic Address control circuit compare circuit i Memory area block Wild register address 2 setup register _ WRAR Wild register data setup 1 Ei register Internal bus ntrol circuit i Wild register address gt compare enable register WREN Wild register data test setup register WROR WRDR Access i _ Memory space CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 185 CHAPTER 14 WILD REGISTER 14 2 Configuration of Wild Register MB95130 MB Series Memory area block The memory area block consists of the wild register data set
355. ers causes the reload counter to start counting Note Write to this register when LIN UART stops 378 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 5 Interrupt of LIN UART 22 5 Interrupt of LIN UART The LIN UART has reception interrupts and transmit interrupts which are generated by following factor and have the assigned interrupt number and interrupt vector Also it has the LIN synch field edge detection interrupt function using the 8 16 bit compound timer interrupt e Reception interrupt When the received data is set in the reception data register RDR or when a reception error occurs Also when a LIN synch break is detected Transmit interrupt When the transmit data is transferred from the transmit data register TDR to the transmission shift register and the transmission starts E Reception Interrupt Table 22 5 1 shows the interrupt control bits and interrupt factors of reception interrupts Table 22 5 1 Interrupt Control Bits and Interrupt Factors of Reception Interrupts Interrupt request flag bit Operation mode Interrupt Interrupt source factor enable bit Flag register 1 Clearing of interrupt request flag Write received data to RDR Read received data Overrun error SSR RIE Write 1 to reception Framing error error flag clear bit Parity error SCR CRE LIN synch break detection ESCR LBIE Write 0 to ESCR LBD
356. erted and the signal will be outputted to the PPGOO pin ch 0 ch 1 will be set to the initial value lt L if REVO1 is 0 or H if it is 1 gt Figure 16 7 6 shows the operation of 16 bit PPG mode Figure 16 7 6 Operation of 16 bit PPG Mode Count clock Cycle T PENOO Cycle setup Duty setu Counter value Counter borrow PPG output source PPGOO Normal polarity PPSO1 and PPS00 m 256 tup PDS01 and PDS00 n 2 Down counter value matches matches duty setting value Inversion polarity ALFA X ase X 2 X X Xs Xa X 26 X oss X X2 Xa X 256 X x Synchronizing with machine clock Y 1 a 2 1 2nxT T Count clock cycle 2 mxT m PPSO1 amp PPS00 n PDSO1 amp PDS00 The value changes depending on the count clock selected and the start timing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 259 CHAPTER 16 8 16 BIT PPG 16 8 Notes on Using 8 16 bit PPG MB951 30 MB Series 16 8 Notes on Using 8 16 bit PPG The following precautions must be followed when using the 8 16 bit PPG E Notes on Using 8 16 bit PPG Operational precaution Depending on the timing between the activation of PPG and count clock an error may occur in
357. es on Use of 8 10 bit A D Converter This section summarizes notes on using the 8 10 bit A D converter E Notes on Use of 8 10 bit A D Converter Notes on programmed setup When the A D conversion function is used the contents of the ADDH and ADDL registers are retained upon completion of A D conversion During A D conversion the values resulting from the last conversion are loaded Do not re select the analog input channel ADC1 ANS3 to ANSO while the A D conversion function is running in particular during continuous activation Disable continuous activation ADC2 EXT 0 before re selecting the analog input channel Starting the reset stop or watch mode stops the 8 10 bit A D converter and initializes each register The CPU cannot return from interrupt processing if the interrupt request flag bit ADCI ADT is 1 with interrupt requests enabled ADC2 ADIE 1 Be sure to clear the ADI bit within the interrupt processing routine Note on interrupt requests If A D conversion is reactivated ADCI1 AD 1 and terminated at the same time the interrupt request flag bit ADC1 ADI is set Error As IAVR AV ssl decreases an error increases relatively 8 10 bit A D converter and analog input power on shut down sequences Turn on the 8 10 bit A D converter power supply AVss and analog input to at the same as or after turning on the digital power supply Voc In addition turn
358. es the sub clock divided by two as its count clock Counter clear circuit This circuit controls the clearing of the watch prescaler Interval timer selector This circuit selects one out of the four bits used for the interval timer among 15 bits available in the watch prescaler counter Watch prescaler control register WPCR This register selects the interval time clears the counter controls interrupts and checks the status B Input Clock The watch prescaler uses the sub clock divided by two as its input clock count clock Bi Output Clock The watch prescaler supplies its clock to the timer for the oscillation stabilization wait time of the sub clock the watchdog timer and the watch counter 158 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER MB95130 MB Series 12 3 Registers of the Watch Prescaler 12 3 Registers of the Watch Prescaler Figure 12 3 1 shows the register of the watch prescaler E Register of the Watch Prescaler Figure 12 3 1 Register of the Watch Prescaler Watch Prescaler Control Register WPCR R W Readable writable Read value is the same as write value RMW instruction bit7 bit6 bit5 bit4 bit3 bit2 bit bito 000B4 WTIF WTIE WTC1 WTCO WCLR R RM1 W R W RO WX RO WX RO WX R W R W RO W Initial value 000000005 R RM1 W Readable writable Read value is different from write value 1 is read
359. escribes the registers of the 16 bit PPG timer E Registers of 16 bit PPG Timer Figure 17 5 1 Registers of 16 bit PPG Timer 16 bit PPG down counter register upper PDCRH Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value PDCRHO DC15 DC14 DC13 DC12 DC11 DC10 DCO9 DC08 000000008 R WX R WX R WX R WX R WX R WX R WX R WX 16 bit PPG down counter register lower PDCRL Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OFAB PDCRLO DC07 DC06 DC05 DC04 DCO3 DCO1 000000008 R WX R WX R WX R WX R WX R WX R WX R WX 16 bit PPG cycle setting buffer register upper PCSRH Address bitiS biti4 biti3 bit12 bitii bitiO bit9 bit8 Initial value OFAC PCSRHO C815 C814 C813 C812 CS11 CS10 C809 CS08 11111111 RW RW RW RW RW RW RW RW 16 bit PPG cycle setting buffer register lower PCSRL Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OFADy PCSRLO CS07 506 505 C804 CS03 502 501 500 111111118 RW RW RW RW RW RW RW RW 16 bit PPG duty setting buffer register upper PDUTH Address bitlb biti4 biti3 biti2 bitii bitiO bit9 bit8 Initial value OFAE PDUTHO DU15 DU14 DU13 DU12 DU11 DU10 DUO9 DUO8 11111111 RW RW RW RW RW RW RW RW
360. eset software reset or external reset caused in main clock mode or main PLL clock mode however the device does not wait for the main clock oscillation stabilization wait time to elapse The device enters sub clock mode when the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 00g Note however that the device waits for the sub clock oscillation stabilization wait time to elapse before entering sub clock mode either if the sub clock has been stopped according to the setting of the sub clock oscillation stop bit in the system clock control register SYCC SUBS in main clock mode or if the sub clock oscillation stabilization wait time has not passed immediately after the power is turned on When the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 01g the device enters sub PLL clock mode after waiting for the sub PLL clock oscillation stabilization wait time Note however that the device does not wait for the sub PLL clock oscillation stabilization wait time to elapse if the sub PLL clock has been oscillating according to the setting of the sub PLL clock oscillation enable bit in the PLL control register PLLC SPEN in main clock mode Note also that the device waits for the sub clock oscillation stabilization wait time to elapse before entering sub PLL clock mode either if the sub clock has been stopped according to the setting of the sub clock oscilla
361. esetting Oscillation circuit input Oscillation circuit output Oscillation circuit input Oscillation circuit output Mode input Mode input Mode input Mode input Mode input Mode input Mode input Reset input Reset input Reset input Reset input Reset input Reset input Reset input I O port peripheral function I O Analog input CM26 10118 3E I O port peripheral function I O Analog input I O port peripheral function I O Analog input Hi Z However the setting of the pull up is effective Input interception However an external interrupt can be input when the external interrupt is enable I O port peripheral function I O Analog input FUJITSU MICROELECTRONICS LIMITED Hi Z However the setting of the pull up is effective Input interception However an external interrupt can be input when the external interrupt is enable Hi Z Input disable 2 501 APPENDIX APPENDIX D Pin Status of MB95130 MB series MB95130 MB Series Table D 1 Pin Status in Each Mode 2 2 Stop mode Watch mode Normal While Pin name operation I O port peripheral function I O Sleep mode I O port peripheral function I O SPL 0 I O port peripheral function I O SPL 1 Hi Z However the setting of the pull up is effective Input interception SPL 0 I O p
362. ess of the main clock stop detection bit CSVCR MM enables user programs to control the Fail Safe routine Figure 25 4 2 shows the example startup flowchart when using the clock supervisor Figure 25 4 2 Example Startup Flowchart when using the Clock Supervisor Reset generated Fail Safe routine PLL use prohibited Main routine PLL clock Main routine main clock 462 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 25 CLOCK SUPERVISOR MB95130 MB Series 25 5 Notes on Using Clock Supervisor 25 5 Notes on Using Clock Supervisor Take note of the following points when using the clock supervisor E Notes on Using Clock Supervisor Points to Note when using the Clock Supervisor CM26 10118 3E Operation of the clock supervisor at power on When the power is turned on the clock supervisor starts monitoring after the oscillation stabilization wait time for the main clock has elapsed Therefore unless the operation continues for longer than the oscillation stabilization wait time for the main clock the clock supervisor will not operate Transition to CR clock mode Do not turn on the PLL after changing to CR clock mode As the frequency is below the lower limit for the input frequency of the PLL circuit the PLL operation will not be guaranteed Disabling the CR oscillation Do not use the CR oscillation enable bit CSVCR RCE to disable the CR oscillation during CR clock mode
363. etting 16 bit PPG 258 Setting 8 bit Independent Mode 254 Setting 8 bit Prescaler 8 bit PPG Mode 256 Single chip Mode cece sees eee 32 Standby Mode vidiri eee 50 N Nested Interrupts Nested ee 102 NOP Instructions Place at Least Three NOP Instructions Immediately Following a Standby Mode Setting Instruction eee edis 71 Note Difference Points among Products and Notes on Selecting a 7 Notes Notes on Using 16 bit PPG Timer 282 Notes on Using 8 16 bit Compound buic TEENS 236 Notes on Using 8 16 bit PPG 260 Notes on Using External Interrupt eee rta rte tire evite ide eee 298 Interval Timer Function One shot Mode 196 One shot Mode MDSE of PCNTHO Register bit 5 D cac e nrbe tinea 280 Operation of Interval Timer Function One shot Mode 219 Operation Arithmetic Operation Instructions 516 Interrupt During Operation of External Interrupt evi mE 295 Operation of 16 bit PPG Mode 259 Operation of 8 bit PPG Independent Mode 254 Operation of 8 bit Prescaler 8 bit PPG MOde iiti costes 256 Operation of Exter
364. ey 10MHz Cycle Foy 16MHz Cycle Foy 216 25MHz Source Cycle MCLK 10MHz MCLK 16MHz MCLK 16 25MHz 2 MCLK MCLK 2 5MHz MCLK 2 8MHz MCLK 2 8 125MHz 4 MCLK MCLK 4 2 5MHz MCLK 4 4MHz MCLK 4 4 0625MHz 8 MCLK MCLK 8 1 25MHz MCLK 8 2MHz MCLK 8 2 0313MHz 16 MCLK MCLK 16 0 625MHz MCLK 16 1MHz MCLK 16 1 0156MHz 32 MCLK MCLK 32 0 3125MHz MCLK 32 0 5MHz MCLK 32 0 5078MHz 277 Foy Foy 27 78kHz Foy 27 125kHz Foy 27 127kHz 28 Foy Foy 28 39kHz Foy 28 62 5kHz Foy 28 63 5kHz CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 83 CHAPTER 6 CLOCK CONTROLLER 6 13 Notes on Use of Prescaler MB95130 MB Series 6 13 Notes on Use of Prescaler This section gives notes on using the prescaler The prescaler uses the machine clock and time base timer clock and operates continuously while these clocks are running Accordingly the operations of individual peripheral resources immediately after they are activated may involve an error of up to one cycle of the clock source captured by the resource depending on the prescaler output value Figure 6 13 1 Clock Capturing Error Immediately after Activation of Peripheral Resources Prescaler output ee Pi Resource activation 1 1 1 1 Clock capturing by resource lt gt 1 1 1 Clock capturing error immediately after resource activation The prescaler count valu
365. f Interval Timer Function in 8 bit Mode Timer 0 Counter value FFH 80H 00H t i Time Timer cycle ifi TOODR TO1DR y e value modified FFH 80H value FFH 1 ele i i i 1 1 1 1 e cc XL Automatically cleared Reactivated Automatically cleared Reactivated 1 1 1 Inverted 1 1 1 1 1 Reactivated with output initial value unchanged 0 1 1 1 Timer output For initial value 1 on activation If the TOODR TO1DR data register value is modified during operation the new value is used from the next active cycle 220 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 8 Operating Description of Interval Timer Function Continuous Mode 15 8 Operating Description of Interval Timer Function Continuous Mode This section describes the interval timer function continuous mode operation of the 8 16 bit compound timer E Operation of Interval Timer Function Continuous Mode The compound timer requires the register settings shown in Figure 15 8 1 to serve as the interval timer function continuous mode Figure 15 8 1 Settings for Counter Function 8 bit Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO 0 0 0 1 TOOCR1 T01CR1 STA HO IE IR BF IF SO OE 1 TMCRO TO1 TOO IIS MOD FE11
366. f the watchdog timer WDTC CS1 CSO 00g or CSI CSO 015 clearing the time base timer also clears the watchdog timer Q Peripheral functions receiving clock from time base timer In the mode where the source oscillation of the main clock is stopped the counter is cleared and the time base timer stops operation In addition if the time base timer is cleared when the output of the time base timer is used in other peripheral functions this will affect the operation such as cycle change The clock for the watchdog timer is also outputted from the initial state However as the watchdog timer counter is cleared at the same time the watchdog timer operates in the normal cycles CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 143 CHAPTER 10 TIME BASE TIMER 10 6 Notes on Using Time base Timer MB951 30 MB Series 144 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 11 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer 11 1 Overview of Watchdog Timer 11 2 Configuration of Watchdog Timer 11 3 Register of The Watchdog Timer 11 4 Explanation of Watchdog Timer Operations and Setup Procedure Example 11 5 Notes on Using Watchdog Timer Code CM26 00106 3E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 145 CHAPTER 11 WATCHDOG TIMER 11 1 Overview of Watchdog Timer MB95130 MB Series 11 1 Overview of Watchdog Timer The watchdog timer functions as a counter used to prevent pro
367. fer Instructions MNEMONIC Operation OPCODE dir A dir lt A GIX off A IX off A ext A ext A EP A lt A Ri A Ri lt A A 48 A d8 A dir A lt dir IX off A lt IX off A ext A lt ext GA A C A A EP A A Ri A lt Ri dir 48 dir d8 IX off d8 off d8 GEP 48 EP d8 Ri d8 Ri d8 dir A dir lt AH dir 1 lt AL GIX off A IX off lt IX off 1 lt AL ext A ext lt AH ext 1 lt AL EP A lt AH EP 1 lt AL lt 416 416 dir lt dir AL lt dir 1 IX off lt IX off AL IX off 1 A ext AH lt ext AL lt ext 1 A A AH A AL lt D A EP 3 lt EP AL e EP D A EP lt EP EP 416 d16 IX A X lt A A lt IX SP lt A lt SP lt lt 1 lt TD TX 416 DO dl6 A PS lt PS PS A PS A SP 416 SP dl6 AH AL dir b1 dir 6 lt 0 AL TL A gt EP lt
368. fer Register PDSOI PDSO0 249 PDUTHO PDUTLO 16 bit PPG Duty Setting Buffer Registers Upper Lower PDUTHO PDUTLO 272 Peripheral function Interrupt Requests from Peripheral Resources 96 Peripheral Resources Not Affected by Clock Mode49 Pin Block Diagram of LIN UART Pins 364 Block Diagram of Pins Related to 8 10 bit A D Converter Block 432 Block Diagram of Pins Related to 8 16 bit Compound iai teen cape tma 203 Block Diagram of Pins Related to 8 16 bit PPG see 242 Block Diagram of Pins Related to External Interrupt CUCU O 291 Block Diagram of Pins Related to UART SIO 317 Block Diagrams of Pins Related to 16 bit PPG internen 268 Pin 23 532 Pin State During a 89 Pin States in Standby Mode 70 Pins of 16 bit PPG 268 Pins of 8 10 bit A D Converter 431 Pins of 8 16 bit PPG sese 242 Pins Related to 8 16 bit Compound Timer 202 Pins Related to External Interrupt Circuit 291 Pins Related to Interrupt Pin Selection Circuit 304 Pins related to 363 Pins Related to Low voltage Detection
369. from the main clock mode or main PLL clock mode to the stop mode When moving from the main clock mode or main PLL clock mode to the sub clock mode or sub PLL clock mode At power on Atlow voltage detection reset The counter of the time base timer is also cleared and stops the operation if a reset occurs while the main clock is still running after the main clock oscillation stabilization wait time has elapsed The counter however continues to operate during a reset if a count is required for the oscillation stabilization wait time E Operating Examples of Time base Timer Figure 10 5 2 shows operating examples of operation under the following conditions 1 When a power on reset is generated 2 When entering the sleep mode during the operation of the interval timer function in the main clock mode or main PLL clock mode 3 When entering the stop mode during the main clock mode or main PLL clock mode 4 When a request is issued to clear the counter The same operation is performed when changing to the time base timer mode as for when changing to the sleep mode In the sub clock mode sub PLL clock mode main clock mode and main PLL clock mode the timer operation is stopped during the stop mode as the time base timer is cleared and the main clock halts Upon recovering from the stop mode the time base timer is used to count the oscillation stabilization wait time CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 141 CHAPTER 10 TIME B
370. from the standby mode when a valid edge pulse is inputted to the pins For information about the standby modes refer to 6 8 Operations in Low power Consumption Modes Standby Modes Note The input signals to the peripheral pins do not generate an external interrupt even when 1 is written to these bits if the INTOO ch 0 of the external interrupt circuit is disabled Do not modify the values of these bits while the INTOO ch 0 of the external interrupt circuit is enabled If modified the external interrupt circuit may detect a valid edge depending on the pin input level If more than one interrupt pin are selected in WICR interrupt pin selection circuit control register simultaneously and the operation of INTOO ch 0 of the external interrupt circuit is enabled the values other than 00g are set to 5101 5100 bits in EICOO register of external interrupt circuit and the interrupt is enabled by writing 1 to the EIEO bit when selecting the valid edge the selected pins will remain enabled to perform input so as to accept interrupts even in a standby mode 308 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT MB95130 MB Series 19 5 Operating Description of Interrupt Pin Selection Circuit 19 5 Operating Description of Interrupt Pin Selection Circuit The interrupt pins are selected by setting WICR interrupt pin selection circuit control register E Operation of Interrupt P
371. ft register and the transmission starts If the transmit data empty flag SSR TDREB is 1 the next transmit data can be written If the transmit interrupt is enabled a transmit interrupt is generated The next transmit data should be written by generating the transmit interrupt or when the transmit data empty flag SSR ITDRE is 1 Note The LIN UART transmit data register is a write only register the reception data register is a read only register Since both registers are located at the same address the write value and read value are different Thus the instructions to operate the read modify write RMW instruction such as the INC DEC instruction cannot be used CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 373 CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series 22 4 5 LIN UART Extended Status Control Register ESCR The LIN UART extended status control register ESCR has the settings for enabling disabling LIN synch break interrupt LIN synch break length selection LIN synch break detection direct access to the SIN and SOT pins continuos clock output in LIN UART synchronous clock mode and sampling clock edge B Bit Configuration of LIN UART Extended Status Control Register ESCR Figure 22 4 6 shows the bit configuration of the LIN UART extended status control register ESCR Table 22 4 4 lists the function of each bit in LIN UART extended status control register ESCR Figure 22 4
372. g A XXX XH N 7 1234 Old PC 1233H i New PC 12344 When this instruction is executed the content of A reaches the same value as the address where the following instruction is stored rather than the address where operation code of this instruction is stored Therefore in Figure E 2 2 the value 12344 stored in A corresponds to the address where the following operation code of MOVW A PC is stored MULU A This instruction performs an unsigned multiplication of AL lower 8 bit of the accumulator and TL lower 8 bit of the temporary accumulator and stores the 16 bit result in A The contents of T temporary accumulator do not change The contents of AH higher 8 bit of the accumulator and TH higher 8 bit of the temporary accumulator before execution of the instruction are not used for the operation The instruction does not change the flags and therefore care must be taken when a branch may occur depending on the result of a multiplication 510 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX E Instruction Overview Figure E 2 3 shows a summary of the instruction Figure E 2 3 MULUA Before executing After executing A 5678H A 1860H 1234 1234 DIVUA This instruction divides the 16 bit value in T by the unsigned 16 bit value in A and stores the 16 bit res
373. g 01 Toggle gt Stop 0 1 completed Abnormal Write DQ7 Toggle 1 operation Chip erase 0 Toggle 1 472 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 5 Checking the Automatic Algorithm Execution Status 26 5 1 Data Polling Flag DQ7 The data polling flag DQ7 is a hardware sequence flag used to indicate that the automatic algorithm is being executing or has been completed using the data polling function E Data Polling Flag 007 Table 26 5 3 and Table 26 5 4 show the state transition of the data polling flag Table 26 5 3 State Transition of Data Polling Flag During Normal Operation Chip erase gt Erasing completed XY Programming gt Programming completed Operating state Table 26 5 4 State Transition of Data Polling Flag During Abnormal Operation At programming When read access takes place during execution of the automatic write algorithm the flash memory outputs the inverted value of bit7 in the last data written to DQ7 If read access takes place on completion of the automatic write algorithm the flash memory outputs bit7 of the value read from the read accessed address to DQ7 At chip erasing When read access is made to the sector currently being erased during execution of the chip erase automatic algorithm bit7 of flash memory outputs 0 Bit7 of flash memory outputs 1 upon completion of chip erasing Note Once the aut
374. g state causes a transition Depending on the state transition however the clock controller does not always wait for the oscillation stabilization wait time For details on state transitions see Sections 6 7 Clock Mode and 6 8 Operations in Low power Consumption Modes Standby Modes CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 53 CHAPTER 6 CLOCK CONTROLLER 6 3 System Clock Control Register SYCC MB95130 MB Series 6 3 System Clock Control Register SYCC The system clock control register SYCC is used to indicate and switch the current clock mode select the machine clock divide ratio and control sub clock oscillation in main clock mode and main PLL clock mode E Configuration of System Clock Control Register SYCC Figure 6 3 1 Configuration of System Clock Control Register SYCC Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value 0007 1010x0115 R WX R WX RW R W R WX RW R W R W Machine clock divide ratio selection bits Source clock Source clock 4 Source clock 8 Source clock 16 SUBS Sub clock oscillation stop bit 0 Starts sub clock oscillation 1 ENT Stops sub clock oscillation Sub clock oscillation stability bit Indicates the sub clock oscillation stabilization wait state or sub clock oscillation being stopped Indicates sub clock oscillation being stable Cock mode selection bits Sub clock mode Sub PLL clock mode Main clock mode Main
375. g transmission the transmission operation will be immediately disabled and initialization will be performed The transmission completion flag TCPL will be set to 1 and the transmission data register empty TDRE bit will also be set to 1 RIE Reception interrupt enable bit Setting the bit to 0 disables reception interrupt Setting the bit to 1 enables reception interrupt A reception interrupt occurs immediately after either the receive data register full bit or an error flag PER OVE FER is set to 1 with this bit set to 1 enabled TCIE Transmission completion interrupt enable bit Setting the bit to 0 disables interrupts by the transmission completion flag Setting the bit to 1 enables interrupts by the transmission completion flag A transmission interrupt occurs immediately after the transmission completion flag TCPL bit is set to 1 with this bit set to 1 enabled TEIE Transmission data register empty interrupt enable bit Setting the bit to 0 disables interrupts by the transmission data register empty Setting the bit to 1 enables interrupts by the transmission data register empty A transmission interrupt occurs immediately after the transmission data register empty TDRE bit is set to 1 with this bit set to 1 enabled FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series CHAPTER 20 UART SIO 20 5 Registers of UART SIO 2
376. gister of Flash Memory eee 468 Sector Configuration of 256 Kbit Flash Memory 467 Flash memory products Basic Configuration of Serial Programming Connection for Flash Memory Products 484 Flash memory status register Flash memory status register ESR za eet tree ree e enit 469 Flash Microcontroller Writing to Flash Microcontroller Using Parallel Writer 521 Flash Microcontroller Programmer Example of Minimum Connection to Flash Microcontroller Programmer 490 Flash Security Flash S cutity nc eee eee ems 481 FPT 28P M17 Package Dimension of FPT 28P M17 7 12 FPT 30P M02 Package Dimension of FPT 30P M02 13 Free run Mode Interval Timer Function Free run Mode 196 Operation of Interval Timer Function Free run Mode esses 223 FSR Flash memory status register FSR Ata dais ai 469 Function Functions of External Interrupt Circuit 288 Input Capture Function esse 197 Interval Timer Function Continuous 196 Interval Timer Function Free run Mode 196 Interval Timer Function One shot Mode 196 Operation of Input Capture Function 231 Operation of Interval Timer Function Continuous Mode 221 Operation of Interval Timer Function Free run
377. gisters Related to Interrupt Pin Selection Circuit Interrupt pin selection circuit control register WICR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value OFEF INTOO SIN SCK ECO UIO UCKO TRGO 01000000g ROWX R W RW RW RW RW RW RW R W Readable writable Read value is the same as write value RO WX Undefined bit Read value is 0 writing has no effect on operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 305 CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT 19 4 Registers of Interrupt Pin Selection Circuit MB951 30 MB Series 19 4 4 Interrupt Pin Selection Circuit Control Register WICR This register is used to determine which of the available peripheral input pins should be outputted to the interrupt circuit and which interrupt pins they should serve as B Interrupt Pin Selection Circuit Control Register WICR Figure 19 4 2 Interrupt Pin Selection Circuit Control Register WICR Interrupt pin selection circuit control register WICR Address bit7 bit6 bits bit4 bit8 bit2 biti Initial value OFEFH INTO si_ sck Eco uio UCKO TRGO 010000008 RO WX R W R W RW RW RW RAN RW TRGO TRGO interrupt pin select bit 0 Deselects TRGO as interrupt input pin 1 Selects TRGO as interrupt input pin UCKO UCKO interrupt pin select bit 0 Deselects UCKO as interrupt input pin 1 Selects UCK
378. grams from running out of control Watchdog Timer Function The watchdog timer functions as a counter used to prevent programs from running out of control Once the watchdog timer is activated its counter needs to be cleared at specified intervals regularly A watchdog reset is generated if the timer is not cleared within a certain amount of time due to a problem such as the program entering an infinite loop The output of either the time base timer or watch prescaler can be selected as the count clock for the watchdog timer The interval times of the watchdog timer are shown in Table 11 1 1 If the counter of the watchdog timer is not cleared a watchdog reset is generated between the minimum time and the maximum time Clear the counter of the watchdog timer within the minimum time Table 11 1 1 Interval Times of Watchdog Timer Interval time Count clock switch bits WDTC CS1 CSO Minimum Maximum time time Count clock type Time base timer output main clock 4AMHz Watch prescaler output sub clock 2 32 768kHz WDTC CSI 0 Count clock switch bit of watchdog timer control register For information about the minimum and maximum times of the watchdog timer interval refer to 11 4 Explanation of Watchdog Timer Operations and Setup Procedure Example 146 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 11 WATCHDOG TIMER MB95130 MB Series 11 2 Configuration of Watchdog Timer 11
379. gth Synchronous Operation mode Stop bit length Data bit format No parity With parity method Normal mode 7 bits or 8 bits Asynchronous 1 bit Multiprocessor 7 bits or LSB first mode 8 bits 1 y 2 bits MSB first Normal mode 8 bits Synchronous None 1 bit 2 bits LIN mode 8 bits Asynchronous 1 bit LSB first Setting disabled 1 is the address data selection bit AD used for communication control in multiprocessor mode The MDO MD bits in the LIN UART serial mode register SMR are used to select the following LIN UART operation modes Table 22 7 2 LIN UART Operation Modes Asynchronous Normal mode Asynchronous Multiprocessor mode Synchronous Normal mode Asynchronous LIN mode Notes Both master and slave operation are supported in a system with master slave connection in mode 1 In mode 3 the communication format is fixed to 8 bit data no parity 1 stop bit LSB first f the mode is changed all transmissions and receptions are canceled and the LIN UART waits for the next operation CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 395 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series E Inter CPU Connection Method You can select either external clock one to one connection normal mode or master slave connection multiprocessor mode In either methods da
380. h prescaler is cleared and stops operation when a reset is generated E Operating Examples of Watch Prescaler 164 Figure 12 5 1 shows operating examples under the following conditions 1 When power on reset is generated 2 When entering the sleep mode during the operation of the interval timer function in the sub clock mode or sub PLL clock mode 3 When entering the stop mode during the operation of the interval timer function in the sub clock mode or sub PLL clock mode 4 When a request is issued to clear the counter The same operation is performed when changing to the watch mode as for when changing to the sleep mode FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER MB95130 MB Series 12 5 Explanation of Watch Prescaler Operations and Setup Procedure Example Figure 12 5 1 Operating Examples of Watch Prescaler Counter value count down Count value detected in WATR SWTS to SWTO Count value detected in Meu t Lu r rr rer rrr er rrr rr KC WPCR WTC1 WTCO Interval cycle WPCR WTC1 WTCO 11g 0000H Sub clock oscillation by transferring Sub clock oscillation stabilization wait time SPCR VIELE 1 to stop mode stabilization wait time 1 Power on reset Clear at interval Clear in interrupt setup processing routine mU WTIF bit WTIE bit 2 SLP bit lt
381. has no effect on operation R W Readable writable Read value is the same as write value Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 251 CHAPTER 16 8 16 BIT PPG 16 6 Interrupts of 8 16 bit PPG MB951 30 MB Series 16 6 Interrupts of 8 16 bit PPG The 8 16 bit PPG outputs an interrupt request when a counter borrow is detected Bi Interrupts of 8 16 bit PPG Table 16 6 1 shows the interrupt control bits and interrupt sources of the 8 16 bit PPG Table 16 6 1 Interrupt Control Bits and Interrupt Sources of 8 16 bit PPG Description PPG timer 01 PPG timer 00 8 bit PPG 8 bit prescaler 8 bit PPG 16 bit PPG Interrupt request flag bit PUFI bit in PUFO bit in PCO Interrupt request enable bit PIEI bit in PCI PIEO bit in PCO Interrupt source Counter borrow of PPG cycle down counter When a counter borrow occurs on the down counter the 8 16 bit PPG sets the counter borrow detection flag bit PUF in the 8 16 bit PPG timer 00 01 control register PC to 1 When the interrupt request enable bit is enabled PIE 1 an interrupt request is outputted to the interrupt controller In 16 bit PPG mode the 8 16 bit PPG timer 00 control register PCOO is available E Registers and Vector Table Related to Interrupts of 8 16 bit PPG Table 16 6 2 Registers and Vector Table Related to Interrupts of 8 16 bit PPG Interrupt Interrupt Interrupt level setup register Vector table addres
382. he 8 16 bit PPG 16 1 Overview of 8 16 bit PPG 16 2 Configuration of 8 16 bit PPG 16 3 Channels of 8 16 bit PPG 16 4 Pins of 8 16 bit PPG 16 5 Registers of 8 16 bit PPG 16 6 Interrupts of 8 16 bit PPG 16 7 Operating Description of 8 16 bit PPG 16 8 Notes on Using 8 16 bit PPG 16 9 Sample Programs for 8 16 bit PPG Timer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 237 CHAPTER 16 8 16 BIT PPG 16 1 Overview of 8 16 bit PPG MB951 30 MB Series 16 1 Overview of 8 16 bit PPG The 8 16 bit PPG is an 8 bit reload timer module that uses pulse output control based on timer operation to perform PPG output The 8 16 bit PPG also operates in cascade 8 bits 8 bits as 16 bit PPG ll Overview of 8 16 bit PPG The following section summarizes the 8 16 bit PPG functions 8 bit PPG output independent operation mode In this mode the unit can operate as 2 8 bit PPG PPG timer 00 and PPG timer 01 8 bit prescaler 8 bit PPG output operation mode The rising and falling edge detection pulses from the PPG timer 01 output can be inputted to the down counter of the PPG timer 00 to enable variable cycle 8 bit PPG output 16 bit PPG output operation mode The unit can also operate in cascade PPG timer 01 upper 8 bits PPG timer 00 lower 8 bits as 16 bit PPG output PPG output operation In this operation a variable cycle pulse waveform is outputted in any duty ratio The unit can also be used as a D A converter in
383. he current value can be read from this register In 16 bit operation set the upper data to TOIDR and lower data to TOODR And write and read TOIDR and TOODR in this order 214 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 5 Registers of 8 16 bit Compound Timer PWM timer functions variable cycle The 8 16 bit compound timer 00 data register TOODR and 8 16 bit compound timer 01 data register TOIDR are used to set L pulse width timer and cycle respectively When the timer starts operation TOOCR1 TOICRI STA 1 the value of each register is transferred to the latch in the 8 bit comparator and two counters start counting from timer output L When the TOODR value held in the latch matches the timer 00 counter value the timer output becomes H and the counting continues until the TOIDR value held in the latch matches the timer 01 counter value When the TO1DR value held in the latch of the 8 bit comparator matches the timer 01 counter value the values of these registers are transferred again to the latch and the next PWM cycle of counting is performed continuously The current count value can be read from this register In 16 bit operation set the upper data and lower data to TO1DR and TOODR respectively And write and read TOIDR and TOODR in this order PWC timer function The 8 16 bit compound timer 00 01 data register TOODR TOIDR is used to read PWC measurement re
384. he device services the interrupt when the CPU s condition code register has been set to accept interrupts If the register has been set to reject interrupts the device resumes processing from the instruction that follows the last instruction executed before entering the standby mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 71 CHAPTER 6 CLOCK CONTROLLER 6 8 Operations in Low power Consumption Modes Standby MB95130 MB Series Modes E Standby Mode State Transition Diagram Figure 6 8 1 and Figure 6 8 2 are standby mode state transition diagrams Figure 6 8 1 Standby Mode State Transition Diagram Dual Clock Product Reset state 2 1 Main clock oscillation stabilization wait time S d Normal top mode 4 Main clock main RUN state PLL clock Sub clock sub PLL Time base timer mode Reset occurs in each state Watch mode Sub PLL clock oscillation stabiliza tion wait time 2 Sleep mode clock oscillation stabilization wait time Main PLL clock oscillation stabiliza tion wait time 72 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 8 Operations in Low power Consumption Modes Standby Modes Figure 6 8 2 Standby Mode State Transition Diagram Single Clock Product Reset state 2 1 Main clock oscillation stabilization wait time 3 Normal Stop mode 4 RUN state Main clock main PLL clock osci
385. he edge polarity select bits SLO1 SLOO is inputted to the external interrupt pin INTOO When this bit and the interrupt request enable bit 0 EIEO are set to 1 an interrupt request is outputted e Writing 0 clears the bit Writing 1 has no effect e 1 is read in read modify write RMW instructions 5101 SLOO Edge polarity select bits 0 These bits are used to select the polarity of the interrupt source edge of the pulse inputted to the external interrupt pin INTOO Edge detection is not performed and no interrupt request is generated when these bits are 00g Rising edges are detected when the bits are 015 falling edges when 10g and both edges when Ilg EIEO Interrupt request enable bit 0 This bit enables or disables the output of interrupt requests to the interrupt controller An interrupt request is outputted when this bit and the external interrupt request flag bit 0 EIRO are 1 When using an external interrupt pin write 0 to the corresponding bit in the port direction register DDR to set the pin as an input The status of the external interrupt pin can be read directly from the port data register PFR regardless of the status of the interrupt request enable bit FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT MB95130 MB Series 18 6 Interrupts of External Interrupt Circuit 18 6 Interrupts of External Interrupt Circuit The
386. he following 3 bit outputs Data Polling Flag DQ7 Toggle Bit Flag DQ6 Execution Time out Flag DQ5 The hardware sequence flags tell whether the write program or chip erase command has been terminated and whether an erase code write can be performed You can reference hardware sequence flags by read access to the address of each relevant sector in flash memory after setting a command sequence Table 26 5 1 shows the bit allocation of the hardware sequence flags Table 26 5 1 Bit Allocation of Hardware Sequence Flags 5 6 872104 DOT Boe know whether the automatic write chip erase command is being executed or has been terminated check the hardware sequence flags or the flash memory program erase status bit in the flash memory status register FSR RDY After programming erasing is terminated flash memory returns to the read reset state e When creating a write erase program read data after checking the termination of automatic writing erasing with the DQ7 DQ6 and DQ5 flags Explanation of hardware sequence flag Table 26 5 2 lists the functions of the hardware sequence flag Table 26 5 2 List of Hardware Sequence Flag Functions Programming Programming u completed TAS State transition when write ad ress onn DQ7 DATA 7 Toggle DATA 6 0 DATA 5 during normal specified operation Chip erasing Erasin
387. he oscillation stabilization wait time to cancel the reset For details on the electrical characteristics see the data sheet Figure 24 4 1 Operations of Low voltage Detection Reset Circuit Vcc Detection cancellation voltage X f X ooo a Lower operating voltage limit Reset signal A Delay B Oscillation stabilization wait time E Operations in Standby Mode The low voltage detection reset circuit remains operating even in standby modes stop sleep sub clock and watch modes CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 451 CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT 24 4 Operations of Low voltage Detection Reset Circuit MB951 30 MB Series 452 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 25 CLOCK SUPERVISOR This chapter describes the functions and operations of the clock supervisor 25 1 Overview of Clock Supervisor 25 2 Configuration of Clock Supervisor 25 3 Register of Clock Supervisor 25 4 Operations of Clock Supervisor 25 5 Notes on Using Clock Supervisor Code CM26 00112 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 453 CHAPTER 25 CLOCK SUPERVISOR 25 1 Overview of Clock Supervisor MB95130 MB Series 25 1 Overview of Clock Supervisor The clock supervisor prevents the situation which is out of control when main clock and sub clock only on dual clock products oscillation
388. he period and duty of the output waveform can be changed by software freely The timer can also generate an interrupt when a start trigger occurs or on the rising or falling edge of the output waveform 16 bit PPG Timer 264 16 bit PPG timer can output the PWM output and the one shot The output wave form can be reversed by setting the register Normal polarity lt Inverted polarity Output waveform PWM waveform Normal polarity L H L Slim Inverted polarity ne H LE One shot waveform Normal polarity Ll H L Inverted polarity H L H The count operation clock can be selected from eight different clock sources MCLK 1 MCLK 2 MCLK 4 MCLK 8 MCLK 16 MCLK 32 Fop 2 or Fcp 28 MCLK Machine clock Fey Main Clock Interrupt can be selectively triggered by the following four conditions Occurrence of a start trigger in the PPG timer Occurrence of a counter borrow in the 16 bit down counter cycle match Rising edge of PPG in normal polarity or falling edge of PPG in inverted polarity Counter borrow rising edge of PPG in normal polarity or falling edge of PPG in inverted polarity FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 2 Configuration of 16 bit PPG Timer 17 2 Configuration of 16 bit PPG Timer Shown below is the block diagram of the 16 bit PPG timer E Block Diagram of 16 bit PPG Timer Figure 17 2 1 Block
389. heck the error flag status and read the received data from the LIN UART reception data register RDR if the reception is normal If a reception error occurs perform error handlings When the received data is read the reception data register full flag bit SSR RDRF is cleared to 0 When the data length is set to 7 bit 0 the bit7 in the RDR register is an unused bit regardless of the transfer direction select bit BDS setting LSB first or MSB first Note Data in the LIN UART reception data register RDR becomes valid when the reception data register full flag bit SSR RDRF is set to 1 and no error occurs SSR PE ORE FRE 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 399 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series Input clock Internal or external clock is used For the baud rate select the baud rate generator SMR EXT 0 or 1 0 Stop bit and reception bus idle flag You can select one or two stop bits at transmission When 2 bit of the stop bit are selected both of the stop bits are detected during reception When the first stop bit is detected the reception data register full flag SSR RDRF is set to 1 When no start bit is detected after that the reception bus idle flag ECCR RBI is set to indicating that the reception is not performed Error detection In mode 0 parity overrun and framing errors can be detected In
390. hen 0101 is written to the watchdog control bits of the watchdog timer control register WDTC WTE3 to WTEO for the first time after a reset The count clock switch bits of the watchdog timer control register WDTC CS1 CS0 should also be set at the same time Once the watchdog timer is activated a reset is the only way to stop its operation Clearing the watchdog timer When the counter of the watchdog timer is not cleared within the interval time it overflows allowing the watchdog timer to generate a watchdog reset The counter of the watchdog timer is cleared when 0101 is written to the watchdog control bits of the watchdog timer control register WDTC WTE3 to WTEO for the second or any succeeding time The watchdog timer is cleared at the same time as the timer selected as the count clock time base timer or watch prescaler is cleared Operations in standby mode Regardless of the clock mode selected the watchdog timer clears its counter and stops the operation when entering a standby mode sleep stop time base timer watch Once released from the standby mode the timer restarts the operation Note The watchdog timer is also cleared when the timer selected as the count clock time base timer or watch prescaler is cleared For this reason the watchdog timer cannot function as such if the software is set to clear the selected timer repeatedly during the interval time of the watchdog timer 152 FUJ
391. hen the SSM bit in the LIN UART extended communication control register ECCR is 1 the start and stop bits are added to the data format as in asynchronous mode Clock supply In clock synchronous mode normal the number of the transmit reception bits must be equal to the number of the clock cycles When the start stop bit is enabled the number of the added start stop bits must be equal as well When the serial clock output is enabled SMR SCKE 1 in sending side of serial clock ECCR MS 0 a synchronous clock is output automatically at transmission reception When the serial clock output is disabled SMR SCKE 0 in receiving side of serial clock ECCR MS 1 the clock for each bit of transmit reception data must be supplied from the outside The clock signal must remain at the mark level H as long as it is irrelevant to transmission reception Clock delay Setting the SCDE bit in the ECCR to 1 a delayed transmit clock is output as shown in Figure 22 7 5 This function is required when the receiving device samples data at the rising or falling edge of the clock Figure 22 7 5 Transmission Clock Delay SCDE 1 Write transmit data p data sample edge SCES 0 Transmit reception Mark level clock normal Transmit clock po dos 43 4 hope x Nee GcbE UOI ves a ao ad oa a a o Mark leve Transmit reception data 0 1 1 0 1
392. hibited 8 16 bit PPG startup register 8 16 bit PPG output reverse register Prohibited PDCRHO 16 bit PPG down counter register upper ch 0 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX I O Map Table A 1 MB95130 MB Series 4 4 Register name nmal abbreviation value PDCRLO 16 bit PPG down counter register lower ch 0 PCSRHO 16 bit PPG cycle setting buffer register upper ch 0 PCSRLO 16 bit PPG cycle setting buffer register lower ch 0 PDUTHO 16 bit PPG duty setting buffer register upper ch 0 PDUTLO 16 bit PPG duty setting buffer register lower ch 0 Address Prohibited LIN UART baud rate generator register 1 LIN UART baud rate generator register 0 UART SIO prescaler select register ch 0 UART SIO baud rate setting register ch 0 Prohibited A D input disable register lower Prohibited Watch counter data register 00111111g Prohibited Input level selection register 2 Prohibited Clock supervisor control register Prohibited Input level selection register Interrupt pin control register Prohibited CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 497 APPENDIX APPENDIX B Table of Interrupt Causes MB95130 MB Series APPENDIX B Table of Interrupt Causes This section describes the table of int
393. i bitio bit8 Initial value OF80 RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 00000000pg RW RW RW RW RW RW RW RW Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 81 RA7 RA6 RAS RA4 RA2 RA1 RAO 000000008 RW RW RW RW RW RW RW RW WRAR1 Address bitlb bitl4 bit12 bitii bitio bit8 Initial value OF 83 RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 00000000pg RW RW RW RW RW RW RW RW Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value OF844 RA7 RA6 RAS RA4 RA2 RA1 RAO 00000000pg RW RW RW RW RW RW RW RW WRAR2 Address bit15 biti4 bit13 biti2 bitii bitio bit8 Initial value OF86 RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 00000000pg RW RW RW RW RW RW RW RW Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 87 RA7 RA6 RAS RA4 RA2 RA1 RAO 00000000pg RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value Table 14 3 3 Functional Description of Each Bit of Wild Register Address Setup Register WRARO to WRAR2 RA15 to RAO These bits set the address to be amended by the wild register function Wild Registers These bits are used to specify the address to be allocated The address is specified in address setting bits accordance with its corresponding wild register number 190 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 14 WILD REGISTER MB95130 MB Series 14 3 Register
394. ial Mode Control Register 1 SMC10 319 20 5 2 UART SIO Serial Mode Control Register 2 5 20 321 20 5 3 UART SIO Serial Status and Data Register SSRO sse 323 20 5 4 UART SIO Serial Input Data Register RDRO sse 325 20 5 5 UART SIO Serial Output Data Register TDRO 326 20 6 Interrupts o YART S O Prata dec nec va ehe rea spo pus deu ERE e de dae 327 20 7 Explanation of UART SIO Operations and Setup Procedure Example 328 20 7 1 Operating Description of Operation Mode 0 329 20 7 2 Operating Description of Operation Mode 1 sssssssssssssseeeeeeeeeenneene enne 336 20 8 Sample Programs for UART SIO irsinin iaaa aan aae aai aiaa ai 342 CHAPTER 21 UART SIO DEDICATEDBAUD RATEGENERATOR 347 21 1 Overview of UART SIO Dedicated Baud Rate Generator sss 348 21 2 Channels of UART SIO Dedicated Baud Rate Generator 349 21 3 Registers of UART SIO Dedicated Baud Rate Generator 350 21 3 1 UART SIO Dedicated Baud Rate Generator Prescaler Selection Register
395. igure 20 7 14 Registers Used for Transmission in Operation Mode 1 SMC10 UART SIO Serial Mode Control Register 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO BDS PEN TDP SBL CBL1 CBLO CKS MD X X X G 1 SMC20 UART SIO Serial Mode Control Register 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO SCKE TXOE RERC RXE TXE RIE TCIE TEIE 0 x x SSRO UART SIO Serial Status and Data Register bit7 bit6 bit5 bit4 bit3 bit2 bit bitO PER OVE FER RDRF TCPL TDRE x x x x x x TDRO UART SIO Serial Output Data Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO TD7 TD6 TD5 TD4 TD3 TD2 TD1 TDO x x x x x x x x RDRO UART SIO Serial Input Data Register bit7 bit6 bit5 bit4 bit3 bit2 bit bitO RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO Used bit X Unused bit 0 Set 1 Set 1 The following two procedures can be used to initiate the transmission process e Set the transmission operation enable bit TXE to 1 and then write transmit data to the UART SIO serial output data register to start transmission CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example Write transmit data to the UART SIO serial output data
396. ime derived from the transition to the clock mode or standby mode To prevent this set the time base timer interrupt request enable bit of the time base timer control register TBTC TBIE to 0 to disable interrupts of the time base timer when entering a mode in which the main clock stops oscillating stop mode sub clock mode or sub PLL clock mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 139 CHAPTER 10 TIME BASE TIMER 10 5 Explanation of Time base Timer Operations and Setup MB95130 MB Series Procedure Example 10 5 Explanation of Time base Timer Operations and Setup Procedure Example This section describes the operations of the interval timer function of the time base timer E Operations of Time base Timer The counter of the time base timer is initialized to 3FFFFFq after a reset and starts counting while being synchronized with the main clock divided by two The time base timer continues to count down as long as the main clock is oscillating Once the main clock halts the counter stops counting and is initialized to 3FFFFFy The settings shown in Figure 10 5 1 are required to use the interval timer function Figure 10 5 1 Settings of Interval Timer Function TBTC bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Address 000Ay TBIF TBIE TBC1 TBCO TCLR 0 1 0 Bit used 1 Set to 1 0 Set to 0 When the time base timer initialization bit in the ti
397. imer control register WDIC tatiana adie ized 150 WICR Interrupt pin selection circuit control register WICR s ii eerie erret pur xen 306 Wild register address compare enable register Wild Register Address Compare Enable Register 538 Wild Register Address Setup Registers Wild Register Address Setup Registers WRARO to 190 Wild Register Data Setup Registers Wild Register Data Setup Registers WRDRO to WRDR2 189 Wild register data test setting register Wild Register Data Test Setup Register WROR 192 Wild Registers Block Diagram of Wild Register Function 185 Registers Related to Wild Register 187 Setup Procedure for Wild Register 193 Wild Register Applicable Addresses 193 Wild Register Function eeeeeeeeeses 184 Wild register number eeeeeeeeeesss 188 WPCR Watch Prescaler Control Register WPCR 160 WRAR Wild Register Address Setup Registers WRARO to iere ea ge 190 WRDR Wild Register Data Setup Registers WRDRO to WRDR2 189 WREN Wild Register Address Compare Enable Register WREN aeiiae eter dere p idein 191 Write Details of Programming Erasing Flash Memory 476 Flash memory program erase 466 Programming Data into Flash Memory WLC diserte ite do 478 Writing Writing to Flash Microco
398. in Selection Circuit The WICR interrupt pin selection circuit control register setting is used to select the input pins to be inputted to INTOO of the external interrupt circuit ch 0 Shown below is the setup procedure for the interrupt pin selection circuit and external interrupt circuit ch 0 which must be followed when selecting the TRGO pin as an interrupt pin 1 Write 0 to the corresponding bit in the port direction register DDR to set the pin as an input 2 Select the TRGO pin as an interrupt input pin in WICR interrupt pin selection circuit control register Write Oly to the WICR register At this point after writing 0 in the EIEO bit of the EICOO register of the external interrupt circuit the operation of the external interrupt circuit is disabled 3 Enable the operation of INTOO of the external interrupt circuit ch 0 Set the SLO1 and SLOO bits of the EICOO register to any value other than 00 in the external interrupt circuit to select the valid edge Also write 1 to the EIEO bit to enable interrupts 4 The subsequent interrupt operation is the same as for the external interrupt circuit When a reset is released WICR interrupt pin selection circuit control register is initialized to 40g and the INTOO bit is selected as the only available interrupt pin Update the value of this register before enabling the operation of the external interrupt circuit when using any pins other than the INTOO pin as ext
399. in Table E 1 1 Table E 1 1 Vector Table Address Corresponding to vct Vector table address jump destination high ranking address subordinate address 0 FFCOy FFClg 1 FFC2y FFC3g 2 FFC4g FFC5g 3 FFC7g 4 8 FFC9g 5 FFCAy FFCBg 6 FFCCy FFCDg 7 FFCEg FFCFg Figure E 1 8 shows an example Figure E 1 8 Example of Vector Addressing CALLV 5 ion gt FE Conversion F F C AH H Pc FED CH DCH 508 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX E Instruction Overview Q Relative addressing This is used when branching to the area in 128 bytes before and behind PC program counter with the addressing shown rel in the instruction table In this addressing add the content of the operand to PC with the sign and store the result in PC Figure E 1 9 shows an example Figure E 1 9 Example of Relative Addressing BNE FEH SET QABCH FFFEH WE In this example by jumping to the address where the operation code of BNE is stored it results in an infinite loop Inherent addressing This is used when doing the operation decided by the operation code with the addressing that does not have the operand in the instruction table In this addressing the operation depends on each instruction Figure E 1 10 shows an example
400. ing states of internal circuits CHAPTER 6 CLOCK CONTROLLER 6 1 Overview of Clock Controller Table 6 1 4 Combinations of Standby Mode and Clock Mode and Internal Operating States Function Main clock Time base TIMER Watch Dual clock product Stop Operating Sub SubPLL clock clock mode mode Dual Dual clock clock product product Stopped Operating Sub Sub PLL clock clock mode mode Dual Dual clock clock product product Stopped Operating Sub Sub PLL clock clock mode mode Dual Dual clock clock product product Stopped Stopped Sub PLL clock mode Dual clock product Stopped Main PLL clock Stopped 1 Operat ing Stopped Stopped Operat 1 i ing Stopped Stopped 1 Stopped Stopped Stopped Sub clock Operating Operating Operating Operating Operating Operating Operat ing Stopped Sub PLL clock Stopped Stopped Operat 3 i ing Stopped Stopped Operat 3 1 ing Stopped Stopped Operat 3 1 ing Stopped 3 Stopped CPU Operating Operating Stopped Stopped Stopped Stopped Stopped Stopped ROM RAM Operating Operating Value held Value held Value held Value held Value held Value held I O port Operating Operating Output held Output held Out
401. ingle clock product an attempt to write 005 or 01g to these bits is ignored leaving their value unchanged SRDY Sub clock oscillation stability bit Dual clock product only Indicates whether sub clock oscillation has become stable When set to 1 the SRDY bit indicates that the oscillation stabilization wait time for the sub clock has passed When set to 0 the SRDY bit indicates that the clock controller is in the sub clock oscillation stabilization wait state or that sub clock oscillation has been stopped This bit is read only Writing has no effect on operation On single clock product the value of these bits is meaningless SUBS Sub clock oscillation stop bit Dual clock product only Stops sub clock oscillation in main clock mode or main PLL clock mode When set to 0 the bit enables sub clock oscillation When set to 1 the bit stops sub clock oscillation Note n sub clock mode or sub PLL clock mode the sub clock oscillates regardless of the value of this bit except in stop mode n main clock mode or main PLL clock mode as well the sub clock oscillates regardless of the value of this bit when sub PLL clock oscillation has been enabled by the PLL clock oscillation enable bit in the PLL control register PLLC SPEN Do not update the SYCC SCSI bit and this bit at the same time Onsingle clock product the value of the bit has no effect on the operation DIV1 DIVO
402. inter RP direct pointer DP and condition code register CCR E Configuration of Dedicated Registers The dedicated registers in the CPU are seven 16 bit registers Accumulator A and temporary accumulator T can also be used with only their lower eight bits in service Figure 5 1 1 shows the configuration of the dedicated registers Figure 5 1 1 Configuration of Dedicated Registers Initial 16bits N value FFFDy PC Program counter Contains the address of the current instruction 00004 AH AL Accumulator A Temporary storage register for arithmetic operation and transfer 0000 TH TL Temporary accumulator T Performs an operation with accumulator 0000H IX Index register Register containing an index address 0000 EP Extra pointer Pointer containing a memory address 0000 SP Stack pointer Contains the current stack location 0030 RP DP CCR Program status PS 7 Register consisting of the register bank pointer direct bank pointer and condition code register E Functions of Dedicated Registers Program counter PC The program counter is a 16 bit counter which contains the memory address of the instruction currently executed by the CPU The program counter is updated whenever an instruction is executed or an interrupt or reset occurs The initial value set immediately after a reset is the mode data read address FFFDy
403. interrupt occurs while a timer interrupt is being processed with these settings in use the interrupts are processed as shown in Figure 8 1 3 Figure 8 1 3 Example of Processing Nested Interrupts Main Program Timer Interrupt Processing External Interrupt Processing Interrupt level 1 Interrupt level 2 CCR IL1 ILO 018 CCR IL1 ILOz 108 Initialize peripheral 1 resources Timer interrupt occurs 2 3 External interrupt l 4 Process external interrupt Suspend Resume Resume main program 8 6 Process timer interrup 5 Return from external interrupt 2 Return from timer interrupt While a timer interrupt is being processed the interrupt level bits in the condition code register CCR IL1 ILO hold the same value as that of the interrupt level setting registers ILRO to ILR5 corresponding to the current timer interrupt level 2 in this example If an interrupt request with a higher priority interrupt level level 1 in the example occurs the higher priority interrupt is processed preferentially To temporarily disable nested interrupt processing while a timer interrupt is being processed set the interrupt enable flag in the condition code register to disable interrupts CCR I 0 or set the interrupt level bits CCR IL1 ILO to 00g Executing the interrupt return instruction RETI after interrupt processing is completed restores the program counter PC and program st
404. interrupt processing The stack pointer SP contains the start address of the stack area E Interrupt Processing Stack Area The stack area is also used to save and restore the program counter PC when subroutine call CALL or vector call CALLV instructions are executed and to temporarily save and restore the registers via the PUSHW and POPW instructions e The stack area is located in RAM together with the data area e tis advisable to initialize the stack pointer SP to the maximum RAM address and allocate data areas starting from the minimum RAM address Figure 8 1 6 shows an example of setting the stack area Figure 8 1 6 Setting Example of Interrupt Processing Stack Area 0000 H 0080 Data area Stack area Y 4 Recommended SP value assuming a maximum RAM address of 02804 Access barred Note The stack area is allocated in descending order of addresses for interrupts subroutine calls and the PUSHW instruction it is deallocated in ascending order of addresses for return PETI RET and POPW instructions When the stack area address used decreases for nested interrupts or subroutines prevent the stack area from overlapping the data area or general purpose register area containing other data CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 105 CHAPTER 8 INTERRUPTS 8 1 Interrupts MB95130 MB Series 106 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 PORT
405. ion Free run Mode Counter value EOH t Although the TOODR T 01DR value is modified it is not updated into the comparison latch TOODR TO1DR value 0 1 i 1 Cleared by program 1 1 1 1 IF bit 1 1 1 i STA bit Activated Matched 1 Matched 1 Matched Matched 1 1 1 Counter value match i r Timer output pin o l 1 The counter is not cleared and the data register settings are not reloaded into the comparison data latch when a match is detected at each point during activation 224 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 10 Operating Description of PWM Timer Function Fixed cycle mode 15 10 Operating Description of PWM Timer Function Fixed cycle mode This section describes the operation of the PWM timer function fixed cycle mode for the 8 16 bit compound timer E Operation of PWM Timer Function Fixed cycle Mode The compound timer requires the settings shown in Figure 15 10 1 to serve as the PWM timer function fixed cycle mode Figure 15 10 1 Settings for PWM Timer Function Fixed cycle Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito TOOCRO TO1CRO IFE C2 C1 CO F3 F2 F1 FO 0 0 1 1 TOOCR1 T01CR1 STA HO IE IR BF IF SO OE 1 TMCRO TO1 IIS MOD FE11 FE10 FEO1 FEOO
406. ions for Debug When using an evaluation device mounted on an MCU board for software development there may be some differences between the operation of the evaluation device and the device you will actually use The following lists some points to note during development SYCC Register Settings During debugging the values of the DIV1 and DIVO bits in the SYCC register may differ from the user settings This is because when a break occurs the CPU adjusts the communications speed between the evaluation device and the BGM adapter to use the optimum speed To prevent this from occurring you need to set response speed optimization to disabled For this information refer also to 2 3 1 Setting Operating Environment in F MC 8L 8FX Family SOFTUNE Workbench USER S MANUAL Flash Memory Types and Sizes Each evaluation device can be used for debugging of a number of different production models series When developing your program please take note of the actual ROM and RAM sizes on the device you intend to use Further evaluation devices use dual operation flash memory However some production models have flash memory containing only one sector Please take note of any differences between the flash memory configurations of the production and evaluation devices particularly if writing a program that performs self updating of flash memory Differences in Flash Memory Content The debugger for the F MC 8FX family uses the software brea
407. ipheral resource pins in the stop mode time base timer mode or watch mode to hold their immediately preceding state or to be placed in a high inpedance state See Pin Status for the states of all pins in standby modes FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 8 Operations in Low power Consumption Modes Standby Modes 6 8 1 Notes on Using Standby Mode Even if the standby control register STBC sets standby mode transition to the standby mode does not take place when an interrupt request has been issued from a peripheral resource When the device returns from standby mode to the normal operating state in response to an interrupt the operation that follows varies depending on whether the interrupt request is accepted or not E Place at Least Three NOP Instructions Immediately Following a Standby Mode Setting Instruction The device requires four machine clock cycles before entering standby mode after it is set in the standby control register During that period the CPU executes the program To avoid program execution during this transition to standby mode enter at least three NOP instructions The device operates normally if you place instructions other than NOP instructions In that case however note that the device may execute the instructions to be executed after being released from standby mode before entering the standby mode and that the device may enter the standby mo
408. iption of 8 16 bit PPG Changed Initial setting 1 Set the port output DDR2 DDR6 gt 1 Set the port output DDRO 16 7 2 8 bit Prescaler 8 bit PPG Mode Changed the register name ll Operation of 8 bit Prescaler 8 bit PPG Mode PPG timer 00 ch 1 gt PPG timer 01 ch 0 CHAPTER 20 UART SIO 20 5 Registers of UART SIO Bi Registers Related to UART SIO Figure 20 5 1 Corrected bit attribute of bitS in SMC20 R W gt Added explanation R1 W Readable writable Read value is always 1 20 5 2 UART SIO Serial Mode Control Register 2 SMC20 E UART SIO Serial Mode Control Register 2 SMC20 Table 20 5 2 Corrected bit description of bit5 Setting the bit to 1 clears the reception error flag Hy Setting the bit to 1 has no effect on operation CHAPTER 22 LIN UART 22 3 LIN UART Pins Bl Block Diagram of LIN UART Pins Figure 22 3 1 Corrected block diagram 22 4 1 LIN UART Serial Control Register SCR E LIN UART Serial Control Register SCR Table 22 4 1 e Deleted Note in Function cell of bit5 Changed Note in Function cell of bit2 22 5 Interrupt of LIN UART E Reception Interrupt Reception interrupt Changed Note 22 8 Notes on Using LIN UART Notes on Using LIN UART Added 6 Handling framing errors Added Figure22 8 1 to Figure 22 8 3 Xii Page Changes For details refer to main body 422 22 9 Sample P
409. ircuit is set up in the following procedure Initial setting 1 Set the interrupt level ILRO 2 Select the edge polarity EIC SLO1 SLOO 3 Enable interrupt requests EIC EIEO 1 Interrupt processing 1 Clear the interrupt request flag EIC EIRO 0 2 Process any interrupt Note The external interrupt input is also used as an I O port Therefore when it is used as the external interrupt input the corresponding bit in the port direction register DDR must be set to 0 input CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 297 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 8 Notes on Using External Interrupt Circuit MB951 30 MB Series 18 8 Notes on Using External Interrupt Circuit This section describes the precautions that must be followed when using the external interrupt circuit E Notes on Using External Interrupt Circuit Set the interrupt request enable bit EIE to 0 disabling interrupt requests when setting the edge polarity select bit SL Also clear the external interrupt request flag bit EIR to 0 after setting the edge polarity The operation cannot recover from the interrupt processing routine if the external interrupt request flag bit is 1 and the interrupt request enable bit is enabled Always clear the external interrupt request flag bit in the interrupt processing routine 298 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series CHAPTER 18 EXTERNAL INTERR
410. ires the register settings shown in Figure 16 7 1 to operate in 8 bit independent mode Figure 16 7 1 8 bit Independent Mode bit7 bite bit5 bit4 bit3 bit2 bit bitO PCO1 PIE1 PUF1 1 512 511 510 PCOO MD1 MDO PIEO PUFO CKS02 CKS01 500 0 0 PPSO1 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PHO N Set PPG output cycle for PPG timer 01 PPSOO PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO N Set PPG output cycle for PPG timer 00 7 PDSO1 DH7 DH6 DH5 DH4 DH3 DH2 DH1 N Set PPG output duty for PPG timer 01 4 PDSOO DL7 DL6 DL5 DL4 DL3 DL2 DL1 DLO N PPG output duty for PPG timer 00 7 PPGS F z z PENO1 x x x REVC REVO1 REVOO x x x Used bit 0 The bit status depends on the number of channels provided E Operation of 8 bit PPG Independent Mode e This mode is selected when the operation mode select bits MD1 MDO in the 8 16 bit PPG timer 00 control register PCOO are set to 00g When the corresponding bit PEN in the 8 16 bit PPG start register PPGS is set to 1 the value in the 8 16 bit PPG cycle setup buffer register PPS is loaded to start down count operation When the count va
411. is set to 1 and TBIE bit is changed from the disable state to the enable state 0 1 an interrupt request is generated immediately TBIF bit is not set when the counter is cleared TBTC TCLR 1 and the time base timer counter underflows at the same time Write 1 to TBIF bit to clear an interrupt request in an interrupt processing routine Note When enabling the output of interrupt requests after canceling a reset TBTC TBIE 1 always clear TBIF bit at the same time TBTC TBIF 0 Table 10 4 1 Interrupts of Time base Timer Description Interrupt condition Interval time set by TBTC TBCI and TBCO has elapsed Interrupt flag TBTC TBIF Interrupt enable TBTC TBIE 138 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 10 TIME BASE TIMER MB95130 MB Series 10 4 Interrupts of Time base Timer E Register and Vector Table for Interrupts of Time base Timer Table 10 4 2 Register and Vector Table for Interrupts of Time base Timer Interrupt Interrupt level setting register Vector table address Interrupt request Source number Registers Setting bit timer Refer to CHAPTER 8 INTERRUPTS for the interrupt request numbers and vector tables of all peripheral functions Note If the interval time set for the time base timer is shorter than the main clock oscillation stabilization wait time an interrupt request of the time base timer is generated during the main clock oscillation wait t
412. ister full RDRF bit is set to 1 A reception interrupt occurs the moment the receive data register full bit is set to 1 when the reception interrupt enable bit RIE contains 1 To read received data read it from the UART SIO serial input data register after checking the error flag OVE in the UART SIO serial status and data register When received data is read from the UART SIO serial input data register RDRO the receive data register full RDRF bit is cleared to 0 Figure 20 7 12 8 bit Reception of Synchronous Clock Mode vo Too oie oxo oer Read to RDRO RDRF Interrupt to interrupt controller 338 Operation when reception error occurs When an overrun error OVE exists received data is not transferred to the UART SIO serial input data register RDRO Overrun error OVE Upon completion of reception for serial data the overrun error OVE bit is set to 1 if the receive data register full RDRF bit has been set to 1 by the reception for the preceding piece of data FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure Example MB95130 MB Series Figure 20 7 13 Overrun error UCKO ILE FEET STE UU J Read to RDRO RDRF Transmission UART SIO operation mode 1 For transmission in operation mode 1 each register is used as follows F
413. it PPG Mode 259 Operation of 8 bit PPG Independent Mode 254 Operation of 8 bit Prescaler 8 bit PPG Mode Sunn 256 Operation of Interval Timer Function Continuous Mode 221 Operation of Interval Timer Function Free run Mode 223 Operation of Interval Timer Function One shot 219 Operation of PWM Timer Function Fixed cycle Mode 225 Operation of PWM Timer Function Variable cycle Mode 227 Operation of Synchronous Mode Operation Mode 2 401 Operations Main Clock Mode 65 Operations in Main PLL Clock Mode 65 Operations in Sleep 75 Operations in Stop Mode 76 Operations in Sub Clock Mode Dual clock product 65 Operations in Sub PLL Clock Mode Dual clock product 65 Operations in Time base Timer Mode 77 Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition 53 Overview of Transitions to and from Standby Mode TE 70 PWM Mode MDSE of PCNTH Register logre 278 PWM Timer Function Fixed cycle Mode 196 PWM Timer Function Variable cycle Mode 196 S
414. it prescaler 8 bit PPG mode has been selected Therefore the setting of this bit has no effect on the operation Set this bit in 16 bit PPG operation mode 0005 1 MCLK 001g 2 MCLK 0105 4 MCLK 0llg S MCLK 1005 16 MCLK 1015 32 MCLK 110g 27 111g 29e Note Use of a sub clock in dual clock product stops the time base timer operation Therefore selecting 110g or 111g is prohibited FUJITSU MICROELECTRONICS LIMITED 247 CHAPTER 16 8 16 BIT PPG 16 5 Registers of 8 16 bit PPG MB951 30 MB Series 16 5 3 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register PPS01 PPS00 The 8 16 bit PPG timer 00 01 cycle setup buffer register PPS01 PPS00 sets the PPG output cycle E 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register PPSO1 PPSOO Figure 16 5 4 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register PPSO1 PPSOO0 PPSO1 bit7 bit5 bit4 bit3 bit2 bit bito Initial value Address PH7 PH6 PH5 PH4 PH3 PH2 PH1 PHO 11111111g OFOCG PPS0 RW RW RW RW RW RW RW RW PPS00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value Address PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 111111116 OF9D PPSOO RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value This register is used to set the PPG output cycle 248 In 16 bit PPG mode PPSO1 serves as the upper 8 bits while PPSO
415. it5 bit4 bit3 bit2 bit bito 0058 PER OVE FER RDRF TCPL TDRE RO WX RO WX R WX R WX R RMt w R WX UART SIO serial output data register Address _ bit7 bit6 bit5 bit4 bit3 bit2 bit bitO 00594 TD7 TD6 TDS TD4 TD2 TDO RW RW RW RW RW RW RW RW UART SIO serial input data register RDRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO 005A RD7 RDe RDS RD4 RD8 RD2 RD1 RDO R WX R W Readable writable Read value is the same as write value RMW instruction R WX Read only Readable writing has no effect on operation RO WX Undefined bit Read value is O writing has no effect on operation R1 W Readable writable Read value is always 1 Initial value 00000000 Initial value 00100000 Initial value 000000015 Initial value 00000000pg Initial value 000000008 R RM1 W Readable writable Read value is different from write value 1 is read by read modify write 318 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 5 Registers of UART SIO 20 5 1 UART SIO Serial Mode Control Register 1 SMC10 UART SIO serial mode control register 1 SMC10 controls the UART SIO operation mode The register is used to set the serial data direction endi
416. ite program data 60 Upper4 bits same as RA and PA Fx FF FE Arbitrary address Both of the two types of read reset command can reset the flash memory to read mode Notes Addresses in the table are the values in the CPU memory map All addresses and data are hexadecimal values However X is an arbitrary value Address U in the table is not arbitrary whose four bits bit15 to bit12 must have the same value as RA and PA Example If RA C48Exy U C If PA 10244 U 1 E Notes on Issuing Commands Pay attention to the following points when issuing commands in the command sequence table The upper address U bits bit15 to bit12 used when commands are issued must have the same value as RA and PA from the first command on If the above measures are not followed commands are not recognized normally Execute a reset to initialize the command sequencer in the flash memory CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 471 CHAPTER 26 256 Kbit FLASH MEMORY 26 5 Checking the Automatic Algorithm Execution Status MB95130 MB Series 26 5 Checking the Automatic Algorithm Execution Status As the flash memory uses the automatic algorithm for a process flow for programming erasing you can check its internal operating status with hardware sequence flags E Hardware Sequence Flag Overview of hardware sequence flag The hardware sequence flag consists of t
417. ite value This register holds data to be transmitted The register accepts a write when the transmission data register empty TDRE bit contains 1 An attempt to write to the bit is ignored when the bit contains 0 When this register is updated at writing complete the transmission data and TDRE 0 without depending on TXE of serial mode control register 2 is 1 or 0 the transmission operation is initialized by writing 0 to TXE TDRE becomes 1 and the update of this register becomes possible Moreover when 0 is written in TXE without the starting transmission when the transmission data is written in TDRO and it has not transmitted TXE to 1 yet TCPL is not set in 1 The transmission data is transferred to the shift register for the transmission it is converted into the serial data and it is transmitted from the serial data output pin When transmit data is written to the UART SIO serial output data register TDRO the transmission data register empty bit TDRE is set to 0 Upon completion of transfer of transmit data to the transmission shift register the transmission data register empty bit TDRE is set to 1 allowing the next piece of transmit data to be written At this time an interrupt Occurs if transmission data register empty interrupts have been enabled Write the next piece of transmit data when transmit data register empty occurs or the transmit data register empty TDRE bit is set to 1 When the
418. ithm is still running for the data polling or toggle bit function If an attempt is made to write 1 to a flash memory address holding 0 for example the flash memory is locked preventing the automatic algorithm from being terminated and valid data from being output from the data polling flag DQ7 As the toggle bit flag DQ6 does not stop toggling the time limit is exceeded and the execution time out flag DQ5 outputs 1 The state in which the execution time out flag DQ5 outputs 1 means that the flash memory has not been used correctly it does not mean that the flash memory is defective When this state occurs execute the reset command CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 475 CHAPTER 26 256 Kbit FLASH MEMORY 26 6 Flash Memory Program Erase MB951 30 MB Series 26 6 Flash Memory Program Erase This section describes the individual procedures for flash memory reading resetting programming and chip erasing by entering their respective commands to invoke the automatic algorithm E Details of Programming Erasing Flash Memory The automatic algorithm can be invoked by writing the read reset program and chip erase command sequence to flash memory from the CPU Writing command sequence to flash memory from the CPU must always be performed continuously The termination of the automatic algorithm can be checked by the data polling function After the automatic algorithm terminates normally the flash memory returns t
419. ito 0055 nese LBR ms scpe ssm 18 Rei rai RX WO ROW HW HW HW RXWO R WX LIN UART baud rate generator register 1 BGR1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito OFBC BGR14 BGR13 BGR12 BGR11 BGR10 BGR9 BGR8 RO WX RW HW HW HW HW HW RW LIN UART baud rate generator register 0 BGRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit OFBDy BGR7 BGR6 BGR5 BGR4 BGR3 BGR2 BGR1 BGRO R W HW HW HW HW HW HW RW R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction R WX Read only Readable writing has no effect on operation RO W Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation RX WO Reserved bit Write value is indeterminate write value is 0 Initial value 000000008 Initial value 00000000pg Initial value 00001000p Initial value 00000000 Initial value 000001008 Initial value 000000 Initial value 00000000pg Initial value 00000000pg CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 365 CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series 22 4 1 LIN UART Serial Control Register SCR The LIN UART serial control register SCR is used to set parity select the stop bit length and data length select the frame data format in mode 1 clear
420. ivision PSS 1 0 ratio ratio ratio BRS 7 0 125000 200000 203125 113636 181818 184659 56818 90909 92330 28736 45977 46695 19231 30769 31250 9615 15385 15625 4808 7692 7813 2404 3846 3906 1 Setting value 0 0 1 Setting value 0 0 1 Setting value 0 0 1 Setting value 0 0 1 Setting value 0 0 2 Setting value 0 1 4 Setting value 1 0 8 Setting value 1 1 aA al A BR A Al A The baud rate can be set in UART mode within the following range Table 21 4 2 Permissible Baud Rate Range in UART Mode PSS 1 0 BRS 7 0 CEOE 354 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART This chapter describes the function and operation of the LIN UART 22 1 Overview of LIN UART 22 2 Configuration of LIN UART 22 3 Pins of LIN UART 22 4 Registers of LIN UART 22 5 Interrupt of LIN UART 22 6 LIN UART Baud Rate 22 7 Operations and Setup Procedure Example of LIN UART 22 8 Notes on Using LIN UART 22 9 Sample Programs of LIN UART Code CM26 00127 2E Page 364 396 422 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 355 CHAPTER 22 LIN UART 22 1 Overview of LIN UART 22 1 MB95130 MB Series Overview of LIN UART The LIN Local Interconnect Network UART is a general purpose serial data communication interface for synchronous or asynchronous start stop synchronization communication with external devices In addition to a bi dir
421. k Diagram of External Interrupt iim M 289 Block Diagram of Pins Related to External Interrupt Circuit ineehitestaertei reins 291 Channels of External Interrupt Circuit 290 External Interrupt Control Register EICOO 293 Functions of External Interrupt Circuit 288 Interrupt Acceptance Control Bits 40 Interrupt During Operation of External Interrupt eiii 295 Interrupt Processing Stack Area 105 Interrupt Processing Steps uuuuss 99 Interrupt Processing Time ss 103 Interrupt when Interval Function is in Operation 138 Interrupt when Interval Timer Function is in Operation Watch Interrupts eeussse 162 Interrupts During 8 10 bit A D Converter Operation desire uk esi ded 439 Interrupts of 16 bit PPG Timer 277 Interrupts of 8 16 bit 252 Interrupts of UART SIO eee 327 Interrupts of Watch Counter 177 Interrupts of Watch Prescaler 162 LIN Synch Field Edge Detection Interrupt 8 16 bit Compound Timer Interrupt 381 List of Registers of External Interrupt CITCUIL th eges 292 Nested Interrupts sesseeeeeeeeeeeeee 102 Notes on Using External Interrupt eundi mS 298 Operation of
422. k instruction to implement break points When continuous or step execution is performed after setting a break point the software break instruction is written to the break address in the flash memory on the evaluation device Accordingly the contents of flash memory after a software break has been inserted by the debugger will be different to the program data image generated by the compiler Before performing a checksum you must remember to clear all break points and synchronize flash memory Restrictions Relating to the Flash Memory on the Evaluation Device The following restrictions apply to the evaluation device for the F MC 8FX family 1 Writing or erasing the lower bank addresses 1000y to is not possible When debugging please do this on the production flash memory model 2 Do not use the chip erase command for the flash memory on the evaluation device When debugging please do this on the production flash memory model CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 21 CHAPTER 2 HANDLING DEVICES 2 1 Device Handling Precautions MB95130 MB Series 22 Operation of Peripheral Functions During a Break When a CPU break occurs the debugger for the F MC 8FX family halts CPU operation instruction code fetch decoding instruction execution updating the PC etc but the peripheral functions PPG timer UART A D converter etc continue to operate The following are some example implications 1 If
423. l interrupt ch 3 295 External interrupt 7 295 8 16 bit compound timer ch 0 lower 218 8 16 bit compound timer ch 0 upper 218 8 16 bit PPG ch 0 upper 252 8 16 bit PPG ch 0 lower 252 16 bit PPG 0 277 CM26 10118 3E FUJITSU MICROELECTRONICS CONTROLLER MANUAL F MC 8FX 8 BIT MICROCONTROLLER MB95130 MB Series HARDWARE MANUAL February 2010 the third edition Published FUJITSU MICROELECTRONICS LIMITED Edited Sales Promotion Dept
424. l interrupt circuit Figure 18 2 1 Block Diagram of External Interrupt Circuit UnitO Interrupt pin select circuit INTOO Edge detection circuit 1 Edge detection circuit 0 Selector Selector External interrupt control register EIC EIE 5100 Internal data bus Interrupt request 0 Interrupt request 1 Only for INT 00 pin of unit 0 See CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT Edge detection circuit When the polarity of the edge detected on a signal inputted to an external interrupt circuit pin INT matches the polarity of the edge selected in the interrupt control register EIC the corresponding external interrupt request flag bit EIR is set to 1 Q External interrupt control register EIC This register is used to select the valid edge enable or disable interrupt requests check for interrupt requests etc CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 289 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 3 Channels of External Interrupt Circuit MB95130 MB Series 18 3 Channels of External Interrupt Circuit This section describes the channels of the external interrupt circuit B Channels of External Interrupt Circuit In MB95130 MB series each unit has four channels of the external interrupt circuit Table 18 3 1 and Table 18 3 2 show the correspondence among the channel pin and register Table 18 3
425. lash Memory Figure 26 2 1 shows the sector configuration of the 256 Kbit flash memory The upper and lower addresses of each sector are given in the figure Figure 26 2 1 Sector Configuration of 256 Kbit Flash Memory Flash memory CPU address Programmer address 8000 18000 32K bytes FFFFy 1FFFFj The programmer address is equivalent to the CPU address which is used when data is written to the flash memory using parallel programmer When a parallel programmer is used for programming erasing the programmer address is used for programming erasing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 467 CHAPTER 26 256 Kbit FLASH MEMORY 26 3 Register of Flash Memory 26 3 Register of Flash Memory MB95130 MB Series This section shows the register of the flash memory E Register of the Flash Memory Figure 26 3 1 Register of the Flash Memory Address 00724 R W R RM1 W R WX R WO RO WX Flash Memory Status Register FSR bito Initial value Reserv 9909x0000 bit7 bit6 bit5 bit4 bit3 bit2 bit Rova Rese ipgeN wre ed ed RO WX RO WX R RM W RWX RW RW R WO Readable writable Read value is the same as write value Readable writable Read value is different from write value 1 is read by read modify write RMW instruction Read only Readable writing has no effect on operation Reserved bit
426. lash memory End of writing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 479 CHAPTER 26 256 Kbit FLASH MEMORY 26 6 Flash Memory Program Erase MB95130 MB Series 26 6 3 Erasing All Data from Flash Memory Chip Erase This section describes the procedure for issuing the chip erase command to erase all data from flash memory E Erasing Data from Flash Memory Chip Erase To erase all data from flash memory send the chip erase command in the command sequence table continuously from the CPU to flash memory The chip erase command is executed in six bus operations Chip erasing is started upon completion of the sixth programming cycle Before chip erasing the user need not perform programming into flash memory During execution of the automatic erase algorithm flash memory automatically programs 0 before erasing all cells automatically Bi Notes on Chip Erase If a hardware reset occurs during erasure the data being erased from flash memory is not guaranteed 480 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 7 Flash Security 26 7 Flash Security The flash security controller function prevents the contents of flash memory from being read through external pins E Flash Security Writing protection code Oly to a flash memory address 8000g restricts access to flash memory barring read write access to flash memory from any external pin
427. lated into a real address according to the rule shown in Figure 5 1 3 Figure 5 1 3 Rule for Translation into Real Addresses in General purpose Register Area Generated address 0 0 L o o o o o 1 R4 R2 RO b2 bi bO bt 4 41 Y d d ld d bo i4 4 Op code Fixed value RP Upper Lower 15 A14 A13 A12 A11 A10 A9 A8 A7 5 A4 AB 2 A1 The register bank pointer specifies the register bank used as general purpose registers in the RAM area There are a total of 32 register banks The current register bank is specified by setting a value between 0 and 31 in the upper five bits of the register bank pointer Each register bank has eight 8 bit general purpose registers which are selected by the lower three bits of the op code The register bank pointer allows the space from 0100 to up to O1FFy to be used as a general purpose register area Note however that the available area is limited depending on the product The initial value after a reset is 0000g E Mirror Address for Register Bank and Direct Bank Pointers The register bank pointer RP and direct bank pointer DP can be written to and read from by accessing the program status PS register using the MOVW A PS and MOVW PS A instructions respectively They can also be written to and read from directly by accessing 36 mirror address 00784 of the register bank pointer
428. lation stabilization wait state or main PLL clock oscillation being stopped Indicates main PLL clock oscillation being stable Main PLL clock multiplier setting bits Main clock x1 Main clock x 2 Main clock x 2 5 Main clock x 4 MPEN Main PLL clock oscillation enable bit 0 Disables main PLL clock oscillation 1 Enables main PLL clock oscillation R W Readable writable Read value is the same as write value R WX Read only Read only Writing does not affect the operation Initial value 56 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series CHAPTER 6 CLOCK CONTROLLER 6 4 PLL Control Register PLLC Table 6 4 1 Functions of Bits in PLL Control Register PLLC 1 2 Bit name Function Enables or disables the oscillation of the main PLL clock in main clock mode or time base timer mode bit ur clock When set to 0 the bit disables main PLL clock oscillation oscillation enable bit When set to 1 the bit enables main PLL clock oscillation In main PLL clock mode the main PLL clock oscillates regardless of the value of this bit either in the RUN state or in sleep mode Set the multiplier for the main PLL clock MPMC1 MPMCO Main PLL clock multiplier setting bits as MPMCI MPMCO bite Main PLL clock multiplier setting bits Note The value of these bits can be changed only when the main PLL clock is stopped Consequently you should not update the bit
429. lects the external clock or dedicated baud rate generator Setting the bit to 0 selects the dedicated baud rate generator Setting the bit to 1 selects the external clock Note Setting this bit to 1 forcibly disables the output of the UCKO pin The external clock cannot be used in clock asynchronous mode UART MD Operation mode selection bit This bit selects clock asynchronous mode UART or clock synchronous mode SIO Setting the bit to 0 selects clock asynchronous mode UART Setting the bit to 1 selects clock synchronous mode SIO Note When modifying the UART SIO serial mode control register 1 SMC10 do not perform the modification during data transmission or reception 320 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 5 Registers of UART SIO 20 5 2 UART SIO Serial Mode Control Register 2 SMC20 UART SIO serial mode control register 2 SMC20 controls the UART SIO operation mode The register is used to enable disable serial clock output serial data output transmission reception and interrupts and to clear the reception error flag E UART SIO Serial Mode Control Register 2 SMC20 Figure 20 5 3 UART SIO Serial Mode Control Register 2 SMC20 Address bit7 bit5 bit4 bit3 bit2 biti bitO Initial value did 00100000 RAN R W R1 W R W R W R W R W R W i TEIE Transmission data register empty interrupt enable bit
430. length Lower 8 bit of accumulator 8 bit length Temporary accumulator Whether 8 bit length or 16 bit length is decided by the instruction used Upper 8 bit of temporary accumulator 8 bit length Lower 8 bit of temporary accumulator 8 bit length Index register 16 bit length Extra pointer 16 bit length Program counter 16 bit length Stack pointer 16 bit length Program status 16 bit length Either of accumulator or index register 16 bit length Condition code register 8 bit length Register bank pointer 5 bit length Direct bank pointer 3 bit length General purpose register 8 bit length i 0 to 7 This shows that x is immediate data Whether 8 bit length or 16 bit length is decided by the instruction used This shows that contents of x are objects of the access Whether 8 bit length or 16 bit length is decided by the instruction used This shows that the address that contents of x show is an object of the access Whether 8 bit length or 16 bit length is decided by the instruction used 504 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series APPENDIX APPENDIX E Instruction Overview E Explanation of Item in Instruction Table Table E 2 Explanation of Item in Instruction Table Item Description MNEMONIC It shows the assembly description of the instruction It shows the number of cycles of the in
431. llation stabilization wait time Reset occurs in each state Main PLL clock oscillation stabiliza tion wait time N Time base timer mode Sleep mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 73 CHAPTER 6 CLOCK CONTROLLER 6 8 Operations in Low power Consumption Modes Standby MB95130 MB Series Modes Table 6 8 1 State Transition Diagram Transitions to and from Standby Modes State Transition Description Normal operation from reset state After a reset the device enters main clock mode If the reset is a power on reset the device always waits for the main clock oscillation stabilization wait time to elapse When the clock mode before the reset is sub clock mode or sub PLL clock mode the device waits for the main clock oscillation stabilization wait time to elapse The device waits for it as well when the standby mode is stop mode When the clock mode before the reset is main clock mode or main PLL clock mode and the standby mode is other than stop mode the device does not wait for the main clock oscillation stabilization wait time to elapse even after entering a reset state in response to a watchdog reset software reset or external reset Sleep mode The device enters sleep mode when 1 is written to the sleep bit in the standby control register STBC SLP The device returns to the RUN state in response to an interrupt from a peripheral resource Stop
432. llocated as part of memory space it can be accessed in the same way as for memory Data area Static RAM is incorporated as the internal data area Theinternal RAM capacity is different depending on the product The area from 00804 to 047Fq is an extended direct addressing area It can be accessed at higher speed by direct addressing instructions with the direct bank pointer set initial value 0080g OOFFy e Addresses 0100y to O1FFg can be used as a general purpose register area Program area ROM is incorporated as the internal program area The internal ROM capacity is different depending on the model e Addresses FFCOg to FFFFy are used as the vector table 26 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series E Memory Map CHAPTER 3 MEMORY SPACE Figure 3 1 1 Memory Map 3 1 Memory Space 0000 00804 01004 02004 047Fy OF 80 OFFFy FFCOy FFFFy I O area Register banks General purpose Data area A lt Extended I O area Program area Direct addressing area Extended direct addressing area CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 27 CHAPTER 3 MEMORY SPACE 3 1 Memory Space MB95130 MB Series 3 1 1 Areas for Specific Applications The general purpose register area and vector table area are used for the specific applications E General purpose Register Area Addresses 01004 to 01
433. load counters also restart when the LIN UART is reset by writing 1 to the SMR UPCL bit Automatic restart reception reload counter only The reception reload counter is restarted when the start bit falling edge is detected in asynchronous mode This is the function to synchronize the reception shift register with the reception data Clear counter When a reset occurs the reload values in the LIN UART baud rate generator registers 1 0 BGR1 BGRO and the reload counter are cleared to 00g and the reload counter halts Although the counter value is temporarily cleared to 00g by the LIN UART reset writing 1 to SMR UPCL the reload counter restarts since the reload value is retained The counter value is not cleared to 00g by the restart setting writing 1 to SMR REST and the reload counter restarts 394 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART 22 7 Operations and Setup Procedure Example of LIN UART LIN UART operates in mode 0 2 for bi directional serial communication in mode 1 for master slave communication and in mode 3 for LIN master slave communication E Operation of LIN UART Operation mode The LIN UART has four operation modes 0 to 3 allowing the connections between CPUs and the data transfer methods to be selected as listed in Table 22 7 1 Table 22 7 1 LIN UART Operation Modes Data len
434. lock Supply States Stops clock supply to the CPU and watchdog timer As a result the CPU stops operation but Sleep mode other peripheral resources continue operating Supplies clock signals only to the time base timer watch prescaler and watch counter while stopping clock supply to other circuits As a result all the functions other than the time base timer watch prescaler watch counter external interrupt and low voltage detection reset option are stopped Time base timer mode is only the standby mode for main clock mode or main PLL clock mode Time base timer mode Stops main clock oscillation but supplies clock signals only to the watch prescaler and watch counter while stopping clock supply to other circuits As a result all the functions other than the watch prescaler watch counter external interrupt and low voltage detection reset option are stopped Watch mode is only the standby mode for sub clock mode or sub PLL clock mode Watch mode Dual clock product only Stops main clock oscillation and sub clock oscillation and stops the supply of all clock Stop mode signals As a result all the functions other than external interrupt and low voltage detection reset option are stopped 50 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series E Combinations of Clock Mode and Standby Mode Table 6 1 4 lists the combinations of clock mode and standby mode and their respective operat
435. ltage detection reset circuit generates a reset if the power supply voltage falls below a predetermined level The logical function of the low voltage detection reset is completely equivalent to the power on reset All the text in this manual concerning power on resets applies to low voltage detection resets as well For details about low voltage detection resets see CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT Clock Supervisor Reset Option Some 5V products have the optional clock supervisor The clock supervisor monitors the main and sub clocks and generates a reset when the oscillation stops due to not given state transition but any abnormality After reset a clock occurred in the built in RC oscillation circuit is provided internally For details on the clock supervisor see CHAPTER 25 CLOCK SUPERVISOR E Reset Time In the case of a software reset or watchdog reset the reset time consists of a total of three machine clock cycles one machine clock cycle at the machine clock frequency selected before the reset and two machine clock cycles at the machine clock frequency initially set after the reset 1 32 of the main clock frequency However the reset time may be extended in machine clock cycles of the frequency selected before the reset via the RAM access protection function which suppresses resets during RAM access In addition when in main clock oscillation stabilization standby mode the reset time is further extended
436. lter function select bits CM26 10118 3E These bits select the filter function for the external signal to timer 00 when the PWC timer or input capture function has been selected Timer 00 filter No filtering Removing H pulse noise Removing L pulse noise Removing H L pulse noise An attempt to write to these bits is nullified during timer operation TOOCR1 STA 1 The settings of these bits have no effect on operation when the interval timer or PWM timer function has been selected filter function does not operate FUJITSU MICROELECTRONICS LIMITED 213 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer MB951 30 MB Series 15 5 4 8 16 bit Compound Timer 00 01 Data Register ch 0 TOODR TO1DR The 8 16 bit compound timer 00 01 data register TOODR TO1DR is used to write the maximum value counted during interval timer or PWM timer operation and to read the count value during PWC timer or input capture operation The TOODR and TO1DR registers correspond to timers 00 and 01 respectively E 8 16 bit Compound Timer 00 01 Data Register TOODR TO1DR Figure 15 5 5 8 16 bit Compound Timer 00 01 Data Register TOODR TO1DR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 0F94 T01DR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDRO 00000000g OF95 TOODR RW RW RW RW RW RW RW RW R W Readable writable Read value is different from
437. lts When a specified edge is detected the counter value is transferred to the 8 16 bit compound timer 00 01 data register Writing a value to the data register updates the measurement data stored there with that value Therefore do not write to the 8 16 bit compound timer 00 01 data register In 16 bit operation the upper data and lower data are transferred to TO1DR and TOODR respectively Read TOIDR and TOODR in this order CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 215 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer MB951 30 MB Series Q Read and write operations Read and write operations of TOODR and TOIDR are performed in the following manner during 16 bit operation and PWM timer function variable cycle e Readfrom TOIDR Read access from the register also involves storing the TOODR value into the internal read buffer e Readfrom TOODR Read from the internal read buffer Write to TOIDR Write to the internal write buffer e Write to TOODR Write access to the register also involves storing the value of the internal write buffer into TOIDR Figure 15 5 6 shows the TOODR and TOIDR registers read from and written to during 16 bit operation Figure 15 5 6 TOODR and TO1DR registers read from and written to during 16 bit operation TOODR Read register buffer TO1DR lt register k TO1DR TOODR TO1DR TOODR write write read read Write data Read data 216
438. lts the operation upon the detection of a falling edge Moreover the PPG timer begins operation of the following rising edge from the beginning The operation can be retriggered by a valid TRGO input hardware trigger regardless of the retrigger setting of the RTRG bit when the TRGO input hardware trigger has been selected Figure 17 7 5 Hardware Trigger in PWM Mode Counter value Time tected ge detecte Rising ed Hardware we Pe PPG NE Normal polarity EE ME _ OO Inverted polarity Falling edge de m7 cae 2 D nxT T Count clock cycle 1 n x T ns m PCSRHO amp PCSRLO register value 2 m x T ns n PDUTHO amp PDUTLO register value E Setup Procedure Example The 16 bit PPG timer is set up in the following procedure Initial setting 1 Set the interrupt level ILR3 ILR4 2 Enable the hardware trigger and interrupts select the interrupt type and enable output PCNTL 3 Select the count clock and the mode and enable timer operation PCNTH 4 Set the cycle PCSRLO PCSRHO 5 Set the duty PDUTHO PDUNTO 6 Start the PPG by the software trigger PCNTH STRG 1 Interrupt processing 1 Process any interrupt 2 Clear the interrupt request flag PCNTL IRQF CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 281 CHAPTER 17 16 BIT PPG TIMER 17 8 Notes on Using 16 bit PPG Timer MB951 30 MB Series 17 8 Notes on Using 16
439. lue dge detected Trigger ignored Software trigger 1 Rising e i PPG Normal polarity PPG Inverted polarity a 2 T Count clock count Clock cycle a m PCSRHO amp PCSRLO register value n PDUTHO amp PDUTLO register value Validating the retrigger RTRG of PCNTHO register bit 4 1 Figure 17 7 2 When Retrigger Is Valid in PWM Mode Counter value Rising edge detected Software trigger mem Restarted by trigger PPG Normal polarity s PPG Inverted polarity 1 x T ns T Count clock cycle 2 m x T ns m PCSRHO amp PCSRLO register value n PDUTHO amp PDUTLO register value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 279 CHAPTER 17 16 BIT PPG TIMER 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example MB951 30 MB Series E One shot Mode MDSE of PCNTHO Register bit 5 1 One shot operation mode can be used to output a single pulse with a specified width when a valid trigger input occurs When retriggering is enabled and a valid trigger is detected during the counter operation the down counter value is reloaded The initial state of the PPG output is L When the 16 bit down counter value matches the value set in the duty setting registers the output changes to H The output changes back to L when the counter reaches 1 The output lev
440. lue reaches 1 the value in the cycle setup register is reloaded to repeat the counting e is output to PPG output synchronizing with the count clock When the down counter value matches the value in the 8 16 bit PPG timer 00 01 duty setup buffer register PDS After H which is the value of duty setting is output L is output to the PPG output If however the PPG output inversion bit is set to 1 the PPG output is set and reset inversely from the above process Figure 16 7 2 shows the operation of the 8 bit PPG independent mode 254 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series Figure 16 7 2 Operation of 8 bit PPG Independent Mode CHAPTER 16 8 16 BIT PPG 16 7 Operating Description of 8 16 bit PPG Count clock 4 A 4 A 4 Ht A FLF PEN Counter start 4 a Stop E Cycle setting 5 PPS Duty setting PDS PPG timer 00 counter value 5 Down counter value matches maiches duty setting value EE Counter borrow PPG output source PPGOO Pin Normal polarity Synchronizing with machine clock Inversion polarity a r2 M 1 1 1 1 1 1 1 1 1 1 1 1 i 1 1 Stop 4 1 1 1 1 1 1 1 1 1 1
441. lutions can be selected FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 1 DESCRIPTION MB95130 MB Series 1 1 Feature of MB95130 MB Series Low power consumption standby mode Stop mode Sleep mode Watch mode Only for dual clock product Time base timer 1 0 port Max 20 General purpose I O ports CMOS 20 Programmable input voltage levels of port Automotive input level CMOS input level hysteresis input level Flash memory security function Protects the content of Flash memory Flash memory device only CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 3 CHAPTER 1 DESCRIPTION 1 2 Product Lineup of MB95130 MB Series MB951 30 MB Series 1 2 Product Lineup of MB95130 MB Series MB95130 MB series is available in three types Table 1 2 1 lists the product lineup and Table 1 2 2 lists the CPUs and peripheral functions E Product Lineup of MB95130 MB Series Table 1 2 1 Product Lineup of MB95130 MB Series Option Classification Product ROM RAM Voltage Clock system LVD Single clock Dual clock MB9S5FV100D 101 60KB 3 75KB Single clock Evaluation products MB95FV100D 103 60KB 3 75KB Dual clock MB95F133MBS MB95F133NBS Single clock MB95F133JBS MB95F133MBW MB95F133NBW Dual clock MB95F133JBW MB95F134MBS MB95F134NBS Single clock Flash memory MB95F134JBS products MB95FI34MBW MB95F134NBW Dual clock MB95F134J BW MB95F136MBS MB95F136NBS Singl
442. master CPU and multiple slave CPUs with two common communication lines as shown in Figure 22 7 14 The LIN UART can be used as the master or slave Figure 22 7 14 Connection Example of LIN UART Master Slave Mode Communication Master CPU Slave CPU 0 Slave CPU 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 411 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series Function Selection For master slave mode communication select the operation mode and the data transfer method as shown in Table 22 7 4 Table 22 7 4 Select of Master Slave Mode Communication Function Operation mode Synchro nous Stop bit Bit direction Master CPU Slave CPU method Address AD 1 transmissi 1 1 J bitor reception AD bit AD bit 8 bit address Asynchro LSB first or transmission transmission nous MSB first Data AD 0 reception reception S on 7 bit or reception 8 bit data Communication procedure Communication is started by transmitting address data from the master CPU The address data whose AD bit is set as 1 determines the slave CPU to be the destination Each slave CPU checks address data by using a program and communicates with the master CPU when the data matches an assigned address Figure 22 7 15 shows a flowchart for master slave mode communication 412 FUJITSU MICROELECTRONICS
443. me base timer control register TBTC TCLR is set to 1 the counter of the time base timer is initialized to 3FFFFF and continues to count down When the selected interval time has elapsed the time base timer interrupt request flag bit of the time base timer control register TBTC TBIF becomes 1 In other words an interrupt request is generated at each interval time selected based on the time when the counter was last cleared 140 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 10 TIME BASE TIMER MB95130 MB Series 10 5 Explanation of Time base Timer Operations and Setup Procedure Example E Clearing Time base Timer If the time base timer is cleared when the output of the time base timer is used in other peripheral functions this will affect the operation by changing the count time or in other manners When clearing the counter by using the time base timer initialization bit TBTC TCLR perform setup so that this does not have unexpected effects on other peripheral functions When the output of the time base timer is selected as the count clock for the watchdog timer clearing the time base timer also clears the watchdog timer The time base timer is cleared not only by the time base timer initialization bit TBTC TCLR but also when the main clock is stopped and a count is required for the oscillation stabilization wait time More specifically the time base timer is cleared in the following situations When moving
444. memory programming erasing is completed further flash memory programming erasing is disabled Setting the bit to 0 Clears the bit Setting the bit to 1 Has no effect on the operation is read from the bit whenever a read modify write RMW instruction is used RDY Flash memory program erase status bit This bit shows the programming erasing status of flash memory Flash memory programming erasing cannot be performed with the RDY bit set to 0 A read reset command can be accepted even when the RDY bit contains 0 The RDY bit is set to 1 upon completion of programming erasing It takes a delay of two machine clock MCLK cycles after the issuance of a program erase command for the RDY bit to be set to 0 Read this bit after for example inserting NOP twice after issuing the program erase command Reserved Reserved bit Be sure to set this bit to O IRQEN Flash memory program erase interrupt enable bit This bit enables or disables the generation of interrupt requests in response to the completion of flash memory programming erasing Setting the bit to 0 Prevents an interrupt request from occurring even when the flash memory operation flag bit is set to 1 FSR RDYIRQ 1 Setting the bit to 1 Causes an interrupt request from occurring even when the flash memory operation flag bit is set to 1 FSR RDYIRQ 1 WRE Flash memory program erase enable bit This bit enables
445. mer Interrupt cycle 0 5 ms 2 1 ms 8 2 ms 32 8 ms at external 4 MHz Watchdog timer Reset generation cycle Main clock at 10 MHz 105 ms Min Sub clock at 32 768 kHz Only for dual clock product 250 ms Min Wild registers ROM data for three bytes can be replaced UART SIO Data transfer is enabled at UART SIO Built in full duplex double buffer Changeable data length 5 6 7 8 bit Built in baud rate generator NRZ method transfer format Error detected function LSB first or MSB first can be selected Serial data transfer is available for clock synchronous SIO and clock asynchronous UART LIN UART A wide range communication speed can be set with the dedicated reload timer Full duplex double buffer Serial data transfer is available for clock synchronous and clock asynchronous LIN function can be used as a LIN master and LIN slave 8 10 bit A D converter Sch 8 bit or 10 bit resolution can be selected 8 16 bit compound timer Can be configured as a 2ch x 8 bit timer or Ich x 16 bit timer Built in timer function PWC function PWM function and capture function Count clock available from internal clocks 7 types or external clocks With square wave output 16 bit PPG PWM mode or one shot mode can be selected Counter operation clock Available from eight selectable clock sources Support for external trigger activation 8 16 bit PPG Can be configured as a 2ch x 8 bit PPG or Ich x 1
446. mit data Data written to this register is serial converted and then outputted B Input Clock The UART SIO uses the output clock internal clock from the dedicated baud rate generator or the input signal external clock from the UCKO pin as its input clock serial clock 314 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 3 Channels of UART SIO 20 3 Channels of UART SIO This section describes the channels of UART SIO E Channels of UART SIO This series contains one channel of the UART SIO Table 20 3 1 and Table 20 3 2show the correspondence of sthe channel pin and register Table 20 3 1 Pins of UART SIO Channel Pin name Pin function Clock input output Data output Data input Table 20 3 2 Registers of UART SIO Channel Register name Corresponding register Representation in this manual UART SIO serial mode control register 1 UART SIO serial mode control register 2 UART SIO serial status and data register UART SIO serial output data register UART SIO serial input data register CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 315 CHAPTER 20 UART SIO 20 4 Pins of UART SIO MB95130 MB Series 20 4 Pins of UART SIO This section describes the pins related to the UART SIO E Pins Related to UART SIO The pins associated with UART SIO are the clock input and output pin UCKO serial data output pin UOO and serial d
447. mode 1 overrun and framing errors can be detected But parity errors cannot be detected Parity You can specify whether or not to add at transmission and detect at reception a parity bit The parity enable bit SCR PEN can be used whether or not to use a parity the parity selection bit SCR P can be used to select the odd or even parity In operation mode 1 the parity cannot be used Figure 22 7 2 Transmission Data when Parity is Enabled Parity error is generated in even parity during reception SCR P 0 SP Transmission of even parity SCR P 0 Transmission of odd parity SCR P 1 AO 313950995 lt cooo oo Data Parity ST Start bit SP Stop bit Parity used PEN 1 Note In operation mode 1 the parity cannot be used Data signaling NRZ data format Data transfer method The data bit transfer method can be the LSB first or MSB first 400 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART 22 7 2 Operation of Synchronous Mode Operation Mode 2 When LIN UART is used in operation mode 2 normal mode the transfer method is clock synchronous E Operation of Synchronous Mode Operation Mode 2 Q Transmit reception data format In synchronous mode you can transmit and receive 8 bit data and select whether or not to include the start bit and stop bit ECCR SSM Wh
448. n Only for 5V products it is an effective register Table 9 4 3 lists the correspondence between port F pins and each register bit Table 9 4 3 Correspondence Between Registers and Pins for Port F Correspondence between related register bits and pins Pin name DDRF ILSR2 Only for 5V products it is an effective register 122 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 4 Port F 9 4 2 Operations of Port F This section describes the operations of port F E Operations of Port F Operation as an output port Setting the corresponding DDR register bit to 1 sets a pin as an output port Fora peripheral function sharing pins disable its output When a pin is set as an output port it outputs the value of the PDR register to pins fdatais written to the PDR register the value is stored in the output latch and output to the pin as it is Reading the PDR register returns the PDR register value Operation as an input port Setting the corresponding DDR register bit to 0 sets a pin as an input port e If data is written to the PDR register the value is stored in the output latch but not output to the pin Reading the PDR register returns the pin value However the read modify write command returns the PDR register value Q Operation at reset Resetting the CPU initializes the DDR register value
449. n 242 Channels of 8 16 bit PPG 241 Interrupts of 8 16 bit PPG suus 252 Notes on Using 8 16 bit PPG 260 Overview of 8 16 bit PPG usus 238 Pins of 8 16 bit PPG eee 242 Registers and Vector Table Related to Interrupts of 8 16 bit PPG cecene 252 Registers of 8 16 bit PPG ues 243 Sample Programs for 8 16 bit PPG Timer 261 8 16 bit PPG Output Inversion Register 8 16 bit PPG Output Inversion Register ENG 251 8 16 bit PPG Start Register 8 16 bit PPG Start Register PPGS 250 8 16 bit PPG Timer 00 Control Register 8 16 bit PPG Timer 00 Control Register ch 0 uo nOD 246 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register 01 00 ipiius iernii enini 248 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register 8 16 bit PPG Timer 00 01 Duty Setup Buffer Register 08501 800 249 8 16 bit PPG Timer 01 Control Register 8 16 bit PPG Timer 01 Control Register ch 0 POOT pes tc 244 8 bit Independent Mode Operation of 8 bit PPG Independent Mode 254 Setting 8 bit Independent Mode 254 8 bit Prescaler 8 bit PPG Operation of 8 bit Prescaler 8 bit PPG Petreius 256 Setting 8 bit Prescaler 8 6
450. n Mode 196 Interval Timer Function One shot Mode 196 Operation of Interval Timer Function Continuous 221 Operation of Interval Timer Function Free run Mode 2 223 Operation of Interval Timer Function One shot Mode 219 Operation of Interval Timer Function Watch 164 When Interval Timer Input Capture or PWC Function Has Been Selected 234 L LIN LIN Master Device eese 415 LIN Master Slave Mode Communication Function 414 LIN Slave DeviGe 3 ences caes ione inna aia terius 416 LIN mode Asynchronous LIN Mode Operation 405 LIN synch field LIN Synch Field Edge Detection Interrupt 8 16 bit Compound Timer Interrupt 381 LIN UART Bit Configuration of LIN UART Baud Rate Generator Register 1 0 BGR1 BGRO 378 Bit Configuration of LIN UART Extended Communication Control Register ECCR 376 Bit Configuration of LIN UART Extended Status Control Register ESCR 374 Block Diagram of LIN UART Pins 364 Functions of LIN UART eese 356 LIN UART Baud Rate Selection 387 LIN UART Block Diagram 359 Operation of LIN UART
451. n enable bit MSVE This bit enables the monitoring of main clock oscillation Main clock When set to 0 The bit disables main clock monitoring monitoring When set to 1 The bit enables main clock monitoring enable bit This bit is set to 1 only when a power on reset occurs SSVE This bit enables the monitoring of sub clock oscillation Sub clock When set to 0 The bit disables sub clock monitoring monitoring When set to 1 The bit enables sub clock monitoring enable bit This bit is set to 1 only when a power on reset occurs This bit enables reset output upon transition to sub mode SRST When set to 0 The bit prevents a reset upon transition to sub clock mode with the sub clock Reset generation halted in main clock mode enable bit When set to 1 The bit causes a reset upon transition to sub clock mode with the sub clock halted in main clock mode This bit is reserved Reserved pur Write 0 to this bit The read value is always 0 Note When the power is turned on the clock supervisor starts monitoring after the oscillation stabilization wait time for the main clock elapses The oscillation stabilization wait time of the main clock must therefore be longer than the time required for the clock supervisor to start operating CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 459 CHAPTER 25 CLOCK SUPERVISOR 25 4 Operations of Clock Supervisor MB95130 MB Series 25 4 Operations of Clock
452. n for timer 01 when the PWC timer or input capture function has been selected The pin cannot be set as the external count clock input pin when the PWC timer or input capture function has been selected This input is not used during 16 bit operation The input can be used as well when the PWM timer function has been selected variable cycle mode To use this input feature set the port direction register DDRO bit2 to set the pin as an input port FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 4 Pins of 8 16 bit Compound Timer Bi Block Diagram of Pins Related to 8 16 bit Compound Timer Figure 15 4 1 Block Diagram of Pins TOO0 and TO01 Related to 8 16 bit Compound Timer Peripheral function input Peripheral function input enable Peripheral function output enable 4 Hysteresis L Peripheral function output ell cese dl 0 Pull up 0 1 Lo SN gt P ch PDR read 1 Automotive r1 Pin Le PDR 0 PDR write Only P24 is selectable In bit operation instruction T gum T9 27 nz DDR read o a DDR g DDR wri o write Stop Watch SPL 1 PUL read ur PUL PUL write ILSR2 read gt ILSR2 ILSR2 write m
453. n if the peripheral function output is enabled Therefore the output value of a peripheral function can be read by the read operation on PDR register However the read modify write command returns the PDR register value Operation as a peripheral function input Set the DDR register bit which is corresponding to the peripheral function input pin to 0 to set a pin as an input port Reading the PDR register returns the pin value regardless of whether the peripheral function uses an input pin However the read modify write command returns the PDR register value Operation at reset Resetting the CPU initializes the DDR register values to 0 and sets the port input enabled 118 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 9 I O PORT MB95130 MB Series 9 3 Port 1 Operation in stop mode and watch mode fthe pin state specification bit in the standby control register STBC SPL is set to 1 when the device switches to stop or watch mode the pin is set forcibly to the high impedance state regardless of the DDR register value Note that the input is locked to L level and blocked in order to prevent leaks due to freed input However if the interrupt input of P10 U10 P12 UCKO ECO P13 TRGO ADTG port is enabled for the external interrupt control register EIC of the external interrupt circuit and the interrupt pin selection circuit control register WICR of the external interrupt selection circuit the input is
454. n neuin nannaa aa enne entren nnns sitne nennen sinis enne 185 14 3 Registers of Wild Register 187 14 3 1 Wild Register Data Setup Registers WRDRO to WRDR2 189 14 3 2 Wild Register Address Setup Registers WRARO to WRAR2 190 14 3 8 Wild Register Address Compare Enable Register WREN 191 14 3 4 Wild Register Data Test Setup Register WROR 192 14 4 Operating Description of Wild Register sesssssssseeeeenennenenennen nennen nennen 193 14 5 Typical Hardware Connection Example esssssessseeeeeeeeeenee nennen nnne 194 CHAPTER 15 8 16 BIT COMPOUND TIMER eeeeeee nennen nnn 195 15 1 Overview of 8 16 bit Compound Timer sess eene nennen enne nnn nennen 196 15 2 Configuration of 8 16 bit Compound Timer 198 15 3 Channels of 8 16 bit Compound Timer ssssssssssssssssseseeeeen nennen nnne nennen enis 201 15 4 Pins of 8 16 bit Compound Timer sse 202 15 5 Registers of 8 16 bit Compound Timer sess nensis 204 15 5 1 8 16 bit Compound Timer 00 01 Co
455. n of A D ADI conversion Interrupt request Interrupt requests are output when this bit and the interrupt request enable bit ADC2 ADIE flag bit are both 1 When written to this bit 0 clears it 1 leaves it unchanged with no affect on others When read by a read modify write RMW instruction the bit returns 1 Indicates that conversion is ongoing during execution of the A D conversion function The bit contains 1 during conversion This bit is read only Any value attempted to be written is meaningless and has no effect on operation ADMV Conversion flag bit Controls the analog switch for shutting down the internal reference power supply ADMVX When the external impedance of the AVR pin is high rush current flows immediately after A D Analog switch for startup and may affect A D conversion precision In this kind of situation this can be avoided by shutting down setting this bit to 1 before A D startup Set the bit to 0 before switching to standby mode in control bit order to reduce current consumption Note that some series do not have AVR pins and are internally connected to AVcc Starts the A D conversion function via software Writing 1 to the bit starts the A D conversion function Note Writing 0 to this bit will not stop operation of the A D conversion function The value read is always 0 A D conversion startup by this bit is disabled with EXT 1 A D converter re starts by
456. nal Interrupt Circuit 296 Operation of Input Capture Function 231 Operation of Interval Timer Function Continuous 221 Operation of Interval Timer Function Free run Mode sess 223 Operation of Interval Timer Function One shot Mode 219 Operation of PWC Timer Function 229 Operation of PWM Timer Function Fixed cycle Mode 225 Operation of PWM Timer Function Variable cycle Mode 227 Operations of Port 0 113 Operations of Port 1 0 teens 118 Operations of Port 123 Operations of Port 128 Read modify write Operation 514 Operation mode Operating Description of UART SIO Operation Mode E eet ina au Raed 329 Operating Description of UART SIO Operation Mode pop 336 Operation of Synchronous Mode Operation Mode 2 401 Oscillation stabilization wait time Oscillation stabilization wait time 52 Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition 53 PLL Clock Oscillation Stabilization Wait Time 53 Oscillation circuit Clock Oscillator Circuit eeeeeeeeee 79 Other Instructions Other Instructions cccccceeece
457. nal interrupt and low voltage detection reset while retaining the contents of registers and RAM that exist immediately before the transition to time base timer mode You can start or stop sub clock oscillation by setting the sub clock oscillation stop bit in the system clock control register SYCC SUBS When the sub clock is oscillating the watch prescaler and watch counter operate Transition to time base timer mode Writing 1 to the watch bit in the standby control register STBC TMD causes the device to enter time base timer mode if the system clock monitor bits in the system clock control register SYCC SCMI SCMO are 10g or 11g The device can enter time base timer mode only when the clock mode is main clock mode or main PLL clock mode Upon transition to time base timer mode the states of external pins are retained when the pin state setting bit in the standby control register STBC SPL is 0 and the states of external pins become high impedance when that bit is 1 those pins are pulled up for which pull up resistor connection has been selected in the pull up setting register Cancellation of time base timer mode The device is released from time base timer mode in response to a reset time base timer interrupt or external interrupt You can start or stop sub clock oscillation by setting the sub clock oscillation stop bit in the system clock control register SYCC SUBS When the sub clock is oscillating you c
458. ned upon completion of A D conversion During A D conversion the values resulting from the last conversion are loaded Do not re select the analog input channel ADC1 ANS3 to ANSO while the A D conversion function is running in particular during continuous activation Disable continuous activation ADC2 EXT 0 before re selecting the analog input channel Starting the reset stop or watch mode stops the 8 10 bit A D converter and initializes each register CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 441 CHAPTER 23 8 10 BIT A D CONVERTER 23 6 Operations of 8 10 bit A D Converter and Its Setup MB95130 MB Series Procedure Examples E Setup Procedure Example Follow the procedure below to set up the 8 10 bit A D converter Initial setting 1 Set the port for input DDRO 2 Set the interrupt level ILR4 3 Enable A D input ADC1 ANSO to ANS3 4 Set the sampling time ADC2 TIMI TIMO 5 Select the clock ADC2 CKDIV 1 CKDIVO 6 Set A D conversion properties ADC2 AD8 7 Select the operation mode ADC2 EXT 8 Select the startup trigger ADC2 ADCK 9 Enable interrupts ADC2 ADIE 1 10 Activate A D ADC1 AD 1 Interrupt processing 1 Clear the interrupt request flag ADC1 ADI 0 2 Read converted values ADDH ADDL 3 Activate A D ADC1 AD 1 442 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 7 Notes on Use of 8 10 bit A D Converter 23 7 Not
459. ng 386 Timing Limit Elapsed Flag Timing Limit Elapsed Flag DOS iii aaa 475 TMCR 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 211 Toggle Bit Flag Toggle Bit Flag DQ6 474 Transfer Instructions Transfer Instructions eese 515 Transition An Interrupt Request may Suppress Transition to Standby Mode eee seer renee 71 Check That Clock mode Transition has been Completed before Setting Standby Mode 71 Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition 53 Overview of Transitions to and from Standby Mode etii IM estos 70 Transitions from Overview of Transitions to and from Standby Mode 70 Transmit interrupt 327 380 Transmit Interrupt Generation and Flag Set Timing TERES 385 Transmit Interrupt Request Generation Timing 386 U UART SIO Block Diagram of Pins Related to UART SIO 317 Block Diagram of UART SIO 313 Channels of UART SIO esses 315 Functions of UART SIO esses 312 Interrupts of UART SIO esses 327 Operating Description of UART SIO Operation Mode edv ies tere 329 Operating Description of UART SIO Operation Mode T T 336 Operation of UART SIO
460. ngth to 2 Set to 1 How to clear the error flag Use the reception error flag clear bit SCR CRE Control item Reception error flag clear bit CRE How to set the transfer direction Use the transfer direction selection bit SSR BDS LSB MSB can be selected for transfer direction in any operation mode Control item Serial data direction control BDS To select the LSB first transfer from the least uon f Set to 0 significant bit To select the MSB first transfer from the most NN Set to 1 significant bit How to clear the reception completion flag Uses the following setting Control item Method To clear the reception completion flag Read the RDR register The first RDR register read is the reception initiation 424 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 9 Sample Programs of LIN UART How to clear the transmit buffer empty flag Uses the following setting Control item Method To clear the transmit buffer empty flag Write to TDR register The first TDR register write is the transmit initiation How to select the data format Address Data Only in mode 1 Use the address data selection bit SCR AD To select the data frame Set to 0 To select the address frame Set to 1 This is effective only at transmission The AD bit is ignored at reception How to set the baud rate See Section 22 6 LIN UART Ba
461. ni n A E nennen E nennen 166 12 7 Sample Programs for Watch Prescaler 167 CHAPTER 13 WATCH COUNTER inde inii ae era aaa da 169 13 1 Overview of Watch Counter n nnn nennt neis 170 13 2 Configuration of Watch Counter sssssssssssssssssseene enne eene nnne nennen nnns nnne enne 171 13 3 Registers of Watch Counter esssssssssssssssssse eene nennen nnns senten nens 173 13 3 1 Watch Counter Data Register WCDR sssssssssssssssseeeeen nennen ennt nens nnne 174 13 3 2 Watch Counter Control Register WCSR sse eene nennen nnne 175 13 4 Intermupts of Watch Counter uocat eter ntt e DE TU ib ua e e Eee eig a 177 13 5 Explanation of Watch Counter Operations and Setup Procedure Example 178 13 6 Notes on Using Watch Counter ssssssssssssesseeee eene nenrr ensi nnns nennen s nnn nennen 180 13 7 Sample Programs for Watch Counter sssssssssssssseseeeeeeeneen enhn nennen nennen nennen tenens 181 CHAPTER 14 WILD REGISTER i i uita quon c i2 IQ UE nec cre 183 14 1 Overview of Wild Register sssssssssssssssseseneeenenne entere nnn sn nenne nnn sin inns rennen 184 14 2 Configuration of Wild Register meciari riun
462. nly Writable is read RO WX Undefined bit Read value is 0 writing has no effect on operation 62 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER 6 6 Standby Control Register STBC MB95130 MB Series Table 6 6 1 Functions of Bits in Standby Control Register STBC Bit name Function STP Stop bit Sets transition to stop mode When set to 0 has no effect on operation When set to 1 the bit causes transition to stop mode When read the bit always returns 0 Note An attempt to write 1 to this bit is ignored if an interrupt request has been issued For details see Section 6 8 1 Notes on Using Standby Mode SLP Sleep bit Sets transition to sleep mode When set to 0 has no effect on operation When set to 1 the bit causes transition to sleep mode When read the bit always returns 0 Note An attempt to write 1 to this bit is ignored if an interrupt request has been issued For details see Section 6 8 1 Notes on Using Standby Mode SPL Pin state setting bit Sets the states of external pins in stop mode time base timer mode and watch mode When set to 0 the bit holds the states levels of external pins in stop mode time base timer mode and watch mode When set to 1 the bit places external pins in a high impedance state in stop mode time base timer mode and watch mode Those pins are pulled up for which pull up resistor connec
463. nly by writing data to the LIN UART transmit data register TDR 380 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 5 Interrupt of LIN UART Bi LIN Synch Field Edge Detection Interrupt 8 16 bit Compound Timer Interrupt Table 22 5 3 shows the interrupt control bits and interrupt factors of the LIN synch field edge detection interrupt Table 22 5 3 Interrupt Control Bits and Interrupt Factors of LIN Synch Field Edge Detection Interrupt Operation mode Interrupt Clearing of Interrupt source source interrupt request enable bit flag Interrupt request flag bit Flag register First falling edge of the LIN synch field ite 0 Mie 0 to Fifth falling edge of TOOCR1 IR the LIN synch field TOOCRI TOOCRI Used bit X Unused bit LIN synch field edge detection interrupt 8 16 bit compound timer interrupt Works for LIN slave operation in operation mode 3 After a LIN synch break is detected the internal signal LS YN is set to 1 at the first falling edge of the LIN synch field and set to 0 after the fifth falling edge When the 8 16 bit compound timer is configured to be input the internal signal and to detect both edges a 8 16 bit compound timer interrupt is generated if enabled The difference in the count values detected by the 8 16 bit compound timer see Figure 22 5 1 corresponds to the 8 bits in the master serial cl
464. nput disable register low AIDRL to 1 e If data is written to the PDR register the value is stored in the output latch but not output to the pin Reading the PDR register returns the pin value However the read modify write command returns the PDR register value Operation as a peripheral function output Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore the output value of a peripheral function can be read by the read operation on PDR register However the read modify write command returns the PDR register value Operation as a peripheral function input Set the DDR register bit which is corresponding to the peripheral function input pin to 0 to set a pin as an input port As with an input port when using the analog input shared pin as another peripheral function input configure it as an input port Reading the PDR register returns the pin value regardless of whether the peripheral function uses an input pin However the read modify write command returns the PDR register value Operation at reset Resetting the CPU initializes the DDR register values to 0 and sets the port input enabled Note that the pin sharing for the analog input is set its port input disabled since A D input disable register low AIDRL is initialized to 0
465. nput capture falling counter clear 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Input capture both edges counter clear C2 C1 co Count clock select bits 0 0 1 x MCLK machine clock 1 2 x MCLK machine clock 0 1 4 x MCLK machine clock 0 0 0 1 1 0 1 1 1 8 x MCLK machine clock 0 0 1 16 x MCLK machine clock 0 1 1 0 1 1 1 32 x MCLK machine clock 1 27 x External clock IF flag interrupt enable IFE 1 0 IF flag interrupt disabled IF flag interrupt enabled R W Readable writable Read value is the same as write value Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 205 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 5 Registers of 8 16 bit Compound Timer MB951 30 MB Series Table 15 5 1 Functional Description of Each Bit of 8 16 bit Compound Timer 00 01 Control Status Register 0 TOOCRO TO1CR0O 1 2 Bit name Function This bit enables or disables IF flag interrupts IFE Setting this bit to 0 disables IF flag interrupts IF flag interrupt enable Setting this bit to 1 an IF flag interrupt request is outputted when both the IE bit TOOCR1 TOICRI IE and the IF flag TOOCRI TOICRI IF are set to 1 These bits select the count clock The count clock is generated by the prescaler Refer to 6 12 Operating Explanation of Prescaler e Write access to these bits is nullified during timer op
466. nsmit Interrupt Generation and Flag Set Timing Transmit interrupts are generated when the transmit data is transferred from the LIN UART transmit data register TDR to the transmission shift register and then the transmission starts E Transmit Interrupt Generation and Flag Set Timing When the data written to the LIN UART transmit data register TDR is transferred to the transmission shift register and then the transmission starts the next data becomes to be writable SSR TDRE 1 If the transmit interrupt is enabled SSR TIE 1 at this time a transmit interrupt is generated TDRE bit is a read only bit and cleared to 0 only by writing data to the LIN UART transmit data register TDR Figure 22 5 4 shows the timing of the transmission and flag set Figure 22 5 4 Timing of Transmission and Flag Set Transmit interrupts generated Transmit interrupts generated Modes 0 1 and 3 Write to TDR TDRE E Serial output 7 PsP sr po o p2 ps 4 D5 D6 D7 DSP ST DO D1 D Transmit interrupts generated Transmit interrupts generated Mode 2 SSM 0 Write to TDR TDRE Serial output 5 06 D7 DO D1 D2 D3 D4 D5 D oo pi ve ps v p7 po p pa ST Start bit DO to D7 Data bits P Parity SP Stop bit AD Address data select bit mode 1
467. nterrupt occurs Figure 20 7 15 8 bit Transmission in Synchronous CLK Mode Writing to TDRO UCKO SE E Do 1 ps pa 05 06 07 Interrupt After falling of UCKO Interrupt After last 1 bit cycle to interrupt when external clock to interrupt when internal clock controller is enabled controller is enabled 340 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB951 30 MB Series 20 7 Explanation of UART SIO Operations and Setup Procedure Example Q Concurrent transmission and reception When external clock is enabled gt Transmission and reception can be performed independently of each other Transmission and reception can therefore be performed at the same time or even when their phases are shifted from each other and overlapping lt When internal clock is enabled gt As the transmitting side generates a serial clock reception is influenced If transmission stops during reception the receiving side is suspended It resumes reception when the transmitting side is restarted Refer to 20 4 Pins of UART SIO for operation with serial clock output and operation with serial clock input CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 341 CHAPTER 20 UART SIO 20 8 Sample Programs for UART SIO MB951 30 MB Series 20 8 Sample Programs for UART SIO We provide sample programs that can be used to operate UART SIO il Sample Programs for UART SIO
468. nterrupts Works for LIN slave operation in operation mode 3 The LIN synch break detection flag bit LBD in the LIN UART extended status control register ESCR is set to 1 when the internal data bus serial input is 0 for 11 bits or longer The LIN synch break interrupt and the LBD flag are cleared by writing 0 to the LBD flag The LBD flag must be cleared before the 8 16 bit compound timer interrupt is generated in the LIN synch field To detect a LIN synch break the reception must be disabled SCR RXE 0 B Transmit Interrupts Table 22 5 2 shows the interrupt control bits and interrupt factors of transmit interrupts Table 22 5 2 Interrupt Control Bits and Interrupt Factors of Transmit Interrupts Interrupt request flag bit Flag Operation mode register Interrupt request Clearing of enable bit interrupt request flag Interrupt factor empty O Used bit Transmit interrupt The transmit data register empty flag bit TDRE in the LIN UART serial status register SSR is set to 1 when the transmit data is transferred from the LIN UART transmit data register TDR to the transmission shift register and the transmission starts If the transmit interrupt is enabled SSR TIE 1 in this case a transmit interrupt request is generated Note Since the initial value of TDRE is 1 an interrupt is generated immediately after the TIE bit is set to 1 after hardware software reset Also the TDRE is cleared o
469. nterrupts see Section 8 1 Interrupts FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 5 CPU MB951 30 MB Series 5 2 General purpose Registers 5 2 General purpose Registers The general purpose registers are memory blocks consisting of eight 8 bit registers per bank A total of up to 32 register banks can be used The register bank pointer RP is used to specify the register bank Register banks are useful for interrupt handling vector call processing and subroutine calls E Configuration of General purpose Registers The general purpose registers are 8 bit registers and are located in register banks in the general purpose register area in RAM e Up to 32 banks can be used where each bank consists of eight registers RO to R7 e The register bank pointer RP specifies the register bank currently being used and the lower three bits of the op code specify general purpose register 0 RO to 7 R7 Figure 5 2 1 shows the configuration of the register banks Figure 5 2 1 Configuration of Register Banks 8 bits 4 e 1F84 107 Bank 31 32 banks The number of banks available is restricted by the RAM capacity available Memory area For information on the general purpose register area available on each model see Section 3 1 1 Areas for Specific Applications CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 41 CHAPTER 5 CPU 5 2 General purpose Registers MB95130 MB
470. ntrol Status Register 0 TOOCRO T01CRO 205 15 5 2 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCR1 TO1CR1 208 15 5 3 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 211 15 5 4 8 16 bit Compound Timer 00 01 Data Register ch 0 TOODR TO1DR 214 15 6 Interrupts of 8 16 bit Compound Timer ssssssssssssseseseeeeenennenneen nennen nensi nnne 217 15 7 Operating Description of Interval Timer Function One shot 219 15 8 Operating Description of Interval Timer Function Continuous 221 15 9 Operating Description of Interval Timer Function Free run 223 15 10 Operating Description of PWM Timer Function Fixed cycle mode 225 15 11 Operating Description of PWM Timer Function Variable cycle Mode 227 15 12 Operating Description of PWC Timer Function sssssssesseseseeeeeneeeneneeen eene 229 15 13 Operating Description of Input Capture Function nens 231 15 14 Operating Description of Noise Filter sssessssssseseeeeeeneeenenneneeenn nennen enne nnne enis 233 15 15 States in Each Mode during Operation
471. ntroller BB Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners E Sample Programs Fujitsu provides sample programs free of charge to operate the peripheral resources of the F MC 8FX family of microcontrollers Feel free to use such sample programs to check the operational specifications and usages of Fujitsu microcontrollers Microcontroller support information http www fujitsu com global services microelectronics product micom support Note that sample programs are subject to change without notice As these pieces of software are offered to show standard operations and usages evaluate them sufficiently before use with your system Fujitsu assumes no liability for any damages whatsoever arising out of the use of sample programs The contents of this document are subject to change without notice Customers are advised to consult with sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the info
472. ntroller Using Parallel Writer 521 WROR Wild Register Data Test Setup Register WROR 192 Register Index A AIDRL A D input disable register lower 108 D DDRO Port O direction register 108 DDR1 Port 1 direction register 108 DDHRF Port F direction register 108 DDRG Port direction register 108 E EICOO External interrupt control register ch 0 ch 1 REUS 293 EIC10 External interrupt control register ch 2 ch 3 aaa nec unde 293 EIC20 External interrupt control register ch 4 ch 5 duo dama tede 293 EIC30 External interrupt control register ch 6 ch 7 293 ILSR Input level selection register 108 ILSR2 Input level selection register 2 108 P PCOO 8 16 bit PPG timer 00 control register ch 0 246 PCO1 8 16 bit PPG timer 01 control register ch 0 rem 244 PC10 8 16 bit PPG timer 00 control register ch 1 246 11 8 16 bit timer 01 control register ch 1 ELE nr tees 244 PCNTHO 16 bit PPG status control register upper Cli 0X em adiit te 273 PCNTLO 16 bit PPG status control register lower HS 273 PCSRHO 16 bit PPG cycle setting buffer register upper CH O 271 PCSRLO 16 bit PPG cycle setting buffer registe
473. o the read reset state The individual operations are explained in the following order Enter read reset state Program data Erase all data chip erase 476 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 6 Flash Memory Program Erase 26 6 1 Placing Flash Memory in the Read Reset State This section explains the procedure for entering the read reset command to place flash memory in the read reset state E Placing Flash Memory in the Read Reset State To place flash memory in the read reset state send the read reset command in the command sequence table continuously from the CPU to flash memory The read reset command is available in two different command sequences one involves a single bus operation and the other involves four bus operations which are essentially the same Since the read reset state is the initial state of flash memory the flash memory always enters this state after the power is turned on and at the normal termination of a command The read reset state is also described as the wait state for command input In the read reset state read access to flash memory enables data to be read As is the case with masked ROM program access from the CPU can be made Read access to flash memory does not require the read reset command If a command is not terminated normally use the read reset command to initialize the automatic algorithm CM26
474. o the serial I O pin Normal read instruction always returns the value of the SIN pin When direct access to the serial output pin data is enabled SOPE 1 the value written to this bit reflects the SOT pin Note The bit operation instruction returns the bit value of the SOT pin in the read cycle CCO Continuous clock output enable bit Enable or disable continuous serial clock output from the SCK pin Setting this bit to 1 with sending side of serial clock in operation mode 2 synchronous enables the continuous serial clock output from the SCK pin if the pin is set as a clock output Note When the CCO bit is 1 the SSM bit in the should be 1 SCES Sampling clock edge select bit Interaction between SOPE and SIOP No effect however the write value is retained Select a sampling edge Setting the SCES to 1 in reception side of serial clock in operation mode 2 synchronous switches the sampling edge from the rising edge to the falling edge When the SCK pin is set as the clock output with sending side of serial clock ECCR MS 0 in operation mode 2 the internal serial clock and the output clock signal are inverted This bit should be 0 in operation modes 0 1 and 3 Write to SIOP Read from SIOP Return the SIN value Write 0 or 1 to SOT Return the SIN value CM26 10118 3E FUJITSU Read the SOT value write 0 or 1 MICROELECTRONICS LIMITED 375
475. ock The new baud rate can be calculated from this value When a new baud rate is set the rate become effective from the falling edge detection of the specified next start bit Figure 22 5 1 Baud Rate Calculation by 8 16 bit Compound Timer LIN synch field H Reception data Stat 0 1 2 3 4 5 6 7 Stop Data 55u Internal signal LSYN orca compound timer Difference in count values Capture value 2 Capture Value 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 381 CHAPTER 22 LIN UART 22 5 Interrupt of LIN UART MB95130 MB Series E Register and Vector Table Related to LIN UART Interrupt Table 22 5 4 Register and Vector Table Related to LIN UART Interrupt Interrupt Interrupt level setting Vector table address request register Interrupt sources number Registers Setting bit Upper Lower Reception Transmission 382 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 5 Interrupt of LIN UART 22 5 1 Reception Interrupt Generation and Flag Set Timing Reception interrupts are a reception completion and an occurrence of a reception error E Reception Interrupt Generation and Flag Set Timing Received data is stored in the LIN UART reception data register RDR when the first stop bit is detected in mode 0 1 2 SSM 1 3 or when the last data bit is detected in mode 2 SSM
476. ode Dual clock product 65 Operations in Sub PLL Clock Mode Dual clock product 65 E ECCR Bit Configuration of LIN UART Extended Communication Control Register ECCR 376 Edge Detection Interrupt LIN Synch Field Edge Detection Interrupt 8 16 bit Compound Timer Interrupt 381 EIC External Interrupt Control Register EICOO 293 Enable Transmission Reception Enable Transmission Reception 396 Erasing Details of Programming Erasing Flash Memory 476 Erasing All Data from Flash Memory Chip Erase ertet 480 Flash memory program erase 466 Notes on Chip 480 ESCR Bit Configuration of LIN UART Extended Status Control Register ESCR 374 Example Setup Procedure Example 253 281 297 Explanation Explanation of Addressing 506 Explanation of Display Sign of Instruction 504 Explanation of Item in Instruction Table 505 External Clock External Clock eee a 391 External Interrupt Circuit Block Diagram of External Interrupt ES a 289 Block Diagram of Pins Related to External Interrupt iiiter potete 291 Channels of External Interrupt Circuit 290 Functions of External Interrupt Circuit 288
477. ode or watch mode set the pin state in stop mode time base timer mode and watch mode and to control the generation of software resets Standby Control Register STBC Figure 6 6 1 Standby Control Register STBC Address pit7 bit6 bit 006 5 sle sRST TMD 00000005 ROW ROW R W ROW RO W RO WX RO WX RO WX bit4 bit3 bit2 bit1 bitO Initial value Watch bit Read Write 0 0 Always reads Has no effect on the operation Main clock mode Sub clock mode Main PLL clock mode Sub PLL clock mode Causes transition to Causes transition to time base time r mode watch mode Software reset bit Read Write 0 Always reads 0 Has no effect on the operation Generates a 3 machine clock reset signal Pin state setting bit Holds external pins in their immediately preceding state in stop mode time base timer mode or watch mode 1 Places external pins in a high impedance state in stop mode time base timer mode or watch mode Sleep bit SLP Read Write 0 Always reads 0 Has no effect on the operation 1 Causes transition to sleep mode Stop bit TP 8 Read Write 0 Always reads 0 Has no effect on the operation Causes transition to stop mode Undefined Initial value R W Readable writable Read value is the same as write value RO W Write o
478. of MB95130 MB Series sssssssssssssseeeeeeennenn nnne nennen nnns innen 9 1 5 ispum LEE 10 1 6 Package Dimension etta ttr te d RR 12 1 7 ilg OSCHPUOM Ee Pr 14 1 8 VO Circuit Typ c c EUER 16 CHAPTER 2 HANDLING DEVICES 19 2 1 Device Handling Precautions ict tote rette i rp ete e ere AAE TA RASA 20 CHAPTER S MEMORY SPACE narra rir nnd aa dui mE YR Rad aga 25 3 1 2 26 3 1 1 Areas for Specific Applications 28 3 2 Memor Map rere i tene ee eae t be at o Dette e pet Daten 29 CHAPTER 4 MEMORY ACCESS nnn nnn nnn nnn nnn 31 4 1 Meimory Access MOGde iin ette Posti red te este e dee ede de ies 32 CHAPTEHRH 5 E e uut 33 5 1 Dedicated Registers Rm 34 5 1 1 Register Bank Pointer RP e e a aia 36 5 1 2 Direct Bank Pointer D Po totes ERU bel e ee EOS Ee Ee rente e 37 5 1 3 Condition Code Register sss 39 5 2 General purpose Registers eene nnne nennen 41 5 3 Placement of 16 bit Data in Memory sssssssssseeeeeeenn eene enne 43 CHAPTER 6 CLOC
479. of Registers of External Interrupt en ic celine Stee 292 Low voltage Detection Reset Circuit Block Diagram of Low voltage Detection Reset Circuit MIS M MELLE e EM a ees Ef re 449 Low voltage Detection Reset Circuit 448 Operations of Low voltage Detection Reset Circuit QD ERE 451 Pins Related to Low voltage Detection Reset Circuit wait 450 M Main clock Operation at the Main Clock Stop Mode 179 Main Clock Mode Operations in Main Clock Mode 65 Main PLL clock mode Operations in Main PLL Clock Mode 65 Manipulation Read Destination on the Execution of Bit Manipulation Instructions 514 Mask Option List Mask Option List eese 519 Master LIN Master Slave Mode Communication Function ccc 414 Master slave mode communication function 411 Master Device LIN Master Device essere 415 530 Master Slave LIN Master Slave Mode Communication Function 414 Master slave mode communication function 411 MB95130 MB Series Block Diagram of All MB95130 MB Series 9 Feature of MB95130 MB 2 Pin Assignment of MB95130 MB Series 10 Product Lineup of MB95130 MB Series 4 MDSE One shot Mode MDSE of PCNTHO Register 280 PWM Mode MDS
480. off the digital power supply Vcc either at the same time as or after turning off the 8 10 bit A D converter power supply AV cc AVss and analog input ANOO to ANO7 Be careful not to let the AVcc AVss and analog input exceed the voltage of the digital power supply when turning the 8 10 bit A D converter on and off Conversion time The conversion speed of the A D conversion function is affected by the clock mode main clock oscillation frequency and main clock speed switching gear function Example Sampling time CKIN x ADC2 TIMI TIMO setting CM26 10118 3E Compare time CKIN x 10 fixed value MCLK AD start processing time Min MCLK MCLK Max MCLK CKIN Conversion time A D start processing time sampling time compare time The error max 1 CKIN 1MCLK may occur depending on the timing of AD startup Program the software satisfied with sampling time and compare time in A D converter of data sheet FUJITSU MICROELECTRONICS LIMITED 443 CHAPTER 23 8 10 BIT A D CONVERTER 23 8 Sample Programs for 8 10 bit A D Converter MB951 30 MB Series 23 8 Sample Programs for 8 10 bit A D Converter Fujitsu provides sample programs to operate the 8 10 bit A D converter E Sample Programs for 8 10 bit A D Converter For sample programs for the 8 10 bit A D converter see Il Sample Programs in Preface E Setting Methods not Covered by Sample Programs Selecting the operating clock for the 8 1
481. ols the clocks resets and other settings based on the information in the CSV control register CSVCR CR oscillator circuit This block is a internal CR oscillator circuit The oscillation can be turned on or off via a control signal from the control circuit This also serves as an internal clock after a clock halt is detected Main clock monitor This block monitors whether the main clock halts Sub clock monitor This block monitors whether the sub clock halts Main clock selector This block outputs the CR clock as the internal main clock upon detection of a main clock halt Sub clock selector This block outputs the clock obtained by dividing the CR clock as the internal sub clock upon detection of a sub clock halt CSV control register CSVCR This block is used to control clock monitoring and CR clock and to check information on halt detection FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 25 CLOCK SUPERVISOR MB951 30 MB Series 25 3 Register of Clock Supervisor 25 3 Register of Clock Supervisor This section describes the clock supervisor registers E Register of Clock Supervisor Figure 25 3 1 shows the register of the clock supervisor Figure 25 3 1 Clock Supervisor Register Clock supervisor control register CSVCR bit 7 6 5 4 3 2 1 0 Address Reserv Reserv Initial value 000FEA d MM SM RCE MSVE SSVE SRST ed 000111006 R W R R R W R W R
482. omatic algorithm has been started read access to the specified address is ignored Data reading is allowed after the data polling flag DQ7 is set to 1 Data reading after the end of the automatic algorithm should be performed following read access made to confirm the completion of data polling CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 473 CHAPTER 26 256 Kbit FLASH MEMORY 26 5 Checking the Automatic Algorithm Execution Status MB95130 MB Series 26 5 2 Toggle Bit Flag DQ6 The toggle bit flag DQ6 is a hardware sequence flag used to indicate that the automatic algorithm is being executed or has been completed using the toggle bit function E Toggle Bit Flag 006 Table 26 5 5 and Table 26 5 6 show the state transition of the toggle bit flag Table 26 5 5 State Transition of Toggle Bit Flag During Normal Operation Chip erase gt Erasing completed 06 Toggle DATA 6 Toggle Stop Programming Programming completed Operating state Table 26 5 6 State Transition of Toggle Bit Flag During Abnormal Operation At programming and chip erasing When read access is made continuously during execution of the automatic write algorithm or chip erase sector erase algorithm the flash memory toggles the output between 1 and 0 at each read access e When read access is made continuously after the automatic write algorithm or chip erase sector erase algorithm is terminated the flash memory outp
483. onfiguration of Low voltage Detection Reset Circuit 24 3 Pins of Low voltage Detection Reset Circuit 24 4 Operations of Low voltage Detection Reset Circuit Code CM26 00111 2E Page 450 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 447 CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT 24 1 Overview of Low voltage Detection Reset Circuit MB951 30 MB Series 24 1 Overview of Low voltage Detection Reset Circuit The low voltage detection reset circuit monitors the power supply voltage and generates a reset signal if the voltage drops below the detection voltage level available as an option to 5 V products only Low voltage Detection Reset Circuit This circuit monitors the power supply voltage and generates a reset signal if the voltage drops below the detection voltage level The circuit can be selected as an option to 5 V products only Refer to the data sheet for details of the electrical characteristics 448 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 24 LOW VOLTAGE DETECTION RESET CIRCUIT MB95130 MB Series 24 2 Configuration of Low voltage Detection Reset Circuit 24 2 Configuration of Low voltage Detection Reset Circuit Figure 24 2 1 is a block diagram of the low voltage detection reset circuit E Block Diagram of Low voltage Detection Reset Circuit Figure 24 2 1 Block Diagram of Low voltage Detection Reset Circuit Reset signal CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 449
484. or continuously upon activation enable detection of the rise of the input clock signal bit Select the clock to use for A D conversion The input clock is generated by the prescaler See CKDIV1 CHAPTER 6 CLOCK CONTROLLER CKDIVO The sampling time can also be changed via this clock selection Clock select bits Change this setting depending on the operating conditions voltage and frequency Note Update this bit only with A D operation stopped CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 437 CHAPTER 23 8 10 BIT A D CONVERTER 23 4 Registers of 8 10 bit A D Converter MB951 30 MB Series 23 4 3 8 10 A D Converter Data Registers Upper Lower ADDH ADDL The 8 10 bit A D converter data registers upper lower ADDH ADDL contain the results of 10 bit A D conversion The high order two bits of 10 bit data correspond to the ADDH register the low order eight bits correspond to the ADDL register E 8 10 bit A D Converter Data Registers Upper Lower ADDL Figure 23 4 4 8 10 bit A D Converter Data Registers Upper Lower ADDH ADDL ADDH bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value Address SARQ SAR8 000000006 006 RO WX RO WX RO WX RO WX RO WX RO WX ADDL bitlb bitl4 bit13 biti2 bitii bit9 bit8 Initial value Address SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SARO 00000000 OO6F yy R W
485. or next start bit occurs edge Reception is ongoing No further errors regardress of no falling edge CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 421 CHAPTER 22 LIN UART 22 9 Sample Programs of LIN UART MB95130 MB Series 22 9 Sample Programs of LIN UART This section provides sample programs for operating the LIN UART il Sample Programs of LIN UART For sample programs of LIN UART see Sample Programs in Preface E Setting Methods not Covered by Sample Programs How to select the operation mode Use the operation mode selection SMR MD 1 0 Operation mode Operation mode selection MD 1 0 Normal Asynchronous Set to 00g Multiprocessor Set to 01g Normal Synchronous Set to 10g LIN Set to 11g Operation clock types and how to select it Use the external clock select bit SMR EXT Clock input External clock select bit EXT To select a dedicated baud rate generator Set to 0 To select an external clock Set to 1 How to control the SCK SIN and SOT pins Use the following setting LIN UART DDRO P02 0 SMR SCKE 0 To set the SCK pin as input To set the SCK pin as output SMR SCKE 1 To use the SIN pin DDRO P04 0 To use the SOT pin SMR SOE 1 422 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 9 Sample Programs of LIN UART How to enable disable the LIN UART operation Use
486. or table address source Watch prescaler The watch prescaler shares the same interrupt request number and vector table as the watch counter Refer to CHAPTER 8 INTERRUPTS for the interrupt request numbers and vector tables of all peripheral functions Note If the interval time set for the watch prescaler is shorter than the oscillation stabilization wait time of the sub clock an interrupt request of the watch prescaler is generated during the oscillation stabilization wait time of the sub clock required for recovery by an external interrupt upon the transition from the sub clock mode or the sub PLL clock mode to the stop mode To prevent this set the interrupt request enable bit WPCR WTIE in the watch prescaler control register to 0 to disable interrupts of the watch prescaler when entering the stop mode during the sub clock mode or the sub PLL clock mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 163 CHAPTER 12 WATCH PRESCALER 12 5 Explanation of Watch Prescaler Operations and Setup MB95130 MB Series Procedure Example 12 5 Explanation of Watch Prescaler Operations and Setup Procedure Example The watch prescaler operates as an interval timer E Operations of Interval Timer Function Watch Prescaler The counter of the watch prescaler continues to count down using the sub clock divided by two as its count clock as long as the sub clock oscillates When cleared WPCR WCLR 1
487. or the Sub PLL clock sub PLL clock has passed oscillation stability bit When set to 0 the SPRDY bit indicates that the clock controller is in the sub PLL clock Dual clock product oscillation stabilization wait state or that sub PLL clock oscillation has been stopped only This bit is read only Any value written is meaningless On single clock product the value of the bit is meaningless 58 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 5 Oscillation Stabilization Wait Time Setting Register WATR 6 5 Oscillation Stabilization Wait Time Setting Register WATR This register is used to set the oscillation stabilization wait time E Configuration of Oscillation Stabilization Wait Time Setting Register WATR Figure 6 5 1 Configuration of Oscillation Stabilization Wait Time Setting Register WATR Address bit7 bit6 bit5 bit4 o bit2 biti bito Initial value 0005H 11111111B R W RAN R W R W R W RW RW R W Number of Main Oscillation Clock 4 MHz 214 2 About 4 10 ms 2 3 2 Fcu About 2 05ms 21 2 About 1 02ms 2 2 Fcu 511 5 us 21 2 Fcu 255 5 us 29 2 127 5 us 2 2 Fcu 63 5 us 31 5 us 15 5 us i ER k 27 26 25 2 7 5 us 3 5 us 2 2 2 25 2 1 5 us 0 5 us 2 0 0 us 1 2 0 0 us 0 0 us 23 2 22 2
488. ort peripheral function I O SPL 1 Hi Z However the setting of the pull up is effective Input interception resetting Hi Z Input enable However it doesn t function T O port T O port Hi Z Input interception T O port Hi Z Input interception Hi Z Input enable However it doesn t function T O port T O port Hi Z Input interception SPL Pin status specification bit of standby control register STBC SPL Hi Z High impedance T O port Hi Z Input interception Hi Z Input enable However it doesn t function Input enabled means that the input function is in the enabled state After reset setting for internal pullup or output pin is recommended 2 Input disable means direct input gate operation from the pin is disable status 3 For the 5V product the C pin is used 502 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX E Instruction Overview APPENDIX E Instruction Overview This section explains the instructions used in 2 8 E Instruction Overview of 2 8 In F MC 8FX there are 140 kinds of one byte machine instructions as the map 256 bytes and the instruction code is composed of the instruction and the operand following it Figure E 1 shows the correspondence of the instruction code and the instruction map Figure E 1 Instruction
489. ount clock output from the time base timer BB Prescaler The prescaler generates the count clock source for various peripheral resources from the machine clock MCLK that drives the CPU and the count clock Q IFeg or 25 Fcp output from the time base timer The count clock source is a clock frequency divided by the prescaler or a buffered clock used by the peripheral resources listed below Note that the prescaler has no control register and operates continuously driven by the machine clock MCLK and the count clock 27 Foy or 25 Fcp of the time base timer CM26 10118 3E 8 16 bit compound timer 16 bit reload timer 8 16 bit PPG Timer 16 bit PPG timer UART SIO Dedicated Baud Rate Generator 8 10 bit A D converter FUJITSU MICROELECTRONICS LIMITED 81 CHAPTER 6 CLOCK CONTROLLER 6 11 Configuration of Prescaler MB951 30 MB Series 6 11 Configuration of Prescaler Figure 6 11 1 is a block diagram of the prescaler E Prescaler Block Diagram Figure 6 11 1 Prescaler Block Diagram Prescaler 2 MCLK Counter value 4 MCLK Count MCLK lock 8 MCLK clock machine cloc 5 bit source counter Output Ip E to control circuit 32 MCLK individua peripher From 27 F cH 27 resource time base 28 F i CH timer 28 F cH MCLK Machine clock internal operating frequency 5 bit counter The machine clock MCLK is counted by a 5 bit counter and the count value is output to the output cont
490. ounter before use In any standby mode other than the sub clock stop mode the watch counter continues to operate E Operation at the Main Clock Stop Mode The interrupt is not generated though the clock counter continues the count operation when entering the main clock stop mode Moreover the clock counter stops too when sub clock oscillation stop bit SYCC SUBS of the system clock control register is set to 1 E Setup Procedure Example The watch counter is set up in the following procedure Initial setting 1 Set the interrupt level ILR5 2 Select the count clock WCDR CS1 CS0 3 Set the counter reload value WCDR RCTRS to RCTRO 4 Activate the watch counter and enable interrupts WCSR ISEL 1 Interrupt processing 1 Clear the interrupt request flag WCSR WCFLG 0 2 Arbitrary processing CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 179 CHAPTER 18 WATCH COUNTER 13 6 Notes on Using Watch Counter MB95130 MB Series 13 6 Notes on Using Watch Counter Shown below are the precautions that must be followed when using the watch counter If the watch prescaler is cleared during the operation of the watch counter the watch counter may not be able to perform normal operation When clearing the watch prescaler set the ISEL bit of the WCSR register to 0 to stop the watch counter in advance When the operation is reactivated by WCSR ISEL O after counter stop please reactivate after confirming reading
491. ous valid read operation Therefore the value of the 16 bit down counter will not be read correctly 270 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB951 30 MB Series 17 5 Registers of 16 bit PPG Timer 17 5 2 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO The 16 bit PPG cycle setting buffer registers are used to set the cycle for the output pulses generated by the PPG 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO Figure 17 5 3 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO 16 bit PPG cycle setting buffer register upper PCSRHO Address 15 biti4 biti2 bitii bit1O bit8 Initial value OFAC PCSRHO CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 111111116 RW HW HW HW HW HW RW RW 16 bit PPG cycle setting buffer register lower PCSRLO Address bit7 bite bit5 bit4 bit3 bit2 bit bito Initial value OFADu PCSRLO CS07 CS06 C805 CS04 503 C802 CS01 CS00 11111111 RW RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value These registers form a 16 bit register which sets the period for the output pulses generated by the PPG The values set in these registers are loaded to the down counter When writing to these registers always use one of the following procedures e Use the MOVW
492. p parity 0 or 1 s Number of stop bits 1 or 2 Figure 22 7 1 shows the transmit reception data format Operation Mode 0 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 397 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB95130 MB Series Figure 22 7 1 Transmit Reception Data Format Operation Mode 0 1 Operation mode 0 D4 Y D5 i SP SP D1 D1 D2 D2 D3 D3 D6 D6 D1 D2 D3 D6 SP Operation mode 1 D1 D1 2 D3 D3 D6 D6 AD D1 D2 D3 D6 i SP D1 D2 D3 D6 SP ST Start bit SP Stop mode P Parity bit AD Address data bit D1 D2j D3 D6 SP SP SP P None Data 8 bit P Present P None Data 7 bit P Present Data 8 bit Data 7 bit Note When the BDS bit in the LIN UART serial status register SSR is set to 1 MSB first the bits are processed in the order of D7 D6 D1 DO P 398 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART Transmission If the transmit data register empty flag bit TDRE in the LIN UART serial status register SSR 15 1 transmit data can be written into the LIN UART transmit data register TDR Writing
493. pe CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 1 CHAPTER 1 DESCRIPTION 1 1 Feature of MB95130 MB Series MB951 30 MB Series 1 1 Feature of MB95130 MB Series In addition to a compact instruction set the MB95130 MB series is a general purpose single chip microcontroller built in abundant peripheral functions E Feature of MB95130 MB Series F MC 8FX CPU core Instruction system optimized for controllers Multiplication and division instructions e 16 bit operation Bittest branch instruction Bitoperation instructions etc Clock Main clock Main PLL clock Sub clock Only for dual clock product Sub PLL clock Only for dual clock product Timer e Ich x 8 16 bit compound timer Can be used as the interval timer PWM timer PWC timer or the input capture Ich x 8 16 bit PPG e Ichx 16 bit PPG Ich x time base timer e Ich watch prescaler Only for dual clock product 1ch x LIN UART e LIN function and an asynchronous clock or a synchronous clock serial data transfer can be used With full duplex double buffer ich x UART SIO e An asynchronous clock or a synchronous clock serial data transfer can be used With full duplex double buffer External interrupt Interrupt by the edge detection Select from rising edge falling edge or both edges Can be used to recover from low power consumption standby mode 8 10 bit A D converter 8 bit or 10 bit reso
494. pin to a power source even when the 8 10 bit A D converter is not being used This is a ground pin of the 8 10 bit A D converter Use this at the same potential as Vgg When A D conversion precision is required take measures to ensure that noise does not interfere with You should connect this pin to a ground GND even when the 8 10 bit A D converter is not being used FUJITSU MICROELECTRONICS LIMITED 431 CHAPTER 23 8 10 BIT A D CONVERTER 23 3 Pins of 8 10 bit A D Converter MB951 30 MB Series E Block Diagram of Pins Related to 8 10 bit A D Converter Figure 23 3 1 Block Diagram of Pins ANOO to ANO7 Related to 8 10 bit A D Converter Hysteresis PUT BOR a Peripheral function input Peripheral function input enable 1 Peripheral function output enable Only P04 is 1 H A selectable 1 Peripheral function output S 9 Re A U D a PDR v E In bit operation instruction DR read o 2 Stop Watch SPL 1 Internal bus v c T V ILSR2 write LUN 432 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series
495. pt it automatically saves the current program counter PC and program status PS values onto a stack Figure 8 1 5 shows how the stack is used at the start of interrupt processing Figure 8 1 5 Stack Operation at Start of Interrupt Processing Immediate before interrupt p Address Memory Immediate after interrupt 027 xx PS 027D xx ec E 027 Address Memory SP 027 gt 027 0 84 PS 704 027Du ps 027 EO u PC jz 027 xx 027 00 SP 02804 0280 xx Pis EOQ0R 02804 xx 0281 0281 H Stack Operation upon Returning from Interrupt When the interrupt return instruction RETI is executed to end interrupt processing the program status PS and then the program counter PC are restored from the stack in the reverse order from which they were saved to the stack when interrupt processing started This restores the PS and PC values to their states prior to starting interrupt processing Note As the accumulator A and temporary accumulator T are not saved onto the stack automatically use the PUSHW and POPW instructions to save and restore the A and T values 104 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 8 INTERRUPTS MB95130 MB Series 8 1 Interrupts 8 1 6 Interrupt Processing Stack Area The stack area in RAM is used for
496. put Capture Function eese 197 Input Clock eueesse 200 240 266 Operation of Input Capture Function 231 When Interval Timer Input Capture or PWC Function Has Been Selected 234 Input Capture Input Capture Function esee 197 Operation of Input Capture Function 231 When Interval Timer Input Capture or PWC Function Has Been Selected 234 528 Input clock Input clock esis iiie niece bees 82 134 Instruction Arithmetic Operation Instructions 516 Branch Instructions eeeeeeeee 517 Explanation of Display Sign of Instruction 504 Explanation of Item in Instruction Table 505 Instruction Map 518 Instruction Overview of F7MC 8FX 503 Other Instructions eeeeseeee 517 Place at Least Three NOP Instructions Immediately Following a Standby Mode Setting Instr ctiorni eite irent perii 71 Read Destination on the Execution of Bit Manipulation Instructions 514 Special Instruction eee eee ee seen eens 510 Transfer Instructions eeeeeeeeeeeeess 515 Instruction Map Instruction 518 Inter CPU Connection Method Inter CPU Connection Method 396 Interrupt Bloc
497. put held Hi Z Output held Hi Z Output held Hi Z Output held Hi Z Time base TIMER Operating Stopped Operating Stopped Operating Stopped Stopped Stopped Watch Prescaler Operating Operating Operating Operating Operating Operating Operat ing Stopped Watch counter Operating Operating Operating Operating Operating Operating Operat ing 4 Stopped External interrupt Operating Operating Operating Operating Operating Operating Operat ing Operat ing Watchdog timer Operating Operating Stopped Stopped Stopped Stopped Stopped Stopped Low voltage detection reset Operating Operating Operating Operating Operating Operating Operat ing Operat ing Other peripheral functions Operating to 1 2 1 3 1 4 Operating Operating Operating Stopped Stopped system clock control register SYCC SUBS is set to 1 watch counter stops CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED Stopped Stopped Operates when the main PLL clock oscillation enable bit in the PLL control register PLLC MPEN is set Stops when the sub clock oscillation stop bit in the system clock control register SYCC SUBS is set to Operates when the sub PLL clock oscillation enable bit in the PLL cont
498. r 8 bit PPG Mode 256 PPG Timer 16 bit PPG Timer 264 8 16 bit PPG Timer 00 Control Register ch 0 PC00 siete itis 246 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register 01 500 248 8 16 bit Timer 00 01 Duty Setup Buffer Register PDSOI PDSO0 249 8 16 bit PPG Timer 01 Control Register ch 0 RECOM aa e nitido 244 Block Diagram of 16 bit PPG Timer 265 Channels of 16 bit PPG Timer 267 Interrupts of 16 bit PPG 277 Notes on Using 16 bit PPG Timer 282 Pins of 16 bit PPG Timer usus 268 Registers and Vector Table Related to Interrupts of 16 bit PPG 277 Registers of 16 bit PPG Timer 269 Sample Programs for 16 bit PPG Timer 283 Sample Programs for 8 16 bit PPG Timer 261 PPGS 8 16 bit PPG Start Register PPGS 250 PPS 8 16 bit PPG Timer 00 01 Cycle Setup Buffer Register 01 500 248 Prescaler Block Diagram of Watch Prescaler 157 Operation of 8 bit Prescaler 8 bit PPG Moderne titre tes 256 Operations of Prescaler ess 83 PreS alesis
499. r is prohibited When the timer stops operation the timer output bit holds the last output value If the 8 16 bit compound timer 00 01 data register is written over during operation the written data will be effective from the cycle immediately after the detection of a synchronous match CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 227 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 11 Operating Description of PWM Timer Function Variable cycle Mode MB95130 MB Series Figure 15 11 2 Operating Diagram of PWM Timer Function Variable cycle Mode TOODR register value 804 and TO1DR register value 804 duty ratio 0 timer 00 value gt timer 01 value Counter timer 00 value 00 00 Counter timer 01 value a gt 80 00 980 00 PWM waveform i TOODR register value 404 and TO1DR register value 80 duty ratio 50 Counter timer 00 value 00 5940 gt 004 3 404 7 00 Counter timer 01 value 00 4 9 000 3980 00 7 04 0044 H004 1 PWM waveform et X L TOODR register value 004 and TO1DR register value duty ratio 99 6 Counter timer 00 value 00 Counter timer 01 value JSS SSeS eS 00 904 FF 00 p i PWM waveform S E One count width le 228 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER
500. r loWeI Ch ceo eue piae ete teret dedo 271 PDCRHO 16 bit PPG down counter register upper teo T ERE DE 270 PDCRLO 16 bit PPG down counter register lower CIT E TE REE T treater 270 PDRO Port O data register 108 PDR1 Port 1 data 108 PDRF F data 108 PDRG Port G 108 PDSOO 8 16 bit PPG timer 00 duty setting buffer register Ch ertet detis ire terius 249 PDSO1 8 16 bit PPG timer 01 duty setting buffer register 0 249 PDS10 8 16 bit PPG timer 00 duty setting buffer register 1 249 PDS11 8 16 bit PPG timer 01 duty setting buffer register 1 249 PDUTHO 16 bit PPG duty setting buffer register upper ch 0 eee ttu 272 PDUTLO 16 bit PPG duty setting buffer register lower 272 PPGS 8 16 bit PPG start 250 PPSOO 8 16 bit PPG timer 00 cycle setup buffer register ch Onara eee heres 248 PPS01 8 16 bit PPG timer 01 cycle setup buffer register 248 PPS10 8 16 bit PPG timer 00 cycle setup buffer register Gh aarian 248 PPS11 8 16 bit PPG timer 01 cycle setup buffer register 248 PULO O pull up control
501. r Block Diagram 47 Overview of Clock Controller 46 clock mode Check That Clock mode Transition has been Completed before Setting Standby Mode 71 CIOCK mode itio tle teste teri teats 49 Clock Mode State Transition Diagram 66 Combinations of Clock Mode and Standby Mode 51 Oscillation Stabilization Wait Time and Clock Mode Standby Mode Transition 53 Peripheral Resources Not Affected by Clock Mode49 Clock Speed Reload Value and Baud Rate of Each Clock Speed Clock supervisor Block Diagram of Clock Supervisor 455 Example Operation Flowchart for the Clock 525 Supervisor 461 Example Startup Flowchart when using the Clock Supervisor ae 462 Notes on using the Clock Supervisor 463 Operations of Clock Supervisor 460 Overview of Clock Supervisor 454 Register of Clock Supervisor 457 Clock supervisor control register Clock supervisor control register CSV CR mide 458 Command Command Sequence Table 471 Notes on Issuing Commands 471 Compound Timer 8 16 bit Compound Timer 00 01 Control Status Register 0 205 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCR
502. r ch 0 Hysteresis Automotive CMOS clock input P13 P13 1 VO TRGO 16 bit PPG ch 0 trigger input Hvst Hit tive CMOS eneral purpose steresis Automotive TRGO ADTG 5 ADTG A D trigger activation input 4 P14 PPGO P14 general purpose I O PPGO 16 bit PPG ch 0 output Hysteresis Automotive CMOS 15 P15 general purpose I O Not shared Hysteresis Automotive CMOS 16 P16 general purpose I O Not shared Hysteresis Automotive CMOS OD Open drain PU Pull up For5V products the hysteresis input can be switched to the automotive input It becomes hysteresis input or CMOS input besides CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 115 CHAPTER 9 I O PORT vM MB95130 MB Series E Block Diagram of Port 1 Figure 9 3 1 Block Diagram of Port 1 Hysteresis 0 E 1 Peripheral function input 4 Peripheral function input enable 1 C 1 Peripheral function output enable r gt 1 Peripheral function output E nc PTT dud d Automotive c 0 14 Pull up IL 1 WN 1 i gt PDR read Ris 1 CL 1 MOS PDR gt T P 0 Only P10 P12 PDR write and P13 are iniit
503. r register PPSOO 8 16 bit PPG timer 00 cycle setup buffer register PDSO1 8 16 bit PPG timer 01 duty setup buffer register PDS00 8 16 bit PPG timer 00 duty setup buffer register mA PPGS 8 IE PPG start 280 REVC 8 16 bit PPG output inversion register This series has only ch 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 241 CHAPTER 16 8 16 BIT PPG 16 4 Pins of 8 16 bit PPG MB95130 MB Series 16 4 Pins of 8 16 bit PPG This section describes the pins of the 8 16 bit PPG E Pins of 8 16 bit PPG PPGO0 pin and PPGO1 These pins function both as general purpose I O ports and 8 16 bit PPG outputs 00 PPGO1 A PPG waveform is outputted to these pins The PPG waveform can be outputted by enabling the output by the 8 16 bit PPG timer 01 00 control registers PC00 POENO 1 PC01 POENI 1 E Block Diagram of Pins Related to 8 16 bit PPG Figure 16 4 1 Block Diagram of Pins PPGO00 PPG01 Related to 8 16 bit PPG Hysteresis l Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Le L 0 Only P04 is selectable al C H Automotive Pull up Yi MN PDR PDR write In bit operation instruction Stop Wa
504. r supply pin GND P00 INTOO AN00 PPG00 POL INTO1 ANO1 PPGO1 PO2 INTO2 ANO2 SCK P03 INTO3 ANO03 SOT General purpose I O port Shared with external interrupt input INTOO A D converter analog input ANOO and 8 16 bit PPG ch 0 output PPGOO General purpose I O port Shared with external interrupt input INTO1 A D converter analog input ANO1 and 8 16 bit PPG ch 0 output PPGOI General purpose I O port Shared with external interrupt input INTO2 A D converter analog input ANO2 and LIN UART clock I O SCK General purpose I O port Shared with external interrupt input INTO3 A D converter analog input ANO3 and LIN UART data output SOT PO4 INT04 ANO04 SIN 14 General purpose I O port Shared with external interrupt input INTO4 A D converter analog input ANO4 and LIN UART data input SIN FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 1 DESCRIPTION MB95130 MB Series 1 7 Pin Description Table 1 7 1 Pin Description 2 2 Vo Pin name circuit Function type POS INTO5 ANOS TOO00 General purpose I O port Shared with external interrupt input INT05 amp INT06 A D converter analog input PO6 INTO6 ANO5 amp ANO6 and 8 16 bit compound timer ch 0 output TO00 amp TO01 ANO0G TOOI General purpose I O port Shared with external interrupt input INTO7 and A D converter analog input ANO7 PO7 INT
505. ral purpose port 1 Output enabled o o Counter borrow detection flag bit for PPG cycle down counter Read Write Counter borrow undetected Flag cleared Counter borrow detected No effect on operation PIEO Interrupt request enable bit 0 Interrupt disabled 1 Interrupt enabled Operation mode select bits 8 bit PPG independent mode 8 bit prescaler 8 bit PPG mode 16 bit PPG mode MCLK Machine clock frequency FcH Main clock oscillation frequency R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction Initial value 246 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG 16 5 Registers of 8 16 bit PPG MB95130 MB Series Table 16 5 2 8 16 bit PPGO Control Register PCO Bit name Function 1 Operation mode select bits These bits select the PPG operation mode Do not modify the bit settings during counting When set to 005 8 bit PPG independent mode When set to Olg 8 bit prescaler 8 bit PPG mode When set to 1xg 16 bit PPG mode PIEO Interrupt request enable bit This bit controls interrupts of PPG timer 00 Set this bit in 16 bit PPG operation mode Setting the bit to 0 disables interrupts of PPG
506. ram PLL controller register PLLC Standby control register STBC oscillator circuit Sub clock control Supply to CPU control circuit Main clock E CH oscillator circuit Main clock control Supply to peripheral resources oscillator circuit Source clock selection _ control circuit From time base timer 2 FcH to 2 F cH From watch prescaler 2 5 to 2 F cL Oscillation stabilization wait circuit 0 D o lt c i SCMO SCS0 System clock control register SYCC Oscillation stabilization wait time setting register WATR 1 Main clock FcH 5 Main PLL clock 2 Sub clock 6 Sub PLL clock 3 Main clock 7 Source clock 4 Sub clock 8 Machine clock MCLK Stop signal Sleep signal Clock for watch prescaler Watch or time base timer 2 Fa Sub clock Clock for time base timer CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 47 CHAPTER 6 CLOCK CONTROLLER 6 1 Overview of Clock Controller MB95130 MB Series The clock controller consists of the following blocks Main clock oscillator circuit This block is the oscillator circuit for the main clock Sub clock oscillator circuit Dual clock product This block is the oscillator circuit for the sub clock Main PLL oscillator circuit This block is the oscillator circuit for the main PLL Sub PLL oscillator
507. ransmit data empty flag bit SSR TDRE is 1 no transmit data transmit data write enabled a transmit interrupt request is generated immediately when transmit interrupt request is enabled SSR TIE 1 To prevent this be sure to set the transmit data before setting the TIE flag to 1 Changing operation setting Reset the LIN UART after changing its settings such as adding the start stop bit or changing the data format The correct operation settings are not guaranteed even if you reset the LIN UART SMR UPCL 1 concurrently with setting the LIN UART serial mode register SMR Therefore after setting the bit in LIN UART serial mode register SMR reset the LIN UART SMR UPCL 1 again Using LIN function Although the LIN functions are available in the mode 3 the LIN format is automatically set in the mode 3 8 bit data no parity 1 stop bit LSB first While the length of LIN break transmit bit is variable the detection bit length is fixed to 11 bits Q Setting LIN slave When starting LIN slave mode be sure to set the baud rate before receiving the LIN synch break in order to make sure that the minimum 13 bits length of the LIN synch break is detected Bus idle function The bus idle is not available in synchronous mode 2 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 417 CHAPTER 22 LIN UART 22 8 Notes on Using LIN UART MB95130 MB Series 418 AD bit LIN UART serial control register SCR Address
508. rasing has been completed No effect gt Undefined bit The value read is always 0 Writing has no effect on the operation gt Undefined bit The value read is always 0 Writing has no effect on the operation R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction R WX Read only Readable writing has no effect on operation R WO Reserved bit Write value is 0 read value is the same as write value RO WX Undefined bit Read value is 0 writing has no effect on operation X Indeterminate Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 469 CHAPTER 26 256 Kbit FLASH MEMORY 26 3 Register of Flash Memory MB95130 MB Series Table 26 3 1 Functions of Flash Memory Status Register FSR Bit name Function Undefined bits The value read is always 0 Writing has no effect on the operation RDYIRQ Flash memory operation flag bit This bit shows the operating state of flash memory The RDYIRQ bit is set to 1 upon completion of the flash memory automatic algorithm when flash memory programming erasing is completed An interrupt request occurs when the RDYIRQ bit is set to 1 if interrupts triggered by the completion of flash memory programming erasing have been enabled FSR IRQEN 1 If the RDYIRQ bit is set to 0 when flash
509. ration in Asynchronous Clock Mode RXE uo st bo pi pa os 4 Ds oef 07 RDRO read RDRF CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 331 CHAPTER 20 UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure MB95130 MB Series Example Reception error in asynchronous clock mode UART If any of the following three error flags PER FER OVE has been set receive data is not transferred to the UART SIO serial input data register RDRO and the receive data register full RDRF bit is not set to 1 either e Parity error PER The parity error PER bit is set to 1 if the parity bit in received serial data does not match the parity polarity bit TDP when the parity control bit PEN contains 1 Framing error FER The framing error FER bit is set to 1 if 1 is not detected at the position of the first stop bit in serial data received in the set character bit length CBL under parity control PEN Note that the stop bit is not checked if it appears at the second bit or later e Overrun error OVE Upon completion of reception of serial data the overrun error OVE bit is set to 1 if the reception of the next data is performed before the previous receive data is read Each flag is set at the position of the first stop bit Figure 20 7 4 Setting Timing for Receiving Errors ulo PER OVE FER Reception interrupt 05 X D6 X D7 X P X SP X SP X
510. register EIC that pin functions as an external interrupt input pin INTOO INTO The state of pins can be read from the port data register PDR whenever input port is set as a pin function However the value of PDR is read when read modify write RMW instruction is used ii Block Diagram of Pins Related to External Interrupt Circuit Figure 18 4 1 Block Diagram of Pins INTOO to INTO Related to External Interrupt Circuit Peripheral function input Peripheral function input enable EENE el Hysteresis RnR col 0 9 1 m gt Bi PDR read 1 Automotive PDR Pin PDR write In bit operation instruction o d 8 g N DDR read DDR LT DDR write Stop Watch SPL 1 ILSR2 read gt ILSR2 ILSR2 write LN CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 291 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 5 Registers of External Interrupt Circuit MB95130 MB Series 18 5 Registers of External Interrupt Circuit This section describes the registers of the external interrupt circuit Bi List of Registers of External Interrupt Circuit Figure 18 5 1 shows the registers of the external interrupt circuit Figure 18 5 1 Registers of External Interrupt Circuit
511. register then set the transmission operation enable bit TXE to 1 to start transmission Transmit data is written to the UART SIO serial output data register TDRO after it is checked that the transmit data register empty TDRE bit is set to 1 When the transmit data is written to the UART SIO serial output data register TDRO the transmit data register empty TDRE bit is cleared to 0 When serial transmission is started after transmit data is transferred from the UART SIO serial output data register TDRO to the transmission shift register and the transmit data register empty TDRE is set to 1 When the use of the external clock signal has been set serial data transmission starts at the fall of the first serial clock signal after the transmission process is started A transmission completion interrupt occurs the moment the transmit data register empty TDRE bit is set to 1 when the transmission interrupt enable bit TIE contains 1 At this time the next piece of transmit data can be written to the UART SIO serial output data register TDRO Serial transmission can be continued with the transmission operation enable bit TXE set to 1 To use a transmission completion interrupt to detect the completion of serial transmission enable transmission completion interrupt output this way TEIE 0 TCIE 1 Upon completion of transmission the transmission completion flag TCPL is set to 1 and a transmission completion i
512. rent baud rates Figure 22 6 1 shows the LIN UART baud rate selection circuit Baud rate derived from the internal clock divided by the dedicated baud rate generator reload counter Two internal reload counters are provided and assigned the transmit and reception serial clock respectively The baud rate is selected by setting a 15 bit reload value in the LIN UART baud rate generator register 1 0 BGR1 BGRO The reload counter divides the internal clock by the specified value It is used in asynchronous mode and in synchronous mode sending side of serial clock To set the clock source select the use of the internal clock and baud rate generator SMR EXT 0 0 Baud rate derived from the external clock divided by the dedicated baud rate generator reload counter The external clock is used as the clock source for the reload counter The baud rate is selected by setting a 15 bit reload value in the LIN UART baud rate generator register 1 0 BGR1 BGRO The reload counter divides the external clock by the specified value It is used in asynchronous mode To set the clock source select the use of the external clock and baud rate generator SMR EXT 1 OTO 0 Baud rate by the external clock one to one mode The clock input from the clock input pin SCK of the LIN UART is used as the baud rate slave 2 operation ECCR MS 1 in synchronous mode It is used in synchronous mode receiving side of serial clock
513. retrigger function Set the bit to 1 When disabling retrigger function Set the bit to 0 Q How to start stop operation on a rising edge of trigger input The hardware trigger enable bit PCNTLO0 EGSO is used When starting operation on rising edge Set the bit to 1 When stopping operation on rising edge Set the bit to 0 Q How to start stop operation on a falling edge of trigger input The hardware trigger enable bit PCNTLO EGS1 is used When starting operation on falling edge Set the bit to 1 When stopping operation on falling edge Set the bit to 0 How to invert PPG output The output inversion bit PCNTLO OSEL is used When inverting PPG output Set the bit to 1 284 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 9 Sample Programs for 16 bit PPG Timer How to set the PPG output to the H or L level The PPG output mask enable bit PCNTHO PGMS and the output inversion bit PCNTLO OSEL are used PPG output mask enable bit Operation PGMS Output inversion bit OSEL When setting output to H level Set the bit to 1 Set the bit to 1 When setting output to L level Set the bit to 1 Set the bit to 0 How to select the interrupt source The interrupt select bits PCNTLO IRS 1 IRSO are used to select the interrupt source Interrupt source Interrupt select bits IRS1 IRSO Trigger by TRGO input softw
514. rite access to this bit sets it to 0 e The bit is read only Any value written is meaningless zs e Read or write access 0 or 1 to this bit sets it to O Corrected description of bitO e Read write access to this bit or a power on reset sets it to 0 e The bit is read only Any value written is meaningless gt e Read or write access 0 or 1 to this bit or a power on reset sets it to 0 CHAPTER 8 INTERRUPTS 8 1 Interrupts B Interrupt Requests from Peripheral Resources Table 8 1 1 Corrected the upper cell of Vector table address of Mode data FFFCu gt CHAPTER 9 I O PORT 9 2 2 Operations of Port 0 Changed 6 Operation of the pull up control register 9 3 2 Operations of Port 1 Changed 6 Operation of the pull up control register 9 5 2 Operations of Port G Changed 6 Operation of the pull up control register CHAPTER 15 8 16 BIT COMPOUND TIMER 15 4 Pins of 8 16 bit Compound Timer Added Figure 15 4 2 xi 15 13 Operating Description of Input Capture Function Page Changes For details refer to main body Added the explanation 15 16 Notes on Using 8 16 bit Com pound Timer Added the explanation CHAPTER 16 8 16 BIT PPG 16 2 Configuration of 8 16 bit PPG Changed Figure 16 2 1 MCLK to PCK6 gt n MCLK 27 28 16 4 Pins of 8 16 bit PPG Changed Figure 16 4 1 Deleted Figure 16 4 2 16 7 Operating Descr
515. rite data into the LIN UART transmit data register TDR To receive data disable the serial output SMR SOE 0 and then write dummy data into the TDR Enabling continuous clock and start stop bit allows bi directional communication as in asynchronous mode 404 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART 22 7 3 Operation of LIN function Operation Mode 3 In operation mode 3 the LIN UART works as the LIN master and the LIN slave In operation mode 3 the communication format is set to 8 bit data no parity stop bit1 LSB first Asynchronous LIN Mode Operation Operation as LIN master In LIN mode the master determines the baud rate for the entire bus and the slave synchronizes to the master Writing 1 to the LBR bit in the LIN UART extended communication control register ECCR outputs 13 to 16 bits at the L level from the SOT pin This bit is the LIN synch break signifying the beginning of a LIN message The TDRE flag bit in the LIN UART serial status register SSR is set to 0 After the break it is set to 1 initial value If the TIE bit in SSR is 1 at this time a transmit interrupt is output The length of the LIN Synch break transmitted is set by the LBLO LBL1 bits in ESCR as in the following table Table 22 7 3 LIN Break Length Break length 13 bits 14 bits 15 bits 16 bits
516. rite value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction RO W Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined Initial value 136 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 10 TIME BASE TIMER MB95130 MB Series 10 3 Registers of the Time base Timer Table 10 3 1 Functional Description of Each Bit of Time base Timer Control Register TBTC Bit name Function Set to 1 when interval time selected by the time base timer elapses TBIF Interrupt request is outputted when this bit and the time base timer interrupt request Time base timer enable bit TBIE are set to 1 interrupt request flag Writing 0 clears the bit bit Writing 1 has no effect on operation 1 is always read in read modify write RMW instruction TBIE This bit enables disables output of interrupt requests to the interrupt controller Time base timer Writing 0 disables output of time base timer interrupt requests interrupt request enable Writing 1 enables output of time base timer interrupt requests bit Interrupt request is outputted when this bit and the time base timer interrupt request flag bit are set to 1 These bits are undefined Undefined bits The read value is always 0 Writing has no effect on the operation These bits s
517. rmal Stop of Clock Oscillation Option External reset An external reset is generated upon L level input to the external reset pin RST An externally input reset signal is accepted asynchronously via the internal noise filter and generates an internal reset signal in synchronization with the machine clock to initialize the internal circuit Consequently a clock is necessary for internal circuit initialization Clock input is therefore necessary for operation with an external clock Note however that external pins including I O ports and peripheral resources are reset asynchronously Additionally there are standard pulse width values for external reset input If the value is below the standard the reset may not be accepted The standard value is listed on the data sheet Please design your external reset circuit so that this standard is met Software reset Writing 1 to the software reset bit of the standby control register STBC SRST generates a software reset Watchdog reset After the watchdog timer starts a watchdog reset is generated if the watchdog timer is not cleared within a preset amount of time 86 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 7 RESET MB95130 MB Series 7 1 Reset Operation Power on reset low voltage detection reset Option A power on reset is generated when the power is turned on Some 5 V products have a low voltage detection reset circuit option integrated The low vo
518. rmation FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non infringement of any third party s intellectual property right or other right by using such information FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for u
519. roducts and notes when selecting the product E Difference Points among Products and Notes on Selecting a Product Notes on using evaluation products The evaluation products are intended to support software development for a number of different F MC 8FX family series and products and it therefore includes additional functions that may not be included in MB95130 MB series Accordingly access to I O address of peripheral functions that are not used in MB95130 MB series is prohibited Reading or writing to these prohibited addresses may cause these unused peripheral functions to operate and lead to unexpected hardware or software problems Take particular care not to use word access to read or write odd numbered bytes in the prohibited areas It causes unexpected read write operation Also as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory and mask ROM products do not use these values in the program The functions corresponding to certain bits in single byte registers may not be supported on some mask ROM and flash memory products However reading or writing to these bits will not cause malfunction of the hardware Also as the evaluation flash memory and mask ROM products are designed to have identical software operation no particular precautions are required Difference of memory space If the memory size on the evaluation product is different to the flash memo
520. rograms of LIN UART Corrected the LIN UART setting for To set the SCK pin as input Setting Methods not Covered by DDR6 P05 0 gt Sample Programs DDRO P02 0 How to control the SCK SIN and SOT pins Corrected the LIN UART setting for To use the SIN pin P DDR6 P07 0 gt DDRO0 P04 0 432 CHAPTER 23 8 10 BIT A D Corrected block diagram CONVERTER 23 3 Pins of 8 10 bit A D Converter Bl Block Diagram of Pins Related to 8 10 bit A D Converter Figure 23 3 1 442 23 6 Operations of 8 10 bit A D Corrected explanation Converter and Its Setup 1 Set the port for input DDR1 Procedure Examples gt Setup Procedure Example 1 Set the port for input DDRO Initial setting 466 CHAPTER 26 256 KBIT FLASH Changed summary MEMORY 26 1 Overview of 256 Kbit Flash Memory ll Overview of 256 Kbit Flash Memory Changed descriptions 470 26 3 1 Flash Memory Status Register Deleted the following description of bit1 FSR e To program data into the flash memory set FSR WRE to 1 to B Flash Memory Status Register FSR write enable the flash memory and set the flash memory sector write Table 26 3 1 control register SWRE0 SWRE1 When FSR WRE disables pro gramming contains 0 write access to flash memory does not take place even though it is enabled by the flash memory write control reg ister SWREO SWREI 471 26 4 Starting the Flash Memory Changed explanation of U Automatic Algorithm E Command Sequence Table Table 26 4 1 U
521. rol circuit Output control circuit The division ratio divided by 2 4 8 16 32 is determined by the counter value of the 5 bit counter Clocks generated by dividing the machine clock by this value will be supplied to individual peripheral resources The circuit also buffers the clock from the time base timer 2 Fcp and supplies it to the peripheral resources B Input Clock The prescaler uses the machine clock or the clock output from the time base timer as the input clock Bi Output Clock The prescaler supplies clocks to the 8 10 bit compound timer 8 16 bit PPG timer 16 bit PPG timer UART SIO dedicated baud rate generator and 8 10 bit A D converter 82 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 12 Operating Explanation of Prescaler 6 12 Operating Explanation of Prescaler The prescaler generates count clock sources to individual peripheral resources il Operations of Prescaler The prescaler generates count clock sources from the frequency divided version of the machine clock MCLK and buffered signals from the time base timer 27 Foy 28 Fcp and supplies them to individual peripheral resources The prescaler remains operating as long as the machine clock and time base timer clocks are supplied Table 6 12 1 lists the count clock sources generated by the prescaler Table 6 12 1 Count Clock Sources Generated by Prescaler Count Clock Cycle F
522. rol register STBC STP Stop bit of standby control register WATR MWTS to MWTO Main clock oscillation stabilization wait time select bit of oscillation stabilization wait time setup register E Setup Procedure Example Initial setting The time base timer is set up in the following procedure 1 Disable interrupts 2 Set the interval time 3 Enable interrupts 4 Clear the counter Interrupt processing TBTC TBIE 0 TBTC TBCI TBCO TBTC TBIE 1 TBTC TCLR 1 1 Clear the interrupt request flag TBTC TBIF 0 2 Clear the counter 142 FUJITSU MICROELECTRONICS LIMITED TBTC TCLR 1 CM26 10118 3E CHAPTER 10 TIME BASE TIMER MB95130 MB Series 10 6 Notes on Using Time base Timer 10 6 Notes on Using Time base Timer Care must be taken for the following points when using the Time base Timer E Notes on Using Time base Timer When setting the timer by program The timer cannot be recovered from interrupt processing when the time base timer interrupt request flag bit TBTC TBIF is set to 1 and the interrupt request enable bit is enabled TBTC TBIE 1 Always clear TBIF bit in the interrupt processing routine Clearing time base timer The time base timer is cleared not only by the time base timer initialization bit TBTC TCLR 1 but also when the oscillation stabilization wait time is required for the main clock When the time base timer is selected for the count clock o
523. rol register PLLC SPEN is set to Watch counter keeps counting and no interrupts occur When the sub clock oscillation stop bit in the 51 CHAPTER 6 CLOCK CONTROLLER 6 2 Oscillation Stabilization Wait Time MB951 30 MB Series 6 2 Oscillation Stabilization Wait Time The oscillation stabilization wait time is the time after the oscillator circuit stops oscillation until the oscillator resumes its stable oscillation at its natural frequency The clock controller obtains the oscillation stabilization wait time by counting a set number of oscillation clock cycles to prevent clock supply to internal circuits Oscillation Stabilization Wait Time The clock controller obtains the oscillation stabilization wait time followed by the initiation of oscillation by counting a set number of oscillation clock cycles to prevent clock supply to internal circuits When a state transition request for starting oscillation when the power is turned on or for restarting halted oscillation at a clock mode change by a reset an interrupt in standby mode or by software the clock controller automatically waits until the oscillation stabilization wait time for the main clock or sub clock has passed and then causes transition to the next state Figure 6 2 1 shows oscillation immediately after being started Figure 6 2 1 Behavior of Oscillator Immediately after Starting Oscillation Normal operation Operation after returning Oscillation time of Oscilla
524. rrupt requests Set the bit to 1 The interrupt request flag WCSR WCFLG is used to clear interrupt requests Control item Interrupt request flag WCFLG To clear an interrupt request Set the bit to 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 181 CHAPTER 13 WATCH COUNTER 13 7 Sample Programs for Watch Counter MB951 30 MB Series 182 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 14 WILD REGISTER This chapter describes the functions and operations of the wild register 14 1 Overview of Wild Register 14 2 Configuration of Wild Register 14 3 Registers of Wild Register 14 4 Operating Description of Wild Register 14 5 Typical Hardware Connection Example Code CM26 00109 1E CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 183 CHAPTER 14 WILD REGISTER 14 1 Overview of Wild Register MB95130 MB Series 14 1 Overview of Wild Register The wild register can be used to patch bugs in the program by using the addresses set in the built in register and amendment data The following section describes the wild register function Wild Register Function The wild register consists of 3 data setup registers 3 upper address setup registers 3 lower address setup registers a 1 byte address compare enable register and a 1 byte data test setup register When certain addresses and modified data are specified in these registers the ROM data can be replaced with the modified data specified in the regist
525. rt Initial setting Set to operation mode 3 Enable serial data output Set baud rate Set Synch break length 1 TIE 0 RXE 1 RIE 1 r Message Reception Transmission YES Data Field No Reception Wake up 80 reception Reception interrupt Receive Data 1 Set transmit data 1 TDR Data 1 1 Enable transmit RXE O0 Reception interrupt interrupts Enable Synch break interrupts TDRE 1 Synch Break transmission Receive Data N Transmit interrupt ECCR LBR 1 Transmit Synch field Set transmit data N TDR 554 TDR Data N Disable transmit LBD 1 interrupts Synch break interrupts 1 Reception interrupt Enable reception LBD 0 _ Disable Synch break Receive Data 1 interrupts Read data 1 RDRF 1 Ly 17 E interrupt Receive Synch field Set Identify field TDR ID Receive Data N Read data N RDRF 1 Reception interrupt Receive ID field No 2 Handle an error 1 Handle an error if it occurs 2 If the FRE or ORE flag is set to 1 write 1 to the SCR CRE bit to clear the error flag If the ESCR LBD bit is set to 1 execute the LIN UART reset Note Detect an error in each process and handle it appropriately CM
526. ructions that can access the program status are MOVW A PS or MOVW PS A The register bank pointer RP and direct bank pointer DP in the program status register can also be read from or written to by accessing the mirror address 0078p Note that the condition code register CCR is part of the program status register and cannot be accessed independently Refer to the FMC 8FX Programming Manual for details on using the dedicated registers CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 35 CHAPTER 5 CPU 5 1 Dedicated Registers Register Bank Pointer RP 5 1 1 MB95130 MB Series The register bank pointer RP in bits 15 to 11 of the program status PS register contains the address of the general purpose register bank that is currently in use and is translated into a real address when general purpose register addressing isu sed E Configuration of Register Bank Pointer RP Figure 5 1 2 shows the configuration of the register bank pointer Figure 5 1 2 Configuration of Register Bank Pointer PS RP DP CCR RP Initial bit15 biti4 bit13 bit12 bitii bit1O bit9 bit8 bit7 bit bits bit4 bits bit2 biti bitO val DP2 DP1 DPO lo N z v C 00000 R4 R3 R2 R1 The register bank pointer contains the address of the register bank currently being used The content of the register bank pointer is trans
527. rupt the CPU requires 9 machine clock cycles to perform the following interrupt processing setup Saves the program counter PC and program status PS values Sets the PC to the start address interrupt vector of interrupt service routine Updates the interrupt level bits PS CCR IL1 ILO in the program status PS register Figure 8 1 4 Interrupt Processing Time Normal instruction execution Interrupt handling Interrupt processing routine i CPU operation Interrupt request Interrupt handling time Interrupt wait time sampling wait time 9 machine clock cycles Interrupt request generated lt gt Last instruction cycle in which the interrupt request is sampled When an interrupt request is generated immediately after the beginning of execution of the DIVU instruction requiring the longest execution cycle 17 machine clock cycles it takes an interrupt processing time of 1749 26 machine clock cycles The machine clock changes depending on the clock mode and main clock speed switching gear function For details see CHAPTER 6 CLOCK CONTROLLER CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 103 CHAPTER 8 INTERRUPTS 8 1 Interrupts MB95130 MB Series 8 1 5 Stack Operations During Interrupt Processing This section describes how registers are saved and restored during interrupt processing Stack Operation at the Start of Interrupt Processing Once the CPU accepts an interru
528. ry or mask ROM product please ensure you understand these differences when developing software Q Current consumption The current consumption of flash memory products is greater than for mask ROM products For the details of current consumption refer to BELECTRICAL CHARACTERISTICS in data sheet Package For detailed information on each package see M Package and Its Corresponding Product and 1 6 Package Dimension Operating voltage The operating voltage may be different depending on the products For the details see BELECTRICAL CHARACTERISTICS in data sheet Difference of MOD pin For mask ROM products a pull down resistor is provided for the MOD pin CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 7 CHAPTER 1 DESCRIPTION 1 3 Difference Points among Products and Notes on Selecting a Product MB951 30 MB Series E Package and Its Corresponding Product MB95F133MBS MB95F133NBS MB95F133JBS MB95F133MBW MB95F133NBW MB95F133JBW Product MB95F134MBS MB95F134NBS MB95F134JBS MB95FV100D 101 MB95F134MBW MB95FV100D 103 MB95F134NBW MB95F134JBS MB95136MB Package MB95F136MBS MB95F136NBS MB95F136JBS MB95F136MBW MB95F136NBW MB95F136JBW FPT 28P M17 FPT 30P M02 BGA 224P M08 O usable x unusable 8 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 1 DESCRIPTION MB95130 MB Series 1 4 Block Diagram of MB95130 MB Series 1 4 Block Diagram of MB95130 MB Series Figure 1
529. s Source request No Register Setting bit Upper Lower ch 0 lower IRQ12 ch 0 upper IRQ13 ch channel Refer to APPENDIX B Table of Interrupt Causes for the interrupt request numbers and vector tables of all peripheral functions 252 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 7 Operating Description of 8 16 bit PPG 16 7 Operating Description of 8 16 bit PPG This section describes the operations of the 8 16 bit PPG E Setup Procedure Example The setup procedure of the 8 16 bit PPG is described below Initial setting 1 2 3 4 5 6 7 8 2 Set the port output DDRO Set the interrupt revel ILR2 ILR3 Select the operating clock enable the output and interrupt PCO1 Select the operating clock enable the output and interrupt select the operation mode PCO00 Set the cycle PPS Set the duty PDS Set the output inversion REVC Start PPG PPGS Interrupt processing 1 2 3 CM26 10118 3E Process any interrupt Clear the interrupt request flag PCO1 PUF1 PC00 PUFO Start PPG PPGS FUJITSU MICROELECTRONICS LIMITED 253 CHAPTER 16 8 16 BIT PPG 16 7 Operating Description of 8 16 bit PPG MB951 30 MB Series 16 7 1 8 bit PPG Independent Mode In this mode the unit operates as two channels PPG timer 00 and PPG timer 01 of the 8 bit PPG E Setting 8 bit Independent Mode The unit requ
530. s 11 5 Notes on Using Watchdog Timer Care must be taken for the following points when using the watchdog timer Notes on Using Watchdog Timer Stopping the watchdog timer Once activated the watchdog timer cannot be stopped until a reset is generated Q Selecting the count clock The count clock switch bits WDTC CS1 0 can be rewritten only when the watchdog control bits WDTC WTE3 to WTEO are set to 0101 upon the activation of the watchdog timer The count clock switch bits cannot be written by a bit operation instruction Moreover the bit settings should not be changed once the timer is activated In the sub clock mode the time base timer does not operate because the main clock stops oscillating In order to operate the watchdog timer in the sub clock mode it is necessary to select the watch prescaler as the count clock beforehand and set WDTC CSI 0 to 10g or 11g Clearing the watchdog timer Clearing the counter used for the count clock of the watchdog timer time base timer or watch prescaler also clears the counter of the watchdog timer The counter of the watchdog timer is cleared when entering the sleep mode stop mode or watch mode Programming precaution When creating a program in which the watchdog timer is cleared repeatedly in the main loop set the processing time of the main loop including the interrupt processing time to the minimum watchdog timer interval time or shorter 154 FUJ
531. s set the multiplier and to indicate the stability of PLL oscillation Oscillation stabilization wait time setting register WATR This register is used to set the oscillation stabilization wait time for the main clock and sub clock 48 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 1 Overview of Clock Controller Clock Mode There are four clock modes available main clock mode main PLL clock mode sub clock mode and sub PLL clock mode Table 6 1 1 shows the relationships between the clock modes and the machine clock operating clock for the CPU and peripheral resources Table 6 1 1 Clock Modes and Machine Clock Selection Clock Mode Machine Clock Main clock mode The machine clock is generated from the main clock main clock divided by 2 The machine clock is generated from the main PLL clock main clock multiplied by the Main PLL clock mode PLL multiplier Sub clock mode Dual clock product only The machine clock is generated from the sub clock sub clock divided by 2 Sub PLL clock mode The machine clock is generated from the sub PLL clock sub clock multiplied by the Dual clock product only PLL multiplier In any of the clock modes the selected clock can also be frequency divided Additionally in modes using a PLL clock a multiplier for the clock frequency can also be set E Peripheral Resources Not Affected by Clock Mode Note that the
532. s as shown in Figure 6 9 1 Figure 6 9 1 Sample Connections of Crystal and Ceramic Oscillators Dual clock product Single clock product Main clock Sub clock Main clock oscillator circuit oscillator circuit oscillator circuit X1 X0A Using external clock As shown inFigure 6 9 2 connect the external clock to the pin while leaving the pin open To supply the sub clock from an external source connect the external clock to the X0A pin while leaving the X1A pin open Figure 6 9 2 Sample Connections of External Clocks Dual clock product Single clock product Main clock oscillator circuit Main clock Sub clock oscillator circuit oscillator circuit X1A X0 X1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 79 CHAPTER 6 CLOCK CONTROLLER 6 9 Clock Oscillator Circuits MB95130 MB Series Note If you use only the main clock without using sub clock oscillation on a dual clock product and it enters sub clock mode for some reason there is no solution for recovering its operation as there is no clock supply available If you use the main clock alone therefore be sure to select a single clock product 80 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 10 Overview of Prescaler 6 10 Overview of Prescaler The prescaler generates the count clock source for various peripheral resources from the machine clock MCLK and the c
533. s either with the main PLL clock oscillation enable bit MPEN set to 1 or with the clock mode selection bits in the system clock control register SYCC SCS1 SCSO set to 11g It is however possible to set these bits at the same time as setting SPEN to 1 Indicates whether main PLL clock oscillation has become stable When set to 1 the MPRDY bit indicates that the oscillation stabilization wait time for the MPRDY main PLL clock has passed bit4 Main PLL clock When set to 0 the MPRDY bit indicates that the clock controller is in the main PLL clock oscillation stability bit oscillation stabilization wait state or that main PLL clock oscillation has been stopped This bit is read only Any value attempted to be written is meaningless and has no effect on operation Enables or disables the oscillation of the sub PLL clock in main clock mode main PLL clock mode sub clock mode or in watch mode SPEN When set to 0 the bit disables sub PLL clock oscillation Sub PLL clock When set to 1 the bit enables sub PLL clock oscillation bit3 oscillation enable bit In sub PLL clock mode the sub PLL clock oscillates regardless of the value of this bit except Dual clock product in watch mode only Even in sub PLL clock mode the sub PLL clock stops oscillation in stop mode regardless of CM26 10118 3E the value of this bit On single clock product the value of the bit has no effect on the operation FUJITSU MICROELECTRONICS
534. s have halted This function switches to an CR clock generated in internal CR oscillator circuit if main clock and sub clock oscillations have halted this feature is optional to 5 V products ll Overview of Clock Supervisor The clock supervisor monitors the main clock and sub clock oscillations and generates an internal reset if it detects that the oscillation has halted In this case the clock supervisor switches to the internal CR clock the clock frequency of the sub clock is equal to the CR clock frequency divided by 2 The reset source register RSRR can be used to determine whether a reset was triggered by the clock supervisor A main clock oscillation halt is detected if the rising edge of the main clock is not detected for 4 CR clock cycles The clock supervisor may detect incorrectly if main clock is longer than 4 CR clock cycles A sub clock oscillation halt is detected if the rising edge of the sub clock is not detected for 32 CR clock cycles The clock supervisor may detect incorrectly if sub clock is longer than 32 CR clock cycles The clock supervisor can prohibit to monitor the main clock and sub clock respectively If the sub clock is halted in the main clock mode a reset does not occur immediately but does occur after switching to the sub clock mode Setting registers enable to prohibit the reset output While the clock stops in main clock and sub clock stop modes clock monitoring is disabled This fun
535. s longer to elapse When the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 10g the device enters main clock mode after waiting for the main clock oscillation stabilization wait time When the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 015 the device enters sub PLL clock mode after waiting for the Sub sub PLL clock oscillation stabilization wait time Note however that the device does PLL Clock not wait for the sub PLL clock oscillation stabilization wait time to elapse if the sub PLL clock has been oscillating according to the setting of the sub PLL clock oscillation enable bit in the PLL control register PLLC SPEN in sub clock mode When the system clock select bits in the system clock control register SYCC SCS1 Main SCSO are set to 115 the device enters main PLL clock mode after waiting for the PLL Clock main PLL clock oscillation stabilization wait time or main clock oscillation stabilization wait time to elapse whichever is longer Sub The device enters sub clock mode when the system clock select bits in the system Clock clock control register SYCC SCS1 SCSO are set to 00g When the system clock select bits in the system clock control register SYCC SCS1 Sub Main SCSO are set to 115 the device enters main PLL clock mode after waiting for the u PLL Clock main PLL clock oscillation stabilization wait tim
536. s of Wild Register 14 3 3 Wild Register Address Compare Enable Register WREN The wild register address compare enable register WREN enables disables the operation of the wild register in accordance with each wild register number Bi Wild Register Address Compare Enable Register WREN Figure 14 3 4 Wild Register Address Compare Enable Register WREN Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value 00764 Reser Reser Reser EN2 ENO 00000000g ved ved ved RO WX RO WX RO WO RO WO RO WO R W R W R W R W Readable writable Read value is the same as write value RO WO Reserved bit Write value is 0 read value is 0 RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined Table 14 3 4 Functional Description of Wild Register Address Compare Enable Register WREN Bit name Function These bits are undefined Undefined bits The read value is 0 Writing has no effect on the operation These bits are reserved Reserved bit The read value is 0 Always set 0 These bits enable disable the operation of the wild register ENO corresponds to wild register number 0 EN2 EN1 ENO Wild register address compare enable bits ENI corresponds to wild register number 1 EN2 corresponds to wild register number 2 When set to 0 disable the operation of the wild register function When set
537. s to 0 and sets the port input enabled Operation in stop mode and watch mode fthe pin state specification bit in the standby control register STBC SPL is set to 1 when the device switches to stop or watch mode the pin is set forcibly to the high impedance state regardless of the DDR register value Note that the input is locked to L level and blocked in order to prevent leaks due to freed input Ifthe pin state specification bit is 0 the state remains in port I O and the output is maintained Operation of the input level selection register 2 The ILSR2 register is a valid register only for 5V models Setting bit2 of the ILSR2 register to 1 changes the port F input level from the hysteresis input level to the automotive input level The hysteresis input level is used when bit2 of the ILSR2 register is 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 123 CHAPTER 9 I O PORT 9 4 Port F MB95130 MB Series Table 9 4 4 shows the pin states of the port Table 9 4 4 Pin State of Port F Normal operation Operating Sleep Stop SPL 1 state Stop SPL 0 Watch SPL 1 Watch SPL 0 At reset Hi Z Input enabled Not functional Hi Z Input cutoff Pin state I O port SPL Pin state specification bit in standby control register STBC SPL Hi Z High impedance Input enabled means that the input function is in the enabled state After reset setting for internal pullup or output pin
538. sar mode Counter free run mode 232 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 15 8 16 BIT COMPOUND TIMER MB95130 MB Series 15 14 Operating Description of Noise Filter 15 14 Operating Description of Noise Filter This section describes the operations of the noise filter for the 8 16 bit compound timer When the input capture or PWC timer function has been selected a noise filter can be used to eliminate the pulse noise of the signal from the external input pin ECO EC1 H pulse noise L pulse noise or H L pulse noise elimination can be selected depending on the register setting TMCRO FE11 FE10 FEO1 FEOO The maximum pulse width from which to eliminate noise is three machine clock cycles When the filter function is active the signal input is subject to a delay of four machine clock cycles Figure 15 14 1 Operation of Noise Filter Wes filter clock External input signal Output filter Wes L Lo Output filter T L noise 1 Output filter H L noise CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 233 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 15 States in Each Mode during Operation MB95130 MB Series 15 15 States in Each Mode during Operation This section describes how the 8 16 bit compound timer behaves when the microcontroller enters watch mode or stop mode or when a suspend TOOCR1 TO1CR1
539. scribes how 16 bit data is stored in memory E Placement of 16 bit Data in Memory State of 16 bit data stored in RAM When you write 16 bit data to memory the upper byte of the data is stored at a smaller address and the lower byte is stored at the next address When you read 16 bit data it is handled in the same way Figure 5 3 1 shows how 16 bit data is placed in memory Figure 5 3 1 Placing 16 bit Data in Memory Before After Memory Memory MOVW 0081H A 0080 0080 A 12344 00811 A 12344 12H 00811 0082 34u 00828 0083 0083 State of operand specified 16 bit data In the same way even when the operands in an instruction specifies 16 bit data the upper byte is stored at the address closer to the op code instruction and the lower byte is stored at the next address That is true whether the operands are either memory addresses or 16 bit immediate data Figure 5 3 2 shows how 16 bit data in an instruction is placed Figure 5 3 2 Storing 16 bit Data in Instruction Example 5678H Extended address MOVW 1234H 16 bit immediate data Assemble XXXO XX XXX2 60 56 78 Extended address XXX5 E4 12 34 16 bit immediate data 8 XX State of 16 bit data in the stack When 16 bit register data is pushed onto the stack upon an interrupt the upper byte is stored at a lower address in the same
540. scription of Each Bit of UART SIO Serial Status and Data Register SSRO Bit name Function bit7 bit6 Undefined bits These bits are undefined Reading always returns 0 Writing to the bits has no effect on operation PER Parity error flag Detect a parity error in received data The flag is set when a parity error occurs during reception Writing 0 to the RERC bit clears this flag If error detection and clearing by RERC occur at the same time the error flag is set preferentially OVE Overrun error flag Detect an overrun error in received data The flag is set when an overrun error occurs during reception Writing 0 to the RERC bit clears this flag If error detection and clearing by RERC occur at the same time the error flag is set preferentially FER Framing error flag Detect a framing error in received data The bit is set when a framing error occurs during reception Writing 0 to the RERC bit clears this flag f error detection and clearing by RERC occur at the same time the error flag is set preferentially RDRF Receive data register full flag This flag indicates the status of the UART SIO serial input data register The bit is set to 1 when receive data is loaded to the serial input data register The bit is cleared to 0 when data is read from the serial input data register TCPL Transmission completion flag This flag indicates the data transmi
541. se requiring extremely high reliability 1 submersible repeater and artificial satellite Please note that FUJITSU MICROELECTRONICS will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions e Exportation release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and or US export control laws The company names and brand names herein the trademarks or registered trademarks of their respective owners Copyright 2007 2010 FUJITSU MICROELECTRONICS LIMITED rights reserved CONTENTS CHAPTEH 1 DESCRIPTION eae recor barn ee ao sua eon enne on rna nena Yu 1 1 1 Feature of 95130 Series iieri nieee isna nnns enne nnns 2 1 2 Product Lineup of MB95130 MB Series 4 1 3 Difference Points among Products and Notes on Selecting a Product 7 1 4 Block Diagram
542. ses rapidly and might thermally damage elements Also take care to prevent the analog power supply voltage AVcc and analog input voltage from exceeding the digital power supply voltage Vcc when the analog system power supply is turned on or off Stable Supply Voltage Supply voltage should be stabilized A sudden change in power supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power supply voltage For stabilization in principle keep the variation in Vcc ripple p p value in a commercial frequency range 50 Hz 60 Hz not to exceed 10 of the standard Vcc value and suppress the voltage variation so that the transient variation rate does not exceed 0 1 V ms during a momentary change such as when the power supply is switched Precautions for Use of External Clock Even when an external clock is used oscillation stabilization wait time is required for power on reset wake up from sub clock mode or stop mode Serial Communication There is a possibility to receive wrong data due to noise or other causes on the serial communication Therefore design a printed circuit board so as to avoid noise Consider receiving of wrong data for example apply a checksum of data at the end to detect an error If an error is detected retransmit the data FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 2 HANDLING DEVICES MB95130 MB Series 2 1 Device Handling Precautions E Precaut
543. sesesseeenee entren inns nnns nennen 252 16 7 Operating Description of 8 16 bit PPG sssssssssssssssssseeeee entere ennemi enis 253 16 7 1 8 bit PPG Independent Mode sse eene nnne nentes street nensi nennen 254 16 7 2 8 bit Prescaler 8 bit PPG Mode sse ener nennen nennen en 256 16 7 3 TO DIEPPQIMOGQO tet te rte rete en ratae tired ur Poirot er 258 16 8 Notes on Using 8 16 bit PPG 0 0 ecc cece cceeeeeeeeeeceaeeeeaaeeceeaeeeeaaaeeseaeeeseeaeseceeeesaessseeeeeseaeeessaeesennees 260 16 9 Sample Programs for 8 16 bit PPG Timer nennen enne 261 CHAPTER 17 16 BIT PPG TIMER eur oru ccc unu CR 263 17 1 Overview of 16 bit PPG Timer ssssssssssssssesseeeee eene sinn nsn nnns nennen 264 17 2 Configuration of 16 bit PPG Timer nennen nennen nne inns nnn 265 17 3 Channels of 16 bit PPG Timer etre tert Geta tete Ete EE DT ege o nue nde 267 17 4 Pins of T6 DIL PPO TimMer code tco ene ire ipd e e ao e I Eae ere eet en ee eo 268 17 5 Registers of 16 bit PPG Timer nnr 269 17 5 4 16 bit PPG Down Counter Registers Upper Lower PDCRHO PDCRLO 270 17 5 2 16 bit PPG Cycle Setting Buffer Registers Upper Lower PCSRHO PCSRLO
544. smission Set the bit to 1 How to set the parity The parity control SMC10 PEN and parity polarity SMC10 TDP bits are used Operation Parity control PEN Parity polarity TDP To set to no parity Set the bit to 0 To set to even parity Set the bit to 1 Set the bit to 0 To set to odd parity Set the bit to 1 Set the bit to 1 How to set the data length The data length select bit SMC10 CBL 1 0 is used Operation Data length select bit CBL 1 0 To set the bit length to 5 Set the bits to 00g To set the bit length to 6 Set the bits to 01g To set the bit length to 7 Set the bits to 10 To set the bit length to 8 Set the bits to 11g How to select the STOP bit length The STOP bit length control bit SMCIO SBL is used To set STOP bit length to 1 Set the bit to 0 To set STOP bit length to 2 Set the bit to 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 343 CHAPTER 20 UART SIO 20 8 Sample Programs for UART SIO MB951 30 MB Series How to clear the error flag The reception error flag clear bit SMC20 RERC is used Reception error flag clear bit RERC Control item When clearing error flags PER OVE FER Set the bit to 0 How to set the transfer direction The serial data direction control bit SMC10 BDS is used LSB first MSB first can be selected for transfer direction in any operation mode Control item Serial data dir
545. software activation or continuous activation of the 8 10 bit A D converter E Operations of 8 10 bit A D Converter s Conversion Function Software activation function The settings shown in Figure 23 6 1 are required for software activation of the A D conversion Figure 23 6 1 Settings for A D Conversion Function Software Activation ADC1 ADC2 ADDH ADDL Used bit x Unused bit 0 Set to 0 1 Setto 1 bit7 bite bit5 bit4 bit3 bit2 bit bito ANS3 ANS2 ANS1 ANSO ADI ADMV ADMVX AD 1 AD8 TIM1 TIMO ADCK ADIE EXT CKDIV1 CKDIVO x 0 A D converted value retained A D converted value is retained 440 When A D conversion is activated the A D conversion function starts working In addition even during conversion the A D conversion function can be reactivated FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER MB95130 MB Series 23 6 Operations of 8 10 bit A D Converter and Its Setup Procedure Examples Continuous activation The settings shown in Figure 23 6 2 are required for continuous activation of the A D conversion function Figure 23 6 2 Settings for A D Conversion Function Continuous Activation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito ADC1 ANS3 ANS2 ANS1 ANSO ADI ADMV ADMVX AD
546. ssion status The bit is set to 1 upon completion of serial transmission Note however that the bit is not set to 1 even upon completion of transmission when the serial output data register contains data to be transmitted in succession Writing 0 to this bit clears its flag If events to set and clear the flag occur at the same time it is set preferentially Writing 1 to this bit has no effect on operation 324 TDRE Transmission data register empty flag This flag indicates the status of the UART SIO serial output data register The bit is set to 0 when transmit data is written to the serial output register The bit is set to 1 when data is loaded to the transmission shift register and transmission starts FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 20 UART SIO MB95130 MB Series 20 5 Registers of UART SIO 20 5 4 UART SIO Serial Input Data Register RDRO The UART SIO serial input data register RDRO is used to input receive serial data UART SIO Serial Input Data Register RDRO Figure 20 5 5 shows the bit configuration of the UART SIO serial input data register RDRO Figure 20 5 5 UART SIO Serial Input Data Register RDRO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value RDRO 005A RD7 RD6 RDS RD4 RDB RD2 RD1 RDO 000000006 R WX R WX R WX R WX R WX R WX Read only Readabl
547. st be followed when using the watch prescaler The watch prescaler cannot be used in single clock option product E Notes on Using Watch Prescaler 166 When setting the prescaler by program The prescaler cannot be recovered from interrupt processing when the watch interrupt request flag bit WPCR WTIF is set to I and the interrupt request enable bit is enabled WPCR WTIE 1 Always clear the WTIF bit within the interrupt routine Clearing the watch prescaler When the watch prescaler is selected as the count clock of the watchdog timer WDTC CS1 50 10g or CS1 CSO 115 clearing the watch prescaler also clears the watchdog timer Watch interrupts In the main clock stop mode the watch prescaler performs counting but does not generate the watch prescaler interrupts IRQ20 Peripheral functions receiving clock from the watch prescaler If the watch prescaler is cleared when the output of the watch prescaler is used in other peripheral functions this will affect the operation by changing the count time or in other manners The clock for the watchdog timer is also outputted from the initial state However as the watchdog timer counter is cleared at the same time as the prescaler counter the watchdog timer operates in the normal cycles FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER MB95130 MB Series 12 7 Sample Programs for Watch Prescaler 12 7 Sample Programs for Watch Prescaler
548. ster EICOO Address bit bit6 bits bits bit2 bit bito Initial value 00481 EICOO 0049u ElC10 EIR1 SL11 SL10 EIE1 EIRO 5101 SLOO EIEO 000000008 004AH EIC20 004Bu EIC30 R RM1 W RW R W R W R RM1W RW RW RW EIEO Interrupt request enable bit 0 0 Disables output of interrupt request 1 Enables output of interrupt request Edge polarity select bits 0 No edge detection Rising edge Falling edge Both edges External interrupt request flag bit 0 Read Write Specified edge not inputted Clears this bit Specified edge inputted No change no effect on others 1 Enables output of interrupt request 0 0 No edge detection 0 1 Rising edge 1 0 Falling edge 1 1 Both edges External interrupt request flag bit 1 Read Write Specified edge not inputted Clears this bit Specified edge inputted No change no effect on others R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction Initial value CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 293 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 5 Registers of External Interrupt Circuit MB95130 MB Series Table 18 5 1 Functional Description of Each Bit of External Interrupt Control Register EICOO
549. struction WCFLG Interrupt request flag bit These bits can read the counter value during counting It should be noted that the correct counter value may not be read if a read is CTRS to CTRO attempted while the counter value is being changed Therefore read the Counter read bits counter value twice to check if the same value is read on both occasions before using it Writing has no effect on the operation 176 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 WATCH COUNTER MB95130 MB Series 13 4 Interrupts of Watch Counter 13 4 Interrupts of Watch Counter The watch counter outputs interrupt requests when the counter underflows counter value 0000015 B Interrupts of Watch Counter When the counter of the watch counter underflows the interrupt request flag bit WCFLG of the watch counter control register WCSR is set to 1 If the interrupt request enable bit ISEL of the watch counter is set to 1 an interrupt request of the watch counter is outputted to the interrupt controller Table 13 4 1 shows the interrupt control bits and interrupt sources of the watch timer Table 13 4 1 Interrupt Control Bits and Interrupt Sources of Watch Timer Item Description Interrupt request flag bit WCELG bit of the WCSR register Interrupt request enable bit ISEL bit of the WCSR register Interrupt source Counter underflow E Register and Vector Table Related to Interrupts of Watch Count
550. struction One instruction cycle is a machine cycle Note The number of cycles of the instruction can be delayed by 1 cycle by the immediately preceding instruction Moreover the number of cycles of the instruction might be extended in the access to the I O area It shows the number of bytes for the instruction Operation It shows the operations for the instruction TL TH AH They show the change auto forwarding from A to T in the content when each TL TH and AH instruction is executed The sign in the column indicates the followings respectively No change dH upper 8 bits of the data described in operation AL and AH the contents become those of the immediately preceding instruction s AL and AH 00 Become 00 They show the instruction into which the corresponding flag is changed respectively The sign in the column shows the followings respectively Nochange Change R Become 0 S Become 1 OP CODE CM26 10118 3E It shows the code of the instruction When a pertinent instruction occupies two or more codes it follows the following description rules Example 48 to 4F This shows 48 49 AF FUJITSU MICROELECTRONICS LIMITED 505 APPENDIX APPENDIX E Instruction Overview E 1 Addressing MB95130 MB Series F2MC 8FX has the following ten types of addressings Direct addressing Extended addressing Bit direct addressing Index addressing
551. sub clock 170 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 13 WATCH COUNTER MB95130 MB Series 13 2 Configuration of Watch Counter 13 2 Configuration of Watch Counter Figure 13 2 1 shows the block diagram of the watch counter E Block Diagram of Watch Counter Figure 13 2 1 Block Diagram of Watch Counter Watch counter control register WCSR ISEL WCFLG 5 CTR4 CTR2 CTR1 CTRO Counter value Interrupt of watch Interrupt of prescaler watch counter Underflow Interrupt enabled Counter 6 bit counter Counter clear Internal bus Counter clock Reload value selected From watch prescaler 4 M csi cso RCTR5 RCTR4 RCTR3 RCTR2 lRCTR1 RCTRO Watch counter data register WCDR Foi Sub clock CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 171 CHAPTER 13 WATCH COUNTER 13 2 Configuration of Watch Counter MB95130 MB Series Counter This is a 6 bit down counter that uses the output clock of the watch prescaler as its count clock Watch counter control register WCSR This register controls interrupts and checks the status Watch counter data register WCDR This register sets the interval time and selects the count clock B Input Clock The watch counter uses the output clock of the watch prescaler as its input clock count clock 172 FUJI
552. sults When PWC measurement is completed the counter value is transferred to this register and the BF bit is set to 1 When the 8 16 bit compound timer 00 01 data register is read the BF bit is set to 0 Transfer to the 8 16 bit compound timer 00 01 data register is not performed with the BF bit containing 1 As the exception when the pulse and cycle measurement TOOCRO TO1CRO F3 F2 F1 FO 1001g is selected the H pulse measurement result is transferred to the 8 16 bit compound timer 00 01 data register with the BF bit set to 1 but the cycle measurement result is not transferred to the 8 16 bit compound timer 00 01 data register with the BF bit set to 1 For cycle measurement therefore the H pulse measurement result must be read before the cycle is completed Note also that the result of H pulse measurement or cycle measurement is lost unless read before the completion of the next H pulse When reading the 8 16 bit compound timer 00 01 data register be careful not to clear the BF bit unintentionally Writing to the 8 16 bit compound timer 00 01 data register updates the stored measurement data with the write value Therefore do not perform a write operation In 16 bit operation the upper data and lower data are transferred to TOIDR and TOODR respectively Read TOIDR and TOODR in this order Input capture function The 8 16 bit compound timer 00 01 data register TOODR TOIDR is used to read input capture resu
553. t treats the INTOO pin input as being fixed at 0 Setting the bit to 1 Selects the INTOO pin as an interrupt input pin and the circuit passes the INTOO pin input to INTOO ch 0 of the external interrupt circuit In this case the input signal to the INTOO pin can generate an external interrupt if INTOO ch 0 operation is enabled in the external interrupt circuit SIN SIN interrupt pin select bit This bit is used to determine whether to select the SIN pin as an interrupt input pin Setting the bit to 0 Deselects the SIN pin as an interrupt input pin and the circuit treats the SIN pin input as being fixed at 0 Setting the bit to 1 Selects the SIN pin as an interrupt input pin and the circuit passes the SIN pin input to INTOO ch 0 of the external interrupt circuit In this case the input signal to the SIN pin can generate an external interrupt if INTOO ch 0 operation is enabled in the external interrupt circuit SCK SCK interrupt pin select bit This bit is used to determine whether to select the SCK pin as an interrupt input pin Setting the bit to 0 Deselects the SCK pin as an interrupt input pin and the circuit treats the SCK pin input as being fixed at 0 Setting the bit to 1 Selects the SCK pin as an interrupt input pin and the circuit passes the SCK pin input to INTOO ch 0 of the external interrupt circuit In this case the input signal to the SCK pin can generate an external interrupt if INTOO
554. t Causes CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 97 CHAPTER 8 INTERRUPTS 8 1 Interrupts MB95130 MB Series 8 1 1 Interrupt Level Setting Registers ILRO to ILR5 The interrupt level setting registers ILRO to ILR5 contain 24 pairs of bits assigned for the interrupt requests from different peripheral resources Each pair of bits interrupt level setting bits as two bit data sets each interrupt level E Configuration of Interrupt Level Setting Registers ILRO to ILR5 Figure 8 1 1 Configuration of Interrupt Level Setting Registers Register Address bit bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value ILRO 000794 L03 1 0 L02 1 0 101 1 0 LOO 1 0 RW 111111116 ILR1 0007A 107 1 0 L06 1 0 LOS 1 0 L04 1 0 RW 111111116 ILR2 0007B4 L11 10 Lio 1 0 09 1 0 Lo8 1 0 RW 111111118 0007C 115 1 0 L14 1 0 L13 1 0 L12 1 0 RW 111111116 ILR4 0007Dy L19 1 0 L18 1 0 L17 1 0 L16 1 0 RW 111111116 ILR5 ooozE L23 10 L22 1 0 Let 1 0 L20 1 0 RW 111111115 The interrupt level setting registers assign each pair of bits for a different interrupt request The values of interrupt level setting bits in these registers specify interrupt service priorities interrupt levels 0 to 3 The interrupt level setting
555. t Pin Selection Circuit 303 Block Diagram of LIN UART Pins 364 Block Diagram of Low voltage Detection Reset Circuit M H T 449 Block Diagram of Pins Related to 8 10 bit A D Converter Block Diagram 432 Block Diagram of Pins Related to 8 16 bit Compound bulis 203 Block Diagram of Pins Related to 8 16 bit PPG seeen 242 Block Diagram of Pins Related to External Interrupt edil a in a 291 Block Diagram of Pins Related to UART SIO 317 Block Diagram of Port 0 111 Block Diagram of Port 1 suus 116 Block Diagram of Port 121 Block Diagram of Port G 126 Block Diagram of Time base Timer 133 Block Diagram of UART SIO 313 Block Diagram of UART SIO Dedicated Baud Rate Generator 348 Block Diagram of Watch Counter 171 Block Diagram of Watch Prescaler 157 Block Diagram of Watchdog Timer 147 Block Diagram of Wild Register Function 185 Block Diagrams of Pins Related to 16 bit PPG ssseeeene 268 Clock Controller Block Diagram 47 LIN UART Block Diagram 359 Prescaler Block Diagram 82 Branch Branch Ins
556. t cycle of watch prescaler QI Count clock switch bits Output cycle of watch prescaler 213 Write to these bits at the same time as activating the watchdog timer by the watchdog control bits No change can be made once the watchdog timer is activated Note Always select the output of the watch prescaler in the sub clock mode or sub PLL clock mode as the time base timer is stopped in these modes Do not select the output of the watch prescaler in single clock product These bits are undefined Undefined bits The read value is 00g Writing has no effect on the operation These bits are used to control the watchdog timer WTE3 WTE2 Writing 01015 activates the watchdog timer in first write after reset or clears it in WTEI WTEO Watchdog control bits second or succeeding write after reset Writing other than 01015 has no effect on operation The read value is 00005 Read modify write RMW instructions cannot be used CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 151 CHAPTER 11 WATCHDOG TIMER 11 4 Explanation of Watchdog Timer Operations and Setup MB95130 MB Series Procedure Example 11 4 Explanation of Watchdog Timer Operations and Setup Procedure Example The watchdog timer generates a watchdog reset when the watchdog timer counter overflows il Operations of Watchdog Timer How to activate the watchdog timer e The timer of the watchdog timer is activated w
557. t on the operation WTCI WTCO Watch interrupt interval time select bits These bits select the interval time Interval time select bits sub clock Fc 32 768kHz 21 X 2 66 125ms 212 X 2 Foy 250ms 213 X 2 Fc4 500ms 21 X 2 1 005 WCLR Watch timer initialization bit CM26 10118 3E This bit clears the counter for the watch prescaler Writing 0 ignored and has no effect on the operation Writing 1 initializes all counter bits to 1 The read value is always 0 Note When the output of the watch prescaler is selected as the count clock of the watchdog timer clearing the watch prescaler with this bit also clears the watchdog timer FUJITSU MICROELECTRONICS LIMITED 161 CHAPTER 12 WATCH PRESCALER 12 4 Interrupts of Watch Prescaler MB95130 MB Series 12 4 Interrupts of Watch Prescaler An interrupt request is generated when the selected interval time of the watch prescaler has elapsed interval timer function B Interrupts in Operation of Interval Timer Function Watch Interrupts In any mode other than the main clock stop mode the watch interrupt request flag bit is set to 1 WPCR WTIF 1 when the watch prescaler counter counts up by using the source oscillation of the sub clock and the time of the interval timer has elapsed If the interrupt request enable bit is also enabled WPCR WTIE 1 and watch counter start interrupt request enable
558. t reload counter is read from this generator E Bit Configuration of LIN UART Baud Rate Generator Register 1 0 BGR1 BGRO Figure 22 4 8 shows the bit configuration of LIN UART baud rate generator register 1 0 BGRO Figure 22 4 8 Bit Configuration of LIN UART Baud Rate Generator Register 1 0 BGR1 BGRO Address bit7 bit6 bitS bit4 bit3 bit2 biti Initial value sont oreca edendo 00000000 RO WXR W R W R W R W R W R W R W LIN UART baud rate generator register 1 Write Write to reload counter bit 8 to bit 14 Read Read transmit reload counter bit 8 to bit 14 x Undefined bit Address bit7 bit6 bitS bit4 bit3 bit2 biti bitO Initial value coro oF fpes R W R W R W R W R W R W R W R W LIN UART baud rate generator register 0 Write Write to reload counter bit 0 to bit 7 Read Read transmit reload counter bit O to bit 7 R W Readable writable Read value is the same as write value RO WX Undefined bit Read value is 0 writing has no effect on operation The LIN UART baud rate generator register sets the division ratio of the serial clock BGRI is associated with the upper bits BGRO is associated with the lower bits The reload value of the counter can be written and the transmit reload counter value can be read from them Byte word access is also possible Writing a reload value to the LIN UART baud rate generator regist
559. ta length parity setting synchronization type must be the same between all CPUs and thus the operation mode must be selected as follows e One to one connection Two CPUs must use the same method in either operation mode 0 or 2 Choose operation mode 0 in an asynchronous system and operation mode 2 in a synchronous system Also for the operation mode 2 set one CPU as sending side of serial clock and the other as the receiving side of serial clock e Master slave connection Select operation mode 1 Use the system as a master slave system E Synchronous Method In asynchronous method the reception clock is synchronized with the reception start bit falling edge In synchronous method the reception clock can be synchronized by the sending side of serial clock signal or the clock signal at operating as sending side of serial clock E Signaling NRZ Non Return to Zero E Enable Transmission Reception The LIN UART uses the SCR TXE bit and the SCR RXE bit to control transmission and reception respectively To disable transmission or reception set as follows If the reception is in progress wait until the reception completed read the reception data register RDR and then disable the reception If the transmission is in progress wait until the transmission completed and then disable the transmission E Setup Procedure Example LIN UART is set in the following procedure Initial setting 1 Set the port input DDR1 2 Set
560. ta pin Enables disables output to the clock pin LIN UART serial status register SSR Operating functions are as follows Check transmission reception or error status Selects the transfer direction LSB first or MSB first Enables disables reception interrupts Enables disables transmit interrupts Q Extended status control register ESCR CM26 10118 3E Enables disables LIN synch break interrupts LIN synch break detection Selects LIN synch break length Direct access to SIN pin and SOT pin Sets continuous clock output in LIN UART synchronous clock mode Sampling clock edge selection FUJITSU MICROELECTRONICS LIMITED 361 CHAPTER 22 LIN UART 22 2 Configuration of LIN UART MB95130 MB Series LIN UART extended communication control register ECCR Bus idle detection e Synchronous clock setting LIN synch break generation B Input Clock LIN UART uses a machine clock or an input signal from the SCK pin as an input clock Input clock is used as clock source of transmission reception of LIN UART 362 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series 22 3 Pins of LIN UART CHAPTER 22 LIN UART 22 3 Pins of LIN UART This section describes LIN UART pins Bi Pins related to LIN UART The LIN UART pins also serve as general purpose ports Table 22 3 1 lists the LIN UART pin Table 22 3 1 LIN UART Pins Pin name Pin function Serial data input Required settings for using the pin Set to
561. tabilization wait time to elapse before entering sub clock mode either if the sub clock has been stopped according to the setting of the sub clock oscillation stop bit in the system clock control register SYCC SUBS in main PLL clock mode or if the sub clock oscillation stabilization wait time has not passed immediately after the power is turned on When the system clock select bits in the system clock control register SYCC SCS1 ve SCSO are set to Olg the device enters sub PLL clock mode after waiting for the ain PLL Clock sub PLL clock oscillation stabilization wait time Note however that the device does not wait for the sub PLL clock oscillation stabilization wait time to elapse if the sub PLL clock has been oscillating according to the setting of the sub PLL clock oscillation enable bit in the PLL control register PLLC SPEN in main PLL clock mode Sub Note also that the device waits for the sub clock oscillation stabilization wait time to PLL Clock elapse before entering sub PLL clock mode either if the sub clock has been stopped according to the setting of the sub clock oscillation stop bit in the system clock control register SYCC SUBS in main PLL clock mode or if the sub clock oscillation stabilization wait time has not passed immediately after the power is turned on When the device waits for the sub clock oscillation stabilization wait time or sub PLL clock oscillation stabilization wait time it waits for whichever i
562. tch SPL 1 Internal bus U c p Only P04 is selectable ILSR2 read gt ILSR2 ILSR2 write LUN 242 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG MB95130 MB Series 16 5 Registers of 8 16 bit PPG 16 5 Registers of 8 16 bit PPG This section describes the registers of the 8 16 bit PPG E Registers of 8 16 bit PPG Figure 16 5 1 shows the registers of the 8 16 bit PPG Figure 16 5 1 Registers of 8 16 bit PPG 8 16 bit PPG timer 01 control register PCO1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value 008A PCO1 PIE1 PUF1 POEN1 CKS12 CKS11 CKS10 000000006 RO WX RO WX RW RW R W R W R W 8 16 bit PPG timer 00 control register PCOO Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 003By MD1 MDO PIEO PUFO POENO CKS02 CKS01 CKS00 000000006 R W R W R W R RM1 wW RW R W R W R W 8 16 bit PPG timer 01 cycle setup buffer register PPS01 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit0 Reset value OF9C PPSO1 PH7 PH6 PH5 PHA PH3 PH2 PH1 PHO 11111111 R W R W R W R W R W R W R W R W 8 16 bit PPG timer 00 cycle setup buffer register 500 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bit0 Reset value OF9D 500 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO 111111116 R W R W R W R W R W R W R W R W 8 16 bit PPG timer 01 duty setup buffer register
563. te The values in parentheses are reference values Please confirm the latest Package dimension by following URL http edevice fujitsu com package en search 12 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series E Package Dimension of FPT 30P M02 CHAPTER 1 DESCRIPTION 1 6 Package Dimension Figure 1 6 2 Package Dimension of FPT 30P M02 003 009 0 10 004 2003 2008 FUJITSU MICROELECTRONICS LIMITED F30003S c 3 5 ARS 0 65 026 0 24 207 30 pin plastic SSOP Lead pitch 0 65 mm Package width x 5 60 x 9 70 mm package length Lead shape Gullwing Sealing method Plastic mold Mounting height 1 45 mm MAX Done P SSOP30 5 6x9 7 0 65 Reference FPT 30P M02 30 pin plastic SSOP Note 1 1 Resin protrusion Each side 0 15 006 Max FPT 30P M02 Note 2 2 These dimensions do not include resin protrusion Note 3 Pins width and pins thickness include plating thickness Note 4 Pins width do not include tie bar cutting remainder a 19 70 0 10 382 004 0 17 0 03 007 001 E 25 60 0 10 7 60 0 20 220 004 299 008 Details of A part Y KL ae A Mounting height 0 25 010
564. teet diiit 81 Prescaler Block Diagram suus 82 Setting 8 bit Prescaler 8 bit PPG Mode 256 Procedure Setup Procedure Example 258 281 297 Product Lineup Product Lineup of MB95130 MB Series 4 Program Sample Programs for 16 bit PPG Timer 283 Sample Programs for 8 16 bit PPG Timer 261 Sample Programs for External Interrupt COECUIL Sonde hes Pete a audeo 299 Setting Methods not Covered by Sample Programs Nosque a T 167 181 342 422 444 Setup Methods without Sample Program 261 283 299 Programming Procedure Flash Memory Programming Procedure 478 PSSR UART SIO Dedicated Baud Rate Generator Prescaler Selection Register PSSRO 351 PWC Operation of PWC Timer Function 229 PWC Timer Function eene 197 When Interval Timer Input Capture or PWC Function Has Been Selected 234 533 PWM Mode PWM Mode MDSE of PCNTH Register bit 520 etes i ierra 278 PWM Timer Operation of PWM Timer Function Fixed cycle Mode 225 Operation of PWM Timer Function Variable cycle Mode 227 PWM Timer Function Fixed cycle Mode 196 PWM Timer Function Variable cycle Mode 196 R RAM Effect of Reset on RAM Contents 88 RDR
565. ter 1 ADC1 8 10 bit A D Converter Data Registers 8 10 bit A D Converter Data Registers Upper Lower ADDH ADDL eene 438 8 16 bit LIN Synch Field Edge Detection Interrupt 8 16 bit Compound Timer Interrupt 381 8 16 bit Compound Timer Block Diagram of 8 16 bit Compound Timer dred 199 Block Diagram of Pins Related to 8 16 bit Compound TIT uiii ria daran 203 Channels of 8 16 bit Compound Timer 201 Notes on Using 8 16 bit Compound act peine uenerunt 236 Pins Related to 8 16 bit Compound Timer 202 Registers and Vector Tables Related to Interrupts of 8 16 bit Compound Timer 218 Registers Related to 8 16 bit Compound ree 204 8 16 bit Compound Timer 00 01 Control Status Register 8 16 bit Compound Timer 00 01 Control Status Register 0 205 8 16 bit Compound Timer 00 01 Control Status Register 1 TOOCR1 TOICRI1 208 8 16 bit Compound Timer 00 01 Data Register 8 16 bit Compound Timer 00 01 Data Register TOODR TOIDR 214 8 16 bit Compound Timer 00 01 Timer Mode Control Register 8 16 bit Compound Timer 00 01 Timer Mode Control Register ch 0 TMCRO 211 8 16 bit PPG Block Diagram of 8 16 bit PPG 239 Block Diagram of Pins Related to 8 16 bit PPG isiti
566. ternal Interrupt Circuit 18 4 Pins of External Interrupt Circuit 18 5 Registers of External Interrupt Circuit 18 6 Interrupts of External Interrupt Circuit 18 7 Explanation of External Interrupt Circuit Operations and Setup Procedure Example 18 8 Notes on Using External Interrupt Circuit 18 9 Sample Programs for External Interrupt Circuit CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 287 CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT 18 1 Overview of External Interrupt Circuit MB951 30 MB Series 18 1 Overview of External Interrupt Circuit The external interrupt circuit detects edges on the signal that is inputted to the external interrupt pin and generates interrupt requests to the CPU E Functions of External Interrupt Circuit The external interrupt circuit has the functions to detect any edge of a signal that is inputted to an external interrupt pin and generate an interrupt request to the CPU This interrupt allows the unit to recover from a standby mode and return to its normal operation 288 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT MB95130 MB Series 18 2 Configuration of External Interrupt Circuit 18 2 Configuration of External Interrupt Circuit The external interrupt circuit consists of the following blocks e Edge detection circuit e External interrupt control register E Block Diagram of External Interrupt Circuit Figure 18 2 1 shows the block diagram of the externa
567. terrupt Pin Selection Circuit The peripheral function pins related to the interrupt pin selection circuit are the TRGO ADTG UCKO UIO SCK SIN and INTOO pins These inputs except INTOO are also connected to their respective peripheral units in parallel and can be used for both functions simultaneously Table 19 3 1 lists the correlation between the peripheral functions and peripheral input pins Table 19 3 1 Correlation Between Peripheral Functions and Peripheral Input Peripheral input pin name Peripheral functions name INTOO Interrupt pin selection circuit TRGO ADTG Interrupt pin selection circuit 16 bit PPG timer trigger input 8 10 bit A D converter trigger input UCKO Interrupt pin selection circuit UART SIO clock input output UIO Interrupt pin selection circuit UART SIO data input ECO Interrupt pin selection circuit 8 16 bit compound timer event input SCK Interrupt pin selection circuit LIN UART clock input output SIN 304 Interrupt pin selection circuit LIN UART data input FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT MB95130 MB Series 19 4 Registers of Interrupt Pin Selection Circuit 19 4 Registers of Interrupt Pin Selection Circuit Figure 19 4 1 shows the registers related to the interrupt pin selection circuit E Registers Related to Interrupt Pin Selection Circuit Figure 19 4 1 Re
568. terrupt request flag bit of the peripheral resource is set to 1 If the interrupt request enable bit of the peripheral resource has been set to enable interrupts the interrupt request is then output to the interrupt controller 4 The interrupt controller always monitors interrupt requests from individual peripheral resources and transfers the highest priority interrupt level to the CPU among the interrupt levels of the currently generated interrupt requests The relative priority to be assigned if another request with the same interrupt level occurs simultaneously is also determined at this time 5 If the received interrupt level or priority is lower than the level set in the interrupt level bits in the condition code register CCR IL1 ILO the CPU checks the content of the interrupt enable flag and if interrupts are enabled CCR I 1 accepts the interrupt 6 The CPU pushes the contents of the program counter PC and program status PS register onto the stack fetches the start address of the interrupt processing routine from the corresponding interrupt vector table changes the value of the interrupt level bits in the condition code register CCR IL1 ILO to the value of the received interrupt level then starts the execution of the interrupt processing routine 7 Finally the CPU uses the RETI instruction to restore the program counter PC and program status PS values from the stack and resumes execution from th
569. th Lead shape Gullwing Sealing method Plastic mold Mounting height 2 80 mm MAX Weight 0 82 g Code FPT 28P M17 Reference P SOP28 8 6x17 75 1 27 28 pin plastic SOP Note 1 1 These dimensions include resin protrusion FPT 28P M17 Note 2 2 These dimensions do not include resin protrusion Note 3 Pins width and pins thickness include plating thickness Note 4 Pins width do not include tie bar cutting remainder 9117 75 020 699 os eua 0 17308 007 1 ll 11 80 0 30 465 012 INDEX 8 604020 wee ga e 339 008 Details of A part _ Mounting height DEA 1 0 25 010 i 25 mU LM A ATO 0 8 li ee L 1 27 050 0 47 0 08 E 019 003 2 134005 Y _0 80 0 20 0 20 0 15 031 008 0085006 0 8840 15 Stand off 9 H 035 006 Le 0 10 004 Dimensions in mm inches 2002 2008 FUJITSU MICROELECTRONICS LIMITED F28048S c 3 5 No
570. th addressing indicated dir b in instruction table In this addressing when the operand address is 00g to 7 it is accessed into 0000g to 007 Moreover when the operand address is 804 to FFy the access can be mapped in 0080g to 047F by setting of direct bank pointer DP The position of the bit in the specified address is specified by the values of the instruction code of three subordinate position bits Figure E 1 3 shows an example Figure E 1 3 Example of Bit Direct Addressing SETB 34H 2 76543210 DP gt 0 0 3 4H XXXXX1XXB Index addressing This is used when the area of the entire 64 K bytes is accessed by addressing shown IX off in the instruction table In this addressing the content of the first operand is sign extended and added to IX index register to the resulting address Figure E 1 4 shows an example Figure E 1 4 Example of Index Addressing MOVW A 5AH IX 27A 5 27FFH 12H 2800H 34H gt 1234H 1 1 Pointer addressing This is used when the area of the entire 64 K bytes is accessed by addressing shown EP in the instruction table In this addressing the content of EP extra pointer is assumed to be an address Figure E 1 5 shows an example Figure E 1 5 Example of Pointer Addressing MOVW A EP EP 27 A5H
571. the reception error flag and enable disable transmission reception Bi LIN UART Serial Control Register SCR Figure 22 4 2 LIN UART Serial Control Register SCR Address bit7 bit6 bits bit4 bit bit2 biti bito Initial value 909 ren p sec cL Ap cme nxe rxe 000000005 R W R W R W R W R W ROW R W R W TXE Transmit operation enable bit 0 Disable transmission 1 Enable transmission RXE Reception operation enable bit 0 Disable reception 1 Enable reception Reception error flag clear bit Write Read No effect 0 is Clear reception error flag always PE FRE ORE read AD Address data format selection bit 0 Data frame 1 Address data frame CL Data length selection bit 0 7 bit 1 8 bit SBL Stop bit length selection bit 0 1 bit 1 2 bit P Parity selection bit 0 Even parity 1 Odd parity PEN Parity enable bit R W Readable writable Read value is the same as write value RX WO Write only Writable 0 is read Initial value 0 No parity 1 With parity 366 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART 22 4 Registers of LIN UART MB95130 MB Series Table 22 4 1 Functions of Each Bit in LIN UART Serial Control Register SCR Bit name Function PEN Parity enable bit Specify whether or not to a
572. the functions except external interrupt and low voltage detection reset while retaining the contents of registers and RAM that exist immediately before the transition to stop mode In main clock mode or main PLL clock mode however you can start or stop sub clock oscillation by setting the sub clock oscillation stop bit in the system clock control register SYCC SUBS When the sub clock is oscillating the watch prescaler and watch counter operate Q Transition to stop mode Writing 1 to the stop bit in the standby control register STBC STP causes the device to enter stop mode At this time the states of external pins are retained when the pin state setting bit in the standby control register STBC SPL is 0 and the states of external pins become high impedance when that bit is 1 those pins are pulled up for which pull up resistor connection has been selected in the pull up setting register In main clock mode or main PLL clock mode a time base timer interrupt request may be generated while the device is waiting for main clock oscillation to stabilize after being released from stop mode by an interrupt If the interrupt interval time of the time base timer is shorter than the main clock oscillation stabilization wait time you should disable interrupt requests output from the time base timer before entering stop mode thereby preventing unexpected interrupts from occurring You should also disable interrupt requests output from the
573. the input port DDR corresponding bit 0 Serial data output Set to output enable SMR SOE 1 Serial clock input output Set to the input port when used as clock input DDR corresponding bit 0 Set to output enable when used as clock output SMR SCKE 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 363 CHAPTER 22 LIN UART 22 3 Pins of LIN UART MB95130 MB Series E Block Diagram of LIN UART Pins Figure 22 3 1 Block Diagram of LIN UART Pins SCK SOT SIN Hysteresis qp 2 2 2 4 Peripheral function input k Peripheral function input enable 1 Peripheral function output enable l Only o4 is 1 Peripheral function output 4 ll ee s a E 0 Automotive Pull up 0 cmos HH lt lt 1 SET N Le P ch PDR read S Pin gt PDR 0 T PDR write In bit operation instruction DDR read gt DDR 4 DDR write Stop Watch SPL 1 sp 3 2 PUL read E gt PUL PUL write AIDR read gt AIDR 4 AIDR write dp REED 79 ILSR read Ls ILSR ILSR write Only P04 is selectable ILSR2 read ILSR2 ILSR2 write pw 364 FUJITSU MICROELECTRON
574. the interrupt level ILR1 ILR2 3 Set the data format enable transmission reception SCR 4 The operation mode baud rate selection pin output enabled SMR 5 The baud rate generator 1 0 BGRI BGRO 396 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART 22 7 1 Operation of Asynchronous Mode Operation Mode O 1 When LIN UART is used in operation mode 0 normal mode or operation mode 1 multiprocessor mode the transfer method is asynchronous Asynchronous Mode Operation Q Transmit reception data format Transmit reception data always begins with a start bit L level followed by a specified data bits length and ends up with at least one stop bit H level The bit transfer direction LSB first or MSB first is determined by the BDS bit in the LIN UART serial status register SSR When a parity is used the parity bit is always placed between the last data bit and the first stop bit In operation mode 0 select 7 bit or 8 bit for the data length You can select whether or not to use a parity Also the stop bit length 1 or 2 can be selected In operation mode 1 a data length is 7 bit or 8 bit the parity is not added and the address data bit is added The stop bit length 1 or 2 can be selected The bit length of transmit reception frame is calculated as follows Length 1 d p s d Number of data bits 7 or 8
575. the reception enable bit SCR RXE Control item Reception enable bit RXE Disable reception Set to 0 Enable reception Set to 1 Use the transmit control bit SCR TXE Control item Transmit control bit TXE Disable transmission Set to 0 Enable transmission Set to 1 How to use an external clock as the LIN UART serial clock Use the one to one external clock enable bit SMR OTO Control item Reception enable bit OTO How to restart the reload counter Use the reload counter restart bit SMR REST Control item Reload counter restart bit REST How to reset the LIN UART Use the LIN UART programmable clear bit SMR UPCL Control item LIN UART programmable clear bit UPCL How to set the parity Use the parity enable bit SCR PEN and the parity select bit SCR P Operation Parity control PEN Parity polarity P To set to no parity Set to 0 To set to even parity Set to 1 Set to 0 To set to odd parity Set to 1 Set to 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 423 CHAPTER 22 LIN UART 22 9 Sample Programs of LIN UART MB95130 MB Series How to set the data length Use the data length select bit SCR CL To set the bit length to 7 Set to 0 To set the bit length to 8 Set to 1 How to select the STOP bit length Use the STOP bit length control SCR SBL To set STOP bit length to 1 Set to 0 To set STOP bit le
576. the timer operation mode select bits TOOCRO TO1CRO F3 F2 F1 FO the timer operation must be stopped TOOCR1 TO1CR1 STA 0 before clearing the interrupt flag TOOCR1 TOICRI1 IF IR interrupt enable bits TOOCR1 TO1CR1 IE TOOCRO TO1CRO IFE and buffer full flag TOOCR1 TOICR1 BF When the PWC or input capture function has been selected an interrupt may occur even before the timer is activated STA 0 Therefore nullify the value of the 8 16 bit compound timer 00 01 data register TOODR TO1DR obtained before the activation In the case of using the input capture function when the timing at which the 8 16 bit compound timer captures a counter value is the detection of either edge of the external input signal TOOCRO TO1CRO F3 F0z1100g or 1111 the operations in falling edge detection vary according to the level of the external input signal as explained below External input signal level H In both free run mode and clear mode the first falling edge is ignored no counter value is transferred to the data register TOODR TO1DR and the pulse width measurement completion edge detection flag TOOCR1 TOICR 1 16 is not set In addition in clear mode the counter is not cleared either External input signal level L The 8 16 bit compound timer starts edge detection from the first rising edge FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 16 8 16 BIT PPG This chapter describes the functions and operations of t
577. timer 00 Setting the bit to 1 enables interrupts of PPG timer 00 An interrupt request IRQ is outputted when the counter borrow detection bit PUFO and PIEO bit are both set to 1 PUFO Counter borrow detection flag bit for PPG cycle down counter This is the counter borrow detection flag for the PPG cycle down counter of PPG timer 00 Only this bit is effective in 16 bit PPG operation mode PC01 PUF1 is not operable Note Always effective in 8 bit mode Writing 1 to this bit is meaningless Writing 0 clears the bit e 1 is read in read modify write RMW instruction When set to 0 Counter borrow of PPG timer 00 undetected When set to 1 Counter borrow of PPG timer 00 detected POENO Output enable bit This bit enables or disables the output of PPG timer 00 pin When set to 0 PPG timer 00 pin is used as a general purpose port When set to 1 PPG timer 00 pin is used as the PPG output pin As the output is supplied from the PPG timer 00 pin in 16 bit PPG operation mode this bit is used to control the operation CKS02 501 CKS00 Operating clock select bits CM26 10118 3E These bits select the operating clock for PPG down counter PPG timer 00 The operating clock is generated from the prescaler Refer to CHAPTER 6 CLOCK CONTROLLER The rising and falling edge detection pulses from the PPG timer 01 output are used as the count clock for PPG timer 00 when the 8 b
578. tion decimaladjustforsubtraction A lt AL v TL lt AL v d8 A dir A e AL v dir A GEP A lt AD v EP A GIX off A lt AL v off A Ri A lt AL v RD A A lt AL TL 516 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E MB95130 MB Series Table E 4 2 Arithmetic Operation Instruction 2 2 MNEMONIC A d8 Operation A AL A 48 APPENDIX APPENDIX E Instruction Overview OPCODE A dir A AL A dir A EP A AL EP A IX off A AL A IX off A Ri A AL A Ri A A lt AL V TL A d8 A lt AL V 48 A dir A AL V dir A EP lt AL V EP A IX off A lt AL v IX off A Ri A AL V Ri dir d8 dir d8 EP 418 d8 IX off d8 off d8 Ri d8 Ri d8 SP lt SP 1 B Branch Instructions SP lt SP 1 Table E 4 3 Branch Instructions BZ BEQ MNEMONIC at branch Operation ifZ IthenPCc PC rel OPCODE BZ BEQ at no branch BNZ BNE at branch ifZ OthenPC lt PC rel BNZ BNE at no branch BC BLO at branch 1thenPC lt PC rel
579. tion Wait Time Setting Register WATR Table 6 5 1 Functions of Bits in Oscillation Stabilization Wait Time Setting Register WATR 2 2 Bit name Function Set the main clock oscillation stabilization wait time Number of Main Cloc Cycles Fou 4 MHz 1113 2142 214 2 About 4 10 ms MWT3 MWT2 MWT1 MWTO 1110g 213 2 213 2 About 2 05 ms 1101g 2125 212 2 Foy About 1 02 ms 11005 211 2 Q i2 Feg 511 5 us 1011p 2102 Foy 255 5 us 1010g 29 2 Foy 127 5 us 1001g 28 2 Foy 63 5 us MWT3 MWT2 1000 27 2 F 31 5 uis MWTI MWTO P Eoo ede Main clock 0111g 25 2 Fcg 15 5 us Oscillation stabilization wait 01105 2 2 Fou 7 5 US time select bits 0101 24 2 FcH 3 5 us 01005 3 23 2 Fe 1 5 us 0011 22 2 Foy 0 5 us 0010p 21 2 Foy 0 0 us 0001p 2 2 Fey 0 015 00005 21 2 Fe 0 0 us Number of cycles is for a minimum value Add 1 F y to the minimum value for a maximum value Note Do not update these bits during main clock oscillation stabilization wait time You should update them in main clock mode or main PLL clock mode You can also update them in sub clock mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 61 CHAPTER 6 CLOCK CONTROLLER 6 6 Standby Control Register STBC MB95130 MB Series 6 6 Standby Control Register STBC The standby control register STBC is used to control transition from the RUN state to sleep mode stop mode time base timer m
580. tion control bit This bit sets the serial data direction endian Setting the bit to 0 the bit specifies transmission or reception to be performed sequentially starting from the LSB side in the serial data register Setting the bit to 1 the bit specifies transmission or reception to be performed sequentially starting from the MSB side in the serial data register PEN Parity control bit This bit enables or disables parity in clock asynchronous mode Setting the bit to 0 no parity Setting the bit to 1 with parity TDP Parity polarity bit This bit controls even odd parity Setting the bit to 0 specifies even parity Setting the bit to 1 specifies odd parity SBL Stop bit length control bit This bit controls the length of the stop bit in clock asynchronous mode Setting the bit to 0 sets the stop bit length to 1 Setting the bit to 1 sets the stop bit length to 2 Note The setting of this bit is only valid for transmission operation in asynchronous mode For receiving operation reception data register full flag is set to 1 after detecting stop bit 1 bit and completing the reception regardless of this bit CBLI CBLO Character bit length control bit These bits select the character bit length as shown in the following table Character bit length The above setting is valid in both asynchronous and synchronous modes CKS Clock selection bit This bit se
581. tion has been selected in the pull up setting register SRST Software reset bit Sets a software reset When set to 0 has no effect on operation When set to 1 the bit generates a 3 machine clock reset signal When read the bit always returns 0 TMD Watch bit On dual clock product this bit sets transition to time base timer mode or watch mode On single clock product the bit sets transition to time base timer mode Writing 1 to the bit in main clock mode or main PLL clock mode causes transition to time base timer mode Writing 1 to the bit in sub clock mode or sub PLL clock mode causes transition to watch mode Writing 0 to this bit has no effect on operation When read the bit always returns 0 Note An attempt to write 1 to this bit is ignored if an interrupt request has been issued For details see Section 6 8 1 Notes on Using Standby Mode Undefined bits CM26 10118 3E The read value is always 0 These bits are undefined This bit is read only Writing has no effect on operation FUJITSU MICROELECTRONICS LIMITED 63 CHAPTER 6 CLOCK CONTROLLER 6 6 Standby Control Register STBC MB95130 MB Series Notes Set the standby mode after making sure that the transition to clock mode has been completed by comparing the values of the clock mode monitor bits SYCC SCM1 SCMO and clock mode setting bits SYCC SCS1 SCS0 in the system clock control register If
582. tion stabilization from stop mode or a reset oscillator lt wait time NIU UU Oscillation stabilized Oscillation started The main clock oscillation stabilization wait time is counted by using the time base timer The sub clock oscillation stabilization wait time is counted by using the watch prescaler The count can be set in the oscillation stabilization wait time setting register WATR Set it in keeping with the oscillator characteristics When a power on reset occurs the oscillation stabilization wait time is fixed to the initial value For masked ROM products however you can specify the initial value of the oscillation stabilization wait time when ordering masked ROM Table 6 2 1 shows the length of oscillation stabilization wait time Table 6 2 1 Oscillation Stabilization Wait Time Factor Oscillation stabilization wait time uu 914 5 Poweronteset Initial value 2 2 Foy where Foy is the main clock frequency Main clock Specified when ROM is ordered for mask ROM products Other than power on reset Register setting value WATR MWT3 MWT2 MWT1 MWTO Sub clock Power on reset Initial value 2 2 Fc where is the sub clock frequency Dual clock product Other than power on reset Register setting value WATR SWT3 SWT2 SWT1 SWTO After the oscillation stabilization wait time of the main clock ends the oscillation stabilization wait time of sub clock m
583. tion stop bit in the system clock control register SYCC SUBS in main clock mode or if the sub clock oscillation stabilization wait time has not passed immediately after the power is turned on When the device waits for the sub clock oscillation stabilization wait time or sub PLL clock oscillation stabilization wait time it waits for whichever is longer to elapse Sub PLL Clock When the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 115 the device enters main PLL clock mode after waiting for the Main main PLL clock oscillation stabilization wait time Note however that the device PLL Clock does not wait for the main PLL clock oscillation stabilization wait time to elapse if the main PLL clock has been oscillating according to the setting of the main PLL clock oscillation enable bit in the PLL control register PLLC MPEN 68 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 7 Clock Mode Table 6 7 1 Clock Mode State Transition Table 2 2 Current State Next State Description The device enters main clock mode when the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 105 The device enters sub clock mode when the system clock select bits in the system clock control register SYCC SCS1 SCSO are set to 005 Note however that the device waits for the sub clock oscillation s
584. tion stopped In this mode the time base timer remains stopped as it requires the main clock for operation If you set standby mode during operation in sub clock mode the device can enter sleep mode stop mode or watch mode il Operations in Main PLL Clock Mode Main PLL clock mode uses the main PLL clock as the machine clock for the CPU and peripheral resources The time base timer and watchdog timer operate with the main clock The watch prescaler and watch counter operate with the sub clock on dual clock product If you set standby mode during operation in main PLL clock mode the device can enter sleep mode stop mode or time base timer mode E Operations in Sub PLL Clock Mode on Dual Clock Product Sub PLL clock mode uses the sub PLL clock as the machine clock for the CPU and peripheral resources with main clock oscillation stopped In this mode the time base timer remains stopped as it requires the main clock for operation The watch prescaler and watch counter operate with the sub clock If you set standby mode during operation in sub PLL clock mode the device can enter sleep mode stop mode or watch mode CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 65 CHAPTER 6 CLOCK CONTROLLER 6 7 Clock Mode MB95130 MB Series E Clock Mode State Transition Diagram The clock modes available are main clock mode main PLL clock mode sub clock mode and sub PLL clock mode The device can switch between these modes according to the se
585. tions of POft O i dd od de b e i 113 9 3 es Gr tend crie De akira aie aaa acted a Aire eee Dae eu ce us 115 9 3 1 Port 1 Feglsters tet aie te tents 117 9 3 2 Operatioris GFPoft les aste oed ce roble eec nS hes eed lb rome 118 9 4 menudo M 120 9 4 1 Port Fi Registers Et tee tea tiet e i eere dui ie ea 122 9 4 2 Operations of Port E ite teet leiden ithe eee 123 9 5 TEM REM 125 9 5 1 Port G JHeglslerg ui doti te e ai eh matt testi siente sot EI SUE 127 9 5 2 Operations Of Port 128 CHAPTER 10 TIME BASE XD e v bk Rin Suse 131 10 1 Overview of Time base Timer 132 10 2 Configuration of Time base Timer nnne en trennen nennen 133 10 3 Registers of the Time base Timer E TEA EARE nennen enitn tnnt 135 10 3 1 Time base Timer Control Register TBTO sse rennen nenne 136 10 4 Interrupts of Time base Timer sssssssesessseeneeneeneeennnn nennen nnne nnne nennen enn 138 10 5 Explanation of Time base Timer Operations and Setup Procedure Example 140 10 6 Notes on Using Time base Timer
586. to inverted OSEL bit in PCNTLO register 1 the PPG output is always masked to 274 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 5 Registers of 16 bit PPG Timer 16 bit PPG Status Control Register Lower PCNTLO Figure 17 5 6 16 bit PPG Status Control Register Lower PCNTLO bi bib bi2 initial value Add 00434 PCNTLo EGS1 EGSO IREN IRGF IRS1 IRSO OsEL 000000008 RW Rw R WR RM1 W RW RW RW RW OSEL Output inversion bit 0 Normal polarity 1 Inverted polarity POEN Output enable bit 0 General purpose I O port 1 PPGO output pin Interrupt type select bit Trigger software trigger and retrigger by TRGO input Counter borrow Rising edge of PPGO output in polarity or falling edge of PPGO output in inverted polarity Duty match Counter borrow rising edge of PPGO output in normal polarity or falling edge of PPGO output inriverted polarity PPG interrupt flag bit Read Write No PPG interrupt Clears this bit No effect on operation IREN PPG interrupt request enable flag 0 Disables interrupt request 1 PPG interrupt generated Enables interrupt request EGSO Hardware trigger enable bitO 0 The falling edge of TRGO has no effect on operation 1 The operation is started by th
587. to this bit sets it to 0 HWR Hardware reset flag bit This bit is set to 1 to indicate that a reset other than a software reset has occurred When any of bits 2 to 5 is set to 1 therefore this bit is set to 1 as well Otherwise the bit retains the value existing before the reset occurred Read or write access 0 or 1 to this bit sets it to 0 SWR Software reset flag bit This bit is set to 1 to indicate that a software reset has occurred Otherwise the bit retains the value existing before the reset occurred Read or write access 0 or 1 to this bit or a power on reset sets it to O Note Reading the reset source register clears its contents To use the reset source register for calculation therefore you should move the contents of the register to RAM in advance CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 91 CHAPTER 7 RESET 7 2 Reset Source Register RSRR MB951 30 MB Series Status of Reset Source Register Table 7 2 2 Status of Reset Source Register Reset Sources Power on reset low voltage detection reset Software reset Watchdog reset External reset Clock supervisor reset CSVR EXTS WDTR PONR HWR SWR 92 Flag set Previous state saved Undefined This bit is set to 1 to indicate that a clock supervisor reset has occurred Always 0 if there is no clock supervisor option
588. tored in the LIN UART reception data register Transmit control circuit This block consists of a transmit bit counter a transmission start circuit and a transmit parity counter The transmit bit counter counts the transmit data bits and sets a flag in the transmit data register when one data transmission is completed according to the specified data length If the transmit interrupt is enabled at this time a transmit interrupt request is generated The transmit start circuit starts transmission when data is written to the TDR The transmit parity counter generates a parity bit for data to be transmitted if the data is parity checked Transmit shift register The data written to the LIN UART transmit data register TDR is transferred to the transmit shift register and output to the SOT pin during bit shifting LIN UART transmit data register TDR This register sets the transmit data The written data is converted to serial data and output Error detection circuit This circuit detects an error upon completion of reception if any If an error occurs the corresponding error flag is set Oversampling circuit In asynchronous mode the LIN UART oversamples received data for five times to determine the received value by majority The LIN UART stops during operation in synchronous mode Interrupt generation circuit This circuit controls all interrupt factors An interrupt is generated immediately if the corresponding interrupt enable
589. troller The clock controller enables disables clock oscillation enables disables clock supply to the internal circuitry selects the clock source and controls the PLL and frequency divider circuits The clock controller controls the internal clock according to the clock mode standby mode settings and the reset operation The current clock mode selects the internal operating clock and the standby mode selects whether to enable or disable clock oscillation and signal supply The clock controller selects the optimum power consumption and features depending on the combination of clock mode and standby mode Dual clock product have four different source clocks a main clock which is the main oscillation clock divided by two a sub clock which is the sub oscillation clock divided by two a main PLL clock which is the main oscillation clock multiplied by the PLL multiplier and a sub PLL clock which is the sub oscillation clock multiplied by the PLL multiplier Single clock product have two different source clocks a main clock which is the main oscillation clock divided by two and a main PLL clock which is the main oscillation clock multiplied by the PLL multiplier 46 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 1 Overview of Clock Controller E Block Diagram of the Clock Controller Figure 6 1 1 shows the block diagram of the clock controller Figure 6 1 1 Clock Controller Block Diag
590. tructions c ssccseeeeeeeeeeeeeseeaees 517 BRSR UART SIO Dedicated Baud Rate Generator Baud Rate Setting Register BRSRO 352 C Causes Table of Interrupt Causes sese 498 CCR Condition Code Register CCR Configuration 39 Channel Channels of UART SIO eese 315 Channels of UART SIO Dedicated Baud Rate Geerierator 349 Channels Channels of 16 bit PPG Timer 267 Channels of 8 16 bit Compound Timer 201 Channels of 8 16 bit PPG 241 Channels of External Interrupt Circuit 290 Chip erase Erasing All Data from Flash Memory 480 Notes Chip Erase 480 Clock Clock Oscillator Circuit eeesseesss 79 ExternalClock 5 5 52 aae aae eoe euet eec 391 Input Clock imet 200 240 266 Input clock n nent tnn 82 134 148 158 172 314 348 362 430 Operations in Sub Clock Mode Dual clock product 65 Operations in Sub PLL Clock Mode Dual clock product 65 Output Clock sss 82 134 158 348 PLL Clock Oscillation Stabilization Wait Time 53 Reload Value and Baud Rate of Each Clock Speed EM 390 Clock Controller Clock Controlle
591. ts RDRF 1 Reception interrupt Receive Data 1 1 Read data 1 RDRF 1 Reception interrupt Receive Data Read data N Disable reception Handle an error H gt Transmit wake up code 1 Handle an error if it occurs 2 If the FRE or ORE flag is set to 1 write 1 to the SCR CRE bit to clear the error flag f the ESCR LBD bit is set 1 execute the LIN UART reset Note Detect an error in each process and handle it appropriately 416 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 8 Notes on Using LIN UART 22 8 Notes on Using LIN UART This section shows notes on using the LIN UART E Notes on Using LIN UART Enabling operation The LIN UART has the TXE transmission and RXE reception enable bit in the LIN UART serial control register SCR for transmission and reception respectively Since both transmission and reception are disabled by default internal value these operations must be enabled before transfer Also you can disable these operations to stop transfer as required Q Setting communication mode The communication mode must be set while the LIN UART is stopped If the mode is set during transmission reception the transmitted received data is not guaranteed Q Timing of enabling transmit interrupts Since the default initial value of the t
592. ts of PC saved on the stack area are the address of the operation code of the next instruction rather than the address of the operation code of CALLV vct Accordingly Figure E 2 7 shows that the value saved in the stack 12324 and 1233 is 56794 which is the address of the operation code of the instruction that follows CALLV vct return address 512 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E APPENDIX MB95130 MB Series APPENDIX E Instruction Overview Table E 2 1 Vector Table Vector table address Vector use call instruction Upper Lower CALLV 7 CALLV 6 CALLV 5 CALLV 4 CALLV 3 CALLV 2 CALLV 1 CALLV 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 513 APPENDIX APPENDIX E Instruction Overview MB951 30 MB Series E 3 Bit Manipulation Instructions SETB CLRB Some peripheral function registers include bits that are read differently than usual by a bit manipulation instruction E Read modify write Operation By using these bit manipulation instructions you can set only the specified bit in a register or RAM location to 1 SETB or clear to 0 CLRB However as the CPU operates data in 8 bit units the actual operation read modify write operation involves a sequence of steps 8 bit data is read the specified bit is changed and the data is written back to the location at the original address Table E 3 1 shows bus operation for bit manipulation instructions
593. ttings in the system clock control register SYCC Figure 6 7 1 Clock Mode State Transition Diagram Dual Clock Product Reset state 1 2 Main clock oscillation stabilization wait time 7 Main clock mode Main PLL 6 clock mode Main PLL clock 5 oscillation stabiliza tion wait time i 9 Sub clock Sub PLL clock oscillation stabilization wait time Reset occurs in each state 3 11 10 Sub clock oscillation stabilization wait time 4 Main clock oscillation P ES stabilization wait time pex Red stabilization wait time 17 12 1 Oscillation 14 stabilization wait time 1 Sub clock mode Sub PLL 1 clock mode O 66 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 7 Clock Mode Figure 6 7 2 Clock Mode State Transition Diagram Single Clock Product Reset state Main clock oscillation stabilization wait time Main clock mode Reset occurs in each state Main PLL clock mode Main PLL clock oscillation stabiliza tion wait time CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 67 CHAPTER 6 CLOCK CONTROLLER 6 7 Clock Mode MB95130 MB Series Table 6 7 1 Clock Mode State Transition Table 1 2 Current State Next State Description After a reset the device waits for the main clock oscillation stabilization wait time to elapse and enters main clock mode If the reset is a watchdog r
594. uction code from the Normal operation address indicated by reset vector Run state and execute the instruction In the case of a power on reset low voltage detection reset and a reset when in sub clock mode sub PLL clock mode or stop mode the CPU performs mode fetch after the main clock oscillation stabilization wait time has elapsed If the external reset input is not cleared after the oscillation stabilization wait time has elapsed the CPU performs mode fetch after the external reset input is cleared E Effect of Reset on RAM Contents When a reset occurs the CPU halts the operation of the command currently being executed and enters the reset status During RAM access execution however RAM access protection causes an internal reset signal to be generated in synchronization with the machine clock after RAM access has ended This function prevents a word data write operation from being cut off by a reset after one byte 88 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 7 RESET MB95130 MB Series 7 1 Reset Operation E Pin State During a Reset When a reset occurs all of the I O ports and peripheral resource pins remain in a high impedance state until setup is performed by software after the reset is released Note Connect a pull up resistor to those pins which remain at high impedance during a reset to prevent the devices the pins from malfunctioning See APPENDIX D Pin Status of MB95130 MB s
595. ud Rate Interrupt related register Use the following interrupt level setting register to set the interrupt level ae Interrupt level setting register Interrupt vector Reception Interrupt level register ILR1 7 Address 0007Ay Address OFFFCy Interrupt level register ILR2 8 Transmission Address 0007B4 Address OFFEAq CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 425 CHAPTER 22 LIN UART 22 9 Sample Programs of LIN UART MB95130 MB Series How to enable disable clear interrupts Interrupt request enable bit SSR RIE SSR TIE is used to enable interrupts UART reception UART transmission Operation Reception interrupt enable Reception interrupt bit RIE enable bit TIE To disable interrupt requests Set to 0 To enable interrupt requests Set to 1 The following setting is used to clear interrupt requests Operation UART reception UART transmission The reception data register full RDRF is cleared by reading the LIN UART serial The transmit data register To clear interrupt input register RDR empty TDRE is set to 0 requests The error flags PE ORE FRE are set to by writing data to the serial 0 by writing 1 to the error flag clear output data register TDR bit CRE 426 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 23 8 10 BIT A D CONVERTER This chapter describes the functions and operations of the 8 10 bit A D convert
596. ue ILRO Interrupt level setting register 0 ILRI Interrupt level setting register 1 ILR2 Interrupt level setting register 2 ILR3 Interrupt level setting register 3 ILR4 Interrupt level setting register 4 ILR5 Interrupt level setting register 5 Prohibited WRARHO Wild register address setup register upper ch 0 WRARLO Wild register address setup register lower ch 0 WRDRO Wild register data setup register ch 0 WRARHI Wild register address setup register upper ch 1 WRARLI Wild register address setup register lower ch 1 WRDRI Wild register data setup register ch 1 WRARH2 Wild register address setup register upper ch 2 WRARL2 Wild register address setup register lower ch 2 WRDR2 Wild register data setup register ch 2 Prohibited TOICRO 8 16 bit compound timer 01 control status register 0 ch 0 TOOCRO 8 16 bit compound timer 00 control status register 0 ch 0 TOIDR 8 16 bit compound timer 01 data register ch 0 TOODR 8 16 bit compound timer 00 data register ch 0 TMCRO 8 16 bit compound timer 00 01 timer mode control register ch 0 Prohibited 8 16 bit PPGO1 cycle setting buffer register ch 0 8 16 bit PPGOO cycle setting buffer register ch 0 8 16 bit PPGO1 duty setting buffer register ch 0 8 16 bit PPGOO duty setting buffer register ch 0 Pro
597. ue OF88j RD7 RD6 RD5 RD4 RD3 RD2 RD1 RDO 00000000pg RAV RW RW RW RW RW RW RW R W Readable writable Read value is the same as write value Table 14 3 2 Functional Description of Each Bit of Wild Register Data Setup Register WRDRO to WRDR2 Bit name Function These bits specify the data to be amended by the wild register function These bits are used to set the amendment data at the address assigned by the wild register address setup register WRAR Data is enabled at the address corresponding to each wild register number RD7 to RDO Wild registers data setup bits Read access of these bits is enabled only when the corresponding data test setting bit in the wild register data test setup register WROR is set to 1 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 189 CHAPTER 14 WILD REGISTER 14 3 Registers of Wild Register MB95130 MB Series 14 3 2 Wild Register Address Setup Registers WRARO to WRAR2 The wild register address setup registers WRARO to WRAR2 set the address to be amended by the wild register function Bi Wild Register Address Setup Registers WRARO WRAR2 Figure 14 3 3 Wild Register Address Setup Registers WRARO to WRAR2 WRARO Address bitlb bitl4 bit12 biti
598. ue is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write RMW instruction ROW Write only Writable 0 is read RO WX Undefined bit Read value is 0 writing has no effect on operation Undefined Initial value 160 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 12 WATCH PRESCALER 12 3 Registers of the Watch Prescaler MB95130 MB Series Table 12 3 1 Functional Description of Each Bit of Watch Prescaler Control Register WPCR Bit name Function WTIF Watch interrupt request flag bit This bit becomes 1 when the selected interval time of the watch prescaler has elapsed nterrupt requests are generated when this bit and the interrupt request enable bit WTIE are set to 1 Writing 0 sets this bit to 0 Writing 1 ignored and has no effect on the operation 1 is always read in read modify write RMW instruction WTIE Interrupt request enable bit This bit enables disables output of interrupt requests to the interrupt controller Writing 0 disables the interrupt request output of the watch prescaler Writing 1 enables the interrupt request output of the watch prescaler Interrupt requests are outputted when this bit and the watch interrupt request flag bit are set to 1 Undefined bits These bits are undefined The read value is always 0 Writing has no effec
599. ult and the 16 bit remainder in A and T respectively When the value in A before execution of instruction is 0 the Z flag becomes 1 to indicate zero division is executed The instruction does not change other flags and therefore care must be taken when a branch may occur depending on the result of a division Figure E 2 4 shows a summary of the instruction Figure E 2 4 DIVUA Before executing After executing A 1234H A 0004H T 5678H ODA8H XCHWA PC This instruction swaps the contents of A and PC resulting in a branch to the address contained in A before execution of the instruction After the instruction is executed A becomes the address that follows the address where the operation code of XCHW A PC is stored This instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine Figure E 2 5 shows a summary of the instruction Figure E 2 5 XCHW A PC Before executing After executing A 5678H E dh A 1235H 1234H 5678 When this instruction is executed the content of A reaches the same value as the address where the following instruction is stored rather than the address where operation code of this instruction is stored Therefore in Figure E 2 5 the value 1235 stored in A corresponds to the address where the following op
600. up registers WRDR wild register address setup registers WRAR wild register address compare enable register WREN and wild register data test setup register WROR The wild register function is used to specify the addresses and data that need to be replaced The wild register address compare enable register WREN enables the wild register function for each wild register data setup register WRDR Moreover the wild register data test setup register WROR enables the normal read function for each wild register data setup register WRDR Control circuit block This circuit compares the actual address data with addresses set in the wild register address setup registers WRDR and if the values match outputs the data from the wild register data setup register WRDR to the data bus The control circuit block uses the wild register address compare enable register WREN to control the operation 186 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 14 WILD REGISTER MB95130 MB Series 14 3 Registers of Wild Register 14 3 Registers of Wild Register The registers of the wild register include the wild register data setup registers WRDR wild register address setup registers WRAR wild register address compare enable register WREN and wild register data test setup register WROR E Registers Related to Wild Register Figure 14 3 1 Registers Related to Wild Register Wild register data setup registers WRDRO to WRD
601. upon detection of a count end edge B Input Capture Function When the input capture function is selected the counter value is stored in a register upon detection of an edge for an external input signal This function is available in either free run mode or clear mode for count operation In the clear mode the counter starts counting from 00g and transfers its value to a register to generate an interrupt upon detection of an edge In this case the counter continues to count from 00g In the free run mode the counter transfers its value to a register to generate an interrupt upon detection of an edge In this case however the counter continues to count without being cleared CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 197 CHAPTER 15 8 16 BIT COMPOUND TIMER 15 2 Configuration of 8 16 bit Compound Timer MB951 30 MB Series 15 2 Configuration of 8 16 bit Compound Timer The 8 16 bit compound timer consists of the following blocks 8 bit counter x 2 channels 8 bit comparator including a temporary latch x 2 channels 8 16 bit compound timer 00 01 data register x 2 channels TOODR TO1DR 8 16 bit compound timer 00 01 control status register 0 x 2 channels TOOCRO TO1CRO 8 16 bit compound timer 00 01 control status register 1 x 2 channels TOOCR1 TO1CR1 8 16 bit compound timer 00 01 timer mode control register TMCRO Output controller x 2 channels Control logic x 2 channels Count clock selector x 2 channels Edge
602. upply is required for serial programming CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 487 CHAPTER 27 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 27 2 Example of Serial Programming Connection MB95130 MB Series Figure 27 2 1 Example of Serial Programming Connection for Flash Memory Products AF220 AF210 AF120 AF110 flash microcontroller programmer i Flash DX10 288 ash memory products P13 TAUX3 19 MOD gt 4 7kQ 1 L1 I a 5 TTXD L 4 13 P10 UIO TRXD 27 P UOO qu TCK 17 6 t P12 UCKO gt inu TICS 10 T User circuit me gt A7kKQ E i 109 pa PST User gt 4 7kQ TVcc m 2 Vcc i user power supply 7 8 GND 14 15 Vss 21 22 1 28 e Pin 14 Pin 1 Pins 3 4 9 11 12 16 17 18 7 20 23 24 25 26 are Open DX10 28S Pin 28 Pin 15 User system Die eto angie Connector manufactured by Hirose Electric Co Ltd pin alignment 488 The circuit 1 shown in Figure 27 2 1 is required if you want to disconnect the UCKO and RST pins from the user circuit during serial programming The TICS signal of the flash microcontroller programmer outputs low during serial writing and this disconnects the user circuit If it is not necessary to disconnect from the user circuit the
603. ure Example 296 18 8 Notes on Using External Interrupt Circuit enne enne 298 18 9 Sample Programs for External Interrupt Circuit sse 299 CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT cernere 301 19 1 Overview of Interrupt Pin Selection Circuit 302 19 2 Configuration of Interrupt Pin Selection Circuit 303 19 3 Pins of Interrupt Pin Selection Circuit nennen nri 304 19 4 Registers of Interrupt Pin Selection Circuit 305 19 4 1 Interrupt Pin Selection Circuit Control Register WICR sese 306 19 5 Operating Description of Interrupt Pin Selection Circuit 309 19 6 Notes on Using Interrupt Pin Selection Circuit 310 CHAPTER 20 UART SI 5 2 i xe cu rere rer rapa pau Faux nous eaaa aanerer aka 311 204 OverviewoT UART SIQO ice eet th eco eee xh cM esae et cri dee o det i bed Ede 312 20 2 Configuration of UART SIO sssssssssssseeeeeeen nnne 313 20 3 Channels of UART SIO sete nei e Ee ape c ee uae anand ge do 315 20 4 2 Pins of DART SIQ eter ned o deer eed dbase e Tues 316 20 5 Registers oFUART SIQ 25 ue eave cnet eg rait De inn dee ue var ue to o dae Prud ec E do a ee ieee 318 20 5 1 UART SIO Ser
604. used The LIN synch break detection works only in operation mode 3 Figure 22 7 8 shows the LIN UART operation in LIN slave modes 406 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 22 LIN UART MB95130 MB Series 22 7 Operations and Setup Procedure Example of LIN UART Figure 22 7 8 LIN UART Operation in LIN Slave Modes Serial clock cycles 0123456 7 8 9101112131415 Serial cee nnnnnnnnnnnnnnnnnnnnmnnr Serial input LIN bus FRE RXE 1 LBD RXE 0 Reception interrupt generated when RXW 1 Reception interrupt generated when RXW 0 LIN bus timing Figure 22 7 9 LIN Bus Timing and LIN UART Signals No clock Previous serial clock Calculation frame Newly calculated serial clock UUU 8 16 bit compound timer count in TIIO input LSYN IRQ TIIO RDRF IRQO RDR read by CPU Ji Reception interrupt enable LIN break e LIN breakdetected interrupt generated IRQ clear by CPU LBD gt 0 IRQ 8 16 bit compound timer IRQ clear input capture of 8 16 bit compound timer count starts IRQ 8 16 bit compound timer IRQ clear Baud rate calculated and set LBIE disabled Enable reception Falling edge of start bit 1 byte of reception data saved to RDR
605. uts bit6 DATA 6 of the value read from the read address at each read access 474 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 26 256 Kbit FLASH MEMORY MB95130 MB Series 26 5 Checking the Automatic Algorithm Execution Status 26 5 3 Execution Time out Flag DQ5 The execution time out flag DQ5 is a hardware sequence flag indicating that the automatic algorithm has been executed beyond the specified time required for programming erasing internal to the flash memory E Execution Time out Flag 005 Table 26 5 7 and Table 26 5 8 show the state transition of the execution time out flag Table 26 5 7 State Transition of Execution Time out Flag During Normal Operation Chip erase Erasing completed Programming gt Programming completed Operating state Table 26 5 8 State Transition of Execution Time out Flag During Abnormal Operation bas At programming and chip erasing When read access is made with the write or chip erase automatic algorithm invoked the flag outputs 0 when the algorithm execution time is within the specified time required for programming erasing or 1 when it exceeds that time The execution time out flag DQ5 can be used to check whether programming erasing has succeeded or failed regardless of whether the automatic algorithm has been running or terminated When the execution time out flag DQ5 outputs 1 it indicates that programming has failed if the automatic algor
606. vice to enter watch mode if the system clock monitor bits in the system clock control register SYCC SCM1 SCMO are 00 or 01g The device can enter watch mode only when the clock mode is sub clock mode or sub PLL clock mode Upon transition to watch mode the states of external pins are retained when the pin state setting bit in the standby control register STBC SPL is 0 and the states of external pins become high impedance when that bit is 1 those pins are pulled up for which pull up resistor connection has been selected in the pull up setting register Cancellation of watch mode The device is released from watch mode in response to a reset watch interrupt or external interrupt Note When watch mode is canceled via an interrupt peripheral resources placed into watch mode during an action resume that action Therefore the initial interval time of the interval timer and other similar settings are rendered indeterminate After recovery from watch mode initialize each peripheral resource as necessary 78 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB95130 MB Series 6 9 Clock Oscillator Circuits 6 9 Clock Oscillator Circuits The clock oscillator circuit generates an internal clock with an oscillator connected to or a clock signal input to the clock oscillation pin B Clock Oscillator Circuit Using crystal and ceramic oscillators Connect crystal and ceramic oscillator
607. watch prescaler before entering stop mode in sub clock mode or sub PLL clock mode Cancellation of stop mode The device is released from stop mode in response to a reset or an external interrupt In main clock mode or main PLL clock mode you can start or stop sub clock oscillation by setting the sub clock oscillation stop bit in the system clock control register SYCC SUBS When the sub clock is oscillating you can also release the device from stop mode using an interrupt by the watch prescaler or watch counter Note When stop mode is canceled via an interrupt peripheral resources placed into stop mode during an action resume that action Therefore the initial interval time of the interval timer and other similar settings are rendered indeterminate After recovery from stop mode initialize each peripheral resource as necessary 76 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 6 CLOCK CONTROLLER MB951 30 MB Series 6 8 Operations in Low power Consumption Modes Standby 6 8 4 Modes Time base Timer Mode Time base timer mode allows only the main clock oscillation sub clock oscillation time base timer and watch prescaler to work The operating clock for the CPU and peripheral resources is stopped in this mode E Operations in Time base Timer Mode In time base timer mode main clock supply is stopped except for the time base timer The device stops all the functions except time base timer exter
608. with count clock The output changes back to L when the H was output until the value of duty setting The output levels will be reversed if OSEL is set to 1 When the retrigger function is disabled RTRG 0 software triggers STRG 1 are ignored during the operation of the down counter When the down counter is not running the maximum time between a valid trigger input occurring and the down counter starting is as follows Software trigger 1count clock cycle 2 machine clock cycles Hardware trigger by TRGO Pin input 1 count clock cycle 3 machine clock cycles The minimum time is as follows Software trigger 2 machine clock cycles Hardware trigger by TRGO Pin input 3 machine clock cycles When the down counter is running the maximum time between a valid retrigger input occurring and the down counter restarting is as follows Software trigger 1 count clock cycle 2 machine clock cycles Hardware trigger by TRGO Pin input 1 count clock cycle 3 machine clock cycles The minimum time is as follows Software trigger 2 machine clock cycles Hardware trigger by TRGO Pin input 3 machine clock cycles 278 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 17 16 BIT PPG TIMER MB95130 MB Series 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example invalidating the retrigger RTRG of PCNTHO register bit 4 0 Figure 17 7 1 When Retrigger Is Invalid in PWM Mode 16 bit down counter va
609. write value Interval timer function The 8 16 bit compound timer 00 01 data register TOODR TO1DR is used to set the interval time When the timer starts operation TOOCR1 TO1CRI STA 1 the value of this register is transferred to the latch in the 8 bit comparator and the counter starts counting When the count value matches the value held in the latch in the 8 bit comparator the value of this register is transferred again to the latch and the count value is reset to to continue to count The current count value can be read from this register An attempt to write 00g to this register is disabled in interval timer function In 16 bit operation set the upper data to TOIDR and lower data to TOODR And write and read TO1DR and TOODR in this order PWM timer functions fixed cycle The 8 16 bit compound timer 00 01 data register TOODR TOIDR is used to set pulse width time When the timer starts operation TOOCR1 TO1CRI1 STA 1 the value of this register is transferred to the latch in the 8 bit comparator and the counter starts counting from timer output H When the count value matches the value held in the latch the timer output becomes L and the counter continues to count until the count value reaches When an overflow occurs the value of this register is transferred again to the latch in the 8 bit comparator and the counter performs the next cycle of counting T
610. x 0 0 0 0 X X x 0 Mode 2 X x x x 0 x 0 Used bit X Unused bit 1 Setto 1 0 Setto 0 Used when SSM 1 Synchronous star stop bit mode Bit correctly set automatically Inter CPU connection For bi directional communication interconnect two CPUs as shown in Figure 22 7 11 Figure 22 7 11 Connection Example of Bi directional Communication in LIN UART Mode 2 CPU 1 Sending side of serial clock CPU 2 Receiving side of serial clock CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 409 CHAPTER 22 LIN UART 22 7 Operations and Setup Procedure Example of LIN UART MB951 30 MB Series Communication procedure example The communication is started from transmitting end at arbitrary timing when data is ready to be transmitted When transmission data is received in the receiving side ANS 1 byte in the example is returned on a regular basis Figure 22 7 12 shows an example of bi directional communication flowchart Figure 22 7 12 Example of Bi directional Communication Flowchart Master Slave Set operation mode match with the transmitting end side Has received data YES Read and process received data Set operation mode 0 or 2 Data transmission ommunicate with one byte data set in TDR NO Has received data NO YES Data transmission Read and process received Transmit one byte data data ANS
611. xternal interrupt circuit il Operation of External Interrupt Circuit When the polarity of an edge of a signal inputted from one of the external interrupt pins INTOO INTO1 matches the polarity of the edge selected by the external interrupt control register EIC 51 00 SLO1 SL10 5111 the corresponding external interrupt request flag bit EIC EIRO EIR1 is set to 1 and the interrupt request is generated Always set the interrupt enable bit to 0 when not using an external interrupt to recover from a standby mode When setting the edge polarity select bit SL set the interrupt request enable bit EIE to 0 to prevent the interrupt request from being generated accidentally Also clear the interrupt request flag bit EIR to 0 after changing the edge polarity Figure 18 7 1 shows the operation for setting the INTOO pin as an external interrupt input Figure 18 7 1 Operation of External Interrupt Input waveform to INTOO pin v V Cleared by Interrupt request flag bit cleared program by program EIRO bit EIEO bit 5101 bit SLOO bit IRQ No edge Rising edge Falling edge Both edges detection 296 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 18 EXTERNAL INTERRUPT CIRCUIT MB95130 MB Series 18 7 Explanation of External Interrupt Circuit Operations and Setup Procedure Example E Setup Procedure Example The external interrupt c
612. xternal interrupt pins 302 FUJITSU MICROELECTRONICS LIMITED CM26 10118 3E CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT MB95130 MB Series 19 2 Configuration of Interrupt Pin Selection Circuit 19 2 Configuration of Interrupt Pin Selection Circuit Figure 19 2 1 shows the block diagram of the interrupt pin selection circuit E Block Diagram of Interrupt Pin Selection Circuit Figure 19 2 1 Block Diagram of Interrupt Pin Selection Circuit To each peripheral function External INTO1 interrupt Pin circui INTO1 Interrupt pin selection circuit _ INTOO Pin TRGO ADTG 5 E 2 Pin E 2 vio INTOO E Unit 0 2 ECO m Pin Sees seca M Lp opp eL WICR register WICR register interrupt pin selection circuit control register This register is used to determine which of the available peripheral input pins should be outputted to the interrupt circuit and which interrupt pins they should serve as Selection circuit This circuit outputs the input from the pin selected by the WICR register to the INTOO input of the external interrupt circuit ch 0 CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 303 CHAPTER 19 INTERRUPT PIN SELECTION CIRCUIT 19 3 Pins of Interrupt Pin Selection Circuit 19 3 Pins of Interrupt Pin Selection Circuit MB95130 MB Series This section describes the pins of the interrupt pin selection circuit E Pins Related to In
613. y Normal mode 7 bits or 8 bits Asynchronous 7 bits Multi r processor 8 bits Asynchronous LSB first mode 1 MSB first Normal mode Synchronous LIN mode Asynchronous LSB first Unavailable 1 is the address data selection bit AD used for communication control in multiprocessor mode The MDO and MD bits in the LIN UART serial mode register SMR are used to select the following LIN UART operation modes Table 22 1 3 LIN UART Operation Modes 0 0 0 Asynchronous Normal mode 0 1 1 Asynchronous Multiprocessor mode 1 0 2 Synchronous Normal mode 1 1 3 Asynchronous LIN mode Mode 1 supports both master and slave operation for the multiprocessor mode Mode 3 is fixed to communication format 8 bit data no parity 1 stop bit LSB first CM26 10118 3E FUJITSU MICROELECTRONICS LIMITED 357 CHAPTER 22 LIN UART 22 2 Configuration of LIN UART MB95130 MB Series 22 2 Configuration of LIN UART LIN UART is made up of the following blocks Reload Counter Reception control circuit Reception shift register LIN UART reception data register RDR Transmit control circuit Transmit shift register LIN UART transmit data register TDR Error detection circuit Oversampling circuit Interrupt generation circuit LIN synch break Synch Field detection circuit Bus idle detection circuit LIN UART serial control register SCR LIN UART serial mode regist
614. y divided by two Note that a 1IMHz or higher oscillator frequency must be input when performing serial writing Oscillation pins Reset pin Setting P10 UI0 Low specifies that serial write mode uses clock synchronous communications As this low input is P10 UIO Serial data input pin handled by the TTXD pin of the flash microcontroller programmer you do not need to provide a pull down for the P10 UI0 pin P11 UOO0 Serial data output pin Setting P12 UCKO High sets serial write mode As this high input is handled by the TCK pin of the flash microcontroller programmer you do not need to provide a pull up for the P12 UCKO pin P12 UCKO Serial clock input pin On the 5 V products the write voltage Vcc 4 5V to 5 5V is Powersupply VOLABSSSUSDI pii supplied from the user system GND pin Common to the GND of the flash microcontroller programmer As the UIO UOO and UCKO pins are also used by the user system you need to provide a control circuit as shown in Figure 27 1 2 if you want to disconnect from the user circuit during serial programming The TICS signal of the flash microcontroller programmer can be used to disconnect from the user circuit during serial writing See the connection example in Figure 27 1 2 for details Figure 27 1 2 Control Circuit AF220 AF210 AF120 AF110 programming control pin Flash memory products programming 2 4 7kQ control pin AF220 AF210 AF120 AF

F2MC-8FX MB95130/MB Series HARDWARE MANUAL

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