DE0 User Manual
Contents
1. Chapter 5 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DEO board These circuits provide demonstrations of the major features on the board such as its video capabilities and SD card storage For each demonstration the Cyclone III FPGA or EPCS4 serial EEPROM configuration file is provided as well as the full source code in Verilog HDL code All of the associated files can be found in the DENdemonstrations folder from the DEO System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the DEO_demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory DEO_demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 5 1 DEO Factory Configuration The DEO board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions e Project directory DEO_Default e Bit stream used DEO_Default sof or DEO_Default pof e Power on the DEO board with the USB cable2. 72 Cyclone III I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives 7 AND 272 DEO User Manual 2 3 Power up the DEO Board The DEO board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board is working properly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DEO board For communication between the host and the DEO board it is necessary to install the Altera USB Blaster driver software If this driver is not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DEO Board This tutorial is available in the directory DENDEO user manual on the DEO System CD ROM 2 Connect the 7 5V adapter to the DEO board 3 Connect a VGA monitor to the VGA port on the DEO board 4 Turn the RUN PROG switch on the left edge of the DEO board to RUN position the PROG position is used only for the AS Mode programming 5 Turn the power on by pressing the ON OFF switch on the DEO board At this point you should observe the following e All user LEDs are flashing e All 7 segment displays are cycling through the numbers 0 to F e The VGA monitor displays the
3. BUTTONO 2 AN H2 BUTTON1 7486245 A A A G3 Cyclone HI BUTTON2 21 ANA F1 Figure 4 5 Connections between the pushbutton and Cyclone III FPGA b depressed p released Before Debouncing LPL LL L L L Schmitt Trigger Debounced Figure 4 6 Switch debouncing Cyclone HI D2 E4 E3 H7 J7 G5 G4 H6 H5 J6 H m m m m m m m E SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SVVO Logic 0 Figure 4 7 Connections between the toggle switches and Cyclone III FPGA 24 DEO User Manual Cyclone HI J1 J2 J3 H1 F2 E1 C1 C2 B2 B1 LEDGO LEDGO LEDG1 LEDG1 LEDG2 LEDG2 M LEDG3 LEDG3 LEDG4 LEDG5 LEDG6 LEDG7 LEDG8 LEDG8 LEDG9 LEDG9 223232232211 Figure 4 8 Connections between the LEDs and Cyclone III FPGA Table 4 1 Pin assignments for the slide switches EEE ee SW 0 PIN_J6 Slide Switch 0 SW 1 PIN H5 Slide Switch 1 SW 2 PIN_H6 Slide Switch 2 SW 3 PIN G4 Slide Switch 3 SWI4 PIN G5 Slide Switch 4 SWISI PIN J7 Slide Switch 5 SWI6 PIN H7 Slide Switch 6 SWI7 PIN E3 Slide Switch 7 SW 8 PIN_E4 Slide Switch 8 SWI9 PIN_D2 Slide Switch 9 Table 4 2 Pin assignments for the pushbutton switches BUTTON 0 PIN H2
4. www terasic com DEO User Manual Development and Education Board Altera DEO Board Chapter 1 DEO Package an ea ma mn man ka aman 1 1 1 bl 1 1 Whe DBU Board 2 Getme Hm an 2 Chapter 2 Altera DEO Board nn 4 2 1 Layout and Components aa 4 22 Block Diagram of the DEO nan lak laa 3 2 3 Powerup th DEU Board nan nn a ea 8 Chapter 3 DEO Control Panel eno aa anna aunaa 10 3 1 Control Panel Setup ann ac aa donu ga ies 10 3 2 Controlling the LEDs and 7 Segment Displays aaa 12 3 3 Switches and BUttONS Ro 14 34 SDRAM and Flash Controller and Programmer 15 3 5 100000 Cp E Dd be 16 360 SDCARD te ocd cT 17 VERG v MR 18 Chapter 4 Using the DEO Board soo 20 4 1 Configuring the Cyclone HI FPGA eka ntah kam 20 T2 Using the LEDs and ylicieh kamu dieu 23 4 3 Using the 7 segment DisplayS eng Bagus 26 44 Clock Ei e 28 4 5 Using th LCD esr mann ema mlam was 29 46 Using the Expansion Header os san mksh 31 4 7 Using VGA o E 34 4 8 RS 232 Serial PORE ose pian ete a udo pan nee 37 4 9 PS 2 Serial Portu 38 4 10 SD Card Soket LETT TN 39 All Using SDRAM and Flash Rc 39 Chapter 5 Examples of Advanced Demonstrations sense 44 5 1 DEO Factory Monumen aa
5. AB15 GPIOO D5 AB14 GPIOO D7 AA13 GND GPIOO D9 AA10 GPIOO D11 AA GPIOO 013 AA5 GPIOO D14 AB4 GPIOO 015 AA4 GPIOO 017 U14 GPIOO D19 W13 GPIOO 021 V12 GND GPIOO D23 V11 GP100 D25 W10 GPIOO D27 V8 GPIOO D29 W6 GPIOO D31 U7 AB11 GPIO1 CLKINO AA11 GPIO1 CLKIN1 AA19 GPIO1 D2 AB18 GPIO1 D4 AA17 GPIO1 D6 5V Y17 GPIO1_D8 U15 GPIO1 D10 W15 GPIO1 D12 R16 GPIO1 CLKOUTO 19 T16 GPIO1 CLKOUT1 AA7 GPIO1 D16 T14 GPIO1 D18 U12 GPIO1 D20 3 3V R11 GPIO1 D22 U10 GPIO1 D24 U9 GPIO1 D26 Y7 GPIO1 D28 V6 GPIO1 D30 GPIO 1 J5 21 Figure 4 14 I O distribution of the expansion headers Table 4 8 Pin assignments for the expansion headers GPIOO D 0 PIN AB16 GPIO Connection 0 IO 0 GPIOO D 1 PIN AA16 GPIO Connection 0 IO 1 GPIOO D 2 PIN AA15 GPIO Connection 0 IO 2 GPIOO D 3 PIN AB15 GPIO Connection 0 IO 3 GPIOO 014 PIN AA14 GPIO Connection 0 IO 4 GPIOO D 5 PIN AB14 GPIO Connection 0 IO 5 GPIOO D 6 PIN AB13 GPIO Connection 0 IO 6 GPIOO 017 PIN AA13 GPIO Connection 0 IO 7 GPIOO_D 8 PIN AB10 GPIO Connection 0 IO 8 GPIOO D 9 PIN AA10 GPIO Connection 0 IO 9 GPIOO D 10 PIN AB8 GPIO Connection 0 IO 10 GPIOO D 11 PIN AA8 GPIO Connection 0 IO 11 GPIOO D 12 PIN AB5 GPIO Connection 0 IO 12 GPIOO D 13 PIN AA5 GPIO Connection 0 IO 13 GPIO0 D 14 PIN AB4 GPIO Connect
6. 3 PIN_B19 Seven Segment Digit 3 3 HEX3_D 4 PIN_C19 Seven Segment Digit 3 4 HEX3 D 5 PIN D19 Seven Segment Digit 3 5 HEX3 D 6 PIN G15 Seven Segment Digit 3 6 HEX3 DP PIN G16 Seven Segment Decimal Point 3 4 4 Clock Circuitry The DEO board includes a 50 MHz clock signals This clock signal is connected to the FPGA that are used for clocking the user logic In addition all these clock inputs are connected to the phase lock loops PLL clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit The clock distribution on the DEO board is shown in Figure 4 11 The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 4 5 GPIO 0 J4 CLK12 AB12 CLK13 AA12 PLL1 CLKOUTn AB3 PLL1 CLKOUTp AA3 G21 CLK4 Cyclone III CLOCK 50 2 B12 CLK9 GPIO 1 J5 CLK14 AB11 CLK15 AA11 PLL4 CLKOUTn pepe GPIO1 CLKOUT1 PLL4 CLKOUTp T16 Figure 4 11 Block diagram of the clock distribution 28 AND S 272 DEO User Manual Table 4 5 Pin assignments for the clock inputs CLOCK 50 PIN G21 50 MHz clock input CLOCK 50 2 PIN B12 50 MHz clock input 4 5 Using the LCD Module The DEO board provides a 2x16 LCD interface In order to use the LCD interface users are required to solder a LCD module onto the DEO board shown in Figure 4 12 The detailed component reference is listed in Table 4 6 Also users
7. 5 LCD DATA 6 PIN D20 LCD Data 6 LCD DATA T PIN C20 LCD Data 7 LCD RW PIN E22 LCD Read Write Select 0 Write 1 Read LCD EN PIN E21 LCD Enable LCD RS PIN F22 LCD Command Data Select 0 Command 1 Data LCD BLON PIN F21 LCD Back Light ON OFF Note that some LCD modules do not have backlight Therefore the LCD BLON signal should not be used in users design projects 4 6 Using the Expansion Header The DEO Board provides two 40 pin expansion headers Each header connects directly to 36 pins of the Cyclone III FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Among these 36 I O pins 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA Finally Figure 4 14 shows the related schematics The figure shows the protection circuitry for only two of the pins on each header but this circuitry is included for all 72 data pins Table 4 8 gives the pin assignments 31 DEO User Manual AB12 GPIOO CLKINO AA12 GPIOO CLKIN1 AA15 GPIOO D2 AA14 GPIOO D4 AB13 GPIOO D6 5V AB10 GPIOO D8 AB8 GPIOO D10 AB5 GPIOO D12 AB3 GPIO0 CLKOUTO 19 AA3 GPIO0 1 1 21 V14 GPIOO D16 Y13 GPIOO_D18 U13 GPIOO D20 3 3V R10 GPIOO_D22 Y10 GPIO0 D24 T8 GPIOO_D26 W7 GPlO0 D28 V5 GPIO0 D30 GPIO 0 J4 GPIOO DO AB16 GPIOO D1 AA16 GP100 D3
8. Pushbutton 0 BUTTON 1 PIN G3 Pushbutton 1 BUTTON 2 PIN F1 Pushbutton 2 25 AND S 272 DEO User Manual Table 4 3 Pin assignments for the LEDs LEDG 0 PIN J1 LED Greenl01 LEDG 1 PIN J2 LED Green 1 LEDG 2 PIN_J3 LED Greenl21 LEDG 3 PIN_H1 LED Green 3 LEDG 4 PIN_F2 LED Greenl41 LEDG 5 PIN E1 LED Green 5 LEDG 6 PIN_C1 LED Greenl61 LEDG 7 PIN_C2 LED Green 7 LEDG 8 PIN_B2 LED Green 8 LEDG 9 PIN_B1 LED Green 9 4 3 Using the 7 segment Displays The DEO board has four 7 segment displays These displays are arranged into two pairs and a group of four with the intent of displaying numbers of various sizes As indicated in Figure 4 9 the seven segments are connected to pins on the Cyclone III FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 4 10 In addition the decimal point is identified as DP Table 4 4 shows the connections between the FPGA pins to the 7 segment displays HEXO DO HEXO DO quum HEXO D1 E HEXO D2 H12 HEXO D5 HEXO D1 HEXO D3 H13 HEXO D6 D Cyclone HEXO D4 HEXO D4 HEX0 D2 HEXO D5 ba HEXO D6 i EE HEXO DP HEXO D3 DP i D13 Figure 4 9 Connections between the 7 segment displays and Cyclone III FPGA 26 DEO User Manual 2
9. Write Success Figure 3 7 Accessing the SDRAM A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 7 depicts the result of writing the hexadecimal value Teff into location 000000 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing of data click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner 15 AND amp 274 DEO User Manual The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789ABCDEF defines four 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively into the memory The Sequential Read function is used to rea
10. as a short reference The DEO board contains a serial EEPROM chip that stores configuration data for the Cyclone III FPGA This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it is possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone III FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration is lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS4 serial EEPROM chip It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DEO board is turned off When the board s power is turned on the configuration data in the EPCS4 device is automatically loaded into the Cyclone III FPGA The sections below describe the steps used to perform both JTAG and AS programming For both methods the DEO board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer a
11. can buy this module from Terasic website http de0 terasic com Table 4 6 The listed information on the LCD module J2 2x16 LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller which is called HD44780 Detailed information for using the display is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet LCD folder on the DEO System CD ROM A schematic diagram of the LCD module showing connections to the Cyclone III FPGA is given in Figure 4 13 The associated pin assignments appear in Table 4 7 29 N DTE YA DEO User Manual 2 X 16 LCD Module sla kii l k m a f r T L AERAN Le UNIVERSITY T 7 m PROGRAM Figure 4 12 LCD module on DEO board Cyclone F21 D22 D21 C22 C21 B22 B21 D20 C20 E21 F22 E22 NO18 427 a91 IVIVd 427 evlvd 4971 evivd a91 rviva a91 MH a91 9gviva a91 sviva a91 21 1 0 a91 NI 421 SH a91 Figure 4 13 Connections between the LCD module and Cyclone III FPGA 30 JAN DTE RYAN DEO User Manual Table 4 7 Pin assignments for the LCD module LCD DATA 0 PIN D22 LCD Data 0 LCD DATA 1 PIN D21 LCD Data 1 LCD DATA 2 PIN C22 LCD Data 2 LCD PIN C21 LCD Data 3 LCD DATA 4 PIN B22 LCD Data 4 LCD DATAJSI PIN B21 LCD Data
12. image shown in Figure 2 3 DEO User Manual Figure 2 3 The default VGA output pattern 44 amp 274 DEO User Manual Chapter 3 DEO Control Panel The DEO board comes with a Control Panel facility that allows users to access various components on the board from a host computer The host computer communicates with the board through an USB connection The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel Software Utility is located in the DEO Control panel folder in the DEO System CD ROM To install it just copy the whole folder to your host computer To activate the Control Panel perform the following steps 1 Make sure Quartus II and USB Blaster Driver are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 7 5 V power supply and turn the power switch ON 3 Setthe RUN PROG switch to the RUN position Start the executable DEO ControlPanel exe on the host computer The Control Panel user interface shown in Figure 3 1 will appear When the control panel window appears it will automatically download the bit stream file sof into the FPGA If any error message shows up as shown in Figur
13. time Press Stop to terminate the monitoring process 16 INDE RYAN DEO User Manual LED 7 SEG Buton Memory PS2 SD CARD VGA ps2 Keyboard Product Name DEO JAN DTE RYAN UNIVERSITY PROGRAM ij as c WWW Cerasic com About Disconnect Exit Connected SDRAM Random Write Success Figure 3 8 Reading the PS2 Keyboards 3 6 SD CARD The function is designed to read the identification and specification of the SD card The I bit SD MODE is used to access the SD card This function can be used to verify the functionality of SD CARD Interface Follow the steps below to exercise the SD card 1 Choosing the SD CARD tab leads to the window in Figure 3 9 2 Insert a SD card to the DEO board then press the Read button to read the SD card The SD card s identification and specification will be displayed in the control window 17 DEO User Manual LED 7 SEG Button Memory PS2 SD CARD vGA SD CARD SD CARD Identification Manufacturer ID 3Eh OEM Application ID 2D48h Product Name Product Revision OOh Serial No 00002D26h Date Code 08Bh SD CARD Specification CSD Version No 1 0 Read Access Time 20 ms Product Name DEO Read Access Time NSAC 1 x100 cycle Max Data Transfer Rate 25 Mbits s Max Read Data Block Length 512 Byte N DTE RYAN Memory Capacity 957 MB UNIVERSITY Read PROGRAM ijasic WWW Lerasic COM About Dis
14. 4 10 Clock Circuitry pin assignment Corrected V1 4 SD card demonstration setup corrected V1 5 Add debounced circuit description 6 2 Copyright Statement Copyright O 2011 Terasic Technologies All rights reserved 53
15. DP 3 Figure 4 10 Position and index of each segment in a 7 segment display Table 4 4 Pin assignments for the 7 segment displays HEXO D 0 PIN E11 Seven Segment Digit O 0 HEXO D 1 PIN F11 Seven Segment Digit O 1 HEXO D 2 PIN H12 Seven Segment Digit O 2 HEXO D 3 PIN H13 Seven Segment Digit O 3 HEXO D 4 PIN G12 Seven Segment Digit O 4 HEXO D 5 PIN F12 Seven Segment Digit O 5 D 6 PIN F13 Seven Segment Digit O 6 HEXO DP PIN D13 Seven Segment Decimal Point 0 1 D 0 PIN A13 Seven Segment Digit 1 0 HEX1 D 1 PIN B13 Seven Segment Digit 1 1 HEX1 D 2 PIN C13 Seven Segment Digit 1 2 HEX1_D 3 PIN_A14 Seven Segment Digit 1 3 HEX1_D 4 PIN_B14 Seven Segment Digit 1 4 HEX1_D 5 PIN_E14 Seven Segment Digit 1 5 HEX1_D 6 PIN_A15 Seven Segment Digit 1 6 HEX1_DP PIN_B15 Seven Segment Decimal Point 1 HEX2_D 0 PIN_D15 Seven Segment Digit 2 0 HEX2_D 1 PIN_A16 Seven Segment Digit 2 1 HEX2_D 2 PIN_B16 Seven Segment Digit 2 2 HEX2_D 3 PIN_E15 Seven Segment Digit 2 3 HEX2_D 4 PIN_A17 Seven Segment Digit 2 4 HEX2_D 5 PIN_B17 Seven Segment Digit 2 5 HEX2_D 6 PIN_F14 Seven Segment Digit 2 6 HEX2_DP PIN_A18 Seven Segment Decimal Point 2 27 INDE RYAN DEO User Manual HEX3_D 0 PIN_B18 Seven Segment Digit 3 0 HEX3_D 1 PIN_F15 Seven Segment Digit 3 1 HEX3_D 2 PIN_A19 Seven Segment Digit 3 2 HEX3_D
16. GA Pattern block can generate many color patterns The VGA Ctr block generate VGA control signals HS and VS that depend on the user s resolution setting that are used to output onto the LCD CRT monitor 49 INDIE RYA DEO User Manual Altera DEO Board 4 bit VGA Circuit VGA Pattern VGA Ctrl amp LCD CRT VGA Connector Monitor SWO Figure 5 5 Block diagram of the VGA Color Pattern demonstration Demonstration Setup File Locations and Instructions Project directory DEO VGA Bit stream used DEO VGA sof or DEO VGA pof e Connect the VGA output of the DEO board to a VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA e The LCD CRT monitor should display the color pattern as shown in Figure 5 6 e Switch SWO can change the color pattern see Figure 5 7 Figure 5 6 illustrates the setup for this demonstration 50 DEO User Manual Figure 5 6 The setup for the VGA color pattern demonstration 51 NOS 274 DEO User Manual Pattern 1 Pattern 2 SWO SWO Figure 5 7 The output color pattern type for the demonstration 52 AND amp 2YAN DEO User Manual Chapter 6 Appendix 6 1 Revision History Version Change Log V1 0 Initial Version Preliminary V1 1 GPIO Pin Assignments Corrected V1 2 SDRAM pin description Corrected V1 3 Figure
17. IO1 D 31 PIN V7 GPIO Connection 1 IO 31 GPIO1 CLKINJOJ PIN AB11 GPIO Connection 1 PLL In GPIO1 CLKIN 1 PIN AA11 GPIO Connection 1 PLL In GPIO1 CLKOUT O PIN R16 GPIO Connection 1 PLL Out GPIO1 CLKOUT 1 PIN T16 GPIO Connection 1 PLL Out 4 7 Using VGA The DEO board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone III FPGA and a 4 bit DAC using resistor network is used to produce the analog data signals red green and blue The associated schematic is given in Figure 4 15 and can support standard VGA resolution 640x480 pixels at 25 MHz 34 NO amp BYA DEO User Manual H17 VGA Ri ANN Hoo VGA R2 ANN H21 VGA R3 AAN 4 MA 2 1 VGA R O MN VGA G O Daxon m kiz DA AZA T voae O J21 VGA G3 ANN 4 e e n Cyclone O E e VGA BO NAN Q O K22 VGA Bi NAN Ce K21 VGA B2 J22 VGA B3 NNN 1 A V Lop VGA VS KAA L21 VGA HS AAA Figure 4 15 Connections between VGA circuit and Cyclone III FPGA The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 16 illustrates the basic timing requirements for each row hori
18. N A7 SDRAM Address 1 1 DRAM ADDR 12 PIN C8 SDRAM Address 12 DRAM DQ 0 PIN D10 SDRAM Datal0 DRAM DQ 1 PIN G10 SDRAM Data 1 DRAM_DQ 2 PIN_H10 SDRAM Data 2 DRAM DQ 3 PIN E9 SDRAM Dataf3 DRAM DQ 4 PIN F9 SDRAM Data 4 DRAM DQ 5 PIN G9 SDRAM Data 5 DRAM DQ 6 PIN H9 SDRAM Data 6 DRAM DQ 7 PIN F8 SDRAM Data 7 DRAM DQ 8 PIN A8 SDRAM Data 8 DRAM DQ 9 PIN B9 SDRAM Data 9 DRAM DQ 10 PIN A9 SDRAM Data 10 DRAM DQ 11 PIN C10 SDRAM Data 11 DRAM DQ 12 PIN B10 SDRAM Data 12 DRAM DQ 13 PIN A10 SDRAM Data 13 DRAM DQ 14 PIN E10 SDRAM Data 14 DRAM DQ 15 PIN F10 SDRAM Data 15 DRAM BA 0 PIN B5 SDRAM Bank Address 0 DRAM BA 1 PIN A4 SDRAM Bank Address 1 DRAM LDOM PIN E7 SDRAM Low byte Data Mask DRAM_UDQM PIN B8 SDRAM High byte Data Mask DRAM RAS N PIN F7 SDRAM Row Address Strobe DRAM CAS N PIN G8 SDRAM Column Address Strobe 41 N DTE YA DEO User Manual DRAM CKE PIN E6 SDRAM Clock Enable DRAM CLK PIN E5 SDRAM Clock DRAM WE N PIN D6 SDRAM Write Enable DRAM CS N PIN G7 SDRAM Chip Select Table 4 16 Flash pin assignments FL ADDR 0 PIN P7 FLASH Address 0 FL ADDR 1 PIN P5 FLASH Address 1 FL ADDR 2 PIN P6 FLASH Address 2 FL ADDR S3 PIN N7 FLASH Address 3 FL ADDR 4 PIN N5 FLASH Address 4 FL ADDR 5 PIN N6 FLASH Address 5 FL ADDR 6 PIN M8 FLASH Address 6 FL ADDR 7
19. PIN M4 FLASH Address 7 FL ADDR 8 PIN P2 FLASH Address 8 FL ADDR 9 PIN N2 FLASH Address 9 FL ADDR 10 PIN N1 FLASH Address 10 FL ADDR 1 1 PIN M3 FLASH Address 1 1 FL ADDR 12 PIN M2 FLASH Address 12 FL ADDR 13 PIN M1 FLASH Address 13 FL ADDR 14 PIN L7 FLASH Address 14 FL ADDR 15 PIN L6 FLASH Address 15 FL ADDR 16 PIN AA2 FLASH Address 16 FL ADDR 17 PIN M5 FLASH Address 17 FL ADDR 18 PIN M6 FLASH Address 1 8 FL ADDR 19 PIN P1 FLASH Address 19 FL ADDR 20 PIN P3 FLASH Address 20 FL ADDR 21 PIN R2 FLASH Address 21 FL DQ 0 PIN R7 FLASH Data 0 FL DQ 1 PIN P8 FLASH Data 1 FL 0012 PIN R8 FLASH Data 2 FL DQ 3 PIN U1 FLASH Data 3 FL DQ 4 PIN V2 FLASH Data 4 FL DQ 5 PIN V3 FLASH Data 5 FL DQ 6 PIN W1 FLASH Data 6 42 DEO User Manual FL DQ 7 PIN Y1 FLASH Data 7 FL 0018 PIN T5 FLASH Data 8 FL DQ 9 PIN T7 FLASH Data 9 FL DQ 10 PIN T4 FLASH Data 10 FL DQ 11 PIN U2 FLASH Data 11 FL DQ 12 PIN V1 FLASH Data 12 FL DQ 13 PIN V4 FLASH Data 13 FL DQI141 PIN W2 FLASH Data 14 FL DQ15 AM1 PIN Y2 FLASH Data 15 FL BYTE N PIN AA1 FLASH Byte Word Mode Configuration FL CE N PIN N8 FLASH Chip Enable FL OE N PIN R6 FLASH Output Enable FL RST N PIN R1 FLASH Reset FL RY PIN M7 LASH Ready Busy output FL WE N PIN P4 FLASH Write Enable FL WP N PIN T3 FLASH Write Protect Programming Acceleration 43 NO PE BYA DEO User Manual
20. TIMER 5 ss VGA Controller ctf va e e JTAG PIO Controller LED Button JTAG Switch Seg7 Blaster S Hardware e SD Card Avalon MM Flash Tristate Bridge D Controller K gt Flash Figure 3 3 The DEO Control Panel concept The DEO Control Panel can be used to light up the LEDs change the values displayed on 7 segment monitor buttons switches status read write the SDRAM and Flash Memory read data from a PS 2 keyboard output color pattern to LCD monitor via VGA connector and read SD CARD specification information The feature of reading writing a word or an entire file from to the Flash Memory allows the user to develop multimedia application Flash Picture Viewer without worrying about how to build a Memory Programmer 3 2 Controlling the LEDs and 7 Segment Displays A simple function of the Control Panel is to allow setting the values displayed on LEDs and the 7 segment displays Choosing the LED tab leads to the window in Figure 3 4 Here you can directly turn the individual LEDs on or off by selecting they individually or by clicking Light All or Unlight All 12 N DTE YAN DEO User Manual Control Panel Y1 0 1 LED 7 SEG Button PS2 SD CARD vGa LED Vv M iv M M v M M Product Name DEO PND 8 RYA UNIVERSITY Light All Unlight All PROGRAM iiasic www terasic com About Disconnect Exit Connected Set Led Succes
21. _AA20 GPIO Connection 1 IO 0 GPIO1_D 1 PIN_AB20 GPIO Connection 1 IO 1 GPIO1_D 2 PIN AA19 GPIO Connection 1 IO 2 GPIO1 D 3 PIN AB19 GPIO Connection 1 IO 3 GPIO1 D 4 PIN AB18 GPIO Connection 1 IO 4 GPIO1 D 5 PIN AA18 GPIO Connection 1 IO 5 GPIO1_D 6 PIN_AA17 GPIO Connection 1 IO 6 GPIO1_D 7 PIN AB17 GPIO Connection 1 10 7 GPIO1 D S PIN Y17 GPIO Connection 1 IO 8 GPIO1 D 9 PIN W17 GPIO Connection 1 IO 9 GPIO1 D 10 PIN U15 GPIO Connection 1 IO 10 GPIO1 D 11 PIN T15 GPIO Connection 1 IO 11 GPIO1 D 12 PIN W15 GPIO Connection 1 IO 12 GPIO1 D 13 PIN V15 GPIO Connection 1 IO 13 GPIO1 D 14 PIN AB9 GPIO Connection 1 IO 14 GPIO1 D 15 PIN AA9 GPIO Connection 1 IO 15 GPIO1_D 16 PIN_AA7 GPIO Connection 1 IO 16 33 DEO User Manual GPIO1 D 17 PIN AB7 GPIO Connection 1 IO 17 GPIO1 D 18 PIN T14 GPIO Connection 1 IO 18 GPIO1 D 19 PIN R14 GPIO Connection 1 IO 19 GPIO1_D 20 PIN U12 GPIO Connection 1 IO 20 GPIO1_D 21 PIN_T12 GPIO Connection 1 101211 GPIO1_D 22 PIN R11 GPIO Connection 1 IO 22 GPIO1 D 23 PIN R12 GPIO Connection 1 IO 23 GPIO1 D 24 PIN U10 GPIO Connection 1 IO 24 GPIO1 0125 PIN T10 GPIO Connection 1 IO 25 GPIO1 Di261 PIN U9 GPIO Connection 1 IO 26 GPIO1 D 27 PIN T9 GPIO Connection 1 101271 GPIO1 D 28 PIN Y7 GPIO Connection 1 IO 28 GPIO1 D 29 PIN U8 GPIO Connection 1 IO 29 GPIO1 D 30 PIN V6 GPIO Connection 1 IO 30 GP
22. ands and screws r Figure 1 2 The feet for the DEO board m Getting Help Here are the addresses vvhere you can get help if you encounter problems e Altera Corporation 101 Innovation Drive NB S RYA DEO User Manual San Jose California 95134 USA Email university altera com e Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web DEO terasic com INDIE RYA DEO User Manual Chapter 2 Altera DEO Board This chapter presents the features and design characteristics of the DEO board 2 1 Layout and Components A photograph of the DEO board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components Power Supply Input USB Blaster Connector Triple 4 bit VGA DAC PS 2 Port SD Card Socket RS 232 Interface Power ON OFF Switch Limp Li bb Le 50 MHz Oscillator 0 4 z nie qu hay f 14 CAR Fees H be 16 x 2LCD Interface Expansion Headers 2 Altera EPCS 4 Cyclone III EP3C16F484 Configuration Device USB Blaster Circuit SDRAM 8 Mbytes FLASH 4 Mbytes 7 Segment Display 4 p m TT LU j E 000 220 25 RUN PROG Switch for OQ gt E375 JTAG AS Modes LA 4 L iH T F T 2 269 A M sas LS ii if MA D i ir Slide Switches 10 User LEDs 10 PushButton Switches 3 Figure 2 1 The DEO bo
23. ard The DEO board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DEO board 4 NO amp BYA DEO User Manual 2 2 Altera Cyclone III 3C16 FPGA device Altera Serial Configuration device EPCS4 USB Blaster on board for programming and user API control both JTAG and Active Serial AS programming modes are supported 8 Mbyte SDRAM 4 Mbyte Flash memory SD Card socket 3 pushbutton switches 10 toggle switches 10 green user LEDs 50 MHz oscillator for clock sources VGA DAC 4 bit resistor network with VGA out connector RS 232 transceiver PS 2 mouse keyboard connector Two 40 pin Expansion Headers Block Diagram of the DEO Board Figure 2 2 gives the block diagram of the DEO board To provide maximum flexibility for the user all connections are made through the Cyclone IIII FPGA device Thus the user can configure the FPGA to implement any system design DEO User Manual User LEDs 10 SDRAM 8 Mbytes PushButton Switches 3 SD Card Socket Slide Switches 10 Triple 4 bit VGA DAC Expansion Headers 2 7 Segment Display 4 E b 1 b C b j a 1 RS 232 Transceiver 16X2 1082100 Interface Interface EP i USB Config A Blaster Device Figure 2 2 Block diagram of the DEO board Following is more detailed
24. ck diagram of this demonstration The system reguires a 50 MHz clock provided from the board Four PIO pins are connected to the SD card socket They are SD CLK SD CMD SD DAT and SD WP N The three pins SD CLK SD CMD and SD DAT are used to implement SD 1 bit Mode protocol for accessing the SD card content The SD 1 bit protocol and FAT File System function are all implemented by NIOS II software The software is stored in the on board SDRAM memory SOMHz 4 On Chip Memory Controller D SDRAM Controller PIO Controller LED BUTTON System Interconnect Fabric Figure 5 1 Block Diagram of the SD Card Demonstration Figure 5 2 shows the software stack of this demonstration The NIOS PIO block provides basic IO functions to access hardware directly The functions are provided from NIOS II system and the 45 NO amp YAN DEO User Manual function prototype is defined in the header file io h The SD CARD block implements SD 1 bit mode protocol for communication with the SD card The FAT File System block implements reading function for FAT16 and FAT 32 file system Long filename is supported By calling the exported FAT functions users can browse files under the root directory of the SD card Furthermore users can open a specified file and read the contents of the file The main block implements main control of this demonstration When the program is executed it detects whether a SD card is ins
25. connect Exit SD CARD read success Figure 3 9 Reading the SD card Identification and Specification 3 7 VGA DEO control panel provides VGA pattern function that allows users to output color pattern to LCD CRT monitor using the DEO FPGA board Please follow the steps below to generate the VGA pattern function pe pepe Choosing the VGA tab leads to the window in Figure 3 10 Plug a D sub cable to the VGA connector of the DEO board and LCD CRT monitor The LCD CRT monitor will display the same color pattern on the control panel window Click the drop down menu shown in Figure 3 10 where you can output the selected color individually 18 DEO User Manual Product Name DEO UNIVERSITY PROGRAM dj asic About www terasic com LED 7 SEG Button Memory PS2 SD CARD VGA Pattern Type Disconnect Exit Connected SD CARD read success Figure 3 10 Controlling VGA display 19 AND TA 274 DEO User Manual Chapter 4 Using the DEO Board This chapter gives instructions for using the DEO board and describes each of its I O devices 4 1 Configuring the Cyclone III FPGA The procedure for downloading a circuit from a host computer to the DEO board is described in the tutorial Getting Started with Altera s DEO Board This tutorial is found in the user manaul folder on the DEO System CD ROM The user is encouraged to read the tutorial first and to treat the information below
26. connected to the USB Blaster port If necessary that is if the default factory configuration of the DEO board is not currently stored in EPCS4 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and green LEDs are flashing e Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors 44 N DTE YAN DEO User Manual The Verilog source code for this demonstration is provided in the DEO Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called DEO Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone III FPGA 5 2 SD Card Many applications use a large external storage device such as a SD card or CF card to store data The DEO board provides the hardware and software needed for SD card access In this demonstration we will show how to browse files stored in the root directory of a SD card and how to read the file contents of a specific file The size of the SD card should be less or egual to 2GB Also it is reguired to be formatted as FAT FAT16 or FAT 32 File System in advance Long file name is supported in this demonstration Figure 5 1 shows the hardware system blo
27. d the contents of the SDRAM and place them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM are to be copied which involves all 8 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the Flash Please note that users need to erase the flash before writing data to it 3 5 PS2 Device The Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time The received scan codes are translated to ASCII code and displayed in the control window Only visible ASCII codes are displayed For control key only Carriage Return ENTER key is implemented This function can be used to verify the functionality of the PS2 Interface Please follow the steps below to exercise the PS2 device 1 Choosing the PS2 tab leads to the window in Figure 3 8 2 Plug a PS2 Keyboard to the FPGA board Then 3 Press the Start button to start PS2Keyboard input receiving process Button caption is changed from Start to Stop 4 In the receiving process users can start to press the attached keyboard The input data will be displayed in the control window in real
28. e 3 2 please check steps 1 to 3 has been performed Then click Download Code button to program FPGA again Note the Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 5 The Control Panel is now ready to be use experiment by setting the value of the LEDs display and observe the result on the DEO board 10 DEO User Manual SEG Button Memory PS2 SD CARD VGA Product Name DEO JAN DTE RYA UNIVERSITY PROGRAM About www terasic com Configure FPGA LED Product Name DEO UNIVERSITY PROGRAM ter asic About www LET BS C COM Figure 3 2 The error message of the DEO Control Panel transfers between the computer and the DEO board 11 The concept of the DEO Control Panel is illustrated in Figure 3 3 The Control Codes that perform the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to issue commands to the control codes It handles all requests and performs data AND amp 274 DEO User Manual FPGA SOPC SEG7 Controller 2 7 SEG Display gt SDRAM Controller SDRAM NIOSI k E PS2 Controller PS2 Keyboard g
29. e DEO board and install USB Blaster driver if necessary e Execute the demo batch file test bat under the batch file folder DEO NIOS SDCARDMlemo batch e After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Copy test files to the root directory of the SD Card e Insert the SD card into the SD Card socket of DEO as shown in Figure 5 3 e Press Button2 of the DEO board to start reading SD Card e The program will display SD Card information as shown in Figure 5 4 47 DEO User Manual m e g LJ g au RIS CT Figure 5 3 Insert SD Card for the SD Card Demonstration 48 INDIE 272 DEO User Manual Figure 5 4 Display SD Card Information for the SD Card Demonstration 5 3 VGA Color Pattern Demonstration The DEO board provides a 4 bit resistor VGA circuit and D SUB VGA connector that allow users to output VGA signals to LCD CRT monitor using Cyclone III FPGA This demonstration will implement a VGA color pattern generator in the FPGA This color pattern generator can generate 2 color patterns using the resolution 640x480 In addition using SWO can switch the output color pattern to LCD CRT monitor Figure 5 5 shows the basic block diagram of this demonstration There are two major blocks in the circuit called VGA Pattern and VGA Ctr The VGA Pattern block controls every pixel value for each horizontal and vertical line therefore the V
30. erted If a SD card is found it will check whether the SD card is formatted as FAT file system If a FAT file system is found it searches all files in the root directory of the FAT file system and displays their names in the nios2 terminal If a text file named test txt is found it will dump the file contents If it successfully recognizes the FAT file system it will turn on the all of green LED On the other hand it will turn off all of the green LED if it fails to parse the FAT file system Half number of the green LED will be turn on if there is no SD card found in the SD Card socket If users press BUTTON of the DEO board the program will perform above process again Main FAT File System SD CARD NIOS II PIO Figure 5 2 Clock Diagram of the SD Card Demonstration B Demonstration Source Code Project directory DEO NIOS SDCARD e Bit stream used DEO TOP SDCARD sof e NIOS II Workspace DEO NIOS SDCARDNSoftware 46 NO amp YAN DEO User Manual B Demonstration Batch File Demo Batch File Folder DEO NIOS SDCARD Demo Batch The demo batch file includes following files Batch File test bat test bashrc s FPGA Configure File DEO TOP SDCARD sof 9 NIOS II Program DEO SDCARD elf B Demonstration Setup e Make sure Quartus II and NIOS II are installed on your PC e Change Switch to PROG Mode to RUN mode in DEO board e Power on the DEO board e Connect USB Blaster to th
31. he supplied USB cable to the USB Blaster port on the DEO board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch see Figure 4 4 to the PROG position The EPCSA chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS4 device to be loaded into the FPGA chip Quartus II USB Blaster Circuit IQUARTUS II Programmer Auto Power on AS Mode PROG RUN Config Cyclone HI EPCS4 Serial Configuration Device Figure 4 3 The AS configuration scheme Figure 4 4 The RUN PROG switch SW2 is set in AS mode 22 AND amp 274 DEO User Manual In addition to its use for JTAG and AS programming the USB Blaster port on the DEO board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 4 2 Using the LEDs and Switches The DEO board provides three pushbutton switches The three outputs called BUTTONO BUTTON 1 and BUTTON2 are connected directly to the Cyclone III FPGA Each switch provides a high logic level 3 3 volts whe
32. information about the blocks in Figure 2 2 Cyclone IIII 3C16 FPGA 15 408 LEs 56 M9K Embedded Memory Blocks 504K total RAM bits e 56 embedded multipliers 4PLLs 346 user I O pins FineLine BGA 484 pin package Built in USB Blaster circuit On board USB Blaster for programming and user API Application programming interface control Using the Altera EPM240 CPLD SDRAM One 8 Mbyte Single Data Rate Synchronous Dynamic RAM memory chip Supports 16 bits data bus 6 4 272 DEO User Manual Flash memory 4 Mbyte NOR Flash memory Support Byte 8 bits Word 16 bits mode SD card socket Provides both SPI and SD 1 bit mod SD Card access Pushbutton switches 3 pushbutton switches Normally high generates one active low pulse when the switch is pressed Slide switches 10 Slide switches Aswitch causes logic 0 when in the DOWN position and logic 1 when in the UP position General User Interfaces 10 Green color LEDs Active high 4 seven segment displays Active low 16x2 LCD Interface Not include LCD module Clock inputs 50 MHz oscillator VGA output Uses a 4 bit resistor network DAC With 15 pin high density D sub connector Supports up to 1280x1024 at 60 Hz refresh rate Serial ports One RS 232 port Without DB 9 serial connector One PS 2 port Can be used through a PS 2 Y Cable to allow you to connect a keyboard and mouse to one port Two 40 pin expansion headers
33. ion 0 IO 14 GPIOO D 15 PIN AA4 GPIO Connection 0 IO 15 32 GPIO1 DO AA20 GPIO1 D1 AB20 GPIO1 D3 AB19 GPIO1 D5 AA18 GPIO1 D7 AB17 GND GPIO1 D9 W17 GPIO1 D11 T15 GPIO1 D13 V15 GPIO1 D14 AB9 GPIO1 D15 AA9 GPIO1 D17 AB7 GPIO1 D19 R14 GPIO1 D21 T12 GND GPIO1 D23 R12 GPIO1 D25 T10 GPIO1 D27 T9 GPIO1 D29 U8 GPIO1 D31 V7 DEO User Manual GPIOO D 16 PIN V14 GPIO Connection 0 IO 16 GPIOO D 17 PIN U14 GPIO Connection 0 IO 17 GPIOO D 18 PIN Y13 GPIO Connection 0 IO 18 GPIOO D 19 PIN W13 GPIO Connection 0 IO 19 GPIOO D 20 PIN U13 GPIO Connection 0 IO 20 GPIOO D 21 PIN V12 GPIO Connection 0 IO 21 GPIOO D 22 PIN R10 GPIO Connection 0 IO 22 GPIOO 0123 PIN V11 GPIO Connection 0 IO 23 GPIOO D 24 PIN Y10 GPIO Connection 0 IO 24 GPIOO D 25 PIN W10 GPIO Connection 0 IO 25 GPIOO D 26 PIN T8 GPIO Connection 0 IO 26 GPIOO 01271 PIN V8 GPIO Connection 0 IO 27 GPIOO D 28 PIN W7 GPIO Connection 0 IO 28 GPIOO D 29 PIN W6 GPIO Connection 0 IO 29 GPIOO D 30 PIN V5 GPIO Connection 0 IO 30 GPIOO D 31 PIN U7 GPIO Connection 0 IO 31 GPIOO CLKINJOJ PIN AB12 GPIO Connection 0 PLL In GPIOO CLKIN 1 PIN AA12 GPIO Connection 0 PLL In GPIOO CLKOUT 0 PIN AB3 GPIO Connection 0 PLL Out GPIOO_CLKOUT 1 PIN_AA3 GPIO Connection 0 PLL Out GPIO1_D 0 PIN
34. n banana timum Re 44 27 Mn Canda Ra 45 5 3 VGA Color Pattern rod ee ERO tiska 49 Chapter 6 AppendiX nn a de naaa aaa aa ak 53 6 1 REVISION History secsec 53 Altera DEO Board 6 2 Copyright Statement ND TS RYA DEO User Manual Chapter 1 DEO Package The DEO package contains all the components needed to use the DEO board in conjunction with a computer that runs the Microsoft Windows software 1 1 Package Contents Figure 1 1shovvs a photograph of the DEO package 111 Le Ci Figure 1 1 The DEO package contents 1 ND TE 274 DEO User Manual The DEO package includes e The DEO board e USB Cable for FPGA programming and control DEO System CD containing o Altera s Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software o the DEO documentation and supporting materials including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises e Clear plastic cover for the board e 7 5 DC wall mount power supply 1 2 The DEO Board Assembly To assemble the included stands for the DEO board e Assemble a rubber silicon cover as shown in Figure 1 2 for each of the four copper stands on the DEO board e The clear plastic cover provides extra protection and is mounted over the top of the board by using additional st
35. n it is not pressed and provides a low logic level 0 volts when depressed There are also 10 slide switches sliders on the DEO board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone III FPGA When a switch is in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch is in the UP position it provides a high logic level 3 3 volts There are 10 user controllable LEDs on the DEO board Each LED is driven directly by a pin on the Cyclone III FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 4 5 and Figure 4 7show the connections between the push buttons slide switches and Cyclone III FPGA As indicated in Figure 4 6 each of these switches is debounced using a Schmitt Trigger circuit The three outputs called BUTTONO BUTTONI and BUTTONG of the Schmitt Trigger devices are connected directly to the Cyclone III FPGA only PCB 10 0100730 A0 version contains the debounced circuit A list of the pin names on the Cyclone III FPGA that are connected to the toggle switches is given in Table 4 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Table 4 2 and Table 4 3 respectively 23 INDE RYAN DEO User Manual
36. nts for each device are listed in Tables 4 15 and 4 16 The datasheets for the memory chips are provided in the Datasheet Memory folder on the DEO System CD ROM 39 DEO User Manual See Table 4 15 See Table 4 15 B5 A4 Cyclone Ill DRAM ADDR 12 0 DRAM DQ 15 0 DRAM BA 0 DRAM BA 1 DRAM_LDQM DRAM_UDQM DRAM_WE_N DRAM_CAS_N DRAM RAS N DRAM CS N DRAM CLK DRAM CKE SDRAM U1 A 12 0 D 15 0 BAO BA1 LDOM UDQM nWE nCAS nRAS ncs CLK CKE Figure 4 21 Connections between SDRAM and Cyclone III FPGA See Table 4 16 See Table 4 16 Y2 P4 R1 Cyclone Ill T3 M7 G8 R6 FL ADDR 12 0 FL DQ 15 0 FL DQ15 AM1 FL RSTN FL BYTE N FLASH U2 A 21 0 DQ 14 0 DQ15 A 1 WE RESET WP ACC RY BY CE OE BYTE Figure 4 22 Connections between Flash and Cyclone III FPGA JAN DTE RYAN DEO User Manual Table 4 15 SDRAM pin assignments sea DRAM ADDR 0 PIN C4 SDRAM Address 0 DRAM ADDR 1 PIN A3 SDRAM Address 1 DRAM ADDR 2 PIN B3 SDRAM Address 2 DRAM_ADDR 3 PIN_C3 SDRAM Address 3 DRAM_ADDR 4 PIN A5 SDRAM Address 4 DRAM ADDR 5 PIN C6 SDRAM Address 5 DRAM ADDR 6 PIN B6 SDRAM Address 6 DRAM ADDR T7 PIN A6 SDRAM Address 7 DRAM ADDR 8 PIN C7 SDRAM Address 8 DRAM ADDR 9 PIN B7 SDRAM Address 9 DRAM ADDR 10 PIN B4 SDRAM Address 10 DRAM ADDR 1 PI
37. ont porch d Display interval c interval c DATA HSYNC I Sync a Figure 4 16 VGA horizontal timing specification Table 4 9 VGA horizontal timing specification Configuration Resolution HxV a us b us c us d us Pixel clock Mhz VGA 60Hz 640x480 3 8 1 9 25 4 0 6 25 640 c Table 4 10 VGA vertical timing specification Configuration Resolution HxV a lines b lines c lines d lines VGA 60Hz 640x480 2 33 480 10 Table 4 11 VGA pin assignments VGA R 0 PIN H19 VGA Red 0 VGA R 1 PIN H17 VGA Redf1 VGA RI PIN H20 VGA Red 2 VGA 13 PIN H21 VGA Redf3 VGA 0101 PIN H22 VGA Green 0 VGA G 1 PIN J17 VGA Green 1 VGA 0121 PIN K17 VGA Green 2 VGA G 3 PIN J21 VGA Green 3 VGA 10 PIN K22 VGA Blue 0 VGA B 1 PIN K21 VGA Blue 1 VGA Bi2l PIN J22 VGA Blue 2 VGA B 3 PIN K18 VGA Blue 3 VGA HS PIN L21 VGA H SYNC VGA VS PIN L22 VGA V SYNC INDE RYA DEO User Manual 4 8 RS 232 Serial Port The DEO board uses the ADM3202 transceiver chip for RS 232 communications Please note that the associated RS232 signals are connected to use as test point as shown in Figure 4 17 To use this interface users need to connect these signals to 9 pin D sub connector or RS232 cable For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s
38. rface are shown in Table 4 13 PS2 KBCLK Cyclone III PS2 KBDAT Figure 4 19 Connections between PS 2 and Cyclone III FPGA Table 4 13 PS 2 pin assignments PS2 KBCLK PIN P22 PS 2 Clock PS2 KBDAT PIN P21 PS 2 Data PS2 MSCLK PIN R21 PS 2 Clock reserved for second PS 2 device PS2 MSDAT PIN R22 PS 2 Data reserved for second PS 2 device 38 AND 272 DEO User Manual 4 10 SD Card Socket The DEO board has a SD card socket and can be accessed as optional external memory in both SPI and 1 bit SD mode Table 4 14 shows the pin assignments for the SD card socket with the Cyclone III FPGA 3 3V Cyclone Hi 535 DATA2 w21 SD DATAS 1 DATA3 v22 SD_CMD i 2 cup 31 vss 3 3V 4 vec v21 LSD CLK s 6 vss AA22 SD DATAO 1 7 pATAO 8 DATA W20 SP_WPn m Figure 4 20 Connections between SD Card and Cyclone III FPGA Table 4 14 SD Card pin assignments SD CLK PIN Y21 SD Clock SD CMD PIN Y22 SD Command bidirectional signal SD DATO PIN AA22 SD Data bidirectional signal SD DAT3 PIN W21 SD Data bidirectional signal SD WP N PIN W20 SD Card write protect signal active low 4 11 Using SDRAM and Flash The DEO board provides a 4 Mbyte Flash memory and 8 Mbyte SDRAM chips Figure 4 21 and Figure 4 22 show the connections between the memory chips and Cyclone III FPGA The pin assignme
39. s Figure3 4 Controlling LEDs Choosing the 7 SEG tab leads to the window in Figure 3 5 In the tab sheet directly use the Up Down control and Dot Check box to specified desired patterns the 7 SEG patterns on the board will be updated immediately Control Panel Y1 0 1 Button Memory PS2 SD CARD VGA 1 2 3 4 dot 7 dot 7 dot dot 41 Jo Jo Product Name DEO JAN DTE RYA UNIVERSITY PROGRAM asic www Lerasic com About Disconnect Exit Set SEG 7 Success Figure 3 5 Controlling 7 SEG display 13 DEO User Manual The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 3 3 Switches and Buttons Choosing the Button tab leads to the window in Figure 3 6 The function is designed to monitor the status of switches and buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the switches and buttons Press the Start button to start button switch status monitoring process and button caption is changed from Start to Stop In the monitoring process the status of buttons and switches on the board is shown in the GUI window and updated in real time Pre
40. s an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DEO Board This tutorial is available on the DEO System CD ROM 20 JAN DTE RYAN DEO User Manual Configuring the FPGA in JTAG Mode Figure 4 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone III FPGA perform the following steps Ensure that power is applied to the DEO board Connect the supplied USB cable to the USB Blaster port on the DEO board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch see Figure 4 2 to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension Quartus II QUARTUS II Programmer USB Blaster Circuit PROG RUN JTAG UART bi JTAG Config Signals Cyclone HI HUN Figure 4 1 The JTAG configuration scheme Figure 4 2 The RUN PROG switch SW2 is set in JTAG mode Configuring the EPCS4 in AS Mode Figure 4 3 illustrates the AS configuration set up To download a configuration bit stream into the EPCSA serial EEPROM device perform the following steps Ensure that power is applied to the DEO board 21 INDE RYA DEO User Manual Connect t
41. ss Stop to end the monitoring process Control Panel Y1 0 1 LED 7 SEG Buton Memory PS2 SD CARD VGA Button Switch II Switch I About www terasic com VISCO Connected Monitoring Button Switch Status Figure 3 6 Monitoring switches and buttons The ability to check the status of button and switch is not needed in typical design activities However it provides users a simple mechanism for verifying if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 14 N DTE YAN DEO User Manual 3 4 SDRAM and Flash Controller and Programmer The Control Panel can be used to write read data to from the SDRAM and FLASH chips on the DEO board Click on the Memory tab and select SDRAM to reach the window in Figure 3 7 Please note to erase the flash memory before writing data to it Control Panel Y1 0 1 LED 7SEG Buton Memory ps2 SD CARD VGA SDRAM 200000h WORDS Si Random Access Address 000000 0000 DATA 0000 Cl Write Read Sequential Write Address 000000 Length 0 File Length 1 ue Write a File to Memory Product Name DEO Sequential Read NU S RYAN A Address 000000 Length fo Entire Memory U N I V E R S I TY Load Memory Contentto a File PROGRAM il as WWW LES C COM About Disconnect Exit Connected SDRAM Random
42. web site or in the Datasheet RS232 folder on the DEO System CD ROM Figure 4 18 shows the related schematics and Table 4 12 lists the Cyclone III FPGA pin assignments with the RS 232 serial port RS232 Signals Figure 4 17 The placement of the RS232 signals U3 ADM3202 u22 RXD 12 RIOUT RXD em 2 VARI RTS 9 R20UT rain RTS Cyclone III sa n uoi PART TKD TIN TOUT 14 rx UART CTS 10 7 vai 52 T21N T2OUT 2 cts i GND1 Figure 4 18 Connections between the ADM232 RS 232 chip and Cyclone HI FPGA 37 AND S 272 DEO User Manual Table 4 12 RS 232 pin assignments UART RXD PIN U22 UART Receiver UART TXD PIN U21 UART Transmitter UART CTS PIN V21 UART Clear to Send UART RTS PIN V22 UART Request to Send 4 9 PS 2 Serial Port The DEO board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse In addition users can use the PS 2 keyboard and mouse on the DEO board simultaneously by plugging an extension PS 2 Y Cable Note that both the PS MSDAT and PS MSCLK signals can be used only when the PS 2 Y cable is connected to the PS 2 connector Figure 4 19 shows the connections between the PS 2 circuit and FPGA Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The pin assignments for the associated inte
43. zontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 4 16 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 4 9 and Table 4 10 show different resolutions of the durations of time periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s web site or in the Datasheet VGA DAC folder on the DEO System CD ROM The pin assignments between the Cyclone III FPGA and the VGA connector are listed in Table 4 11 An example of code that drives a VGA display is described in Sections 5 3 35 DEO User Manual Back porch b Fr
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