Lecture 10: PI/T timer
Contents
1. Timer Base Address Timer Control Reg Timer Int Vect Reg Preload Hi Reg Preload Mid Reg Preload Lo Reg Counter Hi Reg Counter Mid Reg Counter Lo Reg Timer Status Reg Timer Vector reg Timer Mode feedback when this function gets called Microprocessor based System Design Ricardo Gutierrez Osuna Wright State University 47 47 taf 47 iff 47 27 eff main long vtable int count 1250000 set supervisor mode and interrupt mask to 4 asm move w 5 2400 SR setup the stack pointer asm movea 1 20000 SP setup timer control register tcr OxA0 setup vector table entry tivr vtable vtable load cprl count cprm count cprh t 70 long 70 4 isr he counter preload register unsigned char count count gt gt 8 shift right 8 bits unsigned char count count gt gt 8 shift right 8 bits unsigned char count Start timer AECE 0xA1 while 1 do the regular control loop 12 Example Programming a polling loop for the PI T in C language This code will setup a polling loop so the 68320 continuously main checks the ZDS bit of the PI T timer int count 1250000 z r k set supervisor mode and interrupt mask to 4 define tmr unsigned char 0xFE8021 Timer Base Address asm move w 52400 SR define t2. 0 0 x kerha Torne PC3 Toyr and PC7 TIACK are port C functions Toggle a square wave PC3 Tour is a timer function In the run state Toy provides a square wave which 0 1 X with each expiration of is toggled on each zero detect The Tour pin is high in the halt state PC7 TIACK the timer is a port C function PC3 Tour is a timer function In the run or halt state Tour is used as a timer 1 0 0 No vectored interrupt request output Timer interrupt is disabled the pin is always three stated generated on a count of 0 PC7 TIACK is a port C function Since interrupt requests are negated PI T produces no response to an asserted TIACK PC3 Tour is a timer function and is used as a timer interrupt request output The 1 0 1 Generate a vectored timer interrupt is enabled and Tour s low IRQ asserted whenever the ZDS bit interrupt on a count of 0 is set PC7 TIACK is used to detect the 68000 IACK cycle This combination operates in the vectored interrupt mode No autovectored PC3 Tour is a timer function In the run or halt state it is used as a timer interrupt 1 1 0 interrupt generated on a request output The timer interrupt is disabled and the pin always three stated count of 0 PC7 TIACK is a port C function PC3 Tour is a timer function and is used as a timer interrupt request output The 1 1 1 Tae a on a timer interrupt is enabled and Tour s low whenever the ZDS bit is set PC7 TIACK is a port C function This combination operates in an autov
3. Lecture 10 PI T timer a Introduction to the 68230 Parallel Interface Timer Interface with the 68000 PI T Timer registers Timer Control Register e Clock control e Zero detect control MOVEP instruction Examples e Real time clock e Square wave generator Polling Vs Interrupt Programming the PI T in C language Microprocessor based System Design OEL n Ricardo Gutierrez Osuna Wright State University Introduction to the 68230 The 68230 PI T Parallel Interface Timer is a general purpose peripheral e Its primary function is a parallel interface e Its secondary function is a programmable timer The PARALLEL INTERFACE provides 4 modes with various handshaking and buffering capabilities e Unidirectional 8 bit e Unidirectional 16 bit e Bidirectional 8 bit e Bidirectional 16 bit The PROGRAMMABLE TIMER provides a variety of OS services e Periodic interrupt generation e Square wave generation e Interrupt after timeout e Elapsed time measurement e System watchdog This lecture covers the easier programmable timer function e The next two lectures will cover the parallel interface Microprocessor based System Design A Tae Ricardo Gutierrez Osuna Wright State University PI T simplified interface with the MC68000 An address decoder places the PI T at a given location within the address space of the processor e On the SBC68K the PI T base address is FE8000 The 68230 is programmed and used
4. by reading and writing data to the correct memory mapped locations registers The 68230 contains 23 internal registers which are are selected by the state of 5 register select inputs RS RS connected to the address bus A A e Notice that ALL the registers are located at ODD memory locations e Only 9 of the 23 registers are used for the programmable timer function Data to the internal registers is transferred through the data bus D D_ a There are three internal ports e Port A and Port B are used for parallel interface e Port Cis shared by timer and parallel interface Handshaking is accomplished through lines H H System clock PAy PA PC DMAREQ Address PC TOUT decoder PC TIN V ZZZZZZZZZZZ ZZ PCo Microprocessor based System Design 3 OEL n Ricardo Gutierrez Osuna Wright State University PI T timer registers Timer Control Register e Determines the operation modes of the timer Timer Interrupt Vector Register CLK e Stores the interrupt vector number PA Counter Preload Register Do 44 f f 45 e A 24 bit counter with the desired by the a programmer number of counts measured in ticks 7 47 Mutiplexer_ Counter Register Da E Tack 7 5 e A 24 bit counter down counter that is De automatically decremented with every tick Dz gt Timeri ge Tour 32 Timer Status Register pw 34 MZ Ty DTACK
5. cr unsigned char tmr Timer Control Reg define tivr unsigned char tmr 2 Timer Int Vect Reg setup the stack pointer define cprh unsigned char tmr 6 Preload Hi Reg asm movea 1 20000 SP define cprm unsigned char tmr 8 Preload Mid Reg f t setup timer control register define cprl unsigned char tmr 10 Preload Lo Reg ecm GFL i v4 define cnrh unsigned char tmr 14 Counter Hi Reg define cnrm unsigned char tmr 16 Counter Mid Reg 2 load the counter preload register define cnrl unsigned char tmr 18 Counter Lo Reg cprl unsigned char count define tsr unsigned char tmr 20 Timer Status Reg count count gt gt 8 shift right 8 bits defi A R see Ti T cprm unsigned char count a ae a A ae count count gt gt 8 shift right 8 bits define tmrentrl 0x80 Timer Mode cprh unsigned char count Start timer tcr 0x81 k 3 a E The isr function is not needed anymore since the while 1 4 code it used to execute is now performed by main while tsr amp l after it reads that the ZDS bit has been set to 1 check until ZDS goes high printf Five secs has passed n reset the ZDS bit tsr 0x01 Microprocessor based System Design 13 ee t Ricardo Gutierrez Osuna Wright State University
6. e Determines the status of the timer cs a1 Timer control register TCR l e Only Bit 0 Zero Detect Status or ZDS is used olk lt Tour TIACK Zero detect Clock Port C RESET control control control funcBons e In order to clear the ZDS bit after a zero detect a Timer status register TSR pra ed by YOU MUST WRITE A 1 to it YES the ZDS bit is RSi 205 timer cleared by writing a ONE to it ie S RS 96 Count register 24 bits CNTR 7 25 Count register high CNTRH 5 i Count register middle CNTRM Register and Mnemonic Acc Offset Count register low CNTRL Timer Control Register TCR R W 21 Counter preload register a i 7 Counter preload register high CPRH D eae an oy ar E Se Interface Counter preload register middle CPRM to i Counter Preload Register Middle CPRM R W 29 68000 _Counter preload register low CPRL Counter Preload Register Low CPRL R W 31 Counter Register High CNTRH R 2F Timer interrupt vector register TIVR Counter Register Middle CNTRM R 31 Counter Register Low CNTRL R 33 Timer Status Register TSR R W 35 Microprocessor based System Design 4 OEL n Ricardo Gutierrez Osuna Wright State University Timer Control Register Timer Enable TCRO Turns the timer ON and OFF The timer is disabled when the bit is cleared it is enabled when set To start the timer place an 1 in TCRO To stop the timer place a 0 in TCRO Clock Control TCR1 2 e The PI T timer permits different clock p
7. e interrupt vector setup the maximum count jand load it into the CPR set up the TCR Microprocessor based System Design ee Ricardo Gutierrez Osuna Wright State University Halt mode Run mode t Load counter FFFFF Fig as an analog ue 00000015 ZDS bit of TSR Sa 0 1 Tout 0 1 TIACK gt Example Square wave generator The timer produces a square wave at its Toyr output pin e No interrupts are generated supported a Hardware configuration e Tour MUST NOT be connected to an IRQ line or else the 68000 will be interrupted when Tour goes to LOW e TIACK is ignored by the PI T timer in this mode m The SBC68K has a jumper JP6 that allows us to configure the way 68000 and PI T are connected SBC68K User s Manual pp 5 18 m The TCR7 bit is cleared to allow the Tour pin to be toggled each time the counter rolls down to zero The period of the wave is determined by the valued loaded on the counter preload register Halt mode Run mode e n i a Max count 24 bit counter contents a rg as an analog 000000 1 Tour gt gt 0 1 Square wave Microprocessor based System Design 10 Tine TT Ricardo Gutierrez Osuna Wright State University Polling Vs Interrupt An alternative to programming interrupts is to create a polling loop The CPU periodically reads the ZDS bit off the PI T When ZDS 1 the CPU executes the code originally written for the interrupt handler Unless the CPU has nothing else t
8. ectored count of 0 interrupt mode Microprocessor based System Design 7 ee t Ricardo Gutierrez Osuna Wright State University MOVEP instruction The MOVEP instruction is provided to allow transfer of data to alternate bytes in memory e This is very useful for 68000 based peripherals m Instruction format MOVEP size Di d Aj MOVEP size d Aj Di Example MOVEP L DO 5 A0 DO 40 FO 3A 60 1004 40 1006 FO AO 00 10 00 1008 3A 100A 60 Microprocessor based System Design ee Ricardo Gutierrez Osuna Wright State University Example Real time clock PIT TCR TIVR CPR TSR TIME setup EQU EQU EQU EQU EQU EQU LEA MOVE B timevec TIVR A0 MOVE L SOOFFFFFF DO MOVEP L DO CPR A0 MOVE B 10100001 TCR A0 RTS The PI T generates an interrupt at periodic intervals Hardware configuration Tour MUST BE connected to one of the 68000 s IRQ lines TIACK MUST BE connected to the appropriate 68000 s IACK line The counter is reloaded from CPCR on each zero detect The ZDS MUST be cleared by the interrupt handler to remove the interrupt request Sample assembly code FE8000 PI T base address on the SBC68K 21 offset to the timer control reg 23 offset to the timer int vector reg 25 offset to the counter preload reg 35 offset to the timer status reg 4 timevec j location of the PI T int handler PIT AO load th
9. led by 32 thus 0 0 the counter clock is CLK 32 The timer enable bit determines whether the CLK timer is in the run or halt state PC T y is a timer input The prescaler is decremented on the falling edge 0 1 of CLK and the counter is decremented when the prescaler rolls over CLK from 00 to 1F 31 9 Timer is in the run state when BOTH timer enable bit and TIN are asserted TIN PC T y is a timer input and is prescaled by 32 The prescaler is decremented following the rising transition of TIN after being 1 0 synchronized with the internal clock The 24 bit counter is decremented TIN when the prescaler rolls over from 00 to 1F The timer enable bit determines whether the timer is in the run or halt state PC T y is a timer input and prescaling is not used The 24 bit counter is 1 1 decremented following the rising edge of the signal at the T pin after TIN being synchronized with the internal clock The timer enable bit determines whether the timer is in the run or halt state CC Microprocessor based System Design Ricardo Gutierrez Osuna Wright State University Toy7 TIACK control TCR7 TCRS5 a Bits 7 5 of the Timer Control Register control the way the PI T timer behaves on a zero detect ZDS 1 e Whether interrupts are supported vectored auto vectored or none e How does the PC3 T our output pin behave e How is the PC7 TIACK input pin interpreted TCR TCR TCR Timer response Timer response detailed
10. o do between timeouts of the PI T timer polling is a waste of CPU cycles interrupt c polling c main isr set_up_pit_polling clear_zds perform_operation while 1 while zds 1 do nothing until timeout main set_up_pit_interrupt isr clear_zds while 1 do something useful isr perform_operation takes care of the timeout Microprocessor based System Design ee t Ricardo Gutierrez Osuna Wright State University 11 Example Programming interrupts for the PI T in C language This code will setup the 68320 to generate an interrupt every 5 seconds The interrupt service routine isr clears the ZDS bit so the 68320 stops asserting the IRQ line since its interrupt request has been serviced define define define define define define define define define define define define tmr ter tivr cprh cprm cprl cnrh cnrm cnrl tsr unsigned char 0xFE8021 unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char unsigned char tvector 0x40 tmrentrl 0x80 void isr so we get tmr tmr 2 tmr 6 tmr 8 tmr 10 tmr 14 tmr 16 tmr 18 tmr 20 printf Five secs has passed n reset the ZDS bit 0x01 tsr return to main asm rte ERTO
11. ulse operations When the field is 00 every 32 CPU clock cycles become 1 timer tick Counter Load TCR4 After completing its countdown the tick counter is either reset from the Counter Preload Register CPR or it rolls over to F FFFFF a Writing a 0 on TCR4 causes a reload from the CPR a Writing a 1 on TCR4 causes a roll over to FFFFFF m Action on Zero Detect TCR5 7 The timer can select from a series of actions when the tick counter reaches 0 1 1 X 1 0 X 00 or 1X 1 2 0 1 X 0 X 00 or 1X 1 3 1 X 1 1 X 00 or 1X 1 4 0 0 X 1 X 0 0 1 5 0 0 X 1 X 0 X 1 6 1 X 1 1 X 0 1 1 Tout TIACK control Bre ae Clock control ea lead Mode 1 Real time clock Mode 4 Elapsed time measurement Mode 5 Pulse counter Mode 6 Period measurement Mode 2 Square wave generator Mode 3 Interrupt after timeout Microprocessor based System Design 5 CRAI t Ricardo Gutierrez Osuna Wright State University Clock control TCR2 TCR1 The counter can be decremented from three different signals e Ty the external clock input e The output of a 5 bit prescaler driven by CLK and enabled by Tn e CLK the system clock prescaled The 5 bit prescaler allows us to divide the counter frequency by 32 a The SBC68K clock runs at 8MHz 125x10 seconds per count so 1 second will require 250 000 CLK ticks mode 00 TCR Clock Control Example PC T y is a port C function The counter clock is presca
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