PCI-VME Interface: General Description - W-IE-NE
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1. PCIADA Ver 11 ARW 12 DEC 98 S301 8080 SE Er S402 8 cso 12 pssecz00M 22n 33 33 c19 C 00n Ptr Qmm 21 C 00n O a t0u 16 J e 2 i 22 1001 c23 C 1000 c24 Ron 2 2 si EI vaor R4 C 10k H ISPLSI 1024 601 vat PCIS050 LI O 8 dei azor F 93c54681 Em 302 5382 outa 22 10u 16 WAK700 am ou not used CI3 024 100n Figure 8 Layout of the PCIADA board U506 VMEMMS Ver 11 LAYER 1 w TE c Ooo qs ARW 11 NOV 9 37 E tou oJ Figure 7 Layout of VMEMM February 03 17 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH APPENDIX B Power requirements of PCIADA Voltage 5V Current 0 5A Power 2 5 W APPENDIX C Access times PCI to VMEMM VIC Reg D8 600 1000 PCI to VMEMM Adr Reg D16 PCI to VME D8 DStoDTACKca20n 660 JI200 PCI to VME D16 DStoDTACKca20n 660 120 February 03 18 00423 A02. ME A31 A12 uo gy cn og 3 4 VMEMM Control and Status registers You find important information about configuration and controlling of the interface in the VMEMM Control and Status registers Register VMEADDR contains high bytes of VMEbus addresses A31 to A12 of the following accesses Data bit D11 to DO are ignored during write and replied as 0 during read Addresses A31 to A24 A31 to A16 have no meaning for standard short I O VMEbus accesses VMEADDR is read and writeable in word or long word mode February 03 8 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Table 9 Contents of the VMEADDR register for word or long word read write access 31 12 most significant address bit A31 A12 11 0 write no meaning read returns 0 yes yes 0 23 12 most significant address bit A23 A12 11 0 write no meaning read returns 0 lys yes 0 31 16 15 12 most significant address bit A15 A12 11 0 write don t care read returs0 yes yes o Reset functions are handled by the VMEReset register Write data word 0x000a into VMER to perform a VMEbus reset and a global reset of the interface which equals a power up reset After this a reinitialization of VMEMM is mandatory Pushing the reset button on the front panel will cause an interrupt Further actions have to be preformed by software This method allows an individual programming of t
3. de ALME xni west entry PCI VME PCI to VME Interface User s Manual 00423 A0 Table of contents 1 PCI VME INTERFACE GENERAL DESCRIPTIONN sesse ee esse se ee es se ee es se se ee es se ese eg se ee ee ese ee ese 1 2 PCL INTERFACE CARD PCIA D eee eee ioo eo rose see roseis ese ie dese seg dee Se eo ee ee see Po eg ged ge ee de dog we de ee eed 2 2 1 ISSUE EE ET EE EE ER N EO EE EO Bets 2 2 2 MAJOR LCREGISTERS ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ener nsns ee ee ese ess e ese ee ee ee ee ee ee ee assess esas ee ee sese ee ee etes esee 2 2 ANS I e VEE OR EE ER EE EE OE EO EE 4 3 THE VMEMMEBOARD soo et erae ood pe Neap peo ese FOE keep a Neun ETE TS gee Deae ee dee see ge eve de uo Pe ees ae ede ORO segoed AERE 5 3 1 JUMPER SETTINGS see ee ee E ee ee eee eee ern hene ee EE ee ee ee Re ee ee E Re be sette tette terere nn 5 3 9 OPERATION 5 ee dvi Ee EE N lese etd ee ee tex Sn oe eg ee at Ge Rs Ge tere ved BE dedere necu 7 3 MMEMM AREAS ME OIE tete eal EG ET LE uelit nud ee A en ee ER MEO es ee De 7 3 4 VMEMM CONTROL AND STATUS REGISTERS ee esse ee ee ee ee ee e eee emen ee ee ee ee ee ee ese ese ese ese ese ese e ese sese 8 3 5 MAG OLEO dIe SE E E AEE EEEE 10 3 6 INTERRUPTS ede ERR ERE E EE E ERE ERE E EE GE EE GE CE es De 11 4 OPERATING THE INTERFACE iiie teen eee ett kara sd se seges se p aoctor eo e Se PERO S UU
4. Table 8 Contents of the VMEMM which is mapped into the PCI memory area byte AO E VME D15 D00 VME D15 D08 byte AO 24 VME D07 D00 VME D07 D00 word Ex VME D15 D00 VME D15 D00 lword T VME D31 D00 VME D31 D00 E E E E TVEC byte D00 Iack 7 Vector D00 Iack 6 Vector D00 Iack 5 Vector D00 Iack 4 Vector D00 Iack 3 Vector TVEC byte D07 D00 lt Iack 2 Vector TVEC byte I 07 DOO lt Tack 1 Vector VIC byte VIC068A Reg VIC068A Reg ee am VIC byte VICO6BA Reg VICO6BA Reg 0403 VIC byte VICO68A Reg VICO68A Reg per OE VMEMM word VMEADRReg high VMEADRStat high D15 D00 gt VME A31 A16 D15 D00 VME A31 A16 Ed VMEMM word VMEADRReg low VMEADRStat low D15 D12 VME A15 A12 D15 D12 VME A15 A12 D11 D00 x D11 D00 0 d VMEMM lword VMEADRReg VMEADRSta D31 D12 gt VME A31 A12 D31 D12 VM D11 D00 x D11 D00 0 at BN VMEMM word VMEVICReset VMEMMIROSt D15 D00 gt n000a J IRQ 1 aktiv D15 D00 h0005 IPLO IPL1 IPL2 D04 0 0000 VMEMM word VMEVICReg VMEMMSt at DO gt RMC VICO48A DO RMC VICO68A 3 D1 BLT VICO68A 4x D2 WORD Jumper sel D3 SC Jumper sel D07 D04 Modul Number D11 D08 FPGA Revision D15 D12 module Type 1 VIC Global Reset refer to VIC068A Manual 2 VIC Internal Reset refer to VICO68A Manual 3 Read Modify Cycle refer to VICO68A Manual 4 Blocktransfer fix disabled
5. ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee Ee Ee ee Ee ee Ee ee ee neni 14 FIGURE 4 STEPS TO ACCESS THE VME BUS EN EE Ee ee ee Ee Ee Ge elec ee ee ee eg ee Ge OER Ge eed ee ee Gee I Ge Gee Ee 15 FIGURE 5 HANDLING OF AN INTERRUPT 1 esse see se se se se ee ee ee ee ee ee ee ee ee ee ee Ee Ee Ee Ee ee Ee Ee ee Ee ee ee Ee Ee nene ee ee ae ee ee ee ee ee ee ee ee 16 FIGURE 6 STEPS TO UNINSTALL THE INTERFACE ee ese se se ee ee ee se ee ee ee ee ee ee ee ee ee ee ee ee ee ee Ee ee Ee ee Ee ee ee Ee Ee ee Ee ee ee nen ee EE ee ee 16 FIGURE 7 LAYOUT OR V MEMM EE ee rir ee De mte edet nce el See buen pte Se oe See bens tes Dee Ge pee e epe Ese ee bite 17 FIGURE 8 LAYOUT OF THE PCIADA BOARD ees ee ese se se se ee ee ee ee ee ee ee ee ee Ee Ee Ee ee ee ee Ee ee ee ee ee nene ee Ee Ee Ee ee ee ee ee ee ee ee ee 17 Legend Symbols for jumper settings I jumper is installed jumper is not installed February 03 ii 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH PCI VME Interface General Description With the help of the PCI VME interface which consists of the PCI card PCIADA and the VME main board VMEMM users of the VME bus profit of the technical success which takes place in the PC development A huge variety of software is available for a PC In parallel it s performance was constantly improved Modern operating systems were developed which turn the PC into a powerful workstation On the other
6. gives a short description of some VIC68 A registers For further information please refer to the Cypress VICO68 A data sheet which is distributed with this interface Registers can be accessed in byte mode A 4 byte offset has to be considered for address calculations e g VMEMM base 0x403 0x0 VMEMM base 0x403 0x4 The Address Modifier for the next VMEbus access is stored in the Address Modifier Source Register AMSR It does not influence Interrupt Acknowledge Cycles Table 13 Register AMSR VIC base address OxB7 byte access only 7 mutbeO yes fyes JO mustbeO ye yes JO 0 The VIC chip generates a SYSFAIL after each reset of the VMEbus which is deactivated by the Interprocessor Communication Register number 7 ICR7 Table 14 Register ICR7 VIC base address Ox7F byte access only I7 SYSFAIL MASK 1 deaktiviert SYSFAIL further functions are described in the VIC68 A yes manual Register TTR handles the VMEbus timeout Values smaller than the PCIADA timeout e g 4 or 16 us should be inserted Table 15 Timeout coding 32 switched off infinite February 03 10 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Table 16 Register TTR VIC base address 0xA3 byte access only VME BUS Timeout Period see table below Local BUS Timeout Period see table below Arbitration Timeout detected 1 detected yes no O0 W
7. hand the number of UNIX workstations which are equipped with PCI increases strongly The PCI VME interface can be used in this systems too Drivers and programming tools for PCI VME are provided for different operating systems and programming languages A driver for Windows offers an easy access to the VME bus Using pvmon exe a quick check of your VME hardware is possible For C and Turbo Pascal users the Pascal and c libraries provide easy routines to operate VME modules Using the Linux driver all advantages of a multi user and multi tasking operating system can be used for VME operations VMEMM is available as a BU VMEMM 3 and 6U VME module VMEMM 6 It is linked via a standard SCSI 2 cable to the PCIADA card Address modes A16 A24 A32 D8 D16 D32 A16 A24 D8 D16 for VMEMM 3 are possible PCIADA supports 8 16 and 32 bit PCI bus slave access It provides programmable interrupt generation on PC February 03 1 00423 A0 2 1 22 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH PCI interface card PCIADA Operation The major part of the PCIADA card represents the interface chip PCI9050 by PLX Technology It manages PCI bus communications At booting time necessary setting are configured by PCI auto setup No jumpers have to be set on the interface card All PCIADA information such as memory and IRQ requirements are stored in an EEPROM called the PCI Configuration Register PCR Some IDs can be r
8. manual Windows95 will recognize PCIADA as new hardware and will ask for a driver Activate do not install a driver and press o k If you use Pascal drivers you have to edit the emm386 exe in config sys You will find details in a dos pascal readme txt Check your interface using the supplied test programs 4 2 Initializing the interface Necessary steps to initialize the interface are summarized in Figure 3 For further information please refer to the supplied code written in Turbo Pascal DOS and C Windows 95 February 03 13 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GnbH e g from bios calls or from windows registry enable access inLCR USER I O 1 i test user I O 3 try a VME access get PCI address yes access interface After 40 us poll for Interrupt 2 Access uccessful get module type and module ID correct interface initialize VIC6SA remove SYSFAIL end of initialization j Figure 3 Initialization of the VME interface 4 3 VME access Basic steps to access the VMEbus are shown in Figure 4 A VME access which causes a Timeout or a VME BUS Error ends it s cycle normally The Timeout Interrupt can be used to identify these events Alternatively you can check the Interrupt 1 Status Bit February 03 14 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GnbH Fehler Keine g ltige Verkn pfung Fig
9. RQ7 LICR6 has to be considered to calculate the exact timeout It is mandatory to convert internal interrupts into vectors before any other action is performed Usually internal events which are caused by drivers generate vectors between 0x00 to OxOF Other VME boards use Vector addresses from 0x40 to Oxff Note Local interrupts expect VMEMM to generate the interrupt vector Note The PCIADA timeout interrupt has to be mirrored in interrupt vector number 1 February 03 11 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Table 18 Coding of interrupt signals Clock tick interrupt generator 2 I I I nterprocess communication module switch 1 February 03 12 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GnbH 4 Operating the Interface 4 1 Installation 1 2 3 For the installation procedure stay close to the following procedure 1 DER E a SPD 8 Before unpacking the interface be sure that your working area is discharged Switch of and unplug computer and VME crate Be sure that VME crate and Computer are on the same electrical potential Check all jumper settings Refer to section 3 1 for VMEMM There are no jumpers on PCIADA Insert PCIADA into your Computer and fix it by a screw Insert VMEMM into your VME Crate and tight the screws Connect the interface cable to PCIADA and VMEMM To install the PCI VME WINO95 driver follow instructions of the
10. ad ds e Pe Suae UE eH ae eke e ee gede sedes 13 4 INSIEATEBASPIONG Me oid M edes eie eui Msn de SEI Lhe ake AR EE SA pss ek A 13 4 2 INITIALIZING THE INTERFACE ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ener nn ee n nsns ee ee ee usines iss use a ase enenatis ese ese ese uh e utu ee 13 4 3 MME ACEESS 73 nette tte ese Ge De secus ite eC DE Dee Ed LR on Nt tat ee DTE EET Meer De ied 14 4 4 INTERRUPT HANDLING His EG EG Ee ced et GE EG Suc ER cies tet EG ES NS es tet deles iu cede Eg 15 4 5 UNINSTALLING THE INTERFACE ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee nsns nsns nsn esa sss ase sss ese ese ese ase ese sss eE ese ene ee nun 16 APPENDIX A LAYOUT OF PCIADA AND VMEMM e ee ee ee ee ee se se seen se ee es se se ee ese aee ee Ge eese ease eese toas ee eese EG 17 APPENDIX B POWER REQUIREMENTS OF PCIADA ee ee ee ee ee eee se ee es se ge ee es se ee ee eg se ee es see s ee en ee ee see ee essa a 18 APPENDIX C ACCESS TIMES issie os ese ova de de eo Vea o Ewa e de esse de goes dose os oge Dee de ee geen bee de Ee ord gegee de gees ee bee 18 List of figures FIGURE 1 FRONT PANEL OF VMEMM6 AND VMEMMB ees ee ee se se se se ee ee ee ee ee ee ee ee ee ee ee ee ee ee nr rennen 5 FIGURE 2 LOCATION OF JUMPERS OF VMEMM e iese see ee se se se se ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee nnn 6 FIGURE 3 INITIALIZATION OF THE VME INTERFACE ee ee se se se se se ee ee
11. connected Table 3 The User I O Register CNTRL LCR base address 0x50 To enable access to VMEMM write 0x4184 into CNTRL 0x4084 to disable do not modify 000100 b 6 USER 1 02 Type must always be 0 Hem I7 USER 1 02 Direction must always be 1 output yes yes E USER VO2 output 0 disable access to VMEMM 1 enable pe access 9 USERVO3 Type must alwaysbe0 lys yes 0 10 USER 1 03 Direction must always be 0 input lyes yes 10 1 USER 1 03 Input 0 VMEMM failed 1 VMEMMOK _ yes no 0 February 03 3 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH 2 3 Timeout An Access Timeout is implemented in the PCIADA interface which is currently set to about 35 us If the VMEMM is switched of or disconnected during an access timeout causes an Interrupt 2 February 03 4 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH 3 The VMEMM board VMEMM o A24 016 MASTER MODUL reser Connector 50 pol O Co Frontpannel 3U Frontpannel 6U MASTER MODUL Figure 1 front panel of VMEMM6 and VMEMMG 3 1 Jumper Settings VMEMM can be operated as a VME master or slave module which is controlled by the SC jumper Table 4 Insert VMEMM into slot 1 if it should work as VME Master Jumper position can be read out by VMEMM STATUS Table 4 Sett
12. ead out from PCR Table 1 Basic values of the PCI Configuration Register PCR Vendor ID Ox10B5 Device ID 0x9050 Subsystem Vendor ID 0x9050 Subsystem Device ID 0x1167 During PCI setup PCIADA calls for three different memory areas 1 54 Byte Local Configuration Register LCR of the I O area Different control status register and base addresses are available in the LCR Note If no LCR is available in the I O area please refer to the LCR in the memory area 2 LCR in the memory area 8 kByte of the memory area for direct access to VME and the local VMEMM memory area Major LCRegisters Base Addresses for the memory areas described in section 2 1 will be available after booting of the computer They can be obtained via BIOS from the PLX chip Most important are The Interrupt Control Status Register INTCSR handles interrupts of the VIC68A chip installed on VMEMM interrupts of PCIADA itself PCI interrupts and software interrupts Sources for the VIC68 A interrupt which are summarized in the INTERRUPT 1 bits are l seven interrupt requests of the VME bus Mailbox interrupts in the VICO68A chip by a second VME Master interrupts caused by a successful interrupt generation interrupts caused by SYSFAIL or ACFAIL bus timeout interrupt arbitration timeout interrupt VIC68A timer interrupts sl On op PAR 0E OBS interrupt caused by a manual reset February 03 2 00423 A0 User s Manual PCI VME W Ie Ne R Ple
13. he button Interrupt information of the VIC068A chip are stored in the VMEMMIRQ status register An interrupt request sets DO to 1 The request which has highest priority is encoded in D3 to D1 Note The index of the corresponding interrupt vector can be calculated very fast since no shift of VMEMMIRQ shift is necessary Table 10 Register VMEMMIROStatus 15 4 Oye jm OT 3 1 limemuptlevl tyes fo fo 0 0 no interrupt pending interrupt pending yes no JO The VMEVICRegister used to realize unresetable cycles If RMC DO is set signal AS Address Strobe will remain active for all following VMEbus accesses Bits D15 to D1 must be set to 0 Note VMEbus allows only single address unresetable cycles The address must not be changed during the unresetable cycle Table 11 Register VMEVIC SA must be EE IN DS IR RMC 0 No Read Modify Write Cycle 1 Read Modify Write Cycle Various settings of VMEMM are stored in register VMEMMStatus Refer to section 3 1 for WORD and Module Number February 03 9 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Table 12 Register VMEMMSStatus 15 12 module type Identification 0001b for VMEMM Modul 0001b module number coding of Jumpers J304 J301 SC status of system controller Jumper J402 WORD status of word path jumper J401 0 RMC status of VMEVICReg RMO lye no jo 3 5 VIC68A Register This section
14. in amp Baus GmbH The INTERUPT bits controls local events of the PCIADA card Interrupts are caused by 1 Timeout while accessing the VME bus Timeout is fixed to about 35 us 2 Cable is not connected 3 The VME power supply is not switched on 4 VMEMM access has not yet been switch on Before any access to VMEMM user bit I O 2 has to be set Table 1 describes all bits of the INTCSR Table 2 Contents of the Interrupt Control Status Register INTCSR Base address LCR base address Ox4c Local Interrupt 1 enable 1 enable 0 yes yes 1 disable source VMEMM 1 Local Interrupt 1 polarity 1 active high 0 yes yes active low 2 Local Interrupt 1 status 1 active 0 yes no not active 3 Local Interrupt 2 enable 1 enable 0 yes yes 1 disable Source PCIADA Local Interrupt 2 polarity 1 active high 0 yes es NS e m P Local Interrupt 2 status 1 active 0 PP acie mb PCI Interrupt enable 1 enable 0 yes E disable ones global 7__ Software Interrupt t L generate Interrupt __ yes_ yes_ hue EE ese cop The User I O Register CNTRL is divided into three parts which are summarized in Table 3 Part one USER I O1 must not be modified The register USER I O2 1 locks VMEMM during boot time to prevent any access of the Operating System 2 resets Interrupt 2 if it is deleted Register USER I O3 monitors the status of the VME crate on off and the cable connected not
15. ings of the SC jumper readable by VMEMM Status VMEMM works as System Controller default VMEMM works as Slave Choose different Board Numbers which are selected via jumper J304 to J301 if more than one PCIADA is installed in one PC February 03 5 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Table 5 Settings of the Board Number BN Jumpers which can be read out by the register VMEMM Status BN3 BN2 BN1 Bits of BN BNO Low Bit D j beu value BN I VMEMM is available as a 6U and a 3U board Long word access is not possible for the 3U version J1 P1 does not exist The VIC068 A chip checks the WORD Jumper before a long word access Table 6 Settings of the WORD jumper It is readable via VMEMM Status I VIC Chip in word mode VMEMM3 default VIC Chip in long word mode VMEMM6 default 15 EMMx Ver 1x Figure 2 Location of jumpers of VMEMM VMEbus allows multiple masters to share the data transfer bus which needs a special communication between all master boards to organize data transfer Inter process communication are important for this communication The address of this reg
16. ister is set by the VME Short Address Jumper February 03 6 00423 A0 32 3 3 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Note Watch the setting of the VME Short Address The address range can not be masked An access by VMEMM itself will cause a BERR and will not be ended by DTACK Table 7 VME Short Address Jumper Note An inserted jumper means bit 0 A15 A14 A13 A12 ar JA10 A9 A8 VME Short Address I I I I VME Short 0xAA00 default Operation PCIADA accesses a region of the VMEMM memory directly This region is divided into four blocks 1 VMEMM VME addresses All to A31 and control signal RMC are stored here and VME reset is activated Signals VMEMM Stat IRQ Status and A11 to A31 are readable 2 VICO6SA This is the part of the VMEbus Interface Controller which controls the VMEbus 3 Interrupt Vector INTVEC An interrupt acknowledge cycle is stated if one byte of this area is accessed 4 VME Every time this area is accessed a VMEbus transfer will be started Address lines A11 to Al equals PCI address lines A11 to Al VME address lines A31 to A12 are stored in the VMEADR register Following sections describe each memory block in details VMEMM area The size of this block is 8 kByte and it is mapped into the PCI memory The PCI base address is defined by the BIOS during boot time February 03 7 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH
17. ith VME BUS Aquisition Time included Events VMEbus timeout local interrupt number 7 and front panel buttom pushed local interrupt number 6 are processed via local interrupts Timeout causes an interrupt number 7 and the bottom causes interrupt 6 For this reason it is necessary to setup registers LICRx Local Interrupt Control Register and LIVBR Local Interrupt Vector Base Register The upper 5 bits of the interrupt vector are stored in LEIVBR Lower bits codes the source layer of the causing interrupt Please refer to section 3 6 for further information Table 17 Register LICR VIC base address Ox3B Ox3F byte access only Interrupt Mask 0 clear 1 masked off 16 Polarity of input 1 high or rising edge use always a falling edge yes lyes 5 Edgeorlevelsensitive input 1 edge sensitive input use always edge yes yes 4 Autovectorenable Must be 1 LIVBR supplies vector yes ys 3 Interruptstatus interruptisasserted sjo 2 0 Interruptlevelto map always map to the same level as the input lys yes 3 6 Interrupts VMEbuss accesses causing a VMEbus timeout or a BERR signal are treated as a normal access by VMEMM But they result in a local interrupt number 7 which has to be checked by software Pushing the front panel button causes only a local interrupt number 6 AII specific reset functions have to be defined in the software The falling flank of input LI
18. ure 4 Steps to access the VME bus 4 4 Interrupt handling VME Interrupts can be handled in two different ways Either the software polls the corresponding interrupt register or they are converted into interrupts for the PCIADA host computer There are two different interrupt sources which cause a PCI interrupt 1 All VME Interrupts are summarized in Local Interrupt 1 Interrupt Priorities have to be defined in the VIC68A chip except for Interrupts with a certain VME priority which require a high local priority and the VME BUS Error which is fixed to local interrupt level 7 Each Local Interrupt 1 has to be followed by a readout of a byte interrupt vector Figure 5 2 The local Timeout Interrupt on PCIADA causes a Local Interrupt 2 The value is fixed on 35 us after the access was started The interrupt finishes the access resulting into an indefinite value February 03 15 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GmbH Figure 5 Handling of an Interrupt 1 4 5 Uninstalling the interface Figure 6 describes how to uninstall the interface Figure 6 Steps to uninstall the interface February 03 16 00423 A0 User s Manual PCI VME W Ie Ne R Plein amp Baus GnbH APPENDIX A Layout of PCIADA and VMEMM
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