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1. RAM message buffer The following table Registers of the SJA1000 lists these registers grouped according to their usage in a system the addresses are decimal values Note that some registers are available in PeliCAN Mode only and that the Control Register is available in BasicCAN Mode only Furthermore some registers are read only or write only and some can be accessed during Reset Mode only More information about the registers with respect to read and or write access bit definition and reset values can be found in the data sheet SJA1000 http www semiconductors philips com See also chapter Programming Hints for some general register settings TPMC810 User Manual Issue 1 3 Page 8 of 22 TEWS amp TECHNOLOGIES Register Address decimal PeliCAN BasicCAN N Type of Usage Register Name Symbol Mode Mode Functionality Mode MOD 0 Sleep Acceptance Filter Self Test Listen Only and Reset Mode selection Control CR 0 Reset Mode selection in BasicCAN Mode Elements for selecting different operation Command CMR 1 Sleep Mode command in modes BasicCAN Mode Clock Divider CDR 31 31 Set up of clock signal at CLKOUT pin 7 selection of PeliCAN Mode Comparator Bypass Mode TX1 pin 14 Output Mode Acceptance Code ACR 16 19 4 Selection of bit patterns for Mask AMR 20 23 5 Acceptance Filtering See DE EN ee Timing 0 BTRO 6 6 Set up of Bit Timin2. bus UO interface An on board termination option DIP switch is provided for each CAN bus channel to configure on board termination and pass through mode for the CAN bus Each channel can generate an interrupt on INTA The TPMC810 provides front panel I O via two DB9 male connectors and rear panel I O via P14 Optocoupler CAN Controller DC DC Converter SJA1000 Local Control Logic Optocoupler DC DC Converter CAN Controller SJA1000 Figure 1 1 Block Diagram TPMC810 User Manual Issue 1 3 Page 5 of 22 Technical Specification TEWS amp TECHNOLOGIES PMC Interface Mechanical Interface PCI Mezzanine Card PMC Interface Single Size Electrical Interface PCI Rev 2 1 compliant 33 MHz 32 bit PCI 3 3V and 5V PCI Signaling Voltage On Board Devices PCI Target Chip PCI9030 PLX Technology CAN Controller 2 x SJA1000 16MHz Philips CAN Transceiver 2 x TJA1050 Philips UO Interface Number of CAN Bus Channels 2 Isolated against each other CAN Bus Interface CAN High Speed 11898 2 UO Connector PMC P14 I O 64 pin Mezzanine Connector 2 x DB9 front panel connector Physical Data Power Requirements 150mA typical 3 3V DC 330mA typical 5V DC Temperature Range Operating 40 C to 85 C Storage 40 C to 125 C MTBF 404276h Humidity 5 95 non condensing Weight 76g Figure 2 1 Techn
3. FFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Figure 4 4 Configuration EEPROM TPMC810 10 TPMC810 User Manual Issue 1 3 Page 14 of 22 TEWS amp TECHNOLOGIES 4 4Local Software Reset The PCI9030 Local Reset output LRESETo is used to reset the on board local logic The PCI9030 local reset is active during PCI reset or if the PCI adapter software reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the local bus LRESETo asserted The PCI9030 remains in this reset condition until the PCI host clears this bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI interface is not reset TPMC810 User Manual Issue 1 3 Page 15 of 22 TEWS amp TECHNOLOGIES 5 Programming Hints 5 1 SJA1000 CAN Controller The SJA1000 clock input frequency is 16 MHz for both SJA1000 controllers See chapter SJA1000 CAN Controller Registers for an overview of all registers in the different modes Note that some registers are available in PeliCAN Mode only and that the Control Register is available in BasicCAN Mode only Furthermore some registers are read only or write only and some can be accessed during Reset Mode only A message which should be transmitted has to be written to the transmit buffer After a successful reception the microprocessor may r
4. IEN SZ The Embedded I O Company TECHNOLOGIES TPMC810 Isolated 2x CAN Bus Version 1 1 User Manual Issue 1 3 April 2004 D76810800 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek Germany 1 E Liberty Street Sixth Floor Reno Nevada 89504 USA Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 Phone 1 775 686 6077 Fax 1 775 686 6024 e mail info tews com www tews com e mail usasales tews com www tews com TPMC810 10 Isolated 2x CAN bus 2x DB9 front panel connector P14 Back I O TEWS amp TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0x029E that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP_RESET Access terms are described as W Write Only R Read Only R W Read Write R C Read Clear R S Read Set 2003 by TEWS TECHNOLOGIES GmbH Issue Descrip
5. RESS USAGE 1 0 ee eecieceene eee eeeeeteeeteeeeeaeesaeesaeesaeeseesneeenaeeaaes 12 FIGURE 4 3 PCI9030 LOCAL CONFIGURATION REGISTER ce eeceeeeeceeeeeeeeeeseesneesnaessaeenaeeeeeeaaes 13 FIGURE 4 4 CONFIGURATION EEPROM TPMC810 10 00 0 eee eeccceee eee eteeeeeeeeeeeesaeesaeesaesaessaeesaeeaaes 14 FIGURE 5 1 OUTPUT CONTROL REGISTER OCR OO 16 FIGURE 5 2 CLOCK DIVIDER REGISTER CDR OST 17 FIGURE 5 3 RX AND TX BUFFER IN BASICCAN MODE eee ee eeeeeeereeeeeeeeeeaeeeaeeseeeeeaeeeaeesneeenaeeaaes 17 FIGURE 5 4 RX AND TX BUFFER IN PELICAN MODE eee eeeeceeeeeee esse eeeeeeeaeeseeeseeeeeaeeseeeeeenaeeaaes 18 FIGURE 6 1 TRANSCEIVER SILENT MODE SETTINGS ue eee eceeereeee eee eeeeeeeeeeaeeseesaeenaeenaeeenaeeaaes 19 FIGURE 6 2 DIP SWITCH SETTINGS 000 eee ceneeene eee seas cena eee seae eee eteeeseeeseeeseaeesaeesaeeenaesnaeeaees 20 FIGURE 6 3 CAN CHANNEL INTERFACE AAA 20 FIGURE 7 1 DB9 MALE CONNECTOR X1 CHANNEL TI 21 FIGURE 7 2 DB9 MALE CONNECTOR X2 CHANNEL 3 21 FIGURE 7 3 PIN ASSIGNMENT P14 BACK UO CONNECTOR oo ceeceeceereeeseeeeeeeeeeeeesaeesneesaeenaeeeaeeeaaes 22 TPMC810 User Manual Issue 1 3 Page 4 of 22 TEWS S TECHNOLOGIES 1 Product Description The TPMC810 is a standard single width 32 bit PMC with two independent CAN bus channels isolated from system logic and from each other Two Philips SJA1000 CAN controllers CAN specification 2 0B supported are used CAN High Speed transceivers are used for the CAN
6. Software RGS t rau ccaccc cicccseecctecwecctcre exes cence ce entececiec naaa aa daadaa aa naaar a daaa aaao da aaaea Naaien 15 5 PROGRAMMING HIN TS scisiccisssstncieccstccsancesustensstucsoncetucseatssussonsedudsoassduatenssducteaastactede 16 5 1 SJA1000 CAN Controller E 16 6 CONFIGURATION R N Eeer 19 6 1 Transceiver Silent MOC cccsecceseceeseeeeesneeenseeeeeeeeescaeseseeeenseeeeeaeeeseaeesaseaeeneeseseaesaseaeenseaeeeneeeeas 19 6 2 DIP Switch Settings sects taste ete anataenn aasa aaaea ceca aa kaaa aa aa aaa aa aaea a atana eaaa aeaa 20 7 PIN ASSIGNMENT UO CONNECTOR ccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 21 TA Front Panel e DE 21 7 2 BACK VO at oarnein aeaaeae aeaaaee aaa aana aaa aoaaa aaa aana aaa aa eaaa eaaa anaana anaE 22 TPMC810 User Manual Issue 1 3 Page 3 of 22 TEWS amp TECHNOLOGIES Table of Figures FIGURE 1 1 BLOCK DIAGRANM eee eene cece cre cee cee eeae eee eeeeeeeeeseeeseeeseeeseeeseaeesaeesaeesaesaaeesaeseaeeeeseeees 5 FIGURE 2 1 TECHNICAL SPECIFICATION 00 0c eee ccee cere eene eee seer seer eeeeeseeeseaeeeaeeseeeseeesaeeseesaeseseeees 6 FIGURE 3 1 PCI9030 LOCAL SPACE CONFIGURATION ce ecceecees eee eeneeeneeeee eae eaeeeaeeeeeeneeseeeseaeeeaeen 7 FIGURE 3 2 CAN CONTROLLER REGISTER GPD ACE ecieeceeecenee ene enne cent eee eases tae seeseneeeeeeneaeeeaeen 8 FIGURE 3 3 REGISTERS OF GA 000 9 FIGURE 4 17 PCI9030 HEADER EE 11 FIGURE 4 2 PCI9030 PLD BASE ADD
7. ace TPMC810 User Manual Issue 1 3 Page 20 of 22 7 Pin Assignment I O Connector 7 1 Front Panel I O Pin 1 2 3 4 5 6 7 8 9 Signal N C LOW level CAN bus signal Ground channel 1 N C N C Ground channel 1 HIGH level CAN bus signal N C N C Figure 7 1 DB9 Male Connector X1 Channel 1 Signal N C 1 2 LOW level CAN bus signal Figure 7 2 DB9 Male Connector X2 Channel 2 TPMC810 User Manual Issue 1 3 TEWS S TECHNOLOGIES TEWS amp TECHNOLOGIES 7 2 Back I O P14 Pin Signal 1 N C 2 Ground channel 1 3 LOW level CAN bus signal IN channel 1 4 HIGH level CAN bus signal IN channel 1 5 Ground channel 1 6 Ground channel 1 7 LOW level CAN bus signal OUT channel 1 8 HIGH level CAN bus signal OUT channel 1 9 N C 10 NG 11 N C 12 N C 13 N C 14 N C 15 INC 16 Ground channel 2 17 LOW level CAN bus signal IN channel 2 18 HIGH level CAN bus signal IN channel 2 19 Ground channel 2 20 Ground channel 2 21 LOW level CAN bus signal OUT channel 2 22 HIGH level CAN bus signal OUT channel 2 23 Ground channel 2 24 NC 64 Figure 7 3 Pin Assignment P14 Back I O Connector TPMC810 User Manual Issue 1 3 Page 22 of 22
8. ceiver Silent Mode Settings Default value after power on is 0 operating mode TPMC810 User Manual Issue 1 3 Page 19 of 22 TEWS amp TECHNOLOGIES 6 2 DIP Switch Settings The following two figures show the DIP switch settings for one CAN channel Possible line configuration options for each channel are e On board Line Termination on off e P14 Bus Mode connected not connected and pass through on off The on board termination option for a CAN channel node input see P14 I O pin assignment is a 120 ohms split termination network For the pass through option the I O lines are passed through from the node input pins to the node output pins of the P14 I O connector see P14 Back I O pin assignment Switch Numbers Function Description 1 2 Line Termination ON 120 R line termination enabled OFF Line termination disabled 3 4 P14 Connection ON Incoming CAN bus connection enabled OFF Incoming CAN bus connection disabled 5 6 P14 Pass Through ON Outgoing CAN bus connection enabled OFF Outgoing CAN bus connection disabled Figure 6 2 DIP Switch Settings Front I O CAN Transceiver Back I O TJA1050 P14 3 CAN_H e Oe CAN H IN S4 CAN_L e d O O H CAN L IN 1 S2 S5 S6 CAN GND m CAN H OUT EC 120R aaa R _____ CAN_L_OUT WW CAN GND Figure 6 3 CAN Channel Interf
9. e space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the base address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the software must enable the PCI9030 for PCI I O and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9030 set bit 0 to 1 To enable PCI Memory Space access to the PCI9030 set bit 1 to 1 Offset in Config Description Usage 0x10 PCI9030 LCR s MEM Used 0x14 PCI9030 LCR s I O Used 0x18 PC1I9030 Local Space 0 Used 0x1C PCI9030 Local Space 1 Not used 0x30 Expansion ROM Not used Figure 4 2 PCI9030 PLD Base Address Usage TPMC810 User Manual Issue 1 3 Page 12 of 22 TEWS amp TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM The PCI base address for the PCI9030 Local Configuration Registers is PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in the PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI I O Space Offset 0x14 in the PCI9030 PCI Configuration Register Space Do not change hardware dependent bit se
10. ead the received message from the receive buffer and then release it for further use For register access two different modes have to be distinguished e Reset Mode e Operating Mode The Reset Mode see SJA1000 Control Register CR 0x0 for BasicCAN or Mode Register MOD 0x0 for PeliCAN bit Reset Request is entered automatically after a hardware reset or when the controller enters the bus off state see Status Register bit Bus Status The operating mode is activated by resetting of the reset request bit in the control register More information about the registers with respect to read and or write access bit definition and reset values can be found in the data sheet SJA1000 http Awww semiconductors philips com The SJA1000 Output Control Register and Clock Divider Register have to be programmed as follows SJA1000 controllers must be in Reset Mode Bit Symbol Description 7 OCTP1 11 Push Pull output stage 6 OCTN1 5 OCPOL1 0 Normal polarity 4 OCTPO 11 Push Pull output stage 3 OCTNO 2 OCPOLO 0 Normal polarity 1 OCMODE1 01 Test output mode bit reflection 0 OCMODEO 10 Normal output mode Figure 5 1 Output Control Register OCR 0x08 TPMC810 User Manual Issue 1 3 Page 16 of 22 TEWS amp TECHNOLOGIES Bit Symbol Description 7 CAN Mode 0 BasicCAN Mode 1 PeliCAN Mode 6 CBP 1 Bypass input comparator use RX0 only 5 RXINTEN 0 Disable
11. g communication 1 BTR1 7 7 Parameters Output Control OCR 8 8 Selection of Output Driver properties Command CMR 1 1 Commands for Self Reception Clear Data Overrun Release Receive Buffer Abort Transmission and Transmission Request f Status SR 2 2 Status of message buffers Basic elements for the CAN communication status of CAN Core Block Interrupt IR 3 3 CAN Interrupt flags Interrupt Enable IER 4 Enable disable of interrupt events in PeliCAN Mode Control CR 0 Enable disable of interrupt events in BasicCAN Mode Figure 3 3 Registers of SJA1000 TPMC810 User Manual Issue 1 3 Page 9 of 22 TEWS amp TECHNOLOGIES Register Address decimal PeliCAN BasicCAN N Type of Usage Register Name Symbol Mode Mode Functionality Arbitration Lost Capture ALC 11 Shows bit position where arbitration was lost Error Code Capture ECC 12 Shows last error type and location Error Warning Limit EWLR 13 Selection of threshold for generating an Error Warning Interrupt Seen D S RX Error Counter RXERR 14 Reflects the current value of comprehensive error the Receive Error Counter detection and See analyzing TX Error Counter TXERR 14 15 Reflects the current value of the Transmit Error Counter Rx Message Counter RMC 29 Number of messages in the Receive FIFO Rx Buffer Start Addr RBSA 30 Shows the current internal RAM address of the messa
12. ge available in the Receive Buffer Message buffers Transmit Buffer TXBUF 16 28 10 19 Receive Buffer RXBUF 16 28 20 29 Figure 3 3 Registers of the SJA1000 cont TPMC810 User Manual Issue 1 3 Page 10 of 22 PCI9030 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 PCI9030 Header TEWS amp TECHNOLOGIES EN Write 0 to all unused Reserved bits PCI Initial Values Register i EE writeable Hex Values 31 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 032A 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 028000 00 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFEOO 0x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI Cardbus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N 000A 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM N
13. ical Specification TPMC810 User Manual Issue 1 3 Page 6 of 22 TEWS amp TECHNOLOGIES 3 Local Space Addressing 3 1 PCI9030 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces PCI9030 PCI9030 PCI Size Port Endian Description Local PCI Base Address Space Byte Width Mode Space Offsetin PC Mapping Bit Configuration Space 0 2 0x18 MEM 512 8 BIG CAN Controller Address Space 3 Ox1C Not Used 4 0x20 Not Used 5 0x24 Not Used Figure 3 1 PCI9030 Local Space Configuration TPMC810 User Manual Issue 1 3 Page 7 of 22 TEWS amp TECHNOLOGIES 3 2 CAN Controller Register Address Space CAN CONTROLLER REGISTER SPACE pase Addressa Register Name Bi CAN Controller Channel 1 0x000 CAN Controller CH1 Address 0 8 0x001 CAN Controller CH1 Address 1 0x002 CAN Controller CH1 Address 2 8 0x07F CAN Controller CH1 Address 127 8 0x080 OxOFF Reserved CAN Controller Channel 2 0x100 CAN Controller CH2 Address 0 8 0x101 CAN Controller CH2 Address 1 0x102 CAN Controller CH2 Address 2 8 0x17F CAN Controller CH2 Address 127 8 0x180 Ox1FF Reserved Figure 3 2 CAN Controller Register Space 3 2 1 SJA1000 CAN Controller Registers The SJA1000 is controlled via a set of registers control segment and a
14. interrupts on TX1 output 4 0 3 clock off 1 Disable clock output not used 2 CD 2 0 1 CD 1 0 0 CD 0 0 Figure 5 2 Clock Divider Register CDR 0x1F The data to be transmitted on the CAN bus is loaded into the memory area of the SJA1000 called Transmit Buffer The data received from the CAN bus is stored in the memory area of the SJA1000 called Receive Buffer These buffers contain 2 3 or 5 bytes for the identifier and frame information dependent on mode and frame type and up to 8 data bytes e BasicCAN Mode The buffers are 10 bytes long see figure Rx and Tx buffer in BasicCAN Mode 2identifier bytes up to 8 data bytes e PeliCAN Mode The buffers are 13 bytes long see figure Rx and Tx buffer in PeliCAN Mode 1 byte for frame information 2or 4 identifier bytes Standard Frame or Extended Frame up to 8 data bytes Address Name Composition and Remarks Tx buffer Ox0A Identifier Byte 1 8 Identifier bits Rx buffer 0x14 Tx buffer 0x0B Identifier Byte 2 3 Identifier bits 1 Remote Transmission Request bit Rx buffer 0x15 4 bits for the Data Length Code indicating the amount of data bytes Tx buffer OxOC 0x13 Data Byte 1 8 Up to 8 data bytes as indicated by the Data Length Code Rx buffer 0x16 0x1D Figure 5 3 Rx and Tx buffer in BasicCAN Mode TPMC810 User Manual Issue 1 3 Page 17 of 22 TEWS amp TECHNOLOGIES Address Name C
15. omposition and Remarks 0x10 Frame 1 bit indicating if the message contains a Standard or Extended frame Information 1 Remote Transmission Request bit 4 bits for the Data Length Code indicating the amount of data bytes 0x11 0x12 Identifier Byte Standard Frame 11 Identifier bits 1 2 Extended Frame 16 Identifier bits 0x13 0x14 Identifier Byte Extended Frame only 13 Identifier bits 3 4 Frame type Data Byte Up to 8 data bytes as indicated by the Data Length Code Standard 0x13 0Ox1A 1 8 Extended 0x15 0x1C Figure 5 4 Rx and Tx buffer in PeliCAN Mode The whole Receive FIFO 64 bytes can be accessed using the CAN addresses 32 to 95 A read access of the Tx buffer can be done using the CAN addresses 96 to 108 TPMC810 User Manual Issue 1 3 Page 18 of 22 TEWS amp TECHNOLOGIES 6 Configuration Hints 6 1 Transceiver Silent Mode The CAN transceivers can be switched to Silent Mode in this mode the transmitter is disabled Pin S of the TJA1050 CAN transceivers is directly controlled by a GPIO output of the PCI9030 GPIO1 for channel 1 and GPIO8 for channel 2 The level on the GPIO lines can be changed by setting bit 5 GPIO1 or bit 26 GPIO8 in the GPIO Control Register offset 0x54 Value of GPIO1 8 Data PASTE 0 Transceiver is in high speed mode which is the normal operating mode 1 Transceiver is in silent mode transmitter is disabled Figure 6 1 Trans
16. tion Date 1 0 First Issue January 2003 1 1 Correction Configuration EEPROM April 2003 1 2 Correction Configuration EEPROM September 2003 1 3 Weight Added and Version April 2004 TPMC810 User Manual Issue 1 3 Page 2 of 22 TEWS S TECHNOLOGIES Table of Contents 1 PRODUCT DESCRIPTION ssssssnssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 5 2 TECHNICAL SPECIFICATION sisscssscscscsccsscccnccssencranesencwcnasencucnssencuenawencrenssoucsensencwancue 6 3 LOCAL SPACE ADDRESSIN e 7 3 1 PCI9030 Local Space Configuration ccccsccceseeseeeeneeeeeeseeeseaeeenseeeeeeeeescaeseseeeeneeeeseeeeeeseneneeaes 7 3 2 CAN Controller Register Address SpaCe s ssssssennseuneunnnunnnuunnnnunnnnnnunnnunnnnnnnnunnnunnnnnnnnnnnnnnnnnn nna 8 3 2 1 SJA1000 CAN Controller Hegtsiers seas eeeaeeseaeeseneeeseaeeneaeeeed 8 4 PCI9030 TARGET CHIP eo nnmnnn 11 4 1 PCI Configuration Registers PCR ssssssnssuunennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnna 11 AAA eine ET EE 11 4 1 2 PCI Base Address InitialiZation cccccessececsessececeeseeeeeeesaeeeseeaeeeesesaeeesseaeeeesseseeeeseaaes 12 4 2 Local Configuration Register LCR ccssccsseeceseeeseseeeeseeeeneeeeeeeeeescaesenneeenseeeseesesnaesaneeeseeneeeeas 13 4 3 Configuration EEPROM cccsecesecesseeeeseeeeneeeeeneeeesaaesennee ee eeeesaaesasaeeenseeeeeneeescaesaseeeenseaeeeaeeneas 14 4 4 Local
17. ttings in the PCI9030 Local Configuration Registers Offset from PCI Base Register Value Description Address 0x00 Local Address Space 0 Range OxOFFF_FEO0O CAN Controller Address Space 0x04 Local Address Space 1 Range 0x0000_0000 0x08 Local Address Space 2 Range 0x0000_0000 0x0C Local Address Space 3 Range 0x0000_0000 0x10 Local Exp ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000_0001 0x18 Local Re map Register Space 1 0x0000_0000 0x1C Local Re map Register Space 2 0x0000_ 0000 0x20 Local Re map Register Space 3 0x0000_0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0x1502_4120 0x2C Local Address Space 1 Descriptor 0x0000_0000 0x30 Local Address Space 2 Descriptor 0x0000_0000 0x34 Local Address Space 3 Descriptor 0x0000_0000 0x38 Local Exp ROM Descriptor 0x0000_0000 0x3C Chip Select 0 Base Address 0x0000_0081 0x40 Chip Select 1 Base Address 0x0000_0181 0x44 Chip Select 2 Base Address 0x0000_0000 0x48 Chip Select 3 Base Address 0x0000_0000 0x4C Interrupt Control Status 0x0041 Ox4E EEPROM Write Protect Boundary 0x0030 0x50 Miscellaneous Control Register 0x0078_0000 0x54 General Purpose I O Control 0x0224 96D0 0x70 Hidden Power Management data 0x0000_0000 select 0x74 Hidden 2 Power Management data 0x0000_0000 scale Figure 4 3 PCI9030 Local Configuration Register TPMC810 User Manual Iss
18. ue 1 3 Page 13 of 22 TEWS S TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the PCI9030 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data e Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values e Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 to OxFF Reserved See the PCI9030 manual for more information Address Offset 0x00 0x02 0x04 0x06 0x08 Ox0A 0x0C Ox0E 0x00 0x032A 0x1498 0x0280 0x0000 0x0280 0x0000 0x000A 0x1498 0x10 0x0000 0x0040 0x0000 0x0100 0x4801 0x0001 0x0000 0x0000 0x20 0x0000 0x0006 0x0000 0x0003 OxOFFF DNFEOO 0x0000 0x0000 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x1502 0x4120 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0081 0x0000 0x0181 0x0000 0x0000 0x70 0x0000 0x0000 0x0030 0x0041 0x0078 0x0000 0x0224 0x96D0 0x80 0x0000 0x0000 0x0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF 0x90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxA0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxBO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxCO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxE0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFO Ox
19. xt Cap PM Cap ID N 4801 00 01 0x44 PM Data PM CSR EXT PM CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID Y 23 16 00 00 00 06 0x4C VPD Address VPD Nxt Cap VPD Cap ID Y 81 16 0000 00 03 0x50 VPD Data Y 00000000 Figure 4 1 PCI9030 Header TPMC810 User Manual Issue 1 3 Page 11 of 22 TEWS amp TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9030 PCI Base Address Register 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byt
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