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1. 52 C iilino Plan IN Sui v S EET ECT 777 Introduction 1 Statement of Purpose The project goal is to develop a data logger video overlay that can be used in a car The final product should be able to acguire near real time engine data through the On Board Diagnostic Port installed in a car This product will also take video of a ride through the car s windshield with user supplied standard definition camera Next it will overlay OBD data onto the captured video and store it in a portable medium The video stored in the media should be in a computer readable video format like JPEG2000 Raw OBDII data should also be stored as a file in the storage media The driver can select playback video on the spot with overlay or replay the video with data at a time later This product will aid in automotive racing and tuning by being more intuitive for driver s to use and have better functions than existing products on the market 2 Benefits and Features Currently products like Dashware create a data video overlay AFTER a user uploads their video and data to a home computer This feature is not suitable for amateur racers because they may need to review video and data immediately after a race Also this style of operation makes system set up difficult because they cannot test their logging systems in real Our logger so2. Regis enables ter Data received Last instructi Converted data Register Control Converter Bank 2 bytes received bits to video interface Data received from ELM 2 bytes Figure 2 OBD Block diagram Basys2 Development FPGA Board BOOTLOADER Figure 3 Bootloader Block diagram FPGA or MCU ALFAT SD Storage Media Card Writer SD Card STORAGE MODULE Figure 4 Storage Module Block diagram YCrCb to RGB Converter YCrCB Dat YCrCb Register Bank deo In RGB Data Data from OBDII Interface parameter sent signals Address Sprite Data Sprite ROM Figure 5 Video Display Module Block diagram Converter Converter DC DC DC DC Converter Converter E Figure 6 Power Module Block diagram You have described each module and what it does but you have not described the inputs and outputs of each model In other words you have not described how each module interfaces with the others For example you can write The power supply module receives an input from a user controlled switch and outputs a 5V DC supply voltage for the rest of the blocks The power supply module contains a converter 2 2 Block Descriptions 2 2 1 Overall Summary 1 Input Data Module This module obtains input data such as information from the OBD II and the video images from the camera The module then converts them into digital form using a
3. To make sure the data is written to a file the file must be flushed or closed when done or there will be a risk of losing data or corrupting the file system if the storage media was removed or if there was a power loss e F Flush the data of an opened file This command is useful to make sure all data are physically saved in the media e C Close file This command issues flush internally and then release the file handle The flowchart for WRITE operation is as follows 15 To store a file on an SD card Device ALFAT neutral No Power on Yes Hold reset pins lo gt go to reset state Select UART interface Set reset pins hi Wait 50ms Yes Send initialize command Successful Yes Send O open command Successful 16 2 2 5 Display Module Software Video is inputted into the module from the ADC chip as luma and chroma data which is stored in a register This data is then converted to the RGB color space and is sent to the VGA Controller The data from the OBDII module is also sent to the VGA Controller which uses a ROM to call upon and display the correct character sprites Both the raw RGB video data and that of the video with overlaid data are outputted YCrCb Register Bank Description 1 byte is sent from the ADC at one time but the information changes between luma value and the chroma value which is two bytes There are 3 registers then to hold the last value sent
4. Device Handbook Volume 1 p 356 For our design the AS scheme will be used since it has the ability to configure the device at a high frequency 40M HZ 10 Figure 13 3 Single Device AS Configuration 1 Voc 1 Notes to Figure 13 3 1 Connect the pull up resistors to a 3 3 V supply 2 Cyclone II devices use the ASDO to ASDI path to control the configuration device 3 nCEO pin can be left unconnected or used as a user 1 O pin when it does not feed another device s nCE pin Figure 8 Single Device AS Configuration Cyclone II Device Handbook Volume 1 p 362 The EP2C35 essentially goes through 3 states RESET CONFIGURATION and INITIALIZATION before USER MODE as depicted below CONFIGURATION INITIALIZATION USER MODE Figure 9 Cyclone II device configuration states 11 The EP2C35configuration flowchart is as follows Device EP2C35 in neutral Power on reset Successful Yes Enter configuration mode Choose configuration scheme AS FPGA enables config device Basys2 Successful Yes FPGA sends command and address signals to Basys2 Successful 12 2 2 4 Storage Module After the video is processed with the overlaid data it will be stored on a storage device We ll choose the Transcend 16 GB SDHC Class 10 Flash Memory Card as our storage device To simplify the process of writing the file to disk which involves writing complex memory card and USB drivers
5. Verification 3 1 Reguirements 3 1 1 Reguirements Summary 3 1 2 Verifications Summary 1 Input Module The video input can be tested simply by displaying the image from the camcorder onto a screen The latest OBD II information will be stored in a register so we can display the contents of the register onto the screen to be sure they are correct If possible we will use an OBD II simulator to verify our measurements The signal inputs and outputs will be verified with a logic analyzer to ensure accuracy 2 Display Module We will verify that the real time video is displayed on our screen 3 Power Module We will do a simple check to see if the power supply supplies the expected voltage and that the circuit stays powered on during an extended period of time Your verifications lack detail You need to explain exactly how you will test the requirement How will you power the device during testing What equipment will you use to probe the output What is a proper output What should the inputs to the module be How will you supply these inputs 3 1 3 Input Module Requirements Verifications Camcorder Camcorder 1 Output video signal is analog SD NTSC M 1 Ensure analog source the camcorder is powered on and output is enabled by signal MAX9526 a Power the camera and check that it 2 Output video is ITU R 656 uncompressed outputs a proper signal digital video MAX9526 3 Ensure that the ADC chi
6. and manipulate buggy file system we ll use the ALFAT OEM Board FAT32 SD card writer from GHI Electronics Figure 10 ALFAT OEM Board ALFAT SoC Processor User Manual p 45 The ALFAT SoC processor gives the FPGA a simple way to access storage medias such as SD cards and USB Mass Storage devices in a very short time Its key features are as follows e Long File Name supports e FATl6andFAT32 systems 13 e Friendly user interface through UART SPI 126 e No limits on media size file size or file folder count e Up to 8 simultaneous file access For our design we choose to implement it using the UART interface A simple schematic of how Host MCU UART SPI or I2C interface the ALFAT SoC interacts with other devices is USB Mass as follows Storage lt Device 1 USB Mass Storage Device 2 SD SDHC MMC Figure 11 ALFAT 50C interface ALFAT SoC Processor User Manual p 5 After power up the Host MCU our FPGA board controls the ALFAT SoC by sending in commands in human readable ASCII format The command list is as follows Command Description 2060 I LI lt Get version number Low power Initialize Real Time Clock Set current time and date Get current time and date Change Baud rate Enable echo Read status register Test media Get free size Initialize directory list Get next directory entry Format Command Descrip
7. data from the FPGA and routes decompressed output back to the FPGA so that video can be routed to other entities c FPGA The integrated circuit that will be used to design the digital system to process the images and data obtained from the OBD II This block obtains video from the camera and data from the OBD II process them and routes signal through a video compressor decompressor FPGA also streams processed to a storage device the MMC and controls data display for the attached TFT screen 3 Storage Module This module receives the overlaid video from the FPGA and control module and stores it on a storage device for later use A compact flash MMC may be used as the storage device User can also replay video from the storage medium a SDHC Flash Memory Card The flash memory data storage device where the video and data obtained will be stored This block obtains the processed video and data from the FPGA b USB It is possible to achieve higher storage speeds with an FUSB PHY chip over USB interface This item may be used depending on time remaining for project completion 4 Display Module This module displays the overlaid video on a LCD screen from storage through the FPGA control block a TFT Display The LCD display where the processed video obtained from the FPGA will be displayed 5 Power Module This module supplies power to the FPGA and Control Module 2 2 2 Input Module OBD II Interface Instruction Regi
8. is to be done by All Research is not sufficient for an entire week for one person Neither is ordering parts You should not have any to be decided weeks You need to create a plan for the semester If this plan changes that is fine But at the least you need to set out a course of action 4 2 Schedule Week Task Description Group Members 9 16 Proposals Due Software design for storage and boot loader Tung Do Software design for OBD II and ITU R BT 656 Nick Greenway 9 23 Design Reviews Sign up Closes 9 30 Design Reviews Order storage interface Test OBD II interface Board layout order components 10 7 Software development for Boot loader Software development for Video interface Submit board for fab 10 14 Test boot loader Test video interface Assemble the boards 10 21 Individual Progress Reports Due Test overlaid video on storage device Verify correctness of OBD II data obtained Test assembled boards Tung Do Nick Greenway Andrew Wesly Tung Do Nick Greenway Andrew Wesly All Nick Greenway Andrew Wesly Tung Do Nick Greenway Andrew Wesly 50 11 4 Mock up Demos and Mock Presentation Sign up closes Mock Presentation Control Slides Mock Presentation Test Slides Nick Greenway Mock Presentation Design Slides Andrew Wesly 11 11 Last Day to Reguest 1 Revision PCB Fabrication 21 Final software testing Final software testing Nick Greenway Assemble everything in an enclosure
9. 0 LYDS170n 10 LVDS169p DQ2B6 DQ5B6 10 LV DS169n DQ2B5 DQ5B5 10 LVDS168p DQ2B4 DQ5B4 10 LVDS168n DQ2B3 DQ5B3 10 LVDS167p DQ2B2 DQSB2 10 LVDS167n DO2B1 D05B1 10 LVDS166p DQ2BO DQSBO 10 LVDS166n 10 LVDS165p DPCLKS DOS2B DPCLKS DOS2B ec 10 LYDS165n 10 LVDS200n IO LVDS200p DMIB _ IO LYDS199p DQIB7 10 LVDS199n DQIB amp 10 LYDS198p DQIBS _ IO LVDS198n DO1B4 10 LVDS197p CDPCLKYDOSIBV CDPCLKYDOSIB 10 LYDS197n IO LVDS196p DQIB3 _ 10 LVDS196n 10 LYDS194p 10 LVDS194n DQIB2 _ 10 DOIB1 10 LVDS193p DQIBO _ 10 LVDS193n DM3B BWS43BV DM3B1 BWS 3B1 10 LVDS192p DQ3B8 DQ3B17 10 LVDS192n DQ3B7 DQ3B16 10 DO3B6 DO3B15 10 LVDS191p DQ3B5 DQ3B14 10 LVDS191n DQ3BA DQ3B13 10 LYDS190p DO3B3 D03B12 10 LVDS190n DQ3B2 DQ3B11 10 LVDS189p DQ3B1 DQ3B10 10 LVDS189n DQ3BIVDQ3B9 10 LVDS188p DPCLKY DQS3B DPCLKY DQS3B 10 LYDS188n 10 LYDS187p 10 LYDS187n 10 LYDS186p DMSB BWS 5By DM3BO0 BWS 3B0 10 LYDS186n 10 LYDS185p DOSB amp DO3B8 10 LYDS185n DQSB7 DQ3B7 10 LVDS184p DQSBGDQ3B6 10 LVDS184n DQSBS DQ3B5 10 LVDS183p DQSBA DQ3B4 10 LVDS183n DQSBYDQ3B3 10 DQSB DQ3B2 10 VREFBSNO 10 LVDS182p DOSB1 DO3B1 10 LVDS182n DQSB DQ3BO 10 LVDS163n 10 LVDS162p 10 LVDS162n 10 LVDS161p DMOB _ 10 LYDS161n 10 LVDS160p DQOB7 _ 10 LVDS160n DQ0B6 _ 10 LVDS159p DQOBS _ 10 LVDS159n DQOB4 _ 10 LVDS158p
10. 150 150 150 150 150 150 150 150 150 150 Input Rate Limit Approx Min Output Rate Approx Max Output Rate Active Resolution Compressed Data Compressed Data Interface Compression Mode MSPS Mbps Mbps 34 Figure 37 Maximum Pixel Data Input Rates for 121 Ball Package ADV212 Datasheet p 32 44 According to the table for a VDATA irreversible 10 bit data with an input of 48 Msps it is guaranteed to have the output rate in the range of 98 150 Mbps With our input coming in at a rate of 4 5Msps the ratio of the actual input rate to the input rate limit is 4 5 0 09375 48 This gives us a new range of output rate of 98 150 Mbps 0 09375 9 2 14 Mbps OBDII Parameters The OBDII sends one or two bytes of information which then need additional calculations to determine the correct values of the parameters These are done with the following eguations where A denotes the first byte of data and B denotes the second if there is a second data byte Temperature Data 40 degrees Fuel Pressure Data A 3 kPa Engine RPM Data A 256 B 4 rpm Vehicle Speed Data A km hr Throttle Position Data A 100 255 45 You have five modules in your block diagram but only 3 modules in the reguirements and verification section There should be a 1 to 1 mapping between each module in your block diagram and a reguirement verification plan III Reguirements and
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12. Andrew Wesly 11 18 Thanksgiving Break Last day to Reguest Final Revision PCB fab 11 25 Demo and Presentation Sign up closes gt gt a Final tests and verifications Final tests and verifications Nick Greenway Final tests and verifications Andrew Wesly 12 2 DemosandPreentaios Demo Final Paper Intro amp Conclusion Presentation Final Paper Testing amp Verification Demo Final Paper Design Procedure 12 9 Presentations Checkout Final Paper Lab Notebooks Lo Final Paper amp Notebook review and hand in Final Paper amp Notebook review and hand in Final Paper amp Notebook review and hand in 4 1 Contingency Plan In case of exorbitant pcb costs or a crunch for time the following contingency plan may be executed to deliver on proposed Automotive Racing Video Data Logger Replace FPGA IC MAX9526 ADC IC RS232 MODULE and CONTROL switches with Altera DE2 board Modify power supply module to supply 9V to development board Connect ALFAT module to board OBDII module to board 51 Create TFT display connections Possibly implement JPEG2000 encoder decoder Frame rates may be as low as 1fps References 78SR 2 Amp Series Murata Mansfield MA 2009 Online Available http www murata ps com data meters mpm 78sr 2a a00 pdf ADV212 Rev B Analog Devices Norwood MA 2010 Online Available http www analog com static imported files data sheets ADV212 pdf ALFAT SoC Process
13. Automotive Racing Video Data Logger ECE445 Fall 2012 Design Review J TA Igor Fedorov October 1st 2012 Contents IV I PP rc Dias 22 Block Desert 008 ar eb ataq 224 Overall SUIIIAEV I 225 FPGA and Control Module ns 224 SOGE Mod l 23 5 Display Taa qe eee 2249 PO EE M Odile 23 Schematics of itid 24 Simulations and Calculations ies ot a Requirements and 3 1 Requirements 110911018 nera tax ote adve bids STI R quite ments Summary sr n ons Ein oen ete as desde 22 22 Verifications 5 ALS 3 04 FPGA and Control Module uyu uuu a u 353 50206 feat Do Display Module Sali Ja 3 2 Tolerance kista Lat uwa posa gt _ _ _ _ _ _ Cost and schedule ES V dur NE ARCOT ANIIS
14. DQOBY_ IO LYDS155n DQOBO _ lie 10 LVDS154p CDPCLKYDQSOB y CDPCLK YDQSOB 10 LVDS154n 10 LVDS179p DM4B DM5B1 BWS 5B1 10 LVDS179n DOSB17 IO LVDST78p DQ4B7 DQ5B 16 lt 8 IO LVDS178n DQ4B6 DQ5B 15 i 10 LVDS177p DPCLK3 DQS5B DPCLK3 DQSSB 10 LVDS177n IO LYDS151n fa EP2C35F672C6N EP2C35F672C6N D VV gt TK v A A A A m AYO A 4 P P n A A Da WERT gt 5 95 9 gt gt n V i gt P V Bor vz 212 15 8849 TE VV I W Aj Y W TAY A TAY n gt v A c M LX vy n VAT 1 EP2C35F672C6N S C 112 AE26 APR 114 AF12 I AEIS 2 AF25 __ 4_ B6 NH Km E IP H _I4 4 E am EI 6 6 E EP E JI E m pi Hi PB HO PIE R12 15 RI Mi M26 a 2 TH p TIS E E BEA 12 RA Ya R26 EAM apu US ABII VI9 16 W 19 5 1 VI4 LADO Er ADI4 E m ADI8 E AEI U L VCCA PLLI GNDA PLLI VCCD GND PLLI GND PLLI VCCA PLL2 GNDA PLL VCCD PLL2 GND PLL2 GND 12 VCCA PLL3 GNDA PLL3 VCCD PLL3 GND PLL3 GND PLL3 VCCA_PLL4 GNDA PLL4 VCCD
15. E HEADER 28 7 29 3 F 30 2914495 4 A 104 2 37 32 III IIIIIIII II III III 00 0 0 00000000 00000000000000000000000000000000 XII I III II 11 0190 III 111 III 000000000 000 00 0 0 0 0 00 0000400 00 4 00 0000007010 0001000170007 Figure 29 Top Level Schematic of Switches RS232 Display NET E e T t 1 7 HTT TV HTT TTS ET TUUTTI VISIT TIN FT TIT T TTT3 TT TTT N 4 um N 34 E CUART TXD Lx T UART RXD gt P 5 ADS tn 5 IX 33V M L lt 1 AN gt R W 0 LC Res iR 2 S csa Res KT CCDEYADE KI Yi Yi AAL H a AA Vo p jd Hi wi Gir wi Gl US FL UG K Win Kir Wee GT vi E m 1324 Van El Vin J up n Ui m 110 33V O UP DL D T Ci al a III Tad Ro Bl Ri BS Ri Di lt ze EP x Pi 10 LV DS26p DPCLK I DQSILY DPCLK VDOS1L EP2C35F672C6 IO LVDS77n 10 LVDS27
16. PLL4 GND GND PLLA EP2C35F672C6N EP2C35F672C6N A CLOCK CIRCUITRY SUBJECT TO CHANGE 9 30 12 CLK15 LVDSCLK7p INPUT CLK14 LVDSCLK7n INPUT CLK13 LVDSCLK6p INPUT CLK12 LYDSCLK6n INPUT CLK11 LYDSCLK5p INPUT CLK10 LVDSCLK5n INPUT CLK9 LVDSCLK4p INPUT CLK8 LVDSCLK4n INPUT CLK7 LVDSCLK3n INPUT CLK6 LVDSCLK3p INPUT CLK5 LVDSCLK2n INPUT CLK4 LVDSCLK2p INPUT CLK3 LVDSCLKIn INPUT CLK2 LVDSCLKIp INPUT LVDSCLKOn INPUT CLKO LVDSCLKOp INPUT NES M EP2C35F672C6N 39 JTAG Signals may or may not be used SA Li L FPGA TMS 5 gt 3 3V 3 3V O 3 3V O 3 3V 3 3V MI zz bee Zee I EP2C35F672C6N 1 2V V16 116 111 MI7 M17 L18 L17 L16 L11 40 2 4 Simulations and Calculations Color Conversion Calculations From Poynton s Introduction to Digital Video p 176 eguations 9 6 and 9 7 the formula to convert RGB to YCbCr signal is YCbCr T RGB offset where 65481 128 553 24 966 T 37 797 74 203 112 112 93 786 18 214 and 16 offset E 128 This equation can be rewritten as RGB 1 YCbCr offset where 0 00456621 0 0 00625893 T 12 10 00456621 0 00153632 0 00318811 0 00456621 0 00791071 0 Color Conversion Simulation Using the derived eguations we implement our co
17. ble http search murata co jp Ceramy image img A14X M07E1 pdf NDTS Series Murata Mansfield MA 2012 Online Available http www murata ps com data power ncl kdc ndts pdf OBD II UART Online Available https www sparkfun com products 9555 Recommendation ITU R BT 601 5 Studio Encoding Parameters of Digital Television for Standard 4 3 and Widescreen 16 9 Aspect Ratios 1995 Online Available http www intersil com content dam Intersil documents an97 an9728 pdf Single Output LSN 10A Models Murata Mansfield MA 2009 Online Available http www murata ps com data power lsn10a d5 pdf Single Output LSN W3 Models Murata Mansfield MA 2009 Online Available http www murata ps com data power lsn16a w3 pdf 53
18. for each of those There is also a counter that controls the enable for each register which is timed by the input clock Each of these registers then outputs that byte to the YCrCb to RGB converter 17 H CONTROL SIGNAL START OF DIGITAL LINE START OF DIGITAL ACTIVE LINE NEXT LINE EAV CODE BLANKING SAV CODE CO SITED CO SITED X X Y Y Y Y Y DIGITAL STREAM 4 268 4 1440 2 1716 FIGURE 1 BT 656 8 BIT PARALLEL INTERFACE DATA FORMAT FOR 525 60 VIDEO SYSTEMS Figure 13 BT 656 8 bit parallel interface data format for 525 60 video systems from AN9728 Application Notes YCrCb to RGB Converter Description the Y Cr and Cb values are all constantly inputted Then they are converted into the RGB color space The conversion calculations are explained in the next section Once the conversions have been performed the RGB values are sent to the VGA Controller as 3 separate bytes VGA Controller Description The VGA Controller will output information for each individual pixel going from left to right then up to down It will output the input for most of these pixels However at some points this entity will call upon the Sprite ROM which then sends back 8 data bytes each corresponding to 8 pixels on a single row of pixels For each pixel if the bit from the Sprite ROM is low then the video outputted will simply be the RGB value inputted However
19. he data rate transfer speed On a FUSB2805 data can be transmitted and receive at high speed 480Mbps full speed 12Mbps and low speed 1 5Mbps through a 12 bit SDR interface In other words 12Mbps is an achievable speed and data rate design calculations use this rate as a bench mark In this project we use the MAX9526 as our ADC to convert Analog Video into digital signal The MAX9526 is a 10 bit 4x oversampling 54Msps ADC with true 10 but digital processing To decrease bandwidth because of storage limitations however we will down sample the video signals twelve times We down sample by 4 to achieve a video rate of 30 fps After that we further down sample by 3 to achieve 10 fps In other words we will sample at a rate of 54 Msps 12 4 5 Msps The FPGA gets the digital video signal from at this rate from the MAX9526 ADC processes it overlays it with the data obtained from the OBDII and sends it to the ADV212 encoder The ADV212 has the following data input rates Table 23 Maximum Pixel Data Input Rates 121 Ball Package HDATA VDATA Irreversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Reversible Irreversible Irreversible Irreversible Reversible Reversible Reversible 8 bit data 10 bit data 12 bit data 16 bit data 8 bit data 10 bit data 12 bit data 14 bit data 8 bit data 10 bit data 12 bit data 8 bit data 10 bit data 12 bit data 150 150 150 150
20. if the value from the ROM is high then the pixel will be changed to a different color This will create characters on the screen Some of these will be constant to describe the parameters such as RPM air temperature etc Others will be determined by the integer values of the data sent from the OBDII These will be the numeric characters and an if then statement will be used to display the appropriate character sprite ROM Description This entity acts as a simple read only ROM which outputs prewritten data to the VGA depending on the address requested One address is read from at a time and one address is outputted at one time Each address and each line of data are both 1 byte each 18 2 2 6 Power Module The Automotive Racing Video Data Logger device gets power from the 12V car battery However 12V is higher than needed for our device so DC DC voltage converters will be included in the power module to step down 12V to other useful voltages Specifically here are the power reguirements for all the components from the device Voltage s needed Digilent Basys2 Development Board 3 5V 5 5V ALFAT OEM Board 3 3V FPGA board 3 3V 1 8 1 5V 1 2V TFT LCD display SV From the 12V car battery the voltage will be stepped down to 5V and then 5V will be stepped down one more time to get 3 3V to supply power to the ALFAT OEM Board the FPGA Board etc 3 3V will then be stepped down again to 1 8V and 1 5V to supply power
21. k that Vpp is between 1 425 and 1 575 V and that Ipp 1s between 55 and 65 mA using a multimeter Also we must check that Vppio 1s between 3 135 and 3 465 V and is between 40 and 50 mA Finally needs to be between 0 3 and 3 765 V and must be between 280 and 320 mA This can be checked by communicating with the chip through a CPU via a free software codec such as Kakadu First 0 400 must be written to the EIROIE at address 0x5 Then the IRO pin will go low and we will check that EIRQFLG 10 is set using the FPGA and a simple code We will also use the FPGA to read the application ID to ensure that the chip was correctly initialized KS50DWNO V1 F What is the proper clocking rate for the display How will you check the clocking rate What equipment will you need 47 6 Use a multimeter to ensure that Vcc 15 between 0 3 and 5 0V and Icc is between 25 and 35 mA Also Vpp must be between 3 0 and 3 6 V and pp has to be between 15 and 19 mA 3 1 7 Power Module Reguirements Verifications Power Supply enough voltage to power on the 1 Car outlet is live board 2 The board doesn t power off intermittently Supply constant power to the board 3 A multimeter will be used to check the The car voltage is stepped down correctly voltage output of each DC DC converter to to 5V 3 3V 1 8V 1 2V and 1 5V see if SV 3 3V 1 8V 1 2V and 1 5V are All the individual components power on achieved and wo
22. lor conversion on MATLAB as follows 41 function G B y 190 YCoCr2RGB Y Cb Cr sFunction to convert from YCbCr to RGB used for simulation Input checks IT YS 255 Yao C52255 Cb lt 0 C255 Creo error Invalid Input Range end Converting to fixed point max 255 Y Y max 2 7 Cb r Cb max 2 7 Ce pcc 27 New fixed point inputs i r CD E Cr s T matrix and offset used calculations T 65 4281 140 252 24 900 74 202 1127 112 18 212 offset 16 128 128 Inverting the T matrix 1 The final RGB map result rob Tinv YCbCr ortrset Converting the fixed point to RGB results rgb 1 2 7 2500202 mass 2986 3 277 Wa N Some results from this MATLAB code are as follows gt gt R G B YCbCr2RGB 128 128 128 R 0 3560 G 1 0389 B 0 5657 42 gt gt R G B R 0 5772 G 2 0269 B 0 0142 gt gt R G B R 0 1766 G 1 8229 B 0 0142 YCbCr2RGB 255 128 O YCbCr2RGB 255 128 64 43 Data Rate Our data capture rate is limited by our storage rates Maximum write speed for the storage module ALFAT SoC is only 1400 Kbytes s so there will be a need for storage device speed up and video capture down sampling The FUSB2805 transceiver can be soldered into the ALFAT SoC to increase t
23. lves this problem with the abilities to e Record video and create an overlay in real time and e Uselogger hardware to playback captured video e Capture standalone OBDII data According to a few internet reviews some users prefer to have a data logger record video with OBDII data overlayed on the screen whereas other users prefer to have raw video recorded and race data recorded separately Currently there are products like Track vision that record the raw data onto an overlay but do not allow for separate video OBDII streams Our product solves this problem by allowing the user to manually select a recording mode They can pick either OBD II on video overlay raw video recorded with an associated OBDII data file for later analysis We will also implement an intuitive interface for drivers to use with mechanical switches Interface with the data logger should be intuitive for fast set up times and can be done by feel Some products on the market reguire a computer to set up the logger which is not conducive for race conditions when time between race events is critical for success II Design 2 1 Block Diagrams Analog SDHC Flash Video N ADC Memory Card Storage Module FPGA and Cortrol I _ _ I I I JPEG2000 TET OBDII Decoder Display Encoder I I Input Module Display Module 1 N Power Figure 1 Top Level Block diagram Instruction Register k
24. n 00 a Sn DO2RSIDOIRS tjs 10 LVDS136n 10 LVDS115p DO2R4DO1R4 10 LVDS137p DO3R1 D03R10 10 LVDS114n DO2RI DO1R3 10 LVDS137n DQSRJDQSRI 1 lao 10 LVDS114p DQ2RYDQIR 10 LVDS138p DO3R3 DO3R12 Mr 10 LVDS113n DO2R DOIRI 10 LVDS138n DO3R4 D03R13 0 LVDS113p DOZRODQIRO 10 LVDS139p CDPCLKYDOS3RV CDPCLKYDOS3R Baz 10 LVDS112n 10 LVDS139n Ber 10 LVDS112p CDPCLKSIDOS2RY CDPCLKS DOS2R 10 LVDS140p 00315 003LI4 lac 10 LVDS140n DO3RA DO3R15 jay NOF 10 DOSRTIDOSRI6 Ray N 10 LVDS141p DO3R8 DO3R17 aya Tig IO LVDS141n DM3R BWS 3RV DM3RI BWS 3R 1 ert EI LES 10 KZ JA ABB LED 3826 5225 2 T 0 3 3V 075 win 026 A AA Tu io LVDsis7n ae 10 LVDS148p M 10 LVDS148n lo PLLA Up 1 T 10 on T 1 ATY 10 LVDS149p 10 LVDS149n lar 10 LVDSISQp CEO s gt 10 LVDS150n INIT DONE ja DONE EI loge EX EP2C35F672C6N EP2C35F672C6N 10 LVDS176p DPCLK4 DQS4By DPCLK4 DQS4B LI IO LYDS176n 10 DQ4BS DQSB14 10 LYDS175p DQ4BA4 DQSBI3 10 LVDS175n DQ4BYDQSBI2 10 LYDS174p 10 LVDS174n DQ4BJ DQSBI I 10 LVDS173p DO4B1 DO5B10 10 LVDS173n DQ4BO DQS5B9 10 LYDS172p 10 LVDS172n DM2B DMSBO BWS 5B0 lt IO LVDS171p DQ5B8 IO LVDS171n DQ2B7 DQ5B7 10 VREFB7NI 10 LVDS170p 1
25. n ADC and transmits this digital data to the FPGA a Analog Video The analog video obtained from the camera on the windshield The image will be sent to the ADC to be converted into digital form b ADC The Analog to Digital converter that converts standard definition analog video input into a digital form so it can be used by the FPGA ADC input is analog video which is converted to digital images and are then routed to the FPGA c OBD II The On Board Diagnostic system on a car is where information such as the MIL malfunction indicator light DTC diagnostic trouble code I M inspection and maintenance info etc can be extracted from We will focus on polling operating data like engine RPM temperature etc The information obtained from this block is sent to the FPGA 2 FPGA and Control Module This module is the brain of the entire circuit It receives the OBD II data and video images from the input module processes them overlays the data onto the video stream It then routes the overlaid video to the storage and display modules This entity also manages video stream compression decompression This block also boots the system a Bootloader The boot loader is a nonvolatile memory circuit and co processor that configures the FPGA for use when system 1s powered on b JPEG2000 Decoder Encoder A device that compresses decompresses digital video for extended storage and computer access This block receives processed video and
26. nd correct errors and to credit properly the contributions of others 10 to assist colleagues and co workers in their professional development and to support them in following this code of ethics Following the 9 code of the IEEE Code of Ethics 9 to avoid injuring others their property reputation or employment by false or malicious action We will make sure that the data logger device developed from this project will offer the users with data that is as accurate as possible and will not provide them with false information in order to avoid damaging that could occur to the users health their car or other properties IV Cost and Schedule 4 1 Cost Analysis a Labor Total x 2 5 50 hr 9000 22500 Nick Greenway 50 hr 9000 22500 Andrew Wesly 50 hr 9000 22500 67500 b Parts t Cost Elm Electronics ELM Electronics 23 50 23 50 Maxim Integrated 7 97 7 97 Sparkfun 54905 49 95 49 You need to have part numbers in your bill of materials 1 Eleetroniess Control Switches 6 Compnents 6 25 37 50 FPGA 149 50 149 50 Digilent Basys2 1 DigilentInc DigilentInc 100 00 0 Have Development Board used as bootloader GHI Electronics GHI Electronics 59 95 59 95 Display 6522 65 22 Total Labor Cost Total Parts Cost 67 500 791 59 Total Project Cost A task can only have one person in charge of it Therefore you cannot have a task which
27. or User Manual Rev 1 12 GHI Electronics Macomb Township MI 2012 Online Available http www ghielectronics com downloads A LFAT ALFAT 20S0C 20Processor 20User 20Manual pdf BT 656 Video Interface for ICs Intersil Milpitas CA 2002 Online Available http www intersil com content dam Intersil documents an97 an9728 pdf Charles A Poynton A Technical Introduction to Digital Video John Wiley amp Sons Inc 1996 p 175 176 Cyclone II Device Handbook Volume 1 Altera San Jose CA 2008 Online Available http www altera com literature hb cyc2 cyc2 cii5vl pdf Cyclone EP2C35 PCI Development Board Reference Manual Version Altera San Jose CA 2005 Online Available http www altera com literature manual rm pci dev bd cyclone2 ed pdf Digilent Basys 2Board Reference Manual Digilent Pullman WA 2010 Online Available https www digilentinc com Data Products BASYS2 Basys2 rm pdf ELM327 ELM Toronto Online Available http elmelectronics com DSheets ELM327DS pdf FS K50DWNO VI F Rev 2 Kentec Display 2011 Online Available http www kentecdisplay com uploads soft Products spec K50DWNO V1 F 01 pdf 52 IEEE Code of Ethics Online Available http www ieee org about corporate governance p7 8 html MAX9526 Rev 3 Maxim Integrated San Jose CA Online Available http datasheets maximintegrated com en ds MAX9526 pdf MPDTY Series Murata Mansfield MA Online Availa
28. p DPCLKQDQSOLY DPCLKQDQSOL 10 LVDS28n DMOLADMILI BWS IL1 10 LVDS29n _ DQILIT 10 LVDS29p DQOL7 DQILI6 10 10 LVDS30n DO0L amp DOILIS EP2C35F672C6 35 ALFAT OEM 1X16 SIGNAL PINS ux 7 lt 36 in 10 LYDS126n 10 LVDS126p DPCLKT DOSORV DPCLK7 DOSOR IC 7 10 LVDS125n DMOR DMIRUBWS IRI lt m 10 LVDS124n m AKL 10 LVDS127p DPCLK amp DQSIRYDPCLKGDQSIR Rar 10 LVDS124p DOORTIDQIRI6 sm PAKKO 10 LVDS127n Ears 10 LVDS123n 000M6001MI5 3 10 LVDS128p DQIRODQSRO 10 LVDS123p DQORS DQIR14 m ADDR 2 10 LVDS128n DQIRUDQSRI 10 LVDS122n DOOR4 DOIR13 ADDR ENCODE DECODE 10 DQIRYDQ3R2 10 LVDS122p DQORS DQIR12 ka ADDR 2 PINS 10 LVDS129p DQIRYDQSR3 asss 10 LVDSI21n DQOR2 DQIR11 Mo MLK A CLK PORTS MAY 10 LVDS129n fax 10 LVDS121p DQOR1 DQIR10 s M 3 NEED TO CHANGE MI 10 DQORO DQIR9 1 RD PINS 10 LVDS120n far CTRS 5 SSS 10 LVDS120p 0 LVDS131n DQIRVDQSRS Rz 10 VREFBSNI lt 5 0433V 10 LVDS132p 10 LVDS132n far 10 VREFBENO 10 DQIR DQ3R6 pian 10 LVDS133p DQIRT DQ3R7 lt 10 LVDS117n DM2R DMIROBWS 1RO far IO LVDS133n DQIRWDQSRS 10 LVDS117p DOIR8 IO LVDS134p DMIR BWSEIRDNGR BWSESRO Ber 10 DO2R7 D01R7 ae eus 10 LVDS116n DQORGDQIRG Fite MT 19 10 LVDS135n 0 10 LVDS115
29. p is powered at the 2 Check ADC chip power correct wattage 4 Configure the MAX9526 correctly 3 Check that the ADC is programmed This needs more detail How will you power the camera How will you check its output What is a proper output 46 WIG 09555 5 Inputdata signal is OBDII data from car 6 OBDII to ELM signaling is set to ISO 9141 2 for Asian make vehicles 7 Output data is OBDII info over RS 232 interface properly 4 Program the MAX9536 according to data sheet WIG 09555 5 Ensure car is powered on 6 Check automotive accessory power outlet a Check that the outlet is outputting 12 V 7 Verify ISO 9141 2 signaling scheme is selected 6 Make sure OBDII module is powered on and 15 set correctly Store sent information in aregister and use the hex display on the FPGA to check that the correct data is received and stored How will you check the ADC power Using a multimeter Oscilloscope What inputs must the ADC be supplied with 3 1 6 Display Module Reguirements Verifications ADV2 12 1 Displays decompressed video eguivalent to capture rate Video output size maximum of 800X480 resolution Ensure that the ADV212 is powered correctly Configure the ADV212 correctly ADV212 must be initiated properly K50DWNO VI F 6 Ensure the correct power wattage 1s being sent to the display 2 Ensure JPEG2000 video is decompressed and scaled properly 3 Chec
30. rk consistently Ensure each component is connected to its correct voltage supply by checking the voltage before connecting it to a component The tolerance analysis is incomplete You have described what tolerance range is acceptable for the ADC oscillator but you have not explained why the ADC oscillator is vital to your project Moreover you have not described how you will verify that this range of tolerances is acceptable 3 2 Tolerance Analysis Oscillator Frequencies Verify that the ADC oscillator crystal has a frequency of 27 MHz plus or minus 50 ppm 3 3 Ethical Issues The purpose of this project is to develop a data logger device for racer which helps them to better manage the condition of the car while racing With such function our device helps increase the safety and health of the driver which is consistent with the first code of the IEEE Code of Ethics 1 to accept responsibility in making decisions consistent with the safety health and welfare of the public and to disclose promptly factors that might endanger the public or the environment One of the factors that cause car accidents is system defects Our device helps prevent these kinds of accidents by giving drivers immediate information about the system s other car while also them with video of a driving car Throughout the development of the device we will follow the third code closely and only make claims and estimates based on real data acguired from o
31. ster Bank Description When a register is first initialized a 4 or 6 byte data signal is set depending on the instruction being sent If the enable is active then the most significant bit of the data signal is outputted Then the signal is shifted to the left by one bit and a counter increases by one This continues until the counter reaches the number of bits in the instruction Then the signal going to the control register becomes active indicating that the message has been sent This causes the state in the control register to change causing the enable to go low and the register to reinitialize to its original value Instructions we plan to use x0105 Engine coolant temperature Fuel pressure x010C Engine RPM x010D Vehicle speed x010F Intake air temperature x0111 Throttle position x0146 Ambient air temperature x015C Engine oil temperature Note These may be changed depending on parameters available for the car we test The one we use may not be compatible with some of the instructions listed Data Register Description When enabled this register receives data from the OBDII one bit at a time When a bit is received the register shifts the bits to make room for the next one Also a counter is used to keep track of the amount of data received Once all of the data is received a signal is sent to the register control to indicate such Notice that the counter counts to different values depending on whe
32. ther one or two bytes are being received Converter Bank Description When enabled the converter uses an arithmetic eguation to change the data received into the actual factual information from the engine The eguations used are explained in the calculations section These new values are then sent to the video interface Note that if the converter is not enabled its output is set to high impedance so that only one output is being transmitted at any time 2 2 3 FPGA and Control Module a Boot loader According to the Cyclone II Device Handbook Cyclone II devices use SRAM cells to store configuration data Because SRAM memory is volatile all configuration data will be lost once the device powers off Therefore there s a need to implement a boot loader to download configuration data to the Cyclone II devices every time the device powers up In our design we ll use the Digilent Basys2 development board as the FPGA s boot loader The Cyclone II or the EP2C35 processor supports 3 configuration schemes AS active serial PS passive serial and JTAG based configuration To select a configuration scheme the MSEL must be connected to the appropriate digital logic Table 13 1 Cyclone Il Configuration Schemes Configuration Scheme MSEL1 MSELO AS 20MH 0 0 0 O PS 1 1 9 Fast AS 40 MHz 1 9 JTAG based Configuration 2 Figure 7 Cyclone II Configuration Schemes Cyclone II
33. tion gt Z gt 0 lt Initialize MMC SD USB Open file to a free handle Write to a file Read from a file Flush file Close file File seek File tell Delete file or folder Find file or folder Copy From File to Another Rename file Fast Write to file SPI only Figure 12 ALFAT Command Set ALFAT 50C Processor User Manual p 19 14 The command will be send via a UART interface which uses 3 hardware signals e UART TX signal to send data out from ALFAT e UART RX signal to receive data to ALFAT e UART BUSY signal which should be monitored while sending data to ALFAT When hi no more data should be transmitted to ALFAT until it gets lo Besides commands are terminated with line feed and the user must read back the responses for each command properly and check whether the command was successful To write a file to a storage device we need the following commands Initialize and mount the storage device If this command is not called first the file system can be corrupted and other file related commands will fail e Open file for Read Write and Append and give write privileges to it If the file already existed it will be erased and rewritten e W Write to file through a file handle assigned to an open file with write mode This command is accomplished through 3 steps 1 Send W command with file handle and the data size 2 Wait til you get the acknowledge 3 Send the data
34. to logic signals on the FPGA board The power module block diagram from section 2 1 is copied below to illustrate how the car power supply will be converted to use on the device 12V 5V 3 3V 1 5V 1 8V POWER MODULE To other modules Figure 14 Power Module Block diagram 19 Overall the digital flowchart of the system is as follows Initialize ELM327 g Has data for a particular parameter been received from the ELM327 Place data in appropriate register Convert the data into the appropriate decimal values Organize information into a text or excel file Send that file to the storage device Is video being received from our camcorder Yes Convert video to RGB Interlay found values onto the screen with the original video in the background Compress video Send video to the storage device Send video to Compress video storage unit flash Request the next parameter from the ELM327 20 23 Figure 15 Overall Digital Flowchart 21 Your figures and diagrams need to be numbered and labeled with a description As they are now it is unclear to the reader exactly what is inside each figure BOOTLOADER HEADER 2 e lt gt 9 d a 22 SVIOHIIN AH 2848 Li Vd ATSAM AAHHONV GANDISAG SAHHOLIMS 10 6 9 510151524 2 juan
35. ur data logger 3 to be honest and realistic in stating claims or estimates based on available data Working with a data logger device the most importance factor is the accuracy of the information obtained from the system We will be honest and will not falsify the data acguired from our test procedures 48 After this project we will have learned a great deal about various real world industrial systems such as the On board Diagnostic OBD II system the SD Flash memory FAT 32 file system or the ITU R BT 656 protocol This will improve our understanding of these technologies and their applications and also improve our technical competence as directed in the 5 and 6 codes of the IEEE Code of Ethics 5 to improve the understanding of technology its appropriate application and potential 6 to maintain and improve our technical competence and to undertake technological tasks for others only if gualified by training or experience or after full disclosure of pertinent limitations Furthermore while working on the project we will build an environment that promote engineer professionalism which welcomes constructive and honest criticisms acknowledges errors assists peer workers with their professional and academic developments and credits appropriate contributions as cited in the 7 and 10 codes of the IEEE Code of Ethics 7 to seek accept and offer honest criticism of technical work to acknowledge a
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