ADXL345 (Rev. 0) - SparkFun Electronics
Contents
1. SEATING 3 PLANE Figure 20 14 Terminal Land Grid Array LGA CC 14 1 Solder Terminations Finish Is Au over Ni Dimensions shown in millimeters ORDERING GUIDE Measurement Specified Temperature Package Model Range g Voltage Range Package Description Option ADXL345BCCZ 2 4 8 16 2 5 40 C to 85 14 Terminal Land Grid Array LGA CC 14 1 ADXL345BCCZ RL 2 4 8 16 2 5 409 85 C 14 Terminal Land Grid Array LGA CC 14 1 ADXL345BCCZ RL7 2 4 8 16 2 5 409 to 85 C 14 Terminal Land Grid Array LGA CC 14 1 EVAL ADXL345Z Evaluation Board EVAL ADXL345Z M Analog Devices Inertial Sensor Evaluation System Includes ADXL345 Satellite EVAL ADXL345Z S ADXL345 Satellite Standalone 17 RoHS Compliant Part Analog Devices offers specific products designated for automotive applications please consult your local Analog Devices sales representative for details Standard products sold by Analog Devices are not designed intended or approved for use in life support implantable medical devices transportation nuclear safety or other equipment where malfunction of the product can reasonably be expected to result in personal injury death severe property damage or severe environmental harm Buyer uses or sells standard products for use in the above critical applications at Buyer s own risk and Buyer agrees to defend indemnify and hold harmless Analog Devices from any and all2. FIFO Mode Samples Bits Function Bypass None FIFO Specifies how many FIFO entries are needed to trigger a watermark interrupt Stream Specifies how many FIFO entries are needed to trigger a watermark interrupt Trigger Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event 0x39 FIFO STATUS Read Only D7 D6 D5 D4 D3 D2 D1 DO FIFO_TRIG 0 Entries Setting D7 D6 Mode Function 0 0 Bypass FIFO is bypassed 0 1 FIFO FIFO collects up to 32 values and then stops collecting data collecting new data only when FIFO is not full 1 0 Stream FIFO holds the last 32 data values When FIFO is full the oldest data is overwritten with newer data 1 1 Trigger When triggered by the trigger bit FIFO holds the last data samples before the trigger event and then continues to collect data until full New data is collected only when FIFO is not full Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode to INT1 and a value of 1 links the trigger event to INT2 FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring and a 0 means that a FIFO trigger event has not occurred Entries Bits These bits report how many data values are stored in FIFO Access to collect the data from FIFO is provided through the DATAX DATAY and DATAZ registers FIFO reads must be done in bu
3. SPI 3 Wire 14 SCL SCLK Serial Communications Clock Rev 0 Page 5 of 5 THEORY OF OPERATION The ADXL345 is a complete 3 axis acceleration measurement system with a selectable measurement range of 2 g 4 8 g or 16 g It measures both dynamic acceleration resulting from motion or shock and static acceleration such as gravity which allows the device to be used as a tilt sensor The sensor is a polysilicon surface micromachined structure built on top of a silicon wafer Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass Acceleration deflects the beam and unbalances the differential capacitor resulting in a sensor output whose amplitude is proportional to acceleration Phase sensitive demodulation is used to determine the magnitude and polarity of the acceleration POWER SEQUENCING Power can be applied to Vs or in any sequence without damaging the ADXL345 All possible power on modes are summarized in Table 5 The interface voltage level is set with the interface supply voltage Vpp yo which must be present to ensure that the ADXL345 does not create a conflict on the communication bus For single supply operation can be the same as the main supply Vs In a dual supply a
4. the processor must still respond to the activity and inactivity interrupts by reading the INT SOURCE register Address 0x30 and therefore clearing the interrupts If an activity interrupt is not cleared the part cannot go into autosleep mode The asleep bit in the ACT STATUS register Address 0 2 indicates if the part is asleep SLEEP MODE VS LOW POWER MODE In applications where a low data rate is sufficient and low power consumption is desired it is recommended that the low power mode be used in conjunction with the FIFO The sleep mode while offering a low data rate and low average current consumption suppresses the DATA READY interrupt preventing the accelero meter from sending an interrupt signal to the host processor when data is ready to be collected In this application setting the part into low power mode by setting the LOW POWER bit the BW RATE register and enabling the FIFO in FIFO mode to collect a large value of samples reduces the power consumption of the ADXL345 and allows the host processor to go to sleep while the FIFO is filling up USING SELF TEST The self test change is defined as the difference between the acceleration output of an axis with self test enabled and the acceleration output of the same axis with self test disabled see Endnote 4 of Table 1 This definition assumes that the sensor does not move between these two measurements because if the sensor moves a non self test related
5. 9 1 0 89 1 1 169 0 17 17 Register 0x32 to Register 0x37 DATAXO DATAX1 DATAYO DATAY1 DATAZO DATAZ1 Read Only These six bytes Register 0x32 to Register 0x37 are eight bits each and hold the output data for each axis Register 0x32 and Register 0x33 hold the output data for the x axis Register 0x34 and Register 0x35 hold the output data for the y axis and Register 0x36 and Register 0x37 hold the output data for the z axis The output data is twos complement with DATAxO as the least significant byte and DATAxI1 as the most significant byte where x represent X Y or Z The DATA FORMAT register Address 0x31 controls the format of the data It is recommended that a multiple byte read of all registers be performed to prevent a change in data between reads of sequential registers Register 0x38 FIFO CTL Read Write Samples Bits The function of these bits depends on the FIFO mode selected see Table 20 Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT SOURCE register regardless of which FIFO mode is selected Undesirable operation may occur ifa value of 0 is used for the samples bits when trigger mode is used Table 20 Samples Bits Functions D7 D6 D5 D4 D3 D2 D1 DO FIFO MODE Trigger Samples FIFO MODE Bits These bits set the FIFO mode as described in Table 19 Table 19 FIFO Modes
6. R 00000000 Z Axis Data 1 0x38 56 FIFO_CTL R W 00000000 FIFO control 0x39 57 FIFO_STATUS R 00000000 FIFO status Rev 0 Page 14 of 14 REGISTER DEFINITIONS Register OxOO DEVID Read Only D7 D6 D5 D4 D3 D2 D1 DO 1 1 1 0 0 1 0 1 The DEVID register holds a fixed device ID code of 0xE5 345 octal Register OX1D THRESH Read Write The THRESH_TAP register is eight bits and holds the threshold value for tap interrupts The data format is unsigned so the magnitude of the tap event is compared with the value in THRESH_TAP The scale factor is 62 5 mg LSB that is OxFF 16 g A value of 0 may result in undesirable behavior if tap double tap interrupts are enabled Register 0x1E Register Ox1F Register Ox20 OFSX OFSY OFSZ Read Write The OFSX OFSY and OFSZ registers are each eight bits and offer user set offset adjustments in twos complement format with a scale factor of 15 6 mg LSB that is Ox7F 2 g Register 0x21 DUR Read Write The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the 5 threshold to qualify as a tap event The scale factor is 625 us LSB A value of 0 disables the tap double tap functions Register 0x22 Latent Read Write The latent register is eight bits and contains an unsigned time value representing the wait time from the detect
7. SLEEP Measure Sleep Wakeup D7 D6 D5 4 D3 D2 D1 DO 0 ACT X ACT Y ACT 7 Asleep X Y 7 source source source source source source ACT_x Source and TAP_x Source Bits These bits indicate the first axis involved in a tap or activity event A setting of 1 corresponds to involvement in the event and a setting of 0 corresponds to no involvement When new data is available these bits are not cleared but are overwritten by the new data The ACT_TAP_STATUS register should be read before clearing the interrupt Disabling an axis from participation clears the corresponding source bit when the next activity or tap double tap event occurs Asleep Bit A setting of 1 in the asleep bit indicates that the part is asleep and a setting of 0 indicates that the part is not asleep See the Register 0x2D POWER_CTL Read Write section for more information on autosleep mode Register Ox2C BW_RATE Read Write D7 D6 D5 D4 D2 D1 DO 0 0 0 LOW_POWER Rate LOW_POWER Bit A setting of 0 in the LOW_POWER bit selects normal operation and a setting of 1 selects reduced power operation which has somewhat higher noise see the Power Modes section for details Link Bit A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is det
8. damages claims suits or expenses resulting from such unintended use 2009 Analog Devices Inc All rights reserved Trademarks ANALOG registered trademarks are the property of their respective owners D07925 0 5 09 0 DEVICES www analo g com Rev 0 Page 24 of 24
9. ignored during writes to the ADXL345 SPI For SPI either 3 or 4 wire configuration is possible as shown in the connection diagrams in Figure 3 and Figure 4 Clearing the SPI bit in the DATA FORMAT register Address 0x31 selects 4 wire mode whereas setting the SPI bit selects 3 wire mode The maximum SPI clock speed is 5 MHz with 100 pF maximum loading and the timing scheme follows clock polarity CPOL 1 and clock phase CPHA 1 CS is the serial port enable line and is controlled by the SPI master This line must go low at the start of a transmission and high at the end of a transmission as shown in Figure 5 SCLK is the serial port clock and is supplied by the SPI master It is stopped high when CS is high during a period of no transmission SDI and SDO are the serial data input and output respectively Data should be sampled at the rising edge of SCLK ADXL345 PROCESSOR 07925 004 Figure 3 3 Wire SPI Connection Diagram Table 9 SPI Timing 25 C Vs 2 5 V 1 8 V ADXL345 PROCESSOR 07925 003 Figure 4 4 Wire SPI Connection Diagram To read or write multiple bytes in a single transmission the multiple byte bit located after the R W bit in the first byte transfer MB in Figure 5 to Figure 7 must be set After the register addressing and the first byte of data each subsequent set of clock pulses eight clock pulses causes the ADXL345 to point to the next register for a read or wri
10. sensing element in the same manner as acceleration and it is additive to the acceleration experienced by the device This added electrostatic force results in an output change in the x y and z axes Because the electrostatic force is proportional to Vs the output change varies with Vs The self test feature of the ADXL345 also exhibits a bimodal behavior that depends on which phase of the clock self test is enabled However the limits shown in Table 1 and Table 12 to Table 15 are valid for all potential self test values across the entire allowable voltage range Use of the self test feature at data rates less than 100 Hz may yield values outside these limits Therefore the part should be placed into a data rate of 100 Hz or greater when using self test Table 12 Self Test Output in LSB for 2 g Full Resolution Axis Min Max Unit X 50 540 LSB Y 540 50 LSB Z 75 875 LSB Table 13 Self Test Output in LSB for 4 g 10 Bit Resolution Axis Min Max Unit X 25 270 LSB Y 270 25 15 2 38 438 15 Table 14 Self Test Output in LSB for 8 g 10 Bit Resolution Axis Min Max Unit X 12 135 LSB Y 135 12 15 2 19 219 15 Table 15 Self Test Output in LSB for 16 10 Bit Resolution Axis Min Max Unit X 6 67 LSB Y 67 6 15 7 10 110 15 Rev 0 Page 13 of 13 REGISTER MAP Table 16 Register Map Address Hex Dec Name Type Reset Valu
11. shift corrupts the test Proper configuration of the ADXL345 is also necessary for an accurate self test measurement The part should be set with a data rate greater than or equal to 100 Hz This is done by ensuring that a value greater than or equal to 0x0A is written into the rate bits Bit D3 through Bit DO in the BW RATE register Address 0x2C It is also recommended that the part be set to full resolution 16 g mode to ensure that there is sufficient dynamic range for the entire self test shift This is done by setting Bit D3 of the DATA FORMAT register Address 0x31 and writing a value of 0x03 to the range bits Bit D1 and Bit DO of the DATA FORMAT register Address 0x31 This results in a high dynamic range for measurement and a 3 9 mg LSB scale factor After the part is configured for accurate self test measurement several samples of x y and z axis acceleration data should be retrieved from the sensor and averaged together The number of Rev 0 Page 20 of 20 samples averaged is a choice of the system designer but a recom mended starting point is 0 1 sec worth of data which corresponds to 10 samples at 100 Hz data rate The averaged values should be stored and labeled appropriately as the self test disabled data that is Xsr orr Ysr orr and Zsr orr Next self test should be enabled by setting Bit D7 of the DATA FORMAT register Address 0x31 The output needs some time about four samples to settle after enabli
12. when selecting the range of operation for measuring self test In addition note that the range in Table 1 and the values in Table 12 through Table 15 take into account all possible supply voltages Vs and no additional conversion due to Vs is necessary If the self test change is within the valid range the test is considered successful Generally a part is considered to pass if the minimum magnitude of change is achieved However a part that changes by more than the maximum magnitude is not necessarily a failure Rev 0 Page 21 of 21 ADXL345 AXES OF ACCELERATION SENSITIVITY Az Ay 07925 021 Ax Figure 16 Axes of Acceleration Sensitivity Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis Xour 19 Your 00 Zour 0g LJ TOP GRAVITY Xour 0g Xour 09 Your 19 Your 19 Zour 09 Zour 09 1 LJ 19 Your 09 Zour 0g Xour 0g Xour 0g Your 04 Your 04 Zour 19 Zour 1g Figure 17 Output Response vs Orientation to Gravity Rev 0 Page 22 of 22 LAYOUT AND DESIGN RECOMMENDATIONS Figure 18 shows the recommended printed wiring board land pattern Figure 19 and Table 21 provide details about the recommended soldering profile 5 1 0500 0 5500 3 0500 5 3400 0 2500 gt 1 1450 0 2500 07925 014 Figure 18 Recomm
13. 10 3 te is the data hold time that is measured from the falling edge of SCL It applies to data in transmission and acknowledge times 4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal with respect to of the SCL signal to bridge the undefined region of the falling edge of SCL 5 The maximum ts value must be met only if the device does not stretch the low period ts of the SCL signal The maximum value for te is a function of the clock low time ts the clock rise time tio and the minimum data setup time tsmin This value is calculated as tema ts tio 7 Chis the total capacitance of one bus line in picofarads SDA SCL START REPEATED STOP 5 CONDITION START CONDITION 3 CONDITION 5 Figure 10 PC Timing Diagram Rev 0 Page 11 of 11 INTERRUPTS The ADXL345 provides two output pins for driving interrupts INT1 and INT2 Each interrupt function is described in detail in this section functions can be used simultaneously with the only limiting feature being that some functions may need to share interrupt pins Interrupts are enabled by setting the appropriate bit in the INT ENABLE register Address Ox2E and are mapped to either the INT1 or INT2 pin based on the contents of the INT MAP register Address Ox2F It is recom mended that interrupt bits be configured with the interrupts disabled preventing interrupts from being acciden
14. ANALOG DEVICES 3 Axis 2 9 4 0 8 o 16 2 Digital Accelerometer ADXL345 FEATURES Ultralow power as low as 40 pA in measurement mode and 0 1 pA in standby mode at Vs 2 5 V typical Power consumption scales automatically with bandwidth User selectable resolution Fixed 10 bit resolution Full resolution where resolution increases with g range up to 13 bit resolution at 16 g maintaining 4 mg LSB scale factor in all g ranges Embedded patent pending FIFO technology minimizes host processor load Tap double tap detection Activity inactivity monitoring Free fall detection Supply voltage range 2 0 V to 3 6 V voltage range 1 7 V to Vs SPI 3 and 4 wire digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command Wide temperature range 40 C to 85 C 10 000 g shock survival Pb free RoHS compliant Small and thin 3 mm x 5 mm x 1 mm LGA package APPLICATIONS Handsets Medical instrumentation Gaming and pointing devices Industrial instrumentation Personal navigation devices Hard disk drive HDD protection Fitness equipment GENERAL DESCRIPTION The ADXL345 is a small thin low power 3 axis accelerometer with high resolution 13 bit measurement at up to 16 g Digital output data is formatted as 16 bit twos complement and is acces sible through either a SPI 3 or 4 wire or
15. SDO pins are not internally pulled up or down they must be driven for proper operation Limits based on characterization results characterized with 5 MHz and bus load capacitance of 100 pF not production tested 3 The timing values are measured corresponding to the input thresholds Vi and Vix given in Table 8 Rev 0 Page 8 of 8 SCLK SDI d y Y le tspo ADDRESS BITS DATA BITS soo ACE Gra Sn ae am am Figure 5 SPI 4 Wire Write 07925 017 SCLK SDI ADDRESS BITS ar gt lt DATA cons Figure 6 SPI 4 Wire Read gt 4 8 lcspis Y Y ADDRESS BITS DATA BITS SDO NOTES 1 tspo IS ONLY PRESENT DURING READS 07925 019 Figure 7 SPI 3 Wire Read Write Rev 0 Page 9 of 9 With CS tied high to ADXL345 is in mode requiring a simple 2 wire connection as shown in Figure 8 The ADXL345 conforms to the UM10204 Specification and User Manual Rev 03 19 June 2007 available from NXP Semiconductor It supports standard 100 kHz and fast 400 kHz data transfer modes if the timing parameters given in Table 11 and Figure 10 are met Single or multiple byte reads writes are supported as shown in Figure 9 With the SDO ALT ADDRESS pin high the 7 bit C address for the device is 0x1D followed by the R W bit This translates to 0x3A for a write and 0x3B for a read An alternate address of 0x53 followed by the R W bit c
16. Scale Factor at Xour Your Zout 8 g 10 bit resolution 14 0 15 6 17 2 mg LSB Sensitivity at Xour Your Zour 16 g 10 bit resolution 29 32 36 LSB g Scale Factor at Xour Your Zour 16 g 10 bit resolution 28 1 312 34 3 mg LSB Sensitivity Change Due to Temperature 0 01 0g BIAS LEVEL Each axis 0 g Output for Xour Your 150 40 150 mg 0 g Output for Zour 250 80 250 mg 04 Offset vs Temperature for x y Axes 0 8 mg C 0 g Offset vs Temperature for z Axis 45 mg C NOISE PERFORMANCE Noise x y Axes Data rate 100 Hz for 2 g 10 bit or lt 1 0 LSB rms full resolution Noise z Axis Data rate 100 Hz for 2 g 10 bit or lt 1 5 LSB rms full resolution OUTPUT DATA RATE AND BANDWIDTH User selectable Measurement Rate 6 25 3200 Hz SELF TEST Data rate gt 100 Hz 20V lt Vs lt 3 6 V Output Change in x Axis 0 20 2 10 g Output Change in y Axis 2 0 0 20 4 Output Change z Axis 0 30 3 40 g POWER SUPPLY Operating Voltage Range Vs 2 0 2 5 3 6 V Interface Voltage Range Vs lt 2 5V 17 1 8 Vs V Vs225V 2 0 2 5 Vs V Supply Current Data rate 100 Hz 145 Data rate lt 10 Hz 40 Standby Mode Leakage Current 0 1 2 Turn On Time Data rate 3200 Hz 1 4 ms TEMPERATURE Operating Temperature Range 40 85 d WEIGHT Device Weight 20 mg 1 All minimum and maximum specifications are guaranteed Typical specifications are not guaranteed Cross axis sensitivity is defined as coupling between any t
17. TER START SLAVE ADDRESS WRITE REGISTER ADDRESS srART SLAVE ADDRESS READ NACK STOP SLAVE ACK ACK ACK DATA MULTIPLE BYTE READ MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS start SLAVE ADDRESS READ ACK STOP SLAVE DATA 07925 009 Figure 9 PC Device Addressing Rev 0 Page 10 of 10 Table 11 PC Timing Ta 25 C Vs 2 5 V 1 8 V Limit 2 Parameter Min Max Unit Description 400 kHz SCL clock frequency ti 2 5 us SCL cycle time t 0 6 us SCL high time t3 1 3 us tiow SCL low time ta 0 6 us tup sta Start repeated start condition hold time ts 350 ns tsu data setup time te 56 0 0 65 us tup data hold time t7 0 6 us tsu sta setup time for repeated start ts 0 6 us tsu sro Stop condition setup time to 1 3 us teur bus free time between a stop condition and a start condition tio 300 ns tr rise time of both SCL and SDA when receiving 0 ns tr rise time of both SCL and SDA when receiving or transmitting tu 250 ns tr fall time of SDA when receiving 300 ns te fall time of both SCL and SDA when transmitting 20 0 1 Cp ns te fall time of both SCL and SDA when transmitting or receiveing Cb 400 pF Capacitive load for each bus line 1 Limits based on characterization results with fsc 400 kHz and a 3 mA sink current not production tested 2 All values referred to the and the Vi levels given in Table
18. TIONS FOR MOUNTING The ADXL345 should be mounted on the PCB in a location dose to a hard mounting point of the PCB to the case Mounting the ADXL345 at an unsupported PCB location as shown in Figure 12 may result in large apparent measurement errors due to undampened PCB vibration Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the accelerometer s mechanical sensor resonant frequency and therefore effectively invisible to the accelerometer ACCELEROMETERS J PCB Fd MOUNTING POINTS Figure 12 Incorrectly Placed Accelerometers TAP DETECTION The tap interrupt function is capable of detecting either single or double taps The following parameters are shown in Figure 13 for a valid single and valid double tap event e The tap detection threshold is defined by the THRESH register Address Ox1D 07925 010 e The maximum tap duration time is defined by the DUR register Address 0x21 e The tap latency time is defined by the latent register Address 0x22 and is the waiting period from the end of the first tap until the start of the time window when a second tap can be detected which is determined by the value in the window register Address 0x23 e The interval after the latency time set by the latent register is defined by the window register Although a second tap must begin after the latency time has expired it need not finish b
19. an be chosen by grounding the SDO ALT ADDRESS pin Pin 12 This translates to 0 6 for a write and 0xA7 for a read If other devices are connected to the same I C bus the nominal operating voltage level of these other devices cannot exceed Von vo by more than 0 3 V External pull up resistors are necessary for proper operation Refer to the UM10204 Specification and User Manual Rev 03 19 June 2007 when selecting pull up resistor values to ensure proper operation Table 10 Digital Input Output Voltage Parameter Limit Unit Digital Input Voltage Low Level Input Voltage Vu High Level Input Voltage Vin Digital Output Voltage Low Level Output Voltage 0 25 x Vppyo V max 0 75 X Vooo V min 0 2 X Vooo V max Limits based on characterization results not production tested 2 The limit given is only for Vopvo lt 2 V When Vono gt 2 V the limit is 0 4 V max 07925 008 Figure 8 Connection Diagram Address 0x53 SINGLE BYTE WRITE MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS SLAVE ACK ACK MULTIPLE BYTE WRITE MASTER START SLAVE ADDRESS WRITE SLAVE ACK SINGLE BYTE READ REGISTER ADDRESS ac STOP Sd 1THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START NOTES 1 THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING MAS
20. at the RSS value of all axes must be less than THRESH to generate a free fall interrupt The scale factor is 5 ms LSB A value of 0 may result in undesirable behavior if the free fall interrupt is enabled Values between 100 ms and 350 ms 0x14 to 0x46 are recommended Register Ox2A TAP_AXES Read Write D7 D6 D5 D4 D3 D2 D1 DO Rate Bits These bits select the device bandwidth and output data rate see Table 6 and Table 7 for details The default value is 0x0A which translates to a 100 Hz output data rate An output data rate should be selected that is appropriate for the communication protocol and frequency selected Selecting too high of an output data rate with a low communication speed results in samples being discarded Register Ox2D POWER_CTL Read Write 0 0 0 0 Suppress TAP_X TAP_Y TAP_Z enable enable enable D7 D6 D5 D4 D3 D2 D1 DO Suppress Bit Setting the suppress bit suppresses double tap detection if acceleration greater than the value in THRESH_TAP is present between taps See the Tap Detection section for more details TAP xEnable Bits A setting of 1 in the X enable Y enable or Z enable bit enables x or z axis participation in tap detection A setting of 0 excludes the selected axis from participation in tap detection Register OxX2B ACT STATUS Read Only 0 0 Link AUTO
21. cur regardless of the INT_ENABLE register settings and are cleared by reading data from the DATAX DATAY and DATAZ registers The DATA_READY and watermark bits may require multiple reads as indicated in the FIFO mode descriptions in the FIFO section Other bits and the corresponding interrupts are cleared by reading the INT_SOURCE register Register 0x31 DATA FORMAT Read Write D7 D6 D5 D4 D3 D2 D1 DO SELF_TEST SPI INT_INVERT 0 FULL_RES Justify Range Setting D1 DO Frequency Hz 0 0 8 0 1 4 1 0 2 1 1 1 Register OX2E INT ENABLE Read Write D7 D6 D5 D4 DATA_READY SINGLE_TAP DOUBLE_TAP Activity D3 D2 D1 DO Inactivity FREE_FALL Watermark Overrun Setting bits in this register to a value of 1 enables their respective functions to generate interrupts whereas a value of 0 prevents the functions from generating interrupts The DATA_READY watermark and overrun bits enable only the interrupt output the functions are always enabled It is recommended that interrupts be configured before enabling their outputs Register Ox2F INT_MAP Read Write D7 D6 D5 D4 DATA_READY SINGLE_TAP DOUBLE_TAP Activity D3 D2 D1 DO Inactivity FREE_FALL Watermark Overrun Any bits set to 0 in this register send their respective interrupts to the INT1 pin whereas bits set to 1 send their respective interrupts to the INT2 pin All selec
22. digital interface The ADXL345 is well suited for mobile device applications It measures the static acceleration of gravity in tilt sensing appli cations as well as dynamic acceleration resulting from motion or shock Its high resolution 4 mg LSB enables measurement of inclination changes less than 1 09 Several special sensing functions are provided Activity and inactivity sensing detect the presence or lack of motion and if the acceleration on any axis exceeds a user set level Tap sensing detects single and double taps Free fall sensing detects if the device is falling These functions can be mapped to one of two interrupt output pins An integrated patent pending 32 level first in first out FIFO buffer can be used to store data to minimize host processor intervention Low power modes enable intelligent motion based power management with threshold sensing and active acceleration measurement at extremely low power dissipation The ADXL345 is supplied a small thin 3 mm x 5 mm x 1 mm 14 lead plastic package FUNCTIONAL BLOCK DIAGRAM ADXL345 Vs SENSE ELECTRONICS 3 AXIS SENSOR N CONTROL AND DIGITAL INTERRUPT FILTER LOGIC GND Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its
23. e Description 0x00 0 DEVID R 11100101 Device ID 0x01 to 0x01C 1 to 28 Reserved Reserved Do not access 0 1 29 THRESH_TAP R W 00000000 Tap threshold Ox1E 30 OFSX R W 00000000 X axis offset Ox1F 31 OFSY R W 00000000 Y axis offset 0x20 32 OFSZ R W 00000000 Z axis offset 0x21 33 DUR R W 00000000 Tap duration 0x22 34 Latent RW 00000000 Tap latency 0x23 35 Window R W 00000000 Tap window 0x24 36 THRESH_ACT R W 00000000 Activity threshold 0x25 37 THRESH_INACT R W 00000000 Inactivity threshold 0x26 38 TIME_INACT R W 00000000 Inactivity time 0x27 39 R W 00000000 Axis enable control for activity and inactivity detection 0x28 40 THRESH FF R W 00000000 Free fall threshold 0x29 41 TIME FF R W 00000000 Free fall time 0 2 42 5 R W 00000000 Axis control for tap double tap 0 2 43 STATUS R 00000000 Source of tap double tap 0 2 44 BW_RATE R W 00001010 Data rate and power mode control Ox2D 45 POWER R W 00000000 Power saving features control 0 2 46 INT_ENABLE R W 00000000 Interrupt enable control Ox2F 47 INT MAP R W 00000000 Interrupt mapping control 0x30 48 INT SOURCE R 00000010 Source of interrupts 0x31 49 DATA FORMAT R W 00000000 Data format control 0x32 50 DATAXO R 00000000 X Axis Data 0 0x33 51 DATAX1 R 00000000 X Axis Data 1 0x34 52 DATAYO R 00000000 Y Axis Data 0 0x35 53 DATAY1 R 00000000 Y Axis Data 1 0x36 54 DATAZO R 00000000 Z Axis Data 0 0x37 55 DATAZ1
24. e reliability THERMAL RESISTANCE Table 3 Package Characteristics Package Type Device Weight 14 Terminal LGA 150 C W 85 C W 20 mg ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage dy A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 4 of 4 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADXL345 TOP VIEW Not to Scale SCL SCLK Vpp vo 3 SDA SDI SDIO GND SDO ALT ADDRESS RESERVED RESERVED GND NC GND INT2 Vs INT1 Figure 2 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 Vpp vo Digital Interface Supply Voltage 2 GND Must be connected to ground 3 Reserved Reserved This pin must be connected to Vs or left open 4 GND Must be connected to ground 5 GND Must be connected to ground 6 Vs Supply Voltage 7 CS Chip Select 8 Interrupt 1 Output 9 INT2 Interrupt 2 Output 10 NC Not Internally Connected 11 Reserved Reserved This pin must be connected to ground or left open 12 SDO ALT ADDRESS Serial Data Output Alternate Address Select 13 SDA SDI SDIO Serial Data I C Serial Data Input SPI 4 Wire Serial Data Input and Output
25. e start of this window as shown in Figure 15 Additionally a double tap event can be invalidated if an accel Rev 0 Page 19 of 19 eration exceeds the time limit for taps set by the DUR register resulting in an invalid double tap at the end of the DUR time limit for the second tap event also shown in Figure 15 INVALIDATES DOUBLE AT START OF WINDOW Bw E TIME LIMIT iie FOR TAP Br DUR TIME LIMIT gt 8 LATENCY TIME WINDOW FOR TIME SECOND TAP WINDOW LATENT FOR TAPS DUR jos TIME Limit Xui Bw INVALIDATES e DOUBLE TAP AT B END OF DUR 07925 013 Figure 15 Tap Interrupt Function with Invalid Double Taps Single taps double taps or both can be detected by setting the respective bits in the INT ENABLE register Address Ox2E Control over participation of each of the three axes in single tap double tap detection is exerted by setting the appropriate bits in the AXES register Address 0x2A For the double tap function to operate both the latent and window registers must be set to a nonzero value Every mechanical system has somewhat different single tap double tap responses based on the mechanical characteristics of the system Therefore some experimentation with values for the latent window and THRESH_TAP registers is required In general a good starting point is to set the latent register to a value greater than 0x10 to se
26. ected After activity is detected inactivity detection begins preventing the detection of activity This bit serially links the activity and inactivity functions When this bit is set to 0 the inactivity and activity functions are concurrent Additional information can be found in the Link Mode section When clearing the link bit it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write This is done to ensure that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the link bit is cleared may have additional noise especially if the device was asleep when the bit was cleared AUTO_SLEEP Bit If the link bit is set a setting of 1 in the AUTO_SLEEP bit sets the ADXL345 to switch to sleep mode when inactivity is detected that is when acceleration has been below the THRESH_INACT value for at least the time indicated by A setting of 0 disables automatic switching to sleep mode See the description of the sleep bit in this section for more information When clearing the AUTO_SLEEP bit it is recommended that the part be placed into standby mode and then set back to measure ment mode with a subsequent write This is done to ensure that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noi
27. efore the end ofthe time defined by the window register SECOND TAP FIRST TAP THRESHOLD THRESH TAP TMELIMTFOR fi TAPS DUR lac TIME WINDOW FOR LATENCY SECOND TAP T PMINGEND LATENT o m 2 i SINGLE TAP DOUBLE TAP i INTERRUPT INTERRUPT E z Figure 13 Tap Interrupt Function with Valid Single and Double Taps If only the single tap function is in use the single tap interrupt is triggered when the acceleration goes below the threshold as long as DUR has not been exceeded If both single and double tap functions are in use the single tap interrupt is triggered when the double tap event has been either validated or invalidated Several events can occur to invalidate the second tap of a double tap event First if the suppress bit in the TAP_AXES register Address 0x2A is set any acceleration spike above the threshold during the latency time set by the latent register invalidates the double tap detection as shown in Figure 14 INVALIDATES DOUBLE IF SUPRESS BIT SET TIME LIMIT E FOR TAPS LATENCY TIME WINDOW FOR SECOND 2 DUR TIME LATENT TAP WINDOW 5 Figure 14 Double Tap Event Invalid Due to High g Event When the Suppress Bit Is Set A double tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap set by the window register This results in an invalid double tap at th
28. eleration Sensitivity sss 22 fara MID 8 Layout and Design Recommendations 23 ome P 8 Outline 8 E 10 RS 24 Interr pts ucc eee 12 REVISION HISTORY 5 09 Revision 0 Initial Version Rev 0 Page 2 of 2 SPECIFICATIONS Ta 25 C Vs 2 5 V 1 8 V acceleration 0 g Cs 1 tantalum 0 1 uF unless otherwise noted Table 1 Specifications Parameter Test Conditions Min Typ Max Unit SENSOR INPUT Each axis Measurement Range User selectable 2 4 8 16 9 Nonlinearity Percentage of full scale 0 5 Inter Axis Alignment Error 0 1 Degrees Cross Axis Sensitivity 1 OUTPUT RESOLUTION Each axis All g Ranges 10 bit resolution 10 Bits 2 g Range Full resolution 10 Bits 4 g Range Full resolution 11 Bits 8 g Range Full resolution 12 Bits 16 Range Full resolution 13 Bits SENSITIVITY Each axis Sensitivity at Xour Your Zour 2 g 10 bit or full resolution 232 256 286 LSB g Scale Factor at Xour Your Zour 2 g 10 bit or full resolution 3 5 3 9 4 3 mg LSB Sensitivity at Xour Your Zour 4 9 10 bit resolution 116 128 143 LSB g Scale Factor at Xour Your Zout 4 10 bit resolution 7 0 7 8 8 6 mg LSB Sensitivity at Xour Your Zour 8 g 10 bit resolution 58 64 71 LSB g
29. ended Printed Wiring Board Land Pattern Dimensions shown in millimeters RAMP UP TEMPERATURE t PREHEAT RAMP DOWN t25 C TO PEAK TIME CRITICAL ZONE T TO Tp 07925 015 Figure 19 Recommended Soldering Profile Table 21 Recommended Soldering Profile Profile Feature Condition Sn63 Pb37 Pb Free Average Ramp Rate from Liquid Temperature Ti to Peak Temperature T Preheat Minimum Temperature Maximum Temperature Tsmax Time from Tsw to Tsmax ts Tsmax to Ramp Up Rate Liquid Temperature Time Maintained Above t Peak Temperature Tp Time of Actual Tp 5 C te Ramp Down Rate Time 25 C to Peak Temperature 3 C sec max 100 C 150 C 60 sec to 120 sec 3 C sec max 183 C 60 sec to 150 sec 240 0 5 C 10 sec to 30 sec 6 C sec max 6 minutes max 3 C sec max 150 C 200 C 60 sec to 180 sec 3 C sec max 217 C 60 sec to 150 sec 260 0 5 C 20 sec 40 sec 6 C sec max 8 minutes max Based on JEDEC Standard J STD 020D 1 For best results the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used Rev 0 Page 23 of 23 OUTLINE DIMENSIONS PAD A1 BOTTOM VIEW CORNER 3 2 1 0 813 x 0 50 TERR 5 00 0 80 BSC BSC 0 50 TOP VIEW ea 0 79 0 49 095 END VIEW 9 74 os
30. evice triggers an activity interrupt Similarly in ac coupled operation for inactivity detection a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold After the reference value is selected the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH INACT If the difference is less than the value in THRESH INACT for the time in TIME INACT the device is considered inactive and the inactivity interrupt is triggered ACT xEnable Bits and INACT x Enable Bits A setting of 1 enables x y or z axis participation in detecting activity or inactivity A setting of 0 excludes the selected axis from participation If all axes are excluded the function is disabled Register 0 28 FF Read Write The THRESH FF register is eight bits and holds the threshold value in unsigned format for free fall detection The root sum square RSS value of all axes is calculated and compared with the value in THRESH FF to determine if a free fall event occurred The scale factor is 62 5 mg LSB Note that a value of 0 mg may result in undesirable behavior if the free fall interrupt is enabled Values between 300 mg and 600 mg 0x05 to 0x09 are recommended Rev 0 Page 15 of 15 Register 0 29 FF Read Write The TIME FF register is eight bits and stores an unsigned time value representing the minimum time th
31. ion of a tap event to the start of the time window defined by the window register during which a possible second tap event can be detected The scale factor is 1 25 ms LSB A value of 0 disables the double tap function Register 0x23 Window Read Write The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time determined by the latent register during which a second valid tap can begin The scale factor is 1 25 ms LSB A value of 0 disables the double tap function Register 0 24 Read Write The THRESH_ACT register is eight bits and holds the threshold value for detecting activity The data format is unsigned so the magnitude of the activity event is compared with the value in the THRESH_ACT register The scale factor is 62 5 mg LSB A value of 0 may result in undesirable behavior if the activity interrupt is enabled Register 0x25 THRESH_INACT Read Write The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity The data format is unsigned so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register The scale factor is 62 5 mg LSB A value of 0 mg may result in undesirable behavior if the inactivity interrupt is enabled Register 0 26 Read Write The TIME_INACT register is eight bits and contains an unsigned time value rep
32. ion ofless than the value stored in the THRESH INACT register Address 0x25 is experi enced for more time than is specified in the TIME INACT register Address 0x26 The maximum value for TIME INACT is 255 sec FREE FALL The FREE FALL bit is set when acceleration of less than the value stored in the THRESH FF register Address 0x28 is experienced for more time than is specified in the TIME FF register Address 0x29 The FREE FALL interrupt differs from the inactivity interrupt as follows all axes always participate the timer period is much smaller 1 28 sec maximum and the mode of operation is always dc coupled Watermark The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits Register FIFO_CTL Address 0x38 The watermark bit is cleared automatically when FIFO is read and the content returns to a value below the value stored in the samples bits Overrun The overrun bit is set when new data replaces unread data The precise operation of the overrun function depends on the FIFO mode In bypass mode the overrun bit is set when new data replaces unread data in the DATAX DATAY and DATAZ registers Address 0x32 to Address 0x37 In all other modes the overrun bit is set when FIFO is filled The overrun bit is automatically cleared when the contents of FIFO are read FIFO The ADXL345 contains patent pending technology for an embedded 32 level FIFO that can be used to mini
33. le 6 Current Consumption vs Data Rate Ta 25 C Vs 2 5 V 1 8 V Output Data Rate Hz Bandwidth Hz Rate Code lbo WA 3200 1600 1111 145 1600 800 1110 100 800 400 1101 145 400 200 1100 145 200 100 1011 145 100 50 1010 145 50 25 1001 100 25 12 5 1000 65 12 5 6 25 0111 55 6 25 3 125 0110 40 Table 7 Current Consumption vs Data Rate Low Power Mode Ta 25 C Vs 2 5 V 1 8 V Condition Vs Vooo Description Power Off Off Off The device is completely off but there is a potential for a communication bus conflict Bus Disabled On Off The device is on in standby mode but communication is unavailable and will create a conflict on the communication bus The duration of this state should be minimized during power up to prevent a conflict Bus Enabled Off On No functions are available but the device will not create a conflict on the communication bus Standby or On On At power up the device is in standby Measurement mode awaiting a command to enter measurement mode and all sensor functions are off After the device is instructed to enter measurement mode all sensor functions are available Output Data Rate Hz Bandwidth Hz Rate Code loo 400 200 1100 100 200 100 1011 65 100 50 1010 55 50 25 1001 50 25 12 5 1000 40 12 5 6 25 0111 40 Rev 0 Page6 of 6 Auto Sleep Mode Additional power can be sa
34. mize host processor burden This buffer has four modes bypass FIFO stream and trigger see Table 19 Each mode is selected by the settings of the FIFO MODE bits in the FIFO_CTL register Address 0x38 Bypass Mode In bypass mode FIFO is not operational and therefore remains empty FIFO Mode In FIFO mode data from measurements of the x y and z axes are stored in FIFO When the number of samples in FIFO equals the level specified in the samples bits of the FIFO register Address 0x38 the watermark interrupt is set FIFO continues accumulating samples until it is full 32 samples from measurements of the x and z axes and then stops collecting data After FIFO stops collecting data the device continues to operate therefore features such as tap detection can be used after FIFO is full The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register Stream Mode In stream mode data from measurements of the x y and z axes are stored FIFO When the number of samples in FIFO equals the level specified in the samples bits ofthe FIFO_CTL register Address 0x38 the watermark interrupt is set FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x y and z axes discarding older data as new data arrives The watermark interrupt continues occurring until the number of sam
35. ng self test After allowing the output to settle several samples of the x y and z axis acceleration data should be taken again and averaged It is recommended that the same number of samples be taken for this average as was previously taken These averaged values should again be stored and labeled appropriately as the value with self test enabled that is Xsr Ysr and Self test can then be disabled by clearing Bit D7 of the DATA FORMAT register Address 0x31 With the stored values for self test enabled and disabled the self test change is as follows Xsr Xsr Xsr Ysr Zsr Zst_on orr Because the measured output for each axis is expressed in LSBs Xsr Ysr and are also expressed LSBs These values can be converted to g s of acceleration by multiplying each value by the 3 9 mg LSB scale factor if configured for full resolution 16 g mode Additionally Table 12 through Table 15 correspond to the self test range converted to LSBs and can be compared with the measured self test change If the part was placed into full resolution 16 2 mode the values listed in Table 12 should be used Although the fixed 10 bit mode or a range other than 16 g can be used a different set of values as indicated in Table 13 through Table 15 would need to be used Using a range below 8 g may result in insufficient dynamic range and should be considered
36. performed the remaining bytes of data for the current FIFO sample are lost Therefore all axes of interest should be read in a burst or multiple byte read operation To ensure that the FIFO has completely popped that is that new data has completely moved into the DATAX DATAY and DATAZ registers there must be at least 5 us between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register Address 0x39 The end of reading a data register is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high For SPI operation at 1 6 MHz or less the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped For SPI operation greater than 1 6 MHz it is necessary to deassert the CS pin to ensure a total delay of 5 us otherwise the delay will not be sufficient The total delay necessary for 5 MHz operation is at most 3 4 us This is not a concern when using mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads SELF TEST The ADXL345 incorporates a self test feature that effectively tests its mechanical and electronic systems simultaneously When the self test function is enabled via the SELF TEST bit in DATA FORMAT register Address 0x31 an electrostatic force is exerted on the mechanical sensor This electrostatic force moves the mechanical
37. ples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register Rev 0 Page 12 of 12 Trigger Mode In trigger mode FIFO accumulates samples holding the latest 32 samples from measurements of the x y and z axes After a trigger event occurs and an interrupt is sent to the or INT2 pin determined by the trigger bit in the FIFO_CTL register FIFO keeps the last n samples where n is the value specified by the samples bits in the FIFO_CTL register and then operates in FIFO mode collecting new samples only when FIFO is not full A delay of at least 5 us should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples Additional trigger events cannot be recognized until the trigger mode is reset To reset the trigger mode set the device to bypass mode and then set the device back to trigger mode Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO Retrieving Data from FIFO The FIFO data is read through the DATAX DATAY and DATAZ registers Address 0x32 to Address 0x37 When the FIFO is in FIFO stream or trigger mode reads to the DATAX DATAY and DATAZ registers read data stored in the FIFO Each time data is read from the FIFO the oldest x y and z axes data are placed into the DATAX DATAY and DATAZ registers If a single byte read operation is
38. pplication however Vpp vo can differ from Vs to accommodate the desired interface voltage as long as Vs is greater than Vppyo After Vsis applied the device enters standby mode where power consumption is minimized and the device waits for Vppyo to be applied and for the command to enter measurement mode to be received This command can be initiated by setting the measure bit in the POWER register Address 0x2D In addition any register can be written to or read from to configure the part while the device is in standby mode It is recommended to configure the device in standby mode and then to enable measurement mode Clearing the measure bit returns the device to the standby mode Table 5 Power Sequencing POWER SAVINGS Power Modes The ADXL345 automatically modulates its power consumption in proportion to its output data rate as outlined in Table 6 If additional power savings is desired a lower power mode is available In this mode the internal sampling rate is reduced allowing for power savings in the 12 5 Hz to 400 Hz data rate range but at the expense of slightly greater noise To enter lower power mode set the LOW POWER bit Bit 4 in the BW RATE register Address 0x2C The current consumption in low power mode is shown in Table 7 for cases where there is an advantage for using low power mode The current consumption values shown in Table 6 and Table 7 are for a Vs of 2 5 V Current scales linearly with Vs Tab
39. resenting the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared The scale factor is 1 sec LSB Unlike the other interrupt functions which use unfiltered data see the Threshold section the inactivity function uses filtered output data At least one output sample must be generated for the inactivity interrupt to be triggered This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register Register 0 27 INACT Read Write D7 D6 D5 D4 ACT ac dc ACT_X enable ACT_Y enable ACT_Z enable D3 D2 D1 DO INACT ac dc INACT Xenable INACT Y enable 2 enable ACT AC DC and INACT AC DC Bits A setting of 0 selects dc coupled operation and a setting of 1 enables ac coupled operation In dc coupled operation the current acceleration magnitude is compared directly with 5 ACT and THRESH_INACT to determine whether activity or inactivity is detected In ac coupled operation for activity detection the acceleration value at the start of activity detection is taken as a reference value New samples of acceleration are then compared to this reference value and if the magnitude of the difference exceeds the 5 ACT value the d
40. rst or multiple byte mode because each FIFO level is cleared after any read single or multiple byte of FIFO FIFO stores a maximum of 32 entries which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device Rev 0 Page 18 of 18 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING A 1 uF tantalum capacitor Cs at Vs and a 0 1 uF ceramic capacitor Cio at Vop yo placed close to the ADXL345 supply pins is used for testing and is recommended to adequately decouple the accelerometer from noise on the power supply If additional decoupling is necessary a resistor or ferrite bead no larger than 100 Q in series with Vs may be helpful Additionally increasing the bypass capacitance on Vs to a 10 uF tantalum capacitor in parallel with a 0 1 uF ceramic capacitor may also improve noise Care should be taken to ensure that the connection from the ADXL345 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through Vs It is recommended that Vs and Vop vo be separate supplies to minimize digital clocking noise on the Vs supply If this is not possible additional filtering of the supplies as previously mentioned may be necessary Vs Vpp vo Vpp vo ADXL345 INTERRUPT oe SPI OR PC CONTROL INTERFACE 07925 016 Figure 11 Application Diagram MECHANICAL CONSIDERA
41. se especially if the device was asleep when the bit was cleared Measure Bit A setting of 0 in the measure bit places the part into standby mode and a setting of 1 places the part into measurement mode The ADXL345 powers up in standby mode with minimum power consumption Rev 0 Page 16 of 16 Sleep Bit A setting of 0 in the sleep bit puts the part into the normal mode of operation and a setting of 1 places the part into sleep mode Sleep mode suppresses DATA_READY stops transmission of data to FIFO and switches the sampling rate to one specified by the wakeup bits In sleep mode only the activity function can be used When clearing the sleep bit it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write This is done to ensure that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the sleep bit is cleared may have additional noise especially if the device was asleep when the bit was cleared Wakeup Bits These bits control the frequency of readings in sleep mode as described in Table 17 Table 17 Frequency of Readings in Sleep Mode Bits set to 1 in this register indicate that their respective functions have triggered an event whereas a value of 0 indicates that the corresponding event has not occurred The DATA_READY watermark and overrun bits are always set if the corresponding events oc
42. t the window register to a value greater than 0x10 and to set the THRESH register to be greater than 3 g Setting a very low value in the latent window or THRESH register may result an unpredictable response due to the accelerometer picking up echoes of the tap inputs After a tap interrupt has been received the first axis to exceed the level is reported in the ACT STATUS register Address 0 2 This register is never cleared but is overwritten with new data THRESHOLD The lower output data rates are achieved by decimating a common sampling frequency inside the device The activity free fall and single tap double tap detection functions are performed using unfiltered data Since the output data is filtered the high frequency and high g data that is used to determine activity free fall and single tap double tap events may not be present if the output of the accelerometer is examined This may result in trigger events being detected when acceleration does not appear to trigger an event because the unfiltered data may have exceeded a threshold or remained below a threshold for a certain period of time while the filtered output data has not exceeded such a threshold LINK MODE The function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity For proper operation of this feature
43. tally triggered during configuration This can be done by writing a value of 0x00 to theINT ENABLE register Clearing interrupts is performed either by reading the data registers Address 0x32 to Address 0x37 until the interrupt condition is no longer valid for the data related interrupts or by reading the INT SOURCE register Address 0x30 for the remaining interrupts This section describes the interrupts that can be set in the INT ENABLE register and monitored in the INT SOURCE register DATA READY The DATA READY bit is set when new data is available and is cleared when no new data is available SINGLE TAP The SINGLE TAP bit is set when a single acceleration event that is greater than the value in the register Address 0x1D occurs for less time than is specified in the DUR register Address 0x21 DOUBLE TAP The DOUBLE TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register Address 0x1D occur for less time than is specified in the DUR register Address 0x21 with the second tap starting after the time specified by the latent register Address 0x22 but within the time specified in the window register Address 0x23 See the Tap Detection section for more details Activity The activity bit is set when acceleration greater than the value stored in the THRESH ACT register Address 0x24 is experienced Inactivity The inactivity bit is set when accelerat
44. te This shifting continues until the clock pulses cease and CS is deasserted To perform reads or writes on different nonsequential registers CS must be deasserted between transmissions and the new register must be addressed separately The timing diagram for 3 wire SPI reads or writes is shown in Figure 7 The 4 wire equivalents for SPI writes and reads are shown in Figure 5 and Figure 6 respectively Table 8 SPI Digital Input Output Voltage Parameter Limit Unit Digital Input Voltage Low Level Input Voltage Vu High Level Input Voltage Viu Digital Output Voltage Low Level Output Voltage High Level Output Voltage Vou 0 2 x Vooo V max 0 8 x Vooo V min 0 15 x Vooo V max 0 85 xVopyo V min Limits based on characterization results not production tested Limit 3 Parameter Min Max Unit Description 5 2 SPI clock frequency tscik 200 ns 1 SPI clock frequency mark space ratio for the SCLK input is 40 60 to 60 40 tpELAY 10 ns CS falling edge to SCLK falling edge toute 10 ns SCLK rising edge to CS rising edge tois 100 ns CS rising edge to SDO disabled tcs pis 250 ns CS deassertion between SPI communications ts 0 4 x ns SCLK low pulse width space 0 4 x ns SCLK high pulse width mark 95 ns SCLK falling edge to SDO transition tsetup 10 ns SDI valid before SCLK rising edge 10 ns SDI valid after SCLK rising edge 1 The CS SCLK SDI and
45. ted interrupts for a given pin are ORed Register 0x30 INT_SOURCE Read Only The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37 All data except that for the 16 g range must be clipped to avoid rollover SELF_TEST Bit A setting of 1 in the SELF_TEST bit applies a self test force to the sensor causing a shift in the output data A value of 0 disables the self test force SPI Bit A value of 1 in the SPI bit sets the device to 3 wire SPI mode and a value of 0 sets the device to 4 wire SPI mode INT_INVERT Bit A value of 0 in the INT_INVERT bit sets the interrupts to active high and a value of 1 sets the interrupts to active low FULL_RES Bit When this bit is set to a value of 1 the device is in full resolution mode where the output resolution increases with the g range set by the range bits to maintain a 4 mg LSB scale factor When the FULL_RES bit is set to 0 the device is in 10 bit mode and the range bits determine the maximum g range and scale factor Justify Bit A setting of 1 in the justify bit selects left MSB justified mode and a setting of 0 selects right justified mode with sign extension Range Bits These bits set the g range as described in Table 18 Table 18 g Range Setting D7 D6 D5 D4 DATA_READY SINGLE_TAP DOUBLE_TAP Activity D3 D2 D1 DO Inactivity FREE_FALL Watermark Overrun Setting D1 DO g Range 0 0 20 0 1 4
46. use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners See the last page for disclaimers 2 SDA SDI SDIO O SDO ALT ADDRESS Figure 1 SCL SCLK 07925 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2009 Analog Devices Inc All rights reserved TABLE OF CONTENTS Features cos 12 Applications 13 General 1 tM 14 Functional Block DIABESHE a eic at RARE 1 Register Definitions yiii trie raten 15 2 Applications Information eee 19 Specifications a 3 Power Supply 13 Absolute Maximum 4 Mechanical Considerations for Mounting 19 4 ER 19 4 Phresh Old cei e 20 Pin Configuration and Function Descriptions 5 Linke Mode 5 rte TREE 20 Theory of Operation serso 6 ae Power Sedueticitig tee 6 Using Self Teste eode ene 20 Power Savings 6 Axes of Acc
47. ved if the ADXL345 automatically switches to sleep mode during periods of inactivity To enable this feature set the THRESH_INACT register Address 0x25 and the TIME_INACT register Address 0x26 each to a value that signifies inactivity the appropriate value depends on the application and then set the AUTO_SLEEP bit and the link bit in the POWER_CTL register Address 0x2D Current consumption at the sub 8 Hz data rates used in this mode is typically 40 uA for a Vs of 2 5 V Standby Mode For even lower power operation standby mode can be used In standby mode current consumption is reduced to 0 1 typical In this mode no measurements are made Standby mode is entered by clearing the measure bit Bit 3 in the POWER register Address 0x2D Placing the device into standby mode preserves the contents of FIFO Rev 0 Page 7 of 7 SERIAL COMMUNICATIONS and SPI digital communications are available In both cases the ADXL345 operates as a slave mode is enabled if the cs pin is tied high to The CS pin should always be tied high to or be driven by an external controller because there is no default mode if the CS pin is left unconnected Therefore not taking these precautions may result in an inability to communicate with the part In SPI mode the CS pin is controlled by the bus master In both SPI and PC modes of operation data transmitted from the ADXL345 to the master device should be
48. wo axes Bandwidth is half the output data rate 4 Self test change is defined as the output g when the SELF TEST bit 1 in the DATA FORMAT register minus the output 9 when the SELF TEST bit 0 in the DATA FORMAT register Due to device filtering the output reaches its final value after 4 x when enabling or disabling self test where 1 data rate 5Turn on and wake up times are determined by the user defined bandwidth At a 100 Hz data rate the turn on and wake up times are each approximately 11 1 ms For other data rates the turn on and wake up times are each approximately 1 1 in milliseconds where 1 data rate Rev 0 Page 3 of 3 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Acceleration Any Axis Unpowered 10 000 g Any Axis Powered 10 000 g Vs 0 3V to 3 6V Vooo 0 3V to 3 6 V Digital Pins 0 3 V to Vooo 0 3 V or 3 6 V whichever is less All Other Pins 0 3V to 3 6V Output Short Circuit Duration Indefinite Any Pin to Ground Temperature Range Powered 40 C to 105 C Storage 40 C to 105 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect devic
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