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ADSP-21065L EZ-KIT Lite Evaluation System Manual

1. 21 command 51 21 eel s 21 Package 11 PC Configuration pe 12 Pluck dxe ume OBI 37 POST errors arne neo t p Ou ROT 19 POST routines itu e nete es 19 Power 16 Power Supplies ettet e etis 41 Power supply specifications B topeails a ie etr eeu beers 42 POW I OnT6Sel s sce oe 19 Priniesdlxe iue eene de 38 Programming the EMATE eere 31 R Registers MASE tect 17 MODE 7s cA disaster eae aa tae 17 SE 17 SDRAM vsert 48 SDRAM data mask See SDRAM interface data transfer rate sss 48 features skare 48 pin definitionsSee SDRAM interface pin definitions SDRAM memory pp 23 SDRAM pins See SDRAM interface pin definitions Selecting target unntas 32 Serial comImunication 19 SLOTzI6 mode ten 26 Software installation sse 14 Jue 18 Standard Operation sss 16 Starting the debugger es 32 Static discharge Ne 11 Supply c trerit cene hee edant 42 Supply voltage i deese neis 42 synchronous serial Ports sess 19 T Target 32 Technical support 8 Test Communications command
2. sse 11 EMXEE 158065 rere 48 EMAFE Programming pp 31 EPROM operation sese 46 EPROM t6sStS eR OS 20 Error codes POST TOUnDe api depu D tede 19 JUD 11 European power 42 EZ KIT LITE board 40 EZ LAB default settings et 15 F features ses 7 FFT demo 63 pe ordei 37 FLAG VO pits oe ote Uh 16 FLAGO S ee 16 FLAG IL epe ete ede 17 ELAGA 10 ie ete TERRE Werten 17 ELAGLIU 5 EE ee 17 G Gund C A cr eet 37 H Hardware devices CODEG etae itte eds 46 CPLD e quations 3 5 Rede 66 79 EMATE 2 1 525 8 43 EPROM oy 40 power supplies 41 1 gen hehe s 48 WARD 47 Hardware installation sess 13 1 IMASK fegistet zie 17 Installing EZ KIT LITE hardware 13 Installing EZ KIT LITE software 14 Interrupts ROO iier ee 17 RE eH TIRE d 17 M memory SDRAM ikea hee n 31 Memory checks Ne 20 Memory na 23 Memory select lines pe See MSx register eese 16 monitor program components 21 Monitor program
3. Flag Out ABC sse 5594 21910 o 00 0000 JP6 3 2 1 0 2 1 0 0 9 8 7 6 5 4 Figure 5 2 EZ KIT LITE Layout 5 3 1 Boot EPROM The boot EPROM provides up to 1M x 8 bits of program storage that can be loaded by the ADSP 21065L when it is programmed to boot from EPROM Selection of the boot source is controlled by the BMS Boot Memory Select and BSEL EPROM Boot pins The first 256 instructions 1536 bytes are automatically loaded by the ADSP 21065L after reset The remaining program image must be loaded by the program that is installed in those first 256 instructions Refer to the ADSP 21065L SHARC User s Manual for more information on booting 40 5 3 2 User Push Button Switches For user input control there are eight push button switches on the EZ KIT Lite board RESET FLAG 0 3 and IRQ 0 2 RESET switch lets you initiate a power on reset to the DSP If the user loses contact between the EZ KIT Lite board and the PC while running programs use the RESET button to restore communication FLAG 0 3 switches toggle the status of four flag pins FLAG 0 3 to the DSP The IRQ 0 2 switches let you send interrupts IRQ 0 2 to the DSP This manually causes interrupts when executing a program IRQO is shared with the UART and IRQI is shared with the EMAFE connector See Flags section in Chapter 3 for more information on interfacing to the push button switches from DSP program
4. 3 2 2 POST Routines POST Power On Self Test routines are a series of standard tests and initializations that the EZ KIT Lite performs on a power on reset To perform a power on reset disconnect power to the board for at least three seconds and then reconnect power The board automatically resets note that all the LED s light up briefly The user may also reset the board during operation through the Debug gt Reset command from the debugger menu bar Both types of reset cause the DSP to reset to a known state and is followed by a message box that displays the message Communications Success At this point the user should reload any programs he she was working on Table 3 3 shows the types of resets and their functions Table 3 3 Table 3 3 Post Routines EPROM Check Internal Memory Check Error codes are transmitted to the PC and are displayed on the LEDs If the LED remains lit after reset then the error has been caused by the component shown in Table 3 4 Table 3 4 Table 3 4 POST Error Codes Flag LED EPROM UART AD1819 3 2 2 1 Memory Checks The monitor program performs some standard memory checks which are as follows EPROM Internal memory External SDRAM The EPROM test consists of verifying a number in memory If the monitor code is corrupted the monitor may crash before reaching the actual program code These checks include Write then verify all 0 s Write then verify all 1 s Write
5. EMAFE ADDR 74LVT574 C S CHAIN CLK LA CODEC CS1 CODES Csi L QEMAFE 907 gt 74LVTH16245A 3 3Vcc R76 11F 13g 74LCX14 Bypass Caps for 012 Bypass Caps for U14 The ADSP 210 programmed t 65L must be o use a Hold Time Cycle on MS1 for proper operation of this circuit 3 3Vcc 5Vcc 4 2 itle Size B ate rawn ilename Analog Devices Inc ANA One Tech nology Way DEVI Norwood MA 02062 Designed by Paragon Innovations Inc RARAGON mail info p ADSP 21065L EZ LAB EMAFE CODEC Document Number 65 000299 02 1125 01 001 0201 Wednesday November 18 1998 Kris Stafford Filename heet SDA10 gt 71 Non schemati J5 and 44 should be adjusted MS3 gt depending on size of EPROM RAS gt P g Socket for EPROM me 5 anit SDWEHL gt m 1 Rev s 0 0 and 0 1 of the ADSP 21065L begin pam gt 128K x 8 256K x 8 accessing the EPROM at 0x020000 Later TT n 512K x 8 Rev s begin at 0x000000 ensure that spoke gt Not Used the EPROM will work with all revisions sDCLKOL gt 1M x 8 place code at both places VssO Vss1 Vssq0 Vssq1 Vssq2 Vssq3 Shunt Shunt 3 3Vcc iti Jumper3 Jumper3 3 3Vcc PROM_CS L__ gt 32 MT48LC1M16A1 3 3Vcc Analog Devices Inc One Tech nology Way Norwood MA 02062 3 3Vcc 5 5 Designed by Paragon Inn
6. lt 0 u ack lt 1 next state RD4 Continue Read Cycle when RD4 gt u lt 1 u ack v 1 next state lt ENDR1 Continue Read Cycle when ENDR1 u ack 1 u ack v 1 next state IDLE End Read Cycle end case end process uart state with next state select uart_ctrl_d lt 111 when IDLE 101 when CS1 101 when CS2 100 when WR1 100 when WR2 100 when WR3 100 when WR4 101 when WR D1 111 when ENDW1 111 when ENDW2 111 when ENDW3 111 when ENDW4 101 when CS3 101 when CS4 101 when CS5 101 when CS6 001 when RD1 001 when RD2 001 when RD3 001 when RD4 101 when ENDR1 when others kkkkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk State Reset Control state clocked process reset clk begin if reset 1 then present state IDLE UART State rd bar s 1 UART State u en bar lt 1 UART State u wr bar 1 UART State present wstate lt WAITO Wait State elsif rising edge clk then present state lt next state UART State u rd bar uart ctrl d 2 UART State u en bar uart ctrl d 1 UART State u wr bar uart ctrl d 0 UART S
7. 61 Timing changes eise erret 50 Transfers CODEC x und esti to tet beeen ie Sees 21 Ttdxe aie ee tee ims 38 U UART aliasing eee 48 UART Check Initialization Internal Loop acK sse 20 register Write cote d HOD 20 transmitted loop back RN 20 UART ISR segment seen 21 UART specifications Ne 47 V VisualDSP ii 12 13 14 Voltage 42 80
8. 0x0100 0001 0x0100 0001 EMAFE Data reserved for the EZ KIT 0x0100 0004 0x0100 0007 UART reserved for the EZ KIT 0x0300 0000 0x0310 0000 SDRAM reserved for the EZ KIT 1 Use caution when accessing the Boot EPROM The EPROM chip select BMS has the same limitations as MSO EPROM s larger than 128K x 8 have restricted access to their data below address 0x020000 and their data is aliased to other memory locations The user program can access this data from these other locations 24 Table 3 6 shows currently used and available memory locations on the EZ KIT Lite board The user may not change these locations in their programs Table 3 6 Available Memory Locations on the EZ KIT Lite Memory Range Availability 0x00008000 0x0000801F Interrupt Vectors user 48 bit 0x00008020 0x00008023 IRQO vector reserved by monitor and not overwritten on any dxe load PTE FE Vectors user 48 bit ETUDES Vector reserved by monitor Fe Vectors user 48 bit 0x00008100 0x00008FFF User Program Space 3840 48 bit locations internal RAM block 0 0x00009000 0x000097FF Kernel Code 48 bit internal block 0 0x0000C000 0x0000DFFF User space can be configured as 8192 x 32 or 2K x 48 4K x 32 or 4K x 48 2K x 32 0x01000000 EMAFE address location external block 0 0x01000001 EMAFE data location external block 0 0x01000008 0x0100000F 16550 UART registers external block 0 0x0100001
9. 21065L One possibility for the use of these connectors beyond debugging is host control All interrupts bus signals and PWM event signals are available through this port For more information see Expansion Connectors section in Chapter 6 WARNING External port loading can effect external bus speed and performance EMAFE Interface Connector WARNING Using the EMAFE interface connector to connect to a MAFE board can damage the ADSP 21065L EZ KIT Lite the MAFE or both Enhanced Modular Analog Front End EMAFE connector provides a standard interface for connecting analog input output daughter boards The connector has 96 female pins arranged in three rows of 32 pins on a right angle connector The interface supports a 16 bit parallel data path two serial ports an interrupt output and a flag input Refer to Expansion section in Chapter 6 for more information on the EMAFE interface JTAG Connector Emulator Port The JT AG header Figure 5 3 is the connecting point for the JTAG in circuit emulator probe Note that one pin is missing pin 3 to provide keying The pin 3 socket in the mating connector should have a plug inserted at that location The EZ KIT Lite board is shipped with two jumpers installed across pins 7 amp 8 and 9 amp 10 These jumpers must be removed before installing the JTAG probe When the JTAG probe is removed care must be taken to replace these jumpers to ensure that the ADSP 21065L p
10. u 15 O 3 ee re PUSHBUTTON 1 127753 2b g 4 j PUSHBUTTON 1 SW8 1 3 PUSHBUTTON1 100 Ohm 100 Ohm 100 Ohm PUSHBUTTON1 ud gt 10 74LCX14 74LCX14 74LCX14 3 3Vcc 14QU11E tio 79 74LCX14 3 3Vcc 74LCX14 74LCX14 General purpose LE 3 3Vcc 3 3Vcc 3 3Vcc 3 3Vcc 3 3Vcc D5 Power on 3 3Vcc 74LCX14 74LCX14 Analog Devices Inc One Tech nology Way Norwood MA 02062 Designed by Paragon Innovations In M D 43 3Vcc D6 y 74LCX14 74LCX14 mail info paragon tx com itle ADSP 21065L EZ LAB I O MAFE amp Switches Size Document Number B 65 000299 02 1125 01 001 0201 ate Thursday November 19 1998 rawn By Kris Stafford ilename Filename heet C PARAGO Bypass Caps for U16 lt lt ODEC JP3 1 2 if EMAFE Interface uses SPORT1 AD1819 not used 100 Ohm OOOCO nma w JO CODEC RST 11 Y1 5 lt lt RES Y3 Y4 3 3Vcc GND Vcc 14 74LCX125 CODEC CSO Digital and Analog ground planes are connect through a single point through FB13 which should be placed close to the AD1819A CODEC CS1 FB13 Ferrite Bead 24 576MHz C109 43 3Vcc 107 5Vcc Cap added to reduce emissions since 3 3V logic is talking to 5V part Place cap close to signal lines O RESET SDATA OUT SDATA IN SYNC AD1819A 50 51
11. rising edge clk then otherwise key on rising edge if cnt 00000 then if counter hasn t started if addr 0100 AND cs bar 0 then check if reset cnt 1 Start counter codec rst bar 0 Reset codec else if not reset codec rst bar 1 hold reset high end if else if counter has started cde cnt 1 increment counter codec rst bar 0 Reset codec end if end if end process cdc rst end To use the CODEC controls reference the buffer asm and ldf files provided with the demos These files provide access to the necessary variables by overlapping the locations of the variables 71 APPENDIX BILL OF MATERIALS 72 tains ss Besten anufacturer Source P N 1 C4 C7 C11 C22 C24 C38 C42 0 01uF eramic 10 T amp R 50 V AVX 08055E103KATMA 60 C62 C74 C75 C91 C92 C95 C105 anasonic ECU 1H103KBG 119 C122 C124 C127 C129 C130 134 C135 109 C110 MT0805 eramic 5 50 V PCC220CNCT ND cusens O Panasonic ECU V1H101JCG 112 C113 6 18 3 C9 C16 C17 C20 C47 C51 C57 antalum 10 10 V Kemet T491A106K010AS 69 C97 C98 C99 C100 C111 C120 126 C133 C138 39 C117 0 047uF SMT1206 5U 10 50 V IDigikey PCC473BCT ND Panasonic ECU V1Hr73K BW 44 C44 C49 C50 C54 C81 C86 C50 C54 C81 C86 20 DopF ISMTO0805 eramic 596 50 V Digi
12. then verify memory address Write then verify compliment of memory address 3 2 2 2 UART Check Initialization The UART check is done in three stages Two of these stages are implemented in the POST The third is controlled by the host PC when it attempts to connect to the EZ KIT Lite These stages are Register Write This test confirms that the ADSP 21065L is capable of writing to and reading from a register in the UART Three patterns are written to and then read from a register in the and tested All three patterns must be read back correctly to pass this test Internal Loop Back In this test 256 bytes are sent to and read from the UART This test checks the functionality of the UART connections from the ADSP 21065L up to and through the UART chip Transmitted Loop Back The last UART test is performed by the host after the POST is complete In this test the host sends the UART test protocol This protocol specifies the number of bytes that are transmitted to the EZ KIT Lite board and instructs the board to echo the byte stream back to the host This test determines whether the EZ KIT Lite board is set to the correct baud rate and verifies the external connections between the board and the host 20 On power up the EZ KIT Lite board defaults to baud rate of 115200 with 8 data bits 1 stop bit and no parity If you want to change this rate change it after the POST is complete use the Settings gt
13. 1 Installing the EZ KIT Lite Hardware The ADSP 21065L EZ KIT Lite board is designed to run outside the PC as stand alone unit There is no need to remove the chassis from your computer Use the following steps to connect the EZ KIT Lite board 1 Remove the EZ KIT Lite board from the package be careful when handling these boards to avoid the discharge of static electricity which may damage some components 2 Connect the RS 232 cable to an available Comm Port on the PC and to J3 on the ADSP 21065L evaluation board 3 Plug the provided cord into a 120 Volt AC receptacle and plug the connector at the other end of the cable into J1 Power In on the evaluation board of the LEDs light up briefly The FLAG and power red LED remain on If the LEDs do not light up check the power connections To configure your board to take advantage of the audio capabilities of the demos use the following procedure 1 Plug a set of self powered computer speakers into jack J7 Line Out on the board Turn on the speakers and set the volume to an adequate level 2 Connect the line out of an electronic audio device to jack J8 MIC Line In on the board Set jumpers JP1 and JP2 to LINE 3 Set Jumper JP3 to GND to enable the AD1819 codec This is the board default This completes the hardware installation 2 5 2 Installing VisualDSP This EZ KIT Lite comes with the latest evaluation version of VisualDSP for SHARC Family DSPs You mus
14. 3V SaRonix NCH089B 30 0000 Augat 832 AG12D ES Russel BUT 4165 TT APPENDIX C SCHEMATICS 78 U18 182 176 172 163 158 140 130 124 120 110 105 66 a 1 DMAG1 CODEC_ON gt FLAGIA 9 C 3 3Vcc 3 3Vcc XN R57 x S R64 JP6 lt gt gt EVENTO lt gt EVENTI 6 24 2 PWM EVENT BMS PWM EVENTO ADSP 21065L 252 5 lE Inc gt gt gt mla Host Boot EPROM Boot Initially JP6 2 3 SJP6 Ko rs Jo NNNM ALELELLEELELELLELLLL ID O1 co 1 N IND J no no JO OO O1 o1 JO JN O0 O0 o o o co B IN 6 Jo t TDI 3 3Vcc GND BTDI SJP7 SJP8 TRST BTRST 5 BTCK Shunt Shunt 5 When not used jumper pins Key 7 8 GND 9 10 Single Processor Processor 1 Processor 2 INVALID Initially both should be installed lt gt wrt SJP10 Analog Devices Inc One Tech nology Way ANALOG Norwood MA 02062 itle Size B ate Drawn ilename Designed by Paragon Innovations Inc PARAGON mail info paragon t x com ADSP 21065L EZ LAB Proc Main Document Number 65 000299 02 1125 01 001 0201 Wednesday November 18 1998 Kris Stafford Filename TXCLKO
15. Baud Rate command from the debugger menu bar Note that setting the baud rate to a lower number can significantly slow the boards response to all debug activities 3 2 2 3 AD1819 Check Initialization On reset the AD1819 begins transmitting the clock used to synchronize data transfers over SPORTI Once this bit goes high the AD1819 is ready for standard communication over SPORTI The POST then writes and verifies three patterns to an internal register in the AD1819 Ifall three writes are verified the connection is verified 3 2 3 Monitor Program Operation The monitor program runs on the EZ KIT Lite board as part of the DSP executable and pro vides the ability to download debug and run user programs The VisualDSP debugger is the interface for the monitor and using the EZ KIT Lite as a target with the debugger lets you operate the board remotely There are three main components of the monitor program Halt loop e UART ISR Command Processing Kernel The monitor program idles in the Halt loop when it is not running user code While there you can read write memory read write registers download programs set breakpoints change the UART s baud rate modify the AD1819 configuration and single step through code To enter the halt loop from your code you must halt user code either with a breakpoint or a halt instruction At this point the halt loop polls the UART With every character received from the UART the command process
16. CHAIN IN PCHAIN CLK VREFOUT PC BEEP LINE IN R LINE IN L MIC1 MIC2 CD R CDL CD GND VIDEO R VIDEO L AUX R AUX L PHONE MONO OUT LINE OUT R LINE OUT L Line In Circuit Place C82 C85 R39 and R40 as close as possible to J8 Microphone Line In 0 33u Ferrite Bead C83 D 11 Ferrite Bead C139 IVA i PHONEJACK STEREO SW C140 Microphone In Circuit Place FB9 FB10 C and C as close as possible to J7 FB10 J7 Line Out Ferrite Bead FB9 Ferrite Bead PHONEJACK STEREO S W Analog Devices Inc One Tech nology Way ANA QE Norwood MA 02062 D Designed by Paragon Innovations Inc RARAGON mail info p itle Size B ate rawn B ilename ADSP 21065L EZ LAB CODEC Document Number 65 000299 02 1125 01 001 0201 Thursday November 19 1998 Kris Stafford Filename INDEX A ADSP 21065L IDterrupts e doe RU Ge 26 Analog Front End ADISIQZz PIER 26 B Bandpass demo 1 64 Baud Rate command sss 61 baud rate SettingS sese 21 Benchmarking example sss 35 38 BMS pin use with EPROME Ne 40 board features e RE ier tee 7 eedem 37 Break Points Single 22 C Check Initialization et 20 Code listings 67 CODEC as analog front end pp 26 buffer initializati
17. DSP specific technical information and documentation product overviews and product announcements 1 2 For Technical or Customer Support You can reach our Customer Support group in the following ways Email questions to dsptools support analog com e Contact your local Analog Devices sales office or an authorized Analog Devices distributor 1 3 Purpose of This Manual The ADSP 21065L EZ KIT Lite evaluation system manual gives directions for installing the evaluation board and software on the PC Also the manual provides guidelines for running user code on the ADSP 21065L 1 4 Intended Audience This manual is a user s guide and reference to the ADSP 21065L EZ KIT Lite evaluation board DSP programmers who are familiar with Analog Devices SHARC architecture operation and programming are the primary audience for this manual DSP programmers who are unfamiliar with Analog Devices DSPs can use this manual but should supplement this manual with the ADSP 21065L User s Manual the ADSP 21065L Technical Reference and the VisualDSP tools manuals 1 5 Manual Contents Description This manual contains the following information Chapter 1 Introduction Provides manual information and Analog Devices contact information Chapter 2 Getting Started Provides software and hardware installation procedures PC system requirements and basic board information Chapter 3 Using EZ KIT Lite Software Provides information on the EZ
18. KIT Lite system from a software perspective and details the monitor program EMAFE and codec Chapter 4 Demonstration Programs Provides information on VisualDSP debugger operation with the ADSP 21065L EZ KIT Lite benchmarking utilities and demonstration programs Chapter 5 Working With EZ KIT Lite Hardware Provides information on the Hardware aspects of the evaluation system Chapter 6 Expansion Connectors Provides information on EMAFE expansion and descriptions of connector interface signals Chapter 7 Reference Provides information on settings menu commands and demo menu commands Appendix Restrictions amp CPLD Code Listing Provides information on board restrictions you may encounter when using your EZ KIT Lite and the files used on the programmable device s on the EZ KIT Lite board Appendix B Bill of Materials Provides a list of components used in the manufacture of the EZ KIT Lite board Appendix C Schematics Provides a resource to allow EZ KIT Lite board level debugging or to use as a reference design 1 6 Documents and Related Products For more information on the ADSP 21065L and the components of the EZ KIT Lite system see the following documents e ADSP 21065L SHARC User s Manual amp Technical Reference e ADSP 21065L e AC 97 SoundPort The ADSP 2106x family of processors is supported by a complete set of evaluation tools Software tools include a C compiler assembler ru
19. Key PCC221CGCT ND mm RR uF SMTX antalum Low ESR 20 20 Kemit T494X107K020AS SMT0805 INPO 5 50 V IDigikey PCC270CGCT ND Panasonic ECU V1H270JCG 7 nm ISMTO0805 eramic 596 50 V Digi Key PCC470CGCT ND EBEN 59 C64 C65 C66 C67 C68 C76 EE TAJA105KO16R Digi Key PCT3105CT ND 6 C8 C10 C12 C14 C18 C19 C21 0 1 uF SMTO0805 5U 2094 50 V Allied 231 1294 23 C25 C37 C40 C41 C43 C45 C46 Murata GRM40Z5U104M050BL 48 C52 C53 C58 C61 C63 C70 C71 73 72 C73 C93 C94 C96 C101 C102 103 C104 C106 C107 C108 C116 118 C121 C123 C125 C128 C131 132 C136 C137 78 C80 C88 C90 1000 pF SMTO0805 5U 1094 50 V Digikey PCC102BNCT ND 83 C84 33 uF SMT3216 antalum 20 35 V igikey PCS6334CT ND anasonic ECS T1VY334R 16 6 1 D2 D3 D4 D5 D6 ED Green SMT Gull Wing ow Current Diffused T amp R HLMP 7040 11 mA 1 5 V ISMT0805 Itra Bright Red 50 mW anasonic LNJ208R8ARAF OmA 3V a A a ADC 2 0uSec 50 V hoke Coil 2020 pkg FBFBIBO 00545002000 FB13 IEMI Filter SMT1206 0 025 Ohm DC 3A urata BLM31P 5008 FB4 FB5 FB6 FB7 FB8 FB9 FB10 IEMI Filter Bead Inductor 200 mA urata BLM1 1 A601SPB o 2 12 pb HQ2 3 Male Rt Angle IKycon KLD SMT 0202 B ph nm hmm s Bb poNaooM Bamee TSW 13001TD PE ks Ex sunu board cds K22 E9S NJ ON32x3F 100 TH Femal
20. Supplies EPROM Operation UART EMAFE The EZ KIT Lite board schematics are available as an insert at the end of this manual 5 2 System Architecture Flag Inputs Flag Outputs 094294010 FOO IRQ Inputs Line in Stereo Mic in Stereo JTAG f Stereo I O Connector Line Out Stereo SPORT1 SPORTO Expansion Address Data Bus EMAFE Figure 5 1 EZ KIT Lite System Block Diagram The Enhanced Modular Analog Front End EMAFE connector is accessed through the ADSP 21065L processor bus 16 bit parallel interface and through two serial ports that connect directly to the processor One of these serial ports is shared with the on board AD1819A 39 5 3 Board Layout Figure 5 2 shows the layout of the EZ KIT Lite board This figure highlights the locations of the major components and connectors Each of these major components is described in the following sections Line Out MIC Line ia evs i i u u 059 pply pply MIC JP1 Line mic 222 JP1 Line Expansion ee Oscillator Es 3VCC ua Signalf Port JP3 Reset g J3 e 85232 Port Female er 5 Right Angle 82 cPLD as g A18 GND JP4 amp Pin savor Dopod 13 1 E JP8 aa LAS a UART D1 poche Fr IRQ P JP7 i ag In I Fower
21. WR TN I tPPD gt tPPD tPPD EMAFE AD NEN 777 tPPD ptPPD 4 1 13 13 35 78 gt iPPD tPPD Hg 39 emare wre S WDE tDDH tWDE tDDH gt D 0 31 lt lt tPP 5 NGEN 7 gt 1 tBU MD M NEED tBUF2 A LL Figure 5 6 EMAFE Write Cycle Timing Diagram Figure 5 7 EMAFE Read Cycle Timing Parameter Definitions 50 Ons 50ns 1 100ns 150ns EMAFE RD Timings I lt 2 69 gt tDWHA gt ADDR MSxf SWZ BMSHNEK DATT reltDDWR I 2 64 gt tDARL gt 3 1 tWWR tRW 41 tRWR RD L tPPD EMAFE RD tAWRL tDAWH tWW tDDWH WR tPPD tPPD I 21 78 ItPPD 17 36 EMAFE AD _ tPPD gt tPPD EMAFE_WR gt tBUFIVZ tBUF1ZV D 0 31 EMAFE_CS MD 0 15 0 7 P tBUF2 Figure 5 8 EMAFE Read Cycle Timing Diagram 51 6 Expansion Connectors 6 1 Overview The two expansion connectors provide access to the ADSP 21065L s interface pins These pins let the user watch data transmissions In addition the host interface interrupt and pwm event pins are also available on this
22. be modified while the BP demo program is running Use the Settings gt Codec command to change the sample rate input gain and source microphone input or line input Pluck dxe The pluck demo plays a tune to the Line Out connector To hear the output connect powered speakers to J7 Gunn dxe The Peter Gunn demo also plays a tune to the Line Out connector To hear the output connect powered speakers to J7 37 4 5 5 4 5 6 4 5 7 Primes dxe The primes demo program calculates the first 20 prime numbers staring with the number 3 and sends them to the output window The printf function is used in this demo e This demo maps seg dmda into SDRAM Therefore any added interrupts other then the codec s interrupt handler fail For more information see ADSP 21065L Memory Tt dxe The Talk through demo samples data from the Line In of the AD1819 J8 on the board with JP1 and JP2 set appropriately at 48 kHz and then sends the data back out the Line Out of the AD1819 77 e This demo maps seg dmda into SDRAM Therefore any added interrupts other then the codec s interrupt handler fail For more information see ADSP 21065L Memory Map Blink dxe The Blink demo program uses timer interrupt to blink flag LEDs 6 amp 7 38 5 WORKING WITH EZ KIT LITE HARDWARE 5 1 Overview This chapter discusses hardware design issues on the ADSP 21065L EZ KIT Lite board The following topics are covered Power
23. buffer an interrupt occurs If Tx Request gt 0 the interrupt loads the data from the User Tx buffer into the Tx buffer If the variable Tx Request lt 0 the Tx buffer is loaded with Os After the Tx buffer is loaded the DMA is initialized to transmit the new data in the Tx buffer The receive portion of the AD1819 interface is designed in a similar way The for SPORT I s receive register is configured to load the Rx buffer 22 When the Rx buffer is full an interrupt is generated that checks the Rx request variable If the variable gt 0 then the contents of the Rx buffer are written into the User Rx Buffer and the Rx request is cleared Afterwards the DMA is re initialized to fill the Rx buffer again 3 3 Running Your Own Programs This section provides the user with the basic information that is needed to run their own programs on the ADSP 21065L EZ KIT Lite Build these programs using the SHARC tools This information includes rules for using processor memory a description AD 1819 control registers with respect to DSP programming and a simple program generation procedure Although there are many ways to go about developing programs in the VisualDSP environment all program evaluation within the environment should include the following steps Stepl Create a New Project File Step 2 Set Target Processor Project Options Step 3 Add and Edit Project Source Files Step 4 Customize Project Build Options Step 5 Build
24. connector Table 6 1 Expansion Connectors b s mr Dee clus 2651 ow fay lu pe a s m jus lue b bow m n peo ju b 5 ws n as leo opm b no jm y no je opm s m e jus bo s ew ms war muc ius luas sr oo fr mo msi hv Table 6 1 Expansion Connectors Cont 52 Pin Nam Nae si EE panD Eun pe hc as js uu 6 2 EMAFE Expansion WARNING Using the EMAFE interface connector to connect to a MAFE board can damage the ADSP 21065L EZ KIT Lite the MAFE or both This section describes the Enhanced Modular Analog Front End EMAFE Daughter Card interface for the ADSP 21065L digital signal processor evaluation board The EMAFE interface includes additional signal definitions for the IS capabilities of the ADSP 21065L processor The EMAFE allows an upgrade path for evaluating present and future codec s and ADC s 18xx AD7xxx multimedia codec etc with the ADSP 21065L evaluation board Only the analog front end will be placed on a daughter board Each EMAFE daughter board will have its own back plate to allow different input connections 1 e RCA jack Mic in speaker out etc The daughter board is attached to the ADSP 21065L evaluation board by a single 96 pin right ang
25. functionality Ifthe user does not connect an EMAFE to the EZ KIT Lite IRQ1 with SW4 can be configured for other purposes If an EMAFE card 15 attached and it uses IRQI there is no way to disable the EMAFE s control of the interrupt line If the EMAFE is not attached IRQI is available for other uses Note the monitor program does not interact with the EMAFE board and does not have any response to an IRQI request 3 2 1 3 Serial Ports The ADSP 21065L features two synchronous Serial Ports SPORTO and SPORT1 The SPORTS can operate at up to 1x clock frequency providing each with a maximum data rate of 30 Mbit sec Each SPORT has a primary and a secondary set of transmit and receive channels SPORT data can be automatically transferred to and from on chip memory using DMA 18 Each of the SPORTS supports three operation modes DSP SPORT mode PS mode an interface commonly used by audio codecs and TDM Time Division Multiplex multichannel mode For additional information on the serial ports please refer to Chapter 9 of the ADSP 21065L SHARC User s Manual Both of the synchronous serial ports are connected to the EMAFE interface SPORTI is also connected to the on board AD1819 Jumper JP3 is used to disable the AD1819 so it doesn t interfere with the EMAFE For normal operation of the AD1819 JP3 must be connected to GND If the EMAFE is using SPORTI the serial communication to the AD1819A should be disabled by connecting JP3 to 3 3
26. macrocell CPLD with in circuit programmability The functions performed are l Extends the EPROM read cycles board silicon revision 0 0 only The access cycles used by the ADSP 21065L when booting are too short for the EPROM therefore the CPLD deasserts the line long enough to extend the cycle to an appropriate time for the EPROM Translates the read and write cycles into cycles that are appropriate for the UART The timing requirements between the chip select read write lines and data accesses are different between the ADSP 21065L and the UART The CPLD corrects for these differences Additionally there is a minimum time restraint between subsequent access to the UART The CPLD accounts for this needed time delay Translates ADSP 21065L read and write cycles into cycles appropriate for the EMAFE 64 Listing CPLD File xx Copyright c 1998 Analog Devices Inc All Rights Reserved Revision History OPE Hem Eee 05 26 98 Original 05 27 98 inverted ack output to ack bar Allows addition of o
27. to the ADSP 21065L EZ KIT Lite evaluation board running the debug monitor via the serial port no emulator or simulator support Additionally the linker will restrict the user to only 25 2 5k words of the ADSP 21065L s on chip program memory space If the full VisualDSP software suite is purchased the user will obtain new serial number from Analog Devices that will lift the restrictions mentioned above The basic components that are shipped with VisualDSP are e Integrated Development Environment IDE graphical interface for project management allowing the user to set project options access the code generation tools and launch the debugger e Debugger allows the user to view the insides of the DSP and perform debug operations such as read write memory read write registers load programs run step halt and more e SHARC Family Code Generation Tools C compiler assembler runtime libraries and librarian linker simulator and PROM splitter e Example Projects Both VisualDSP and the ADSP 21065L EZ KIT Lite are shipped with example projects and C and Assembly source code that demonstrate various features of the tools and ADSP 21065L DSP 2 5 Installation Procedures The following procedures are provided for the safe and effective use of the ADSP 21065L evaluation board Itis important that you follow these instructions in the order presented to ensure correct operation of your software and hardware 2 5
28. 0 wr_bar rd_bar cs_ bar in std_logic 65 bms bar in std logic Wait u en bar u rd bar u wr bar out std logic ack out std logic e cs bar e rd bar e wr bar e addr out std logic codec rst bar out std logic EPROM input UART Outputs to DSP EMAFE Outputs CODEC Reset attribute pin_avoid of interface entity is 1 13 21 33 avoiding programming contol pins Need to lock pin numbers to prevent accidental changes attribute pin numbers of interface entity is reset 26 clk 7 wr bar 29 rd _ bar 9 cs bar 15 addr 3 11 addr 2 12 addr 1 14 addr 0 27 amp amp bms bar 10 u en bar 30 u rd bar 32 u wr bar 22 amp ack 18 e cs bar 36 e rd bar 23 e wr bar 24 e addr 37 amp codec rst bar 8 end interface architecture state machine of interface is type StateType is IDLE CS1 CS2 WRI WR2 ENDW2 ENDW3 ENDW4 CS3 CS4 CS5 RD2 RD3 RD4 ENDR1 Signal present state next state StateType Signal u ack std logic ACK signal generated from UART Signal u ack v std logic UART ACK valid signal Signal w ack std logic ACK signal generated from EPROM signal w ack v std logic EPROM ACK valid signal Signal uart ctrl d std logic vector 2 downto 0 u rd bar d u en bar u wr bar d next state of uart control signals type WAIT STATE is WAITO WAIT1 WAIT2 WAIT3 WAIT4 WAIT6 Signal present
29. 0 AD1819 reset address external block 0 0x03000000 0x030FFEFF User space external block 3 1048320 32 bit locations in SDRAM 25 3 3 2 Using the AD1819A SoundPort Codec as the Analog Front End There are two ways you can use the AD1819 SoundPort codec on the 21065L EZ KIT Lite with the VisualDSP debugger Method 1 Use the codec DMA buffers and the codec interrupt handler within the EPROM monitor that are installed by the AD1819 SPORT I initialization routine in the EPROM Monitor Program This method is useful if you want to quickly test your DSP algorithm This method may be preferable for early DSP evaluation and the user does not need to be concerned with many of the details of the AD1819 theory of operation The following section provides coding guidelines for the programmer to link in the required codec and SPORT DMA buffers All of the audio demos provided with the ADSP 21065L EZ KIT Lite use this method for communicating with the codec for RS 232 host codec control Method 2 Disabling and Overwriting the SPORT1 DMA codec buffers and down loading a custom AD1819 SPORT I initialization routine with the RS 232 monitor The custom user routine includes instructions necessary to reset the codec program SPORTI activates serial port I transmit and receive DMA transfers and programs any AD1819a register to a desired configuration This method may be preferable if you want to test AD1819 code that may be downloa
30. 2 Open Top Gold Plating Samtec 2SN BK G SFs SJP11 222 ks SJP8 SHUNT2 O Open Open Top w Hande w Handle A 881545 1 881545 1 m SW2 SW3 SW4 SW5 SW6 SW7 SWITCH er omentary SPST washable amp K KT11P2JM 75 rp HEADERIXI 100 TH Male single TSW 101 07 L S 51 oltage 5 8 ink 3 3V Analog Devices ADP3310AR 3 3 IRegulator 74LVCH162 SSOP 48 45A HE E Audio OpAmp 8 Pin SOIC Dual Single Supply 4V to Analog Devices SSM2135S 36V 4LCX574 SSOP 20 Octal Edge Trigg D Flip Flops Fairchild 74LCX574MTC 3 State out puts 5V Motorola MC74LCX574DT olerant 24 mA 1 5 8 5 ns B 3V PE 5 8 AC 97 Compliant 5 0V Analog Devices AD1819A JST odec 74LCX125 SSOP 14 Quad bus buffers w 3 state Fairchild 74LCX125MTC outputs w Bus Hold 5 Motorola MC74LCX125DT 22 00 5 3 3 IMacronix MX27L2000 DC 20 MI Ee ES ERE ER TI 83MHz 3 3V INEC uPD4516161AG5 A10 RE E eme Regulator HTTP eier 3 3 76 olerant 3 3 V oshiba 74LCX 14FT Rx 5 V ee DONUM 74LPT245 ISOP 20 Octal Bus Transceiver w Bus Digikey PI74LPT245AS ND Hold 5V Tolerant 32 64 1 E 1 0 4 0 ns 3 3 V Open collector Hex inverter B 5ns 5 0 V a a 75mA 12ns 5 0V 3 3V ee ee eee 18 432MHz rystal Parallel 50 ppm pson MA 505 24 576M C2 4 576MHz Oscillator 50 ppm 20 mA IM Tron M3A14FAD30 0000 30 0 MHz 3
31. 3 gt seg bnk3 This ensures that the linked variables reside as follows DM user tx buf is placed at addresses 0x030FFFO00 0 030 05 e DM user tx ready is placed at address 0x030FFF06 DM user rx buf is placed at addresses 0x030FFF07 0x030FFFOC DM user rx ready is placed at address 0x030FFFOD For examples on how these codec variables are declared and linked together with ADSP 30 210651 EZ KIT Lite and assembly programs the user can inspect the source files for the EZ KIT Lite audio demos 3 3 4 DSP Programming of the AD1819 Indexed Control Registers The monitor program provides setup routine for the AD1819 Table 3 7 shows the registers used by the DSP and their state after reset The user can use the monitor buffers contained in the demo programs or write their own code to use the AD1819 codec The code must initialize these registers when using the AD1819 For example programs and further documentation on AD 1819 programming with the ADSP 21065L you can visit our web site at www analog com dsp Table 3 7 DSP Programming of the AD1819 Indexed Control Registers Address fndex Register Name Label in 2106x program Master Volume Mono MASTER VOLUME MONO 0x8000 FR Microphone Volume MIC VOLUME 0x8008 Line Volume LINE IN VOLUME 0x8808 Record Gain RECORD GAIN OxOFOF w l General Purpose GENERAL PURPOSE 0x8000 Sample Rate 0 SAMPLE RATE GENERATE 0 0 80 il Sa
32. 9001at the SPORT1 Tx interrupt vector location 3 3 3 2 Linking Your Code to the RS 232 Monitor DMA Buffers The monitor constantly sends and receives packets from the codec To send data to the codec the user needs to put the desired data into the codec transmit buffer and set the transmit variable Similarly to receive data from the codec the receive variable should be set to a value gt 0 The variable may then be polled for the change back to 0 When this happens codec data has been transferred into the codec receive buffer and may be read Figure 3 1 shows the software structure of the codec data transfer The transfer is set up by the RS232 monitor program via EPROM boot 27 User Tx Buffer User Rx Buffer Tx Request Tx Buffer Rx Request AD1819A Codec SPORT1 Figure 3 1 ADSP 21065L EZ KIT Lite Monitor Kernel Codec Transfer Scheme 3 3 3 2 1 DSP Codec Transmit Sequence 1 The SPORTI transmit DMA empties the transmit buffer a SPORTI transmit interrupt occurs If the variable Tx Request gt 0 then the interrupt loads the data from the User Tx Buffer into the Tx Buffer otherwise the Tx Buffer is loaded with Os After the Tx Buffer is loaded the DMA is re initialized to transmit the new data in the Tx Buffer With this structure set up by the monitor the user needs to only put data in the User Tx Buffer and then set Tx Request to 1 to send data to the codec 3 3 3 2 2 DS
33. ADSP 21065L EZ KIT Lite Evaluation System Manual Part Number 82 000490 01 Revision 1 0 December 2000 ANALOG DEVICES Notice Analog Devices Inc reserves the right to make changes to or to discontinue any product or service identified in this publication without notice Analog Devices assumes no liability for Analog Devices applications assistance customer product design customer software performance or infringement of patents or services described herein In addition Analog Devices shall not be held liable for special collateral incidental or consequential damages in connection with or arising out of the furnishing performance or use of this product Analog Devices products are not intended for use in life support applications devices or systems Use of an Analog Devices product in such applications without the written consent of the Analog Devices officer is prohibited Users are restricted from copying modifying distributing reverse engineering and reverse assembling or reverse compiling the ADSP 21065L EZ KIT Lite operational software one copy may be made for back up purposes only No part of this document may be reproduced in any form without permission Trademark and Service Mark Notice The Analog Devices logo SHARC the SHARC logo VisualDSP the VisualDSP logo and EZ ICE are registered trademarks and TigerSHARC the TigerSHARC logo White Mountain DSP VisualDSP the VisualDSP logo Apex ICE EZ KIT Lite Mo
34. C include the following file found in buffers asm in your code TITLE BUFFERS ASM BUFFERS ASM Links variables into the same locations the kernel uses so that the demo can talk to the kernel to use its codec isr GLOBAL user tx buf GLOBAL user tx ready GLOBAL user rx buf GLOBAL user rx ready GLOBAL user data out ptr GLOBAL user num data GLOBAL user data type SEGMENT DM seg bnk3 make the buffers line up the same as in the kernel 29 var user tx buf 6 var user tx ready Var user rx buf 6 var user rx ready ENDSEG Note that these variables have leading underscore to make them C compatible If writing in assembly code include the following segment within the data variable declaration section in the same assembly codec file as the DSP code SEGMENT DM seg bnk3 VAR user tx buf 6 VAR user tx ready Codec isr set up by the kernel flags and buffers VAR user rx buf 6 VAR user rx ready ENDSEG In addition to the variable declaration the users needs to tell the linker to place these variables in the specified monitor kernel program locations for the codec in bank 3 This is done by including the following lines in the Linker Description File MEMORY seg bnk3 TYPE DM RAM 5 0 030 00 END 0x030FFFFF WIDTH 32 PROCESSOR SECTIONS seg_bnk3 INPUT SECTIONS SOBJECTS seg_bnk3 SLIBRARIES seg_bnk
35. IST OF FIGURES FIGURE 6 1 PHYSICAL LAYOUT OF ADSP 21065L DSP EVALUATION BOARD AND EMAFE DAUGHTER INTRODUCTION Thank you for purchasing the ADSP 21065L EZ KIT Lite evaluation kit The evaluation board 15 designed to be used in conjunction with VisualDSP development environment and is based on the ADSP 21065L SHARC floating point digital signal processor DSP The kit is shipped with an evaluation board and VisualDSP software The VisualDSP that comes with the kit will only operate with the evaluation board The complete version must be purchased seperately Using the EZ KIT Lite with VisualDSP you can observe the ADSP 21065L DSP execute programs from on chip RAM interact with on board devices and communicate with other peripherals You can access the ADSP 21065L SHARC processor using the PC through a serial port or an optional JTAG emulator The monitor program that runs on the EZ KIT Lite gives you access to the ADSP 21065L processor s internal memory space through the serial port In contrast the JTAG emulator allows the PC to perform in circuit emulation through the processor s JTAG interface The board s features include e Analog Devices ADSP 21065L DSP running at 60MHz e Analog Devices ADI819A 16 bit SoundPort Codec e RS232 interface e Socketed EPROM 128K x 8 on board or 256K x 8 512K x 8 and x 8 selectable e SDRAM IM x 32 e Four push buttons for Flag inputs e Three push buttons for IRQ i
36. MAFE 96 pin connector also has the following power connections routed from the ADSP 21065L evaluation board to the EMAFE daughter board Table 6 2 Evaluation Board Power Connections Pin Power Connection VDDI Digital power 5V 150 mA VDD2 Digital power 3 3V 150 mA 54 The connector provides standard interface for connecting analog input output daughter boards The connector has 96 pins arranged in three rows of 32 pins The pinout is given in Table 6 3 anda description of each of the pins is listed alphabetically in Tables 6 4 through 6 6 Table 6 3 EMAFE Connector XCLKO CLKO XCLKI pus 7 ror pus xp 55 6 2 1 EMAFE Connector Interface Signal Descriptions Table 6 4 EMAFE Connector Interface Signal Description Row Parallel Data Bit 0 BUFFERED ADSP 21065L D16 D2 Parallel Data Bit 2 BUFFERED ADSP 21065L D18 4 Parallel Data Bit 4 BUFFERED ADSP 21065L D20 Digital Ground Parallel Data Bit 6 BUFFERED ADSP 21065L D22 Parallel Data Bit 8 BUFFERED ADSP 21065L D24 D10 Parallel Data Bit 10 BUFFERED ADSP 21065L D26 DD1 Digital Power 5v MDI2 Parallel Data Bit 12 BUFFERED ADSP 21065L D28 MDI4 Parallel Data Bit 14 BUFFERED ADSP 21065L D30 Flag Input Digital Ground R RD XDI ag 56 Table 6 5 Connector Interface Signal Description Row n Digital Power 3 3V sed se
37. P Codec Receive Sequence 1 The receive portion of the codec interface is designed in similar way to the transmit portion The DMA for SPORT I s receive register is configured to load the Rx Buffer When the Rx Buffer is full an interrupt is forced that checks the Rx Request variable If the variable gt 0 then the contents of the Rx Buffer is written into the User Rx Buffer and the Rx Request is cleared The DMA is re initialized to fill the Rx Buffer again 28 3 3 3 3 RS 232 Monitor Codec Memory To use the monitor s codec variables examine the buffers asm and ldf files provided with the demos These two files provide access to the necessary variables by overlapping the locations of the variables The RS 232 Monitor Program was complied and linked to place the following user variables and buffers to communicated to the codec in the following memory locations 0x030FFF00 0x030FFF05 User CODEC transmit buffer DM user tx buf 0x030FFF06 User CODEC transmit ready flag DM user tx ready OxO30FFFO7 0x030FFFOC User CODEC receive buffer DM user rx buf 0x030FFFOD User CODEC receive ready flag DM user rx ready When writing code the user needs to define variables so that they are linked in to these exact locations as was defined by the monitor kernel so that your DSP code has access to the kernel codec buffers To use this scheme for passing audio data for user DSP algorithm written in
38. S SW CPA BR1 BR2 DMAR1 DMAG1 DMAR2 DMAG2 IRQO IRQ1 IRQ2 FLAG O 3 FLAG 4 9 MFLAG PWM EVENTO PWM HBR HBG CS REDY SBTS SW CPA BR1 BR2 DMAR1 DMAG1 DMAR2 DMAG2 DSP_CLK RESET Proc Main A 0 23 D 0 31 ACK WR RD PROM_CS MSO MS1 MS2 MS3 SDA10 RAS CAS SDWE DQM SDCKE SDCLKO TFSO DTOA DTOB TXCLKO RFSO DROA DROB RXCLKO TFS1 DT1A DT1B TXCLK1 RFS1 DR1A DR1B RXCLK1 CODEC ON Br L UART CPLD A 0 5 EMAFE_WR 0 7 EMAFE_RD EMAFE_CS ACK EMAFE_ADDR WR RD CODEC_RST PROM_CS MS1 PLD_CLK RST UART CPLD 0 19 D O 31 RD PROM_CS MS3 SDA10 RAS CAS SDWE DQM SDCKE SDCLKO D 0 15 WR EMAFE_RD EMAFE_CS EMAFE_ADDR IRQ1 MFLAG TFSO DTOA DTOB TXCLKO RFSO DROA DROB RXCLKO TFS1 DT1A DT1B CODEC 5 TXCLK1 RFS1 CHAIN CLK DR1A CHAIN IN DR1B CODEC 50 RXCLK1 CODEC CS1 CHAIN CLK CHAIN IN CODEC 50 CODEC CS1 DT1A TXCLK1 RFS1 DR1A RXCLK1 CODEC Analog Devices Inc One Tech nology Way ANA QE Norwood MA 02062 D Designed by Paragon Innovations Inc RARAGON mail info p itle ADSP 21065L EZ LAB Page Title Size Document Number B 65 000299 02 1125 01 001 0201 ate Wednesday November 18 1998 rawn By Kris Stafford ilename Filename heet Cap added to reduce emissions since 3 3V log
39. a Debug Version of the Project Step 6 Debug the Project Step 7 Build a Release Version of the Project By following these steps DSP projects build consistently and accurately with minimal project management The ADSP 21065L SHARC Technical Reference and ADSP 21065L SHARC User s Manual provides detailed information on programming the processor and the VisualDSP manuals provide information on code evaluation with the SHARC tools Do not run more than one ADSP 21065L EZ KIT Lite Session in the debugger at any one time You may run an EZ KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ KIT Lite session Before making changes to the source code in the IDE the user needs to clear all breakpoints and close the source window Then make the changes rebuild the program and reload it into the debugger 3 3 1 ADSP 21065L Memory Map The ADSP 21065L EZ KIT Lite board contains 1M x 32 of external SDRAM This memory is connected to MS3 Memory Select The ADSP 21065L has 544 Kbits of internal SRAM that can be used for either program or data storage The configuration of on chip SRAM is detailed in the ADSP 21065L SHARC User s Manual Table 3 5 shows the memory map of the ADSP 21065L EZ KIT Lite The IMDWO bit in the SYSCON register must be set to 1 to keep communication with the host This bit determines if data accesses made to internal memory block 0 are 40 bit three co
40. actory default 5 6 EPROM Operation The EPROM shipped with the EZ KIT Lite is a 256K x 8 bit EPROM The socket can accommodate a 128K x 8 256K x 8 512K x 8 ora 1M x 8 bit EPROM If any of these other EPROMS are used jumpers 1 4 and JP5 should be changed to route the correct signals to the EPROM Settings for these jumpers are shown in Table 5 4 46 EPROM addressing differs depending on the silicon revision of the ADSP 21065L on your EZ KIT Lite board For revision 0 1 silicon EPROM addressing begins at address 0x020000 For revision 0 2 and greater addressing begins at address 0x000000 i e you can use all memory space see Figure 5 4 5 6 1 Designers Note When JP6 is removed or connected to GND the ADSP 21065L is initialized to boot from the EPROM On this board the ACK line is used to control wait states EPROM Addressing Actual Addressing e 0x03FFFF 0x07FFFF Mirrored 0x020000 EPROM 0x060000 0x040000 Ox03FFFF 0x000000 0x03FFFF Initial Address of EPROM Boot J3 0x020000 rev 0 1 0x020000 Initial Address 0x000000 of EPROM Boot rev 0 2 0x000000 Figure 5 4 EPROM Address 256K x 8 example 5 7 UART The UART used is a 5V part therefore a 74LVTH245 is used to translate the data coming from the UART to the required 3 3V logic needed by the processor 5 7 1 Designers Note To access the UART correctly the relationship between the timing of the data chip select and the read writ
41. d IDi sed sed IDi sed sed 57 Table 6 6 Connector Interface Signal Description Row AME MDI Parallel Data Bit I BUFFERED ADSP 21065L D17 D3 Parallel Data Bit 3 BUFFERED ADSP 21065L D19 D5 Parallel Data Bit 5 BUFFERED ADSP 21065L D21 DGND Digital Ground D7 Parallel Data Bit 7 BUFFERED ADSP 21065L D23 Parallel Data Bit 9 BUFFERED ADSP 21065L D25 Parallel Data Bit 11 BUFFERED ADSP 21065L D27 c3 pb igital Power 5v c22 Parallel Address Bit 6 LATCHED ADSP 21065L D22 CS Module Select Asserted Low WR Module Write Asserted Low Cos Digital Power Sv IR C7 RESO Receive Frame Sync Port 0 Digital Ground Digital Ground eceive Clock Port I Receive Frame Sync Port 1 Receive Data Port 1 eceive Clock Port 0 58 7 Reference 7 1 Overview This chapter is a reference for VisualDSP Because the debugger is dynamic menu selections commands and dialogs change depending on the target being used This chapter provides information on all of the menu selections commands and dialogs when the target is the ADSP 21065L evaluation board For all other debugger commands see the VisualDSP Guide amp Reference Note that grayed out commands are unavailable with this target 7 2 Settings Menu Commands All of the commands that pertain to the EZ KIT Lite board are contained in the Settings and Demo menus The Settings menu provides access
42. de bmtools h int clock start clock count clock start count start lt insert code here gt clock count count end clock start For complete code example that shows the version of the benchmark utility see the DFT c bm example that is included in the Examples folder An assembly version of the count start and count end functions are also available To use this version insert a pair of function calls one to start the cycle count count start and another to end the cycle count count end The elapsed number of cycles is stored within a 48 bit wide memory location ecount save These functions are completely self contained no saving or restoring of registers 1s necessary User must Run any program that uses this code from when the function count start starts to at least as far as the function count end returns without halting or stepping to obtain an accurate cycle count Call count start insert code here Call count end For a complete code example that shows the assembly version of the benchmark utility see the DFT assm bm program that is included in the Examples folder Note that both the C and assembly utilities require that bmtools dlb be included in the Libraries statement of the project s LDF Linker Description File For more information on LDF files refer to the Linker amp Utilities Manual for ADSP 21xxx Family DSPs Both the assembly and C versions of the benchmarking utilities should operat
43. ded via the SHARC JT AG burnt into a new EPROM or to test AD1819 functionality in a new custom based 21065L design For detailed AD1819 and SHARC interface information and example source that demon strates this second method contact Analog Devices DSP hotline or search our web site for the following document Interfacing The ADSP 21065L SHARC DSP to the AD1819a AC 97 SoundPort codec Further information on the AC 97 serial protocol may be found in the AD1819A Datasheet 3 3 3 Method 1 Using the Monitor s Codec DMA Buffers and Interrupt Handler This section provides more detail on Method 1 from the previous section The ADSP 21065L uses DMA transfers to automatically send and receive data from the codec After codec reset the codec begins transmitting the clock used to synchronously transfer data across SPORT1 The ADSP 21065L in turn initiates all transmissions with the codec by sending a frame synchronization pulse Even though the codec transmits the data clock it may not be ready for normal operation While the codec is not ready it holds the first bit codec Ready bit of SLOT 0 low When ready this bit is driven high Once this bit goes high the codec is ready for standard communication with the ADSP 21065L The AD1819 initially expects all data transfers to be in packets according the AC 97 spec ification where there is 1 x 16 bit time slot and 12 x 20 bit slots in the TDM audio frame This packet scheme does not work well i
44. dy and equipment and can discharge without detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD precautions are recommended to avoid performance degradation or loss of functionality Fab SEREIRE DEVICE Unused EZ KIT Lites should be stored in the protective shipping package The ADSP 21065L EZ KIT Lite evaluation board package should contain the following items If any item is missing contact the vendor where you purchased your EZ KIT Lite or Analog Devices e ADSP 21065L EZ KIT Lite board Power cable with DC power supply 7 5 Volts e RS 232 serial port 9 pin cable EZ KIT Lite CD containing examples target dll files help files and utilities e VisualDSP CD e Registration card please fill out and return 11 2 3 PC Configuration For correct operation of the VisualDSP software and EZ KIT Lite demos all computers must have the minimum configuration shown below Table 2 1 PC Minimum Configuration 2 button mouse 2 button mouse 100 MB available space 100 MB available space 32 MB RAM 32 MB RAM CD ROM CD ROM 2 4 VisualDSP The ADSP 21065L EZ KIT Lite system is shipped with the VisualDSP Integrated Development Environment IDE debugger and code generation tools VisualDSP is limited in functionality by the EZ KIT Lite serial number that is shipped with this product The EZ KIT Lite serial number restricts the VisualDSP debugger to only connect
45. e Right Angle Samtec SSW 132 T 02 T T RA ERE JACK Bn 500VDC horizontal Switcheraft 35 2 1 10074 Mae Bamtee TSW 17 07 T S P1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 ON3M DmmSMT Samtec 103 01 5 5 5 74 1 20V anasonic ERJ 6GEY J390 Panasonic ERJ 6GEYJ101 R19 R20 R21 R22 R23 R24 R25 R20 R21 R22 R23 R24 R25 910 bi00hm ISMTO0805 hick Film 5 1 10 W 100 V Bourns CR0805 911 JVCA IR34 R36 R42 R44 R76 IK Ohm SMTO0805 hick Film 5 1 10 W 100 VBourns CR0805 102 JVCA Panasonic ERJ 6GEYJ102 hk 35 R35 R37 R43 R45 R43 R45 47K Ohm SMT0805 hick Film 5 1 10 W Digi Key P47KACT ND R38 R41 0K Ohm SMT0805 hick Film 5 1 10 W Allied 297 9552 Digi Key P20KACT ND bo R R39 R40 R40 IK SMT0805 hick Film 5 1 10 W Digi Key P5 1KACT ND IM iMOhm ISMTO0805 hick Film 5 1 10 W Digi Key P1 0MACT ND Digikey 767 163 R33 ND Digikey 767 161 R10K ND GA 5K Ohm ISMTO0805 hick Film 5 1 10 W 100 V Bourns CR0805 152 JVCA s R R9 R10 R12 R14 R15 R17 26 10 Ohm hick Film 5 1 10 W 100 V Bourns CR0805 103 JVCA 27 R29 R31 R32 R47 R48 R49 R50 anasonic ERJ 6GEYJ103 51 R57 R64 R72 R75 R78 R79 R80 00250 SMT 1 1 4W Dale WSL1206R025FB25 QUEM NEM ER T Ohm EMTI206 1 LA W Dale WSL1206R050FB25 SJP1 SJP2 SJP3 SJP4 SJP5 SJP6 SHUNT
46. e and license have been installed click the Windows Start menu 1 Select Programs gt VisualDSP gt Debugger from the Start menu The debugger interface appears 2 From the Session menu select New Session The Target Selection dialog appears 3 Configure the debug session as shown in Figure 4 1 and click OK Target Selection 21x Debug target Processor 21065L Platform JEZ KIT Lite Target name PosP2l 065L EZ KIT Lite EZ KIT 210 Cancel Figure 4 1 Target Selection Dialog A Target Message dialogue box will appears 32 Target Message N Hit Reset button on board Figure 4 2 Target Message 4 Press the Reset button on the evaluation board All the LEDs light up and after a brief delay lt 2 seconds all of the LEDs turn off except for the FLAG and power LEDs Make sure that the LEDs turn off except for the FLAG9 and power LEDs before you click OK During this delay the POST tests run which verify operation of RAM the AD1819 the UART and the EPROM After the LEDs go dark a message box opens with the message shown in Figure 4 3 Target N Communications Success Figure 4 3 Target Communications Status Message Box 5 Click OK The initialization completes and the disassembly window opens The code in the disassembly window is the EZ KIT Lite monitor program 4 3 Debugger Operation with the ADSP 21065L EZ KIT Lite The VisualDSP Debugger Guide amp Reference and the D
47. e in the command processing kernel This kernel parses the commands and executes the instructions If the instruction requires data to be sent back to the host the kernel initiates the response 3 2 3 1 Break Points The ability to stop the execution of code and examine processor registers and memory is extremely helpful when debugging code Note that the debugger automatically inserts breakpoints an the function Main when the Settings gt Run To Main command is checked and at the exit instruction 3 2 4 AD1819 Transmissions After reset the AD 1819 generates the clock used to transfer data across SPORT1 The ADSP 21065L initiates all transmissions with the AD1819 by sending synchronization pulse Even though the AD 1819 transmits the data clock it may not be ready for normal operation Until the AD1819 is ready it holds the first bit AD1819 Ready bit of SLOT 0 low When ready this bit is driven high The first transmission to the AD1819 is done differently than subsequent transmissions The packets initially expected by the AD1819 do not have consistent size This first transmission instructs the AD1819 to standardize the packet size to 16 bit This command is created by shifting and stuffing bits in the transmit buffer Slot 0 in each transmission specifies which slots contain valid data The ADSP 21065L uses DMA transfers to automatically send and receive data from the AD1819 When the transmit empties the transmit
48. e lines needed to be changed Most of these changes were implemented through a CPLD An additional 10ns delay was needed on the control lines Since this delay was not possible through the CPLD a digital delay was added to the circuit It is important to note that the UART and the CPLD only decode a subset of the available address lines Because of this partial decoding the UART is aliased throughout the MS1 address space 47 5 8 EMAFE The indexed addressing required by the EMAFE interface is implemented through the CPLD The CPLD controls the loading of the address as well as the data direction of the data bus As with the UART the address is only partially decoded The aliasing seen with the UART also exists with the EMAFE interface in the MS1 address space On the ADSP 21065L data is valid when the WR line goes high If an address hold cycle is enabled in the WAIT register the data stays valid through the WR transition The parallel communication between the ADSP 21065L processor on the evaluation board and the EMAFE consists of some control logic for the control lines MC RD WR CS etc an 8 bit latch that stores the address information MA 7 0 and a transceiver buffer for the data lines MD 15 0 The address lines are latched and the data lines are buffered to reduce digital noise on the EMAFE board The serial ports from the ADSP 21065L are directly wired to the EMAFE connector interface pins Level shifting of serial p
49. e on any SHARC processor The maximum number of cycles that can be counted is 2 gt 1 36 4 5 Demonstration Programs The demos included with the EZ KIT Lite are designed to show the user the features and capabilities of the VisualDSP Debugger and the ADSP 21065L DSP The demos are listed by the executable file name and are described by their output All of the demos are located in the directory C Program Files Analog Devices VisualDSP 21k ADSP21065L EZ KIT Demos e not run more than one ADSP 21065L EZ KIT Lite Session in the debugger at any one time User may run an EZ KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ KIT Lite session 4 5 1 4 5 2 4 5 3 4 5 4 FFT dxe The DFT demo performs a frequency analysis on an analog signal presented to the board Use the Demo menu command in the debugger to change how the DFT is performed e This demo maps seg dmda into SDRAM Therefore any added interrupts other then the codec s interrupt handler fail For more information see ADSP 21065L Memory Map BP dxe The BP demo modifies a signal by subjecting it to a bandpass filter As in the previous demo the source of the signal may be changed through the codec controls available through the Settings Codec command A demo specific control window is also available to change some parameters of the bandpass filter Several AD1819 options can also
50. e the debugger to crash The IMDWO bit in the SYSCON register must be set to 1 to keep communication with the host The IMDWO bit determines if data accesses made to block 0 are 48 bit three column accesses 1 or 32 bit two column accesses 0 The monitor program requires three column data accesses to memory block 0 If The IMDWO bit is set to 0 the monitor accesses incorrect memory locations within block 0 See User s Manual for further discussion of IMDWO The setting of IMDWO will have no effect on C programming as long as RND32 is not set for 40 bit floating point precision Do not run more than one ADSP 21065L EZ KIT Lite session in the debugger at any one time You may run an EZ KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ KIT Lite session 63 12 The product as documented describes the debugger s Settings Codec Sample Rate menu command as follows Opens the Sample Rate dialog that lets you select a sample rate from 7000 to 48000 Hz The default sample rate is 48000 Do NOT change the sample from this setting If you need to change sample rates for your program you will need to write your own CODEC driver Information on doing this is provided in Chapter 3 of the ADSP 21065L EZ KIT Lite Evaluation System Manual A 1 CPLDFile Listing A 1 shows the Cypress WARP file used to program the CPLD on the board The CPLD is a CY73711 83AC which is a 32
51. ebugger Tutorial for ADSP 2106x Family DSPs contains most of the information you need to operate the VisualDSP Debugger with your EZ KIT Lite evaluation board Because the manual was written using simulator as target there are some differences and restrictions in debugger operation that are described in this section 4 3 1 Loading Programs Because you are loading programs into hardware target the load process takes bit more time then loading in the simulator Wait for the Load Complete message in the Output window before you attempt any debug activities 33 4 3 2 4 3 3 To load program use the following procedure 1 From the File menu select Load The Open Processor Program dialog appears 2 Navigate to the folder where the DSP executable file resides The demos that are supplied with the EZ KIT Lite are located in C Program Files Analog Device VisualDSP 21k EZ KITs 21065L demos folder 3 Select the dxe file and click Open The file loads and the message Load Complete appears in the Output window when the load process has completed Registers and Memory To see current values in registers use the F12 key or the Window Refresh command Values may not be changed while the user program is running The current version of the VisualDSP Debugger does not let you view hardware stack information Setting Breakpoints and Stepping Breakpoints set in the last three instructions of do loo
52. ection A18 IMx8 A18 512K x 8 5 5 3 Processor ID Jumpers During typical operation of the EZ KIT Lite board there is only a single DSP in the system Jumpers JP7 and JP8 should be checked to guarantee that the board is configured as a single processor system In the case where a second processor is attached to the board through the expansion connectors these jumpers should be changed to configure the EZ KIT Lites ADSP 21065L processor as processor 1 or processor 2 in the multiprocessor system The debug monitor will not properly boot from the EPROM if the IDs are not configured for a single processor System configuration options are shown in Table 5 5 Table 5 5 Processor Selection GND Single Processor factory default 45 5 5 3 1 Line In Selection Jumpers The EZ KIT Lite uses a single stereo phone jack for line in and the microphone JP1 and JP2 are use to select between the two functions The valid settings for these jumpers are shown in Table 5 6 Table 5 6 Line In Selection Microphone In 5 5 3 2 AD1819 Codec Selection Jumper SPORT I is shared between the AD1819 and the EMAFE interface Jumper disables the drive capability of the AD1819 on the SPORT lines thereby preventing contention between the two devices When SPORTI 15 not used by the EMAFE device or an EMAFE device is not installed JP3 should be connected to ground enabling the AD1819 Table 5 7 AD1819 Codec Selection AD1819 selected f
53. er pin The processor drives this pin high during reset until SDRAM is started MSx O Z Memory select lines of external memory bank configured for SDRAM Connect to SDRAM s CS chip select pin I O Z SDRAM Row Address Select pin Connect to SDRAM s RAS pin SDA10 O Z SDRAM 10 pin SDRAM interface uses this pin to retain control of the SDRAM device during host bus requests Connect to SDRAM s 10 pin I Input Output S Synchronous Z Hi Z There are two 1M x 16 bit SDRAM chips on the EZ KIT Lite board connected to MS3 They are configured to be accessed in parallel providing 1M x 32 bits of external data memory starting at address 0x3000000 The ADSP 21065L uses address line 13 as the bank select Additionally the ADSP 21065L has a separate address line line 10 for the SDRAM since this line is used during refresh This allows refresh to occur while another data transfer runs on the data bus See Chapter 10 SDRAM Interface in the ADSP 21065L SHARC User s Manual for more information on the SDRAM controller 5 11 Timing Diagrams Figure 5 5 EMAFE Write Cycle Timing Parameter Definitions 49 Ons 50ns 100ns 150ns d 1 d dg d d od EMAFE Write Timings tDWHA tDRHA ADDR MSxf SWiBMSSEE PI tAWRL tAWRL tDAWH tDAW gt gt tDDWR tDDWH tWW gt tw gt tWWF gt tDDWH
54. ftware your PC and EZ KIT Lite have the default settings shown in Table 2 2 You can change these settings through the Settings menu in the debugger Table 2 2 User Configurable EZ KIT Lite Settings Selection Default Setting Codec Sample Rate 48000 Hz Codec Source Microphone Codec Gain 2 5 4 2 On Line Help The VisualDSP Debugger comes with a complete on line help file and Adobe pdf files of all manuals e You can use the context help button to get help on any command or icon Or e Highlight a command and press F1 For help on commands and dialogs click from the toolbar Help gt Help Topics to get to the Debugger Help help file 3 USING EZ KIT LITE SOFTWARE 3 1 Overview The combination of the EZ KIT Lite board and the monitor software operate as a target for the VisualDSP debugger The debugger allows viewing of the processor registers and memory perform several debugging activities such as setting breakpoints stepping through code and plotting range of memory If VisualDSP is not installed please install it from the VisualDSP CD that came with this product For more information refer to Chapter 2 section VisualDSP This chapter provides monitor level software information on how the EZ KIT Lite board operates with the installed software This chapter also provides information that helps the user run his her own programs on the ADSP 21065L EZ KIT Lite board This information appears i
55. ic is talking to 5V part Place cap close to signal lines BDO BD BD2 BD BD4 BD gt o1 INI 4 o PO m 0 G ko Joo BD 3 3Vcc IND ID 74LPT245A 5881 45Vcc E C53 m 3 3Vcc D 1M Xi 18 432MHz C55 5 C56 PC16550 z Mid ES 3 Io co ICD QOO ISRVPP SCLK ISR SDI 5 0Vcc NC SDO GND IN T2 IN R1 OUT R2 OUT ADM232A IRQO gt Keep this trace away from J3 connector ack HE 22 kere 1 BET Ne outs Ferrite Bead Ferrite Bead Ferrite Bead Vec V RT hee totes UART_EN h24 EMAFE WR 36 EMAFE CS EMAFE CS gt EMAFE ADDR Z EMAFE ADDR gt CODEC RST NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC10 NC11 NC12 NC13 NC14 itle Size B CY7C371i ate rawn ilename IN3 OUT3 NC NC NC NC Analog Devices Inc NC8 ANA One Tech nology Way NC9 ANAL Norwood MA 02062 Designed by Paragon Innovations Inc RARAGON mail info p ADSP 21065L EZ LAB I O UAR T amp CPLD Documen t Number 65 0000299 02 1125 01 001 0201 Wednesday November 18 1998 Kris Stafford Filename heet ONAM S lt resere_ 12 I S DMAG1s 5 HEADER 30X2 Expansion ONAM ONNU gt HEADER 30X2 Expansion DMAG2 PWM gt IRQ1 4 ap EXT CLK R13 100 Ohm C64 5 3 3Vcc PUSHBUTTON 1 W5
56. ing kernel verifies whether a full command has been received If a command has been received the kernel processes the command otherwise control 1s returned to the halt loop to wait for more characters The only method of executing your code once the halt loop has been entered is to send a Run or Single Step command in the debugger The UART ISR is entered when user code is running but the host is still interacting with the board As the host sends bytes the UART ISR takes the data stream from the UART and builds the command As with the halt loop each character received is passed to the command processing kernel Unlike the halt loop the monitor returns to the user code immediately after the interrupt 1s serviced 21 The following restrictions should be followed to ensure correct board operation The host loses contact with the monitor while the user program is running if the user program disables the UART interrupt or changes the UART interrupt vector The host loses contact with the monitor while the program is running and in an ISR when nesting is turned off The host loses contact with the monitor while the program is running and in the timer ISR provided the highest priority timer vector is used The host cannot halt with the debugger s Debug Halt command if global IRQ enable is disabled IRPTEN bit however breakpoints will work Command processing initiated from either the UART ISR or the Halt Loop is don
57. le mounted male connector and two mechanical standoffs to give stability to the entire arrangement when the daughter board and evaluation board are attached The evaluation board has a 96 pin right angle mounted female connector The signal lines that need to be routed to the EMAFE daughter board from the evaluation board should be kept to a minimum to reduce noise Signals routed to the EMAFE daughter board from the ADSP 21065L evaluation board are defined below Please note Analog Devices does not provide a daughter board the user must design this board 53 Line Out MIC Line ie Vs FRE pply MIC JP1 Line wc dl JP1 Line J3 Expansion Connectors Codec ET Oscillator NES avec Ns I Port gnal Po JP3 s Reset J6 Female Right Angle EMAFE Port CPLD CPLD PGM Port A18 N 33 GND JP4 Pin vere IDo OOGe 13 1 19 JP8 AE Ler JP5 UART ID1 J10 JP7 Flag In I IRQ Power Ou sss o o o JP6 3 2 1 0 2 1 0 9 8 7 6 5 4 Figure 6 1 Physical Layout of ADSP 21065L DSP evaluation board and EMAFE daughter board EMAFE Signal Description The EMAFE 96 pin connector routes the following signals from the evaluation board to the EMAFE daughter board 16 Data lines 8 Address lines 3 Parallel Bus Control lines e 16 Synchronous Serial Port lines 1 Interrupt output 1 Flag input The E
58. lumn accesses set 1 or 32 bit two column accesses cleared 0 The monitor program requires three column data accesses to memory block 0 23 On reset restart and halt the debug monitor kernal forces IMDWO to 1 and IMDWI to 0 but user code should also set these bits to ensure that it operates in the same way on both the simulator and the EZ KIT Lite board These settings only affect data accesses not instruction fetches Block 0 resides in Three Column memory If you are storing data in Block 0 it must be in three column format The user may not use DAG2 PM data bus to access SDRAM because SDRAM is mapped into an address that is greater than 24 bits For example the C segment seg pmda should not be mapped to SDRAM If the user is using interrupt handlers in his her program i e interrupt then seg dmda must not be located in external SDRAM In this case seg dmda MUST be located in internal memory This is caused by a problem with the interrupt handlers in libc dIb A correction will be posted to the Analog Devices FTP site Table3 5 Memory Map Ser Address Address 0x0000 8000 0x0000 9FFF Block 0 Normal Address internal memory 0x0000 C000 0x0000 DF Block 1 Normal Address internal memory FF 0x0001 0000 0x0001 3FFF Block 0 Short word FF FF 0x0001 8000 0x0001 BF Block 1 Short word EPROM through BMS 0x0002 0000 0x0002 FFF 0x0100 0000 0x0100 0000 EMAFE Address reserved for the EZ KIT
59. mple Rate 1 SAMPLE RATE GENERATE 1 0xBB80 3 3 5 EMAFE Programming Communicating with the EMAFE is done through either of the SPORTS or through indexed addressing To read or write memory on the EMAFE the memory should be written to address 0x0100 0000 After writing the address the data can be read from or written to address 0x0100 0001 Multiple reads or writes are executed without rewriting the address Because of the bus timings of the ADSP 21065L an address hold cycle must be added to the bus cycles of MS1 to communicate with the EMAFE This is done in the WAIT register of the ADSP 21065L and guarantees that the data remains valid when the WR line goes high invalid If this is not done the data and or address written to the EMAFE may not be stored correctly As stated in the previous section must be connected to 3 3Vcc if SPORTI is used on the EMAFE or the AD1819 will contend with the EMAFE s operation 31 4 DEMONSTRATION PROGRAMS 4 1 Overview This chapter describes loading and running the demonstration programs supplied with the ADSP 21065L EZ KIT Lite board The demos are designed to run on the VisualDSP Debugger which is supplied on the CD that shipped with this product For detailed information on debugger features and operation see the VisualDSP Debugger Guide amp Reference and the Debugger Tutorial for ADSP 2106x Family DSPs 4 2 Starting the VisualDSP Debugger After the VisualDSP softwar
60. n DMA transfer schemes nor to standard Multi channel Mode data transfers with the ADSP 21065L which expects all slots to be the same number of bits To realign your data set the SLOT 16 bit in the AD1819 s Serial Configuration register as soon the serial port is enabled To do this the program must per form a single transfer using the initial packing style 26 After the SLOT 16 bit is set all subsequent packets are standardized to 16 bits Once the data is aligned the EPROM s monitor POST routine then writes and verifies three patterns to an internal register in the codec If all three writes are verified the codec connection is verified The ADSP 21065L then continually transmits and receives data from the codec Slot 0 in each transmission specifies which slots contain valid data and are called the Tag Phase time slot 3 3 3 1 Linking Your Code to the RS 232 Monitor Codec Interrupt Handlers To use the EPROM monitor s interrupt handler for the AD1819 the user needs to use one of the following methods C code link your code with the file demorth asm this is located in the demos tt folder This file contains a replacement for the standard C runtime header 060 hdr asm This file also includes a jump to the EPROM codec interrupt handler at the SPORTI Tx interrupt vector location Assembly use the demorth asm file as the interrupt vector table or create your own interrupt vector table that includes a jump to address 0x
61. n the following sections e Standard Operation Describes the operation of the EZ KIT Lite board from Power On self Test POST routines to the AD1819 codec s operation Running Your Own Programs Provides information about writing and running your own DSP executables that link with the monitor program to run on the EZ KIT Lite board 3 2 Standard Operation This section covers the standard operation of the EZ KIT Lite board It describes the I O capabilities of the on board components board power up and the on board Monitor program 3 2 1 I O Devices 3 2 1 1 Flags The ADSP 21065L has 12 asynchronous FLAG I O pins that let you interact with the run ning program All flags are configured as inputs on reset of the DSP For more information on the Flag pins see Chapter 12 System Design Flag Pins in the ADSP 21065L SHARC User s Manual The flags and their uses are as follows FLAGos3 are connected to the push buttons on the EZ KIT Lite board and are for user input For instance the user can tell the program to poll for a flag and when it occurs do some other operation such as jump to another instruction The push button flags are set as inputs through the MODE2 register Once configured they may be read through the ASTAT register e FLAG connect to the LEDs and supply feedback for program execution For example the user can write code to trigger a flag and the corresponding LED when a routine is complete
62. nputs e Six user programmable LEDs e Power supply regulation EMAFE Enhanced Modular Analog Front End connector for expansion e Expansion connectors The EZ KIT Lite board is equipped with hardware that facilitates interactive demonstrations The push button switches and user programmable LEDs provide user control and board status Additionally the AD1819A SoundPort Codec provides access to an audio input selectable as line level or microphone and an audio output line level The EZ KIT Lite includes a monitor program stored in non votilitile memory The monitor program allows the user to download execute and debug ADSP 21065L programs By removing the socketed EPROM replacing it with an EPROM containing user code the board can run as a stand alone unit without the PC The user can also connect emulator to the EZ KIT Lite Through JTAG emulator you can load programs start and stop program execution observe and alter registers and memory and perform other debugging operations JTAG emulators are purchased seperately through Analog Devices Additionally the EZ KIT Lite provides expansion connectors that let the user examine the processor signals as well as provide an interface for host control 1 1 For More Information About Analog Devices Inc Products Analog Devices is accessible on the Internet at www analog com The DSP web page is directly accessible at www analog com dsp This page provides access to
63. ntime libraries and librarian linker simulator and PROM splitter See the following documents VisualDSP Getting Started Guide e VisualDSP User s Guide for the ADSP 21xxx Family DSPs e Assembler Manual for the ADSP 21xxx Family DSPs e Compiler amp Library Manual for the ADSP 21xxx Family DSPs Linker amp Utilities for the ADSP 21xxx Family DSPs Product Bulletin for VisualDSP and the ADSP 21xxx Family DSPs documents are found on the Analog Devices Technical Documentation web site at If you plan to use the EZ KIT Lite in conjunction with the JTAG emulator refer to the documentation that accompanies the emulator Your software installation kit includes on line help as part of the Windows interface These help files provide information about the ADSP 21065L evaluation board and accompanying tools 2 GETTING STARTED 2 1 Overview This chapter provides information to install the software and the ADSP 21065L evaluation board It is important that installation of the software and hardware are in the order presented for correct operation This chapter also provides basic board information and conatins the following sections e Contents of your EZ KIT Lite package e PC configuration e Installation procedures 2 2 Contents of Your EZ KIT Lite Package The EZ KIT Lite evaluation board contains ESD electrostatic discharge sensitive devices Electrostatic charges readily accumulate on the human bo
64. og The dialog fields for the Bandpass demo are as follows Input Source Select input from the AD 1819 or noise from the DSP Filter Range Change the filter applied to the demo 62 APPENDIX A RESTRICTIONS amp CPLD CODE LISTING The following restrictions apply to configuration level release 2 01 of the ADSP 21065L evaluation board For information on any ADSP 21065L silicon anomalies see the anomaly sheet that accompanied this product 1 10 11 Breakpoints set in the last three instructions of a do loop are allowed but cause your code to run incorrectly Breakpoints set after a delayed branch instruction and before the branch occurs causes your code to run incorrectly mi Using the single stepping function steps through a delayed branch instruction and the last three instructions of a do loop The host loses contact with the monitor while the user program is running if the user program disables the UART interrupt or changes the UART interrupt vector The host loses contact with the monitor while the program is running and in an ISR when nesting is turned off The host loses contact with the monitor while the program is running and in the timer ISR provided the highest priority timer vector is used The current version of the EZ KIT monitor does not let you view hardware stack information Do not use the reset button while the debugger is open unless the debugger requests you to This will caus
65. ol This command opens a dialog box that lets the user change several operating functions of the FFT and BP demos Figure 7 3 shows the dialog box that accompanies the FFT demo Select the Demo Control command for a demo which has no dialogs an error message that says This demo does not require user input will appear Click OK and continue with the demo FFT Demo Controls Source Domain Window Codec Frequency None C Noise C Time C Hamming T Blackman Dynamic Peak Log View output graphically in real time by choosing Plot under the C Dynamic Peak Linear Memory menu selection Select 7 Address 0x3008105 Cumulative Peak Log Sride 1 Datazint Count 128 Cumulative Peak Linear icis Right click on the graph and __ choose AutoUpdate Figure 7 4 FFT Demo Dialog Table 7 1 FFT Demo Dialog Description Dialog Field Description Select the source for the FFT the codec or random number generator Splits the original DFT using one of the following methods DIT Decimation in Time or DIF Decimation in Frequency A filter to use on the Fourier transform Scaling refers to how and how much data is captured while the FFT is running Dynamic Scaling is a snapshot of current FFT high and low limits activity Cumulative Scaling shows FFT activity over time limits activity 61 Figure 7 5 Bandpass Demo Controls Dial
66. on esse 26 DMA er Lt 18 hardware specifications sss 39 slot 16 mode 26 TDM schemes iti re 19 Codec command eR ure itte 62 Codec Sample Rate dialog 62 CODEC Transmissions data packets dee eR 27 Comm Port 62 Commands Baud ssa eR RR ete 61 Ode Ah 62 Comm iie ect E eene 62 Demo menu ueniet TERR 63 Test Communications sese 61 Computer resources for the EZ LAB board 12 Contents of package Ne 11 CPLD Equations 66 Customer support 8 data packets 22 using in CODEC 15510 5 27 Debugger SLT Iso ep Oa ias 32 Default Settings on the EZ LAB 15 Demo menu commands eere 63 Demo programs OVELVICW Sih rite nate dale ets 32 Demonstration programs bandpass filter 37 Blinks satset 38 ger Um 37 Peter Gunn theme etes 37 Pluck eon DR DOT 37 lusit 38 Jo ss NES 38 Demonstration 2 37 Dialogs Bandpass demo eee 64 Codec Sample 62 EET 63 DMA transfers ton neo ee neo ee diee 22 E Electrostatic Discharge
67. ort signals from the ADSP 21065L may be required for 5 non 3 3V compliant peripherals on the EMAFE board or from SV peripherals on the EMAFE board to the 3 3v non SV tolerant ADSP 21065L For information on EMAFE pins see EMAFE Expansion in Chapter 6 5 9 AD1819 As with the UART the AD1819 is a 5V device To prevent over driving the SPORT lines on the ADSP 21065L the lines from the AD1819 are buffered through a 74LVT125 This buffer has the additional purpose of bypassing the AD1819 s control of SPORTI when SPORTI is required by the EMAFE This 1s done to prevent contention between the two devices on the SPORTI lines On power up the AD1819 reads the SDATA OUT signal line If the pin is high or floating the AD1819 enters a test mode To prevent the AD1819 from entering this mode a pull down resistor has been added to the line 5 10 SDRAMS The processor s SDRAM interface enables it to transfer data to and from synchronous DRAM SDRAM at 2xCLKIN The synchronous approach coupled with 2xCLKIN frequency supports data transfer at a high throughput up to 240 Mbytes sec All inputs are sampled and all outputs are valid at the rising edge of the clock SDCLK Table 5 8 lists and describes the processor s SDRAM pins and their connections 48 Table 5 8 SDRAM pin connections 2 I O Z SDRAM Column Address Select pin Connect to SDRAM s CAS buffer pin DQM O Z SDRAM Data Mask pin Connect to SDRAM s DQM buff
68. ovations Inc RARAGON Dd D itle ADSP 21065L EZ LAB Memon Size Document Number B 65 000299 02 1125 01 001 0201 ate Wednesday November 18 1998 rawn By Kris Stafford ilename Filename Pin 1 is the center pin FB1 19 0 01uF DC Jack PLM250S40 72 23 Rubber Foot Rubber Foot 74 Z5 Rubber Foot Rubber Foot Heat sink HQ1 573300 Q1 R73 NDB6020P 2 4 0 025 Ohm ADP3310 3 3 Heat sink HQ2 573300 Q2 R74 NDB6020P C15 4 0 05 Ohm ADP3310 5 0 LL 3 3Vcc FB4 Ferrite Bead C8 is used to minimize noise on the board where 5Vcc crosses the 3 3Vcc plane 74LCX14 5 0V 0 5 Locate Ferrite Bead across voltage split in plane 5VA 5Vcc Ferrite 16 E 1 VOC OUT GND 30 0000MHz 74LCX14 74LCX14 U21C 74LCX14 74LCX14 3 3Vcc ADM708T Analog Devices Inc One Tech nology Way ANA 26 Norwood MA 02062 D Designed by Paragon Innovations Inc RARAGON mail info paragon tx com itle ADSP 21065L EZ LAB PWR RST Size Document Number B 65 000299 02 1125 01 001 0201 ate Thursday November 19 1998 rawn By Kris Stafford ilename Filename heet A 0 23 D O 31 ACK WR RD MSO MS1 MS2 MS3 EXT_CLK RESET PWR RST EXT_CLK DSP_CLK PL GLK PLD CLK RESET RST PWR RST IRQO IRQ1 IRQ2 FLAG O 3 FLAG 4 9 PWM EVENTO PWM HBR HBG CS REDY SBT
69. p are allowed but this causes improper debugger operation Breakpoints set after delayed branch instruction and before the branch occurs causes improper debugger operation Using the single stepping function steps through delayed branch instruction and the last three instructions of a do loop The debugger automatically inserts breakpoints an the function Main when the Settings Run To Main command is checked and at the exit instruction 34 4 3 4 Resetting the EZ KIT Lite Board The EZ KIT Lite board can be reset with the push button switch on the board or with the Debug gt Reset command in the debugger menu bar Both resets clear and reset the chips memory and debug information so there will be need to reload any programs that were running The Debug gt Restart command resets the processor however the processor retains all debug information and memory contents e The following sequence must be used when starting the debugger 1 Start the debugger from the windows Start menu Start gt Programs gt VisualDSP gt Debugger 2 The debugger starts and the Target message Hit Reset Button appears 3 Press the Reset button on the board 4 Wait approximately three seconds for the LED s except power and FLAG9 to turn off 5 Click OK The message Communications Success appears Do not use the reset button while the debugger is open unless the debugger requests you to press it e While the use
70. pen collector buffer to be added 05 29 98 Changed address of UART 08 15 98 Locked pins to prevent changes on next rev s 09 22 98 Changed functionality driven only when needed Added Codec reset functionality 09 28 98 Changed functionality of Codec Reset lusec low 21065L VHD VHDL code for the CPLD on the ASPL 21065L evaluation board Addresses A2 Al AO mum ER UART QO I c EMAFE Address 0 0 0 0 mus Ue EMAFE Data 0 0 0 1 mu QE CODEC RESET 0 1 0 0 Note The ACK line is only driven when needed mem When the codec reset is written the codec rst line goes low for gt lusec library ieee use ieee std logic 1164 all use work std arith all entity interface is port reset in std logic asynchronous reset clk in std_logic Clock input addr in std logic vector 3 down to
71. r The power connector supplies DC voltages to the EZ KIT Lite board Table 5 1 shows the power connector pinout If the user does not use the power supply provided with the EZ KIT Lite board replace it with one that has the connections shown in Table 5 1 Table 5 1 Power Connector Terminal Connection Outer Ring GND 5 4 2 European Power Supply Specifications Table 5 2 European Power Supply Specifications DC VOLTAGE 7 5V 5 Full Load CURRENT 1 2 Amps Minimum Rating RIPPLE 500 mV rms Max Full Load DC CONNECTOR Type Switchcraft 760 style FEMALE Plug Size 5 5 OD X 2 5 ID X 9 5 length millimeters Polarity Center is Postitive inside terminal 42 5 4 3 5 4 4 5 4 5 5 4 6 AD1819 Connections When the AD1819A is enabled on the EZ KIT Lite board accessing the audio input and output jacks on the board is possible Each of the audio connectors are stereo mini jacks and accept standard commercially available stereo mini plugs Microphone Line in Input jack connects to the LINE IN LINE IN right pins or the MICI and MIC2 of the AD1819A SoundPort Stereo Codec depending on the setting of jumpers JP1 and JP2 Jumper settings are explained in Table 5 6 The LINE Output jack connects to the left L LINE OUT and right R LINE OUT pins of the codec Expansion Port Connectors The two expansion port connectors provide access to the bus signals of the ADSP
72. r may load several programs into the debugger during a single debug session without resetting the EZ KIT Lite board it is recommended to reset the board prior to loading a new program 4 4 Benchmarking Utilities An evaluation platform needs to report an accurate cycle count in order for you to develop efficient DSP programs Because the monitor program running on the EZ KIT Lite board 15 intrusive the debugger s cycle counter located in the status bar does not work To get an accurate cycle count the EZ KIT Lite comes with a set of benchmarking utilities These utilities come in both C and assembly code types Use the following procedures to enable accurate cycle counting of any DSP program In C embed the count start and count end functions in your code The count start is a function that returns an initial starting value of the current cycle counter The user then uses this value as an argument to the count end function The count end function returns the total number of elapsed cycles between count start and count end These functions are a completely self contained so the user does not need to save or restore any processor registers The following is an example of how to write these functions into your existing code 35 User must run any program that uses this code from when the function count start starts to at least as far as the function count end returns without halting or stepping to obtain an accurate cycle count Hinclu
73. rocessor initializes correctly on power up 43 The power up sequence is 1 JTAG Emulator 2 ADSP 21065L EZ KIT Lite board To remove power reverse the order Jumpers Figure 5 3 JTAG Connector With Jumpers Installed Figure 5 3 shows the locations of the configuration jumpers on the EZ KIT Lite board and which pin on the jumpers is the GND pin These jumpers should be checked before using the board to ensure proper operation Each of the jumper selection blocks are described in the following sections 5 5 Jumpers 5 5 1 Boot Mode Selection Jumper The jumper JP6 controls the behavior of the ADSP 21065L processor when the system is reset from power up or when the RESET button is used When the jumper is not connected to GND or is removed the processor boots from the EPROM If the jumper is connected to GND the processor attempts to boot from its host interface through the expansion port Table 5 3 Boot Mode Selection HOST boot EPROM boot factory default 44 5 5 2 Size Selection Jumpers The EZ KIT Lite supports 128K x 8 256K x 8 512K x 8 and IM x 8 EPROMs each of which is selectable through jumpers JP4 and JP5 The EPROM socket is originally populated with a 256K x 8 EPROM Ifa different EPROM is used JP4 and 1 5 should be adjusted to accommodate the different size Table 5 4 shows the pins that the jumpers for JP4 and JP5 should be connected to Table 5 4 EPROM Size Sel
74. s 5 3 3 User LED s There are six flag LEDs on the EZ KIT Lite board for user output that are available The FLAG 4 9 LEDs are controlled by the FLAG outputs of the DSP and are labeled according to the flag output that controls them See Flags section in Chapter 3 for more information on interfacing to the user LEDs from DSP programs 5 3 3 1 Power LED The Power LED when on indicates that 3 3V DC used by the DSP and digital circuitry is present 5 4 Power Supplies ADP3310s generate the 3 3V and SV power required by the board These parts are linear regulators that also regulate current The resistor placed between the Vin and IS pins limits the amount of current through the device The resistance R s needed for a given maximum output current o is determined with the equation below R 0 05 1 5X1 Power regulation is done through a P channel FET To help disperse the heat from the FET a heatsink is attached to the drain Note that the regulated voltage is available on the heat sink since the voltage is regulated from the drain of the FET 41 The minimum supply voltage for the ADSP 21065L is 3 0V An ADM708T is used to monitor the supply voltage and holds the processor in reset 1f the power supply s voltage is below 3 08V The board hardware may also be reset via the push button that is connected to this part For more information see User Push button Switches section in this Chapter 5 4 1 Power Connecto
75. state lt 1 else ack lt 1 w ack lt 0 end if when WAITI gt ack lt 0 w ack lt 1 next wstate lt WAIT2 when WAIT2 gt ack lt 0 w ack v 1 next wstate WAIT3 when WAIT3 gt w ack lt 0 w ack v 1 next wstate lt WAIT4 when WAIT4 gt lt 0 w ack lt 1 next wstate WAIT5 AND RD 1 then Yes No Continue Continue Continue Continue Check for EPROM RD Delay ignore Delay Delay Delay Delay 70 when WAIT5 gt Continue Delay ack lt 0 w ack lt 1 next wstate WAIT6 when WAIT6 gt Release Delay w ack 1 w ack v 1 next wstate WAITO end case end process wait state Codec Reset rst process clk addr cs bar reset variable cdc cnt std logic vector 4 downto 0 begin if reset 1 then If reset cnt others gt 0 reset counter codec rst bar 0 pass reset to codec elsif
76. t install this software prior to installing the EZ KIT Lite software Insert the VisualDSP CD into the CD ROM drive This will bring up the CD browser Click on the Install VisualDSP option This will launch the setup wizard Follow this wizard with the on screen instructions 2 5 3 Installing the VisualDSP EZ KIT Lite License Before the VisualDSP software can be used the license must be installed To install the EZ KIT Lite license follow these steps 1 Make sure VisualDSP has been installed first 2 Insert the VisualDSP CD into the CD ROM drive if it is not already in the drive 3 Once the CD browser is on the screen select the Install License option 4 Now follow the setup wizard instructions Note Make sure that you have the proper serial number located on the back of the CD holder 2 5 4 Installing the EZ KIT Lite Software The EZ KIT Lite software is supplied on a separate CD ROM To install the EZ KIT Lite software follow these steps 1 Make sure VisualDSP has been installed first 2 Close all Windows applications The install will not work correctly if any VisualDSP applications are running 3 Insert the EZ KIT Lite CD into the CD ROM drive The setup will automatically start Follow the installation wizard by choosing the appropriate options 4 When the setup has completed reboot the machine if necessary 2 5 4 1 Default Settings After you have installed the board and utility so
77. tate present wstate lt next wstate Wait State end if end process state clocked ack lt 1 when reset 1 else u_ack AND w_ack when u_ack_v 1 OR w ack v 1 else Vs Generate ACK EMAFE Control logic Control the buffering of data to and from the EMAFE interface 69 e rd bar lt rd bar e wr bar lt wr bar e cs bar lt 0 when addr 0001 AND cs bar 0 else 1 e addr 0 when addr 0000 AND cs bar 0 AND wr bar 0 else 1 kkkxkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Wait Generator for EPROM kckckckckockckckckckckckckck kck ck ck ck k kk kk Delay the accesses to the EPROM since the DSP will try to access it at 30 MHz wait state process rd bar bms bar present wstate State selection and ack control variable rd std logic variable bms std logic begin rd not rd bar bms not bms bar case present wstate is when WAITO gt if bms w_ack lt E 0 ack lt 1 next w
78. the LED will light The LED flags are configured through the IOCTL register and are set read through the IOSTAT register e FLAG is available to the EMAFE interface and is used for signaling The EMAFE flag is configured through the IOCTL register and is set read through the IOSTAT register e is reserved for the monitor to determine if the AD1819 codec is enabled When using the monitor program supplied with the EZ KIT Lite board do not use or alter this flag pin Table 3 1 Flag Summary Push button Input SW3 SW5 SW7 SW8 Reserved for monitor 3 2 1 2 Interrupts Each of the three external interrupts IRQ gt of the ADSP 21065L are directly accessible through push button switches SW2 SW4 and SW6 on the EZ KIT Lite board IRQo are wire Or ed IRQ is used to implement interrupt driven serial routines with the UART and IRQ is provided for use with an EMAFE board and can be set to read and write registers The external interrupts are controlled through the MODE1 MODE2 and IMASK regis ters and are configured in one of two ways by modifying the vector table or through instructions in user code The MODE register also controls the interrupt sensitivity between level and edge To prevent an interrupt from being masked write to the particular interrupt in the IMASK register The monitor program running on the ADSP 21065L uses three interrupts IRQO and SFT3 for normal operation These interr
79. to the following commands Settings Test Communications Breakpoints AlteF9 interrupts STEENS Preferences Baud Rate Comm Port b Codec v Enable Stdio Support Figure 7 1 Settings Menu Commands 7 2 1 Test Communications Tests the PC EZ KIT Lite communications Responses are Communications Success or various error messages sent to the Output window In most cases resetting the EZ KIT Lite reestablishes communication 7 2 2 Baud Rate Sets up the baud rate of the COM port Choices are 9600 19200 38400 57600 and 115200 The default rate is 115200 Once change is made resetting is not needed for subsequent debug sessions Using rate 9600 causes the EZ KIT Lite to operate very slowly and can also cause it to hang 59 7 2 3 Comm Port Selects a PC communications port for the EZ KIT Lite board Choices are Comm 1 4 7 2 4 Codec Sets several options for codec operation These commands are Update Updates and refreshes the menu changes you selected Sample Rate Opens the Sample Rate dialog Figure 7 2 that lets you select sample rate from 7000 to 48000 Hz Codec Sample Rate Figure 7 2 Sample Rate Dialog Source Choose Microphone or Line In Co d ec Figure 7 3 Source Setting Gain Select Select a gain from 0 0 to 22 5 in 1 5 increments 60 7 3 Demo Menu Commands The Demo menu has one command Demo Contr
80. untain ICE Summit ICE Trek ICE and The DSP Collaborative are trademarks of Analog Devices Inc Microsoft and Windows are registered trademarks and Windows NT is a trademark of Microsoft Corporation Adobe and Acrobat are trademarks of Adobe Systems Incorporated other brand and product names are trademarks or service marks of their respective owners Limited Warranty The ADSP 21065L EZ KIT Lite hardware is warranted against defects in materials and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer Copyright 2000 Analog Devices All rights reserved Revision 1 0 December 2000 TABLE OF CONTENTS LIST OF TABLES PC MINIMUM CONFIGURATION USER CONFIGURABLE EZ KIT LITE SETTINGS FLAG SUMMARY INTERRUPTS USED BY THE MONITOR PROGRAM TABLE 3 3 POST ROUTINES TABLE 3 4 POST ERROR CODES MEMORY MAP AVAILABLE MEMORY LOCATIONS ON THE EZ KIT LITE DSP PROGRAMMING OF THE AD1819 INDEXED CONTROL REGISTERS POWER CONNECTOR EUROPEAN POWER SUPPLY SPECIFICATIONS MODE SELECTION EPROM SIZE SELECTION PROCESSOR SELECTION LINE IN SELECTION AD1819 CODEC SELECTION SDRAM PIN CONNECTIONS EXPANSION CONNECTORS EVALUATION BOARD POWER CONNECTIONS EMAFE CONNECTOR EMAFE CONNECTOR INTERFACE SIGNAL DESCRIPTION ROW EMAFE CONNECTOR INTERFACE SIGNAL DESCRIPTION Row B EMAFE CONNECTOR INTERFACE SIGNAL DESCRIPTION Row C FFT DEMO DIALOG DESCRIPTION L
81. upt vectors are provided in the demorth asm file that comes with the EZ KIT Lite When writing code these interrupts and their corresponding vectors should not be altered If these vectors are overwritten the kernel may not work as shown in Table 3 1 For more information on the registers that control interrupts and a complete list of inter rupt vector addresses see Appendix E and F in the ADSP 21065L SHARC Technical Reference Table 3 2 Interrupts Used by the Monitor Program Deseripion rost Functionality if Overwritten Multiplexed from the UART through Debugger s ability to interrupt an open collector device running code Used to signal the monitor to send Ability to send messages from data back to the Host user code to the debugger AD1819 Transmit Interrupt Monitor s ability to control the AD1819 SPR1 AD1819 Receive Interrupt The following rules and restrictions should be followed when using interrupts Youcannot step into an interrupt nterrupts are disabled when the user program is halted board cannot communicate with the host if an interrupt higher than IRQO is used board cannot communicate with the host if interrupt nesting is disabled Ifthe user does not require the supplied monitor program IRQO with SW2 can be configured by the user In the initialization code of the user s program the interrupt vector for IRQO must be replaced This removes all monitor
82. wstate next wstate WAIT STATE begin UART Control logic WR D1 ENDWI1 CS6 RD1 WAIT5 uart state process present state cs bar rd bar wr bar addr variable rd std logic variable wr std logic 66 variable cs std logic begin rd not rd bar wr not wr bar cs not cs bar case present state is when IDLE u ack 1 u ack v lt 0 if cs 1 AND rd OR wr 1 AND std_match addr 001 then Proceed only if next state lt CS1 addressed and rd wr else next state IDLE Not needed for clarity end if when CS1 gt u ack lt 1 u ack v lt 0 if cs 1 AND rd OR wr 1 AND std match addr 001 then Proceed only if next state CS2 addressed and rd wr else next state IDLE Improper cycle end if when CS2 gt u ack lt 0 Signal extended cycle u ack v 1 if wr 1 then next state lt WR1 Write cycle else next state CS3 Read cycle end if when WR1 gt u lt 0 u ack v 1 ne
83. xt state WR2 Continue Write Cycle when WR2 u ack 0 u ack v 1 next state when WR3 gt u ack lt u ack v lt 1 next state when WR4 gt u ack lt u ack v lt 1 next state when WR D1 u ack v lt I next state lt ENDW1 1 1 lt Continue Write Cycle VOL s lt WR4 Continue Write Cycle noL lt WR D1 Continue Write Cycle UO ts Continue Write Cycle 67 when ENDW1 gt u ack lt 0 u ack lt TI next_state lt ENDW2 Continue Write Cycle when ENDW2 gt u lt 0 u_ack_v lt 1 next_state lt ENDW3 Continue Write Cycle when ENDW3 gt u ack lt 0 u_ack_v lt 1 next_state lt ENDW4 Continue Write Cycle when ENDW4 gt u ack lt 1 u_ack_v lt 1 next state lt IDLE End Write Cycle when CS3 gt u ack lt 0 u v lt 1 next state lt CS4 Continue Read Cycle when CS4 gt u ack lt 0 u ack v 1 next state lt CS5 Continue Read Cycle when CS5 gt u ack lt 0 u ack v 1 next state lt CS6 Continue Read Cycle when CS6 gt u ack lt 0 ucack v e VL next state lt RD1 Continue Read Cycle when RD1 gt u ack lt 0 u ack v 1 next state RD2 Continue Read Cycle when RD2 gt lt 0 u ack v 1 next state RD3 Continue Read Cycle when RD3 gt

ADSP-21065L EZ-KIT Lite Evaluation System Manual

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