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ARM 920T-um_s3c2410x 3832 KB

1. 2 X 1 XIX XX Qo X OG S OX OOO OCOD QUE OO OO OQ UOI T EO OO XD XO CO O OO QC OOO OO CX ELS OO OO Oe TE X ON OO OG OO X CoL XD Oe De UO OY OOO 62 0 12 OO OO Ce OO oO OOS So OOO XX OO OOOO XO XX OO OO IQ OOOO OO OO OS Oe BOTTOM VIEW Figure 1 3 S3C2410X01 Pin Assignments 272 FBGA ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments FREE EEE Function BUS REQ PWR off nRESET Type a x C Gm m m C oaas ____ me 1 me 03 pr P P ES wow vom P P Cr prs ____ Hz D2 p es DAS me 1 me D ____ Hz Hz I me Di par Hz Hz 1 ne pes ____ Hz o E2 ____ 1 me papa ____ Hz Hz 1 m Er pua DAT Hz Hz 1 ne F8 vssmor pr P P F8 wso vso P s F2 __ emo 1 Fr roue om owe 1 e F4 Toumoeez cmm owe 1 muse em 1 fa TCLKO GPB4 ee G5 wero aee nxoackvers7
2. 1 i 3cycdes i Figure 8 3 Burst 4 Transfer Size ELECTRONICS 8 5 DMA 3C2410X01 RISC MICROPROCESSOR Examples Single service in Demand Mode with Unit Transfer Size The assertion of XNXDREQ is need for every unit transfer Single service mode The operation continues while the XnXDREQ is asserted Demand mode and one pair of Read and Write Single transfer size is performed XSCLK A ERE E EEPE E ETETE ee LEE u 5 BN LL JJ Figure 8 4 Single service in Demand Mode with Unit Transfer Size Single service in Handshake Mode with Unit Transfer Size XnXDREQ s XnXDACK A i i Double synch coun i i i Read X Write _2oycles H i i 1 Read Figure 8 5 Single service in Handshake Mode with Unit Transfer Size Whole service in Handshake Mode with Unit Transfer Size XSCLK moren TG Double synch H i 1 b b 1 5 b H 1 f 5 1 ite Zeycles Read X Write 2 Read X Write Figure 8 6 Whole service in Handshake Mode with Unit Transfer Size 8 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR DMA DMA SPECIAL REGIS
3. Gras i e ws Rio mnrissmioukvarer Gear ma 1 e Um amnseres 1 6 fenner es Pw eeo 1 6 Rn _ eron 1 me PH wmoxwowGPa Geo _ om 1 te Ur wrewmPowGeGIS some I te TH Grom owe 1 te ewreainvrowGrais Grans owe 1 te m cr ou te Lum F fov 1 fe DP1 PDPO RE EEC po fo fu DNO SITT a um wow 1 fu mS wow wow 1 fu joe LL Ls 1 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments Continued FRE NENNE Function QBUS REQ PWR off nRESET a ven 1 fam ____ am a mo Pris ana ____ am no 7 fans Aw n Ris fan Aw a mo NS fam AN A ro Pis v P P P Xow Xm mcvp mevo p P P Pi voiweL P P P ae prp P P Pir wuce wc 9
4. Start 4 Data Bits Stop 4 lt Pulse Width 3 16 Bit Frame Figure 11 6 Infra Red Transmit Mode Frame Timing Diagram IR Receive Frame Start 4 Datta Bits J Stop 4 Bit Bit Figure 11 7 Infra Red Receive Mode Frame Timing Diagram ELECTRONICS 11 9 UART 53 2410 01 RISC MICROPROCESSOR UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCONO ULCON1 and ULCONe in the UART block ee A Infra Red Mode Determine whether or not to use the Infra Red mode 0 Normal mode operation 1 Infra Red Tx Rx mode Number of Stop Bit 2 Specify how many stop bits are to be used for end of frame signal 0 One stop bit per frame 1 Two stop bit per frame Word Length 1 0 Indicate the number of data bits to be transmitted or received per frame 00 5 bits 01 6 bits 10 7 bits 11 8 bits Parity Mode 5 3 Specify the type of parity generation and checking during UART transmit and receive operation Oxx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 11 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART CONTROL REGISTER There are three UART control registers including UCONO
5. ped Cache eee TT _ Gachetockdown foare oocom a NOTES 1 Register location 0 provides access to more than one register The register accessed depends upon the value of the opcode_2 field See the register description for details 2 Separate registers for instruction and data See the register description for details 2 4 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL ACCESSING CP15 REGISTERS Throughout this section the following terms and abbreviations are used Table 2 3 CP15 Abbreviations Unpredictable For reads the data returned when reading from this location is unpredictable it could have any value For writes writing to this location will cause unpredictable behavior or an unpredictable change in device configuration Should be zero When writing to this location all bits of this field should be 0 In all cases reading from or writing any data values to any CP15 registers including those fields specified as unpredictable or should be zero will not cause any permanent damage All CP15 register bits that are defined and contain state are set to zero by BnRES except V Bit in register 1 which takes the value of macrocell input VINITHI when BnRES is asserted CP15 registers can only be accessed with MRC and MCR instructions in a privileged mode The instruction bit pattern of the MCR and MRC instructions is shown in Figure 2 1 The assembler for these instructions is MC
6. o Gey mo vos gt OoOo GPs vwa gt 7 we TN GP mw vo ams Lem mew xm GPD1 Input output SeedsbePiFumlon GPs SA GPE mua Input output SPICLKO Gre mua so GPEH wo semsoo mua so Ges wo gt wo sr gt GP wo sm G s so Ges wo spar mo es ns cook Ge sse gt oo wo gt JAE 9 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS Table 9 1 S3C2410 Port Configuration Continued pin Funcions wo em gt ami wo em gt em seiestsblePinFunetiom Gee Input output EINT15 SPICLK1 Gea ENS am nr ELECTRONICS 9 5 PORTS 53 2410 01 RISC MICROPROCESSOR Table 9 1 S3C2410 Port Configuration Continued ssiesblerinFuneom amu www am gt ams cam gt 9 6 ELECTRONICS 53 2410 01 RISC MICROPROCE
7. GPHDAT 0x56000074 Port H Data GPHUP 0x56000078 Pull up Control H ELECTRONICS 1 35 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued _ Endian L Endian Write RW GSTATUS1 0x560000B0 External Pin Status 1 36 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued wer tem tem _ Name B Endian L Endian Write BCDHOUR 0x5700007B 0x57000078 BCD Hour A D converter ADCCON 0x58000000 lt W ADC Control ADCTSC 0x58000004 ADC Touch Screen Control ADCDLY 0x58000008 ADC Start or Interval Delay ADCDATO 0x5800000C ADC Conversion Data ADCDAT1 0x58000010 ADC Conversion Data 0 R sasas am ELECTRONICS 1 37 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued men emm dm Endian Endian Write SD interface T SDIRSP2 0x5A00001C SDI DU RN SDIRSP3 0x5A000020 SDI SDI Response SDIDTimer 0 5 000024 ME SDI Data Busy Timer SDI SDI Data control control SDIDatCnt 0x5A000030 SDI Data Remain Counter SDIFIFOStaus 50 04000030 RW 1 38 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Cautions on 53 2410 Special Registers 1 In the little endian mode L endi
8. lt REQ4 INT_ADC Figure 14 1 Priority Generating Block 14 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control ARB_MODE and two bits of selection control signals ARB_SEL as follows If ARB SEL bits are 006 the priority order is REQO REQ1 REQ2 REQ3 REQ4 and REQ5 If ARB SEL bits are 01b the priority order is REQO REQ2 REQ3 REQ4 REQ1 and 5 If ARB SEL bits are 10b the priority order is REQO REQ3 REQ4 REQ1 2 and REQ5 If ARB SEL bits are 11b the priority order is REQ0 REQ4 REQ1 REQ2 REQ3 and REQ5 Note that REQO of an arbiter always has the highest priority and REQ5 has the lowest one In addition by changing the ARB SEL bits we can rotate the priority of REQ1 to REQ4 Here if ARB MODE bit is set to 0 ARB SEL bits are not automatically changed making the arbiter to operate in the fixed priority mode note that even in this mode we can reconfigure the priority by manually changing the ARB SEL bits On the other hand if ARB MODE bit is 1 ARB SEL bits are changed in rotation fashion e g if is serviced ARB SEL bits are changed to 01b automatically so as to put REQ into the lowest priority The detailed rules of ARB SEL change are as follows If REQO or REQS is serviced SEL bits not changed at all If is serviced
9. e P p fate Nis P P P s 18 uuce wace l ____ vooop p P P BE Es EINT1 GPF1 kO We ENAME RAN M er 1 mis enoa 1 WM enses ems 1 fe L5 ems 1 oe Ur femmer l6 uaes come 1 fe cmo 1 fe L2 farson om ome 1 el Kis ome ome 6 Ki o ama 1 Ki mov ome KW moums ELECTRONICS PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 1 272 Pin FBGA Pin Assignments Continued Function BUS REQ PWR off nRESET ozara Gens Kiz CNN A7 Tar NL NL NL S nFRE GPA20 3 nFWE GPA19 B 41 is dic Al m2 AO m2 31 530 430 t t t t t t ALE GPA18 CLE GPA17 NL LUN CUN KM LN BEN G13 nwarr nWAIT is Fi7 nacs7 Fi6 neose Fi5 nacssiarat necss Ei nacssGPAM necss Ei _ nocse Ei nscsuaewi
10. Pin Type Pin Example Pin States in Power_OFF Mode GPIO output pin GPBO input Output GPIO data register value is used GPIO input pin GPBO output Input GPIO bi directional pin GPG6 SPIMOSI Input Function output pin nGCSo Output the last ouput level is held Function input pin nWAIT Input 1 8V Regulator 1 8V 53 2410 01 Power CTRL Alive Block External Interrupt Core amp Peripherals Figure 7 14 Power OFF Mode ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT Signaling EINT 15 0 for Wakeup The 53 2410 01 can be woken up from Power OFF mode only if the following conditions are met a Level signals H or L or edge signals rising or falling or both are asserted on EINTn input pin b The EINTn pin has to be configured as EINT in the GPIO control register nBAT has to be level lt is important to configure the EINTn in GPIO control register as an external interrupt pins considering the condition a above Just after the wakeup the corresponding EINTn pin will not be used for wakeup This means that the pin can be used as an external interrupt request pin again Entering IDLE Mode If CLKCON 2 is set to 1 to enter the IDLE mode the S3C2410X01 will enter IDLE mode after some delay until the power control logic receives ACK signal from the CPU wrapper PLL On Off The PLL can only be turned off for low po
11. 2 TTC H 0 5200022 EP2 total transfer counter higher byte 0x00 0x5200022F EP3 L 0x5200024C R W EP3 DMA total transfer counter lower byte 0x00 0x5200024F byte EP3 TTC M 0x52000250 R W EP3 DMA total transfer counter middle byte 0x00 0x52000253 byte EP3 TTC H 0 52000254 R W EP3 DMA total transfer counter higher byte 0x00 0x52000257 byte a irm UJ r lt J Sr 0 aK oe EP4 TTC L 0 52000264 R W EP4 DMA total transfer counter lower byte 0x00 0x52000267 byte EP4 TTC M 0 52000268 R W EP4 DMA total transfer counter middle byte 0x00 0x5200026B byte EP4 H 0x5200026C R W EP4 DMA total transfer counter higher byte 0x00 0x5200026F byte EPn_TTC_L 7 0 DMA total transfer count value lower byte UJ EPn TTC M 7 0 FRE DMA total transfer count value middle byte EPn TTC H 3 0 DMA total transfer count value higher byte 13 24 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER 05 20 2002 INTERRUPT CONTROLLER Preliminary OVERVIEW The interrupt controller in the S3C2410X01 receives the request from 56 interrupt sources These interrupt sources are provided by internal peripherals such as the DMA controller the UART IIC
12. UV UNP SBZ Figure 2 6 Register 10 The entries in the TLBs are replaced using a round robin replacement policy This is implemented using a victim counter which counts from entry 0 up to 63 and then wraps back round to the base value and continues counting wrapping around to the base value from 63 each time There are two mechanisms available for ensuring entries are not removed from the TLB Locking an entry down prevents it from being selected for overwriting during a table walk this is achieved by programming the base value to which the victim counter reloads For example if the bottom 3 entries 0 2 are to be locked down the base counter should be programmed to 3 An entry can also be preserved during an Invalidate All instruction This is done by ensuring the P bit is set when the entry is loaded into the TLB ELECTRONICS 2 21 PROGRAMMER S MODEL ARM920T PROCESSOR Load a single entry into TLB location 0 make it immune to Invalidate All and lock it down MCR to CP15 register 10 opcode 2 0x1 Base Value 0 Current Victim 0 P 1 MCR I prefetch Assuming an TLB miss occurs then entry 0 will be loaded MCR to CP15 register 10 opcode_2 0x1 Base Value 1 Current Victim 1 P 0 Load a single entry into D TLB location 0 make it immune to Invalidate All and lock it down MCR to CP15 register 10 opcode 2 0x0 Base Value 0 Current Victim 0 P 1 Data load LDR LDM or store STR STM Assumi
13. Wa EIN Nd nGCS0 NGCSO 0 0 0 0 0 0 J17 J16 J15 J12 J14 J13 G17 13 F17 E17 D17 17 0 7 1 14 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments Continued Default State State I O State Function BUS PWR off nRESET Type REQ nWE nOE we Hz _ noe mE me B16 _ wz Ai6 _ Dams mz Bi nmas He AT im 814 NN Am 17 5 4 P vso P BIS ap Dis aos 40085 46086 Am NN Em DH FH ws ves BH aom AM anomna Gf aris ADDRIS Amo ELECTRONICS 1 15 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 1 272 Pin FBGA Pin Assignments Continued Function BUS REQ PWR off nRESET Type abomena Hr om OU 50 appRisGPA ADDRIS OU ADDma om oo A9 apprevaras abonar om oo D9 appmeaoPA abone ee ob om ES Hic OU B9 _
14. abonas om oo C9 _ abonas om oo ES appresGPA aoores oo om C8 F9 D G9 B8 A8 D E C dic C9 C8 B8 112 D7 E7 C7 wowe er CD 1 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments Continued Default I O State I O State I O State Function QBUS REQ off nRESET Eod a Fs ws ws A3 pame owe Hz Mz t B3 pw _____ Hz Hz Mz te A ow ___ Hz He He te Ai ____ Hz Hz Mz t 8 Joa ono Mz te Notes 1 The QBUS REQ shows the pin states at the external bus which is used by the other bus master 2 mark indicates the unchanged pin state at Bus Request mode Hi z or Pre means Hi z or Previous state and it is determined by the setting of MISCCR register Al AO means analog input analog output P and mean power input and output respectively The I O state OnRESET shows the pin status in the On RESET duration below 4FCLK nRESET gt lt gt 4 sk UM ELECTRONICS 1 17 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR 7 table below shows I O types and the descriptions
15. can be enabled simultaneously by writing a 1 to bit 0 and to bit 12 in CP15 register 1 with a single MCR instruction INSTRUCTION CACHE OPERATION If the ICache is disabled each instruction fetch results in a separate non sequential memory access on the ASB giving very low performance to burst memory such as page mode DRAM or synchronous DRAM Therefore the ICache should be enabled as soon as possible after reset If the ICache is enabled an ICache lookup is performed for each instruction fetch regardless of the setting of the Ctt bit in the relevant MMU translation table descriptor If the required instruction is found in the cache the lookup is called a cache hit If the required instruction is not found in the cache the lookup is called a cache miss If the instruction fetch is a cache hit and Ctt 1 indicating a cacheable region of memory then the instruction is returned from the cache to the ARM9TDMI CPU core If itis a cache miss and Ctt 1 then an 8 word linefill will be performed possibly replacing another entry The entry to be replaced called the victim is chosen from the entries which are not locked using either a random or round robin replacement policy If Ctt 0 indicating a non cacheable region of memory then a single non sequential memory access will appear on the ASB NOTES If Ctt 0 indicating a non cacheable region of memory then the cache lookup should result in a cache miss The only way that it can resul
16. SUSPEND_INT_EN 0 R W Suspend interrupt enable bit 0 Interrupt disable 1 Enable 13 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE FRAME NUMBER REGISTER FPAME_NUM1_REG FRAME_NUM2_REG When the host transfers USB packets each Start Of Frame SOF packit includes a frame number The USB device controller catches this frame number and loads it into this register automatically Register Address Description Reset Value FRAME NUM1 REG 0x52000170 L Frame number lower byte register 0x00 0x52000173 B Dus FRAME NUM1 7 0 R w Frame number lower byte value ___ 00 FRAME NUM2 REG 0x52000174 L R Frame number higher byte register 0x00 0x52000177 B byte FRAME_NUM2 7 0 W Frame number higher byte value 00 ELECTRONICS 13 11 USB DEVICE 53 2410 01 RISC MICROPROCESSOR INDEX REGISTER INDEX_REG The INDEX register is used to indicate certain endpoint registers effectively The MCU can access the endpoint registers MAXP REG IN_CSR1_REG IN CSR2 REG OUT_CSR1_REG OUT CSR2 REG OUT FIFO CNT1 REG and OUT FIFO CNT2 REG for an endpoint inside the core using the INDEX register Register Address Description Reset Value INDEX REG 0x52000178 L R W Register index register 0x00 0x5200017B B byte INDEX 7 0 RW R Indicate a certain endpoint 00 13 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE END POINTO CONTROL STATUS REGISTER EPO CSR This
17. Timer 4 start stop 20 Determine start stop for Timer 4 0 Stop 1 Start for Timer 4 Timer 3 auto reload on off 19 Determine auto reload on off for Timer 3 0 One shot 1 Interval mode auto reload Timer 3 output inverter on off 18 Determine output inverter on off for Timer 3 0 Inverter off 1 Inverter on for Timer 3 manual update note 17 Determine manual update for Timer 3 0 No operation 1 Update TCNTB3 TCMPB3 Timer 3 start stop 16 Determine start stop for Timer 3 0 Stop 1 Start for Timer 3 Timer 2 auto reload on off 15 Determine auto reload on off for Timer 2 0 One shot 1 Interval mode auto reload Timer 2 output inverter on off 14 Determine output inverter on off for Timer 2 0 Inverter off 1 Inverter on for TOUT2 Timer 2 manual update te 13 Determine the manual update for Timer 2 0 No operation 1 Update TCNTB2 TCMPB2 Timer 2 start stop 12 Determine start stop for Timer 2 0 Stop 1 Start for Timer 2 Timer 1 auto reload on off 11 Determine the auto reload on off for Timer1 0 One shot 1 Interval mode auto reload Timer 1 output inverter on off 10 Determine the output inverter on off for Timer1 0 Inverter off 1 Inverter on for TOUT1 Timer 1 manual update note Determine the manual update for Timer 1 0 No operation 1 Update TCNTB1 TCMPB1 Timer 1 start stop Determine start stop for Timer 1 E 0 Stop
18. UART 1 Line Control 0x50004004 UART 1 Control UART 1 FIFO Control UART 1 Modem Control UART 1 Tx Rx Status UART 1 Rx Error Status UFSTAT1 0x50004018 UART 1 FIFO Status UART 1 Modem Status UART 1 Transmission Hold UART 1 Receive Buffer R W _ 1 Baud Rate Divisor R W UART 2 Line Control UART 2 Control UART 2 FIFO Control UART 2 Tx Rx Status WE 0 Status UART 0 Rx Error UARTORxEmorStatus UART 2 Rx Error Status UART 2 FIFO Status UART 2 Transmission Hold UART 2 Receive Buffer R W UART 2 Baud Rate Divisor 1 30 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued we am demo Name B Endian L Endian Write IT Timer Control Timer Count Buffer 0 R Timer Count Observation RW R Timer Count Observation RW RO Timer Count Observation 2 TCNTB3 0x51000030 R W Timer Count Buffer 3 Timer Count TCNTB4 0x5100003C Timer Count Buffer 4 TCNTO4 0x51000040 Count Observation 4 ELECTRONICS 1 31 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued ce emm B Endian L Endian Write USB Device IT R Frame Number Lower Byis OUT_CSR1_REG 0x52000193 0x52000190 Out Endpoint Control Status FIFO 0x520001C7 0 520001 4 Endpoint 1 FIFO 1 32 E
19. Figure 15 6 TFT LCD Timing Example 15 22 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 SAMSUNG TFT LCD PANEL 3 5 PORTRAIT 256K COLOR REFLECTIVE A SI TFT LCD The S3C2410X01 supports SEC TFT LCD panel SAMSUNG 3 5 Portrait 256K Color Reflective a Si TFT LCD LTS350Q1 PD1 TFT LCD panel with touch panel and front light unit LTS350Q1 PD2 TFT LCD panel only The S3C2410X01 provides timing signals as follows to use LTS350Q1 PD1 and PD2 STH Horizontal Start Pulse TP Source Driver Data Load Pulse INV Digital Data Inversion LCD HCLK Horizontal Sampling Clock CPV Vertical Shift Clock STV Vertical Start Pulse OE Gate On Enable REV Inversion Signal REVB Inversion Signal So LTS350Q1 PD1 and PD2 can be connected with the S3C2410X01 without using the additional timing control logic But the user should additionally apply Vcom generator circuit various voltages INV signal and Gray scale voltage generator circuit which is recommended by PRODUCT INFORMATION SPEC of LTS350Q1 PD1 and PD2 Detailed timing diagram is also described in PRODUCT INFORMATION SPEC of LTS350Q1 PD1 and PD2 Refer to the documentation PRODUCT INFORMATION of LTS350Q1 PD1 and PD2 which is prepared by AMLCD Technical Customer Center of Samsung Electronics Co LTD CAUTION The 53 2410 01 has HCLK working as the clock of AHB bus Accidentally SEC TFT LCD panel LTS350Q1 PD1 and PD2 has Horizont
20. PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR FEATURES Architecture e Integrated system for hand held devices and general embedded applications 16 32 Bit RISC architecture and powerful instruction set with ARM920T CPU core e Enhanced ARM architecture MMU to support WinCE 32 and Linux e Instruction cache data cache write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance ARM920T CPU core supports the ARM debug architecture e Internal Advanced Microcontroller Bus Architecture AMBA AMBA2 0 AHB APB System Manager Little Big Endian support e Address space 128M bytes for each bank total 1G bytes Supports programmable 8 16 32 bit data bus width for each bank e Fixed bank start address from bank 0 to bank 6 Programmable bank start address and bank size for bank 7 e Eight memory banks Six memory banks for ROM SRAM and others Two memory banks for ROM SRAM Synchronous DRAM e Fully Programmable access cycles for all memory banks e Supports external wait signals to expend the bus cycle Supports self refresh mode in SDRAM for power down e Supports various types of ROM for booting NOR NAND Flash EEPROM and others NAND Flash Boot Loader Supports booting from NAND flash memory internal buffer for booting e Supports storage memory for NAND flash memory after booting Cache Memory 64 set associative
21. X Y Position Conversion Delay Value 2 Waiting for Interrupt Mode When Stylus down occurs in Waiting for Interrupt Mode this register generates Interrupt signal INT_TC at intervals of several ms for Auto X Y Position conversion Note Do not use Zero value 0x0000 Note 1 Before ADC conversion Touch screen uses X tal clock or EXTCLK Waiting for Interrupt Mode 2 During ADC conversion PCLK is used ELECTRONICS 16 9 A D CONVERTER AND TOUCH SCREEN 3C2410X01 RISC MICROPROCESSOR ADC CONVERSION DATA ADCDATO REGISTER ADCDATO 0x5800000C RO ADC conversion data register UPDOWN 15 Up or down state of Stylus at Waiting for Interrupt Mode 0 Stylus down state 1 Stylus up state AUTO PST 14 Automatic sequencing conversion of X position and Y position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position Reserved 11 10 XPDATA X position conversion data value Normal ADC include Normal ADC conversion data value Data value 0 13 12 Manual measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode 16 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR A D CONVERTER AND TOUCH SCREEN ADC CONVERSION DATA ADCDAT1 REGISTER ADCDAT 1 0x58000010 ADC conversion data register 15 UPDOWN Up or down state of Stylus at Waiting for Interrupt Mode 0 Stylus dow
22. 1 Negate remainder if dividend sign 1 Effectively zero a4 as top bit will be shifted out later Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence just div 4 42 MOVS BEQ CMP MOVLS BLO CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV divide by zero a3 a2 LSR 1 a3 a3 LSL 1 s loop a2 a3 a4 a4 a4 a2 a2 a3 a3 al a3 a3 LSR 1 S loop2 al a4 ip ip ASL 1 a1 a1 0 a2 a2 0 Ir Justification stage shifts 1 bit at a time NB LSL 1 is always OK if LS succeeds ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code Thumb Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 MOV a2 al LSR a3 a1 2 SUB al a3 LSR a3 al 4 ADD al a3 LSR a3 a1 8 ADD a1 a3 LSR a3 a1 16 ADD a1 a3 LSR al 3 ASL a3 a1 2 ADD a3 a1 ASL a3 1 SUB a2 a3 CMP a2 10 BLT FTO ADD al 1 SUB a2 10 0 MOV Ir ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 ai 10 SUB a1 a1 Isr 2 ADD al al al Isr 4 ADD a1 a1 a1 Isr 8 ADD a1 a1 al Isr 1
23. 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from RdHi The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to RdHi The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write a two s complement signed 64 bit result ELECTRONICS 3 25 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR OPERAND RESTRICTIONS e R15 must not be used as an operand or as a destination register e RdLo and Rm must all specify different registers CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N is equal to bit
24. 6 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT 05 24 2002 CLOCK amp POWER MANAGEMENT Preliminary OVERVIEW The clock amp power management block consists of three parts clock control USB control and power control The Clock control logic in S3C2410X01 can generate the required clock signals including FCLK for CPU HCLK for the AHB bus peripherals and PCLK for the APB bus peripherals The S3C2410X01 has two Phase Locked Loops PLLs one for FCLK HCLK and PCLK and the other dedicated for USB block 48Mhz The clock control logic can make slow clocks without PLL and connect disconnect the clock to each peripheral block by software which will reduce the power consumption For the power control logic the S3C2410X01 has various power management schemes to keep optimal power consumption for given task The power management block in the S3C2410X01 can activate five modes NORMAL mode SLOW mode IDLE mode and Power OFF mode NORMAL mode the block supplies clocks to CPU as well as all peripherals in the S3C2410X01 In this mode the power consumption will be maximized when all peripherals are turned on It allows the user to control the operation of peripherals by software For example if a timer is not needed the user can disconnect the clock to the timer to reduce power consumption SLOW mode Non PLL mode Unlike the Normal mode the Slow mode uses an external clock or EXTCLK d
25. Read ICache lock down base p15 0 Rd c9 c0 1 Write ICache victim and lockdown base MCR 15 0 9 0 1 2 20 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 10 TLB LOCK DOWN REGISTER Register 10 is the TLB lock down register The TLB lock down register is 0x0 on reset There is a TLB lock down register for each of the TLBs the value of opcode_2 determines which TLB register to access opcode 2 0x0 causes the D TLB register to be accessed opcode 2 0x1 causes the TLB register to be accessed Reading CP15 register 10 returns the value of the TLB lock down counter base register the current victim number and the preserve bit P bit Note that bits 19 1 are unpredictable when read Writing CP15 register 10 updates the TLB lock down counter base register the current victim pointer and the state of the preserve bit Bits 19 1 should be zero when written Table 2 19 shows the instructions needed to access the TLB lock down register Table 2 19 Accessing the TLB Lock Down Register 10 Read D TLB lock down TLB lock down MRC p15 0 Rd c10 c0 0 Write D TLB lock down TLB lock down MCR p15 0 Rd c10 c0 0 Read TLB lock down TLB lock down MRC p15 0 Rd c10 c0 1 Write TLB lock down TLB lock down MCR p15 0 Rd c10 c0 1 Figure 2 6 shows the format of bits in register 10 31 26 25 20 19 18 17 16 15 14 13 12 11109 876543210
26. Store R1 at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load R1 from contents of R2 R3 4 Conditionally load byte at R6 5 into R1 bits O to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 33 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR HALFWORD AND SIGNED DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 2827 25 24 23 22 21 20 19 16 15 12 11 8 765 4 3 Des Dom oe 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfword 1 1 Signed byte 1 1 halfword 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre ad
27. The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 28 27 22 21 20 19 16 15 12 11 _ w amp D 15 12 11 8 3 0 Registers 19 16 Destination Register 20 Set Condition Code 0 Do not after condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs Rn is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 s complement or unsigned integers The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplication of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38
28. 8 8 DATA FIFO DATA EXT FIFO STATUS Figure 12 1 USB Host Controller Block Diagram This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 12 1 USB HOST 53 2410 01 RISC MICROPROCESSOR USB HOST CONTROLLER SPECIAL REGISTERS S3C2410 USB cost controller complies with OHCI Rev 1 0 Refer to Open Host Controller Interface Rev 1 0 specification for detail information OHCI REGISTERS FOR USB HOST CONTROLLER 0900004 HeCommonsiatus HemerrptStaus 6490006 ae 0460000 uo HeerupDiable _ox49000014 e oxao000010 HeComwHeadED 0x49000020 Ls HeComwCumemED px HcBulkHeadED 0x49000028 HeBukCurentED ox49000020 Pea 0x49000030 HcFmRemaining 0x49000038 HeFmNumber Oweooc HePeriodieStan 0x49000040 m HetsTiveshols _ox49000044 HeRhDesciorB oxaoooooac 0x490000s0 HenPorStanust 049000 Hephponsausz um 12 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE 05 24 2002 USB DE
29. CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR PLL VALUE SELECTION GUIDE It is not easy to find a proper PLL value So We recommended referring to the following PLL value recommendation table Input Frequency Output Frequency MDIV PDIV SDIV 12 00MHz 16 934MHz N A N A N A 12 00MHz 22 50MHz N A N A N A 82 052 12 00MHz 45 00MHz 82 0x52 1 3 12 00Mhz 48 00Mhz 40 0x28 1 2 12 00MHz 56 25MHz 142 0x86 2 3 12 00MHz 79 00MHz 71 0x47 1 2 106 0469 mor aa mum s 2 1 109 2 16 074 2 1 wo 2 1 sou 1 1 C ome nom 1 1 1 1 mos 1 1 sos 1 I 1 sos 1 1 som woan 3 I 1 The 48 00Mhz output is used for UPLLCON register n 7 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK CONTROL REGISTER CLKCON 0x4C00000C R W Clock generator control register Ox7FFFO 18 Control PCLK into SPI block 0 Disable 1 Enable 17 Control PCLK into IIS block 0 Disable 1 Enable 16 Control PCLK into block 0 Disable 1 Enable ADC amp Touch Screen 15 Control PCLK into ADC block 0 Disable 1 Enable RTC 14 Control PCLK into RTC control block Even if this bit is cleared to 0 RTC timer is alive 0 Disable
30. ELECTRONICS 1 19 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 2 S3C2410 Signal Descriptions Continued Signal uo LCD Control Unit VD 23 0 O STN TFT SEC TFT LCD Data Bus LCD PWREN STN TFT SEC TFT LCD panel power enable control signal VCLK LCD clock signal VFRAME Frame signal VLINE STN LCD line signal STN VM alternates the polarity of the row and column voltage VSYNC O TFT Vertical synchronous signal HSYNC TFT Horizontal synchronous signal VDEN O Data enable signal LEND O TFT Line End signal SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal o SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCD HCLK SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal SEC SEC Samsung Electronics Company TFT LCD panel control signal ISTH 00 SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCDVF 2 0 SEC TFT Timing control signal for specific TFT LCD OE REV REVB Interrupt Control Unit EINT 23 0 EN External Interrupt request nXDREQ 0 1 External DMA request nXDACKI1 0 External DMA acknowledge UART RxD 2 0 EX UART receives data input TxD 2 0 UART transmits data output nCTS 1 0 aM UART clear to send input signal nRTS 1 0 UART request to send output signal
31. EXAMPLES LDRH R1 R2 R3 Load R1 from the contents of the halfword address contained in R2 R3 both of which are registers and write back address to R2 STRH R3 R4 14 Store the halfword in at R14 14 but don t write back LDRSB R8 R2 223 Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 LDRNESH R11 RO Conditionally load R11 with the sign extended contents of the halfword address contained in RO HERE Generate PC relative offset to address FRED STRH R5 PC FRED HERE 8 Store the halfword in R5 at address FRED FRED ELECTRONICS 3 39 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load LDM or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data around main memory THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can also transfer to and from the user bank see below The register list is a 16 bit field in the instruction wit
32. Figure 10 6 Inverter On Off The following procedure describes how to maintain TOUT as high or low assume the inverter is off 1 Turn off the auto reload bit And then TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn lt TCMPn the output level is high If TCNTn gt TCMPhn the output level is low 3 The TOUTn can be inverted by the inverter on off bit in TCON The inverter removes the additional circuit to adjust the output level 10 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device This function enables the insertion of the time gap between a turn off of a switching device and a turn on of another switching device This time gap prohibits the two switching devices from being turned on simultaneously even for a very short time TOUTO is the PWM output nTOUTO is the inversion of the TOUTO If the dead zone is enabled the output wave form of TOUTO and nTOUTO will be TOUTO DZ and nTOUTO DZ respectively nNTOUTO_DZ is routed to the TOUT pin In the dead zone interval TOUTO DZ and nTOUTO DZ can never be turned on simultaneously Deadzone Interval Figure 10 7 The Wave Form When a Dead Zone Feature is Enabled ELECTRONICS 10 9 PWM TIMER S3C2410X01 RISC MICROPROCESSOR DMA REQUEST MODE The PWM timer can generate
33. RES SEL 1 Same the LPC3600 0 320x240 1 2 240x320 LPC EN Determine LPC3600 Enable Disable 1 LPC3600 Enable 15 38 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 Register Setting Guide STN The LCD controller supports multiple screen sizes by special register setting The CLKVAL value determines the frequency of VCLK This value has to be determined such that the VCLK value is greater than data transmission rate The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register The data transmission rate is given by the following equation Data transmission rate HS x VS x FR x MV HS Horizontal LCD size VS Vertical LCD size FR Frame rate MV Mode dependent value Table 15 6 MV Value for Each Display Mode mode Mono 4 bit single scan display 1 4 16 level gray 4 bit single scan display 16 level gray 8 bit single scan display or 4 bit dual scan display Color 4 bit single scan display Color 8 bit single scan display or 4 bit dual scan display The LCDBASEU register value is the first address value of the frame buffer The lowest 4 bits must be eliminated for burst 4 word access The LCDBASEL register value depends on LCD size and LCDBASEU The LCDBASEL value is given by the following equation LCDBASEL LCDBASEU LCDBASEL offset This document is a preliminary user s manual So our company will present it
34. RISC MICROPROCESSOR lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR STR cond H SB SH Rd lt address gt can be 1 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 Transfer halfword quantity Load sign extended byte Only valid for LDR Load sign extended halfword Only valid for LDR An expression evaluating to a valid register number An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register A post indexed addressing specification Rn lt expression gt Rn Rm offset of lt expression gt bytes offset of contents of index register Rn and Rm are expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining In this case base write back should not be specified Writes back the base register set the W bit if is present ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET
35. SEL bits are changed to 016 If REQ2 is serviced SEL bits are changed to 10b If REQ3 is serviced SEL bits are changed to 11b If REQ4 is serviced SEL bits are changed to 000 ELECTRONICS 14 5 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller source pending register interrupt mode register mask register priority register and interrupt pending register All the interrupt requests from the interrupt sources are first registered in the source pending register They are divided into two groups including Fast Interrupt Request FIQ and Interrupt Request IRQ based on the interrupt mode register The arbitration procedure for multiple IRQs is based on the priority register SOURCE PENDING SRCPND REGISTER The SRCPND register is composed of 32 bits each of which is related to an interrupt source Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced Accordingly this register indicates which interrupt source is waiting for the request to be serviced Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register In addition the SRCPND register is not affected by the priority logic of interrupt controller In the interrupt service routine for a specif
36. Type Descriptions d1i vdd1ih s3i vss3i 1 8V Vdd Vss for internal logic dic vdd1ih_core s3i vss3i 1 8V Vdd Vss for internal logic without input driver d3o vdd3op s3o vss3op 3 3V Vdd Vss for external logic d3t vdd3t abb s3t vss3t abb 3 3V Vdd Vss for analog circuitry phis phot 16phot sm r10 phiar10_abb Analog input pad with 10 ohm resistor abb m26 phsoscm26 Oscillator cell with enable and feedback resistor te phbsu100ct6sm Bi directional pad LVCMOS schmitt trigger 100Kohm pull up resistor with control tri state lo 6mA t8 phbsu100ct8sm Bi directional pad LVCMOS schmitt trigger 100Kohm pull up resistor with control tri state 10 8 t12 phbsu100ct12sm Bi directional pad LVCMOS schmitt trigger 100Kohm pull up resistor with control tri state lo 12mA d8 phbsu100cd8sm Bi directional pad LVCMOS schmitt trigger 100Kohm pull up resistor with control open drain lo 8mA 1 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW SIGNAL DESCRIPTIONS Table 1 2 S3C2410 Signal Descriptions Signal 10 Desipons Bus Controller OM 1 0 OM 1 0 sets S3C2410 in the TEST mode which is used only at fabrication Also it determines the bus width of nGCSO The pull up down resistor determines the logic level during the RESET cycle 00 Nand boot 01 16 bit 10 32 bit 11 Test mode ADDR 26 0 oO ADDR 26 0 Address Bus outputs the m
37. 0 Master mode IISLRCK and IISCLK are output mode 1 Slave mode IISLRCK and IISCLK are input mode Transmit receive mode 7 6 00 transfer 01 Receive mode select 10 Transmit mode 11 Transmit and receive mode Active level of left right 5 0 Low for left channel High for right channel channel 1 High for left channel Low for right channel Serial interface format 0 IIS compatible format 4 EN 1 MSB Left justified format Serial data bit per channel 0 8 bit 1 16 bit 1 Master clock frequency 0 2565 1 38415 select fs sampling frequency 0 Serial bit clock frequency 00 16fs 01 32fs select 10 48fs 11 NA Notes 1 The IISMOD register is accessible for each halfword and wordunit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word 21 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIS BUS INTERFACE IIS PRESCALER IISPSR REGISTER IISPSR 0x55000008 Li HW Li W Bi W R W IIS prescaler register 0 0 0 5500000 Bi HW Prescaler control Data value 0 31 Note Prescaler A makes the master clock that is used the internal block and division factor is N 1 Prescaler control B 4 0 Data value 0 31 00000 Note Prescaler B makes the master clock that is used the external block and division factor is N 1 Notes 1 The IISPSR regi
38. 0 Priority does not rotate 1 Priority rotate enable ARB_MODE2 2 Arbiter 2 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB_MODE1 1 Arbiter 1 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable MODEO 0 Arbiter 0 group priority rotate enable 1 0 Priority does not rotate 1 Priority rotate enable 14 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT PENDING INTPND REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request which is unmasked and waits for the interrupt to be serviced has the highest priority Since the INTPND register is located after the priority logic only one bit can be set to 1 and that interrupt request generates IRQ to CPU In interrupt service routine for IRQ you can read this register to determine which interrupt source is serviced among the 32 sources Like the SRCPND register this register has to be cleared in the interrupt service routine after clearing the SRCPND register We can clear a specific bit of the INTPND register by writing a data to this register It clears only the bit positions of the INTPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are INTPND 0X4A000010 R W Indicate the interrupt request statu
39. K issued or not OUT PKT RDY condition happens This is only useful for DMA mode 0 Interrupt Enable 1 Interrupt Disable ELECTRONICS 13 17 USB DEVICE 53 2410 01 RISC MICROPROCESSOR END POINT FIFO REGISTER EPN_FIFO_REG The EPn_FIFO_REG enables the MCU to access to the EPn FIFO Register Address R W Description Reset Value EPO FIFO 0 520001 0 1 R W End Pointo FIFO register OxXX 0x520001C3 B byte EP1 FIFO 0x520001C4 R W End Point1 FIFO register OxXX 0x520001C7 byte EP2 FIFO 0x520001C8 R W End Point2 FIFO register OxXX 0x520001CB byte KIRA Lp BE Lg EP3_FIFO 0x520001CC R W End Point3 FIFO register OxXX 0x520001CF byte EP4_FIFO 0x520001D0 R W End Point4 FIFO register OxXX 0x520001D3 byte FIFO DATA 7 0 FIFO data value 13 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE MAX PACKET REGISTER MAXP_REG MAXP_REG 0x52000180 L R W End Point MAX packet register 0x01 0x52000183 B byte MAXP 3 0 R W 0000 Reserved 0001 MAXP 8 Byte0010 MAXP 16 Byte 0100 MAXP 32 Byte1000 MAXP 64 Byte For EPO MAXP 8 is recommended For EP1 4 MAXP 32 or MAXP 64 is recommended And if MAXP 32 the dual packet mode will be enabled automatically ELECTRONICS 13 19 USB DEVICE 53 2410 01 RISC MICROPROCESSOR END POINT OUT WRITE COUNT REGISTER OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG These registers maintain the number of bytes in t
40. Note that the THUMB opcode will contain 53 as the Word 8 value ELECTRONICS 4 29 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 13 ADD OFFSET TO STACK POINTER 15 14 13 12 11 10 6 0 1 9 8 7 1 6 0 7 bit Immediate Value 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 4 14 Format 13 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 4 14 The ADD SP Instruction THUMB assembler ARMequivalent 0 ADD SP ADD R13 R13 mm Add Imm to the stack pointer SP 1 ADD SP Imm SUB R13 R13 flmm Add Imm to the stack pointer SP NOTE The offset specified by 1 can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD SP 4268 R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the Word value and 5 0 ADD SP 44 104 SP R13 SP 104 but don t set th
41. SDI Baud Rate Prescaler SDIPRE Register Reset Val SDIPRE 0x5A000004 SDI baud rate prescaler register 0 0 Prescaler Value 7 0 Initial Value Determine SDI clock SDCLK rate as above equation 0x00 Baud rate PCLK 2 Prescaler value 1 SDI Command Argument Register SDICARG Reset Value SDICARG 0x5A000008 SDI command argument register SDICARG initial Value CmdArg 31 0 Command Argument 0x00000000 ere 19 4 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR SD HOST CONTROLLER SDI Command Control SDICCON Register Reset Val SDICCON 0x5A00000C SDI command control register SDICCON Description Abort Command 12 Determine whether command type is for abort for 5010 AbortCmd 0 normal command 1 abort command CMD12 CMD52 2227 Command with 11 Determine whether command type is with data for SDIO Data WithData 0 without data 1 with data LongRsp Determine whether host receives a 136 bit long response or not 0 0 short response 1 long response WaitRsp Determine whether host waits for a response or not RE 0 no response 1 wait response BEEN Command Determine whether command operation starts or not Start CMST 0 command ready 1 command start SDI Command Status SDICSTA Register Reset Value SDICSTA 0x5A000010 R W SDI command status register 0 0 SDICSTA Bi iitialValue Response 12 CRC check failed when command response
42. The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 256 Color Displays Color displays require 3 bits Red Green and Blue of image data per pixel and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines Figure 15 3 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays 4096 Color Displays Color displays require 3 bits Red Green and Blue of image data per pixel and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines This RGB order is determined by the sequence of video data in video buffers 15 8 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR MEMORY DATA FORMAT STN BSWP 0 Mono 4 bit Dual Scan Display Video Buffer Memory Address Data 0000H A 31 0 0004H B 31 0 1000H 31 0 1004H _ M 31 0 Mono 4 bit Single Scan Display amp 8 bit Single Scan Display Video Buffer Memory Address Data 0000H A 31 0 0004H B 31 0 0008H C 31 0 LCD CONTROLLER 05 20 2002 LCD Pane
43. am o G6 P P P am Gr P P P ate Hi Jvssem ____ P p p s H4 monano Gem 1 fe H2 _ ome o sro fu ELECTRONICS 1 9 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 1 272 Pin FBGA Pin Assignments Continued MD omo oi S Function BUS REQ PWR off nRESET Type 5 too o i X fuenoierco emo owe 1 3 owe 1 7 6 uee 1 KS vonam P P P ee Vssam ____ P p p al ema ome 7 NUN NN Ke covers eros 714 weoec 6m owe 1 Ms wececn owe 15 Woam P P P aio Mi vssam s L6 L3 L1 L2 L4 5 VD13 GPD5 VD14 GPD6 VD15 GPD7 1 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments Continued EEE Function BUS REQ PWR off nRESET Type 72 Gp owe 1 R8 ees ___ R4 _ Go owe Uz voreero owe 1 fe T _ Gi owe fe Us voawerois
44. and 4 both source and destination are in the peripheral bus The main advantage of the DMA is that it can transfer the data without CPU intervention The operation of DMA can be initiated by software or requests from internal peripherals or external request pins This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 8 1 DMA 3C2410X01 RISC MICROPROCESSOR DMA REQUEST SOURCES Each channel of the DMA controller can select one of DMA request source among four DMA sources if HW DMA request mode is selected by DCON register Note that if S W request mode is selected this DMA request sources have no meaning at all Table 8 1 shows four DMA sources for each channel dl il el Rl nXDREQ1 UART1 I2SSDI SPIO USB device EP2 125500 125501 USB device EP3 Table 8 1 DMA Request Sources for Each Channel nXDREQO and nXDREQ1 represent two external sources External Devices and 125500 I2SSDI represent IIS transmitting and receiving respectively DMA OPERATION DMA uses three state FSM finite state machine for its operation which is described in the three following steps State 1 As an initial state the DMA waits for a DMA request If it comes it goes to state 2 At this state DMA ACK and INT REQ are 0 State 2 In this state DMA ACK become
45. and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 word store STR should generate word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 3 30 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET USE OF R15 Write back must not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When R15 is the source register Rd of a register store STR instruction the stored value will be address of the instruction plus 12 Restriction on the use of base register When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value EXAMPLE LDR RO R1 R1 Therefore a post indexed LDR or STR wher
46. and others In these interrupt sources the UARTn and EINTn interrupts are OR ed to the interrupt controller When receiving multiple interrupt requests from internal peripherals and external interrupt request pins the interrupt controller requests or IRQ interrupt of the ARM920T core after the arbitration procedure The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register which helps users notify which interrupt is generated out of various interrupt sources 2 SUBSRCPND SUBMASK SRCPND INTPND Request sources without sub register LCD interrupt has different features Please see the chapter 15 LCD Controller FIGURE 14 1 INTERRUPT PROCESS DIAGRAM This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 14 1 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR INTERRUPT CONTROLLER OPERATION F bit and I bit of Program Status Register PSR If the F bit of PSR in ARM920T CPU is set to 1 the CPU does not accept the Fast Interrupt Request FIQ from the interrupt controller Likewise If I bit of the PSR is set to 1 the CPU does not accept the Interrupt Request IRQ from the interrupt controller So the interrupt controller can receive interrupts by clearing F bit or I bit of the PSR to 0
47. and polarity Dead zone generation Supports external clock sources RTC Real Time Clock Full clock feature msec second minute hour date day month and year 32 768 KHz operation Alarm interrupt Time tick interrupt General purpose input output ports 24 external interrupt ports 117 multiplexed input output ports ELECTRONICS 1 3 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR UART 3 channel UART with DMA based or interrupt based operation Supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive Tx Rx Supports external clocks for the UART operation UCLK e Programmable baud rate Supports IrDA 1 0 e Loopback mode for testing Each channel has internal 16 byte Tx FIFO and 16 byte Rx FIFO DMA Controller 4 ch DMA controller Supports memory to memory IO to memory memory to IO and 10 to IO transfers Burst transfer mode to enhance the transfer rate A D Converter amp Touch Screen Interface 8 ch multiplexed ADC 500KSPS and 10 bit Resolution LCD Controller STN LCD displays Feature Supports 3 types of STN LCD panels 4 bit dual scan 4 bit single scan 8 bit single scan display type e Supports monochrome mode 4 gray levels 16 gray levels 256 colors and 4096 colors for STN LCD e Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum virtual screen size is 4 Mbytes Maximum virtual screen siz
48. by setting one to this bit 0 not detect 1 data finish detect Only busy check finish This flag is cleared by setting one to this bit 0 not detect 1 busy finish detect Start bit is not detected on all data signals in wide bus mode This flag is cleared by setting one to this bit 0 not detect 1 command end Data transmit in progress Data receive in progress 0x0 Initial Value ELECTRONICS 3C2410X01 RISC MICROPROCESSOR SD HOST CONTROLLER SDI FIFO Status SDIFSTA Register RW Reset Value SDIFSTA 0x5A000088 SDI FIFO status register 00 SDIFSTA miasme FIFO available Indicate that FIFO data is available for transmission when Detect for Tx DatMode SDIDCON 12 is data transmit mode If DMA mode is TFDET enable SD host requests DMA operation 0 not detect FIFO full 1 detect 0 lt FIFO lt 15 FIFO available 12 Indicate that FIFO data is available for reception when DatMode Detect for Rx SDIDCON 12 is data receive mode If DMA mode is enable SD RFDET host requests DMA operation 0 not detect FIFO empty 1 detect 1 lt FIFO lt 16 Tx FIFO Half Full 11 Set 1 whenever Tx FIFO is less than 33byte TFHalf 0 33 lt Tx FIFO lt 64 1 0 lt Tx FIFO lt 32 Tx FIFO Empty 10 to 1 whenever Tx FIFO is empty TFEmpty 1 lt Tx FIFO lt 64 1 Empty Obyte Rx FIFO Last Data Sa to 1 whenever Rx FIFO has last data of all block Ready
49. except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 Contents of Rm carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 22 Bit 31 of Rmis again used as the carry output and each bit of operand 2 is also equal to bit 31 of Rm The result is therefore all ones or all zeros according to the value of bit 31 of Rm ELECTRONICS 3 13 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR Rotate right ROR operations reuse the bits which overshoot in a logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example ROR 5 is shown in Figure 3 9 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right The form of the shift field which might be expected to give ROR 0 is used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 Contents of Rm in Value of Operand 2 Figure 3 10 Rotate Right Extended 3 14 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION
50. mostly they just save code USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Rn p If Rn p OR Rm q THEN GOTO Label BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q condition not satisfied try other test BEQ Label Absolute Value TEQ Rn 0 Test sign RSBMI Rn Rn 0 and 2 s complement if necessary Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 Multiply by 4 CMP Rb 5 Test value ADDCS Complete multiply by 5 ADDHI Complete multiply by 6 Combining Discrete and Range Tests TEQ 127 Discrete test CMPNE 1 Range test MOVLS IF lt Rc ASCII 127 THEN ELECTRONICS 3 59 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit available from your supplier A short general purpose divide routine follows Enter with numbers in Ra and Rb MOV Rent 1 Bit to control the division Div1 CMP Rb 0x80000000 Move Rb until greater than Ra CMPCC Rb Ra MOVCC Rb Rb ASL 1 MOVCC Rent Rent ASL 1 BCC Div1 MOV Rc 0 Div2 CMP Ra Rb Test for possible subtraction SUBCS Ra Ra Rb Subtract if ok ADDCS Rc Rc Rcnt Put relevant bit into result MOVS Rent Rent _SR 1 Shift control
51. 1 Enable GPIO 13 Control PCLK into GPIO block 0 Disable 1 Enable 1 1 1 1 1 1 UART2 12 Control PCLK into UART2 block 1 0 Disable 1 Enable 1 1 1 1 1 1 1 Control PCLK into UART1 block 0 Disable 1 Enable Register CLKCON UART1 UARTO 10 Control PCLK into UARTO block 0 Disable 1 Enable Control PCLK into SDI interface block 0 Disable 1 Enable Control PCLK into PWMTIMER block 0 Disable 1 Enable USB device 7 Control PCLK into USB device block 0 Disable 1 Enable Control HCLK into USB host block 0 Disable 1 Enable LCDC 5 Control HCLK into LCDC block 0 Disable 1 Enable NAND Flash Controller 4 Control HCLK into NAND Flash Controller block 1 0 Disable 1 Enable SDI PWMTIMER USB host Control Power Off mode of S3C2410 0 Disable 1 Transition to Power OFF mode Enter IDLE mode This bit is not be cleared automatically POWER OFF IDLE BIT N 0 Disable 1 Transition to IDLE mode Reserved io ELECTRONICS 7 19 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR CLOCK SLOW CONTROL CLKSLOW REGISTER CLKSLOW 0x4C000010 Slow clock control register 0x00000004 UCLK ON 7 0 UCLK ON UPLL is also turned on and the UPLL lock time is inserted automatically 1 UCLK OFF UPLL is also turned off Reserve
52. 1 Requested INT_TIMER4 0 Not requested 1 Requested INT 0 Notrequested 1 Requested INT_WDT 0 Not requested 1 Requested INT_TICK 0 Not requested 1 Requested 4_7 0 Not requested 1 Requested 0 2 0 Not requested 1 Requested EINT1 0 Not requested 1 Requested EINTO 0 Not requested 1 Requested 9 4 3 0 Not requested 1 Requested 2 ELECTRONICS 14 7 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR INTERRUPT MODE INTMOD REGISTER This register is composed of 32 bits each of which is related to an interrupt source If a specific bit is set to 1 the corresponding interrupt is processed in the FIQ fast interrupt mode Otherwise it is processed in the IRQ mode normal interrupt Note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller you should use the FIQ mode only for the urgent interrupt Thus only one bit of INTMOD can be set to 1 INTMOD 0X4A000004 R W Interrupt mode regiseter 0x00000000 0 IRQ mode 1 FIQ mode Note If an interrupt mode is set to FIQ mode in the INTMOD register FIQ interrupt will not affect both INTPND and INTOFFSET registers In this case the two registers are valid only for IRQ mode interrupt source 14 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTMOD Description mitialstate INT ADC INT INT SPI 0 IRQ
53. 1 Start for Timer 1 Note The bits have to be cleared at next writing 4 ELECTRONICS 10 13 PWM TIMER S3C2410X01 RISC MICROPROCESSOR TCON Continued Dead zone enable 4 Determine the dead zone operation 0 Disable 1 Enable Timer 0 auto reload on off 3 Determine auto reload on off for Timer 0 0 One shot 1 Interval mode auto reload Timer 0 output inverter on off 2 Determine the output inverter on off for Timer 0 0 Inverter off 1 Inverter on for TOUTO Timer 0 manual update note 1 Determine the manual update for Timer 0 0 No operation 1 Update TCNTBO TCMPBO Timer 0 start stop Determine start stop for Timer 0 0 Stop 1 Start for Timer 0 NOTE The bit have to be cleared at next writing 10 14 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER TIMER 0 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTBO 0x5100000C R W Timer 0 count buffer register 0x00000000 TCMPBO 0x51000010 Timer 0 compare buffer register 0x00000000 Timer 0 compare buffer register 15 0 Set compare buffer value for Timer 0 0x00000000 Timer 0 count buffer register 15 0 Set count buffer value for Timer 0 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER TCNTOO TCNTOO 0x51000014 count observation register 0x00000000 Timer 0 observation register 15 0 Set count observation value for Timer 0 0x00000000 ELECTRONICS 1
54. 12 5000 MHz 20 4800 48 8281 KHz 1 3421 1 8 PCLK 50 MHz 0 1600 6 2500 MHz 40 9601 24 4140 KHz 2 6843 1 16 PCLK 50 MHz 0 3200 3 1250 MHz 81 9188 12 2070 KHz 5 3686 BASIC TIMER OPERATION TCNTn TCMP TCNTn TCMPn Timer is stopped TCMPn 1 1 1 1 1 1 1 1 1 1 I u Manual update 1 Interrupt request 1 Auto reload 1 Figure 10 2 Timer Operations A timer except the timer ch 5 has TCNTBn TCNTn TCMPBn and TCMPn TCNTn and TCMPn are the names of the internal registers The TCNTn register can be read from the TCNTOn register The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0 When the TCNTn reaches 0 an interrupt request will occur if the interrupt is enabled ELECTRONICS 10 3 PWM TIMER S3C2410X01 RISC MICROPROCESSOR AUTO RELOAD amp DOUBLE BUFFERING S3C2410X01 PWM Timers have a double buffering function enabling the reload value changed for the next timer operation without stopping the current timer operation So although the new timer value is set a current timer operation is completed successfully The timer value can be written into Timer Count Buffer register TCNTBn and the current counter value of the timer can be read from Timer Count Observation register TCNTOn If the TCNTBn is read the read value does not indicate the current state of the counter b
55. 15 5 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR 256 Level Color Mode Operation The S3C2410X01 LCD controller can support an 8 bit per pixel 256 color display mode The color display mode can generate 256 levels of color using the dithering algorithm and FRC The 8 bit per pixel are encoded into 3 bits for red 3 bits for green and 2 bits for blue The color display mode uses separate lookup tables for red green and blue Each lookup table uses the REDVAL 31 0 of REDLUT register GREENVAL 31 0 of GREENLUT register and BLUEVAL 15 0 of BLUELUT register as the programmable lookup table entries Similar to the gray level display 8 group or field of 4 bits in the REDLUR register i e REDVAL 31 28 REDLUT 27 24 REDLUT 23 20 REDLUT 19 16 REDLUT 15 12 REDLUT 1 1 8 REDLUT 7 4 and REDLUTT S 0 are assigned to each red level The possible combination of 4 bits each field is 16 and each red level should be assigned to one level among possible 16 cases In other words the user can select the suitable red level by using this type of lookup table For green color the GREENVAL 31 0 of the GREENLUT register is assigned as the lookup table as was done in the case of red color Similarly the BLUEVAL 15 0 of the BLUELUT register is also assigned as a lookup table For blue color 2 bits are allocated for 4 blue levels different from the 8 red or green levels 4096 Level Color Mode Operation The 53 2410 01 LCD controller can supp
56. 15 7 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR Display Types The LCD controller supports 3 types of LCD drivers 4 bit dual scan 4 bit single scan and 8 bit single scan display mode Figure 15 2 shows these 3 different display types for monochrome displays and Figure 15 3 show these 3 different display types for color displays 4 bit Dual Scan Display Type A 4 bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half as shown in Figure 15 2 The end of frame is reached when each half of the display has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 4 bit Single Scan Display Type A 4 bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 4 pins VD 3 0 for the LCD output from the LCD controller can be directly connected to the LCD driver and the 4 pins VD 7 4 for the LCD output are not used 8 bit Single Scan Display Type An 8 bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred
57. 24 Set the signaling method of the EINT22 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN21 23 Filter Enable for EINT21 0 Disable 1 Enable EINT21 22 20 Set the signaling method of the EINT21 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN20 19 Filter Enable for EINT20 0 Disable 1 Enable EINT20 18 16 Set the signaling method of the EINT20 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN19 15 Filter Enable for EINT19 0 Disable 1 Enable EINT19 14 12 Set the signaling method of the EINT19 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN18 Filter Enable for EINT18 0 Disable 1 Enable EINT18 10 8 Set the signaling method of the EINT18 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN17 Filter Enable for EINT17 0 Disable 1 Enable EINT17 6 4 Set the signaling method of the EINT17 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN16 Filter Enable for EINT16 0 Disable 1 Enable EINT16 2 0 Set the signaling method of the EINT16 000 Low level 001 High level 01x F
58. 48Mhz for USB UCLK does not fed until the PLL UPLL is configured Condition UCLK State UPLL State After reset or EXTCLK UPLL is turned off by CLKSLOW register or EXTCLK After configuring UPLL L during PLL lock time On 48Mhz after PLL lock time UPLL is turned on by CLKSLOW register 48Mhz ELECTRONICS 7 7 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR FCLK HCLK and PCLK FCLK is used by ARM920T HCLK is used for AHB bus which is used by the ARM920T the memory controller the interrupt controller the LCD controller the DMA and the USB host block PCLK is used for APB bus which is used by the peripherals such as WDT IIS I2C PWM timer MMC interface ADC UART GPIO RTC and SPI The S3C2410X01 supports selection of Dividing Ratio between and PCLK This ratio is determined by HDIVN and PDIVN of CLKDIVN control register HDIVN PDIVN DivideRatio Ratio p E FCLK 2 2 E 12 xo 2 2 2 2 _ 14 _ 2 4 recommended After setting PMS value it is required to set CLKDIVN register The setting value of CLKDIVN will be valid after PLL lock time The value is also available for reset and changing Power Management Mode The setting value can also be valid after 1 5 HCLK Only 1HCLK can validate the value of CLKDIVN register changed from Default 1 1 1 to other
59. 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values INSTRUCTION CYCLE TIMES MULL takes 15 m 1 l and MLAL 15 m 2 I cycles to execute where m is the number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed INSTRUCTIONS SMULL SMLAL e If bits 31 8 of the multiplier operand are all zero or all one e If bits 31 16 of the multiplier operand are all zero or all one e If bits 31 24 of the multiplier operand are all zero or all one e Inall other cases For Unsigned Instructions UMULL UMLAL e If bits 31 8 of the multiplier operand are all zero e If bits 31 16 of the multiplier operand are all zero e If bits 31 24 of the multiplier operand are all zero e Inall other cases S and are defined as sequential S cycle and internal I cycle respectively 3 26 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions Mnemonic _____ Description Purpose UMULL cond S RdLo RdHi Rm Rs Unsigned Multiply Long 32 x 32 64 UMLAL cond S RdLo RdHi Rm Rs Unsigned Multiply amp Accumulate Long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed Multiply Long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed Multiply amp Ac
60. Baud Rate Generation Each UART s baud rate generator provides the serial clock for the transmitter and the receiver The source clock for the baud rate generator can be selected with the S3C2410X01 s internal system clock or UCLK In other words dividend is selectable by setting Clock Selection of UCONn The baud rate clock is generated by dividing the source clock PCLK or UCLK by 16 and a 16 bit divisor specified in the UART baud rate divisor register UBRDIVn The UBRDIVn can be determined by the following expression UBRDIVn in PCLK bps 16 1 Where the divisor should be from 1 to 216 1 For accurate UART operation the S3C2410X01 also supports UCLK as a dividend If the S3C2410X01 uses UCLK which is supplied by an external UART device or system then the serial clock of UART is exactly synchronized with UCLK So the user can get the more precise UART operation The UBRDIVn can be determined UBRDIVn int UCLK bps x 16 1 Where the divisor should be from 1 to 25 1 and UCLK should be smaller than PCLK For example if the baud rate is 115200 bps and PCLK or UCLK is 40 MHz UBRDIVn is determined UBRDIVn int 40000000 115200 x 16 1 int 21 7 1 21 1 20 Loopback Mode The S3C2410X01 UART provides atest mode referred to as the Loopback mode to aid in isolating faults in the communication link This mode structurally enables the connection of RXD and TXD in the UART In this mode therefore transmi
61. Cache hits should never occur 2 Non cached buffered NCB Reads and writes are not cached and always perform accesses on the ASB Cache hits should never occur Writes are placed in the write buffer and will appear on the ASB The CPU continues execution as soon as the write is placed in the write buffer Reads may be externally aborted Writes can not be externally aborted Cached write through mode WT Reads which hit in the cache will read the data from the cache and do not perform an access on the ASB Reads which miss in the cache cause a linefill All writes are placed in the write buffer and will appear on the ASB The CPU continues execution as soon as the write is placed in the write buffer Writes which hit in the cache update the cache Writes cannot be externally aborted Cached write back mode WB Reads which hit in the cache will read the data from the cache and do not perform an ASB access Reads which miss in the cache cause a linefill Writes which miss in the cache are placed in the write buffer and will appear on the ASB The CPU continues execution as soon as the write is placed in the write buffer Writes which hit in the cache update the cache and mark the appropriate half of the cache line as dirty and do not cause an ASB access Cache write backs are buffered Writes Cache write misses and cache write backs cannot be externally aborted NOTES 1 The control register C bit Ccr being z
62. DATA DATAO S3C2410 generates 512 Byte ECC Parity Code during Write Read operation ECC Parity Code consists of Bytes per 512 Byte data 24 bit ECC Parity Code 18 bit Line parity 6 bit Column Parity ECC generator block executes the followings 1 When MCU writes data to NAND the ECC generator block generates ECC code 2 When MCU reads data from NAND the ECC generator block generates ECC code and compares it with pre written ECC code 6 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR NAND FLASH MEMORY MAPPING ELECTRONICS OxFFFF_FFFF 0x6000_0000 0x4800_0000 0x4000_OFFF 0x4000_0000 0x3800_0000 0x3000_0000 0x2800_0000 0x2000_0000 0x1800_0000 0x1000_0000 0x0800_0000 0x0000_0000 NAND FLASH CONTROLLER Not Used Not Used SFR Area SFR Area BootSRAM 4KBytes Not Used SDRAM BANK7 nGCS7 SDRAM BANK7 nGCS7 SDRAM BANK6 nGCS6 SDRAM BANK6 nGCS6 SROM 5 nGCS5 SROM 5 nGCS5 SROM BANK4 nGCS4 SROM BANK4 nGCS4 SROM nGCS3 SROM nGCS3 SROM BANK2 nGCS2 SROM BANK2 nGCS2 SROM BANK1 nGCS1 SROM BANK1 nGCS1 SROM BANKO nGCSO BootSRAM 4KBytes 0 01 10 OM 1 0 00 a Not using NAND flash for b Using NAND flash booting ROM This document is a
63. DCLK1DIV 1 Reewd DCLK1SelCK 17 Select DCLK1 source clock 0 POLK 1 UCLK USB DCLK1EN 16 DCLK1 Enable 0 Disable 1 Enable Reserved 15 12 0000b DCLKOCMP 11 8 DCLKO Compare value clock toggle value lt DCLKODIV If the DCLKODIV is n Low level duration is 1 High level duration is DCLKODIV 1 1 DCLKODIV 7 4 DCLKO Divide value DCLKO frequency source clock DCLKODIV 1 Reserved jm DCLKOSeICK 1 Select DCLKO source clock 0 PCLK 1 UCLK USB DCLKOEN DCLKO Enable 0 Disable 1 Enable DCLKnCMP 1 DCLKnDIV 1 9 22 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS External Interrupt Control Register EXTINTn The 24 external interrupts can be requested by various signaling methods The EXTINTn configures the signaling method between the level trigger and edge trigger for the external interrupt request and also configures the signal polarity To recognize the level interrupt the valid logic level on EXTINTn pin must be retained at least for 40ns because of the noise filter EINT 15 0 EXTINTO 0x56000088 External interrupt control register 0 EINT7 30 28 Set the signaling method of the EINT7 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT6 26 24 Set the signaling method of the EINT6 000 Low level 001 High level 01x Falling edge trigge
64. Divide Ratio 1 1 2 1 2 2 and 1 2 4 FCLK CLKDIVN 0x00000000 HCLK PCLK Figure 7 6 Changing CLKDIVN Register Value NOTES 1 CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK 2 If HDIVN 1 the CPU bus mode has to be the asynchronous bus mode using following instructions MMU_SetAsyncBusMode pl5 0 r0 cl c0 0 orr 0 1 iA mcr pl5 0 r0 cl c0 0 7 8 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT POWER MANAGEMENT The power management block controls the system clocks by software for the reduction of power consumption in the S3C2410X01 These schemes are related to PLL clock control logics HCLK and PCLK and wakeup signals Figure 7 7 shows the clock distribution of the S3C2410X01 The S3C2410X01 has five power down modes The following section describes each power management mode The transition between the modes is not allowed freely For available transitions among the modes see Figure 7 8 Clock Control Register FCLK HCLK PCLK UCLK 48M Input Clock FCLK definition If SLOW mode FCLK z input clock divider ratio If NORMAL mode P M amp S value MPLL clock Figure 7 7 The Clock Distribution Bl
65. Figure 15 2 Monochrome Display Types STN This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 11 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR VD3 VD2 VD1 00 03 VD2 VD1 1 Pixel VD7 06 VD5 VD4 VD7 VD6 VD5 VD4 4 bit Dual Scan Display 1 Pixel 4 bit Single Scan Display VD7 06 VD5 VD4 VD3 VD2 VD1 VDO 1 G1 B1 R2 G2 B2 R3 G3 1 Pixel 8 bit Single Scan Display Figure 15 3 Color Display Types STN 15 12 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD 7 0 signal VCLK signal is used to clock the data into the LCD driver s shift register After each horizontal line of data has been shifted into the LCD driver s shift register the VLINE signal is asserted to display the line on the panel The VM signal provides an AC signal for the display The LCD uses the signal to alternate the polarity of the row and column voltages which are used to turn the pixels on and off because the LCD plasma tends to deteriorate whenever subjected to a DC voltage It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals Figure 15 4 shows
66. GPBDAT 0x56000014 The data register for port B Undefined 0x0 GPBCON GPB10 GPB9 GPB8 2 8 GPB7 NB ANN GPB6 GPB5 1 0 00 Input 10 NXDREQO 00 Input 10 nXDACKO 00 Input 10 nXDREQ1 00 Input 10 nXDACK1 00 Input 10 nXBREQ 00 Input 10 NXBACK 00 Input 10 TCLKO 00 Input 10 TOUT3 00 Input 10 TOUT2 00 Input 10 TOUT1 00 Input 10 TOUTO Description 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved Undefined When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read 9 10 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PORTS PORT C CONTROL REGISTERS GPCCON GPCDAT and GPCUP GPCCON 0x56000020 Configure the pins of port C 0 GPCUP 0x56000028 Pull up disable register for port C 0x0 GPCDAT 0x56000024 The data register for por
67. LCD BUS LCD Controller Controller Arbitration DMA 4ch EEE P SDI P_UAR EE Figure 7 1 Clock Generator Block Diagram ELECTRONICS 7 3 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR PHASE LOCKED LOOP PLL The MPLL within the clock generator as a circuit synchronizes an output signal with a reference input signal in frequency and phase In this application it includes the following basic blocks as shown in Figure 7 2 the Voltage Controlled Oscillator VCO to generate the output frequency proportional to input DC voltage the divider P to divide the input frequency Fin by p the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector PFD the divider S to divide the VCO output frequency by s which is Mpll the output frequency from MPLL block the phase difference detector the charge pump and the loop filter The output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation Mpll m Fin p 2 m M the value for divider M 8 p P the value for divider P 2 The UPLL within the clock generator is the same as the MPLL in every aspect The following sections describe the operation of the PLL including the phase difference detector the charge pump the Voltage controlled oscillator VCO and the loop filter Phase Difference Detector PFD The PFD monitors the phase difference
68. LCD line PAGEWIDTH 10 0 Virtual screen page width the number of half words 000000000 This value defines the width of the view port in the frame Note The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0 Example 1 LCD panel 320 240 16gray single scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0x80000 0x50 0x200 Oxef 1 Oxa2b00 Example 2 LCD panel 320 240 16gray dual scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 120 1 0x77 PAGEWIDTH 320 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0x80000 0x50 0x200 0x77 1 0x91580 Example 3 LCD panel 320 240 color single scan Frame start address 0x0c500000 Offset dot number 1024 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 8 16 0xa0 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0 80000 0xa0 0x200 Oxef 1 0xa7600 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing w
69. MEMORY CONTROLLER 3C2410X01 RISC MICROPROCESSOR SDRAM Memory Interface Examples Figure 5 11 Memory Interface with 16 bit SDRAM 4Mx16 2ea 4banks Note Refer to Table 5 2 for the Bank Address configurations of SDRAM 5 10 ELECTRONICS MEMORY CONTROLLER 2 cycles 2 cycles Tcoh 1 cycle Tacp Tcah 3 cycles oo gt gt 88 FE Tacc 5 11 53 2410 01 RISC MICROPROCESSOR PROGRAMMABLE ACCESS CYCLE Figure 5 12 S3C2410X01 nGCS Timing Diagram ELECTRONICS 3C2410X01 RISC MICROPROCESSOR MEMORY CONTROLLER Cb B B mE B E 1 CL 3 CL 2 Read Bank Precharge 2 cycle Tcas 2 cycle Tcp 2 cycle 2 cycle Trp Tred Figure 5 13 S3C2410X01 SDRAM Timing Diagram ELECTRONICS 5 12 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER BUS WIDTH amp WAIT CONTROL REGISTER BWSCON Reset Value BWSCON 0x48000000 Bus width amp wait status control register 0x000000 swscon sm Desevipon riasan ST7 31 Determine SRAM for using UB LB for bank 7 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS7 30 Determine WAIT status for bank 7 0 WAIT disable 1 WAIT enable DW7 29 28 Determine data bus width for bank 7 00 8 bit 01 16 bit 10 32 bit 11 reserved ST6 27 Determine SRAM for us
70. Port Configuration Porta Selectable Pin Functions Output only ADDR26 Output only ADDR23 GPA2 Output only ADDR17 Gmo Outputony Amm 9 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS Table 9 1 S3C2410 Port Configuration Continued er out oo Gm mw mona gt Ger rom ee p ned oe cms ne Input output ams om Gee mor Toug em cmo mw gt Selectable Pin Functions Input output are vos gt a imot ve an imot we gt amm mot we vi gt mw gt Gm wo ig e wo i gt gt eros mw xw wo mw gt ver gt gt um gt ELECTRONICS 9 3 PORTS 53 2410 01 RISC MICROPROCESSOR Table 9 1 S3C2410 Port Configuration Continued PotD Input output VD23 550 vo ner gt omi mo vo Gmi mo wo GP mo ve gt gt ew mas wa Input output VD17
71. R14 53 2410 RISC MICROPROCESSOR Unstack 3 registers Save all registers R15 SP CPSR unchanged R15 SP CPSR SPSR mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SP RO R3 R14 BL somewhere LDMED SP RO R3 R15 3 46 Save RO to R3 to use as workspace and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 Lu po m we ow 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory manager is warned to treat them as inseparable This cl
72. RFLast not received yet 1 Last data ready Rx FIFO Full Set to 1 whenever Rx FIFO is full RFFull 0 0 lt lt 63 1 Full 64byte Rx FIFO Half Full Set to 1 whenever Rx FIFO more than 31byte RFHalf 0 0 lt Rx FIFO lt 31 32 lt Rx FIFO lt 64 FIFO Count 6 0 Number of data byte in 0000000 FFCNT SDI Data SDIDAT Register w Reset Value SDIDAT 0x5A00003C Li W Bi W SDI data register 0x5A00003F Bi B SDIDAT initial State Data Register 31 This field contains the data to be transmitted or received over the 0x00000000 SDI channel Access by Word Byte unit when endian mode is Little ine Access by Word unit when endian mode is Big Bi B Access by Byte unit when endian mode is Big ELECTRONICS 19 9 SD HOST CONTROLLER 3C2410X01 RISC MICROPROCESSOR SDI Interrupt Mask SDIIMSK Register Register Address R W Description Reset Value SDIIMSK 0x5A000040 SDI interrupt mask register 0 0 SDIMSK RspCrc Interrupt 17 Response CRC error interrupt he MEM 0 disable 1 interrupt enable CmdSent Interrupt 16 Command sent without response interrupt Enable 0 disable 1 interrupt enable CmdTout Interrupt 15 Command response timeout interrupt luc aD 0 disable 1 interrupt enable RspEnd Interrupt 14 Command response received interrupt Enable 0 disable 1 interrupt enable RWaitReq I
73. Register If bitO of Rn 1 subsequent instructions decoded as THUMB instructions If bit of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute where S and N are defined as sequential S cycle and non sequential N cycle respectively ASSEMBLER SYNTAX BX branch and exchange BX cond Rn cond Two character condition mnemonic See Table 3 2 Rn is an expression evaluating to a valid register number USING R15 AS AN OPERAND If R15 is used as an operand the behavior is undefined ELECTRONICS 3 5 ARM INSTRUCTION SET Examples 3 6 ADR RO Into_THUMB 1 BX RO CODE16 Into THUMB ADR R65 Back ARM BX R5 ALIGN CODE32 Back to ARM 53 2410 RISC MICROPROCESSOR Generate branch target address and set bit 0 high hence arrive in THUMB state Branch and change to THUMB state Assemble subsequent code as THUMB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state Branch and change back to ARM state Word align Assemble subsequent code as ARM instructions ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instructio
74. SCL period 3 Set IICSTAT to enable Serial Output START Master Tx mode has been configured Write slave address to IICDS l Write OxFO M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Stop ii Write new data Write OxDO Stop transmitted to IICDS to IICSTAT I 1 Clear pending bit to resume l l The data of the IICDS is Wait until the stop shifted to SDA condition takes effect Clear pending bit END Figure 20 6 Operations for Master Transmitter Mode ELECTRONICS 20 7 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR START Master Rx mode has been configured Write slave address to IICDS Write OxBO M R Start to IICSTAT I The data of the IICDS slave address is transmitted ACK period and then interrupt is pending Read a new data from Write 0x90 M R Stop IICDS to IICSTAT I Clear pending bit to resume SDA is shifted to IICDS condition takes effect Clear pending bit END Figure 20 7 Operations for Master Receiver Mode 20 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE START Slave Tx mode has been configured detects
75. SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount Rs can be any general register other than R15 If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted result will exactly match that of an instruction specified shift with the same value and shift operation If the value in the byte is 32 or more the result will be a logical extension of the shift described above LSL by 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm NO a e O DD gt ROR by n where n is greater than 32 will give the same result and carry out as ROR by n 32 therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above NOTES The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 15 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR IMMEDIATE O
76. SMALL PAGE REFERENCES Figure 3 8 illustrates the complete translation sequence for a 4KB small page If a small page descriptor is included in a fine page table the upper two bits of the page index and low order two bits of the fine page table index overlap Each fine page table entry for a small page must therefore be duplicated four times Modified virtual address 20 19 12 11 8 7 Translation table base 31 14 13 Translation base SS 18 14 13 Translation base Table index T B Level one descriptor 109 8 54321 31 109 210 Coarse page table base address L2 table index Level two descriptor 1211109 8 7 65 43 2 1 oo e ee E Physical address 31 12 11 0 Figure 3 8 Small Page Translation from a Coarse Page Table 3 14 ELECTRONICS ARM920T PROCESSOR MMU TRANSLATING TINY PAGE REFERENCES Figure 3 9 on page 3 16 illustrates the complete translation sequence for a 1KB tiny page Page translation involves one additional step beyond that of a section translation the level one descriptor is the fine page table descriptor and this is used to point to the level one descriptor NOTES The domain specified in the level one description and access permissions specified in the level one description together determine whether the access has permissions to proceed See section Domain access control on page 3 19 for details ELECTRONICS 3 15 MMU ARM920T PROCESSOR Modified virt
77. Status SDIDSTA Register Reset Value SDIDSTA 0x5A000034 R W SDI data status register SDIDSTA Read Wait Request Occur RWaitReq SDIO Interrupt Detect IOlntDet FIFO Fail error FFfail CRC Status Fail CrcSta Data Receive CRC Fail DatCrc Data Time Out DatTout Data Transfer Finish DatFin Busy Finish BusyFin Start Bit Error SbitErr Tx Data progress On TxDatOn Rx Data Progress On RxDatOn 19 8 Bit pescription 10 Read wait request signal transmits to SD card The request signal is stopped and this flag is cleared by setting one to this bit for SDIO 0 not occur 1 Read wait request occur SDIO interrupt detects This flag is cleared by setting one to this bit for SDIO 0 not detect 1 SDIO interrupt detect FIFO fail error when FIFO occurs overrun underrun misaligned data saving This flag is cleared by setting one to this bit 0 not detect 1 FIFO fail CRC Status error when data block sent CRC check failed returned from card This flag is cleared by setting one to this bit 0 not detect 1 status fail Data block received error CRC check failed calculated by host This flag is cleared by setting one to this bit 0 not detect 1 receive crc fail Data Busy receive timeout This flag is cleared by setting one to this bit 0 not detect 1 timeout Data transfer completes data counter is zero This flag is cleared
78. UCLK 1 UART clock signal AIN 7 0 ADC input 7 0 Vref ADC Vref IIC Bus IICSDA IO IIC bus data IICSCL IIC bus clock 79 1 20 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 S3C2410 Signal Descriptions Continued I2SLRCK 0 IIS bus channel select clock I2SSDO IIS bus serial data output I2SSDI EUN IIS bus serial data input I2SSCLK IO IIS bus serial clock CDCLK CODEC system clock nXPON Plus X axis on off control signal XMON Minus X axis on off control signal nYPON Plus Y axis on off control signal YMON Minus Y axis on off control signal TES br pco e e SPIMISO 1 0 SPIMISO is the master data input line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role When SPI is configured as a slave these pins reverse its role 5810 C SODATISO GPn 116 0 10 General inpuloutput ports some pors are ouputonly SPIMOSI 1 0 ELECTRONICS 1 21 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 2 S3C2410 Signal Descriptions Continued Signal vo Despon JTAG TEST LOGIC nTRST nTRST TAP Controller Reset resets the TAP controller at start If debugger is used A 10K pull up resistor has to be connected If debugger black ICE is not used nTRST pin must be at L or low active pulse ER TAP Controller Mode Select controls the sequenc
79. Unconditional branch Long branch with link 15 14 13 12 11 10 9 Figure 4 1 THUMB Instruction Set Formats 4 2 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET OPCODE SUMMARY The following table summarizes the THUMB instruction set For further information about a particular instruction please refer to the sections listed in the right most column Table 4 1 THUMB Instruction Set Opcodes Lo Register Hi Register Condition Operand Operand Codes Set ADD Add AND AND branch EOR EOR Load multiple Lm ma v gt ze lt lt lt lt ELECTRONICS 4 3 THUMB INSTRUCTION SET S3C2410X RISC MICROPROCESSOR Table 4 1 THUMB Instruction Set Opcodes Continued Lo Register Hi Register Condition B Set PUSH Push register Y mo ote av Subtract with Carry STA Sere mate sm smwws wh ste v s sa me gt 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 condition codes are unaffected by the format 5 version of this instruction 4 4 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 1 MOVE SHIFTED REGISTER 15 14 13 12 11 10 6 5 3 2 0 2 0 Destination Register 5 3 Source Register 10 6 Immediate Vale 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 4 2 Format 1 OPERATI
80. Write Count Register1 will be loaded in this register automatically In case of INDMA mode the MCU should set proper value by software Register Address Description Reset Value 9T EP1 DMA FIFO 0x52000208 R W DMA transfer FIFO counter base register 0x00 0x5200020B EP2 DMA FIFO 0x52000220 L EP2 DMA transfer FIFO counter base register 0x00 0x52000223 B e EP3 DMA FIFO 0x52000248 L RAW EP3 DMA transfer FIFO counter base register 0x00 0x5200024B 4 DMA FIFO 0x52000260 EP4 DMA transfer FIFO counter base register 0x00 0x52000263 ud UJ Un EPn_FIFO_CNT 7 0 RW EP DMA transfer FIFO counter value ELECTRONICS 13 23 USB DEVICE 53 2410 01 RISC MICROPROCESSOR DMA TOTAL TRANSFER COUNTER REGISTER EPN_DMA_TTC_L M H This register should have total number of bytes to be transferred using DMA total 20 bit counter Register Address Description Reset Value BN DMA total transfer counter lower byte EP1 DMA total transfer counter middle byte 0x00 EP1 DMA TTC L 0x5200020C 0x5200020F TTC 0 52000210 0x52000213 EP1 TTC H 0 52000214 R W EP1 DMA total transfer counter higher byte 0x00 0x52000217 EE p or EP2 TTC L 0 52000224 EP2 DMA total transfer counter lower byte 0x00 0x52000227 EP2 TTC 0 52000228 EP2 total transfer counter middle byte 0x00 0x5200022B
81. a lookup This will miss and a linefill will be performed loading the cache line into the entry specified by the replacement counter Once all the instructions have been loaded they are then locked by writing to CP15 register 9 to set the replacement counter base to be one higher than the number of locked cache lines See Data cache lockdown on page 4 9 for a more complete explanation of cache locking 4 4 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER DATA CACHE AND WRITE BUFFER The ARM920T includes a 16KB data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance The DCache has 512 lines of 32 bytes 8 words arranged as a 64 way set associative cache and uses virtual addresses from the ARM9TDMI CPU core The write buffer can hold up to 16 words of data and 4 separate addresses The operation of the data cache and write buffer are intimately connected The DCache supports write through WT and writeback WB memory regions controlled by the C and B bits in each section and page descriptor within the MMU translation tables For clarity these bits are referred to as Ctt and Bit in the following text For details see Data cache and write buffer operation on page 4 6 Each DCache line has two dirty bits one for the first 4 words of the line the other for the last 4 words and a single virtual TAG address and valid bit for the entire 8 word line The physical address from which e
82. a possible error if the operands were 2 s complement signed The C flag will be set to the carry out of bit 31 of the ALU the Z flag will be set if and only if the result was zero and the N flag will be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 11 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR SHIFTS When the second operand is specified to be a shifted register the operation of the barrel shifter is controlled by the Shift field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may be contained in an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 11 Tlf 6 5 Shift type 6 5 Shift type 00 logical left 01 logical right 00 logical left 01 logical right 10 arithmetic right 11 rotate right 10 arithmetic right 11 rotate right 11 7 Shift amount 11 8 Shift register 5 bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left LSL takes th
83. amp COMPARE BUFFER REGISTER TCNTB3 TCMPB3 TCNTB3 0 51000030 R W Timer count buffer register 0x00000000 TCMPB3 0x51000034 Timer 3 campare buffer register 0x00000000 Timer 3 compare buffer register 15 0 Set compare buffer value for Timer 3 0x00000000 15 0 Set count buffer value for Timer 3 0x00000000 TCNTB3 Timer 3 count buffer register TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 Register Reset Value TCNTO3 0 5100003 Timer 3 count observation register 0x00000000 Timer 3 observation register 15 0 Set count observation value for Timer 3 0x00000000 10 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR m D TIMER 4 COUNT BUFFER REGISTER TCNTB4 TCNTB4 0x5100003C R W Timer 4 count buffer register 0x00000000 Timer 4 count buffer register 15 0 Set count buffer value for Timer 4 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 TCNTO4 0 51000040 R 4 count observation register 0x00000000 Timer 4 observation register 15 0 Set count observation value for Timer 4 0x00000000 ELECTRONICS 10 19 PWM TIMER S3C2410X01 RISC MICROPROCESSOR NOTES 10 20 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART 05 20 2002 1 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER Preliminary OVERVIEW The S3C2410X01 Universal Asynchronous Receiver and Transmitter UART provides three independent asynchronous serial I O SIO ports each of which can opera
84. an external crystal or an external clock EXTCLK The clock generator includes an oscillator Oscillation Amplifier which is connected to an external crystal and also has two PLLs Phase Locked Loop which generate the high frequency clock required in the S3C2410X01 CLOCK SOURCE SELECTION Table 7 1 shows the relationship between the combination of mode control pins OM3 and OM2 and the selection of source clock for the S3C2410X01 The OM 3 2 status is latched internally by referring the and OM pins at the rising edge of nRESET Table 7 1 Clock source selection at boot up Mode ON 3 2 MPLL state UPLL state Main Clock source USB Clock source NOTES 1 Although the MPLL starts just after a reset the MPLL output Mpll is not used as the system clock until the software writes valid settings to the MPLLCON register Before this valid setting the clock from external crystal or EXTCLK source will be used as the system clock directly Even if the user does not want to change the default value of MPLLCON register the user should write the same value into MPLLCON register 2 ON 32 is used to determine a test mode when OM 1 0 is 11 7 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT EXTCLK i CLKOUT POWER Ju ARM920T PCLK USB Nand Flash MEMORY INTERRUPT Host I F Controller Controller Controller Pa i USB O O o T H
85. and 4 7 0 These 8 bits determine prescaler value for Timer 0 and 1 ELECTRONICS 10 11 PWM TIMER S3C2410X01 RISC MICROPROCESSOR TIMER CONFIGURATION REGISTER1 TCFG1 TCFG1 0x51000004 5 MUX amp DMA mode selecton register 0x00000000 00000 DMA mode 23 20 Select DMA request channel 0000 0000 No select all interrupt 0001 0010 Timer1 0011 Timer2 0100 Timer3 0101 Timer4 0110 Reserved MUX 4 19 16 Select MUX input for PWM Timer4 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 MUX 3 15 12 Select MUX input for PWM Timers 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 MUX 2 11 8 Select MUX input for PWM Timer2 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 MUX 1 7 4 Select MUX input for PWM Timer1 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLKO MUX 0 3 0 Select MUX input for PWM 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 1 External TCLKO 10 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER TIMER CONTROL TCON REGISTER TCON 0x51000008 R W Timer control register 0x00000000 Bit Description Initial state Timer 4 auto reload on off 22 Determine auto reload on off for Timer 4 0 One shot 1 Interval mode auto reload Timer 4 manual update note 21 Determine the manual update for Timer 4 0 operation 1 Update TCNTB4
86. and CLKVAL 9 0 0000000000 STN VCLK HCLK CLKVAL x 2 CLKVAL gt 2 TFT VCLK HCLK CLKVAL 1 x2 CLKVAL 20 MMODE 7 Determine the toggle rate of the VM 0 Each Frame 1 The rate defined by the MVAL PNRMODE 6 5 Select the display mode 00 4 bit dual scan display mode STN 01 4 bit single scan display mode STN 10 8 bit single scan display mode STN 11 TFT LCD panel BPPMODE 4 1 Select the BPP Bits Per Pixel mode 0000 1 bpp for STN Monochrome mode 0001 2 bpp for STN 4 level gray mode 0010 4 bpp for STN 16 level gray mode 0011 8 bpp for STN color mode 0100 12 bpp for STN color mode 1000 1 bpp for TFT 1001 2 bpp for TFT 1010 4 bpp for TFT 1011 8 bpp for TFT 1100 16 bpp for TFT 1101 24 bpp for TFT ENVID LCD video output and the logic enable disable 0 Disable the video output and the LCD control signal 1 Enable the video output and the LCD control signal 15 26 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 LCD Control 2 Register LCDCON2 0X4D000004 LCD control 2 register 0x00000000 VBPD 31 24 TFT Vertical back porch is the number of inactive lines at the start 0x00 of a frame after vertical synchronization period STN These bits should be set to zero on STN LCD LINEVAL 23 14 TFT STN These bits determine the vertical size of LCD panel 0000000000 VFPD 13 6 TFT Vertical front porch is the number of ina
87. base address Rb and store bits 0 15 of Rd at the resulting address LDRH Rd Rb LDRH Rd Rb Add 1 to base address Rb Load bits 0 15 from the resulting address into Rd and Set bits 16 31 to zero NOTE is a full 6 bit address but must be halfword aligned ie with bit O set to 0 since the assembler places gt gt 1 in the field 4 24 ELECTRONICS 53 2410 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES THUMB INSTRUCTION SET All instructions in this format have an equivalent ARM instruction as shown in Table 4 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R6 R1 56 LDRH R4 R7 4 ELECTRONICS Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28 as the Offset5 value Load into R4 the halfword found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value 4 25 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 11 SP RELATIVE LOAD STORE 15 14 13 10 8__7 D 12 11 we O 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 12 Format 11 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in
88. between Fref and Fvco and generates a control signal tracking signal when it detects a difference The Fref means the reference frequency as shown in the Figure 7 2 Charge Pump PUMP The charge pump converts PFD control signals into a proportional charge in voltage across the external filter that drives the VCO Loop Filter The control signal which the PFD generates for the charge pump may generate large excursions ripples each time the Fvco is compared to the Fref To avoid overloading the VCO a low pass filter samples and filters the high frequency components out of the control signal The filter is typically a single pole RC filter with a resistor and a capacitor Voltage Controlled Oscillator VCO The output voltage from the loop filter drives the VCO causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage When the Fvco matches Fref in terms of frequency as well as phase the PFD stops sending control signals to the charge pump which in turn stabilizes the input voltage to the loop filter The VCO frequency then remains constant and the PLL remains fixed onto the system clock Usual Conditions for PLL amp Clock Generator PLL amp Clock Generator generally use the following conditions Loop filter capacitance External X tal frequency 6 20 Mhz External capacitance used for X tal 15 22 pF The value could be changed FCLK must be more than three times
89. byte address of most significant byte Figure 2 1 Big Endian Addresses of Bytes within Words LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 Higher Address Word Address Lower Address significant byte is at lowest address Word is addressed by byte address of least significant byte Figure 2 2 Little Endian Addresses of Bytes within Words INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state Data Types ARM920T supports byte 8 bit halfword 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries 2 2 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL OPERATING MODES ARM920T supports seven modes of operation e User usr The normal ARM program execution state Designed to support a data transfer or channel process irq Used for general purpose interrupt handling Supervisor svc Protected mode for the operating system e Abort mode abt Entered after a data or instruction prefetch abort System sys A privileged user mode for the operating system e Undefined und Entered when an undefined instruction is executed Mode chan
90. company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 16 1 A D CONVERTER AND TOUCH SCREEN 3C2410X01 RISC MICROPROCESSOR ADC amp TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16 1 shows the functional block diagram of the S3C2410X01 A D converter and Touch Screen Interface Note that the A D converter is a recycling type A pull up resister is attached to AIN 7 on VDDA_ADC So XP pad of the touch screen panel should be connected with AIN 7 of the 53 2410 01 and YP pad of the touch screen panel should be connected with one of AIN 5 External Transister Control amp Touch Convert Screen Controller INT ADC Control Generation Waiting for Interrupt Mode INE TE Figure 16 1 ADC and Touch Screen Interface Functional Block Diagram 16 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR A D CONVERTER AND TOUCH SCREEN EXAMPLE FOR TOUCH SCREEN In this example AIN 7 is connected with XP and AIN 5 is connected with YP pad of the touch screen panel To control pads of the touch screen panel XP XM YP and YM four external transistors are applied and control signals including nYPON nXPON and are connected with four external transistors External Transistor External Voltage Source Control S3C2410X01 Figure 16 2 Example of ADC and Touch Screen Interface The following proc
91. display mode the Number of valid VD data line should be 8 LINEVAL Vertical display size 1 In case of single scan display type LINEVAL Vertical display size 2 1 In case of dual scan display type The rate of VCLK signal depends on the configuration of the CLKVAL field in the LCDCON1 register Table 15 1 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 2 VCLK Hz HCLK CLKVAL x 2 The frame rate is the VFRAM signal frequency The frame rate is closely related to the field of WLH 1 0 VLINE pulse width WDLY 1 0 the delay width of after VLINE pulse HOZVAL LINEBLANK and LINEVAL in the LCDCON1 2 3 4 registers as well as VCLK and HCLK Most LCD drivers need their own adequate frame rate The frame rate is calculated as follows frame rate Hz 1 VCLK x HOZVAL 1 1 HCLK x A B LINEBLANK x 8 x LINEVAL 1 A 24 pg 15 4 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 Table 15 1 Relation between VCLK and CLKVAL STN HCLK 60MHz CLKVAL 60MHz X VCLK 1023 60 MHz 2046 29 3 kHz VIDEO OPERATION The S3C2410X01 LCD controller supports 8 bit color mode 256 color mode 12 bit color mode 4096 color mode 4 level gray scale mode 16 level gray scale mode as well as the monochrome mode For the gray or color mode it is required to implement the shades of gray level or color according to time based dithering algorithm and Fram
92. during a linefill locking them into the cache There is a register for each of the ICache and DCache the value of opcode 2 determines which cache register to access opcode 2 0x0 causes the DCache register to be accessed opcode 2 0x1 causes the ICache register to be accessed The Opcode 1 and CRm fields should be zero Reading CP15 register 9 returns the value of the cache lock down register which is the base pointer for all cache segments NOTE Only bits 31 26 are returned Bits 25 0 are unpredictable Writing CP15 register 9 updates the cache lock down register both the base and the current victim pointer for all cache segments Bits 25 0 should be zero The victim counter specifies the cache line to be used as the victim for the next linefill This is incremented using either a random or round robin replacement policy determined by the state of the RR bit in register 1 The victim counter generates values in the range base to 63 This locks lines with index values in the range 0 to base 1 If base 0 there are no locked lines Writing to CP15 register 9 updates the base pointer and the current victim pointer The next linefill will use and then increment the victim pointer The victim pointer will continue incrementing on linefills and will wrap around to the base pointer For example setting the base pointer to Ox3 prevents the victim pointer from selecting entries 0x0 to 0x2 locking them into the cache Load a
93. expression should symbolise 32 bit value of which the most significant four bits are written to the 7 and V flags respectively Key cond Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 lt psr gt CPSR CPSR all SPSR or SPSR all CPSR and CPSR all are synonyms as are SPSR and SPSR all lt psrf gt CPSR flg or SPSR flg lt gt Where this is used the assembler will attempt to generate shifted immediate 8 bit field to match the expression If this is impossible it will give an error EXAMPLES In User mode the instructions behave as follows MSR CPSR_all Rm CPSR 81 28 lt Rm 31 28 MSR CPSR flg Rm CPSR 81 28 lt Rm 31 28 MSR CPSR flg 40xA0000000 CPSR 31 28 lt set N C clear Z V MRS Rd CPSR Rd 31 0 lt CPSR 31 0 In privileged modes the instructions behave as follows MSR CPSR all Rm CPSR 31 0 lt Rm 31 0 MSR CPSR flg Rm CPSR 81 28 Rm 31 28 MSR flg 40x50000000 CPSR 31 28 lt 0x5 set Z V clear MSR SPSR all Rm SPSR lt mode gt 31 0 lt Rm 31 0 MSR SPSR flg Rm SPSR lt mode gt 31 28 Rm 31 28 MSR SPSR flg 0xC0000000 SPSR lt mode gt 31 28 lt OxC set N Z clear C V MRS Rd SPSR Rd 31 0 lt SPSR lt mode gt 31 0 ELECTRONICS 3 21 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA
94. fault enable Data address alignment fault checing 0 Fault checking disabled 1 Fault checking enabled M bit MMU enable 0 MMU disabled 1 MMU enabled Register 1 bits 31 30 select the clocking mode of the ARM920T as shown in Table 2 11 Table 2 11 Clocking Modes Reed 4 po pe ELECTRONICS 2 11 PROGRAMMER S MODEL ARM920T PROCESSOR Enabling the MMU Care must be taken with the address mapping of the code sequence used to enable the MMU see Enabling the MMU on page 3 25 See Instruction cache enable disable on page 4 3 and Data cache and write buffer enable disable on page 4 6 for restrictions and effects of having caches enabled with the MMU disabled REGISTER 2 TRANSLATION TABLE BASE TTB REGISTER This is the translation table base register for the currently active first level translation table The contents of register 2 are shown in Table 2 12 Table 2 12 Register 2 Translation Table Base Register Bits Function 31 14 Pointer to first level translation table base Read write 13 0 Reserved Read Unpredictable Write Should be zero Reading from register 2 returns the pointer to the currently active first level translation table in bits 31 14 Writing to register 2 updates the pointer to the first level translation table from the value in bits 31 14 of the written value Bits 13 0 should be zero when written and are unpredictable when read The following instructions can be
95. for all gray levels are also shown in Table 15 2 In the STN LCD display we should be reminded of one item i e Flicker Noise due to the simultaneous pixel on and off on adjacent frames For example if all pixels on first frame are turned on and all pixels on next frame are turned off the Flicker Noise will be maximized To reduce the Flicker Noise on the screen the average probability of pixel on and off between frames should be the same In order to realize this the Time based Dithering Algorithm which varies the pattern of adjacent pixels on every frame should be used This is explained in detail For the 16 gray level FRC should have the following relationship between gray level and FRC The 15 gray level should always have pixel on and the 14 gray level should have 6 times pixel on and one times pixel off and the 13 gray level should have 4 times pixel on and one times pixel off and the 0 gray level should always have pixel off as shown in Table 15 2 Table 15 2 Dither Duty Cycle Examples Pre dithered Data Duty Cycle Pre dithered Data Duty Cycle gray level number level mee 6 7 4 5 2 5 34 ___ ___ 1 __ 9 2 15 NE ___ 4257 __ 090 _ _ _ This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS
96. handler should return from the interrupt by executing SUBS 14 1 4 Abort An abort indicates that the current memory access cannot be completed It can be signaled by the external ABORT input ARM920T checks for the abort exception during memory access cycles There are two types of abort e Prefetch abort occurs during an instruction prefetch e Data abort occurs during a data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken until the instruction reaches the head of the pipeline If the instruction is not executed for example because a branch occurs while it is in the pipeline the abort does not take place If a data abort occurs the action taken depends on the instruction type e Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this e The swap instruction SWP is aborted as though it had not been executed e Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM instruction The abort mechanism allows the implementation of a dema
97. internal I cycle respectively 3 54 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC Load from memory to coprocessor STC Store from coprocessor to memory L When present perform long transfer N 1 otherwise perform short transfer N 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor cd An expression evaluating to a valid coprocessor register number that is placed in the field lt Address gt can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes 3 A post indexed addressing specification Rn lt expression offset of lt expression gt bytes 1 write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARM920T register number NOTES If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM920T pipelining EXAMPLES LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2
98. interrupt request The TICNT register has an interrupt enable bit and the count value for the interrupt The count value reaches 0 when the tick time interrupt occurs Then the period of interrupt is as follows Period n 1 128 second n Tick time count value 1 127 This RTC time tick may be used for real time operating system RTOS kernel time tick If time tick is generated by the RTC time tick the time related function of RTOS will always synchronized in real time ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register RTCRST The round boundary 30 40 or 50 sec of the second carry generation can be selected and the second value is rounded to zero in the round reset For example when the current time is 23 37 47 and the round boundary is selected to 40 sec the round reset changes the current time to 23 38 00 NOTE All RTC registers have to be accessed for each byte unit using the STRB and LDRB instructions or char type pointer 32 768KHZ X TAL CONNECTION EXAMPLE The Figure 17 2 shows a circuit of the RTC unit oscillation at 32 768Khz 32768Hz Figure 17 2 Main Oscillator Circuit Example ELECTRONICS 17 3 REAL TIME CLOCK S3C2410X01 RISC MICROPROCESSOR REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL RTCCON REGISTER The RTCCON register consists of 4 bits such as the RTCEN which controls the read write enable of the BCD registers CLKSEL CNTS
99. is whether it waits for the deasserted DACK or not In the Handshake mode DMA controller waits for the deasserted DREQ before starting a new transfer If it finds the deasserted DREQ it deasserts DACK and waits for another asserted DREQ In contrast in the Demand mode DMA controller does not wait until the DREQ is deasserted It just deasserts DACK and then starts another transfer if DREQ is asserted We recommend using Handshake mode for external DMA request Sources to prevent unintended starts of new transfers SYNC 30 Select DREQ DACK synchronization 0 DREQ and DACK are synchronized to PCLK APB clock 1 DREQ and DACK are synchronized to HCLK AHB clock Therefore for devices attached to AHB system bus this bit has to be set to 1 while for those attached to APB system it should be set to 0 For the devices attached to external systems the user should select this bit depending on which the external system is synchronized with between AHB system and APB system INT 29 Enable Disable the interrupt setting for CURR TC terminal count 0 CURR interrupt is disabled The user has to view the transfer count in the status register i e polling 1 interrupt request is generated when all the transfer is done i e CURR becomes 0 TSZ 28 Select the transfer size of an atomic transfer i e transfer performed each time DMA owns the bus before releasing the bus 0 aunit transfer is performed 1 a burst transfer of
100. is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 17 3C2410X RISC MICROPROCESSOR ELECTRICAL DATA HASI SOSI 99 2 2 2 Figure 24 18 SDRAM Page Hit Miss READ Timing Trp ELECTRONICS 24 18 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 gt ADDR BA gt A10 AP Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i 1 gt 1 1 1 1 1 Before executing auto self refresh command all banks must be in idle state Figure 24 19 SDRAM Self Refresh Timing Trp 2 Trc 4 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 19 3C2410X RISC MICROPROCESSOR ELECTRICAL DATA lt lt 2 Trcd 2 Figure 24 20 SDRAM Single Write Timing Trp ELECTRONICS 24 20 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 ADDR BA Figure 24 21 SDRAM Page Hit Miss Write Timing Trp 2 Trcdz2 Tcl 2 This document is a preliminary user s manual So our company will present its revision as of the date on
101. line should be eight bits in total The bytes can be unlimitedly sent or received during the bus transfer operation Data is always sent from most significant bit MSB first and every byte should be immediately followed by an acknowledge ACK bit This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 20 1 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR Address Register Comparator IICCON IICSTAT 4 bit Prescaler Shift Register SDA IIC Bus Control Logic Shift Register IICDS Y Data Bus Figure 20 1 IIC Bus Block Diagram 20 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE The S3C2410X01 IIC bus interface has four operation modes Master transmitter mode Master receive mode Slave transmitter mode Slave receive mode Functional relationships among these operating modes are described below START AND STOP CONDITIONS When the IIC bus interface is inactive it is usually in Slave mode In other words the interface should be in Slave mode before detecting a Start condition on the SDA line a Start condition can be initiated with a High to Low transition of the SDA line while the clock signal of SCL is High When the interface state is changed to
102. manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 9 3C2410X RISC MICROPROCESSOR ELECTRICAL DATA HCLK Tacc ADDR nGCSx nWE nBEx Tcos DATA Figure 24 9 ROM SRAM WRITE Timing 1 2 Tcos 2 Tacc 4 Toch 2 2 0 ST 0 Tacs ELECTRONICS 24 10 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 Figure 24 10 ROM SRAM WRITE Timing 11 Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 1 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 11 ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR kc 5 gt Figure 24 11 Masked ROM Single READ Timing Tacs 2 Tcos 2 8 01 10 11 Tpac tRDS ADS RDS ARDS gt x gt 4 gt lt lt gt 4 4 1 RDH C55 tRDH 2 tRDH Figure 24 12 Masked ROM Consecutive READ Timing Tacs 0 Tcos 0 Tacc 3 Tpac 2 PMC 01 10 11 24 12 ELECTRONICS 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 Figure 24 13 SDRAM Single Burst READ Timing Trp 2 Trcdz2 Tcl 2 DW 16bit This document is a preliminary user s
103. nBE 3 0 ELECTRONICS 5 13 MEMORY CONTROLLER S3C2410X01 RISC MICROPROCESSOR BUS WIDTH amp WAIT CONTROL REGISTER BWSCON Continued 10 Determine WAIT status for bank 2 0 WAIT disable 1 WAIT enable data bus width for bank 2 ESAE 8 bit 01 16 bit 10 32 bit 11 reserved 7 Determine SRAM for using UB LB for bank 1 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 ENT WAIT status for bank 1 WAIT disable 1 WAIT enable 5 4 Determine data bus width for bank 1 00 8 bit 01 16 bit 10 32 bit 11 reserved DWO 2 1 Indicate data bus width for bank 0 read only 01 16 bit 10 32 bit The states are selected by OM 1 0 pins fo Note 1 All types of master clock in this memory controller correspond to the bus clock For example HCLK in SRAM is the same as the bus clock and SCLK in SDRAM is also the same as the bus clock In this chapter Memory Controller one clock means one bus clock 2 nBE 3 0 is the AND signal nWBE 3 0 and nOE 5 14 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER BANK CONTROL REGISTER BANKCONn nGCS0 nGCS5 0 48000010 Bank 3 control register 0x0700 BANKCON4 0x48000014 Bank 4 control register 0x0700 5 0 48000018 Bank 5 control register 0x0700 Tacs 14 13 Address set up time before nGCSn 00 0 clock 01 2 1 clock 10 2 2 clo
104. on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 22 1 SPI INTERFACE 53 2410 01 RISC MICROPROCESSOR BLOCK DIAGRAM LSB MSB Tx 8bit Shift Reg 0 MSB LSB Rx 8bit Shift Reg 0 8bit Prescaler 0 Prescaler Register 0 Status Register 0 APB I F 0 INT DMA 0 Pin Control Logic 0 INT 0 INT 1 lt REQO REQ1 lt ACK1 LSB MSB Tx 8bit Shift Reg 1 MSB LSB Rx 8bit Shift Reg 1 SPI Clock PCLK 8bit Prescaler 1 Master gt CPOL Prescaler Register 1 CPHA Pin Control Logic 1 Status Register 1 INTO INT 1 lt APB I F 1 REQO REQ1 lt INT DMA 1 gt Figure 22 1 SPI Block Diagram 22 2 ELECTRONICS 3 2410 01 RISC MICROPROCESSOR SPI INTERFACE 05 20 2002 SPI OPERATION Using the SPI interface the S3C2410X01 send receive 8 bit data simultaneously with an external device serial clock line is synchronized with the two data lines for shifting and sampling of the information When the SPI is the master transmission frequency can be controlled by setting the appropriate bit to SPPREn register You can modify its frequency to adjust the baud rate data register value When the SPI is a slav
105. preliminary user s manual booting ROM Figure 6 4 NAND Flash Memory Mapping 05 25 2002 So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number 6 5 NAND FLASH CONTROLLER 3C2410X01 RISC MICROPROCESSOR SPECIAL FUNCTION REGISTERS NAND FLASH CONFIGURATION NFCONF REGISTER Description Reset Value NFCONF 0x4E000000 NAND Flash configuration Enable Disable NAND Flash controller enable disable 0 Disable NAND Flash Controller 1 Enable NAND Flash Controller After auto boot this bit is cleared to 0 automatically For the access to the NAND flash memory this bit must be set Initialize ECC Initialize ECC decoder encoder 0 Not initialize ECC 1 Initialize ECC 53 2410 supports only 512 Byte ECC checking so it is required to set ECC initialized per 512 Bytes NAND Flash Memory NAND Flash Memory nFCE control chip enable 0 NAND flash nFCE L active 1 NAND flash nFCE inactive After auto boot nCE will be inactive CLE amp ALE duration setting value 0 7 Duration HCLK TACLS 1 TWRPHO 6 4 TWRPHO duration setting value 0 7 pu ES Duration HCLK TWRPHO 1 Reserved Bl 7 TWRPH 1 2 0 TWRPH 1 duration setting value 0 7 Duration HCLK TWRPH1 1 6 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR NAND FLASH CONTROLLER 05 25 2002 NAN
106. publishing we will show the revision with a proper version number ELECTRONICS 22 9 SPI INTERFACE 3C2410X01 RISC MICROPROCESSOR NOTES 22 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR BUS PRIORITIES 05 22 2002 BUS PRIORITIES Preliminary OVERVIEW The bus arbitration logic determines the priorities of bus masters It supports a combination of rotation priority mode and fixed priority mode BUS PRIORITY MAP The S3C2410X01 holds eleven bus masters including DRAM refresh controller LCD DMA DMAO DMA1 DMA2 DMA3 USB HOST DMA EXT BUS MASTER Test interface controller TIC and ARM920T The following list shows the priorities among these bus masters after a reset DRAM refresh controller LCD_DMA DMAO DMA1 DMA2 DMA3 USB host DMA External bus master 9 TIC 10 ARM920T 11 Reserved WD Among those bus masters four DMAs operate under the rotation priority while others run under the fixed priority This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 23 1 BUS PRIORITIES 23 2 NOTES 53 2410 01 RISC MICROPROCESSOR ELECTRONICS S3C2410X RISC MICROPROCESSOR ELECTRICAL DATA 2 4 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS 05 25 2002 Table 24 1 Absolute Maximum Rating Parameter _____ _
107. received This is 0 Fail RspCrc R W cleared by setting one to this bit 0 not detect 1 crc fail Command Sent 11 Command sent not concerned with response This flag is cleared CmdSent R W by setting one to this bit 0 not detect 1 2 command end Command Time 10 Command response timeout 64clk This flag is cleared by setting Out CmdTout R W one to this bit 0 not detect 1 timeout Response Receive Command response received This flag is cleared by setting one 9 End RspFin R W to this bit 0 not detect 1 response end CMD line progress Command transfer in progress On CmdOn 0 not detect 1 in progress Rspindex 7 0 Response index 6bit with start 2bit 8bit R um ELECTRONICS 19 5 SD HOST CONTROLLER 3C2410X01 RISC MICROPROCESSOR SDI Response Register 0 SDIRSPO Register Address R W Description Reset Value SDIRSPO 0x5A000014 SDI response register 0 0 0 SDIRSPO Bit 31 0 Card status 31 0J short card status 127 96 long 0x00000000 SDI Response Register 1 SDIRSP1 RW SDIRSP1 0x5A000018 R SDI response register 1 SDIRSP1 Bit Description Initial Value RCRC7 31 24 CRC7 with end bit short card status 95 88 long 23 0 Unused short card status 87 64 long 0x000000 SDI Response Register 2 SDIRSP2 RW SDIRSP2 0x5A00001C R SDI response register 2 0 0 SDIRSP2 initial Value 31 0 Unused
108. requested 1 Requested LGG 0 Not requested 1 Requested __ INT_ERR2 8 0 requested 1 Requested 0 INT_TXD2 7 0 Not requested 1 Requested 0 INT_RXD2 6 0 Not requested 1 Requested 0 5 0 Not requested 1 Requested INT_TXD1 4 0 Not requested 1 Requested 0 INT_RXD1 3 0 Not requested 1 Requested 0 INT_ERRO 2 0 Not requested 1 Requested 0 INT_TXDO 1 0 Not requested 1 Requested 0 0 Not requested 1 Requestes _____ o 14 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SUB MASK INTSUBMSK REGISTER This register has 11 bits each of which is related to an interrupt source If a specific bit is set to 1 the interrupt request from the corresponding interrupt source is not serviced by the CPU note that even in such a case the corresponding bit of the SUBSRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced Register Address R W Description Reset Value INTSUBMSK 0X4A00001C R W Determine which interrupt source is masked masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked meseved pl 0 Service available 1 Masked M M 0 Service available 1 Masked INTERR B 0 Service available 1 Masked 0 Service available 1 Masked 0 Service a
109. start signal and IICDS receives data compares IICADD and IICDS the received slave address Y The address match interrupt is generated Write data to IICDS Clear pending bit to resume Stop Y The data of the IICDS is shifted to SDA l Interrupt is pending Figure 20 8 Operations for Slave Transmitter Mode ELECTRONICS 20 9 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR START Slave Rx mode has been configured detects start signal and IICDS receives data compares IICADD and IICDS the received slave address Y The address match interrupt is generated I Read data to IICDS Clear pending bit to resume Stop Y SDA is shifted to IICDS I Interrupt is pending Figure 20 9 Operations for Slave Receiver Mode 7 20 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE IIC BUS INTERFACE SPECIAL REGISTERS MULTI MASTER IIC BUS CONTROL IICCON REGISTER IICCON 0x54000000 control register Acknowledge generation 1 7 IIC bus acknowledge enable bit 0 Disable 1 Enable In Tx mode the IICSDA is free in the ack time In Rx mode the IICSDA is L in the ack time Tx clock source selection Source clock of transmit clock prescaler sel
110. the DCache can be pushed out to main memory by cleaning the cache 4 10 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER Situations which necessitate cache cleaning and invalidating include e writing instructions to a cacheable area of memory using STR or STM instructions for example self modifying code JIT compilation copying code from another location downloading code via the EmbeddedICE JTAG debug features updating an exception vector entry e another bus master such as a DMA controller modifying a cacheable area main memory e turning the MMU on or off e changing the virtual to physical mappings in the MMU page tables e turning the ICache or DCache on if its contents are no longer coherent The DCache should be cleaned and both caches invalidated before the cache and write buffer configuration of an area of memory is changed by modifying Ctt or Btt in the MMU translation table descriptor This is not necessary if it is known that the caches cannot contain any entries from the area of memory whose translation table descriptor is being modified Changing the process ID in CP15 register 18 does not change the contents of the cache or memory and does not affect the mapping between cache entries and physical memory locations It only changes the mapping between ARM9TDMI addresses and cache entries This means that changing the process ID does not lead to any coherency issues No cache cleaning or cache inval
111. the alarm enable and the alarm time Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode but only through ALMINT in the normal operation mode RTCALM 0x57000050 L R W RTC alarm control register 0x0 0x57000053 B by byte nl 49 ALMEN Alarm global enable 0 Disable 1 Enable YEAREN 5 Year alarm enable 0 Disable 1 Enable MONREN 4 Month alarm enable 0 Disable 1 Enable HOUREN 2 Hour alarm enable 0 Disable 1 Enable MINEN 1 Minute alarm enable 0 Disable 1 Enable SECEN Second alarm enable 0 Disable 1 Enable DAYEN 3 Day alarm enable 0 Disable 1 Enable ELECTRONICS 17 5 REAL TIME CLOCK S3C2410X01 RISC MICROPROCESSOR ALARM SECOND DATA ALMSEC REGISTER ALMSEC 0x57000054 L R W Alarm second data register 0 0 0x57000057 B by byte n SECDATA 6 4 BCD value for alarm second 0 5 ALARM MIN DATA ALMMIN REGISTER ALMMIN 0x57000058 L R W Alarm minute data register 0x00 0x5700005B B by byte MINDATA 6 4 BCD value for alarm minute BERN 0 5 oom ALARM HOUR DATA ALMHOUR REGISTER ALMHOUR 0x5700005C L R W Alarm hour data register 0x0 0x5700005F B by byte HOURDATA 5 4 BCD value for alarm hour KE 0 2 00 17 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR REAL TIME CLOCK ALARM DATE DATA ALMDATE REGISTER ALMDATE 0x57000060 L R W A
112. the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 21 ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR Table 24 5 Clock Timing Constants Vppp 3 3V Vpp 1 8V 25 C typ 30 External clock to HCLK without PLL HCLK internal to CLKOUT ns S Reset assert time after clock stabilization tRESW 4 or EXTCLK Power on oscillation setting time losc1 4096 XTIpll or EXTCLK 4096 or EXTCLK The interval before CPU runs after nRESET is lRSToRUN or released EXTCLK STOP mode return oscillation setting time tosce 24 22 ELECTRONICS S3C2410X RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 Table 24 6 ROM SRAM Bus Timing Constants Vpp 1 8 V 0 15 V TA 0 to 70 C Vexr 3 3V 0 3V Parameter romernas osy ml ROM SRAM Output enable Delay Daa saime ws 3 we fm ______ ROM SRAM Write Byte Enable Delay ROM SRAM external Wait Setup time ROM SRAM external Wait Hold time Table 24 7 Memory Interface Timing Constants Vpp 1 8 V 0 15 0 to 70 C VExT 3 3V 0 3 _ fm 39 fm Seam o Jos SORA Got sends tm
113. the receiver should send an ACK bit to the transmitter The ACK pulse should occur at the ninth clock of the SCL line Eight clocks are required for the one byte data transfer The master should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse The ACK bit transmit function can be enabled or disabled by software IICSTAT However the ACK pulse on the ninth clock of SCL is required to complete the one byte data transfer operation Clock to Output 1 gt 114 1 4 1 1 1 1 E Data Output by Transmitter Data Output by Receiver SCL from 1 Master 1 Condition Clock Pulse for Acknowledgment Figure 20 5 Acknowledge on the IIC Bus ELECTRONICS 20 5 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR READ WRITE OPERATION In Transmitter mode when the data is transferred the IIC bus interface will wait until IIC bus Data Shift IICDS register receives a new data Before the new data is written into the register the SCL line will be held low and then released after it is written The S3C2410X01 should hold the interrupt to identify the completion of current data transfer After the CPU receives the interrupt request it
114. the sign extended halfword found at the address formed by adding R2 to R4 ELECTRONICS 4 21 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 15 14 13 10 6 5 3 2 0 12 11 ptt pete omes hm gt 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transfer word quantity 1 Transfer byte quantity Figure 4 10 Format 9 4 22 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 4 10 Table 4 10 Summary of Format 9 Instructions STR Rb lmm STR Rd Rb Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address LDR Rb Imm LDR Rb Calculate the source address by adding together the value in Rb and Imm Load Rd from the address STRB Rb lmm STRB Rb Hmm Calculate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address LDRB Rb LDRB Rd Rb lmm Calculate source address by adding together the value in Rb and Imm Load the byte value at the address into Rd NOTE For word accesse
115. the timing requirements for the LCD driver interface This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 13 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR Full Frame Timing MMODE 0 INT_FrSyn MEM VFRAME VM VLINE LINE1 LINE2LINE3LINEALINES LINEG Full Frame Timing MMODE 1 MVAL 0x2 INT_FrSyn 1 VFRAME VM VLINE LINE LINEZLINESLINE4L INES 1 INT_FrSyn First Line Timing 1 VFRAME NE c VM decreases amp 1 1 Display the 1st line VLINE Display the last line of the previous frame 1 1 LINECNT First Line Check amp Data Timing VFRAME WLH VCLK Figure 15 4 8 bit Single Scan Display Type STN LCD Timing 15 14 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver such as VSYNC HSYNC VCLK VDEN and LEND signal These control signals are highly related with the configurations on the LCDCON1 2 3 4 5 registers in the REGBANK Base on these programmable configurations on the LCD control registers in the REGBANK the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers The VSYNC sig
116. this bit to finish the STALL condition 1 The MCU issues a STALL handshake to the USB Set by the MCU if it intends to flush the packet in Input related FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in process the USB waits until the transmission is complete before FIFO flushing If two packets are loaded into the FIFO only first packet The packet is intended to be sent to the host is flushed and the corresponding IN PKT RDY bit is cleared Valid only For Iso mode Set by the USB when in ISO mode an IN token is received and the IN PKT RDY bit is not set The USB sends a zero length data packet for such conditions and the next packet that is loaded into the FIFO is flushed This bit is cleared by writing 0 Set by the MCU after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the MCU sets SEND STALL bit this bit cannot be set ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE IN CSR2 REG 0x52000188 L RAN IN END POINT control status register2 0x20 0x5200018B B byte Description Initial State IN CSR2 REG iu Baj IN_DMA_INT_EN Reserved ELECTRONICS If set whenever th
117. timing control logic unit for LTS350Q1 PD1 or LTS350Q1 PD2 Figure 15 1 LCD Controller Block Diagram The 53 2410 01 LCD controller is used to transfer the video data and to generate the necessary control signals such as VFRAME VLINE VM and so on In addition to the control signals the S3C2410X01 has the data ports for video data which are VD 23 0 as shown in Figure 15 1 The LCD controller consists of a REGBANK LCDCDMA VIDPRCS TIMEGEN and LPC3600 See the Figure 15 1 LCD Controller Block Diagram The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller The LCDCDMA is a dedicated DMA which can transfer the video data in frame memory to LCD driver automatically By using this special DMA the video data can be displayed on the screen without CPU intervention The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD 23 0 data ports to the LCD driver after changing them into a suitable data format for example 4 8 bit single scan or 4 bit dual scan display mode The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers The TIMEGEN block generates VFRAME VLINE VCLK VM and so on The description of data flow is as follows FIFO memory is present in the LCDCDMA When FIFO is empty or partially empty the LCDCDMA requests data fetching f
118. to clear or to sign extend the upper 16 bits A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 ELECTRONICS 3 29 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR memory register LDR from word aligned address memory register LDR from address offset by 2 Figure 3 15 Little Endian Offset Addressing Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register A shift operation is then required to move
119. to interpret the access permission ap bits NOTES Tiny pages do not support sub page permissions and therefore only have one set of access permission bits Bits 31 10 tiny pages 31 12 small pages or bits 31 16 large pages are used to form the corresponding bits of the physical address TRANSLATING LARGE PAGE REFERENCES Figure 3 7 on page 3 13 illustrates the complete translation sequence for a 64KB large page As the upper four bits of the page index and low order four bits of the coarse page table index overlap each coarse page table entry for a large page must be duplicated 16 times in consecutive memory locations in the coarse page table If a large page descriptor is included in a fine page table the upper six bits of the page index and low order six bits of the fine page table index overlap each fine page table entry for a large page must therefore be duplicated 64 times 3 12 ELECTRONICS ARM920T PROCESSOR MMU Modified virtual address 20 19 16 15 12 11 0 Translation table base 14 13 Translation base 2 18 Translation base Table index B Level one descriptor J oman DI 31 10 9 210 Coarse page table base address L2 table index Level two descriptor 1615 1211109 8765 4 3 2 1 Physical address 16 15 Figure 3 7 Large Page Translation from a Coarse Page Table ELECTRONICS 3 13 MMU ARM920T PROCESSOR TRANSLATING
120. types of LCD panels 4 bit dual scan 4 bit single scan and 8 bit single scan display type Supports the monochrome 4 gray levels and 16 gray levels Supports 256 colors and 4096 colors for color STN LCD panel Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 256 color mode 4096x1024 2048x2048 1024x4096 and others TFT LCD displays Supports 1 2 4 or 8 bpp bit per pixel palettized color displays for TFT Supports 16 bpp non palettized true color displays for color TFT Supports 24 bpp non palettized true color displays for color TFT Supports maximum 16M color TFT at 24bit per pixel mode Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 64K color mode 2048x1024 and others This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 1 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory Its features also include Dedicated interrupt functions INT_FrSyn and INT_FiCnt sy
121. used to tell a coprocessor to perform some internal operation No result is communicated back to ARM920T and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can overlap other activity allowing the coprocessor and ARM920T to perform independent tasks in parallel COPROCESSOR INSTRUCTIONS The S3C44B0X unlike some other ARM based processors does not have an external coprocessor interface It does not have a on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C44BOX These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor can not be connected to the 53 44 the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 28 27 24 23 20 19 16 15 12 11 7 5 4 3 ws ewe ww e 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20 Coprocessor operation code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM920T The remaining bits are used by coproces
122. when the MMU is enabled The access control mechanisms of the MMU detect the conditions that produce these faults If a fault is detected as the result of a memory access the MMU will abort the access and signal the fault condition to the CPU core The MMU retains status and address information about faults generated by the data accesses in the fault status register and fault address register see section Fault address and fault status registers on page 3 18 The MMU does not retain status about faults generated by instruction fetches An access violation for a given memory access inhibits any corresponding external access with an abort returned to the CPU core ELECTRONICS 3 17 MMU ARM920T PROCESSOR FAULT ADDRESS AND FAULT STATUS REGISTERS On a data abort the MMU places an encoded 4 bit value FS 3 0 along with the 4 bit encoded domain number in the Data fault status register FSR Similarly on a prefetch abort in the Prefetch fault status register intended for debug purposes only In addition the modified virtual address associated with the data abort is latched into the fault address register FAR If an access violation simultaneously generates more than one source of abort they are encoded in the priority given in Table 3 4 The fault address register is not updated by faults caused by instruction prefetches FAULT STATUS The remainder of this chapter describes the various access permissions and controls supported by th
123. you should set IICCON 4 1 although you does not use the interrupt ELECTRONICS 20 11 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR MULTI MASTER IIC BUS CONTROL STATUS IICSTAT REGISTER IICSTAT 0x54000004 IIC Bus control status register Mode selection IIC bus master slave Tx Rx mode select bits 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode IIC Bus busy signal status bit 0 read Not busy when read write STOP signal generation 1 read Busy when read Busy signal status START STOP condition write START signal generation The data in IICDS will be transferred automatically just after the start signal IIC bus data output enable disable bit Serial output 0 Disable Rx Tx 1 Enable Rx Tx B NEN Arbitration status flag 3 IIC bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O mE mE Address as slave status IIC bus address as slave status flag bit flag 0 Cleared when START STOP condition was detected 1 Received slave address matches the address value in the IICADD IIC bus address zero status flag bit 0 Cleared when START STOP condition was detected 1 Received slave address is 00000000b IIC bus last received bit status flag bit 0 Last received bit is 0 ACK was received 1 Last received bit is 1 ACK was not received Address zero status
124. 0 15 PWM TIMER S3C2410X01 RISC MICROPROCESSOR TIMER 1 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB1 TCMPB1 TCNTB1 0x51000018 R W 1 count buffer register 0x00000000 TCMPB1 0x5100001C Timer 1 campare buffer register 0x00000000 TCMPB1 Timer 1 compare buffer register 15 0 Set compare buffer value for Timer 1 0x00000000 Timer 1 count buffer register 15 0 Set count buffer value for Timer 1 0x00000000 Timer 1 Count Observation Register TCNTO1 Register Reset Value TCNTO1 0x51000020 Timer 1 count observation register 0x00000000 Timer 1 observation register 15 0 Set count observation value for Timer 1 0x00000000 10 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER TIMER 2 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB2 TCMPB2 TCNTB2 0x51000024 R W Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 Timer 2 campare buffer register 0x00000000 Timer 2 compare buffer register 15 0 Set compare buffer value for Timer 2 0x00000000 15 0 Set count buffer value for Timer 2 0x00000000 TCNTB2 Timer 2 count buffer register TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 Register Reset Value TCNTO2 0x5100002C 2 count observation register 0x00000000 Timer 2 observation register 15 0 Set count observation value for Timer 2 0x00000000 ELECTRONICS 10 17 PWM TIMER S3C2410X01 RISC MICROPROCESSOR TIMER 3 COUNT BUFFER REGISTER
125. 0 MHz LCD Data Rate 8 x 640 x 480 x 60 8 18 432Mbyte s LCD DMA Burst Count 18 432 16 1 152M s Trp Tred CL 2 4 1 x 1 60MHz 0 250ms LCD System Load 1 152 x 250 0 288 System Bus Occupation Rate 0 288 1 x 100 28 8 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 41 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR Register Setting Guide TFT LCD The CLKVAL register value determines the frequency of VCLK and frame rate Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 VFPD 1 x HSPW 1 HBPD 1 HFPD 1 HOZVAL 1 x 2x CLKVAL 1 HCLK For applications the system timing must be considered to avoid under run condition of the fifo of the Icd controller caused by memory bandwidth contention Example 4 TFT Resolution 240 x 240 VSPW 2 VBPD 14 LINEVAL 239 VFPD 4 HSPW 25 HBPD 15 HOZVAL 239 HFPD 1 CLKVAL 5 HCLK 60 M hz The parameters below must be referenced by LCD size and driver specifications VSPW VBPD LINEVAL VFPD HSPW HBPD HOZVAL and HFPD If target frame rate is 60 70Hz then CLKVAL should be 5 So Frame Rate 67Hz 15 42 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR A D CONVERTER AND TOUCH SCREEN 05 20 2002 1 6 ADC amp TOUCH SCREEN I
126. 0000 y __ stos T Taie d SROMSDRAM SROM SDRAM 2MB 4MB 8MB 16MB nGCS6 nGCS6 32MB 64MB 128MB 0 3000 0000 SROM SROM nGCS5 nGCS5 0x2800 0000 y L 4 fr ae ee SROM SROM 1GB nGCS4 nGCS4 HADDR 29 0 0x2000 0000 em _ Accessible iin SROM SROM Sgan nGCS3 nGCS3 Ox1800 0000 y hemmer SROM SROM nGCS2 nGCS2 Ox1000 0000 SROM SROM nGCS1 nGCS1 0x0800 0000 SROM 128MB NGCSO Boot Internal 0x0000 0000 _ 4 SRAM 4KB Y Not using NAND flash for boot ROM Using NAND flash for boot ROM Note SROM means ROM or SRAM type memory Figure 5 1 S3C2410X01 Memory Map after Reset Table 5 1 Bank 6 7 Addresses Bank 6 Start address 0x3000 0000 0x3000 0000 0x3000 0000 0 3000 0000 0x3000 0000 0 3000 0000 0 3000 0000 Bank 7 Start address 0x3020 0000 0x3040 0000 0x3080 0000 0x3100 0000 0x3200 0000 0x3400 0000 0 3800 0000 Note Bank 6 and 7 must have the same memory size 5 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER FUNCTION DESCRIPTION BANKO BUS WIDTH The data bus of BANKO 0 should be configured in width as one of 16 bit and 32 bit ones Because the BANKO works as the booting ROM bank map to 0x0000_0000 the bus width of BANKO should be determined before the first ROM access which will depend on the logic level of OM 1 0 at Reset
127. 1 reserved transfer count becomes 0 The channel on off bit DMASKTRIGn 1 TC 19 0 Initial transfer count or transfer beat Note that the actual number of bytes that are transferred is computed by the following equation DSZ x TSZ x TC Where DSZ TSZ 1 or 4 and TC represent data size DCONn 21 20 transfer size DCONn 28 and initial transfer count respectively This value will be loaded into only if the CURR_SRC is 0 and the DMA ACK is 1 selected by DCONn 23 is set to 0 DREQ off to prevent unintended further start of new SWHW SEL 23 Select the DMA source between software S W request mode and hardware H W request mode 0 S W request mode is selected and DMA is triggered by setting SW TRIG bit of DMASKTRIG control register 1 DMA source selected by bit 26 24 triggers the DMA operation DMA operation 8 10 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR DMA DMA STATUS DSTAT REGISTER DSTATO ox4b000014 R DMA 0 count register 000000h DSTAT1 0x4b000054 1 count register 000000h DSTAT2 0x4b000094 DMA 2 count register 000000h DSTAT3 0x4b0000d4 E DMA 3 count register 000000h DSTATn Bit Description Initial State STAT 21 20 Status of this DMA controller 00 Indicates that DMA controller is ready for another DMA request 01 Indicates that DMA controller is busy for transfers CURR TC 19 0 Current value of transfer count 00000h Note that transfer count i
128. 1 D odd n gt 1 D 1 D lt gt 1 ADD 3 If C MOD 4 3 say 24n D 1 D odd gt 1 D 1 0 lt gt 1 RSB MOV Rb Ra LSL zin Rb Ra D Rb Rb LSL n ADD Rb Ra Ra LSL n Rb Ra D Rb Ra Rb LSL n RSB Rb Ra Ra LSL Rb Ra D Rb Ra Rb LSL n 53 2410 RISC MICROPROCESSOR Multiply by 3 and then by 2 Multiply by 5 Multiply by 2 and add in next digit This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB RSB ADD rather than by ADD ADD 3 62 Rb Ra Ra LSL 2 Rb Ra Rb LSL 2 Rb Ra Rb LSL 2 Rb Ra Ra LSL 3 Rb Rb Rb LSL 2 Multiply by 3 Multiply by 4 3 1 11 Multiply by 4 11 1 45 Multiply by 9 Multiply by 5 9 45 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Ro Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Rc LSL Rb Enter with address in Ra 82 bits uses Rb Rc result in Rd Note d must be less than c e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes how in bits and test if aligned Produce bottom of result word if not aligned Get other shift amount Combine two halves to get result 3 63 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR NOTES 3 64 ELECTRONICS S3C2410X RISC MICROPROCESSOR
129. 1 0 00 Input Description 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 2 nCTS1 01 Output 11 2 nRTS1 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved Undefined 10 nCTSO GPH 10 0 10 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read GPHUP Deseription 4 GPH 10 0 10 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled 9 20 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS MISCELLANEOUS Control Register MISCCR Pads related USB are controlled by this register for USB host or for USB device MISCCR 0x56000080 R W Miscellaneous control register 0x10330 21 20 Reserved to 00b nEN_SCKE 19 0 Normal 1 level Used to protect SDRAM during the Power_OFF moe nEN_SCLK1 18 0 SCLK1 SCLK 1 SCLK1 L level Used to protect SDRAM during the Power_OFF moe nEN_SCLKO 17 0 SCLKO 1 SCLKO level Used to protect SDRAM during the Power_OFF moe nRSTCON 16 nRSTOUT software control SW_RESET 0 n
130. 1 10 fm gt 2 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 4 5 Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair NOTE All instructions in this group set the CPSR condition codes Table 4 5 Summary of Format 4 Instructions op THUMB assembler ARMEquipment Am 1001 NEG Rs RSBS Rs 0 Rs Ed ELECTRONICS 4 11 1000 TST Rd Rs TST Rd Rs Set condition codes on Rd AND Rs THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES 53 2410 RISC MICROPROCESSOR All instructions in this format have an equivalent ARM instruction as shown in Table 4 5 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES EOR ROR NEG CMP MUL R3 R4 R1 RO R5 R3 R2 R6 RO R7 R3 EOR R4 and set condition codes Rotate Right R1 by the value in RO store the result in R1 and set condition codes Subtract the contents of R3 from zero Store the result in R5 Set condition codes R5 Set the condition codes on the result of R2 R6 RO 7 RO and set condition codes ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 5 HI REGISTER OPERATIONS BRANCH EXCHANGE 15 14 13 12 11 10 9 8 7 6 5 3 2 0 moms 2 0 Destination Register 5 3 So
131. 1 FIQ INT UARTO 0 IRQ 1 FIQ INT 0 IRQ 1 FIQ INT USBH INT USBD Reserved INT URRT1 O IRQ 1 FIQ INT_SPIO 0 IRQ 1 FIQ INT DMA3 INT DMA2 0 IRQ 1 FIQ INT 0 IRQ 1 FIQ INT DMAO INT LCD INT UART2 INT TIMER4 0 IRQ 1 FIQ INT TIMER3 0 IRQ 1 FIQ INT TIMER2 INT TIMER INT TIMERO INT WDT 0 1 FIQ INT TICK 0 1 FIQ o 8 Reserved Notused EINTB 23 EINT4 7 0 IRQ 1 FIQ EINT3 0 IRQ 1 zu EINTO 0 IRQ 1 ELECTRONICS 14 9 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR INTERRUPT MASK INTMSK REGISTER This register also has 32 bits each of which is related to an interrupt source If a specific bit is set to 1 the CPU does not service the interrupt request from the corresponding interrupt source note that even in such a case the corresponding bit of SRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced Register Address R W Description Reset Value INTMSK 0X4A000008 R W Determine which interrupt source is masked The masked OxFFFFFFFF interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 14 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER em Dosor 7 Niwor dm 0 Semice avalable 12 Masked FIT n Reserved ENTE 23 5 ENTA 7 a ENTS a Era 2 ENTO D ELECTRONICS 14 11 INTERRUPT CO
132. 10 8 Source Destination Register 12 11 Opcode 0 2 MOV 1 2 ADD 3 SUB Figure 4 4 Format 3 OPERATIONS The instructions in this group perform operations between Lo register and an 8 bit immediate value The THUMB assembler syntax is shown in Table 4 4 NOTE All instructions in this group set the CPSR condition codes Table 4 4 Summary of Format 3 Instructions 00 MOV Ra MOVS Rd fOffset8 Move 8 bit immediate value into 01 CMP Rd Offset8 CMP Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Offset8 ADDS Rd Rd Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rad Offset8 SUBS Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd ELECTRONICS 4 9 THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES 53 2410 RISC MICROPROCESSOR All instructions in this format have an equivalent ARM instruction as shown in Table 4 4 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES MOV CMP ADD SUB RO 128 R2 62 R1 255 R6 145 RO 128 and set condition codes Set condition codes on R2 62 R1 R1 255 and set condition codes R6 R6 145 and set condition codes ELECTRONICS S3C2410X RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 4 ALU OPERATIONS 15 14 13 9 6 5 3 2 0 12 1
133. 2 Bi HW FENTRY 15 0 Transmit Receive data for IIS NOTES 1 The IISFIFO register is accessible for each halfword and word unit using STRH and LDRH instructions or short int type pointer in Little Big endian mode 2 Li HW Little HalfWord Bi HW Big HalfWord 21 8 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR SPI INTERFACE 05 20 2002 SPI INTERFACE PRELIMINARY OVERVIEW The 53 2410 01 Serial Peripheral Interface SPI can interface the serial data transfer The S3C2410X01 includes two SPI each of which has two 8 bit shift registers for transmission and receiving respectively During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially 8 bit serial data at a frequency is determined by its corresponding control register settings If you only want to transmit received data can be dummy Otherwise if you only want to receive you should transmit dummy 1 data There are 4 I O pin signals associated with SPI transfers the SPICLKO 1 the MISO 1 data line the MOSI SPIMOSIO 1 data line and the active low SS 550 1 pin input FEATURES SPI Protocol ver 2 11 compatible 8 Shift Register for transmit 8 Shift Register for receive 8 Prescaler logic Polling Interrupt and DMA transfer mode This document is a preliminary user s manual So our company will present its revision as of the date
134. 20 9 26 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS External Interrupt Mask Register EINTMASK Interrupt mask register for 20 external interrupts EINT 23 4 EINTMASK 0x560000A4 External interupt mask register OxOOFFFFFO 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked EINT13 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked ENT 9 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked Bo b ELECTRONICS 9 27 PORTS 53 2410 01 RISC MICROPROCESSOR External Interrupt Pending Register EINTPENDn Interrupt pending register for 20 external interrupts EINT 23 4 You can clear a specific bit of the ENITPEND register by writing 1 on the corresponding bit of this register EINTPEND 0 560000 8 R W External interupt pending register 0 0 EINT13 0 Not requested Bo fo o ooo O 9 28 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Req
135. 20 D 19 16 05 12 Da 08591 oo Pr P p Po p Pa Pm P E P e 0084 Pes Par pao po PP PP 2BPP Display BSWP 0 HWSWP 0 D 51 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Toon mm ee re mo ps pe pr re This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 19 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR 256 PALETTE USAGE TFT Palette Configuration and Format Control The 53 2410 01 provides 256 color palette for TFT LCD Control The user can select 256 colors from the 64K colors in these two formats The 256 color palette consists of the 256 depth x 16 bit SPSRAM The palette supports 5 6 5 R G B format and 5 5 5 1 R G B 1 format When the user uses 5 5 5 1 format the intensity data l is used as a common LSB bit of each RGB data So 5 5 5 1 format is the same as R 5 1 G 5 1 B 5 1 format In 5 5 5 1 format for example the user can write the palette as in Table 15 5 and then connect VD pin to TFT LCD panel R 5 1 VD 23 19 VD 18 VD 10 or VD 2 G 5 1 VD 15 11 VD 18 VD 10 VD 2 B 5 1 VD 7 3 VD 18 VD 10 or VD 2 and set FRM565 of LCDCONS register to 0 Tab
136. 3 18 The data FSR is defined in ARM architecture v4T Additionally a pipelined prefetch FSR is available for debug purposes only The pipeline matches that of the ARM9TDMI The following instructions can be used to access the data and prefetch FSR MRC p15 0 Rd c5 0 0 read data FSR value MCR p15 0 Rd c5 0 0 write data FSR value MRC p15 0 Rd c5 0 1 read prefetch FSR value MCR p15 0 Rd c5 0 1 write prefetch FSR value The ability to write to the FSR is useful for a debugger to restore the value of the FSR The register should be written using the read modify write method Bits 31 8 should be zero 2 14 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 6 FAULT ADDRESS REGISTER Register 6 is the fault address register FAR which contains the modified virtual address of the access being attempted when the last fault occurred The FAR is only updated for data faults not for prefetch faults The address for a prefetch fault can be found in R14 The following instructions can be used to access the FAR MRC p15 0 Rd c6 0 0 read FAR data MCR p15 0 Rd 0 0 write FAR data The ability to write to the FAR is intended for a debugger to restore a previous state REGISTER 7 CACHE OPERATIONS Register 7 is a write only register used to manage the instruction and data caches ICache and DCache The cache operations provided by register 7 are described in Table 2 15 Table 2 15
137. 3 22 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value 10 operand B has the value 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represented as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct results and Rd Rn and Rs may use the same register when required ELECTRONICS 3 23 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V oVerflow flag is unaffected INSTRUCTION CYCLE TIMES MUL takes 15 ml and MLA 15 m 1 I cycles to execute where S and are defined as sequential S cycle and internal I cycle respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the
138. 31 20 of the modified virtual address to produce a 30 bit address as illustrated in Figure 3 3 on page 3 7 This address selects a 4 byte translation table entry which is a level one descriptor for either a section or a page table Modified virtual address 31 20 19 0 Translation table base 31 14 13 0 Translation base 999 12 18 31 14 13 210 Translation base Table index 0 0 Level one descriptor 31 0 Figure 3 3 Accessing the Translation Table Level One Descriptors ELECTRONICS 3 7 MMU ARM920T PROCESSOR LEVEL ONE DESCRIPTOR The level one descriptor returned is either a section descriptor a coarse page table descriptor or a fine page table descriptor A section descriptor provides the base address of a 1MB block of memory The page table descriptors provide the base address of a page table that contains level two descriptors There are two sizes of page table coarse page tables have 256 entries splitting the 1MB the table describes into 4KB blocks e fine page tables have 1024 entries splitting the 1MB the table describes into 1KB blocks coarse page ato tase 1 ofi conse pago ab a domain o section Fine page Figure 3 4 Level One Descriptors The two least significant bits indicate the descriptor type Table 3 2 Interpreting Level One Descriptor Bits 1 0 Generates a section translation fault Coarse page table Indicates t
139. 384fs 16fs 32fs 48fs 32fs 4815 21 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIS BUS INTERFACE IIS BUS INTERFACE SPECIAL REGISTERS IIS CONTROL IISCON REGISTER IISCON 0x55000000 Li HW R W IIS control register 0x100 0x55000002 Bi HW IISCON Bit Description Left Right channel index 8 0 Left 1 Read only 1 Right Transmit FIFO ready flag 7 0 Not ready empty Read only 1 Ready not empty Receive FIFO ready flag 6 0 Not ready full Read only 1 Ready not full Transmit DMA service request 5 0 Disable 1 Enable Receive DMA service request 4 0 Disable 1 Enable 0 Transmit channel idle command In Idle state the IISLRCK is inactive Pause Tx 0 Not idle 1 Idle Receive channel idle command 2 In Idle state the IISLRCK is inactive Pause Rx 0 Not idle 1 Idle IIS prescaler 1 0 Disable 1 Enable IIS interface 0 0 Disable stop 1 Enable start Notes 1 The IISCON register is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word ELECTRONICS 21 5 IIS BUS INTERFACE 3C2410X01 RISC MICROPROCESSOR IIS MODE REGISTER IISMOD REGISTER IISMOD 0x55000004 Li W Li HW Bi W R W IIS mode register 0 0 0x55000006 Bi HW Master slave mode select 8
140. 6 MOV a1 a1 Isr 3 ADD a3 a1 a1 asl 2 SUBS a2 a2 a3 asl 1 ADDPL al a1 1 ADDMI a2 a2 10 MOV Ir ELECTRONICS 4 43 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR NOTES 4 44 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER 05 25 2002 MEMORY CONTROLLER Preliminary OVERVIEW The S3C2410X01 memory controller provides memory control signals required for external memory access The 53 2410 01 has the following features Little Big endian selectable by a software Address space 128Mbytes per bank total 1GB 8 banks Programmable access size 8 16 32 bit for all banks except 16 32 bit Total 8 memory banks Six memory banks for ROM SRAM etc Remaining two memory banks for ROM SRAM SDRAM etc Seven fixed memory bank start address One flexible memory bank start address and programmable bank size Programmable access cycles for all memory banks External wait to extend the bus cycles Supporting self refresh and power down mode in SDRAM This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 5 1 MEMORY CONTROLLER 3C2410X01 RISC MICROPROCESSOR 0 40000 0000 gt 1 0 01 10 i s OM 1 0 00 SROM SDRAM SROM SDRAM 2MB 4MB 8MB 16MB nGCS7 nGCS7 32MB 64MB 128MB Refer to 0 3800
141. 6C L 16 FRAME NUM1 REG Frame number 1 register 0x170 L 0 173 FRAME NUM2 REG Frame number 2 register INDEX REG EPO FIFO REG Offset Address B B 0x140 L 0x143 0 147 Function address register Wm 2 gt Index register EndpointO FIFO register EP1 FIFO REG Endpoint1 FIFO register EP2 FIFO REG Endpoint2 FIFO register FIFO REG Endpoint3 FIFO register EP4 REG Endpoint4 FIFO register EP1 DMA CON EP1 DMA UNIT EP1 DMA FIFO TTC L EP1 DMA TTC M EP1 DMA TTC H Endpoint1 DMA control register Endpoint1 DMA unit counter register Endpoint DMA FIFO counter register Endpoint1 DMA transfer counter low byte register Endpoint1 DMA transfer counter middle byte register Endpoint1 DMA transfer counter high byte register 0x214 L 0 217 ELECTRONICS 13 3 USB DEVICE EP2_DMA_CON EP2_DMA_UNIT EP2_DMA_FIFO EP2_DMA_TTC_L EP2_DMA_TTC_M EP2_DMA_TTC_H EP3_DMA_CON EP3_DMA_UNIT EP3_DMA_FIFO EP3_DMA_TTC_L EP3_DMA_TTC_M 53 2410 01 RISC MICROPROCESSOR Endpoint2 DMA control register Endpoint2 DMA unit counter register Endpoint2 DMA FIFO counter register Endpoint2 DMA transfer counter low byte register Endpoint2 DMA transfer counter middle byte register Endpoint2 DMA transfer counter high byte register Endpoint3 DMA control register Endpoint3 DMA unit counter register Endp
142. 9 Format 8 OPERATION These instructions load optionally sign extended bytes or halfwords and store halfwords The THUMB assembler syntax is shown below Table 4 9 Summary of format 8 instructions THUMB assembler ARM equivalent Action Rb Ro Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rad Rb Ro LDRH Rd Rb Ro Load halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to O LDSB Rd Rb Ro LDRSB Rd Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rd Rb Ro LDRSH Rd Rb Ro Load sign extended halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to bit 15 4 20 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 9 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R4 RO Store the lower 16 bits of R4 at the address formed by adding RO to R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding R1 to R7 LDSH R3 R4 R2 Loadinto R3
143. 98 ft 39 me fee fm nm nm This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 23 ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR NOTES 24 24 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR MECHANICAL DATA 05 22 2002 MECHANICAL DATA PRELIMINARY PACKAGE DIMENSIONS Dimensions in Milimeters 5NnSWVS 0 30 0 05 TOP VIEW SIDE VIEW Figure 25 1 272 FBGA 1414 Package Dimension 1 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 25 1 MECHANICAL DATA 3C2410X01 RISC MICROPROCESSOR AT BALL PAD DD 52 e e e 2 ODO a QU utu o BOTTOM VIEW 272 SOLDER BALLS Figure 25 2 272 FBGA 1414 Package Dimension 2 25 2 ELECTRONICS ARM920T PROCESSOR INTRODUCTION Appendix 1 ARM920T INTRODUCTION The ARM920T is a member of the ARM9TDMI family of general purpose microprocessors which includes AR
144. A tag is in the instruction cache the instruction data is returned to the ARM9TDMI 4 If the instruction cache misses IMVA tag is not in the instruction cache then the IMMU performs translation to produce the instruction PA IPA This address is given to the AMBA bus interface to perform an external access Table 2 4 Address Types in ARM920 Domain Domain Caches amp TLBs AMBA bus 2 6 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 0 ID CODE REGISTER This is a read only register which returns a 32 bit device ID code The ID code register is accessed by reading CP15 register 0 with the opcode 2 field set to any value other than 1 the CRm field should be zero when reading For example MRC p15 0 Rd c0 c0 0 returns ID register The contents of the ID code are shown in Table 2 5 Table 2 5 Register 0 ID Code 23 20 Specification revision 0 1 19 16 Architecture version 4 0 2 ELECTRONICS 2 7 PROGRAMMER S MODEL ARM920T PROCESSOR REGISTER 0 CACHE TYPE REGISTER This is a read only register which contains information about the size and architecture of the caches allowing operating systems to establish how to perform such operations as cache cleaning and lockdown Future ARM cached processors will contain this register allowing RTOS vendors to produce future proof versions of their operating systems The cache type register is accessed by reading CP15 register 0 with the opcode_2 field s
145. ACK Porch 10 ACTIVE 11 FRONT Porch HSTATUS 18 17 TFT Horizontal Status read only 00 HSYNC 01 BACK Porch 10 ACTIVE 11 FRONT Porch 16 13 This bit is reserved and the value should be 0 BPP24BL 12 TFT This bit determines the order of 24 bpp video memory 0 LSB valid 1 MSB Valid FRM565 11 TFT This bit selects the format of 16 bpp output video data 0 5 5 5 1 Format 1 5 6 5 Format INVVCLK 10 STN TFT This bit controls the polarity of the VCLK active edge 0 The video data is fetched at VCLK falling edge 1 The video data is fetched at VCLK rising edge INVVLINE STN TFT This bit indicates the VLINE HSYNC pulse polarity 0 normal 1 inverted INVVFRAME 8 STN TFT This bit indicates the VFRAME VSYNC pulse polarity 0 normal 1 inverted INVVD 7 STN TFT This bit indicates the VD video data pulse polarity 0 Normal 1 VD is inverted 15 30 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 LCD Control 5 Register Continued INVVDEN 6 TFT This bit indicates the VDEN signal polarity 0 normal 1 inverted INVPWREN STN TFT This bit indicates the PWREN signal polarity 0 normal 1 inverted 5 INVLEND 4 TFT This bit indicates the LEND signal polarity 0 normal 1 inverted 0 PWREN 3 STN TFT LCD_PWREN output signal enable disable 0 Disable PWREN signal 1 Enable PWREN signal ENLEND 2 TFT LEND output signal ena
146. C mode The THUMB assembler syntax for this instruction is shown below Table 4 18 The SWI Instruction THUMB assembler ARMequivalent Action SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES SWI 18 Take the software interrupt exception Enter Supervisor mode with 18 as the requested SWI number 4 36 ELECTRONICS S3C2410X RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 18 UNCONDITIONAL BRANCH 15 14 13 10 0 1 12 11 oo S 10 0 Immediate Value Figure 4 19 Format 18 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction Table 4 19 Summary of Branch Instruction THUMB assembler ARM equivalent B label BAL label halfword offset Branch PC relative Offset11 lt lt 1 where label is PC 2048 bytes NOTE The add
147. Cache is disabled and the write buffer contents are discarded There is no explicit write buffer enable bit implemented in ARM920T Situations in which the write buffer is used are described below The DCache is enabled by writing 1 to the Cer bit and disabled by writing 0 to the Ccr bit The DCache must be enabled only when the MMU is enabled This is because the MMU translation tables define the cache and write buffer configuration for each memory region When the DCache is disabled the cache contents are ignored and all data accesses appear on the Advanced System Bus as separate non sequential accesses If the cache is subsequently re enabled its contents will be unchanged Depending on the software system design the cache may need to be cleaned after it is disabled and invalidated before it is re enabled See Cache coherence on page 4 10 The MMU and DCache can be enabled or disabled simultaneously with a single MCR which changes bit 0 and bit 2 in the control register CP15 register 1 DATA CACHE AND WRITE BUFFER OPERATION The DCache and write buffer configuration of each memory region is controlled by the C and B bits in each section and page descriptor in the MMU translation tables For clarity these bits are referred to as Ctt and Btt in the following text The configuration is modified by the DCache enable bit in the CP15 control register which is referred to as Ccr If the DCache is enabled a DCache lookup is performed for ea
148. D These bits indicate A 21 1 of the start address 0x0000 of the lower address counter which is used for the lower frame memory of dual scan LCD For single scan LCD These bits indicate A 21 1 of the end address of the LCD frame buffer LCDBASEL the fame end address gt gt 1 1 LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 Note Users can change the LCDBASEU and LCDBASEL values for scrolling while the LCD controller is turned on But users must not change the value of the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register for the LCD FIFO fetches the next frame data prior to the change in the frame So if you change the frame the pre fetched FIFO data will be obsolete and LCD controller will display an incorrect screen To check the LINECNT interrupts should be masked If any interrupt is executed just after reading LINECNT the read LINECNT value may be obsolete because of the execution time of Interrupt Service Routine ISR 15 32 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 FRAME Buffer Start Address 3 Register LCDSADDR3 0X4D00001C STN TFT Virtual screen address set 0x00000000 OFFSIZE 21 11 Virtual screen offset size the number of half words 00000000000 This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new
149. D FLASH COMMAND SET NFCMD REGISTER NFCMD 0 4 00004 R W NAND flash command set register mss NAND command vaig NAND FLASH ADDRESS SET NFADDR REGISTER NFADDR 0 4 000008 NAND flash address set register Reserved 58 Reseved Address 7 0 NAND flash memory address value NAND FLASH DATA NFDATA REGISTER R W Description Reset Value NFDATA 0 4 00000 R W NAND flash data register iss Data 7 0 NAND Flash read program data value In case of write Programming data In case of read Read data This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 6 7 NAND FLASH CONTROLLER 3C2410X01 RISC MICROPROCESSOR NAND FLASH OPERATION STATUS NFSTAT REGISTER NFSTAT 0x4E000010 oR NAND Flash operation status nes RnB NAND Flash memory ready busy status This signal is checked through nWAIT pin 0 NAND Flash memory busy 1 NAND Flash memory ready to operate NAND FLASH ECC NFECC REGISTER Register Address R W Description Reset Value NFECC 0x4E000014 Flash ECC Error Correction Code register ECC2 23 16 Error Correction Code 2 L ww __ ECC1 15 8 Error Correction Code 1 Fo ECCO 7 0 Error Correction Code 0
150. DEL ARM920T PROCESSOR ABOUT THE ARM9TDMI PROGRAMMER S MODEL The ARM9TDMI processor core implements ARM v4T architecture and so executes the ARM 32 bit instruction set and the compressed Thumb 16 bit instruction set The programmer s model is fully described in the ARM Architecture Reference Manual The ARM9TDMI Technical Reference Manual gives implementation details including instruction execution cycle times The ARM v47T architecture specifies a small number of implementation options The options selected in the ARM9TDMI implementation are listed in Table 2 1 For comparison the options selected for the ARM7TDMI implementation are also shown Table 2 1 ARM9TDMI Implementation Option Processor ARM Data abort model Value stored by direct core architecture STR STRT STM of PC ARM7TDMI Base updated Address of Inst 12 ARM9TDMI v4T Address of Inst 12 The ARM9TDMI is code compatible with the ARM7TDMI with two exceptions The ARM9TDMI implements the base restored data abort model which significantly simplifies the software data abort handler e The ARM9TDMI fully implements the instruction set extension spaces added to the ARM 32 bit instruction set in architecture v4 and v4T These differences are explained in more detail below DATA ABORT MODEL The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI The difference in the data abort model affects only a very s
151. DIDSTn Bit _ Initial State D ADDR 30 0 Base address start address of destination for the transfer This bit 0x00000000 value will be loaded into CURR_SRC only if the CURR DST is 0 and the DMA ACK is 1 DMA INITIAL DESTINATION CONTROL DIDSTC REGISTER DIDSTn Bit Description Initial State Bit 1 is used to select the location of destination 0 the destination is in the system bus AHB 1 the destination is in the peripheral bus APB Bit 0 is used to select the address increment 0 Increment 1 Fixed If it is 0 the address is increased by its data size after each transfer in burst and single transfer mode If itis 1 the address is not changed after the transfer In the burst mode address is increased during the burst transfer but the address is recovered to its first value after the transfer 8 8 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR DMA DMA CONTROL DCON REGISTER DCONO 0x4b000010 DMA 0 control register 0x00000000 DCON1 0 46000050 DMA 1 control register 0x00000000 DCON2 0x4b000090 DMA 2 control register 0x00000000 DCON3 0x4b0000d0 ON DMA 3 control register 0x00000000 DCONn Bit Deseription Initial State DMD HS 31 Select one between Demand mode and Handshake mode 0 Demand mode is selected 1 Handshake mode is selected In both modes DMA controller starts its transfer and asserts DACK for a given asserted DREQ The difference between the two modes
152. EL and CLKRST for testing RTCEN bit can control all interfaces between the CPU and the RTC so it should be set to 1 in an RTC control routine to enable data read write after a system reset Also before power off the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers RTCCON 0x57000040 L R W RTC control register 0 0 0 57000043 by byte CLKRST 3 RTC clock count reset 0 reset 1 Reset CLKSEL 1 BCD clock select 0 XTAL 1 27 divided clock 1 Reserved XTAL clock only for test RTC control enable 0 Disable 1 Enable Note Only BCD time count and read operation can be performed CNTSEL 2 BCD count select 0 Merge BCD counters 1 Reserved Separate BCD counters 0 Notes 1 All RTC registers have to be accessed for each byte unit using STRB and LDRB instructions or char type pointer 2 L Little endian B Big endian TICK TIME COUNT TICNT REGISTER Register Descripion Reset Value R W TICNT 0x57000044 L R W Tick time count register 0x0 0x57000047 B by byte TICK INT ENABLE 7 Tick time interrupt enable 0 Disable 1 Enable TICK TIME COUNT Tick time count value 1 127 000000 This counter value decreases internally and users cannot read this counter value in working 7 17 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR REAL TIME CLOCK RTC ALARM CONTROL RTCALM REGISTER The RTCALM register determines
153. ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER DATA CACHE ORGANIZATION The DCache is organized as 8 segments each containing 64 lines and each line containing 8 words The line s position within its segment is a number from 0 to 63 which is called the index A line in the cache can be uniquely identified by its segment and index The index is independent of the line s virtual address The segment is selected by bits 7 5 of the virtual address of the line Bits 4 2 of the virtual address specify which word within a cache line is accessed For halfword operations bit 1 of the virtual address specifies which halfword is accessed within the word For byte operations bits 1 0 specify which byte within the word is accessed Bits 31 8 of the virtual address of the each cache line is called the TAG The virtual address TAG is stored in the cache along with the 8 words of data when the line is loaded by a linefill Cache lookups compare bits 31 8 of the modified virtual address of the access with the stored TAG to determine whether the access is a hit or miss The cache is therefore said to be virtually addressed DATA CACHE LOCKDOWN Data can be locked into the DCache causing the DCache to guarantee a hit and providing optimum and predictable execution time When no data is locked in the DCache and a linefill occurs the replacement algorithm chooses a victim cache line to be replaced by selecting an index in the range 0
154. ER amp FIFO REGISTER There are three UART transmit buffer registers including UTXHO UTXH1 and UTXH2 in the UART block UTXHn has an 8 bit data for transmission data UTXHO 0x50000020 L UART channel 0 transmit buffer register 0x50000023 B by byte UTXH1 0x50004020 L W UART channel 1 transmit buffer register 2 UTXH2 0x50008020 L W UART channel 2 transmit buffer register TXDATAn 7 0 Transmit data UARTn o Note L The endian mode is Little endian B The endian mode is Big endian UART RECEIVE BUFFER REGISTER HOLDING REGISTER amp FIFO REGISTER There are three UART receive buffer registers including URXHO URXH1 and URXH2 in the UART block URXHn has an 8 bit data for received data R R R URXHO 0x50000024 L UART channel 0 receive buffer register 0x50000027 B by byte URXH1 0x50004024 L UART channel 1 receive buffer register 0x50004027 B by byte URXH2 0x50008024 UART channel 2 receive buffer register 0x50008027 by byte RXDATAn 7 0 Receive data for UARTn a NOTE When an overrun error occurs the URXHn must be read If not the next received data will also make an overrun error even though the overrun bit of UERSTATn had been cleared ELECTRONICS 11 19 UART 53 2410 01 RISC MICROPROCESSOR UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIVO UBRDIV1 and UBRDIV2 in the UART block The value stored in t
155. FLT is L level triggered While CPU is in Power OFF mode assertion of the nBAT_FLT will prohibit the wake up from the power down mode So Any wake up source will be masked if NBAT FLT is asserted which is protecting the system malfunction of the low battery capacity ADC Power Down The ADC has an additional power down bit in ADCCON If the S3C2410X01 enters the STOP mode the ADC should enter its own power down mode 7 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT CLOCK GENERATOR amp POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER LOCKTIME LOCKTIME 0 4 000000 PLL lock time count register U_LTIME 23 12 UPLL lock time count value for UCLK OxFFF U_LTIME gt 150uS M_LTIME 11 0 MPLL lock time count value for FCLK HCLK and PCLK OxFFF M_LTIME gt 150uS PLL CONTROL REGISTER MPLLCON AND UPLLCON Mpll m Fin p 2 m MDIV 8 PDIV 2 s SDIV PLL VALUE SELECTION GUIDE Fout m Fin p s where m MDIV 8 p PDIV 2 s SDIV Fin 25 p 16 7e6 m Fin 10 p 0 7 6 48 sqrt m 1 8 Fin p m 330e6 MPLLCON 0 4 000004 MPLL configuration register 0x0005C080 UPLLCON 0x4C000008 UPLL configuration register 0x00028080 Pucov neida NOTE When you set MPLL amp UPLL values simultaneously set MPLL value MPLL value first and then UPLL value Is p ELECTRONICS 7 17
156. FUNC_ADDR_REG This register maintains the USB device controller address assigned by the host The Micro Controller Unit MCU writes the value received through a SET_ADDRESS descriptor to this register This address is used for the next token Register Address Description Reset Value FUNC_ADDR_REG 0x52000140 L RAW Function address register 0x00 0x52000143 B byte FUNC ADDR RE MCU Description Initial G State ADDR UPDATE 7 R R Set by the MCU whenever it updates the SET CLEAR FUNCTION ADDR field in this register This bit will be cleared by USB when DATA END bit in EPO CSR register FUNCTION ADDR 6 0 R W The MCU write the unique address assigned by host to this field ELECTRONICS 13 5 USB DEVICE 53 2410 01 RISC MICROPROCESSOR POWER MANAGEMENT REGISTER PWR_REG This register acts as a power control register in the USB block Register Address Description Reset Value PWR_REG 0x52000144 L R W Power management register 0x00 0x52000147 B byte PWR_ADDR MCU Description Initial State ISO_UPDATE 7 R W Used for ISO mode only If set GFI waits for a SOF token to set IN PKT RDY even though a packet to send is already loaded by MCU If an IN token is received before a SOF token then a zero length data packet will be sent mew USB RESET 3 SET Set by the USB if reset signaling is received from the host This bit remains set as long as reset signaling persists on the bus
157. Function Descriptions Register 7 Invalidate cache Invalidates all cache data including any dirty data 7919 Use with caution Invalidate single entry using Invalidates a single cache line discarding any dirty data note modified virtual address Use with caution Clean D single entry using either Writes the specified cache line to main memory if the line is marked valid index or modified virtual address and dirty and marks the line as not dirty Note The valid bit is unchanged Clean and Invalidate D entry Writes the specified cache line to main memory if the line is marked valid using either index or modified and dirty note virtual address The line is marked not valid Prefetch cache line Performs an ICache lookup of the specified modified virtual address If the cache misses and the region is cacheable a linefill will be performed NOTE Dirty data is data that has been modified in the cache but not yet written to main memory ELECTRONICS 2 15 PROGRAMMER S MODEL ARM920T PROCESSOR The function of each cache operation is selected by the opcode_2 and fields in the MCR instruction used to write CP15 register 7 Writing other opcode 2 or CRm values is unpredictable Reading from CP15 register 7 is unpredictable Table 2 16 on page 2 16 shows instructions that can be used to perform cache operations with register 7 Table 2 16 Cache Operations Register 7 Invalidate ICache amp DCache MCR p15 0 Rd c7 c7 0 SB
158. ICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT Power_OFF Mode The block disconnects the internal power So there occurs no power consumption due to CPU and the internal logic except the wake up logic in this mode Activating the Power OFF mode requires two independent power sources One of the two power sources supplies the power for the wake up logic The other one supplies other internal logics including CPU and should be controlled for power on off In the Power OFF mode the second power supply source for the CPU and internal logics will be turned off The wakeup from Power OFF mode can be issued by the EINT 15 0 or by RTC alarm interrupt Procedure to Enter Power_OFF mode 1 Set the GPIO configuration adequate for Power OFF mode 2 Mask all interrupts in the INTMSK register 3 Configure the wake up sources properly including RTC alarm The bit of EINTMASK corresponding to the wake up source has not to be masked 4 Set USB pads as suspend mode MISCCR 13 12 11b 5 Save some meaning values into GSTATUS 4 3 register These register are preserved during Power OFF mode 6 Configure MISCCR 1 0 for the pull up resisters on the data bus D 31 0 If there are a external BUS holder such as 741 VCH162245 turn off the pull up resistors If not turn on the pull up resistors Stop LCD by clearing LCDCON1 ENVID bit Read rREFRESH and rCLKCON registers in order to fill the TLB 9 Let SDRAM enter the self refre
159. INTERFACE 3C2410X01 RISC MICROPROCESSOR SPI Transfer Format The S3C2410X01 supports 4 different format to transfer the data Figure 22 2 shows four waveforms for SPICLK CPOL 0 CPHA 0 Format A o 7 3 5 6 SPICLK MSB of character just received CPOL 0 CPHA 1 Format B Cycle 2 15 5 T7 SPICLK LSB of previously transmitted character CPOL 1 CPHA 0 Format A o 5 MOSI MISO MSB of character just received CPOL 1 CPHA 1 Format B Cycle 1 2 3 4 5 6 7 8 MOSI MISO LSB of previously transmitted character Figure 22 2 SPI Transfer Format 22 4 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR SPI INTERFACE 05 20 2002 Transmitting procedure by DMA 1 SPI is configured as DMA mode DMA is configured properly The SPI requests DMA service DMA transmits 1byte data to the SPI The SPI transmits the data to card Return to Step 3 until DMA count becomes 0 The SPI is configured as interrupt or polling mode with SMOD bits Receiving procedure by DMA 1 The SPI is configured as DMA start with SMOD bits and setting TAGD bit DMA is configured properly The SPI receives 1byte data from card The SPI requests DMA service DMA receives the data from the SPI Write data OxFF automatically to SPTDATn Return to Step 4 until DMA count becomes 0 The SPI is conf
160. Input 10 EINT9 GPGO 1 0 00 Input 10 EINT8 9 18 01 Output 11 Reserved 01 Output 11 SPICLK1 01 Output 11 SPIMOSI1 01 Output 11 SPIMISO1 01 Output 11 LCD_PWRDN 01 Output 11 nSS1 01 Output 11 nSS0 01 Output 11 Reserved 01 Output 11 Reserved ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS GPG 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read GPGUP Bit Deseription O GPG 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled GPG 15 11 are pull up disabled state at the initial condition ELECTRONICS 9 19 PORTS 53 2410 01 RISC MICROPROCESSOR PORT H CONTROL REGISTERS GPHCON GPHDAT and GPHUP Pull up disable register for port H GPHCON GPH10 21 20 00 Input 10 CLKOUT1 GPH9 19 18 00 Input 10 CLKOUTO GPH8 17 16 00 Input 10 UCLK GPH7 15 14 00 Input 10 RXD2 GPH6 13 12 00 Input 10 TXD2 GPH5 11 10 00 Input 10 RXD1 GPH4 00 Input 10 TXD1 GPH3 7 6 00 Input 10 RXDO GPH2 5 4 00 Input 10 TXDO GPH1 3 2 00 Input 10 nRTSO GPHO
161. K STN These bits indicate the blank time in one horizontal line STN duration time These bits adjust the rate of the VLINE finely The unit of LINEBLANK is HCLK X 8 Ex If the value of LINEBLANK is 10 the blank time is inserted to VCLK during 80 HCLK HFPD TFT 7 0 TFT Horizontal front porch is the number of VCLK periods between 0X00 the end of active data and the rising edge of HSYNC 15 28 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 LCD Control 4 Register LCDCON4 0x4D00000C LCD control 4 register 0x00000000 MVAL 15 8 STN These bit define the rate at which the VM signal will toggle if 0X00 the MMODE bit is set to logic 1 7 0 TFT Horizontal sync pulse width determines the HSYNC pulse s 0X00 high level width by counting the number of the VCLK STN WLH 1 0 bits determine the VLINE pulse s high level width by counting the number of the HCLK WLH 7 2 are reserved 00 16 HCLK 01 32 HCLK 10 64 HCLK 11 128 HCLK STN This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 29 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR LCD Control 5 Register LCDCONS 0 40000010 LCD control 5 register 0x00000000 VSTATUS 20 19 TFT Vertical Status read only 00 VSYNC 01 B
162. LECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued e Came B Endian L Endian rite USB Device Continued 4 DMA CON 0x5200025B 0x52000258 EP4 DMA Interface Control 4 TX HI 0x5200026F 0x5200026C EP4 DMA Total Tx Counter ELECTRONICS 1 33 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued Register Name Address Address Read B Endian L Endian Write Watchdog Timer WTCON 0x53000000 R W Watch Watch Dog TimerMode Timer Mode WTDAT 0x53000004 Watch Dog Timer Data WTCNT 0x53000008 Watch Dog Timer Count Watch Dog Timer Count Timer Count IICCON 0x54000000 Control IICSTAT 0x54000004 Status IICADD 0x54000008 Address IICDS 0x5400000C Data Shift IISCON 0x55000000 02 0x55000000 IIS Control IISMOD 0x55000004 06 0x55000004 IIS Mode IISPSR 0x55000008 0A 0x55000008 IIS Prescaler IISFCON 0x5500000G 0E 0x5500000C HW W IIS FIFO Control IISFIFO 0x55000012 0x55000010 IIS FIFO Entry 1 34 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued Register Address Address Read Function Name B Endian L Endian Write port GPACON 0x56000000 Port A Control GPEDAT 0x56000044 Port E Data GPGCON 0x56000060 Port G Control
163. M9TDMI ARM9TDMI 940 ARM9TDMI core plus cache and protection unit ARM920T ARM9TDMI core plus cache and MMU The ARM9TDMI processor core is a Harvard architecture device implemented using a five stage pipeline consisting of fetch decode execute memory and write stages and can be provided as a stand alone core which can be embedded into more complex devices The stand alone core has a simple bus interface that allows users to design their own caches memory systems around it The ARM9TDMI family of microprocessors supports both the 32 bit ARM and 16 bit Thumb instruction sets allowing the user to trade off between high performance and high code density The ARM920T is a Harvard cache architecture processor which is targeted at multiprogrammer applications where full memory management high performance and low power are all important The separate instruction and data caches in this design are 16KB each in size with an 8 word line length The ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for instruction and data addresses The ARM920T supports the ARM debug architecture and includes logic to assist in both hardware and software debug The ARM920T also includes support for coprocessors exporting the instruction and data buses along with simple handshaking signals The ARM920T interface to the rest of the system is via unified address and data buses This in
164. Master mode a data transfer on the SDA line can be initiated and SCL signal generated A Start condition can transfer a one byte serial data over the SDA line and a Stop condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The IIC bus gets busy when a Start condition is generated Stop condition will make the IIC bus free When a master initiates a Start condition it should send a slave address to notify the slave device One byte of address field consists of a 7 bit address and a 1 bit transfer direction indicator showing write or read If bit 8 is 0 it indicates a write operation transmit operation if bit 8 is 1 it indicates a request for data read receive operation The master will finish the transfer operation by transmitting a Stop condition If the master wants to continue the data transmission to the bus it should generate another Start condition as well as a slave address In this way the read write operation can be performed in various formats Start Stop Condition Condition Figure 20 2 Start and Stop Condition ELECTRONICS 20 3 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length The bytes can be unlimitedly transmitted per transfer The first byte following a Start co
165. NTBn will not be reloaded into the counter The value of TCMPBn is used for pulse width modulation PWM The timer control logic changes the output level when the down counter value matches the value of the compare register in the timer control logic Therefore the compare register determines the turn on time or turn off time of an PWM output FEATURE Five 16 bit timers Two 8 bit prescalers amp Two 4 bit divider Programmable duty control of output waveform PWM Auto reload mode or one shot pulse mode Dead zone generator This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 10 1 PWM TIMER S3C2410X01 RISC MICROPROCESSOR Dead Zone Generator 8 Bit Prescaler Clock Control a Logic1 8 Bit Prescaler Divider Control Logic4 Figure 10 1 16 bit PWM Timer Block Diagram 10 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER PWM TIMER OPERATION PRESCALER amp DIVIDER An 8 bit prescaler and a 4 bit divider make the following output frequencies 4 bit divider settings Minimum resolution Maximum resolution Maximum interval prescaler 0 prescaler 255 TCNTBn 65535 1 2 PCLK 50 0 0400 us 25 0000 10 2400 97 6562 0 6710 sec 1 4 PCLK 50 MHz 0 0800
166. NTERFACE PRELIMINARY OVERVIEW The 10 bit CMOS analog to digital converter ADC of the S3C2410X01 is a recycling typed device with 8 channel analog inputs It converts the analog input signal into 10 bit binary digital codes at a maximum conversion rate of 500KSPS with 2 5MHz A D converter clock The A D converter operates with on chip sample and hold function and power down mode is supported The S3C2410X01 supports Touch Screen Interface which consists of a touch screen panel four external transistors an external voltage source AIN 7 and AIN 5 see Figure 16 2 Touch Screen Interface controls and selects control signals nYPON YMON nXPON and XMON and analog pads AIN 7 AIN 5 which are connected with pads of touch screen panel and the external transistor for X position conversion and Y position conversion Touch Screen Interface contains an external transistor control logic and an ADC interface logic with an interrupt generation logic FEATURES Resolution 10 bit Differential Linearity Error 1 0 LSB Integral Linearity Error 2 0LSB Maximum Conversion Rate 500 KSPS Low Power Consumption Power Supply Voltage 3 3V Analog Input Range 0 3 3V On chip Sample and hold Function Normal Conversion Mode Separate X Y position conversion Mode Auto Sequential X Y Position Conversion Mode Waiting for Interrupt Mode This document is a preliminary user s manual So our
167. NTROLLER 53 2410 RISC MICROPROCESSOR PRIORITY REGISTER PRIORITY PRIORITY 0 4 00000 IRQ priority control register PRIORITY Bit Description 77 Initial State ARB SEL6 20 19 Arbiter 6 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB SEL5 18 17 Arbiter 5 group priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 ARB_SEL4 16 15 Arbiter 4 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB SELS3 14 13 Arbiter 3 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB SEL2 12 11 Arbiter 2 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB SEL1 10 9 Arbiter 1 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB SELO 8 7 Arbiter O group priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 ARB_MODE6 Arbiter 6 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB_MODE5 5 Arbiter 5 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB_MODE4 4 Arbiter 4 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 3 Arbiter 3 group priority rotate enable
168. OM1 Operating Mode 1 OMO Operating Mode 0 Booting ROM Data width Nand Flash Mode eee wc MEMORY SROM SDRAM ADDRESS PIN CONNECTIONS MEMORY ADDR PIN 3C2410X01 ADDR 3C2410X01 ADDR 3C2410X01 ADDR 8 bit DATA BUS 16 bit DATA BUS 32 bit DATA BUS ELECTRONICS 5 3 MEMORY CONTROLLER 3C2410X01 RISC MICROPROCESSOR SDRAM BANK ADDRESS PIN CONNECTION Table 5 2 SDRAM Bank Address Configuration 512K x 16 x 2B 4MB 16Mb EE x 4 x 2B x x 16 x 2B a me 16Mb 2M x 4 x 2B 1M x 8x 2B 8MB 64Mb 4M x 8 x 2B 2M x 8 x 48 T OM x 16 x 28 a 55 1M x 16 x 4B x 1 22 21 512K x 32 4B ae 2M x 4 x 2B x9 64Mb 8M x 4 x 2B 4M x 4 x 4B 2 4M x 8 x 2B 2M x 8 x 4B nes 22 x 2M x 16 x 2B x9 x 16x 4B x2 A 23 22 m AM x 8x 4B x 1 x6 2M x 16 x 4B x 1 64Mb 8M x 4 x 2B 4M x 4 x 4B ned a 4M x 8 x 2B 2M x 8x 4B 4 A 24 23 AM x 8 x 4B 2 2M x 16 x 4B 2 E 256Mb 8M x 8x 4B x 1 4M x 16 x 4B x ia x16 S S 4M x 8 x 4B x A 25 24 4M x 16 x 4B 16M x 8x 48 8M x 8 x 4Bank A 26 25 512Mb 82M x 4 x 4B x2 16M x 8 x 4B 2 5 4 ELECTRONICS 6 6 6 6 6 6 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER nWAIT PIN OPERATION If the WAIT corresponding to each memor
169. ON These instructions move a shifted value between Lo registers The THUMB assembler syntax is shown in Table 4 2 NOTE All instructions in this group set the CPSR condition codes Table 4 2 Summary of Format 1 Instructions THUMB Assembler ARM Equipment _____ LSL Rd Rs Offset5 MOVS Rs LSL Offset5 Shift Rs left by a 5 bit immediate value and store the result in Rd 01 LSR Rd Rs Offset5 MOVS Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store the result in Rd 10 ASR Rad Rs Offset5 MOVS Rs ASR Offset5 Perform arithmetic shift right on Rs by a 5 bit immediate value and store the result in Rd ELECTRONICS 4 5 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 2 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Setcondition codes on the result 4 6 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 2 ADD SUBTRACT 15 14 13 12 11 10 9 8 6 5 3 2 0 mote hm gt 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Vale 9 Opcode 10 Immediate Flag 0 Register operand 1 Imme
170. ONn register and control the signal of nRTS by software In AFC nRTS depends on the condition of the receiver and nCTS signals control the operation of the transmitter The UART s transmitter transfers the data in FIFO only when nCTS signals are activated in AFC nCTS means that other UART s FIFO is ready to receive data Before the UART receives data nRTS has to be activated when its receive FIFO has a spare more than 2 byte and has to be inactivated when its receive FIFO has a spare under 1 byte in AFC nRTS means that its own receive FIFO is ready to receive data Transmission Reception in UART A in UART A Figure 11 2 UART AFC Interface Note UART 2 does not support AFC function because the S3C2410X01 has no nRTS2 and nCTS2 Example of Non Auto Flow control controlling nRTS and nCTS by software Rx operation with FIFO 1 Select receive mode Interrupt or DMA mode 2 Check the value of Rx FIFO count in UFSTATn register If the value is less than 15 users have to set the value of UMCONn 0 to 1 activating nRTS and if it is equal or larger than 15 users have to set the value to 0 inactivating nRTS 3 Repeat the Step 2 Tx operation with FIFO 1 Select transmit mode Interrupt or DMA mode 2 Check the value of UMSTATn O If the value is 1 activating nCTS users write the data to Tx FIFO register 11 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART RS 232C interface If users want to connect
171. PERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate value This value is zero extended to 32 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 WRITING TO R15 When Rd is a register other than R15 the condition code flags in the CPSR may be updated from the ALU flags as described above When is R15 and the flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When is R15 and the flag is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state changes which atomically restore both PC and CPSR This form of instruction should not be used in User mode USING R15 AS AN OPERANDY If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TEQ TST CMP AND CMN OPCODES NOTES TEQ TST CMP and CMN do not write the result of their operation but do set flags in the CPSR An assembler should always set the S
172. R The MCU writes a 1 to flush the FIFO This bit can be set only when OUT_PKT_RDY DO is set The packet due to be unloaded by the MCU will be flushed DATA_ERROR 3 R W Valid only in ISO mode This bit should be sampled with OUT_PKT_RDY When set it indicates the data packet due to be unloaded by the MCU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second packet has an error then this bit gets set only after the first packet is unloaded This bit is automatically cleared when OUT_PKT_RDY gets cleared 385 7 OVER RUN 2 R Clear R W Valid only in ISO mode This bit is set if the core is not able to load an OUT ISO token into the FIFO The MCU clears this bit by writing 0 c 20 o OUT PKT RDY R SET Set by the USB after it has loaded a packet of CLEAR data into the FIFO Once the MCU reads the packet from FIFO this bit should be cleared by MCU write a 0 13 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE OUT_CSR2_REG 0x52000194 L End Point out control status register2 0x52000197 B Description Initial State If the MCU is set whenever the MCU reads data from the OUT FIFO OUT PKT RDY will automatically be cleared by the logic without any intervention from the MCU Determine endpoint transfer type 0 Configures endpoint to Bulk mode 1 Configures endpoint to ISO mode E Determine whether the interrupt should be
173. R MRC cond 15 1 Rd CRn CRm opcode 2 28 27 26 25 2423 212019 16 15 12111098 7 5 4 3 BRIT ene m Figure 2 1 CP15 MRC and MCR Bit Pattern Instructions CDP LDC and STC along with unprivileged MRC and MCR instructions to CP15 will cause the undefined instruction trap to be taken The CRn field of MRC and MCR instructions specifies the coprocessor register to access The CRm field and opcode 2 field are used to specify a particular action when addressing registers Attempting to read from a non readable register or writing to a non writable register will cause unpredictable results The opcode 1 opcode 2 and CRm fields should be zero except when the values specified are used to select the desired operations in all instructions which access CP15 Using other values will result in unpredictable behavior ELECTRONICS 2 5 PROGRAMMER S MODEL ARM920T PROCESSOR Addresses in ARM920T Three distinct types of address exist in an ARM920T system e virtual address VA e modified virtual address MVA physical address Below is an example of the address manipulation when the ARM9TDMI requests an instruction 1 The VA of the instruction IVA is issued by the ARM9TDMI 2 This is translated by the ProcID to the instruction MVA IMVA It is the that the instruction cache and MMU see 3 If the protection check carried out by the IMMU on the IMVA does not abort and the IMV
174. R15 when interrupts and exceptions arise or when Branch and Link instructions are executed within interrupt or exception routines Register 15 holds the Program Counter PC In ARM state bits 1 0 of R15 are zero and bits 31 2 contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC Register 16 is the CPSR Current Program Status Register This contains condition code flags and the current mode bits FIQ mode has seven banked registers mapped to R8 14 R8 fiq R14 fiq In ARM state many FIQ handlers do not need to save any registers User IRQ Supervisor Abort and Undefined each have two banked registers mapped to R13 and R14 allowing each of these modes to have a private stack pointer and link registers ELECTRONICS 2 3 PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR ARM State General Registers and Program Counter System amp User FIQ Supervisor Abort Undefined 2 R1 R2 R3 R4 R5 R7 JJ I R10 R15 PC R15 PC R15 PC RO R2 R8 R5 R6 87 D R8 D R9 fa D R10 fia BRI D R12 D R13 fig fig ARM State Program Status Registers DXSPSR svc P SPSR_abt NSPSR SPSR_und banked register Figure 2 3 Register Organization in ARM State 2 4 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL The THUMB State Register Set The THUMB state register set is a s
175. RONICS 3 7 ARM INSTRUCTION SET ASSEMBLER SYNTAX 53 2410 RISC MICROPROCESSOR Items in are optional Items in lt gt must be present B L cond expression L cond lt expression gt Examples here BAL CMP BEQ ADDS BLCC Used to request the Branch with Link form of the instruction If absent R14 will not be affected by the instruction A two character mnemonic as shown in Table 3 2 If absent then AL ALways will be used The destination The assembler calculates the offset here Assembles to OXEAFFFFFE note effect of PC offset there Always condition used as default R1 0 Compare 1 with zero and branch to fred if R1 was zero otherwise continue fred Continue to next instruction sub ROM Call subroutine at computed address R1 1 Add 1 to register 1 setting CPSR flags onthe result then call subroutine if sub the C flag is clear which will be the case unless R1 held OxFFFFFFFF ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 4 28 27 26 25 24 21 20 19 16 15 12 11 0 mc mc 15 12 Destination register 0 Branch 1 Branch with link 19 16 1st operand register 0 Branch 1 Branch with link 20 Set condition codes 0 Do not after condi
176. RSTOUT 0 1 nRSTOUT 1 Reserved 15 14 Reserved to 00b USBSUSPND1 13 13 USB Port 1 mode 0 Normal 1 Suspend USBSUSPNDO 12 12 USB Port 0 mode 0 Normal 1 Suspend CLKSEL1 10 8 CLKOUT1 output singnal source 000 MPLL CLK 001 UPLLCLK 010 FCLK 011 HCLK 100 PCLK 101 DCLK1 11x Reserved mee mh mm CLKSELO 6 4 CLKOUTO output singnal source 000 MPLL CLK 001 UPLLCLK 010 FCLK 011 HCLK 100 PCLK 101 DCLKO 11x Reserved USBPAD 3 0 Use pads related USB for USB device 1 Use pads related USB for USB host mew SPUCR1 1 DATA 31 16 port pull up resister 0 Enabled 1 Disabled SPUCRO DATA 15 0 port pull up resister 0 Enabled 1 Disabled Note CLKOUT is prepared only for monitoring an internal clock situation On Off status or frequency ELECTRONICS 9 21 PORTS 53 2410 01 RISC MICROPROCESSOR DCLK CONTROL REGISTERS DCLKCON This register defines DCLKn signals which work as clocks for external sources See the following figure for how to make the DCLKn signals The DCLKCON can actually operate only when CLKOUTT 1 0 is set to send the DCLKn signals DCLKCON 0x56000084 DCLKO 1 control register DCLK1CMP 27 24 DCLK1 Compare value clock toggle value lt DCLK1DIV If the DCLK1DIV is n Low level duration is n 1 High level duration is DCLK1DIV 1 1 DCLK1DIV 23 20 DCLK1 Divide value DCLK1 frequency source clock
177. Rising edge triggered 11x Both edge triggered E EINT13 22 20 Set the signaling method of the EINT13 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered D EINT12 18 16 Set the signaling method of the EINT12 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered ns EINT11 14 12 Set the signaling method of the EINT11 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered m EINT10 10 8 Set the signaling method of the EINT10 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT9 6 4 Set the signaling method of the EINT9 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT8 2 0 Set the signaling method of the 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 9 24 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PORTS FLTEN23 31 Filter Enable for EINT23 0 Disable 1 Enable EINT23 30 28 Set the signaling method of the EINT23 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN22 Filter Enable for EINT22 0 Disable 1 Enable EINT22 26
178. S and Harvard cache architecture with separate 16KB instruction and 16KB data caches each with an 8 word line length By providing a complete set of common system peripherals the S3C2410X01 minimizes overall system costs and eliminates the need to configure additional components The integrated on chip functions that are described in this document include 1 8V int 1 8V 2 5V 3 3V memory 3 3V external I O microprocessor with 16KB 16 D Cache MMU e External memory controller SDRAM Control and Chip Select logic LCD controller up to 4K color STN and 256K color TFT with 1 ch LCD dedicated DMA 4 ch DMAs with external request pins 3 ch UART IrDA1 0 16 Byte Tx FIFO and 16 Byte Rx FIFO 2 ch SPI e 1 ch multi master IIC BUS 1 ch IIS BUS controller SD Host interface version 1 0 amp Multi Media Card Protocol version 2 11 compatible e 2 port USB Host 1 port USB Device ver 1 1 4 ch PWM timers amp 1 ch internal timer e Watch Dog Timer 117 bit general purpose I O ports 24 ch external interrupt source Power control Normal Slow Idleand Power off mode 8 ch 10 bit ADC and Touch screen interface RTC with calendar function e On chip clock generator with PLL This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 1 1
179. S pin is controlled by MSTR bit of SPCONn register The direction of nSS pin is always input When the SPI is a master nSS pin is used to check multi master error provided the SPPIN s ENMUL bit is active and another GPIO should be used to select a slave If the SPI is configured as a slave the nSS pin is used to select SPI as a slave by one master SPPINO 0x59000008 SPI channel 0 pin control register SPPIN1 0x59000028 SPI channel 1 pin control register SPPINn Bit Description Initial State 73 Multi Master The SS pin is used as an input to detect multi master error when the SPI error detect system is a master Enable 0 disable general purpose ENMUL 1 multi master error detect enable This bit should be 77 Master Out Determine MOSI drive or release when 1byte transmit is completed only Keep KEEP master 0 release 1 drive the previous level The SPIMISO MISO and SPIMOSI MOSI data pins are used for transmitting and receiving serial data When the SPI is configured as a master SPIMISO MISO is the master data input line SPIMOSI MOSI is the master data output line and SPICLK SCK is the clock output line When the SPI becomes a slave these pins perform reversed roles In a multiple master system SPICLK SCK pins SPIMOSI MOSI pins and SPIMISO MISO pins are tied to configure a group respectively A master SPI can experience a multi master error when other SPI device working as a master select
180. SSOR I O PORTS PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER GPACON GPHCON In the S3C2410X01 most pins are multiplexed So It is require to determine which function is selected for each pin port control register PRCON determines the function of each pin If GPFO GPF7 and GPGO GPG7 are used for wakeup signals in Power OFF mode these ports must be configured in Interrupt mode PORT DATA REGISTER GPADAT GPHDAT If ports are configured as output ports data can be written to the corresponding bit of the PnDAT If ports are configured as input ports the data can be read from the corresponding bit of the PnDAT PORT PULL UP REGISTER GPBUP GPHUP The port pull up register controls the pull up resister enable disable of each port group When the corresponding bit is 0 the pull up resister of the pin is enabled When 1 the pull up resister is disabled If the port pull up register is enabled the pull up resisters work without pin s functional setting input output DATAn EINTn etc MISCELLANEOUS CONTROL REGISTER This register controls DATA port pull up resister hi z state USB pad and CLKOUT selection EXTERNAL INTERRUPT CONTROL REGISTER EXTINTn The 24 external interrupts are requested by various signaling methods The EXTINTn register configures the signaling method among the low level trigger high level trigger falling edge trigger rising edge trigger and both edge trigger for the external interrupt
181. SSOR I O PORTS PORT D CONTROL REGISTERS GPDCON GPDDAT and GPDUP Pull up disable register for port D Reserved oxse000006 Undefined GPD15 31 30 00 Input 01 Output 10 VD23 11 nSS0 GPD14 29 28 00 Input 01 Output 10 VD22 11 2 nSS1 GPD13 27 26 00 Input 01 Output 10 VD21 11 Reserved GPD12 25 24 00 Input 01 Output 10 VD20 11 Reserved GPD11 23 22 00 Input 01 Output 10 019 11 Reserved GPD10 21 20 00 Input 01 Output 10 VD18 11 Reserved GPD9 19 18 00 Input 01 Output 10 VD17 11 Reserved GPD8 17 16 00 Input 01 Output 10 VD16 11 Reserved GPD7 15 14 00 Input 01 Output 10 VD15 11 Reserved GPD6 13 12 00 Input 01 Output 10 VD14 11 Reserved GPD5 11 10 00 Input 01 Output 10 VD13 11 Reserved GPD4 00 Input 01 Output 10 VD12 11 Reserved GPD3 7 6 00 Input 01 Output 10 VD11 11 Reserved GPD2 5 4 00 Input 01 Output 10 VD10 11 Reserved GPD1 3 2 00 Input 01 Output 10 VD9 11 Reserved GPDO 1 0 00 Input 01 Output 10 VD8 11 Reserved ELECTRONICS 9 13 PORTS 53 2410 01 RISC MICROPROCESSOR GPD 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin
182. SSOR REAL TIME CLOCK BCD HOUR BCDHOUR REGISTER BCDHOUR 0x57000078 L R W BCD hour register Undefined 0x5700007B B by byte ml HOURDATA 5 4 BCD value for hour 0 2 Bo BCD DATE BCDDATE REGISTER BCDDATE 0x5700007C L BCD date register Undefined 0x5700007F B by byte mm LE DATEDATA 5 4 BCD value for date 8 po 0 BCD DAY BCDDAY REGISTER BCDDAY 0x57000080 L R W BCD a day of the week register Undefined 0x57000083 B by byte DATEDAY 2 0 Ren value for a day of the week Esempi p 1 ELECTRONICS 17 9 REAL TIME CLOCK S3C2410X01 RISC MICROPROCESSOR BCD MONTH BCDMON REGISTER BCDMON 0x57000084 L R W BCD month register Undefined 0x57000087 B by byte gg 4 BCD value for month 0 1 BCD YEAR BCDYEAR REGISTER BCDYEAR 0x57000088 L R W BCD year register Undefined 0x5700008B B by byte YEARDATA 7 0 BCD value for year 00 99 17 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR WATCH DOG TIMER 05 22 2002 WATCHDOG TIMER Preliminary OVERVIEW The S3C2410X01 watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors It can be used as a normal 16 bit interval timer to request interrupt service The watchdog timer generates the reset signal for 128 PCLK cycles FEATURES Nor
183. STAT2 in the UART block UFSTATO 0x50000018 R UART channel 0 FIFO status register 0x00 UFSTAT1 0x50004018 UART channel 1 FIFO status register UFSTAT2 0 50008018 UART channel 2 FIFO status register Reserved sf Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 byte lt Tx FIFO data lt 15 byte 1 Full hi mu Rx FIFO Full Set to 1 automatically whenever receive FIFO is full during receive operation 0 0 byte lt Rx FIFO data lt 15 byte 1 Full Tx FIFO Count 7 4 Number of data in Tx FIFO Rx FIFO Count 3 0 Number of data in Rx FIFO ELECTRONICS 11 17 UART 53 2410 01 RISC MICROPROCESSOR UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTATO UMSTAT1 and UMSTAT2 in the UART block UMSTATO 0x5000001C R UART channel 0 Modem status register UMSTAT1 0x5000401C oR UART channel 1 Modem status register aa af Delta CTS 2 Indicate that the nCTS input to the S3C2410X01 has changed state since the last time it was read by CPU Refer to Figure 11 8 0 Has not changed 1 Has changed nl Clear to Send 0 CTS signal is not activated nCTS pin is high 1 CTS signal is activated nCTS pin is low Delta CTS Read_UMSTAT Figure 11 8 nCTS and Delta CTS Timing Diagram 11 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART UART TRANSMIT BUFFER REGISTER HOLDING REGIST
184. SUSPEND MODE 1 SET Set by USB automatically when the device enter CLEAR into suspend mode It is cleared under the following conditions 1 The MCU clears the RESUME bit by writing 0 in order to end remote resume signaling 2 The resume signal form host is received SUSPEND EN R W Suspend mode enable control bit 0 Disable default The device will not enter suspend mode 1 Enable suspend mode MCU RESUME 2 R W R Set by the MCU for MCU Resume CLEAR The USB generates the resume signaling during 10ms if this bit is set in suspend mode 13 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE INTERRUPT REGISTER EP_INT_REG USB_INT_REG The USB core has two interrupt registers These registers act as status registers for the MCU when it is interrupted The bits are cleared by writing a 1 not 0 to each bit that was set Once the MCU is interrupted MCU should read the contents of interrupt related registers and write back to clear the contents if it is necessary Register Address R W Description Reset Value EP_INT_REG 0x52000148 L R W EP interrupt pending clear register 0x00 0x5200014B B byte EP_INT_REG MCU Description Initial State EP1 EP4 For BULK INTERRUPT IN endpoints Interrupt Set by the USB under the following conditions 1 IN PKT RDY bit is cleared 2 FIFO is flushed 3 SENT STALL set For BULK INTERRUPT OUT endpoints Set by the USB under the following conditi
185. TALL CLE AR protocol violation An interrupt is generated when this bit is set The MCU should write 0 to clear this bit IN PKT RDY SET CLEAR Set by the MCU after writing a packet of data into EPO FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so as the MCU to load the next packet For a zero length data phase the MCU sets DATA END at the same time OUT PKT RDY SET Set by the USB once a valid token is written to the FIFO An interrupt is generated when the USB sets this bit The MCU clears this bit by writing a 1 to the SERVICED OUT PKT RDY bit D ELECTRONICS 13 13 4 3 2 1 USB DEVICE 53 2410 01 RISC MICROPROCESSOR END POINT IN CONTROL STATUS REGISTER IN_CSR1_REG IN_CSR2_REG IN_CSR1_REG 0x52000184 L R W IN END POINT control status register1 0x00 0x52000187 B byte IN CSR1 REG Reserved CLR DATA TOGGLE SENT STALL SEND STALL FIFO FLUSH CLEAR UNDER RUN R Set CLEAR m PKT RDY CLEAR 13 14 Description Initial State Used in Set up procedure 0 There are alternation of DATAO and DATA1 1 The data toggle bit is cleared and PID in packet will maintain DATAO Set by the USB when an IN token issues a STALL handshake after the MCU sets SEND_ STALL bit to start STALL handshaking When the USB issues a STALL handshake IN PKT RDY is cleared 0 The MCU clears
186. TERS Each DMA channel has nine control registers 36 in total since there are four channels for DMA controller Six of the control registers control the DMA transfer and other three ones monitor the status of DMA controller The details of those registers are as follows DMA INITIAL SOURCE DISRC REGISTER DISRCn i Description Initial State S_ADDR Base address start address of source data to transfer This bit 0x00000000 value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1 DMA INITIAL SOURCE CONTROL DISRCC REGISTER Bit 1 is used to select the location of source 0 the source is in the system bus AHB 1 the source is in the peripheral bus APB Bit 0 is used to select the address increment 0 Increment 1 Fixed If it is 0 the address is increased by its data size after each transfer in burst and single transfer mode If itis 1 the address is not changed after the transfer In the burst mode address is increased during the burst transfer but the address is recovered to its first value after the transfer ELECTRONICS 8 7 DMA 3C2410X01 RISC MICROPROCESSOR DMA INITIAL DESTINATION DIDST REGISTER DIDSTO ox4b000008 RW 0 initial destination register 0x00000000 DIDST1 0x4b000048 DMA 1 initial destination register 0x00000000 DIDST2 0x4b000088 DMA 2 initial destination register 0x00000000 DIDST3 0x4b0000c8 E DMA 3 initial destination register 0x00000000
187. THUMB INSTRUCTION SET THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restrictions by 16 bit format is fully notified for using the Thumb instructions ELECTRONICS 4 1 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure 15 14 13 12 11 10 Move Shifted register Add subtract Move compare add subtract immediate ALU operations 2 5 NM Hi register operations branch exchange Word8 PC relative load Load store with register offset 1 1 H S 1 Load store sign extended byte halfword Load store with immediate offset ol Load store halfword MGE _ SP relativeloadistore EN SP ma 24 2 Add offset to stack pointer Pushipop register a _ Multiple load store cons Sotses Conditional branch Software interrupt Offset1 1
188. USER S MANUAL 53 2410 32 Bit RISC Microprocessor Revision 0 1 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW 05 22 2002 PRODUCT OVERVIEW PRELIMINARY INTRODUCTION This manual describes SAMSUNG s 53 2410 01 16 32 bit RISC microprocessor This product is designed to provide hand held devices and general applications with cost effective low power and high performance micro controller solution in small die size To reduce total system cost S3C2410X01 includes the following components separate 16KB Instruction and 16KB Data Cache MMU to handle virtual memory management LCD Controller STN amp TFT NAND Flash Boot Loader System Manager chip select logic and SDRAM Controller 3 ch UART 4 ch DMA 4 ch Timers with PWM I O Ports RTC 8 ch 10 bit ADC and Touch Screen Interface IIC BUS Interface IIS BUS Interface USB Host USB Device SD Host amp Multi Media Card Interface 2 ch SPI and PLL for clock generation The 53 2410 01 was developed using an 920 core 0 18um CMOS standard cells and a memory complier Its low power simple elegant and fully static design is particularly suitable for cost and power sensitive applications It adopts a new bus architecture called Advanced Microcontroller Bus Architecture AMBA The 53 2410 01 offers outstanding features with its CPU core 16 32 bit ARM920T RISC processor designed by Advanced RISC Machines Ltd The ARM920T implements MMU AMBA BU
189. VDD 3 3V SCLK up to 100MHz 2 5V SCLK up to 85MHz 1 8V SCLK up to 66MHz VSSOP P 53 2410 port VSS pes RTC VDD 1 8 V Not support 3 3V This pin must be connected to power properly if RTC isn t used P 5362410 and aigra voo asy P S302 10UPLLanaloganddgialVSS Apc P 92020 O O P Notes 1 means input output 2 means analog input analog output 3 ST means schmitt trigger 4 P means power ELECTRONICS 1 23 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR 3C2410 Special Registers Table 1 3 S3C2410 Special Registers uer de Cas _ Name B Endian L Endian Write BANKCON4 0x48000014 BANK4 Control 1 24 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued Basil FA tae a cU 0c B Endian L Endian Write USB Host Controller Control and Status Group HcDoneHead 0x49000030 Frame Counter Group HcLSThreshold 0x49000044 Interrupt Controller Interrupt Controller SRCPND 0X4A000000 Interrupt Request Status INTMOD 0X4A000004 EE Interrupt Mode Control INTMSK 0X4A000008 Interrupt Mask Control Memory Pointer Group PRIORITY 0X4A00000C INTPND 0X4A000010 INTOFFSET 0X4A000014 SUBSRCPND 0X4A000018 INTSUBMSK 0X4A00001C NN IRQ Priority Control Interrupt Request Stat
190. VICE CONTROLLER OVERVIEW Universal Serial Bus USB device controller is designed to provide a high performance full speed function controller solution with DMA interface USB device controller allows bulk transfer with DMA interrupt transfer and control transfer USB device controller supports Full soeed USB device controller compatible with the USB specification version 1 1 DMA interface for bulk transfer Five endpoints with FIFO EPO 16byte Register EP1 64byte IN OUT FIFO EP2 64byte IN OUT FIFO EP3 64byte IN OUT FIFO EP4 64byte IN OUT FIFO dual port asynchronous RAM dual port asynchronous RAM dual port asynchronous RAM dual port asynchronous RAM interrupt or DMA interrupt or DMA interrupt or DMA interrupt or DMA Integrated USB Transceiver FEATURE Fully compliant with USB Specification Version 1 1 Full speed 12Mbps device Integrated USB Transceiver Supports control interrupt and bulk transfer Five endpoints with FIFO One bi directional control endpoint with 16 byte FIFO EPO Four bi directional bulk endpoints with 64 byte FIFO EP1 EP2 EP3 and EP4 Supports DMA interface for receive and transmit bulk endpoints EP1 EP2 EP3 and EP4 Independent 64byte receive and transmit FIFO to maximize throughput Supports suspend and remote wakeup function This document is a preliminary user s manual So our company will present its revision as of the date on t
191. X tal or EXTCLK FCLK gt 3X tal or 3EXTCLK 7 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT MPLLCAP UPLLCAP P 5 0 4 M M 7 0 External Divider Moll Upll S 1 0 S Figure 7 2 PLL Phase Locked Loop Block Diagram Fret Loop Filter R Internal External OSC a X TAL oscillation OM 3 2 00 b External clock source OM 3 2 11 Figure 7 3 Main Oscillator Circuit Examples ELECTRONICS 7 5 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used i e the PLL clock Mpll or the direct external clock XTIpll or EXTCLK When PLL is configured to a new frequency value the clock control logic disables the FCLK until the PLL output is stabilized using the PLL locking time The clock control logic is also activated at power on reset and wakeup from power down mode Power On Reset XTIpll Figure 7 4 shows the clock behavior during the power on reset sequence The crystal oscillator begins oscillation within several milliseconds When nRESET is released after the stabilization of OSC clock the PLL starts to operate according to the default PLL configuration However PLL is commonly known to be unstable after power on reset so Fin is fed directly to FCLK instead of the Mpll PLL output before the software newly configures the PLLCON Even if the u
192. Z SBZ Invalidate ICache single entry using MVA Prefetch ICache line using MVA Invalidate DCache single entry using MVA MVA format MCR p15 0 Rd c7 c6 1 Clean DCache single entry using MVA MVA format MCR 15 0 7 10 1 Clean and Invalidate DCache entry using MVA MVA format MCR p15 0 Rd c7 c14 1 Clean DCache single entry using index MCR p15 0 Rd c7 c10 2 Clean and Invalidate DCache entry using index Index format MCR p15 0 Rd c7 c14 2 Drain write buffer 1 MCR p15 0 Rd c7 c10 4 Wait for interrupt 2 MCR p15 0 Rd c7 c0 4 NOTES 1 Will stop execution until the write buffer has drained 2 Will stop execution in a LOW power state until an interrupt occurs 2 16 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL The operations which can be carried out upon a single cache line identify the line using the data passed in the MCR instruction The data is interpreted using one of the following formats 31 SBZ Figure 2 2 Register 7 MVA Format 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 54321 SBZ SBZ Figure 2 3 Register 7 Index Format The use of register 7 is discussed in Chapter 4 Caches Write Buffer and Physical Address TAG PATAG RAM ELECTRONICS 2 17 PROGRAMMER S MODEL ARM920T PROCESSOR REGISTER 8 TLB OPERATIONS Register 8 is write only register used to manage the translation lookaside buffers TLBs the instruction TLB and the data TLB Five o
193. ___ owe fe T4 wozmssuGPD cro owe 6 P womssooepis apo 1 wpm P P P 4 7704 vsem P e P Ts me voo e P dio Rs vss P 75 eseo owe PS esoo owe 1 N onoukere2 e owe 6 Us essowssuepes ome 1 Us esspowsspvePEs ome 3 fe om 1 8 P6 ares 6 R6 SDDATO GPE7 GPE7 2 t8 NI _ __ ae 1 fe P7 soares area _ wae RT _ __ oreo me ae T7 semsoweren are __ Hae fe Ur are __ Hae fe P8 soomes Gem __ fe Mr P P P de vssiam vsem e P s L7 wscuoeea area ma me __ _ Hae 8 R amp enee 6960 fe us entserer Goa T eriomssoarce 1 ELECTRONICS 1 11 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 1 272 Pin FBGA Pin Assignments Continued Default I O State I O State State Function QBUS REQ PWR off nRESET EINT12 LCD_PWREN GPG4 O L t8 GPG4 Us Jmmnasemsoveres Gras _ ma 1
194. ____ Um 3 3V Interface 5V 6 5 Tolerant input buffer DC Output Voltage 3 3V Output buffer DC Input Current 200 Storage Temperature Tera 65 to 150 C RECOMMENDED OPERATING CONDITIONS Table 24 2 Recommended Operating Conditions Ram p DC Input Voltage 3 3V Input buffer 3 3 0 3 3 3V Interface 5V 3 0 5 25 Tolerant input buffer DC Voltage Vout 3 3V ae buffer This document is a preliminary user s manual am So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 1 ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR D C ELECTRICAL CHARACTERISTICS Table 24 3 and 24 4 define the DC electrical characteristics for the standard LVCMOS buffers Table 24 3 Normal I O PAD DC Electrical Characteristics Vpp 3 3V 0 3V 40 to 85 Parameters Type max Uni IH High level input voltage Vi Low level input voltage LVCMOS interface Stein est Vr Schmit wager postive going ovs 20 fv lt lt lt Schmit rigger negatve going iveshold_Jomos os V li High level input current e lu Low level input current Input buffer 0 10 Tnputbuterwin pute ________ High level output voltage o VoL Low level output volt
195. a DMA request at every specific time The timer keeps DMA request signals nDMA REQ low until the timer receives an ACK signal When the timer receives the ACK signal it makes the request signal inactive The timer which generates the DMA request is determined by setting DMA mode bits in TCFG1 register If one of timers is configured as DMA request mode that timer does not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation ww o ow 9 9 ww me or o ow 9 9 ww me ov e 9 9 wn me ov ow om o av ww me ov on ov or av wm me ow on ov ov em moser ow o am 9 9 UU UU UU UU UU UU UU UU INT4tmp _ 101 nDMA_ACK nDMA_REQ INT4 Figure 10 8 Timer4 DMA Mode Operation 10 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTERO TCFGO Timer input clock Frequency PCLK prescaler value 1 divider value prescaler value 0 255 divider value 2 4 8 16 TCFGO 0x51000000 Configures the two 8 bit prescalers 0x00000000 Bit Description Initial State 31 24 Dead zone length 23 16 These 8 bits determine the dead zone length The 1 unit time 0x00 of the dead zone length is equal to that of timer 0 15 8 These 8 bits determine prescaler value for Timer 2 3
196. accept the data and a coprocessor will only respond if its number matches the contents of this field The CRd field and the bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors but by convention CRd is the register to be transferred or the first register where more than one is to be transferred and the N bit is used to choose one of two transfer length options For instance N 0 could select the transfer of a single register and N21 could select the transfer of all the registers for context switching ADDRESSING MODES ARM920T is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to U 1 or subtracted from U 0 the base register Rn this calculation may be performed either before P 1 or after P 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always writ
197. acceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 11 incremental cycles to execute where S N and are defined as sequential S cycle non sequential and internal I cycle respectively ASSEMBLER SYNTAX lt SWP gt cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers Examples SWP RO R1 R2 Load RO with the word addressed by R2 and store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and Store bits 0 to 7 of R3 at R4 SWPEQ RO RO R1 Conditionally swap the contents of the word addressed by R1 with RO 3 48 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 28 27 24 23 0 1111 Comment Field Ignored by Processor 31 28 Condition Field Figure 3 24 Software Interrupt Instructio
198. ach line was loaded is stored in the PA TAG RAM and is used when writing modified lines back to memory A linefill always loads a complete 8 word line When a store hits in the DCache if the memory region is WB the associated dirty bit is set marking the appropriate half line as being modified If the cache line is replaced due to a linefill or if the line is the target of a DCache clean operation the dirty bits are used to decide whether the whole half or none of the line is written back to memory The line is written back to the same physical address from which it was loaded regardless of any changes to the MMU translation tables The DCache implements allocate on read miss Random or round robin replacement can be selected under software control via the RR bit CP15 register 1 bit 14 Random replacement is selected at reset Data can also be locked in the DCache such that it cannot be overwritten by a linefill This operates with a granularity of 1 64th of the cache which is 64 words 256 bytes All data accesses are subject to MMU permission and translation checks Data accesses which are aborted by the MMU will not cause linefills or data accesses to appear on the ASB For clarity the C bit bit 2 in CP15 register 1 is referred to as the Ccr bit throughout the following text ELECTRONICS 4 5 CACHES WRITE BUFFER ARM920T PROCESSOR DATA CACHE AND WRITE BUFFER ENABLE DISABLE On reset all DCache entries are invalidated the D
199. ack at the end of the second cycle of the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the base second or later in the transfer order will store the modified value will always overwrite the updated base if the base is in the list DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH This can happen on any transfer during a multiple register load or store and must be recoverable if ARM920T is to be used in a virtual memory system Abort during STM Instructions If the abort occurs during a store multiple instruction ARM920T takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When ARM920T detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible e Ov
200. ad the CPSR along with the PC or force transfer of user bank when in privileged mode Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes The equivalence between the names and the values of the bits in the instruction are shown in the following table 3 6 Table 3 6 Addressing Mode Names Name omr tw um Post nerementLoad two ia 3 9 1 PeDermetlod ea 3 9 Post Decrement Load Pre icrement Sire sm sme o 1 Postincrement Stor ster sma o 9 Pre Decrement Store Ssmo sme o 1 9 Post Decrement store smeo sma o 9 9 FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to a full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or descending If ascending a STM will go up and LDM down if descending vice versa IA IB DA DB allow control when LDM STM are not being used for stacks and simply mean Increment After Increment Before Decrement After Decrement Before ELECTRONICS 3 45 ARM INSTRUCTION SET EXAMPLES LDMFD __ SPI1 RO R1 R2 STMIA RO RO R15 LDMFD __ SPI R15 LDMFD _ SPI R15 4 STMFD R13 RO
201. age i LL MEN NN REI E In eem eet dp qe Note Type B6 means 6mA output driver cell Type B8 means 8mA output driver cell Type B12 means 12mA output driver cells 24 2 ELECTRONICS 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 Table 24 4 USB DC Electrical Characteristics Symbol Parameter Condition Min Unit 2 Fe 45 mcam f Ti florists o Vor fremme fe we v Vor Static Output Low 1 5Kohm to 3 6V This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 3 ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR A C ELECTRICAL CHARACTERISTICS tXTALCYC 1 2 VDD 1 2 VDD The clock input from the X pin Figure 24 1 XTIpll Clock Timing tEXTCYC tEXTHIGH tEXTLOW gt VIH VIH 1 2 VDD 1 2 VDD Note The clock input from the EXTCLK pin Figure 24 2 EXTCLK Clock Input Timing 24 4 ELECTRONICS 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 EXTCLK tEX2HC 4 HCLK internal HCLK internal CLKOUT HCLK Figure 24 4 HCLK CLKOUT SCLK in case that EXTCLK is used This document is a preliminary user s manual So our company will present its revision as of the d
202. ake effect only after the finish of current transfer i e when CURR_TC becomes 0 On the other hand any change made to other registers and or fields takes immediate effect Therefore be careful in changing those registers and fields ELECTRONICS 8 13 DMA NOTES 3C2410X01 RISC MICROPROCESSOR ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS 05 22 2002 INPUT OUTPUT PORTS Preliminary OVERVIEW The 53 2410 01 has 117 multi functional input output port pins The ports are Port A GPA 23 output port Port B GPB 11 input output port Port C GPC 16 input output port Port D GPD 16 input output port Port E GPE 16 input output port Port F GPF 8 input output port Port G GPG 16 input output port Port H GPH 11 input output port Each port can be easily configured by software to meet various system configurations and design requirements You have to define which function of each pin is used before starting the main program If a pin is not used for multiplexed functions the pin can be configured as I O ports Initial pin states are configured seamlessly to avoid problems This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 9 1 PORTS 53 2410 01 RISC MICROPROCESSOR Table 9 1 53 2410
203. al Sampling Clock HCLK These two HCLKs may cause confusion So note that HCLK of the 53 2410 01 is HCLK and other HCLK of the LTS350 is LCD HCLK Check that the HCLK of SEC TFT LCD panel LTS350Q1 PD1 and PD2 is changed to LCD HCLK This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 23 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR VIRTUAL DISPLAY TFT STN S3C2410X01 supports hardware horizontal or vertical scrolling If the screen is scrolled the fields of LCDBASEU and LCDBASEL in LCDSADDR1 2 registers need to be changed see Figure 15 8 except the values of PAGEWIDTH and OFFSIZE The video buffer in which the image is stored should be larger than the LCD panel screen in size PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen This is the data of line 1 of virtual screen This is the fata of line 2 of virtual screen This is the data of line 2 of virtual screen This is the data of line 3 of virtual screen This is the data of line 3 of virtual screen This is the of line 4 of virtual This is the data of line 4 of virtual screen LINEVAL 1 This Js the data of line 5 of virtual seen This is the data of line 5 of virtual screen is the data of line 6 of virtual screen This is the data of line 6 of virtual screen 5
204. alling edge triggered 10x Rising edge triggered 11x Both edge triggered ELECTRONICS 9 25 PORTS 3C2410X01 RISC MICROPROCESSOR External Interrupt Filter Register EINTFLTn The EINTFLTn controls the length of filter for 8 external interrupts EINT 23 16 EINTFLTO 0x56000094 Reserved EINTFLT2 0x5600009C BECA External interrupt control register 2 00 EINTFLT3 0x4C6000A0 External interrupt control register 3 FLTCLK19 31 Filter clock of EINT19 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT19 30 24 Filter width of EINT19 FLTCLK18 23 Filter clock of EINT18 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT18 22 16 Filter width of EINT18 FLTCLK17 15 Filter clock of EINT17 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT17 14 8 Filter width of EINT17 FLTCLK16 7 Filter clock of EINT16 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT16 6 0 Filter width of EINT16 FLTCLK23 31 Filter clock of EINT23 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT23 30 24 Filter width of EINT23 FLTCLK22 23 Filter clock of EINT22 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT22 22 16 Filter width of EINT22 FLTCLK21 15 Filter clock of EINT21 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT21 14 8 Filter width of EINT21 FLTCLK20 7 Filter clock of EINT20 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT20 feo Filter width of EINT
205. ampling of the information Making the appropriate bit settings to the SDIPRE register depends on the transmission frequency You can modify its frequency to adjust the baud rate data register value Programming Procedure common SDI modules can be programmed following these basic steps 1 Set SDICON to configure properly with clock and interrupt 2 Set SDIPRE to configure with a proper value 3 Wait 74 SDCLK clock cycle in order to initialize the card CMD Path Programming 1 Write command argument 32 bit to SDICARG register 2 Determine command types and start command by setting SDICCON 8 3 Confirm the end of SDI command operation when the specific flag of SDICSTA is set If the type of command is no response the flag is SDICSTA 1 1 If the type of command is with response the flag is SDICSTA 9 4 Clear the corresponding flag of the SDICSTA register by writing one to the flag bit DAT Path Programming 5 Write timeout period to SDIDTIMER register 6 Write block size block length to SDIBSIZE register normally 0x200 byte 7 Determine the mode of block wide bus DMA etc and start data transfer with setting SDIDCON register 8 Write Tx data to SDIDAT register while Tx FIFO is available by checking SDIFSTA available half or empty register 9 Read Rx data from SDIDAT register while Rx FIFO is available by checking SDIFSTA available half or be last data register 10 Confirm the end of SDI data o
206. an address must be used In the big endian mode B endian address must be used The special registers have to be accessed for each recommended access unit All registers except ADC registers RTC registers and UART registers must be read written in word unit 32bit at little big endian Make sure that the ADC registers RTC registers and UART registers be read written by the specified access unit and the specified address Moreover one must carefully consider which endian mode is used W 32 bit register which must be accessed by LDR STR or int type pointer int HW 16 bit register which must be accessed by LDRH STRH or short int type pointer short int B 8 bit register which must be accessed by LDRB STRB or char type pointer char int ELECTRONICS 1 39 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR NOTES 1 40 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL PROGRAMMER S MODEL OVERVIEW 53 2410 has been developed using the advanced ARM920T core which has been designed by Advanced RISC Machines Ltd PROCESSOR OPERATING STATES From the programmer s point of view the ARM920T can be in one of two states e ARM state which executes 32 bit word aligned ARM instructions e THUMB state which can execute 16 bit halfword aligned THUMB instructions In this state the PC uses bit 1 to select between alternate halfwords NOTES Transition between these two states does not affect the proce
207. anch if N set and V set or N clear and V clear greater or equal 1011 BLT label BLT label Branch if N set and V clear or N clear and V set less than 1100 BGT label BGT label Branch if Z clear and either N set and V set or N clear and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be halfword aligned ie with bit O set to O since the assembler actually places label gt gt 1 in field SOffset8 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 1 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES CMP 45 Branch to over if RO gt 45 BGT over Note that the THUMB opcode will contain the number of halfwords to offset over Must be halfword aligned ELECTRONICS 4 35 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 17 SOFTWARE INTERRUPT 15 14 13 12 11 10 7 0 1 9 8 ptt ve _____ 7 0 Comment Field Figure 4 18 Format 17 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM state and enters Supervisor SV
208. and UCON2 in the UART block UART UCONO 0x50000004 RAN UART channel 0 control register UCON1 0x50004004 UART channel 1 control register UCON2 0x50008004 UART channel 2 control register serine Clock Selection Tx Interrupt Type Rx Interrupt Type Rx Time Out Enable Rx Error Status Interrupt Enable Loopback Mode Send Break Signal ELECTRONICS Select PCLK or UCLK for the UART baud rate 0 PCLK UBRDIVn int PCLK bps x 16 1 UCLK UBRDIVn int UCLK bps x 16 Interrupt request type 0 Pulse Interrupt is requested as soon as the Tx buffer becomes empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode 1 Level Interrupt is requested while Tx buffer is empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode Interrupt request type 0 Pulse Interrupt is requested the instant Rx buffer receives the data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode 1 Level Interrupt is requested while Rx buffer is receiving data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode Enable Disable Rx time out interrupt when UART FIFO is enabled The interrupt is a receive interrupt 0 Disable 1 Enable Enable the UART to generate an interrupt upon an exception such as a break frame error parity error or overrun error during a receive operation 0 Do not generate receive error status interrupt 1 Generate rec
209. and setting the corresponding bit of INTMSK to 0 Interrupt Mode 920 has two types of Interrupt mode or IRQ All the interrupt sources determine which mode is used at interrupt request Interrupt Pending Register The 53 2410 01 has two interrupt pending resisters source pending register SRCPND and interrupt pending register INTPND These pending registers indicate whether or not an interrupt request is pending When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1 and at the same time only one bit of the INTPND register is set to 1 automatically after arbitration procedure If interrupts are masked the corresponding bits of the SRCPND register are set to 1 This does not cause the bit of INTPND register changed When a pending bit of the INTPND register is set the interrupt service routine starts whenever the flag or F flag is cleared to 0 The SRCPND and INTPND registers can be read and written so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method Interrupt Mask Register This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1 If an interrupt mask bit of INTMSK is 0 the interrupt will be serviced normally If the corresponding mask bit is 1 and the interrup
210. apping between the ARM9TDMI and the Caches and MMU Virtual address VA Modified virtual address MVA issued by ARM9TDMI input to caches and MMU Figure 2 8 Address Mapping Using CP15 Register 13 ELECTRONICS 2 23 PROGRAMMER S MODEL ARM920T PROCESSOR Changing the ProcID performing a fast context switch A fast context switch is done by writing to CP15 register 13 The contents of the caches and TLBs do not have to be flushed after a fast context switch because they still hold valid address tags It should be noted that the two instructions after the MCR to write the ProcID will have been fetched with the old ProcID ProcID 0 MOV r0 1 SHL 25 Fetched with ProclD 0 MCR p15 0 r0 c13 c0 0 Fetched with 0 A1 Fetched with ProclD 0 A2 Fetched with ProcID 0 A3 Fetched with 1 REGISTER 15 TEST CONFIGURATION REGISTER Register 15 is used for test purposes Accessing reading or writing this register will cause the ARM920T to have unpredictable behavior 2 24 ELECTRONICS ARM920T PROCESSOR MMU Appendix 3 MMU ABOUT THE MMU ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI The MMU is controlled from a single set of two level page tables stored in main memory and are enabled by M Bit in CP15 register 1 providing a single address translation and protection scheme Th
211. as been modified and that main memory has not been updated to reflect the change a cache writeback occurs Depending on whether one or both halves of the cache line are dirty the writeback will perform a 4 or 8 word sequential burst write access on the ASB The writeback data is placed in the write buffer and then the linefill data is read from the ASB The CPU can the continue while the writeback data is written to memory via the ASB Load multiple LDM instructions accessing NCNB or NCB regions perform sequential bursts on the ASB Store multiple STM instructions accessing NCNB regions also perform sequential bursts on the ASB The sequential burst will be split into two bursts if it crosses a 1KB boundary This is because the smallest MMU protection and mapping size is 1KB so the memory regions on each size of the 1KB boundary may have different properties This means that no sequential access generated by ARM920T will cross a 1KB boundary which can be exploited to simplify memory interface design For example a simple page mode DRAM controller could perform a page mode access for each sequential access provided the DRAM page size is 1KB or larger See also Cache coherence on page 4 10 DATA CACHE REPLACEMENT ALGORITHM The DCache and replacement algorithm is selected by the RR bit in the CP15 Control register CP15 register 1 bit 14 Random replacement is selected at reset Setting the RR bit to 1 selects round robin re
212. as shown in Table 4 16 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STMIA RO R3 R7 Store the contents of registers R3 R7 starting at the address specified in RO incrementing the addresses for each word Write back the updated value of RO ELECTRONICS 4 33 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 16 CONDITIONAL BRANCH 15 14 13 12 11 8 7 0 7 0 8 bit Signed Immediate 11 8 Condition Figure 4 17 Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 4 17 The Conditional Branch Instructions THUMB assembler ARMequivalent Branch if set unsigned higher or same Branch if C clear unsigned lower Branch if N clear positive or zero Branch if V clear no overflow Branch if C set and Z clear unsigned higher 4 34 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET Table 4 17 The Conditional Branch Instructions Continued THUMB assembler ARMequivalent 1001 BLS label BLS label Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Br
213. ass of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation BYTES AND WORDS This instruction class may be used to swap a byte 1 or a word B 0 between an 920 register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers In particular the description of Big and Little Endian configuration applies to the SWP instruction ELECTRONICS 3 47 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction DATA ABORTS If the address used for the swap is un
214. ate on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 5 3C2410X RISC MICROPROCESSOR ELECTRICAL DATA 1 1 1 1 1 1 gt HOHER 1 1 1 1 1 1 1 1 1 1 SCIP SOH 4 SH Me SAU 508 gt i 4 gt lt gt ELECTRONICS 0 DW 16bit 0 ST 0 Tacc 2 Toch 0 Tcah 0 PMC Figure 24 5 ROM SRAM Burst READ Timing l 0 Tcos Tacs 24 6 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 RAD gt lt nc gt Figure 24 6 ROM SRAM Burst READ Timing Il Tacs 0 Tcos 0 Tacc 2 Toch 0 Tcah 0 PMC 0 ST 1 DW 16bit This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 7 ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR Figure 24 7 ROM SRAM READ Timing 1 Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2 PMC 0 ST 0 24 8 ELECTRONICS 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 Toch gt 4 RDS gt Figure 24 8 ROM SRAM READ Timing II Tacs 2 Tcos 2 Tacc 4 Toch 2 Tcah 2cycle PMC 0 ST 1 This document is a preliminary user s
215. be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN 15 20 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 A 31 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 21 A 20 A 19 A 18 A 17 A 16 Re rt 94 82 eo ro ee ce oo ne Tex 2 A 15 A 14 A 13 12 A 11 10 9 A 8 A 6 A 5 A 4 A S 2 0 LCD Panel 16BPP 5 5 5 1 Format Non Palette 31 A 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 22 A 21 A 20 A 19 A 18 A 17 A 16 Rt 95 2 ct co 82 81 R4 R2 R1 RO G5 G4 G3 G2 GO B4 B3 B2 B1 BO 5 A 14 13 A 12 A 11 A 10 A 9 8 A 7 A 6 5 A 4 A S A 2 A 0 LCD Panel 16BPP 5 6 5 Format Non Palette Figure 15 5 16BPP Display Types TFT This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 21 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR INT FrSyn VSYNC LINEVAL 1 1 FRAME HSPW 1 1 HOZVAL 1
216. bit MOVNE Rb Rb LSR 1 Halve unless finished BNE Div2 Divide result in remainder in Ra Overflow Detection in the ARM920T 1 Overflow in unsigned multiply with a 32 bit result UMULL Rd Rt Rm Rn 3106 cycles Rt 0 1 cycle and a register BNE overflow 2 Overflow in signed multiply with a 32 bit result SMULL Rd Rt Rm Rn 3106 cycles TEQ Rt Rd ASR 31 1 cycle and a register BNE overflow 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL Rd Rt Rm Rn 4to 7 cycles TEQ Rt 0 1 cycle and a register BNE overflow 4 Overflow in signed multiply accumulate with a 32 bit result SMLAL Rd Rt Rm Rn 4to 7 cycles TEQ Rt Rd ASR 31 1 cycle and a register BNE overflow 3 60 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL RI Rh Rm Rn ADDS RI RI Ra1 ADC Rh Rh Ra2 BCS overflow 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers 6 Overflow in signed multiply accumulate with a 64 bit result SMULL RI Rh Rm Rn ADDS RIRI Ra1 ADC Rh Rh Ra2 BVS overflow 3 to 6 cycles Lower accumulate Upper accumulate 1 cycle and 2 registers NOTES Overflow checking is not applicable to unsigned and signed multiplies with a 64 bit result since overflow does not occur in such calculations PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo rand
217. ble base Indexed by modified virtual address bits 19 12 Tiny page table base Indexed by modified virtual address bits 19 10 Figure 3 1 Translating Page Tables Section 1MB Coarse page table 256 entries Fine page table 1024 entries MMU Level two fetch Large page base Large page Indexed by modified virtual address bits 15 0 Small page base Small page Indexed by modified virtual address bits 11 0 Tiny page base Tiny page Indexed by modified virtual address bits 9 0 3 5 MMU ARM920T PROCESSOR HARDWARE TRANSLATION PROCESS TRANSLATION TABLE BASE The hardware translation process is initiated when the TLB does not contain a translation for the requested modified virtual address The translation table base TTB register points to the base address of a table in physical memory which contains section and or Page descriptors The 14 low order bits of the TTB register are set to zero on a read and the table must reside on a 16KB boundary 31 14 13 0 Translation table base p Figure 3 2 Translation Table Base Register The translation table has up to 4096 x 32 bit entries each describing 1MB of virtual memory This allows up to 4GB of virtual memory to be addressed Figure 3 1 on page 3 5 illustrates the table walk process 3 6 ELECTRONICS ARM920T PROCESSOR MMU LEVEL ONE FETCH Bits 31 14 of the translation table base register are concatenated with bits
218. ble disable 0 Disable LEND signal 1 Enable LEND signal BSWP 1 STN TFT Byte swap control bit 0 Swap Disable 1 2 Swap Enable HWSWP 0 STN TFT Half Word swap control bit 0 Swap Disable 1 Swap Enable This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 31 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR FRAME BUFFER START ADDRESS 1 REGISTER LCDSADDR1 0X4D000014 STN TFT Frame buffer start address 1 register 0x00000000 LCDBANK 29 21 These bits indicate A 30 22 of the bank location for the video buffer 0x00 in the system memory LCDBANK value cannot be changed even when moving the view port LCD frame buffer should be within aligned 4MB region which ensures that LCDBANK value will not be changed when moving the view port So care should be taken to use the malloc function LCDBASEU 20 0 For dual scan LCD These bits indicate A 21 1 of the start address 0x000000 of the upper address counter which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD For single scan LCD These bits indicate A 21 1 of the start address of the LCD frame buffer FRAME Buffer Start Address 2 Register Reset Value LCDSADDR2 0X4D000018 STN TFT Frame buffer start address 2 register 0x00000000 20 0 LCDBASEL For dual scan LC
219. by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The following table shows the exception vector addresses Table 2 3 Exception Vectors address MeemEmy 777 Abo prefech 04000000 Abr data RDS ELECTRONICS 2 13 PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR Exception Priorities When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority Reset Data abort FIQ IRQ Prefetch abort m Lowest priority 6 Undefined Instruction Software interrupt Not All Exceptions Can Occur at Once Undefined Instruction and Software Interrupt are mutually exclusive since they each correspond to particular non overlapping decodings of the current instruction If a data abort occurs at the same time as and FIQs are enabled ie the CPSR s flag is clear ARM920T enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The time for this ex
220. c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from R5 write this address back to R5 and use long transfer option probably to store multiple words NOTES Although the address offset is expressed in bytes the instruction offset field is in words The assembler will adjust the offset appropriately ELECTRONICS 3 55 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR COPROCESSOR REGISTER TRANSFERS MRC MCR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between ARM920T and a coprocessor An example of a coprocessor to ARM920T register transfer MRC instruction would be a FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM920T register A FLOAT of a 32 bit value in ARM920T register into a floating point value within the coprocessor illustrates the use of ARM920T register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the ARM920T CPSR flags As an example the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of executio
221. c6 MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and 6 and transfer the result back to R3 ELECTRONICS 3 57 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR UNDEFINED INSTRUCTION The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction format is shown in Figure 3 28 31 2827 2524 cone on Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 2S 11 1N cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 58 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some
222. cache entry is stored in the physical address TAG RAM for use during cache line write backs in addition to the virtual address TAG stored in the cache CAMs This means that the MMU is not involved in cache write back operations removing the possibility of TLB misses related to the write back address Cache maintenance operations to provide efficient cleaning of the entire data cache and to provide efficient cleaning and invalidation of small regions of virtual memory The latter allows ICache coherency to be efficiently maintained when small code changes occur for example self modifying code and changes to exception vectors The write buffer can hold 16 words of data and four addresses ELECTRONICS 4 1 CACHES WRITE BUFFER ARM920T PROCESSOR INSTRUCTION CACHE The ARM920T includes a 16KB instruction cache The ICache has 512 lines of 32 bytes 8 words arranged as a 64 way set associative cache and uses modified virtual addresses translated by CP15 register 13 see Address translation on page 3 4 from the ARM9TDMI core The ICache implements allocate on read miss Random or round robin replacement can be selected under software control via the RR bit CP15 register 1 bit 14 Random replacement is selected at reset Instructions can also be locked in the ICache such that they cannot be overwritten by a linefill This operates with a granularity of 1 64th of the cache which is 64 words 256 bytes All instruction accesses are subje
223. cache line into ICache line 0 and lock it down MCR to CP15 register 9 opcode 2 0x1 Victim Base 0x0 MCR I prefetch Assuming the ICache misses a linefill will occur to line O MCR to CP15 register 9 opcode 2 0x1 Victim Base 0x1 Further ICache linefills will now occur into lines 1 63 Load a cache line into DCache line 0 and lock it down MCR to CP15 register 9 opcode 2 0 0 Victim Base 0x0 Data load LDR LDM Assuming the DCache misses a linefill will occur to line 0 MCR to CP15 register 9 opcode 2 0x0 Victim Base 0x1 Further DCache linefills will now occur into lines 1 63 NOTE Writing CP15 register 9 with the CRm field set to 000001 updates the current victim pointer only for the specified segment only Bits 31 26 specify the victim bits 7 5 specify the segment for a 16KB cache and all other bits should be zero This encoding is intended for debug use It is not necessary and not advised to use this encoding ELECTRONICS 2 19 PROGRAMMER S MODEL ARM920T PROCESSOR Figure 2 5 shows the format of bits in register 9 31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 111098 7 6 5 432 1 0 UNP SBZ Figure 2 5 Register 9 Table 2 18 shows the instructions needed to access the cache lock down register Table 2 18 Accessing the Cache Lock Down Register 9 Function wa Read DCache lock down base p15 0 Rd c9 c0 0 Write DCache victim and lockdown base MCR p15 0 Rd c9 c0 0
224. cache with 16KB and D Cache 16KB 8words length per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm e Write through or write back cache operation to update the main memory e The write buffer can hold 16 words of data and four addresses 1 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Clock amp Power Manager On chip MPLL and UPLL UPLL generates the clock to operate USB Host Device MPLL generates the clock to operate MCU at maximum 200Mhz 1 8V Clock can be fed selectively to each function block by software Power mode Normal Slow Idle and Power off mode Normal mode Normal operating mode Slow mode Low frequency clock without PLL Idle mode The clock for only CPU is stopped Power off mode The Core power including all peripherals is shut down Woken up by EINT 15 0 or RTC alarm interrupt from Power Off mode Interrupt Controller 55 Interrupt sources One Watch dog timer 5 timers 9 UARTs 24 external interrupts 4 DMA 2 RTC 2 ADC 1 IIC 2 SPI 1 SDI 2 USB 1 LCD and 1 Battery Fault Level Edge mode on external interrupt source Programmable polarity of edge and level Supports Fast Interrupt request FIQ for very urgent interrupt request Timer with Pulse Width Modulation PWM 4 ch 16 bit Timer with PWM 1 ch 16 bit internal timer with DMA based or interrupt based operation Programmable duty cycle frequency
225. ception entry should be added to worst case FIQ latency calculations 2 14 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL INTERRUPT LATENCIES The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchronizer Tsyncmax if asynchronous plus the time for the longest instruction to complete the longest instruction is an LDM which loads all the registers including the PC plus the time for the data abort entry Texc plus the time for entry Tfiq At the end of this time ARM920T will be executing the instruction at Ox1C Tsyncmax is 3 processor cycles is 20 cycles Texc is 3 cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for or IRQ consists of the shortest time the request can take through the synchronizer Tsyncmin plus Tfiq This is 4 processor cycles RESET When the nRESET signal goes LOW ARM920T abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again ARM920T 1 Overwrites R14 svc and SPSR svc by copyin
226. ch data access initiated by the ARM9TDMI CPU core regardless of the value of the Ctt bit in the relevant MMU translation table descriptor If the accessed virtual address matches the virtual address of an entry in the cache the lookup is called a cache hit If the required address does not match any entry in the cache the lookup is called a cache miss In this context a data access means any type of load read or store write or swap instruction including LDR LDRB LDRH LDM LDC STR STRB STRH STC SWP and SWPB To ensure that accesses appear on the ASB in program order ARM920T will wait for all writes in the write buffer to complete on the ASB before starting any other ASB access The ARM9TDMI CPU core can continue executing at full speed reading instructions and data from the caches and writing to the DCache and write buffer while buffered writes are being written to memory via the ASB Table 4 1 describes the DCache and write buffer behavior for each type of memory configuration Ctt AND means the bitwise Boolean AND of Ctt with Ccr 4 6 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER Table 4 1 Data Cache and Write Buffer Configuration Ctt and Cer Data cache write buffer and memory access behavior Non cached non buffered NCNB Reads and writes are not cached and always perform accesses on the ASB and may be externally aborted Writes are not buffered The CPU halts until the write is completed on the ASB
227. check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit ELECTRONICS 11 15 UART 53 2410 01 RISC MICROPROCESSOR UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTATO UERSTAT1 and UERSTAT2 in the UART block UERSTATO 0x50000014 UART channel 0 Rx error status register UERSTAT 1 0x50004014 KE UART channel 1 Rx error status register EC NE UERSTAT2 0x50008014 oR UART channel 2 Rx error status register 00 Break Detect 3 Setto 1 automatically to indicate that a break signal has been received 0 No break receive 1 Break receive Interrupt is requested Parity Error 1 Setto 1 automatically whenever a parity error occurs during receive operation 0 No parity error during receive 1 Parity error Interrupt is requested Overrun Error Set to 1 automatically whenever an overrun error occurs during receive operation 0 No overrun error during receive 1 Overrun error Interrupt is requested Note These bits UERSATn 3 0 are automatically cleared to 0 when the UART error status register is read Frame Error 2 Set to 1 automatically whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error Interrupt is requested 11 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTATO UFSTAT1 and UF
228. cks 11 4 clocks Tcos 12 11 Chip selection set up time before nOE 00 0 clock 01 1 clock 10 2 2 clocks 11 2 4 clocks Toch 7 6 Chip selection hold time after nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Address hold time after nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Page mode access cycle Page mode 00 2 clocks 01 clocks 10 4 clocks 11 6 clocks Page mode configuration 00 normal 1 01 4 data 10 8 data 11 16 data Tacc Access cycle 111 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks Note When nWAIT signal is used Tacc gt 4 clocks 000 ELECTRONICS 5 15 MEMORY CONTROLLER S3C2410X01 RISC MICROPROCESSOR BANK CONTROL REGISTER BANKCONn nGCS6 nGCS7 BANKCON6 0x4800001C Bank 6 control register 0x18008 BANKCON7 0x48000020 Bank 7 control register 0x18008 16 15 Determine the memory type for bank6 and bank7 00 ROM or SRAM 01 Reserved Do not use 10 Reserved Do not use 11 Sync DRAM Memory Type ROM or SRAM MT 00 15 bit Tacs 14 13 Address set up time before nGCS 00 0clock 01 1clock 10 2 clocks 11 4 clocks 11 4 clocks 12 11 Chip selection set up time before nOE 00 0clock 01 1clock 10 2 clocks Tacc 10 8 Access cycle 000 1 clock 010 3 clocks 100 6 clocks 110 10 clocks Toch 7 6 Chip selection hold time a
229. code flags on the result MOV Rd Hs MOV Hs Move a value from a register in the range 8 15 to a register in the range 0 7 10 1 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 10 MOV Hd Hs MOV Hd Hs Move a value between two registers in the range 8 15 11 BX Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 6 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register Bit 0 of the address determines the processor state on entry to the routine Bit0 0 Causes the processor to enter ARM state Bit 0 1 Causes the processor to enter THUMB state NOTE The action of H1 1 for this instruction is undefined and should not be used 4 14 ELECTRONICS 53 2410 RISC MICROPROCESSOR EXAMPLES Hi Register Operations ADD PC R5 CMP R4 R12 MOV R15 R14 Branch and Exchange ADR R1 outof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outofTHUMB USING R15 AS AN OPERAND THUMB INSTRUCTION SET PC PC R5 but don t set the condition codes Se
230. ct to MMU permission and translation checks Instruction fetches which are aborted by the MMU will not cause linefills or instruction fetches to appear on the ASB For clarity the bit bit 12 in CP15 register 1 is referred to as the Icr bit throughout the following text The C bit from the MMU translation table descriptor corresponding to the address being accessed is referred to as Cit 4 2 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER INSTRUCTION CACHE ENABLE DISABLE On reset the ICache entries are all invalidated and the ICache is disabled The ICache is enabled by writing 1 to the Icr bit and disabled by writing 0 to the Icr bit The ICache is usually used with the MMU enabled in which case the C bit in the relevant MMU translation table descriptor indicates whether an area of memory is cacheable If the ICache is enabled with the MMU disabled all instruction fetches are treated as cacheable When the ICache is disabled the cache contents are ignored and all instruction fetches appear on the ASB as separate non sequential accesses NOTES ARM920T implements a non sequential access on the ASB as an A TRAN cycle followed by an S TRAN cycle It does not produce N TRAN cycles If the cache is subsequently re enabled its contents will be unchanged If the contents are no longer coherent with main memory the ICache should be invalidated prior to being enabled see Register 7 Cache operations on page 2 15 The MMU and
231. ctive lines at the end of 00000000 a frame before vertical synchronization period STN These bits should be set to zero on STN LCD VSPW 5 0 TFT Vertical sync pulse width determines the VSYNC pulse s high 000000 level width by counting the number of inactive lines STN These bits should be set to zero on STN LCD This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 27 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR LCD Control 3 Register LCDCON3 0X4D000008 LCD control 3 register 0x00000000 HBPD TFT 25 19 TFT Horizontal back porch is the number of VCLK periods between 0000000 the falling edge of HSYNC and the start of active data WDLY STN STN WDLY 1 0 bits determine the delay between VLINE and VCLK by counting the number of the HCLK WDLY 7 2 are reserved 00 16 HCLK 01 32 HCLK 10 64 HCLK 11 128 HCLK HOZVAL 18 8 TFT STN These bits determine the horizontal size of LCD panel 00000000000 HOZVAL has to be determined to meet the condition that total bytes of 1 line are 2n bytes If the x size of LCD is 120 dot in mono mode x 120 cannot be supported because 1 line consists of 15 bytes Instead x 128 in mono mode can be supported because 1 line is composed of 16 bytes 2n LCD panel driver will discard the additional 8 dot LINEBLAN
232. cumulate Long 32 x 32 64 64 where cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 EXAMPLES UMULL R1 R4 R2 R3 R4 R1 R2 R3 UMLALS R1 R5 R2 R3 R5 R1 R2 R3 R5 R1 also setting condition codes ELECTRONICS 3 27 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 Lew dos _ 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 25 Immedia
233. current processor state must be preserved so that the original program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a fixed order See Exception Priorities on page 2 14 Action on Entering an Exception When handling an exception the ARM920T 1 Preserves the address of the next instruction in the appropriate Link Register If the exception has been entered from ARM state then the address of the next instruction is copied into the Link Register that is current PC 4 or PC 8 depending on the exception See Table 2 2 on for details If the exception has been entered from THUMB state then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14 svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions If the processor is in THUMB state when an exc
234. d Reserved MPLL_OFF 5 0 is turned on After PLL stabilization time minimum 150us SLOW_BIT can be cleared to 0 1 PLL is turned off PLL is turned off only when SLOW BIT is 1 SLOW BIT 4 MPLL output 1 SLOW mode FCLK input clock 2 x SLOW VAL SLOW VAL gt 0 FCLK input clock SLOW VAL 0 input clock or EXTCLK Reserved SLOW_VAL 2 0 The divider value for the slow clock when SLOW_BIT is on CLOCK DIVIDER CONTROL CLKDIVN REGISTER CLKDIVN _ 0x4C000014 Clock divider control register 0x00000000 CLKDIVN Bit Description Initial State 2 Special bus clock ratio for the chip verification HDIVN 1 0 HCLK has the clock same as the HEN PDIVN 0 0 PCLK has the clock same as the HCLK LN 7 7 20 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR DMA 05 25 2002 DMA Preliminary OVERVIEW The 53 2410 01 supports four channel DMA controller that is located between the system bus and the peripheral bus Each channel of DMA controller can perform data movements between devices in the system bus and or peripheral bus with no restrictions In other words each channel can handle the following four cases 1 both source and destination are in the system bus 2 the source is in the system bus while the destination is in the peripheral bus 3 the source is in the peripheral bus while the destination is in the system bus
235. d Wait Request signal transmits to SDDAT2 pin in the condition below n read multiple operation request signal transmission begins at 2clocks after the end of the data block Transmission ends when the user writes one to SDIDSTA 10 ELECTRONICS 19 3 SD HOST CONTROLLER 3C2410X01 RISC MICROPROCESSOR SDI SPECIAL REGISTERS SDI Control SDICON Register RW Reset Value SDICON 0x5A000000 SDICON Byte Order Type ByteOrder Receive SDIO Interrupt from card RcvlOInt Read Wait Enable RWaitEn FIFO Reset FRST Clock Out Enable ENCLK Byte Order Type Type A D 7 0 1 initial Value R W SDI control register Determine byte order type when you read write data from to SD host FIFO with word boundary 0 Type A 1 B i Determine whether SD host receives SDIO Interrupt from the card or not for SDIO 0 ignore 1 receive SDIO Interrupt Determine read wait request signal generate when SD host waits the next block in multiple block read mode This bit needs to delay the next block to be transmitted from the card for SDIO 0 disable no generate 1 Read wait enable use SDIO BH Reset FIFO value This bit is automatically cleared 0 normal mode 1 FIFO reset Determine whether SDCLK Out enable or not 0 0 disable prescaler off 1 clock enable D 15 8 D 23 16 gt D 31 24 D 31 24 2 D 23 16 gt D 15 8 D 7 0
236. d subtract offset bofore transfer 31 28 Condition Field Figure 3 16 Halfword and Signed Data Transfer with Register Offset 3 34 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET 28 27 25 24 23 22 21 20 19 16 15 12 11 876543 m Do SEP om 3 0 Immediate Offset Low Nibble 6 5 SH 0 0 SWP instruction 0 1 Unsigned halfword 1 1 1 1 Signed byte Signed halfword 11 8 Immediate Offset High Nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base
237. dge of the clock signal The IISLRCK line changes one clock period before the MSB is transmitted This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission Furthermore it enables the receiver to store the previous word and clear the input for the next word MSB LEFT JUSTIFIED MSB left justified bus format is the same as IIS bus format architecturally Only different from the IIS bus format the MSB justified format realizes that the transmitter always sends the MSB of the next word whenever the IISLRCK is changed ELECTRONICS 21 3 IIS BUS INTERFACE S3C2410X01 RISC MICROPROCESSOR MSB justified Format or 16 Figure 21 2 IIS Bus and MSB Left justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency PCLK can be selected by sampling frequency as shown in Table 21 1 Because PCLK is made by IIS prescaler the prescaler value and PCLK type 256 or 384fs should be determined properly Serial bit clock frequency type 16 32 48fs can be selected by the serial bit per channel and PCLK as shown in Table 21 2 Table 21 1 CODEC clock CODECLK 256 or 384fs IISLRCK 8 000 11 025 16 000 22 050 32 000 44 100 48 000 64 000 88 200 96 000 fs KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz 256fs MHz 384fs Table 21 2 Usable serial bit clock frequency IISCLK z 16 or 32 or 48fs Serial clock frequency IISCLK CODECLK
238. diate oerand Figure 4 3 Format 2 OPERATION These instructions allow the contents of a Lo register or a 3 bit immediate value to be added to or subtracted from a Lo register The THUMB assembler syntax is shown in Table 4 3 NOTE All instructions in this group set the CPSR condition codes Table 4 3 Summary of Format 2 Instructions THUMB Assembler ARM Equipment ADD Rd Rs Rn ADDS Rd Rs Rn Add contents of Rn to contents of Rs Place result in Rd 1 ADD Rd Rs Offset3 ADDS Rd Rs Offset3 Add 3 bit immediate value to contents of Rs Place result in Rd ERES SUB Rd Rs Rn SUBS Rd Rs Rn Subtract contents of Rn from contents of Rs Place result in Rd SUB Rd Rs Offset3 SUBS Rd Rs Offset3 Subtract 3 bit immediate value from contents of Rs Place result in Rd Ed ELECTRONICS 4 7 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 3 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD RO R3 R4 SUB R6 R2 6 RO and set condition codes on the result R2 6 and set condition codes 4 8 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 7 0 12 11 10 8 ome 7 0 Immediate Vale
239. ding prefetch effects NOTES If the MMU is enabled then disabled and subsequently re enabled the contents of the TLBs will have been preserved If these are now invalid the TLBs should be invalidated before the MMU is re enabled See Register 8 TLB operations on page 2 18 ELECTRONICS 3 25 MMU 3 26 NOTES ARM920T PROCESSOR ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER APPENDIX 4 CACHES WRITE BUFFER ABOUT THE CACHES AND WRITE BUFFER The ARM920T includes an instruction cache a data cache a write buffer and a Physical Address TAG RAM to reduce the effect of main memory bandwidth and latency on performance The ARM920T implements separate 16KB instruction and 16KB data caches The caches have the following features Virtually addressed 64 way associative cache 8 words per line 32 bytes per line with one valid bit and two dirty bits per line allowing half line write backs Write through and write back cache operation write back caches are also known as copy back caches selected per memory region by the C and B bits in the MMU translation tables for data cache only Pseudo random or round robin replacement selectable via RR bit in CP15 register 1 Low power CAM RAM implementation Caches independently lockable with granularity of 1 64th of cache which is 64 words 256 bytes For compatibility with Microsoft WindowsCE and to reduce interrupt latency the physical address corresponding to each data
240. e 16 bit shift register SFTR Parallel data is shifted to serial data output in the transmit mode and serial data input is shifted to parallel data in the receive mode TRANSMIT OR RECEIVE ONLY MODE Normal transfer IIS control register has FIFO ready flag bits for transmit and receive FIFOs When FIFO is ready to transmit data the FIFO ready flag is set to 1 if transmit FIFO is not empty If transmit FIFO is empty FIFO ready flag is set to 0 When receive FIFO is not full the FIFO ready flag for receive FIFO is set to 1 it indicates that FIFO is ready to receive data If receive FIFO is full FIFO ready flag is set to 0 These flags can determine the time that CPU is to write or read FIFOs Serial data can be transmitted or received while the CPU is accessing transmit and receive FIFOs in this way 21 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIS BUS INTERFACE DMA TRANSFER In this mode transmit or receive FIFO is accessible by the DMA controller DMA service request in transmit or receive mode is made by the FIFO ready flag automatically TRANSMIT AND RECEIVE MODE In this mode IIS bus interface can transmit and receive data simultaneously AUDIO SERIAL INTERFACE FORMAT IIS BUS FORMAT The IIS bus has four lines including serial data input IISDI serial data output IISDO left right channel select IISLRCK and serial bit clock IISCLK the device generating IISLRCK and IISCLK is the master Serial da
241. e other master supplies the clock When the programmer writes byte data to SPTDATn register SPI transmit receive operation will start simultaneously In some cases nSS should be activated before writing byte data to SPTDATn Programming Procedure When byte data is written into the SPTDATn register SPI starts to transmit if ENSCK and MSTR of SPCONn register are set You can use a typical programming procedure to operate an SPI card To program the SPI modules follow these basic steps 1 Set Baud Rate Prescaler Register SPPREn 2 Set SPCONn to configure properly the SPI module 3 Write data OxFF to SPTDATn 10 times in order to initialize MMC or SD card 4 Seta GPIO pin which acts as nSS to low to activate the MMC or SD card 5 Tx data Check the status of Transfer Ready flag REDY 1 and then write data to SPTDATn 6 Rx data 1 SPCONn s TAGD bit disable normal mode write OXFF to SPTDATn then confirm REDY to set and then read data from Read Buffer 7 Rx data 2 SPCONn s TAGD bit enable Tx Auto Garbage Data mode confirm REDY to set and then read data from Read Buffer then automatically start to transfer 8 Set a GPIO pin which acts as nSS to high to deactivate MMC or SD card This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 22 3 SPI
242. e 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word B 0 between ARM920T register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM920T core The two possible configurations are described below Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register Two shift operations are then required
243. e MCU writes MAXP data IN_PKT_RDY will automatically be set by the core without any intervention from MCU If the MCU writes less than MAXP data IN PKT RDY bit has to be set by the MCU Used only for endpoints whose transfer type is programmable 1 Configures endpoint to ISO mode 0 Configures endpoint to Bulk mode Used only for endpoints whose direction is programmable 1 Configures Endpoint Direction as IN 0 Configures Endpoint Direction as OUT Determine whether the interrupt should be issued or not when the EP1 IN PKT RDY condition happens This is only useful for DMA mode 0 Interrupt enable 1 Interrupt Disable R 13 15 USB DEVICE 53 2410 01 RISC MICROPROCESSOR END POINT OUT CONTROL STATUS REGISTER OUT_CSR1_REG OUT_CSR2_REG OUT_CSR1_REG 0x52000190 L RAN End Point out control status register 0x00 0x52000193 B State CLR DATA TOGGLE 7 R W CLEAR When the MCU writes a 1 to this bit the data toggle sequence bit is reset to DATAO SENT_STALL 6 CLEAR SET Set by the USB when an OUT token is ended with a STALL handshake The USB issues a stall handshake to the host if it sends more than data for the OUT TOKEN R SEND_STALL 5 R W 0 The MCU clears this bit to end the STALL condition handshake IN PKT RDY is cleared 1 The MCU issues a STALL handshake to the USB The MCU clears this bit to end the STALL condition handshake IN RDY is cleared FIFO_FLUSH 4 R W CLEA
244. e Rate Control FRC method The selection can be made following a programmable lockup table which will be explained later The monochrome mode bypasses these modules FRC and lookup table and basically serializes the data in FIFOH and FIFOL if a dual scan display type is used into 4 bit or 8 bit if a 4 bit dual scan or 8 bit single scan display type is used streams by shifting the video data to the LCD driver The following sections describe the operation on the gray and color mode in terms of the lookup table and FRC Lookup Table The 53 2410 01 can support the lookup table for various selection of color or gray level mapping ensuring flexible operation for users The lookup table is the palette which allows the selection on the level of color or gray Selection on 4 gray levels among 16 gray levels in case of 4 gray mode selection on 8 red levels among 16 levels 8 green levels among 16 levels and 4 blue levels among 16 levels in case of 256 color mode In other words users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode The gray levels cannot be selected in the 16 gray level mode all 16 gray levels must be chosen among the possible 16 gray levels In case of 256 color mode 3 bits are allocated for red 3 bits for green and 2 bits for blue The 256 colors mean that the colors are formed from the combination of 8 red 8 green and 4 blue levels 8x8x4 256 In the color mode the lookup tab
245. e Register DITHMODE 0X4D00004C R W STN Dithering mode register 0x00000 This register reset value is 0x00000 But user can change this value to 0x12210 Refer to a sample program source for the latest value of this register DITHMODE Bit Description Initial state DITHMODE 18 0 Use one of following value for your LCD 0x00000 0x00000 or 0x12210 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 35 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR Temp Palette Register Reset Value TPAL 0X4D000050 R W TFT Temporary palette register 0x00000000 This register value will be video data at next frame TPALEN 24 Temporary palette register enable bit 0 Disable 1 Enable TPALVAL 23 0 Temporary palette value register 0x000000 TPALVAL 23 16 RED TPALVAL 15 8 GREEN TPALVAL 7 0 BLUE 15 36 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 LCD Interrupt Pending Register LCDINTPND 0X4D000054 Indicate the LCD interrupt pending register INT FrSyn 1 LCD frame synchronized interrupt pending bit 0 The interrupt has not been requested 1 The frame has asserted the interrupt request INT FiOnt LCD FIFO interrupt pending bit 0 The interrupt has not been requested 1 LCD FIFO interrupt is req
246. e Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR instructions take 15 1N 11 and LDR PC take 25 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 31 ARM INSTRUCTION SET ASSEMBLER SYNTAX 53 2410 RISC MICROPROCESSOR lt LDR STR gt cond B T Rd lt Address gt where LDR STR cond B T Rd Rn and Rm lt Address gt can be 1 shift Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 is present then byte transfer otherwise word transfer is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is not allowed when a pre indexed addressing mode is specified or implied An expression evaluating
247. e back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and the address will be incremented by one word for each subsequent transfer ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system Use of R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried Instruction cycle times Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where n The number of words transferred b The number of cycles spent in the coprocessor busy wait loop S and I are defined as sequential S cycle non sequential N cycle and
248. e condition codes Note that the THUMB opcode will contain 26as the Word7 value and S 1 4 30 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 14 PUSH POP REGISTERS 14 11 7 0 Register List 8 PC LR Bit 0 Do not store LR Load PC 1 Store LR Load PC 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 15 Format 14 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 4 15 NOTE The stack is always assumed to be Full Descending Table 4 15 PUSH and POP Gu J THUMB assembler ARM equivalent PUSH Rlist STMDB 813 Rlist the registers specified by Rlist onto the stack Update the stack pointer PUSH Rlist LR STMDB R13 Push the Link Register and the registers Rlist R14 specified by Rlist if any onto the stack Update the stack pointer 1 POP Rlist LDMIA R13 Rlist Pop values off the stack into the registers specified by Rlist Update the stack pointer 1 1 POP Rlist PC LDMIA R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer ELECTRONICS 4 31 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES All instructions in this
249. e contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map into the result are discarded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 Contents of Rm Value of Operand 2 00000 Figure 3 6 Logical Shift Left NOTES LSL 0 is a special case where the shifter carry out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A logical shift right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 12 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET 31 5 4 0 Contents of Rm carry out 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 32 to be specified An arithmetic shift right ASR is similar to logical shift right
250. e data MMU and details how these are interpreted to generate faults Table 3 4 Priority Encoding of Fault Status Highest Alignment 0600 1 invalid MVA of access priority causing abort Translation Section Page 060101 invalid MVA of access 0b0111 valid causing abort Domain Section Page 061001 valid MVA of access 0b1011 valid causing abort Permission Section Page 001101 valid MVA of access 061111 valid causing abort Lowest External abort on NCNB Section Page 061000 valid MVA of access priority access or NCB read 0b1010 valid causing abort NOTES 1 Data FSR only Alignment faults may write either 0b0001 or 0b0011 into FS 3 0 Invalid values in domain 3 0 occur because the fault is raised before a valid domain field has been read from a page table descriptor Any abort masked by the priority encoding may be regenerated by fixing the primary abort and restarting the instruction NCNB means Non Cacheable and Non Bufferable NCB means Non Cacheable but Bufferable 2 Instruction FSR only The same priority applies as for the Data fault status register except that alignment faults cannot occur and external aborts apply only to NC Non cacheable reads 3 18 ELECTRONICS ARM920T PROCESSOR MMU DOMAIN ACCESS CONTROL MMU accesses are primarily controlled via domains There are 16 domains and each has a 2 bit field to define access to it Two types of user are supported clients and managers See Table 3 5 The domains are defin
251. e destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section Endianness and byte halfword selection Little Endian Configuration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A halfword load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory sy
252. e in 256 color mode 4096x1024 2048x2048 1024x4096 and others Thin Film Transistor TFT color displays Feature Supports 1 2 4 or 8 bpp bit per pixel palette color displays for color TFT e Supports 16 bpp non palette true color displays for color TFT Supports maximum 16M color TFT at 24 bpp mode Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 64K color mode 2048x1024 and others 1 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Watch dog Timer 16 bit Watchdog Timer e Interrupt request or system reset at time out IIC Bus Interface e 1 ch Multi Master IIC Bus Serial 8 bit oriented and bi directional data transfers can be made at up to 100 Kbit s in Standard mode or up to 400 Kbit s in Fast mode IIS Bus Interface 1 IIS bus for audio interface with DMA based operation Serial 8 16 bit per channel data transfers 128 Bytes 64 Byte 64 Byte FIFO for Tx Rx Supports IIS format and MSB justified data format USB Host e 2 port USB Host Complies with Rev 1 0 Compatible with USB Specification version 1 1 USB Device 1 port USB Device 5 Endpoints for USB Device Compatible with USB Specification version 1 1 SD Host Interface e Compatible with SD Memory Card Protocol version 1 0 Compatible with SDIO Card Protocol
253. e instruction and data TLBs in the MMU can be independently locked and flushed The MMU features are standard ARM V4 MMU mapping sizes domains and access protection scheme mapping sizes are 1MB sections 64KB large pages 4KB small pages and new 1KB tiny pages access permissions for sections access permissions for large pages and small pages can be specified separately for each quarter of the page these quarters are called sub pages 16domains implemented in hardware 64 entry instruction TLB and 64 entry data TLB hardware page table walks round robin replacement algorithm also called cyclic e invalidate whole TLB via CP15 Register 8 e invalidate TLB entry selected by modified virtual address via CP15 register 8 e independent lockdown of instruction TLB and data TLB via CP15 register 10 ACCESS PERMISSIONS AND DOMAINS For large and small pages access permissions are defined for each sub page 1KB for small pages 16KB for large pages Sections and tiny pages have a single set of access permissions All regions of memory have an associated domain A domain is the primary access control mechanism for a region of memory and defines the conditions in which an access can proceed The domain determines whether the access permissions are used to qualify the access the access is unconditionally allowed to proceed the access is unconditionally aborted In the latter two cases the access permission att
254. e next index after it has loaded a line into the last available segment with the current index As there are 8 segments this will occur after 8 cache lines have been loaded Once all the data has been loaded it is locked by writing to CP15 register 9 to move the replacement counter base to be one higher than the highest index of the locked cache lines The software routine that loads and locks the data in the DCache can be located in a cacheable region of memory providing it does not contain any loads or stores other than the loads which are used to bring the data to be locked into the DCache The data to be loaded must be from a memory region which is cacheable ELECTRONICS 4 9 CACHES WRITE BUFFER ARM920T PROCESSOR CACHE COHERENCE The ICache and DCache contain copies of information normally held in main memory If these copies of memory information get out of step with each other because one is updated and the others are not updated they are said to have become incoherent If the DCache contains a line which has been modified by a store or swap instruction and the main memory has not been updated the cache line is said to be dirty Clean operations force the cache to write dirty lines back to main memory On the ARM920T software is responsible for maintaining coherence between main memory the ICache and the DCache Register 7 Cache operations on page 2 15 describes facilities for invalidating the entire ICache or individual ICache l
255. e of the TAP controller s Ce A 10K pull up resistor has to be connected to TMS pin TCK TAP Controller Clock provides the clock input for the JTAG logic A 10K pull up resistor must be connected to TCK pin TDI TAP Controller Data Input is the serial input for test instructions and data A 10K pull up resistor must be connected to TDI pin o TDO TAP Controller Data Output is the serial output for test instructions and data Reset Clock amp Power nRESET ST nRESET suspends any operation in progress and places S3C2410 into a known reset state For a reset nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized nRSTOUT For external device reset contro nRSTOUT nRESET amp nWDTRST SW RESET PWREN KA 1 8V core power on off control signal nBATT_FLT EE Probe for battery state Does not wake up at power off mode in case of low battery state ON 3 2 OM 3 2 determines how the clock is made OM 3 2 00b Crystal is used for MPLL CLK source and UPLL CLK source OM 3 2 01b Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source OM 3 2 10b EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source OM 3 2 11b EXTCLK is used for MPLL CLK source and UPLL CLK source EXTCLK External clock source When ON 3 2 11b EXTCLK is used for MPLL CLK source and UPLL CLK source When ON 3 2 10b EXTCLK is used for MPLL CLK source onl
256. e page descriptor provides the base address of a 64KB block of memory Coarse page tables have 256 entries each entry describing 4KB These entries can provide base addresses for either small or large pages Large page descriptors must be repeated in 16 consecutive entries Fine page tables have 1024 entries each entry describing 1KB These entries can provide base addresses for either tiny small or large pages Small page descriptors must be repeated in 4 consecutive entries and large page descriptors must be repeated in 64 consecutive entries The figure below shows the format of level one descriptors 16 15 1211109 8 765 43 2 1 0 tm wo vage pave sma age nese accross oro aos sos avo 8 fo sman page mweweweses 8 7 try pave Figure 3 6 Page Table Entry Level One Descriptor Bits 1 0 indicate the page size and validity and are interpreted as follows Table 3 3 Interpreting Page Table Entry Bits 1 0 meaning we 0 Large page Indicates that this is a 64KB page Small page Indicates that this is a 4KB page Tiny page Indicates that this is a 1KB page ELECTRONICS 3 11 MMU ARM920T PROCESSOR Bit 3 2 C amp B indicate whether the area of memory mapped by this page is treated as write back cacheable write through cacheable non cached buffered or non cached non buffered Domain access control on page 3 19 and Fault checking sequence on page 3 21 show how
257. e will show the revision with a proper version number ELECTRONICS 15 33 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR RED Lookup Table Register Reset Value REDLUT 0X4D000020 STN Red lookup table register 0x00000000 31 0 REDVAL These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible red combinations 000 REDVAL 3 0 001 REDVAL 7 4 010 REDVAL 11 8 011 REDVAL 15 12 100 REDVAL 19 16 101 REDVAL 23 20 110 REDVAL 27 24 111 REDVAL 31 28 GREEN Lookup Table Register GREENLUT 0X4D000024 STN Green lookup table register 0x00000000 31 0 GREENVAL These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible green combinations 000 GREENVAL 3 0 001 GREENVAL 7 4 010 GREENVAL 1 1 8 011 GREENVAL 15 12 100 19 16 101 GREENVAL 23 20 110 GREENVAL 27 24 111 31 28 BLUE Lookup Table Register Reset Value BLUELUT 0 40000028 STN Blue lookup table register 0x0000 BLUEVAL 15 0 These bits define which of the 16 shades will be chosen by each of 0x0000 the 4 possible blue combinations 00 BLUEVAL 3 0 01 BLUEVAL 7 4 10 BLUEVAL 11 8 11 BLUEVAL 15 12 Note Address from 0x14A0002C to 0x14A00048 should not be used This area is reserved for Test mode 15 34 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 Dithering Mod
258. ection bit 0 IICCLK fpei 16 1 IICCLK fpei 512 Tx Rx Interrupt 9 5 IIC Bus Tx Rx interrupt enable disable bit 0 Disable 1 Enable Interrupt pending flag 2 3 4 IIC bus Tx Rx interrupt pending flag This bit cannot be written to 1 When this bit is read as 1 the IICSCL is tied to L and the IIC is stopped To resume the operation clear this bit as O 0 1 No interrupt pending when read 2 Clear pending condition amp Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write Transmit clock value 4 IIC Bus transmit clock prescaler Undefined IIC Bus transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock IICCLK IIGCON 3 0 1 Notes 1 Interfacing with EEPROM the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode 2 IIC bus interrupt occurs 1 when a 1 byte transmit or receive operation is completed 2 when a general call or a slave address match occurs or 3 if bus arbitration fails 3 To adjust the setup time of IICSDA before IISSCL rising edge IICDS has to be written before clearing the IIC interrupt pending bit 4 ICCLK is determined by IICCON 6 Tx clock can vary by SCL transition time When IICCON 6 0 IICCON 3 0 0x0 or 0x1 is not available 5 If the IICON 5 0 IICON 4 does not operate correctly So It is recommended that
259. ed in the domain access control register Figure 3 10 illustrates how the 32 bits of the register are allocated to define the 16 2 bit domains 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110987654321 7 IIS III Is Figure 3 10 Domain Access Control Register Format Table 3 5 defines how the bits within each domain are interpreted to specify the access permissions Table 3 5 Interpreting Access Control Bits in Domain Access Control Register Value Meaning Notes No Access Any access will generate a domain fault 01 Client Accesses are checked against the access permission bits in the section or page descriptor Reserved Currently behaves like the no access mode 11 Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated ELECTRONICS 3 19 MMU ARM920T PROCESSOR Table 3 6 shows how to interpret the access permission AP bits and how their interpretation is dependent upon the S and R bits control register bits 8 and 9 Table 3 6 Interpreting Access Permission AP Bits Supervisor User Permissions Permissions No access No access Any access generates a permission fault 1 Read only No access Supervisor read only permitted 1 Read only Read only Any write generates a permission fault __ 1 Rew 01 X X Read write No access Access allowed only in supervisor mode 10 X X Read write Read on
260. edure is suggested 1 Connect pads of the touch screen panel to the S3C2410X01 using external transistor see Figure 16 2 2 Select Separate X Y Position Conversion Mode or Auto Sequential X Y Position Conversion Mode to get X Y position 3 Set Touch Screen Interface to Waiting Interrupt Mode 4 If interrupt occurs then appropriate conversion Separate X Y Position Conversion Mode or Auto Sequential X Y Position Conversion Mode is activated 5 After get the proper value about X Y position return to Waiting for Interrupt Mode Note 1 External voltage source should be 3 3 V 2 Internal resistance of the external transistor should be under 5 ohm ELECTRONICS 16 3 A D CONVERTER AND TOUCH SCREEN 3C2410X01 RISC MICROPROCESSOR FUNCTION DESCRIPTIONS A D Conversion Time When the PCLK frequency is 50MHz and the prescaler value is 49 total 10 bit conversion time is given A D converter freq 50 2 49 1 1MHz Conversion time 1 1MHz 5cycles 1 200KHz 5 us Note This A D converter is designed to operate at maximum 2 5MHz clock so the conversion rate can go up to 500 KSPS Touch Screen Interface Mode 1 Normal Conversion Mode Normal Conversion Mode AUTO_PST 0 XY_PST 0 is generally used for General Purpose ADC Conversion This mode can be initialized by setting the ADCCON and ADCTSC and completed with a read the XPDATA Normal ADC value of ADCDATO ADC Data Register 0 2 Separate X Y Posi
261. ee Table 3 2 for details In THUMB state only the Branch instruction is capable of conditional execution see Figure 3 46 for details The Control Bits The bottom 8 bits of a PSR incorporating T and M 4 0 are known collectively as the control bits These will be changed when an exception arises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits I and bits are the interrupt disable bits When set these disable the IRQ and interrupts respectively The mode bits The M2 M1 and MO bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode bits define a valid processor mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be applied Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these u
262. egister in PLL on state The SLOW clock is generated during the SLOW mode Figure 7 11 shows the timing diagram ELECTRONICS 7 11 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR SLOW_BIT Slow mode enable Slow mode disable MPLL OFF FCLK Divided external clock It changes to PLL clock after slow mode off Figure 7 11 Issuing Exit from Slow mode command in PLL on state If the user switches from SLOW mode to Normal mode by disabling the SLOW BIT in the CLKSLOW register after PLL lock time the frequency is changed just after SLOW mode is disabled Figure 7 12 shows the timing diagram Software lock time Mpll SLOW BIT m Slow mode enable Slow mode disable MPLL OFF yy PLL off on FCLK Divided OSC clock It changes to PLL clock after slow mode off Figure 7 12 Issuing Exit from Slow mode command after lock time If the user switches from SLOW mode to Normal mode by disabling SLOW BIT and MPLL_OFF bit simultaneously in the CLKSLOW register the frequency is changed just after the PLL lock time Figure 7 13 shows the timing diagram HW lock time je gt Mpll SLOW BIT Slow mode enable Slow mode disable MPLL OFF y PLL off on FCLK Divided changes to PLL clock OSC clock after lock time automatically Figure 7 13 Issuing Exit_from_Slow_mode command and the instant PLL_on command simultaneously 7 12 ELECTRON
263. eive error status interrupt Setting loopback bit to 1 causes the UART to enter the loopback mode This mode is provided for test purposes only 0 Normal operation 1 Loopback mode Setting this bit causes the UART to send a break during 1 frame time This bit is automatically cleared after sending the break signal 0 Normal transmit 1 Send break signal 0x00 11 11 UART 53 2410 01 RISC MICROPROCESSOR UART CONTROL REGISTER CONTINUED Transmit Mode 3 2 Determine which function is currently able to write Tx data to the UART transmit buffer register 00 Disable 01 Interrupt request or polling mode 10 DMAO request Only for UARTO request Only for UART2 11 DMA1 request Only for UART1 Receive Mode 1 0 Determine which function is currently able to read data from UART receive buffer register 00 Disable 01 Interrupt request or polling mode 10 DMAO request Only for UARTO request Only for UART2 11 DMA1 request Only for UART1 Note When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest 11 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCONO UFCON1 and UFCON2 in the UART bloc
264. eld MSR transfer register contents or immediate value to PSR flag bits only 31 28 27 26 25 24 23 22 21 12 11 0 e Fd 3e we 22 Destination PSR 0 1 SPSR lt mode 25 Immediate Operand 0 Source operand is a register 1 SPSH current mode 11 0 Source Operand 0 00000000 Rm 3 0 Source Register 11 4 Source operand is an immediate value 11 0 m 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 11 PSR Transfer ELECTRONICS 3 19 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR RESERVED BITS Only twelve bits of the PSR are defined in ARM920T N Z C V I F T M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM920T programs and future processors the following rules should be observed e reserved bits should be preserved when changing the value PSR Programs should not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the appropriate PSR register to a general register using the MRS instruction changing only the r
265. elevant bits and then transferring the modified value back to the PSR register using the MSR instruction EXAMPLES The following sequence performs a mode change MRS RO CPSR Take a copy of the CPSR BIC RO RO 0x1F Clear the mode bits ORR RO RO new_mode Select new mode MSR CPSR RO Write back the modified CPSR When the aim is simply to change the condition code flags in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR flg 0xF0000000 Setall the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as Sequential S cycle 3 20 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLY SYNTAX e MRS transfer PSR contents to a register MRS cond lt gt MSR transfer register contents to PSR lt psr gt Rm e MSR transfer register contents to PSR flag bits only lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp V flags respectively e MSR transfer immediate value to PSR flag bits only lt psrf gt lt expression gt
266. em should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour USE OF R15 Write back should not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 should not be specified as the register offset Rm When R15 is the source register Rd of a Half word store STRH instruction the stored address will be address of the instruction plus 12 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 1S 1N 11 LDR H SH SB PC take 2S 2N 1l incremental cycles S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STRH instructions take 2N incremental cycles to execute ELECTRONICS 3 37 ARM INSTRUCTION SET ASSEMBLER SYNTAX 53 2410
267. emory address of the corresponding bank DATA 31 0 DATA 31 0 Data Bus inputs data during memory read and outputs data during memory write The bus width is programmable among 8 16 32 bit nGCS 7 0 nGCS 7 0 General Chip Select are activated when the address of a memory is within the address region of each bank The number of access cycles and the bank size can be programmed nWE Write Enable indicates that the current bus cycle is a write cycle noe o nOE Output Enable indicates that the current bus cycle is a read cycle nXBREQ nXBREQ Bus Hold Request allows another bus master to request control of the local bus BACK active indicates that bus control has been granted nXBACK nXBACK Bus Hold Acknowledge indicates that the S3C2410 has surrendered control of local bus to another bus master nWAIT nWAIT requests to prolong a current bus cycle As long as nWAIT is L the current bus cycle cannot be completed SDRAM SRAM nSRAS SDRAM Row Address Strobe nSCAS SDRAM Column Address Strobe nSCS 1 0 O SDRAM Chip Select DQM 3 0 SDRAM Data Mask SCLK 1 0 SDRAM Clock SCKE SDRAM Clock Enable nBE 3 0 Upper Byte Lower Byte Enable In case of 16 bit SRAM nWBE 3 0 Write Byte Enable DE Command Latch Enable LE Address Latch Enable nFCE Flash Chip Enable nFRE Nand Flash Read Enable nFWE Nand Flash Write Enable NCON 1 0 Nand Flash Configuration V
268. eption occurs it will automatically switch into ARM state when the PC is loaded with the exception vector address Action on Leaving an Exception On completion the exception handler 1 Moves the Link Register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTES An explicit switch back to THUMB state is never needed since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception 2 10 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL Exception Entry Exit Summary Table 2 2 summarizes the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14 x MOV PC R14 MOVS PC R14 svc MOVS PC R14 und SUBS PC R14 4 SUBS PC R14 4 SUBS PC R14 abt 4 SUBS PC R14 abt 8 NA A A NOTES 1 Where is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority 3 Where PC is the address of the Load or Store instruction which generated the data abort 4 The value saved in R14_svc up
269. er the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range RO R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions For more information refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM920T contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are Hold information about the most recently performed ALU operation e Control the enabling and disabling of interrupts Setthe processor operating mode The arrangement of bits is shown in Figure 2 6 Condition Code Flags Reserved Control Bits 7 6 5 4 3 2 1 0 Lo Overflow Mode bits Carry Borrow Extend State bit Zero FIQ disable Negative Less Than IRQ disable Figure 2 6 Program Status Register Format ELECTRONICS 2 7 PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR The Condition Code Flags The Z and V bits are the condition code flags These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally s
270. ero disables all lookups in the cache while the translation table descriptor C bit Ctt being zero only stops new data being loaded into the cache With Ccr 1 and Ctt 0 the cache will still searched on every access to check whether the cache contains an entry for the data 2 Itis an operating system software error if a cache hit occurs when reading from or writing to a region of memory marked as NCNB or NCB The only way this can occur is if the operating system changes the value of the C and B bits in a page table descriptor while the cache contains data from the area of virtual memory controlled by that descriptor The cache and memory system behavior resulting from changing the page table descriptor in this way is unpredictable If the operating system needs to change the C and B bits of a page table descriptor it must ensure that the caches do not contain any data controlled by that descriptor In some circumstances the operating system may need to clean and flush the caches to ensure this ELECTRONICS 4 7 CACHES WRITE BUFFER ARM920T PROCESSOR A linefill performs an 8 word burst read from the ASB and places it as a new entry in the cache possible replacing another line at the same location within the cache The location which is replaced called the victim is chosen from the entries which are not locked using either a random or round robin replacement policy If the cache line being replaced is marked as dirty indicating that it h
271. ersion start by read mode is set to 1 A D conversion starts simultaneously whenever converted data is read X Conversion Y Conversion _ gt gt gt XP Stylus Down Stylus Up A B A Dx 1 X Tal Clock A 1 External Clock D x 1 PCLK Dx 1 PCLk D DELAY Value of ADCDLY Register Figure 16 3 Timing Diagram in Auto Sequential X Y Position Conversion Mode 16 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR A D CONVERTER AND TOUCH SCREEN ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL ADCCON REGISTER ADCCON 0x58000000 ADC control register ECFLG 15 End of conversion flag read only 0 A D conversion in process 1 End of A D conversion PRSCEN A D converter prescaler enable 0 Disable 1 Enable PRSCVL A D converter prescaler value Data value 1 255 Note that division factor is N 1 when the prescaler value is N SEL_MUX Analog input channel select 000 AINO 001 AIN 1 010 AIN 2 011 AIN3 100 AIN4 101 5 110 6 111 AIN 7 XP STDBM 2 Standby mode select 0 Normal operation mode 1 Standby mode READ_ START 1 A D conversion start by read 0 Disable start by read operation 1 Enable start by read operation ENABLE_START A D conversion starts by setting this bit If READ START is enabled this value is not valid 0 No operation 1 A D conversion starts and this bit is cleared after the start u
272. ertain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in Table 3 3 3 10 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected the C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the Z flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions AND 0000 Operand1 AND operand2 Operand2 operand1 is ignored Operand1 AND NOT operand2 Bit clear NOT operand2 operand1 is ignored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of
273. erwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved e base register is restored to its modified value if write back was requested This ensures recoverability in the case where the base register is also in the transfer list and may have been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 11 and LDM PC takes n 1 S 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal I cycle respectively STM instructions take n 1 S 2N incremental cycles to execute where n is the number of words transferred 3 44 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDM STM gt cond lt FD ED FA EAIIA IB DA DB gt Rn lt Rlist gt where cond Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 1 If present requests write back W 1 otherwise W 0 If present set bit to lo
274. ession If this is impossible it will give an error lt shift gt lt Shiftname gt lt register gt or lt shiftname gt expression or RRX rotate right one bit with extend lt shiftname gt s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code EXAMPLES ADDEQ R2 R4 R5 If the Z flag is set make R2 R4 R5 TEQS R4 3 Test R4 for equality with 3 The 5 is in fact redundant as the assembler inserts it automatically SUB R4 R5 R7 LSR R2 Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into R4 MOV PC R14 Return from subroutine MOVS PC R14 Return from exception and restore CPSR from SPSR mode ELECTRONICS 3 17 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ TST CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the CPSR or SPSR mode to be moved to a general register The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR mode register The MSR instruction also allows an immediate val
275. et to 1 For example MRC p15 0 Rd c0 c0 1 returns cache details The format of the register is shown in Table 2 6 Table 2 6 Cache Type Register Format Ree Fen vae Red am S wo a hm SS hs 2 ee Bits 28 25 indicate which major cache class the implementation falls into 0x6 means that the cache provides e Cache clean step operation e Cache flush step operation e Lock down facilities 2 8 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Bits 20 18 give the data cache size Bits 8 6 give the instruction cache size Table 2 7 on page 2 9 shows the meaning of values used for cache size encoding Table 2 7 Cache Size Encoding mw s Bits 17 15 give the data cache associativity Bits 5 3 give the instruction cache associativity Table 2 8 on page 2 9 shows the meaning of values used for cache associativity encoding Table 2 8 Cache size encoding mw s Bits 13 12 give the data cache line length Bits 1 0 give the instruction cache line length ELECTRONICS 2 9 PROGRAMMER S MODEL ARM920T PROCESSOR Table 2 9 shows the meaning of values used for line length encoding Table 2 9 Line Length Encoding Bits 13 12 Bits 1 0 Words Per Line 0 2 REGISTER 1 CONTROL REGISTER This register contains the control bits of the ARM920T All reserved bits should either be written with zero or one as indicated or written using read mod
276. fer of R1 R5 and R7 in the case where Rn 0x1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses do not affect the instruction However the bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 0x100C 0x100C 0 1000 0 1000 OxOFF4 1 Ox100 0x1000 OxOFF4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 41 ARM INSTRUCTION SET 3 42 53 2410 RISC MICROPROCESSOR 0x100C 0x1000 OxOFF4 0x1000 0x100C 0x1000 5 0x1000 2 7 5 1 4 7 3 Figure 3 21 Post Decrement Addressing 0x100C 0x1000 OxOFF4 0x100C 0x1000 OxOFF4 0x100C 0x1000 OxOFF4 0x100C 0x1000 OxOFF4 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET 0x100C 0x100C 0x1000 0x1000 OxOFF4 1 xt 00 0x1000 OxOFF4 Figure 3 22 Pre Decrement Addressing USE OF THE S BIT When the S bit is
277. fered writes read lock write sequence to non cacheable memory In the case of a read lock write SWP sequence in which the read aborts the write will always be attempted 3 24 ELECTRONICS ARM920T PROCESSOR MMU INTERACTION OF THE MMU AND CACHES The MMU is enabled and disabled using bit 0 of the CP15 control register ENABLING THE MMU To enable the MMU 1 Program the translation table base and domain access control registers 2 Program level 1 and level 2 page tables as required 3 Enable the MMU by setting bit 0 in the control register Care must be taken if the translated address differs from the untranslated address as several instructions following the enabling of the MMU may have been prefetched with the MMU off using physical virtual address flat translation and enabling the MMU may be considered as a branch with delayed execution A similar situation occurs when the MMU is disabled Consider the following code sequence MRC p15 0 R1 c1 CO 0 Read control rejection R1 0x1 MCR p15 0 R1 C1 C0 0 Enable MMUS Fetch Flat Fetch Flat Fetch Translated The instruction and data caches can be enabled simultaneously with the MMU using a single MCR instruction DISABLING THE MMU To disable the MMU clear bit 0 in the control register The data cache should be disabled prior to or at the same time as the MMU is disabled by clearing Bit 2 of the control register See the paragraph in Enabling the MMU regar
278. flag Last received bit status flag 20 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE MULTI MASTER IIC BUS ADDRESS IICADD REGISTER IICADD 0x54000008 RW IIC Bus address register Slave address 7 0 7 bit slave address latched from the IIC bus XXXXXXXX When serial output enable 0 in the IICSTAT IICADD is write enabled The IICADD value can be read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER Register Address R W Description Reset Value AN IICDS 0x5400000C IIC Bus transmit receive data shift register Data shift 7 0 8 bit data shift register for Tx Rx operation XXXXXXXX When serial output enable 1 in the IICSTAT IICDS is write enabled The IICDS value can be read any time regardless of the current serial output enable bit IICSTAT setting ELECTRONICS 20 13 IIC BUS INTERFACE 53 2410 01 RISC MICROPROCESSOR NOTES 20 14 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIS BUS INTERFACE 05 22 2002 2 1 IIS BUS INTERFACE PRELIMINARY OVERVIEW Currently many digital audio systems are attracting the consumers on the market in the form of compact discs digital audio tapes digital sound processors and digital TV sound The S3C2410X01 Inter IC Sound IIS bus interface can be u
279. flag for these instructions even if this is not specified in the mnemonic The TEQP form of the TEQ instruction used in earlier ARM processors must not be used the PSR transfer operations should be used instead The action of TEQP in the ARM920T is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode INSTRUCTION CYCLE TIMES Data Processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Data processing with register specified shift and PC written 25 1N 11 NOTE 5 1 as defined sequential S cycle non sequential N cycle and internal I cycle respectively em 3 16 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET ASSEMBLER SYNTAX e MOV MVN single operand instructions lt opcode gt cond S Rd lt Op2 gt e CMP CMN TEQ TST instructions which do not produce a result lt opcode gt cond Rn lt Op2 gt e AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt Op2 gt where lt Op2 gt Rm lt shift gt or lt expression gt cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number lt gt If this is used the assembler will attempt generate a shifted immediate 8 bit field to match the expr
280. following the BL is placed in LR and bit 0 of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction 4 38 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 4 20 The BL Instruction THUMB assembler ARMequivalent Action BL label none LR PC OffsetHigh 12 1 temp next instruction address PC LR OffsetLow lt lt 1 LR temp 1 EXAMPLES BL faraway Unconditionally Branch to faraway next and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned ELECTRONICS 4 39 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than using a sequence of 4 or mo
281. format have an equivalent ARM instruction as shown in Table 4 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine 4 32 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 12 11 10 8 m ms 7 0 Register List 10 8 Base Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 16 Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 4 16 The Multiple Load Store Instructions THUMB assembler ARMequivalent STMIA Rb Rlist STMIA Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address LDMIA Rb Rlist LDMIA Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction
282. fresh_count 1 HCLK Ex If refresh period is 15 6 us and HCLK is 60 MHz the refresh count is as follows Refresh count 2 1 60x15 6 1113 ELECTRONICS 5 17 MEMORY CONTROLLER S3C2410X01 RISC MICROPROCESSOR BANKSIZE REGISTER BANKSIZE 0x48000028 Flexible bank size register BURST_EN ARM core burst operation enable 0 Disable burst operation 1 Enable burst operation 7 4 SCKE_EN 5 SDRAM power down mode enable control by SCKE 0 SDRAM power down mode disable 1 SDRAM power down mode enable BK76MAP 2 0 BANK6 7 memory 010 128MB 128MB 001 64MB 64MB 000 32M 32M 111 16M 16M 110 8M 8M 101 4 4 100 2M 2M SCLK_EN SCLK is enabled only during SDRAM access cycle for reducing power consumption When SDRAM is not accessed SCLK becomes L level 0 SCLK is always active 1 SCLK is active only during the access recommended 5 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER SDRAM MODE REGISTER SET REGISTER MRSR MRSRB6 0x4800002C MRSRB7 0x48000030 imag WBL Mode register set register bank6 Mode register set register bank7 pp Write burst length X Xx XXX X XX 0 Burst Fixed 1 Reserved Test mode 00 Mode register set Fixed 01 10 and 11 Reserved CAS latency 000 1 clock Others reserved 010 2 clocks 01123 clocks Burst type 0 Sequential Fixed 1 Reserved Burst length 000 1 Fixed Othe
283. fter 00 0 clock 10 2 clocks Tcah 5 4 Address hold time after nGCSn 00 0 clock 01 1clock 1022clocks 11 4 clocks Tacp 3 2 Page mode access cycle Page mode 00 2 clocks 10 4 clocks 11 6 clocks 1 0 Page mode configuration 00 normal 1 data 1028 consecutive accesses 11 16 consecutive accesses Memory Type SDRAM MT 11 4 bit Trcd 3 2 RAS to CAS delay 00 2 clocks 5 16 01 3 clocks 10 4 clocks SCAN 1 0 Column address number 00 8 bit 9 bi 01 9 bit 001 2 clocks 011 4 clocks 101 8 clocks 111 14 clocks 01 1 clock 11 4 clocks 01 3 clocks 01 4 consecutive accesses 10 10 bit ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER REFRESH CONTROL REGISTER REFRESH 0x48000024 SDRAM refresh control register 0 0000 C RERESH Bh Description REFEN 23 SDRAM Refresh Enable 0 Disable 1 Enable self or CBR auto refresh TREFMD 22 SDRAM Refresh Mode 0 CBR Auto Refresh 1 Self Refresh In self refresh time the SDRAM control signals are driven to the appropriate level Trp 21 20 SDRAM RAS pre charge Time 00 2 clocks 01 3 clocks 19 18 SDRAM RC minimum Time 00 4 clocks 01 5 clocks 10 6 clocks 11 7 clocks 1511 Refresh 10 0 SDRAM refresh count value Refer to chapter 6 SDRAM refresh Counter controller bus priority section Refresh period 2 re
284. fter the present transmission word is transmitted completely After the break signal transmission it continuously transmits data into the Tx FIFO Tx holding register in the case of Non FIFO mode Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can detect overrun error parity error frame error and break condition each of which can set an error flag The overrun error indicates that new data has overwritten the old data before the old data has been read The parity error indicates that the receiver has detected an unexpected parity condition The frame error indicates that the received data does not have a valid stop bit The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time Receive time out condition occurs when it does not receive any data during the 3 word time this interval follows the setting of Word Length bit and the Rx FIFO is not empty in the FIFO mode ELECTRONICS 11 3 UART 53 2410 01 RISC MICROPROCESSOR Auto Flow Control AFC The S3C2410X01 s UART 0 and UART 1 support auto flow control with nRTS and nCTS signals In case it can be connected to external UARTS If users want to connect a UART to a Modem disable auto flow control bit in UMC
285. ftware correcting 4 The Steppingstone 4 KB internal SRAM buffer can be used for another purpose after NAND flash booting This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 6 1 NAND FLASH CONTROLLER 3C2410X01 RISC MICROPROCESSOR BLOCK DIAGRAM System Bus InternalL Butter 4KB Contrlol Register Bank State Machine ECC NAND Flash Encoder Decoder Interface Figure 6 1 NAND Flash Controller Block Diagram OPERATION SCHEME Auto Boot Mode CPU Access Boot Code c Steppingstone 4 KB Buffer NAND Flash Controller oon Flash Mode Figure 6 2 NAND Flash Operation Scheme User Access Special Function Registers 6 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR NAND FLASH CONTROLLER 05 25 2002 AUTO BOOT MODE SEQUENCE 1 Reset is completed 2 When the auto boot mode is enabled the first 4 KBytes of NAND flash memory is copied onto Steppingstone 4 KB internal buffer 3 The Steppingstone is mapped to nGCSO 4 CPU starts to execute the boot code on the Steppingstone 4 KB internal buffer Note In the auto boot mode ECC is not checked So The first 4 KBytes of NAND flash should have no bit e
286. g the current values of the PC and CPSR into them The value of the saved PC and SPSR is not defined Forces M 4 0 to 10011 Supervisor mode sets the and F bits in the CPSR and clears the CPSR s T bit Forces the PC to fetch the next instruction from address 0x00 Execution resumes in ARM state ELECTRONICS 2 15 PROGRAMMER S MODEL 2 16 NOTES 53 2410 RISC MICROPROCESSOR ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core FORMAT SUMMARY The ARM instruction set formats are shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109876543210 es one m mr cons ove mm me 0 1 EN 0000 Cond Offset Cond CP CRn CP CP CRm Opc Cond 00 1 1 Ignored by processor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109876543210 Figure 3 1 ARM Instruction Set Format ELECTRONICS ARM INSTRUCTION SET Data Processing PSR Transfer Multiply Multiply Long Single Data Swap Branch and Exchange Halfword Data Transfer register offset Halfword Data Transfer immendiate offset Single Data Transfer Undefined Block Data Transfer Branch Coprocessor Data Transfer Co
287. ges may be made under software control or may be brought about by external interrupts or exception processing Most application programs will execute in User mode The non user modes known as privileged modes are entered in order to service interrupts or exceptions or to access protected resources REGISTERS ARM920T has a total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode dictate which registers are available to the programmer The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non User modes mode specific banked registers are switched in Figure 2 3 shows which registers are available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers RO to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register used to store status information Register 14 is used as the subroutine link register This receives a copy of R15 when a Branch and Link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14 svc R14 irq R14 R14 abt and R14 und are similarly used to hold the return values of
288. gether the value in Rb and the value in Ro Store the contents of Rd at the address STRB Rb STRB Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rad Rb Ro LDR Rb Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into Rd LDRB Rd Rb LDRB Rd Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro Load the byte value at the resulting address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 80 87 Load into R2 the byte found at the address formed by adding R7 to RO ELECTRONICS 4 19 THUMB INSTRUCTION SET S3C2410X RISC MICROPROCESSOR FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALFWORD 15 14 13 12 11 10 9 8 6 5 3 2 0 hm 2 0 Destination Register 5 3 Base Register 8 6 Offset Register 10 Sign Extended Flag 0 Operand not sing extended 1 Operand sing extended 11 H Flag Figure 4
289. gment x 26 bits row There are two test interfaces to the PA TAG RAM Debug interface see Scan chain 4 debug access to the PA TAG RAM AMBA test interface see PA TAG RAM test 4 12 ELECTRONICS ARM920T PROCESSOR CLOCK MODES APPENDIX 5 CLOCK MODES OVERVIEW The ARM920T has two functional clock inputs BCLK and Internally the 920 is clocked by GCLK which can be seen on the CPCLK output as shown in Figure 5 1 GCLK can be sourced from either BCLK or FCLK depending on the clocking mode selected using nF bit and iA bit in CP15 register 1 see Register 1 Control register on page 2 10 The three clocking modes are FastBus synchronous and asynchronous The ARM920T is a static design and both clocks can be stopped indefinitely without loss of state From Figure 5 1 it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK which can be either FCLK or BCLK depending on the clocking mode CPCLK ARM920T MO AMBA bus Rest of ARM920T interface Figure 5 1 ARM920T Clocking ELECTRONICS 5 1 CLOCK MODES ARM920T PROCESSOR FASTBUS MODE In this mode of operation the BCLK input is the source for GCLK The FCLK input is ignored This mode is typically used in systems with high speed memory SYNCHRONOUS MODE This mode is typically used in systems with low speed memory In this mode GCLK can be sourced from BCLK and FCLK BCLK is used to control the AMBA memory in
290. h each bit corresponding to a register A 1 in bit 0 of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 28 27 25 24 23 22 21 20 19 16 15 0 Lus p 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 40 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre post bit P and the up down bit U The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lowest register also gets transferred to from the lowest memory address By way of illustration consider the trans
291. hat this is a coarse page table descriptor Indicates that this is a section descriptor Fine page table Indicates that this is a fine page table descriptor 3 8 ELECTRONICS ARM920T PROCESSOR MMU SECTION DESCRIPTOR Bits 3 2 C amp B indicate whether the area of memory mapped by this section is treated as write back cacheable write through cacheable non cached buffered or non cached non buffered Bit 4 should be written to 1 for backward compatibility Bits 8 5 specify one of the 16 possible domains held in the domain access control registers that contain the primary access controls Bit 9 is always written as 0 Bits 11 10 AP specify the access permissions for this section Bits 19 12 are always written as 0 Bits 31 20 form the corresponding bits of the physical address for a section COARSE PAGE TABLE DESCRIPTOR Bits 3 2 are always written as 0 Bit 4 is always written as 1 Bits 8 5 specify one of the 16 possible domains held in the Domain access control registers that contain the primary access controls Bit 9 is always written as 0 Bits 31 10 form the base for referencing the level two descriptor The coarse page table index for the entry is derived from the modified virtual address If a coarse page table descriptor is returned from the level one fetch a level two fetch is initiated FINE PAGE TABLE DESCRIPTOR Bits 3 2 are always written as 0 Bit 4 is always written as 1 Bits 8 5 specify
292. he baud rate divisor register UBRDIVn is used to determine the serial Tx Rx clock rate baud rate as follows UBRDIVn int PCLK bps x 16 1 or UBRDIVn int UCLK bps x 16 1 Where the divisor should be from 1 to 2 1 and UCLK should be smaller than PCLK For example if the baud rate is 115200 bps and PCLK or UCLK is 40 MHz UBRDIVn is UBRDIVn in ___ 50000028 Rw rate J 65005408 RW rate dvsiorregitert oxs0008026 RW Bava rate UBRDIV 15 0 Baud rate division value UBRDIVn gt 0 11 20 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB HOST 05 24 2002 USB HOST CONTROLLER OVERVIEW 3C2410 supports 2 port USB host interface as follows Rev 1 0 compatible USB Rev1 1 compatible e Two down stream ports Support for both LowSpeed and HighSpeed USB devices gt RCFO RegData 32 APP_SDATA 32 CONTROL USB CONTROL STATE gt HGI DATA 32 CONTROL TxEnl CONTROL CONTROL TxDpls a LIST TxDmns gt ED TD_DATA 32 ae ED TD STATUS 32 ED amp TD APP MDATA 32 REGS aa HCM ADH RcvData RcvDpls DATA 32 14 STATUS i RcvDmns 4 4 CONTROL HC DATA 8 RH DATA 8 DF_DATA 8 DF DATA 8 gg 5
293. he conditions encoded by the field the instruction is executed otherwise it is ignored There are sixteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a Branch B in assembly language becomes BEQ for Branch if Equal which means the Branch will only be taken if the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary sm Fm ignore 3 4 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the program counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or THUMB instructions 28 27 24 23 20 19 16 15 12 11 ooo 3 0 Operand
294. he packet as the number is unloaded by the MCU Register Address R W Description Reset Value OUT FIFO CNT1 REG 0x52000198 L R End Point out write count register1 0x00 0x5200019B B byte OUT FIFO CNT1 REG Bit MCU USB Description Initial State OUT CNT LOW 7 0 Lower byte of write count OUT_FIFO_CNT2_REG 0x5200019C L R End Point out write count register2 0x00 0x5200019F B byte OUT CNT HIGH 7 0 W Higher byte of write count The OUT CNT HIGH may be always 0 normally 13 20 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE DMA INTERFACE CONTROL REGISTER EPN DMA CON EP1 DMA CON 0x52000200 L R W EP1 DMA interface control register 0x00 0x52000203 B byte EP2 DMA CON 0x52000218 L R W EP2 DMA interface control register 0x00 0x5200021B B byte CON 0x52000240 L R W EP3 interface control register 0x00 0x52000243 B byte 4 CON 0x52000258 L R W EP4 interface control register 0x00 0x5200025B B byte EPn_DMA_CON MCU Description Initial State RUN_OB 7 R W Read DMA Run Observation 0 DMA is stopped 1 DMA is running Write Ignore EPn_DMA_TTC_n register 0 DMA requests will be stopped if EPn TTC n reaches 0 1 DMA requests will be continued although EPn_DMA_TTC_n reaches 0 STATE 6 4 w DMA State Monitoring DEMAND_MODE 3 R W DMA Demand mode enable bit 0 Demand mode disable 1 Demand mode enable OUT_RUN_OB 2 R W R W Funct
295. he page header After formal publishing we will show the revision with a proper version number ELECTRONICS 13 1 USB DEVICE RT_VM_IN RT_VP_IN RXD RT_VP_OUT RT_VM_OUT RT_UX_OEN RT_UXSUSPEND 53 2410 01 RISC MICROPROCESSOR MC ADDR 13 0 DATA IN 31 0 MC DATA OUT 31 0 USB CLK SYS CLK SYS RESETN MC WR WR RDN MC CSN MC INTR DREQN 3 0 DACKN 3 0 Figure 13 1 USB Device Controller Block Diagram ELECTRONICS 3C2410X01 RISC MICROPROCESSOR USB DEVICE USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB device controller All special function register is byte accessible or word accessible If you access byte mode offset address is different in little endian and big endian All reserved bit is zero Common indexed registers depend on INDEX register INDEX_REG offset address 0X178 value For example if you want to write EPO CSR register you must write 0x00 on the INDEX REG before writing IN CSR1 register NOTE All register must be resettled after performing Host Reset Signaling Register Name Description NON INDEXED REGISTERS FUNC_ADDR_REG PWR_REG Power management register 0x144 L EP INT REG EPO EP4 Endpoint interrupt register 0x148 L 0x14B B USB INT REG USB interrupt register 0x158 L Ox15B B EP INT EN REG EP0 EP4 Endpoint interrupt enable register USB INT EN REG USB Interrupt enable register 0x1
296. he transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer TRANSFERS FROM R15 A coprocessor register transfer from ARM920T with R15 as the source register will store the PC 12 INSTRUCTION CYCLE TIMES MRC instructions take 1 6 1 1 1C incremental cycles to execute where S I and are defined as sequential S cycle internal I cycle and coprocessor register transfer C cycle respectively MCR instructions take 1S bl 1C incremental cycles to execute where 6 is the number of cycles spent in the coprocessor busy wait loop ASSEMBLER SYNTAX lt p lt expression1 gt Rd cn cm lt expression2 gt Move from coprocessor to ARM920T register L 1 MCR Move from ARM920T register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field Rd An expression evaluating to a valid ARM920T register number cn and cm Expressions evaluating to the valid coprocessor register numbers CRn and CRM respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 c5 and and transfer the single 32 bit word result back to MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 on R4 and place the result in
297. ic interrupt source the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly If you return from the ISR without clearing the bit the interrupt controller operates as if another interrupt request came in from the same source In other words if a specific bit of the SRCPND register is set to 1 it is always considered as a valid interrupt request waiting to be serviced The time to clear the corresponding bit depends on the user s requirement If you want to receive another valid request from the same source you should clear the corresponding bit first and then enable the interrupt You can clear a specific bit of the SRCPND register by writing a data to this register It clears only the bit positions of the SRCPND corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are SRCPND 0X4A000000 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 14 6 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INT SPI1 0 Notrequested 1 Requested INT_UARTO 0 Not requested 1 Requested INT_IIC 0 Not requested 1 Requested INT_UART1 0 Not requested 1 Requested INT_SPIO 0 Not requested 1 Requested INT_DMA2 0 Not requested 1 Requested INT DMA1 0 Not requested
298. idation is required when the process ID is changed At reset the DCache and ICache entries are all invalidated and the DCache and ICache are disabled The software design also needs to consider that the pipelined design of the ARM9TDMI core means that it fetches three instructions ahead of the current execution point So for example the three instructions following an MCR which invalidates the ICache will have been read from the ICache before it is invalidated ELECTRONICS 4 11 CACHES WRITE BUFFER ARM920T PROCESSOR CACHE CLEANING WHEN LOCKDOWN IS IN USE The clean D single entry using index and clean and invalidate D entry using index operations can leave the victim pointer set to the index value used by the operation In some circumstances if DCache locking is in use this could leave the victim pointer in the locked region leading to locked data being evicted from the cache The victim pointer can be moved outside the locked region by implementing the cache loop enclosed by the reading and writing of the Base and Victim pointer MRC p15 0 c9 0 0 Read D Cache Base into Rd Index Clean or Index Clean and Invalidate loops MCR p15 0 c9 0 0 Write D Cache Base and Victim from Rd Clean D single entry using VA and clean and invalidate D entry using VA operations do not move the victim pointer so there is no need to reposition the victim pointer after using these operations IMPLEMENTATION NOTES This sec
299. ify write The reserved bits have an unpredictable value when read To read and write this register MRC p15 0 Rd c1 0 0 read control register MCR p15 0 Rd c1 cO 0 write control register All defined control bits are set to zero on reset except the V Bit which is set to zero at reset if the VINITHI pin is LOW or one if the VINITHI pin is HIGH The functions of the control bits are shown in Table 2 10 2 10 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Table 2 10 Control Register 1 bit Functions Register Bits Name Funcion Value Asynchronous clock select See Table 2 11 on page 2 11 30 notFastBus select See Table 2 11 on page 2 11 29 15 Reserved Read Unpredictable Write Should be zero Round robin replacement 0 Random replacement 1 Round robin replacement V bit Base location of exception 0 Low addresses 0 0000 0000 registers 1 High addresses OxFFFF 0000 Instruction cache enable Instruction cache disabled Instruction cache enabled 11 10 Reserved Read 00 Write 00 R bit ROM protection This bit modifies the MMU protection system See Table 3 6 on page 3 20 S bit System protection This bit modifies the MMU protection system See Table 3 6 on page 3 20 7 B bit Big endian little endian 0 Little endian operation 1 Big endian operation 6 3 Reserved Read 1111 Write 1111 2 C bit Data cache enable 0 Data cache disabled 1 Data cache enabled 1 A bit Alignment
300. igured as polling mode with SMOD bits and clearing TAGD bit If SPSTAn s REDY flag is set then read the last byte data Note Total received data DMA TC values the last data in polling mode Step 9 The first DMA received data is dummy and so the user can neglect it This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 22 5 SPI INTERFACE S3C2410X01 RISC MICROPROCESSOR SPI SPECIAL REGISTERS SPI CONTROL REGISTER SPCONO 0x59000000 SPI channel 0 control register SPCON1 0x59000020 SPI channel 1 control register SPCONn ET SPI Mode Select Determine how and by what SPTDAT is read written SMOD 00 polling mode 01 interrupt mode 10 DMA mode 11 reserved SCK Enable 4 Determine whether you want SCK enable or not for only master ENSCK 0 disable 1 enable Master Slave Determine the desired mode master or slave Select MSTR 0 slave 1 master Note In slave mode there should be set up time for master to initiate Tx Rx Clock Polarity Determine an active high or active low clock Select CPOL 0 active high 1 active low Select CPHA format A 1 format B Tx Auto Garbage n whether the receiving data only needs or not Data mode enable 0 normal mode 1 Tx auto garbage data mode TAGD Note In normal mode if
301. in Virtual Display Single Scan 15 24 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 LCD POWER ENABLE STN TFT The S3C2410X01 provides Power enable PWREN function When PWREN is set to make PWREN signal enabled the output value of LCD PWREN pin is controlled by ENVID In other words If LCD PWREN pin is connected to the power on off control pin of the LCD panel the power of LCD panel is controlled by the setting of ENVID automatically The 53 2410 01 also supports INVPWREN bit to invert polarity of the PWREN signal This function is available only when LCD panel has its own power on off control port and when port is connected to LCD PWREN pin ENVID LCD PWREN VFRAME STN LCD LCD PWREN VSYNC HSYNC VDEN lt 4 1 FRAME TFT LCD Figure 15 8 Example of PWREN function PWREN 1 INVPWREN 0 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 25 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Reset Value LCDCON1 0X4D000000 R W LCD control 1 register 0x00000000 LINECNT 27 18 Provide the status of the line counter 0000000000 read only Down count from LINEVAL to 0 CLKVAL 17 8 Determine the rates of VCLK
302. ines and for cleaning or invalidating DCache lines or for invalidating the entire DCache To clean the entire DCache efficiently software should loop though each cache entry using the clean D single entry using index operation or the clean and invalidate D entry using index operation This should be performed by a two level nested loop going though each index value for each segment See Data cache organization on page 4 9 DCache and memory coherence is generally achieved by e cleaning the DCache to ensure memory is up to date with all changes e invalidating the ICache to ensure that the ICache is forced to re load instructions from memory Software can minimize the performance penalties of cleaning and invalidating caches by e Cleaning only small portions of the cache when only a small area of memory needs to be made coherent for example when updating an exception vector entry e invalidating only small portions of the ICache when only a small number of instructions are modified for example when updating an exception vector entry e Not invalidating the ICache in situations where it is known that the modified area of memory cannot be in the cache for example when mapping a new page into the currently running process The ICache needs to be made coherent with a changed area of memory after any changes to the instructions which appear at a virtual address and before the new instructions are executed Dirty data in
303. ing UB LB for bank 6 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS6 26 Determine WAIT status for bank 6 0 WAIT disable 1 WAIT enable DW6 25 24 Determine data bus width for bank 6 00 28 bit 01 16 bit 10 32 bit 11 reserved ST5 23 Determine SRAM for using UB LB for bank 5 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 0 WS5 22 Determine WAIT status for bank 5 0 WAIT disable 1 WAIT enable DW5 21 20 Determine data bus width for bank 5 00 8 bit 01 16 bit 10 32 bit 11 reserved ST4 19 Determine SRAM for using UB LB for bank 4 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS4 18 Determine WAIT status for bank 4 0 WAIT disable 1 WAIT enable DWA 17 16 Determine data bus width for bank 4 00 8 bit 01 16 bit 10 32 bit 11 reserved ST3 15 Determine SRAM for using UB LB for bank 3 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS3 14 Determine WAIT status for bank 3 0 WAIT disable 1 WAIT enable DW3 13 12 Determine data bus width for bank 3 00 8 bit 01 16 bit 10 32 bit 11 reserved ST2 11 Determine SRAM for using UB LB for bank 2 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated
304. ionally separated into write and read operation OUT_DMA_RUN Write operation 0 Stop 1 Run Read operation OUT DMA Run Observation IN DMA RUN 1 RAN Start DMA operation 0 Stop 1 Run DMA_MODE_EN R W R Clear Set DMA mode If the RUN OB has been wrtten as 0 and EPn_DMA_TTC_nreaches 0 MODE EN bit will be cleared by USB 0 Interrupt Mode 1 DMA Mode gt gt ELECTRONICS 13 21 USB DEVICE 53 2410 01 RISC MICROPROCESSOR DMA UNIT COUNTER REGISTER EPN_DMA_UNIT This register is valid in Demand mode In other modes this register value must be set to 0x01 Register Address Description Reset Value EP1 DMA UNIT 0x52000204 R W EP1 DMA transfer unit counter base register 0x00 0x52000207 EP2 DMA UNIT 0x5200021C EP2 DMA transfer unit counter base register 0x00 0x5200021F EP3 DMA UNIT 0x52000244 R W EPS3DMA transfer unit counter base register 0x00 0x52000247 T EP4 UNIT 0x5200025C EP4 DMA transfer unit counter base register 0x00 0x5200025F bus har pl AAJN EPn_UNIT_CNT 7 0 R W R EP DMA transfer unit counter value 0x00 13 22 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE DMA FIFO COUNTER REGISTER EPN_DMA_FIFO This register has values in byte size in FIFO to be transferred by DMA In case of OUT DMA RUN enabled the value in OUT FIFO
305. irectly as in the S3C2410X01 without PLL In this mode the power consumption depends on the frequency of the external clock only The power consumption due to PLL is excluded IDLE mode the block disconnects clocks FCLK only to the CPU core while it supplies clocks to all other peripherals The IDLE mode results in reduced power consumption due to CPU core Any interrupt request to CPU can be woken up from the Idle mode Power OFF mode the block disconnects the internal power So there occurs no power consumption due to CPU and the internal logic except the wake up logic in this mode Activating the Power OFF mode requires two independent power sources One of the two power sources supplies the power for the wake up logic The other one supplies other internal logics including CPU and should be controlled for power on off In the Power OFF mode the second power supply source for the CPU and internal logics will be turned off The wakeup from Power OFF mode can be issued by the EINT 15 0 or by RTC alarm interrupt This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 7 1 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7 1 shows a block diagram of the clock architecture The main clock source comes from
306. is the data of line 7 of virtual screen This is the data of line 7 e virtual screen This is the data of line 8 of virtual screen View Port The same size of LCD panel This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen Vhis is the data of line 11 of virtual screen LCDBASEU Before Scrolling LCDBASEL This is the data of 1 of virtual screen This is the data of line virtual screen This is the data of line of vi This is the data of line 4 of virtua screen This is the data of line 5 of virtua screen This is the data of 6 of virtua screen This is the data of line 779 virtua screen This is the data of line 8 of virtua screen This is the data of line 9 of virtual screen screen This is the data of line 1 of virtual screen This is the data of line 2 of virtual screen This is the data of line 3 of virtual screen This is the Qata of line 4 of virtual sqreen This is the data of line 5 of virtual sqreen This is the data of line 6 of virtual sqreen This is the data of line 7 of virtual sqreen This is the data of line 8 of virtual sqreen This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen After Scrolling Figure 15 7 Example of Scrolling
307. ister 0x8000 Count value 15 0 The current count value of the watchdog timer 0x8000 8 4 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR SD HOST CONTROLLER 05 25 2002 Secure Digital Interface for SDIO SDI Features SD Memory Card Spec ver 1 0 MMC Spec 2 11 compatible SDIO Card Spec ver 1 0 compatible 16 words 64 bytes FIFO depth 16 for data Tx Rx 40 bit Command Register SDICARG 31 0 SDICCON 7 0 136 bit Response Register SDIRSPn 127 0 SDICSTA 7 0 8 bit Prescaler logic Freq System Clock 2 P 1 CRC7 amp CRC16 Generator Normal and DMA Data Transfer Mode byte or word transfer 1bit 4bit wide bus Mode 8 Block Stream Mode Switch support BLOCK DIAGRAM CMD Reg CMD Control bbyte m PADDR Resp Reg 8 CRC7 RxCMD PSEL 17byte gt Prescaler SDCLK gt TxCMD PWDATA 32 32 DAT Control 32 32 4 RxDAT 3 0 DREQ gt INT This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 19 1 SD HOST CONTROLLER 53 2410 01 RISC MICROPROCESSOR SD OPERATION A serial clock line is synchronized with the five data lines for shifting and s
308. k UFCONO 0x50000008 RAN UART channel 0 FIFO control register UFCON1 0x50004008 UART channel 1 FIFO control register UFCON2 0x50008008 R W UART channel 2 FIFO control register oxo Tx FIFO Trigger Level Determine the trigger level of transmit FIFO 00 Empty 01 4 byte 10 8 byte 11 12 byte Rx FIFO Trigger Level Determine the trigger level of receive FIFO 00 4 byte 01 8 byte 10 12 byte 11 16 byte SSCs Tx FIFO Reset 2 Auto cleared after resetting FIFO 0 Normal 1 Tx FIFO reset Rx FIFO Reset 1 Auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset FIFO Enable 0 0 Disable 1 Enable Note When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest ELECTRONICS 11 13 UART 53 2410 01 RISC MICROPROCESSOR UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCONO and UMCON 1 in the UART block UMCONO 0x5000000C RAN UART channel 0 Modem control register 0 0 Reserved der omon Ta oesi Reserved EU If AFC bit is disabled nRTS must be controlled by software 0 H level Inactivate nRTS 1 L level Activate nRTS Request to Send If AFC bit is enabled this value will be ig
309. l A 31 A 30 L 31 L 30 LCD Panel A 31 A 30 A 29 A 0 B 31 B 30 B 0 C 31 01 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 9 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR MEMORY DATA FORMAT STN BSWP 0 CONTINUED In 4 level gray mode 2 bits of video data correspond to 1 pixel In 16 level gray mode 4 bits of video data correspond to 1 pixel In 256 level color mode 8 bits 3 bits of red 3 bits of green and 2 bits of blue of video data correspond to 1 pixel The color data format in a byte is as follows sis Bursa Gee Bu In 4096 level color mode 12 bits 4 bits of red 4 bits of green 4 bits of blue of video data correspond to 1 pixel The following table shows color data format in words Video data must reside at 3 word boundaries 8 pixel as follows RGB order DATA 6724 mau neas ma ird 15 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 VD3 VD2 VD1 VDO VD3 VD2 VD1 4 bit Dual Scan Display VD2 VD1 VDO VD3 VD2 VD1 4 bit Single Scan Display VD6 VD5 VD3 VDO 8 bit Single Scan Display
310. larm date data register 0x01 0x57000063 B by byte gp om DATEDATA 5 4 BoD value for alarm date from 0 to 28 29 30 31 ALARM MON DATA ALMMON REGISTER ALMMON 0x57000064 L R W Alarm month data register 0x01 0x57000067 B by byte MONDATA _ BCD value for alarm month mm 24 8 0 0 ALARM YEAR DATA ALMYEAR REGISTER ALMYEAR 0x57000068 L R W Alarm year data register 0x0 0x5700006B B by byte YEARDATA 7 0 BCD value for year 0x0 00 99 ELECTRONICS 17 7 REAL TIME CLOCK S3C2410X01 RISC MICROPROCESSOR RTC ROUND RESET RTCRST REGISTER RTCRST 0x5700006C L R W RTC round reset register 0 0 0x5700006F B by byte RTCRST Round second reset enable SRSTEN 0 Disable 1 Enable SECCR 2 0 Round boundary for second carry generation 011 over than 30 sec 100 over than 40 sec 101 over than 50 sec Note If other values 0 1 2 6 or 7 are set no second carry is generated But second value can be reset BCD SECOND BCDSEC REGISTER RIW Reset Value BCDSEC 0x57000070 L R W BCD second register Undefined 0x57000073 B by byte SECDATA 6 4 BCD value for second 0 5 Bo fors BCD MINUTE BCDMIN REGISTER BCDMIN 0x57000074 L R W BCD minute register Undefined 0x57000077 B by byte MINDATA 6 4 BCD value for minute 0 5 9 3 0 17 8 ELECTRONICS 53 2410 01 RISC MICROPROCE
311. le 15 4 5 6 5 Format INDEXBiPos 15 14 13 12 11 10 9 7 6 5 43 21 01 Address edi al i i ad iil rea Ra Ri Gs Ge as 61 ao 8s oxapooosos C Ro Gs Ge o Gs 6 8s Number vB ss 22 21 2010 15 7 418 Table 15 5 5 5 5 1 Format moeren Pos 15 10 e 7 4 2 o Address ___ ne ri Ro Gs 62 er es 1 0 40000400 ra Re Rv Ro 64 Gs Ge Gr es 1 0 40000404 pg ESSE ESSE Re n Ro Gs ae 8o 1 exapoorro Number vB ss 22 21 20 15 1 v e s 4 818 Notes 1 0 40000400 is Palette start address 2 VD18 VD10 and VD2 have the same output value I 3 DATA 31 16 is invalid Palette Read Write When the user performs Read Write operation on the palette VSTATUS of LCDCONS5 register must be checked for Read Write operation is prohibited during the ACTIVE status of VSTATUS Temporary Palette Configuration The 53 2410 01 allows the user to fill a frame with one color without complex modification to fill the one color to the frame buffer or palette The one colored frame can
312. le can be used for suitable selections Eight red levels can be selected among 16 possible red levels 8 green levels among 16 green levels and 4 blue levels among 16 blue levels In case of 4096 color mode there is no selection as in the 256 color mode Gray Mode Operation The 53 2410 01 LCD controller supports two gray modes 2 bit per pixel gray 4 level gray scale and 4 bit per pixel gray 16 level gray scale The 2 bit per pixel gray mode uses a lookup table BLUELUT which allows selection on 4 gray levels among 16 possible gray levels The 2 bit per pixel gray lookup table uses the BULEVAL 15 0 in Blue Lookup Table BLUELUT register as same as blue lookup table in color mode The gray level 0 will be denoted by BLUEVAL 3 0 value If BLUEVAL 3 0 is 9 level 0 will be represented by gray level 9 among 16 gray levels If BLUEVAL 3 0 is 15 level O will be represented by gray level 15 among 16 gray levels and so on Following the same method as above level 1 will also be denoted by BLUEVAL 7 4 the level 2 by 1 8 and the level by BLUEVAL 15 12 These four groups among BLUEVAL 15 0 will represent level 0 level 1 level 2 and level 3 In 16 gray levels there is no selection as in the 16 gray levels This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS
313. le registers are read For example when the user reads the registers from BCDYEAR to BCDMIN the result is assumed to be 2059 Year 12 Month 31 Date 23 Hour and 59 Minute When the user read the BCDSEC register and the value ranges from 1 to 59 Second there is no problem but if the value is 0 sec the year month date hour and minute may be changed to 2060 Year 1 Month 1 Date 0 Hour and 0 Minute because of the one second deviation that was mentioned In this case the user should re read from BCDYEAR to BCDSEC if BCDSEC is zero BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery which supplies the power through the RTCVDD pin into the RTC block even if the system power is off When the system is off the interfaces of the CPU and RTC logic should be blocked and the backup battery only drives the oscillation circuit and the BCD counters to minimize power dissipation 17 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR REAL TIME CLOCK ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power off mode or normal operation mode In normal operation mode the alarm interrupt ALMINT is activated In the power off mode the power management wakeup PMWKUP signal is activated as well as the ALMINT The RTC alarm register RTCALM determines the alarm enable disable status and the condition of the alarm time setting TICK TIME INTERRUPT The RTC tick time is used for
314. le service mode or Whole service mode 8 2 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR DMA EXTERNAL DMA DREQ DACK PROTOCOL There are three types of external DMA request acknowledge protocols Single service Demand Single service Handshake and Whole service Handshake mode Each type defines how the signals like DMA request and acknowledge are related to these protocols Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation which can make one DMA operation Figure 8 1 shows the basic Timing in the DMA operation of the S3C2410X01 setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes If the completion of XnXDREQ meets its setup time it is synchronized twice and then XnXDACK is asserted After assertion of XnXDACK DMA requests the bus and if it gets the bus it performs its operations XnXDACK is deasserted when DMA operation is completed ser 9 3ns Setup XnXDREQ Ri gt 4 9 3ns Setup 2XSCLK 3 6 6ns Delay XnXDACK H E Read X Write Y 5 C sxseuk 6 8ns Delay Figure 8 1 Basic DMA Timing Diagram ELECTRONICS 8 3 DMA 3C2410X01 RISC MICROPROCESSOR Demand Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK Figure 8 2 shows the differences between the two
315. length four is performed ELECTRONICS 8 9 DMA 3C2410X01 RISC MICROPROCESSOR 27 SERVMODE Select the service mode between Single service mode and Whole service mode 0 Single service mode is selected in which after each atomic transfer single or burst of length four DMA stops and waits for another DMA request 1 Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0 In this mode additional request are not required Note that even in the Whole service mode DMA releases the bus after each atomic transfer and then tries to re get the bus to prevent HWSRCSEL starving of other bus masters 26 24 Select DMA request source for each DMA DCONO 000 nXDREQO 001 UARTO 010 SDI 011 100 USB device DCON1 000 nXDREQ1 001 UART1 010 12SSDI 011 SPI 100 USB device EP2 DCON2 000 28SDO 001 I2SSDI 010 SDI 011 100 USB device EP3 DCON3 000 UART2 001 801 010 SPI 011 100 USB device EP4 These bits control the 4 1 MUX to select the DMA request source of each DMA These bits have meanings only if H W request mode is RELOAD 22 the reload on off option 0 auto reload is performed when a current value of transfer count becomes 0 i e all the required transfers are performed DMA channel DMA REQ is turned off when a current value of 21 20 Data size to be transferred 00 Byte 01 Half word 10 Word 1
316. lette for various selection of color mapping providing flexible operation for users This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 15 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR MEMORY DATA FORMAT TFT This section includes some examples of each display mode 24BPP Display BSWP 0 HWSWP 0 BPP24BL 0 000H Dummy Bit 004H Dummy Bit 008H Dummy Bit P3 BSWP 0 HWSWP 0 BPP24BL 1 mus 000H P1 Dummy Bit _ 14 LCD Panel 15 16 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 16BPP Display BSWP 0 HWSWP 0 LCD Panel This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 17 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR 8BPP Display BSWP 0 HWSWP 0 LCD Panel 15 18 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 4BPP Display BSWP 0 HWSWP 0 ee _ P P P P Ps Pe P om mo om pe eo ms me pio Pao pei pee pes BSWP 1 HWSWP 0 108128 0127 24 0123
317. ly Writes in user mode cause permission fault 11 X X Read write Read write All access types permitted in both modes 1 mo 3 20 ELECTRONICS ARM920T PROCESSOR MMU FAULT CHECKING SEQUENCE The sequence by which the MMU checks for access faults is different for sections and pages The sequence for both types of access is shown below The conditions that generate each of the faults are described on the following pages Modified virtual address Check address alignment Misaligned Section fault EN Page Get page Invalid translation table entry fault Section Page access 00 access 00 domain Reserved 10 Check domain status Reserved 10 domain fault fault Client 01 Client 01 Manager 11 en Violation Check access Check access Violation Pen P permissions permissions p fault fault Physical address Figure 3 11 Sequence for Checking Faults ELECTRONICS 3 21 MMU ARM920T PROCESSOR ALIGNMENT FAULT If alignment fault is enabled A Bit in CP15 register 1 set the MMU will generate an alignment fault on any data word access the address of which is not word aligned or on any halfword access the address of which is not halfword aligned irrespective of whether the MMU is enabled or not An alignment fault will not be generated on any instruction fetch nor on any byte access NOTES If the access generates an alignment fault the access sequence will abort without reference to f
318. mal interval timer mode with interrupt request Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 time out This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 18 1 WATCHDOG TIMER 3C2410X01 RISC MICROPROCESSOR WATCHDOG TIMER OPERATION Figure 18 1 shows the functional block diagram of the watchdog timer The watchdog timer uses only PCLK as its source clock The PCLK frequency is prescaled to generate the corresponding watchdog timer clock and the resulting frequency is divided again Interrupt POLK 8 bit Prescaler AONT Reset Signal Generator RESET Down Counter WTCON 15 8 WTCON 4 3 WTCON 2 WTCON 0 Figure 18 1 Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control WTCON register Valid prescaler values range from 0 to 28 1 The frequency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t watchdog 1 PCLK Prescaler value 1 Division factor WTDAT amp WTCNT Once the watchdog timer is enabled the value of watchdog timer data WTDAT register cannot be automatically reloaded into the timer coun
319. mall section of operating system code the data abort handler It does not affect user code With the base restored data abort model when a data abort exception occurs during the execution of a memory access instruction the base register is always restored by the processor hardware to the value the register contained before the instruction was executed This removes the need for the data abort handler to unwind any base register update which may have been specified by the aborted instruction 2 2 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception That is ARM instructions with opcode 27 25 06011 and opcode 4 1 are undefined on all ARM processors including the ARM9TDMI and ARM7TDMI ARM architecture v4 and v4T also introduced a number of instruction set extension spaces to the ARM instruction set These are arithmetic instruction extension space control instruction extension space coprocessor instruction extension space load store instruction extension space Instructions in these spaces are undefined they cause an undefined instruction exception The ARM9TDMI fully implements all the instruction set extension spaces defined in ARM architecture v4T as undefined instructions allowing emulation of future instruction set additions The system control coproces
320. manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 24 13 3C2410X RISC MICROPROCESSOR ELECTRICAL DATA lt a ra lt Figure 24 14 SDRAM MRS Timing ELECTRONICS 24 14 ELECTRICAL DATA 53 2410 RISC MICROPROCESSOR 05 25 2002 CD a NEUE DES EE e s m Y D _ A Q Ov 9 A A Ov o kp a lt 4 lt amp CD 0 lt 4 x G 5 2 amp CD CD lt lt r DATA tSDH 2 Trcd 2 Tcl 2 Figure 24 15 SDRAM Single READ Timing l Trp manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number This document is a preliminary user 24 15 ELECTRONICS ELECTRICAL DATA 3C2410X RISC MICROPROCESSOR ADDR BA A10 AP gt 41505 gt Figure 24 16 SDRAM Single READ Timing Il Trp 2 Trcdz2 Tcl 3 24 16 ELECTRONICS 53 2410 RISC MICROPROCESSOR ELECTRICAL DATA 05 25 2002 SAD SAD gt ADDR BA A10 AP Before executing auto self refresh command all banks must be in idle state Figure 24 17 SDRAM Auto Refresh Timing Trp 2 Trc 4 This document
321. modes At the end of one transfer Single Burst transfer DMA checks the state of double synched XnXDREQ Demand mode f XnXDREQ remains asserted the next transfer starts immediately Otherwise it waits for XNXDREQ to be asserted Handshake mode f XnXDREQ is deasserted DMA deasserts XnXDACK in 2cycles Otherwise it waits until XNXDREQ is deasserted Caution XnXDREQ has to be asserted low only after the deassertion high of XnXDACK Demand Mode XnXDREQ _ 2cyces 1st Transfer 2nd Transfer XnXDACK i mr lm a synch 3 Handshake Mode BUS Aequisiton Transfer TV XnXDACK le i Double 2cycles gt 2cycles y synch i y Figure 8 2 Demand Handshake Mode Comparison 8 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR DMA Transfer Size There are two different transfer sizes unit and Burst 4 DMA holds the bus firmly during the transfer of the chunk of data Thus other bus masters cannot get the bus Burst 4 Transfer Size Four sequential Reads and Writes respectively are performed in the Burst 4 Transfer Note Unit Transfer size One read and one write are performed SUNN XnXDREQ wu XnXDACK H Double synch
322. mp Power Management LOCKTIME 0x4C000000 lt R W PLL Lock Time Counter CLKDIVN 0x4C00001 4 Clock divider Control LCD Controller LCDCON1 LCDCON2 LCDCONS LCDCON4 LCDCONS LCDSADDR1 LCDSADDR2 LCDSADDR3 REDLUT GREENLUT BLUELUT DITHMODE TPAL LCDINTPND LCDSRCPND LCDINTMSK LPCSEL Tw Tm 0X4D000014 STN TFT Frame Buffer Start Address1 0X4D000018 STN TFT Frame Buffer Start Address2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued Register Address Address Read Function Name B Endian L Endian Write NFCONF 0x4E000000 R W Flash Flash Configuration NFCMD 0 4 000004 Flash Address PD Address NAND Flash Data 7 NANO Fash Operation ELECTRONICS 1 29 PRODUCT OVERVIEW 3C2410X01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued Register Address Address Read Function Name Endian L Endian Write PART RW UARTOLineControl UART 0 FIFO Control UART 0 Modem UART 0 Modem Control UTRSTATO 0x50000010 UERSTATO 0x50000014 UFSTATO 0x50000018 UART 0 FIFO Status 0 UART 0 FIFO Status o Status UART 0 Modem Status 0 Modem UART 0 Modem Status W UART o Transmission ad UART o Receive Bufer osmo w aw over
323. multiplier operand specified by Rs Its possible values are as follows If bits 32 8 of the multiplier operand are all zero or all one If bits 32 16 of the multiplier operand are all zero or all one If bits 32 24 of the multiplier operand are all zero or all one N In all other cases ASSEMBLER SYNTAX MUL cond S Rd Rm Rs MLA cond S Rd Rm Rs Rn cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 EXAMPLES MUL R1 R2 R3 Ri R2 R3 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 R3 R4 Setting condition codes 3 24 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results Signed and unsigned multiplication each with optional accumulate give rise to four variations 31 28 27 23 22 21 20 19 16 15 12 11 _ ooo os mm as D 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate
324. n 28 27 2423 212019 16 15 12 11 7 5 4 3 mer om I 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The field is used as for all coprocessor instructions to specify which coprocessor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 56 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of t
325. n The software interrupt instruction is used to enter Supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR svc If the SWI vector address is suitably protected by external memory management hardware from modification by the user a fully protected operating system may be constructed RETURN FROM THE SUPERVISOR PC is saved in R14 svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14 svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and N are defined as sequential S cycle and non sequential N cycle ELECTRONICS 3 49 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR ASSEMBLER SYNTAX SWI cond e
326. n be used to determine the virtual address associated with a prefetch abort Fault address register Writing to this register causes the MMU to perform TLB maintenance operations either invalidating all the unpreserved entries in the TLB or invalidating a specific entry TLB lock down 10 I amp D 31 20 amp 0 Allows specific page table entries to be locked into the register TLB and the TLB victim index to be read written opcode 2 0x0 accesses the D TLB lock down register opcode 2 0x1 accesses the TLB lock down register Locking entries in the TLB guarantees that accesses to the locked page or section can proceed without incurring the time penalty of a TLB miss This allows the execution latency for time critical pieces of code such as interrupt handlers to be minimized TLB operations register ELECTRONICS 3 3 MMU ARM920T PROCESSOR All the CP15 MMU registers except register 8 contain state and can be read using MRC instructions and written using MCR instructions Registers 5 and 6 are also written by the MMU during a data abort Writing to Register 8 causes the MMU to perform a TLB operation to manipulate TLB entries This register cannot be read The instruction TLB I TLB and data TLB D TLB both have a copy of register 10 the opcode 2 field in the CP15 instruction is used to determine which one is accessed The system control coprocessor CP15 is described in Programmer s Model on page 2 1 Details of regi
327. n encoding is shown in Figure 3 3 below 31 2827 252423 0 Ce 24 Link bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instructions contain a signed 2 s complement 24 bit offset This is shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the prefetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction Branches beyond 32Mbytes must use an offset or absolute destination which has been previously loaded into a register In this case the PC should be manually saved in R14 if a Branch with Link type operation is required THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and R14 1 0 are always cleared To return from a routine called by Branch with Link use MOV PC R14 if the link register is still valid LDM Rn PC if the link register has been saved onto a stack pointed to by Rn INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S 1N incremental cycles where S and N are defined as sequential S cycle and internal I cycle ELECT
328. n it gets to the top of the receive FIFO without reading out data in it overrun error ELECTRONICS 11 5 UART 53 2410 01 RISC MICROPROCESSOR UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register The error status FIFO indicates which data among FIFO registers is received with an error The error interrupt will be issued only when the data which has an error is ready to read out To clear the error status FIFO the URXHn with an error and UERSTATn must be read out For example It is assumed that the UART Rx FIFO receives A B C D and E characters sequentially and the frame error occurs while receiving B and the parity error occurs while receiving D The actual UART receive error will not generate any error interrupt because the character which was received with an error has not been read yet The error interrupt will occur when the character is read out Figure 11 3 shows the UART receiving the five characters including the two errors 0 When no character is read out After A is read out The frame error in B interrupt occurs The B has to be read out 1 2 After C is read out The parity error in D interrupt occurs The D has to be read out Error Status FIFO Break Error Parity Error Frame Error Figure 11 3 UART Receiving 5 Characters with 2 Errors 11 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART
329. n off bit is changed the TOUTn logic value will also be changed whether the timer runs Therefore it is desirable that the inverter on off bit is configured with the manual update bit ELECTRONICS 10 5 PWM TIMER S3C2410X01 RISC MICROPROCESSOR TIMER OPERATION Figure 10 4 Example of a Timer Operation Figure10 4 shows the result of the following procedure 1 10 11 Enable the auto reload function Set the TCNTBn to 160 50 110 and the TCMPBn to 110 Set the manual update bit and configure the inverter bit on off The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn respectively And then set the TCNTBn and the TCMPBn to 80 40440 and 40 respectively to determine the next reload value Set the start bit provided that manual update is 0 and the inverter is off and auto reload is on The timer starts counting down after latency time within the timer resolution When the TCNTn has the same value as that of the TCMPn the logic level of the TOUTn is changed from low to high When the TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary register At the next timer tick the TCNTn is reloaded with the temporary register value TCNTBn In Interrupt Service Routine ISR the TCNTBn and the TCMPBn are set to 80 204 60 and 60 respectively for the next duration When the TCNTn has the same value as the TCMPn the logic level of TOUTn is changed f
330. n page 4 1 3 2 ELECTRONICS ARM920T PROCESSOR MMU MMU PROGRAM ACCESSIBLE REGISTERS Table 3 1 shows system control coprocessor CP15 registers which are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU Table 3 1 CP15 SE Functions Register description ee bits to enable the MMU M bit enable data address alignment checks A bit and to control the access protection scheme S bit and R bit Translation table 31 14 Holds the physical address of the base of the translation base register table maintained in main memory This base address must be a 16KB boundary and is common to both TLBs Register _ Control register Domain access Comprises sixteen 2 bit fields control register Each field defines the access control attributes for one of 16 domains 015 00 Fault status register 5 18 D Indicates the cause of a data and prefetch abort and the domain number of the aborted access when an abort occurs Bits 7 4 specify which of the 16 domains 015 00 was being accessed when a fault occurred Bits 3 0 indicate the type of access being attempted The value of all other bits is unpredictable The encoding of these bits is shown in Table 3 4 on page 3 18 Holds the virtual address associated with the access that caused the data abort See Table 3 4 on page 3 18 for details of the address stored for each type of fault ARM9TDMI Register 14 ca
331. n state 1 Stylus up state AUTO_PST 14 Automatically sequencing conversion of X position and Y position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position mag YPDATA Y position conversion data value Data value 0 XY PST 13 12 Manual measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode ELECTRONICS 16 11 A D CONVERTER AND TOUCH SCREEN 3C2410X01 RISC MICROPROCESSOR NOTES 16 12 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR REAL TIME CLOCK 05 22 2002 REAL TIME CLOCK Preliminary OVERVIEW The Real Time Clock RTC unit can be operated by the backup battery while the system power is off The RTC can transmit 8 bit data to CPU as Binary Coded Decimal BCD values using the STRB LDRB ARM operation The data include the time by second minute hour date day month and year The RTC unit works with an external 32 768 KHz crystal and also can perform the alarm function FEATURES BCD number second minute hour date day month and year Leap year generator Alarm function alarm interrupt or wake up from power off mode Year 2000 problem is removed Independent power pin RTCVDD Supports millisecond tick time interrupt for RTOS kernel time tick Round reset function This document is a preliminary user s manual So our company will present its revision as of the date
332. nal is asserted to cause the LCD s line pointer to start over at the top of the display The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2 3 registers The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 The rate of signal depends on the CLKVAL field in the LCDCON1 register Table 15 3 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 0 VCLK Hz HCLK CLKVAL 1 x2 The frame rate is VSYNC signal frequency The frame rate is related with the field of VSYNC VBPD VFPD LINEVAL HSYNC HBPD HFPD HOZVAL and CLKVAL in LCDCON1 and LCDCON2 3 4 registers Most LCD drivers need their own adequate frame rate The frame rate is calculated as follows Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 VFPD 1 x HSPW 1 HBPD 1 HFPD 1 HOZVAL 1 x 2x CLKVAL 1 HCLK Table 15 3 Relation between VCLK and CLKVAL TFT HCLK 60MHz CLKVAL 60MHz X VCLK 60 MHz 4 15 0 MHz 60 MHz 6 10 0 MHz 1023 60 MHz 2048 30 0 kHz VIDEO OPERATION The TFT LCD controller within the S3C2410X01 supports 1 2 4 or 8 bpp bit per pixel palettized color displays and 16 or 24 bpp non palettized true color displays 256 Color Palette The 53 2410 01 can support the 256 color pa
333. nd paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 fora prefetch abort or SUBS PC R14 abt 8 fora data abort This restores both the PC and the CPSR and retries the aborted instruction 2 12 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL Software Interrupt The software interrupt instruction SWI is used for entering Supervisor mode usually to request a particular supervisor function A SWI handler should return by executing the following irrespective of the state ARM or Thumb MOV PC R14 svc This restores the PC and CPSR and returns to the instruction following the SWI NOTES nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM920T CPU core Undefined Instruction When ARM920T comes across an instruction which it cannot handle it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set
334. ndition should have the address field The address field can be transmitted by the master when the IIC bus is operating in Master mode Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are always sent first Write Mode Format with 7 bit Addresses Slave Address 7bits DATA 1 Byte gt Write Data Transferred Data Acknowledge Write Mode Format with 10 bit Addresses Slave Address Slave Address 1st 7 bits 2nd Byte Write Data Transferred Data Acknowledge Read Mode Format with 7 bit Addresses Slave Address 7 bits DATA xx Read Data Transferred Data Acknowledge Read Mode Format with 10 bit Addresses Slave Address Slave Address Slave Address 2nd Byte 1517 Bits DATA Read Read Data Transferred Data Acknowledge NOTES 1 6 Start rS Repeat Start P Stop A Acknowledge 2 From Master to Slave From Slave to Master Figure 20 3 IIC Bus Interface Data Format 20 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE 1 1 1 1 Acknowledgement Acknowledgement Signal from Receiver Signal from Receiven 1 1 1 1 1 1 ie ae ACK 1 Byte Complete Interrupt Clock Line Held Low While within Receiver Interrupts are Serviced Figure 20 4 Data Transfer on the IIC Bus ACK SIGNAL TRANSMISSION To complete a one byte transfer operation
335. ng a D TLB miss occurs then entry 0 will be loaded MCR to CP15 register 10 opcode 2 0 0 Base Value 1 Current Victim 1 P 0 REGISTERS 11 12 amp 14 RESERVED Accessing reading or writing any of these registers will cause unpredictable behavior REGISTER 13 PROCESS ID Register 13 is the process identifier register The process identifier register is 0 0 on reset Reading from CP15 register 13 returns the value of the process identifier Writing CP15 register 13 updates the process identifier to the value in bits 31 25 Bits 24 0 should be zero Register 13 bit assignments are shown in Figure 2 7 31 25 24 23 22 21 20 19 18 17 16 15 14 131211109 8 7 6 5 4 3 2 1 SBZ Figure 2 7 Register 13 Register 13 can be accessed using the following instructions MRC p15 0 Rd c13 cO 0 read process identifier MCR p15 0 Rd c13 0 0 write process identifier 2 22 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Using the process Identifier ProcID Addresses issued by the ARM9TDMI core in the range 0 to 32MB are translated by CP15 register 13 the ProcID register Address A becomes ProcID x 32MB It is this translated address that is seen by both the Caches and MMU Addresses above 32MB undergo no translation This is shown in Figure 2 8 on page 2 23 The ProclD is a seven bit field enabling 64 x 32MB processes to be mapped NOTES If ProcID is zero as it is on reset then there is a flat m
336. nored In this case the S3C2410X01 will control nRTS automatically Note UART 2 does not support AFC function because the S3C2410X01 has no nRTS2 and nCTS2 11 14 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART UART TX RX STATUS REGISTER There are three UART Tx Rx status registers including UTRSTATO UTRSTAT1 and UTRSTAT2 in the UART block UTRSTATO 0x50000010 R UART channel 0 Tx Rx status register UTRSTAT1 0x50004010 oR UART channel 1 Tx Rx status register E UTRSTAT2 0x50008010 oR UART channel 2 Tx Rx status register Transmitter empty Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty 0 Not empty 1 Transmitter transmit buffer amp shifter register empty Transmit buffer empty Set to 1 automatically when transmit buffer register is empty 0 The buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested when Tx FIFO Trigger Level is set to 00 Empty If the UART uses the FIFO users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit Receive buffer data ready Set to 1 automatically whenever receive buffer register contains valid data received over the RXDn port 0 Empty 1 The buffer register has a received data In Non FIFO mode Interrupt or DMA is requested If the UART uses the FIFO users should
337. nterrupt 13 Read wait request interrupt m ed 0 disable 1 interrupt enable pw IOlntDet Interrupt SD host receives SDIO Interrupt from the card for SDIO Bl EE disable 1 interrupt enable FFfail Interrupt FIFO fail error interrupt bh ap 0 disable 1 interrupt enable CrcSta Interrupt CRC status errors interrupt i IL 0 disable 1 interrupt enable DatCrc Interrupt Data CRC fail interrupt i ANE 0 disable 1 interrupt enable i DatTout Interrupt Data timeout interrupt 0 disable 1 interrupt enable NEN DatFin Interrupt Data counter zero interrupt LR 0 disable 1 interrupt enable BusyFin Interrupt Busy checks complete interrupt ae 0 disable 1 interrupt enable SBitErr Interrupt Start bit error interrupt eae 0 disable 1 interrupt enable BUE TFHalf Interrupt Tx FIFO half interrupt Bi EA 0 disable 1 interrupt enable m TFEmpty Interrupt Tx FIFO empty interrupt ede 0 disable 1 interrupt enable NN RFLast Interrupt Rx FIFO has last data interrupt Ji 0 disable 1 interrupt enable RFFull Interrupt Rx FIFO full interrupt ewe 0 disable 1 interrupt enable KA Rx FIFO half interrupt 0 disable 1 interrupt enable RFHalf Interrupt Enable 19 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE 05 22 2002 IIC BUS INTERFACE Preliminary OVERVIEW The 53 2410 01 RISC microprocessor can s
338. ntrol register bits 8 and 9 If the access is not allowed a section permission fault is generated Large page small page If the level one descriptor defines a page mapped access and the level two descriptor is for a large or small page four access permission fields ap3 ap0 are specified each corresponding to one quarter of the page Hence for small pages ap3 is selected by the top 1KB of the page and is selected by the bottom 1KB of the page For large pages ap3 is selected by the top 16KB of the page and is selected by the bottom 16KB of the page The selected AP bits are then interpreted in exactly the same way as for a section see Table 3 6 on page 3 20 the only difference being the fault generated is a page permission fault Tiny page If the level one descriptor defines a page mapped access and the level two descriptor is for a tiny page the AP bits of the level one descriptor define whether or not the access is allowed in the same way as for a section The fault generated is a page permission fault ELECTRONICS 3 23 MMU ARM920T PROCESSOR EXTERNAL ABORTS In addition to the MMU generated aborts the ARM920T can be externally aborted by the AMBA bus which may be used to flag an error on an external memory access However not all accesses can be aborted in this way and the Bus Interface Unit BIU ignores external aborts that can not be handled The following accesses may be aborted non cached reads unbuf
339. nused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero 2 8 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL Table 2 1 PSR Mode Bit Values Visible THUMB state registers Visible ARM state registers User R7 RO LR SP PC CPSR R7 RO LR fiq SP fiq PC CPSR SPSR fiq R7 RO LR irq SP irq PC CPSR SPSR irq Supervisor R7 RO LR svc SP svc PC CPSR SPSR Abort 7 LR_abt SP_abt PC CPSR SPSR abt Undefined R7 RO LR und SP und PC CPSR SPSR und System R7 RO LR SP PC CPSR R7 RO R14 fiq R8 fig PC CPSR SPSR fiq R12 RO R14 R13 PC CPSR SPSR irq R12 RO R14 svc R13 svc PC CPSR SPSR svc R12 RO R14 abt R13 abt PC CPSR SPSR abt R12 RO R14 und R13 und PC CPSR Reserved bits The remaining bits in the PSR s are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or Zero ELECTRONICS PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be handled the
340. o BCLK to perform the access The delay when switching from FCLK and BCLK is a minimum of one BCLK cycle and a maximum of one and a half BCLK cycles An example of the clock switching is shown in Figure 5 4 When switching from BCLK to FCLK the minimum delay is one FCLK cycle and the maximum delay is one and half FCLK cycles An example of the clock switching is shown in Figure 5 5 Figure 5 5 Switching from FCLK to BCLK in Asynchronous Mode ELECTRONICS 5 3 CLOCK MODES ARM920T PROCESSOR NOTES 5 4 ELECTRONICS
341. ock Diagram ELECTRONICS 7 9 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR IDLE_BIT 1 Interrupts EINT RTC alarm Ly NORMAL Set IDLE_BIT 0 amp STOP_BIT 0 SLOW_BIT 0 EINT RTC alarm PLL is turned on automatically SENS STOP 1 SLOW BIT 1 Figure 7 8 Power Management State Machine Table 7 2 Functional Block Clock State In Each Power Mode HELL ARM920T AHB Modules WDT APB Modules USB host UCLK Ew oq o NOTE 1 USB host and RTC are excluded 2 WDT is excluded 3 SEL selectable turned on X turned off 7 10 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT NORMAL Mode In normal mode all peripherals and the basic blocks including power management block the CPU core the bus controller the memory controller the interrupt controller DMA and the external master may operate fully But the clock to each peripheral except the basic blocks can be stopped selectively by software to reduce the power consumption IDLE Mode In IDLE mode the clock to the CPU core is stopped except the bus controller the memory controller the interrupt controller and the power management block To exit the IDLE mode EINT 23 0 or RTC alarm interrupt or the other interrupts should be activated EINT is not available until GPIO block is turned on SLOW Mode Non PLL Mode Power consumption can be reduced in the SLOW mode b
342. oint3 DMA FIFO counter register Endpoint3 DMA transfer counter low byte register Endpoint3 DMA transfer counter middle byte register 0x228 L 0x22B B Ox22C L 0x22F B 0x240 L 0x243 B 0x244 L 0x247 B 0x248 L 0x24B B Ox24C L 0x24F B 0x250 L 0x253 B EP3_DMA_TTC_H EP4_DMA_CON EP4_DMA_UNIT EP4_DMA_FIFO EP4_DMA_TTC_L 0x254 L 0x247 B 0x258 L 0x25B B Ox25C L 0x25F B Endpoint3 DMA transfer counter high byte register Endpoint4 DMA control register Endpoint4 DMA unit counter register Endpoint4 DMA FIFO counter register 0x260 L 0x263 B Endpoint4 DMA transfer counter low byte register TTC M Endpoint4 DMA transfer counter middle byte register EP4 DMA TTC H Endpoint4 DMA transfer counter high byte register COMMON INDEXED REGISTERS REG 0x18C L 0x18F B IN INDEXED REGISTERS CSR1 REG EPO CSR Endpoint MAX packet register EP In control status register 1 EPO control status 0x184 L 0x187 B register IN CSR2 REG OUT INDEXED REGISTERS OUT CSR1 REG OUT CSR2 REG OUT FIFO CNT1 REG OUT FIFO CNT2 REG EP In control status register 2 0x188 L 0x18B B EP out control status register 1 0x190 L 0x193 B EP out control status register 2 0x194 L 0x197 B 0x198 L Ox19B B 0x19C L Ox19F B EP out write count register 1 EP out write count register 2 13 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE FUNCTION ADDRESS REGISTER
343. om numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles TST Rb Rb LSR 1 MOVS Rc Ra RRX ADC Rb Rb Rb EOR Rc Rc Ra LSL4H2 EOR Ra Ro Ro LSRH20 Enter with seed in Ra 32 bits Rb 1 bit in Rb Isb uses Rc Top bit into carry 33 bit rotate right Carry into Isb of Rb involved similarly involved new seed in Ra Rb as before MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2 n 1 2 4 8 16 32 MOV Ra Rb LSL n Multiplication by 2 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 2 n 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS ARM INSTRUCTION SET Multiplication by 6 ADD MOV Ra Ra Ra LSL 1 Ra Ra LSL 1 Multiply by 10 and add in extra number ADD ADD General recursive method for Rb Ra C C a constant Ra Ra Ra LSL 2 Ra Rc Ra LSL4H 1 If C even say 2 n D D D 1 D lt gt 1 MOV 2 If C MOD 4 1 say C 24n D
344. on reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending on the state of the ISYNC input signal When ISYNC is LOW nFIQ and nIRQ are considered asynchronous and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14_fig 4 FIQ may be disabled by setting the CPSR s F flag but note that this is not possible from User mode If the F flag is clear ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction ELECTRONICS 2 11 PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR IRQ The IRQ Interrupt Request exception is a normal interrupt caused by a LOW level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting the bit in the CPSR though this can only be done from a privileged non User mode Irrespective of whether the exception was entered from ARM or Thumb state an IRQ
345. on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 17 1 REAL TIME CLOCK S3C2410X01 RISC MICROPROCESSOR REAL TIME CLOCK OPERATION TIME TICK RTCRST Reset Leap Year Generator Y f mn are on mo 4 gt Alarm Generator Regi ster PMWKUP ALMI NT Figure 17 1 Real Time Clock Block Diagram LEAP YEAR GENERATOR The leap year generator can determine the last date of each month out of 28 29 30 or 31 based on data from BCDDATE BCDMON and BCDYEAR This block considers leap year in deciding on the last date An 8 bit counter can only represent 2 BCD digits so it cannot decide whether 00 year the year with its last two digits zeros is a leap year or not For example it cannot discriminate between 1900 and 2000 To solve this problem the RTC block in S3C2410X01 has hard wired logic to support the leap year in 2000 Note 1900 is not leap year while 2000 is leap year Therefore two digits of 00 in S3C2410X01 denote 2000 not 1900 READ WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block To display the second minute hour date month and year the CPU should read the data in BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON and BCDYEAR registers respectively in the RTC block However a one second deviation may exist because multip
346. one of the 16 possible domains held in the domain access control registers that contain the primary access controls Bits 11 9 are always written as 0 Bits 31 12 form the base for referencing the level two descriptor The fine page table index for the entry is derived from the modified virtual address If a fine page table descriptor is returned from the level one fetch a level two fetch is initiated ELECTRONICS 3 9 MMU ARM920T PROCESSOR TRANSLATING SECTION REFERENCES Figure 3 5 illustrates the complete section translation sequence Note that access permissions contained in the level one descriptor must be checked before the physical address is generated 31 20 19 0 Translation table base 31 14 13 0 Translation base uuu 12 18 Translation base Table index Section level one descriptor 20 19 1211109 8 ee Jose 1010101 Physical address 20 19 Figure 3 5 Section Translation 3 10 ELECTRONICS ARM920T PROCESSOR MMU LEVEL TWO DESCRIPTOR If the level one fetch returns either a coarse page table descriptor or a fine page table descriptor this provides the base address of the page table to be used The page table is then accessed and a level two descriptor is returned This defines either a tiny a small or a large page descriptor page descriptor provides the base address of a 1KB block of memory asmallpage descriptor provides to the base address of a 4KB block of memory alarg
347. ons 1 Sets OUT PKT RDY bit 2 Sets SENT STALL bit For ISO IN endpoints Set by the USB under the following conditions 1 UNDER RUN bit is set 2 IN PKT RDY bit is cleared 3 FIFO is flushed Note conditions 1 and 2 are mutually exclusive For ISO OUT endpoints Set by the USB under the following conditions 1 OUT PKT RDY bit is set 2 OVER RUN bit is set Note Conditions 1 and 2 are mutually exclusive EPO Interrupt Correspond to endpoint 0 interrupt Set by the USB under the following conditions 1 OUT_PKT_RDY bit is set 2 IN_PKT_RDY bit is cleared 3 SENT_STALL bit is set 4 SETUP_END bit is set 5 DATA_END bit is cleared it indicates the end of control transfer ELECTRONICS 13 7 USB DEVICE 53 2410 01 RISC MICROPROCESSOR USB_INT_REG 0x52000158 L 0x5200015B B USB_INT_REG MCU RESET 2 R Interrupt CLEAR RESUME 1 R SET Interrupt CLEAR SUSPEND 0 R SET Interrupt CLEAR R W USB interrupt pending clear register 0x00 byte Description Initial State Set by the USB when it receives reset signaling Set by the USB when it receives resume signaling while in Suspend mode If the resume occurs due to a USB reset then the MCU is first interrupted with a RESUME interrupt Once the clocks resume and the SEO condition persists for 3ms USB RESET interrupt will be asserted Set by the USB when it receives suspend signalizing This bit is set whenever there is no activity for 3ms on the bu
348. ort a 12 bit per pixel 4096 color display mode The color display mode can generate 4096 levels of color using the dithering algorithm and FRC The 12 bit per pixel are encoded into 4 bits for red 4 bits for green and 4 bits for blue The 4096 color display mode does not use lookup tables 15 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 DITHERING AND FRAME RATE CONTROL For STN LCD displays except monochrome video data must be processed by a dithering algorithm The DITHFRC block has two functions such as Time based Dithering Algorithm for reducing flicker and Frame Rate Control FRC for displaying gray and color level on the STN panel The main principle of gray and color level display on the STN panel based on FRC is described For example to display the third gray 3 16 level from a total of 16 levels the 3 times pixel should be on and 13 times pixel off In other words 3 frames should be selected among the 16 frames of which 3 frames should have a pixel on on a specific pixel while the remaining 13 frames should have a pixel off on a specific pixel These 16 frames should be displayed periodically This is basic principle on how to display the gray level on the screen so called gray level display by FRC The actual example is shown in Table 15 2 To represent the 14 gray level in the table we should have a 6 7 duty cycle which mean that there are 6 times pixel on and one time pixel off The other cases
349. ow as the first bit of address generating master will get the mastership while High as the first bit of address generating master should withdraw the mastership If both masters generate Low as the first bit of address there should be an arbitration for the second address bit again This arbitration will continue to the end of last address bit ABORT CONDITIONS If a slave receiver cannot acknowledge the confirmation of the slave address it should hold the level of the SDA line High In this case the master should generate a Stop condition and to abort the transfer If a master receiver is involved in the aborted transfer it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave The slave transmitter should then release the SDA to allow a master to generate a Stop condition CONFIGURING IIC BUS To control the frequency of the serial clock SCL the 4 bit prescaler value can be programmed in the IICCON register The IIC bus interface address is stored in the IIC bus address IICADD register By default the IIC bus interface address has an unknown value 20 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR IIC BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx Rx operations 1 Write own slave address on IICADD register if needed 2 Set IICCON register a Enable interrupt b Define
350. p ELECTRONICS 16 7 A D CONVERTER AND TOUCH SCREEN 3C2410X01 RISC MICROPROCESSOR ADC TOUCH SCREEN CONTROL ADCTSC REGISTER ADCTSC 0x58000004 ADC touch screen control register 0x058 Reserved 8 This bit should be zero YM SEN 7 Select output value of YMON 0 YMON output is 0 YM Hi Z 1 YMON output is 1 YM GND YP_SEN Select output value of nYPON 0 nYPON output is 0 YP External voltage 1 nYPON output is 1 YP is connected with AIN 5 XM SEN Select output value of XMON 0 XMON output is 0 XM Hi Z 1 XMON output is 1 XM GND XP SEN Select output value of nXPON 0 nXPON output is 0 XP External voltage 1 nXPON output is 1 XP is connected with AIN 7 PULL UP Pull up switch enable 0 XP pull up enable 1 XP pull up disable AUTO_PST Automatically sequencing conversion of X position and Y position 0 Normal ADC conversion 1 Auto Sequential X Y Position Conversion Mode XY_PST Manual measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode 16 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR A D CONVERTER AND TOUCH SCREEN ADC START DELAY ADCDLY REGISTER ADCDLY 0x58000008 ADC start or interval delay register 0x00ff DELAY 0 1 Normal Conversion Mode Separate X Y Position Conversion OOff Mode and Auto Sequential X Y Position Conversion Mode
351. peration when the flag of data transfer finish SDIDSTA 4 is set 11 Clear the corresponding flag of SDIDSTA register by writing one to the flag bit 19 2 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR SD HOST CONTROLLER SDIO OPERATION There are two functions of the SDIO operation SDIO Interrupt receiving and Read Wait Request generation These two functions can operate when bit and RwaitEn bit of SDICON register is activated respectively Detailed steps and conditions for the two functions are described below SDIO Interrupt In SD 1bit mode the interrupt is received through all ranges from SDDAT1 pin In SD 4bit mode SDDAT1 pin is shared between to receive data and interrupts When interrupt detection ranges Interrupt Period are 1 Single Block the time between A and B A 2clocks after the completion of a data packet The completion of sending the end bit of the next with data command 2 Multi Block SDIDCON 21 0 the time between A and B restart interrupt detection range at C A 2clocks after the completion of a data packet B 2clocks after C 2clocks after the end bit of the abort command response 3 Multi Block SDIDCON 21 1 the time between A and B restart at A A 2clocks after the completion of a data packet B 2clocks after n case of last block interrupt period begins at last A but it does not end at B CMD53 case Read Wait Request Regardless of 1bit or 4bit mode Rea
352. perations are defined and the function to be performed is selected by the opcode 2 and CRm fields in the MCR instruction used to write CP15 register 8 Writing other opcode 2 or CRm values is unpredictable Reading from CP15 register 8 is unpredictable Table 2 17 on page 2 18 shows instructions that can be used to perform TLB operations using register 8 Table 2 17 TLB Operations Register 8 Invalidate TLB s SBZ MCR p15 0 Rd c8 c7 0 Invalidate D TLB single entry using MVA MVA format MCR p15 0 Rd c8 c6 1 NOTE These functions invalidate all the un preserved entries in the TLB Invalidate TLB single entry functions invalidate any TLB entry corresponding to the modified virtual address given in Rd regardless of its preserved state See Register 10 TLB lock down register on page 2 21 Figure 2 4 shows the modified virtual address format used for operations on single entry TLB lines using register 8 31 10 9 0 8 76543 2 1 Modified virtual address ________ __________ e 582 Figure 2 4 Register 8 MVA Format 2 18 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 9 CACHE LOCK DOWN REGISTER Register 9 is the cache lock down register The cache lock down register is 0 0 on reset The cache lock down register allows software to control which cache line in the ICache or DCache respectively is loaded for a and to prevent lines in the ICache or DCache from being evicted
353. placement SWAP INSTRUCTIONS Swap instruction SWP or SWPB behavior is dependent on whether the memory region is cacheable or non cacheable Swap instructions to cacheable regions of memory are useful for implementing semaphores or other synchronization primitives in multithreaded uniprocessor software systems Swap instructions to non cacheable memory regions are useful for synchronization between two bus masters in a multi master bus system This could be two processors or a processor and a DMA controller When a swap instruction accesses a cacheable region of memory WT or WB the DCache and write buffer behavior will be the same as having a load followed by a store according to the normal rules described The BLOK pin will not be asserted during the execution of the instruction It is guaranteed that no interrupt can occur between the load and store portions of the swap When a swap instruction accesses a non cacheable NCB or NCNB region of memory the write buffer is drained and a single word or byte will be read from the ASB The write portion of the swap will then be treated as non bufferable regardless of the value of Btt and the processor stalled until the write is completed on the ASB The BLOK pin will be asserted to indicate that the read and write should be treated as an atomic operation on the bus Like all other data accesses a swap to a non cacheable region which hits in the cache indicates a programming error 4 8
354. processor Data Operation Coprocessor Register Transfer Software Interrupt 3 1 ARM INSTRUCTION SET S3C2410X RISC MICROPROCESSOR NOTES Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken for instance a Multiply instruction with bit 6 changed to a 1 These instructions should not be used as their action may change in future ARM implementations INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set Mnemonic Instruction gt fem CDP Coprocessor specific EOR Rd Rn AND NOT 2 OR Op2 AND NOT Rn LDM Stack manipulation Pop MCR Move CPU register to coprocessor cRn rRn lt op gt cRm register MLA Multiply Accumulate Rd Rm x Rs Rn 3 2 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET Table 3 1 The ARM Instruction Set Continued MRC Move from coprocessor register to Rn cRn lt op gt cRm CPU register MSR Move register to PSR status flags Subtract Rd Rn Op2 ELECTRONICS 3 3 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils t
355. put port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read GPFUP Deseription 4 GPF 7 0 7 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 17 PORTS 3C2410X01 RISC MICROPROCESSOR PORT G CONTROL REGISTERS GPGCON GPGDAT and GPGUP If GPG 7 0 will be used for wakeup signals at Power OFF mode the ports will be set in Interrupt mode R GPGCON 0x56000060 AN Configure the pins of port G 0 0 GPGDAT 0x56000064 The data register for port G Undefined GPGUP 0x56000068 Pull up disable register for port G OxF800 ____ Bt __ Description GPG15 31 30 00 Input 01 Output 10 EINT23 11 2 nYPON GPG14 29 28 00 Input 01 Output 10 EINT22 11 YMON GPG13 27 26 00 Input 01 Output 10 EINT21 11 nXPON GPG12 25 24 00 Input 01 Output 10 EINT20 11 XMON GPGCON GPG11 23 22 00 Input 01 Output 10 EINT19 11 TCLK1 GPG10 21 20 00 Input 01 Output 10 EINT18 11 Reserved GPG9 19 18 00 Input 01 Output 10 EINT17 11 Reserved GPG8 17 16 00 Input 10 EINT16 GPG7 15 14 00 Input 10 EINT15 GPG6 13 12 00 Input 10 EINT14 GPG5 11 10 00 Input 10 EINT13 GPG4 00 Input 10 EINT12 GPG3 7 6 00 Input 10 EINT11 GPG2 5 4 00 Input 10 EINT10 GPG1 3 2 00
356. quested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Notrequested 1 Requested 14 14 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT OFFSET INTOFFSET REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register This bit can be cleared automatically by clearing SRCPND and INTPND Register Address R W Description Reset Value INTOFFSET Indicae the interrupt request source 0x00000000 INT Source The OFFSET value INT Source The OFFSET value INT RTC 30 INT TIMER4 14 INT UARTO 28 INT TIMER2 12 INT 27 INT TIMER1 11 moms es reno Note FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt ELECTRONICS 14 15 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR SUB SOURCE PENDING SUBSRCPND REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are Register Address R W Description Reset Value SUBSRCPND 0X4A000018 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 0 Not
357. r frame The VFRAME signal is asserted to bring the LCD s line pointer to the top of the display to start over The VM signal helps the LCD driver alternate the polarity of the row and column voltages which are used to turn the pixel on and off The toggling rate of VM signals depends on the MMODE bit of the LCDCON1 register and MVAL field of the LCDCON4 register If the MMODE bit is 0 the VM signal is configured to toggle on every frame If the MMODE bit is 1 the VM signal is configured to toggle on the every event of the elapse of the specified number of VLINE by the MVAL 7 0 value Figure 15 4 shows an example for MMODE 0 and for MMODE 1 with the value of MVAL 7 0 0x2 When MMODE 1 the VM is related to MVAL 7 0 as shown below VM Rate VLINE Rate 2 MVAL The VFRAME and VLINE pulse generation relies on the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2 3 register Each field is related to the LCD size and display mode In other words the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation HOZVAL Horizontal display size Number of the valid VD data line 1 In color mode Horizontal display size 3 Number of Horizontal Pixel In the 4 bit single scan display mode the Number of valid VD data line should be 4 In case of 4 bit dual scan display the Number of valid VD data lineshould also be 4 while in case of 8 bit single scan
358. r viewing all gray levels on user s own LCD Select the gray level quality through the following procedures 1 Get the latest dithering pattern register value from SAMSUNG 2 Display 16 gray bar in LCD 3 Change the frame rate into an optimal value 4 Change the VM alternating period to get the best quality 5 As viewing 16 gray bars select a good gray level which is displayed well on your LCD 6 Use only the good gray levels for quality LCD Refresh Bus Bandwidth Calculation Guide The 53 2410 01 LCD controller can support various LCD display sizes To select a suitable size for the flicker free LCD system application the user have to consider the LCD refresh bus bandwidth determined by the LCD display size bit per pixel bpp frame rate memory bus width memory type and so on LCD Data Rate Byte s bpp x Horizontal display size x Vertical display size x Frame rate 8 LCD DMA Burst Count Times s LCD Data Rate Byte s 16 Byte LCD DMA using 4words 16Byte burst Pdma means LCD DMA access period In other words the value of Pdma indicates the period of four beat burst 4 words burst for video data fetch So Pdma depends on memory type and memory setting Eventually LCD System Load is determined by LCD DMA Burst Count and Pdma LCD System Load LCD DMA Burst Count x Pdma Example 3 640 x 480 8bpp 60 frame sec 16 bit data bus width SDRAM Trp 2HCLK Tred 2HCLK CL 2HCLK and HCLK frequency is 6
359. re instructions Thumb ARM 1 Multiplication 2 n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 2 1 3 5 9 17 LSL Rt Rb n ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n RSBRa Rb Rb LSL n SUB Ra Rt Rb 4 Multiplication by 2 n 2 4 8 LSL Ra Rb n MOV Ra Rb LSL MVN Ra Ra RSBRa Ra 0 5 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by C 2 n41 2 n 1 2 or 2 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra n MOV Ra Ra LSL zin 4 40 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code Thumb code signed divide Signed divide of R1 by RO returns quotient in RO remainder in R1 Get abs value of RO into R3 ASR R2 RO 31 Get 0 or 1 in R2 depending on sign of RO EOR RO R2 EOR with 1 OxFFFFFFFF if negative SUB RO R2 and ADD 1 SUB 1 to get abs value SUB always sets flag so go amp report division by 0 if necessary BEQ divide b
360. red 10x Rising edge triggered 11x Both edge triggered EINT5 22 20 Set the signaling method of the EINT5 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EXTINTO Bit Description EINT4 18 16 Set the signaling method of the EINT4 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT3 14 12 Set the signaling method of the EINT3 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT2 10 8 Set the signaling method of the EINT2 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT1 6 4 Set the signaling method of the EINT1 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINTO 2 0 Set the signaling method of the EINTO 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered ELECTRONICS 9 23 PORTS 53 2410 01 RISC MICROPROCESSOR EINT15 30 28 Set the signaling method of the EINT15 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 7 EINT14 26 24 Set the signaling method of the EINT14 000 Low level 001 High level 01x Falling edge triggered 10x
361. register has the control and status bits for Endpoint 0 Since a control transaction is involved with both IN and OUT tokens there is only CSR register mapped to the IN CSR1 register share INT CSR and can access by writing index register 0 and read write INT CSR Register Address R Description Reset Value AN EPO CSR 0x52000184 L R W Endpoint 0 status register 0x00 0x52000187 B byte EPO CSR MCU Description Initial State SERVICED SE 7 W CLEAR The MCU should write a 1 to this bit to clear TUP END SETUP END SERVICED OU W CLEAR The MCU should write a 1 to this bit to clear T PKT RDY OUT PKT RDY SEND STALL 5 R W CLEAR MCU should write a 1 to this bit at the same time it clears OUT PKT RDY if it decodes an invalid token 0 Finish the STALL condition 1 The USB issues a STALL and shake to the current control transfer SETUP_END SET Set by the USB when a control transfer ends before DATA END is set When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO DATA END S CLEAR Set by the MCU on the conditions below 1 After loading the last packet of data into the FIFO at the same time IN PKT RDY is set 2 While it clears OUT PKT RDY after unloading the last packet of data 3 For a zero length data phase INIT Set by the USB if a control transaction is stopped due to a ET SENT_S
362. register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained if necessary by setting the offset to zero Therefore post indexed data transfers always write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected ELECTRONICS 3 35 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR HALFWORD LOAD AND STORES Setting 5 0 and H 1 may be used to transfer unsigned Half words between an 920 register and memory The action of LDRH and STRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below Signed byte and halfword loads The S bit controls the loading of sign extended data When S 1 the H bit selects between Bytes H 0 and Half words H 1 The L bit should not be set low Store when Signed S 1 operations have been selected The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit The LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of th
363. request The 8 external interrupt pin has a digital filter refer to EINTFLTn on page 9 26 Only 16 EINT pins EINT 15 0 are used for wakeup sources POWER OFF MODE AND I O PORTS All GPIO register values are preserved in Power OFF mode Refer to the Power OFF mode in the chapter Clock amp Power Management The EINTMASK can t prohibit the wake up from Power OFF mode But If ENTMASK is masking one of EINT 15 4 the wake up can be done but the EINT4 7bit and EINT8 23 bit of the SRCPND will not set to 1 just after the wake up ELECTRONICS 9 7 PORTS 53 2410 01 RISC MICROPROCESSOR PORT CONTROL REGISTER PORT A CONTROL REGISTERS GPACON GPADAT GPA22 22 0 Output 1 GPA21 21 0 Output 1 nRSTOUT nRSTOUT nRESET amp nWDTRST amp SW_RESET 0 Output GPA14 14 0 Output 12nGCS3 GPA12 12 0 Output 1 nGCS1 GPAS 0 Output 1 ADDR20 4 0 Output 1 ADDR19 9 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS GPA 22 0 22 0 When the port is configured as output port the pin state is the same as the that of the corresponding bit When the port is configured as functional pin undefined value will be read ELECTRONICS 9 9 I O PORTS 3C2410X01 RISC MICROPROCESSOR PORT B CONTROL REGISTERS GPBCON GPBDAT and GPBUP GPBCON 0x56000010 R EM Ww AN GPBUP 0x56000018 Pull up disable register for port B Configure the pins of port B 00 0x0
364. ress specified by label is a full 12 bit two s complement address but must always be halfword aligned ie bit O set to 0 since the assembler places label gt gt 1 in the Offset11 field EXAMPLES here B here Branch onto itself Assembles to OXE7FE Note effect of PC offset B jimmy Branch to jimmy Note that the THUMB opcode will contain the number of halfwords to offset jimmy Must be halfword aligned ELECTRONICS 4 37 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 19 LONG BRANCH WITH LINK 15 14 13 10 9 12 11 10 0 Long Branch and Link Offset High Low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 4 20 Format 19 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit O which must be 0 and creates two THUMB instructions Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address is placed in PC the address of the instruction
365. ributes are ignored There are 16 domains which are configured using the domain access control register ELECTRONICS 3 1 MMU ARM920T PROCESSOR TRANSLATED ENTRIES Each TLB caches 64 translated entries During CPU memory accesses the TLB provides the protection information to the access control logic If the TLB contains a translated entry for the modified virtual address the access control logic determines whether access is permitted f access is permitted and an off chip access is required the MMU outputs the appropriate physical address corresponding to the modified virtual address e f access is permitted and an off chip access is not required the cache services the access e f access is not permitted the MMU signals the CPU core to abort If a TLB misses it does not contain an entry for the virtual address the translation table walk hardware is invoked to retrieve the translation information from a translation table in physical memory Once retrieved the translation information is written into the TLB possibly overwriting an existing value The entry to be written is chosen by cycling sequentially through the TLB locations To enable use of TLB locking features the location to be written can be specified using CP15 register 10 TLB lockdown When the MMU is turned off as happens on reset no address mapping occurs and all regions are marked as non cacheable and non bufferable See About the caches and write buffer o
366. rom low to high When the TCNTn reaches 0 the TCNTn is reloaded automatically with the TCNTBn triggering an interrupt request In Interrupt Service Routine ISR auto reload and interrupt request are disabled to stop the timer When the value of the TCNTn is same as the TCMPn the logic level of the TOUTn is changed from low to high Even when the TCNTn reaches 0 the TCNTn is not any more reloaded and the timer is stopped because auto reload has been disabled No more interrupt requests are generated ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER PULSE WIDTH MODULATION PWM Write Write Write TCMPBn 60 TCMPBn 40 TCMPBn 30 Write Write Write TCMPBn 50 30 Next PWM Value Figure 10 5 Example of PWM PWM function can be implemented by using the TCMPBn PWM frequency is determined by TCNTBn Figure 10 5 shows a PWM value determined by TCMPBn For a higher PWM value decrease the TCMPBn value For a lower PWM value increase the TCMPBn value If an output inverter is enabled the increment decrement may be reversed The double buffering function allows the TCMPBn for the next PWM cycle written at any point in the current PWM cycle by ISR or other routine ELECTRONICS 10 7 PWM TIMER S3C2410X01 RISC MICROPROCESSOR OUTPUT LEVEL CONTROL Inverter off 1 1 1 1 1 OTL Inverter Initial State Period 1 i 1 Timer Stop
367. rom the frame memory based on the burst memory transfer mode consecutive memory fetching of 4 words 16 bytes per one burst request without allowing the bus mastership to another bus master during the bus transfer When the transfer request is accepted by bus arbitrator in the memory controller there will be four successive word data transfers from system memory to internal FIFO The total size of FIFO is 28 words which consists of 12 words FIFOL 16 words respectively The S3C2410X01 has two FIFOs to support the dual scan display mode In case of single scan mode one of the FIFOs FIFOH can only be used This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 3 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR STN LCD CONTROLLER OPERATION TIMING GENERATOR TIMEGEN The TIMEGEN generates the control signals for the LCD driver such as VFRAME VLINE VCLK and VM These control signals are closely related to the configuration on the LCDCON1 2 3 4 5 registers in the REGBANK Based on these programmable configurations on the LCD control registers in the REGBANK the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers The VFRAME pulse is asserted for the duration of the entire first line at a frequency of once pe
368. rror NAND FLASH MODE CONFIGURATION 1 Set NAND flash configuration by NFCONF register 2 Write NAND flash command onto NFCMD register 3 Write NAND flash address onto NFADDR register 4 Read Write data while checking NAND flash status by NFSTAT register R nB signal should be checked before read operation or after program operation NAND FLASH MEMORY TIMING HCLK CLE ALE N TWRPHO TWRPHI1 Figure 6 3 TACLS 0 TWRPHO0z1 TWRPH1 0 This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 6 3 NAND FLASH CONTROLLER 3C2410X01 RISC MICROPROCESSOR PIN CONFIGURATION D 7 0 Data Command Address In Out Port shared with the data bus CLE Command Latch Enable Output ALE Address Latch Enable Output nFCE NAND Flash Chip Enable Output nFRE NAND Flash Read Enable Output nFWE NAND Flash Write Enable Output nWAIT NAND Flash Ready nBusy Input BOOT AND NAND FLASH CONFIGURATIONS 1 OM 1 0 00b Enable NAND Flash controller auto boot mode 2 NCON 0 NAND Flash memory page size selection 0 256 Bytes Page 1 512 Bytes Page 3 NCON 1 NAND Flash memory address step selection 0 8 Step addressing 1 4 Step addressing 512 BYTE ECC PARITY CODE ASSIGNMENT TABLE DATAS Dataa DATAS
369. rs Reserved Note MRSR register must not be reconfigured while the code is running on SDRAM Important Note In STOP mode SL_IDLE mode SDRAM has to enter SDRAM self refresh mode ELECTRONICS 5 19 MEMORY CONTROLLER 5 20 NOTES 3C2410X01 RISC MICROPROCESSOR ELECTRONICS S3C2410X01 RISC MICROPROCESSOR NAND FLASH CONTROLLER 05 25 2002 NAND FLASH CONTROLLER Preliminary OVERVIEW Recently a NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM 53 2410 01 boot code can be executed on an external NAND flash memory In order to support NAND flash boot loader the S3C2410X01 is equipped with an internal SRAM buffer called Steppingstone When booting the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed Generally the boot code will copy NAND flash content to SDRAM Using hardware ECC the NAND flash data validity will be checked Upon the completion of the copy the main program will be executed on the SDRAM FEATURES 1 NAND Flash mode Support read erase program NAND flash memory 2 Auto boot mode The boot code is transferred into Steppingstone during reset After the transfer the boot code will be executed on the Steepingstone 3 Hardware ECC detecting block for hardware detecting and so
370. rs data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level Tx interrupt is generated if Transmit mode in control register is selected as Interrupt request or polling mode In the Non FIFO mode transferring data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request occurs instead of Rx or Tx interrupt in the situation mentioned above Table 11 1 Interrupts in Connection with FIFO FIFO Mode Non FIFO Mode Rx interrupt Generated whenever receive data reaches the Generated by the receive holding register trigger level of receive FIFO whenever receive buffer becomes full Generated when the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive any data during 3 word time receive time out This interval follows the setting of Word Length bit Tx interrupt Generated whenever transmit data reaches the Generated by the transmit holding trigger level of transmit FIFO Tx FIFO trigger register whenever transmit buffer Level becomes empty Error interrupt Generated when frame error parity error or break Generated by all errors However if signal are detected another error occurs at the same time only one interrupt is generated Generated whe
371. rs defined in CP14 are accessible with MCR and MRC instructions system control coprocessor CP15 which provides additional registers that are used to configure and control the caches MMU protection system the clocking mode and other system options of the ARM920T such as big or little endian operation The registers defined in CP15 are accessible with MCR and MRC instructions These are described in CP15 register map summary on page 2 4 The ARM920T also features an external coprocessor interface which allows the attachment of a closely coupled coprocessor on the same chip for example a floating point unit Registers and operations provided by any coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions e Memory accesses for instruction fetches and data loads and stores may be cached or buffered Cache and write buffer configuration and operation is described in detail in following chapters The MMU page tables which reside in main memory describe the virtual to physical address mapping access permissions and cache and write buffer configuration These are created by the operating system software and accessed automatically by the ARM920T MMU hardware whenever an access causes a TLB miss e The ARM920T has a Trace Interface Port which allows the use of Trace hardware and tools for real time tracing of instructions and data ELECTRONICS 2 1 PROGRAMMER S MO
372. s 0 the value specified by Imm is full 7 bit address but must be word aligned ie with bits 1 0 set to 0 since the assembler places lmm gt gt 2 in the field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 0 13 Store the lower 8 bits of R1 at the address formed by adding 13 to RO Note that the THUMB opcode will contain 13 as the Offset5 value ELECTRONICS 4 23 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 10 LOAD STORE HALFWORD 15 14 13 10 6 5 3 2 0 12 11 pt ones ra 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 4 11 Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory Addresses are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 4 11 Table 4 11 Halfword Data Transfer Instructions THUMB assembler ARMequivalent Action STRH Rd Rb 1 Rd Rb Add 1 to
373. s 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request Note If the FIQ mode interrupt occurs the corresponding bit of INTPND will not be turned on as the INTPND register is available only for IRQ mode interrupt ELECTRONICS 14 13 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR INTPND Bit Description Initial State mao dem O Notrequesied t Requesed o INT RTC 30 0 Notrequested 1 Requested 0 INT SPI1 29 0 Notrequested 1 Requested 0 NTUARTQ mj O Notrequestes T Remesed INT 27 0 Not requested 1 Requested 0 musen 9 0 T Remesed INT USBD 25 0 Not requested 1 Requested 0 24 Not used 0 0 Not requested 1 Requested INT_SPIO 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested po 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Re
374. s Thus if the MCU does not stop the clock after the first suspend interrupt it will continue to be interrupted every 3ms as long as there is no activity on the USB bus By default this interrupt is disabled ELECTRONICS 53 2410 01 RISC MICROPROCESSOR USB DEVICE INTERRUPT ENABLE REGISTER EP INT EN REG USB INT REG Corresponding to each interrupt register The USB device controller also has two interrupt enable registers except resume interrupt enable By default usb reset interrupt is enabled If bit 0 the interrupt is disabled If bit 1 the interrupt is enabled EP INT EN REG 0x5200015C L R W Determine which interrupt is enabled OxFF 0x5200015F B byte EP INT EN REG Bit MCU USB Description Initial State 4 INT 4 R W EP4 Interrupt Enable bit 1 0 Interrupt disable 1 Enable 1 EP3 INT EN EP3 Interrupt Enable bit 0 Interrupt disable 1 Enable EP2_INT_EN 2 R W EP2 Interrupt Enable bit 1 0 Interrupt disable 1 Enable EP1_INT_EN 1 R W EP1 Interrupt Enable bit 1 0 Interrupt disable 1 Enable EPO_INT_EN R W Interrupt Enable bit 1 0 Interrupt disable 1 Enable ELECTRONICS 13 9 USB DEVICE 53 2410 01 RISC MICROPROCESSOR USB INT EN REG 0x520016C L R W Determine which interrupt is enabled 0x04 0x5200016F B byte INT MASK REG MCU Description Initial State RESET INT EN 2 R W Reset interrupt enable bit 1 0 Interrupt disable 1 Enable Reseved
375. s 1 and the counter CURR_TC is loaded from DCON 19 0 register Note that the DMA ACK remains 1 until it is cleared later State 3 In this state sub FSM handling the atomic operation of DMA is initiated The sub FSM reads the data from the source address and then writes it to destination address In this operation data size and transfer size single or burst are considered This operation is repeated until the counter CURR_TC becomes 0 in Whole service mode while performed only once in Single service mode The main FSM this FSM counts down the CURR_TC when the sub FSM finishes each of atomic operation In addition this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON 29 register is set to 1 In addition it clears DMA ACK if one of the following conditions is met 1 CURR_TC becomes 0 in the Whole service mode 2 Atomic operation finishes in the Single service mode Note that in the Single service mode these three states of main FSM are performed and then stops and waits for another DMA REQ And if DMA REQ comes in all three states are repeated Therefore DMA ACK is asserted and then deasserted for each atomic transfer In contrast in the Whole service mode main FSM waits at state 3 until CURR_TC becomes 0 Therefore DMA ACK is asserted during all the transfers and then deasserted when TC reaches 0 However INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode Sing
376. s greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned 4 16 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value ELECTRONICS 4 17 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 7 LOAD STORE WITH REGISTER OFFSET 4 18 15 14 13 12 11 10 9 8 6 5 3 2 0 m 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 4 8 Format 7 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 4 8 Table 4 8 Summary of Format 7 Instructions STR Rad Rb Ro STR Rb Ro Pre indexed word store Calculate the target address by adding to
377. s initially set to the value of DCONn 19 0 register and decreased by one at the end of every atomic transfer ELECTRONICS 8 11 DMA 3C2410X01 RISC MICROPROCESSOR DMA CURRENT SOURCE DCSRC REGISTER DCSRCO 0 4000018 DMA 0 current Source Register 0x00000000 DCSRC1 0x4b000058 DMA 1 current Source Register 0x00000000 DCSRC2 0x4b000098 DMA 2 current Source Register 0x00000000 DCSRC3 0x4b0000d8 ES DMA 3 current Source Register 0x00000000 DCSRCn Description initial State CURR SRC 30 0 Current source address for DMAn 0x00000000 CURRENT DESTINATION DCDST REGISTER 7 0 R DMAO curent destination register 0x00000000 peost R 1 curent destination register 0x00000000 2 DMA Z curent destination register 0x00000000 DCDST3 3 current destination register 0x00000000 CURR_DST 30 0 Current destination address for DMAn 0x00000000 8 12 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR DMA DMA MASK TRIGGER DMASKTRIG REGISTER DMASKTRIGO 0 46000020 RW DMA 0 mask trigger register DMASKTRIG1 0 40000060 RW DMA 1 mask trigger register 000 ___ DMASKTRIG2 0x4b0000a0 R W DMA 2 mask trigger register DMASKTRIG3 0x4b0000e0 RW DMA 3 mask trigger register E DMASKTRIGn Description Initial State STOP 2 Stop the DMA operation 1 DMA stops as soon as the c
378. s revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 39 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR Example 1 160 x 160 4 level gray 80 frame sec 4 bit single scan display HCLK frequency is 60 MHz WLH 1 WDLY 1 Data transmission rate 160 x 160 x 80 x 1 4 512 kHz CLKVAL 58 VCLK 517KHz HOZVAL 39 LINEVAL 159 LINEBLANK 10 LCDBASEL LCDBASEU 3200 Note The higher the system load is the lower the cpu performance is Example 2 Virtual screen register 4 level gray Virtual screen size 1024 x 1024 LCD size 320 x 240 LCDBASEU 0x64 4 bit dual scan 1 halfword 8 pixels 4 level gray Virtual screen 1 line 128 halfword 1024 pixels LCD 1 line 320 pixels 40 halfword OFFSIZE 128 40 88 0x58 PAGEWIDTH 40 0x28 LCDBASEL LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 100 40 88 x 120 0x3C64 15 40 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 Gray Level Selection Guide The 53 2410 01 LCD controller can generate 16 gray level using Frame Rate Control FRC The FRC characteristics may cause unexpected patterns in gray level These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates Because the quality of LCD gray levels depends on LCD s own characteristics the user has to select an appropriate gray level afte
379. s set request coproc 2 to do operation 5 type 2 on CR2 and CR3 and put the result in CR1 3 52 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC or store STC a subset of a coprocessors s registers directly to memory ARM920T is responsible for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 28 27 25 24 23 22 21 20 19 16 15 12 11 0 m D D 9 ae 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions ELECTRONICS 3 53 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR THE COPROCESSOR FIELDS The CP field is used to identify the coprocessor which is required to supply or
380. s the 53 2410 SPI as a slave When this error is detected the following actions are taken immediately But you must previously set SPPINn s ENMUL bit if you want to detect this error 1 The SPCONn s MSTR bit is forced to 0 to operate slave mode 2 The SPSTAn s MULF flag is set and an SPI interrupt is generated 22 8 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR SPI INTERFACE 05 20 2002 SPI Baud Rate Prescaler Register Reset alus SPPREO 0x5900000C SPI cannel 0 baud rate prescaler register SPPRE1 0x5900002C SPI cannel 1 baud rate prescaler register initial State Prescaler Value 7 0 Determine SPI clock rate as above equation 0x00 Baud rate PCLK 2 Prescaler value 1 Note Baud rate should be less than 25MHz SPI Tx Data Register Reset Value SPTDATO 0x59000010 SPI channel 0 Tx data register SPTDAT1 0x59000030 SPI channel 1 Tx data register SPTDATA Bi Description Tx Data Register 7 0 This field contains the data to be transmitted over the SPI channel SPI Rx Data Register Reset Value SPRDATO 0 59000014 SPI channel 0 Rx data register SPRDAT1 0x59000034 SPI channel 1 data register SPRDATA Ei beserion iia State Rx Data Register 7 0 This field contains the data to be received over the SPI channel This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal
381. sed to implement a CODEC interface to an external 8 16 bit stereo audio CODEC IC for mini disc and portable applications The IIS bus interface supports both IIS bus data format and MSB justified data format The interface provides DMA transfer mode for FIFO access instead of an interrupt It can transmit and receive data simultaneously as well as transmit or receive data alternatively at a time This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 21 1 IIS BUS INTERFACE S3C2410X01 RISC MICROPROCESSOR TxFIFO RxFIFO BLOCK DIAGRAM IPSR_A IPSR_B Figure 21 1 IIS Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface register bank and state machine BRFC Bus interface logic and FIFO access are controlled by the state machine 5 bit dual prescaler IPSR One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator 64 byte FIFOs TxFIFO and RxFIFO In transmit data transfer data are written to TxFIFO and in the receive data transfer data are read from RxFIFO Master IISCLK generator SCLKG In master mode serial bit clock is generated from the master clock Channel generator and state machine CHNC IISCLK and IISLRCK are generated and controlled by the channel state machin
382. ser does not want to change the default value of PLLCON register after reset the user should write the same value into PLLCON register by software The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency FCLK can be configured as PLL output Mpll immediately after lock time Y PLL can operate after OM 3 2 is latched nRESET OSC 2 PLL is initially configured by software Clock 2 Disable ve 2 Y VCO is adapted to new clock frequency VCO output n FCLK logic operates by xrip A FCLK is new frequency Figure 7 4 Power On Reset Sequence when the external clock source is a crystal oscillator 7 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR CLOCK amp POWER MANAGEMENT Change PLL Settings In Normal Operation Mode During the operation of the S3C2410X01 in NORMAL mode the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted During the lock time the clock is not supplied to the internal blocks in the S3C2410X01 Figure 7 5 shows the timing diagram JUUUUUQUU PMS Setting PLL Lock time It changes to new PLL clock after automatic lock time Figure 7 5 Changing Slow Clock by Setting PMS Value USB Clock Control USB host interface and USB device interface needs 48Mhz clock In the S3C2410X01 the USB dedicated PLL UPLL generates
383. set RACMD 1 after command sent assume DatMode sets to 2 b10 Busy After Determine when busy receive start after command sent or not Command 0 directly after DatMode set BACMD 1 after command sent assume DatMode sets to 2 b01 Block mode 17 Data transfer mode BlkMode 0 stream data transfer 1 block data transfer Wide bus enable Determine enable wide bus mode 7 WideBus 0 standard bus mode only SDIDAT 0 used 1 wide bus mode SDIDAT 3 0 used DMA Enable 15 Enable DMA Bc 0 disable polling 1 enable Stop by force 14 Determine whether data transfer stop by force or not 0 normal 1 stop by force Data Transfer 13 12 Determine the direction of data transfer Mode DatMode 00 ready 01 only busy check start 10 data receive start 11 data transmit start 11 0 Block Number 0 4095 Do not care when stream mode If you want one of TARSP RACMD and BACMD bits SDIDCON 20 18 to 1 you need to write on SDIDCON register ahead of on SDICCON register always need for SDIO um ELECTRONICS 19 7 SD HOST CONTROLLER 3C2410X01 RISC MICROPROCESSOR SDI Data Remain Counter SDIDCNT Register Register Address R W Description Reset Value SDIDCNT 0x5A000030 SDI data remain counter register 0 0 SDIDONT Bi Description initial Value BlkNumCnt 23 12 Remaining block number 0x000 BlkCnt 11 0 Remaining data byte of 1 block 0x000 SDI Data
384. set in a LDM STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruction is a LDM then SPSR mode is transferred to CPSR at the same time as R15 is loaded STM with R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the User bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the User bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked register during the following cycle inserting a dummy instruction such as MOV RO RO after the LDM will ensure safety USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 43 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is written b
385. sh mode by setting the REFRESH 22 1b 10 Wait until SDRAM self refresh is effective 1 11 Set MISCCR 19 17 111b to make SDRAM signals SCLKO SCLK1 and SCKE protected during Power OFF mode 12 Set the Power OFF mode bit in the CLKCON register Procedure to Wake up from Power OFF mode 1 The internal reset signal will be asserted if one of the wake up sources is issued It s exactly same with the case of the assertion of the external nRESET pin 2 Check GSTATUS2 2 in order to know whether or not the power up is caused by the wake up from Power OFF mode 3 Release the SDRAM signal protection by setting MISCCR 19 17 000b 4 Configure the SDRAM memory controller 5 Wait until the SDRAM self refresh is released 6 The information in GSTATUS 3 4 be used for user s own pourpose because the value in GSTATUS 3 4 has been preserved during Power OFF mode ELECTRONICS 7 13 CLOCK amp POWER MANAGEMENT Power Control of VDDi and VDDiarm 53 2410 01 RISC MICROPROCESSOR In Power_OFF mode only VDDi and VDDiarm will be turned off which is controlled by PWREN pin If PWREN signal is active H VDDi and VDDiarm are supplied by an external voltage regulator If PWREN pin is inactive L the VDDi and VDDiarm are turned off NOTE Although VDDi and VDDiarm may be turned off the other power pins have to be supplied Pin States in Power_OFF Mode The pin states of the Power_OFF mode is as follows
386. short card status 63 32 long 0x00000000 SDI Response Register 3 SDIRSP3 RW SDIRSP3 0x5A000020 SDI response register 3 Bit Deseripon initial Value 31 0 Unused short card status 31 0 long 0x00000000 SDI Data Busy Timer SDIDTIMER Register SDIDTIMER 0x5A000024 R W SDI data busy timer register 0x2000 SDIDTIMER initial Value 15 0 Data busy timeout period 0 65535 cycle 0x2000 19 6 ELECTRONICS 3C2410X01 RISC MICROPROCESSOR SD HOST CONTROLLER SDI Block Size SDIBSIZE Register Reset Value SDIBSIZE 0x5A000028 R W SDI block size register SDIBSIZE initial Value BlkSize 11 0 Block Size value 0 4095 byte Do not care when stream mode 0x000 In Case of multi block BlkSize must be aligned to word 4byte size BlkSize 1 0 00 SDI Data Control SDIDCON Register RW Reset Value SDIDCON 0x5A00002C SDI data control register SDIDCON Bi DBeseripion WmiiaiValue SDIO Interrupt Determine whether SDIO Interrupt period is 2 cycle or extend Period Type more cycle when last data block is transferred for SDIO PrdType 0 exactly 2 cycle 1 more cycle likely single block Transmit After Determine when data transmit start after response receive or not Response 0 directly after DatMode set TARSP 1 after response receive assume DatMode sets to 2 b11 Receive After Determine when data receive start after command sent or not Command 0 directly after DatMode
387. should write a new data into the IICDS register again In Receive mode when data is received the IIC bus interface will wait until IICDS register is read Before the new data is read out the SCL line will be held low and then released after it is read The 53 2410 01 should hold the interrupt to identify the completion of the new data reception After the CPU receives the interrupt request it should read the data from the IICDS register BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters If a master with a SDA High level detects the other master with a SDA active Low level it will not initiate a data transfer because the current level on the bus does not correspond to its own The arbitration procedure will be extended until the SDA line turns High However when the masters simultaneously lower the SDA line each master should evaluate whether or not the mastership is allocated to itself For the purpose of evaluation each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters will detect Low on the bus because the Low status is superior to the High status in power When this happens L
388. sor CP15 allows configuration and control of the caches MMU protection system and clocking mode of the ARM920T The ARM920T coprocessor 15 registers are described under the following sections e Accessing 15 registers on page 2 5 e Register 0 ID code register on page 2 7 e Register 0 Cache type register on page 2 8 e Register 1 Control register on page 2 10 e Register 2 Translation table base TTB register on page 2 12 e Register 3 Domain access control register on page 2 13 e Register 4 Reserved on page 2 14 e Register 5 Fault status registers on page 2 14 e Register 6 Fault address register on page 2 15 e Register 7 Cache operations on page 2 15 e Register 8 TLB operations on page 2 18 e Register 9 Cache lock down register on page 2 19 e Register 10 TLB lock down register on page 2 21 e Registers 11 12 amp 14 Reserved on page 2 22 e Register 13 Process ID on page 2 22 e Addresses in ARM920T on page 2 6 e Register 15 Test configuration register on page 2 24 ELECTRONICS 2 3 PROGRAMMER S MODEL ARM920T PROCESSOR CP15 REGISTER MAP SUMMARY CP15 defines 16 registers The register map for CP15 is shown in Table 2 2 Table 2 2 CP15 Register Map Register Wweddibe _ 20 j Oaheyp Unpredictable O Om 2 Tansiaion ablebase 3 Domanaesscowo Domain access comro 4 ____ ____ ____ Fass
389. sors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP5 field is used to contain an identifying number in the range 0 to 15 for each coprocessor and a coprocessor will ignore any instruction which does not contain its number in the CP5 field The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field and possibly in the CP field on the contents of CRn and CRm and place the result in CRd ELECTRONICS 3 51 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop S and are defined as sequential S cycle and internal I cycle Assembler syntax CDP cond p lt expression1 gt cd cn cm lt expression2 gt cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP Opc field cd cn and cm Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES CDP p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and CR3 and put the result in CR1 CDPEQ p2 5 c1 c2 c3 2 If Z flag i
390. ssor mode or the contents of the registers SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state Entering ARM State Entry into ARM state happens e On execution of the BX instruction with the state bit clear the operand register processor taking an exception IRQ RESET UNDEF ABORT SWI etc In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address MEMORY FORMATS ARM920T views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to 3 hold the first stored word bytes 4 to 7 the second and so on ARM920T can treat words in memory as being stored either in Big Endian or Little Endian format ELECTRONICS 2 1 PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR BIG ENDIAN FORMAT In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher Address Word Address Lower Address Most significant byte is at lowest address Word is addressed by
391. stant to either the PC or the SP and load the resulting address into a register The THUMB assembler syntax is shown in the following table Table 4 13 Load Address THUMB assembler ARM equivalent ADD Rd PC lmm ADD Rd R15 Add to the current value of the program counter PC and load the result into Rd ADD Rd SP tlmm ADD Rd R13 Add stlmm to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by lmm is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places 1 gt gt 2 in field Word 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0 The CPSR condition codes are unaffected by these instructions 4 28 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 13 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD R2 PC 572 R2 PC 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212 SP R13 212 but don t set the condition codes
392. stem memory is used as the display memory Supports Multiple Virtual Display Screen Supports Hardware Horizontal Vertical Scrolling Programmable timing control for different display panels Supports little and big endian byte ordering as well as WinCE data formats Supports SEC TFT LCD panel SAMSUNG 3 5 Portrait 256K Color Reflective a Si TFT LCD LTS350Q1 PD1 TFT LCD panel with touch panel and front light unit LTS350Q1 PD2 TFT LCD panel only EXTERNAL INTERFACE SIGNAL VFRAME VSYNC STV Frame synchronous signal STN vertical synchronous signal TFT SEC TFT signal VLINE HSYNC CPV Line synchronous pulse signal STN horizontal sync signal TFT SEC TFT signal VOLK LCD HCLK Pixel clock signal STN TFT SEC TFT signal VD 23 0 LCD pixel data output ports STN TFT SEC TFT VM VDEN TP AC bias signal for the LCD driver STN data enable signal TFT SEC TFT signal LEND STH Line end signal TFT SEC TFT signal LCD PWREN LCD panel power enable control signal LCDVFO SEC TFT Signal OE LCDVF1 SEC TFT Signal REV LCDVF2 SEC TFT Signal REVB The 33 output ports in totalincludes 24 data bits and 9 control bits 15 2 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 BLOCK DIAGRAM System Bus VCLK LCD_HCLK VLINE HSYNC CPV VFRAME VSYNC STV VIDEO VDEN TP MUX LPC3600 LCDVFO LCDVF1 LCDVF2 LCDCDMA VIDPRCS VD 23 0 LPC3600 is a
393. stem should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour 3 36 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET Big Endian Configuration A signed byte load LDRSB expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary on data bus inputs 23 through to 16 if itis a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A halfword load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is on a word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit 0 of the supplied address is HIGH then the 920 will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory syst
394. ster format and the coprocessor instructions to access them are given there ADDRESS TRANSLATION The MMU translates virtual addresses generated by the CPU core and by CP15 register 13 into physical addresses to access external memory It also derives and checks the access permission using a translation lookaside buffer TLB The MMU table walking hardware is used to add entries to the TLB The translation information which comprises both the address translation data and the access permission data resides in a translation table located in physical memory The MMU provides the logic needed to traverse this translation table and load entries into the TLB There are up to two stages to the hardware table walking and hence permission checking process The number of stages depends on whether the address in question has been marked as a section mapped access or a page mapped access There is one size of section and three sizes of page mapped access large pages small pages and tiny pages The translation process always starts out in the same way with a level one fetch A section mapped access requires only a level one fetch but a page mapped access requires a subsequent level two fetch 3 4 ELECTRONICS ARM920T PROCESSOR TTB base Indexed by modified virtual address bits 31 20 ELECTRONICS Level one fetch Translation table Section base Indexed by modified virtual address bits 19 0 4096 entries Coarse page ta
395. ster is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 L HW W Little HalfWord Word Bi HW W Big HalfWord Word IIS FIFO CONTROL IISFCON REGISTER R W IISFCON 0x5500000C Li HW Li W Bi W IIS FIFO interface register 0x0 0x5500000E Bi HW Transmit FIFO access mode select 15 0 Normal 1 Receive FIFO access mode select 14 0 Normal 1 Transmit FIFO 13 0 Disable 1 Enable Receive FIFO 12 0 Disable 1 Enable Transmit FIFO data count 11 6 Data count value 0 32 000000 Read only Receive FIFO data count 5 0 Data count value 0 32 000000 Read only NOTES 1 The IISFCON register is accessible for each halfword and word unit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word ELECTRONICS 21 7 IIS BUS INTERFACE S3C2410X01 RISC MICROPROCESSOR IIS FIFO IISFIFO REGISTER 15 bus interface contains two 16 byte FIFO for the transmit and receive mode Each FIFO has 16 width and 24 depth form which allows the FIFO to handles data for each halfword unit regardless of valid data size Transmit and receive FIFO access is performed through FIFO entry the address of FENTRY is 0x15508010 IISFIFO 0x55000010 Li HW R W IIS FIFO register 0 0 0x5500001
396. t C Undefined 0x0 Undefined UM IN ELECTRONICS 00 Input 10 VD 7 00 Input 10 VD 6 00 Input 10 VD 5 00 Input 10 VD 4 00 Input 10 VD 3 00 Input 10 VD 2 00 Input 10 VD 1 00 Input 10 VD 0 00 Input 10 LCDVF2 00 Input 10 LCDVF1 00 Input 10 LCDVFO 00 Input 10 VM 00 Input 10 VFRAME 00 Input 10 VLINE 00 Input 10 VCLK 00 Input 10 LEND 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved PORTS 53 2410 01 RISC MICROPROCESSOR GPC 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read GPCUP Bt peseptm GPC 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 53 2410 01 RISC MICROPROCE
397. t in a cache hit is if software has changed the value of the Ctt bit in the MMU translation table descriptor without invalidating the cache contents This is a programming error as the behavior in this case is architecturally unpredictable and varies between implementations ELECTRONICS 4 3 CACHES WRITE BUFFER ARM920T PROCESSOR INSTRUCTION CACHE REPLACEMENT ALGORITHM The ICache and DCache replacement algorithm is selected by the RR bit in the CP15 control register CP15 register 1 bit 14 Random replacement is selected at reset Setting the RR bit to 1 selects round robin replacement INSTRUCTION CACHE LOCKDOWN Instructions can be locked into the ICache causing the ICache to guarantee a hit and providing optimum and predictable execution time Instructions are locked into the ICache by first ensuring the code to be locked is not already in the cache This is tested by flushing either the whole ICache or specific lines A short software routine can then be used to load the instructions into the ICache The software routine must either be non cacheable or already in the ICache but not in an ICache line which is about to be overwritten The instructions to be loaded must be from a memory region which is cacheable The software routine operates by writing to CP15 register 9 to force the replacement counter to a specific ICache line and by using the prefetch ICache line operation available via CP15 register 7 to force the ICache to perform
398. t is generated the source pending bit will be set 14 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR INTERRUPT CONTROLLER INTERRUPT SOURCES The interrupt controller supports 56 interrupt sources as shown in the table below Sources Descriptions Arbiter Group ADC EOC and Touch interrupt INT_ADC INT_TC INT_RTC RTC alarm interrupt ARB5 INT_SPI1 SPI interrupt ARB5 UARTO Interrupt ERR RXD and TXD INT_IIC interrupt ARB4 INT_USBD USB Device interrupt ARB4 Reserved Reserved ARB4 UART1 Interrupt ERR TXD INT_SPIO SPIO interrupt ARB4 LCD interrupt INT_FrSyn and INT_FiCnt UART2 Interrupt ERR and TXD Watch Dog timer interrupt ELECTRONICS 14 3 INTERRUPT CONTROLLER 53 2410 RISC MICROPROCESSOR INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters six first level arbiters and one second level arbiter as shown in Figure 14 1 below 4 REQ1 EINTO ARBITERO 4 REQA EINT3 ARBITER6 REQU EINTA 7 5 REQVEINTS 23 REQ2 reserved ARBITER 4 REQ3 nBATT FLT 4 REQA INT 4 ARBITER2 4 REQS INT UART2 ARM IRQ REQO INT LCD 4 REQ2 INT_DMA1 ARBITERS REQ3 INT DMA2 REQ4 INT_DMA3 lt REGS INT SDI lt REQO INT_SPIO lt REQ1 INT UART1 ARBITER4 REQ2 reserved lt REQS INT_IIC 4 4 REQ 2 INT SPI ARBITERS
399. t of Watchdog timer 0 Disable 1 Enable Clock select 4 3 Determine the clock division factor 00 16 01 32 10 64 11 128 Reserved 1 Reserved This bit must be 0 in normal operation Reset enable disable Enable or disable bit of Watchdog timer output for reset signal 1 Assert reset signal of the S3C2410X01 at watchdog time out 0 Disable the reset function of the watchdog timer Interrupt generation Enable or disable bit of the interrupt 0 Disable 1 Enable ELECTRONICS 18 3 WATCHDOG TIMER 3C2410X01 RISC MICROPROCESSOR WATCHDOG TIMER DATA WTDAT REGISTER The WTDAT register is used to specify the time out duration The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation However using 0x8000 initial value will drive the first time out In this case the value of WTDAT will be automatically reloaded into WTCNT WTDAT 0x53000004 R W Watchdog timer data register 0x8000 Count reload value 15 0 Watchdog timer count value for reload 0x8000 WATCHDOG TIMER COUNT WTCNT REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially so the WTCNT register must be set to an initial value before enabling it WTCNT 0x53000008 Watchdog timer count reg
400. t the condition codes on the result of R4 R12 Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outof THUMB into R1 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUNB state is entered ie ARM state here Now processing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit 0 cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution ELECTRONICS 4 15 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 6 PC RELATIVE LOAD 15 14 13 7 0 12 11 10 8 llolsl we 7 0 Immediate Value 10 8 Destination Register Figure 4 7 Format 6 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The THUMB assembler syntax is shown below Table 4 7 Summary of PC Relative Load Instruction THUMB assembler ARMequivalent Acton gt LDR R PC lmm LDR R15 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by lmm is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places lmm gt gt 2 in field Word 8 The value of the PC will be 4 byte
401. ta is transmitted in 2 s complement with the MSB first The MSB is transmitted first because the transmitter and receiver may have different word lengths The transmitter does not have to know how many bits the receiver can handle nor does the receiver need to know how many bits are being transmitted When the system word length is greater than the transmitter word length the word is truncated least significant data bits are set to 0 for data transmission If the receiver gets more bits than its word length the bits after the LSB are ignored On the other hand if the receiver gets fewer bits than its word length the missing bits are set to zero internally And therefore the MSB has a fixed position whereas the position of the LSB depends on the word length The transmitter sends the MSB of the next word at one clock period whenever the IISLRCK is changed Serial data sent by the transmitter may be synchronized with either the trailing HIGH to LOW or the leading LOW to HIGH edge of the clock signal However the serial data must be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when transmitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted IISLRCK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading e
402. te Offset Offset is an immediate value 11 0 Offset 11 0 11 0 Unsigned 12 bit immediate offset 11 4 3 0 3 0 Offset register 11 4 Shift applied to Rm 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 28 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET OFFSETS AND AUTO INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction or a second register possibly shifted in some way The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base value may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed data transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware SHIFTED REGISTER OFFSET Th
403. te in Interrupt based or DMA based mode In other words the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART The UART can support bit rates of up to 115 2K bps using system clock If an external device provides the UART with UCLK then the UART can operate at higher speed Each UART channel contains two 16 byte FIFOs for receive and transmit The 53 2410 01 UART includes programmable baud rates infra red IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator a transmitter a receiver and a control unit as shown in Figure11 1 The baud rate generator can be clocked by PCLK or UCLK The transmitter and the receiver contain 16 byte FIFOs and data shifters Data is written to FIFO and then copied to the transmit shifter before being transmitted The data is then shifted out by the transmit data pin TxDn Meanwhile received data is shifted from the receive data pin RxDn and then copied to FIFO from the shifter FEATURES RxD1 TxD1 RxD2 and TxD2 with DMA based or interrupt based operation UART Ch 0 1 and 2 with IrDA 1 0 amp 16 byte FIFO UART Ch 0 and 1 with nRTSO nCTSO nRTS1 and nCTS1 Supports handshake transmit receive This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal p
404. ter WTCNT In this reason an initial value must be written to the watchdog timer count WTONT register before the watchdog timer starts CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2410X01 is in debug mode using Embedded ICE the watchdog timer must not operate The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal DBGACK signal Once the DBGACK signal is asserted the reset output of the watchdog timer is not activated as the watchdog timer is expired 18 2 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR WATCH DOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL WTCON REGISTER The WTCON register allows the user to enable disable the watchdog timer select the clock signal from 4 different sources enable disable interrupts and enable disable the watchdog timer output The Watchdog timer is used to resume the S3C2410X01 restart on mal function after its power on if controller restart is not desired the Watchdog timer should be disabled If the user wants to use the normal timer provided by the Watchdog timer enable the interrupt and disable the Watchdog timer WTCON 0x53000000 R W Watchdog timer control register 0x8021 w on S arsane Prescaler value 15 8 Prescaler value 0x80 The valid range is from 0 to 28 1 Reserved 7 6 Reserved These two bits must be 00 in normal operation Watchdog timer Enable or disable bi
405. terface FCLK is used to control the internal ARM9TDMI processor core and any cache operations FCLK must have a higher frequency and must also be an integer multiple of BCLK with a BCLK transition only when FCLK is HIGH An example is shown in Figure 5 2 Figure 5 2 Synchronous Clocking Mode If the ARM920T performs an external access for example a cache linefill the ARM920T will switch to BCLK to perform the access The delay when switching from FCLK to BCLK is a minimum of one FCLK phase and a maximum of one BCLK cycle An example of the clock switching is shown in Figure 5 3 The delay when switching from BCLK to FCLK is a maximum of one FCLK phase Figure 5 3 Switching from FCLK to BCLK in Synchronous Mode Care must be taken if BCLK is stopped by the system so that when BCLK is restarted it does not violate any of the above restrictions 5 2 ELECTRONICS ARM920T PROCESSOR CLOCK MODES ASYNCHRONOUS MODE This mode is typically used in systems with low speed memory In this mode of operation GCLK can be sourced from BCLK and FCLK BCLK is used to control the AMBA memory interface FCLK is used to control the internal ARM9TDMI processor core and any cache operations The one restriction is that FCLK must have a higher frequency than BCLK An example is shown in Figure 5 4 Figure 5 4 Asynchronous Clocking Mode If the ARM920T performs an external access for example a cache miss or a cache line fill ARM920T will switch t
406. terface is compatible with the Advanced Microcontroller Bus Architecture AMBA bus scheme either as a fully compliant AMBA bus master or as a slave for production test The ARM920T also has a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation ELECTRONICS 1 1 INTRODUCTION ARM920T PROCESSOR PROCESSOR FUNCTIONAL BLOCK DIAGRAM Shows the functional block diagram of the ARM920T 11 Extamal Instruction Instruction 31 0 Cache MMU Interface masa 13 ID 31 0 IVA 31 0 Trace ARM9TDMI AMBA Interface Processor Core Bus Port Integral EmbeddedICE Interface DAV 31 0 DD 31 0 Write Buffer DMVA 31 0 DPA 31 0 JTAG Data Data Write Back Cache MMU PA TAG RAM WBPA 31 0 DINDEX 31 0 Figure 1 1 ARM920T Functional Block Diagram 1 2 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Appendix 2 PROGRAMMER S MODEL ABOUT THE PROGRAMMER S MODEL ARM920T incorporates the ARM9TDMI integer core which implements the ARMVvAT architecture It executes the ARM and Thumb instruction sets and includes Embedded ICE JTAG software debug features The programmer s model of the ARM920T consists of the programmer s model of the ARM9TDMI with the following additions and modifications The ARM92OT incorporates two coprocessors 14 which allows software access to the debug communications channel The registe
407. the following table Table 4 12 SP Relative Load Store Instructions THUMB assembler ARM equivalent Action STR Rd STR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR Rd lmm LDR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied in Imm is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places gt gt 2 in the Word8 field 4 26 ELECTRONICS 53 2410 RISC MICROPROCESSOR THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R4 5 4921 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value ELECTRONICS 4 27 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR FORMAT 12 LOAD ADDRESS 0 14 ws gt 7 0 8 bit Unsigned Constant 10 8 Destination Register 11 Source 0 PC 1 SP Figure 4 13 Format 12 OPERATION These instructions calculate an address by adding an 10 bit con
408. the UART to modem interface instead of null modem nRTS nCTS nDSR nDTR DCD and nRI signals are needed In this case the users can control these signals with general I O ports by software because the AFC does not support the RS 232C interface Interrupt DMA Request Generation Each UART of the S3C2410X01 has seven status Tx Rx Error signals Overrun error Parity error Frame error Break Receive buffer data ready Transmit buffer empty and Transmit shifter empty all of which are indicated by the corresponding UART status register UTRSTATn UERSTATn The overrun error parity error frame error and break condition are referred to as the receive error status each of which can cause the receive error status interrupt request if the receive error status interrupt enable bit is set to one in the control register UCONn When a receive error status interrupt request is detected the signal causing the request can be identified by reading the value of UERSTSTn When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level Rx interrupt is generated if Receive mode in control register UCONn is selected as 1 Interrupt request or polling mode In the Non FIFO mode transferring the data of the receive shifter to the receive holding register will cause Rx interrupt under the Interrupt request and polling mode When the transmitter transfe
409. tion Conversion External Voltage NEUEN AIN 5 Hi Z Y Position Conversion AIN 7 External Voltage EE Waiting for Interrupt Mode gt When Touch Screen Controller is in Waiting for Interrupt Mode it waits for Stylus down The controller generates Interrupt INT_TC signals when the Stylus is down on Touch Screen Panel After an interrupt occurs X and Y position can be read by the proper conversion mode Separate X Y position conversion Mode or Auto X Y Position Conversion Mode Table 16 3 Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode XP XM YP YM Waiting for Interrupt Mode Pull up AIN 5 Standby Mode Standby mode is activated when STDBM of ADCCON register is set 1 In this mode A D conversion operation is halted and XPDATA Normal ADC of ADCDATO and YPDATA of ADCDAT1 contain the previous converted data ELECTRONICS 16 5 A D CONVERTER AND TOUCH SCREEN 3C2410X01 RISC MICROPROCESSOR Programming Notes 1 The A D converted data can be accessed by means of interrupt or polling method With interrupt method the overall conversion time from A D converter start to converted data read may be delayed because of the return time of interrupt service routine and data access time With polling method by checking the ADCCON 15 end of conversion flag bit the read time ADCDAT register can be determined 2 A D conversion can be activated in different way After ADCCON 1 A D conv
410. tion Conversion Mode Separate X Y Position Conversion Mode is consist of two Conversion Modes X Position Mode and Y Position Mode The first mode is operated in the following way X Position Mode AUTO PST 0 and XY PST 1 writes X position conversion data to XPDATA of ADCDATO register After conversion The Touch Screen Interface generates the Interrupt source INT to Interrupt Controller Y Position Mode AUTO PST 0 and XY PST 2 writes Y position conversion data to XPDATA of ADCDATO After the conversion the Touch Screen Interface also generates the Interrupt source INT to Interrupt Controller Table 16 1 Condition of Touch Screen Panel Pads in Separate X Y Position Conversion Mode _ mM 16 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR A D CONVERTER AND TOUCH SCREEN Auto Sequential X Y Position Conversion Mode Auto Sequential X Y Position Conversion Mode AUTO_PST 1 and XY_PST 0 is operated in the following way The Touch Screen Controller automatically converts X position and Y position The Touch Screen Controller writes X measurement data to XPDATA of ADCDATO and then writes Y measurement data to YPDATA of ADCDAT1 After Auto Sequential Position Conversion The Touch Screen Controller generates Interrupt source INT to Interrupt Controller Table 16 2 Condition of Touch Screen Panel Pads in Auto Sequential X Y Position Conversion Mode XP YP YM X Posi
411. tion codes 1 Set condition codes 24 21 Operation codes 0000 Op1 AND Op2 0001 EOR Rd Op1 EOR Op2 0010 SUB Rd Op1 Op2 0011 RSB Rd 2 1 0100 ADD Rd 1 2 0101 ADC Rd 1 2 0110 SBC Rd OP1 Op2 C 1 0111 RSC Rd 2 1 1 1000 TST set condition codes on Op1 AND Op2 1001 TEO set condition codes on OP1 EOR Op2 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes Op1 0p2 1100 ORR Rd Op1 OR Op2 1101 MOV Rd Op2 1110 BIC Rd Op1 AND NOT Op2 1111 2 MVN Rd NOT Op2 25 Immediate operand 0 Operand 2 is a register 1 Operand 2 is an immediate value 11 0 Operand 2 type selection 11 34 0 3 0 2nd operand register 11 4 Shift applied to Rm 11 8 7 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition field Figure 3 4 Data Processing Instructions ELECTRONICS 3 9 ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands The first operand is always a register Rn The second operand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction C
412. tion describes the behavior of the ARM920T implementation in areas which are architecturally unpredictable For portability to other ARM implementations software should not depend on this behavior A read from a non cacheable NCB or NCNB region which unexpectedly hits in the cache will still read the required data from the ASB The contents of the cache will be ignored and the cache contents will not be modified This includes the read portion of a swap SWP or SWPB instruction A write to a non cacheable NCB or NCNB region which unexpectedly hits in the cache will update the cache and will still cause an access on the ASB PHYSICAL ADDRESS TAG RAM The ARM920T implements a PA TAG RAM in order to perform write backs from the data cache A write back occurs when dirty data that is about to be overwritten by linefill data comes from a memory region that is marked as a write back region This data is written back to main memory to maintain memory coherency Dirty data is data that has been modified in the cache but not updated in main memory When a line is written into the data cache the physical address TAG DPA 31 5 is written into the PA TAG RAM If this line comes to be written back to main memory the PA TAG RAM is indexed into by the data cache and the physical address WBPA 31 0 is returned to the AMBA Bus interface so that it can perform the write back The PA TAG RAM Array for a 16k data cache comprises 8 segments x 64 rows se
413. to 63 The segment is specified by bits 7 5 of the virtual address of the data access which missed Data is locked into the DCache by restricting the range of victim numbers produced by the replacement algorithm so that some cache lines are never selected as victims The base pointer for the DCache victim generator can be set by writing to CP15 register 9 The replacement algorithm chooses a victim cache line in the range base to 63 locking in the cache the lines with index in the range 0 to base 1 Data is loaded and locked into the DCache by first ensuring the data to be locked is not already in the cache This can be ensured by cleaning and flushing either the whole DCache or specific lines A short software routine can then be used to load the data into the DCache The software routine to load the data operates by writing to CP15 register 9 to force the replacement counter to a specific DCache line and then executing a load instruction to perform a cache lookup This will miss and a linefill will be performed bringing 8 words of data into the cache line specified by the replacement counter in the segment specified by bits 7 5 of the modified virtual address accessed by the load To load further lines into the cache the software routine can loop performing one load from each line to be loaded As each line contains 8 words each loop should add 32 bytes to the load address The software routine needs to move the victim counter to th
414. to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining In this case base write back should not be specified An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS ARM INSTRUCTION SET 53 2410 RISC MICROPROCESSOR EXAMPLES STR STR LDR LDR LDREQB STR PLACE ELECTRONICS R1 R2 R4 R1 R2 R4 R1 R2 416 R1 R2 R3 LSL 2 R1 R6 5 R1 PLACE Store R1 at R2 R4 both of which are registers and write back address to R2
415. tput pins The timer 0 has dead zone generator which is used with a large current device The timer 0 and 1 share an 8 bit prescaler while the timer 2 3 and 4 share other 8 bit prescaler Each timer has a clock divider which 5 different divided signals 1 2 1 4 1 8 1 16 and TCLK Each timer block receives its own clock signals from the clock divider which receives the clock from the corresponding 8 bit prescaler The 8 bit prescaler is programmable and divides the PCLK according to the loading value which is stored in TCFGO and TCFG1 registers The timer count buffer register TCNTBn has an initial value which is loaded into the down counter when the timer is enabled The timer compare buffer register TCMPBn has an initial value which is loaded into the compare register to be compared with the down counter value This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit down counter which is driven by the timer clock When the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation has been completed When the timer counter reaches zero the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation However if the timer stops for example by clearing the timer enable bit of TCONn during the timer running mode the value of TC
416. tted data is received to the receiver via RXD This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel This mode can be selected by setting the loopback bit in the UART control register UCONn Break Condition The break is defined as a continuous low level signal for one frame transmission time on the transmit data output ELECTRONICS 11 7 UART 53 2410 01 RISC MICROPROCESSOR Infra Red IR Mode The S3C2410X01 UART block supports infra red IR transmission and reception which can be selected by setting the Infra red mode bit in the UART line control register ULCONn Figure 11 3 illustrates how to implement the IR mode In IR transmit mode the transmit pulse comes out at a rate of 3 16 the normal serial transmit rate when the transmit data bit is zero In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value see the frame timing diagrams shown in Figure 11 6 and 11 7 Encoder Figure 11 4 IrDA Function Block Diagram 11 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART amp SIO Frame Start 4 Data Bits Stop 4 Bit Bit 0 1 0 1 0 0 1 1 0 1 Figure 11 5 Serial Frame Timing Diagram Normal UART lt IR Transmit Frame
417. ual address 20 19 Fabia ner L2 table index Translation table base 1413 Translation base ma 18 Translation base Table index Ts B Level one descriptor 12 11 emus DI ee ee Level two descriptor Physical address 31 10 9 0 Figure 3 9 Tiny Page Translation from a Fine Page Table 3 16 ELECTRONICS ARM920T PROCESSOR MMU SUB PAGES Access permissions can be defined for sub pages of small and large pages If during a page walk a small or large page has a non identical sub page permission only the sub page being accessed is written into the TLB For example a 16KB large page sub page entry will be written into the TLB if the sub page permission differs and a 64KB entry will be put in the TLB if the sub page permissions are identical When sub page permissions are used and the page entry then needs invalidating all four sub pages must be invalidated separately MMU FAULTS AND CPU ABORTS The MMU generates an abort on the following types of faults e alignment faults data accesses only e translation faults e domain faults permission faults In addition an external abort may be raised by the external system as a result of certain types of external data access Alignment fault checking is enabled by the A bit in CP15 register 1 Alignment fault checking is not affected by whether or not the MMU is enabled Translation domain and permission faults are only generated
418. ublishing we will show the revision with a proper version number ELECTRONICS 11 1 UART BLOCK DIAGRAM Peripheral BUS Transmitter 53 2410 01 RISC MICROPROCESSOR Transmit Buffer Register 16 Byte Transmit Shifter Transmit FIFO Register FIFO mode Transmit Holding Register Non FIFO mode Control E Buad rate Unit Generator Receiver Receive Shifter lt Receive Buffer Register 16 Byte Receive Holding Register Non FIFO mode only Receive FIFO Register FIFO mode In FIFO mode all 16 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register Figure 11 1 UART Block Diagram with FIFO ELECTRONICS 53 2410 01 RISC MICROPROCESSOR UART UART OPERATION The following sections describe the UART operations that include data transmission data reception interrupt generation baud rate generation Loopback mode Infra red mode and auto flow control Data Transmission The data frame for transmission is programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits which can be specified by the line control register ULCONn The transmitter can also produce the break condition which forces the serial output to logic 0 state for one frame transmission time This block transmits break signals a
419. ubset of the ARM state set The programmer has direct access to eight general registers RO R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked Stack Pointers Link Registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State General Registers and Program Counter System amp User FIQ Supervisor Abort Undefined THUMB State Program Status Registers banked register Figure 2 4 Register Organization in THUMB state ELECTRONICS 2 5 PROGRAMMER S MODEL 53 2410 RISC MICROPROCESSOR The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way e THUMB state RO R7 and ARM state RO R7 are identical e THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 e THUMB state LR maps onto ARM state R14 e The THUMB state Program Counter maps onto the ARM state Program Counter R15 This relationship is shown in Figure 2 5 THUMB state ARM state 2 2 2 o Hi registers Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 ELECTRONICS 53 2410 RISC MICROPROCESSOR PROGRAMMER S MODEL Accessing Hi Registers in THUMB State In THUMB state registers R8 R15 the Hi registers are not part of the standard register set Howev
420. ue or register contents to be transferred to the condition code flags N Z C and V of CPSR or SPSR lt mode gt without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RESTRICTIONS e n user mode the control bits of the CPSR are protected from change so only the condition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed e Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state The SPSR register which is accessed depends on the mode at the time of execution For example only SPSR is accessible when the processor is in mode e You must not specify R15 as the source or destination register e Also do not attempt to access an SPSR in User mode since no such register exists 3 18 ELECTRONICS S3C2410X RISC MICROPROCESSOR ARM INSTRUCTION SET MRS transfer PSR contents to a register 31 28 27 23 22 21 16 15 12 11 00010 000000000000 15 12 Destination Register 22 Source PSR 0 CPSR 1 SPSR_ lt current mode gt 31 28 Condition Field MSR transfer register contents to PSR 31 28 27 23 22 21 12 11 4 Pd wm 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR ocurrent mode 31 28 Condition Fi
421. uested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 53 2410 01 RISC MICROPROCESSOR I O PORTS General Status Register GSTATUSn GSTATUSO 0 560000 GSTATUS1 0x560000B0 External pin status Undefined Chip ID 0x32410000 GSTATUSS 0x560000B8 GSTATUS4 0x560000BC 0 1 Infrom register Infrom register mi nBATT FLT 0 Status of nBATT FLT pin CHIP ID 81 0 ID register 0x32410000 PWRST 0 Power on reset if this bit is set to 1 The setting is cleared by writing 1 to this bit OFFRST 1 Power OFF reset The reset after the wakeup from Power OFF mode The setting is cleared by writing 1 to this bit WDTRST 2 Watchdog reset The reset derived from Watchdog timer The setting is cleared by writing 1 to this bit inform 31 0 Infrom register This regiser is cleard by power on reset Otherwise preserve data value inform 31 0 Infrom register This regiser is cleard by power on reset Otherwise preserve data value ELECTRONICS 9 29 I O PORTS 9 30 NOTES 3C2410X01 RISC MICROPROCESSOR ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER 05 25 2002 PWM TIMER Preliminary OVERVIEW The 53 2410 01 has five 16 bit timers Timer 0 1 2 and 3 have Pulse Width Modulation PWM function Timer 4 has an internal timer only with no ou
422. uested when LCD FIFO reaches trigger level LCD Source Pending Register LCDSRCPND 0X4D000058 Indicate the LCD interrupt source pending register INT FrSyn 1 LCD frame synchronized interrupt source pending bit 0 0 The interrupt has not been requested 1 The frame has asserted the interrupt request INT FiOnt 0 LCD FIFO interrupt source pending bit 0 The interrupt has not been requested 1 2 LCD FIFO interrupt is requested when LCD FIFO reaches trigger level This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 15 37 LCD CONTROLLER 3C2410X01 RISC MICROPROCESSOR LCD Interrupt Mask Register Reset Value LCDINTMSK 0X4D00005C R W Determine which interrupt source is masked 0x3 The masked interrupt source will not be serviced FIWSEL 2 Determine the trigger level of LCD FIFO 0 4 words 1 8 words INT FrSyn 1 Mask LCD frame synchronized interrupt 0 The interrupt service is available 1 The interrupt service is masked INT FiOnt 0 Mask LCD FIFO interrupt 0 The interrupt service is available 1 The interrupt service is masked LPC3600 Control Register Register Address R W Description Reset Value LPCSEL 0X4D000060 This register controls the LPC3600 modes 0 4 CPV_SEL Same as the LPC3600 MODE SEL Same as the LPC3600
423. undefined value will be read GPDUP Bit Deseription GPD 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled GPD 15 12 are pull up disabled state at the initial condition ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS PORT E CONTROL REGISTERS GPECON GPEDAT and GPEUP Reserved Undeined GPE15 31 30 00 Input 01 Output open drain output 10 IICSDA 11 Reserved GPE14 29 28 00 Input 01 Output open drain output 10 IICSCL 11 Reserved GPE13 27 26 00 Input 01 Output 10 SPICLKO 11 Reserved GPE12 25 24 00 Input 01 Output 10 SPIMOSIO 11 Reserved GPE11 23 22 00 Input 01 Output 10 SPIMISOO 11 Reserved GPE10 21 20 00 Input 01 Output 10 SDDAT3 11 Reserved GPE9 19 18 00 Input 01 Output 10 SDDAT2 11 Reserved GPE8 17 16 00 Input 01 Output 10 SDDAT1 11 Reserved GPE7 15 14 00 Input 01 Output 10 SDDATO 11 Reserved 13 12 00 Input 01 Output 10 SDCMD 11 Reserved GPE5 11 10 00 Input 01 Output 10 SDCLK 11 Reserved 4 9 8 00 Input 01 Output 10 1285800 11 12550 7 6 00 Input 01 Output 10 12550 11 nSS0 GPE2 5 4 00 Input 01 Output 10 CDCLK 11 Reserved GPE1 3 2 00 10 00 10 Input 01 Output 28SCLK 11 Reserved Input 01 O
424. upport a multi master IIC bus serial interface A dedicated serial data line SDA and a serial clock line SCL carry information between bus masters and peripheral devices which are connected to the IIC bus The SDA and SCL lines are bi directional In multi master IIC bus mode multiple S3C2410X01 RISC microprocessors can receive or transmit serial data to or from slave devices The master S3C2410X01 can initiate and terminate data transfer over the IIC bus IIC bus in the S3C2410X01 uses Standard bus arbitration procedure To control multi master IIC bus operations values must be written to the following registers Multi master IIC bus control register IICCON Multi master IIC bus control status register IICSTAT Multi master Tx Rx data shift register IICDS Multi master IIC bus address register IICADD When the IIC bus is free the SDA and SCL lines should be both at High level A High to Low transition of SDA can initiate a Start condition A Low to High transition of SDA can initiate a Stop condition while SCL remains steady at High Level The Start and Stop conditions can always be generated by the master devices A 7 bit address value in the first data byte which is put onto the bus after the Start condition has been initiated can determine the slave device which the bus master device has selected The 8 bit determines the direction of the transfer read or write Every data byte put onto the SDA
425. urce Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 4 6 Format 5 OPERATION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 4 6 NOTES In this group only CMP Op 01 sets the CPSR condition codes The action of H1 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used Table 4 6 Summary of Format 5 Instructions THUMB assembler ARM equivalent Action ADD Hs ADD Rd Hs Add a register in the range 8 15 to a register in the range 0 7 ADD Rs ADD Hd Rs Add a register in the range 0 7 to a register in the range 8 15 ADD Hd Hs ADD Hd Hs Add two registers in the range 8 15 Hs CMP Rd Hs Compare a register in the range 0 7 with a register in the range 8 15 Set the condition code flags on the result CMP Hd Rs CMP Hd Rs Compare a register in the range 8 15 with a register in the range 0 7 Set the condition code flags on the result ELECTRONICS 4 13 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR Table 4 6 Summary of Format 5 Instructions Continued CMP Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition
426. urrent atomic transfer ends If there is no current running atomic transfer DMA stops immediately The CURR TC CURR SRG and CURR DST will be 0 Note Due to possible current atomic transfer stop operation may take several cycles The finish of the operation i e actual stop time can be detected as soon as the channel on off bit DMASKTRIGn 1 is set to off This stop is actual stop ON_OFF 1 DMA channel on off bit 0 DMA channel is turned off DMA request to this channel is ignored DMA channel is turned on and the DMA request is handled This bit is automatically set to off if we set the DCONn 22 bit to no auto reload and or STOP bit of DMASKTRIGn to stop Note that when DCON 22 bit is no auto reload this bit becomes 0 when CURR reaches 0 If the STOP bit is 1 this bit becomes 0 as soon as the current atomic transfer is completed Note This bit should not be changed manually during DMA operations i e this has to be changed only by using DCON 22 or STOP bit SW TRIG 0 Trigger the DMA channel in S W request mode 1 it requests a DMA operation to this controller Note that this trigger gets effective after S W request mode has to be selected DCONn 23 and channel ON OFF bit has to be set to 1 channel on When DMA operation starts this bit is cleared automatically Note You can freely change the values of DISRC register DIDST registers and TC field of DCON register Those changes t
427. urther permission checks TRANSLATION FAULT There are two types of translation fault section and page Section A section translation fault is generated if the level one descriptor is marked as invalid This happens if bits 1 0 of the descriptor are both O Page A page translation fault is generated if the level one descriptor is marked as invalid This happens if bits 1 0 of the descriptor are both 0 DOMAIN FAULT There are two types of domain fault section and page In both cases the level one descriptor holds the 4 bit domain field which selects one of the 16 2 bit domains in the domain access control register The two bits of the specified domain are then checked for access permissions as detailed in Table 3 6 on page 3 20 In the case of a section the domain is checked once the level one descriptor is returned and in the case of a page the domain is checked once the level one descriptor is returned If the specified access is either no access 00 or reserved 10 then either a section domain fault or page domain fault occurs 3 22 ELECTRONICS ARM920T PROCESSOR MMU PERMISSION FAULT If the 2 bit domain field returns 01 client then access permissions are checked as follows Section If the level one descriptor defines a section mapped access the AP bits of the descriptor define whether or not the access is allowed according to Table 3 6 on page 3 20 Their interpretation is dependent upon the setting of the S and R bits co
428. us RO Interrupt request source offset Sub source pending Interrupt sub mask xm ELECTRONICS 1 25 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued Register Address Address Read Function Name B Endian L Endian Write IT DIDSTC1 0x4B00004C DMA 1 Initial Destination Control DMASKTRIG1 0x4B000060 R W DMA 1 Mask Trigger DCON2 0x4B000090 DMA 2 Control DCSRC2 0x4B000098 DMA 2 Current Source DCDST2 0x4B00009C DMA 2 Current Destination DMASKTRIG2 0x4B0000A0 DMA 2 Mask Trigger DSTAT2 0x4B000094 DMA 2 Count 1 26 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 3 S3C2410 Special Registers Continued Register Address Address Read Function Name FETT Endian L Endian Write DMA DMA Coninued lt lt lt R W DMA 3 Initial DMA 3 Initial Source DMA 3 Initial Source Initial 3 Initial Source Control DMA 3 Initial Destination EE Initial Destination DMA 3 Initial Destination DMA 3 Initial Destination Control DMA 3 DMA3Count DMA 3 Current Source DMA 3 Current Destination 3 Current Destination Destination DMA 3 Mask Trigger ELECTRONICS 1 27 PRODUCT OVERVIEW 53 2410 01 RISC MICROPROCESSOR Table 1 3 S3C2410 Special Registers Continued Register Address Address Read Name B Endian L Endian Write Clock a
429. used to access the TTB MRC p15 0 Rd c2 c0 0 read TTB register MCR p15 0 Rd c2 c0 0 write TTB register 2 12 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 3 DOMAIN ACCESS CONTROL REGISTER Register 3 is the read write domain access control register consisting of sixteen 2 bit fields Each of these 2 bit fields defines the access permissions for the domains shown in Table 2 13 Table 2 13 Register 3 Domain Access Control D9 19 18 D2 1 3 2 D 6 The encoding of the two bit domain access permission field is given in Table 3 5 on page 3 19 The following instructions can be used to access the domain access control register MRC p15 0 Rd c3 c0 0 read domain 15 0 access permissions MCR p15 0 Rd 0 write domain 15 0 access permissions ELECTRONICS 2 13 PROGRAMMER S MODEL ARM920T PROCESSOR REGISTER 4 RESERVED Accessing reading or writing this register will cause unpredictable behavior REGISTER 5 FAULT STATUS REGISTERS Register 5 is the fault status register FSR The FSR contains the source of the last data fault indicating the domain and type of access being attempted when the data abort occurred Table 2 14 Fault Status Register 31 9 UNP when read SBZ for write ss Owhen read SBZ for write Domain being accessed when fault occurred 015 00 Fault type The fault type encoding is shown in Fault address and fault status registers on page
430. ut the reload value for the next timer duration The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0 The value written into the is loaded to the TCNTn only when the TCNTn reaches 0 and auto reload is enabled If the TCNTn becomes 0 and the auto reload bit is 0 the TCNTn does not operate any further Write Write TCNTBn 100 TCNTBn 200 Start 150 Auto reload tM lt 4 0 _t_ 150 100 Interrupt Figure 10 3 Example of Double Buffering Function 10 4 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0 So a starting value of the TCNTn has to be defined by the user in advance In this case the starting value has to be loaded by the manual update bit The following steps describe how to start a timer 1 Write the initial value into TCNTBn and TCMPBn 2 Set the manual update bit of the corresponding timer It is recommended that you configure the inverter on off bit whether use inverter or not 3 Set start bit of the corresponding timer to start the timer and clear the manual update bit If the timer is stopped by force the TCNTn retains the counter value and is not reloaded from TCNTBn If a new value has to be set perform manual update NOTE Whenever TOUT inverter o
431. utput 2SLRCK 11 Reserved ELECTRONICS 9 15 PORTS 53 2410 01 RISC MICROPROCESSOR GPE 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as a functional pin undefined value will be read GPE 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled 9 16 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR I O PORTS PORT F CONTROL REGISTERS GPFCON GPFDAT and GPFPU If GPFO GPF7 will be used for wakeup signals in Power OFF mode the ports will be set in Interrupt mode Reserved Undetned GPF7 15 14 Input 01 Output EINT7 11 Reserved GPF6 13 12 Input 01 Output inc EINT6 11 Reserved GPF5 11 10 Input 01 Output e EINT5 11 Reserved GPF4 Input 01 Output EINT4 11 Reserved GPF3 7 6 Input 01 Output 11 Reserved GPF2 5 4 Input 01 Output EINT2 11 Reserved GPF1 3 2 Input 01 Output Tm EINT1 11 Reserved GPFO 1 0 Input 01 Output EINTO 11 Reserved NOTE 0 7 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as out
432. vailable 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked INTRO 0 Service available 1 Masked ELECTRONICS 14 17 INTERRUPT CONTROLLER 3C2410X RISC MICROPROCESSOR NOTES 14 18 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR LCD CONTROLLER 05 20 2002 LCD CONTROLLER PRELIMINARY OVERVIEW The LCD controller in the S3C2410X01 consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver The LCD controller supports monochrome 2 bit per pixel 4 level gray scale or 4 bit per pixel 16 level gray scale mode on a monochrome LCD using a time based dithering algorithm and Frame Rate Control FRC method and it can be interfaced with a color LCD panel at 8 bit per pixel 256 level color and 12 bit per pixel 4096 level color for interfacing with STN LCD It can support 1 bit per pixel 2 bit per pixel 4 bit per pixel and 8 bit per pixel for interfacing with the palettized TFT color LCD panel and 16 bit per pixel and 24 bit per pixel for non palettized true color display The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate FEATURES STN LCD displays Supports 3
433. version 1 0 64 Bytes FIFO for Tx Rx DMA based or Interrupt based operation Compatible with Multimedia Card Protocol version 2 11 SPI Interface Compatible with 2 ch Serial Peripheral Interface Protocol version 2 11 2x8 bits Shift register for Tx Rx DMA based or interrupt based operation ELECTRONICS 1 5 PRODUCT OVERVIEW Operating Voltage Range Core 1 8V Memory 1 8 2 5 3 3V 1 0 3 3V Operating Frequency Up to 200 MHz Package 272 FBGA 1 6 53 2410 01 RISC MICROPROCESSOR ELECTRONICS 53 2410 01 RISC MICROPROCESSOR Block Diagram ARM920T IV2A 31 IPA 31 0 Instruction CACHE 6KB ARMO9TDMI Processor core Internal Embedded ICE DD 31 0 DVA 31 0 DV2A 81 Meri res 3 Data CACHE 16KB DPA 31 0 PRODUCT OVERVIEW External Coproc Interface EE EE PA Tag RAM LCD LCD CONT DMA BUS CONT Arbitor Decode USB Host CONT gt ExtMaster gt NAND Flash Boot Loader Interrupt CONT Power Management gt Memory CONT SRAM NOR SDRAM Clock Generator Bridge amp DMA 4Ch oe P EN 22 gt ko USB Device SDI MMC ELECTRONICS lt 12C ala ADC Timer PWM 0 3 4 Internal 1 7 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW
434. wer consumption in slow mode If the PLL is turned off in any other mode MCU operation is not guaranteed When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on then SLOW BIT should be clear to move to another state after PLL stabilization Pull up Resistors on the Data Bus and Power OFF Mode In Power OFF mode the data bus D 31 0 or D 15 0 is in Hi z state But because of the characteristics of I O pad the data bus pull up resistors have to be turned on for low power consumption in Power OFF mode D 31 0 pin pull up resistors can be controlled by the GPIO control register MISCCR However if there is a external bus holder such as 74LVCH162245 on the data bus turning off the data bus pull up resistors will be reduce power consumption ELECTRONICS 7 15 CLOCK amp POWER MANAGEMENT 53 2410 01 RISC MICROPROCESSOR Output Port State and Power_OFF Mode If output is L the current will be consumed through the internal parasitic resistance if the output is H the current will not be consumed For an output port the current consumption can be reduced if the output state is H It is recommended that the output ports be in H state to reduce current consumption in Power_OFF mode Battery Fault Signal nBAT_FLT There are two functions in nBAT_FLT pin as follows When CPU is not in Power OFF mode nBAT FLT pin will cause the interrupt request The interrupt attribute of the nBAT
435. xpression cond Two character condition mnemonic Table 3 2 lt expression gt Evaluated and placed in the comment field which is ignored by ARM920T Examples SWI ReadC Get next character from read stream SWI Writel k Output a to the write stream SWINE 0 Conditionally call supervisor with 0 in comment field Supervisor code The previous examples assume that suitable supervisor code exists for instance 0x08 B Supervisor SWI entry point EntryTable Addresses of supervisor routines DCD ZeroRtn DCD ReadCRtn DCD WritelRtn Zero EQU 0 ReadC EQU 256 Writel EQU 512 Supervisor SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13_svc points to a suitable stack STMFD R13 RO R2 R14 Save work registers and return address LDR RO R14 4 Get SWI instruction BIC RO RO 0xFFO00000 Clear top 8 bits MOV R1 RO LSR 8 Get routine offset ADR R2 EntryTable Get start address of entry table LDR R15 R2 R1 LSL 2 Branch to appropriate routine WritelRtn Enter with character in RO bits 0 7 LDMFD R13 RO R2 R15 Restore workspace and return restoring processor mode and flags 3 50 ELECTRONICS 53 2410 RISC MICROPROCESSOR ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 25 This class of instruction is
436. y When ON 3 2 01b EXTCLK is used for UPLL CLK source only If it isn t used it has to be H 3 3V Al Crystal Input for internal osc circuit When ON 3 2 006 is used for MPLL CLK source and UPLL CLK source When ON 3 2 01b XTIpll is used for MPLL CLK source only When OM 3 2 10b is used for UPLL CLK source only If it isn t used has to be 3 3V XTOpll AO Crystal Output for internal osc circuit When OM 3 2 00b is used for MPLL CLK source and UPLL CLK source When ON 3 2 01b XTIpll is used for MPLL CLK source only When ON 3 2 10b is used for UPLL CLK source only If it isn t used it has to be a floating pin 1 22 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1 2 S3C2410 Signal Descriptions Continued signal o Deseipon Reset Clock amp Power continued CLKOUT 1 0 Clock output signal The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK UPLL CLK FOLK HCLK PCLK VDDalive S3C2410 reset block and port status register VDD 1 8V It should be always supplied whether in normal mode or in power off mode VDDi VDDiarm P 53 2410 core logic VDD 1 8V for CPU VSSiVSSiarm P 3 2410 core logic VSS VDDi MPLL P 8382410 MPLL analog and digital VDD 1 8 V VSSi MPLL P 53 2410 MPLL analog and digital VSS VDDOP P 53 2410 port VDD 3 3V VDDMOP S3C2410 Memory I O
437. y applying a slow clock and excluding the power consumption from the PLL The is the frequency of divide by n of the input clock or EXTCLK without PLL The divider ratio is determined by SLOW VAL in the CLKSLOW control register and CLKDIVN control register Table 7 3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock SLOW VAL FCLK HCLK PCLK UCLK 1 1 Option 1 2 Option 1 1 Option 1 2 Option HDIVN 0 HDIVN 1 PDIVN O PDIVN 1 EXTCLK or EXTCLK or EXTCLK or HCLK HCLK 2 48Mhz XTIpll 1 XTIpll 1 2 00 1 EXTCLK or EXTCLK or EXTCLK or HCLK HCLK 2 48Mhz XTlpll 2 2 XTIpll 4 010 EXTCLK or EXTCLK or EXTCLK or HCLK HCLK 2 48Mhz XTIpll 4 XTIpll 4 8 XTlpll 6 XTlpll 6 XTlpll 12 XTlpll 8 XTlpll 8 16 XTlpll 10 XTlpll 10 XTlpll 20 XTlpll 12 XTlpll 12 XTlpll 24 XTlpll 14 XTlpll 14 XTlpll 28 In SLOW mode PLL will be turned off to reduce the PLL power consumption When the PLL is turned off in the SLOW mode and the user changes power mode from SLOW mode to NORMAL mode the PLL needs clock stabilization time PLL lock time This PLL stabilization time is automatically inserted by the internal logic with lock time count register The PLL stability time will take 150us after the PLL is turned on During PLL lock time the FCLK becomes SLOW clock Users can change the frequency by enabling SLOW mode bit in CLKSLOW r
438. y bank is enabled the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active nWAIT is checked from tacc 1 nOE will be deasserted at the next clock after sampling nWAIT is high The nWE signal have the same relation with nOE Figure 5 2 63 2410 01 External nWAIT Timing Diagram Tacc 4 ELECTRONICS 5 5 MEMORY CONTROLLER S3C2410X01 RISC MICROPROCESSOR nXBREQ nXBACK Pin Operation If NXBREQ is asserted the S3C2410X01 will respond by lowering nXBACK If nXBACK L address data bus and memory control signals are in Hi Z state as shown in Table 1 1 When nXBREQ is de asserted the nXBACK will also be de asserted SCLK SCKE A 24 0 D 31 0 nGCS nOE nWE nWBE nXBREQ nXBACK Figure 5 3 S3C2410X01 nXBREQ nXBACK Timing Diagram 5 6 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER ROM Memory Interface Examples nWBEO A10 nOE A11 nGCSn 12 A13 A14 A15 A16 Figure 5 5 Memory Interface with 8 bit ROM x 2 ELECTRONICS 5 7 MEMORY CONTROLLER 3C2410X01 RISC MICROPROCESSOR Figure 5 7 Memory Interface with 16 bit ROM 5 8 ELECTRONICS 53 2410 01 RISC MICROPROCESSOR MEMORY CONTROLLER SRAM Memory Interface Examples Figure 5 9 Memory Interface with 16 bit SRAM x 2 ELECTRONICS 5 9
439. y zero Get abs value of R1 by xoring with OXFFFFFFFF and adding 1 if negative ASR RO R1 31 Get 0 or 1 in depending on sign of R1 EOR R1 RO EOR with 1 OxFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value signs 0 or 1 RO amp R2 for later use in determining sign of quotient amp remainder PUSH RO R2 Justification shift 1 bit at a time until divisor RO value is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes LSR RO R1 1 MOV R2 R3 B FTO just LSL R2 1 0 CMP R2 RO BLS just MOV RO 40 Set accumulator to 0 B FTO Branch into division loop div_ LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 If successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 Terminate when R2 R3 ie we have just BNE div_ tested subtracting the ones value ELECTRONICS 4 41 THUMB INSTRUCTION SET 53 2410 RISC MICROPROCESSOR Now fix up the signs of the quotient RO and remainder R1 POP EOR EOR SUB EOR SUB MOV ARM Code signed_divide ANDS sip bit 31 sign of result RSBMI EORS bit 30 sign of a2 RSBCS R2 R3 R3 R2 RO R3 RO R3 R1 R2 R1 R2 Ir a4 a1 amp 80000000 a1 a1 0 ip a4 a2 ASR 32 a2 a2 0 Get dividend divisor signs back Result sign Negate if result sign
440. you only want to receive data you should transmit dummy OxFF data Clock Phase 2 one of two fundamentally different transfer formats 22 6 ELECTRONICS S3C2410X01 RISC MICROPROCESSOR SPI INTERFACE 05 20 2002 SPI STATUS REGISTER Reset Value SPSTAO 0x59000004 R SPI channel 0 status register SPSTA1 0x59000024 SPI channel 1 status register SPSTAn Bi miasme m Data Collision This flag is set if the SPTDATn is written or the SPRDATn is read Error Flag DCOL while a transfer is in progress and cleared by reading the SPSTAn 0 not detect 1 collision error detect 1 Multi Master Error This flag is set if the nSS signal goes to active low while the SPI is Flag MULF configured as a master and SPPINn s ENMUL bit is multi master errors detect mode MULF is cleared by reading SPSTAn 0 not detect 1 multi master error detect Transfer Ready 0 This bit indicates that SPTDATn or SPRDATn is ready to transmit Flag REDY or receive This flag is automatically cleared by writing data to SPTDATn 0 not ready 1 data Tx Rx ready This document is a preliminary user s manual So our company will present its revision as of the date on the page header After formal publishing we will show the revision with a proper version number ELECTRONICS 22 7 SPI INTERFACE 3C2410X01 RISC MICROPROCESSOR SPI PIN CONTROL REGISTER When the SPI system is enabled the direction of pins except nS

ARM 920T-um_s3c2410x 3832 KB

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