PQ7_DesignGuide_rev 2 0
Contents
1. 3 gt gt 0 mr o ang 16 No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 6 2 PCI Express Link Topology 2 Carrier Board Qseven Module 4 k Transmitter and Package Card Device A TX Path AC Coupling Capacitors AC Coupling Capacitors RX Path TX Path a P A ar P a ay a m an 40 39UU07 PAEDSsaidx3 pie ui ppy sseidx3 Did Receiver and Package 1O19UU0J puez afp3 uaaaso 1 N Table 6 3 Carrier Board PCI Express Insertion Loss Budget Segment Loss Budget Value Max Trace Length Comments at 1 25 GHz dB Carrier Board Topology 1 5 5dB 14 5 inches Carrier Board with onboard PCI Express TX path device Carrier Board Topology 1 5 9dB 15 7 inches Carrier Board with onboard PCI Express RX path device Carrier Board Topology 2 4 1dB 7 7 inches Carrier Board with PCI Express TX path Connector for Add In Card or ExpressCard Carrier Board Topology 2 4 1dB 7 7 inches Carrier Board with PCI Express RX path Connector for Add In Card or ExpressCard The trace lengths presented in Table are based on the following assumptions e Typical damping of the PCB trace of 0 35dB inch 1 25GHz common value for FR 4 based material e The RX path budget includes the additional damping of the DC decoupling capacitors and 2 additional vias for connecting the decoupling capa2. Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7 731 9888 http www portwell com tw 16 2 Features 16 2 1 eMMC Interface Features eMMC 4 5 controller supported e Transfers the data in 1 bit 4 bit and 8 bit modes Transfers data in the following speed classes Baseline 1 4 8 bit up to 25Mhz HS SDR DDR 4 8 bit up to SOMhz and HS200 4 8 bit up to 200MHz 4 5 controller only Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity e Supports MMC Plus and MMC mobile e Supports both round robin and priority based arbitration for transmit operation Run time configurabilty of channel ID bits Table 184 eMMC Signals o eMMC Clock V1P8S The frequency may vary between 26 and 52 MHz Vo eMMC Port Data bits 0 to 7 V1P8S Bidirectional port used to transfer data to and from eMMC device By default after power up or reset only DIO is used for data transfer A wider data bus can be configured for data transfer using either D 0 D 3 or D 0 D 7 by the MultiMedia Card controller The MUltiMedia Card includes internal pull ups for data lines D 1 D 7 Immediately after entering the 4 bit mode the card disconnects the internal pull ups of lines D 1 D 2 and D 3 Correspondingly immediately after entering to the 8 bit mode the card disconnects the internal pull ups of lines D 1 D 7 Vo eMMC Port Command V1P8S This signal
3. SPLMSO 202 SPLLCS4 203 SPISCK_ 204 MFGNC4 VCC 5V SB MFG NC2 VCC VCC VCC VCC VCC VCC Note Please refer to PQ7 series modules user manual for detail information 12 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw D QSEVEN fe ak Board Design 5 1 PCB Design Rules The PO7 series Specification provides a rich set of modern high speed differential serial interfaces Designing PO7 series Carrier Boards must be followed the certain design rules The most important design rule is route high speed serial interfaces as differential pairs The two lines in the pair must be length matched and should have uniform edge to edge spacing They should have a minimum of layer changes If they do change layers both lines in the pair should change The preferred reference plane for the high speed pairs is a single continuous GND plane If the differential pair is referenced to a power plane avoid routing the pair across a power plane split 5 2 Trace Impedance Considerations Most high speed interfaces used in a Qseven design for a Carrier Board are differential pairs that need a well defined and consistent differential and single ended impedance he differential pairs should be edge coupled There are two basic structures used for high speed differential and single ended signals The first is micr
4. This specification suggests two connector heights 7 8mm and 7 5mm Figure 2 1 MXM connector 68 12 2 682 61 50 2 421 2 008 3 002 118 043 LALA AA ANANA AA AA ed KOR A AA EVER MOR EDEL FU 01 6 Pos NO 1 3 50 a5 A SQ i t 020 POS NO 229 51 00 014 2 008 CONN DUTLINE The connectors mentioned in Table 2 1 are only a partial list of what is offered by the manufacturers Table 2 1 MXM Connector Manufacturer Part Number Specification Resulting height Overall height of between carrier board the MXM Connector and Oseven module Aces 88882 2Dxx 88882 2Dxx 5 0mm 7 5mm Yamaichi BEC05230S9xFREDC BECO5230S9xFREDC 5 0mm 7 8mm Foxconn AS0B32x S78N xH AS0B32x S78N xH 5 0 mm 7 8 mm The components located on the top side of the module are up to 5 5mm high The bottom components have a maximum height of 2 5mm while the standard distance between the standard MXM connector on the carrier board and the PO7 series module is 2 7mm When using the standard MXM connector with an overall height of 5 5mm carrier board component placement below the PQ7 series module is not permitted Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www_portwell com tw If it is necessary to place carrier board components below the PQ7 series module then a MXM connector with an overall height of 7 8mm must be used and no carrier b
5. USB_SSRX1 s5 USB 23 0cH se USBOTOCK 6 5 SDIO Interface Signals SDIO stands for Secure Digital Input Output Devices that support SDIO can use small devices such as SD Card or MMC Card flash memories Table 6 11 Signal Definition SDIO Description VO Type lou lu SDIO CD SDIO Card Detect This signal indicates when a SDIO MMC CMOS 3 3V VO card is present SDIO CLK SDIO Clock With each cycle of this signal a one bit transfer CMOS 3 3V O on the command and each data line occurs This signal has maximum frequency of 48 MHz SDIO_CMD SDIO Command Response This signal is used for card CMOS 3 3V VO initialization and for command transfers During initialization OD PP mode this signal is open drain During command transfer this signal is in push pull mode SDIO_LED SDIO LED Used to drive an external LED to indicate when CMOS 3 3V maximA O transfers occur on the bus SDIO_WP SDIO Write Protect This signal denotes the state of the CMOS 3 3V VO write protect tab on SD cards SDIO_PWR SDIO Power Enable This signal is used to enable the power CMOS 3 3V O being supplied to a SD MMC card device SDIO DATO 7 SDIO Data lines These signals operate in push pull mode CMOS 3 3V VO PP Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 30 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 2
6. Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www_portwell com tw reflections and affect signal quality Keep the length of high speed clock and periodic signal traces that run parallel to high speed signal lines at a minimum to avoid crosstalk Based on EMI testing experience the minimum suggested spacing to clock signals is 50mil Use a minimum of 20mil spacing between the differential signal pairs and other signal traces for optimal signal quality This helps to prevent crosstalk Route all traces over continuous planes VCC or GND with no interruptions Avoid crossing over anti etch if at all possible Crossing over anti etch split planes increases inductance and radiation levels by forcing a greater loop area 94 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 8 1 Symmetrical and Non Symmetrical Routing Avoid Non symmetrical Routing Preferred Symmetrical Routing A an Figure 8 2 Trace Edge to Reference Plane Guidance VCC plating Signal Traces GND reference plane Layer 3 Layer 1 Layer 3 Trace Edge to Plane Edge Minimum Distance 95 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw e When trace length matching occurs the matching should be made as
7. The reference voltage is determined by the requirements of the module s PHY and may be as low as OV and as high as 3 3V The reference voltage output shouldbe current limited on the module In a case in which the reference is shorted to ground the current must be limited to 250mA or less GBE_LINK Ethernet controller 0 link indicator active low aa 3 3V max 10 mA O GBE LINK100 Ethernet controller 0 100Mbit sec link indicator active low EE 3 3V max 10 mA O GBE_LINK1000 Ethernet controller 0 1000Mbit sec link indicator active low Ga 3 3V max 10 mA O GBE ACTH Ethernet controller O activity indicator active low ee 3 3V max 10 mA O 21 No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7 731 9888 http www portwell com tw 6 2 1 Gigabit Ethernet Insertion Loss Budget Figure 6 3 Gigabit Ethernet Link Topology 10 39UU07 pie a6p3 uaaaso SNSUBEN 12U13U13 LAN Cable Table 6 5 Signal Definition Ethernet Segment La Ls Le Lo Total Qseven Ethernet implementations should conform to insertion loss values less than or equal to those shown in Table above The insertion loss values shown account for frequency dependent material losses only Cross talk losses are separate from material losses in the Gigabit Ethernet specification Device Down implementations in which the Ethernet target device is implemented on the carrier board for instance an Ethernet swi
8. USB 2 3 OCH USB 4 5 OCR and USB 6 7 OCR are used to flag a USB over current situation Carrier Board USB current monitors may may pull these lines to GND with open drain drivers to indicate that the monitor s current limit has been exceeded Do not pull up these lines to 3 3V on the Carrier Board These pins are already pull high to VSB3 at PO series Carrier Boards that supply power to external USB devices over a USB cable should implement current limiting hardware and should drive the appropriate over current line If the USB target device is on the Carrier Board then it is not necessary to implement the current limiting and to drive the over current line for that port The over current line may be left open Route USB signals as differential pairs with a 850 differential impedance and a 500 single ended impedance Ideally a USB pair is routed on a single layer adjacent to a ground plane USB pairs should not cross plane split Keep layer transitions to a minimum If the differentialpair is referenced to a power plane avoid routing the pair across a power plane split and should be well bypassed 26 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http Table 6 9 Signal Definition USB www portwell com tw Description VO Type lo USB POT Universal Serial Bus Port 0 differential pair USB VO USB PO USB P1 Universal Serial Bus Port 1 diffe
9. ae GP2 I2C DAT eDPO_HPD 2 Sospo oar woseic par GP2 I2C CLK eDPO_HPD KANE ae XCANOTX 130 NOR S a 133 DP LANE3 TMDS CLK 134 RSVD _ _ 135 GND 136 6D TT 137 DP_LANE1 TMDS_LANE1 138 DPAAUC 139 DP LANE1 TMDS LANET 140 DPAUC 11 6ND 12 CC GND 143 DP LANE2 TMDS LANEO 144 RSVD TT 145 DP LANE2 TMDS LANEO 146 RSVD O 147 6MD _ Jl 18 6ND O 149 DP LANEO TMDS LANE2 150 HDMI CTRL DAT 151 DP LANEO TMDS LANE2 152 HDMI CTRL CLK 153 DP HOMIHPD 154 RSVD TU 155 PCIE CIK REF 156 _ PCIE WAKER 157 PCIE CLK REF 158 PCIE RST 159 CC GND 160 6ND 55 161 PCE3TX 42 PCIES_RX 163 PCIES TX _ 164 PCIE3_RX 165 6ND 166 OND 11 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7 731 8888 F 886 2 7731 9888 http www_portwell com tw Pin Signal Pin Signal 167 PCIE2 TX 168 POE2RXF 19 PCIE2 TX 170 POEZRX 179 POEOTX 180 PCIEO RX 181 PCIEOTDC 182 PCEORX O 183 GMD 184 GND 185 LPC_ADO GPIOO 186 LPC AD1 GPIO1 189 LPC CLK GPlO4 190 LPC FRAME GPIO5 191 SERIRQ GPIO6 192 LPC LDRO IGPIO7 SPKR R m p pum gure FAN_TACHOIN FAN_PWMOUT es Geter 19 ce Paw oori _ 197 8D 198 GND 199 SPLMOSI _ 200 SPLLCSO 201
10. an external circuitry le Input low current The I is the maximum input low current that must be provided to the Oseven module via external circuitry in order to guarantee a proper logic low level of the signal P Power Input NC Not Connected PCIE PCI Express differential pair signals In compliance with the PCI Express Base Specification 1 1 GB_LAN Gigabit Ethernet Media Dependent Interface differential pair signals In compliance with IEEE 802 3ab 1000Base T Gigabit Ethernet Specification USB Universal Serial Bus differential pair signals In compliance with the Universal Serial Bus Specification 2 0 SATA Serial Advanced Technology Attachment differential pair signals In compliance with the Serial ATA High Speed Serialized AT Attachment Specification 1 0a LVDS Low Voltage Differential Signaling differential pair signals In compliance with the LVDS Owner s Manual 4 0 TMDS Transition Minimized Differential Signaling differential pair signals In compliance with the Digital Visual Interface DVI Specification 1 0 CMOS Logic input or output 16 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 1 Pa Express Interface Signal According to the PCI Express Base Specification Revision 1 1 a total available interconnect loss budget of 13 2 dB is allowed between the PCI Express host device on the Qseven CPU module and the P
11. as Table 3 1 shows the minimum gt maximum and PO7 series configuration of the feature set Table 3 1 QSEVEN Supported Features PCI Express Oem e S USB20ports B Z a LVDS channels Dual Channel 24bits embadded High Definition Audio AC 97 UART JO k x Zx E O Secure Digital VO 8 bit for SD MMC BEER DE aaa CAN Bus JO ON O ower Buttoni PIE Y Reset Button JI NCS a EP EE EE Thermal control JO JO Note Please refer to PQ7 series modules user manual for detail information Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 4 Qseven Connector Pin out Figure 4 1 Connectors Pin out Description Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Pin Signal Pin Signal GBE MDI3 GBE_MDI3 GBE_LINK100 GBE LINK1000 GBE MDI1 GBE MDI1 GBE LINK GBE CTREF SUS STATE PWRBTN SLP_BTN LID BIN 23 GND HCN 25 6ND 26 PWGIN O 27 BATLOWH 28 RSTBTN 29 SATAO TX 30 SATAK 31 SATA0TX 32 SATALTK O 33 SATAACT 34 GND 35 SATAO RX 36 SATALRG 37 SATAORX 38 SATAT_RX O 39 6MD 4 GND BIOS_DISABLE BOOT_ALT 2 SDIO_CLK E SDIO CDY E NE SDIO LED SDIO CMD SDIO WP 47 SDIO PWRf SDIO DAT1 SDIO DAT
12. ede ee ee ee ee ee 37 Table 6 13 Signal Definition LVDS ccscecsscsceccscscetcecececcscnseccscsccccscsceccsceceess 40 Table 6 14 Signal Definition DisplayPort scscsccscscsscscsscscsceccscsccccscsccccscsccees 42 Table 6 15 Signal Definition HDMI ccscscsscsceccscsccccscsccccscsccccscsccccscsscccscsccess 44 Table 6 16 Signal Definition LPC sesse sesse see ee ee ee ee ee ee ee ee ee Gee ee ee ee 45 Table 6 17 Signal Definition CAN BUS osse ses esse sesse eek ee ee ee ee ee ee Ge ee Gee ee ee ee 45 Table 6 18 Signal Definition SPI c csccsceccscsceccccsccccscsccccscsccccscsccccsceseccscsceecs 46 Table 6 19 Signal Definition of UART cccsccscecsscsceccscsccccscsccccscsccccscsccccsceseess 46 Table 6 20 Signal Definition Input Power cscsccccsceccscsccccscsccccsceccccscececcsceceees 46 Table 6 21 Signal Definition Power Control sesse sesse sesde ee ee ee ee ee ee ee ee ee 47 Table 6 22 Signal Definition Power Management sis ses esse sesse ee ee ee Ge ee ee ee 47 Table 6 23 Signal Definition Miscellaneous siese sesse se sesse see ee ee ee ee ee ee Gee ee ee ee 48 Table 6 24 Signal Definition Manufacturing cccsccsccccscsccccscsccccscsccccscsceccscsceees 49 Table 6 25 Signal Definition Miscellaneous sees esse ses esse ee ee ee ee ee Ge ee ee ee ee ee 50 Table 6 26 Signal Definition Fan Control sesse sees ese see ee ee ee ee ee ee Gee ee ee ee 50 Table 7
13. fan tachometer input When not in use for this CMOS 3 3V IGP TIMER IN primary purpose it can be used as General Purpose Timer Input 50 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 1 Input Power Requirements PQ7 series modules are designed to be driven with a single 5V input power rail Additionally two optional power rails are specified by QSEVEN to provide a 5V standby voltage on the PO7 series module as well as a 3V Real Time Clock RTC supply voltage which is provided by a battery cell located on the carrier board If the carrier board does not require standby functionality then the 5V standby power rail can be omitted The same applies to the 3V RTC battery voltage If no RTC CMOS backup functionality is required by the system then the 3V RTC supply battery voltage can be omitted If the standby 5V power rail VCC 5V SB is not provided by the carrier board then the VCC_5V_SB pins pins 205 206 of the Oseven module must be connected with the main VCC power rail pins pins 211 230 Table 7 1 Input Power Characteristics Power Rail Nominal Input Input Range Max Input Ripple VCC 5V 4 75V 5 25V 50 mV VCC_5V_SB 5V 4 75V 5 25V 50 mV VCC RTC 3V 2 0V 3 3V 20 mV NOTE If the standby 5V power rail VCC 5V SB is not provided by the carrier board then all pins must be connected together wit
14. is used for card initialization and transfer of commands It has two modes open drain for initialization and push pull for fast command transfer eMMC RCOMP This signal is used for pre driver slew rate compensation o eMMC Reset Signals V1P8S Active low to reset 33 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Table 186 SD Card Signals Direction O SD Card Clock VSDIO The freguency may vary between 24 and 50 MHz 1 0 SD Card Data bits 0 to 3 VSDIO Bidirectional port used to transfer data to and from SD card By default after power up or reset only D 0 is used for data transfer A wider data bus can be configured for data transfer using D 0 D 3 1 0 SD Card Detect V1P8S Active low when a card is present Floating pulled high with internal PU when a card is not present SE VSDIO This signal is used for card initialization and transfer of commands It has two modes open drain for initialization and push pull for fast command transfer SD3 1PBEN O SD Card 1 8V Enable V1P8S Indicates the voltage of the SD Card to the power delivery subsystem The default voltage 3 3 V is requested when this signal is driven low 1 8 V is requested when this signal is high This voltage change applies to the SD3_V1P8V3P3_S3 VSDIO rail on the SoC SD3_RCOMP SD Card RCOMP This signal is used for pre driver slew rate c
15. of via transitions Maintain parallelism between SATA differential signals with the trace spacing needed to achieve same differential impedance Deviations will normally occur due to package breakout and routing to connector pins Ensure minimum deviations in length Table 6 6 Signal Definition SATA Description VO Type loh SATAO_RX Serial ATA channel 0 Receive Input differential pair SATA SATAO RX SATAO TX Serial ATA channel 0 Transmit Output differential pair SATA O SATAO TX SATA1 RX Serial ATA channel 1 Receive Input differential pair SATA SATA1_RX SATA1_TX Serial ATA channel 1 Transmit Output differential pair SATA O SATA1 TX SATA ACTH Serial ATA Led Open collector output pin driven during SATA OC 3 3V max TOMA O command activity 6 3 1 Serial ATA Insertion Loss Budget The Serial ATA source specification provides insertion loss figures only for the SATA cable Figure 6 4 Serial ATA Link Topology Serial ATA Link Topology Carrier Board Oseven Module Transmitter and Package 4 SATA Device B TX Path AC Coupling Capacitors 10122UU0 VIV TVIN3S 10129uUu0 gt VIV TVIN3S RX Path TX Path 10128uu03 pie aDp3 uanasH t iir Receiver and Package SATA Cable 24 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw SATA specification 3 1 defines the sig
16. request Support of the DisplayPort interface is chipset dependent and therefore may not be available on all Qseven modules The DisplayPort interface signals are shared with the signals for the TMDS interface The hot plug detect HPD output from DisplayPort sink device is a 3 3 V active high signal For example as below a logic invertion circuit is required on the motherboard since the input on the SOC is a 1 8 V active low signal 42 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 6 8 HPD Passgate Design Recommendation V1P8_S3 DP CONNECTOR 43 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 8 HDMI Interface Signals High Definition Multimedia Interface HDMI is a licensable compact audio video connector interface for transmitting uncompressed digital streams HDMI encodes the video data into TMDS for digital transmission and is backward compatible with the single link Digital Visual Interface DVI carrying digital video Both HDMI and DVI were pioneered by Silicon Image and are based on TMDS Silicon Image s powerful high speed serial link technology The HDMI specification requires the receiver to be terminated to AVCC nominally 3 3 V through Rt nominally 50 O The HDMI receiver requirements
17. these pins shall be left unconnected 45 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 11 spi interface Signals The Serial Peripheral Interface SPI is a 4 pin interface that provides a potentially lower cost alternative for system devices such as EEPROM and flash components Table 6 18 Signal Definition SPI Description VO Type lout SPI MOSI Master serial output Slave serial input signal SP serial output data CMOS 3 3V O from Qseven module to the SPI device SPI_MISO Master serial input Slave serial output signal SPI serial input data CMOS 3 3V from the SPI device to Oseven module SPI SCK SPI clock output CMOS 3 3V O SPI CSO SPI chip select 0 output CMOS 3 3V O SPI_CS1 SPI Chip Select 1 signal is used as the second chip select when two CMOS 3 3V O devices are used Do not use when only one SPI device is used 6 12 UART Interface Signals Table 6 19 Signal Definition of UART Signal Description VO Type lo fi VO UARTO TX Serial Data Transmitter CMOS 3 3V max1mA O UARTO RX Serial Data Reciever CMOS 3 3V gt 5mA UARTO_CTS Handshake signal ready to send data CMOS 3 3V gt 5mA UARTO_RTS Handshake signal ready to receive data CMOS 3 3V max 1mA O 6 13 Input power pin The PQ7 series operate entirely from 5 volt input power All other necessary voltages are generated on the PQ7 SERIES using onb
18. 1 Input Power Characteristics ccsccccscscscsccccccccscscnceccccccccscscscsceccecccecs 51 Table 7 2 Input Power Sequencing cscscecsecccscscsccccccccecscncsceccccecccscscscscescecececs 52 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 1 Qseven Specification PO7 series Specification defines requirements for highly integrated compact moduleswith standard I O interfaces and connections Key capabilities defined in the PQ7 specification include support for PCI Express Serial ATA USB 2 0 o USB 3 0 e DisplayPort TMDS e Secure Digital I O interface e LPC interface e Gigabit Ethernet e LVDS Display Interface e High Definition Digital Audio HDA e Intergrated Interchip Sound 12S PQ7 series have a standardized form factor of 70mm x 70mm and have specified pin outs based on the high soeed MXM system connector Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 2 Qsven Connector PQ7 series utilizes a 230 pin card edge connector The MXM connector accommodates various connector heights for different carrier board application needs
19. 2 PCI Express Link Topology 2 scscscsccscscscecsccccscscscsceccccccecscscscescececes 19 Figure 6 3 Gigabit Ethernet Link Topology ccssecscscscscsccccscscscsccccccccscscncecesecs 22 Figure 6 4 Serial ATA Link TOpOlogy cscscscsccccccccscscscscccsccccscscscececcccecscscscesesees 24 Figure 6 5 USB 2 0 Link TOpOlOgy ccsscscscscscsccccscscncsccccccccscncscececsccccscncssecesecs 28 Figure 6 6 SD and SDIO Protocol Interface Block Diagram 31 Figure 6 7 SD SDIO Protocol Clock DATA CMD Routing Topology 32 Figure 6 8 HPD Passgate Design RECOMMENATION ceccccccecscscecscescccscscscscerees 43 Figure 7 1 Input Power Sequencing SE aj ONE Fe z k Figure 8 1 Symmetrical and Non Symmetrical ROUtING csccscscsecscscsccscsceees 55 Figure 8 2 Trace Edge to Reference Plane Guidance sscscsscsccsccccsccsceccnceeens 55 Figure 8 3 Length Matching Example cccscscsccscscsccscscsccscscsccscnccccncsccscncsceees 56 Figure 8 4 Serpentining Example cscsccscscsccscsccccscsccccscsccccsceccccscecsscscnsoess 56 Figure 8 5 Acceptable Bends vs Tight Bends Example cscsccscscsecscscsecscsceees 57 Figure 8 6 Via Pair Placement WE sesse ses EE RE GR GE GR RE GE RE GR RE GR GE EE 57 Figure 8 7 Via Pair Placement esesseseseseecesescececescecesescecesesceceses
20. 38 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 6 6 SD and SDIO Protocol Interface Block Diagram SCH SD SDIO SD SDIO Protocol Device or 10kOhm to 39kOhm Card Command RAK Command so CMD WN Response CMD Write Daa 5D DATA 3 0 Meee DATA 2 0 NOTES 1 A 10 kO to 39 kO 5 pull up resistor to VCC is required for SD CMD 2 The Intel SCH has integrated the required pull up resistors on the DATA 3 0 signals 3 A 10 KO 5 pull up resistor to VCC is recommended for both SD CD and SD WP 31 No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 6 7 SD SDIO Protocol Clock DATA CMD Routing Topology Qseven Module Carrier Board NOTE SDIO signal include SD CLK SD CMD SD_DATA 3 0 Trace length at carrier side limit at 2 8 inch PQ7 M106 SDIO Design PO7 M106 IL Use SD card 3 0 Interface PO7 M106 IE Use SD card 3 0 Interface eMMC 4 5 Interface The Storage Control Cluster SCC consists of SDIO SD Card and eMMC controllers to support mass storage and IO devices e One eMMC 4 5 interface e One SD Card 3 0 interface e One SDIO 3 0 interface for SDIO based WIFI Note All units in the SCC support both PCI mode and ACPI mode of operation A level shifter may be needed on the platform for SDIO 3 0 compliance An eMMC 4 41 controller also exists but shouldn t be used 32
21. B USB Connector and Ferrite Loss Le 3 6 dB USB cable and far end connector loss per source specification Total 6 05 dB Qseven USB implementations should conform to insertion loss values less than or equal to those shown in Table 6 10 above The insertion loss values shown account for frequency dependent material losses only Cross talk losses are separate from material losses in the USB specification Device Down implementations in which the USB target device is implemented on the carrier board may add the ferrite and USB connector insertion loss values to the carrier board budget The carrier board insertion loss budget then becomes LC LD or 2 68 dB 28 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 4 2 USB 3 0 Clint PQ7 M106 IL ZR1 don t have USB 3 0 Clint Signal If want to use USB 3 0 Clint Signal need to modify schematic O seven Pin81 84 Table 16 139 USB 3 0 Interface Client Device Signals MEEL ET USB3DEV RXP N 0 Data In High speed serialized data inputs USB3DEV TXP N 0 Data Out High speed serialized data outputs USB3DEV REXT 0 I Resistor Compensation An external resistor 1 24K V1POA 1 Ohm must be connected between this pin and package ground z Jus 670C l JUSB4 SOGE n 81 USB P5 USB SSTXI 82 usa P4 USB SSRXI ___ 83 __ USB_P5 USB_SSTX1 84 __ USB_P4
22. C CLK GPO_I2C DAT SMB CLK GP1 i2C CLK SMB DAT GP1 I2C DAT SMB ALERT SPKR GP PWM OUT2 BIOS DISABLE IBOOT ALT RSVD GP 1 Wire Bus Description Watchdog trigger signal This signal restarts the watchdog timer of the Oseven module on the falling edge of a low active pulse Watchdog event indicator High active output used for signaling a missing watchdog trigger Will be deasserted by software system reset or a system power down General Purpose VC bus 0 clock line General Purpose VC bus 0 data line Clock line of System Management Bus Multiplexed with General Purpose I2C bus 1 clock line Data line of System Management Bus Multiplexed with General Purpose C bus 1 data line System Management Bus Alert input This signal may be driven low by SMB devices to signal an event on the SM Bus Primary functionality is output for audio enunciator the speaker in PC AT systems When not in use for this primary purpose it can be used as General Purpose PWM Output Module BIOS disable input signal Pull low to disable module s on board BIOS Allows off module BIOS implementations This signal can also be used to disable standard boot firmware flash device and enable an alternative boot firmware source for example a boot loader Do not connect General Purpose 1 Wire bus interface Can be used for consumer electronics control bus CEC of HDMI 48 VO Type CMOS 3 3V C
23. CI Express device on the carrier board ExpressCard or PCI Express add in card The specifications contained herein apply to all high speed signals of each interface width definition The signaling rate for encoded data is 2 5 Gigabit transfers s and the signaling is point to point PCI Express PCle signals are high speed differential pairs with a nominal 850 differential impedance Route them as differential pairs preferably referenced to a continuous GND plane with a minimum of via transitions Table 6 2 Signal Definition PCI Express Description VO Type lou lu PCIEO RX PCI Express channel 0 Receive Input differential pair PCIE PCIEO RX PCIEO TX PCI Express channel 0 Transmit Output differential pair PCIE O PCIEO TX PCIE1 RX PCI Express channel 1 Receive Input differential pair PCIE PCIE1 RX PCIE1_TX PCI Express channel 1 Transmit Output differential pair PCIE O PCIE1 TX PCIE2 RX PCI Express channel 2 Receive Input differential pair PCIE PCIE2 RX PCIE2 TX PCI Express channel 2 Transmit Output differential pair PCIE O PCIE2 TX PCIE3 RX PCI Express channel 3 Receive Input differential pair PCIE PCIE3 RX PCIE3 TX PCI Express channel 3 Transmit Output differential pair PCIE O PCIE3 TX PCIE CLK REF PCI Express Reference Clock for Lanes 0 to 3 PCIE O PCIE CLK REF PCIE WAKEf PCI Express Wake Event Sideband wake signal asserted by CMOS 3 3V 25mA components requesting wakeup Suspend PCIE RS
24. DS interface And maximum supported cable length is 7 inches 41 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 7 DisplayPort Interface Signals DisplayPort DP is an open industry standard digital display interface that is under development within the Video Electronics Standards Association VESA The DisplayPort specification defines a scalable digital display interface with optional audio and content protection capability It defines a license free royalty free state of the art digital audio video interconnect intended to be used primarily between a computer and its display monitor Route DP differential pairs with 850 differential impedance and 500 single end impedance Table 6 14 Signal Definition DisplayPort Shared With Description VO Type lovin WO DP LANE3 TMDS CLK DisplayPort differential pair lines lane 3 PCIE O DP LANE3 TMDS_CLK DP LANE2 TMDS LANEO DisplayPort differential pair lines lane 2 PCIE O DP LANE2 TMDS_LANEO DP_LANE1 TMDS LANE1 DisplayPort differential pair lines lane 1 PCIE O DP LANE1 TMDS_LANE1 DP_LANEO TMDS LANE2 DisplayPort differential pair lines lane 0 PCIE O DP_LANEO TMDS_LANE2 DP AUX Auxiliary channel used for link management and PCIE VO DP_AUX device control Differential pair lines DPHDMI_HPD Hot plug detection signal that serves as an CMOS 3 3V interrupt
25. MOS 3 3V CMOS 3 3V OD CMOS 3 3V OD CMOS 3 3V OD Suspend CMOS 3 3V OD Suspend CMOS 3 3V OD Suspend CMOS 3 3V CMOS 3 3V CMOS 3 3V 0 WO WO VO VO VO NC VO Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 17 Manufacturing Signals The MFG_NC 4 0 pins are reserved for manufacturing and debugging purposes It s recommended to route the signals to a connector on the carrier board The carrier board must not drive the MFG_NC pins or have pull up or pull down resistors implemented for these signals MFG NCI4 0 are defined to have a voltage level of 3 3V It must be ensured that the carrier board has the correct voltage levels for JTAG UART signals originating from the module For this reason a level shifting device may be required on the carrier board to guarantee that these voltage levels are correct in order to prevent damage to the module More information about implementing a carrier board multiplexer can be found in the Qseven Design Guide For more information about vendor specific functionality of MFG_NC 4 0 refer to the vendor s module documentation Table 6 24 Signal Definition Manufacturing Description VO Type borlu MFG_NCO This pin is reserved for manufacturing and debugging n a n a n a purposes May be used as JTAG TCK signal for boundary scan purposes durin
26. N port defines to support a 10 100 Megabits per second or Gigabit Ethernet The Module Specification specifies that LAN magnetics must reside on the Carrier Board not on the Module The LAN interface consists of four differential pair signals designated as GBE MDI0 thru GBE MDI3 Additionally there are four single ended signals that provide link status information along with a reference voltage for the magnetics center tap Route LAN differential pairs with 1000 differential impedance and 500 single end impedance Table 6 4 Signal Definition Ethernet Description VO Type loh GBE MDI0 Media Dependent Interface MDI differential pair 0 The MDI can GB LAN VO GBE MDI0 operate in 1000 100 and 10Mbit sec modes This signal pair is used for all modes GBE_MDI1 Media Dependent Interface MDI differential pair 1 The MDI can GB_LAN VO GBE MDI operate in 1000 100 and 10Mbit sec modes This signal pair is used for all modes GBE MDI2 Media Dependent Interface MDI differential pair 2 The MDI can GB LAN VO GBE MDI2 operate in 1000 100 and 10Mbit sec modes This signal pair is only used for 1000Mbit sec Gigabit Ethernet mode GBE_MDI3 Media Dependent Interface MDI differential pair 3 The MDI can GB_LAN VO GBE MDI3 operate in 1000 100 and 10Mbit sec modes This signal pair is only used for 1000Mbit sec Gigabit Ethernet mode GBE_CTREF Reference voltage for carrier board Ethernet channel 0 magnetics REF center tap
27. O _ SDIO_DATO SDIO_DAT3 Va ma 48 MM SDODAT2 52 SDIO DAT5 SDIO DAT4 54 SDIO DAT7 56 60 62 GBE_MDI2 GBE_MDI2 LPC ADO GBE_LINK1000 GBE_MDIO GBE MDI0 SUS S54 SUS S34 SDIO DAT6 RSVD 57 HAD BITCLK I2S CLK 64 SMBALERTR HAD SDI I2S SDI 66 GPON2C CLK 67 HAD SDO I2S SDO 68 GPO_LI2C_DAT SMB CLK GP1 I2C CLK SMB DAT GP1 I2C DAT 71 GND 74 GND 75 80 82 M 79 USB6T7OCR 10 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7 731 8888 F 886 2 7731 9888 http www portwell com tw Signal Signal EE ONE serio 8 B0006 87 SSB PST BTC CSB P2 89 USB Par 9 USB Par 91 Us CC 9 USBID 93 USB Pt 9 USBPO 95 USBPir 9 USB POH 97 6D 8 6ND O 99 eDPO TX0 LVDS A0 100 eDP1 TX0 LVDS BOT 101 eDPO TX0 LVDS A0 102 eDP1 TX0 LVDS BO _ 103 eDPO_TX1 LVDS A1 104 eDP1 TX1 LVDS BT _ 105 eDPO TX1 LVDS A1 106 eDP1 TX1 LVDS B1 107 eDPO TX2 LVDS A2 108 eDP1_TX2 LVDS B2 109 eDPO TX2 LVDS A2 110 eDP1 TX2 LVDS B2 114 LVDS PPEN 112 LVDS BLEN O 113 eDPO TX3 LVDS A3 114 eDP1 TX3 LVDS B3 115 eDPO TX3 LVDS A3 116 eDP1 TX3 LVDS B3 117 6m n8 CGN eDPO AUX eDP1_AUX LVDS A CLK 10 LVDS B CLK eDP0 AUX eDP1_AUX a saak spak LVDS BLT CTRL Se o wn
28. Qseven Design Guide For Designing Qseven Carrier boards Revision 2 0 Portwell Inc 3F Na 92 Sec 1 Nei Hu Rd Taipei Taiwan T 886 2 2799 2020 F BB6 2 2799 1010 http www portweil com tw E mail info 0mail portwell com Revision History 2009 3 1 Initial Release Update to Rev 2 0 2 0 2014 08 20 Update PQ7 M106 Design info Update Input Power Seguencing info r in E a ee wy Portwell Inc Table of Contents N PP ME 8 QSEVEN SpecilicatOM a EE NOS s Nan OD D ee GE aa AE A NB Ge 5 OSEVEII oe idee BE EE EE EE de 6 QSEVEN Feature OVen ew ne de ee ee N ve do ed sea ee OG de De we ENE ei 8 OSEVEN Connector PIN OUT access inae Co sd ese De see dee ee wn UD ee UDD De ed DE Ge ed 9 QSEVEN Carrier Board Design aui dued nu DS RE OE OR dans RO GE ee 13 5 1 PCB Desiei RUNES assesseer ee Gn en Oe Re EE ee 13 5 2 Trace Impedance Considerations iss esse see ese ee ee Re ee ee ee ee 13 Signal Descriptions ie SR ER ARE NG NE N Ee ER Re OE ER Re Ge Ee GE ee le 16 6 1 PCI Express Interface Signial cccscsccscsssccscsccccsceccccsceccccsceccccscescess 17 6 1 1 PCI Express Insertion Loss BUCgEet scecscscsccscscscscecsccccecs 18 6 2 Gigabit Ethernet Sigtnals cccccccscscscsssccccscscncsccccccccscncsceccccccscscnces 21 6 2 1 Gigabit Ethernet Insertion Loss Budget 22 6 2 2 LAN Component Placemen
29. T Reset Signal for external devices CMOS 3 3V maximA O PCle pairs need to be length matched within a given pair but the different pairs do not need to be matched The transmit pairs are designated as PCIEO TX and PCIEO TX thru PCIE1 TX and PCIE1 TX Transmit in this context means that the signals are transmitted out of the Module No coupling Capacitors are needed on Carrier Board PCle transmit lines The coupling caps are located on the Module The receive pairs are designated PCIEO RX and PCIEO RX thru PCIE1 RX and PCIE1 RX Receive in this context means that the signals are received by the Module Coupling capacitors are needed on the Carrier Board on these lines if the PCle target device is down on the Carrier Board Locate the coupling capacitors near the transmit pins of the Carrier Board s PCle target device If the PCle target device is on a slot card then no coupling caps are needed on the lines on the Carrier Board because the coupling caps will be on the slot card 17 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 1 1 PCI Express Insertion Loss Budget Figure 6 1 PCI Express Link Topology 1 Qseven Module Carrier Board Transmitter and Package Onboard Device AC Coupling Capacitors ad RX Path Receiver and Package AC Coupling Capacitors Q n D lt 5 m o o D A W ng o O
30. ber of active data lines This feature allows easy trade off between hardware cost and system performance Note that while DAT1 SD3_D 3 1 are not in use the SoC will tri state those signals Figure 105 SD Memory Card Bus Topology SD Host 35 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 107 eMMC Interface eMMC Host 36 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw High Definition Audio Signals The High Definition Audio or AC 97 or 12S interface are features that are platform dependent and therefore may not be available in all cases Table 6 12 Signal Definition HAD Signal Description VO Type LI VO HDA RST HD Audio AC 97 Codec Reset CMOS 3 3V O I2S RST Multiplexed with 12S Codec Reset HDA_SYNC Serial Bus Synchronization CMOS 3 3V O I2S WS Multiplexed with 12S Word Select from Codec HDA_BCLK HD Audio AC 97 24 MHz Serial Bit Clock from Codec CMOS 3 3V O I2S CLK Multiplexed with 12S Serial Data Clock from Codec HDA SDO HD Audio AC 97 Serial Data Output to Codec CMOS 3 3V O I2S SDO Multiplexed with 12S Serial Data Output from Codec HDA SDI HD Audio AC 97 Serial Data Input from Codec CMOS 3 3V I2S_ SDI Multiplexed with 12S Serial Data Input from Codec 6 5 1 HDA Placement and Routing G
31. cecesesesceseseecesesee 58 r in E a ee 3 E Portwell Inc Table 2 1 MXM CONNECTION ao EG EN ie Ge GR Y YY YG 6 Table 3 1 QSEVEN Supported Features cscscsssscccscscscsccccccccscscsceccccccscscscscesees 8 Table 6 1 Signal Terminology sers Re ck EE RE de EE GE ee O se EE Oe Re es 16 Table 6 2 Signal Definition PCI Express cccsccscsssscsccccscsccccscsccccscsccccscsseecsceseess 17 Table 6 3 Carrier Board PCI Express Insertion Loss Budget lt 19 Table 6 4 Signal Definition Ethernet scccsscscsccscsccccscsccccscsccccscescccscsseecsceceess 21 Table 6 5 Signal Definition Ethernet cccsccsceccscsccccscsccccscsccccscsceccscsceccsceseees 22 Table 6 6 Signal Definition SATA esse ses esse ses see ee ee ee ee EA ee ee ee ee Ge ee ee ee ee ee 24 Table 6 7 SATA Gen 1 Loss Budget Allocation csccccscscscscccsccccscscscscescecececs 25 Table 6 8 SATA Gen2 Loss Budget Allocation cscsccecscscscsccccccccscscscececcccececs 25 Table 6 9 Signal Definition USB csccccscsssscscecsscsccccscsccccscnccccscsccccscsseccscsceess 27 Table 6 10 Signal Definition Etherinet cccscecsscscecsscsccccscsccccscsccccscescecsceccees 28 Table 6 11 Signal Definition SDIO cscecsscscecsscsceccscsccccscnccccnsuccccncsceccscsceees 29 Table 6 12 Signal Definition HAD sesse esse ese sees ese sees ese ee ee ee ee
32. citors e Maximum 2 vias per trace for a RX path and maximum 4 vias per trace for a TX path on the connection from the the Qseven connector on the Qseven carrier board to an onboard device e Maximum 2 vias per trace for a RX path and maximum 2 vias per trace for a TX path on the connection from the Qseven connector on the Oseven carrier board to a PCI Express extension socket that is compliant to the properties defined in the PCI Express Card Electromechanical 19 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Specification this includes standard PCI Express cards as well as ExpressCards e Trace routing is implemented according to the design rules for high speed differential traces The values in Table above are derived from a signal integrity simulation and reflect a worst case scenario Designers that face the necessity to deviate from the given values have to conduct a suitable signal integrity simulation to guarantee compliance to the PQ7 series specification and the underlying PCI Express specification For USB3 0 HDMI and DisplayPort interface signals the description offered in this section is also applicable 20 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 2 Gigabit Ethernet Signals The LA
33. close as possible to the point where the length variation occurs as shown in Figure 8 3 so the discontinuity won t propagate across the channel For example length matching in a chipset breakout area or connector pin field should occur within the first 125 mils 3 175 mm of the structure that causes the length mismatch Figure 8 3 Length Matching Example Preferred O matching gt TT Alternative matching e Serpentine layout introduces discontinuity to the channel and should be minimized so as to make it transparent to the signal This is done by making its electrical length shorter than the signal rise time In general keeping serpentine routing length lt 100 mils is adequate Trace spacing should not become greater than two times the original spacing See Figure 8 4 Figure 8 4 Serpentining Example lt 100 mils G Intra pair differential skew compensation Recommended dimensions A B C D E F G 3W W trace width and S2 lt 2S1 e Keep bends to a minimum Bends can introduce common mode noise into the system which can affect the signal integrity of the differential signal pair 56 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw e f bends are required they should be at a 135 degree angle or greater there should be no 90 degree bends or turns An adequate air gap should be maintained between the ins
34. d to monitor the CMOS 25mA USB power over current of the USB Ports 6 and 7 3 3V Suspend USB ID USB ID pin CMOS Configures the mode of the USB Port 1 If the signal is 3 3V Suspend detected as being high active the BIOS will automatically configure USB Port 1 as USB Client and enable USB Client support This signal should be driven as OC signal by external circuitry USB CC USB Client Connect pin CMOS If USB Port 1 is configured for client mode then an 3 3V Suspend externally connected USB host should set this signal to high active in order to properly make the connection with the module s internal USB client controller If the external USB host is disconnected this signal should be set to low active in order to inform the USB client controller that the external host has been disconnected A level shifter protection circuitry should be implemented on the carrier board for this signal 27 No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 6 5 USB 2 0 Link Topology USB Device Common Mode Choke 40 2auuo gsn 40 2auuo gt gsn USB Cable Table 6 10 Signal Definition Ethernet Segment Loss Budget Value max Trace Length Comments at 240 MHz La 0 4 dB 6 inches Module Trace 0 28 dB GHz inch Le 0 05 dB MXM Connector at 240 MHz Lc 1 dB 14 inches Carrier Board Trace 0 28 dB GHz inch Lo 1 00 d
35. e IC pins with wide traces to reduce impedance Place the crystal or oscillator as close as possible to the codec 38 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 6 LVDS Flat Panel Signal LVDS is a high speed low power data transmission standard used for display connections to LCD panels The Intel SCH supports a Low Voltage Differential Signaling interface that allows the Intel Graphics Media Adapter to communicate directly to an on board flat panel display The LVDS interface supports pixel color depths of 18 and 24 bits Route LVDS differential pairs with 1000 differential impedance and 500 single end impedance Keep traces as short as possible The LVDS flat panel configuration within the BIOS of the Qseven module shall be implemented in accordance to the DisplaylD specification that is under development within the Video Electronics Standards Association VESA For more information about the LVDS flat panel configuration with DisplaylD refer to the specification Display Identification Data DisplaylD Structure Version 1 0 that is available on the webpage of the Video Electronics Standards Association VESA The LVDS interface can be used either as a single channel or as a dual channel depending on the properties of the platform used for the Oseven uOseven module It is also possible to use the LVDS interface as
36. e LPC CLKOUT signals support two loads with no external buffering Table 6 16 Signal Definition LPC Description VO Type louli f LPC AD 0 3 Multiplexed Command Address and Data CMOS 3 3V VO GPIO 0 3 General purpose input output 0 3 LPC FRAME LPC frame indicates the start of a new cycle or the termination of CMOS 3 3V VO a broken cycle GPIO5 General purpose input output 5 LPC LDRO LPC DMA request CMOS 3 3V VO GPIO7 General purpose input output 7 LPC_CLK LPC clock CMOS 3 3V VO GPIO4 General purpose input output 4 SERIRO Serialized Interrupt CMOS 3 3V VO GPIO6 General purpose input output 6 6 10 CAN Bus Interface Signals Controller Area Network CAN or CAN bus is a message based protocol designed specifically for automotive applications but now is also used in other areas such as industrial automation and medical equipment Table 6 17 Signal Definition CAN Bus Description lou ti WO CANO TX CAN Controller Area Network TX output for CAN Bus channel 0 CMOS 3 3V O In order to connect a CAN controller device to the Oseven module s CAN bus it is necessary to add transceiver hardware to the carrier board CANO RX RX input for CAN Bus channel 0 In order to connect a CAN CMOS 3 3V controller device to the Oseven module s CAN bus it is necessary to add transceiver hardware to the carrier board If the CAN Bus interface is not used and or the Oseven module s chipset does not support CAN Bus then
37. e enabling secondary function for MFG NCO 3 JTAG UART When MFG NC4 is high active it is being used for JTAG purposes When MFG NC4 is low active it is being used for UART purposes 49 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 18 Thermal Management Signals PO7 SERIES provides the THRM and THRMTRIP signals which are used for system thermal management In most current system platforms thermal management is closely associated with system power management Table 6 25 Signal Definition Miscellaneous Description WO Type lorh THRM Thermal Alarm active low signal generated by the external CMOS 3 3V hardware to indicate an over temperature situation This signal can be used to initiate thermal throttling 6 19 Fan Control THRMTRIP Thermal Trip indicates an overheating condition of the CMOS 3 3V O Implem i processor If THRMTRIP goes active the system pinentang immediately transitions to the S5 State Soft Off m Table 6 26 Signal Definition Fan Control Description VO Type loh VO FAN PWMOUT Primary functionality is fan speed control Uses the Pulse Width CMOS 3 3V O IGP PWM OUT1 Modulation PWM technique to control the Fan s RPM based on the OC CPU s die temperature When not in use for this primary purpose it can be used as General Purpose PWM Output FAN TACHOIN Primary functionality is
38. econdary channel differential pair 0 LVDS O LVDS BO eDP1 TX0 Display Port secondary channel differential pair 0 LVDS O eDP1_TXO0 LVDS_B1 LVDS secondary channel differential pair 1 LVDS O LVDS B1 eDP1_TX1 Display Port secondary channel differential pair 1 LVDS O eDP1 TX1 LVDS_B2 LVDS secondary channel differential pair 2 LVDS O LVDS_B2 eDP1_TX2 Display Port secondary channel differential pair 2 LVDS O eDP1 TX2 LVDS_B3 LVDS secondary channel differential pair 3 LVDS O LVDS B3 eDP1 TX3 Display Port secondary channel differential pair 3 LVDS O eDP1_TX3 LVDS_B_CLK LVDS secondary channel differential pair clock lines LVDS O LVDS_B_CLK eDP1_AUX Display Port secondary auxiliary channel LVDS O eDP1 AUX LVDS DID CLK Primary functionality is DisplaylD DDC clock line used for LVDS CMOS 3 3V VO GP2 I2C CLK flat panel detection If the primary functionality is not used itcan OD be used as a General Purpose C bus clock line LVDS DID DAT Primary functionality DisplaylD DDC data line used for LVDS flat CMOS 3 3V VO GP2 I2C DAT panel detection If the primary functionality is not used itcanbe OD used as a General Purpose C bus data line LVDS BLC CLK Control clock signal for external SSC clock chip If the primary CMOS 3 3V VO eDP1_HPD functionality is not used it can be used as an emedded OD DisplayPort secondary Hotplug detection LVDS BLC DAT Control data signal for external SSC clock chip CMOS 3 3V VO eDPO HPD If
39. g production or as a vendor specific control signal When used as a vendor specific control signal the multiplexer must be controlled by the MFG NC4 signal MFG NC1 This pin is reserved for manufacturing and debugging n a n a n a purposes May be used as JTAG TDO signal for boundary scan purposes during production May also be used via a multiplexer as a UART TX signal to connect a simple UART for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG NC4 signal MFG NC2 This pin is reserved for manufacturing and debugging n a n a n a purposes May be used as JTAG TDI signal for boundary scan purposes during production May also be used via a multiplexer as a UART_RX signal to connect a simple UART for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG_NC4 signal MFG_NC3 This pin is reserved for manufacturing and debugging n a n a n a purposes May be used as JTAG_TMS signal for boundary scan purposes during production May also be used via a multiplexer as vendor specific BOOT signal for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG_NC4 signal MFG_NC4 This pin is reserved for manufacturing and debugging n a n a n a purposes May be used as JTAG_TRST signal for boundary scan purposes during production May also be used as control signal for a multiplexer circuit on the modul
40. h the standard 5V power rail VCC 51 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 7 1 Input Power Sequencing PO7 series input power sequencing requirements are as follows ATX Mode Start Sequence o VCC RTC must come up at the same time or before VCC_5V_SB comes up o VCC 5V SB must come up at the same time or before VCC comes up e PWGIN must be active at the same time or after VCC comes up Stop Sequence e PWGIN must be inactive at the same time or before VCC goes down o VCC must go down at the same time or before VCC 5V SB goes down o VCC 5V SB must go down at the same time or before VCC RTC goes down Figure 7 1 Input Power Seguencing VCC RTC VCC 5V SB Table 7 2 Input Power Sequencing item Description Value T1 VOC RTC rise to VCC 5V SB rise 20 ms T2 VCC 5V SB rise to VCC rise 20ms T3 VCC rise to PWGIN rise 20 ms T4 PWGIN fall to VCC fall 20ms T5 VCC fall to VCC 5V SB fall 20ms T6 VCC_5V_SB fall to VCC_RTC fall 2 0 ms AT Mode 92 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw AT mode only provides main voltage VCC ATX Detect pin shall pull low then power button control by EC on PQ7 series module The sequence VCC and PWGIN are the same as ATX Table 7 2 Input Power Sequenc
41. ide traces of a bend The gap should be four times the trace width or greater The lengths of the segments in a bend should be 1 5 times the trace width or greater See e Figure 8 5 and Figure 8 6 for examples Figure 8 5 Acceptable Bends vs Tight Bends Example Preferred Not Considered Tight Bends o SSD SO 8 A void Tight Bends Figure 8 6 Via Pair Placement OL gt 135 degrees A gt 4x the trace width B gt 1 5x the trace width C gt 1 5x the trace width of Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw e The via count can be reduced but not increased from the maximum interface via requirements given in this document Remove pads from unused internal layers to minimize excess via capacitance The differential pair via placement must be symmetrical Vias on the differential pair should not only match in number but also in relative location Figure 8 7 Via Pair Placement Via Pair Bottom layer Top layer diff pair cw diff pair Preferred Via placement is in same location amp symmetric Avoid Via placement is NOT in same location symmetric 58
42. ign guide Figure 5 2 Stripline Diagram NOTE The trace spacing vary from one signal group to the other Each signal group s values are specified in their respective sections within this design guide Figure 5 3 Differential Trace Dimension Terminology Transmit Pair Receive Pair Trace Width Differential Pair Pitch _ 14 No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Figure 5 4 Trace Spacing vs Trace Width Examples 15 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 Signal Descriptions The symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When is not present the signal is asserted when at a high voltage level Differential pairs are indicated by trailing and signs for the positive or negative signal The following terminology is used to describe the signals types in the I O columns for the tables located below Table 6 1 Signal Terminology Term Description Input Pin O Output Pin OC Open Collector OD Open Drain PP Push Pull VO Bi directional Input Output Pin lot Output low current The la is the maximum output low current the module must be able to drive to
43. ing Item Description Value T1 VCC_RTC rise to VCC_5V_SBrise 2 0 ms T2 VCC_5V_SB rise to VCC rise 20ms T3 VCC rise to PWGIN rise gt 0 ms T4 PWGIN fall to VCC fall 2 0 ms T5 VCC fall to VCC 5V SB fall 20ms T6 VCC_5V_SB fall to VCC_RTC fall 20 ms 9 General Considerations for Differential Signal The following is a list of suggestions for designing with high speed differential signals This should help implement these interfaces while providing maximum PO7 SERIES carrier board performance e Use controlled impedance PCB traces that match the specified differential impedance e Keep the trace lengths as short as possible e The differential signal pair traces should be trace length matched and the maximum trace length mismatch should not exceed the specified values Match each differential pair per segment e Route differential signals onthe signal layer nearest to the ground plane using aminimum of vias and corners This will reduce signal eflections and impedance changes Use GND stitching vias when changing layers e Avoid tight bends When it becomes necessary to turn 90 use two 45 turns or an arc instead of making a single 90 turn e Do not route traces under crystals crystal oscillators clock synthesizers magnetic devices or ICs that use and or generate clocks e Stubs on differential signals should be avoided due to the fact that stubs will cause signal 53 Portwell Inc No 242 Bo Ai St Shu Lin Dist New
44. ls csccscscscscecsccccscscncscccsccccscscscscesees 47 6 17 Miscellaneous Signals os ae SE Oe GN Ee ee ER se SE Ee eie 48 6 18 Manufacturing Signals scscsccscsssccscscsccscscsccsceccccscecsecscessccsces 49 6 19 Thermal Management Signals scsccccscscscscsccccccscscsccccccccscscces 50 6 20 Fan Control Implementation ccscscscecsccccscscscscccsccccscscscscecees 50 Input Power Requirements sd de es Oe Ge ee dd ge EG AG Ee de 51 7 1 Input Power Sequencing sezam si oe Ge Ge GE Ee 52 General Considerations for Differential Signal cscsccscssscsscscsccscececcsceccecs 53 Portwell Inc Figure 2 1 MXM onnectOl issie oi ine ee ed oe Se GE DE Ge es Ee Ge SG do oe de 6 Figure 2 2 Overall Height including Heat spreader of the Qseven Module 7 Figure 4 1 Connector Pin out Description ssesessesescescsesescescecesceseecescesescescesesceseese 9 Figure 5 1 Microstrip Diagram cccscscscscscscscscccecccscccccccccccccccccscccccscecscccscecsseces 14 Figure 5 2 Stripllne Diagram sesesesseceseseecesescecesescecesesceceseseeceseseeceseseeceseseecesesee 14 Figure 5 3 Differential Trace Dimension Terminology csscscsccscscsccscsccccscsceees 14 Figure 5 4 Trace Spacing vs Trace Width Examples cscsccscscsecscscsccscsccccscsceees 15 Figure 6 1 PCI Express Link Topology 1 ccscsccscscsceccccccecscscsceccccccecscscscescceeees 18 Figure 6
45. nal budget from chip to mated connector The trace lengths presented in Table 6 X are based on the following assumptions e Typical damping of the PCB trace of 0 42dB inch 1 5GHz common value for FR 4 based material e The budget includes the additional damping of the DC decoupling and the Qseven connector losses e Trace routing is implemented according to the design rules for high speed differential traces Table 6 7 SATA Gen 1 Loss Budget Allocation Segment Loss Budget Value Max Trace Comments at 0 75 GHz dB Length LA 0 5 dB 2 5 inches Module Trace 0 28 dB GHz inch Coupling Caps 0 40 dB Le 0 40 dB MXM Connector 0 75 GHz Lc 1 55 dB 12 Carrier Board Trace 0 28 dB GHz inch Total 2 85 dB Table 6 8 SATA Gen2 Loss Budget Allocation Segment Loss Budget Value Max Trace Comments at 1 5 GHz dB Length La 1 05 dB 2 5 inches Module Trace 0 28 dB GHz inch Coupling Caps 0 40 dB Le 0 50 dB MXM Connector 1 5 GHz Lc 1 05 dB 2 5 inches Carrier Board Trace 0 28 dB GHz inch Total 3 00 dB 25 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 4 USB Interface Signals A common mode choke is advisable if USB pairs on the Carrier Board are routed to a connector for use with an external cable PQ7 SERIES can support up to 8 USB 2 0 ports and 2 USB SuperSpeed Signals USB O 1 OCH
46. oard component can exceed a maximum height of 2 5mm The heatspreader offered for PQ7 series modules acts as a thermal coupling device and is not heat sink Heat dissipation devices such as a heat sink with fan or heat pipe may need to be connected to the heat spreader The dissipation of heat will fluctuate between different CPU boards Refer to the PQ7 series module user s manual for heat spreader dimensions and specifications The standoff for the heat spreader and carrier board must not exceed 5 6 mm overall external diameters It ensures that the standoff contact area does not exceed the defined mounting hole footprint on the PQ7 series module The screw that is to be used for mounting must be a metric thread M2 5 DIN7985 ISO7045 PO7 series modules are defined to feature ultra low power CPU and chipset solutions with an ultra low Thermal Design Power TDP The modules power consumption not exceeds 12W Figure 2 2 Overall Height including Heat spreader of the Qseven Module Oseven Module PCB Oseven Connector Heatspreader 1 20 A 0 1 6 0 See Note Note Dimension is dependent All measurements are in millimeters on connector height used All dimensions without tolerance 0 2mm a Y Portwell Inc ma ie No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 3 Qsven Feature Overview The Oseven mandatory and optional feature
47. oard power supplies Table 6 20 Signal Definition Input Power Signal Description Jie VCC Power Supply 5VDC 5 P VCC 5V SB Standby Power Supply 5VDC 5 P VCC RTC 3 V backup cell input VCC RTC should be connected to a 3V backup cell for RTC P operation and storage register non volatility in the absence of system power VCC RTC 2 4 3 3 V GND Power Ground P 46 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 14 Power control signal Table 6 21 Signal Definition Power Control Description of Power Control signals VO Type lou Tn VO PWGIN High active input for the Oseven module indicates that all power CMOS z4mA rails located on the carrier board are ready for use 5V PWRBTN Power Button Low active power button input This signal is CMOS 210mA triggered on the falling edge 3 3V Standby 6 15 Power Management signals It must be guaranteed that all the carrier board power rails that are generated out of the VCC power rail will be enabled by the SUS S3 signal Table 6 22 Signal Definition Power Management Description of Power Management signals VO Type lovy RSTBTN Reset button input This input may be driven active low by an CMOS 210mA external circuitry to reset the Oseven module 3 3V BATLOW Battery low input This signal may be driven active low by external CMOS gt 10 mA circui
48. ompensation SD3_PWREN O SD Card Power Enable PTT vires Tissot noo o mone wer on SO 34 16 2 2 16 2 3 16 2 3 1 No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw SDIO SD Card Interface Features e Up to 832Mbits per second data rate using 4 parallel data lines e Transfers the data in 1 bit and 4 bit SD modes e Transfers the data in following UHS I modes HS and DDRSO e Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity e Designed to work with I O cards Read only cards and Read Write cards Supports Read wait Control e SDIO only validated with WIFI devices Storage Interfaces Overview This section provides a very high level overview of the SD SDIO eMMC 4 5 specification Refer to the SD and eMMC specifications for complete details SD Card 3 0 Bus Interface The SD Card bus has a single master single slaves card synchronous topology refer to Figure 105 During initialization process commands are sent to the card allowing the application to detect the card and assign logical addresses to the physical slot All data communication in the Card Identification Mode uses the command line CMD only SD bus allows dynamic configuration of the number of data lines After power up by default the SD Card will use only SD3_D 0 for data transfer After initialization the host can change the bus width num
49. ostrip in which a trace or trace pair is referenced to a single ground or power plane The outer layers of multi layer PCBs are microstrips A diagram of a microstrip cross section is shown in Figure 5 1 below The second structure is stripline in which a trace or pair of traces is sandwiched between two reference planes as shown in Figure 5 2 below If the traces are exactly halfway between the reference planes then the stripline is said to be symmetric or balanced Usually the traces are a lot closer to one of the planes than the other Inner layer traces on multi layer PCBs are usually asymmetric striplines Before proceeding wjth a Carrier Board layout designers should decide on aPCB stack up and on trace parameters primarily the trace width and differential pair spacing It is quite harder to change the differential impedance of a trace pair after layout work is done than it is to change the impedance of a single ended signal It is more important for the PCB designer and the Project Engineer to determine the routing parameters for differential pairs ahead of time 13 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www_portwell com tw Figure 5 1 Microstrip Diagram race Width NOTE The trace spacing vary from one signal group to the other Each signal group s values are specified in their respective sections within this des
50. rential pair USB VO USB P1 This port may be optionally used as USB client port USB P2 Universal Serial Bus Port 2 differential pair USB VO USB P2 USB Pat Universal Serial Bus Port 3 differential pair USB VO USB Pa USB_P4 Universal Serial Bus Port 4 differential pair USB VO USB_P4 USB_SSRX1 Multiplexed with receive signal differential pairs for the USB SSRX1 Superspeed USB data path USB P5 Universal Serial Bus Port 5 differential pair USB VO USB_P5 USB SSTX1 Multiplexed with transmit signal differential pairs for the O USB 55TX1 Superspeed USB data path USB P6 Universal Serial Bus Port 6 differential pair USB VO USB_P6 USB SSRX0 Multiplexed with receive signal differential pairs for the USB SSRKD Superspeed USB data path USB P7 Universal Serial Bus Port 7 differential pair USB VO USB P7 USB SSTX0 Multiplexed with transmit signal differential pairs for the O USB_SSTX0 Superspeed USB data path USB 0 1 OCR Over current detect input 1 This pin is used to monitor the CMOS gt 5mA USB power over current of the USB Ports 0 and 1 3 3V Suspend USB 2 3 OCR Over current detect input 2 This pin is used to monitor the CMOS 25 mA USB power over current of the USB Ports 2 and 3 3 3V Suspend USB_4 5 OC Over current detect input 3 This pin is used to monitor the CMOS gt 5 mA USB power over current of the USB Ports 4 and 5 3 3V Suspend USB 6 7 OCR Over current detect input 4 This pin is use
51. require the native HDMI signals from the SOC to be level shifted Route HDMI DVI differential pairs with 850 differential impedance and 500 single end impedance Table 6 15 Signal Definition HDMI Shared With Description VO Type lo ly TMDS CLK DP LANE3 TMDS differential pair clock lines TMDS O TMDS_CLK DP_LANE3 TMDS_LANEO DP_LANE2 TMDS differential pair lines lane 0 TMDS O TMDS_LANEO DP_LANE2 TMDS_LANE1 DP_LANE1 TMDS differential pair lines lane 1 TMDS O TMDS_LANE1 DP_LANE1 TMDS_LANE2 DP_LANEO TMDS differential pair lines lane 2 TMDS O TMDS_LANE2 DP_LANEO HDMI CTRL CLK DDC based control signal clock for HDMI CMOS 3 3V VO device OD Note Level shifters must be implemented on the camer board for this signal in order to be compliant with the HDMI Specification HDMI CTRL DAT DDC based control signal data for HDMI CMOS 3 3V VO device OD Note Level shifters must be implemented on the carrier board for this signal in order to be compliant with the HDMI Specification DP_HDMI_HPD Hot plug detection signal that serves as an CMOS 3 3V interrupt request 44 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 9 LPC interface Signal The Intel SCH implements an LPC interface as described in the LPC 1 1 Specification The LPC bridge function of the Intel SCH resides in PCI Device 31 Function 0 Th
52. t ccccccscscscecsccccssecscscecsccccecs 23 6 3 Serial ATA Interface Signals sesse sesse sesse ee ee ee GR Gee ee ee ee ee ee 24 6 3 1 Serial ATA Insertion Loss Budget ses esse ske sesse se se ee ee se ee ee 24 6 4 USB Interface Signals t Mb F M Y 26 6 4 1 USE ient 4 IX MM tee PERI IE 6 5 SDIO Interface Sigtals ccccscscsscscscsccsceccccsceccccscecsccsceccccececcscsceceeees 29 6 6 High Definition Audio Sigtals cscsscscsccscscsccscsccccsceccccsceccccsceceecs 37 6 6 1 HDA Placement and Routing Guidelines 37 6 7 LVDS Flat Panel o OE EE 39 6 7 1 LVDS Implementation Guidelines sesse sesse ee ese ee ee Ee ee 41 6 8 DisplayPort Interface Signals ccccccscscsccscscsccsceccccsceccccsceccccsceceecs 42 6 9 MD MIMNterface Signals GRY SS Ne Ge GENE ON ee Ge Ge de eN ds 44 6 10 EPG interface Sienal ss iese RS De DE da es be ee GE Ge Re De Dee 45 6 11 CAN Bus Interface Signals cscscsccssscsscsceccscsccccsceccccscsceccscsceess 45 6 12 SPI Interface SIC MAIS ues ee Ee ve Ge OE er De eo Ge oe Ge 46 6 13 UART Interface Signals cscsssssscssscssccssccsccssccsccssccnccscccnccssccnsess 46 6 14 Input power DIT O OH De ER RHO eN de Ge de oo ede 46 6 15 Power control signal ss EE EE SERE ste EER OE we GR GE EG Se ee EE Oe Ee N 47 6 16 Power Management signa
53. tch may add the insertion loss for the RJ45 Ethernet jack and integrated magnetics to the carrier board budget This insertion loss value is typically 1 dB The carrier Loss Budget Value at 100 MHz 0 08 dB 0 02 dB 0 15 dB 24 00 dB 24 25 dB max Trace Comments Length 2 inches Module trace 0 28 dB GHz inch 4 inches MXM connector at 100 MHz Carrier Board trace 0 28 dB GHz inch Cable and cable connectors integrated magnetics per source spec board insertion loss budget then becomes LC 1 dB or 1 15 dB 22 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 2 2 LAN Component Placement When using RJ45 connectors without integrated magnetics the discrete magnetics module has to be placed as close as possible to the RJ45 connector The distance between the magnetics module and RJ45 connector must be less than 1 inch This distance mequirement must be observed during the carrier board layout when implementing LAN 23 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw 6 3 Serial ATA Interface Signals Serial ATA SATA signals are high speed differential pairs with a nominal 850 differential impedance Route them as differential pairs preferably referenced to a continuous GND plane with a minimum
54. the primary functionality is not used it can be used as an OD emedded DisplayPort primary Hotplug detection 40 No 242 New Taipei City 238 886 2 7731 8888 F 886 2 7731 9888 http www portw PQ7 M106 VGA Connector Design VGA_RED 204 204 Bo Ai St Shu Lin Dist VGA_VSYNC 209 207 VGA_HSYNC 207 209 6 6 1 LVDS Implementation Guidelines Many carrier board designs do not need the full range of LVDS performance offered by PQ7 series modules It depends on the flat panel configuration of the PQ7 SERIES as well as the carrier board design as to how many LVDS signal pairs are supported If the LVDS display interface of the PQ7 series is not implemented all signals associated with this interface should be left open This display port is normally used in conjunction with the pipe functions of panel up scaling and 6 to 8 bit dithers This display port is also used in conjunction with the panel power sequencing and additional associated functions When enabled the LVDS constant current drivers consume significant power Individual pairs or sets of pairs can be selected to be powered down when not being used While disabled individual or sets of pairs will enter a low power state When the port is disabled all pairs enter a low power mode The panel power sequencing can be set to override the selected power state of the drivers during power sequencing A maximum pixel clock of 112 MHz is supported for the LV
55. try to signal that the system battery is low or may be used to 3 3V Suspend signal some other external battery management event WAKE External system wake event This may be driven active low by CMOS 10 mA external circuitry to signal an external wake up event 3 3V Suspend SUS_STAT Suspend Status indicates that the system will be entering a low CMOS max imA O power state soon 3 3V Suspend SUS_S3 S3 State This signal shuts off power to all runtime system CMOS max 1mA O components that are not maintained during S3 Suspend to Ram S4 3 3V Suspend or S5 states The signal SUS S3 is necessary in order to support the optional S3 cold power state SUS_S5 S5 State This signal indicates S4 or S5 Soft Off state CMOS max imA O 3 3V Suspend SLP_BTN Sleep button Low active signal used by the ACPI operating system CMOS 210mA to transition the system into sleep state or to wake it up again This 3 3V Suspend signal is triggered on falling edge LID BIN LID button Low active signal used by the ACPI operating system to CMOS 10 mA detect a LID switch and to bring system into sleep state or to wake it 3 3V Suspend up again Open Close state may be software configurable 47 6 16 Miscellaneous Signals Table 6 23 Signal Definition Miscellaneous Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7 731 9888 http www portwell com tw WDTRIG WDOUT GPO I2
56. two independent single LVDS channels To do this it is recommended to set the configuration of the LVDS display with an external EEPROM 39 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7 731 8888 F 886 2 7731 9888 http www portwell com tw Table 6 13 Signal Definition LVDS Signal Description WO Type loh VO LVDS PPEN Controls panel power enable CMOS 3 3V max1mA O LVDS BLEN Controls panel backlight enable CMOS 3 3V max1mA O LVDS BLT CTRL Primary functionality is to control the panel backlight brightness CMOS 3 3V O GP_PWM_OUTO via pulse width modulation PWM When not in use for this primary purpose it can be used as General Purpose PWM Output LVDS A0 LVDS primary channel differential pair 0 LVDS O LVDS_AO eDPO TX0 Display Port primary channel differential pair 0 LVDS O eDPO TXO LVDS A17 LVDS primary channel differential pair 1 LVDS O LVDS A1 eDPO TX1 Display Port primary channel differential pair 1 LVDS O eDPO TX1 LVDS_A2 LVDS primary channel differential pair 2 LVDS O LVDS A2 eDPO TX2 Display Port primary channel differential pair 2 LVDS O eDPO TX2 LVDS_A3 LVDS primary channel differential pair 3 LVDS O LVDS_A3 eDPO_TX3 Display Port primary channel differential pair 3 LVDS O eDPO TX3 LVDS A CLK LVDS primary channel differential pair clock lines LVDS O LVDS_A_CLK eDPO_AUX Display Port primary auxiliary channel LVDS O eDPO AUX LVDS BOT LVDS s
57. uidelines HDA RST is the reset signal to external Codec This signal should have a series termination of 330 5 HDA_SDO is a serial TDM data output to the Codec The serial output is double pumped for a bit rate of 48 Mb s for HD Audio This signal should have a series termination of 33 O15 A non stuffed resistor site for a 1kQ 2596 pull up to 3 3V should be provided HDA_SYNC is 48 kHz fixed rate sample sync to the Codec It is also used to encode the stream number This signal should have a series termination of 330 5 It has a weak internal pull down and should not be pulled high Ground return paths for the analog signals must be given special consideration Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines Locate the analog and digital signals as far as possible from each other Partition the carrier board with all analog components grouped together in one area and all digital components in another Keep digital signal traces especially the clock as far as possible from the analog input and voltage reference pins 37 Portwell Inc No 242 Bo Ai St Shu Lin Dist New Taipei City 238 Taiwan T 886 2 7731 8888 F 886 2 7731 9888 http www portwell com tw Route analog power and signal traces over the analog ground plane Route digital power and signal traces over the digital ground plane Position the bypassing and decoupling capacitors close to th
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