XC886/888LM Series Errata Sheet, Step AC
Contents
1. Table 7 Module Register SFR RMA Products Address P Affected 6 CC61SRH FD 0 0 All cont d CC62SRL FE 0 0 All CC62SRH FF 0 0 All T12PRL 9C 0 1 All T12PRH 9D 0 1 All T13PRL 9E 0 1 All T13PRH 9F 0 1 All T12DTCL A4 0 1 All T12DTCH Ady 0 1 All TCTROL A64 0 1 All TCTROH AT 0 1 All T12MSELL 9A 0 2 All T12MSELH 0 2 All IENL 9C 0 2 All IENH 9D 0 2 All INPL 9E 0 2 All INPH OF 0 2 All PSLR A64 0 2 All MCMCTR AT 0 2 All TCTR2L FA 0 2 All TCTR2H 0 2 MODCTRL FC 0 2 All MODCTRH FD 0 2 All TRPCTRL FE 0 2 All TRPCTRH FF 0 2 All PISELOL 9E 0 3 All PISELOH OF 0 3 All PISEL2 0 3 All XC886 888LM Series AC 18 36 Rel 1 6 28 02 2011 Cifineon Errata Sheet Functional Deviations Table 7 Module Register SFR RMA Products Address P Affected 6 T13L FC 0 3 All contd T43H FD 0 3 All CMPSTATH FF 0 3 All ADC GLOBCTR CA 0 0 All PRAR CC 0 0 All LCBR CD 0 0 All INPCRO CE 0 0 All ETRCR CF 0 0 All CHCTRO CA 0 1 All CHCTR1 CB 0 1 All CHCTR2 CC 0 1 All CHCTR3 CD 0 1 All CHCTR4 CE 0 1 All CHCTR5 CF 0 1 All CHCTR6 D2 0 1 All CHCTR7 0 1 RCRO CA 0 4 All RCR1 CB 0 4 All RCR2 CC 0 4 All RCR3 CD 0 4 All CHINPR CD 0 5 All EVINPR D34 0 5 All CRCR1 CA 0 62. However for applications with strict low power down current requirements it is mandatory that no active voltage source is supplied at any GPIO pin when Vppp is not powered on PLL XC8 H001 Check oscillator run bit 2048 VCO cycles after oscillator run detection is restarted When performing a loss of lock recovery or changing to an external oscillator one of the steps required is to restart the oscillator run detection logic by setting OSC CON ORDRES bit to 1 After the oscillator run detection logic is restarted the user should wait for minimum 2048 VCO cycles approximately between 30 us and 200 us XC886 888LM Series AC 34 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints depending on VCO base frequency before checking the status of the oscillator run bit 05 CON OSCR SYS XC8 H001 Usage of the Bit Protection Scheme When the bit protection scheme is enabled bit field PASSWD PASS should always be used to open and close write access to the protected bits The scheme should be disabled only if it is not required in the application In the unlikely event that the scheme is enabled again after disabling it while the write access is still open the write access will remain open until the count of 32 CCLK cycles is completed SYS XC8 H003 Effective write for Read Modify Write instructions of two bytes one machine cycle When read modify write instructions requiring 2 bytes and 1 machine cycle
3. Table 6 Application Hints Hint Short Description Chg Pg ADC_AI H001 Arbitration Mode with disabled 24 Arbitration Slots ADC XC8 H001 Arbitration mode when using external 24 trigger at the selected input line REQTR BROM XC8 H001 SYSCONO RMAP handling in ISR 25 BROM XC8 H002 Obtain Product Derivative Information 25 With Chip Identification Number CCU6_XC8 H002 CCU6 PM event in center aligned mode New 26 FLASH XC8 H002 Programming to invalid P Flash address 27 range 5000 to 5FFF may corrupt existing P Flash data FLASH XC8 H003 Verify if a Flash program or erase 27 operation is successful XC886 888LM Series AC 5 36 Rel 1 6 28 02 2011 Infineon Errata Sheet History List Change Summary Table 6 Application Hints cont d Hint Short Description Chg Pg INT XC8 H003 Interrupt Flags of External Interrupt 0 and 27 1 INT XC8 H004 NMI Interrupt Request With No NMI Flag 29 Set INT XC8 H005 Not all Flags are qualified for clearing 30 Pending Interrupt Request LIN XC8 H001 LIN BRK field detection logic 32 LIN XC8 H002 LIN Break Synch field detection 33 ate OCDS XC8 H002 NMI request is lost on Debug entry 34 and during Debug PIN XC8 H001 Current over GPIO pin must not source 34 Vppe higher than 0 3V PLL XC8 H001 Check oscillator run bit 2048 VCO cycles 34 after oscillator run detection is restarted SYS XC8 H001 Usage of the Bit Protection
4. Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet XC886 888LM Series AC 2 36 Rel 1 6 28 02 2011 Infineon Errata Sheet History List Change Summary 1 History List Change Summary Table 2 History List Version Date Remark 1 0 01 12 2006 1 1 15 02 2007 1 2 08 06 2007 1 3 23 11 2007 1 4 22 02 2008 1 5 13 02 2009 Table 3 Errata fixed in this step Errata Short Description Chg EVR XC8 005 Reset toggling issue for repeated power up Fixed FLASH XC8 004 Wrong data fetched during backward read Fixed access in P Flash with Parallel Read Mode enabled Table 4 Functional Deviations Functional Short Description Chg Pg Deviation BROM XC8 006 IRAM data is corrupted after any warm 7 reset BROM XC8 010 SYSCONO RMAP Switching Error T XC886 888LM Series AC 3 36 Rel 1 6 28 02 2011 Cifineon Errata Sheet History List Change Summary Table 4 Functional Deviations cont d Functional Short Description Chg Pg Deviation CD_XC8 001 Set and Clear of Error Bit in CORDIC Linear 8 Vectoring Mode CD_XC8 002 Data Fetch to CD_STATC Register may 8 capture an incorrect error status
5. INT_XC8 004 Unable to Detect New Interrupt Request if 9 Any One of Timer 2 Timer 21 UART1 Interrupt Flags Is Not Cleared Unexpectedly INT_XC8 005 Write to IRCONO Blocks Interrupt Request 12 of External Interrupt 0 1 LIN_XC8 001 Fast LIN BSL does not support baud rate 12 of up to 115 2 kHz OCDS XC8 008 Watchdog Timer behavior during Debug 12 with Suspend PIN XC8 005 Glitches on TCK when switching between 13 clock sources PIN XC8 006 Port 4 pads excluding P4 2 toggle once 13 upon a power on or hardware reset PIN XC8 007 External pull up device is required on MBC 14 pin to enter user mode PM XC8 003 Wake up triggered before power down New 14 sequence completed SYS XC8 001 MOV direct direct instruction might 15 cause a wrong value to be written to the destination register T2 XC8 001 Timer 2 is not suspended during debug in 21 counter mode UART XC8 001 Bits RB8 Tl and RI in UART1 SCON SFR 21 XC886 888LM Series AC cannot be Written by SETB CLR and CPL Instructions 4 36 Rel 1 6 28 02 2011 Luni Errata Sheet History List Change Summary Table 4 Functional Deviations cont d Functional Short Description Chg Pg Deviation UART XC8 002 Bits FDEN and FDM in UART1 FDCON 21 SFR cannot be Written by Read Modify Write Instructions Table 5 Deviations from Electrical and Timing Specification ACIDC ADC Short Description Chg Pg Deviation
6. Scheme 35 SYS XC8 H003 Effective write for Read Modify Write New 35 instructions of two bytes one machine cycle SYS XC8 H004 Switch PLL to prescaler mode beforea New 36 WDT reset XC886 888LM Series AC 6 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations 2 Functional Deviations BROM XC8 006 IRAM data is corrupted after any warm reset After any warm reset i e reset without powering off the device boot up via User Mode affects certain IRAM data The affected IRAM address ranges are 1 00 07 2 80 C7 Workaround None BROM XC8 010 SvSCONO RMAP Switching Error When executing from XRAM if SYSCONO RMAP is switched using an one machine cycle read modify write instruction e g ORL dir A and the SFR is accessed immediately by an one machine cycle instruction e g MOV A dir or a PUSH instruction the SFR from the previous mapping might be accessed instead This RMAP switching error does not occur if code is executed from the Flash memory Workaround When executing code from XRAM use two machine cycle instructions to either switch RMAP or access the SFR Alternatively add one or more instructions e g NOP between the one machine cycle RMAP switching and SFR accessing instructions XC886 888LM Series AC 7 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations CD XC8 001 Set and Clear of Error Bit in CORDIC Linear Vectoring Mode In linear v
7. Timer 2 is not suspended during debug in counter mode Timer 2 is not suspended even if Timer 2 suspend control is enabled by setting bit MODSUSP T2SUSP during debug if Timer 2 is set to counter mode Workaround None UART XC8 001 Bits RB8 TI and RI in UART1 SCON SFR cannot be Writ ten by SETB CLR and CPL Instructions The bits RB8 and RI in UART1 SCON SFR which is a bitaddressable SFR are not updated when written with SETB CLR and CPL instructions As a result the UART1 module is not fully compatible with standard 8051 code Workaround Use MOV bit C instruction to write to the bits RB8 TI and RI in UART1 SCON SFR or target the write access on the whole register UART XC8 002 Bits FDEN and FDM in UART1 FDCON SFR cannot be Writ ten by Read Modify Write Instructions The bits FDEN and FDM in UART1 FDCON SFR are not updated when written with the read modify write instructions listed in the table below Table 8 Affected Read Modify Write Instructions Hex Code INC dir 05 DEC dir 15 ANL dir A 52 ANL dir data 53 ORL dir A 42 XC886 888LM Series AC 21 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations Table 8 Affected Read Modify Write Instructions Hex Code ORL dir data 43 XRL dir A 62 XRL dir data 63 A dir C5 DJNZ dir rel D5 Workaround Use MOV instructions except MOV dir dir Hex Code 85 when writing to th
8. jump to Start reti return from interrupt Figure 3 Note The Boolean CLR and CPL instructions cannot be used to clear RI and TI bits of UART1 Refer to UART XC8 001 XC886 888LM Series AC 11 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations INT XC8 005 Write to IRCONO Blocks Interrupt Request of External Inter rupt 0 1 Any write read modify write or direct MOV to the SFR IRCONO will block an incoming interrupt request from external interrupt O or 1 even though the respective flag EXINTO or EXINT1 is set Workaround After any write to the IRCONO check read IRCONO the flags EXINTO and EXINT1 If any flag is set run the service routine otherwise proceed In case of enabled for interrupt the service routine should be duplicated one copy as the interrupt service routine with reti executed another copy in main code memory for software call with ret executed LIN XC8 001 Fast LIN BSL does not support baud rate of up to 115 2 kHz Fast LIN BSL supports only a baud rate of up to 57 6 kHz and not up to 115 2 kHz as described in the user s manual Workaround None OCDS 8 008 Watchdog Timer behavior during Debug with Suspend The WDT may be enabled for suspend stops counting in debug mode In this suspended state when the WDT is refreshed by writing WDTCON WDTRS the timer base counter which provide the clock to WDT is not refreshed to zero The effect is that on exiting Monitor Mod
9. All CRPR1 CB 0 6 All CRMR1 CC 0 6 All QMRO CD 0 6 All XC886 888LM Series AC 19 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations For example in the sample code below there are two MOV direct direct instructions that write the value of one register into another All the source and destination registers in these two instructions are from the direct address range 80 to FF The P1 DATA register is not one of the affected registers listed in the table above and therefore it is written with the correct value of the CC60SRL register On the other hand the CC60SRH register is one of the affected registers and therefore it is written with the wrong value of the B register Sample Code interrupt MUL A B MOV CC60SRL A MOV P1 DATA CC60SRL MOV CC60SRH B RETI Workaround Instead of using the MOV direct direct instruction use other instructions or an intermediate variable to write to the targeted register For example the two MOV direct direct instructions in the earlier sample code can be replaced with MOV direct A instructions hex code F5 Both the P1 DATA and CC60SRH registers will now be written with the correct source register values Sample Code interrupt MUL A B MOV CC60SRL A MOV Pl DATA A XCH A B MOV CC60SRH A RETI XC886 888LM Series AC 20 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations T2 XC8 001
10. Boot ROM or if the code to read the CD_STATC register is located in the D Flash XC886 888LM Series AC 9 36 Rel 1 6 28 02 2011 uai Errata Sheet Functional Deviations Being of interrupt structure 2 the interrupt request of UART1 is detected on the rising edge of a positive pulse The problem is that it may occur at some point in the application that any new UART1 interrupt request can no longer be detected after a return from interrupt reti due to service of earlier event s This happens when the following conditions are true 1 UART1 events are serviced by interrupt i e flags are checked and cleared only in the interrupt routine ISR 2 Either RI or TI is set at any one time throughout the ISR even while the other is cleared such that at least one of the flags is still set after reti causing the UART1 request line which is an OR function of the two flags RI and TI to remain set throughout the ISR and after reti Two example scenerios are illustrated in the following figure TI E g 1 RI UART1 request TI E g 2 RI UART1 request Figure 2 RI UART1 request I L 1 l 1 I 1 I 1 i T T ISR ehtered ISR xited 1 I 1 1 I 852 Lp T ij 1 1 This means any future UART1 RI or TI event is not able to cause a rising edge a
11. CON BB 1 XC88x XC878 CORDIC CD_STATC 0 1 88 878 MDU MDUSTAT BO 1 XC88x XC878 XC886 888LM Series AC 15 36 Rel 1 6 28 02 2011 Cifineon Errata Sheet Functional Deviations Table 7 Module Register SFR RMA Products Address P Affected SSC CONH 0 All Operating Mode UART1 C8 1 XC88x XC878 FDCON CC 1 XC88x XC878 T2 T2CON 0 All T21 T2CON 1 XC88x XC878 OCDS MMCR2 E9 1 All MMCR F1 1 All MMSR F2 1 All MMICR FA 1 All T2CCU CCTCON 0 1 XC878 COSHDW 0 2 XC878 COCON 0 3 XC878 CCOL C1 0 2 XC878 CCOH C2 0 2 XC878 CC1L C3 0 2 XC878 CC1H 0 2 878 CC2L C5 0 2 XC878 CC2H 0 2 XC878 CC3L C1 0 3 XC878 CC3H C2 0 3 XC878 CC4L C3 0 3 XC878 CC4H 0 3 XC878 CC5L C5 0 3 XC878 CC5H 0 3 XC878 XC886 888LM Series AC 16 36 Rel 1 6 28 02 2011 Cifineon Errata Sheet Functional Deviations Table 7 Module Register SFR RMA Products Address P Affected 6 CC63SRL 9A 0 0 All CC63SRH 9B 0 0 All MCMOUTSL 9E 0 0 All MCMOUTSH OF 0 0 All CC60SRL FA 0 0 All CC60SRH 0 0 All CC61SRL FC 0 0 All XC886 888LM Series AC 17 36 Rel 1 6 28 02 2011 Cifineon Errata Sheet Functional Deviations
12. CON BRK FDCON EOFSYN and FDCON ERRSYN to 0 It is also recommended to toggle the BCON BRDIS bit after the reception of each complete LIN frame to avoid a wrong Break field detection in noisy environments i e spikes on the LIN bus XC886 888LM Series AC 33 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints OCDS XC8 H002 Any NMI request is lost on Debug entry and during De bug All NMI events are disabled while in debug mode This has two main effects 1 On debug entry any pending NMI request will be lost although the status flag remains set The probability of losing an NMI request in this way is very low since NMI always has the highest priority to be serviced 2 Any NMI event that occurs during debugging is not able to generate an NMI request event interrupt is lost although the status flag will be set It is normally not critical that on exit from debug mode the CPU must service NMI requests that had occurred while in debug mode The fact that the debug system is not specified to support NMI interrupt while in debug mode makes the above trivial As precaution avoid starting any debug session while expecting an NMI event PIN XC8 H001 Current over GPIO pin must not source Vppp higher than 0 3V When ppp is not powered on the current over a GPIO pin has to be limited in such a way that Vppp Vssp lt 0 3V This prevents the supply of the device via the ESD diode between the GPIO pin
13. CONO register will cause the device to go into power down mode When this bit is set flash memory will start the powered down sequence immediately If a wakeup event happens before flash powers down completely the device will not be able to wake up normally The flash memory requires the following maximum time to complete power down 160 usec if the flash is in program or erase mode 350 nsec if the flash is in read or idle mode XC886 888LM Series AC 14 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations Workaround None SYS XC8 001 MOV direct direct instruction might cause a wrong value to be written to the destination register The MOV direct direct instruction hex code 85 that access registers direct address ranging from 80 to FF does not write the correct value of the source register to the destination register if the destination register is a register listed in the table below The source register can be any register from the direct address range 80 to FF Table 7 Module Register SFR RMA Products Address P Affected SCU IRCONO B4 0 0 XC88x XC878 IRCON1 B5 0 0 XC88x XC878 IRCON2 B6 0 0 XC88x XC878 IRCONS3 B4 0 3 All IRCON4 B5 0 3 All NMISR BC 0 0 XC88x XC878 FDCON E9 0 0 XC88x XC878 PMCONO B4 0 1 XC88x XC878 OSC CON B6 0 1 XC88x XC878 PLL CON B7 0 1 XC88x MISC_CON E9 0 1 XC88x XC878 WDT WDT
14. Cinfineon Errata Sheet Rel 1 6 28 02 2011 Device XC886 888LM Series Marking Step AC Package PG TQFP 48 64 This Errata Sheet describes the deviations from the current user documentation The module oriented classification and numbering system uses an ascending sequence over several derivatives including already solved deviations So gaps inside this enumeration can occur This Errata Sheet covers the following devices e XC886 888 6 8FF e XC886 888LM 6 8FF Table 1 Current Documentation XC886 888CLM User s Manual V1 3 Feb 2010 XC886 888CLM Data Sheet V1 2 Jul 2009 SAA XC886CLM Data Sheet V1 1 Aug 2010 SAL XC886CLM Data Sheet V1 0 May 2010 Each erratum identifier follows the pattern Module Arch TypeNumber Module subsystem or peripheral affected by the erratum e Arch microcontroller architecture where the erratum was firstly detected Al Architecture Independent detected on module level CIC Companion ICs TC TriCore 32 bit X 1 XC2000 16 bit XC8 XC800 8 bit none C16x 16 bit XC886 888LM Series AC 1 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Type none Functional Deviation P Parametric Deviation H Application Hint D Documentation Update Number ascending sequencial number within the three previous fields As this sequence is used over several derivatives including already solved deviations gaps inside this enumeration can occur Note
15. NMI interrupt flags are found Consider the following NMI interrupt service routine pseudo code and scenerio where a NMI interrupt source A event leads to interrupt request of the NMI node and CPU vectors to the NMI interrupt routine Meanwhile NMI interrupt source B and its flag becomes active any time in the duration indicated by T entry point of interrupt node service routine 4 reti return from interrupt Figure 6 XC886 888LM Series AC 29 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints In this case NMI flag B will be cleared as a standard procedure by the NMI interrupt routine in the current service However the pending interrupt request for the NMI node remains activated after RETI as it is only cleared by hardware when CPU acknowledge the NMI interrupt and vectors to the NMI service routine This leads to following servicing of the NMI interrupt node again but potentially no active NMI flag is found i e dummy NMI interrupt service The point to note is that the NMI interrupt source B is not lost as it was actually serviced in the current service of the NMI interrupt node The recommendation is to ignore these dummy NMI interrupt vectoring INT XC8 H005 Not all Flags are qualified for clearing Pending Interrupt Request For interrupts of structure 2 qualified event status flags are used for clearing any pending interrupt request to the core An event flag is qualified as long as th
16. e bits FDEN and FDM in UART1 FDCON SFR XC886 888LM Series AC 22 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Deviations from Electrical and Timing Specification 3 Deviations from Electrical and Timing Specification XC886 888LM Series AC 23 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints 4 Application Hints ADC ALHO001 Arbitration Mode with disabled Arbitration Slots In arbitration mode bit ARBM 1g in register PRAR the arbiter only runs while at least one conversion request is pending otherwise it waits in an idle state for a request to become active This leads to a constant and reproducible latency from an incoming request to the conversion start Each request source x x 0 1 can be individually selected via the Arbitration Slot Enable bits ASENx in register PRAR to take part in the arbitration round However if a disabled request source bit ASENx 0g has a pending request the related conversion is not started but the arbiter does not stop and wait As a result the latency for requests generated on other arbitration slots is not constant To avoid this effect first disable the request generation of the respective source by setting bit ENGT Og in the corresponding register QMRO or CRMR 1 before disabling the arbitration slot via ASENx 0g ADC XC8 H001 Arbitration mode when using external trigger at the se lected input line REQTR If an external trigger is expected at
17. e event is enabled for interrupt By this means as long as all qualified flags of the node are cleared any still active pending interrupt request to the core will be cleared by hardware However with existing implementation not all event flags are qualified for clearing the pending interrupt request to core These flags are listed in the following table corresponding to the interrupt node the flag belongs to Table 9 Interrupt Vector Assignment Unqualified Flags Node Address Belonging to Node NMI 0073 Watchdog Timer NMI NMIWDT PLL NMI NMIPLL Flash NMI NMIFLASH OCDS NMI NMIOCDS VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XC886 888LM Series AC 30 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints Table 9 Interrupt Vector Assignment Unqualified Flags Node Address Belonging to Node XINTR5 002B LIN EOFSYN ERRSYN XINTR8 00434 External Interrupt 2 EXINT2 CORDIC EOC UART1 RI TI UART1 Fractional Divider NDOV Normal Divider Overflow MDU IRDY IERR XINTR9 004B External Interrupt 3 EXINT3 External Interrupt 4 EXINT4 External Interrupt 5 EXINT5 External Interrupt 6 EXINT6 Note Some events e g TF2 EXF2 of Timer 2 Timer21 NDOV of UART NDOV RI and TI of UART1 do not have separate interrupt enable apart from its interrupt node enable These event flags are therefore always qualifi
18. e in user mode the WDT may count a little shorter to overflow This shortened time is less than one WDT count XC886 888LM Series AC 12 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations Workaround None This WDT behavior occurs only during debug where WDT is enabled for suspend PIN XC8 005 Glitches on TCK when switching between clock sources The JTAG clock input has multiple sources two in XC886 variants P0 0 P2 0 and three in XC888 variants P0 0 P2 0 P5 6 Unexpected glitches may occur when the clock source is switched from 1 0 0 to P2 0 or 2 P2 0 to PO 0 or 3 P5 6 as a normal GPIO pin to TCK These glitches may potentially bring the system into an undefined state Workaround To prevent the occurrence of such glitches during the clock switching the following 2 workarounds are proposed 1 The user has to follow a specific sequence when carrying out any of the above clock switching When switching from 0 to P2 0 or vice versa the user must first switch the clock source to P5 6 before proceeding to switch to the desired clock source Similarly when switching P5 6 from a normal GPIO pin the user must first assigned to either 0 0 or P2 0 before switching from this clock source to P5 6 Valid only for XC888 variants 2 The user has to configure all the TCK pins as input and drive them to either all zero or all one before switching the clock source fro
19. ectoring mode the Error bit of register CD STATC is set immediately on detecting overflow When detected between iterations the Error status is not held internally till the end of the calculation As the Error bit is defined such that it is cleared on any read access to the register e g JB BSY SW checking of the Error bit only at the end of calculation may miss to detect an overflow error condition Workaround Especially in linear vectoring mode if the error condition setting of Error bit must be detected any read access should be done on the whole CD STATC register e g MOV and the Error bit checked in all read instances CD XC8 002 Data Fetch to CD STATC Register may capture an incorrect error status The error bit CD STATC ERROR is defined such that the bit is cleared on any read access to the register Therefore it is necessary to perform a data fetch on the register and check for the error bit in order not to lose the error status However if the CPU inserts a wait state during the execution of the read instruction from the Flash and extends the read access by another two clock cycles multiple read accesses will be performed on the CD STATC register and the error bit will be cleared by the time the CPU performs the final read As a result the CPU does not capture the correct error status There is no problem if the code to read CD STATC register is located in the XRAM Workaround The following workarounds can be used
20. ed if the interrupt node is enabled Consider the case where an enabled interrupt node is shared by more than 2 events and where at least two of the events A and B are enabled for interrupt while at least one event C is not enabled for interrupt In this case flag C is one of the flags listed in above table While the interrupt routine is already running due to event A having occurred event B and C occurs any time in the duration indicated by T XC886 888LM Series AC 31 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints entry point of interrupt node service routine check flag A 4 clear flag A check flag B clear flag B reti return from interrupt Figure 7 This sets the pending interrupt request while flag B is set Although event B is serviced and flag B is cleared in the following service routine on return from interrupt the pending interrupt request remains activated This is because event C is not enabled for interrupt and therefore flag C is neither checked nor cleared in the interrupt routine while flag is not qualified This leads to following servicing of the interrupt node again but potentially no active flag is found i e dummy interrupt service To prevent such dummy interrupt vectoring on the above listed interrupt nodes do not use mixed interrupt servicing and polling scheme i e enable all events of the node for interrupt if interrupt node is enabled Otherwise if mixed interru
21. equivalent to 2 CCLK cycles for execution such as INC dir are executed from memories without any wait states the actual write to the destination is delayed by the internal bus for up to one CCLK cycle This means that even though the CPU completes the instruction execution after 2 CCLK cycles the write through the internal bus may take effect only after a further CCLK cycle The list of affected read modify write instructions is shown below Table 10 Mnemonic Hex Code Bytes No of CCLK cycles without wait states INC dir 05 2 2 DEC dir 15 2 2 ANL dir A 52 2 2 ORL dir A 42 2 2 XRL dir A 62 2 2 1 Applicable also to Flash memory with parallel read feature XC886 888LM Series AC 35 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints Table 10 Mnemonic Hex Code Bytes No of CCLK cycles without wait states XCH A dir C5 2 2 CLR bit C2 2 2 SETB bit D2 2 2 CPL bit B2 2 2 SYS XC8 H004 Switch PLL to prescaler mode before a WDT reset A WDT reset does not reset the clock system If a WDT reset occurs while the PLL is in base mode PLL CON OSCDISC 1 the system will be held in reset until the next power on or hardware reset This is because the system requires the PLL to be locked PLL CON LOCK 1 or in the prescaler mode CON OSCDISC 0 PLL CON VCOBYP 1 before the reset can be released If the above behaviour is not desired it i
22. m one pin to another PIN XC8 006 Port 4 pads excluding P4 2 toggle once upon a power on or hardware reset All Port 4 pads excluding P4 2 are stated to have Hi Z as the reset state However these pads are pulled up internally when a power on or hardware reset is asserted They are returned to the Hi Z state with internal pull ups XC886 888LM Series AC 13 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations disabled only after the reset is deasserted The result is that these pads toggle once upon a power on or hardware reset Workaround There are two proposed workarounds 1 Implement external pulls on the external circuitry to prevent the toggle of the Port 4 pins In case low level is required strong external pull downs in the range of 2 kO to 3 kQ must be used 2 Use alternate pins of the same function from the other ports For example for motor control applications which make use of the CCUG output pins Port 3 pins can be used instead PIN XC8 007 External pull up device is required on MBC pin to enter user mode Although MBC pin is specified to be pull up in the reset state an external pull up device is still required to enter user mode Workaround Implement external pull up in the range of 4 7 KQ to 100 on the external circuitry for MBC pin Alternatively MBC pin could be tied to high PM 8 003 Wake up triggered before power down sequence completed Setting the PD bit in PM
23. nd therefore not able to trigger an interrupt request to the core as if the UART1 interrupts had been disabled until both RI and TI flags are cleared at some time The clearing of flags would have to be done by user s code XC886 888LM Series AC Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations additionally outside of the UART1 interrupt routine which is however normally not feasible with an interrupt service scheme Note This condition affects only the detection of UART1 interrupt events RI and TI It does not block the detection of other interrupt events belonging to the same interrupt node Workaround There are two suggested workaround 1 If other events of interrupt node XINTR8 EX2 need not be enabled for interrupt disable this interrupt node and use software polling of the flags instead 2 Before return from interrupt check again if RI or TI is still set due to new request since the last check If so jump and execute the ISR routine from start Exit only when all flags are checked to be cleared However dummy interrupt of the node may occur after return from interrupt and should be ignored Another drawback is if UART1 events are occurring at high rate the CPU may be stuck in the service routine of the UART1 interrupt for a long time entry point of interrupt node service routine Start check flag RI m flag RI flag flag Finish if RI or TI is set
24. pt servicing and polling scheme is to be used ignore these dummy interrupt vectoring LIN XC8 H001 LIN BRK field detection logic Based on the hardware implementation the maximum number of bits in the BRK field must follow the formula 4095 Maximum number of bits in BRK field Baud Rate x Sample Frequency XC886 888LM Series AC 32 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints PCLK Sample Frequency BGSEL 8x2 For example if LIN baudrate is 19 2kbps BGSEL 0 and CPU frequency is 24MHz the maximum number of bits in BRK field would be 19 2k x 4095 24M 8 26 2 bits If the maximum number of bits in the BRK field exceeded the internal counter will overflow which results in baudrate detection error Therefore the user is advised to choose the appropriate BGSEL value for the required baudrate detection range The calculated value above does not consider sample error and transmission error nevertheless it can be used as a guideline LIN XC8 H002 LIN Break Synch field detection The LIN Break Synch field detection is default enabled after every reset BCON BRDIS bit 0 However to ensure the first standard LIN frame can always be detected it is recommended to initialize the detection logic in the user code before receiving the frame This is through the following two steps 1 Toggle BCON BRDIS bit set the bit to 1 before clearing it back to 0 2 Clear the three status flags FD
25. s recommended to switch the PLL to prescaler mode and with the on chip oscillator as the input clock source OSC CON OSCSS 0 whenever a WDT prewarning is entered XC886 888LM Series AC 36 36 Rel 1 6 28 02 2011
26. sequence A manual check on the Flash data or the carry flag is necessary to determine if the program or erase operation is successful INT XC8 H003 Interrupt Flags of External Interrupt 0 and 1 External interrupt O and 1 may individually be selected via respective bits EXINTx in EXICONO register to request interrupt on falling edge rising edge both edges or to bypass the edge detection XC886 888LM Series AC 27 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints Panes eb oH x EXINTO e 10 o e __ Fm IRCONO 0 oT X TCON 1 0003 ft How EXO H IENO O Br EXINTO TCON O to EXICONO 0 1 CPU o H EXINT1 Hen te EINT1 X e Fel IRCONO 1 TCON 3 EX1 0013 H qJ IENO 2 TCON 2 EXINT1 EXICONO 2 3 EA IENO 7 Figure 5 Edge detection is done in the system unit If enabled an active event will set the EXINTx flag and correspondingly set the IEx flag in TCON It should be noted that after any external interrupt x event flag EXINTx must be cleared In case of falling edge as active event this allows any future active event to be able to set the as interrupt request In case of low level as active event this prevents unintended recurring triggering of interrupt request Besides the above notes the following
27. should be noted on the behavior regarding setting and clearing of the external interrupt x x 0 or 1 flags applicable to both edge and bypass edge detection modes Setting of External Interrupt x Flags 1 The flag TCON will be set in all modes selectable via EXICONO register 2 Flag IRCONO EXINTx will be set in all modes as long as an active edge is detected flag EXINTx will not be set for low level as active event XC886 888LM Series AC 28 36 Rel 1 6 28 02 2011 Gafineon Clearing of External Interrupt x Flags 1 2 3 Errata Sheet Flag is cleared automatically by hardware wh vectored to Flag EXINTx has to be cleared by software Clearing one external interrupt x flag will not clear Application Hints en the interrupt is being the other Especially clearing flag EXINTx will not clear the flag Being of interrupt structure 1 the flag IEx is the request polled by the CPU for interrupt servicing Therefore user has to take care to clear the flag 11 Ex before switching from SW polling method to enabling the external interrupt x node to prevent potential dummy interrupt request select in EXICONO register Always clear both EXINTx and IEx flags before if changing the trigger INT XC8 H004 NMI Interrupt Request With No NMI Flag Set It might occur in the application that sometimes NMI interrupt requests are serviced but no active
28. the selected input line REQTR to trigger a pending request the arbitration mode should be set PRAR ARBM 1 where the arbitration is started by pending conversion request This selection will minimize the jitter between asynchronous external trigger with respect to the arbiter and the start of the conversion The jitter can only be minimized while no other conversion is running and no higher priority conversion can cancel the triggered conversion In this case a constant delay no jitter has to be taken into account between the trigger event and the start of the conversion XC886 888LM Series AC 24 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints BROM XC8 H001 SYSCONO RMAP handling in ISR The ISR has to handle SYSCONO RMAP correctly when Flash user routines provided in the Boot ROM are used together with the interrupt system Any ISR with the possibility of interrupting these user routines has to do the following in the interrupt routine save the value of the RMAP bit at the beginning restore the value before the exit This is to prevent access of the wrong address map upon return to the Flash user routine since the RMAP bit may be changed within the interrupt routine The critical point is when Flash user routines sets RMAP to 1 and the interrupt occurs that needs RMAP at 0 in the ISR Please note that NMI is an interrupt as well BROM XC8 H002 Obtain Product Derivative Information With Chip Iden tifica
29. tion Number The chip identification number is an unique 4 byte data that is assigned to each product derivative based on the following differentiations product variant type e device step Therefore to identify a product derivative the number can be obtained and matched to a list of product derivatives and their corresponding numbers which can be found in the latest product data sheet The number is read using the in application user subroutine GET CHIP INFO or BSL mode A Description on the usage of GET CHIP INFO and BSL mode can be found in the latest user s manual XC886 888LM Series AC 25 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints CCUG XC8 H002 CCUG PM event in center aligned mode After detecting a period match PM A in centre aligned mode T12 counts down from PM 1 as shown below 0x201 0x200 0x200 PMA PMB Ox1FF Ox1FF Period Matc PM Ox1FE Ox1FE Figure 4 Counting sequence of T12 center aligned mode This means a second PM event PM B will occur during the counting down If ADC is triggered externally via ETRx2 T12PM it will be triggered twice in succession Depending on how real time the application code is running as well as the T12 count rate and ADC conversion rate the application could observe two ADC interrupts once at PM A and once at PM B To avoid triggering twice the ADC interrupts it is suggested to use ETRx6 from m
30. to avoid incorrect data fetching from the STATC register The PUSH dir and POP dir instructions can be used to read the CD STATC register in all conditions XC886 888LM Series AC 8 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Functional Deviations The following MOV instructions can be used to read the CD STATC register if the P Flash parallel read mode is enabled default and the MOV instruction is placed an odd address of the P Flash MOV Rx dir where x 0 7 MOV Rn dir where n 0 or 1 MOV dir The following MOV instruction can be used to read the CD STATC register if the P Flash parallel read mode is enabled default and the MOV instruction is placed an even address of the P Flash MOV dir dir INT XC8 004 Unable to Detect New Interrupt Request if Any One of Timer 2 Timer 21 UART1 Interrupt Flags Is Not Cleared Unexpectedly Note In the current device step the bug in Timer 2 and Timer 21 has been fixed Therefore the errata is applicable only UART1 As illustrated in the simplified figure the UART1 interrupt flags RI and TI are combined as one interrupt request output These flags are located within the UART 1 kernel with a single interrupt request line as output from the kernel UART1 gt interrupt detection Figure 1 1 The workaround does not work if the P Flash parallel read mode is disabled through the parallel read disable subroutine in the
31. ulti channel mode instead of ETRx2 as the trigger source for ADC Additional initialization are as follows Configure MCMCTR SWSEL 101 Transfer on T12 period match e Configure MCMCTR SWSYN 00 Direct transfer e Write to MCMOUTSTL CF To enable multi Channel PWM pattern on CC6x and COUT6x Note Independent of the external trigger the CCUG internal triggers based T12 PM e g T12 PM interrupt or shadow transfer are only activiated once while T12 is counting up XC886 888LM Series AC 26 36 Rel 1 6 28 02 2011 Infineon Errata Sheet Application Hints FLASH XC8 H002 Programming to invalid P Flash address range 5000 to 5FFF may corrupt existing P Flash data For the 24 KByte Flash variant writing to the unavailable program memory addresses from 5000 to 5FFF can lead to corruption of existing data in the valid P Flash addresses from 4000 to 4FFF The user has to make sure not to write to the addresses from 5000 to 5FFF FLASH XC8 H003 Verify if a Flash program or erase operation is suc cessful The Flash memory cannot be programed or erased under a PLL loss of lock condition In the Boot ROM program and erase routines the Boot ROM checks that the PLL NMI flag NMISR FNMIPLL is zero to ensure no PLL loss of lock has occurred before starting the program or erase sequence If the PLL NMI flag is set the Boot ROM will set the carry flag PSW cy and exit the routine without starting the program or erase
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