AD9680-1000EBZ - Digi-Key
Contents
1. Rev 18 Jun 2014 12 34 Page 6 File Config Help oO oF at CHIP PORT CFO LSB Fist Controllor vo akso ss aa from CHIF ID 4 5 Unknown CHIP GRADE 6 Unknown Data Path Soft Reset Figure 8 Sending a Soft Reset to the AD9680 4 The JESD204B quick configuration and Lane Rate registers are available in the ADCBase3 tab Set the Lane Rate setting register Ox56E to Maximum Lane Rate File Contig Help Masmum Lane Rate Mode Seral Line Rate must be gt 6 25 Gbps and lt 12 5 Gbps Figure 9 Setting the JESD204B Lane Rate 5 Set the JESD204B Quick Configuration register 0x570 For 1OOOMSPS operation with no DDCs the values for L M F are 4 2 1 Rev 18 Jun 2014 12 34 Page 7 By sPicontroller 3 0 15 3905 USB Ezusb 0 CS 1 AD9680_ 14bit_1 256SspiR2Si cfg ADI680_14Bit_ File Config Help wes EB 0 oE Global ADCBase0 ADCBase1 ADCBase2 ADCBase3 ADCBased ADCBase5 ADCA ADCB Maximum Lane Rate Mode Senal Line Rate must be gt 6 25 Gbps and lt 12 5 Gbps PLLSTATUS REG S6F JESD2046 LINK CTRL REG 5 1 4 JESD2O046 Standby Mode Read eros for all converter samples JESD204B QUICK JESD2046 Serial Tail Bit PN Enable CONFIGURATION REGIS 0I M JESD204B Serial Test Sample Enable Number of Lanes lv JESD2046 Serial Lane Synchronization Enable 4 JESOZO46 Seral Initial Lane Alignment Sequence Mode Number of Converters Enabled r JE2. Figure 6 ADC Data Capture Figure 6 Changing the ADC Capture Settings 5 On the General tab make sure the clock frequency is set to LOOOMHz or other clock frequency The FFT capture length may be changed to 131072 128k or 262144 256k per channel The ADs7 V1 FPGA software supports up to 2M FFT capture 1M per channel Rev 18 Jun 2014 12 34 Page 5 ADC Data Capture Settir General Capture Board Device Evaluation Boards Output Data Capture ADSTV1 SBCEOEF 3936 000008 Data Length Devi Ch Data B21 44 EVICE AD 9680 Ch B Data 62144 Clock Frequency MHz li ood Select Data Ich A Data Figure 7 Setting the clock frequency and Capture length 6 Click on the Capture Board tab and browse to the ad9680_ads7v1_09242013_0949am bin file Click the Program button The FPGA_DONE LED should illuminate on the ADS7 V1 board indicating that the FPGA has been correctly programmed The bin file is available at the ftp site ftp ftp analog com pub HSC_ADC Apps ADs7 V1_packet Firmware ad9680_ ads7v1_09242013 094 9am bin 7 On the Device tab Make sure that Enable Alternate REFCLK option is unchecked 8 Click OK SPiController Setup 1 Click Start All Programs Analog Devices SPiController SPlController 2 Select the AD9680 14Bit_1 25GSspiRO3 cfg if prompted 3 In the Global tab under the Generic Read Write section write 0x81 to register 0x000 This issues a Soft reset for the DUT
3. This option allows the buffer current to change to enable better harmonic performance at different frequencies At high analog input frequencies the buffer current may need to be increased to optimize harmonic distortion performance HD2 HD3 Keep in mind that at high frequencies the performance is also jitter limited So increasing the buffer currents may lead to diminishing returns with higher power consumption Refer to the datasheet to understand the relationship between livp s and Buffer Current Setting 3 Analog Input Differential Termination 16 This sets the input termination Recommended settings are 500 200 100 50 ohms At lower termination settings the harmonic distortion performance may show improvement but the analog input signal amplitude will be reduced 4 Input Full Scale Range 25 At high input frequencies in order to preserve the linearity of the input buffer it may be beneficial to reduce the input full scale range in order to get more harmonic distortion performance This in turn may negatively affect the SNR of the ADC Obtaining an FFT 1 Click the Run button in VisualAnalog you should see the captured data similar to the plot shown in Figure 12 Rev 18 Jun 2014 12 34 Page 9 File Aale mla elr E P RE E Ch A FFT Denies SADS 50M 100M 150M 200M 250M 300M 350M 400M 450M Date 4 29 2014 Time 10 22 01 4M Sample Frequency 1000 MHz Samples 65536 SNA 65 24 dB SNAFS 66 242 dB SINAD 65 17 d
4. ANALOG DEVICES One Technology Way P O Box 9106 Norwood MA 02062 9106 Tel 781 329 4700 Fax 781 461 3113 www analog com EVALUATING THE AD9680 ANALOG TO DIGITAL CONVERTER Preface This user guide describes the AD9680 evaluation board AD9680 1000EBZ which provides all of the Support circuitry required to operate the ADC in its various modes and configurations The application software used to interface with the devices Is also described The AD9680 data sheet provides additional information and should be consulted when using the evaluation board All documents and software tools are available at www analog com hsadcevalboard For additional information or questions send an email to highspeed converters analog com AD9680 1000EBZ Ref Clock E Sample Clock Figure 1 AD9680 1000EBZ Evaluation Board Rev 18 Jun 2014 12 34 Page 1 OSOS Typical Measurement Setup Ref Clock LS 4 a Teh ae i Le 4 WEEET zE T i p Gi sample Cloch o Figure 2 Evaluation Board Connection AD9680 1000EBZ on Left and ADS7 V1EBZ on Right Features e Full featured evaluation board for the AD9680 e SPI interface for setup and control e Wide band Balun driven input e No external supply needed Uses 12V 1A and 3 3V 3A supplies from FMC e VisualAnalog and SPI controller software interfaces Helpful Documents e AD9680 Data Sheet e ADS7 V1EBZ evaluation kit ADS7 V1EBZ e AN 905 Application N
5. Bc DC Frequency 0 MHz DC Power 51 345 dBFS Fund Frequency 172 117 MHz Fund Power 1 002 dBFS Fund Bins 41 Harm 2 Power 88 839 dBc Harm 3 Power 90 57 dBc Harm 4 Power 87 034 dBc Harm 5 Power 91 916 dBc H Harm amp Power 102 326 dBc Worst Other Frequency 270 839 MHz Worst Other Power 89 222 dBFS Noise Hz 153 232 dBFS Hz Average Bin Moise 111 397 dBFS THD 83 129 dBc SFORA 87 005 dBc Tf2MHz S004 Figure 12 AD9680 1000 FFT at 170MHz Analog Input 2 Adjust the amplitude of the input signal so that the fundamental is at the desired level Examine the Fund Power reading in the left panel of the VisualAnalog FFT window 3 To save the FFT plot do the following Float Form Click on the Float Form button in the FFT window Figure 13 Floating the FFT window 2 Click on File Save Form As button and Save it to a location of choice Graph AD9680 FFT Save ik Nal Page setup Print Exit Figure 14 Saving the FFT Rev 18 Jun 2014 12 34 Page 10 OSOS Troubleshooting Tips FFT plot appears abnormal e If you see a normal noise floor when you disconnect the signal generator from the analog input be sure you are not overdriving the ADC Reduce input level if necessary e In VisualAnalog Click on the Settings button in the Input Formatter block Check that Number Format is set to the correct encoding twos compliment by default Repeat for the ot
6. G 58 50 coaxial cable to connect the signal generator output to the ADC Evaluation Board For best results use a narrow band band pass filter with 50 Q terminations and an appropriate center frequency ADI uses TTE Allen Avionics and K amp L band pass filters 9 On the ADC evaluation board use a clean signal generator with low phase noise to provide an input signal for channel B to P202 Use a shielded RG 58 50 Q coaxial cable to connect the signal generator output to the ADC Evaluation Board For best results use a narrow band band pass filter with 50 Q terminations and an appropriate center frequency ADI uses TTE Allen Avionics and K amp L band pass filters Visual Analog Setup 1 Click Start All Programs Analog Devices VisualAnalog VisualAnalog 2 On the VisualAnalog New Canvas window click ADC Dual AD9680 Rev 18 Jun 2014 12 34 Page 4 VisualAnalog New Canva e New Existing Recent Categories Templates J AD9613 O AD9627 i AD3627 11 Average FFT Two Tone Average 3 yj 409628 Two Tone C ADSESS af AAD96386 af ADQBAD O ADGA of ADIE44 O ADGBAS Open Cancel aaaalFigure 4 Selecting the AD9680 canvas 3 If VisualAnalog opens with a collapsed view click on the Expand Display icon see figure 5 a n in Se if Expand Di J Figure 5 Expanding Display in VA 4 Click the Settings button in the ADC Data Capture block as shown in
7. SD2O46 Seral Frame Alignment Character Number of Octets Frame Insertion FACI Disable r JESD2046 Serial Transmit Link Power Down active high Figure 10 Setting the JESD204B Quick Configuration Register 6 After the quick configuration setting is completed the PLL Lock Detect register 0x56F will read 0x80 to denote a lock The SPIController interface will show a 1 to denote a lock 7 Toggle the JESD204B link by checking and then unchecking the JESD204B Serial Transmit Power Down box 8 Individual Channel control for ADC A and ADC B are done using the Device Index Register 0x008 Global ADCBasel ADCBase1 ADCBase2 ADCBase3 ADCBase4 at CHIP PORT CFG 0 DEY ICE INDE 8 ADC IQ Reset DUT VE CHIF ID 4 5 c Read Fi Unknown CHIP GRADE 6 SPI CONFIG B 1 SPI Single Instruction Read Enable Unknown Data Path Soft Reset Chip Die Revision P Read CHIP TYPE REG 3 Read in the Global tab l cunno imocerm mi O C Figure 11 Device Index Rev 18 Jun 2014 12 34 Page 8 LL for ADC Channel A and Channel B 9 Under ADC A and ADC B tabs the options for Channel A and B are listed Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate Only the following options need to be operated with 1 Chip Configuration Register 2 This option allows the channel to be powered on 2 Buffer Current Setting 18
8. e Standard B USB port of the ADS7 V1EBZ board to the PC with Rev 18 Jun 2014 12 34 Page 3 i OSOS the supplied USB cable 3 Turn on the ADS7 V1EBZ 4 The ADS7 V1EBZ will appear in the Device Manager as shown in Figure 3 f a Device Manager File Action View Help p e E mi 0G a lE ADI Development Tools kF Analog Devices ADST V1 Batteries 3 Bluetooth Radios Computer a ControlVault Device a Disk drives Sa Display adapters Figure 3 Device Manager showing ADS7 V1EBZ 5 If the Device Manager does not show the ADS7 V1EBZ listed as shown in Figure 2 unplug all USB devices from the PC uninstall and re install SPIController and VisualAnalog and restart the hardware setup from step 1 6 On the ADC evaluation board provide a clean low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm This is the ADC Sample Clock 7 On the ADC evaluation board provide a clean low jitter clock source to connector J804 and set the amplitude to 10dBm This is the Reference Clock for the gigabit transceivers in the FPGA The REFCLK frequency can be calculated using the following empirical formulae 10 Mx Norime xf S wt bps lane where L Lane lLineRate f ADC CLOCK Nprime 8 or 16 Default Nprime 16 REFCLK ou Decimalonkatio 8 On the ADC evaluation board use a clean signal generator with low phase noise to provide an input signal for channel A to P200 Use a shielded R
9. her channel e Issue a Data Path Soft Reset through SPIController Global tab as shown in Figure 15 D SPIController 3 0 15 3905 USB Ezusb 0 C31 AD9680_14bit_1 256 File Config Help a CO oE S Global ADCBase0 ADCEasel ADCBase2 ADCBase3 ADCBase4 CHIP PORT CFG 0 DEVICE INDE 8 ADC M LSB First Controller will also be updated from V A Reset DUT vB CHIP ID 4 5 Read R Unknown SPI CONFIG B 1 CHIF GHADE 6 SFI Single Instruction Read Enable Unknown Data Path Sott Reset Chip Die Revision fi Read CHIP TYPE REG 3 Read LPR REP Pee ek Pa ea m through SPiController Figure 15 Issuing a data path soft reset The FFT plot appears normal but performance is poor e Make sure you are using the appropriate band pass filter on the analog input e Make sure the signal generators for the clock and the analog input are clean low phase noise e If you are using non coherent sampling change the analog input frequency slightly or use coherent frequencies e Make sure the SPI config file matches the product being evaluated The FFT window remains blank after the Run button is clicked e Make sure the evaluation board is securely connected to the ADS7 V1 e Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated Rev 18 Jun 2014 12 34 Page 11 Oo O on the ADS7 V1 If this LED is not illuminated reprogram the FPGA thr
10. ote VisualAnalog Converter Evaluation Tool Version 1 0 User Manual e AN 878 Application Note High Speed ADC SPI Control Software e ADI SPI Application Note ADI Serial Control Interface Standard Rev 18 Jun 2014 12 34 Page 2 O SOS e AN 835 Application Note Understanding ADC Testing and Evaluation Software Needed e VisualAnalog ftp ftp analog com pub HSSP_SW VisualAnalog VisualAnalog_Setup exe e SPIController ftp ftp analog com pub adispi A2DComponents Install SPIController_Setup exe Design and Integration Files e ftp ftp analog com pub HSC_ADC Apps AD9680CE04B Design Support e FPGA BIN file ftp ftp analog com pub HSC_ ADC Apps ADs7 V1_packet Firmware ad9680 _ ads7v1 09242013 0949 am bin Equipment Needed e Analog signal source and antialiasing filter e Sample clock source e 12V 6 5A switching power supply such as the SL POWER CENB1080A1251F01 supplied with ADS7 V1EBZ e PC running Windows e USB 2 0 port e AD9680 1000EBZ board e ADS7 V1EBZ FPGA based data capture kit Getting Started This section provides quick start procedures for using the AD9680 1000EBZ board Configuring the Board Before using the software for testing configure the evaluation board as follows 1 Connect the AD9680 1000EBZ evaluation board to the ADS7 V1EBZ data capture board as shown in Figure 2 2 Connect one 12V 6 5A switching power supply such as the CENB1080A1251F01 supplied to P4 on the ADS7 V1EBZ board Connect th
11. ough VisualAnalog If the LED still does not illuminate disconnect the USB and power cord for 15 seconds Connect again and repeat the ADS7 V1 setup process e Make sure the correct FPGA bin file was used to program the FPGA e Be sure that the correct sample rate is programmed Click on the Settings button in the ADC Data Capture block in VisualAnalog and verify that the Clock Frequency is properly set General Capture Board Device Evaluation Boards Output Data Capture aD Sv BCEE F 3838 00000F Device aD gs0 Clock Frequency MIH z i ngg Select Data Eh 4 Data mon o Figure 16 Setting the correct clock frequeency in VisualAnalog e Ensure that the REFCLOCK is ON and set to the appropriate frequency e Restart SPIController VisualAnalog indicates that the FIFO capture timed out or FIFO not ready for read back e Make sure all power and USB connections are secure e Make sure that the REFCLOCK is ON and set to the appropriate frequency VisualAnalog displays a blank FFT when the RUN button is clicked e Ensure that the clock to the ADC is supplied Using SPIController ADCBaseO tab the status of the clock can be read out See figure 17 Rev 18 Jun 2014 12 34 Page 12 File Contig Help Ba 0 oE Sg Global ADCBase0 ADCBase1 ADCBase2 ADCBase3 ADCBase4 ADCBase5 ADC A ADL CHIP PIN CTRL AEG 40 External Power Down Pin Functionality Power Down Pin
12. r Fast Detect B Fin Functionality Disabled SYSREF CONTROL REG 120 Fast Detect A Pin Functionality ae vale l SYSREF Flag Reset Disabled m SYSREF Transition Selection CLOCK DIVIDER CONTROL REG 106 Low to HIGH Figure 17 Clock lanut S armnle Clack Dirazan Fastin Detection Status Register e Ensure that the ADC s PLL is locked by checking the status of the PLL lock detect register 0x56F This can be done using SPIController Analog Devices Inc All rights reserved Trademarks and E ARIAS registered trademarks are the property of their respective owners a Tail Rev 18 Jun 2014 12 34 Page 13
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