FADC System
Contents
1. D 2 1 Power OD ERR ERR EE ARE 5 2 1 1 Load Iber mug csv fet EL 2 1 2 Select Clock SOUPrCES sade cara Reset FADE TE E ae ia 6 2 2 Modes of S ce Normal data taking 6 2 2 2 External test mode nibble or transparent mode 6 2 2 3 Internal test ModE 6 2 3 VME 7 2 4 VME command notation 7 Addresses and coding 8 3 1 VME base addresses 3 2 Mechanical coding 9 s fe Cure bua ar 9 i yy TF rriodules ea ym bdo d ARS d aria 9 PFALUGIE uan ERRARE REM A I 4 1 Address 11 4 2 Bus SyStemMS 11 4 2 1 EU Sr EW ee 11 4 2 2 Local Bus 1 17 1 0 12 4 2 2 1 Timing Control TIP A esas yee aeons 14 4 2 2 7 7 Event number and DAP Final Memory 14 4 2 2 1 2 Fast Or counter ext test mode start test pulse 14 4 2 2 2 Signal Processing 15 4 2 2 2 1 Read ADC event buffer 5 15 4 2 2 2 2 Read Write Pedestal Threshold memory 15 4 2 2 2 3 Read Fast Or trigger2. 15 4 2 2 2 4 Head hitmap L 1 5 76 22 29 Simple Processor 5 ove PS 16 4 2 3 Local Bus A21 A01 1 20 02 0 16 ese Ine eria el ens 16 4 2 4 Serial Bus 1 LO A21 A19 20 A18 1 and FRO SS da set ot a are IE ada qx VE ne xc EI CODO doa ve 17 4 2 4 1 Enable reset LO counters qu 4 2 4 2 Read LO 18 4 2 4 2 1 Read straight LO 18 4 2 4 2 2 Head VME system clock gated LO counter 78 4 2 4 3 Module interconnection links 18 4 2 5 Serial Bus 2 A21 A20 0 0 A19 A18 1 17 1 0 5 5 1 Address Space us ax RC e 5 2 General functions 21 5 2 1 Reset TTM or standalone 21 5 2 2 Clock Sole vei bre ea 22 5 3 L1 5 22 5 4 Standalone test functions es 5 4 1 Normal readout 5 23 5 4 2 Simulate external test mode 23 5 4 3 4 channel analog test output RI45 23 5 4 3 1 Automatic DAG 23 5 4 3 2 Set static DAC 24 5 5 PCI
3. N_START Data Address Ox14 write Initially the FADCTF boards should be switched to test mode A write operation to START generates a single ADCCLK5 window The width of this window is 200ns for the first 4 calls then 4x400ns 4x600ns The number of stored samples depends on 5MHz 1 1 1 1 2 2 2 2 or 20MHz 4 4 4 4 8 8 8 8 readout speed A write operation to N RESET resets the width of the clock window its initial state N RESET 5 4 3 4 channel analog test output NB The front panel input signal is always added to the DAC output 5 4 3 1 Automatic DAC ramp VME bus addr bits 31 30 29 28 11 10 9 8 7 6 5 4 3 2 1 0 offset from S_BASE Address 0 X Xx x x Data x x x r 0 disable automatic DAC ramp r 1 enable automatic DAC ramp 200ns per step during sequencer cycling 23 5 4 3 2 Set static DAC value VME bus addr bits 31 30 29 28 11 10 9 8 7 6 5 4 3 2 11 9 offset from S_BASE Ddc Daa x x x x x x x d 9 d d d static 7 bit DAC value requires DAC ramp disabled 5 5 PCI Link test input NB The cable has to be connected to the dedicated Sequencer input on the front panel The PCI Link data format is explained in the FADC User s Manual 5 5 1 Read MREQUEST BUSY and trigger status VME bus addr bit
4. 2 0 0 ut 0x3 THPD4 0x000 i 2 361 WRITE THRPD 54 2 0 0 1 waitl jwhile Ki 4 WRITE THRPD MEM 11 1 2 1 lt 254 1 WRITE THRPD VXIout 0x3 THPD 0 ti VXIout 0 3 THPD4 ii for 1 2 1 lt 254 1 4 0 00 2 361 WRITE THRPD MEM VXIout 0x3 THPD4 0 11 for 1 0 1 lt 256 1 2 it VXIin 0x3 THPD4 0x Hn da i 1 zdata amp 0x3 Vf 18 for 0 lt 16 READ THPD MEM printf 4d DATE j 8 tt for 1 0 1 lt 8 1 printf print n printf n n dot INININININININ SEQUENCER VXIout 0x3 TTM SEQU RW 4 0x20800000 TTM SEQUENCER VXIout 0x3 TTM SEQU RW 4 0x00830000 IP FADC System Belle SVD 2 0 readout BELLE cae HEPHYVIENNA Programmer s Manual VO 93 23 June 2003 DISCLAIMER The FADCTF is a complex electronic system which can be damaged if handled improperly In particular the following guidelines must be respected by the operator We decline any responsibility for errors damage or injury resulting from such misuse e Crate and modules belong together Do not use the VME modules FADCTF Sequencer PCI Link in a VME crate other than the one provided with the system The user defined V1 and 2 rails are used to supply special voltages to the FADCTF modules while the Sequencer board provides 12V which is required by the S
5. d 16 bit counter for VME system clock gated with LO pulses 4 2 4 3 Module interconnection links offset from F BASE 0x040006 0 o o o o o To o o ollo o o o o 1 1 Data Sl x x x x uj 0 disable output of upper half of module interconnection links 1 enable output of upper half of module interconnection links 0 disable output of lower half of module interconnection links 1 enable output of lower half of module interconnection links u 1 1 1 not allowed both outputs are disabled 4 2 5 Serial Bus 2 DAQ A21 A20 0 A19 A18 1 and 17 01 0 This serial bus is transparent to VME with the address lines 21 20 0 19 18 1 and A17 A01 0 and communicates with the DACs for the baseline shift of each input channel The 8 bit DACs used on the FADCTF boards are four Analog Devices DAC8841 with 8 outputs each They have serial address data and clock lines and need a strobe signal to set the output The graph below shows a load cycle where the DAC expects 4 address bits followed by 8 data bits and finally a load signal which actually executes the request 18 SDI X az X at X ao X pr X X os X pa X ps X X p XK Do gt DAC REGISTER LOAD gt CLK om LD Moreover the DACs can be set to the central value 0x80 when a signal is applied to the Preset input The address data clock and preset lines are
6. 17 00041 0 0 0009 10X0 jnopee1 2HIWOZ 1 nopeaa ZHIWS 0 LQ sjeuDis sjeuBls VA eAnisod 0 0 Sjeuuetp UOWWOD 93 SLIM YALNNOD H399l8 L HO LSVJ s1ejunoo 319 91 sseJppe ue es sseJppe ue es 14 0 ssaJppe lt 5 1 ANY SLIM ssaippe oDueiJ ssaJppe ue es 50319 Hdddn81N3 3 1 I o did 3 00061 0 0 0007 10X0 000910X0 93H 9dva 000S10x0 954 0002 10 0 000c 0X0 000110X0 000J00X0 000900X0 000P00X0 000400 0 000 00X0 000600X0 000 00 0 000900X0 000S00x0 000 00X0 000200 0 000100X0 13 4 2 2 1 Timing Control TIP1 4 2 2 7 7 Event number and DAP Final Memory VME bus addrdata bits 16 15 14 13 12 11 10 9 8 7 6 5 4 32 110 offset from F BASE 0 018000 1 1 0 9119 9 o Daa wie x x xt tx x x x x cjjx x b aj
7. 8 7 6 5 2 2 1 0 offset from S_BASE sr 0 sr 1 Sequencer reset fr 0 fr 1 FIFO reset clear i 0 external mode repeat distribute TTM signals i 1 internal mode generate all signals by VME triggered sequencer requires front panel switch in int left position 21 5 2 2 Clock source VME bus addr bits 31 30 29 28 11 10 9 8 7 6 5 4 3 2 1 9 offset from S_BASE Address O08 0 ofo offo 0 o 0 Data x x x x x x x x x x x x tm __ 0 ofo 0 0 0 0 0 1 1 0 wie x x x x x x Ix x x x x qj Clock source selection in external mode either set by switch or VME ttm 0 use TTM clock ttm 1 use front panel clock input Clock source selection in internal mode set by switch and VME q 0 use front panel clock input 4 1 use internal quartz oscillator The table below gives a summary which conditions must be met to select a specific clock source indicates that this mode is not possible The clock source is selected by one of ttm or q registers where the other one is irrelevant Example To select the quartz oscillator internal mode must be enabled both on the front panel switch and by VME and q set to 1 while ttm is don t care Front panel VME mode Clock source ADDR 0x08 O0xOc switch ADDR 0x00 TTM Front panel Quartz INT don t ttm O0 ttm 1 External i O ttm 0
8. A21 A19 0 A18 1 and 17 0 This serial bus is transparent to VME with the address lines 21 19 0 A18 1 and A17 A03 40 and communicates with the LO trigger processor This bus is used to read the LO trigger counters of which one simply counts the LO pulses while the other counts the VME clock gated with that LO trigger pulses Moreover the upper or lower half of the 16 lines of interconnection between FADCTF modules can be enabled for output NB This is only an additional measure to avoid shorting of two outputs Nevertheless the LO trigger processor Altera device must be properly configured such that the proper pins are defined as an output 4 2 4 1 Enable reset LO counters VME bus addr data bits 21 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 offset from F BASE 004000 0 o o 1 o o To o o 0 o o o o o To o 0 Daa gt x x x x x x x x disable both counters enable both counters o nw no reset static reset for both counters 17 4 2 4 2 Read LO counters 4 2 4 2 1 Read straight LO counter VME bus addr data bits 21 20 15 14 13 12 11 10 9 8 765413210 offset from F_BASE 0 040000 0 o o o o 0 o o oflo o o 0 o 0 d 16 bit counter for LO pulses 4 2 4 2 2 Head VME system clock gated LO counter offset from F BASE 0x040002 0 o o o o ollo o o ollo o o o o o 1
9. JTAG read IOP JTAG write DAPs JTAG read DAPs JTAG write TIP JTAG read TIP Heload Alteras from EEPROMs Strobe for general Reset Data Processors Timing Control L1 5 Final Memory Local Buses 1 amp 2 4 2 2 Local Bus 1 A17 A21 0 This bus contains of 16 bit wide address and data lines address strobe write strobe read strobe and the general reset lines It is accessible by VME with the address lines 1 7 21 0 and communicates with the Timing Control Unit TIP1 the Data Processors DAPx and the optional simple L1 5 Trigger Processor TRP1 A general reset is issued by a write operation to the VME address F_BASE T Ox3cO000 The table below shows an overview of all devices on Local Bus 1 details are given on the following pages 12 pesnun WYHALTV H399ls L S11 000210 0 0 1581 195 jeuBis ues 158 e qeue 10 1524 8 e qesip 0 519 1O 1se J ejqeue Ve3L1V IlOHLNOO uodn jejsuem lt 9IGesip 008810 0 Jequunu JUSAS 9SE9JOUI WLL 0 equunu esn Ve3ilclv 000810 0 000JL0X0 000910X0 011 deep iq 82 X p 000P10X0 1 dewy 5
10. a 0 use TTM event number a 1 use internal event number for test purposes b 0 b 1 increase internal event number useful only with a 1 c 0 normal DAP gt final memory transfer upon L1 5 accept c 1 disable DAP gt final memory transfer NO _AUTOREAD for test purposes in this mode the DAP event buffer FIFOs can be read out by VME using ME 0 otherwise the data would have been transferred to the Final Memory 4 2 2 1 2 Fast Or counter ext test mode start test pulse VME bus addrdata bits 16 15 14 13 12 11 10 9 8 7 6 5 42 2 1 0 offset from F_BASE Address 0 018800 0 YO pt o Of oO 0o 0o 0 00 x x x x x x x x x b x x x x e rd b aj a 0 disable Fast Or counters global line to all DAPs a 1 enable Fast Or counters b 0 zz b 1 reset Fast Or counters global line to all DAPs c 0 normal data taking c 1 enable external test mode nibble or transparent mode d 0 d 1 generate internal start signal and thus initiate storage of 128 ADC samples e 0 set test pulse LOW NB test pulse is AC coupled e 1 set test pulse HIGH NB The 16 bit values written to the this register can be read back on the same address intended for testing Local Bus 1 14 4 2 2 2 Signal Processing DAPx 4 2 2 2 1 Read ADC event buffer FIFOs VME bus adar bits 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 9 offset from F_BASE DAP2 0x001000 0 0
11. ttm 1 Internal i 1 q 0 q 1 5 3 TTM L1 5 accept The Sequencer can be used to generate L1 5 accept Reject signal which is sent to the TTM with a custom cable The pulse is then transmitted over the TTM Sequencer P2 backplane VMEbusaddrbis 31 30 29 28 11 10 9 8 7 6 5 4 3 2110 offset from S BASE oxsc 1 o ojo offo o 1 TIT 1 0 wie x x x x x x Ix x x x x rj 1 generate 11 5 accept pulse on pins 27 and 28 for test purposes ee 5 4 Standalone test functions Please note that the internal mode only becomes effective if the front panel Switch is set to int left position 5 4 1 Normal readout cycle s VME bus addr bits 31 30 29 28 11 10 9 8 7 6 5 4 3 2 110 offset from S BASE Address 004 0 ojo 0 0 o offo 1 o x x x x x x x sto 115 sta 0 sta 1 generate readout sequence including Fast Or EFT start 115 0 do not send L1 5 accept 11521 send L 1 5 accept after readout sto 0 loop readout sequence forever until sto 1 is set sto 1 stop after current readout sequence NB The sto signal can either be issued together with sta generating a single sequence or at any later time thus stopping after the current sequence has finished 5 4 2 Simulate external test mode VME bus addr bits 31 30 29 28 10 9 8 7 6 5 4 3 2 110 offset from 5_
12. 16 bit Fast Or trigger counter enable disable reset 1 NB Fast Or is a gate to the 20MHz clock for the counter thus counting depends on Fast Or width 15 4 2 2 2 4 Read hitmap L1 5 data VME bus adar bits 16 15 14 13 12 offset from F_BASE TRD2 0x019000 TRD3 0x01a000 TRD4 0x01b000 TRDS 0x01d000 TRD6 0x01e000 TRD7 0x01f000 2 serialized hitmap data for 11 5 trigger multiplexed from 4 input channels 4 x 128 bit deep FIFO 4 2 2 3 Simple L1 5 processor VME bus addr bits 16 7_6_5 4 offset from F_BASE 01000 1 1 1 0 x x x x xJ x x x Currently not implemented 4 2 3 Local Bus 2 A21 A01 1 A20 402 0 This bus also uses 16 bit wide data lines It is accessible by VME with the address lines A21 1 A20 A02 0 01 1 and communicates with the Final Memory Unit DACPR1 4 2 3 1 Final Memory VME bus addr data bits 21 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 offset from F_BASE DACPR1 020002 1 o To o o oJ o o o o o o 1 wie x x x x x x x c b Daa Tx x x x x x x x x x x fj Data read a 1 650 stosa e du du du du du du du du Data read a 1 b 1 ___ sto sta ch ch ch ch dd 44 dd dd dd dd dd 0 read FIFO empty flag a 1 read Final Memory FIFO 0 read bits 0 15 of Final Memory only with a 1 1 r
13. Altera We decline any responsibility for the consequences of such action 3 2 2 FADCTF modules The FADCTF modules are be equipped with pins that match the crate coding All valid combinations of slot number coding module type and VME base address are shown in the table below NB The codes are shown when looking from the rear VME connector side towards the back of the FADCTF front panel Crate Coding rear view Slot 4 7 10 13 16 19 5 8 11 14 17 20 6 9g 12 15 18 21 4 vi 10 13 16 5 8 11 14 17 20 6 12 T9 18 21 VME base address 0 04 Ox07 OxOa OxOd Ox10 0x13 0x05 0x08 OxOb OxOe 0x11 0x14 0x06 0x09 OxOc OxOf Ox12 0x15 0x24 0x27 Oxed 0x30 0x33 0x25 0x28 Oxeb Ox2e 0x31 Ox34 0x26 0x29 Oxec Oxef 0x32 0x35 10 4 FADCTF 4 1 Address space Each module within a crate wil have its own A32 address space representing a contiguous data block of 16MB bits 23 Bits A31 A24 of the base address can be selected by two switches which are located close to the rear end of the PCB between The VME connectors P1 and Pe Each switch provides a range of OxO OxF resulting in a total space of 256 different addresses Switch SWe serves the highest 4 bits while SW1 sets bits A27 A24 as indicated in the drawing below A32 address bits 21 30 29 28 27 26 25 24 2322 21 2 1 sw BR The address bits A23 and A22 are reserved for
14. DAP3 0x002000 0 0 DAP4 0x003000 0 0 DAP5 0x005000 0 0 DAP6 0x006000 0 0 DAP7 0x007000 0 0 TCR ECC FCR sto stop bit CH 2 bit channel number one of 4 inputs sta start bit ME 2 bit FIFO number one of 4 FIFOs e 4 bit event number d 10 bit ADC data 4 2 2 2 2 Read Write Pedestal Threshold memory VME bus adar 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 9 offset from F_BASE THPD2 0 009000 0 00 000 0 1 THPD4 0 00 000 0 1 a THPD5 0x00d000 1 0 a a THPD6 0 00 000 1 1 a a a a a a a THPD7 0 001000 11 o 1 a a a Dae o t t t t t t t 10 bit threshold data a 7 bit strip channel number 0 127 CH 2 bit channel number one of 4 inputs 4 2 2 2 3 Read Fast Or trigger counters VME bus adar bits 16 15 14 13 12 411 10 9 8 7 6 5 4 3 2 1 0 offset from F_BASE 0x011000 0 0 0 0 0 0 0 0 0 0x012000 0 1 0 0 0 0 0 013000 0 1 0 0 0 0 0 0 0 0 015000 1 0 0 0 0 0 0 0 0 0 016000 1 1 0 0 0 0 0 0 0 0x017000 1 1 0 0 0 EX S RI Data c c c c a 0 positive VA1TA signals a 1 negative VA1TA signals common to all 4 input channels set CH 00 b 0 5MHz ADC readout b 1 20MHz ADC readout
15. F modules Moreover we have to distinguish two crates and rz Crate VME base address bits 1 24 ro Slot number rz Slot number 20 Since the Sequencer must be inserted in slot 3 it will have the base address 0 03000000 in the crate and Ox23000000 in the rz crate illustration below gives an overview of all base addresses Segment number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 3 segment groups LM R LM LM L M a S u u jue foe foe foe foe fe uu O E BE BE IR IR JR JR IR JR IR IR dm uou uw uw tu 2 x N a 5 x O c VME p Crate Slots 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 60 90 VME base addr erate 0x03 0x04 0x05 0x06 0x07 0x08 0 09 0 0 0 0 0 00 0 0 0x10 0x11 0x12 0x13 0x14 0x15 bits 1 24 erate 0x23 0x24 0x25 0x26 0x27 0x28 0x29 Ox2A Ox2B 0 2 Ox2D Ox2E Ox2F 0x30 0x31 0x32 0x33 0x34 0x35 3 2 Mechanical coding 3 2 1 Crates Mechanical codin
16. Link test 24 Sa Head XKREQUEST BUSY and trigger status 24 5 5 2 Set PCI Link KENABLE and XREADY 24 E cj t Read TE nik data 1 Contact The FADC system is designed built and maintained by Institute of High Energy Physics Austrian Academy of Sciences Nikolsdorfergasse 18 A 1050 Vienna Austria Phone 43 1 5447328 0 Fax 43 1 5447328 54 e Overview This document describes the VME connectivity of the FADC system components Please refer to the FADCTF User s Manual for an introduction to the FADCTF system hardware The VME base address of the Sequencer module is called s and the base address of one FADCTF module is _ 2 1 Power on 2 1 1 Load Altera chips When the crate power is switched on the Altera chips are loaded from EEPROMSs or flash memories However the supply voltages may still ramp up and thus may cause errors during the loading process Thus it is recommended to re load the Altera chips on the FADCTF boards by the two VME commands FADCTF 0 2 0000 00 1 start Altera loading wait gt 50us FADCTF 0 2 0000 00 0 stop Altera loading The actual loading process will take a few seconds during which no VME commands shall be issued 2 1 2 Select clock source Most of the logic units on the FADCTF will need a clock for proper functioning Thus before sending any fur
17. common to all four DACs only the Load strobes are individual Due to historical reasons the first and last DACs are only utilized by 50 The matching between analog inputs 1 24 and DACs 8 channels each can be found in the table below The input numbering scheme follows the drawing in the FADC User s Manual top to bottom Input DAC INP1 4 DAC 1 INP5 8 DAC 2 INP9 12 INP13 16 DAC 3 INP1 7 20 INP21 24 DAC 4 As mentioned above only 4 out of 8 outputs are used on DAC 1 and DAC 4 The VME address map is shown below VME bus addr data bits 21 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 110 offset from F_BASE _ O 1 1 O o o o To o o 0 o o ie x x e 3 142 i p x DAC Daa 1 address data line SDI clock line CLK p preset all DAC outputs to 0x80 191 load strobe DAC1 INP1 4 182 load strobe DAC1 INP5 12 193 load strobe DAC1 INP13 20 194 load strobe DAC1 INP21 24 19 Sample Function Set a specific DAC to a specified 8 bit value void LOAD _DAC8841 int inp int ivalue inp 1 24 corresponding input channel ivalue 0 255 8 bit DAC value ine Glos Send serial address for 1 0 1 lt 4 1 VXIout 3 F_BASE DAC_Strobe 2 inp 3 amp 7 1 amp 8 gt gt 1 3 2 Send serial data value for 1 0 1 lt 8 1 VXIout 3 F_BASE DAC_Strobe 2 ivalue am
18. data acquisition under the control of the TTM system and with PCl Link output is the default condition after power on or after a general reset GENRES Thus no more settings are required 2 2 2 External test mode nibble or transparent mode Each will present one channel in transparent mode that is digitized and read out by the FADC system This mode requires clock start and ADC clock signals from the TTM system EFT should be low The following VME registers are linked to the external test mode FADCTF F BASE 0x018800 002 1 external test mode see 4 2 2 1 2 p 14 FADCTF BASE DAPx D01270 1 5 or 20MHz see 4 2 2 2 3 p 15 NB The sample taking clock has to be set for each DAP unit addresses DAP 2 3 4 0x001000 Ox002000 0 003000 DAP 5 6 7 0 005000 0 006000 007000 2 2 3 Internal test mode This mode is used to find potential errors within a module or a crate and does not require system the PCI Link Instead can use VME commands on the Sequencer to create the necessary input signals First of all the Sequencer must be set into the internal test mode requires the front panel switch in INT left position Seq S BASE 0x00 000 1 Sequencer internal mode see 5 2 1 21 The signals for a readout cycle can be generated by the Sequencer using Seq S_BASE 0x04 000 1 Generate readout cycle see 5 4 1 23 NB There are additional options for the readout cycle which are desc
19. ead bits 16 31 of Final Memory only with a 1 c 0 amp d 0 normal data output through PCI Link 1 amp 4 0 test mode POSTFIFO c 0 amp d 1 test mode PREFIFO f FIFO empty flag only with 0 sto stop bit sta start bit e 4 bit event number ch channel number 0 12 dd 10 bit ADC data of down DAPs 5 6 7 du 10 bit ADC data of up DAPs 2 3 4 16 When the toggle test mode is enabled Final Memory contents are read out but the data are replaced by alternating all zeros and all ones thus presenting the maximum load onto the output lines for test purposes Once the final memory is empty no more O 1 will be pushed out Only a half word 16 bits of the 32 bit data word can be read out at a time due to limitations in the 1 0 pins of the used Altera devices However since the data is stored in a FIFO one cannot read both half words of the same data packet since the FIFO is already cleared by the readout of one half word and the next readout refers to the next event data This procedure may be subject to future changes The final memory 32 bit data word as it appears on the PCI Link output is shown below 31 30 29 28 27 126 25 24 123 22 21 20 19 1817 16 15 14 13 12 1110 9 8 7 65 4 3 2110 Event 10 bit ADC data down STOSTA Channel 10 bit ADC data up 4 2 4 Serial Bus 1 LO
20. g has been introduced to prevent the modules from wrong insertion The reason for this are the LO and optionally L1 5 trigger processor interconnections Two output buses must not be connected together or the Altera chips will take damage from overheating Plastic pins are inserted at each slot of the crate 3 at bottom and 3 on top and on the counterpart of the FADCTF modules By this method a module can only be inserted in a matching slot In total there are 6 different LO firmware versions One for Left Middle and Right modules each in and rz crates This is reflected by 6 different mechanical codings as shown below With equal codes for top an bottom pins for each slot one mechanically equal red pin indicates is detached at left middle or right position to indicate the type of module Module segment triplets are equal and so is the mechanical coding which is identical e g for slots 4 7 10 13 16 19 as well as the LO processor The code pins are oriented horizontally and vertically in ro and rz crates respectively ro crate Slot Slot IMPORTANT The pin coding in the VME crates must never be removed since it prevents wrong insertion of modules which can damage the LO processor
21. p 128 gt gt 1 3 2 Load DAC value VXIout 3 F_BASE DAC_Strobe 2 0x10 lt lt inp 3 gt gt 3 20 5 Sequencer 5 1 Address Space Very similar to the FADCTF modules the Sequencer will have its own AG2 address space representing a contiguous data block of 16MB bits 23 The highest 8 address bits be selected by two hex switches on the PCB which are located close to the rear end between the P1 and P2 connectors A32 address bits 31 30 29281 27 26 25 24231 22 21 2 1 sw EENEUUNEN The type of VME transfer should be set for non privileged 32 bit data access Concerning the address modifier lines only 5 0 32 bit data is required we don t care about AMO Let s call the base address of the Sequencer s_BasE 5 2 General functions There is an int ext switch on the Sequencer front panel As long as it is set to ext right position the Sequencer will only repeat the TTM signals regardless of the VME register settings However it is possible to select the clock source to either TTM or the LEMO front panel input The latter expects TTL levels and has an adjustable threshold between 550 and e950mv Alternatively the internal quartz clock and the standalone test functions can only be enabled if the switch is in int position 5 2 1 Reset TTM or standalone VME bus addr bits 31 30 29 28 11 10 9
22. parc interface Moreover the FADCTF modules are mechanically coded with the corresponding counterparts in the crate e Always power off to change modules Never remove or insert a VME module of the system when the crate power is on Ensure that each module is fully inserted needs some force The VME interface Altera EPM7256S core is not specified for hot swapping can take damage by contention between logic levels and power supply during plugging of the module or in case of bad contact e Double check the VME base addresses It is extremely important that each FADCTF module has the correct VME base address set Altera programming l O interfacing to neighboring modules as used by the LO trigger processor rely on the correct VME base address setting which corresponds to the mechanical coding If the address is wrong and outputs of two modules are connected both modules will be damaged by overheating e Do not use the JTAG feature Programming Altera devices on the FADCTF modules is for experts only All Altera devices except for the VME protocol interface can be programmed by the JTAG bus that is accessible by VME Obviously much harm can be done by improper use of this feature The worst case is to blow up all Altera devices on the board Table of Contents SS Ee
23. ribed in chapter 5 4 7 p 23 2 3 VME implementation Many registers allow write and read operations but in most cases these functions are not accessing the same registers Thus writable registers usually cannot be read back except for the TIP1 B register in the Timing Control Unit of the FADCTF We are sorry that the VME implementation is a bit confusing and not really intuitive because it is historically grown During the development features were added continuously but we refrain from re designing the protocol since this would have large implications on existing software 2 4 VME command notation The VME commands shown here are in the National Instruments CVI notation which consists of the write command VXIout type address bytes data and the similar read command VXIin type address bytes S amp data The first argument specifies the type of VME transfer address modifier followed by the address up to 32 bits the number of bytes to be transferred 1 2 or 4 and the data word up to 32 bits to be written or read With this knowledge the input output functions can be easily translated to match the requirements of other systems such as the Sparc CPU All surrounding code is written in plain C language Addresses and coding 3 1 VME base addresses Each VME module will get its own A32 address space Basically the numbering scheme will follow the slot numbers for what concerns the Sequencer and the FADCT
24. s 31 30 29 28 11 10 9 8 7 6 5 4 3 2 4000 offset from S_BASE Address 004 0 0 0 o offo 1 0 red x x x x x x x 10 bus req req status of XREQUEST line bus status of P2 TTM BUSY wired or of all modules on the P2 backplane 10 status of P2_LO wired or of all modules on the P2 backplane 11 status of P2_L1 wired or of all modules on the P2 backplane res reserved 5 5 2 Set PCI Link XENABLE and XREADY VME bus addr bits 31 30 29 28 11 10 9 8 7 6 5 4 3 2 offset from 5 BASE 0x18 x x x x 0 set XENABLE and XREADY high idle condition en 1 set XENABLE and XREADY low ready to receive data 5 5 3 Read PCI Link data VME bus addr bits 31 30 29 28 11 10 9 8 7 6 5 4 3 2 07 offset from S_BASE Address o0 19 oo 0 9 9 9 9 9 Daa read 9 d d d o d d d d d d d d d 32 bit PCI Link FIFO 16k words data 24
25. the broadcast mode If these bits are both set every FADCTF module reacts regardless of address bits 1 24 This is useful e g to generate a global synchronous test pulse or to globally turn on off the Fast Or counters Let s call a module s base address Base All VME addresses in the tables within this document are shown in HEX format 4 2 Bus systems 4 2 1 Overview A FADCTF module has a total number of 7 internal buses which are all accessible by VME e 2 parallel buses Local Bus 1 and 2 e serial buses DAC and LO processor e JTAG buses These bus systems and their VME connectivity will be described in detail below A general reset RES issued by VME affects the parallel buses 1 and 2 and puts the module into a state ready for normal data taking i e all registers are set for that purpose VME addresses relative to sBasE of the individual buses are shown in the table below 11 Bus Local Bus 1 Local Bus 2 Serial Bus 1 STROSEQ1 Serial Bus 2 JTAG Bus 1 JTAG Bus 2 JTAG Bus 3 NCONFIG RES VME address rel to F_BASE 0 000000 OxO20000 0 040000 0 080000 OxOcO000 Ox100000 Ox140000 0 180000 Ox1c0000 Ox240000 Ox280000 0000 Ox3cO000 Description Data Processors Timing Control L 1 5 Proc Final Memory Write read LO processor Strobe for Sequencer V1 obsolete Load DACs JTAG write IOP
26. ther VME commands the clock source should be set in the Sequencer Its default condition after power on is to transparently repeat all TTM signals including the clock However it is recommended to reset the Sequencer and set the desired clock source by VME Seq S BASE 0x00 D30 1 Sequencer FIFO reset clear Seq S_BASE 0x00 D31 1 Sequencer reset see 5 2 1 p 21 Seq S BASE 0x08 D0O ttm TTM or ext clock see 5 2 2 p 22 Seq S_BASE 0x0c 000 9 ext quartz clock see 5 2 2 22 NB The switch the Sequencer front panel has be be in INT left position and internal mode see 5 2 7 p 21 has to be selected to enable the internal quartz clock The TTM clock can only be chosen in external mode power on default while the front panel input clock is selectable regardless of switch or mode 2 1 3 Reset FADCTF Although the FADCTF should be in normal data taking mode by default after power on it is recommended to send a general reset by VME which definitely sets it to that state FADCTF 0 3 0000 031 00 FADCTF reset see 4 2 1 p 11 NB The reset signal is issued by any write operation to this VME address regardless of the data bits 2 2 Modes of operation After everything is properly initialized the user must decide in which mode the FADCTF shall be put In the final environment of the FADC system there will be 3 different modes of operation described below 2 2 1 Normal data taking The normal
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