MCF5485 Reference Manual Errata
Contents
1. Location Description Table 13 1 Page 13 2 Replace table with the one below to better illustrate the interrupt priority and level assignments aaa Priority Supported Interrupt ICR IL ICR IP So rces 7 6 8 63 4 7 Mid point 7 IRQ7 3 2 8 63 0 7 4 8 63 6 Mid point 6 IRQ6 3 0 8 63 7 4 8 63 5 Mid point 5 IRQ5 3 0 8 63 7 4 8 63 4 Mid point 4 IRQ4 3 0 8 63 7 4 8 63 3 Mid point 3 IRQ3 3 0 8 63 7 4 8 63 2 Mid point 2 IRQ2 3 0 8 63 7 4 8 63 1 Mid point 1 IRQ1 3 0 8 63 Chapter 17 Change instances throughout of 4 1 1 1 to 3 1 1 1 4 2 2 2 to 3 2 2 2 and 3 1 1 1 to 2 1 1 1 Section 17 1 1 Page 17 1 Change FlexBus maximum operating frequency from 66 MHz to 50 MHz Figure 17 28 Page 17 28 Remove internal termination dashed lines for FBCS BE BWE TBST and OE signals Figure 17 32 Page 17 30 Remove internal termination dashed lines for FBCS BE BWE TBST and OE signals Figure 17 34 Page 17 31 Remove internal termination dashed lines for FBCS BE BWE TBST and OE signals Table 21 2 Page 21 8 Change MAXMB description from This 6 bit field to This 4 bit field MCF5485 Reference Manual Errata Rev 5 4 Freescale Semiconductor Errata for Revision 4 Table 1 MCF5485RM Rev 4 Errata continued Location Description Section 22 4 4 52. 15 14 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 R 0 COR CRY CRY CAN1 0 PSC 0 USB FEC1 FECO DMA CANO FB PCI MEM yan EN ENB ENA EN EN EN EN EN EN EN EN EN EN Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Addr MBAR 0x300 Figure 2 System PLL Control Register SPCR Table 6 SPCR Field Descriptions Bits Name Description 31 PLLK System PLL Lock Status Read only lock status of the system PLL 1 PLL has obtained frequency lock 0 PLL has not locked 30 15 Reserved should be cleared 14 COREN Core amp Communications Sub System Clock Enable Controls clocks for the CF4 Core System SRAM CommBus Arbiter 12C Comm Timers and External DMA modules 13 CRYENB Crypto Clock Enable B Controls the fast clock to the SEC 12 CRYENA Crypto Clock Enable A Controls the slow clock to the SEC 11 CAN1EN CAN1 Clock Enable 10 _ Reserved should be cleared 9 PSCEN PSC Clock Enable Controls clock for all PSC modules 8 Reserved should be cleared 7 USBEN USB Clock Enable 6 FEC1EN FEC1 Clock Enable 5 FECOEN FECO Clock Enable 4 DMAEN Multi channel DMA Clock Enable 3 CANOEN CANO Clock Enable 2 FBEN FlexBus Clock Enable 1 PCIEN PCI Bus Clock Enable 0 MEMEN Memory Clock Enable Controls clocks of the SDRAM controller module MCF5485 Reference Manual Errata Rev 5 12 Freescale Semiconductor Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Ta
3. Setting this bit also sets USBAISR EPSTALL instead of Setting this bit also sets USBAISR EPHALT Table 29 37 Page 29 39 EPnlISR EOT bit description add a note to the last sentence of the first paragraph stating The EOT interrupt will not assert for an isochronous OUT packet that experiences a PID sequencing error Section 29 4 3 1 Page 29 54 Add a section below USB Packets entitled Handshakes with the following paragraphs The USB device will return a NYET handshake packet to an OUT transaction if there is already data present in the FIFO and there are less than 2 MAXPACKETSIZE bytes free in the FIFO In cases where the FIFO depth is larger than 2 MAXPACKETSIZE i e 3x or 4x the following behavior will occur If after a transfer that returned a NYET handshake there is at least 1 MAXPACKETSIZE of free space in the FIFO the device will ACK the first PING request from the host and accept another MAXPACKETSIZE transfer from the host The device will again send a NYET handshake The only time the device will NAK a PING is when there is less than 1 MAXPACKETSIZE of free space in the FIFO Table 30 41 Page 30 45 Change bit description of the FECFRST SW_RST bit to Software Reset This bit controls the soft reset of the FEC FIFOs A soft reset will reset the FIFO pointers and byte counters but not the status and control registers To cause a soft reset this bit should be set and then cleared by application
4. MCF5485RM Rev 2 1 Errata continued Revision History Location Description Table 31 1 Page 31 5 Remove overbar from ALE at location AD6 Table 31 1 Page 31 7 port port e Replace PPSCLn entries under the GPIO column with PPSC1PSCOn There is no PPSCL e Replace PPSCHn entries under the GPIO column with PPSC3PSC2n There is no PPSCH Figure 31 3 Page 31 11 Remove overbar from ALE at location AD6 Figure 31 7 Page 31 15 Remove overbar from ALE at location AD6 Figure 31 11 Page 31 19 Remove overbar from ALE at location AD6 5 Revision History Table 8 provides a revision history for this document Table 8 Revision History Table Rev Number Substantive Changes Date of Release 0 Initial release Added ball P3 errata Added DSPI MDIS errata Added four USB chapter errata USBCR APPLOCK PSTALL EPnISR EOT and handshakes section addition Added SDDATA and SDADDR errata Added I2I ICR gt I2CR errata Added MAPBGA gt PBGA errata 08 2005 Added many errata Missing bit numbers in register diagrams Add remove overbars to Table 2 1 amp 2 2 Correct ALE signal name and remove overbars throughout Fix clock divide ratio tables Add clock frequency correlation figure Add PLL memory map section Removal of GPT errata Removal of extra in PAR_CSO bit description Add section regarding Comm Timer external clock Change CTCRa S bit descriptio
5. com and do a keyword search for 98ARS23880W for the updated drawing MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor Errata for Revision 3 3 Errata for Revision 3 Table 2 MCF5485RM Rev 3 Errata Location Description Section 29 1 2 Page 29 1 Added the following note at the end of the features list NOTE The USB 2 0 device controller requires a minimum XLB system clock frequency of 66 MHz Section 29 1 3 1 Page 29 2 Added the following note at the end of this section NOTE The USB 2 0 device controller requires a minimum XLB system clock frequency of 66 MHz Section 25 1 3 Page 25 3 Replaced the Comm Timer External Clock table with the following Table 25 1 Comm Timers External Clock Channel External Signal 0 PSCOBCLK 1 PSC1BCLK PSC2BCLK PSC3BCLK TINO TIN1 TIN2 TINS NI OO oO B amp B WO Added FIFO Controller chapter that describes the features of the FIFO controller implemented on many of the communication peripherals Section 29 2 1 Page 29 5 Added the following additional note below the existing note 8 and 16 bit registers offsets OxBO00 to OxB3FF should not be accessed until the MCF548x is connected to a USB with a stable VBUS The interrupt generated at the end of the reset signalling USBISR RSTSTOP can be used as an idication of a stable USB connection MCF5485 Reference Manual E
6. shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part ey Z freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2009 All rights reserved MCF5485RMAD Rev 5 4 2009
7. software Change bit description of the FECFRST RST_CTL bit to Reset control Setting this bit allows the FEC controller to perform a soft reset of the FIFOs when the FEC is disabled ECR ETHER_EN cleared Table 31 1 Page 31 1 Add column to indicate whether the signal has a pull up resistor These signals have a pull up resistor at all times DSCLK TRST BKPT TMS DSI TDI These signals have a pull up resistor whenever configured for general purpose input default state after reset PCIBR 4 3 PCIGNT 4 3 E1MDIO E1MDC E1TXCLK E1TXEN E1TXDJ 3 0 E1COL E1RXCLK E1RXDV E1RXD 3 0 E1CRS E1TXER E1RXER Table 31 1 Page 31 1 Ball P3 should be SD_VDD instead of EVDD Table 31 1 Page 31 1 The GPIO bit number for each of the UART control signals are incorrect for Table 31 1 However they are correct for Table 2 1 e Y23 PSC1RTS pin Change GPIO entry from PPSCL7 to PPSC1PSCO6 e AB23 PSC3RTS pin Change GPIO entry from PPSCH7 to PPSC3PSC26 e AB26 PSCORTS pin Change GPIO entry from PPSCL3 to PPSC1PSC02 AC19 PSC2CTS pin Change GPIO entry from PPSCH2 to PPSC3PSC23 AD26 PSC2RTS pin Change GPIO entry from PPSCH3 to PPSC3PSC22 AE23 PSCOCTS pin Change GPIO entry from PPSCL2 to PPSC1PSC03 AF23 PSC83CTS pin Change GPIO entry from PPSCH6 to PPSC3PSC27 AF25 PSC1CTS pin Change GPIO entry from PPSCL6 to PPSC1PSC07 MCF5485 Reference Manual Errata Rev 5 16 Freescale Semiconductor Table 3
8. 1 6 50 0 83 33 100 166 66 200 00101 1 2 25 0 41 5 50 0 83 02 100 0 166 66 01111 1 4 25 0 100 200 NOTES 1 All other values of AD 12 8 are reserved 2 Note that DDR memories typically have a minimum speed of 83 MHz Some vendors specifiy down to 75 MHz Check with the memory component specifications to verify MCF5485 Reference Manual Errata Rev 5 10 Freescale Semiconductor Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Section 2 2 6 1 Page 2 24 Figure 1 correlates CLKIN internal bus and core clock frequencies for the 1x 4x multipliers Add the following after Table 2 4 CLKIN MHz CLKIN Internal Clock Core Clock lt 2x gt lt 2x gt 25 0 50 0 50 0 100 0 100 0 200 0 lx 4x gt lt 2x gt 25 0 100 0 200 0 gt gt gt 25 40 50 60 70 30 40 50 60 70 80 90 100 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Internal Clock MHz Core Clock MHz Figure 1 CLKIN Internal Bus and Core Clock Ratios Section 3 8 1 Page 3 40 Change the second sentence of the first paragraph from The second holds the 32 bit program counter address of the faulted instruction to The second holds the 32 bit program counter address of the faulted or interrupted instruction Table 3 23 Page 3 44 The Interrupt exception entry s description is outdated Chang
9. 16 SDDQS2 VSS EVDD USBVDD SDBA1 SDBAO MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor Errata for Revision 4 Table 1 MCF5485RM Rev 4 Errata continued Location Description Figure 32 1 Page 32 8 Remove extraneous overbars from the following pin signals B5 SDDQS2 B6 SDDATA21 C6 SDVDD D4 SDDATA16 D6 VSS Change F1 from SDDDATA10 to SDDATA10 remove extra D Change B3 from SDDDATA18 to SDDATA18 remove extra D Figure 32 2 Page 32 9 Remove extraneous overbars from the following pin signals A15 DSI TDI A16 TCK A18 MTMOD1 A19 PLLVDD A21 PSTDDATA1 A23 PSTDDATA7 B15 TMS B22 E1RXCLK C15 DSCLK C21 VSS C25 SCL E24 EVDD H23 IVDD H24 EVDD Figure 32 3 Page 32 10 Remove extraneous overbars from the following pin signals P4 IVDD AF2 AD25 Figure 32 4 Page 32 11 Remove extraneous overbars from the following pin signals U24 EVDD V26 PCIAD30 AA25 PSCOTXD AC18 VSS AC20 IVDD AC26 PSC2TXD AE18 USBVDD AE21 PSC3RXD AF18 USBRBIAS AF21 TIN2 AF22 TINO Figure 32 5 Page 32 12 Remove extraneous overbars from the following pin signals B5 SDDQS2 B6 SDDATA21 C6 SDVDD D4 SDDATA16 D6 VSS Change F1 from SDDDATA10 to SDDATA10 remove extra D Change B3 from SDDDATA18 to SDDATA18 remove extra D Figure 32 6 Page 32 13 Remove extraneous overbars from the following pin signals A15 DSI TDI A16 TCK
10. A18 MTMOD1 A19 PLLVDD A21 PSTDDATA1 A23 PSTDDATA7 B15 TMS C21 VSS C25 SCL E24 EVDD H23 IVDD H24 EVDD Figure 32 7 Page 32 14 Remove extraneous overbars from the following pin signals P4 IVDD AF2 AD25 Figure 32 8 Page 32 15 Remove extraneous overbars from the following pin signals U24 EVDD V26 PCIAD30 AA25 PSCOTXD AC18 VSS AC20 IVDD AC26 PSC2TXD AE18 USBVDD AE21 PSC3RXD AF18 USBRBIAS AF21 TIN2 AF22 TINO Figure 32 9 Page 32 16 Remove extraneous overbars from the following pin signals B5 SDDQS2 B6 SDDATA21 C6 SDVDD D4 SDDATA16 D6 VSS Change F1 from SDDDATA10 to SDDATA10 remove extra D Change B3 from SDDDATA18 to SDDATA18 remove extra D Figure 32 10 Page 32 17 Remove extraneous overbars from the following pin signals A15 DSI TDI A16 TCK A18 MTMOD1 A19 PLLVDD A21 PSTDDATA1 A23 PSTDDATA7 B15 TMS B22 E1RXCLK C15 DSCLK C21 VSS C25 SCL E24 EVDD H23 IVDD H24 EVDD Figure 32 11 Page 32 18 Remove extraneous overbars from the following pin signals P4 IVDD AF2 AD25 Figure 32 12 Page 32 19 Remove extraneous overbars from the following pin signals U24 EVDD V26 PCIAD30 AA25 PSCOTXD AC18 VSS AC20 IVDD AC26 PSC2TXD AE21 PSC3RXD AF18 USBRBIAS AF21 TIN2 AF22 TINO Change figure title from MCF5485 5484 Lower Right to MCF5481 5480 Lower Right Section 32 6 Page 32 20 Update package drawing See http www freescale
11. Freescale Semiconductor Reference Manual Addendum MCF5485RMAD Rev 5 4 2009 MCF5485 Reference Manual Errata by Microcontroller Solutions Group This errata document describes corrections to the MCF5485 Reference Manual order number MCF5485RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com coldfire for the latest updates The current version available of the MCF5485 Reference Manual is Revision 5 Freescale Semiconductor Inc 2009 All rights reserved akwWND Table of Contents Errata fOr REVISION Sissi csstscisscdssaciseastaticceacncivaxdain 2 Errata for Revision A nimre 2 Errata for Revision S sicicnccscsssersssaaacaccarsteasaasasecacis T EWata tor Revision idl aceras nei 9 Revision HIStOTY ssiri pa ad passcstisanesdsosadpasacraasiatie 17 e O S 2 freescale semiconductor Errata for Revision 5 1 Errata for Revision 5 None to report 2 Errata for Revision 4 Table 1 MCF5485RM Rev 4 Errata Location Description Chapter 1 Corrected maximum frequency errors throughout PCI 50 MHz FlexBus 50 MHz SDRAM 100 and 200 MHz Table 1 2 Page 1 7 Replace with the following table AD 12 8 roe EARE aA ARE TELIFONI i aoe roe Range MHz Range MHz 00011 1 2 41 67 50 0 83 33 100 166 66 200 00101 1 2 25 0 41 67 50 0 83 33 100 0 166 66 01111 1 4 25 0 100 200 NOTES 1 Al
12. M change instance of less than alarm bytes to more than alarm bytes and change instance of more than alarm bytes to less than alarm bytes Figure 26 22 Page 26 33 Remove shading from W field as the PSCRFARn and PSCTFARn registers are R W accessible Section 26 4 Page 26 44 Add section 15 3 7 PSC FIFO System from the MPC5200 User s Manual to before section 26 4 9 Looping Modes Change the following text to apply to the MCF548x MPC5200 gt MCF548x BestComm Multichannel DMA MR1 PSCMRIin SR PSCSRn ORERR ERR Figre 27 1 Page 27 1 Change IFDR to I2FDR and IADR to I2ADR in figure Section 27 3 2 1 Page 27 3 Change instances of I2AR to I2ADR Section 27 3 2 3 Page 27 5 Change I2ZICR to I2CR throughout section Chapter 27 After section 27 3 2 4 change instances of R W to R W throughout chapter MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor 15 Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Section 28 6 1 Page 28 5 Remove instances of MDIS bit as it is not present on this version of the DSPI Table 29 3 Page 29 13 USBCR APPLOCK bit description the bit setting numbers are incorrrect When cleared 0 APPLOCK is deasserted When set 1 APPLOCK is asserted Table 29 29 Page 29 33 Endpoint status register s PSTALL entry the last sentence should be
13. PO the following steps should be followed 1 Wait for the EOF event for the packet with the last data payload This will ensure that the IN endpoint s FIFO is empty 2 Set the TXZERO bit in the EPOSR or EPnINSR 3 Clear the TXZERO bit immediately after the ZLP has been sent The USBAISR ACK event and EPINFO register can be monitored to determine that the ZLP from the active endpoint was properly received It is important that the FIFO be empty when the TXZERO bit is set Once set the USB Device Controller will send a ZLP even if valid data is present in the FIFO It is also important that the application clears the TXZERO bit as soon as possible after the ZLP is sent The USB 2 0 Device Controller will continue to send ZLPs in response to IN tokens for the same endpoint until the TXZERO bit is cleared For EPO the TXZERO bit should only be set by the application The USB 2 0 Device Controller will clear the TXZERO bit automatically 4 Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata Location Description Throughout Replace all instances of MAPBGA with PBGA as this is the correct package that the devices are available in Throughout Fix missing bit numbers above register diagrams throughout Figure 2 1 Page 2 2 e Replace all PPSCLn entries in the figure with PPSC1PSCOn There is no PPSCL port e PSCOCTS pin Change GPIO entry from PPSCL2 to PPSC1PSC03 e PSCORTS pin Change GPIO entry from PPSCL3 to
14. PPSC1PSC02 e PSCICTS pin Change GPIO entry from PPSCL6 to PPSC1PSC07 e PSC1RTS pin Change GPIO entry from PPSCL7 to PPSC1PSCO6 e PSC2CTS pin Change GPIO entry from PPSCH2 to PPSC3PSC23 e PSC2RTS pin Change GPIO entry from PPSCH3 to PPSC3PSC22 e PSC3CTS pin Change GPIO entry from PPSCH6 to PPSC3PSC27 e PSC8RTS pin Change GPIO entry from PPSCH7 to PPSC3PSC26 Table 2 1 Page 2 3 Add column to indicate whether the signal has a pull up resistor These signals have a pull up resistor at all times DSCLK TRST BKPT TMS DSI TDI These signals have a pull up resistor whenever configured for general purpose input default state after reset PCIBR 4 3 PCIGNT 4 3 E1MDIO E1MDC E1TXCLK E1TXEN E1TXDJ 8 0 E1COL E1RXCLK E1RXDV E1RXD 8 0 E1CRS E1TXER E1RXER MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Table 2 1 Page 2 3 Remove overbars from the following signals FRADDR1 FBADDRO SDDATA SDADDR SDBA TIN3 TOUT3 Table 2 1 Page 2 3 In entry AD6 remove overbar from ALE and change description from Transfer start to Address latch enable Table 2 1 Page 2 6 Add overbars to IRQ 6 5 Table 2 2 Page 2 11 e Replace PPSCLn entries under the GPIO column with PPSC1PSCOn There is no PPSCL port e Replace PPSCHn entries under the GPIO column with PP
15. Page 22 8 Add the following at the end of the RNG section CAUTION There is no known cryptographic proof showing that this is a secure method of generating random data In fact there may be an attack against the random number generator if its output is used directly in a cryptographic application the attack is based on the linearity of the internal shift registers In light of this it is highly recommended to use the random data produced by this module as an input seed to a NIST approved based on DES or SHA 1 or cryptographically secure RSA generator or BBS generator random number generation algorithm It is also recommended to use other sources of entropy along with the RNG to generate the seed to the pseudorandom algorithm The more random sources combined to create the seed the better The following is a list of sources which can be easily combined with the output of this module e Current time using highest precision possible e Mouse and keyboard motions or equivalent if being used on a cell phone or PDA e Other entropy supplied directly by the user NOTE See Appendix D of the NIST Special Publication 800 90 Recommendation for Random Number Generation Using Deterministic Random Bit Generators for more information http csrc nist gov Table 27 2 Page 27 4 Correct PSCRFCR and PSCTFCR from 8 bits to 32 bits wide in memory map Section 27 7 2 Correct PSCRFCR and PSCTFCR values from OF to OC00_0000 throughout ex
16. SC3PSC2n There is no PPSCH port Table 2 2 Page 2 11 The GPIO bit number for each of the UART control signals are incorrect for Table 2 2 However they are correct for Table 2 1 e Y23 PSC1RTS pin Change GPIO entry from PPSCL7 to PPSC1PSCO06 e AB23 PSC3RTS pin Change GPIO entry from PPSCH7 to PPSC3PSC26 e AB26 PSCORTS pin Change GPIO entry from PPSCL3 to PPSC1PSC02 e AC19 PSC2CTS pin Change GPIO entry from PPSCH2 to PPSC3PSC23 e AD26 PSC2RTS pin Change GPIO entry from PPSCH3 to PPSC3PSC22 e AE23 PSCOCTS pin Change GPIO entry from PPSCL2 to PPSC1PSC03 e AF23 PSC3CTS pin Change GPIO entry from PPSCH6 to PPSC3PSC27 e AF25 PSC1ICTS pin Change GPIO entry from PPSCL6 to PPSC1PSC07 Table 2 2 Page 2 12 Remove overbars from the following signals IVDD TCK PLLVDD PSTDDATA1 PSTDDATA7 SDDATA21 PSTDDATA2 E1 RXCLK E1RXD2 SDVDD SDDATA31 SDADDR4 DSCLK VSS EVDD PCIAD29 PCIAD30 SCL SDDATA16 AD17 AD20 E1CRS EOTXD2 TOUT2 TOUT1 PSC2TXD ALE EOTXD3 SDBA1 SDBAO USBVDD PSC3RXD AD25 USBRBIAS TIN1 TIN2 TINO Table 2 2 Page 2 12 Add overbars to the following signals IRQ3 IRQ2 Table 2 4 Page 2 24 Replace table with the following Table 4 MCF548x Divide Ratio Encodings at Clock CLKIN PCI and FlexBus ternal XLB SDRAM Gore Frequency AD 12 8 Ratio Frequency Range MHz bus and PSTCLK Range MHz a y g Frequency Range MHz g 00011 1 2 4
17. amples Change WRITE TAG 00 to WFR 0 throughout examples Table 27 41 Page 27 49 In step 1 change value of PSCSICR to 00 and remove the RxDCD sub row as this bit is not implemented In step 6 change value of PSCACR to 01 and remove the IEC1 sub row as this bit is not implemented Table 27 44 Page 27 52 In step 6 remove the IEC1 sub row as this bit is not implemented Section 28 7 2 4 Page 28 21 Change second sentence from The TX FIFO holds from 1 to 16 longwords to The TX FIFO holds from 1 to 4 longwords Section 28 7 2 5 Page 28 22 Change second sentence from The RX FIFO holds from 1 to 16 received to The RX FIFO holds from 1 to 4 received Chapter 30 Add note to beginning of chapter CAUTION The MCF548x devices contain a silicon errata that affects the usage of the USB device controller Please see MCF5485 Device Errata MCF5485DE at http www freescale com coldfire for details Section 30 3 4 5 2 Page 30 54 Add the following to the end of step 5 In the case of a Control Read an empty Data OUT packet is used in the status stage to indicate a successful transfer To accomplish this the TXZERO bit in the EPnNOUTSR should also be set Table 31 4 Page 31 6 Correct MIB block counters end addresses to MBAR 0x92FF and MBAR Ox9AFF Table 32 1 Page 32 1 Remove extraneous overbars from the following signals SDDATA31 SDADDR4 SDDATA
18. ble 10 2 Page 10 9 Bits BA DT and AT The 0 and 1 are switched Setting each bit enables operation while clearing disables operation The 0 and 1 or the corresponding descriptions need to be swapped for all three bits Section 11 4 2 Page 11 9 Remove all text from bullet item 2 starting with This scenario works for all pulses except This errata does not apply to this processor Section 13 1 1 Page 13 2 Correct the cross reference link at top of page that reads Section 3 8 1 Exception Stack Frame Definition Table 15 27 Page 15 26 In the bit 7 6 PAR1_E1MDC entry change 11 bit setting description from E1MDC pin configured for FEC1 MDC function to E1MDC pin configured for FEC1 E1MDC function to be consistent with rest of section Table 15 34 Page 15 33 Remove extraneous from DSPICS0 SS in second sentence of the PAR_CS0 bit description Table 16 1 Page 16 2 Extend SSCR entry to include bytes 2 amp 3 as well as bytes 0 and 1 since it is a 32 bit register Section 17 6 5 4 2 Page 17 26 Change transfer start to address latch enable in second sentence Section 21 4 9 Page 21 30 Figure 21 14 and Table 21 18 are missing Add them as shown below and correct the cross references to them LN se Time Segment 1 Time Segment 2 PROP_SEG PSEG1 2 PSEG2 1 4 16 8 25 Time Quanta 1 Bit Time Transmi
19. dpoint is received For commands that require application intervention the application must set this bit when it completes the activity for the command This bit should not be cleared by the application 0 Control command in process default 1 Control command completed Section 29 2 5 2 Page 29 36 Updated FIFOHI and FIFOLO descriptions 5 FIFOHI FIFO high When configured as an OUT FIFO this indicates that the number of bytes in the FIFO has surpassed the high level alarm value 4 FIFOLO FIFO low When configured as an IN FIFO this indicates that the number of bytes in the FIFO has fallen below the FIFO low level alarm value MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor Errata for Revision 2 1 Table 2 MCF5485RM Rev 3 Errata continued Location Description Section 29 3 Page 29 50 Made minor layout changes throughout the Functional Description section Some major updates include the addition of some clarified Handshake information and the addition of a section on Sending Zero Length Packets A packet with a payload size less than wMaxPacketSize is used to indicate the end of a transfer For transfers with a total payload that is evenly divisible by wMaxPacketSize a zero length packet ZLP may need to be transferred to indicate to the Host that the transfer has ended To send a zero length packet on an endpoint other then endpoint zero E
20. e from Interrupt exception processing with interrupt recognition and vector fetching includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8 bit interrupt vector Autovectoring can optionally be configured through the system interface module SIM to Please refer to Chapter 13 Interrupt Controller Table 10 1 Page 10 3 Add missing table using Table 4 from this document MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor 11 Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Section 10 2 Page 10 5 10 2 PLL 10 2 1 PLL Memory Map Register Descriptions Insert the following section before section 10 2 XL Bus Arbiter Table 5 System PLL Memory Map MBAR Offset Name ByteOd Byte1 Byte2 Byte3 Access 0x300 SPCR R W System PLL Control Register 10 2 2 System PLL Control Register SPCR The system PLL control register SPCR defines the clock enables used to control clocks to a set of peripherals Unused peripherals can have their clock stopped reducing power consumption In addition the SPCR contains a read only bit for the system PLL lock status At reset the clock enables are set enabling all system PLL gated output clocks
21. ects boundary scan register while applying fixed values to output pins and asserting functional reset SAMPLE 000001 Selects boundary scan register for shifting sampling and preloading without disturbing functional operation IDCODE _ 011101 Selects IDCODE register for shift CLAMP 011111 Selects bypass while applying fixed values to output pins and asserting functional reset HIGHZ 111101 Selects bypass register while tri stating all output pins and asserting functional reset ENABLE 000010 Selects TEST_CTRL register BYPASS 111111 Selects bypass register for data operations Section 23 4 3 4 Page 23 9 Remove section as the TEST_LEAKAGE instruction is not supported Section 23 4 3 7 Page 23 9 Remove section as the LOCKOUT_RECOVERY instruction is not supported Table 24 20 Page 24 22 Correct Base Address Mask Register 1 mnemonic from EREQMASKO to EREQMASK1 Section 24 3 4 2 Page 24 22 Correct overbar in first sentence From After DREQ is asserted this register contains to After DREQ is asserted this register contains MCF5485 Reference Manual Errata Rev 5 14 Freescale Semiconductor Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Section 25 1 2 Page 25 3 Add the following section after section 24 1 2 24 1 3 Comm Timer External Clock 7 0 The comm timer external clock is the alte
22. er Added FIFO controller chapter errata Added Comm Timer External Clock table errata Added note regarding register access until USB is stable errata Added EPnOUTSR and EPnINSR bit field description errata Added EPnISR bit field description errata 7 2006 The following errata were added to Rev 4 of the MCF5485RM 4 1 Added extraneous and missing overbars errata to signals table and pinout diagrams Added USBVBUS errata Added FEC MIB counter memory map errata Added internal termination figure errata for longword write bursts Added FlexBus chapter wait states errata Added interrupt level priority table Added USB Device Requests step 5 errata Added PSC examples errata Added GSRn and SSRn register access errata Added clocking options table errata Added MAXMB bit description errata Added clarification to multiple CAN controllers in overview chapter Added E1MDIO and E1MDC signal table errata Added AD3 bit setting errata in overview chapter Added cache initialization sequence errata 5 2007 Added package drawing errata Added Flexbus PCI and SDRAM maximum operating frequency errata Added RNG caution and note Added DSPI FIFO size errata Added PSC PSCRFCR and PSCRFCR register size and example settings errata Added MCF5485RM rev 5 section 4 2009 MCF5485 Reference Manual Errata Rev 5 18 Freescale Semiconductor Revision History MCF5485 Reference Manual Er
23. l other values of AD 12 8 are reserved Section 1 4 6 7 Page 1 10 Change last sentence to The two CAN controllers can interface to two separate 16 message buffer CAN networks or a single 32 message buffer CAN network Table 2 1 Page 2 3 Remove extraneous overbars from the following signals TSIZ1 TSIZO Add overbar to PCITRDY Table 2 1 Page 2 6 E1MDIO entry Remove Y from pull up column This signal cannot be configured as a GPIO so there is no pull up E1MDC entry Remove Y from pull up column This signal cannot be configured as a GPIO so there is no pull up Change I O entry from O 1 O to O Table 2 2 Page 2 10 Remove extraneous overbars from the following pin signals A15 DSI W23 DSPICS5 AA23 IVDD AA25 PCSOTXD AB26 PPSC1PSC02 Add overbar to B13 RSTI Table 2 4 Page 2 22 Replace with the following table AD 12 8 fae sta ea li AU PST OLI FEAU f Pane W Range MHz Range MHz 00011 1 2 41 67 50 0 83 33 100 166 66 200 00101 1 2 25 0 41 67 50 0 83 33 100 0 166 66 01111 1 4 25 0 100 200 NOTES 1 All other values of AD 12 8 are reserved Table 2 7 Page 2 24 Swap the bit settings for AD3 in this table When AD3 is asserted BE 3 0 are asserted for both read and write cycles When negated BE 3 0 are asserted for write cycles only MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor Errata fo
24. n and diagram Figure 26 1 broken cross reference Correct PSCISRn TXRDY and PSCRFSRn PSCTFSRn ALARM descriptions Make PSCRFARn and PSCTFAR register diagrams R W Add section from MPC5200UM Change I2AR gt I2ADR Change R W gt R W_b Change FECFRST SW_RST RST_CTL bit descriptions 09 2005 MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor 17 Revision History Table 8 Revision History Table continued Rev Number Substantive Changes Date of Release 2 Added PPSCLn and PPSCL o errata for Table 2 2 and Table 31 1 Added UART control signal s GPIO bit number errata in Table 2 2 and Table 31 1 Added JTAG IR codes errata Added FlexCAN chapter s missing tables and figure Added PAR_E1MDC bit description errata Added interrupt exception description errata in the ColdFire core chapter Added broken cross reference at beginning of Chapter 13 Added exception stack frame s second longword clarification Added IC block diagram s register naming errata Added DMA Base Address Mask Register 1 mnemonic errata Added extraneous overbar in DMA chapter 12 2005 Added XARB_CFGI BA DT AT bit setting errata Added SSCR register width errata Added SEC 64 bit registers errata Added PSCRFCRn PSCTFCR 30 bit errata 1 2006 The following errata were added to Rev 3 of the MCF5485RM Added errata regarding minimum system clock for proper operation of the USB controll
25. r Revision 4 Table 1 MCF5485RM Rev 4 Errata continued Location Description Section 2 2 8 2 Page 2 26 Change sentence from This is the USB cable Vbus monitor input to This is the USB cable Vbus monitor input which is 5 V tolerant Section 7 13 Page 7 30 Change value written to DO in first line of code from OxA30C_8100 to OxA70C_ 8100 to enable cache inhibited imprecise mode Table 10 1 Page 10 2 Replace with the following table AD 12 8 ron Se eu Frequency nana eoTCUCrieueney i Eain Range MHz Range MHz 00011 1 2 41 67 50 0 83 33 100 166 66 200 00101 1 2 25 0 41 67 50 0 83 33 100 0 166 66 01111 1 4 25 0 100 200 NOTES 1 All other values of AD 12 8 are reserved Table 11 1 Page 11 2 Change GSRn s Access entry to R W as some status bits may be cleared by writing a 1 to them Figure 11 4 Page 11 7 Change GSRnr TEXP PWMP COMP CAPT bits write row to wic as they may be written with a 1 to clear them Table 12 1 Page 12 1 Change SSRn s Access entry to R W as some status bits may be cleared by writing a 1 to them Figure 12 4 Page 12 4 Change SSRn BE ST bits write row to wic as they may be written with a 1 to clear them MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor Errata for Revision 4 Table 1 MCF5485RM Rev 4 Errata continued
26. rata Rev 5 Freescale Semiconductor 19 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integ
27. rated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer
28. rnate clock signal and is provided by the user The user must write a 1 to CTCR S in the variable channel and write a 1001 to CTCR S within the fixed channel to select this signal If this signal is selected all timing will be with respect to this clock signal This signal is restricted to being half the frequency or less of the system bus clock Table 4 7 Comm Timers External Clock Timer Channel External Signal 0 TINO TIN1 TIN2 TIN3 PSC3BCLK PSC2BCLK PSC1BCLK PSCOBCLK N O aj A j N Table 25 2 Page 25 5 In the S bit description change the 1001 setting from Reserved to External clock Table 25 3 Page 25 7 The S bit field is incorrect Bits 31 29 should be reserved and only bit 28 should be the S bit And the S bit description should be Clock enable source select Selects the clock rate for the fixed timer channels The clock rate for the timer is the internal system clock divided by an 8 bit prescaler 1 External Clock 0 Sysclk Note The external bus clock cannot be an faster than half the frequency of the system clock Section 26 1 Page 26 1 Fix broken cross reference to Figure 26 1 Table 26 13 Page 26 20 In description of TXRDY change PSCTFALARM to PSCTFAR Section 26 3 3 24 Page 26 30 Change bit 30 of PSCRFCRn PSCTFCRn register to reserved as the WFR field is only one bit wide Table 26 30 Page 26 31 In description of ALAR
29. rrata Rev 5 Freescale Semiconductor Errata for Revision 3 Table 2 MCF5485RM Rev 3 Errata continued Location Description Section 29 2 4 4 Page 29 33 Changed the INT bit description to Interrupt This bit is set and cleared by the application and is only relevant for interrupt IN endpoints When an interrupt IN token is received the USB device controller will use this bit to determine how to respond If cleared a NAK response will be sent If set the USB device controller will send a data packet if data is available or a NAK if no data is available 0 No interrupt pending on this endpoint default 1 Interrupt pending on this endpoint Changed the TXZERO bit description to Transmit a zero byte packet For control endpoints this bit should only be set by the application and cleared by the USB device controller For non control endpoints the application must set this bit prior to sending a zero byte packet to the host and clear this bit after the zero byte data packet has been successfully transmitted to the host 0 NOP default 1 Transmit a zero byte packet Changed the CCOMP bit description to Control command complete Relevant only for control endpoints For those commands that do not need application intervention the application can ignore the CCOMP bit It will be reset in the setup phase and set in the status phase automatically It will remain set until the next setup token for the particular en
30. t Point Sample Point single or triple sampling Figure 21 14 Segments within the Bit Time Table 21 18 Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point Sample Point A node samples the bus at this point If the three samples per bit option is selected then this point marks the position of the third sample MCF5485 Reference Manual Errata Rev 5 Freescale Semiconductor 13 Errata for Revision 2 1 Table 3 MCF5485RM Rev 2 1 Errata continued Location Description Section 21 4 9 Page 21 30 Add the following table below the note at the end of the section and correct the cross reference pointing to it Table 21 19 CAN Standard Compliant Bit Time Segment Settings Time Segment 1 Time Segment 2 Panwa S 5 10 2 1 2 4 11 3 Esi 5 12 4 1 4 6 13 5 1 4 7 14 6 1 4 8 15 7 1 4 9 16 8 1 4 Section 22 5 Page 22 8 Split various 64 bit registers into two 32 bit registers labeled High and Low in memory map table as well as the following sections Changed registers include EUACR SIMR SISR SICR EUASR CCPSRn Table 23 5 Page 23 8 The JTAG IR codes are incorrect Replace table with the following Instruction IR 5 0 Instruction Summary EXTEST 000000 Sel
Download Pdf Manuals
Related Search