EDP Baseboard EDP-BB-4A User Manual
Contents
1. 12V CPU Module Analog Module 2 ule Fuse i i E Peso i f i Volt Ref i 4 in i fueses 3V3 Reg l l Voc CM i d i I o i 2 HE i LE iL T j pd VAGND System GND SGND 12V GND 12V GND 2 6 Positive Supplies The 12V line comes via the screw terminals on the baseboard or the mini jack It is fused and filtered before entering the EDP backplane The 3V3 and 5V voltage regulators are driven from the 12V 2 6 14 Logic Supplies Both 3V3 and 5V are available on the EDPCON to support both 5V and 3V3 processors and devices To allow the interfacing of I O devices at the required voltage the positive supply to the CPU I O domain is routed into the EDPCON through Vcc CM Itis intended to be used for pull ups on I O pins and powering small active components that connect directly to the CPU such as discrete logic op amps etc Vcc CM is limited to 500mA total current draw from other modules and the baseboard Vcc CM is connected inside the CM to the voltage used by the CPU s I O domain Electrocomponents plc Vsn 1 1 Page 19 7 PARIMmaIme nc EDP Technical Notes Radiospares RADIONICS RS 2 6 2 Analogue Supply The Analogue supply to the CPU ADC may be derived from the local Vcc or from a precision reference located on the Analogue AM Ideally the Analogue AM and CM should be in adjacent positions on the baseboard to keep the signal length to a minimum if the latter is chosen2. 1 3 3 1 EDPCON1 Signal Description ANx VAGND GPIOx GPIOx_MCIxxx GPIOx I28 XXX IRQx GPIOx X I2C INT CPU DACx GPIOx EVMx GPIOx GPIOx ADx EVGx GPIOx EVM2 GPIO41 CAPADC ASCO RX TTL ASCO TX TTL ASC1 RX TTL ASC1 TX TTL ASC1 TX TTL ASCO DTR ASC1 RX TTL ASCO DSR EVM GPIOx ASCO XxTS SPI XXXX ETH xxx l2C GEN1 SDA SCL MOTOR XXXX EMRG TRP CAN1_RX TX VCC_CM 3V3 5V 12V 12VGND SGND Electrocomponents plc Vsn 1 1 Analogue signals Analogue ground referenced to CPU and Analogue application analogue signal grounds Pins that can only be set to 1 or 0 by a CPU instruction It has no special or alternate function Pins that have basic I O function like GPIOx but which also form an SM MMC card interface Pins that have basic I O function like GPIOx but which also form an 12S interface Pins that are used by the three C busses to request a CPU interrupt Note IRQ GPIO16 CNTRL I2C INT should always be reserved for use by the C CNTRL I2C bus Pins where CPUs with true digital to analogue converter outputs are always connected Alternatively PWM will be available if there is no DAC Pins which have basic I O function but which also can measure timed events pulse times and durations e g CAPCOM input Pins with basic I O function but which also can form a multiplexed address and data bus Pins which have basic I O function but which also can generat
3. The lC ADC on the analogue module can use the Vcc_CM or the local precision voltage references either 3V3 or 5V The 5V reference is driven from the 12V to guarantee no drop out problems As the anti aliasing filters are run at 5V the local ADC is not tied to the same voltage range as the CPU s ADC It is the user s responsibility to make sure that the input does not exceed the permissible input voltage range of the CPU ADC Protection resistors are provided to prevent damage 2 7 Limits and Restrictions Vcc CM max current 500mA 3V3 max current 2000mA BV max current 2000mA 3V3 current 5V current Vcc OM 2000mA SGND max current 2000mA 12VGND max current 2000mA Warning Only attempt to fit two CPU modules to the baseboard at the same time when you are really certain you know what you re doing If they have different peripheral supply voltages then damage is likely to occur Electrocomponents plc Vsn 1 1 Page 20 p PARInNAIme n TU ERR Radiospares RADIONICS RS 2 8 EDP Control Busses 2 8 1 lC Busses The EDP uses C as the data and control backbone Depending on the capabilities of the CM fitted up to three independent C busses are available I C channel CNTRL_12C is the primary lC device bus and is used
4. 98 AD3 Hi 97 AD2 5 i 96 AD1 ii 95 ADO i p 93 ALE i i 90 RD i i 91 WRL i i 75 WRH B is A16 st 52 7 CSO SRAM i 8 CS1 CS8900 4 9 CS2 z n 10 CS3 x 5 84 CAN1 RX s 87 CAN TX a i USB DEBUG D i USB DEBUG D 7 E 76 SCLKO a a 67 MRSTO Y 68 MTSRO 82 P42 7 25 SDA2 s 26 SCL2 M NG 82 NG 8 84 He 85 86 NG 8 88 CANH contro physical layer CAN1 89 90 CANL contro physical layer CAN1 gt 9 CPU s Vcc 3V3 or 5V 93 9 Voc 3V3 from reg 95 06 Vcc 5V from reg 97 98 Digital GND BE yo Amp 100 Way Electrocomponents plc Vsn 1 1 Page 13 z P APIS EDP BB 4A Technical Notes Radiospares RADIONICS RS 1 5 Inter Module Communication With up to four modules on the EDPCON bus some form of inter module communication is required With a limited number of CPU pins available it is necessary to use a serial communications protocol to for example take readings from a high precision ADC at the same time as read a serial EEPROM on a further module The IC protocol is used as the main communication channel for such actions although provision is made for SPI or even a CAN physical layer Possible Actual 7 bit 2 Actual 7 bit 2 PCD lC channel lC channel C t PCF8575TS 0x20 0x27 CNTRL XXXX XXXX DIP configuration switches TP aene 0160 0057 CNTRL CNTRL 4 Kbyte EEPROM D esses onc oar owe om o one our Ces omar on am on om om There are three possible I C channels availabl
5. GND For microcontroller systems such a collection of signals is of very limited use especially for single chip CPUs that use no external bus It also takes no account of the specialist pin functions available on microcontrollers such as CAN FC SPI signal measurement and signal generation peripherals Electrocomponents plc Vsn 1 1 Page 4 7 PARIAAIMe EDP BB 4A Technical Notes Radiospanes RADIONICS RS 1 3 1 Standardised Signal Set for Embedded Microcontrollers The EDPCON1 and 2 connectors thus defines a set of signals on a standardised format that are relevant to typical 8 16 and 32 bit microcontrollers In addition to address bus data bus and chip select signals they include three l C channels two CAN channels groups of pins able to create interrupts in response to external events groups of pins able to create pulse trains others dedicated to motor control IS memory cards and many other common microcontroller I O types All of these signals are contained within two 0 8mm dual row connectors of 140 and 100 pins each 3 4 au nr 7 8 ANT ANB n AN9 om f 12 a 13 14 ga mm 5 f m VAGND 7 18 VAGND GPIOD 19 20 21 2 23 24 25 26 27 28 29 30 31 3 3 34 RESIN 4 2 35 36 RESOUT 3 4 IRQ GPIOI6 CNTRLDCINT 37 3 2C GENO SDA Iz IRQ GPIOI8 DC GENO INT 39 P DENS 12 IRQ GPIO20 DC G
6. 12VGND at star point in baseboard Page 8 EDP BB 4A Technical Notes 3V3 Vbatt Radiospares RADIONICS RS Permanent 3V3 supply from Lithium cell on baseboard where fitted 1 3 3 2 EDPCON Signal Description RESIN Reset input to CPU module RESEOUT Reset out signal from CPU module where available I2C_GENO_SDA SCL Secondary I C bus data and clock where available SGND Digital logic ground connects to 12VGND at star point in baseboard Axx_ADxx 16 bit multiplexed address data bus when enabled by jumpers on CPU module ALE CPU module s address latch enable signal RD CPU module s READ signal WR CPU module s WRITE or WRITELOW signal WRH CPU module s WRITE or WRITEHIGH signal ZPSEN A16 CPU module s PSEN signal 8051 or A16 where available CSO CPU module s first chip select signal CS1 CPU module s second chip select signal CS2 CPU module s third chip select signal CS3 CPU module s fourth chip select signal CANO_RX TX Logic level connection to CPU module s first CAN module where USB DEBUG CNTRL SPI XX CNTRL I2C SDA SCL fitted USB signals connected to FTDI USB JTAG device on CPU module Signals connected to CPU module s first SPI peripheral Signals connected to CPU module s first or primary I C channel This is the I C control backbone for the EDP baseboard CANHO CANLO CPU module s first CAN module via physical layer drivers VCC_CM Peripheral operating
7. i deg 19 2 6 2 Analogue S pply iater Mint ie thin 20 2 7 Limits and Restrictions 20 2 8 EDP Control BUSs6S tete citer tte e Lade 21 2 8 1 PE a a isi ant 21 2 9 er bU 23 Electrocomponents plc Vsn 1 1 Page 2 f PARIAANIMme He EDP BB 4A Technical Notes sadiospares RADIONICS R5 1 The EDP System 1 1 Introduction 1 1 1 EDP Baseboard The EDP Baseboard or motherboard consists of 4 stations with the minimum configuration of the motherboard with a single plug in processor module All 4 stations are identical and there are many permutations of CPU modules and Application modules possible Even with just the minimum configuration of Motherboard and CPU module for example you can easily run a web server through the standard onboard Ethernet connection There are various application modules we have introduced an initial starter range consisting of basic digital and analogue I O a motor control module and a communications module The more advanced user will discover that it is possible to run more than one processor module on the motherboard in a Master and Slave configuration The motherboard is an Extended Euro card size 220 x 100 mm fitted with rubber feet to lay flat on the bench but able to be used in a standard rack system Add a 64 way DIN RS 381 8696 connector and you can plug the EDP into a backplane Connectors for four module stations are supplied arranged to ensure correct module
8. voltage of CPU module currently fitted 3V3 3V3 supply from baseboard voltage regulator 45V 5V supply from baseboard voltage regulator SGND Digital logic ground connects to 12VGND at star point in baseboard 1 4 The EDP Virtual CPU Concept A microcontroller that has its I O pins mapped appropriately onto the EDPCON1 and EDPCON2 connectors appears to be a virtual CPU to other I O devices fitted on the bus Thus for example a 14 bit ADC device on the EDPCON baseboard will see a CPU module also on the bus as a virtual CPU whose pinout is defined by the EDP bus Currently two popular microcontrollers Infineon XC167 and ST STR9 have had their I O pins mapped onto the EDPCON system These two devices have some features in common UARTs capture and compare pins ADC CAN but the STR9 also has USB device Thus the pin mapping to the EDPCON is not 100 in that on the XC167 version the USB device pins are unused Both devices have dedicated motor control peripherals which although they have different pin names have virtually the same functionality Hence for example a brushless DC motor control module with half bridges can be designed to interface to the motor control region of the EDPCON bus without any regard for the CPU type to be ultimately used The net result is that subject some limitations a range of modules bearing different CPUs can be freely connected to a range of I O modules The EDPCON has been designed to accommodate all th
9. 0 0000 0000 E oo 8 o o8B i B o e IE a ag no E L 8 pn u lo EL DOC CEBIT z S S B D I I La 100 OOO000o B B B umi LL TT nmonmonomonnnonmonnonnooononnnonunonnonnnarnonnonn oo O O Oo H TIEREN CCCII d DOONAN OECD CD CC CECI o DUDRDODRDUDONDDODDODIDODDODOOGDUDOIDOOODODTDODCTDOCIDOODODNUUN jn Dorm DODDDUYDIODNDODONDOCDOORORECUOBNOCCDOCREORRROINIOOOOROOEI oo R TIC doon 7 O000000000000000900000000000000000000000On o Oo a I o Oo oumanmonomocomeomooumoomonomosomeornoumnoomonenosomoom Oo O o OO O O Oo O goes EL CD CC CEBCUET A o a Sogo DDMTUDTTIIOOOORDOORODODRODORDDOODU TRO ce nnnn o ce O00000000000000000000000 e OOOO lOOOOOOOOOOOOOOOOOOOOOOO0 oooo O0000000000000000000000 0 O a O Ol020000000000000000000000 5 O O00000000000000000000000 0000 A 6 200000000000000000000000 o o o Oo 4 o Q1 Electrocomponents plc Vsn 1 1 Page 17 7 D ARABAIS EDP Technical Notes mnadiaspames RADIONICS 2 4 EDP I O Pin Headers All the signals in the EDP backplane are available here on 0 1 pin headers for connection to test equipment etc P601 P602 P603 AN10 1 2 ANS AN6 AN 2 ANIL 3 4 AN9 ANI4 ri VAGND 5 6 AN REF ANS AN 6 77 CPU DACOI_GPIOIS 7 8 EVM0 GPIO21 IRQ GPIO2 DC INT 8 CPU DACO0_GPIO17 8 GPIOIS LDSTX SDA EVMI GPIO23 9 10 GPIO25 ADI GPIO
10. 26 AD6 10 IRQ GPIO20 DC GEN INT 10 IRQ GPIO18 DC GENO INT GPI027_ADI4 uon GPIO29 ADI3 GPIO30 AD4 n IRQ GPIO16 CNTRL DC Int 12 GPIO14 MCIPWR GPI031_AD12 DM GPIO33 ADI1 GPIO34 AD2 14 GPIO0 BM GPIO MCIDATO GPIO35 AD10 15 16 GPIO37 AD9 GPIO38 ADO 16 GPIO D 16 GPIO3 GP1039 ADS 17 18 EVM2 GPIO4 CAPADC EVGI GPIO42 18 EVG2 GPIO44 GPIO4 MCIDATI 17 18 GPI06_MCIDAT2 EVM3 GPIO43 19 20 EVM4 GPIO45 EVG3 GPIO46 20 EVG4 GPIO48 GPIOS DSTX WS 19 20 GPIO7_DSRX_CLK EVMS GPIO47 n 2 EVM GPIO49 EVG5_GPIOSO 2 EVG6 GPIO52 GPIO9 DSRX WS 22 GPIO8_MCIDAT3 EVM7 GPIO51 B A4 EVMS GPIO53 EVG7 GPIO54 M EVGS GPIO56 GPIO10 MCICLK BU GPIO 1 DSRX SDA EVM9 GPIO55 5 26 EVG9_GPIOS7 EVG10_GPIOSS 6 EVGI2 GPIO60 GPIOI3 DSTX CLK 25 26 RESIN EVG11_GPIOS9 y EVGI3 GPIO61 EVG14 GPIO62 EVG16 GPIO64 RESOUT 2 DC GENO SDA EVG15 GPIO63 20 30 EVGI7 GPIO65 EVGI8 GPIO66 20 30 ASCO RX TTL DC GENO SCL 29 30 CNTRL SPI CLK EVG19_GPIO67 31 32 EVM10_GPI068_ASCO CTS ASCO TX TIL 31 32 ASCI RX TIL CNTRL SPI MRST 32 CNTRL SPIMTSR EVG20 GPIO69 ASCO RTS 3 34 SPI_SSC MRST_MISO ASCI TX TIL 33 34 ll ASCI TX TTL_ASCO DTR CNTRL SPI CS_NSS 33 CNTRL NC SDA SPI SSC MTSR_MOSI 35 36 SPI SSC CLK ASCI RX TIL_ASCO DSR ls 35 36 SPI SSC CS NSS CNTRLDC SCL 35 USB HOST D MOTOR POL 31 38 MOTOR POH ETH 37 38 USB HOST D 37 3 USB DEV D MOTOR PIL 30 40 MOTORPIH ETH 39 40 USB DEV D CANHO MOTOR P2L 4 4 MOTOR PH ETH LNK LED 4 4 CANLO D 3VBAT MOTOR PWM B4 EMG TRP ETH SPD LED B 4 DC GENI SDA vec CM D HV3 h MOTOR H0 ENCO 45 4
11. 6 MOTOR H1 ENCI LC GENI SCL 45 46 CANI RX 15v 4 SGND MOTOR H2_ENC2 41 4 MOTOR TCO FB CANITX 47 48 x DV 4 12VGND Header 24X2 Header 24X2 Header 24X2 P602 a 2 Electrocomponents plc Vsn 1 1 Page 18 z IPAPImAI e ne DB ha No Radiospares RADIONICS RS 2 5 Grounding Arrangements The system ground SGND and 12V ground 12V GND are connected together at a star point on the baseboard The 12V GND is used for high current devices like the motor controller and the Darlington output drivers on the digital I O module System ground is used for all returns on logic devices on all modules It can be used for analogue returns but there is a risk of noise ground bounce Analogue ground VAGnd by default is an offshoot of the system ground which occurs only on the CM It is routed to the VAGnd pins of the CPU and also acts as a return for filter circuits used for analogue inputs It is optionally possible to connect the SGND to the Analogue ground on the analogue module although this should not be necessary unless there are a large number of resistive sensors being used In this case the link connecting VAGnd and SGND on the CM must be opened to avoid ground loops This is determined by the CPU le design Itis not a movable link 12V anc
12. 7 D ARAIA EDP BB 4A Technical Notes Radiospares RADIONICS RS L o 2 o o L o o 9 D D D D LJ D LJ EJ LJ LJ LJ AXIULLITIITILIILIILLILLLILLLLZ ZT Embedded Development Platform EDP Baseboard EDP BB 4A User Manual Electrocomponents plc Vsn 1 1 Page 1 7 PARIMaunme He EDP BB 4A Technical Notes adiospares RADIONICS R5 Contents 1 The EDP System 3 1 1 Iggjore Ore itol n MT 3 1 1 1 EDP Baseboard teet ntn e guae ae n en eh ie aenean 3 1 1 2 Reusable Components 3 1 1 3 Bread Boarding Platform 3 1 2 EDP Modules Available NOW eene 4 1 3 Basic EDP Concepts ssh antennes 4 1 3 1 Standardised Signal Set for Embedded Microcontrollers 5 1 3 2 Grouping of Signals on the EDP Connectors ssssse 6 1 3 3 EDP Signal Names ri rte per ette teta tte xe coda 8 1 4 The EDP Virtual CPU Concept 9 1 4 1 Example of Real CPU to EDPCON Mapping 11 1 5 Inter Module Communication 14 1 6 Inter EDP System Communications esses 14 2 Using the EDP Baseboard 15 2 1 EDP GConnectols eret ere nee kel aiment etre 15 2 2 EDP Baseboard User Options Placement 16 2 3 EDP Baseboard Component Placement 17 2 4 EDP l O Pin Head rs e dtr tte et inet 18 2 5 Grounding Arrangements 19 2 6 Positive Supplies essent 19 2 6 1 LOGIC SUpplies 2 Interior tede itr etae
13. A ava 12C_GENO I2C GENI Only CMs can optionally have pull ups to 3V3 Electrocomponents plc Vsn 1 1 Page 21 7 PARIMaAIme nc EDP Technical Notes Radiospares RADIONICS RS 2 8 1 1 Available I C Interrupt Request Lines Each of the three potential I C channels has a dedicated interrupt request line into the CM A spare interrupt line is provided that can be allocated to any channel as defined by the user However it is up to the user to make sure that the software is able to recognise the l C device that requested the interrupt I2C CTRL IRQ GPIO16 CNTRL l2C integral pull ups I2C GENO IRQ GPIO18 GENO l2C integral pull ups I2C_GEN1 IRQ GPIO22 GEN1 l2C integral pull ups Uncommitted IRQ GP1024_12C_INT integral pull ups Electrocomponents plc Vsn 1 1 Page 22 r PARInNANIme n EDP ERR Radiospares RADIONICS RS 2 9 CAN Network The on board CAN network CAN CNTRL is intended to allow the interconnection of modules and other EDP systems via CAN The first CAN module on any CPU is by default allocated to the CANHO and CANLO bus This is the CAN physical layer i e after the CAN transceivers and can run at up 1MB s The 120R termination resistors at the ends of the network are located on the CM and at the end of the baseboard that carries the Ethernet and USB connectors If the CAN CNTRL bus is taken off board via the DIN41612 expansion connector then the 120R resistor on the baseboard must be disconn
14. ANO TX Vcc to BB Vcc 3V3 from reg Vcc 5V from reg Digital GND 12V 2A 12V 2A 12V Power GND 12V Power GND Electrocomponents plc Vsn 1 1 Tyco Amp 140 Way Page 12 Radiospares RADIONICS RS XC167 Pin And Function NC 30 AN1 32 AN3 34 AN5 40 AN7 38 AN9 36 AN11 44 AN13 46 AN15 GUARD AN GND 80 P4 0 81 P4 1 64 P3 5 65 P3 6 66 P3 7 12 CC5IO 13 CC6IO 14 CC7IO 25 CC20IO 26 CC2110 127 CC2310 124 CC2210 POH 7 POH 6 POH 5 POH 4 POH 3 POH 2 POH 1 POH O 18 CC3110 cs8900A INT 17 CC3010 16 CC2910 15 CC2810 134 CC2710 133 CC2610 132 CC25IO 131 CC2410 24 CC19IO 23 CC18lO 22 CC17IO 21 CC1610 56 CC1510 55 CC1410 124 CC2210 121 CC62 128 MRST1 129 MTSR1 130 SCLK1 117 CC60 118 COUT60 119 CC61 120 COUT61 121 CC62 122 COUT62 123 COUT63 124 CTRAP 127 8C6POSO 128 C6POS1 129 4C6POS2 61 CAPIN 3V3 Vbatt Vcc to BB Vcc 3V3 from reg Vcc 5V from reg Digital GND 12V 2A 12V 2A 12V Power GND 12V Power GND 7 D AMIMAIIP EDP BB 4A Technical Notes Radiospares RADIONICS R5 1 4 1 2 Infineon XC167 EDPCON2 Mapping 142 RSTIN 1 2 3 RSTOUT 23 SDA1 5 6 24 SCL1 8 Digital GND 9 40 116 AD15 11 12 115 AD14 13 14 114 AD13 15 16 113 AD12 17 18 112 AD11 19 2 111 AD10 94 106 AD9 4 105 AD8 25 26 102 AD7 7 28 101 AD6 29 30 100 AD5 ib 99 AD4 33 34
15. C NTON f z mooom N o 2 0 oO S L A Tonto 3 A DITOTEDUODSCTONDTTDOTRIOOOIODORICDOURNODOEDOODIDOOCIOHIOODONCOO 00 O Lu og OUEN OUEN NOONAN Oo oo AAA ocr ws EROTOQDRIEOEEOOOGOOQIQODIENGTDORGTTHEDIDEINOXTOU O O o AFO O O O P501 12V high current E coco CDN screw terminals S Sogo S ONMNENNONNONNNNNENNANONNNNNTIONTTNE g J502 12V 2A jack socket P601 IO pin headers F trro Bo 3 oF o o o On O le 9 9 3 OOo O O 3 Oo ojo ojoo ool OO OO OO Oo OO OO OO OO 0000 P602 IO pin headers P603 IO pin headers P504 Connect CPU analog ground to system ground 3 50 SGND 3 50 o o o o o 9 oo olo olo o o olo ollo o 0010 0100 Olooloo oo o olo oloo oolooloo oolo ollo o oo o olo o oolo oloo o olo olo o o olo olo o o olo olo o o olo olo o oolooloo o olo olo o oo loo o Oo Oo Oo Imo o o o o Electrocomponents plc Vsn 1 1 Page 16 7 PARIALIMe TEN Radiospares RADIONICS R5 2 3 EDP Baseboard Component Placement The location of the major items on the EDP baseboard is shown below O LIOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO oo g O 0 0 O 0000 9000 mH 5089 0000 ngon 00000000 DODD OI A E DDDRDORIDOOROIOOORIOBOCITODRDORIYDOOTETOEDOCIDNEDOROIDOIE 00000000 0000 000
16. ENI INT 41 4 SGND l5 N 43 A15 ADIS i5 i 45 46 1 13 14 47 48 1 15 16 49 50 1 17 18 51 52 19 20 53 54 24 2 55 56 23 24 57 58 1 25 26 59 60 127 28 61 62 29 30 63 64 1 3 32 65 66 1 3 34 67 68 35 36 69 70 1 37 38 71 72 39 40 is n 41 42 75 76 43 m 7 T8 1 45 46 79 80 1 47 48 81 82 1 49 50 83 84 51 52 85 86 1 53 54 87 88 55 56 89 90 1 57 58 91 92 9 60 m o a E SCIT SCO DTR Y TS a 30 65 66 T 99 100 67 68 101 102 65 70 103 104 CNTRL SPI MRST n D 105 106 CNTRLSPIMTSR n n 107 108 CNTRL NSS 75 76 109 110 CNTRL EC SDA Im 78 111 112 J CNTRLI2C SCL m a 113 114 EMG TRP i USB HOST D la 2 115 116 USB HOST D lg 117 118 SE 95 86 1t9 120 E lg 88 121 12 a 90 123 124 CANLO ot 9 cu 125 126 VCC_CM lt amp 93 9 a 127 128 3V3 lt f 05 96 y lt z 129 130 e g lo 98 i 131 132 SGND f 9 100 133 134 D 135 136 Tyco Amp 100 Way 137 138 139 140 Tyco Amp 140 Way Electrocomponents plc Vsn 1 1 Page 5 EDP BB 4A Technical Notes 1 3 2 Grouping of Signals on the EDP Connectors The EDPCON1 and 2 connector specification divide the total available 240 pins into groups or regions of similar characteristics as shown below 1 3 2 1 EDPCON1 Connector I O Regions EDPCON1 carries both analogue and digital signals The analogue signals are grouped together in a quiet zone Analog Reference Analog channels region Analog Ground AGN ks 21 Gen
17. EVM10_GPIO68_ASCO CTS ASCOTXTIL z EVG20_GP1069_ASCO RTS ASC RX TIL SPI SSC MRST MISO ASCI TX TIL os o6 SPI SSC MISR MOSI ASC TX TIL ASCODIR es EE SPI SSC CLK ASCI RX TIL ASCO DSR 90 00 MOTOR POL SPi SSC 8CS_NSS 1 MOTOR POH ETH TX a 5 MOTOR PIL ETH TX MOTOR PIH ETH RX MOTOR PIL ETH RX EIHINKLED EIHRXLED EIHSPDLED DC GENI SDA DC GENI SCL CAN RX CANI TX VCC_CM lt CS0 CS1 CS2 CS3 CANOTX DVCC_CM D 3V3 gt 5V SGND Tyco Amp 100 Way EDPCON2 Connector Tyco Amp 140 Way EDPCON1 Connector Electrocomponents plc Vsn 1 1 Page 15 DADIONI c EDP Technical Notes mnmadiospames RADION 2 2 EDP Baseboard User Options Placement There are a number of user selectable functions on the baseboard as shown below 100 00 mm 3 50 3 50 T N 1 a LIOOOOOOOOOOOOOOOOOOOOOOOOOOCOOOOO o o o 9 Qooooooo000OQO90000000 00000000009 v L oo 8 8 8 8 8 OQ1 0080 noon 0000 pg 29 S502 BW DIP switch to _ _ _ 20000000 1 allow user settings via I2C T B LIDTDXYDIDOOCOTOOCOOOOOOCOOUDOIOUDAIAITDIOOOS T 8W DIP switch I2C SX oun i O S501 CPU reset ec oo oo f E address AO o a j ott a a g Ta OODOOOTOOOOUMONONOOMODODOOOMOOMNONMNO P401 CAN CTRL 120R S 88 AO terminating resistor Do B i J601 J603 EEPROM ae I2C addresses E0 E1 E2 B 000000000000100000001000000000000000000M0000 000000000000000 A CL ooo moomoo a a O0 OO O C o DON
18. PIO1 CAPADC 6 64 E PIO EVA GPIOUS T EWS GPIOUT 69 70 EVM _GPIO49 n 72 EVW _GPI0St 73 14 EVM8 GPIO53 15 76 EVM GPIOSS 1 78 79 80 8 82 83 M 85 86 8 88 89 90 91 92 93 94 95 96 97 98 99 100 MOTOR POL 11 102 i MOTOR 107 108 MOTOR PA 109 410 MOTOR P2H 111 112 MOTOR PWM 113 114 EMG TRP 115 116 MOTOR H ENCO 417 118 MOTOR HI ENCI 119 120 Mods 11 2 n DONE 123 124 epe 125 126 an Sash 127 128 T 129 130 sw L 1 132 N 1 133 134 Ha 135 136 weno 187 138 8000 139 140 Tyco Amp 140 Way Page 6 Electrocomponents plc Vsn 1 1 7 Ia EDP BB 4A Technical Notes Radiospares RADIONICS R5 1 3 2 2 EDPCON Connector Regions EDPCON carries mainly bus signals such as IC SPI CAN and the multiplexed 16 bit external bus from the CPU module CPU Reset IN amp OUT uel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 CAN RX TX 61 62 63 64 65 66 67 68 69 70 n 72 73 74 75 76 T 78 70 80 8 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 SGND 99 100 Tyco Amp 100 Way Electrocomponents plc Vsn 1 1 Page 7 EDP BB 4A Technical Notes RadiospaRres RADIONICS 1 3 3 EDP Signal Names The generic signals present on the connectors have names which indicate their primary and secondary functions
19. by default to communicate with I C devices on the baseboard and application modules The lC address space is based on the 7 bit addressing scheme C devices that are able to generate an interrupt request by default use the IRQ GPIO16 CNTRL I2C INT line with the option of using up to another three interrupt capable lines A pull up resistor is provided on IRQ GPIO16 CNTRL 12C INT so that the open collector INT outputs on l C devices can signal an interrupt by pulling this line down The IC bus runs at 3V3 so any 5V devices must be connected via a level shifting mechanism The C bus devices require pull up resistors on the SDA and SCL lines and these are incorporated on the baseboard There are three possible I C channels available although in most cases the default one I2C_CTRL will be sufficient EDP modules that carry I C device do where possible allow the user to configure the I C addresses This allows for example up to three digital I O modules to be fitted with the GPIO devices on each module given a unique address Where the address space of a particular IC channel becomes full devices can be connected to an alternative channel to get access to a completely new address space 3v3 IRQ GPIO16_CNTRL_12C IRQ GPIO18 GENO I2C IRQ GPIO22 GENI I2C IRQ GPIO24 120 INT M SCL CNTRL_12C D
20. e events like timed pulses and transitions e g CAPCOM output Pins which have basic I O function but which also can measure pulse times and durations e g CAPCOM input If the CPU supports the triggering of ADC readings on an edge the function will be on this pin Logic level connection to CPU module s serial port 0 receive pin Logic level connection to CPU module s serial port 0 transmit pin Logic level connection to CPU module s serial port 1 receive pin Logic level connection to CPU module s serial port 1 transmit pin If CPU supports DTR function on ASCO the function is available here If CPU supports DSR function on ASCO the function is available here Event measurement general I O and ASCO RTS and CTS functions where available Pins associated with SPI function where supported by CPU module Pins connected to an Ethernet PHY on CPU module where available Pins connected to CPU s C channel 1 Pins required for driving three phase AC and DC brushless motors including inputs for Hall sensors and tachometers or other speed related signals Emergency stop trip function for motor control Logic level connection to CPU module s second CAN module where fitted Peripheral operating voltage of CPU module currently fitted 3V3 supply from baseboard voltage regulator 5V supply from baseboard voltage regulator Raw 12V from power input to baseboard Ground connection to power supply Digital logic ground connects to
21. e although in most cases the default one I2C_CTRL will be sufficient EDP modules that carry I C device do where possible allow the user to configure the IC addresses This allows for example up to three digital I O modules to be fitted with the GPIO devices on each module given an unique address Where the address space of a particular 1 C channel becomes full devices can be connected to an alternative channel to get access to a completely new address space 1 6 Inter EDP System Communications In a situation where there are multiple EDP baseboards each with their own CPU modules in a complete system an IC bus can still be used to allow the CPUs to communicate but the use of a CAN bus is strongly recommended EDP I O signals that are intended to be taken off board are brought out on a standard DIN41612 64 way connector Electrocomponents plc Vsn 1 1 Page 14 EDP BB 4A Technical Notes Radiospares RADIONICS RS 2 Using the EDP Baseboard This section gives information on the features of the EDP baseboard its connectors and the overall structure of the EDP system 2 1 EDP Connectors The EDP bus contained in the EDP baseboard is accessed through two Tyco AMP 0 8mm pitch connectors The signal names are intended to convey something of the capabilities of that signal For example signal EVGO_GPIO40 is a pin that can generate timed events i e pulses and pulse trains as well as performing simple on off pin control EDPCONI IO Co
22. e common peripherals found on current microcontrollers including advanced interfaces like SD MMC and lS Thus it is possible to map almost any microcontroller to this format Electrocomponents plc Vsn 1 1 Page 9 mnadiospgames EDP BB 4A Technical Notes Nd9 IENUIA Uld OVE NOOdQ3 Nd9 IENHIA Uld OVE NOOdQ3 Page 10 Vsn 1 1 Electrocomponents plc f PARIAANIMme He EDP BB 4A Technical Notes sadiospares RADIONICS R5 1 4 4 Example of Real CPU to EDPCON Mapping This is the mapping developed for the Infineon XC167 and used on the RS EDP CM XC167 module 1 4 1 1 Infineon XC167 EDPCON1 Mapping This mapping assigns the XC167 pins and hence peripherals into the appropriate regions on the EDPCON1 connector Electrocomponents plc Vsn 1 1 Page 11 EDP BB 4A Technical Notes XC167 Pin And Function 41 VAREF 29 ANO 31 AN2 33 ANA 39 AN6 37 AN8 35 AN10 43 AN12 45 AN14 42 GUARD AN GND 92 P20 2 128 MRST1 62 P3 3 63 P3 4 129 MTSR1 130 SCLK1 77 P3 15 83 P4 3 P3 2 P3 5 P3 6 P3 7 POL 7 POL 6 POL 5 POL 4 POL 3 POL 2 POL 1 POL O 49 CC8IO 50 CC9IO 51 CC10lO 52 CC1110 53 CC1210 54 CC1310 55 CC1410 56 CC15lO 8 CC1IO 9 CC2IO 10 CC310 11 CC4IO 12 CC5IO 13 CC6IO 70 RxDO 69 TxDO 60 RxD1 59 TxD1 NC P20 2 83 P4 3 Ethernet TX CS8900 Ethernet TX Ethernet RX Ethernet RX Ethernet LINK LED Ethernet RX LED NC NC NC 85 CANO RX 86 C
23. ected by removing the P201 link The CAN CNTRL bus is available through a 9 way D connector on the optional EDP AM CO1 A communications module Make solder bridge when CAN CTRL is only used on baseboard Default closed Only CMs have 120R resistor Electrocomponents plc Vsn 1 1 Page 23 r D ARIANA SC neg E TENA Radiospares RADIONICS RS Hitex UK Ltd Electrocomponents plc Page 24
24. eral IO pins that have no interrupt capability but which may have an SD MMC card interface General IO pins that have an interrupt capability General IO pins that have no interrupt capability or which form an external multiplexed address and data bus IO pins with CAN functionality 2 AVR Sunniy Digital Ground SGND 12V Power Ground 12V GND Analog channels region pi true digital to analog conversion mode General IO pins that have no interrupt capability or which form an external multiplexed address and data bus General IO pins that have an interrupt capability and are able to measure the edges of pulsetrains or timed edge transitions e g capture compare capture pins 10 pins that have specific motor driving functions Baseboard backup battery CPU Peripheral Supply Voltage AN REF 1 2 x ANO 3 4 AN1 AN2 AN3 AN4 ANS MEE z AN10 n g AN11 AN12 f 14 AN13 15 16 ANTA 1 8 ANIS 20 GPIO MCIDATO 2 A PIO4 MCIDAT 25 2 POB MODATS a 2 L 29 30 GPIO10 MCICLK 31 32 GPI012 MCICMD DL 3 A 35 36 a ET 4 42 ED GPIO2 IROGPOZ i 43 4 EWM GP023 GPIO24 ADT 45 46 P1025 AD15 GPIO26 ADS 4 48 GPIOZI AD 4 GPIO28 ADS 49 50 P1029 4013 GPIO3 AD4 GPIO31 4D12 GPIO32 AD3 a A GPI033 ADI GPIOM AD2 55 56 P1035 AD10 GPIO35 ADI GPI037 ADS GP1038_ ADO 2 GPI039 ADS EVG 6 61 EVO G
25. fitting There are also fitted 3 3V and 5V voltage regulators a back up battery an RJ45 Ethernet connector a mini USB connector 12 volt power supply jack I O breakout header and eight DIP switches ported onto the system C bus The DIP switches allow the user software running on a processor module to read a configuration setting enabling I O ports to be set up correctly for example or for CAN or TCP IP addresses to be set Depending on the capability of the particular processor module in use up to three C buses and two CAN networks are available Many of the application modules use an IC bus for primary communication with the processor providing maximum flexibility Some processor chips will require 5 volts others 3 3 volts A factory link on the module selects the correct supply from the connector This supply is linked to a further connector pin on all the other module stations providing a correct voltage reference or bus pull up for the application modules 1 1 2 Reusable Components The EDP baseboard is designed to be used and reused with new CPU and application modules being introduced on a regular basis Its robust design has been rigorously tested and every effort has been made at the design stage to protect the EDP from the most common human errors the motherboard will have a significantly longer life than the average development board and is suitable for use in specialist one off and low volume products Typical applications m
26. ight be industrial controllers scientific instrument controllers data logging and remote monitoring For these reasons the EDP will prove attractive to all design engineers looking for a cost effective solution which allows them to significantly improve their development process and thus deliver products in reduced time Design engineers consultants educators and trainers will quickly realise the benefits and recognise the potential of the development platform modules system as an effective solution 1 1 3 Bread Boarding Platform With the difficulty in applying traditional bread boarding techniques to today s tiny SMT components evaluating new active devices has become major problem There is usually no alternative to creating a special try out PCB using rapid PCB production houses just to get a new device up and running Electrocomponents plc Vsn 1 1 Page 3 mAmnminamnme nece EDP BB 4A Technical Notes Radiospares RADIONICS RS The EDP has been designed to host such experimental and trial designs providing clean 5 and 3V3 supplies and instant access to a range of standard microcontrollers and I O blocks and devices The design information necessary to allow you to create your own module for experimenting with new devices is available free of charge but in many cases RS will already have such a module available to save you the effort The EDP represents the start of a continuous launch process which will see the int
27. nnector nol EDPCON2 Bus Control Connector GPIO1 DSRX SDA GPIOI3 DSTX CLE GPIOIS DSTX SDA RQ GPIOI6 CNTRLDCINT gt CPU DACO0_GPIOI7 RESIN RQ GPIOIS DC GENUINT i yd CPU DACO _GPIOIS RESOUT RQ GPIO20 INC GENT INT EVMO GPIO2I DCE J102 RESIN RESOUT DC GENO SDA RQ GPI022 DC INT P EVMI GPIO23 DC GENO SCL DC GENO SCL GPO ADT GHO3 ADIS SGND PION ADS GPIO ADI4 AL AL GPIO23 ADS GPION_ADI3 at GPIO30 AD GPIO31 ADI RUE AADIS A Al2_ADI2 Al2_AD12 GPIO33 ADS GBO33 ADI ADIT RADE GPIO34 AD2 GPIO3S ADI0 CPIO3S ADT EL GPIO38 ADO jl GPIO39 AS ADS EVG0_GPIO lt 0 AT ADT EVGI GB 1 s EVG GPIO44 1S ADS EVG3 GPIO46 z EVGS GPIO4S a EVGS GPIOSO EVM7 GPIOSI A10 ADIO A9 ADS AS ADS A7 ADT A6 AD6 AS ADS A4 AD4 A3 AD3 A2 AD AL ADI A0 ADO ALE RD EWR A4 ADS A3 AD3 A2 AD2 Al ADI A0 ADO ALE RD WR WRH SPSEN CSO0 CS1 CS2 CS3 CANO RX CANOTX USB DEBUG D USB DEBUG D CNTRL SPICLK F CNTRL SPICLK 7 5 CNTRL SPI MRST CNTRL SPIMTSR 5 CNTRL SPIMTSR CNTRL SPI amp CS NSS A i CNTRL SPI CS_NSS CNTRL DC SDA 2 CNTRLDC SDA CNTRL DC SCL 3 CNTRLDC SCL USB HOST D USB HOST D USB DEV D USB DEV D CANEO CANLO EVG GPI052 EVMS GPIO53 EVG GP1054 E EVMS_GPIOSS EVG8_GPIOS6 EVG9_GPIOS7 EVG10_GPIOSS EVG11_GPIOS9 EVGl2 GPIO60 EVG13 GPIO61 EVGl4 GPIO62 3 EVG15 GPIO63 EVG16_GPIOG EVG17 GPIO65 EVGlIS GPIO66 EVG19 GPIO67 ASCO RX TIL 1 o0
28. roduction of new processor and application modules on a monthly basis 1 2 EDP Modules Available Now Processor Module ST Microelectronics STR912 Processor Module Infineon XC167 Application Module Analogue Input Application Module Digital Input Output Application Module Brushed DC Motor Control Application Module Basic Communications 1 3 Basic EDP Concepts The EDP allows microcontrollers and I O devices to communicate through a standardised interface To some extent this interface is analogous to PC104 or STE busses where a connector pin out is defined that allows the interconnection of address and data bus connected devices Such busses tend to include only power line data and address busses plus control signals such as chip selects and interrupt request lines 1 IOCHCK GND 2 7 RSTDRV 3 D6 5V 4 D5 IRQ9 5 D4 5V 6 D3 DRQ2 7 D2 12V 8 DI ENDXFR 0 GND GND 9 Do 12V 1 MEMCSI6 SBHE 0 IOCHRDY GND KEY 2 1OCS16 LA23 I AEN SMEMW 3 IRQIO LA22 2 Ald SMEMR 4 IRQII LA21 3 Als IOW 5 IRQI2 LA20 4 AI7 IOR 6 IRQIS LAI9 5 A16 DACK3 7_ IRQI4 LAIS 6 AIS DRQ3 8 DACKO LAI7 7 AW DACKI 9 DRQO MEMR 8 AI3 DRQI 0 DACK5 MEMW 9 Al2 REFRESH 1 DRQS SD8 20 All SYSCLK DACK6 S 21 A10 IRQ7 DRQ6 S 22 A9 IRQ6 DACK7 5 23 A8 IRQS DRQ7 S 24 A7 IRQ4 5V SD13 25 IRQ3 MASTER
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