PAN1321 Specification
Contents
1. ooooooooommooo Pad Driver and Input Stages Pull ups and Pull downs Protection Circuits eee ee eee System Power Consumption AC Characteristics o oooooooooooo o HE Parts RR AA Characteristics RF Part Bluetooth Related Specifications User s Manual Hardware Description Table of Contents Revision 3 2 2011 10 17 PAN1321 SPP Panasonic BA Table of Contents 7 Package Information a PAKO DAGSA DAR ana Rd Ree ADA BEA INDANG A 28 7 1 Package Markingi iii elt e a riw s F Rel A RR Ree EEE o 28 7 2 Production Package sulle e uere ue bal uer Peu uer d e RANG 28 7 2 1 PIM TK SE 29 8 Important Application Information o 30 8 1 Reference Design icc us dao isis hr ER ee ad Epi AERE ER plaid ES 30 8 2 FCC Class B Digital Devices Regulatory Notice liliis 31 8 3 FCC Wireless Notice een a emer ue EAR EG Ru EAE ERA enero 31 8 4 FCC Interference Statement llli rn 32 8 5 FCG Identifier LP A a ag ajan ak dead PANA PANG 32 8 6 European R amp TTE Declaration of Conformity aaa aaa 32 8 7 Bluetooth Qualified Design ID 1 RI IIR aaa aa aaa 34 8 8 Industry Canada Certification rn 34 8 9 Label Design of the Host Product iilis eee ae 34 8 10 Regulatory Test House s aa ciudad Aak kapa KAKAK BA ERR DER EA Dba e e ido 34 9 Assembly Guidelines a aa a hn 35 9 1 General Description of the Module2. aa a aaa aa aa aaa aa aa aaa ea 35 9 2 Printed Circuit Board Design ccc aa aaa a aa aa aa aaa aaa eee 35 9 3 Solder Paste Printing nasa saa asa aa aa a NEGEN aa i anana E a san aan rn 35 9 4 Assembly ceni ls Ag ANK a eee Weis ede A Lea EORR pus ER UR m 36 9 4 1 Component Placement ehh hn 36 9 4 2 AA AA ald dee da 36 9 4 3 gie KEN PERPE 37 9 5 Soldering Profile a ku aana AA ave ben dox weer Road ik RO EUR s 38 9 6 HOWOIK cas BG BA i e eae en ieee Inc SAR a 39 9 6 1 Removal Procedure sos Na NAGA KPA ARA whee RU ERE vu RE eo ee add LR 39 9 6 2 Replacement Procedure 00 cee ee hh 39 9 6 2 1 Alternative 1 Dispensing Solder 00 cee tenes 39 9 6 2 2 Alternative 2 Printing Solder 0 0 00 aa aaa aa aa aaa teens 40 9 7 Inspection sa aaa A aa aa gi he erum A a a aaa 40 9 8 Component Salvage ss cuts es nee s ee ee ee rA TR ee OR a ae ee 40 9 9 Voids in the Solder Joints zina araci ka kasan aaa aan m rn 41 9 9 1 Expected Void Content and Reliability aa eee 41 9 9 2 Parameters with an Impact on Voiding eaaa eae 41 10 Terminology as cc he eee dhe ead Ba NGA rd Lig 43 11 Heterences 1 oss KW ak nk hhe ha eed E wk ta este pes i RE E eds 47 User s Manual 5 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic PAN KACE List of Figures List of Figures Figure 1 Simplified Block Diagram of PAN1321 SPP aaa a ees 9 Figure 2 Pin Configuration f
3. Figure 8 N T o T s e N m e 2 2 gt 0 tc e mo C 2 2 _ BE So sa o oo nO DI PAN1321 SPP Panasonic a Important Application Information ENW89811K4CF 22 xx is intended to be installed inside end user equipment ENW89811K4CF 22 xx is Bluetoooth qualified and also FCC certified and Industry Canada approved and conforms to R amp TTE European requirements and directives with the reference design described in Figure 8 FCC certification is valid together with the following antennas having in mind that this module has the Johansson antenna included Table 17 Antennas Manufacturer Model Type Peak antenna gain Impedance GigAnt Titanis Swivel 4 dBi 50 ohm Tyco Electronics P N 1513151 1 Module 4 dBi 50 ohm Murata LDA312G7313F 237 Ceramic chip 0 dBi 50 ohm Infineon reference design Printed inverted F Antenna 4 dBi 50 ohm PIFA Johansson 2450AT43A100 Ceramic chip antenna 2 dBi 50 ohm Inwave BST 2450 Dipole antenna 2 dBi 50 ohm When using any of the above antennas installed in the appropriate manner it is possible to re use the approvals for the end product It is however required to have a written consent from Infineon Technologies AG to re use the regulatory approvals for the FCC Canada and Europe Manufacturers of mobile fixed or portable devices incorporating this device are advised to clarify any regulatory questions and to have their complete produc
4. Pin 1 A1 is marked on bottom footprint and on the top of the shield on the module according to Figure 7 Diameter of pin 1 mark on the shield is 0 15 mm PAN 1321 22 07 ENW89811K4CF 0902401 FCC ID T7VEBMU PT T E Pin 1 marking top side Pin 1 marking bottom side Figure 7 Top View and Bottom View User s Manual 29 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP ENW89811K4CF Important Application Information Panasonic 8 Reset 3U 3 3k m 3 ba C6 1088n i sol Reset l5 Ic3 Power Supply Section 3U E s 22 S A am IC26 2 Serial Level Converter ON OFF ak 3U 3U 3 3k R Modul Connector BE ACTIVE IMS IBST ICK CK ANTENNA PAN13XX Power Sel Ext Int ONOFF 339 R11 UART1 TXD RXD Important Application Information Reference Design JTAG Mode UDDUART ON OFF 2 UDDURRT UEXT 3172 JP1 Function 1 2 Use On Board regulator 2 9 Connect directly to input UDDPCM ON OFF PAN 13XX Application Board c 2009 Panasonic Reference Design Schematics TITLE Reference Design PAN13xx Document Number REU 1 2 Date 19 08 2010 10 52 42 Sheet 1 1 8 1
5. C4 TRST l Internal2 PD PD JTAG interface D1 P0 10 O OD Internal2 Z Z Port 0 10 D2 P0 8 O OD Internal2 PD PD Port 0 8 D3 P1 1 l O OD Internal2 PU PUN Port 1 1 or TCK JTAG interface D4 PO 3 l O OD VDD1 Conf Conf Port 0 3 PD def PD def D5 P0 2 O OD VDD1 Z Z Port 0 2 E1 P0 12 SDAO 1 0 OD Internal2 PU PU 12C data signal E2 P0 13 SCLO 1 0 OD Internal2 PU PU 12C clock signal E3 P1 3 O OD Internal2 Z Z Port 1 3 or TDO JTAG interface E4 P0 0 O OD VDD1 PD PD Port 0 0 LPM wakeup output E5 P0 1 O OD VDD1 PD PD Port 0 1 E6 P0 5 O OD VDDUART Z Z Port 0 5 or UARTRXD UART receive data F2 P1 2 l O OD Internal2 PU PUD Port 1 2 or TDI JTAG interface F3 P0 11 l O OD Internal2 Z Z Port 0 11 User s Manual 10 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF General Device Overview Table 1 Pin Description Pin Symbol Input Supply Voltage During After Function No Output Reset Reset F4 P0 14 1 0 VDDUART Z Z Port 0 14 LPM wakup input F5 P0 7 l O OD VDDUART Z Z Port 0 7 or UARTCTS UART CTS flow control F7 P0 4 l O OD VDDUART PU PU Port 0 4 or UARTTXD UART transmit data F8 P0 6 l O OD VDDUART PU PU Port 0 6 or UARTRTS UART RTS flow control A4 VSUPPLY SI Power supply A5 A6 C1 VREG SO Regulated Power supply F6 VDDUART SI UART interface Power supply C5 VDD1 SI Power supply A1 VSS Ground A7 A9 C8 C9 D7 D8
6. E8 E9 F1 F9 1 Fixed pull up pull down if JTAG interface is selected not affected by any chip reset If JTAG interface is not selected the port is tristate Descriptions of acronyms used in the pin list Acronym Description Input O Output OD Output with open drain capability Z Tristate PU Pull up PD Pull down A Analog e g Al means analog input S Supply e g SO means supply output User s Manual 11 Hardware Description Revision 3 2 2011 10 17 PAN1321 SPP m Panasonic e General Device Overview 1 5 System Integration PAN1321 SPP is optimized for a low bill of material BOM and a small PCB size Figure 3 shows a typical application example AT command interface SPP Serial Port Profile API RFCOMM BT Baseband Voltage BT RF Regulator VSUPPLY Antenna Example Application PAN1311 vsd Figure3 Example of a Bluetooth System using eUniStone User s Manual 12 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic Ba General Device Overview The UART interface is used for communication between the host and PAN1321 SPP The lines UARTTXD and UARTRXD are used for commands events and data The lines UARTRTS and UARTCTS are used for hardware flow control Low power mode control of PAN1321 SPP and the host can be implemented in by using the pins P0 14 and PO 0 P0 14 is used by the host to
7. if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered PAN1321 SPP Panasonic aaa ENW89811K4CF 22 xx Infinion s BlueMoon Universal Platform Revision History 2011 10 17 Revision 3 2 Previous Version 3 1 Page Subjects major changes since last revision Rev1 0 Initial version Rev2 0 Due to better range with another ceramic antenna we have updated module height from 1 8mm to 2 8mm Changes made in Production Package on Page 28 If you need smaller height let us discuss your individual case Rev3 0 Releasing this document and correct the ordering code to ENW89811K4CF which is the 85 C version Rev3 1 Add the Chapter 8 Modified Figure 5 Package Marking on Page 28 and Figure 7 Top View and Bottom View on Page 29 Rev3 2 Fixed all pins for the product life time in Chapter 1 4 Added Table 2 Firmware Releases as of 2011 10 17 on Page 13 and updated the Chapter 11 Trademarks of Infineon Technologies AG used in this document BlueMoon User s Manual 3 Revision 3 2 2011 10 17 Hardware Desc
8. 2 Block Diagram EEPROM 7 VDD1 Ceramic Antenna VDD_UART UART Filter GPIO Matching V supply Voltage Regulator Crystal 26 MHz PAN1321 Block Diagram vsd Figure 1 Simplified Block Diagram of PAN1321 SPP 1 3 Pin Configuration LGA 1 06 S 1 O O e O O O e O O e Figure 2 Pin Configuration for PAN1321 SPP in Top View footprint User s Manual 9 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF 1 4 Pin Description All mentioned pins are fix for the product lifetime Pins not listed below shall not be connected General Device Overview Table 1 Pin Description Pin Symbol Input Supply Voltage During After Function No Output Reset Reset A2 P1 6 l O OD Internal1 Z Z Port 1 6 A3 RESET Al Internal Input Input Hardware Reset active low A8 P1 5 l O OD Internal1 Input Input Port 1 5 B1 P1 7 l O OD Internal PD Input PD Input Port 1 7 B2 P1 8 O OD Internal1 PD PD Port 1 8 B3 P1 0 O OD Internal2 PUN PUN Port 1 0 or TMS JTAG interface B4 P1 4 l O OD Internal2 Z Z Port 1 4 or RTCK JTAG interface B5 ONOFF Connect to VDD1 and refer to chapter 11 item 3 B9 SLEEPX 1 0 VDDUART PD H Sleep indication signal C2 P0 9 O OD Internal2 Z Z Port 0 9 C3 JTAG Internal2 PU PU Mode selection Port 1 0 JTAG 1 Port
9. 4 Absolute Maximum Ratings 2 2 aaa aaa a aaa aaa eae 20 Table 5 Operating Conditions rsson p acce ata EROR RUE Kg Sed a a ORT e 20 Table 6 Internal1 1 5 V Supplied Pins aaa aaa RII 21 Table 7 Internal2 2 5 V Supplied Pins ooococcccccoo II I 21 Table 8 VDDUART Supplied Pins 22 eR RII Rn 21 Table 9 VDD1 Supplied PINS 1 522 zEk REIR RE ERR eed ag debe Wed eee eae ed 22 Table10 ONOFFPIN 0 0 a gg aa BE hh has 22 Table 11 Pull up and Pull down Currents ass sana s an aa kan gag eee ENES ene eens 23 Table 12 Max Load at the Different Supply Vollages_ a a eee 24 Table 13 BDR Transmitter Part iei KA DAG ANAN ada ND ANG eee eae LANANG E BA aa ag ha 24 Table 14 BDR Receiver Part iia ia a A a aaa TAN Ta donc oe RA BASA OR RT CUR DR 25 Table 15 EDR Transmitter Parti saa anaa ata wa wa eme alc eee ana a oque BB d ARE ROGA Na aaa d RE 26 Table 16 EDR Receiver Pan cce ERR a aan ah Eu Ru E BA CR an D TE AS Ue apaa ee UR a ae a 26 Table 17 Antennas s tananan O eee ar pai sat eased Cer ROI an ak Ro DR G6 OR de A e a c de DE 31 User s Manual 7 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic eres General Device Overview 1 General Device Overview 1 1 Features General Complete Bluetooth 2 0 EDR solution Configurable for BT 1 2 Ultra low power design in 0 13 um CMOS Temperature range from 40 C to 85 C Integrates ARM7TDMI RAM and patchable ROM e On
10. If it is intended to send a defect PAN1321 module back to the supplier for failure analysis please note that during the removal of this component no further defects must be introduced to the device because this may hinder the failure analysis at the supplier This includes ESD precautions not to apply high mechanical force for component removal and to prevent excess moisture content in the package during salvage risk of pop corning failures Therefore if the maximum storage time out of the dry pack see label on packing material is exceeded after board assembly the PCB has to be dried 24h at 125 C before soldering off the defect component because otherwise too much moisture may have been accumulated User s Manual 40 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic mi Assembly Guidelines 9 9 Voids in the Solder Joints 9 9 1 Expected Void Content and Reliability The content of voids is larger on LGA modules than for modules with BGA or leads At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air The void content of the PAN1321 module conforms to IPC A 610D 2596 or less voiding area area Figure 17 shows an example of void content at a module assembled at production site Normally you can see the whole spectra of void content variation within the same lot and occasion of assembly Voids IPC A 610D vsd Figu
11. SPP AT application running on the eBMU chip under QD ID B014433 Manufacturers of Bluetooth devices incorporating PAN1321can reference the same QD ID number Bluetooth QD ID B014433 PAN1321 SPP BT2 0 8 8 Industry Canada Certification PAN1321 complies with the regulatory requirements of Industry Canada IC license IC 216Q EBMU Manufacturers of mobile fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and or RF exposure limits Users can obtain Canadian information on RF exposure and compliance from www ic gc ca This device has been designed to operate with the antennas listed in Table 17 above having a maximum gain of 4 0 dBi Antennas not included in this list or having a gain greater than 4 0 dBi are strictly prohibited for use with this device The required antenna impedance is 50 ohms The antenna used for this transmitter must not be co located or operating in conjunction with any other antenna or transmitter 8 9 Label Design of the Host Product It is recommended to include the following information on the host product label Contains transmitter Module FCC ID T7 VEBMU IC 216QEBMU 8 10 Regulatory Test House The test house used by Panasonic in the Bluetooth and Regulatory approvals for the module PAN1321 Eurofins Product Service GmbH Storkower Str 38c D 15526 Reichenwalde b Berlin GERMANY Tel 49 33631 888 0 Fax 49 33631 888 650
12. anim omues Apa e een eM SN 200 C PRIOR IO E RR RI RR RE RE aa EAT wee er ko PA A A Su 6 C sec max 25 C LE 8 minutes max Time s LeadFree Solder Profile vsd Figure 15 Eutectic Leadfree Solder Profile User s Manual 38 Hardware Description Revision 3 2 2011 10 17 PAN1321 SPP Panasonic ae a Assembly Guidelines At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality whereas overheating the board with its components has to be avoided Using infrared ovens without convection special care may be necessary to assure a sufficiently homogeneous temperature profile for all solder joints on the PCB especially on large complex boards with different thermal masses of the components The most recommended types are therefore forced convection or vapour phase reflow Nitrogen atmosphere can generally improve solder joint quality but is normally not necessary The reflow profiles and other reflow parameters are dependent on the used solder paste The paste manufacturer provides a reflow profile recommendation for this product Additionally it is important not to overheat the PAN1321 module by a too large reflow peak temperature PAN1321 contain several plastic packages and is there by sensitive of the moisture content level at the time of board assembly Overheating in combination with excessive moisture content
13. could result in package delaminations or cracks popcorn effect The heating rate should not exceed 3 C s and max sloping rate should not exceed 4 C s PAN1321 shall be handled according to MSL3 which means a floor life of 168h in 30 C 60 r h The PAN1321 module can be soldered according to max J STD 020C curve assuming that all other conditions are followed stated in Product Specification Qualification Report and in Application Note Restriction is that PAN1321 can be soldered two times since one time is already consumed when soldering devices on Module 9 6 Rework 9 6 1 Removal Procedure 1 Heat the module with an appropriate heating nozzle according to the instruction of the equipment or on a hot plate about 225 C dependent on the board Hot plate can only be used if the board is single side assembled The temperature of the module shall be 200 220 C 2 Use grippers or a pair of tweezers to remove the module The module has to be gripped on two opposite edges of the module not on the shield 3 Remove excess solder by using solder sucker suction soldering irons or solder wick 9 6 2 Replacement Procedure Replacement can be done in two ways dependent of how the solder is applied Solder can be applied either by dispensing on the mother board or by printing the solder paste directly on the module 9 6 2 1 Alternative 1 Dispensing Solder A dispenser with controlled volume must be used to assure the same volume on every pa
14. module voltage regulators External supply 2 9 4 1 V e On module EEPROM with configuration data e Reference clock included Low power clock from internal oscillator or external low power clock e g 32 768 kHz Dynamic low power mode switching Interfaces lt AT command interface over UART configurable from 9600 baud up to 3 25 MBaud General purpose l Os with interrupt capabilities JTAG for boundary scan and debug RF Transmit power typ 2 5 dBm default settings Receiver sensitivity typ 86 dBm Integrated antenna switch balun and antenna filter Integrated LNA with excellent blocking and intermodulation performance lt No external components except antenna Digital demodulation for optimum sensitivity and co adjacent channel performance Bluetooth Bluetooth V2 0 EDR compliant SPP Device A and B support 1 ACL link with stream or command mode SPP Device A and B Visible while connected e SPP Device A and B Visible connectable when not connected SPP Device A and B Device Discovery capable after receiving OK on data transfer Sniff mode is supported with above capabilities 5 trusted devices stored in EEPROM Testing Enable DUT Crystal calibration H4 with UART HW flow control RTS CTS e Security modes Modes 1 and Mode 3 Master Slave role switch User s Manual 8 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic mt General Device Overview 1
15. www eurofins com User s Manual 34 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic ae aa Assembly Guidelines 9 Assembly Guidelines The target of this document is to provide guidelines for customers to successfully introduce the PAN1321 SPP module in production This includes general description PCB design solder printing process assembly soldering process rework and inspection 9 1 General Description of the Module PAN1321 SPP is a Land Grid Array LGA 6x9 module made for surface mounting The pad diameter is 0 6 mm and the pitch 1 2 mm All solder joints on the module will reflow during soldering on the mother board All components and shield will stay in place due to wetting force Wave soldering is not possible Surface treatment on the module pads is Nickel 5 8 um Gold 0 04 0 10 um Figure 11 shows the pad layout on the module seen from the component side UARTRXD d SLEEPX 8 RESET VSUPPLY VSUPPLY VSUPPLY GND Ai A2 A3 A4 Ab A6 A7 A8 A9 Figure 11 Pad Layout on the Module top view 9 2 Printed Circuit Board Design The land pattern on the PCB shall be according to the land pattern on the module which means that the diameter of the LGA pads on the PCB shall be 0 6 mm It is recommended that each pad on the PCB shall be surrounded by a solder mask clearance of about 75 um to avoid overlapping solder mask and pad 9 3 Solder Paste Printing T
16. 001111 sequence Minimum modulation deviation 115 145 kHz for 01010101 sequence Ratio Deviation 01010101 0 8 1 Deviation 00001111 Initial carrier frequency 75 kHz 7 tolerance foffset User s Manual 24 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF Table 13 BDR Transmitter Part cont d Electrical Characteristics Parameter Symbol Values Min Typ Max Unit Note Test Condition Carrier frequency drift one slot fdrift 10 25 kHz Carrier frequency drift three slots fdrift 10 40 kHz Carrier frequency drift five slots fdrift 10 40 kHz Carrier frequency driftrate one slot fdriftrate 20 kHz 50 ms Carrier frequency driftrate three slots fdriftrate 20 kHz 50 ms Carrier frequency driftrate five slots fdriftrate 20 kHz 50 ms Table 14 BDR Receiver Part Parameter Symbol Values Min Typ Unit Note Test Condition Sensitivity 86 dBm Ideal wanted signal C I performance 4th adjacent channel 51 dB C I performance 3rd adjacent channel 1st adj of image dB C I performance 2nd adjacent channel image dB C I performance 1st adjacent channel dB C I performance co channel dB C I performance 1st adjacent channe
17. ART The UART Universal Asynchronous Receiver and Transmitter interface is compatible with standard UART H4 4 wire The lines UARTTXD and UARTRXD are used for commands events and data The lines UARTRTS and UARTCTS are used for hardware flow control A separate supply voltage VDDUART makes it easy to connect the UART interface to any system 3 1 1 1 Baud Rates The supported baud rates are listed in Table 3 together with the small deviation error that results from the internal clock generation The default baud rate is 115200 Baud Table 3 UART Baud Rates Wanted Baud Rate Real Baud Rate Deviation Error 96 9600 9615 0 16 19200 19230 0 16 38400 38461 0 16 57600 57522 0 14 115200 115044 0 14 230400 230088 0 14 460800 464285 0 76 921600 928571 0 76 1843200 1857142 0 76 3250000 3250000 0 User s Manual Hardware Description 15 Revision 3 2 2011 10 17 PAN1321 SPP Panasonic e General Device Capabilities 4 General Device Capabilities This chapter describes features available in the PAN1321 ENW89811K4CF 22 xx core Actual feature set and how to access the features can be found in the AT Command document 1 Release specific performance characteristics like data speed is related in the SW Release Notes 2 4 1 HCI The PAN1321 module can be programmed over UART with a specific application for RF test purposes like TX continuous or TX burst mode This test applic
18. Identification Number Packet Loss Concealment Phase Locked Loop Power Management Unit Power On Reset Packet Traffic Arbitration Packet Type Table Quality Of Service Random Access Memory Radio Frequency Read Only Memory Received Signal Strength Indication Request To Send UART flow control signal Receive Receive Data UART signal Synchronous Connection Oriented logical transport Special Interest Group Bluetooth SIG Software Synthesizer Reference Input To Be Determined Test Clock JTAG signal 45 Hardware Description Terminology Revision 3 2 2011 10 17 Panasonic PAN1321 SPP ENW89811K4CF TDI TDO TL TMS TX TXD UART ULPM VCO WLAN User s Manual Test Data In JTAG signal Test Data Out JTAG signal Transport Layer Test Mode Select JTAG signal Transmit Transmit Data UART signal Universal Asynchronous Receiver 8 Transmitter Ultra Low Power Mode Voltage Controlled Oscillator Wireless LAN Local Area Network 46 Hardware Description Terminology Revision 3 2 2011 10 17 PAN1321 SPP Panasonic e References 11 References 1 SPP AT Image Version 1 6 Release Note Rev1 0 2010 06 22 SPP AT Image Version 1 8 Release Note Rev1 0 2011 09 05 SPP AT Image Version 2 1 Release Note Rev1 0 2011 09 05 Always the latest revision as a zip file will be available under the link below SPP AT Image Release Notes 2 SPP AT Application User s
19. Manual Software Description Always the latest revision as a pdf file will be available under the link below SPP AT User s Manual Software Description 3 PAN1321 Application Note Design Guide Always the latest revision as a pdf file will be available under the link below PAN1321 Application Note Design Guide User s Manual 47 Revision 3 2 2011 10 17 Hardware Description
20. October 2011 ENW89811K4CF Bluetooth QD ID B014433 End Product Listing FCC ID T7VEBMU IC ID 216QEBMU PAN1321 SPP Infineon s BlueMoonUniversal Platform Wireless Modules User s Manual Hardware Description Revision 3 2 agb Edition 2011 10 17 Published by Panasonic Electronic Devices Europe GmbH Zeppelinstrasse 19 D 21337 L neburg Germany 2011 Panasonic Electronic Devices Europe GmbH All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact your nearest Panasonic Office in Germany or one of our Distributor or write an e mail to wireless eu panasonic com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Panasonic Office Panasonic Electronic Devices may only be used in life support devices or systems with the express written approval of Panasonic Devices
21. PSK 99 DEVM 20 96 Differential phase encoding 99 100 Yo 1st adjacent channel power 40 26 dBc 2nd adjacent channel power 20 dBm Carrier power measured at basic rate 3rd adjacent channel power 40 dBm _ Carrier power measured at basic rate Table 16 EDR Receiver Part Parameter Symbol Values Unit Note Test Condition Min Typ Max DQPSK Sensitivity 88 83 dBm Ideal wanted signal 8DPSK Sensitivityl B 83 77 dBm Ideal wanted signal DQPSK BER Floor Sensitivity 84 60 dBm 8DPSK BER Floor Sensitivity 79 60 dBm DQPSK C I performance 53 40 dB 4th adjacent channel DQPSK C I performance 47 20 dB 3rd adjacent channel 1st adj of image DQPSK C I performance 31 7 dB 2nd adjacent channel image User s Manual 26 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF Table 16 EDR Receiver Part cont d Electrical Characteristics Parameter Symbol Values Unit Note Test Condition Min Typ Max DQPSK C I performance 7 0 dB 1st adjacent channel DQPSK C I performance 11 13 dB co channel DQPSK C I performance 9 0 dB 1st adjacent channel DQPSK C I performance 44 1 80 dB 2nd adjacent channel DQPSK C I performance 50 1 40 dB 3rd adjacent channel 8DPSK C I performance 48 33 dB 4th adj
22. VDDUART V Input high voltage 0 7 VDDUART VDDUART 0 3 V PO 5 UARTRXD Input high voltage 0 7 VDDUART 3 6 V Other pins User s Manual Hardware Description 21 Revision 3 2 2011 10 17 Panasonic PAN1321 SPP ENW89811K4CF Electrical Characteristics Table 8 VDDUART Supplied Pins cont d Parameter Symbol Values Unit Note Test Condition Min Typ Max Output low voltage 0 25 V IOL 5 MA VDDUART 2 5 V Output low voltage 0 15 V IOL 2 mA VDDUART 2 5 V Output high voltage VDDUART V IOH 5 mA 0 25 VDDUART 2 5 V Output high voltage VDDUART V IOH 2 mA 0 15 VDDUART 2 5 V Continuous Load 5 mA Pin Capacitance 10 pF Magnitude Pin Leakage 0 01 1 uA Input and output drivers disabled 1 The totaled continuous load for all VDDUART supplied pins shall not exceed 35 mA at the same time Table 9 VDD1 Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 3 0 2 VDD1 V Input high voltage 0 7 VDD1 3 6 V Output low voltage 0 25 V IOL 5 mA VDD1 2 5 V Output low voltage 0 15 V IOL 2 mA VDD1 2 5 V Output high voltage VDD1 V IOH 5 mA 0 25 VDD1 22 5 V Output high voltage VDD1 V IOH 2 mA 0 15 VDD1 22 5 V Continuous Load 5 mA Pin Capacitance 10 pF E Magnitude Pin Leakage 0 01 1 uA Input and outp
23. acent channel 8DPSK C I performance 44 13 dB 3rd adjacent channel 1st adj of image 8DPSK C I performance m 25 O dB i 2nd adjacent channel image 8DPSK C I performance 5 5 dB 1st adjacent channel 8DPSK C I performance 17 21 dB co channel 8DPSK C I performance 5 5 dB 1st adjacent channel 8DPSK C I performance 36 25 dB 2nd adjacent channel 8DPSK C I performance 46 33 dB 3rd adjacent channel Maximum input level 20 dBm User s Manual 27 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF 7 Package Information 7 1 Package Marking Package Information PAN1321 HW SW Ordering Code ENW89811K4CF Date Code YYWWDLL FCC ID FCC ID 7VEBMU Case Version HW Hardware Version SW Software Version Machine readable 2D bar code Panasonic usage only could be changed without any notice Figure 5 Package Marking 7 2 Production Package 2 8 Production Package vsd Figure 6 Production Package All dimensions are in mm Tolerances on all outer dimensions height width and length are 0 2 mm User s Manual 28 Hardware Description Revision 3 2 2011 10 17 PAN1321 SPP Panasonic aa Package Information 7 2 1 Pin Mark
24. allow PAN1321 SPP to enter low power mode and P0 0 is used by PAN1321 SPP to wake up the host when attention is required Additionally the host could hardware reset PAN1321 SPP using the RESET pin Power is supplied to a single VSUPPLY input from which internal regulators can generate all required voltages The UART and the GPIO s interfaces have separate supply voltages so that they can comply with host signaling 1 6 FW version PAN1321 SPP is available in different firmware FW versions Please check corresponding release documents for latest information in chapter 11 item 1 The identifier about the software version will be visible on the module please refer to Figure 5 here it is the identifier SW There are actual 4 different firmware releases available in Table 2 Table 2 Firmware Releases as of 2011 10 17 Sw FW Comment marking on firmware the module version 07 1 6 first standard release free of charge 08 1 8 second standard release free of charge should be used for new projects 20 2 0 first iPhone release special license fee is needed 21 2 1 second iPhone release special license fee is needed should be used for new projects User s Manual 13 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP ENW89811K4CF Panasonic Basic Operating Information 2 Basic Operating Information 2 1 Power Supply PAN1321 SPP is supplied from a single supply voltage VSUPPLY This su
25. ation is controlled over the UART through Infineon specific HCI commands The commands supported by this test application are described in the document T8753 2 Infineon_Specific_HCI_Commands 7600 paf 4 2 Firmware ROM Patching 4 2 1 Patch Support PAN1321 SPP contains dedicated hardware that makes it possible to apply patches to the code and data in the firmware ROM The hardware is capable of replacing up to 32 blocks of 16 bytes each with new content This area can be filled with any combination of code and data The firmware patch is stored in EEPROM and automatically loaded after startup This provides a flexible bugfix solution for the ROM part of the firmware User s Manual 16 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic e Bluetooth Capabilities 5 Bluetooth Capabilities 5 1 Supported Features Bluetooth V2 0 EDR compliant Enhanced Data Rate up to 3 Mbit s Adaptive Frequency Hopping AFH All packet types Authentication Pairing and Encryption e SPP Device A and B support 1 ACL link with stream or command mode SPP Device A and B Visible while connected SPP Device A and B Visible connectable when not connected SPP Device A and B Device Discovery capable after receiving OK on data transfer Sniff mode is supported with above capabilities 5 trusted devices stored in EEPROM Enable DUT Crystal calibration H4 with UART HW flow control RTS CTS e Securi
26. ctrical Characteristics 6 1 Absolute Maximum Ratings Table 4 Absolute Maximum Ratings Parameter Symbol Values Unit Note Test Condition Min Typ Max Storage temperature 40 125 C VSUPPLY supply voltage 0 3 6 0 V VDDUART supply voltage 0 9 4 0 V x VDD1 supply voltage 0 9 4 0 V VREG 0 3 4 0 V VSUPPLY 54V VREG 0 3 VSUPPLY V VSUPPLY lt 4 V ONOFF 0 3 VSUPPLY 0 3 V Input voltage range 0 9 4 0 V Output voltage range 0 9 4 0 V 9 ESD 1 0 kV According to MIL STD883D method 3015 7 Note Stresses above those listed here are likely to cause permanent damage to the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability Maximum ratings are absolute ratings exceeding only one of these values may cause irreversible damage to the integrated circuit Maximum ratings are not operating conditions 6 2 Operating Conditions Table 5 Operating Conditions Parameter Symbol Values Unit Note Test Condition Min Typ Max Operating temperature 40 85 C Main supply voltage Vsupply 2 9 4 1 V VDDUART 135 3 6 V VDD1 135 3 6 V User s Manual 20 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF 6 3 6 3 1 DC Characteristics Pad Driver and Input Stages For more inf
27. d The volume on each pad shall be about 0 04 mm 1 Dispense 0 04 mm on each LGA pad 2 Pick the module by a nozzle and place in the right position on the board 3 Reflow the solder User s Manual 39 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic ae a Assembly Guidelines 9 6 2 2 Alternative 2 Printing Solder To print solder on the module a fixture must be used The purpose of the fixture is to get a flat surface and fix the stencil and module for printing An example of how this fixture can be designed is shown in Figure 16 Solder paste stencil EP Cavity of the module Toning pus Vacuum holes Fixture Bottom Solder Printing vsd Figure 16 Solder Printing Assemble the fixture to the bottom Place the module in the cavity with the LGA pads upwards Place the solder paste stencil on the fixture and make sure it fits to the tooling pins and the module Apply vacuum to fix the solder paste stencil Apply solder paste on the stencil and print by using a blade Turn everything bottom fixture and stencil upside down Separate carefully the bottom from the fixture Pick the module by a nozzle and place in the right position on the board Reflow the solder O 0 NGO OTSE IN gt 9 7 Inspection Automatic inspection of the solder paste printing before assembly is highly recommended to ensure high yield and good long term reliability 9 8 Component Salvage
28. des information to the host every time a new CQDDR proposal is sent to a remote device User s Manual 18 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic ENG KACE Bluetooth Capabilities 5 2 2 RSSI and Output Power Control 5 2 2 1 Received Signal Strength Indication RSSI PAN1321 SPP supports received signal strength measurements and uses LMP signaling to keep the output power of a remote device within the golden receive power range The range is set with the BD_DATA parameters RSSI_Min and RSSI_Max 5 2 2 2 Output Power Control PAN1321 SPP supports power control according to the Bluetooth 2 0 EDR specification The output power can be controlled in up to 4 configurable steps PAN1321 SPP can work as a class 2 or 3 device depending on the settings Finetuning can be used on the power steps A default sub state power step can be set The power step configuration is set through BD DATA parameters The Inquiry output power can be programmed with the Write Inquiry Transmit Power Level command introduced in the 2 0 Bluetooth Core specification 5 2 2 3 Ultra Low Transmit Power For high security devices the output power can be reduced to a value that reduces the communication range to a few inches This mode is enabled with the HCl command Infineon TX Power Config User s Manual 19 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic a a Electrical Characteristics 6 Ele
29. e information about AFH operation The commands Infineon Enable AFH Info Sending and Infineon Disable AFH Info Sending turn on and off the Infineon AFH Info events that provide detailed information about channel classification channel maps interferers etc If enabled by the Infineon Enable Infineon Events command the Infineon AFH Extraordinary RSSI event informs the host whenever extraordinary RSSI measurements in unused slots have been started This is done when the number of known good channels has decreased below a critical limit and periodically after a defined time The Infineon Set AFH Measurement Period command can be used to configure the duration of the AFH measurement period 5 2 1 4 Channel Quality Driven Data Rate Change CQDDR PAN1321 SPP supports channel quality driven data rate change according to the Bluetooth 2 0 EDR specification A device that receives an LMP preferred rate message is not required to follow all recommendations PAN1321 SPP normally at least follows the recommendation whether to use forward error correction FEC or not If possible recommendations about packet size and modulation scheme will be taken into account When PAN1321 SPP sends an LMP preferred rate to another device the proposal always includes preferences for all parameters The HCI commands Infineon Enable CQDDR Info Sending and Infineon Disable CQDDR Info Sending turn on and off sending of the Infineon CQDDR Info event This event provi
30. ended Synchronous Connection Oriented logical transport Extended Voice packet type Forward Error Correction Frequency Hop Synchronization packet First In First Out buffer Frequency Modulation Firmware Gaussian Frequency Shift Keying modulation General Purpose Input Output Global System for Mobile communication Host Controller Interface Infineon Specific HCI command set Header Error Check High quality Voice packet type Hardware Inter IC Control bus Inter IC Sound bus Inquiry Access Code IDentifier Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial Scientific amp Medical frequency band Joint Test Action Group Local Area Network Lower Address Part Link Manager Link Manager Protocol Low Noise Amplifier Local Oscillator Low Power Mode s Low Power Oscillator Least Significant Bit Byte Logical Transport Address 44 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF MSB MSRS NG NOP NVM OCF OGF P PA PCB PCM PDU PER PIN PLC PLL PMU POR PTA PTT Q QoS R RAM RF ROM RSSI RTS RX RXD S SCO SIG SW SYRI T TBD TCK User s Manual Most Significant Bit Byte Master Slave Role Switch No Connection No OPeration Non Volatile Memory Opcode Command Field Opcode Group Field Power Amplifier Printed Circuit Board Pulse Coded Modulation Protocol Data Unit Packet Error Rate Personal
31. etooth 2 0 EDR Module Brand name PAN1321 PAN1311 Model name ENW89811K4CF ENW89810K5CF to which this declaration relates is in compliance with all the applicable essential requirements and other provisions of the European Council Directive 1999 5 EC Radio and Telecommunications Terminal Equipment Directive R amp TTE The conformity assessment procedure used for this declaration is Annex IV of this Directive Product compliance has been demonstrated on the basis of CENSO AOL V 1 8 1 F ticle 3 1 b Elect tic C tibilit EN 301 489 17 V2 1 1 or article 3 1 b Electromagnetic Compatibility e ee E bag NA For article 3 2 Effective use of spectrum allocated The technical contruction file is kept available at Panasonic Electronic Devices Europe GmbH Zeppelinstrasse 19 21337 Lueneburg Germany Issued on 31st of March 2010 Signed by the manufacturer Company name Panasonic Electronic Devices Europe GmbH Lo SE Signature Er Printed name Heino Kaehler Title Manager Wireless Modules Figure 10 Declaration of Conformity User s Manual 33 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic ae Important Application Information 8 7 Bluetooth Qualified Design ID Panasonic has submitted End Product Listing EPL for PAN1321 based on Infineon eBMU plattform in the Qualified Product List of the Bluetooth SIG These EPL are referring the Bluetooth qualfication of the
32. he following measures Reorient or relocate the antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio or television technician for help 8 3 FCC Wireless Notice This product emits radio frequency energy but the radiated output power of this device is far below the FCC radio frequency exposure limits Nevertheless the device should be used in such a manner that the potential for human contact with the antenna during normal operation is minimized To meet the FCC s RF exposure rules and regulations The system antenna used for this transmitter must not be co located or operating in conjunction with any other antenna or transmitter User s Manual 31 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic re Important Application Information The system antenna used for this module must not exceed 4 dBi Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance Manufacturers of mobile fixed or portable devices incorporating this module are advised to clarify any regulatory questions and to have their complete product tested and approved for FCC compliance 8 4 FCC Interference Statement This device complies with Part 15 of the FCC Rules Operation is
33. he solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree lead composition A no clean solder paste is preferred since cleaning of the solder joints is difficult because of the small gap between the module and the PCB Preferred thickness of the solder paste stencil is 100 127 um 4 5 mils The apertures on the solder paste stencil shall be of the same size as the pads 0 6 mm User s Manual 35 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP ENW89811K4CF Panasonic Assembly Guidelines 9 4 Assembly 9 4 1 Component Placement In order to assure a high yield good placement on the PCB is necessary As a rule of thumb the tolerable misplacement is 150 um This means that the PAN1321 module can be assembled with a variety of placement systems It is recommended to use a vision system capable of package pad recognition and alignment that evaluates the pad locations on the package in contrast to outline centring This eliminates the pad to package edge tolerance The recommendation is to pick and place the module with a nozzle in the centre of the shield The nozzle diameter shall not be bigger than 4 mm 9 4 2 Pin Mark Pin 1 A1 is marked on bottom footprint and on the top of the shield on the module according to Figure 12 Diameter of pin 1 mark on the shield is 0 15 mm 1 00 mm Figure 2a Top View Figure 2b Botto
34. l dB C I performance 2nd adjacent channel dB C I performance 3rd adjacent channel dB Blocking performance 30 MHz 2 GHz dBm Some spurious responses but according to BT specification Blocking performance 2 GHz 2 4 GHz dBm Blocking performance 2 5 GHz 3 GHz dBm Blocking performance 3 GHz 12 75 GHz dBm Some spurious responses but according to BT specification User s Manual Hardware Description 25 Revision 3 2 2011 10 17 Panasonic PAN1321 SPP ENW89811K4CF Table 14 BDR Receiver Part cont d Electrical Characteristics Parameter Symbol Values Unit Note Test Condition Min Typ Max Intermodulation performance 39 34 dBm Valid for all intermodulation tests Maximum input level 20 dBm Table 15 EDR Transmitter Part Parameter Symbol Values Unit Note Test Condition Min Typ Max Output power high gain 2 5 2 dBm Relative transmit power 4 0 6 1 dB PxPSK PGFSK Carrier frequency stability oil 75 kHz Carrier frequency stability wi 0 75 kHz Carrier frequency stability 0 2 10 kHz DPSK RMS DEVM 10 20 96 8DPSK RMS DEVM 10 13 96 DPSK Peak DEVM 20 35 96 8DPSK Peak DEVM 20 25 96 DPSK 9996 DEVM 30 96 8D
35. m View Figure 12 Pin Marking User s Manual 36 Revision 3 2 2011 10 17 Hardware Description ba PAN1321 SPP Panasonic aa Assembly Guidelines 9 4 3 Package PAN1321 is packed in tape on reel according to Figure 13 Measured from centreline of sprocket hole ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED SECTION X X Estimated max 0 05 030 SECTION Y Y Figure 13 Tape on Reel User s Manual 37 Revision 3 2 2011 10 17 Hardware Description Panasoni c PAN1321 SPP ENW89811K4CF Assembly Guidelines 9 5 Soldering Profile Generally all standard reflow soldering processes vapour phase convection infrared and typical temperature profiles used for surface mount devices are suitable for the PAN1321 module Wave soldering is not possible Figure 14 and Figure 15 shows example of a suitable solder reflow profile One for leaded and one for leadfree solder Recommended temp profile lt 10 1s for reflow soldering 30 20 10s Temp I Cl 235 C max 220 5 C 200 C 150 10 C Time s Lead Solder Profile vsd Figure 14 Eutectic Lead Solder Profile Recommended temp profile for reflow soldering J STD 020C Temp C VY Ug a A A CUM A AA Serres sete A veg AA ii Coe pe en A
36. older and create voids Too long reflow time gives larger voids Too short reflow time gives a fraction of voids User s Manual 42 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic e Terminology 10 Terminology A ACK Acknowledgement ARQ Automatic Repeat reQuest B b bit bits e g kb s B Byte Bytes e g kB s BALUN BALanced UNbalanced BD ADDR Bluetooth Device Address BER Bit Error Rate BMU BlueMoon Universal BOM Bill Of Material BT Bluetooth BW Bandwidth C CMOS Complementary Metal Oxide Semiconductor COD Class Of Device CODEC COder DECoder CPU Central Processing Unit CQDDR Channel Quality Driven Data Rate CRC Cyclic Redundancy Check CTS Clear To Send UART flow control signal CVSD Continuous Variable Slope Delta modulation CDCT Clock Drift Compensation Task CQDDR Channel Quality Driven Data Rate D DC Direct Current DDC Device Data Control DM Data Medium Rate packet type DMA Direct Memory Access DH Data High Rate packet type DPSK Differential Phase Shift Keying modulation DQPSK Differential Quaternary Phase Shift Keying modulation DSP Digital Signal Processor DUT Device Under Test E EDR Enhanced Data Rate EEPROM Electrically Erasable Programmable Read Only Memory User s Manual 43 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic Tk KACE eSCO EV FEC FHS FIFO FM FW GFSK GPIO GSM HCl HCI HEC LT_ADDR M User s Manual Terminology Ext
37. or PAN1321 SPP in Top View footprint aaa 9 Figure 3 Example of a Bluetooth System using eUniStone isle eee 12 Figure 4 UART Interface ees ie nd es nente Rem huh eh ede QUEUE a aan Rada gla E eae 15 Figure 5 Package Matking ese RE RR LARS Ye dade RUE ERU Ua EE E Lae MANA 28 Figure 6 Production Package eile pene oe eques Eee e pud FUE perd E i 28 Figure 7 Top View and Bottom View sesak eaaa a ae a a KKN a eee eae 29 Figure 8 Reference Design Schematias aa aaa e 30 Figure 9 Equipment Labelle cca owt atan e da e conn WI Ds e BR e b EN mused A 32 Figure 10 Declaration of Conformiiy a hr 33 Figure 11 Pad Layout on the Module top view auaa aaaea 35 Figure 12 Pin Marking ss cet Rte Ee Eos eb eoe RR UC be RR deb Pee do 36 Figure 13 Tape On Reel i e Peewee heaved e eR penis Vel wedded WET Red els 37 Figure 14 Eutectic Lead Solder Profile liliis 38 Figure 15 Eutectic Leadfree Solder Profile liliis 38 Figure 16 Solder Printing ss as ajaa Aan pa a ae EA WA e a A a KADA NAK rn 40 Figure 17 X ray Picture Showing Voids Conforming to IPC A 610D ae 41 User s Manual 6 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic Ba List of Tables List of Tables Table 1 PIMDESCUPUON Cm 10 Table 2 Firmware Releases as of 2011 10 17 20 eee 13 Table 3 UART Baud Rates soii a e Den E RUD RR CR Ya adja ee OE NOR Ae ARA RA ad sah 15 Table
38. ormation see Chapter 1 4 Electrical Characteristics Table 6 Internal1 1 5 V Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 3 0 27 V Input high voltage 1 15 3 6 V E Output low voltage 0 25 V IOL 1 mA Output high voltage 1 1 V IOH 1 MA Continuous Load 1 mA l Pin Capacitance 10 pF Magnitude Pin Leakage 0 01 1 uA Input and output drivers disabled 1 The totaled continuous load for all Internal1 supplied pins shall not exceed 2mA at the same time Table 7 Internal2 2 5 V Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 3 0 45 V Input high voltage 1 98 2 8 V P0 10 Input high voltage 1 93 3 6 V Other pins Output low voltage 0 25 V IOL 5 MA Output low voltage 0 15 V IOL 2 mA Output high voltage 2 0 V IOH 5 mA Output high voltage 2 1 V IOH 2 mA Continuous Load 5 mA l Pin Capacitance 10 pF Magnitude Pin Leakage 0 01 1 PA Input and output drivers disabled 1 The totaled continuous load for all Internal2 supplied pins shall not exceed 35 mA at the same time Table 8 VDDUART Supplied Pins Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 3 0 2
39. pply voltage must always be present The PAN1321 SPP chip is supplied from an internally generated 2 5 V supply voltage This voltage can be accessed from the VREG pin This voltage may not be used for supplying other components in the host system but can be used for referencing the host interfaces The GPIO s and the UART interface are supplied with dedicated independent reference levels via the VDD1 and VDDUART pins All other digital I O pins are supplied internally by either 2 5 V Internal2 or 1 5 V Internal Section 1 4 provides a mapping between pins and supply voltages The I O power domains VDD1 and VDDUART are completely separated from the other power domains and can stay present also in low power modes 2 2 Clocking PAN1321 SPP contains a crystal from which the internal 26 MHz system clock is generated Also the low power mode clock of 32 kHz is generated internally which means that no external clock is needed User s Manual 14 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF 3 Interfaces 3 1 UART Interface Interfaces The UART interface is the main communication interface between the host and PAN1321 SPP The interface consists of four UART signals and two wake up signals as shown in Figure 4 UARTTXD UARTRXD UARTRTS UARTCTS WAKEUP BT WAKEUP HOST UARTTXD PAN1321 UARTRXD UARTRTS UARTCTS P0 14 input P0 0 output Figure4 UART Interface 3 1 1 U
40. ption 23 Revision 3 2 2011 10 17 PAN1321 SPP Panasonic a a Electrical Characteristics 6 3 4 System Power Consumption Table 12 Max Load at the Different Supply Voltages Parameter Symbol Values Unit Note Test Condition Min Typ Max Vsupply 100 mA Peak current Note l O currents are not included since they depend mainly on external loads 6 4 AC Characteristics 6 5 RF Part 6 5 1 Characteristics RF Part The characteristics involve the spread of values to be within the specific temperature range Typical characteristics are the median of the production All values refers to Infineon reference design All values will be updated after verification Characterisation 6 5 1 1 Bluetooth Related Specifications Table 13 BDR Transmitter Part Parameter Symbol Values Unit Note Test Condition Min Typ Max Output power high gain 0 5 2 5 4 5 dBm Default settings Output power highest gain 4 5 dBm Maximum settings Power control step size 4 6 8 dB Frequency range fL 2400 2401 3 MHz Frequency range fH 2480 7 2483 5 MHz 20 dB bandwidth 0 930 1 MHz 2nd adjacent channel power 40 20 dBm 3rd adjacent channel power 60 40 dBm gt 3rd adjacent channel power 64 40 dBm Max 2 of 3 exceptions 52 MHz offset might be used Average modulation deviation 140 156 175 kHz for 00
41. re 17 X ray Picture Showing Voids Conforming to IPC A 610D 9 9 2 Parameters with an Impact on Voiding If the void content has to be reduced following parameters have an impact Solderability on module and PCB Bad solderability is often connected to oxidation and has therefore a major impact on voiding Flux will get entrapped on oxidized surfaces In general Ni Au pads show fewer voids than HASL and OSP Solder paste Higher activity of the flux will remove oxide rapidly and less flux will get entrapped Voiding increases with increasing solder paste exposure time since long exposure time will result in more oxidation and moisture pickup Pad size A large soldering pad means that the outgassing flux has a longer way to the surface of the solder and will thereby create more voids Solder paste Smaller powder size and higher metal load means more metal surface to deoxidize and thereby more entrapped flux and voiding Higher metal load does also mean higher viscosity and more difficult for outgassed flux to remove from the solder User s Manual 41 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic ae Assembly Guidelines Stencil thickness A thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the s
42. ription Panasonic PAN1321 SPP ENW89811K4CF Table of Contents 1 1 1 2 1 3 1 4 1 5 1 6 2 1 2 2 3 1 3 1 1 3 1 1 1 4 1 4 2 4 2 1 5 1 5 2 5 2 1 5 2 1 1 5 2 1 2 5 2 1 3 5 2 1 4 5 2 2 5 2 2 1 5 2 2 2 5 2 2 3 6 6 1 6 2 6 3 6 3 1 6 3 2 6 3 3 6 3 4 6 4 6 5 6 5 1 6 5 1 1 Table of Contents oo o List of Figures ooo List of Tables pe General Device Overview Gat les cid oi IG A Kg ina Block Diagram asar aaa gg ag Ba a BAG eee Pin Configuration LGA eae Pin Description aaa KK KAKA KR RAY System Integration_ a EW version o erasa KANA ee eet eee AREE Basic Operating Information Power Supply aaa aa aaa CIOCKING uet sees met t as Fl Ei iue tne Dor teg one nod IP VERRE SA ga Firmware ROM Patching eee Patch Support saksa aa aa aa rasaae ee eee Bluetooth Capabilities Supported Fealures_ cece eee eae PAN1321 SPP Specifics and Extensions During Connection 0000e ee eee Role Switch a Dynamic Polling Strategy Adaptive Frequency Hopping AFH Channel Quality Driven Data Rate Change CQDDR RSSI and Output Power Control Received Signal Strength Indication RSSI Output Power Control Ultra Low Transmit Power Electrical Characteristics Absolute Maximum Ratings Operating Conditions ooooooo DC Characteristics
43. subject to the following two conditions 1 This device may not cause harmful interference 2 This device must accept any interference received including interference that may cause undesired operation 8 5 FCC Identifier FCC ID T7VEBMU 8 6 European R amp TTE Declaration of Conformity Hereby Panasonic Electronic Devices Europe GmbH declares that the Bluetooth module ENW89811K4CF 22 xx is in compliance with the essential requirements and other relevant provisions of Directive 1999 5 EC As a result of the conformity assessment procedure described in Annex Ill of the Directive 1999 5 EC the end customer equipment should be labelled as follows CE Figure 9 Equipment Label PAN1321 in the specified reference design can be used in the following countries Austria Belgium Cyprus Czech Republic Denmark Estonia Finland France Germany Greece Hungary Ireland Italy Latvia Lithuania Luxembourg Malta Poland Portugal Slovakia Slovenia Spain Sweden The Netherlands the United Kingdom Switzerland and Norway User s Manual 32 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP ENW89811K4CF Panasonic Important Application Information Declaration of Conformity DoC 1999 5 EC We Panasonic Electronic Devices Europe GmbH High Frequency Products Business Group Zeppelinstrasse 19 21337 Lueneburg Germany declare under our sole responsibility that the product Type of equipment Blu
44. t tested and approved for compliance FCC or other when applicable When using other antennas a class permissive change is required for FCC approval The normal procedure is to first provide a technical test report showing that 4 dBi is not exceeded and to continue working with a regulatory test house to finalize the approval for a new antenna implementation There are no parts in ENW89811K4CF 22 xx that can be modified by the user except modifications of the device BD data and loading of SW patches Any changes or modifications made to this device that are not expressly approved by Infineon may void the user s authority to operate the equipment 8 2 FCC Class B Digital Devices Regulatory Notice This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by 1 or more of t
45. ty modes Modes 1 and Mode 3 e Master Slave role switch Quality of Service Channel Quality Driven Data Rate change Sniff Hold Role Switch lt RSSI and Power Control Power class 2 and 3 e Standard Bluetooth test mode Active Tester Mode and RF Test Modes User s Manual 17 Revision 3 2 2011 10 17 Hardware Description PAN1321 SPP Panasonic a Bluetooth Capabilities 5 2 PAN1321 SPP Specifics and Extensions 5 2 1 During Connection 5 2 1 1 Role Switch Only one role switch can be performed at a time If a role switch request is pending other role switch requests on the same or other links are rejected If a role switch fails PAN1321 SPP will automatically try again a maximum of three times Encryption if present is stopped in the old piconet before a role switch is performed and re enabled when the role switch has succeeded or failed 5 2 1 2 Dynamic Polling Strategy In addition to the regular polling scheme PAN1321 SPP dynamically assigns unused slots to links where data is exchanged This adapts very well to bursty traffic and improves throughput and latency on the links 5 2 1 3 Adaptive Frequency Hopping AFH PAN1321 SPP supports adaptive frequency hopping according to the Bluetooth 2 0 EDR specification AFH switch and channel classification are supported both as master and slave Channel classification from the host is also supported A number of HCl commands and events are available to provid
46. ut drivers disabled 1 The totaled continuous load for all VDD1 supplied pins shall not exceed 35 mA at the same time Table 10 ONOFF PIN Parameter Symbol Values Unit Note Test Condition Min Typ Max Input low voltage 0 7 V Input high voltage 1 7 x VSUPPLY V x Input current 0 01 1 pA ONOFF 0 V User s Manual 22 Revision 3 2 2011 10 17 Hardware Description Panasonic PAN1321 SPP ENW89811K4CF Electrical Characteristics 6 3 2 Pull ups and Pull downs Table11 Pull up and Pull down Currents Pin Pull Up Current Pull Down Current Unit Conditions Min Typ Max Min Typ Max P0 12 260 740 1300 N A N A N A uA Pull up current P0 13 measured with P0 0 22 1130 350 23 150 380 ua Pinvoltage 0V PO 1 P0 2 Pull down current P0 3 measured with P0 4 42 24 68 30 20 Ep Tg oa P0 5 supply voltage P0 6 P0 7 Min measured at 125 C P0 10 with supply 1 35 V P0 8 P0 9 Typ measured at 27 C P0 11 with supply 2 5V P0 14 P0 15 Max measured at P1 0 1 1 16 0 17 0 75 15 0 14 uA 40 C with P1 1 supply 3 63 V P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P1 8 6 3 3 Protection Circuits All pins have an inverse protection diode against VSS P0 10 has an inverse diode against Internal2 PO 5 UARTRXD has an inverse diode against VDDUART All other pins have no diode against their supply User s Manual Hardware Descri
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