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USER`S MANUAL

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1. FMUSR Flash Memory User Programming Control Register 11H Page 8 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write RAN R W RAN RAN RAN RAN RAN RAN Addressing Mode addressing mode 7 0 Flash Memory Programing Mode Enable Bits Others Disable User Programing Mode 10100101 Enable User Programing Mode FMSECH Memory Sector Address Register High Byte 12H Page 8 Bit Identifier 7 6 5 4 3 2 4 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode All addressing mode 7 0 Flash Memory Sector Address Bits High address of sector that s accessed FMSECL Memory Sector Address Register Low Byte 13H Page 8 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode All addressing mode 7 0 Flash Memory Sector Address Bits Low address of sector that s accessed 4 12 ELECTRONICS CONTROL REGISTERS S3C84MB F84MB UM REV1 00 IMR Interrupt Mask Register Bit Identifier RESET Value Read Write Addressing Mode 7 DDH Set 1 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W Register addressing mode only Interrupt Level 7 IRQ7 Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 6 IRQ6
2. PACONL Port 4 Control Register Low Byte F7H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 INT3 0 0 Input mode falling edge interrupt 0 1 Input mode rising edge interrupt 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output 5 4 P4 2 INT2 0 0 Input mode falling edge interrupt 0 1 Input mode rising edge interrupt 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output 3 2 P4 1 INT1 0 0 Input mode falling edge interrupt 0 1 Input mode rising edge interrupt 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output 1 0 P4 0 INTO 0 0 Input mode falling edge interrupt 0 1 Input mode rising edge interrupt 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output ELECTRONICS 4 25 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 PAINT Port 4 Interrupt Control Register FAH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 External Interrupt INT7 Enable Bit 0 Disable interrupt 1 Enable interrupt 6 P4 6 External Interrupt INT6 Enable Bit 0 Disable interrupt 1 En
3. Parameter Symbol Conditions Min Typ Max Unit Resolution 10 bit Total accuracy Vpp 5 12 V 3 Integral Linearity Error ILE AVrer 5 12V 2 Em Linearity DLE 2106 gt LSB Offset Error of Top EOT 1 3 Offset Error of Bottom EOB 50 5 2 Conversion time 10 bit resolution Max fano 2 5MHz en 7 7 ns Analog input voltage Vian AVss AVner V Analog input impedance Ran 2 1000 Analog reference voltage AVper 2 4 Vpp Analog ground AVss Vss Vss 40 3 Analog input current lADIN Vpp 5V 10 Analog block current lapc AVrer 5V 1 3 AVner 0 5 1 5 2 2 pu 10d 200 un NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc is an operating current during A D conversion Table 19 7 LVR Low Voltage Reset Circuit Characteristics Ta 40 C to 85 C Vpp 2 4 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Low Voltage Level Vivre LVR is enabled by smart option 2 4 2 8 3 2 V 252 3 5 4 0 4 5 ELECTRONICS ELECTRICAL DATA S3C84MB F84MB UM REV1 00 Table 19 8 Flash Memory D C Electrical Characteristics Ta 40 C to 85 C 2 4 V to 5 5 V Vss 0 V
4. 6 72 Rotate Right t ER CE o tp iei d 6 73 Rotate Righitithrougli te ath de D e teer t Des cte en 6 74 Select Bank 0 8s re ate be eee 6 75 Select Bank ee ee eee o ae dE raa ed dae des 6 76 Subtract with Camry isis ir cie ee oreste Hed i de 6 77 SEL Canny aste totu uris 6 78 Shift Aight Arithmetica e th e uet terae tet ud 6 79 Set Register PONTE 001 1 3 14 14100100800080 6 80 Stop Operaatio adeo 6 81 5 oi neben tatto d A Lum 6 82 Swap NI DIES 6 83 Test Complement under 0 1 1 11100 6 84 Test under Mask eie 6 85 Walt for Ded ua 6 86 Eogical Exclusive OR rn a ett aeter ee eR a 6 87 S3C84MB F84MB MICROCONTROLLER S3C84MB F84MB UM REV1 00 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are Efficient register oriented archit
5. P1CONEX Port 1 Extention Control Register OEH 8 Bit Identifier 7 6 5 4 3 2 21 0 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode addressing mode 7 Selection Bit 0 PORT1 7 Setting 1 PWM3 6 P1 6 PWM2 Selection Bit 0 PORT1 6 Setting 1 PWM2 5 P1 5 PWM1 Selection Bit 0 PORT1 5 Setting 1 PWM1 4 P1 4 PWMO Selection Bit 0 PORT1 4 Setting 1 PWMO 3 2 Not used for the 53084 84 1 P1 1 UART2 Rx Selection Bit 0 PORT1 1 Setting 1 UART2 Rx 0 P1 0 UART2 Tx Selection Bit 0 PORT1 0 Setting 1 UART2 Tx NOTE 1 When the UART2 is operating in mode 0 SIO Rx input P1CONEX 1 must be set to 0 and P1CON 0 1 must be set to input mode or input with pull up mode 00 or 10 In other operating modes mode 0 Rx output 1 2 3 P1CONEX 0 1 must be set to 41 and P1CON 0 1 values are don t care ELECTRONICS 4 19 CONTROL REGISTERS P2CONH Port 2 Control Register High Byte Bit Identifier RESET Value Read Write Addressing Mode 7 6 4 20 S3C84MB F84MB UM REV1 00 F2H Set 1 Bank 0 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P2 7 TAOUT 0 0 Input mode 0 1 I
6. UARTCON 1 UART Control Register FBH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 4 54 Register addressing mode only Operating mode and baud rate selection bits 0 0 Mode 0 SIO mode fxx 16 x BRDATA1 1 Mode 1 8 bit UART fxx 16 x 1 1 0 1 1 0 Mode 2 9 bit UART fxx 16 1 1 Mode 3 9 bit UART fo 16 x BRDATA1 1 Multiprocessor communication enable bit for modes 2 and 3 only 0 Disable 1 Enable Serial data receive enable bit 0 Disable 1 Enable If Parity disable mode location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If Parity enable mode parity selection bit for transmit data in UART mode 2 3 0 Even parity 1 Odd parity If Parity disable mode location of the 9th data bit that was received in UART mode 2 3 0 or 1 If Parity enable mode parity selection bit for receive data in UART mode 2 3 0 Even parity 1 Odd parity A result of parity error will be saved in UARTPRT register after parity checking of the received data Receive interrupt enable bit 0 Disable Receive interrupt 1 Enable Receive interrupt Transmit interrupt enable bit 0 Disable Transmit interrupt 1 Enable Transmit Interrupt
7. BXOR uin ste oi eite itte tedio CALL Call edrojo io y ERE ES CCF Complement Carry CLR ClO An mde eite t uan ieu COM Complement inanuia unia aai d et Hide Ld died CP Lr CPIJE Compare Increment and Jump on Equal CPIJNE Compare Increment and Jump on DA Decimal 56 s der dg dne re t eati ere enia t o pe diae DEC Decremoert 1 EU eive DECW Decremoent Word seders enana EEN rete e td RE DI Disable Interrupts tert tibt etes DIV Divide Unsigned esee cd tee DJNZ Decrement and Jump if 2 El Enable Interrupts 2 uio EE eee aut ENTER e eo AE ee aedi e A dE EXIT eoe IDLE Idle Operation et o re di eret acce et INC Incremento gi Inerement IRET Interrupt Return ty odo c nei de dua cea Eu ded JP Jump icis d a E rag dete ee E uto eg E JR ee E LD rr ED Mr EP ER T LDB or Tool ERN EE S3C84MB F84MB UM REV1 00 MICROCONTROLLER xxi Instruction M
8. Conversion Data Register Low Byte ADDATAL F9H Set 1 Bank 1 Read only AESESEZESESEXE Figure 15 2 A D Converter Data Register ADDATAH ADDATAL ADCON 7 4 ADCON 2 1 Select one input pin of the assigned To ADCON 3 Glock EOC Flag Selector ADCON 0 AD C Enabl AD C Enable Analog Comparator Successive Approximation Logic Input Pins ADCO ADC14 P6 0 P7 6 P7 0 P7 7 Multiplexer ADCON O A D Conversion enable 10 bit result is loaded into A D Conversion Data Register 10 bit D A Conversion Result Converter ADDATAH ADDATAL To Data Figure 15 3 A D Converter Circuit Diagram ELECTRONICS 10 BIT A D CONVERTER S3C84MB F84MB UM REV1 00 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to AVger usually AVrer Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 AVrer CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a maximum ADC input clock frequency 2 5 MHz one clock
9. Transmit Dit 0 0 ae ae Bt detect sample Time 1 210011 1111111 0111 11111 RIP Figure 14 10 Timing Diagram for UART Mode 3 Operation ELECTRONICS 14 11 UART 0 1 2 S3C84MB F84MB UM REV1 00 SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C8 series multiprocessor communication feature lets a master S3C84MB F84MB send a multiple frame serial message to a slave device in a multi S3C84MB F84MB configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART modes 2 or 3 In these modes 2 and 3 9 data bits are received The 9th bit value is written to RB8 UARTCONn 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCONn register When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In
10. 22 2 18 4 18 4 Flash Memory Sector Address Register FMSECH 18 5 18 5 Flash Memory Sector Address Register 18 5 18 6 Sectors in User Program esee 18 6 18 7 Sector Erase Flowchart in User Program 18 7 18 8 Byte Program Flowchart in a User Program 18 11 18 9 Program Flowchart in a User Program 18 12 19 1 Input Timing for External Interrupts Ports 4 Port 8 5 Port 8 6 19 5 19 2 Input Timing for RESE Tiii dee 19 5 19 3 Stop Mode Release Timing Initiated by 19 6 19 4 Clock Timing Measurement at 19 10 19 5 Operating Voltage 2 00 0 0 00000 eene nennen nnns nnns 19 10 20 1 S3C84MB F84MB 80 QFP Standard Package Dimension in Millimeters 20 1 20 2 S3C84MB F84MB 80 TQFP Standard Package Dimension in Millimeters 20 2 21 1 S3F84MBu Pin Assignments 80 21 2 21 2 53 84 Pin Assignments 80 21 3 22 1 Development System Configuration 00 22 2 22 2 TB84MB Targe
11. 3 3 Indirect Register Addressing to Program Memory 3 4 Indirect Working Register Addressing to Register File 3 5 Indirect Working Register Addressing to Program or Data Memory 3 6 Indexed Addressing to Register 3 7 Indexed Addressing to Program or Data Memory with Short Offset 3 8 Indexed Addressing to Program or Data 3 9 Direct Addressing for Load Instructions 2 3 10 Direct Addressing for Call and Jump 3 11 Indirect 3 12 Relative Addressihig n teer tuti sods cats Enron aac 3 13 Immediate 3 14 S3C84MB F84MB UM REV1 00 MICROCONTROLLER List of Figures continued Figure Title Page Number Number 4 1 Register Description 4 5 5 1 S3C8 Series Interrupt Types sssssssssssssssseee nennen nennen nennen 5 2 5 2 S3C84MB F84MB Interrupt Structure 5 4 5 3 ROM Vector Address nnns 5 5 5 4 Interrupt Function 5 8 5 5 System Mode Register SYM
12. neto He ec a e d dtd a i Hp d a i dete Ht o ee des 16 1 PWM Control Register 2222 16 1 2 E eror eh PR onines or rdiet duce edu e etae dne da Repub a eu acd 16 3 PWM2 Function 16 4 Staggered PWM 224 4 2 210 00 16 5 E M 16 6 rent Hn o Hl S Edad ee 16 6 PWM Data and Extension 16 6 PWM Glock Rate env y d doc 16 6 PWMO and PWM1 Function 16 8 Chapter 17 Pattern Generation Module TN DTE 17 1 Pattern G eratlon FIOW 545 1 leone da Heo a lie 17 1 S3C84MB F84MB UM REV1 00 MICROCONTROLLER ix Table of Contents Continued Chapter 18 Embedded FLASH Memory Interface Overview Flash Memory Control Registers Flash Memory Control Register Flash Memory User Programming Enable Register Flash Memory Sector Address Register Sector Erase Programming miles Hard Lock Protection Chapter 19 Electrical Data Overview
13. 4 0000 1 11 Pin Circuit Type E P6 iiid ettet ette ee tees 1 11 Pin Circuit Type G 5 7 5 4 1 11 Program Memory Address 2 2 1 2 2 Smart Opto M ER 2 3 Internal Register File Organization 2 5 Register Page Pointer enn 2 6 Set 1 Set 2 Prime Area H6glsler ic eet recrute 2 8 8 Byte Working Register Areas Slices sssssseeeneene 2 9 Contiguous 16 Byte Working Register 2 10 Non Contiguous 16 Byte Working Register Block 2 11 16 Bit Register AN be tA eevee eee 2 12 Register File 2 13 Common Working Register 02204 nnns 2 14 4 Bit Working Register Addressing ssssseene enne 2 16 4 Bit Working Register Addressing Example sene 2 16 8 Bit Working Register 00 2 17 8 Bit Working Register Addressing 2 2 18 Stack Operations is iate Ile t qe etd e o pnd Gee 2 19 Register AddIessing iu conte roe n 3 2 Working Register 00 2 3 2 Indirect Register Addressing to Register
14. 0 7 0 6 0 5 0 4 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Alternative function mode PGOUT lt 7 4 gt 2 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Alternative function mode PGOUT lt 3 2 gt 1 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Alternative function mode PGOUT lt 1 gt 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Alternative function mode PGOUT lt 0 gt ELECTRONICS 4 17 CONTROL REGISTERS P1CON Port 1 Control Register Bit Identifier RESET Value Read Write Addressing Mode 7 6 5 4 4 18 S3C84MB F84MB UM REV1 00 F1H Set 1 Bank 0 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P1 7 P1 6 0 0 Input mode 0 1 Input mode pull up 1 Push pull output P1 5 P1 4 0 0 Input mode 0 1 Input mode pull up 1 Push pull output 0 0 Input mode 0 1 Input mode pull up 1 Push pull output P1 1 P1 0 0 0 Input mode 0 1 Input mode pull up 1 x Push pull output ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS
15. Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H Q00H gt Register OOH 02H register 01H register 02H 70H If the general register 00H contains the value 01H and the register 01H the value 70H the statement POPUI 02H 900H loads the value 70H into the destination general register 02H The user stack pointer the register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3C84MB F84MB UM REV1 00 PUSH Push to Stack PUSH Operation Flags Format Examples src SP lt SP 1 5 src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4 OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and the general register 40H the value 4FH the statemen
16. 15 2 A D Converter Data Register ADDATAH ADDATAL 15 3 A D Converter Circuit 2244000 15 4 A D Converter Timing 15 5 Recommended A D Converter Circuit for Highest Absolute Accuracy S3C84MB F84MB UM REV1 00 MICROCONTROLLER xiii List of Figures Concluded Figure Title Page Number Number 16 1 PWM Control Register 16 2 16 2 Block Diagram for PWM2 and nenne 16 3 16 3 PWM Waveforms for PWM2 PWS sess nemen enn enne 16 4 16 4 PWM Clock to PWM2 Output Delays see 16 5 16 5 Block Diagram for PWMO and 1 16 7 16 6 Decision Flowchart for PWMO Programming 16 9 17 1 Pattern Generation 17 1 17 2 PG Control Register 17 2 17 3 Pattern Generation Circuit 22 17 2 18 1 Program Memory Address 18 2 18 2 Flash Memory Control Register 40000 18 4 18 3 Flash Memory User Programming Enable Register
17. FF i BDATAL 7EH 7EH FF 0 BDATAL 7EH 7EH Figure 11 6 Timer Output Flip Flop Waveforms in Repeat Mode ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P2 4 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 us 37 9 kHz 1 3 Duty Timer is used in repeat mode Oscillation frequency is 4 MHz 0 25 us TBDATAL 8 795 us 0 25 us 35 18 TBDATAH 17 59 5 0 25 us 70 36 Set P2 4 to TBPWM mode ORG START DI LD ELECTRONICS 0100H TBDATAH 70 2 TBDATAL 35 2 TBCON 400100111B P2CONH 03 Reset address Set 17 5 us Set 8 75 us Clock Source lt fy Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop T FF high Set P2 4 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P2 4 8 BIT A B C 0 1 S3C84MB F84MB UM REV1 00 PROGRAMMING TIP To generate a one pulse signal through P2 4 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The progra
18. ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTER UARTCON2 uART Control Register 03H Page 8 Bit Identifier 7 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELECTRONICS Register addressing mode only Operating mode and baud rate selection bits 0 0 Mode 0 SIO mode 16 x 2 1 Mode 1 8 bit UART fxx 16 x 2 1 0 1 1 0 Mode 2 9 bit UART 5 16 1 1 Mode 2 9 bit UART fxx 16 BRDATA2 1 Multiprocessor communication enable bit for modes 2 and 3 only 0 Disable 1 Enable Serial data receive enable bit 0 Disable 1 Enable If Parity disable mode location of the 9th data bit to be transmitted in UART mode 2 3 0 or 1 If Parity enable mode parity selection bit for transmit data in UART mode 2 3 0 Even parity 1 Odd parity If Parity disable mode location of the 9th data bit that was received in UART mode 2 3 0 or 1 If Parity enable mode parity selection bit for receive data in UART mode 2 3 0 Even parity 1 Odd parity A result of parity error will be saved in UARTPRT register after parity checking of the received data Receive interrupt enable bit 0 Disable Receive interrupt 1 Enable Receive interrupt Transmit interrupt enable bi
19. 4 16 POCON Port O Control Register iade fisse edt dece eee 4 17 P1CON Port 1 Control 40 204 4 18 1 Port 1 Extension Control 000 4 19 P2CONH Port 2 Control Register High Byte sse 4 20 P2CONL Port 2 Control Register Low 2 240444040 0 4 21 Port Control Register High 4 22 P3CONL Port Control Register Low 2 4 23 P4CONH Port 4 Control Register High 4 24 P4CONL Port 4 Control Register Low 44 00000 0 4 25 P4INT Port 4 Interrupt Control Register sssssssssse eene 4 26 PAINTPND Port 4 Interrupt Pending 4 27 P5CONH Port 5 Control Register High 4 28 P5CONL Port 5 Control Register Low Byte 4 29 P6CON Port 6 Registar ed e etes 4 30 7 Port 7 Gontrol Register 4 31 P8CONH Port 8 Control Register High Byte 4 32 P8CONL Port 8 Control Register Low Byte 4 0222 111 4 33 P8INTPND Port 8 Interrupt Pending
20. Clock Source Selection Bits O O fxx 16 0 1 fxx 8 1 0 fxx 4 1 1 fyy 1 A D Start or Enable Bit 0 Disable operation 1 Start operation NOTE Maximum ADC clock input 2 5 MHz 4 6 ELECTRONICS S3C84MB F84MB UM REV1 00 BRDATAO uaRTO Baud Rate Data Register Bit Identifier RESET Value Read Write Addressing Mode 7 0 NOTE Refer to UARTCONO register CONTROL REGISTERS BRDATA1 UART1 Baud Rate Data Register Bit Identifier RESET Value Read Write Addressing Mode 7 0 NOTE Refer to UARTCON register BRDAT A2 uART Baud Rate Data Register Bit Identifier RESET Value Read Write Addressing Mode 7 0 NOTE Refer to UARTCON register ELECTRONICS EAH Set1 Bank1 7 6 5 A 3 2 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Register addressing mode only Baud Rate Data for UARTO fxx 16 x BRDATA 1 FCH Set 1 Bank1 7 6 5 A 3 2 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Register addressing mode only Baud Rate Data for UART1 9 fxx 16 x BRDATA 1 04H Page 8 7 6 5 A 3 2 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W All addressing mode Baud Rate Data for UART2 fxx 16 x BRDATA 1 4 7 CONTROL REGISTERS S3C84MB F84
21. be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to BTCON O ELECTRONICS 10 1 BASIC TIMER S3C84MB F84MB UM REV1 00 Basic Timer Control Register BTCON D3H Set 1 R W we Watchdog timer enable bit Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTONT Basic timer input clock selection bit 00 fxx 4096 01 5 1024 10 fxx 128 11 fxx 16 Not used Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3C84MB F84MB UM REV1 00 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock The MCU is reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at r
22. 4 34 PGCON Pattern Generation Control 4 35 S3C84MB F84MB UM REV1 00 MICROCONTROLLER xix List of Register Descriptions continued Register Full Register Name Page Identifier Number PP Register Page Pointer i a a ia 4 36 PWMOEX 1EX PWM 0 1 Extension Register ssssssssssesseseeeen enne enne 4 37 PWMCON PWM Control 4 38 RPO Register Pointer Q sar inpren M 4 39 aia iad aa hi ain ad es 4 39 SIOCON SIO Control Register tease 4 40 SIOPS SIO Prescaler Register 2 5 d Iidem edet au etie tes 4 41 SIOCON 1 SIO1 Gontrol Reglster icc ai ai lie testis ia d i de Needs 4 42 SIOPS1 SIO1 Prescaler 2 2 4 1 1 4 43 SPH Stack Pointer High Byte ener 4 44 SPL Stack Pointer Low Byte entente nennen 4 44 STOPCON Stop Control Register ssssssssssssssseseseenee eee enne nnne nennen 4 44 SYM System Mode Register ssssssssssssssseseeeene nennen nennen nnns streiten en 4 45 T1CONO Timer 1 0 Control 4 46 1 Timerzt 1 Control Register terre es b cet 4 47 Timer
23. 9 17 9 12 Port 5 High Byte Control Register PBCONH sees 9 19 9 13 Port 5 Low Byte Control Register PSCONL seen 9 20 9 14 Port 6 Control Register 9 21 9 15 Port 7 Control Register P7CON 9 23 9 16 Port 8 High Byte Control Register 9 25 9 17 Port 8 Low Byte Control Register 8 9 26 9 18 Port 8 Interrupt Pending Register 9 27 xii S3C84MB F84MB MICROCONTROLLER List of Figures continued Figure Title Number 10 1 Basic Timer Control Register BTCON 10 2 Basic Timer Block 11 1 Timer A Control Register 11 2 Timer Functional Block 11 3 Timer B Functional Block Diagram eene 11 4 Timer B Control Register 2 11 5 Timer Data Registers TBDATAH TBDATAL 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 7 Timer C 0 1 Control Register TCCONO TCCONYH 11 8 Timer C 0 1 Functional Block Diagram 12 1 Timer 1 0
24. Parameter Symbol Conditions Min Typ Max Unit Logic power supply Vpp 2 4 5 0 5 5 V Flash memory Vpp 2 4 V to 5 5 V operating current Foot during reading a 10 mA Foo 2 4V to 5 5V Fppe 10 mA during programming Vpp 24V to 55V Foo during erasing 10 Table 19 9 Flash Memory Electrical Characteristics Ta 40 C to 85 C Vpp 2 4 V to 5 5 V Vss 0 V Parameter Symbol Conditions Min Typ Max Unit Programming time Ftp 20 30 50 us Chip Erasing time Ft 10 mS LM Vpp 24V to 55V Sector Erasing time Ftp2 10 mS Data access time Ftns 100 nS Number of Fnwe 10 000 writing erasing Data Retention Time Ftpr 10 Years NOTES 1 The Programming time is the time during which one byte 8 bit is programmed 2 Thechip erasing time is the time during which all 64K byte block is erased 3 The sector erasing time is the time during which one 128 byte block is erased 19 8 ELECTRONICS S3C84MB F84MB UM REV1 00 ELECTRICAL DATA Table 19 10 Main Oscillator Frequency fosc Ta 40 C to 85 C Vpop 2 4 V to 5 5 V Oscillator Clock Circuit Test Condition Min Typ Max Unit Crystal 2 4 V to 5 5 V 1 10 MHz Vpp 45V to 55V 1 16 C2 Ceramic 2 4 V to 5 5 V 1 10 Vpp 45V to 55V 1 16 External clock Vbo 2 4 V to 5 5V 1 10 Vpp 45V to 55V 1 16 Table
25. gt gt 1 IRQ4 gt IRQ3 Undefined Group C 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register ELECTRONICS 5 13 INTERRUPT STRUCTURE S3C84MB F84MB UM REV1 00 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while
26. 1 Stack address OFBH R3 R3 Stack address HP1 Stack address OFCH Stack address OFDH PP Stack address OFEH ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM8RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3C84MB F84MB UM REV1 00 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 3 2
27. A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located in set1 bank 1 at address F7H ADCON is read write addressable using 8 bit instructions only But EOC bit ADCON 3 is read only ADCON has four functions Bits 7 4 select an analog input pin ADCO ADCH14 3 indicates the end of conversion status of the A D conversion Bits 2 1 select a conversion speed Bit 0 starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the eight analog input pins ADCO ADC 14 by manipulating the 4 bit value for ADCON 7 ADCON 4 A D Converter Control Register ADCON F7H Set 1 Bank 1 R W ADCON 3 bit is read only T4 6 D 4 3 2 0 A D Start or Enable bit A D Input Pin Selection bits E 7 6 5 4 A D Input Pin 0000 ADCO Clock Selection bit 0001 ADC1 0010 ADC2 2 1 Conversion Clock 0011 ADC3 fxx 16 0100 ADC4 fxx 8 0101 ADC5 fxx 4 0110 ADC6 fxx 1 0111 ADC7 1000 ADC8 1001 ADC9 End of Conversion bit read only 1010 ADC10 0 Conversion not complete 1011 11 1 Conversion complete 1100 ADC12 1101 ADC13 1110 ADC14 Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS S3C84MB F84MB UM 1 00 10 BIT A D CONVERTER Conversion Data Register High Byte ADDATAH F8H Set 1 Bank 1 Read only
28. T1CKO P3 0 CJ 28 NT7 P4 7 29 NT6 P4 6 C 30 NTO P4 0 C 36 ADC7 P7 7 37 ADC6 P7 6 CJ 38 ADC5 P7 5 39 ADC4 P7 4 40 T1CAPO P3 2 26 1 1 1 TCOUT1 P3 7 21 TCOUTO P3 6 22 T1OUT1 P3 5 CJ 23 T1OUTO P3 4 24 T1CAP1 P3 3 25 Figure 1 3 S3C84MB F84MB Pin Assignment 80 TQFP PRODUCT OVERVIEW P8 2 SCK1 3 P8 4 INT8 P8 5 INT9 P6 0 ADC8 P6 1 ADC9 P6 2 ADC10 P6 3 ADC1 1 P6 4 ADC12 VDD2 VSS2 P6 5 ADC13 P6 6 ADC14 P6 7 P7 0 ADCO P7 1 ADC1 P7 2 ADC2 P7 3 ADC3 AVSS AVREF PRODUCT OVERVIEW S3C84MB F84MB UM REV1 00 PIN DESCRIPTIONS Table 1 1 S3C84MB F84MB Pin Descriptions 80 QFP Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins P0 0 PO0 7 Bit programmable port input or output mode D 80 73 PGO PG7 selected by software input or push pull output Software assignable pull up Alternately 0 0 0 7 can be used as the PG output port PGO PG7 P1 0 P1 7 I O Bit programmable port input or output mode D 72 65 TxD2 RxD2 selected by software input or push pull output Software assignable pull up PWM2 PWM3 2 0 2 7 Bit programmable port input or output mode D 8 1 500 selected by software input push pull output SIO Software assignable pull up SCKO Alternately P2 0 P2 7 can be used as I O for TBPWM TIMERA TIMERB SIO TACK TACAP TAOUT 0 7 Bit programmable port
29. 40 to 85 Vop 24 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Operating voltage Vop fosc 10 MHz 2 4 5 5 Input high voltage Vin All input pins except 0 8 Vpp Vpp Xin Vpp 0 5 Vpp V Input low voltage Vii All input pins except Vio 0 2 Vio 0 4 ELECTRONICS S3C84MB F84MB UM REV1 00 Table 19 2 D C Electrical Characteristics Continued 40 C to 85 Vpp 2 4 V to 5 5 V ELECTRICAL DATA RESETB Parameter Symbol Conditions Min Typ Max Unit Output high voltage Vpp 5 V lou 1 mA All output pins except Vpp 1 0 0 2 6 2 5 V 4 0 2 2 0 V Output low voltage Vo Voo 5 V lop 4 mA All output pins except V E 0 4 20 Vpp 5 V 16 Port 0 2 6 Input high leakage Vin 3 current All input pins except ij Vin Vpp Xie Xo d Input low leakage Vin OV 3 current All input pins except Vin ViN Vi 20V 20 Xin Xour Output high leakage Vout e _ 3 current All I O pins and Output pins Output low leakage Vout 0 _ _ 3 current All I O pins and Output pins Pull up resistor Vi 20V Voo 5 V 10 96 Port 0 8 Ta 25 C All Output Pin except zi a dd RESETB Vin 0 V Vpp 3 V 10 96 Port 0 8
30. 5 10 5 6 Interrupt Mask Register 5 11 5 7 Interrupt Request Priority Groups nennen 5 12 5 8 Interrupt Priority Register 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register 6 6 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator 7 1 7 2 System Clock Circuit 7 2 7 3 System Clock Control Register 1 7 3 9 1 Port 0 Control Register 2 2 4 64 9 4 9 2 Port 1 Control Register 00 0 0 9 6 9 3 Port 1 Extension Control Register 9 7 9 4 Port 2 High Byte Control Register 2 9 9 9 5 Port 2 Low Byte Control Register P2CONL sse 9 10 9 6 Port High Byte Control Register PS8CONH sse 9 12 9 7 Port Low Byte Control Register PSCONL seen 9 13 9 8 Port 4 High Byte Control Register 48 9 15 9 9 Port 4 Low Byte Control Register PACONL sse 9 16 9 10 Port 4 Interrupt Control Register 9 17 9 11 Port 4 Interrupt Pending Register
31. Control 4 2 1 ener nnne enn nnne nent 4 48 TBCON Timer B Control 4 422444 4 nnne 4 49 TCCONO Timer C 0 Control 4 50 1 Timer C 1 Control 4 51 TINTPND Timer A 1 Interrupt Pending Register 2 4 52 UARTCONO UARTO Control Register esses eene 4 53 UARTCON 1 VARTI ret rd t e Mae 4 54 UARTCON2 UART2 Gontrol BeglSter teret pte ees ted et tbt e ceti 4 55 UARTPND UART1 0 Pending Register sss ener 4 56 UARTPRT UARTO 1 2 Parity Control Register 4 57 XX S3C84MB F84MB MICROCONTROLLER List of Instruction Descriptions Instruction Full Register Name Mnemonic ADC Add with Garry aiios ite ae ru Bag eae edle apis ADD 22 52 16 MN AND Logra AND x23 oi 555 225 usc t Lt orsa BAND BIUAND irit eti ftne etant Fete t edat BCP mL eae a uti BITC Bit Gomplement te eet e b qud BITR Bit Rea eae ta aene BITS slm M c E BOR Bit OB anie ite aa Meet dte HD des BTJRF Bit Test Jump Relative on BTJRT Bit Test Jump Relative on
32. 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 0 0 9 AO 60 1 1 6 F 1 6 F 9A 66 1 Flags C Setifthere was a carry from the most significant bit cleared otherwise see table Z Setif result is 0 cleared otherwise S Setif result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3C84MB F84MB UM REV1 00 DA Decimal Adjust DA Example Continued Given The working register RO contains the value 15 BCD the working register R1 contains 27 BCD and the address 27H contains 46 BCD ADD R1 RO 0 H lt 0 Bits 4 7 3 bits 0 3 C RT lt 3CH DA R1 R1 lt 06 If an addition is performed using the BCD values 15 27 the result should be 42 sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO lt H lt 0 Bits 4 7 3 bits 0 3 1 R1 R1 lt 31 0 leave the value 31 BCD in the address 27H QR1 ELECTRONICS S3C84MB F84MB UM REV1 00 DEC Decremen
33. 0000 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1447H the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and the stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and the stack pointer are the same as in the first example if the program address 0040H contains 35H and the program address 0041H contains 21H the statement CALL 40 produces the same result as in the second example ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one C Complemented No other flags are aff
34. 01010001B R9 33H R10 40H R11 40H RR10 R9 R11 RO WR BYTE FMCON 01010000B PP 80H FMUSR 00 PP 0 ELECTRONICS RR10 gt Address copy R10 high address R11 low address User Program mode enable Set sector address located in target address to write data SECTOR128 sector base address 4000H Programming mode enable Load data 33H to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Write data 33H at flash memory location Reset address in the same sector by INC instruction Check whether the end address for programming reach 407FH or not Programming stop User Program mode disable 18 13 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 Case3 Programming to the flash memory space located in other sectors WR INSECTOR2 LD RO 40 LD R1 40H LD PP 80H LD FMUSR 0 5 LD FMSECH 01 LD FMSECL 00H LD PP 40 SB1 LD 01010001B 5 0 LD R9 0 LD R10 01H LD R11 40H CALL WR BYTE LD RO 40 WR INSECTOR50 LD PP 80H LD FMSECH 19 LD FMSECL 00 LD PP 40 LD R9 55H LD R10 19 LD R11 40H CALL WR BYTE WR INSECTOR128 LD PP 80H LD FMSECH 40 LD FMSECL 00 LD PP 40 LD R9 LD R10 40H LD R11 40H WR 1 LDC QRR10 R9 INC R11 DJNZ R1 WR_BYTE1 SB1 L
35. 4 When Data Counter 8 Bit Comparator PWM Output 1 When Data gt Counter Lower 8 Bit of 14 bit Counter PWM S3C84MB F84MB UM REV1 00 PWMO AND PWM1 FUNCTION DESCRIPTION The PWM output signal toggles to Low level whenever the lower 8 bit counter matches the reference value stored in the module s data register 1 If the value in the PWM data register is not zero an overflow of the lower counter causes the PWM output to toggle to High level In this way the reference value written to the data register determines the module s base duty cycle The value in the 6 bit extension counter the lower six bits of the upper counter is compared with the extension settings in the 6 bit extension data register PWMOEX PWM1 EX This 6 bit extension counter value bits 2 7 together with extension logic and the PWM module s extension register is then used to stretch the duty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles see Table 16 2 If for example the value in the extension register is 1 the 32nd cycle will be one pulse longer than the other 63 cycles If the base duty cycle is 5096 the duty of the 32nd cycle will therefore be stretched to approximately 5196 duty For example if you write 80H to the extension register all odd numbered pulses will be one cycle longer If you write FCH to the extension register all pulses will be s
36. 59 8 Duration 206 us 10 MHz x tal 11 15 8 BIT A B C 0 1 PROGRAMMING TIP Using the Timer C 0 INITIAL MAIN TCUN INT 11 16 ORG 0000h VECTOR OBCh TCUN INT ORG 0100h LD SYM 00h LD IMR 00000100b LD SPH 00000000b LD SPL 11111111b LD BTCON 1010001 1b LD P3CONH 001 10000b LD TCDATAO 80h LD 000011106 EI MAIN ROUTINE JR T MAIN Interrupt service routine e IRET END S3C84MB F84MB UM REV1 00 Disable Global Fast interrupt Enable IRQ2 interrupt Set stack area Disable Watch dog high speed Enable TCOUTO output non divide interval Enable interrupt Duration 0 825ms 10 MHz x tal ELECTRONICS S3C84MB F84MB UM REV1 00 16 BIT TIMER 1 0 1 16 BIT TIMER 1 0 1 OVERVIEW The S8C84MBJ F84MBJ has two 16 bit timer counters The 16 bit timer 1 0 1 is a 16 bit general purpose timer counter Timer 1 0 1 has three operating modes of which you select using the appropriate T1 CONO T1CON1 setting is Interval timer mode Toggle output at TTOUTO T1OUT1 pin Capture input mode with a rising or falling edge trigger at the T1CAP1 pin PWM mode T1PWMO T1PWM1 PWM output shares their output port with T1OUTO T1OUT1 pin Timer 1 0 1 has the following functional components Clock frequency divider fx divided by 1024 256 64 8 or 1 with multiplexer External clock input pin T1CKO T1CK1 A 16 bit counter T1CNT
37. 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http Awww seminix com ELECTRONICS 22 7 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER S3C84MB F84MB UM REV1 00 SPW uni ma Single OTP MTP FLASH Programmer e Download Upload and data edit function e PC based operation with USB port 9 Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection Fast programming speed 4Kbyte sec e Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software SEMINIX TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com AS pro On board programmer for Samsung Flash MCU e Portable amp Stand alone Samsung OTP MTP FLASH Programmer for After Service e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e HEX file download via USB port from PC e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Internal large buffer memory 118M Bytes e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Two kind of Power Supplies User system power or USB power adapter e Support Firmware up
38. Chapter 20 Mechanical Data Overview Chapter 21 S3F84MBJ Flash MCU ei Operating Mode Characteristics Chapter 22 Development Tools ed dt addenda die dd TO T Programming Socket Adapter TB84MB Target Board HINZU ta SLOP SLED cc EUM OTP MTP Programmer Writer S3C84MB F84MB UM REV1 00 MICROCONTROLLER Figure Number I ll l 0 3 lll it 1 eo A o 2 11 2 12 2 13 2 14 2 15 2 16 3 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 List of Figures Title Page Number S3C84MB F84MB Block 1 3 S3C84MB F84MB Pin Assignment 80 1 4 S3C84MB F84MB Pin Assignment 80 0 1 5 Pin Circuit B 1 9 Pin GIrcult Ty pe Q ee HE EDT dares I Pen 1 9 Pin Circuit Type D PO P1 P2 except P2 3 P8 except P8 4 8 5 1 10 Pin Circuit D 1 P4 P8 4 1 10 Pin Circuit Type E 0
39. DFH In the SSC84MB F84MB microcontroller a paged register file expansion is implemented for data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set1 R W Source page selection bits Destination Page 0 0000 Source Page 0 Destination Page 8 1000 Source Page 8 NOTE In the S3C84MB F84MB microcontroller pages 0 8 are implemented A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to address other pages Figure 2 4 Register Page Pointer PP PROGRAMMING TIP Using the Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination lt 0 Source lt 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD PP 10H Destination lt 1 Source lt 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR ORO 00H NOTE You should refer to page 6 40 and use DJNZ instruction properly when DJNZ instruction is used in your program 2 6 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register f
40. E6H FOH F2H F4H F6H A2H Sources Timer A match capture Timer A overflow Timer B underflow H W S3C84MB F84MB_UM_REV1 00 Reset Clear H W S W H W S W Timer C 0 match overflow H W S W Timer 1 match overflow H W S W Timer 1 0 match capture Timer 1 1 match capture Timer 1 1 overflow 0 Timer 1 0 overflow 1 1 SIOO receive transmit S W 5101 receive transmit S W P8 4 external interrupt S W P8 5 external interrupt S W P4 0 external interrupt S W P4 1 external interrupt S W P4 2 external interrupt S W P4 3 external interrupt S W P4 4 external interrupt S W P4 5 external interrupt S W P4 6 external interrupt S W P4 7 external interrupt S W UARTO data receive S W UARTO data transmit UART1 data receive S W UART1 data transmit S W UART2 data receive S W UART2 data transmit S W H W S W H W S W H W S W H W S W 1 Within a given interrupt level the lower vector address has high priority For example B8H has higher priority than BAH within the level IRQO the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting 5 4 Figure 5 2 S3C84MB F84MB Interrupt Structure ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the 53084 84 inter
41. Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 5 IRQ5 Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 4 IRQ4 Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 3 IRQ3 Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 2 IRQ2 Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 1 IRQ1 Enable Bit 0 Disable mask 1 Enable un mask Interrupt Level 0 IRQO Enable Bit 0 Disable mask 1 Enable un mask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU ELECTRONICS 4 13 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 IPH instruction Pointer High Byte DAH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value X X X X X X Read Write Addressing Mode R W R W R W R W R W R W R W R W Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address 15 8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 Bit Identifier 7 6 5 4 3 2 4 0 RESET V
42. Program Memory Register File OPERAND 8 bit Register re nates fx i v Point to One o Z Register in Register 2 2 One Operand mse Instruction Value used Instruction Execution Sample Instruction DEC CNTR Where ONTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 RPO or RP1 Selected RP points to start of working Program Memory 4 bit EL NEN register orking Register dst block OPCODE Point to the OPERAND Working Register Two Operand 108 Instruction Example Sample Instruction ADD R1 R2 Where R1 R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Re
43. R6 06H R7 1CH R4 06H R5 1 LDW 00H 02H Register 00H 03H register 01H OFH register 02H register OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04 001 gt Register 03H register 05H OFH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H OFH register OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H and 03H into the destination word OOH and 01H This leaves the value 03H in the general register 00H and the value OFH in the register 01H Other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3C84MB F84MB UM REV1 00 MULT Multiply Unsigned MULT Operation Flags Format Examples dst src dst dst x src INSTRUCTION SET The 8 bit destination operand the even numbered register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Set ifthe result is gt 255 cleared otherwise Given Register 20H register 01H 03H register 02H MULT MULT MULT 00H 02H 00H 01H gt 00H 30H Setif MSB of the result is a 1 cleared otherwise Z Setif the result is 0 cleared otherwise S V Clea
44. Register ESH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELECTRONICS Register addressing mode only Operating mode and baud rate selection bits 0 0 Mode 0 SIO mode fxx 16 x BRDATAO 1 Mode 1 8 bit UART 16 x BRDATAO 1 0 1 1 0 Mode 2 9 bit UART 5 16 1 1 Mode 3 9 bit UART fxx 16 x BRDATAO 1 Multiprocessor communication enable bit for modes 2 and 3 only 0 Disable 1 Enable Serial data receive enable bit 0 Disable 1 Enable If Parity disable mode location of the 9th data bit to be transmitted in UART mode 2 3 0 or 1 If Parity enable mode parity selection bit for transmit data in UART mode 2 3 0 Even parity 1 Odd parity If Parity disable mode location of the 9th data bit that was received in UART mode 2 3 O or 1 If Parity enable mode parity selection bit for receive data in UART mode 2 3 0 Even parity 1 Odd parity A result of parity error will be saved in UARTPRT register after parity checking of the received data Receive interrupt enable bit 0 Disable Receive interrupt 1 Enable Receive interrupt Transmit interrupt enable bit 0 Disable Transmit interrupt 1 Enable Transmit Interrupt 4 53 CONTROL REGISTERS S3C84MB F84MB UM REV1 00
45. S3C84MB F84MB UM REV1 00 UART 0 1 2 BLOCK DIAGRAM 5 8 Internal Data Bus 1 Baud Rate Generator Zero Detector Write to UARTDATA gt Start Shift Tx Control EN Tx Clock Send IRQ7 a TIE Interrupt 4 EC RIE Rx Clock Receive Rx Control Start Shift 1 to 0 Transition 1 Detector Bit Detector 1 Shift Register UARTDATA 8 Internal Data Bus Figure 14 6 UART Functional Block Diagram ELECTRONICS 14 7 UART 0 1 2 S3C84MB F84MB UM REV1 00 UARTO MODE 0 FUNCTION DESCRIPTION In mode 0 UARTO is input and output through the RxDO P5 3 pin and TxDO P5 2 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCONO 6 and 7 to 2 Write transmission data to the shift register UDATAO E2H set 1 bank 1 to start the transmission operation Mode 0 Receive Procedure 1 Select mode 0 by setting UATCONO 6 and 7 to 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UARTO receive enable bit UARTCONO 4 to 1 4 The shift clock will now be output to the TxDO P5 2 pin and will read the data at the RxDO P5 3 pin A UARTO receive interrupt IRQ7 vector FO
46. The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 2 14 F3 Irr r Given RO 7FH R6 21H and R7 LDCPI RR6 RO RR6 bRRG 1 TFH the contents of RO is loaded into program memory location 2200H 21FFH 1H RO R6 22H R7 00H LDEPI RR6 RO RR6 lt bRR6 1 TFH the contents of RO is loaded into external data memory location 2200H 21FFH 1H RO R6 22H R7 00H LDEPI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 57 INSTRUCTION SET S3C84MB F84MB UM REV1 00 DW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register OOH 1AH register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt
47. The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Setif a borrow occurred cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise 9 Always set to 1 I Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 22 r r 6 23 r Ir src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 register 01H 21H register 02H register OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H Register 01H register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H SUB 01H 90H gt Register 01H 91H S and V 1 SUB 01H 65H gt Register 01H OBCH 5 1 0 In the first example if he working register R1 contains the value 12H and if t
48. These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD refers to program memory and LDED refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 E2 r Irr Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 RR6 1 LDED R8 RR6 contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H LDED instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples NOTE dst src dst src dst lt src rr m 1 These instructions are used for user stacks or blo
49. UARTCONO E3H Set 1 Bank 1 R W UARTCON 1 FBH Set 1 Bank 1 RAW 2 03H Page 8 R W See table below Transmit interrupt enable bit 0 Disable 1 Enable Multiprocessor communication 4 enable bit for modes 2 only 0 Disable 1 Enable Received interrupt enable bit 0 Disable 1 Enable If PENn 0 pa dcs 5 it Location of the 9th data bit that was received UART mode 2 0 or 1 If PENn 0 else parity bit for Rx data Location of the 9th data bit to be 0 1 040 transmitted in UART mode 2 0 or 1 else parity bit for Tx data 0 1 Odd Operating mode and baud rate selection bits MS1 50 Description Baud Rate Shift Register fXX 16xBRDATA 1 8 bit UART fXX 16xBRDATA 1 8 bit UART 16 9 bit UART fXX 16xBRDATA 1 NOTES 1 In mode 2or 3 if the UARTCON S5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Parity enable bits PEN is located in the UARTPRT register at address 06H Page 8 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 and 3 only Figure 14 1 UART Control Regi
50. and the 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fyx 8 fo 2 or 1 When the divided clock is selected to system clock be careful using interrupt If the interrupt interval is short than interrupt service routine processing time interrupt request cannot be guaranteed System Clock Control Register CLKCON 4 Set 1 R W we Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fxx 16 01 fxx 8 10 fxx 2 11 fxx 1 non divided Figure 7 3 System Clock Control Register CLKCON ELECTRONICS 7 3 S3C84MB F84MB UM REV1 00 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESETB pin is forced to Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S3C84MB F84MB into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESETB pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both Vpp and RESETB are High level the RESETB
51. dels 6 10 6 0101011614 6 6 12 S3C84MB F84MB Set 1 Bank 0 Register Values after RESET 8 2 S3C84MB F84MB Set 1 Bank 0 Register Values after RESET 8 3 S3C84MB F84MB Set 1 Bank 1 Register Values after RESET 8 4 S3C84MB F84MB Page 8 Register Values after 8 5 S3C84MB F84MB Port Configuration Overview sese 9 1 Port Data Register Summary sssssssssssssssseee eene nennen nens 9 2 Commonly Used Baud Rates Generated by BRDATAO BRDATA1 BRDATA2 14 6 PWMO PWM1 Control and Data Registers 16 7 PWM Output Stretch Values for Extension Registers PNMOEX PWM1EX 16 8 ISP Sector Size ee e edi etc ari udi ete edi 18 3 S3C84MB F84MB UM REV1 00 MICROCONTROLLER Table Number 19 1 19 2 19 3 19 4 19 5 19 6 19 7 19 8 19 9 19 10 19 11 22 1 22 2 22 3 xvi List of Tables continued Title Page Number Absolute Maximum 19 2 D C Electrical 19 2 A C Electrical Characteristics 2 19 5 Input Output Capacitance 0 4 0 0 0 19 6 Dat
52. input or output mode D 30 23 T1CKO selected by software input or push pull output T1CK1 Software assignable pull up T1CAPO Alternately P3 0 P3 7 can be used as I O for T1CAP1 TIMERCO C1 TIMER10 11 T1OUTO T1OUT1 TCOUTO TCOUT1 1 6 ELECTRONICS S3C84MB F84MB UM REV1 00 PRODUCT OVERVIEW Table 1 1 S3C84MB F84MB Pin Descriptions 80 QFP Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins 4 0 4 7 Bit programmable port input or output mode D 1 38 31 1 selected by software input push pull output INT7 Software assignable pull up 4 0 4 7 can alternately be used as inputs for external interrupts INTO INT7 respectively with noise filters and interrupt controller P5 0 P5 7 Bit programmable port input or output mode G 22 17 11 9 TxD1 selected by software input or push pull output RxD1 Software assignable pull up TxDO Alternately P5 0 P5 3 can be used as I O for serial RxDO por UARTO UART1 respectively P6 0 P6 7 V O N channel open drain output Alternatively used as F 58 54 51 49 ADC8 analog input pins for A D converter modules ADC14 7 0 7 7 General purpose digital input ports Alternatively E 48 45 42 39 ADCO used as analog input pins for A D converter ADC7 modules P8 0 P8 5 Bit programmable port input or output mode D D 1 64 59 INT8 INT9 selected by software inp
53. register 02H 2EH C 0 In the first example if the general register 00H has the value 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register 00H leaving the value 55H 01010101B The MSB of the register resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET RR Rotate Right RR Operation Flags Format Examples dst C lt dst 0 dst 7 dst 0 dst n dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag S 3 Set if the bit rotated from the least significant bit position bit zero was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 EO R 4 E1 IR Given Register 31H register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR 01H Register 01 02H register 02H 8BH C 1 In the first example if the general re
54. the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B ELECTRONICS 2 15 ADDRESS SPACES S3C84MB F84MB UM REV1 00 Selects RPO or Address OPCODE 4 bit address Register pointer provides three provides five low order bits high order bits LONE EE M Together they create an 8 bit register address Figure 2 12 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register 01110 address 0110 1110 INCES 76H Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES 8 WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much
55. 1 to TACON 3 The timer A overflow interrupt TAOVF is interrupt level IRQO and has the vector address BAH When a timer overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer A match capture interrupt IRQO vector B8H you must write TACON 1 to 1 To generate the exact time interval you should write 1 to TACON 3 and 0 to TINTPND 0 which cleared counter and interrupt pending bit Timer A Control Register EAH Set 1 Bank 0 R W Reset 00H ERDPIBDBLIJe Timer A input clock selection bit used fxx 1024 fxx 256 Timer A match capture interrupt fxx 64 enable bit 11 External clock TACK 0 Disable interrupt Enable interrrupt Timer A operating mode selection bit 00 Interval mode TAOUT mode Timer A overflow interrupt enable bit 01 Capture mode capture on rising edge 0 Disable overflow interrupt counter running OVF can occur 1 Enable overflow interrrupt 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF interrupt and match 0 No effect Timer A counter clear bit interrupt can occur 1 Clear the timer A counter when write NOTE When the counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Pending bit of overflow and match capture intterupt are located in TINTPND 9 0 register F
56. 19 11 Main Oscillator Clock Stabilization Time TA 40 C to 85 C 2 4 V to 5 5 V Oscillator Test Condition Min Typ Max Unit Crystal fosc 400kHz 10 Ceramic Stabilization occurs when Vpp is equal to the minimum _ _ 4 ms oscillator voltage range External clock input high and low level width txu tx 50 ns NOTE Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power on occurs or when Stop mode is ended by a RESET signal ELECTRONICS 19 9 ELECTRICAL DATA S3C84MB F84MB UM REV1 00 l fosci a Figure 19 4 Clock Timing Measurement at Xi Figure 19 5 Operating Voltage Range 19 10 ELECTRONICS S3C84MB F84MB UM REV1 00 MECHANICAL DATA 2 0 Mechanical Data OVERVIEW 23 90 0 30 20 00 0 20 80 QFP 1420C a 0 10 MAX 17 90 0 30 14 00 0 20 O 0 35 0 10 080 015 MAX 12 lt 2 65 0 10 pud e 3 00 0 80 0 20 NOTE Dimensions in millimeters Figure 20 1 S3C84MB F84MB 80 QFP Standard Package Dimension in Millimeters ELECTRONICS 20 1 MECHANICAL DATA S3C84MB F84MB UM REV1 00 14 00 BSC E 0 09 0 20 80 TQFP 1212 Q 0 0 0 60 0 15 0 05 0 15 1 00 gt 0 0
57. 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations ELECTRONICS 2 7 ADDRESS SPACES S3C84MB F84MB UM REV1 00 PRIME REGISTER SPACE The lower 192 bytes 00 of the S3C84MB F84MB s eight 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the register page pointer PP to the appropriate source and destination values Set 1 FFH Bank 0 Bank 1 COH Ed CPU and system control General purpose Peripheral and 1 Figure 2 5 Set 1 Set 2 Prime Area Register 2 8 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you ca
58. 22 0020 20 IPH 00 21 IPL 50 22 Data 140 Memory Stack Stack 6 42 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET IDLE Operation IDLE Operation See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 6F Example The instruction IDLE stops the CPU clock but it does not stop the system clock ELECTRONICS 6 43 INSTRUCTION SET S3C84MB F84MB UM REV1 00 INC Increment INC Operation Flags Format Examples dst dst dst 1 The contents of the destination operand are incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r OtoF dst 2 4 20 R 4 21 IR Given RO 1BH register OOH OCH and register 1BH OFH INCRO RO 1CH INCOOH gt Register 00H INC RO RO 1BH register 01H 10H In the first example if the destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The seco
59. 6613 e E mail openice aijisystem com e URL http www aijisystem com e GW PRO2 Gang Programmer for OTP MTP FLASH MCU 8 devices programming at one time Fast programming speed 1 2Kbyte sec PC based control operation mode or Stand alone Full Function regarding OTP MTP program Read Program Verify Protection Blank e Data back up even at power break After setup in Design Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation status displayed in LCD panel SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com ELECTRONICS 22 9
60. 9 21 nma p EE 9 22 m 9 24 10 Basic Timer QVOIVIOW i aii v HEB ead Face d ota dad 10 1 Basics Timer BT ii tien oii cape ates E te eite n ie pe nde ir tefie 10 1 Basic Timer Control Register BTCON ccccceeeeeeeeeneeeeeeeeceaeeeeaaeeeeaeeseeaeeesaaeeseeeeseaeeesaeeseaaeseeeeeeeas 10 1 Basic Timer Function 10 3 S3C84MB F84MB UM REV1 00 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 bit Timer A B C 0 1 OBI eiie coda cere Ao dn ose e NOE 11 1 IM m A 11 1 Function DeseriptiOris ori op troppe od nodi qeu d sre 11 2 Timer A Control Register TACON 11 3 Block Diagramm serrr Ea sere eaten nii cedere aeo aie ie ette dats 11 4 8 8 Timer B cct tm eR 11 5 OV SI VIEW sf mit rie EE 11 5 Block Diagram i et rete nt m Ite e LAE 11 5 Timer B Control Register enne enne 11 6 Timer B Pulse Width Calculations eer erbe cate RR ERR 11 7 11 11 Meas 11 11 Timer 0 1 Contro
61. De X D7 X Stop Bit TIP Transmit PAD Bude Du 06 27 Feng Bt detect TTL TL TTL LLL RIP Figure 14 9 Timing Diagram for UART Mode 2 Operation 14 10 ELECTRONICS S3C84MB F84MB UM REV1 00 UART 0 1 2 UARTO MODE 3 FUNCTION DESCRIPTION In mode 3 11 bits are transmitted through the TxDO or received through the RxDO Mode is identical to mode 2 except for baud rate which is variable Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 Mode 3 Transmit Procedure 1 Select the baud rate generated by setting BRDATAO 2 Select mode operation 9 bit UARTO by setting UARTCONO bits 6 and 7 11B Also select the 9th data bit to be transmitted by writing UARTCONO 3 8 to 0 or 1 3 Write transmission data to the shift register UDATAO E2H set 1 bank 1 to start the transmit operation Mode 3 Receive Procedure 1 Select the baud rate to be generated by setting BRDATAO 2 Select mode 3 and set the RE Receive Enable bit in the UARTCONO register to 1 3 The receive operation will be started when the signal at the RxDO pin goes to low level Hen n dI Write to Shift Register UARTDATA shit IL dL TxD start Bit X Di X 2 X X D4 X ps X 06 X D7 X TB8 Stop Bit TIP
62. ELECTRONICS 3 13 ADDRESSING MODES S3C84MB F84MB UM REV1 00 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO Z0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual The locations and read write characteristics of all mapped registers in the S3C84MB F84MB register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Bank 0 Registers Register Name Mnemonic Decimal Hex Timer control register TBCON 208 R W Timer B data register high byte TBDATAH 209 D1H R W Timer B data register low byte TBDATAL 210 D2H R W Basic timer control register BTCON 211 D3H R W Clock control regis
63. IBM PC AT or Compatible RS 232C USB Emulator SK 1200 or OPENIce i500 Target PROM OTP Writer Unit Application System RAM Break Display Unit Probe Adapter TB84MB EVA Figure 22 1 Development System Configuration 22 2 ELECTRONICS S3C84MB F84MB UM REV1 00 DEVELOPMENT TOOLS TB84MB TARGET BOARD The 84 target board is used for the S3C84MB F84MB microcontroller It is supported by the SMDS2 SMDS2 5 820 or SK 1000 development system TB84MB To User Vcc Idle Stop AQ RESET J101 J102 160 S3E84MO EVA Chip Jojoeuuo5 40 Pin Connector 40 Pin Connector External Triggers 1 SMDS2 SMDS2 JP4 Figure 22 2 TB84MB Target Board Configuration ELECTRONICS DEVELOPMENT TOOLS S3C84MB F84MB UM REV1 00 Table 22 1 Power Selection Settings for TB84MB To User Voc Operating Mode Comments Settings The ICE SK 1200 OPENICce supplies Vcc to the target board evaluation chip and To User Vcc the target system ZR SK 1200 OPENIce Vec supplies Vcc only to the target TB84MB board evaluation chip The To User Vcc target system must have its own power supply SK 1200 OPENIce Table 22 2 Emulator Version Selection Settings for TB84MB JP4 Settings Emulator Version m SK 1200 OPENIce 1500 SMDS2 Default Setting SMDS2 SMDS2 JP4 MM Go suos JP4 22 4 ELECTRONICS S3C84MB F84MB UM REV1 00 DEVELOPMENT TOOLS T
64. IR Examples Given R1 07H and register 07H OF1H COM R1 R1 COM 1 R1 OF8H 07H register 07H OEH In the first example the destination working register R1 contains the value 07H 00000111B The statement R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of the destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS 6 29 INSTRUCTION SET S3C84MB F84MB UM REV1 00 dst src Operation dst src Flags Format Examples The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Setif a borrow occurred src gt dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 A2 r r 6 r Ir opc src dst 3 6 A4 R R A5 R IR dst src 3 6 AG R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the and 5 flags The destination working register R1 contains the value 02H a
65. OOH 3FH registerO1H 37H OR 01H OOH gt Register OOH 08H register 01H OR 00H 02H gt Register OOH OAH In the first example if the working register RO contains the value 15H and the register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result 3FH in the destination register RO Other examples show the use of the logical OR instruction with various addressing modes and formats ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET POP Pop from Stack POP Operation Flags Format Examples dst dst SP SP lt SP 1 The contents of the location addressed by the stack pointer loaded into the destination The stack pointer is then incremented by one No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 8 51 IR Given Register 01H register 01H 1 SPH 0D8H SPL OD9H OFBH and stack register OFBH 55H POP 00H Register OOH 00H gt Register OOH 55H SP 00FCH 01H register 01H 55H SP 00FCH In the first example the general register 00H contains the value 01H The statement POP 00H loads the contents of the location OOFBH 55H into the destination register OOH and then increments the stack pointer by one The register OOH then contains the value 55H and the SP points to the location OOFCH ELECTRONICS 6 63 INSTR
66. Open drain mode 5 4 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Open drain mode ELECTRONICS S3C84MB F84MB UM REV1 00 P5CONL Port 5 Control Register Low Byte Bit Identifier RESET Value Read Write Addressing Mode 7 6 ELECTRONICS CONTROL REGISTERS F9H Set 1 Bank 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P5 3 RxDO 0 0 Input mode RxDO input Input mode pull up mode RxDO input 0 1 1 0 Push pull output 1 1 Alternative output mode RxDO output P5 2 TxDO 0 0 Input mode Input mode pull up mode 0 1 1 0 Push pull output 1 1 Alternative output mode TxDO output P5 1 RxD1 0 0 Input mode RxD1 input Input mode pull up mode RxD1 input 0 1 1 0 Push pull output 1 1 Alternative output mode RxD1 output P5 0 TxD1 0 0 Input mode Input mode pull up mode 0 1 1 0 Push pull output 1 1 Alternative output mode TxD1 output 4 29 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 P6CON Port 6 Control Register OFH 8 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0
67. P0 4 Input mode Input mode pull up Push pull output Alternative function mode PGOUT 7 4 Input mode Input mode pull up Push pull output Alternative function mode PGOUT 3 2 Input mode Input mode pull up Push pull output Alternative function mode PGOUTT 1 Input mode Input mode pull up Push pull output Alternative function mode PGOUT 0 Figure 9 1 Port 0 Control Register POCON 9 4 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS PORT 1 Port 1 is an 8 bit I O Port that you can use two ways General purpose I O Alternative function PWMO PWMs3 output Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H in set 1 bank 0 Port 1 Control Register P1CON Port 1 pins are configured individually by bit pair settings in one control registers located in set 1 bank 0 P1CON F1H When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Alternative function PWMO PWMS can be controlled in P1CONEX PORT1 Extension Control register ELECTRONICS 9 5 PORTS Port 1 Control Register P1 CON F1H Set 1 Bank 0 R W 5 4 3 2 1 7 1 6 1 5 1 4 P1 3 P1 2 P1 1 P1 0 7 6 bit P1 7 P1 6 S3C84MB F84MB UM REV1 00 Input mode Input mode pull up Push pull outpu
68. Program Mode Enable FMCON lt 01010000 Mode Select Write data at flash LDC RR n R data User Program Mode Disable YES Write again NO NO FMUSR lt 00 User Program Mode Disable 5 Check Sector YES Finish Writing Check Address YES INC R n 1 Increse Address YES R data New 8 bit Data Update Data Write Figure 18 9 Program Flowchart in a User Program Mode 18 12 ELECTRONICS S3C84MB F84MB UM REV1 00 EMBEDDED FLASH MEMORY INTERFACE d Programming Tip Programming Case1 1BYTE Programming WR BYTE Write data to flash memory address 4010H LD LD SB1 LD SBO PP 80H FMUSR 0A5H FMCON 01010001B FMSECH 40 FMSECL 00H R9 R10 40H R11 0H RR10 R9 FMCON 01010000B FMUSR 00 PP 0 User Program mode enable Programming mode enable Set flash sector address Set sector address of pointer to write data Load data to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Write data AAH at flash memory location 4010H Programming stop User Program mode disable Case2 Programming in the same sector WR INSECTOR LD WR BYTE LDC INC DJNZ SB1 LD SBO LD LD LD RO 40 PP 80H FMUSR 0A5H FMSECH 40 FMSECL 00H PP 0 FMCON
69. Read Write R W R W R W R W R W R W R W Addressing Mode addressing mode 7 Not Used 6 P6 6 ADC14 0 Open Drain Output 1 ADC14 5 P6 5 ADC13 0 Open Drain Output 1 ADC13 4 P6 4 ADC12 0 Open Drain Output 1 ADC12 3 P6 3 ADC11 0 Open Drain Output 1 ADC11 2 P6 2 ADC10 0 Open Drain Output 1 ADC10 P6 1 ADC9 0 Open Drain Output 1 ADC9 0 P6 0 ADC8 0 Open Drain Output 1 ADC8 4 30 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS P7CON Port 7 Control Register F5H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P7 7 ADC7 0 Input mode 1 ADC7 6 P7 6 ADC6 0 Input mode 1 ADC6 5 P7 5 ADC5 0 Input mode 1 ADC5 4 P7 4 ADC4 0 Input mode 1 ADC4 3 P7 3 ADC3 0 Input mode 1 ADC3 2 7 2 ADC2 0 Input mode 1 ADC2 4 P7 1 ADC1 0 Input mode 1 ADC 1 0 P7 0 ADCO 0 Input mode 1 ADCO ELECTRONICS 4 31 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 P8CONH Port 8 Control Register High Byte EDH Set 1 Bank 0 Bit Identifier 6 5 4 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode 7
70. S Setifthe result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Hex dst src 2 4 B2 6 B3 src dst 3 6 B4 5 dst src 3 6 B6 Addr Mode dst src r r r Ir R R R IR R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR XOR XOR XOR XOR RO R1 RO R1 00H 01H 00H 01H 00H 54H R1 02H RO 4 R1 02H register 02H 23H Register OOH 29H register 01H 02H Register OOH 08H register 01H 02H register 02H 23H Register OOH In the first example if the working register RO contains the value 0C7H and if the register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result in the destination register RO ELECTRONICS 6 87 S3C84MB F84MB UM REV1 00 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the S3C84MB F84MB by an external crystal can range from 1 MHz to 16 MHz The maximum CPU clock frequency is 16 MHz The Xn and Xour pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop
71. S3C84MB F84MB UM REV1 00 PROGRAMMING Programming PWMO to Sample Specifications Continued LD PWMCON 01 BTJRF dec R3 0 pwmoO inc ADD R1 48H JR NC pwmO data end INC RO JR NZ pwmO data end LD RO 4 amp OFFH LD R1 JR T pwmO data end pwmO dec SUB R1 44H JP NC pwm0_data_end SUB RO 01H JR NC pwm0_data_end CLR RO CLR R1 0 data end LD PWMOEX R1 LD PWMO RO 16 10 PS 0 Select 23 437 kHz PWM frequency Enable the PWM counter IF R8 0 0 then jump to pwmO dec If R3 0 1 then add 48H to the PWM data If no carry go to pwmO data end R0 RO 1 If no overflow jump to pwmO data end for update If overflow set OFFH to RO Set OFCH to R1 Jump to pwmO data end unconditionally R3 0 0 so subtract 44H from PWM data If no borrow jump to 0 data end for update Decrement RO RO RO 1 If no borrow jump to pwmO data end Clear data RO Clear data R1 Load new value to PWMOEX bits 2 7 Load new value to PWMO ELECTRONICS S3C84MB F84MB UM 1 00 PATTERN GENERATION MODULE PATTERN GENERATION MODULE OVERVIEW PATTERN GENERATION FLOW You can output up to 8 bit through 0 7 by tracing the following sequence First of all you have to change the PGDATA into what you want to output And then you have to set the PGCON to enable the pattern generation module and select the trigge
72. SP7 SPO is stored in the SPL register D9H After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C84MB F84MB the SPL must be initialized to an 8 bit value the range 00H FFH The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 00H ELECTRONICS 2 19 ADDRESS SPACES S3C84MB F84MB UM REV1 00 2 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP SPL 0FFH PP RPO 1 R3 R3 RPO SPL lt FFH Normally the SPL is set to OFFH by the initialization routine Stack address OFEH lt PP Stack address OFDH RPO Stack address OFCH
73. T1CK1 0 1 Input mode pull up T1CK1 1 x Push pull output 1 0 P3 0 T1CKO 0 0 Input mode T1CKO 0 1 Input mode pull up 1 1 X Push pull output ELECTRONICS 4 23 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 P4CONH Port 4 Control Register High Byte F6H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 4 24 Register addressing mode only P4 7 INT7 0 0 Input mode falling edge interrupt Input mode rising edge interrupt 0 1 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output P4 6 INT6 0 0 Input mode falling edge interrupt Input mode rising edge interrupt 0 1 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output P4 5 INT5 0 0 Input mode falling edge interrupt Input mode rising edge interrupt 0 1 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output P4 4 INT4 0 0 Input mode falling edge interrupt Input mode rising edge interrupt 0 1 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS
74. T4 6 5 4 3 2 0 Not P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 6 0 Used 6 bit P6 6 ADC14 0 Open Drain output 1 Alternative Function ADC14 5 bit P6 5 ADC13 0 Open Drain output 1 Alternative Function ADC13 4 bit P6 4 ADC12 0 Open Drain output 1 Alternative Function ADC12 3 bit P6 3 ADC11 0 Open Drain output 1 Alternative Function ADC1 1 2 bit P6 2 ADC10 0 Open Drain output 1 Alternative Function ADC10 1 bit P6 1 ADC9 0 Open Drain output 1 Alternative Function ADC9 0 bit P6 0 ADC8 0 Open Drain output 1 Alternative Function ADC8 Figure 9 14 Port 6 Control Register P6CON ELECTRONICS 9 21 PORTS S3C84MB F84MB UM REV1 00 PORT 7 Port 7 is an 8 bit Input port that you can use two ways General purpose Input Alternative function ADCO ADC7 input Port 7 is accessed directly by reading the port 7 data register P7 at location E7H in set 1 bank 0 Port 7 Control Register P7CON Port 7 pins are configured individually by bit pair settings in one control registers located in set 1 bank 1 P7CON When programming the port please remember that any alternative peripheral function you configure using the port 7 control registers must also be enabled in the associated peripheral module 9 22 ELECTRONICS S3C84MB F84MB UM REV1 00 ELECTRONICS Port 7 Control Register P
75. TBDATAL 11 6 ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 TIMER B PULSE WIDTH CALCULATIONS tiow 1 tLow To generate the above repeated waveform consisted of low period time ti ow and high period time When T FF 0 tiow TBDATAL 2 x 1 fx OH lt TBDATAL lt 100H where The selected clock TBDATAH 2 x 1 fx OH TBDATAH 100H where fx The selected clock When T FF 1 tiow TBDATAH 2 x 1 fx OH TBDATAH 100H where fx The selected clock TBDATAL 2 x 1 fx lt TBDATAL 100H where fx The selected clock To make 24 us and 15 us fosc 4 MHz fx 4 MHz 4 1 MHz When T FF 0 24 us TBDATAL 2 fx TBDATAL 2 x 106 TBDATAL 22 15 us TBDATAH 2 fx TBDATAH 2 1us TBDATAH 13 When T FF 1 15 us TBDATAL 2 TBDATAL 2 x 1us TBDATAL 13 24 us TBDATAH 2 fx TBDATAH 2 1us TBDATAH 22 ELECTRONICS 11 7 8 BIT A B C 0 1 S3C84MB F84MB UM REV1 00 Timer B Clock T FF 0 TBDATAL 01 00H FF TBDATAL 00H 01 FF BDATAL 00H 00H FF 1 BDATAL 00H 00H mer Clock FF E 1 DATAL DEH DATAH 1EH FF TBDATAL DEH 1EH
76. TT CONO T1CON1 to Select the timer 1 0 1 operating mode interval timer capture mode or PWM mode Select the timer 1 0 1 input clock frequency Clear the timer 1 0 1 counter T1CNTHO LO T1CNTH1 L1 Enable the timer 1 0 1 overflow interrupt Enable the timer 1 0 1 match capture interrupt T1CONO is located in set 1 and Bank 1 at address EAH and is read write addressable using Register addressing mode T1CON1 is located set 1 and Bank 1 at address and is read write addressable using Register addressing mode A reset clears T1 CONO T1CON1 to OOH This sets timer 1 0 1 to normal interval timer mode selects an input clock frequency of fx 1024 and disables all timer 1 0 1 interrupts To disable the counter operation please set T1CON 0 1 7 5 to 111B You can clear the timer 1 0 1 counter at any time during normal operation by writing a 1 to T1 CON 0 1 3 To generate the exact time interval you should write 1 to T1 CON 0 1 2 and clear appropriate pending bits of the TINTPND register To detect match capture or overflow interrupt pending condition when T1INTO T1INT1 or TTOVFO T1OVF1 is disabled the application program should poll the pending bit TINTPND register bank 0 E9H When a 1 is detected a timer 1 0 1 match capture or overflow interrupt is pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to t
77. Ta 25 C 2 All Output Pin except p is oe RESETB Vin 0 V Vpp 5 V 10 96 Port 0 8 TA 25 C 150 250 400 RESETB Rp2 Vin 0 V Vpp 3 V10 Port 0 8 TA 25 C 300 500 800 ELECTRONICS ELECTRICAL DATA S3C84MB F84MB UM REV1 00 Table 19 2 D C Electrical Characteristics Concluded Ta 40 C to 85 C Vpp 2 4 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit Supply current Vpp 4 5 V to 5 5 V 40 50 16 MHz Run mode PDT 2 4 V to 5 5 V gt 14 10 MHz mode mA Vpp 2 4 5 Vto 5 5 V 25 5 16 MHz Idle mode 0022 Voo 2 4 V to 5 5 V 3 10 MHz Idle mode Vpp 24Vto5 5V STOP mode LVR Enable an 24Vto55V I STOP mode LVR Disable 189 298 Vpp 2 4 V to 5 5 V uA Ipps STOP mode LVR Enable 100 200 IVC Disable Vpp 2 4 V to 5 5 V Ippe STOP mode LVR Disable 10 20 IVC Disable NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads ELECTRONICS S3C84MB F84MB UM REV1 00 ELECTRICAL DATA Table 19 3 A C Electrical Characteristics Ta 40 C to 85 C Vpp 2 4 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit aa vies T pi 0 8 Vpp V Toa Interrupt Input Low a _ 0 2 Vpp Te Interrupt Input Qum Vop 5 V 1096 180 ns RESET input low width Vpp 5 1 0
78. XL 4 14 B7 XL rr r dst 0000 DA 4 14 r DA 5 0000 DA 4 14 7 DA r opc dstjO0001 DA DA 4 14 AT r DA opc 0001 DA DA 4 14 B7 DA r 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 Forthe formats 3 and 4 the destination XS rr and the source address XS rr are both one byte 3 Forthe formats 5 and 6 the destination XL rr and the source address XL rr are both two bytes 4 The DA and the r source values for the formats 7 and 8 are used to address program memory The second set of values used in the formats 9 and 10 are used to address data memory 5 LDEinstruction can be used to read write the data of 64 Kbyte data memory 6 52 ELECTRONICS S3C84MB F84MB UM REV1 00 LDC LDE Load Memory INSTRUCTION SET LDC LDE Continued Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103 4FH 0104H 0105 6DH and 1104 88H External data memory locations 0103H 0104H 2 0105H 7DH and 1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H LDE RO RR2 RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H LDC RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 RO R2 R3 change LDE RR2 RO 11H conte
79. address which is located in the destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors user should load sector address to FMSECH and FMSECL Register according to the sector Refer to page 15 16 PROGRAMMING TIP Programming Flash Memory Sector Address Register High Byte FMSECH 12H Page 8 R W Flash Memory Sector Address Register Enable bit You have to input High address of sector thats accessed Figure 18 4 Flash Memory Sector Address Register FMSECH Flash Memory Sector Address Register Low Byte 13H Page 8 RW Flash Memory Sector Address Register Enable bit You have to input Low address of sector thats accessed Figure 18 5 Flash Memory Sector Address Register FMSECL ELECTRONICS 18 5 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode The only unit of flash memory to be erased and written in User Program Mode is called sector The program memory of SSF84MB 64Kbytes flash memory is divided into 512 sectors Every sector has all 128 byte sizes So the sector to be located destination address should be erased first to program a new data one byte into flash memory Minimum 10ms delay time for the
80. an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You can not however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and point to the upper slice see Figure 2 6 Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements 2 PROGRAMMING Setting the Register Pointers SRP 70H RPO 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange RP1 OF8H Register File Contains 32 8 Byte Slices 8 Byte Slice 16 Byte Contiguous 1 Ras block RPO Figure 2 7 Contiguous 16 Byte Working Register Block 2 10 ELECTRONICS S3C84MB F84MB UM REV1 00 CFH R15 8 Byte Slice C8H R8 Register File 16 Contains 32 Non Contiguous 8 Byte Slices Working Register block 8 B
81. an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received 14 12 ELECTRONICS S3C84MB F84MB UM REV1 00 UART 0 1 2 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 Set all S3C84MB F84MB devices masters and slaves to UART mode 2 or 3 Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 2 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3C84MB F84MB Interconnect TxD RxD TxD RxD TxD
82. and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3C series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C84MB F84MB microcontroller Also included in Part II are electrical mechanical Flash MCU and development tools data It has 16 chapters Chapter 7 Clock Circuit Chapter 15 10 bit A D Converter Chapter 8 RESET and Power Down Chapter 16 PWM Chapter 9 I O Ports Chapter 17 Pattern Generation Module Chapter 10 Basic Timer Chapter 18 Embedded Flash Memory Interface Chapter 11 8 bit Timer A B C 0 1 Chapter 19 Electrical Data Chapter 12 16 bit Timer 1 0 1 Chapter 20 Mechanical Data Chapter 13 Serial Port Chapter 21 S3F84MB Flash MCU Chapter 14 UART 0 1 Chapter 22 Development Tools S3C84MB F84MB_UM_REV1 00 MICROCONTROLLER Table of Contents Part Programming Model Chap
83. bit LSB of the destination or the source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst b 0 src 3 6 67 ro Rb src 1 dst 3 6 67 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bitin length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example the source register 01H contains the value 05H 00000101B and the destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register with the bit 0 value of the register R1 destination leaving the value 06H 00000110 in the register R1 ELECTRONICS 6 17 INSTRUCTION SET S3C84MB F84MB UM REV1 00 BCP Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared T
84. bit will be cleared automatically just after the corresponding operation completed In other words when S3F84MB is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase it will get the result of erasing selected sector as user s a purpose and Flash Operation Start Bit of FMCON register is also clear automatically 2 If user executes sector erase operation with FMUSR disabled 0 bit Flash Operation Start Bit remains high which means start operation and is not cleared even though next instruction is executed So user should be careful to set FMUSR when executing sector erase for no effect on other flash sectors ELECTRONICS 18 7 EMBEDDED FLASH MEMORY INTERFACE Programming Sector Erase Case1 Erase one sector LD PP 80h LD FMUSR 0A5H LD FMSECH 2 LD FMSECL 00H SB1 LD FMCON 10100001B SBO LD FMUSR 0 LD PP 0 S3C84MB F84MB UM REV1 00 User Program mode enable Set Sector 4 200H 27FH You can set FMSECL from 00H to 7FH Start sector erase User Program mode disable Case2 Erase flash memory space from Sector n to Sector n m Pre define the number of sector to erase LD PP 40 LD SecNumH 00H LD SecNumL 128 LD R6 01 LD R7 7DH LD R2 SecNumH LD R3 SecNumL ERASE LOOP CALL SECTOR ERASE XOR 4 11111111 INCW RR2 LD SecNumH R2 LD SecNumL R3 DECW RR6 LD R8 R6 OR R8
85. bit clear when write 0 1 Interrupt request is pending P4 4 INT4 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P4 3 INT3 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P4 2 INT2 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P4 1 INT1 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P4 0 INTO Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 27 CONTROL REGISTERS P5CONH Port 5 Control Register High Byte Bit Identifier RESET Value Read Write Addressing Mode 7 6 4 28 S3C84MB F84MB UM REV1 00 F8H Set 1 Bank 0 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only 5 7 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Open drain mode P5 6 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Open drain mode P5 5 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1
86. cycle is 400 ns If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time 10 clock 50 clocks 50 clock x 400 ns 20 us at fanc 22 5 MHz 1 clock time 1 fapc ADCON O lt 1 Conversion 50 ADC Clock Start ADDATA Previous Value ADDATAH 8 bit ADDATL 2 bit Setup Time 40 Clock 10 Clock Figure 15 4 A D Converter Timing Diagram 15 4 ELECTRONICS S3C84MB F84MB UM REV1 00 10 BIT A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 1 2 Analog input must remain between the voltage range of AVss and AVner Configure P7 0 P7 7 for analog input before A D conversions To do this you load the appropriate value to the P7CON for ADCO ADC14 register Before the conversion operation starts you must first select one of the eight input pins ADCO ADC14 by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Reference Voltage AVner Input S3C84MB F84MB ADCO ADC14 AVss Vss NOTE The symbol R1 signifies an offset
87. data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively An means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C84MB F84MB Set 1 Bank 0 Register Values after RESET Register Name Mnemonic Address Bit Values After RESET Dec Hex 7 6 5 4 3 2 1 0 Timer control register TBCON 208 DOH Timer B data register high byte TBDATAH 209 1 1 1 1 1 1 1 1 Timer B data register low byte TBDATAL 210 D2H 1 1 1 1 1 1 1 1 Basic timer control register BTCON 211 D3H Clock Control register CLKCON 242 DAH 0 System flags register FLAGS 213 D5H x X X X X x 0 0 Register pointer 0 RPO 214 D6H 1 1 0 00 Register pointer 1 RP1 215 D7H 1 1 010 1 Stack pointer high byte SPH 216 D8H x X X X X Stack pointer low byte SPL 217 D9H x X X X Instruction pointer high byte IPH 218 DAH x X X X X Instruction pointer low byte IPL 219 DBH x x X X x x Xx Interrupt request register IRQ 220 010 0 0 0 Interrupt mask register IMR 221 DDH x X Syst
88. full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Figure 2 9 16 Bit Register Pair 2 12 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES Special Purpose Registers General Purpose Register Control Registers System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset
89. high voltage Therefore 12 5V into Vpp TEST pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions in user program mode programming reading sector erase and one protection mode Hard lock protection ELECTRONICS 18 1 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store On Board Program Software Boot program code for upgrading application code by interfacing with I O port pin The ISP sectors can t be erased or programmed by LDC instruction for the safety of On Board Program Software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the tool program mode by serial programming tools The size of ISP sector can be varied by settings of smart option Refer to Figure 2 2 and Table 18 1 You can choose appropriate ISP sector size according to the size of On Board Program Software Internal Program Memory Flash 64 KByte 1FFh 2FFh 4FFh or 8FFh ISP Sector 100h Interrupt Vector Area 040h Smart Option Rom Cell 0
90. if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations have been performed it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero In operations that test register bits and in shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is cleared to O after a logic operation has been performed Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA in
91. information and programming examples for each instruction in the S3C8 series instruction set Information is arranged in a consistent format for improved readability and for quick reference The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Flag settings that may be affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3C84MB F84MB UM REV1 00 ADC Add with Carry ADC dst src Operation dst lt dst src c The source operand along with the carry flag setting is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction lets the carry value from the addition of low order operands be carried into the addition of high order operands Flags C Setifthere is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and t
92. mode Transmit receive mode Shift Start Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Txatrising edges Rx at falling edges SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting Auto clear bit SIO Shift Operation Enable Bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter SIO Interrupt Enable Bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO Interrupt Pending Bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS SIOPS sio Prescaler Register Set 1 Bank 1 Bit Identifier E 6 4 2 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 1 0 ELECTRONICS Register addressing mode only Baud rate Input clock 55 SIOPS 1 x2 or SCK input clock CONTROL REGISTERS S3C84MB F84MB UM REV1 00 SIOCON1 SIO1 Control Register 00H PAGE 8 Bit Identifier T 6 4 3 2 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode All addressing mode 7 SIO Shift Clock Selection Bit 0 Internal clock P S clock 1 External clock SCK1 6 Data Direction
93. or Selected RP points to start of working register block Program Memory 4 bit Working Register Address 5222 dst Register Next 2 bit Point Pair Roter uunc eee m m References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in OPERAND Instruction Sample Instructions LDC R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external me
94. p us Figure 19 1 Input Timing for External Interrupts Ports 4 Port 8 5 Port 8 6 Figure 19 2 Input Timing for RESET ELECTRONICS 19 5 ELECTRICAL DATA S3C84MB F84MB UM REV1 00 Table 19 4 Input Output Capacitance Ta 40 C to 85 C Vpp 20 V Parameter Symbol Conditions Min Typ Max Unit Input capacit pacitance Output f 1 ra pins B _ 10 pF capacitance gur I O capacitance Cio Table 19 5 Data Retention Supply Voltage in Stop Mode Ta 40 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage Vpppr Stop mode 2 4 5 5 V Data retention supply current IpppR Stop mode Vpppr 24V 8 uA NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads Oscillation Stabilization Time Y Stop Mode 4 idle Mode Data Retention Mode of Operating Modt STOP Instruction Interrupt twait is the same as 4096 x 16 x BT clock Figure 19 3 Stop Mode Release Timing Initiated by Interrupts 19 6 ELECTRONICS S3C84MB F84MB UM REV1 00 Table 19 6 A D Converter Electrical Characteristics Ta 40 C to 85 C 2 4 V to 5 5 V Vss 0 V ELECTRICAL DATA
95. pending bit when write 1 Interrupt pending CONTROL REGISTERS TINTPND rimer A 1 Interrupt Pending Register S3C84MB F84MB UM REV1 00 E9H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C84MB F84MB 5 Timer 1 1 Overflow Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit No interrupt pending Clear pending bit when write 1 Interrupt pending 3 Timer 1 0 Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write 1 Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 1 Timer A Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write 1 Interrupt pending 0 Timer Match Capture Interrupt Pending Bit No interrupt pending Clear pending bit when write 1 Interrupt pending 4 52 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTER UARTCONO uanro Contro
96. pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation Interrupt is disabled watchdog function basic timer is enabled Ports 0 8 are set to input mode Port 6 is set to open drain output Peripheral control and data registers are disabled and reset to their default hardware values program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the Test pin is tied to Vss A reset enables access to the 64 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET POWER DOWN HARDWARE RESET VALUES S3C84MB F84MB UM REV1 00 Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral
97. program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows an example of how to use an ENTER statement Before After Address Data Address Data Address Address 0040 Ent r 0110 40 Enter Address H 41 Address H Address L 42 Address L 0022 Address H 0020 43 Address 110 20 IPH 00 21 IPL 50 22 22 Data Stack ELECTRONICS 6 41 INSTRUCTION SET S3C84MB F84MB UM REV1 00 EXIT exit EXIT Operation IP 5 lt 5 2 IP IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex 1 16 2 The diagram below shows an example of how to use EXIT statement Before After Address Data Address Data IP 0050 IP 0043 Address Data Address Data PC PC 0110 50 PCL old 60 Main 51 0022 Memory
98. rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 PC jumps to SKIP location If the working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3C84MB F84MB UM REV1 00 BTJRT sit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1 then lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC Otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst src opc src 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 00000111 the sta
99. register file ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET SBC subtract with Carry SBC Operation Flags Format Examples dst src dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Set if a borrow occurred src gt dst cleared otherwise Set if the result is 0 cleared otherwise Z S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Always set to 1 T Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 32 r r 6 33 r Ir opc src dst 3 6 34 R R 6 35 R IR opc dst src 3 6 36 R IM Given R1 10H R2 C 1 register 01H 20H register 02H and r
100. the example the working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements the register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3C84MB F84MB UM REV1 00 El Enable Interrupts Operation Flags Format Example SYM 0 1 The El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have the highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when the EI instruction is executed No flags are affected Bytes Cycles Opcode Hex 1 4 9F Given SYM 00H If the SYM register contains the value 00H that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts SYM O is the enable bit for global interrupt processing ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET ENTER Enter ENTER Operation SP SP 2 lt IP lt lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The
101. the first example the destination working register R1 has the value 07H 00000111B and the source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of the register 01H the source with bit zero of R1 the destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of the source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3C84MB F84MB UM REV1 00 CALL Call Procedure CALL Operation Flags Format Examples dst SP 5 1 5 lt PCL SP lt SP 1 SP lt PCH PC lt dst The contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations OOOOH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000
102. the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects or RP1 Address These address 1 working register address addressing Register pointer Three low order bits provides five high order bits 8 bit physical address Figure 2 14 8 Bit Working Register Addressing ELECTRONICS 2 17 ADDRESS SPACES S3C84MB F84MB UM REV1 00 RPO Selects RP1 R11 1 8 bit address Register 1100 011 form instruction 10101 0 1 1 address LD R11 R2 Specifies working register addressing Figure 2 15 8 Bit Working Register Addressing Example 2 18 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES SYSTEM AND USER STACK The S3C8 series microco
103. 0 Bit Identifier 7 6 5 4 3 2 41 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 TCOUT1 0 0 Input mode Input mode pull up 0 1 1 0 Push pull output 1 1 Alternative output mode TCOUT 1 5 4 P3 6 TCOUTO 0 0 Input mode Input mode pull up 0 1 1 0 Push pull output 1 1 Alternative output mode TCOUTO 3 2 5 T10UT1 0 0 Input mode Input mode pull up 0 1 1 0 Push pull output 1 1 Alternative output mode T1OUT1 1 0 P3 4 T10UTO 0 0 Input mode Input mode pull up 0 1 1 0 Push pull output 1 1 Alternative output mode T1OUTO 4 22 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS P3CONL Port 3 Control Register Low Byte F5H Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 T1CAP1 0 0 Input mode T1CAP1 0 1 Input mode pull up T1CAP1 1 x Push pull output 5 4 P3 2 T1CAPO 0 0 Input mode T1CAPO 0 1 Input mode pull up T1CAPO 1 x Push pull output 3 3 P3 1 T1CK1 0 0 Input mode
104. 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 Register addressing mode only Timer B Input Clock Selection Bits 0 O fxx 0 1 fyy 2 1 0 fxx 4 1 1 fo 8 Timer B Interrupt Time Selection Bits 0 O Elapsed time for low data value 0 1 Elapsed time for high data value 1 0 Elapsed time for low and high data values 1 1 Invalid setting Timer B Interrupt Enable Bit 0 Disable Interrupt 1 Enable Interrupt Timer B Start Stop Bit 0 Stop timer B 1 Start timer B Timer B Mode Selection Bit 0 One shot mode 1 Repeating mode Timer B Output flip flop Control Bit 0 T FF is low 1 T FF is high NOTE fx x is selected clock for system ELECTRONICS 4 49 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 TCCONO rimer C 0 Control Register F2H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Not used for the S3C84MB F84MB must keep always 0 6 4 Timer 3 bits Prescaler Bits 0 0 0 Non devided 0 0 1 Divided by 2 0 1 0 Divided by 3 0 1 1 Divided by 4 1 0 0 Divided by 5 1 0 1 Divided 1 1 0 Divided by 7 1 1
105. 00H contains the value 55H 01010101B the statement rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in the destination register OOH The sign flag and the overflow flag are both cleared to 0 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting the bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3C84MB F84MB UM REV1 00 SB1 Select Bank 1 SB1 Operation Flags Format Example BANK lt 1 The 581 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers No flags are affected Bytes Cycles Opcode Hex 1 4 5F The statement SB1 sets FLAGS 0 to 1 selecting the bank 1 register addressing if bank 1 is implemented in the microcontroller s internla
106. 1 Divided by 8 3 Timer C Counter Clear Bit 0 No effect 1 Clear the timer C 0 counter Auto clear bit 2 Timer C Mode Selection Bit 0 fxy 1 8 PWM mode 1 fxx 64 amp interval mode 1 Timer C Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 0 Timer C Pending Bit 0 No interrupt pending 0 Clear pending bit when write 1 Interrupt pending 4 50 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTER TCCON1 Timer C 1 Control Register F3H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 4 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode ELECTRONICS Register addressing mode only Not used for the S3C84MB F84MB must keep always 0 Timer C 3 bits Prescaler Bits 0 0 O Non devided 0 0 1 Divided by 2 0 1 0 Divided by 3 0 1 1 Divided by 4 1 0 0 Divided by 5 1 0 1 Divided 1 1 0 Divided by 7 1 1 1 Divided by 8 Timer C Counter Clear Bit 0 No effect 1 Clear the timer C 1 counter Auto clear bit Timer C Mode Selection Bit 0 fyx 1 amp PWM mode 1 fo 64 amp interval mode Timer C Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Timer C Pending Bit 0 No interrupt pending 0 Clear
107. 1 Push pull output 5 4 bit P3 2 T1 CAPO Input mode T1CAP0 Input mode pull up T1CAPO Push pull output 3 2 bit P3 1 T1CK1 Input mode T1CK1 Input mode pull up T1CK1 Push pull output 1 0 bit P3 0 T1 CKO Input mode T1CKO Input mode pull up T1CKO Push pull output Figure 9 7 Port 3 Low Byte Control Register P3CONL ELECTRONICS 9 13 l O PORTS S3C84MB F84MB UM REV1 00 PORT 4 Port 4 is an 8 bit I O Port that you can use two ways General purpose I O External interrupt inputs for INTO INT7 Port 4 is accessed directly by writing or reading the port 4 data register P4 at location E4H in set 1 bank 0 Port 4 Control Register P4CONH P4CONL Port 4 pins are configured individually by bit pair settings in two control registers located in set 1 bank 0 PACONL low byte F7H and PACONH high byte F6H When you select output mode a push pull circuit is configured In input mode three different selections are available Schmitt trigger input with interrupt generation on falling signal edges Schmitt trigger input with interrupt generation on rising signal edges Schmitt trigger input with pull up resistor and interrupt generation on falling signal edges Port 4 Interrupt Enable and Pending Registers PAINT P4INTPND To process external interrupts at the port 4 pins two additional control registers are provided the port 4 interrupt enable register PAINT set 1 bank 0 and
108. 1 Control Register TT CONO 1 12 2 Timer A and Timer 1 0 1 Pending Register TINTPND 12 3 Timer 1 0 1 Functional Block 13 1 SIO Module Control Register 1 13 2 SIO Prescaler Register 13 3 SIO Functional Block Diagram sse 13 4 SIO Timing Transmit Receive Mode Tx at falling edge SIOCON 4 0 13 5 SIO Timing in Transmit Receive Mode Tx at rising edge SIOCON 4 1 13 6 SIO Timing in Receive Only Mode Rising edge start 14 1 UART Control Register UARTCONO UARTCON1 UARTCON2 14 2 UART Interrupt Pending Register 14 3 UART Parity Register ttn nente tne deinen 14 4 UART Data Register UDATAO UDATA1 2 14 5 UART Baud Rate Data Register BRDATAO BRDATA1 BRDATA2 14 6 UART Functional Block Diagram eene 14 7 Timing Diagram for UART Mode 0 Operation 14 8 Timing Diagram for UART Mode 1 14 9 Timing Diagram for UART Mode 2 14 10 Connection Example for Multiprocessor Serial Data Communications 15 1 A D Converter Control Register
109. 1 R1 IM r1 Irr2 xL E B CLR CLR XOR XOR XOR XOR XOR LDC R1 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 1 Ir r2 RA r1 Irr2 RR2 RR1 IRZ RR1 RR1 IML r1 Ir2 H D SRA SRA CPIJNE LDC CALL LD LD R1 IR 1 Irr r2 RA 2 1 1 IR1 IM Ir1 r2 E E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs X F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 2 1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET Table 6 5 OPCODE Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX 8 9 B C D E F U 0 LD LD DJNZ JR LD JP INC NEXT r1 R2 r2 R1 r1 RA 1 cc DA r1 P 1 1 1 i ENTER P 2 EXIT E 3 WFI R 4 SBO 5 SB1 N 6 IDLE 7 J STOP B 8 DI B 9 El L A RET E B IRET C RCF H D i j sc E E CCF X F LD LD DJNZ JR LD JP INC NOP r1 R2 r2 R1 r1 RA 1 cc DA r1 ELECTRONICS 6 11 INSTRUCTION SET S3C84MB F84MB UM REV1 00 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if
110. 131 NTO P4 0 38 ADC7 P7 7 39 ADC6 P7 6 140 Figure 21 1 S3F84MB Pin Assignments 80 QFP 21 2 ELECTRONICS S3C84MB F84MB UM REV1 00 TACK P2 5 TBPWM P2 4 P2 3 5 2 2 510 2 1 500 2 0 P5 7 SDAT P5 6 SCLK P5 5 VDD1 VSS1 RxDO0 P5 3 RESETB 5 2 RxD1 P5 1 TxD1 P5 0 ELECTRONICS S3F84MB FLASH MEMORY MCU L Od LOd LLd eaxg L 8d LOS 08 61 924 4 1 651 lt 1 1 841 00d 05Dd 9261 SL 04 694 VLL vOd vOd 4 L3 404694 eL L3 904994 ILL 70 0 1 014 0 1 9 1 084 18 S3C84MB F84MB 80 1212 NT0 P4 0 136 NT2 P42 L 34 ADC7P77 C 37 TCOUT1 P3 7 C 21 TCOUTO P3 6 122 T1OUT1 P35 C4 23 T1OUTO P34 24 T1CAP1P3 3 C 25 T1CAP0P3 2 C 26 T1CK1 P3 1 T1CK0 P3 0 28 NT7 PA7 129 6 6 30 C4 31 4 44 32 33 NT1 P4 1 ADC6 P7 6 L 38 ADC5 P7 5 139 ADC4 P7 4 40 Figure 21 2 S3F84MB Pin Assignments 80 P8 2 SCK1 P8 3 P8 4 INT8 P8 5 INT9 P6 0 ADC8 P6 1 ADC9 P6 2 ADC10 P6 3 ADC11 P6 4 ADC12 VDD2 VSS2 P6 5 ADC13 P6 6 ADC14 P6 7 P7 0 ADCO P7 1 ADC1 P7 2 ADC2 P7 3 ADC3 AVSS AVREF 21 3 S3F84MB FLASH MEMORY MCU S3C84MB F84MB UM REV1 00 Table 21 1 Descriptions of Pins Used to Read Write the Flash ROM 10 11 Main Chip During Programming Pin pin Name To Function Seria
111. 2 and register 03H 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3C84MB F84MB UM REV1 00 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 PC lt PC Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst RA 3 12 D2 r Ir Given R1 02H R2 and
112. 26 E2H 1 1 1 1 1 1 1 1 UARTO control register UARTCONO 227 0 0 0 UARTO baud rate data register BRDATAO 228 E4H 1 1 1 1 1 1 1 1 UARTO 1 pending register UARTPND 229 ESH 0 0 0 0 Timer 1 0 data register high byte T1DATAHO 230 E6H 1 1 1 1 1 1 1 1 Timer 1 0 data register low byte TIDATALO 231 E7H 1 1 1 1 1 1 1 1 Timer 1 1 data register high byte TIDATAH1 232 E8H 1 1 1 1 1 1 1 1 Timer 1 1 data register low byte T1DATAL1 233 E9H 1 1 1 1 1 1 1 1 Timer 1 0 control register T1CONO 234 FAH 0 0 0 0 0 0 Timer 1 1 control register T1CON1 235 EBH 0 Timer 1 0 counter register high byte TICNTHO 236 0 0 0 0 0 0 Timer 1 0 counter register low byte T1CNTLO 237 EDH 0 0 Timer 1 1 counter register high byte T1CNTH1 238 EEH 0 0 0 Timer 1 1 counter register low byte T1CNTL1 239 EFH 0 Timer 0 data register TCDATAO 240 1 1 1 1 1 1 1 1 Timer C 1 data register TCDATA1 241 FiH 1 1 1 1 1 1 1 1 Timer C 0 control register TCCONO 242 FH 0 10 10 1010 Timer 1 control register 1 243 0 SIO prescaler control register SIOPS 244 F4H O 010 010 Port 7 control register P7CON 245 FH 0 0 0 Location F6H is not mapped A D converter control register ADCON 247 FH 010 0 A D converter data reg
113. 3Ch Figure 18 1 Program Memory Address Space NOTE User can select suitable ISP protection size by 3EH 1 and 0 If ISP Protection Enable Disable Bit SEH 2 is 1 3EH 1 and 0 are meaningless 18 2 ELECTRONICS S3C84MB F84MB UM REV1 00 EMBEDDED FLASH MEMORY INTERFACE Table 18 1 ISP Sector Size Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 2 Bit 1 Bit 0 1 X X 0 0 0 0 0 100H 1FFH 256 Bytes 256 Bytes 0 0 1 100H 2FFH 512 Bytes 512 Bytes 0 1 0 100H 4FFH 1024 Bytes 1024 Bytes 0 1 1 100H 8FFH 2048 Bytes 2048 Bytes NOTE The area of the ISP sector selected by smart option bit 2 3EH 0 can t be erased and programmed by LDC instruction in user program mode ELECTRONICS 18 3 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 FLASH MEMORY CONTROL REGISTERS FLASH MEMORY CONTROL REGISTER FMCON register is available only in user program mode to program some data to the flash memory Flash Memory Control Register FMCON FDH Set 1 Bank 1 R W Flash Memory Mode Selection Bits Not Used sl Flash Operation Start Bit INT Enable Bit 0 Operation stop During Sector Erase 1 Operation start 0 Interrupt Disable This bit will be cleared automatically 1 Interrupt Enable just after the corresponding operation completed Programing mode Erase mode Hard lock mode Not used Setocr Era
114. 4 3 2 4 32 Register addressing mode only Not used for the S3C84MB F84MB P8 5 INT9 0 0 Input mode falling edge interrupt 0 1 Input mode rising edge interrupt 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output P8 4 INT8 0 0 Input mode falling edge interrupt 0 1 Input mode rising edge interrupt 1 0 Input mode pull up falling edge interrupt 1 1 Push pull output ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS P8CONL Ports Control Register Low Byte EEH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELECTRONICS Register addressing mode only P8 3 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Not Used P8 2 0 0 Input mode SCK1 Input 0 1 Input mode pull up SCK1 Input 1 0 Push pull output 1 1 SCK1 Output P8 1 0 0 Input mode 511 0 1 Input mode pull up 1 0 Push pull output 1 1 Not Used P8 0 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 501 4 33 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 P8INTPND Ports Interrupt Pending Register EFH Set 1 Bank 0 Bit I
115. 5 1 20 NOTE Dimensions are in millimeters Figure 20 2 S3C84MB F84MB 80 TQFP Standard Package Dimension in Millimeters 20 2 ELECTRONICS S3C84MB F84MB UM REV1 00 S3F84MB FLASH MEMORY MCU 2 1 S3F84MB FLASH MCU OVERVIEW The SSF84MB single chip CMOS microcontroller is the Flash MCU It has an on chip Flash MCU ROM The Flash ROM is accessed by serial data format NOTE This chapter is about the Tool Program Mode of Flash MCU If you want to know the User Program Mode refer to the Chapter 18 Embedded Flash Memory Interface ELECTRONICS 21 1 S3F84MB FLASH MEMORY MCU S3C84MB F84MB UM REV1 00 L O0d I9d LEd eaxg 0871 004 094 8461 LLL 9 1 vOd vOd GZE0 SO0d SOd VLL 904 994 2 104 204 2211 89 1 VvLd ONMd L9L3 99 41 99 1 Zld eNMd TAOUT P2 7 P8 0 SO1 TACAP P2 6 8 1 511 2 5 P8 2 SCK1 TBPWM P2 4 P8 3 P2 3 P8 4 INT8 5 2 2 P8 5 INT9 SIO P2 1 P6 0 ADC8 SOO0 P2 0 P6 1 ADC9 P5 7 P6 2 ADC10 SDAT P5 6 P6 3 ADC11 SCLK P5 5 S3C84MB F84MB P6 4 ADC12 VDD1 VDD2 VSS1 80 QFP 1420C vss2 Xour P6 5 ADC13 XIN P6 6 ADC14 5 7 5 4 P7 0 ADCO RxDO0 P5 3 P7 1 ADC1 RESETB P7 2 ADC2 TxDO0 P5 2 P7 3 ADC3 RxD1 P5 1 AVSS TxD1 P5 0 AVREF TCOUT1 P3 7 P7 4 ADC4 TCOUTO P3 6 P7 5 ADC5 T1OUT1 P35 CJ 25 T1OUTO P34 7 26 T1CAP1 P33 CJ 27 T1CAPO P32 CJ 28 T1CK1 P3 1 T1CKO P3 0 130 NT7 P4 7
116. 7CON Set 1 Bank 1 R W o P7 7 7 6 7 5 P7 4 P7 3 7 2 P7 1 7 0 ADC7ADC6ADCS5ADCA4ADCSADC2ADC1ADCO bit P7 7 ADC7 0 Input mode 1 ADC input mode 6 bit P7 6 ADC6 0 Input mode 1 ADC input mode 5 bit P7 5 ADC5 0 Input mode 1 ADC input mode 4 bit P7 4 ADC4 0 Input mode 1 ADC input mode 3 bit P7 3 ADC3 0 Input mode 1 ADC input mode 2 bit P7 2 ADC2 0 Input mode 1 ADC input mode 1 bit P7 1 ADC1 0 Input mode 1 ADC input mode 0 bit P7 0 ADCO 0 Input mode 1 ADC input mode Figure 9 15 Port 7 Control Register P7CON PORTS 9 23 l O PORTS S3C84MB F84MB UM REV1 00 PORT 8 Port 8 is an 6 bit I O Port that you can use three ways General purpose I O Alternative function SCK1 511 SO1 External interrupt inputs for INT8 INT9 Port 8 is accessed directly by writing or reading the port 8 data register P8 at location E8H set 1 bank 0 Port 8 Control Register PBCONH P8CONL Port 8 pins are configured individually by bit pair settings in two control registers located in set 1 bank 0 P8CONL low byte EEH and P8CONH high byte EDH When you select output mode a push pull circuit is configured In input mode three different selections are available Schmitt trigger input with interrupt generation on falling signal edges Schmitt trigger input with interrupt generation on rising signal edges
117. 84MB F84MB UM REV1 00 DIV pivide Unsigned DIV Operation Flags Format Examples dst src dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers C Set if the V flag is set and the quotient is between 28 and 29 1 cleared otherwise 2 Set if the divisor or the quotient 0 cleared otherwise S Set if MSB of the quotient 1 cleared otherwise V Setif the quotient is gt 28 or if the divisor 0 cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 29 cycles Given RO 10H R1 03H R2 40H register 40H 80H DIVRRO R2 gt RO R1 40H DIVRRO R2 RO 03H R1 20H DIVRRO 20H RO 03H R1 80H In the first example the destination working register pair RRO contains the values 10H RO and R1 and the register R2 contains the value 40H The s
118. B 3 Set Flash Memory User Programming Enable Register FMUSR 00000000B 55 PROGRAMMING Hard Lock Protection LD PP 80H LD FMUSR 0A5H User Program mode enable SB1 LD FMCON 01100001B Hard Lock mode set amp start SBO LD FMUSR 0 User Program mode disable LD PP 40 18 16 ELECTRONICS S3C84MB F84MB UM REV1 00 OVERVIEW In this chapter 53084 84 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics A C electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode A D converter electrical characteristics ELECTRONICS ELECTRICAL DATA ELECTRICAL DATA ELECTRICAL DATA Table 19 1 Absolute Maximum Ratings S3C84MB F84MB UM REV1 00 25 Parameter Symbol Conditions Rating Unit Supply voltage Vpp 0 3 to 6 5 Input voltage Vi 0 3 to Vpp 0 3 V Output voltage Vo 0 3 to Vpp 0 3 Output current high lou One I O pin active 15 All I O pins active 60 m Output current low lo One I O pin active 30 Total pin current for port 200 Operating temperature TA 40 to 85 Storage temperature 65 to 150 Table 19 2 D C Electrical Characteristics TA2
119. Control Bit 0 MSB first mode 1 LSB first mode 5 SIO1 Mode Selection Bit 0 Receive only mode 1 Transmit receive mode 4 Shift Start Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Txatrising edges Rx at falling edges 3 5101 Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting Auto clear bit 2 5101 Shift Operation Enable Bit O Disable shifter and clock counter 1 Enable shifter and clock counter 5101 Interrupt Enable Bit 0 Disable SIO1 interrupt 1 Enable SIO1 interrupt 0 5101 Interrupt Pending Bit 0 Nointerrupt pending 0 Clear pending condition when write 1 Interrupt is pending 4 42 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS SIOPS 1 sio Prescaler Register 01H PAGE 8 Bit Identifier E 6 5 4 3 2 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W RAN R W R W R W R W R W Addressing Mode All addressing mode 7 0 Baud rate Input clock 5o SIOPS1 1 x2 or SCK1 input clock SPH stack Pointer High Byte D8H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value X x X x x Xx Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 0 ELECTRONICS Register addressing mode only Sta
120. D FMCON 01010000B SBO LD PP 80H 18 14 User Program mode enable Set sector address located in target address to write data SECTOR2 sector base address 100H Programming mode enable Load data to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Set sector address located in target address to write data SECTORBO sector base address 1900H Load data 55H to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Set sector address located in target address to write data SECTOR128 sector base address 4000H Load data to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Write data at flash memory location Programming stop ELECTRONICS S3C84MB F84MB UM REV1 00 EMBEDDED FLASH MEMORY INTERFACE LD FMUSR 00 User Program mode disable LD PP 0 WR BYTE LDC RRI1O0 R9 Write data written by R9 at flash memory location INC R11 DJNZ RO RET READING The read operation starts by LDC instruction The program procedure in user program mode 1 Load a flash m
121. Data Value Baud rate Input clock fxx SIOPS 1 x 2 or SCLK input clock Figure 13 2 SIO Prescaler Register SIOPS BLOCK DIAGRAM Pending SIO INT 3 Bit Counter SIOCON O IRQ4 Clear SIOCON 1 SIOCON 7 SIOCON 3 Interrupt Enable Shift Clock Source Select SIOCON 4 Shift Clock SIOCON 2 Edge Select hift Enabl PTE Shift Enable Mode Select SIOPS U Bit SIO Shift Buffer SIODATA F SO P2 0 SIOCON 6 LSB MSB First Mode Select Prescaled Value 1 SIOPS 1 Data BUS Figure 13 3 SIO Functional Block Diagram ELECTRONICS 13 3 SERIAL I O PORT SERIAL I O TIMING DIAGRAMS Shift Clock Sl Data Input S3C84MB F84MB UM REV1 00 SO Data Output Figure 13 4 SIO Timing in Transmit Receive Mode Tx at falling edge SIOCON 4 0 Shift Clock SI Data Input SO Data Output Figure 13 5 SIO Timing in Transmit Receive Mode Tx at rising edge SIOCON 4 1 Transmit Complete 2111111111111 Transmit Complete ELECTRONICS S3C84MB F84MB UM REV1 00 SET SIOCON 3 SERIAL PORT Transmit Complete Figure 13 6 SIO Timing in Receive Only Mode Rising edge start 7 PROGRAMMING TIP Use Internal Clock to Transmit and Receive Serial Data 1 The method that uses interrupt is used DI LD P2CONL 03 LD IMR 40001000006 SB1 LD SIODATA TDATA LD SIOPS 90H LD SIOCON 2 SBO EI SIOINT PUSH
122. E S3C84MB F84MB UM REV1 00 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM O to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate 5 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit Not used for the S3C84MB F84MB 0 Disable all interrupts processing must keep 0 1 Enable all interrupts processing Fast interrupt level bits Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing 0000 Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bi
123. ELECTRONICS USER S MANUAL S3C84MB F84MB 8 BIT CMOS MICROCONTROLLERS January 2009 REV 1 00 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2009 Samsung Electronics Inc All Rights Reserved Important Notice Information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C84MB F84MB 8 Bit CMOS Microcontrollers User s Manual Revision 1 00 Publication Number 21 53 84 84 012009 Copyright 2006 2009 Samsung Electronics Co Ltd Typical param
124. H 20H register 02H 02H LOOP 30H and register OFFH LD RO 10H LD RO 01H LD 01H RO LD R1 RO LD RO R1 LD 00H 01H LD 02H 00H LD 00H O0AH LD 00H 10H LD 00H 02H LD RO LOOP R1 LD 4LOOP RO R1 14 10 RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register 00H 01H Register OOH OAH Register OOH 01H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 0AH Register 31H OAH RO 01H R1 OAH ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src 4610 src b or dst b lt 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 47 ro Rb src b 1 dst 3 6 47 Rb ro NOTE In the second byte of the instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and gener
125. H occurs when UARTCONO 1 is set to 1 Write to Shift Register UDATA Shift RxD Data Out DO D1 D2 D3 D4 D5 D6 D7 Write to UARTPND Clear RIP and set RE Transmit Shift RxD Data In DO H D1 D2 H D3 H D4 H D5 H D6 H D7 TxD Shift Clock Figure 14 7 Timing Diagram for UART Mode 0 Operation 14 8 ELECTRONICS S3C84MB F84MB UM REV1 00 UART 0 1 2 UARTO MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxDO pin or received through the RxDO pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCONO register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by setting BRDATAO 2 Select mode 1 8 bit UARTO by setting UARTCONO bits 7 and 6 to 01B 3 Write transmission data to the shift register UDATAO E2H set 1 bank 1 The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by setting BRDATAO 2 Select mode 1 and set the RE Receive Enable bit in the UARTCONO register to 1 3 The start bit low 0 condition at the RxDO P5 3 pin will cause the UARTO module to start the serial data receive operation Tx Clock Write to Shift Register UDATA IL
126. HO LO T1CNTH1 L1 16 bit comparator and two 16 bit reference data register T1DATAHO LO T1DATAH1 L1 I O pins for capture input T1 CAPO T1CAP1 or match output T1OUTO T1OUT1 Timer 1 0 overflow interrupt IRQ3 vector C2H and match capture interrupt IRQ3 vector COH generation Timer 1 1 overflow interrupt IRQ3 vector C6H and match capture interrupt IRQ3 vector C4H generation Timer 1 0 control register T1 CONO set 1 EAH Bank 1 read write Timer 1 1 control register T1CON1 set 1 EBH Bank 1 read write ELECTRONICS 12 1 16 1 0 1 S3C84MB F84MB UM REV1 00 FUNCTION DESCRIPTION Timer 1 0 1 Interrupts IRQ3 Vectors C2H and The timer 1 0 module can generate two interrupts the timer 1 0 overflow interrupt T1OVFO and the timer 1 0 match capture interrupt 11 T1OVFO is interrupt level vector 2 T1INTO also belongs to interrupt level IRQ3 but is assigned the separate vector address COH A timer 1 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 0 match capture interrupt T1INTO pending condition is also cleared by hardware when it has been serviced The timer 1 1 module can generate two interrupts the timer 1 1 overflow interrupt T1OVF1 and the timer 1 1 match capture interrupt T1INT1 T1OVF1 is interrupt level vector C6H also belongs to interrupt
127. M or match output TAPWM TAOUT Timer A overflow interrupt IRQO vector and match capture interrupt IRQO vector B8H generation Timer A control register TACON set 1 bank0 EAH read write ELECTRONICS 11 1 8 BIT A B C 0 1 S3C84MB F84MB UM REV1 00 FUNCTION DESCRIPTION Timer Interrupts IRQO Vectors BBH and BAH The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQO vector TAINT also belongs to interrupt level IRQO but is assigned the separate vector address B8H A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQO and is assigned the separate vector address B8H When timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register TADATA The match signal generates a timer A match interrupt TAINT vector B8H and clears the counter If for examp
128. MB UM REV1 00 BTCON Basic Timer Control Register D3H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset 1 0 1 0 Disable watchdog timer function Others Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits 0 0 fxx 4096 0 1 fxx 1024 1 0 fyy 128 1 1 1 16 Not used 1 Basic Timer Counter Clear Bit 0 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 0 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to 0 the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to 0 3 The fyx is selected clock for system main OSC or sub OSC 4 8 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS System Clock Control Register D4H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Va
129. MO P1 2 P1 0 TxD2 P0 6 PG6 P0 4 PG4 P0 2 PG2 P0 0 PGO Figure 22 3 40 Pin Connectors for TB84MB S3C84MB F84MB 80 QFP Package 52 I 5 9 7 5 5 Q Q Target Board J102 Target Cable for 40 Pin Connector Part Name AS40D A Order Code SM6306 Target System J102 J101 41 421 1 79 80 39 40 Figure 22 4 TB84MB Cable for 80 Adapter 40 Pin DIP Connectors ELECTRONICS S3C84MB F84MB UM REV1 00 22 2 Third parties for development tools DEVELOPMENT TOOLS SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer In Circuit Emulator for 5 8 family 500 SmartKit SK 1200 OTP MTP Programmer SPW uni AS pro US pro BlueChips Combi GW PRO2 8 gang programmer Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice 1500 it System e TEL 82 31 223 661 1 e FAX 82 331 223 6613 e E mail openice aijisystem com e URL http www aijisystem com SK 1200 Seminix TEL
130. P3 0 P3 3 1 TTCAPO T1CK1 T1CKO High byte pins P3 4 P3 7 TCOUT1 TCOUTO T1OUT1 T1OUTO To individually configure the port 3 pins P3 0 P3 7 you make bit pair settings in two control registers located in set 1 bank 0 PSCONL low byte F5H and PSCONH high byte Port 3 Control Registers P3CONL Two 8 bit control registers are used to configure port 3 pins PSCONL F5H set 1 Bank 0 for pins P3 0 P3 3 and P3CONH F4H set 1 Bank 0 for pins P3 4 P3 7 Each byte contains four bit pairs and each bit pair configures one pin of port 3 ELECTRONICS 9 11 PORTS S3C84MB F84MB UM REV1 00 Port 3 Control Register High Byte PSCONH Set 1 Bank 0 R W 1 24 4 T1OUTO 5 100 1 6 P3 7 TCOUT1 6 bit P3 7 TCOUT1 Input mode Input mode pull up Input mode Input mode pull up Push pull output Alternative function TCOUTO Input mode Input mode pull up Push pull outputt Alternative function T1 OUT1 Input mode Input mode pull up Push pull outputt Alternative function T1 OUTO Figure 9 6 Port 3 High Byte Control Register 9 12 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 3 Control Register Low Byte PSCONL F5H Set 1 Bank 0 R W lis cer en mom d 0 T1CKO P3 1 T1CK1 P3 2 T1CAPO P3 3 T1CAP1 7 6 bit P3 3 T1CAP1 Input mode T1CAP1 Input mode pull up T1CAP
131. R7 CP 8 00H JP NZ ERASE LOOP Set sector number Selection the sector128 base address 4000H Set the sector range m to erase into High byte R6 and Low byte R7 Display ERASE LOOP cycle ELECTRONICS S3C84MB F84MB UM REV1 00 SECTOR ERASE LD LD MULT MULT ADD NOCARRY LD LD R12 SecNumH R14 SecNumL RR12 480H RR14 480H R13 R14 R10 R13 R11 R15 ERASE START LD LD LD LD SB1 LD SBO ERASE STOP LD LD RET PP 80h FMUSR 0A5H FMSECH R10 FMSECL R11 FMCON 10100001B FMUSR 00 PP 00h ELECTRONICS EMBEDDED FLASH MEMORY INTERFACE Calculation the base address of a target sector The size of one sector is 128 bytes BTJRF FLAGS 7 NOCARRY INC R12 User program mode enable Set sector address Select erase mode enable amp Start sector erase User program mode disable 18 9 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 PROGRAMMING A flash memory is programmed in one byte unit after sector erase And for programming safety s sake must set FMSECH FMSECL to flash memory sector value The write operation of programming starts by LDC instruction The Program Procedure in User Program Mode 1 2 3 Must erase sector before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 01010001 Set Flash Memory Sector Address Regist
132. REGISTER FLAGS The flags register FLAGS contains eight bits which describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions Two other flag bits FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether register bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then two write will simultaneously occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W vse 7 e s 4 277 B Bank address status flag BA Carry flag C Fast interrupt Zero flag Z status flag FS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET FLAG DESCRIPTIONS FIS BA Carry Flag FLAGS 7 The C flag is set to 1
133. RPO SRPO RDATA SB1 LD RO SIODATA OR SIOCON 08H AND SIOCON 11111110b POP RPO IRET ELECTRONICS Disable All interrupts 2 2 2 0 are selected to alternative function for SI SO SCK respectively Enable IRQ4 Interrupt Load data to SIO buffer Baud rate input clock fxx 144 1 x 2 Internal clock MSB first transmit receive mode Select Tx falling edges to start shift operation Clear 3 bit counter and start shifting Enable shifter and clock counter Enable SIO interrupt and clear pending Load received data to general register SIO restart Clear interrupt pending bit SERIAL PORT S3C84MB F84MB UM REV1 00 27 PROGRAMMING Use Internal Clock to Transfer and Receive Serial Data Continued 2 The method that uses software pending check is used SlOtest LD BTJRF SIODATA TDATA SIOPS 90H SIOCON 2CH R6 SIOCON SlOtest R6 0 SIOCON 0FEH RDATA SIODATA Disable All interrupts Load data to SIO buffer Baud rate input clock fxx 144 1 x 2 Internal clock MSB first transmit receive mode Select falling edges to start shift operation clear 3 bit counter and start shifting Disable SIO interrupt and pending clear To check whether transmit and receive is finished Check pending bit Pending clear by software Load received data to RDATA ELECTRONICS S3C84MB F84MB UM REV1 00 UART 0 1 2 UART 0 1 2 OVERVIEW The UART block has a full duplex serial port with progra
134. RPO points to locations COH C7H and to locations C8H CFH that is to the common working register area NOTE In the S3C84MB F84MB microcontroller pages 0 8 are implemented Pages 0 7 contain all of the addressable registers in the internal register file Page 0 8 Page 0 7 Register Addressing Only All Indirect EUH Addressing Indexed Addressing Modes Modes Can be pointed by Register Pointer Figure 2 10 Register File Addressing ELECTRONICS 2 13 ADDRESS SPACES S3C84MB F84MB UM REV1 00 COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H RP1 C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH RPO RPI Figure 2 11 Common Working Register Area 2 14 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES 2 PROGRAMMING Addressing the Common Working Register Area As the following examples show you should access working registers in the common a
135. RR heads 18 16 S3C84MB F84MB UM REV1 00 MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control Register 2 442 4004 eene 4 6 BRDATAO UARTO Baud Rate Data Register 4 7 BRDATA1 UART1 Baud Rate Data Register 4 7 BRDATA2 UART2 Baud Rate Data Register 4 7 BTCON Basic Timer Control Register essent 4 8 CLKCON System Clock Control Register 220044 00000 000 4 9 FLAGS system Flags Register ote tede Liter tan e oaa 4 10 FMCON Flash Memory Control 4 11 FMUSR Flash Memory User Programming Control 4 12 FMSECH Flash Memory Sector Address Register High Byte 4 12 FMSECL Flash Memory Sector Address Register Low 4 12 IMR Interrupt Mask 0 2 1 1 ennemis 4 13 IPH Instruction Pointer High Byte 4 14 IPL Instruction Pointer Low Byte a 4 14 IPR Interrupt Priority Register utet ege teg oe iB str 4 15 IRQ Interrupt Request
136. RxD TxD RxD Master Slave 1 Slave 2 Slave n S3C84MB S3C84MB S3C84MB S3C84MB F84MB F84MB F84MB F84MB Figure 14 11 Connection Example for Multiprocessor Serial Data Communications ELECTRONICS 14 13 S3C84MB F84MB UM REV1 00 10 BIT A D CONVERTER 10 BIT A D CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the fifteen input channels to equivalent 10 bit digital values The analog input level must lie between the AVner AVss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type ADC control register ADCON set 1 bank 1 F7H read write but ADCON 3 is read only Eight multiplexed analog data input pins ADCO ADC1 4 10 bit A D conversion data output register ADDATAH ADDATAL Internal AVgee and AVss FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must configure P6 0 6 P7 0 7 to analog input before A D conversions because the P6 0 6 P7 0 7 pins can be used alternatively as normal I O or analog input pins To do this you load the appropriate value to the PECON P7CON for ADCO ADC14 register And you write the channel selection data in the A D converter control register ADCON to select one of the fifteen analog input pins ADCn n 0 14 and set the conversion s
137. Schmitt trigger input with pull up resistor and interrupt generation on falling signal edges Port 8 Interrupt Enable and Pending Registers P8INTPND To process external interrupts at the port 8 pins one additional control register is provided the port 8 interrupt enable register P8INTPND EFH set 1 bank 0 The port 8 interrupt pending register P8INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P8INTPND register at regular intervals When the interrupt enable bit of any port 8 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding P8INTPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a O to the corresponding P8INTPND bit 9 24 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 8 Control Register High Byte EDH Set 1 Bank 0 R W 8 5 8 4 Not used INT9 INT8 3 2 bit P8 5 INT9 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output 1 0 bit P8 4 INT8 00 Input mode falling edge
138. T kia Chapter 5 Interrupt Structure COV OT MIO TTE Interrupt Types fete eo ee es AA ge ecd ay A ei gu S3C84MB F84MB Interrupt Structure Interrupt Vector 6 1 1 1 Enable Disable Interrupt Instructions El DI System Level Interrupt Control Registers Interrupt Processing Control 0 00 0 enne snnt nnns Peripheral Interrupt Control Registers System Mode Register SYM Interrupt Mask Register IMR aiii nnns nenne antenne nitens Interrupt Priority Register Interrupt Request Register IRQ ssssssssssssessss Interrupt Pending Function Interrupt Source Polling Sequence Interrupt Service Routines ssssssssssssssssseseeeeee eene nnn enne nnns nnns tnnt ns Generating interrupt Vector Addresses Nesting of Vectored Interrupts Chapter 6 Instruction Set vi ocu m M DECEBAT Register Addressing Addressing MOGSS amei peg p a et dae een a Ge dva a dc Flags Register FLAGS Flag 81 1 161 6101 3855 CM Instruction Set Notation CP Instruction Descriptions S3C84MB F84MB UM REV1 00 MICROCONTROLLER Table of Contents Conti
139. T REG nMEM R W note Mode 15 0 0 0000 1 Flash ROM Read 0 0000H 0 Flash ROM Progr 3 3V 3 3V 0 0000H 1 Flash ROM Verify 1 0 Flash ROM Read Protection NOTE 0 means Low level 1 means High level ELECTRONICS 21 5 S3C84MB F84MB UM REV1 00 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the 53 7 53 9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all 53 8 53 8 microcontrollers All required target system cables and adapters are included with the device specific target board TB84MB is a specific target board for the development of application systems using 53 84 PROGRAMMING SOCKET ADAPTER When you program S3F84MB s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for 4 ELECTRONICS 22 1 DEVELOPMENT TOOLS S3C84MB F84MB UM REV1 00
140. T signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 and CLKCON 4 are cleared to 00 After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3F84MBJ interrupt structure that be used to release Stop mode External interrupts P4 0 INTO P4 7 INT7 P8 4 INT8 and P8 5 INT9 Please note the following conditions for Stop mode release f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged f you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair
141. TCCON 2 Timer C Data Register Read Write Data Bus NOTE When PWM mode match signal cannot clear counter Figure 11 8 Timer C 0 1 Functional Block Diagram ELECTRONICS 11 13 8 BIT A B C 0 1 PROGRAMMING TIP Using the Timer INITIAL MAIN TAMC INT TAOV INT 11 14 ORG 0000h VECTOR 8 INT VECTOR INT ORG 0100h LD SYM 00h LD IMR 00000001b LD SPH 00000000b LD SPL 0FFh LD BTCON 10100011b LD TADATA 80h LD TACON 01001010b EI MAIN ROUTINE JR T MAIN Interrupt service routine IRET Interrupt service routine IRET END S3C84MB F84MB UM REV1 00 Disable Global Fast interrupt gt SYM Enable IRQO interrupt Set stack area Disable watch dog Match interrupt enable 3 30 ms duration 10 MHz x tal ELECTRONICS S3C84MB F84MB UM REV1 00 2 PROGRAMMING Using the Timer INITIAL MAIN TBUN INT ORG 0000h VECTOR 0C8h TBUN INT ORG 0100h LD SYM 00h LD IMR 0000001 0b LD SPH 00000000b LD SPL 0FFh LD BTCON 10100011b LD P2CONH 00000011b LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b EI MAIN ROUTINE JR T MAIN Interrupt service routine END ELECTRONICS 8 BIT TIMER A B C 0 1 Disable Global Fast interrupt Enable interrupt Set stack area Disable Watch dog Enable TBPWM output Enable interrupt repeating
142. TL JL dL di Start Bit DO Stop Bit Transmit o 1111 RxD Start Bit DO D1 D2 D3 D4 05 D6 D7 Stop Bit pie He Figure 14 8 Timing Diagram for UART Mode 1 Operation ELECTRONICS 14 9 UART 0 1 2 S3C84MB F84MB UM REV1 00 UARTO MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxDO pin or received through the RxDO pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit Stop bit 1 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCONO 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCONO 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 clock frequency Mode 2 Transmit Procedure 1 Select mode 2 9 bit UARTO by setting UARTCONO bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 2 Write transmission data to the shift register UDATAO E2H set 1 bank 1 to start the transmit operation Mode 2 Receive Procedure 1 Select mode 2 and set the receive enable bit RE in the UARTCONO register to 1 2 The receive operation starts when the signal at the RxD pin goes to low level eL JL mnm n IL JL JL 7 Write to Shift Register UARTDATA shit IL dL TxD start Bit X X ps X ps X
143. TM Test under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 72 r r 6 73 r Ir src dst 3 6 74 R R 75 R IR dst src 3 6 76 R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H RO R1 OC7H R1 02H Z 0 RO QR1 RO R1 02H register 02H 23H Z 0 00H 01H Register OOH 2BH register 01H 02H Z 0 TM 00H Q01H gt Register OOH 2BH register 01H 02H register 02H 23H Z 0 00H 54H gt Register 00H 2BH Z 1 In the first example if the working register RO contains the value OC7H 11000111B and the register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask v
144. UCTION SET S3C84MB F84MB UM REV1 00 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02 000 gt Register 00H 41H register 02H 6FH register 42H 6FH If the general register 00H contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 900H loads the contents of the register 42H into the destination register The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode
145. W PIN ASSIGNMENT TAOUT P2 7 TACAP P2 6 TACK P2 5 TBPWM P2 4 P2 3 5 2 2 SIO P2 1 500 2 0 5 7 SDAT P5 6 SCLK P5 5 VDD1 VSS1 Xour Xin TEST P5 4 RxD0 P5 3 RESETB TxD0 P5 2 RxD1 P5 1 TxD1 P5 0 TCOUT1 P3 7 TCOUTO P3 6 08 L1 004 094 82 1 204 294 LLL 04 694 92 1 v Od vOd 1 S 0d SOd tL 904 994 ZF 1 Z0d Z49d eL L3 014 20 1 14 20 89 3 19 L3 99 1 9 Ld eWMd S9 61 ZLd e WMd S3C84MB F84MB 80 QFP 1420C S3C84MB F84MB UM REV1 00 P8 0 SO1 8 1 511 P8 2 SCK1 P8 3 P8 4 INT8 P8 5 INT9 P6 0 ADC8 P6 1 ADC9 P6 2 ADC10 P6 3 ADC1 1 P6 4 ADC12 VDD2 VSS2 P6 5 ADC13 P6 6 ADC14 P6 7 P7 0 ADCO P7 1 ADC1 P7 2 ADC2 P7 3 ADC3 AVSS AVREF P7 4 ADC4 P7 5 ADC5 T1CKO P3 0 CJ 30 NT7 P4 7 J 31 NTO P4 0 L 38 ADC7 P7 7 39 ADC6 P7 6 40 T1CAPO P3 2 28 1 1 1 T1OUT1 P3 5 CJ 25 T1OUTO P3 4 CJ 26 T1CAP1 P3 3 27 Figure 1 2 63 84 Pin Assignment 80 QFP 1 4 ELECTRONICS S3C84MB F84MB UM REV1 00 TACK P2 5 TBPWM P2 4 P2 3 5 2 2 SIO P2 1 SOO P2 0 P5 7 SDAT P5 6 SCLK P5 5 VDD1 VSS1 Xour Xin TEST P5 4 RxD0 P5 3 RESETB TxD0 P5 2 RxD1 P5 1 TxD1 P5 0 ELECTRONICS L Od LOd L Hd eaxg 08 21 9 ed dvOVl 62 L3 2041 1 92 L3 204 94 92 1 Od eOd VLL vOd vod ez S O0d SOd eL L1 9 0d 9Od 21 Z0d 79d 02 4 014 20 1 82 1 004 094 S3C84MB F84MB 80 1212
146. W UDATA2 05H Page 8 R W 6 5 4 3 Transmit or receive data Figure 14 4 UART Data Register UDATAO UDATA1 UDATA2 UART BAUD RATE DATA REGISTER BRDATAO BRDATA1 BRDATA2 The value stored in the baud rate register BRDATAO BRDATA1 BRDATA2 lets you determine the UART clock rate baud rate UART Baud Data Register BRDATO E4H Set 1 Bank 1 R W BRDAT1 FCH Set 1 Bank 1 R W BRDAT2 04H Page 8 R W 6 5 4 3 Baud Rate data Figure 14 5 UART Baud Rate Data Register BRDATAO BRDATA1 BRDATA2 BAUD RATE CALCULATIONS UARTO Mode 0 Baud Rate Calculation In mode 0 the baud rate is determined by the UARTO baud rate data register BRDATAO in sett bank 1 at address E4H Mode 0 baud rate fxx 16 x BRDATAO 1 Mode 2 Baud Rate Calculation The baud rate in mode 2 is fixed at the fosc clock frequency divided by 16 Mode 2 baud rate fxx 16 Modes 1 and 3 Baud Rate Calculation In modes 1 and 3 the baud rate is determined by the UARTO baud rate data register BRDATAO in set 1 bank 1 at address 4 Mode 1 and 3 baud rate fxx 16 x BRDATAO 1 ELECTRONICS 14 5 UART 0 1 2 S3C84MB F84MB UM REV1 00 Table 14 1 Commonly Used Baud Rates Generated by BRDATAQ 1 2 BRDATAO 1 2 Mode Baud Rate o Oscillation Clock Decimal _ Mode 2 0 5 MHz 8MHz x x o 14 6 ELECTRONICS
147. WM circuits you must set PWMCON O to 1 If the counter is stopped it retains its current count value when re started it resumes counting from the retained count value The 3 bit prescaler controls the clock input frequency to the PWM counter By modifying the prescaler value you can divide the input clock by one non divided two three four five six seven or eight The prescaler output is the clock frequency of the PWM counter PWM CONTROL REGISTER PWMCON The control register for the PWM module is located at the register address 07H in Page 8 Bit settings in the PWMCON register control the following functions 3 bit prescaler for scaling the PWM counter clock Stop start or resume the PWM counter operation A reset clears all PWMCON bits to logic zero disabling the entire PWM module ELECTRONICS 16 1 PWM S3C84MB F84MB UM REV1 00 PWM Control Register 07H Pwge 8 RW Not Used Not Used Input Clock Selection bits PWM Counter Enable bits 0 Stop Counter 1 Start Resume Counting Figure 16 1 PWM Control Register 16 2 ELECTRONICS S3C84MB F84MB UM REV1 00 PWM PWM2 PWM3 The S8C84MB F84MB microcontrollers have two 8 bit PWM circuits called 2 These 8 bit circuits have the following components 8 bit counter with 3 bit prescaler 8 bit comparators 8 bit PWM data registers PWMDAT2 PWMDATS3 PWM output pin
148. a Retention Supply Voltage in Stop Mode 19 6 A D Converter Electrical 19 7 LVR Low Voltage Reset Circuit Characteristics 19 7 Flash Memory D C Electrical 19 8 Flash Memory A C Electrical Characteristics sse 19 8 Main Oscillator Frequency rnm mtn 19 9 Main Oscillator Clock Stabilization Time te4 eee 19 9 Descriptions of Pins Used to Read Write the Flash 21 4 Operating Mode Selection 2 21 5 Power Selection Settings for 22 4 Emulator Version Selection Settings for 4 22 4 Using Single Header Pins as the Input Path for External Trigger Sources 22 5 S3C84MB F84MB MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM clear Page 0 1 nennen 2 6 Setting the Register Pointers 1 2 1111 esent enne nnns intr nasi trennen nnns sn 2 10 Using the RPs to Calculate the Sum of a Series of 2 11 Addressing the Common Working Register Area ssssss
149. a register SIODATA1 2 0x02 R W UART2 control register UARTCON2 3 0x03 R W UART2 baud rate data register BRDATA2 4 0x04 R W UART2 data register UDATA2 5 0x05 R W UART 0 1 2 parity register UARTPRT 6 0x06 R W PWM control register PWMCON 7 0x07 R W data register main byte PWMDATO 8 0x08 R W data register extension byte PWMOEX 9 0 09 R W PWM1 data register main byte PWMDAT1 10 Ox0A R W PWM1 data register extension byte PWM1EX 11 0x0B R W 2 Data register PWMDAT2 12 0 0 R W PWMS Data register PWMDAT3 13 0x0D R W PORT1 Extension Control register P1CONEX 14 0 0 R W PORTS Control register P6CON 15 OxOF RAN Stop Mode Control Register STOPCON 16 0x10 RAN Flash memory user enable register FMUSR 17 0x11 R W Flash memory sector register High byte FMSECH 18 0x12 R W Flash memory sector register Low byte FMSECL 19 0x13 R W 4 4 ELECTRONICS S3C84MB F84MB UM REV1 00 Name of individual bit or related bits Bit number s that is are appended to the register name for bit addressing Register ID Register name FLAGS System Flags Register Bit Identifier RESET Value Read Write R W R W R W R W Bit Addressing Register addressing Mode 7 Carry Flag C CONTROL REGISTERS Register location Register address in the internal hexadecimal register file D5H Set 1 4 3 2 1 9 X X X X X 0 0 R W R W R R W 0 Operation does not generate a carry or borrow con
150. able 22 3 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Connector from Triggers External Trigger Sources of the Ch1 Application System ui 11 You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 only for the SMDS2 breakpoint and trace functions IDLE LED The Green LED is ON when the evaluation chip S3E84MB is in idle mode STOP LED The Red LED is ON when the evaluation chip S3E84MB is in stop mode ELECTRONICS 22 5 DEVELOPMENT TOOLS TAOUT P2 7 TACK P2 5 P2 3 SIO P2 1 P5 7 P5 5 Vss N C P5 4 RESETB RxD1 P5 1 TCOUT1 P3 7 T1OUT1 P3 5 T1CAP1 P3 3 T1CK1 P3 1 INT7 P4 7 INT5 P4 5 INT3 P4 3 INT1 P4 1 ADC7 P7 7 5 o Q lt 2 6 2 4 P2 2 SCKO 2 0 500 5 6 VDD1 N C N C TEST P5 3 RxDO P5 2 TxDO P5 0 TxD1 P3 6 TCOUTO P3 4 T1OUTO P3 2 T1CAPO P3 0 T1CKO P4 6 INT6 P4 4 INT4 P4 2 INT2 P4 0 INTO P7 6 ADC6 ADC5 P7 5 AV REF ADC3 P7 3 ADC1 P7 1 P6 7 ADC13 P6 5 Vppe ADC1 1 P6 3 ADC9 P6 1 INT9 P8 5 P8 3 SH P8 1 PWM3 P1 7 PWM1 P1 5 P1 3 RxD2 P1 1 PG7 PO 7 PG5 P0 5 PG3 P0 3 PG1 P0 1 N C Not connected S3C84MB F84MB UM REV1 00 40 PIN DIP Connector P7 4 ADC4 AVss P7 2 ADC2 P7 0 ADCO P6 6 ADC14 Vss2 P6 4 ADC12 P6 2 ADC10 P6 0 ADC8 P8 4 INT8 P8 2 SCK1 P8 0 SO1 P1 6 PWM2 P1 4 PW
151. able interrupt 5 4 5 External Interrupt INT5 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 4 4 External Interrupt 4 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 4 3 External Interrupt INT3 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 4 2 External Interrupt INT2 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P4 1 External Interrupt INT1 Enable Bit 0 Disable interrupt 1 Enable interrupt 0 4 0 External Interrupt INTO Enable Bit 0 Disable interrupt 1 Enable interrupt 4 26 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS PAINTPND Port 4 Interrupt Pending Register FBH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode ELECTRONICS Register addressing mode only P4 7 INT7 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P4 6 INT6 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P4 5 INT5 Interrupt Pending Bit 0 Interrupt request is not pending pending
152. able overflow interrupt 1 Enable overflow interrupt 4 47 CONTROL REGISTERS TACON Timer A Control Register Bit Identifier RESET Value Read Write Addressing Mode 7 6 S3C84MB F84MB UM REV1 00 EAH Set 1 Bank 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only Timer A Input Clock Selection Bits 0 0 fxx 1024 0 1 fxx 256 1 0 fxx 64 1 1 External clock TACK Timer A Operating Mode Selection Bits 0 0 Interval mode TAOUT mode 0 1 Capture mode capture on rising edge counter running OVF can occur 1 0 Capture mode capture on falling edge counter running OVF can occur 1 1 PWM mode OVF interrupt can occur Timer A Counter Clear Bit 0 No effect 1 Clear the timer A counter After clearing return to zero Timer A Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer A Match Capture Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Timer A Start Stop Bit 0 Stop Timer A 1 Start Timer A ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTER TBCON Timer B Control Register DOH Set 1 Bank 0 Bit Identifier 7 6 5 4 3
153. al register OOH 05H LDB R0 00H 2 gt RO LDB 00H 0 RO gt RO 07H register OOH 05H 06H register OOH 04H In the first example the destination working register RO contains the value 06H and the source general register OOH the value 05H The statement LD RO0 00H 2 loads the bit two value of the register into bit zero of the RO register leaving the value 07H in the register RO In the second example is the destination register The statement LD 00H 0 RO0 loads bit zero of the register RO to the specified bit bit zero of the destination register leaving 04H in the general register ELECTRONICS 6 51 INSTRUCTION SET S3C84MB F84MB UM REV1 00 LDC LDE Load Memory LDC LDE Operation Flags Format 1 2 3 4 5 6 T 8 9 10 NOTES dst src dst src dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 C3 r Irr opc src dst 2 10 D3 Irr r opc dst src XS 3 12 E7 r XS rr opc src dst XS 3 12 F7 XS rr r dst src XL XL 4 14 A7 r XL rr opc src dst XL
154. alue X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 0 4 14 Register addressing mode only Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS IPR Interrupt Priority Register FFH Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 4 and 1 ELECTRONICS Register addressing mode only Priority Control Bits for Interrupt Groups A B and C 0 0 0 Group priority undefined 0 0 1 gt gt 0 1 0 gt gt 0 1 1 gt gt 1 0 0 gt gt 1 0 1 gt gt 1 1 0 gt gt 1 1 1 Group priority undefined Interrupt Subgroup C Priority Control Bit 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Interrupt Group C Priority Control Bit 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt 5 Interrupt Subgroup B Priority Control Bit 0 IRQ3 gt IRQ4 1 IRQ4 gt IRQ3 Interrupt Group B Priority Control Bit 0 IRQ2 IRQS IRQ4 1 IRQS IRQ4 gt 2 Interrupt Group A Prio
155. alue does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3C84MB F84MB UM REV1 00 WEI wait tor Interrupt WFI Operation The CPU is effectively halted before an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 1 2 3 Example The following sample program structure shows the sequence of operations that follow WFI statement Main program EI Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed 6 86 ELECTRONICS S3C84MB F84MB UM REV1 00 XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst lt dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different Otherwise a bit is stored C Unaffected Z Setif the result is 0 cleared otherwise
156. and wake up functions Programmable frequency divider for the CPU clock fx divided by 1 2 8 or 16 System clock control register CLKCON S3C84MB F84MB Figure 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator ELECTRONICS 7 1 CLOCK CIRCUIT S3C84MB F84MB UM REV1 00 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows n Stop mode the main oscillator is halted Stop mode is released and the oscillator started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock n Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Main System Oscillator 1 8 1 4096 Circuit Frequency STOP Instruction piu Circuit 114 1 2 1 8 1 16 CLKCON 4 3 IDLE Instruction Figure 7 2 System Clock Circuit Diagram 7 2 ELECTRONICS S3C84MB F84MB UM REV1 00 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the bank 0 of set 1 address It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated
157. ank 0 R W 5 4 5 5 5 6 7 6 bit P5 7 Input mode Input mode pull up P5 7 Input mode Input mode pull up Push pull output Open drain mode Input mode Input mode pull up Push pull output Open drain mode Input mode Input mode pull up Push pull output Open drain mode Figure 9 12 Port 5 High Byte Control Register ELECTRONICS 9 19 PORTS S3C84MB F84MB UM REV1 00 Port 5 Control Register Low Byte PSCONL F9H Set 1 Bank 0 R W ve P5 0 P5 1 TxD1 P5 3 P5 2 RxD1 TxDO RxDO 7 6 bit P5 3 RxDO Input mode RxDO input Input mode pull up RxDO input Push pull output Alternative output mode RxDO output Input mode Input mode pull up Push pull output Alternative output mode TxDO output Input mode RxD1 input Input mode pull up RxD1 input Push pull output Alternative output mode RxD1 output Input mode Input mode pull up Push pull output Alternative output mode TxD1 output Figure 9 13 Port 5 Low Byte Control Register 9 20 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS PORT 6 Port 6 is an 8 bit I O port that you can use two ways Open Drain Output Alternative function ADCO ADC7 input Port 6 pins are accessed directly by writing the port6 data register P6 at location E6H in set 1 bank 0 Port 6 Control Register OFH Page 8 R W
158. ared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3C84MB F84MB interrupt structure pending conditions for IRQ4 IRQ5 IRQ6 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3C84MB F84MB UM REV1 00 INTERRUPT SOURCE POLLING SEQUENCE The dme 28 interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source perip
159. ble interrupt 1 Enable interrupt 0 bit P8 4 INT8 0 Disable interrupt 1 Enable interrupt Figure 9 18 Port 8 Interrupt Pending Register P8INTPND ELECTRONICS 9 27 S3C84MB F84MB UM REV1 00 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT in two different ways As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only Basic timer control register BTCON set 1 read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fxx 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits 7 4 The 8 bit basic timer counter set 1 bank 0 FDH
160. cified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R1 3 R1 OFH If the working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3C84MB F84MB UM REV1 00 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src 4610 lt dst 0 OR src b dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 07 ro Rb src 1 dst 3 6 07 Rb ro NOTE In the second byte of the 3 byte instruction format the destination or the source address is f
161. ck Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset 4 43 CONTROL REGISTERS SPL stack Pointer Low Byte Bit Identifier RESET Value Read Write Addressing Mode 1 0 STOPCON Bit Identifier RESET Value Read Write Addressing Mode 7 0 4 44 S3C84MB F84MB UM REV1 00 D9H Set 1 7 6 5 4 3 2 0 RAN RAN RAN R W R W R W R W R W Register addressing mode only Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SPO The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset Stop Control Register 10H Page 8 5 A 3 2 4 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W All addressing mode Stop Control Bit 1010 0101 Enable STOP Instruction Others Disable STOP Instruction ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS SYM System Mode Register DEH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value x x 0 0 Read Wr
162. ck area LD SPL 11111111b LD BTCON 1010001 1b Disable Watch dog SB1 LDW T1DATAHO 0F0h LD T1CONO0 01000110b fxx 256 interval clear counter Enable interrupt Duration 6 17ms 10 MHz x tal SBO EI MAIN MAIN ROUTINE JR T MAIN e e e Interrupt service routine e IRET END ELECTRONICS 12 7 S3C84MB F84MB UM REV1 00 SERIAL PORT SERIAL I O PORT OVERVIEW Serial I O module SIO can interface with various types of external devices that require serial data transfer SIO has the following functional components SIO data receive transmit interrupt IRQ4 vector CAH ACH generation 8 bit control register SIOCON set 1 bank 1 E1H read write SIOCON 1 Page 8 read write Clock selection logic 8 bit data buffer SIODATA SIODATA1 8 bit prescaler SIOPS set 1 bank 1 read write SIOPS1 Page 8 01H read write 3 bit serial clock counter Serial data pins 500 510 501 511 External clock input output pin SCK0 SCK1 The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO modules follow these basic steps SIO0 1 Configure P2 1 P2 0 and P2 2 to alternative function SIO SOO SCKO for interfacing SIO module by setting the P2CONL register to appro
163. ck transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Ir an even number for program memory and odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 r Irr Given 10H R7 33H 12H program memory locations 1033H 1034H external data memory locations 1033H and 1034H OD5H LDCI R8 RR6 contents of program memory location 1033H is loaded into R8 and is incremented by RR6 lt RR6 1 R8 R6 10H R7 34H R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by RR6 lt RR6 1 R8 ODDH R6 10H R7 34H LDEI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 55 INSTRUCTION SET S3C84MB F84MB UM REV1 00 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples NOTE dst src dst src m 1 dst src These instr
164. cognition All peripherals and blocks can issue interrupt requests In other words peripheral and operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C84MB F84MB interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C84MB F84MB uses twenty seven vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each v
165. d in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3C84MB F84MB UM REV1 00 Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load ext
166. d is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero n urren Instruction OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Progra Memor Address Used PC Value Displacement Current Instruction OPCODE Signed FP Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing
167. dentifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode 7 6 4 34 Register addressing mode only Not used for the S3C84MB F84MB P8 5 INT9 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P8 4 INT8 Interrupt Pending Bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Not used for the S3C84MB F84MB P8 5 INT9 Interrupt Enable 0 Disable interrupt 1 Enable interrupt P8 4 INT8 Interrupt Enable 0 Disable interrupt 1 Enable interrupt ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS Pattern Generation Control Register FEH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode 7 4 ELECTRONICS Register addressing mode only Not used for the S3C84MB F84MB Software Trigger Start Bit 0 No effect 1 Software trigger start will be automatically cleared PG Operation Disable Enable Selection Bit 0 PG operation disable 1 PG operation enable PG Operation Trigger Mode Selection Bits 0 Timer A match siganal triggering Timer B u
168. ditio EN Operation generates carry out or borrow into high orderbit7 Zero Flag Z EN Operation result is a non zero value Operation result is zero Sign Flag S 0 Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 R Read only W Write only R W Read write Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit Description of the effect of specific bit settings RESETvalue notation Not used Undetermined value 0 Logic zero 1 Logic one Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONICS 4 5 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 ADCON A D Converter Control Register F7H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R R W R W R W Addressing Mode 7 4 Register addressing mode only A D Input Pin Selection Bits 0 0 O 0 ADCO ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12 ADC13 Oo ADC14 Others Not used for the S3C84MB F84MB End of Conversion Bit Read only 0 A D conversion opration is in progress 1 A D conversion opration is complete
169. dr Mode Hex dst dst 2 8 80 RR 81 IR Given RO 12H R1 34H R2 30H register OFH and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H register 31H 20H In the first example the destination register RO contains the value 12H and the register R1 the value 34H The statement DECW RRO addresses and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem it is recommended to use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR 2 0 JR NZ LOOP ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 lt 0 Bit zero of the system mode control register 5 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value in the register and clears 5 0 to disabling interrupt processing ELECTRONICS 6 37 INSTRUCTION SET S3C
170. e you must write appropriate value to SIOCON Serial I O Module Control Registers SIOCON E1H Set 1 Bank 1 00H Page 8 R W SIO interrupt pending bit 0 No interrupt pending 0 Clear pending condition when write 1 Interrupt is pending SIO Shift clock selection bit 0 Internal clock P S clock 1 External Clock SCk Data direction control bit SIO interrupt enable bit 0 MSB first mode 0 Disable SIO interrupt 1 LSB first mode 1 Enable SIO interrupt SIO mode selection bit SIO shift operation enable bit 0 Receive only mode 0 Disable shifter and clock counter 1 Transmit receive mode 1 Enable shifter and clock counter Shift clock edge selection bit SIO counter clear and shift start bit 0 Tx at falling edges Rx at rising edges 0 No action 1 Tx at rising edges Rx at falling edges 1 Clear 3 bit counter and start shifting Figure 13 1 SIO Module Control Register SIOCON 13 2 ELECTRONICS S3C84MB F84MB UM REV1 00 SERIAL PORT SIO PRESCALER REGISTER SIOPS SIOPS1 The control register for the serial I O interface module is located set 1 bank 1 at address FAH SIOPS and Page 8 at address 01H SIOPS1 The value stored in the SIO prescaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock fxx SIOPS value 1 x 2 or input clock SIO Pre Scaler Register SIOPS F4H Set 1 Bank 1 01H Page8 R W SIOPS
171. e format for an unconditional jump 2 In the first byte of the 3 byte instruction format conditional jump the condition code and the OPCODE are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL_W LABEL W 1000 PC 1000H JP 00 gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement 00 replaces the contents of the PC with the contents of the register pair and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3C84MB F84MB UM REV1 00 JR Jump Relative JR cc dst Operation If cc is true PC lt dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes at the beginning of this chapter The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following
172. e output pins SI SO SCK Synchronous SIO pins D 7 8 9 P2 1 P2 0 P2 2 RESETB System reset pull up resistor 240 B 19 TEST Pull down register connected internally 16 VDD1 VDD2 Power input pins 12 53 zx VSS1 VSS2 13 52 Xin Xour Main oscillator pins 2 15 14 _ 1 8 ELECTRONICS S3C84MB F84MB UM REV1 00 PRODUCT OVERVIEW PIN CIRCUITS Schmitt Trigger Figure 1 4 Pin Circuit Type B RESETB Data Output Disable Figure 1 5 Pin Circuit Type C ELECTRONICS 1 9 PRODUCT OVERVIEW S3C84MB F84MB UM REV1 00 Pull Up Enable Data Pin Circuit Output Type C Disable Pull Up Enable Data Pin Circuit Output Type C Disable Ext INT Noise Filter Input Normal Figure 1 7 Pin Circuit Type D 1 P4 P8 4 P8 5 1 10 ELECTRONICS S3C84MB F84MB UM REV1 00 PRODUCT OVERVIEW ADC In Enable Data Figure 1 8 Pin Circuit Type E ADCO ADC7 N Channel ADC En IO ADC Figure 1 9 Pin Circuit Type F P6 Open drain Pull up Enable Enable Data Output Disable Digital Input Figure 1 10 Pin Circuit Type G P5 7 P5 4 ELECTRONICS 1 11 S3C84MB F84MB UM REV1 00 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C84MB F84MB microcontroller has two types of address space Internal program memory ROM Internal register file RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addres
173. e register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem it is recommended to use the INCW instruction as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3C84MB F84MB UM REV1 00 IRET Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal iRET Fast FLAGS lt 5 PC IP SP SP 41 FLAGS lt FLAGS PC SP FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex opc 1 12 BF IRET Bytes Cycles Opcode Fast Hex opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the addr
174. e user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 83 IR R Given Register 00H register 01H 05H and register 04H 2AH PUSHUI 00H 01H gt Register OOH 04H register 01H 05H register 04H 05H If the user stack pointer the register for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET RCF neset Carry Flag RCF Operation Flags Format Example RCF C 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3C84MB F84MB UM REV1 00 RET Return RET Operation Flags Format Example PC 5 SP lt SP 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction The contents of the locat
175. ected Bytes Cycles Opcode Hex 1 4 Given The carry flag 0 If the carry flag 0 the CCF instruction complements it in the FLAGS register 0D5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3C84MB F84MB UM REV1 00 CLR Clear CLR dst Operation dst lt 0 Flags Format Examples The destination location is cleared to O No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register 00 4FH register 01H 02H and register 02H 5EH CLR 00H Register 00 00H CLR 901H E Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR OOH clears the destination register OOH value to OOH In the second example the statement CLR 01 uses Indirect Register IR addressing mode to clear the 02H register value to 00H ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET Complement COM dst Operation dst dst The contents of the destination location are complemented one s complement All 1s are changed to Os and vice versa Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 60 R 4 61
176. ector can have several interrupt sources In the S3C84MB F84NB interrupt structure there are twenty seven possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3C84MB F84MB UM REV1 00 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source 54 Type 2 One level IRQn one vector V4 multiple sources S 5 Type 3 One level IRQn multiple vectors V4 V multiple sources S4 S5 S4 4 Spam In the S3C84MB F84MB microcontroller two interrupt types are implemented Levels Vectors Sources 1 IRQn V1 Si 51 2 IRQn S2 S3 Sn 51 3 2 NOTES 1 The nu
177. ecture Selectable CPU clock sources Idle and Stop power down mode released by interrupt or reset Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3C84MB F84MB MICROCONTROLLER The S3C84MB F84MB single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process based on Samsung s latest CPU architecture The 53 84 is a microcontroller with a 64 mask programmable ROM embedded The SSF84MB is a microcontroller with a 64K byte Full Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C84MB F84MB by integrating the following peripheral modules with the powerful SAM8RC core Nine programmable ports including eight 8 bit ports and one 6 bit ports for a total of 70 pins bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and watchdog function system reset Four 8 bit timer counter and two 16 bit timer counter with selectable operating modes 3 asynchronous UART 2 synchronous SIO 15 channel A D converter The S8C84MB F84MB is versatile microcontroller for CD ROM and ADC application etc They are current
178. ed Half Carry Flag H 0 No carry out of bit 3 or no underflow into bit 3 by addition or subtraction 1 Addition generated carry out of bit or subtraction generated underflow into bit 3 Fast Interrupt Status Flag FIS 0 Interrupt return IRET in progress when read 1 Fast interrupt service routine in progress when read Bank Address Selection Flag BA 0 Bank 0 is selected 1 Bank 1 is selected ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS FMCON Flash Memory Control Register FDH Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R R W Addressing Mode 7 4 ELECTRONICS Register addressing mode only Flash Memory Mode Selection Bits 0 1 0 1 Programing Mode 1 0 1 0 Sector Erase Mode 0 1 1 0 Lock Mode Others Not used for the S3C84MB F84MB Interrupt Enable Bit During Sector Erase 0 Interrupt Disable 1 Interrupt Enable Sector Erase Status Bit 0 Sector is Successfully Erased 1 Sector Erase Fail Not used for the S3C84MB F84MB Flash Operation Start Bit Without Programming Mode amp Read Mode 0 StopBit 1 Start Bit CONTROL REGISTERS S3C84MB F84MB UM REV1 00
179. egister register 01H 02H and register 02H 17H RL 00H gt Register 00H 55H 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if the general register 00H contains the value 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry C and the overflow V flags ELECTRONICS 6 71 INSTRUCTION SET S3C84MB F84MB UM REV1 00 RLC Rotate Left through Carry RLC Operation Flags Format Examples dst dst 0 lt lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C and the initial value of the carry flag replaces bit zero 7 0 C Setifthe bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register OAAH register 01H 02H and register 02H 17H C 0 RLC 00H Register OOH RLC 01H Register 01H 54H 1 02H
180. egister 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 register OAH SBC 01 02 Register 01H 1CH register 02H 03H SBC 01H Q02H Register 01H 15H register 02H 03H register OAH SBC 01H 28AH Register 01H 95H C S and V 1 In the first example if the working register R1 contains the value 10H and the register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in the register R1 ELECTRONICS 6 77 INSTRUCTION SET S3C84MB F84MB UM REV1 00 SCF set Carry Flag SCF Operation C 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex 1 4 The statement SCF sets the carry flag to 1 6 78 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET SRA shitt Right Arithmetic SRA Operation Flags Format Examples dst dst 7 dst 7 C lt dst 0 dst n dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into the bit position 6 C Set if the bit shifted from the LSB position bit
181. egular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fy 4096 If an interrupt is used to release stop mode the value increases at t
182. em mode register SYM 222 0 X X 0 0 Register page pointer PP 223 010 0410 0 0 0 0 ELECTRONICS S3C84MB F84MB UM REV1 00 RESET and POWER DOWN Table 8 2 53 84 4 Set 1 Bank 0 Register Values after RESET Register Name Address Bit Values After Reset Dec Hex 7 6 5 4 3 2 1 0 Port 0 data register PO 224 0 0 0 Port 1 data register P1 225 Port 2 data register P2 226 0 0 0 0 0 0 0 Port 3 data register 227 ESH 0 0 0 0 Port 4 data register P4 228 EH 0 40 Port 5 data register P5 229 0 0 Port 6 data register P6 230 EH 0 0 0 0 0 0 0 0 Port 7 data register P7 231 0 0 0 Port 8 data register P8 232 010 Timer A 1 interrupt pending register TINTPND 233 0 0 0 0 Timer A control register TACON 234 0 0 0 0 0 Timer data register TADATA 235 EBH 1 1 1 1 1 1 1 1 Timer A counter register TACNT 236 0410 0 0 Port 8 control register high byte P8CONH 237 EDH O0 0 0 0 Port 8 control register low byte P8CONL 238 0 0 0 0 0 0 0 0 Port 8 interrupt pending register P8INTPND 239 0 01 14 10 0 Port 0 co
183. emory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode PROGRAMMING TIP Reading LD R2 03H Load flash memory s upper address to upper register of pair working register LD R3 00H Load flash memory s lower address to lower register of pair working register LOOP LDC RO RR2 Read data from flash memory location Between 300H and 3FFH INC R3 CP JP NZ LOOP ELECTRONICS 18 15 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 HARD LOCK PROTECTION User can set Hard Lock Protection by writing 0110B in FMCONT 4 This function prevents the changes of data in a flash memory area If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that In tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in user program mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON 01100001
184. eneration Timer C 0 control register TCCONO set 1 bank1 F2H read write Timer C 1 control register TCCON1 set 1 bank1 F3H read write ELECTRONICS 11 11 8 BIT A B C 0 1 S3C84MB F84MB UM REV1 00 TIMER C 0 1 CONTROL REGISTER TCCONO 1 Timer C Control Register TCCONO F2H Set 1 Bank 1 R W Reset 00H 1 F3H Set 1 Bank 1 R W Reset 00H 7 6 5 4 3 2 0 LSB Not Used Timer C pending bit 0 No interrupt pending 1 interrupt pending Timer C 3 bits prescaler bits 000 Non devided 001 Devided by 2 010 Devided by 3 011 Devided by 4 100 Devided by 5 Timer C mode selection bit 101 Devided by 6 0 1 amp PWM mode 110 Devided by 7 1 64 amp interval mode 111 Devided by 8 Timer C interrupt enable bit 0 Disable interrupt 1 Enable interrrupt Timer C counter clear bit 0 No effect 1 Clear the timer A counter when write NOTE When the counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 7 Timer 0 1 Control Register 0 1 11 12 ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 BLOCK DIAGRAM Overflow 2 6 4 Data Bus Pending 0 3 bit 8 bit Up Counter TCCON 3 Pre Read Only scaler 8 bit Comparator 0 Timer C Buffer Reg
185. er FMSECH FMSECL to sector value of the address to write data Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR 00000000B NOTE In programming mode it doesn t care whether 05 value is 0 or 1 18 10 ELECTRONICS S3C84MB F84MB UM REV1 00 Start FMSECH High Address of Sector FMSECL lt Low Address of Sector R n 4 High Address to Write R n 1 lt Address to Write R data 4 8 0 Data FMUSR lt X 0A5H FMCON 4 01010000B LDC lt lt RR n R data FMUSR 00 Finish 1 BYTE Writing EMBEDDED FLASH MEMORY INTERFACE Set Secotr Base Address Set Address and Data User Program Mode Enable Mode Select Write data at flash User Program Mode Disable Figure 18 8 Byte Program Flowchart in a User Program Mode ELECTRONICS 18 11 EMBEDDED FLASH MEMORY INTERFACE S3C84MB F84MB UM REV1 00 FMSECH lt High Address of Sector Set Secotr Base Address FMSECL Low Address of Sector R n High Address to Write Set Address and Data R n 1 lt Address to Write R data 8 04 Data FMUSR 0A5H User
186. erase is required after setting sector address and triggering erase start bit 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool Sector 511 128 Byte Sector 510 128 Byte Sector 19 128 Byte Sector 18 128 Byte Sector 0 17 128 Byte x 18 Figure 18 6 Sectors in User Program Mode 18 6 ELECTRONICS S3C84MB F84MB UM REV1 00 EMBEDDED FLASH MEMORY INTERFACE The Sector Erase Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Sector Address Register FMSECH FMSECL 3 Set Flash Memory Control Register FMCON to 10100001 4 Set Flash Memory User Programming Enable Register FMUSR to 00000000B Select Bank1 FMUSR 4 0 5 User Programimg Mode Enable FMSECH High Address of Sector FMSECL lt Low Address of Sector Base Address FMCON lt 10100001B Mode Select amp Start Erase FMUSR 00H User Prgramming Mode Disable Select Finish One Sector Erase Figure 18 7 Sector Erase Flowchart in User Program Mode NOTES 1 If user erases a sector selected by Flash Memory Sector Address Register FMSECH FMSECL FMUSR should be enabled just before starting sector erase operation And to erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 17 That
187. ering then pattern data are output 17 3 S3C84MB F84MB UM REV1 00 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMEORY INTERFACE OVERVIEW The S3F84MB has an on chip flash memory internally instead of masked ROM The flash memory is accessed by instruction LDC This is a sector erasable and a byte programmable flash User can program the data in a flash memory area any time you want The S3F84MB s embedded 64K byte memory has two operating features as below User Program Mode Tool Program Mode Refer to the chapter 21 63 84 FLASH MCU Flash ROM Configuration The S3F84MB flash memory consists of 512 sectors Each sector consists of 128bytes So the total size of flash memory is 512x128 bytes 64KB User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time 64Kbyte Internal flash memory Sector size 128 Bytes 10years data retention Fast programming Time Sector Erase 10ms min Byte Program 40us min Byte programmable User programmable by LDC instruction Sector 128 Bytes erase available External serial programming support Endurance 10 000 Erase Program cycles min Expandable OBPTM On Board Program User Program Mode This mode supports sector erase byte programming byte read and one protection mode Hard Lock Protection The S3F84MB has the internal pumping circuit to generate
188. ernal data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH src Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing NOTE LDE LDED LDEI LDEPP and LDEPI instructions can be used to read write the data from the 64 Kbyte data memory 6 2 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3C84MB F84MB UM REV1 00 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jum
189. errupt Timer A overflow interrupt pendig bit pending bit 0 No interrupt pending Noi i i intemuptpendiig 0 o interrupt pending 1 Interrupt pending Timer 1 1 match capture interrupt Timer 1 0 match capture interrupt pending bit pending bit 0 No interrupt pending 0 No interrupt pending 1 Interrupt pending 1 Interrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrupt pending NOTE 0 also means Clear pending bit when write Figure 12 2 Timer A and Timer 1 0 1 Pending Register TINTPND ELECTRONICS 12 5 16 1 0 1 S3C84MB F84MB UM REV1 00 BLOCK DIAGRAM T1CON 7 5 1 0 Overflow fxx 256 gt fxx 64 gt fxx 8 gt M fxx 1 gt U X 16 bit Up Counter T1CON 2 TICON2 TICK T1CON 1 16 bit Comparator Emi M U Pending U 19 Pendno TINTPND 16 bit Timer Buffer T1CON 4 3 T1CON 4 3 16 bit Timer Data Register T1DATAH L PG output signal Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 12 3 Timer 1 0 1 Functional Block Diagram 12 6 ELECTRONICS S3C84MB F84MB UM REV1 00 16 BIT TIMER 1 0 1 PROGRAMMING TIP Using the Timer 1 0 ORG 0000h VECTOR OE4h T1MC_INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00001000b Enable IRQ3 interrupt LD SPH 00000000b Set sta
190. ertificate No FM24653 All semiconductor products designed and manufactured in accordance with the highest quality standards and Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyunggi Do Korea Box 37 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page http www samsung com Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR Samsung Electronics LSI Development Group Gi Heung South Korea PRODUCT NAME S3C84MB F84MB 8 bit CMOS Microcontroller DOCUMENT NAME S3C84MB F84MB User s Manual Revision 1 00 DOCUMENT NUMBER 21 00 S3 C84MB F84NMB 012009 EFFECTIVE DATE January 2009 REVISION HISTORY In a tool program mode user must connect TEST pinto Vdd EXE REVISION DESCRIPTIONS FOR REVISION 1 0 Chapter 3 Subjects Major changes comparing with last version Chapter Name Page 21 Flash Memory MCU 1 6 Flash Memory MCU sector is added Preface The S3C84MB F84MB Microcontroller User s Manual is designed for application designers and programmers who are using the 53084 84 microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It ha
191. ess 100H and the IP to keep the return address The last instruction in the service routine is normally a jump to IRET at the address FFH This loads the instruction pointer with 100H again and causes the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH IRET 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last tow instruction The IRET cannot be immediately proceeded by an instruction which clears the interrupt status as with a reset of the IPR register ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET JP sump JP cc dst Conditional JP dst Unconditional Operation If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst cc opc dst 3 8 ccD DA cc 0toF dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byt
192. et 1 Bank 0 R W e 5 5 11111111 PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO P4INTPND Bit Configuration Settings 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 9 11 Port 4 Interrupt Pending Register PAINTPND ELECTRONICS 9 17 l O PORTS S3C84MB F84MB UM REV1 00 PORT 5 Port 5 is an 8 bit I O port with individually configurable pins Port 5 pins are accessed directly by writing or reading the port 5 data register P5 at location 5 in set 1 bank 0 P5 7 P5 4 can serve as inputs outputs push pull or open drain P5 3 P5 0 can serve as inputs outputs push pull or you can configure the following alternative functions Low byte pins P5 3 P5 0 TxDO RxD1 TxD1 Port 5 Control Register 5 P5CONL Port 5 has two 8 bit control registers PSCONH for P5 4 P5 7 and PSCONL for P5 0 P5 3 A reset clears the P5CONH and P5CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 5 control registers must also be enabled in the associated peripheral module 9 18 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 5 Control Register High Byte PSCONH F8H Set 1 B
193. eters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics objectives Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI C
194. executes this instruction Typically one or more NOPs are executed in sequence in order to affect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered ELECTRONICS 6 61 INSTRUCTION SET S3C84MB F84MB UM REV1 00 OR Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a O is stored C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 42 r r 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register OOH 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register
195. g edge OVF can occur 1 1 PWM mode Timer 1 Counter Enable Bit 0 No effect 1 Clear the timer 1 counter Auto clear bit Timer 1 Match Capture Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Overflow Interrupt Enable 0 Disable overflow interrupt 1 Enable overflow interrupt ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS T1CON 1 Timer 1 1 Control Register EBH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 5 ELECTRONICS Register addressing mode only Timer 1 Input Clock Selection Bits 0 0 O fxx 1024 fyx Non divide 5o 256 External clock falling edge fxx 64 External clock rising edge fxx 8 l 0 Counter stop Timer 1 Operating Mode Selection Bits 0 Interval mode Capture mode Capture on rising edge OVF can occur Capture mode Capture on falling edge OVF can occur 4 6 PWM mode Timer 1 Counter Enable Bit 0 No effect 1 Clear the timer 1 counter Auto clear bit Timer 1 Match Capture Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Overflow Interrupt Enable 0 Dis
196. ge You can select rising or falling edges to trigger this operation Timer 1 0 also gives you capture input source the signal edge at the T1CAPO pin You select the capture input by setting the capture input selection bit in the port 3 control register PSCONL set 1 bank 0 F5H Both kinds of timer 1 0 interrupts T1OVFO T1INTO can be used in capture mode the timer 1 0 overflow interrupt is generated whenever a counter overflow occurs the timer 1 0 capture interrupt is generated whenever the counter value is loaded into the T1 data register T1DATAHO LO By reading the captured data value in T1DATAHO LO and assuming a specific value for the timer 1 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1 CAPO pin In capture mode for Timer 1 1 a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the T1 data register T1DATAH1 L1 for rising edge or falling edge You can select rising or falling edges to trigger this operation Timer 1 1 also gives you capture input source the signal edge at the T1CAP1 pin You select the capture input by setting the capture input selection bit in the port 3 control register PSCONL set 1 bank 0 F5H Both kinds of timer 1 1 interrupts T1OVF1 can be used in capture mode the timer 1 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 1 capture interr
197. gister Name Mnemonic Decimal Hex Location R W Port 0 data register 224 Set 1 Bank 0 RAN Port 1 data register P1 225 E1H Set 1 Bank 0 RAN Port 2 data register P2 226 E2H Set 1 Bank 0 RAN Port 3 data register P3 227 Set 1 Bank 0 RAN Port 4 data register P4 228 EAH Set 1 Bank 0 R W Port 5 data register P5 229 E5H Set 1 Bank 0 R W Port 6 data register P6 230 E6H Set 1 Bank 0 R W Port 7 data register P7 231 E7H Set 1 Bank 0 R W Port 8 data register P8 232 E8H Set 1 Bank 0 R W 9 2 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS PORT 0 Port 0 is an 8 bit I O Port that you can use two ways General purpose I O Alternative function PGOUT7 PGOUTO Port 0 is accessed directly by writing or reading the port 0 data register PO at location set 1 bank 0 Port 0 Control Register POCON Port 0 pins are configured individually by bit pair settings in one control registers located in set 1 bank 0 POCON When programming the port please remember that any alternative peripheral I O function you configure using the port 0 control registers must also be enabled in the associated peripheral module ELECTRONICS 9 3 PORTS S3C84MB F84MB UM REV1 00 Port 0 Control Register POCON Set 1 Bank 0 R W ve 4 0 PO 7 PO 6 2 PO 1 5 4 PGOUT 3 2 PGOUT 1 0 PGOUT 7 4 7 6 bit PO 7 P0 6 P0 5
198. gister OOH contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and the overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3C84MB F84MB UM REV1 00 RRC Rotate Right through Carry RRC Operation Flags Format Examples dst dst 7 lt C lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand and the carry flag are rotated right one bit position initial value of bit zero LSB replaces the carry flag and the initial value of the carry flag replaces bit 7 MSB C Setifthe bit rotated from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R 4 C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H Register OOH RRC 01H gt Register 01H 2AH C 4 02H register 02H 1 In the first example if the general register
199. gister addressing mode Program Memory Register File abit Register OPCODE Point to One VA Register in Register OneOperand O File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL 5 Where SHIFT is the label of 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3C84MB F84MB UM REV1 00 INDIRECT REGISTER ADDRESSING MODE Continued Register File REGISTER Example E struction iud m 16 Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File uncus Tu 4 RPO or RP1 RPO or Selected RP points Program Memory to start fo 4 bit working register Rose O block dst Working Register pot Point to the ADDRESS Address Working Register tof 11101 Value used in OPERAND iuc 1 Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3C84MB F84MB UM REV1 00 INDIRECT REGISTER ADDRESSING MODE Concluded Register File RPO
200. grade SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com US pro Portable Samsung OTP MTP FLASH Programmer e Portable Samsung OTP MTP FLASH Programmer e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e Convenient USB connection to any IBM compatible PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com ELECTRONICS S3C84MB F84MB UM REV1 00 DEVELOPMENT TOOLS e Support Samsung standard Hex or Intel Hex format Driver software run under various O S Windows 95 98 2000 XP Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Support Firmware upgrade Jul 2002 USER s Manual a Rev 0 1 ADI System Co Ltd BlueChips Combi BlueChips combi is a programmer for all Samsung MCU It can program not only all Samsung OTP MTP Flash MCU but also the popular E E PROMs New devices will be supported just by adding device files or upgrading the software It is connected to host PC s serial port and controlled by the software System e TEL 82 31 223 661 1 e FAX 82 31 223
201. h 8 bit 9 bit in UART Synchronous SIO e Programmable baud rate e Two synchronous serial I O modules Pattern Generation Module e Pattern generation module triggered by timer match signal and S W Operating Temperature Range 407C 85 C Operating Voltage Range 2 4 V to 5 5 V at 10MHz fosc 4 5 V to 5 5 V at 16MHz fosc Package Type e 80 QFP 80 pin TQFP Built in RESET circuit LVR e Low Voltage check to make system reset Viyn 2 8 4 0V by Smart Option Smart Option ELECTRONICS S3C84MB F84MB UM REV1 00 PRODUCT OVERVIEW BLOCK DIAGRAM RESETB P2 7 TAOUT P2 6 TACAP P2 5 TACK P2 4 TBOUT P3 7 TCOUT1 P3 6 TCOUTO 4 1100 0 2 1 P3 0 T1CKO P3 5 T1OUT1 1 P3 1 T1CK1 2 2 5 2 1 510 2 0 500 P8 0 SO1 P8 1 SI1 P8 2 SCK1 P5 3 RXDO P5 2 TXDO P5 1 RXD1 P5 0 TXD1 P1 1 RXD2 P1 0 TXD2 0 7 1 0 1 7 OSC RESETB 8 Bit Port and Interrupt Control Basic Timer 0 7 8 Bit Timer CounterA B SAM8 RC CPU 8 Bit Timer Counter 4 0 4 7 0 1 INTO INT7 16 Bit Timer Counter10 11 P5 0 P5 7 64K Byte 2064 Byte ROM RAM P6 0 P6 7 5100 1 ADC8 ADC14 UARTO 1 2 14bit PWMO 1 7 0 P8 0 P8 5 P7 0 P7 7 P1 4 PWMO PG PGO INT8 INT9 ADCO ADC7 P1 5 PWM1 P1 6 PWM2 P1 7 PWM3 Figure 1 1 S3C84MB F84MB Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIE
202. he result is of the opposite sign cleared otherwise g Always cleared to 0 T Set if there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 12 r r 6 13 r Ir opc src dst 3 6 14 R R 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 C flag 1 register 01H 20H register 02H register OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H ADC 01 002 gt Register 01H 2BH register 02H 03H ADC 01 811 gt Register 01H 32H In the first example the destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds and the carry flag value 1 to the destination value 10H leaving 14H in the register R1 6 14 ELECTRONICS S3C84MB F84MB UM REV1 00 ADD Add ADD Operation Flags Format Examples dst src dst lt dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed 7 6 V Set if there is a carry from the most sig
203. he contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 17 ro Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 R1 register 01H 01H If the destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values not identical the zero flag bit Z is cleared the FLAGS register OD5H ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET BITC Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bit in the destination C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst 48611010 2 4 57 rb NOTE the sec
204. he interrupt pending bit If interrupts match capture or overflow are enabled the pending bit is cleared automatically by hardware ELECTRONICS 12 3 16 1 0 1 S3C84MB F84MB UM REV1 00 Timer 1 Control Register T1CONO EAH Set 1 Bank 1 R W 1 1 EBH Set 1 Bank 1 R W 7 ee Timer 1 clock source selection bit Timer 1 overflow interrupt 000 fxx 1024 enable bit 001 fxx 0 Disable overflow interrupt 010 fxx 256 1 Enable overflow interrrupt 011 External clock T1CK falling edge 100 fxx 64 Timer 1 match capture interrupt enable bit 101 External clock T1CK rising edge 0 Disable interrupt 110 fxx 8 1 Enable interrrupt 111 Counter stop Timer 1 counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 PWM mode OVF and can occur NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 Timer 1 0 1 Control Register TI CONO 1 ELECTRONICS S3C84MB F84MB UM REV1 00 16 BIT TIMER 1 0 1 Timer A 1 Pending Register TINTPND E9H Set 1 Bank 0 R W e 2 4 3 2 4 e Not used Timer A match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 1 overflow int
205. he port 2 control register 2 set 1 bank 0 F2H When P2CONH 5 4 is 00 the TACAP input or normal input is selected When P2CONH 5 4 is set to 10 normal output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the TA data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to Select the timer A operating mode interval timer capture mode or PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Clear timer A match capture interrupt pending conditions TACON is located in set 1 Bank 0 at address EAH and is read write addressable using Register addressing mode A reset clears TACON to 00 This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a
206. he rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a BTONT 4 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER S3C84MB F84MB UM REV1 00 RESET or STOP Basic Timer Control Register Write 1010xxxxB to disable 4096 fxx 1024 8 Bit Up Counter Read Only fxx 128 R NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Start the CPU note Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 8 BIT TIMER A B C 0 1 8 BIT TIMER A OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting Interval timer mode Toggle output at TAOUT Capture input mode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM PWM output shares its output port with TAOUT pin Timer A has the following functional components Clock frequency divider fx divided by 1024 256 or 64 with multiplexer External clock input pin TACK 8 bit counter 8 bit comparator and 8 bit reference data register pins for capture input PW
207. he register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH the destination register R1 6 82 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET SWAP swap Nibbles SWAP Operation swapped Flags Format Examples dst dst 0 3 e dst 4 7 The contents of the lower four bits and the upper four bits of the destination operand are 0 C Undefined Z Setif the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 FO R 4 F1 IR Given Register 00H register 02H 03H and register 03 OA4H SWAP 00H Register 00 SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if the general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and the upper four bits nibbles in the OOH register leaving the value 11100011 ELECTRONICS 6 83 INSTRUCTION SET S3C84MB F84MB UM REV1 00 TCM rest Complement under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the co
208. heral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The 1 2 3 4 CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence o gi d t mw c Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatena
209. igure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 BIT A B C 0 1 S3C84MB F84MB UM REV1 00 BLOCK DIAGRAM TACON 2 TACON 7 6 Overflow TINTPND 1 fxx 1024 fxx 256 M U 8 bit Up Counter TACON 3 Read Only TACON 1 Pending TINTPND O TAOUT TAPWM TACON 5 4 Timer A Data Register Read Write PG output Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 8 BIT TIMER B OVERVIEW The S3C84MB F84MB micro controller has an 8 bit counter called timer B Timer B which be used to generate the carrier frequency of a remote controller signal Pending bit of timer B is cleared automatically by hardware Timer B has two functions Asa normal interval timer generating a timer B interrupt at programmed time intervals generate a programmable carrier pulse for a remote control signal at P2 4 BLOCK DIAGRAM 2 f PG output signal TBCON 6 7 TBCON 2 TBCON 0 8 Bit Down Counter TB Underflow TBUF TBPWM P2 4 TBCON 3 4 5 Timer Data Timer B Data Low Byte Register High Byte Register Data Bus Data Bus NOTE case of setting TBCON 5 4 at 10 the value of the TBDATAL reg
210. ile locations COH FFH The upper 32 byte area of this 64 byte space is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 64 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S3C84MB F84MB the set 2 address range COH FFH is accessible on pages 0 7 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set
211. interrupt 01 Input mode rising edge interrupt 10 Input mode pull up falling edge interrupt 11 Push pull output Figure 9 16 Port 8 High Byte Control Register PBCONH ELECTRONICS 9 25 PORTS S3C84MB F84MB UM REV1 00 Port 8 Control Register Low Byte P8CONL Set 1 Bank 0 R W 4 3 2 P8 3 P8 2 SCK1 P8 1 SI1 P8 0 SO1 7 6 bit P8 3 00 Input mode 01 Input mode pull up 10 Push pull output 11 Not Used 5 6 bit P8 2 SCK1 00 Input mode SCK1 Input 01 Input mode pull up SCK1 Input 10 Push pull output 11 Alternative Function SCK1 output 3 2 bit P8 1 SI1 00 Input mode 511 01 Input mode pull up 511 10 Push pull output 11 Not Used 1 0 bit P8 0 SO1 00 Input mode 01 Input mode pull up 10 Push pull output 11 Alternative Function SO1 Figure 9 17 Port 8 Low Byte Control Register P8CONL 9 26 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 8 Interrupt Pending Register P8INTPND EFH Set 1 Bank 0 R W d Ll d LL P8 5 P8 4 P8 5 P8 4 Not used ot use PND9 PND8 INT9 INT8 5 bit P8 5 PND9 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 bit P8 4 PND8 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 bit P8 5 INT9 0 Disa
212. inters are selected is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets the register pointer 0 RPO at the location OD6H to 40H and the register pointer 1 RP1 at the location OD7H to 48 H The statement SRPO 50H would set RPO to 50H and the statement SRP1 68H would set RP1 to 68H Before execute the STOP instruction You must set the STPCON register as 101001015 Otherwise the STOP instruction will not execute ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 Example The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3C84MB F84MB UM REV1 00 SU B subtract SUB dst src Operation dst dst src
213. ion addressed by the stack pointer are popped into the program counter The next statement to be executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 10 Given SP SP 101AH and PC 1234 RET gt PC 101AH SP 00 The RET instruction pops the contents of the stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in the location OOFEH 1AH into the PC s low byte and the instruction at the location 101AH is executed The stack pointer now points to the memory location OOFEH ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET RL Rotate Left RL Operation Flags Format Examples dst C lt dst 7 dst 0 lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag as shown in the figure below 31 Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 4 91 IR Given R
214. is an 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 P2 0 P2 7 can serve as inputs outputs push pull or you can configure the following alternative functions Low byte pins P2 0 P2 2 SCKO 610 SOO High byte pins P2 4 P2 7 TACAP TACK TBPWM Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers 2 for P2 4 P2 7 and 2 for 2 0 2 3 A reset clears the P2CONH P2CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module 9 8 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 2 Control Register High Byte P2CONH F2H Set 1 Bank 0 R W Mo d n 4 2 41 2 6 2 7 7 6 bit P2 7 TAOUT Input mode Input mode pull up Push pull output Alternative output mode TAOUT Input mode TACAP Input mode pull up TACAP Push pull output Not used Input mode TACK Input mode pull up TACK Push pull output Not used 1 0 bit P2 4 TBPWM Input mode I
215. is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C84MB F84MB Register Type Summary Register Type Number of Bytes General purpose registers including 16 byte common 2 064 working register area the 192 byte prime register area and the 64 byte set 2 area CPU and system control registers 16 Mapped clock peripheral control and data registers 84 Total Addressable Bytes 2 164 2 4 ELECTRONICS S3C84MB F84MB UM REV1 00 Bank 0 System and Peripheral Control Registers Register Addressing Moda System and Peripheral Control Registers Register Addressing Moda General Purpose Register Register Addressing Moda Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Page 0 Prime Data Registers All Addressing Modes Figure 2 3 Internal Register File Organization ELECTRONICS ADDRESS SPACES 2 5 ADDRESS SPACES S3C84MB F84MB UM REV1 00 REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 2 064 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP
216. ister high byte ADDATAH 248 F8H O 0 0 0 0 0 0 0 A D converter data register low byte ADDATAL 249 0 0 0 0 0 0 UART1 data register UDATA1 250 FAH 1 1 1 1 1 1 1 1 UART1 control register UARTCON1 251 UART1 baud rate data register BRDATA1 252 FCH 1 1 1 1 1 1 1 1 Flash memory control register FMCON 253 FIH 0 Pattern generation control register PGCON 254 O 0 0 0 Pattern generation data register PGDATA 255 FFH 0 0410 0 0 0 8 4 ELECTRONICS S3C84MB F84MB UM REV1 00 RESET and POWER DOWN Table 8 4 S3C84MB F84MB Page 8 Register Values after RESET Address Bit Values After Reset Register Name Mnemonic Hex 7 6 5 4 3 2 1 0 SIO1 control register SIOCON1 0 00H 5101 prescaler control register SIOPS1 1 01H 5101 SIODATA1 2 02H 0 0 0 UART2 control register UARTCON2 3 03H 0 2 baud rate data register BRDATA2 4 04H 111 10 1 10 1 41 1 UART2 data register UDATA2 5 05H 1 1 1 1 1101 1 UART 0 1 2 parity register UARTPRT 6 06H 1010 0 1010 0 PWM control register PWMCON 7 07H 1010 0 1 1 10 data register main byte PWMDATO 8 08H 1 111111 11 111 1 PWMO data register extensi
217. ister is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded with the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded with the value of the 8 bit counter To output TBPWM as carrier wave you have to set 2 1 0 as 11 Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 BIT A B C 0 1 S3C84MB F84MB UM REV1 00 TIMER B CONTROL REGISTER TBCON Timer B Control Register TBCON Set 1 Bank 0 R W we rTspTspespspe sTs ee Timer B input clock selection bit Timer B output flip flop 00 fxx 1 control bit 01 fxx 2 0 T FF is low 10 fxx 4 1 T FF is high 11 fxx 8 Timer B mode selection bit Timer B interrupt time selection bit 0 One shot mode 00 Elapsed time for low data value 1 Repeating mode 01 Elapsed time for high data value 10 Elapsed time for low and high data value Timer B start stop bit 11 Invaild setting 0 Stop timer 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W Reset Value FFh Timer B Data Low Byte Register TBDATAL D2H Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH
218. ister pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C84MB F84MB RP1 Register Pointer 1 D7H Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode 7 3 ELECTRONICS Register addressing only Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice Not used for the S3C84MB F84MB 4 39 CONTROL REGISTERS SIOCON sio Control Register Bit Identifier RESET Value Read Write Addressing Mode 7 4 40 S3C84MB F84MB UM REV1 00 E1H Set 1 Bank 1 7 6 i 4 3 2 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only SIO Shift Clock Selection Bit 0 Internal clock P S clock 1 External clock SCK Data Direction Control Bit 0 MSB first mode 1 LSB first mode SIO Mode Selection Bit 0 Receive only
219. ite R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used for S3C84MB F84MB must keep 0 4 2 Fast Interrupt Level Selection Bits 0 IRQO 0 1 0 1 0 IRG2 0 1 1 IRQ3 1 0 O 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 1 Fast Interrupt Enable Bit 0 Disable fast interrupt processing 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 0 Disable global interrupt processing 1 Enable global interrupt processing NOTE Following a reset you enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O ELECTRONICS 4 45 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 T1CONO rimer 1 0 Control Register EAH Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 4 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 5 4 46 Register addressing mode only Timer 1 Input Clock Selection Bits 0 0 0 1024 0 0 1 fxx Non divide 0 1 0 fxx 256 0 1 1 External clock falling edge 1 0 0 fxx 64 1 0 1 External clock rising edge 1 1 0 8 1 1 1 Counter stop Timer 1 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode Capture on rising edge OVF can occur 1 0 Capture mode Capture on fallin
220. l Register 11 12 Block Diagram tete itae ree ate cs 11 13 Chapter 12 16 bit Timer 1 0 1 OVSIVIOW ri e ea e e Ee A UE att 12 1 Function Description i cedri e 12 2 Timer 1 0 1 Control Register T1 CONO 12 3 lee acum 12 6 Chapter 13 Serial I O Port EE 13 1 Programming Procedure cie caede cit taste tege ei eta sa eene 13 1 SIO Control Register essen 13 2 SIO Prescaler Register SIOPS 51 51 13 3 Block Diagram cu 13 3 822 recita iretur pe diaago 13 4 viii S3C84MB F84MB UM REV1 00 MICROCONTROLLER Table of Contents Continued Chapter 14 UART 0 1 i e IER 14 1 Programming Procedure 4 4 enhn nnns estende 14 1 Uart Control Register UARTCONO UARTCON1 UARTCONO 14 2 Uart Interrupt Pending Register 14 3 Uart Parity Control and Statu
221. l data pin Output port when reading and input P5 6 SDAT 10 8 port when writing SDAT P5 6 be assigned as an Input push pull output port P5 5 SCLK 11 9 Serial clock pin Input only pin Tool mode selection when TEST pin sets Logic value 1 If user uses the flash writer tool mode ex spw2 TEST Vpp 16 14 etc user should connect TEST pin to Vpp S3F84MB supplies high voltage 12 5V by internal high voltage generation circuit RESETB RESETB 19 17 Chip Initialization 12 13 Power supply pin for logic circuit Vpp should be tied Vss Vss 22 i to 3 3V during programming NOTE Parentheses indicate pin number for 80 TQFP package Test Pin Voltage The TEST pin on socket board for writer must be connected to 3 3V The TEST on socket board must not be connected Vpp 12 5V which is generated from Writer So the specific socket board for SSF84MB must be used when writing or erasing using OTP MTP writer ELECTRONICS S3C84MB F84MB UM REV1 00 S3F84MB FLASH MEMORY MCU OPERATING MODE CHARACTERISTICS When logical high is supplied to the Vpp TEST pin of the S3F84MB the Flash ROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 21 2 below Table 21 2 Operating Mode Selection Criteria Address Vpp Vpp TES
222. le you write the value 10H to TADATA and to TACON the counter will increment until it reaches 10H At this point the TA interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although timer A overflow interrupt is occurred this interrupt is not typically used in PWM type applications Instead the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the TA data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the timer A capture input selection bit in t
223. level IRQ3 but is assigned the separate vector address C4H A timer 1 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 1 match capture interrupt T1INT1 pending condition is also cleared by hardware when it has been serviced Interval Mode match The timer 1 0 module can generate an interrupt the timer 1 0 match interrupt T1INTO T1INTO belongs to interrupt level and is assigned the separate vector address COH In interval timer mode a match signal is generated and T1OUTO is toggled when the counter value is identical to the value written to the T1 reference data register T1 DATAHO LO The match signal generates a timer 1 0 match interrupt 11 vector COH and clears the counter The timer 1 1 module can generate an interrupt the timer 1 1 match interrupt T1INT1 T11INT1 belongs to interrupt level and is assigned the separate vector address In interval timer mode a match signal is generated and T1OUT1 is toggled when the counter value is identical to the value written to the T1 reference data register T1 DATAH1 L1 The match signal generates a timer 1 1 match interrupt T1INT1 vector and clears the counter Capture Mode In capture mode for Timer 1 0 a signal edge that is detected at the T1 CAPO pin opens a gate and loads the current counter value into the T1 data register T1DATAHO LO for rising edge or falling ed
224. lue 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 5 Not used for the S3C84MB F84MB must keep always 0 4 3 CPU Clock System Clock Selection Bits 9 0 0 fyy 16 0 1 fxx 8 1 0 2 1 1 1 non divided 2 0 Not used for the S3C84MB F84MB must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 9 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 FLAGS System Flags Register D5H Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value X X X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only Carry Flag C 0 Operation does not generate a carry or underflow condition 1 Operation generates a carry out or underflow into high order bit 7 Zero Flag Z 0 Operation result is a non zero value 1 Operation result is zero Sign Flag S 0 Operation generates a positive number MSB 0 1 Operation generates a negative number MSB 1 Overflow Flag V 0 Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 Decimal Adjust Flag D 0 Add operation completed 1 Subtraction operation complet
225. ly available in 80 pin and 80 pin package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU SAM8RC core Memory e 2064 bytes internal register file e 64K bytes internal program memory S8C84MB Mask ROM S3F84MB Flash type memory Oscillation Sources e Crystal Ceramic e CPU clock divider 1 1 1 2 1 8 1 16 Instruction Set e 78 instructions IDLE and STOP instructions added for power down modes Instruction Execution Time e 400 ns at 10 MHz fosc minimum Interrupts 27 interrupt sources with 27 vectors e 8 level 27 vector interrupt structure 1 Ports e Total 70 bit programmable pins Timers and Timer Counters e One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode e 8 bit timer counter Timer B Carrier frequency or PWM generator e Two 8 bit timer with PWM mode Timer 0 1 e Two 16 bit capture timer counter Timer 10 11 with two operating modes Interval mode Capture mode for pulse period or duty S3C84MB F84MB UM REV1 00 A D Converter e 10 bit resolution e 15 analog input channels e Max 2 5MHz clock PWM e Two 14 bit PWM e Two 8 bit PWM Asynchronous UART e Full duplex 3 channels UARTs Programmable baud rate e Supports serial data transmit receive operations wit
226. m parameters are 1 Timer B is used in one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us TBDATAH 40 us 0 25 us 160 TBDATAL 1 Set P2 4 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAH 160 2 Set40 us LD TBDATAL 1 Setany value except 00H LD 00010001 Clock Source lt fosc Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high LD P2CONH 03 Set 2 4 to TBPWM mode Pulse out LD TBCON 00010101B Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts 11 10 ELECTRONICS S3C84MB F84MB UM REV1 00 8 BIT TIMER A B C 0 1 8 BIT TIMER C 0 1 OVERVIEW The 8 bit timer C 0 1 is an 8 bit general purpose timer counter Timer C 0 1 has two operating modes you can select one of them using the appropriate TCCONO and TCCON1 setting Interval timer mode Toggle output at TCOUTO TCOUT 1 pin PWM mode TCOUTO TCOUT1 Timer C 0 1 has the following functional components Clock frequency divider with multiplexer 8 bit counter 8 bit comparator and 8 bit reference data register TCDATAO TCDATA1 PWM or match output TCOUTO TCOUT1 Timer C 0 match overflow interrupt IRQ2 vector BCH generation Timer C 1 match overflow interrupt IRQ2 vector BEH g
227. match capture 2 194 C2H Timer 1 0 overflow 1 192 Timer 1 0 match capture 0 190 Timer C 1 match overflow IRQ2 1 188 Timer 0 match overflow 0 200 C8H Timer B underflow IRQ1 186 Timer A overflow IRQO 1 184 B8H Timer A match capture 0 SIO1 receive transmit IRQ4 2 UART2 transmit IRQ7 5 UART2 receive 4 NOTES 1 2 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In additi
228. mber of Sn and Vn value is expandable 2 In the S3C84MB F84MB implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE S3C84MB F84MB INTERRUPT STRUCTURE The S3C84MB F84MB microcontroller supports twenty seven interrupt sources All twenty seven of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE Levels IRQO IRQ1 IRQ2 NOTES Vectors B8H BAH C8H BCH BEH COH C2H C6H CAH ACH CCH CEH 2 E4H
229. mmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Serial I O with baud rate of fxx 16 x BRDATA 1 8 UART mode variable baud rate 9 bit UART mode fxx 16 9 0 UART mode variable baud rate UART receive and transmit buffers are both accessed via the data register UDATAO is set 1 bank 1 at address E2H UDATAMt is set 1 bank 1 at address FAH UDATA2 is Page 8 at address 05H Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost In all operating modes transmission is started when any instruction usually a write operation uses the UDATAO UDATA1 UDATA2 register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 UARTPND 3 UARTPND 5 is 0 and the receive enable bit UARTCONO 4 UARTCON1 4 UARTCON2 4 is 1 In mode 1 2 and 3 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCONO 4 UARTCON 1 4 UARTCON2 4 is set to 1 PROGRAMMING PROCEDURE To p
230. mory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory when implemented Register File or points to x start of OPERAND working register block Value used in Instruction Program Memory Teo d Base Address Address wo Operan 2 Example OPCODE Working Register 1 of 8 Sample Instruction LD BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3C84MB F84MB UM REV1 00 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to RPO or RP1 RPO or Selected RP points to start of Program Memory OFFSET NEXT 2 Bits EUM Register Register Address OPCODE Point to Working Pair block 2 16 Bit address added to Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation t
231. n manipulating UARTPND values ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTER UARTPRT UARTO 1 2 Parity Control Register 06H Page 8 Bit Identifier 7 6 5 3 2 RESET Value 0 0 0 0 0 Read Write R R R R W R W R W Addressing Mode ELECTRONICS addressing mode Not used for S3C84MB F84MB UART2 Parity Status Bit 0 No Error 1 Parity Error UART1 Parity Status Bit 0 No Error 1 Parity Error UARTO Parity Status Bit 0 No Error 1 Parity Error Not used for S3C84MB F84MB UART2 Parity Enable Bit 0 Disable 1 Enable UART1 Parity Enable Bit 0 Disable 1 Enable UARTO Parity Enable Bit 0 Disable 1 Enable 4 57 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 NOTES 4 58 ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and re
232. n move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers RO R15 the registers an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2 The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and After a reset RPO and RP1 always point to the 16 byte common area in set 1 Slice 32 11111 Slice 31 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 6 8 Byte Working Register Areas Slices ELECTRONICS 2 9 ADDRESS SPACES S3C84MB F84MB UM REV1 00 USING THE REGISTER POINTERS After a reset RP point to the working register common area RPO points to addresses COH C7H and points to addresses C8H CFH To change register pointer value you load a new value to RPO and or RP1 using
233. nal memory interface is not implemented in the S3C84MB F84MB microcontroller NOTE Before IMR register is changed to any value all interrupts must be disabled Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C84MB F84MB UM REV1 00 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of 5 0 Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El Interrupt Request Register Polling RESET Read only Cycle IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you co
234. nce data registers PWMO PWM1 6 bit extension data registers PWM1EX PWM output pins PWM1 The PWMO and PWM1 circuits are enabled by the PWMCON register 07H Page 8 PWM COUNTER The PWM counter is a 14 bit increasing counter comprised of a lower byte counter and an upper byte counter To determine the PWM module s base operating frequency the lower byte counter is compared to the PWM data register value In order to achieve higher resolutions the lower six bits of the upper byte counter can be used to modulate the stretch cycle To control the stretching of the PWM output duty cycle at specific intervals the 6 bit extended counter value is compared with the 6 bit value bits 2 7 that you write to the module s extension register PWM DATA AND EXTENSION REGISTERS Two PWM duty data registers located Page 8 determine the output value generated by each 14 bit PWM circuit PWMO and are read write addressable 8 bit data registers PWMO 08H PWM1 0AH 6 bit extension registers F5H PWM1EX F7H of which only bits 2 7 are used To program the required PWM output you should load the appropriate initialization values into the 8 bit data registers PWMO PWM 1 and the 6 bit extension registers PWMOEX PWM1EX To start the PWM counter or to resume counting you should set 5 to 1 A reset operation disables all PWM output The curren
235. nd example shows the effect an INC instruction has on the register at the location assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 RR A1 IR Given RO R1 02H register 02H OFH and register OFFH INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register 00H In the first example the working register pair RRO contains the value 1AH in the register RO and 02H in the register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in the register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of the general register 03H from OFFH to 00H and th
236. nd the source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative the C and the S flag values are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement R1 R2 generates 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in the working register R3 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE Operation Flags Format Example dst src RA If dst src 0 PC lt PC Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst RA 3 12 C2 r Ir Given R1 02H R
237. nderflow siganal triggering 1 0 Timer 1 0 match siganal triggering 1 Software triggering mode 4 35 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 Register Page Pointer DFH Set 1 Bit Identifier 7 6 5 4 3 2 1 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 0 0 0 Destination page 0 0 0 0 1 Destination page 1 0 0 1 0 Destination page 2 0 0 1 1 Destination page 0 1 0 0 Destination page 4 0 1 0 1 Destination page 5 0 1 1 0 Destination page 6 0 1 1 1 Destination page 7 1 0 0 0 Destination page 8 Other Value Not Used 3 0 Source Register Page Selection Bits 0 0 0 0 Source page 0 0 0 0 1 Source page 1 0 0 1 0 Source page 2 0 0 1 1 Source page 0 1 0 0 Source page 4 0 1 0 1 Source page 5 0 1 1 0 Source page 6 0 1 1 1 Source page 7 1 0 0 0 Source page 8 Other Value Not Used NOTE In the S3C84MB F84MB microcontroller the internal register file is configured as eight pages Pages 0 7 The pages 0 1 are used for general purpose register file and page 2 7 is used for data register or general purpose registers 4 36 ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS PWMOEX 1EX P
238. nemonic LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD LDCPI LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SBO SB1 SBC SCF SRA SRP SRPO SRP1 STOP SUB SWAP TCM TM WFI XOR xxii List of Instruction Descriptions continued Full Register Name Page Number Load Ts 6 52 Load Memory and Decrement sse nennen nennen nns 6 54 Load Memory and nennen nnns 6 55 Load Memory with 6 56 Load Memory with Pre Increment 6 57 6 58 Multiply Unsigried a a a rb 6 59 Macc 6 60 No Operation ra e do nd te ice e e e adds 6 61 P DEA 6 62 o tatu 6 63 Pop User Stack Decrementing sse enne 6 64 Pop User Stack Incrementing essen 6 65 Push to Stack i iet tend eme te au d ER ER ee A 6 66 Push User Stack enne 6 67 Push User Stack 6 68 Reset Carry Flag aede e fe En dao ta ed i de 6 69 tate net tate a tate nsa e bisects e 6 70 Rotate Ton dod uid coe diste Dre oue 6 71 Rotate Left through
239. nificant bit of the result cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Always cleared to Set if a carry from the low order nibble occurred Bytes Cycles dst src 2 4 6 src dst 3 6 opc dst src 3 6 Opcode Addr Mode Hex dst src 02 r r 03 r Ir 04 R R 05 R IR 06 R IM Given R1 12H R2 register 01H 21H register 02H register OAH ADD ADD ADD ADD ADD R1 R2 R1 R2 01H 02H 01H 02H 01H 25H gt R1 15H R2 03H gt R1 1CH R2 03H Register 01H 24H register 02H 03H Register 01H 2BH register 02H 03H Register 01H 46H In the first example the destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in the register R1 ELECTRONICS 6 15 INSTRUCTION SET AND Logical AND AND Operation Flags Format Examples dst src dst dst AND src S3C84MB F84MB UM REV1 00 The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation causes a 1 bit to be stored whenever the cor
240. nput mode pull up Push pull output Alternative output mode TBPWM When use this port 2 user must be care of the pull up resistance status Figure 9 4 Port 2 High Byte Control Register 2 ELECTRONICS 9 9 PORTS S3C84MB F84MB UM REV1 00 Port 2 Control Register Low Byte P2CONL F3H Set 1 Bank 0 R W 5 4 3 2 2 3 2 2 5 2 1 510 2 0 500 7 6 bit P2 3 00 Input mode 01 Input mode pull up 10 Push pull output 11 Not Used 5 6 bit 2 2 5 0 00 Input mode SCKO Input 01 Input mode pull up SCKO Input 10 Push pull output 11 Alternative Function SCKO output 3 2 bit P2 1 SIO 00 Input mode 510 01 Input mode pull up 510 10 Push pull output 11 Not Used 1 0 bit P2 0 SOO 00 Input mode 01 Input mode pull up 10 Push pull output 11 Alternative Function SOO NOTE When use this port 2 user must be care of the pull up resistance status Figure 9 5 Port 2 Low Byte Control Register P2CONL 9 10 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS PORT Port is an 8 bit I O port that can be used for general purpose I O The pins are accessed directly by writing or reading the port 3 data register at location E3H in set 1 bank 0 P3 7 P3 0 can serve as inputs outputs push pull or you can configure the following alternative functions Low byte pins
241. nput mode pull up 1 0 Push pull output 1 1 Alternative output mode TAOUT 2 6 0 0 Input mode TACAP 0 1 Input mode pull up TACAP 1 0 Push pull output 1 1 Not used P2 5 TACK 0 0 Input mode TACK 0 1 Input mode pull up TACK 1 0 Push pull output 1 1 Not used P2 4 TEPWM 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Alternative output mode TBPWM ELECTRONICS S3C84MB F84MB UM REV1 00 P2CONL Port 2 Control Register Low Byte Bit Identifier RESET Value Read Write Addressing Mode 7 6 ELECTRONICS CONTROL REGISTERS F3H Set 1 Bank 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P2 3 0 0 Input mode 0 1 Input mode pull up 1 0 Push pull output 1 1 Not Used P2 2 SCK 0 0 Input mode SCK input Input mode pull up SCK input 0 1 1 0 Push pull output 1 1 Alternative output mode SCK output P2 1 SI 0 0 Input mode Sl Input mode pull up Sl 0 1 1 0 Push pull output 1 1 Not used 2 0 5 0 0 Input mode Input mode pull up 0 1 1 0 Push pull output 1 1 Alternative output mode SO CONTROL REGISTERS Port 3 Control Register High Byte S3C84MB F84MB UM REV1 00 Set 1 Bank
242. ns remains at Low level for the first 256 counter clocks Then each PWM waveform is repeated continuously at the same frequency and duty cycle until one of the following three events occurs counter is stopped counter clock frequency is changed A new value is written to the PWM data register Counter Clock PWMDAT 0 PWMDAT 1 PWMDAT 80h PWMDAT FFh Figure 16 3 PWM Waveforms for PWM2 PWM3 16 4 ELECTRONICS S3C84MB F84MB UM REV1 00 PWM STAGGERED PWM OUTPUTS The PWMO PWMS outputs are staggered in order to reduce the overall noise level on the pulse width modulation circuits If you load the same value to the PWMO PWMS data registers a match condition data register value is equal to the lower 8 bit count value will occur on the same clock cycle for all the PWM circuits The output of PWM1 3 is delayed by one half of CPU clock for subsequent clock cycles see Figure 16 4 2 Clock Dela 1 Clock Dela 1 Clock Dela Figure 16 4 PWM Clock to PWM2 PWM3 Output Delays ELECTRONICS 16 5 PWM S3C84MB F84MB UM REV1 00 PWMO PWM 1 The S3C84MB F84MB pulse width modulation PWM module has two 14 bit PWM circuits PWMO and PWM 1 The 14 bit PWM circuits have the following components 14 bit counter with 3 bit prescaler an 8 bit counter with 6 bit extension is used for 14 bit output resolution 8 bit comparator and extension cycle circuit 8 bit refere
243. ntrol register P1CON 241 RAN Port 2 control register high byte P2CONH 242 F2H RAN Port 2 control register low byte P2CONL 243 RAN Port 3 control register high byte P3CONH 244 RAN Port 3 control register low byte P3CONL 245 F5H RAN Port 4 control register high byte PACONH 246 F6H RAN Port 4 control register low byte PACONL 247 F7H RAN Port 5 control register high byte P5CONH 248 F8H RAN Port 5 control register low byte P5CONL 249 F9H RAN Port 4 interrupt control register PAINT 250 FAH RAN Port 4 interrupt pending register PAINTPND 251 FBH RAN Location FCH is factory use only Basic timer counter register 253 FDH R Location FEH is not mapped Interrupt priority register IPR 255 FFH R W 4 2 ELECTRONICS S3C84MB F84MB UM REV1 00 Table 4 3 Set 1 Bank 1 Registers CONTROL REGISTERS Register Name Mnemonic Decimal Hex SIO data register SIODATA 224 EOH RAN SIO Control register SIOCON 225 E1H R W UARTO data register UDATAO 226 E2H RAN UARTO control register UARTCONO 227 RAN UARTO baud rate data register BRDATAO 228 EAH R W UARTO 1 pending register UARTPND 229 E5H R W Timer 1 0 data register high byte T1DATAHO 230 E6H R W Timer 1 0 data register low byte T1DATALO 231 E7H R W Timer 1 1 data register high byte T1DATAH1 232 E8H R W Timer 1 1 data register lo
244. ntrol register POCON 240 FOH Port 1 control register P1CON 241 F1H 0 0 0 0 0 0 0 0 Port 2 control register high byte P2CONH 242 2 0 0 0 0 0 0 0 0 Port 2 control register low byte P2CONL 243 0 0 0 0 0 0 0 0 Port 3 control register high byte P3CONH 244 FAH O 0 0 0 0 0 0 0 Port 3 control register low byte PSCONL 245 0 10 0 10 0 Port 4 control register high byte PACONH 246 FeH 0 0 0 0 0 0 0 0 Port 4 control register low byte PACONL 247 7 0 0 0 0 0 0 0 0 Port 5 control register high byte P5CONH 248 FBH 0 40 Port 5 control register low byte P5CONL 249 F9H 0 0 0 Port 4 interrupt control register PAINT 250 FAH 0 0 0 0 0 0 0 0 Port 4 interrupt pending register PAINTPND 251 FBH 0 0 0 0 0 0 0 0 Location FCH is factory use only Basic timer counter register 253 FDH 010 010 Location is not mapped Interrupt priority register IPR 255 FFH x X X X X X ELECTRONICS 8 3 RESET and POWER DOWN S3C84MB F84MB UM REV1 00 Table 8 3 S3C84MB F84MB Set 1 Bank 1 Register Values after RESET Register Name Address Bit Values After Reset Dec Hex 7 66 5 4 3 2 1 0 SIO data register SIODATA 224 EOH 0 0 0 0 0 0 0 SIO Control register SIOCON 22 EIH UARTO data register UDATAO 2
245. ntrol the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer A overflow Timer A match capture TINTPND TACON TADATA TACNT E9H bank 0 EAH bank 0 EBH bank 0 ECH bank 0 Timer B underflow IRQ1 TBCON bank 0 TBDATAH TBDATAL D1H D2H bank 0 Timer C 0 match overflow Timer C 1 match overflow TCCONO 1 TCDATAO TCDATA1 F2H bank 1 bank 1 bank 1 F1H bank 1 Timer1 0 match capture IRQ3 T1DATAHO T1DATALO E6H E7H bank 1 Timer1 0 overflow T1DATAH1 T1DATAL1 E8H E9H bank 1 Timer1 1 match capture T1CONO T1CON1 EAH EBH bank1 Timer1 1 overflow T1CNTLO ECH EDH bank1 TICNTH1 T1ONTL1 EEH EFH bank1 SIO receive transmit IRQ4 SIOCON SIODATA bank1 SIO1 receive transmit SIOCON1 SIODATA1 OOH 02H Page 8 P8 5 external interrupt IRQ5 P8CONH P8CONL EDH EEH bankO P8 4 external interrupt P8INTPND banko P4 7 0 external interrupt IRQ6 P4CONH F6H bank 0 P4CONL F7H bank 0 P4INT FAH bank 0 P4INTPND FBH bank 0 UARTO receive transmit IRQ7 UARTCONO E3H bank 1 UART1 receive transmit UARTCON1 FBH bank 1 UART2 receive transmit UARTCON2 03H Page 8 UDATAO UDATA1 E2H FAH bank 1 UDATA2 05H Page8 UARTPND E5H bank 1 UARTPRT 06H Page8 ELECTRONICS 5 9 INTERRUPT STRUCTUR
246. ntrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C84MB F84MB architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS registers are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte
247. nts of RO is loaded into external data memory location 0104H RR2 RO R2 R3 nochange LDC RO 01H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO R2 01H R3 04H LDC 01H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC RO 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H 04H LDE RO 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H 04H LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO lt contents of external data memory location 1104H RO 98H LDC 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE The LDC and the LDE instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3C84MB F84MB UM REV1 00 LDCD LDED Load Memory and Decrement LDCD LDED Operation Flags Format Examples NOTE dst src dst src dst lt src 17 1
248. nued Part Hardware Descriptions Chapter 7 Clock Circuit i i ETE 7 1 System CIOCKEGINCUIE cst dieci 7 1 Clock Status During Power Down 240 0 000 7 2 System Clock Control Register 0 000000 7 3 Chapter 8 RESET and Power Down System tea Een APR t eh ace Ta PE tee DIA a Ex 8 1 OVELVIGW xaxov 8 1 Normal Mod Reset Operation eo beer tent e eii ced ee UC 8 1 Hardware Reset Values nme e i ei EIER DUE ER A ee 8 2 Power BDown MOodes cpi ATEM i cea hawk 8 6 SIlOpiMOGG ote ie eto tete dive etat ete dte tite esta ded te 8 6 8 7 Chapter 9 Ports MI E H M des 9 1 Port Data Registers nete Et e Oe 9 2 d te dpt E dp eee tdg te T e eee ed ce un 9 3 ETE 9 5 POM 2 9 8 oae EIE 9 11 ge MCI E 9 14 eaa 9 18
249. o LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES INDEXED ADDRESSING MODE Continued Register File 1 or RP1 Selected Ooo RP points to start of working register p Program Memory OFFSET OFFSET NEXT 2 Bits block 4 bit Working dst src src Register Address Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory gt Register Point to Working Pair 16 Bits 16 Bits OPERAND Value used in 16 Bits 111 Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3C84MB F84MB UM REV1 00 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destina
250. ode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Figure 9 8 Port 4 High Byte Control Register PACONH ELECTRONICS 9 15 PORTS S3C84MB F84MB UM REV1 00 Port 4 Control Register Low Byte PACONL F7H Set 1 Bank 0 R W we P4 3 P4 2 P4 1 P4 0 2 INT1 INTO 7 6 bit P4 3 INTS Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Figure 9 9 Port 4 Low Byte Control Register PACONL 9 16 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 4 Interrupt Control Register PAINT FAH Set 1 Bank 0 R W ve D 5 5 11111111 INT7 6 INT5 4 INT2 INTO PAINT Bit Configuration Settings 0 Interrupt disable 1 Interrupt enable Figure 9 10 Port 4 Interrupt Control Register PAINT Port 4 Interrupt Pending Register PAINTPND FBH S
251. on TB8 0 or the odd parity generation TB8 1 in the transmit mode The UARTCON 2 RB8 is also for settings of the even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 and UARTCON 3 TB8 are a normal control bit as the data bit in this case PENn must be disable 0 in mode 2 3 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to 0 or BD The receive parity error flag RPEn will be set to 0 or 1 depending on parity error whenever the 8t data bit of the received data has been shifted UART Parity Register UARTPRT 06H Page 8 R W 2 2 Not used Not used UART2 Parity Error Status UARTO Parity Enable Disable 0 No error 0 Disable 1 Parity error 1 Enable UART1 Parity Error Status UART1 Parity Enable Disable 0 No error 0 Disable 1 Parity error 1 Enable UARTO Parity Error Status UART2 Parity Enable Disable 0 No error 0 Disable 1 Parity error 1 Enable Figure 14 3 UART Parity Register 14 4 ELECTRONICS S3C84MB F84MB UM REV1 00 UART 0 1 2 UART DATA REGISTER UDATAO UDATA1 UDATA2 UART Data Register UDATAO E2H Set 1 Bank 1 R W 1 Set 1 Bank 1 R
252. on byte PWMOEX 9 09H 0 0 data register main byte PWMDAT 1 10 111111711111 1111 PWM data register extension byte 11 OBH 0 0 2 Data register PWMDAT2 12 OCH 1 11111 11 111 1 PWMS Data register 13 1 1 111101 1 PORT Extension Control register P1CONEX 14 0 0 010 0 0 PORTS Control register P6CON 15 OFH Stop Mode Control Register STOPCON 16 10H Flash memory user enable register FMUSR 17 11H Flash memory sector register High byte FMSECH 18 12H 0 Flash memory sector register Low byte FMSECL 19 13H ELECTRONICS 8 5 RESET POWER DOWN S3C84MB F84MB UM REV1 00 POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 200 uA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vss to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESE
253. on to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register ID R W Function Description Interrupt mask register IMR R W _ Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ7 Interrupt priority register IPR R W Controls the relative processing priorities of the interrupt levels The seven levels of S3C84MB F84MB are organized into three groups A B and C Group A is IRQO and IRQ1 group is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register IRQ R This register contains a request pending bit for each interrupt level System mode register SYM R W _ This register enables disables fast interrupt processing dynamic global interrupt processing and external interface control An exter
254. ond byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R1 1 1 05 If the working register R1 contains the value 07H 00000111 the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in the register R1 Because the result of the complement is not the zero flag Z the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3C84MB F84MB UM REV1 00 BITR Bit Reset BITR Operation Flags Format Example dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst b O 2 4 77 rb NOTE the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H BITR R1 1 1 05 If the value of the working register R1 is 07H 00000111 the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET BITS Bit set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the spe
255. operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode 6 8 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6 6 r Working register only Rn 0 15 rb Bit b of working register Rn b n 0 15 b 0 7 rO Bit O LSB of working register Rn n 0 15 rr Working register pair RRp p 0 2 4 14 R Register or working register reg or Rn reg 0 255 n 0 15 Rb Bit b of register or working register reg b reg 0 255 b 0 7 RR Register pair or working register pair reg or RRp reg 0 254 even number only where p 0 2 14 IA Indirect addressing mode addr addr 0 254 even number only Ir Indirect working register only 0 15 IR Indirect register or indirect working register Rn or reg reg 0 255 0 15 Irr Indirect working register pair only p 0 2 14 IRR Indirect register pair or indirect working RRp or reg reg 0 254 even only register pair where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 XL Indexed long offset addressing mode addr RRp addr range 0 65535 where 2 14 DA Direc
256. orities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 Group IRQ5 IRQ6 IRQ7 B21 B22 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority D7 D4 D1 0 IRQO gt IRQ1 0 Undefined 1 IRQ1 gt IRQO gt gt Group gt gt 0 IRQ2 gt IRQ3 IRQ4 gt gt 1 IRQS IRQ4 gt IRQ2 gt gt Subgroup gt gt 0 IRQ3 gt IRQ4
257. our bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR R1 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example the destination working register R1 contains the value 07H 00000111B and the source register 01H the value 03H 00000011 The statement BOR R1 01H 1 logically ORs bit one of the register 01H source with bit zero of R1 destination This leaves the same value 07H in the working register R1 In the second example the destination register 01H contains the value 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of the register 01H destination with bit zero of R1 source This leaves the value in the register 01H ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET BTJRF Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC lt PC dst The specified bit within the source operand is tested If it is a O the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter Otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst src src 0 dst 3 10 37 RA
258. p relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask dst src Test under mask 6 4 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SBO Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP Src Set register pointers SRPO src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter Stop mode ELECTRONICS 6 5 INSTRUCTION SET S3C84MB F84MB UM REV1 00 FLAGS
259. priately value Load an 8 bit value to the SIOCON control register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 To transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 then the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 is set to 1 and an SIO interrupt request is generated ELECTRONICS 13 1 SERIAL I O PORT S3C84MB F84MB UM REV1 00 SIO CONTROL REGISTER SIOCON The control register for the serial interface module SIOCON is located in set 1 bank 1 at address E1H SIOO and Page 8 at address 00H SIO1 It has the control settings for SIO module Clock source selection internal or external for shift clock Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source P S clock at the SCK selects receive only operating mode the data shift operation and the interrupt are disabled and the data direction is selected to MSB first So if you want to use SIO modul
260. rea locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H lt the value in location 40H Examples 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 C3H lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 five high order bits in the register pointer select an 8 byte slice of the register space three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged
261. red D Unaffected H Unaffected Bytes Cycles Opcode Hex src dst 3 22 84 22 85 22 86 Register OOH 01H register 01H register 02H 09H Register OOH register 01H Register OOH 06H register 01H OOH Addr Mode dst src RR R RR IR RR IM 09H register O3H 06H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3C84MB F84MB UM REV1 00 NEXT next NEXT Operation PC lt IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex 1 10 The following diagram shows example of how to use the NEXT instruction Before After Address Data IP Address Address Data PC 0120 43 Address 43 Address 44 Address L 44 Address L 45 Address 45 Address 120 130 Routin Memory Memory 6 60 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET NOP No Operation NOP Operation No action is performed when the CPU
262. register 03H 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84MB F84MB UM REV1 00 DA Decimal Adjust INSTRUCTION SET DA dst Operation dst DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand is not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1
263. resistor with a value of from 50 to 1000 If this resistor is omitted the absolute accuracy will be maximum of 3LSBs 1 10 2 100 to 1000pF 3 100 to 1000pF R1 50 to 1000 R2 10 to 1 Figure 15 5 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 15 5 10 BIT A D CONVERTER S3C84MB F84MB UM REV1 00 PROGRAMMING TIP Configuring A D Converter ADO CHK ADS SB1 TM JR LD SBO P7CON 11111111B ADCON 00000001B ADCON 00001000B Z ADO_CHK ADOBUFH ADDATAH ADOBUFL ADDATAL ADCON 00110001B ADCON 00001000B Z AD3_CHK AD3BUFH ADDATAH AD3BUFL ADDATAL P7 7 P7 0 A D Input MODE Channel ADCO Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data Channel AD3 fxx 16 Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data ELECTRONICS S3C84MB F84MB UM REV1 00 PWM PULSE WIDTH MODULATION OVERVIEW The S8C84MB F84MB microcontrollers have two 14 bit PWM circuits and two 8 bit PWM circuits The 14 bit circuits are called PWMO PWM1 the 8 bit circuits are PNM2 PWMS The operation of all the PWM circuits is controlled by a single control register PWMCON PWMCON also contains a 3 bit prescaler for adjusting the PWM frequency cycle The PWM counter is a 14 bit incrementing counter It is used by the 14 bit PWM circuits To start the counter and enable the P
264. responding bits in the two operands are both logic ones otherwise a bit value is stored The contents of the source are unaffected Unaffected Set if the result is 0 cleared otherwise Always cleared to Unaffected Unaffected dst src src dst opc dst src Set if the result bit 7 is set cleared otherwise Bytes Cycles 4 6 Opcode Addr Mode Hex dst src 52 r r 53 r Ir 54 R R 55 R IR 56 R IM Given R1 12H R2 03H register 01H 21H register 02H register OAH AND AND AND AND AND R1 R2 R1 R2 01H 02H 01H 02H 01H 25H 23 R1 R1 Register 01H Register 01H Register 01H 21H 02H R2 03H 02H R2 03H 01H register 02H 00H register 02H 03H 03H In the first example the destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in the register R1 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src 4610 lt 4810 AND src b or dst b lt dst b AND 0 The specified bit of the source or the destination is logically ANDed with the zero
265. ring signal From now bits of PGDATA are on the P0 0 P0 7 whenever the selected triggering signal occurs Write pattern data to PGDATA Triggering signal selection PGCON 3 0 Triggering signal generation Data output through 0 0 0 7 Figure 17 1 Pattern Generation Flow ELECTRONICS 17 1 PATTERN GENERATION MODULE Pattern Generation Module Control Register PGCON FEH Set 1 Bank 1 R W Not used Timer A match signal triggering Timer B underflow signal triggering Timer 1 0 match signal triggering S W triggering mode Bit2 0 PG operation disable 1 PG operation enable Bit3 0 No effect 1 S W trigger start auto clear Figure 17 2 PG Control Register PGDATA Set 1 Bank 1 FFH PG Buffer S W Timer A match signal Timer B underflow signal Timer 1 0 match signal Figure 17 3 Pattern Generation Circuit Diagram S3C84MB F84MB_UM_REV1 00 ELECTRONICS S3C84MB F84MB UM 1 00 PATTERN GENERATION MODULE Programming Tip Using the Pattern Generation INITIAL MAIN ORG ELECTRONICS 0000h 0100h SYM 00h IMR 01h SPH 0h SPL 0FFh BTCON 10100011b CLKCON 0001 10006 POCON 11111111b PGDATA 10101010b PGCON 00001111b T MAIN Disable Global interrupt SYM Enable IRQO interrupt High byte of stack pointer SPH Low byte of stack pointer gt SPL Disable Watch dog Non divided Enable PG output Setting pattern data Trigg
266. rity Control Bit 0 IRQO gt IRQ1 1 IRQ1 gt IRQO 4 15 CONTROL REGISTERS IRQ Interrupt Request Register Bit Identifier RESET Value Read Write Addressing Mode 4 16 S3C84MB F84MB UM REV1 00 DCH Set 1 7 6 5 4 3 0 0 0 0 0 0 0 0 R R R R R R Register addressing mode only Level 7 IRQ7 Request Pending Bit 0 Not pending 1 Pending Level 6 IRQ6 Request Pending Bit 0 Not pending 1 Pending Level 5 IRQ5 Request Pending Bit 0 Not pending 1 Pending Level 4 IRQ4 Request Pending Bit 0 Not pending 1 Pending Level 3 IRQ3 Request Pending Bit 0 Not pending 1 Pending Level 2 IRQ2 Request Pending Bit 0 Not pending 1 Pending Level 1 IRQ1 Request Pending Bit 0 Not pending 1 Pending Level 0 IRQO Request Pending Bit 0 Not pending 1 Pending ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS POCON Port 0 Contro Register Set 1 Bank 0 Bit Identifier 7 6 5 4 3 2 4 0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode 7 6 Register addressing mode only
267. rogram the UARTO modules follow these basic steps 1 Configure P5 3 and P5 2 to alternative function RxDO TxDO for UARTO module by setting the PSCONL register to appropriatly value Load an 8 bit value to the UARTCONO control register to properly configure the UARTO 1 module For interrupt generation set the UARTO interrupt enable bit UARTCONO 1 or UARTCONO 0 to 1 When you transmit data to the UARTO buffer writing data to UDATAO the shift operation starts When the shift operation transmit receive is completed UARTO pending bit UARTPND 1 UARTPND 0O is set to 1 and an UARTO interrupt request is generated ELECTRONICS 14 1 UART 0 1 2 S3C84MB F84MB UM REV1 00 UART CONTROL REGISTER UARTCONO UARTCON1 UARTCON2 The control register for the UART is called UARTCONO in set 1 bank 1 at address UARTCONI in set 1 bank 1 at address FBH 2 in 8 at address It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations modes 2 and 3 only UART transmit and receive interrupt control A reset clears the UARTCONO UARTCON1 UARTCONe value to 00H So if you want to use UARTO UART1 or UART2 module you must write appropriate value to UARTCONO UARTCON1 2 UART Control Register
268. rresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 62 r r 6 63 r Ir opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H register 02H 23H TCM RO R1 gt RO OC7H R1 02H 2 1 TCM RO R1 gt RO R1 02H register 02H 23H Z 0 TCM 00H 01H gt Register OOH 2BH register 01H 02H Z 1 TCM 00H Q01H gt Register OOH 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2BH Z 0 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement RO R 1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET
269. rrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed ELECTRONICS 8 7 S3C84MB F84MB UM REV1 00 PORTS I O PORTS OVERVIEW The S3C84MB F84MB microcontroller has nine bit programmable I O ports PO P8 port 8 are 6 bit ports and the others are 8 bit ports This gives a total of 70 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3C84MB F84MB I O port functions Table 9 1 S3C84MB F84MB Port Configuration Overview Port Configuration Options Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately 0 0 0 7 can be used as the PG output port PGO PG7 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P1 4 P1 7 can be used as PWMO PWMA output and P1 0 P1 1 can be used as UART2 Tx Rx Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P2 0 P2 7 can be used as I O for TIMERA TIMERB SIO Bit programmable port input or output mode selected by software input or push pull o
270. rupt structure are stored in the vector address area of the internal 64 Kbyte ROM see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 65 535 64 Kbyte Memory Area 0100H lt RESET Address FFH Interrupt Vector Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE Table 5 1 Interrupt Vectors S3C84MB F84MB UM REV1 00 Vector Address Request Reset Clear pO MEE Level Level HW SW 256 100H Basic timer WDT overflow RESETB 246 F6H UART1 transmit IRQ7 3 244 UART1 receive 2 242 F2H UARTO transmit 1 240 UARTO receive 0 238 4 7 external interrupt IRQ6 y 236 4 6 external interrupt 6 234 P4 5 external interrupt 5 232 E8H P4 4 external interrupt 4 230 E6H P4 3 external interrupt 3 228 4 4 2 2 226 2 4 1 external interrupt 1 224 4 0 external interrupt 0 206 P8 5 external interrupt IRQ5 1 204 P8 4 external interrupt 0 202 5100 receive transmit IRQ4 5 198 C6H Timer 1 1 overflow IRQ3 3 196 Timer 1 1
271. s PWM2 PWM3 PWM2 PWMWMS circuits are controlled by the PWMCON register 07H Page 8 8 Bit 8 Bit Data Register Data Buffer Bi 0 When Data Counter 8 Bit PWM Output Comparator 1 When Data gt Counter fosc 8 bit Counter Prescal PWMCON 0 Figure 16 2 Block Diagram for PWM2 and ELECTRONICS 16 3 PWM S3C84MB F84MB UM REV1 00 2 FUNCTION DESCRIPTION All the two 8 bit PWM circuits function identically each has its own 8 bit data register and 8 bit comparator Each circuit compares a unique data register value to the lower 8 bit value of the 8bit PWM counter PWM2 PWMS data registers are located in Page 8 at locations respectively These data registers are read write addressable By loading specific values into the respective data registers you can modulate the pulse width at the corresponding PWM output pins 2 The level at the output pins toggles High and Low at a frequency equal to the counter clock divided by 256 2 The duty cycle of the PWMO PWM1 pins ranges from 0 to 99 6 based on the corresponding data register values To determine the PWM output duty cycle its 8 bit comparator sends the output level High when the data register value is greater than the lower 8 bit count value The output level is Low when the data register value is less than or equal to the lower 8 bit count value The output level at the PWM2 PWMNMS pi
272. s Enable 1 0 Enable 11 2048 Byte Disable Tem Used LVR Enable Control Bit LVR Level Selection Bit 0 Enable LVR Disable LVR Others Not Used NOTES 1 Protection Start Address is 0100h 2 This internal Vpp level is used when the IVC is disabled in STOP mode 3 The value of unused bits of 03CH 03DH 03EH and must be logic 1 Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACES S3C84MB F84MB UM REV1 00 REGISTER ARCHITECTURE In the S3C84MB F84MB implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In addition set 2 is logically expanded 8 separately addressable register pages page 0 7 In case of 53 84 84 the total number of addressable 8 bit registers is 2 164 Of these 2 164 registers 16 bytes are for CPU and system control registers 84 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 2 048 registers are for general purpose use You can always address set 1 register locations regardless of which of the 9 register pages is currently selected Set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages
273. s Register 14 4 Uart Data Register UDATAO UDATA1 2 14 5 Uart Baud Rate Data Register BRDATA1 2 14 5 Baud Rate Calculations UARTO cccccceesceceeeeeeeaeeeeaeeeeeeeeecaaeeeeaaeseeeeeceaeessaaeseeaeeseaeeesiaeeessaeeeeeesaas 14 5 Block Diagram eur ncaa carn teeter 14 7 Uart Mode 0 Function Description CEEA ARIETE 14 8 1 Description ciet tcr te cerni tc rae 14 9 Uart Mode 2 Function Description eene nennen nnne ener nennen nnn nnns 14 10 Uart Mode Function 14 11 Serial Communication for Multiprocessor 14 12 Chapter 15 10 bit A D Converter OVBIVIOW cox caius eles Ie Pe eee ta da ex iva doce 15 1 Funcion Descrlptigri s tuc tette qux actam qud tri dee 15 1 A D Converter Control Register 15 2 Internal Reference Voltage 15 4 ere tomo SE 15 4 Internal A D Conversion 15 5 16 Pulse Width Modulation
274. s six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C84MB F84MB with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C84MB F84MB interrupt structure in detail and further prepares you for additional information presented the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation
275. se Status Bit 0 Sector is Sucessfully Erased 1 Sector Erase Fail Figure 18 2 Flash Memory Control Register FMCON FLASH MEMORY USER PROGRAMMING ENABLE REGISTER After reset the user programming mode is disabled because the value of FMUSR is 00000000B If necessary you can use the user programming mode by setting the value of FMUSR is 10100101 Flash Memory User Programming Enable Register FMUSR 00H Page 8 R W Flash Memory User Programming Enable bits 0000 0000 Disable user Programming Mode 1010 0101 Enable user Programming Mode others Not used Figure 18 3 Flash Memory User Programming Enable Register FMUSR 18 4 ELECTRONICS S3C84MB F84MB UM REV1 00 EMBEDDED FLASH MEMORY INTERFACE FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Address Sector Register High Byte indicates the high byte of sector address One sector consists of 128 bytes Each sector s address starts or XX80H that is a base address of sector is or XX80H So bit 6 0 of FMSECL don t mean whether the value is 1 or 0 We recommend that itis the simplest way to load the sector base address into FMSECH and FMSECL register When programming the flash memory user should program after loading a sector base
276. ses and data between the CPU and the register file The S8C84MB F84MB has an internal 64 Kbyte mask programmable ROM FLASH ROM and 2064 byte RAM ELECTRONICS 2 1 ADDRESS SPACES S3C84MB F84MB UM REV1 00 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C84MB has 64 Kbytes of internal mask programmable program memory The program memory address range is therefore OH FFFFH see Figure 2 1 The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 65 535 64 KByte Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESS SPACES SMART OPTION Smart option is the ROM option for starting condition of the chip The ROM addresses used by smart option are from 003CH to 003FH The default value of ROM is FFH ROM Address 003CH Not Used ROM Address 003DH Not Used ROM Address 003EH ma P Not Used Internal Vpp s 29 Selection election Bi 00 IVC Control Bit In STOP Mode 3 ISP Protection 01 256 Byte 0 _ 512 0 Disable IVC in STOP Enable Bit 19 1024 Byte Alway
277. setting remains unchanged and the currently selected clock value is used external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed Using an internal Interrupt to Release Stop Mode Activate any enabled interrupt causing stop mode to be released Other things are same as using external interrupt 8 6 ELECTRONICS S3C84MB F84MB UM REV1 00 RESET and POWER DOWN IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The inte
278. sssssssee esee nnne nns 2 15 Standard Stack Operations Using PUSH and 2 2 0 11000 enne nnns 2 20 Chapter 11 8 bit Timer A B C 0 1 To generate 38 kHz 1 8duty signal through 2 4 nennen ener nennen nns 11 9 To generate one pulse signal through 11 10 Usna tme TImer Ax ite e ien RE 11 14 Using the Timer B iioi ee edge den petu redet epe de 11 15 Using the Timer 610 m 11 16 Chapter 12 16 bit Timer 1 0 1 Urg the Timer T 0 12 7 Chapter 13 Serial I O Port Use Internal Clock to Transmit and Receive Serial 13 5 Chapter 15 10 A D Converter Configuring A D Converter sse 15 6 Chapter 17 Pattern Generation Module Using the Pattern 17 3 Chapter 18 Embedded FLASH Memory Interface Seclor 66 v vehat td ie v exeo ad ae oaa Tue Roa dA 18 8 PrOgrarmimibig ccs and ceed Ue aa sme EMPIRE I REN t amare athe 18 13 FROACIIG REMO 18 15 Hard Eock Protecton o ae eae teat aca ne boca D ae OU Ven e EO oO E Ee E ER D TP PR NE Ra
279. ster UARTCONO UARTCON 1 14 2 ELECTRONICS S3C84MB F84MB UM REV1 00 UART 0 1 2 UART INTERRUPT PENDING REGISTER UARTPND The UART interrupt pending register UARTPND is located in set 1 bank 1 at address E5H it contains the UARTO 1 2 data transmit interrupt pending bit and the receive interrupt pending bit In mode 0 the receive interrupt pending flag UARTPND 1 UARTPND 3 UARTPND 5 bit is set to 1 when the 8th receive data bit has been shifted In mode 1 2 or 3 the UARTPND 1 UARTPND 3 UARTPND 5 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 UARTPND 3 UARTPND 5 flag must then be cleared by software in the interrupt service routine In mode 0 the transmit interrupt pending flag UARTPND 0 UARTPND 2 UARTPND 4 is set to 1 when the 8th transmit data bit has been shifted In mode 1 2 or 3 the VARTPND O UARTPND 2 UARTPND 4 bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UARTPND 0O UARTPND 2 UARTPND 4 flag must then be cleared by software in the interrupt service routine UART Pending Register UARTPND Set 1 Bank 1 R W RIP2 TIP2 RIP1 TIP1 RIPO Not used MN UARTO transmit interrupt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending UART2 receive interr
280. struction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is normally not accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when the SBO instruction is executed and is set to 1 select bank 1 when the SB1 instruction is executed ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3C84MB F84MB UM REV1 00 Table 6 2 Flag Notation Conventions Flag Description C T lt NN Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst src PC FLAGS RP Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate
281. t 0 Disable Transmit interrupt 1 Enable Transmit Interrupt 4 55 CONTROL REGISTERS S3C84MB F84MB UM REV1 00 UARTPND UARTO 1 2 Pending Register E5H Set 1 Bank 1 Bit Identifier 7 6 5 4 3 2 1 RESET Value 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for S3C84MB F84MB 5 UART2 receive interrupt pending flag 0 Not pending read Clear pending bit when write 1 Interrupt pending 4 UART2 transmit interrupt pending flag 0 Not pending read Clear pending bit when write 1 Interrupt pending 3 UART1 receive interrupt pending flag 0 Not pending read Clear pending bit when write 1 Interrupt pending 2 UART1 transmit interrupt pending flag 0 Not pending read Clear pending bit when write 1 Interrupt pending UARTO receive interrupt pending flag 0 Not pending read Clear pending bit when write 1 Interrupt pending 0 UARTO transmit interrupt pending flag 0 Not pending read Clear pending bit when write 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a O to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for LDB whe
282. t DEC Operation Flags Format Examples dst dst dst 1 The contents of the destination operand are decremented by one Unaffected Set if the result is 0 cleared otherwise Set if result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected TUOSONSOS Bytes Cycles dst 2 4 4 Given R1 and register 03H 10H DEC R1 gt R1 02H DEC R1 gt Register 03H INSTRUCTION SET Opcode Addr Mode Hex dst 00 R 01 IR In the first example if the working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3C84MB F84MB UM REV1 00 DECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst 481 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Ad
283. t Not Used 5 4 bit P1 5 P1 4 Input mode Input mode pull up Push pull output Not Used 3 2 bit P1 3 P1 2 Input mode Input mode pull up Push pull output Not Used 0 bit P1 1 P1 0 Input mode Input mode pull up Push pull output Not Used Figure 9 2 Port 1 Control Register P1CON 9 6 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 1 Extension Control Register P1 CONEX Set 1 Bank 0 R W T4 6 5 4 3 2 0 P1 7 P1 6 P1 5 P1 4 NotUsed P1 1 P1 0 7 P1 7 0 Normal Port 1 7 Fucntion Alternative function 6 P1 6 0 Normal Port 1 6 Fucntion Alternative function PWM2 5 P1 5 0 Normal Port 1 5 Fucntion Alternative function PWM1 4 P1 4 0 Normal Port 1 4 Fucntion Alternative function PWMO 3 2 Not Used 1 P1 1 0 Normal Port 1 1 Fucntion Alternative function UART2 Rx 9TE 0 P1 0 0 Normal Port 1 0 Fucntion Alternative function UART2 Tx Figure 9 3 Port 1 Extension Control Register PICONEX NOTE When the UART2 is operating in mode 0 SIO Rx input P1CONEX 1 must be set to 0 and P1CON 0 1 must be set to input mode or input with pull up mode 00 or 10 In other operating modes mode 0 Rx output mode1 2 3 P1CONEX 0 1 must be set to 1 and P1CON 0 1 values don t care ELECTRONICS 9 7 l O PORTS S3C84MB F84MB UM REV1 00 PORT2 Port 2
284. t PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of the register 40H into the location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET PUSHUD Push User stack Decrementing PUSHUD Operation Flags Format Example dst src IR lt IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given Register 00H 03H register 01H 05H and register 02H PUSHUD 000 01 gt Register 00 02H register 01H 05H register 02H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3C84MB F84MB UM REV1 00 PUSHUI Push user stack Incrementing PUSHUI Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments th
285. t counter value is retained when the counter stops When the counter starts counting resumes at the retained value PWM CLOCK RATE The timing characteristics of both 14 bit output channels are identical and are based on the maximum CPU clock frequency The 3 bit prescaler value in the register determines the frequency of the counter clock You can set PWMCON 6 4 to divide the CPU clock frequency by 1 non divided 2 3 4 5 6 7 or 8 Because the maximum CPU clock rate for the S3C84MB F84MB microcontrollers is 16 MHz the maximum base PWM frequency is 62 5 kHz 16 MHz divided by 256 This assumes a non divided CPU clock 16 6 ELECTRONICS S3C84MB F84MB UM REV1 00 PWM Table 16 1 PWMO and 1 Control and Data Registers Register Name Mnemonic Address Page 8 Function PWMO Data Register PWMO 08h 8 bit PWMO basic cycle frame value PWMOEX 09h 6 bit extension stretch value PWMO Data Register PWM1 OAh 8 bit PWM1 basic cycle frame value PWM1EX OBh 6 bit extension stretch value PWM Control Register PWMCON 07h PWMO counter stop start resume and 3 bit prescaler for CPU clock also contains capture A control settings 6 Bit extension Register 14 bit Counter Overflow 8 Bit Data Register fosc PWMCON O ELECTRONICS Extension Data Buffer Prescaler Figure 16 5 Block Diagram for PWMO and PWM1 Upper 6 Bit of 14 bit Counter Extension Control Logic
286. t Board 22 3 22 3 40 Pin Connectors for 84 S3C84MBJ 80 QFP 22 6 22 4 TB84MB Cable for 80 QFP 22 6 xiv S3C84MB F84MB MICROCONTROLLER Table Number 14 1 16 1 16 2 18 1 List of Tables Title Page Number S3C84MB F84MB Pin Descriptions 80 1 6 S3C84MB F84MB Register Type 2 4 Set 1 Bank O Reglslers e AW devel ener eo do exe dat e aaa 4 1 Set 1 Bank O R6gisters ee tUe ee cele redes da eode Ug dae ann das 4 2 Set T Bank 1 Registers 4 3 Page 8 Registers esce dc duce c dua av dg dea e eeu 4 4 interrupt Vectors eee 5 6 Interrupt Control Register Overview 5 7 Interrupt Source Control and Data Registers 5 9 Instruction Group 4 1 ener 6 2 Flag Notation 6 8 Instruction Set nnnm nens 6 8 Instruction Notation Conventions 1 1 1200044 000000 0 6 9 Opcode Quick Mene
287. t addressing mode addr addr range 0 65535 RA Relative addressing mode addr addr a number from 127 to 128 that is an offset relative to the address of the next instruction IM Immediate addressing mode data data 0 255 IML Immediate long addressing mode data data 0 65535 ELECTRONICS 6 9 INSTRUCTION SET Table 6 5 OPCODE Quick Reference S3C84MB F84MB UM REV1 00 OPCODE MAP LOWER NIBBLE HEX 0 1 2 3 4 5 6 7 U 0 DEC DEC ADD ADD ADD ADD ADD BOR R1 IR 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb P 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 P 2 INC INC SUB SUB SUB SUB SUB BXOR R1 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb E 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA R 4 DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 5 POP POP AND AND AND AND AND BITC R1 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b N 6 COM COM TCM TCM TCM TCM TCM BAND R1 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b B 8 DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 B 9 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 L A INCW INCW CP CP CP CP CP LDC RR1 1 r1 r2 r1 Ir2 R2 R1 IR2 R
288. t corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH 5 1 R W we IRQO IRQ2 IRQ5 IRQ7 6 Interrupt level enable bit 0 Disable IRQ interrupt 1 Enable IRQ interrupt Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3C84MB F84MB UM REV1 00 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level pri
289. tart or enable bit ADCON O An 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 1 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of a 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH ADDATAL registers where it can be read The ADC module enters an idle state Remember to read the contents of ADDATAH and ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at the ADCO ADC14 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result ELECTRONICS 15 1 10 BIT A D CONVERTER S3C84MB F84MB UM REV1 00
290. tatement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation 1 If r 0 PC dst The working register being used as counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE In case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst r opc dst 2 8 jump taken rA RA 8 no jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In
291. ted 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent ELECTRONICS 5 17 S3C84MB F84MB UM REV1 00 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment include
292. tement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET BXOR Bit BXOR BXOR Operation Flags Format Examples dst src b dst b src 4610 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or the source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 27 ro Rb src b 1 dst 3 6 27 Rb ro NOTE the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 0000001 1B BXOR R1 01H 1 gt R1 06H register 01H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In
293. ter 1 Product Overview S3C8 Series Microcontrollers S3C84MB F84MB Microcontroller Features Block Diagram Pin Assignment Pin Descriptions Pin Circuits Chapter 2 Address Spaces OVOIVIOW x o LLLA Program Memory ROM SMart e Register ArCniteCture Register Page Pointer Register Set 1 FRREGISIEr SEU ES Prime Register Space Working Registers E Using the Register Pointers Hegister Addressinig eoi Pe bk eei Common Working Register Area COH CFH 4 Bit Working Register Addressing 8 Bit Working Register Addressing System and User Stack Chapter 3 Addressing Modes MI HE Register Addressing Mode eene Indirect Register Addressing Mode IR Indexed Addressing Mode X Direct Address Mode DA Indirect Address Mode 1 10 10100 a Relative Address Mode RA Immediate Mode IM S3C84MB F84MB UM REV1 00 MICROCONTROLLER Table of Contents Continued Chapter 4 Control Registers GRU
294. ter CLKCON 212 D4H R W System flags register FLAGS 213 D5H R W Register pointer 0 RPO 214 D6H R W Register pointer 1 215 7 R W Stack pointer high byte SPH 216 D8H R W Stack pointer low byte SPL 217 D9H R W Instruction pointer high byte IPH 218 DAH R W Instruction pointer low byte IPL 219 DBH R W Interrupt request register IRQ 220 DCH R Interrupt mask register IMR 221 DDH R W System mode register SYM 222 DEH R W Register page pointer PP 223 DFH R W ELECTRONICS 4 1 CONTROL REGISTERS Table 4 2 Set 1 Bank 0 Registers S3C84MB F84MB UM REV1 00 Register Name Mnemonic Decimal Hex Port 0 data register 224 EOH RAN Port 1 data register P1 225 E1H RAN Port 2 data register P2 226 E2H RAN Port 3 data register P3 227 RAN Port 4 data register P4 228 EAH RAN Port 5 data register P5 229 5 RAN Port 6 data register P6 230 E6H R W Port 7 data register P7 231 E7H R W Port 8 data register P8 232 E8H R W Timer A 1 interrupt pending register TINTPND 233 E9H R W Timer A control register TACON 234 EAH RAN Timer A data register TADATA 235 EBH R W Timer counter register TACNT 236 ECH R Port 8 control register high byte P8CONH 237 EDH RAN Port 8 control register low byte P8CONL 238 EEH RAN Port 8 interrupt pending register P8INTPND 239 EFH R W Port 0 control register POCON 240 FOH R W Port 1 co
295. the JR statement Flags No flags are affected Format Bytes Cycles Opcode Addr Mode note Hex dst cc opc dst 2 6 ccB RA cc O toF NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Example Given The carry flag 1 and LABEL X 1FF7H JR C LABEL_X 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is currently in the program counter Otherwise the program instruction following the JR will be executed 6 48 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET LD Loap LD dst src Operation dst src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 r IM 4 r8 r R src opc dst 2 4 r9 R r r 0toF opc dst src 2 4 C7 r Ir 4 D7 Ir r opc src dst 3 6 E4 R R E5 R IR opc dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R opc dst src 3 6 87 r x r src dst X 3 6 97 x r r ELECTRONICS 6 49 INSTRUCTION SET L D Load LD Continued S3C84MB F84MB UM REV1 00 Examples Given RO 01H R1 OAH register 01H register 01
296. the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 R IRQO IRQ2 IRQ5 Interrupt level request pending bit 0 IRQ interrupt is not pending 1 IRQ interrupt is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3C84MB F84MB UM REV1 00 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C84MB F84MB interrupt structure the timer B underflow interrupt IRQ1 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cle
297. the port 4 interrupt pending register PAINTPND FBH set 1 bank 0 The port 4 interrupt pending register P4INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P4INTPND register at regular intervals When the interrupt enable bit of any port 4 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding P4INTPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must clear the pending condition by writing a 0 to the corresponding P4INTPND bit 9 14 ELECTRONICS S3C84MB F84MB UM REV1 00 PORTS Port 4 Control Register High Byte PACONH F6H Set 1 Bank 0 R W ve P4 7 P4 6 P4 5 P4 4 INT7 6 5 INT4 7 6 bit P4 7INT7 Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Input mode falling edge interrupt Input mode rising edge interrupt Input mode pull up falling edge interrupt Push pull output Input m
298. the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes Binary Mnemonic Description Flags Set 0000 F Always false 1000 Always true 0111 1 Carry 1 1111 1 0 0110 0 2 Zero 2 1 1110 0 NZ Not zero Z 0 1101 PL Plus 5 0 0101 Minus 5 1 0100 OV Overflow V 1 1100 NOV No overflow 0 0110 1 Equal 1 1 1110 7 Not equal 2 0 1001 Greater than or equal 5 0 0001 LT Less than S V 1 1010 GT Greater than Z OR S V 0 0010 LE Less than or equal Z 5 V 1 1111 1 UGE Unsigned greater than or equal 0 0111 1 ULT Unsigned less than 1 1011 UGT Unsigned greater than C20 AND Z 0 1 0011 ULE Unsigned less than or equal C OR 2 1 NOTES 1 It indicate condition codes which are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used Following a CP instruction you would probably want to use the instruction EQ 2 Foroperations using unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed
299. tion address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte dst src or 1 _dst sre_ LSB Selects Program OPCODE Memory or Data Memory 0 2 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3C84MB F84MB UM REV1 00 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3C84MB F84MB UM REV1 00 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operan
300. tretched by one cycle except the 64th pulse PWM output goes to an output buffer and then to the corresponding PWMO and PWM1 output pin In this way you can obtain high output resolution at high frequencies Table 16 2 PWM Output Stretch Values for Extension Registers PWMOEX PWM1EX Bit Stretched Cycle Number 7 1 3 5 7 9 55 57 59 61 63 6 2 6 10 14 50 54 58 62 5 4 12 20 28 44 52 60 4 8 24 40 58 3 16 48 2 32 1 Not Used 0 Not Used 16 8 ELECTRONICS S3C84MB F84MB UM REV1 00 PWM 2 PROGRAMMING TIP Programming PWMO to Sample Specifications This example shows how to program the 14 bit pulse width modulation module PWMO The program parameters are as follows The oscillation frequency of the main crystal is 6 MHz data is in the working register RO PWMOEX PWMO extension value is in the working register R1 bits 2 7 The program performs the following operations 1 Set the PWMO frequency to 23 437 kHz 2 If R3 0 1 then PWM lt PWM 12H If an overflow occurs from RO then RO lt and R1 lt OFCH 3 If R3 0 0 then PWM lt PWM 11H If an underflow occurs from RO then RO 00H and R1 00H PWMCON lt s 01h RO Min value RO Max value R1 Min value R1 Max value Figure 16 6 Decision Flowchart for PWMO Programming Tip ELECTRONICS 16 9 PWM
301. uctions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 2 14 F2 Irr r Given 77H R6 30H and R7 00 LDCPD RR6 RO RR6 lt RR6 1 TTH the contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 LDEPD RR6 RO RR6 lt RR6 1 TTH the contents of RO is loaded into external data memory location 2FFFH 3000H 1H LDEPD instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS S3C84MB F84MB UM REV1 00 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples NOTE dst src dst src rr 1 dst lt src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first incremented
302. upt is generated whenever the counter value is loaded into the T1 data register By reading the captured data value in T1DATAH1 L1 and assuming a specific value for the timer 1 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the pin 12 2 ELECTRONICS S3C84MB F84MB UM REV1 00 16 BIT TIMER 1 0 1 PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUTO T1OUT1 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 0 1 data register In PWM mode however the match signal does not clear the counter but can generate a match interrupt The counter runs continuously overflowing at FFFFH and then continuous increasing from 0000H Whenever an overflow is occurred an overflow 1 interrupt can be generated Although you can use the match or the overflow interrupt in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the T1OUTO T1OUT 1 is held to low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value One pulse width is equal to tc 1 0 1 CONTROL REGISTER T1CONO T1CON1 You use the timer 1 0 1 control register
303. upt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending UART2 transmit interrupt pending flag UARTO receive interrupt pending flag 0 Not pending 0 Not pending 0 Clear pending bit when write 0 Clear pending bit when write 1 Interrupt pending 1 Interrupt pending UART1 receive interrupt pending flag UART1 transmit interrupt pending flag 0 Not pending 0 Not pending 0 Clear pending bit when write 0 Clear pending bit when write 1 Interrupt pending 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Figure 14 2 UART Interrupt Pending Register UARTPND ELECTRONICS 14 3 UART 0 1 2 S3C84MB F84MB UM REV1 00 UART PARITY CONTROL and STATUS REGISTER UARTPRT In mode 2 9 bit UART data by setting the parity enable bit PENO 1 2 of UARTPRT register to 17 the 9 data bit of transmit data will be an automatically generated parity bit Also the 9 data bit of the received data will be treated as a parity bit for checking the received data In parity enable mode PENn 1 UARTCON 3 TB8 and UARTCON 2 RB8 will be a parity selection bit for transmit and receive data respectively The UARTCON 3 TB8 is for settings of the even parity generati
304. ut or push pull output SO1 Software assignable pull up 511 P8 4 P8 5 alternately be used as inputs for SCK1 external interrupts INT8 9 respectively with noise filters and interrupt controller ELECTRONICS 1 7 PRODUCT OVERVIEW S3C84MB F84MB UM REV1 00 Table 1 1 S C84MB F84MB Pin Descriptions 80 QFP Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins ADO AD7 Analog input pins for A D converter module E 48 45 7 0 7 7 Alternatively used as general purpose digital 42 39 input port 7 AVREF AVSS A D converter reference voltage and ground 43 44 RxD1 y o Serial data RxD pin for receive input and D 18 21 P5 3 P5 1 transmit output mode 0 TxDO TxD1 Serial data TxD pin for transmit output and D 20 22 P5 2 P5 0 shift clock input mode 0 TACK External clock input pins for timer A D 3 2 5 Capture input pins for timer D 2 P2 6 TAOUT Pulse width modulation output pins for timer A D 1 P2 7 TBPWM Carrier frequency output pins for timer B D 4 P2 4 TCOUTO Timer 8 bit PWM mode output or counter D 24 23 P3 6 P3 7 TCOUT1 match toggle output pins T1CKO External clock input pins for timer 1 D 39 30 P3 0 P3 1 T1CK1 T1CAPO Capture input pins for timer 1 D 28 27 P3 2 P3 3 T1CAP1 T1OUTO Timer 1 16 bit PWM mode output or counter D 26 25 P3 4 P3 5 T1OUT1 match toggl
305. utput Software assignable pull up Alternately P3 0 P3 7 can be used as I O for TIMERCO C1 TIMER1 0 11 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up P4 0 P4 7 can alternately be used as inputs for external interrupts INTO INT7 respectively with noise filters and interrupt controller Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P5 0 P5 3 can be used as I O for serial port UARTO UART1 respectively N channel open drain output only port Alternately P6 0 P6 6 be used as ADC8 ADC 14 input General purpose digital input ports Alternatively used as analog input pins for A D converter modules Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up P8 4 P8 5 can alternately be used as inputs for external interrupts INT8 INT9 respectively with noise filters and interrupt controller P8 0 P8 2 can be used as I O SIO1 ELECTRONICS 9 1 l O PORTS S3C84MB F84MB UM REV1 00 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all five S3C84MB F84MB 1 port data registers Data registers for ports 0 1 2 3 4 5 6 7 and 8 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary Re
306. w byte T1DATAL1 233 E9H R W Timer 1 0 control register T1CONO 234 EAH R W Timer 1 1 control register 1 235 R W Timer 1 0 counter register high byte T1CNTHO 236 ECH R Timer 1 0 counter register low byte 0 237 EDH R Timer 1 1 counter register high byte 238 R Timer 1 1 counter register low byte TICNTL1 239 EFH R Timer C 0 data register TCDATAO 240 FOH R W Timer C 1 data register TCDATA1 241 F1H RAN Timer C 0 control register TCCONO 242 F2H R W Timer C 1 control register TCCON1 243 F3H R W SIO prescaler control register SIOPS 244 F4H R W Port 7 control register P7CON 245 F5H R W Location F6H is not mapped A D converter control register ADCON 247 F7H R W A D converter data register high byte ADDATAH 248 F8H R A D converter data register low byte ADDATAL 249 F9H R UART1 data register UDATA1 250 FAH R W UART1 control register UARTCON1 251 FBH R W UART1 baud rate data register BRDATA1 252 FCH R W Flash memory control register FMCON 253 FDH R W Pattern generation control register PGCON 254 FEH R W Pattern generation data register PGDATA 255 FFH R W ELECTRONICS 4 3 CONTROL REGISTERS Table 4 4 Page 8 Registers S3C84MB F84MB UM REV1 00 Register Name Mnemonic Decimal Hex SIO1 control register SIOCON1 0 0x00 R W SIO1 prescaler control register SIOPS1 1 0x01 RAN 5101 dat
307. wM 0 1 Data Extention Register 09H OBH PAGES RESET Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode All addressing mode Extention Bit Stretched Cycle Number 1 3 5 7 9 55 57 59 61 63 2 6 10 14 50 54 58 62 4 12 20 44 52 60 8 24 40 56 16 48 32 Not used Not used ELECTRONICS 4 37 CONTROL REGISTERS PWMCON PwM Control Register Bit Identifier RESET Value Read Write Addressing Mode 4 38 S3C84MB F84MB UM REV1 00 07H 7 6 5 4 3 2 1 0 0 0 0 0 R W R W R W R W All addressing mode Not Used Input Clock Selection Bits 0 0 0 0 0 1 fy 2 0 1 0 0 1 1 4 1 0 O fxx 5 1 0 1 fxx 6 1 1 0 fxy 7 1 1 1 fxx 8 Not Used PWM Counter Enable Bit 0 Stop Counter 1 Start Resume Counting ELECTRONICS S3C84MB F84MB UM REV1 00 CONTROL REGISTERS Register Pointer 0 D6H Set 1 Bit Identifier 7 6 5 4 3 2 0 RESET Value 1 1 0 0 0 Read Write RAN R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the reg
308. yte Slice Figure 2 8 Non Contiguous 16 Byte Working Register Block 11001 00000 PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers ADDRESS SPACES Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO R3 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS ADDRESS SPACES S3C84MB F84MB UM REV1 00 REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes
309. zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 DO R 4 D1 IR Given Register 00H 9AH register 02H 03H register O3H OBCH and 1 SRA 00H gt Register OOH OCD 0 SRA 02H gt Register 02H register C 0 In the first example if the general register 00H contains the value 9AH 10011010B the statement SRA shifts the bit values in the register right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in the destination register 00H ELECTRONICS 6 79 INSTRUCTION SET S3C84MB F84MB UM REV1 00 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples NOTE src src src If src 1 1 and src 0 Othen 3 7 lt src 3 7 If src 1 src 0 1 then RP1 3 7 lt src 3 7 If src 1 Oandsrc 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 4 7 lt src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write or both of the register pointers and RP1 Bits 3 7 of the selected register pointer are written unless both register po

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