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1. The DSP2 board was designed with terminal resistors R 1 and R_2 on channels i1 i3 udc for current input signals Since MiniSKiiP IGBT bridge provides voltage signals for 11 i3 and udc terminal resistors are not inserted Resistors R 3 and R_4 are building a voltage divider for 10V input signal R_4 doesn t have its own mounting place on PCB and must be placed on the back of C 1 24
2. 0x900007 15 14 13 12 1 10 9 8 Bll Bll Bll B11 B11 B10 B9 B8 R R R R R R R R 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO R R R R R R R R On each interrupt value from position counter is transferred to this register and COUTER IS CLEARED Position must be externally accumulated Value is 16 bit long in 2 nd 14 FPGA Registers Reference complement notation And must be extended to 32 bits with sign and added to software position value Maximal number of pulses between two interrupts must be less than 2048 pulses Input signal are sampled 15 million times every second so maximal input frequency must be under 3 75MHz In this version of FPGA firmware counter has eleven data bits and sign Incremental Encoder Time Read Register R_INC_TIME address 0x900008 15 14 13 12 11 10 9 8 STATUS 0 0 0 B11 B10 B9 B8 R R R R R R R R 7 6 5 4 3 2 1 0 B7 B6 BS B4 B3 B2 BI BO R R R R R R R R STATUS I data are invalid 0 data are valid B11 BO time between previous interrupt pulse and last pulse from incremental encoder This register is used with improved MT method for speed measurement Most significant bit is set when no pulses are received in last period from incremental encoder In this case the other bits are not valid If position was changed this register contains the time betwe
3. University of Maribor s a 2 Faculty m lectri Er gineering puter Science gt Se ee SC Ori eg rente T EPETTITDIPTIETU TIT TTITLITSIDO OPET TIT E Up YMTMSTESDUSIES M d APUD AM UM LAM MAT AVV DSP2 H User s Manual i Institute of Robotics Copyright 2001 University of Maribor Faculty of Electrical Engineering and Computer Science Institute of Robotics Smetanova ulica 17 2000 MARIBOR SLOVENIA http www ro feri uni mb si Welcome html 12 Manual version V 0 704 17 March 13 2001 Firmware version V0 80 April 17 2000 PCB version V1 00 Februar 12 2000 Bios version V1 10 Mai 12 2000 Terminal version Vl1 1a Jan 23 2000 Contents Contents AA RN ii DSP board overview Simplified Function Diagram DSP2 Memory Map Interrupts FPGA Registers Reference 5 1 5 1 1 AD Operation 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 AD Unit Register ADCTRL address 0x900002 WRITE Register ADO address 0x900001 READ ADANA A A QU N N Registers AD1 address 0x900002 AD2 address 0x900003 AD3 address 0x900004 JI Registers ADI address 0x900002 AD2 address 0x900003 AD3 address 0x900004 17C EEPROM Register W I2C address 0x90000E RegisterR I2C address 0x90000E Asynchronous Serial Communications Interface Receiver Status Register RS STAT address 0x900006 Serial Control Regist
4. B3 B2 BI BO R R R R R R R R AD BUSY A D converter status 1 conversion is in progress You must wait until bit is set 0 0 conversion finished Note Same busy bit ADO AD_BUSY is used for all four analogue converters because the conversion is simultaneous B0 B15 16 bit unsigned data udc IF AD_BUSY is 0 FPGA Registers Reference Registers AD1 address 0x900002 AD2 address 0x900003 AD3 address 0x900004 15 14 13 12 11 10 9 8 Bll Bll Bll Bll Bll B10 B9 B8 R R R R R R R R 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO R R R R R R R R AD1 AD2 and AD3 are data registers that contain AD conversion results Bit 11 is a sign bit and is extended to bits 12 thru 15 to form 2 complement Note Same busy bit ADO BUSY is used for all four analog converters because the conversion is simultaneous B0 B15 16 bit unsigned data udc IF AD_BUSY is 0 Registers AD1 address 0x900002 AD2 address 0x900003 AD3 address 0x900004 15 14 13 12 11 10 9 8 Bll Bll Bll Bll Bll B10 B9 B8 R R R R R R R R 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO R R R R R R R R AD1 AD2 and AD3 are data registers that contain AD conversion results Bit 11 is a sign bit and is extended to bits 12 thru 15 to form 2 complement Note Sa
5. 1 1 1 R R R R R R R R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R R R R R R R R Status of bridge B EN bridge enable 12 FPGA Registers Reference With bridge on and bridge off you can toggle hardware flip flop Bridge enable show the state of this flip flop State of the flip flop can also be changed with error signal from IGBT Bridge to zero Error signal in Mini SKiiP bridge includes over current earth connection sum of phase currents must be zero over heat 5 5 FLASH PROM Interface Flash PROM Register W_FLASH address 0x90000F 15 14 13 12 11 10 9 8 NC NC NC NC B11 B10 B9 B8 JW JW W JW JW JW JW JW 7 6 5 4 3 2 1 0 NC NC NC NC XXI XX6 A17 F A16 F JW JW W JW JW JW JW JW Logical outputs A16 F A16 FLASH A17 F A17 FLASH These two bits are for change page in FLASH Because only 8 bit data width FLASH is only used for boot loader program After download FLASH is disabled In future user program can be downloaded from FLASH XX6 test pin xx6 XXI test pin xxl Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware For XX6 and XX1 see section FPGA extension pins 5 6 Analog Output Unit Analog Output 0 Register DAO address 0x900000 15 14 13 12 11 10 9 8 NC NC NC NC B11 B10 B9 B8 JW JW W JW JW J
6. 16 bit User must extend read value to 32 bits depend on data type 5 1 1 AD Operation AD conversion is started by interrupt request After approximately 2 5 microseconds simultaneous conversion of all four channels is finished You have time to next interrupt to read converted data Fourth channel AD3 is connected to multiplexer which choose one of eight analogue inputs Decision is made with register ADCTRL and bits 0 to 2 Note In current version of FPGA firmware April 17 2000 A D conversion is started when write to ADCTRL register appear FPGA Registers Reference Register ADCTRL address 0x900002 WRITE 15 14 13 12 11 10 9 8 NC NC NC NC NC NC NC NC JN JW JN JN JN JN JW JN 7 6 5 4 3 2 1 0 NC NC NC NC NC AD_MUX2 AD MUXI AD MUXO JN JW JN JW JN JN JW JN Table 3 AD3 Input selection table ADCTRL AD MUX2 AD MUXI AD MUXO Analog 0x0000 0 0 0 CHO 0x0001 0 0 l CHI 0x0002 0 1 0 CH2 0x0003 0 l l CH3 0x0004 l 0 0 CH4 0x0005 l 0 l CH5 0x0006 l l 0 CH6 0x0007 1 1 1 CH7 Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware Register ADO address 0x900001 READ 15 14 13 12 11 10 9 8 ap_Busy 0 0 0 B11 B10 B9 B8 R R R R R R R R 7 6 5 4 3 2 1 0 B7 B6 BS B4
7. First order input RC filters time constant 33us for il and 13 and 100us for udc Two channel 12bit D A converter with serial input and unipolar output 0 to 4V RS232 full duplex interface with fixed Baud Rate 38400kBd 8bits 1stop No parity RS485 interface not implemented in this firmware version April 17 2000 RS422 receiver for incremental encoder Three logic inputs and one output all optically isolated 12V passive Bridge protection circuit o Interlock between bottom and top IGBT activation and dead time o Minimum pulse width minimum pause width o In the presence of fault signal the bridge is shut down unconditionally Three phase synchronous pulse width modulator o Twelve bit up down counter for triangle generation o Symmetrical output pulses o 66 6ns time resolution o can generate interrupt pulses ones or twice in one modulator period Incremental encoder speed measurement with improved MT method o 66 6ns time resolution o Position register contain position increment during sampling period o Time register contain relative time in one modulator period of last position change o Booth registers are saved on interrupt and are available until next interrupt Stand alone operation Program is preloaded in FLASH Operation with personal computer o Code Composer software development environment o Standard RS232 serial interface 38400Bd and Terminal software o MPSD interface for XDS510 emulator o Multipoint communications RS485 and CAN
8. Signal Pin Pin 5 Signal Signal a 4 GND 7 5V Connectors and Jumpers Locations Pin Signal Pin Signal Pin Signal 2 GND 5 Ri 8 b 3 b 6 a 9 i All input signals are RS422 compatible Complementary signals with TTL levels 5V power supply can provide maximum 100mA output current 64 P5IGBT Bridge digital I O Pin Signal Pin Signal Pin Signal Vpf 6 TOP3 11 VCC 2 TOPI 7 GND 12 BOT3 3 RELAY 8 BOTI 13 VCC 4 TOP2 9 GND 14 ERROR 5 GND 10 BOT2 ADM705AR R39 1 25V 1K1 Figure 7 Power Fail Input Detail If level on Vpf input is under 18V PFO is activated On PCB this signal is connected to INT3 input line of DSP But because at reset of DSP this line is used to choose boot sequence voltages on Vpf under 18V can start wrong start up sequence So PFO is disconnected from IRQ3 and left open In future this output will be connected to free pin of FPGA and with firmware in it indirectly again connected to IRQ3 Generally this is used to detect power fail few milliseconds before controller go in reset state and safely stop application R38 and R39 are placed near P1 connector bridge analogue inputs and are shown on PCB picture for fast analogue inputs TOP1 TOP2 TOP3 BOTI BOT2 and BOT3 are signals for 6 IGBT s in bridge Active is high output SV level RELAY output sign
9. supply voltage for op amp Fast analog inputs modifications 7 Fast analog inputs modifications Table 6 Normal current fast analogue input configuration R3 current input to A D converter Il B UDC BATA AGND AGND AGND AVCC AVSS T 36us T 36us T 1 10us Picture shows fast analogue input schematic R1 R10 100E R17 100E R26 100E R2 RII R18 R27 R3 R8 IKI R14 IK1 R24 IKI RA C 1 C333nF C8 33nF C19 100nF D2 connected to AVSS AVSS AGND AD converter input range 4 096 to 4 096 to 0 to 4 095V 4 094V 4 094V Current input range 40 96 to 40 96 to 0 to 40 95mA 40 94mA 40 94mA Table 7 Modified fast analogue input configuration for use with MiniSKiiP IGBT module voltage input R3 to A D converter Il I3 UDC D2 mE T 36us T 36us T 110us AGND AGND AGND AGND AVCC AVSS Picture shows fast analogue input schematic RI RIO R17 R26 R 2 RII R18 R27 R 3 R8 IKI R14 IK1 R24 IKI R 4 xx XX XX C 1 C3 33nF C8 33nF C19 100nF D2 connected to AVSS AVSS AGND AD converter input range 4 096 to 4 096 to 0 to 4 095V 4 094V 4 094V Input voltage 10to 10V 10 to 10V 0 to 10V 23
10. use SIEMENS CAN controller with multiplexed data and address bus Write is made immediately to registers in FPGA and then transferred to controller Before next operation you must check busy bit and in case if bit is set wait Read is different because with fist write you set address and after operation is complete you can read requested data in status register 16 6 Connectors and Jumpers Locations J6 TE A ors e Jas n ara P5 2222412 or n e ca x M jp p DOM e E p real M LEO J10 e loge ERI c qct a t P1 e 00 is n H ui s o o E a DE TT m e Ga 28 e H e 1 J 4 sss TTT ANT jti Jo T SERRE Em qe eee p fe e s J2 eron E T P4 e i P3 a x J9 J8 1 T J1 J7t 1000000000008 mesas Figure 6 Connectors and Jumpers Locations 6 1 P1 IGBT Bridge Analogue inputs Pin Signal Pin Signal Pin Signal 1 GND 5 AGND 9 B 2 V 6 CHI 10 UDC 3 AGND 7 Il 4 CHO 8 6 2 P3 Serial communication RS232 Pin Signal Pin Signal Pin Signal 1 4 RX SEC 7 CTS 2 IX 5 GND 8 RTS 3 RX 6 TX SEC 9 SEC can be used in future FPGA configurations for second serial interface on the same connector For this you must have Y cable to split signals 6 3 P4 Incremental encoder input Pin
11. 0x880000 Ox89FFFF RAM 128K 32bits 0x900000 Ox900FFF FPGA 16bits DSP2 Memory Map Interrupts 4 Interrupts External interrupts are controlled by firmware in FPGA In this version April 17 2000 only one interrupt INTO are generated by three phase pulse width modulator Interrupt can be generated once or twice in one modulator period Interrupt INT1 is used for boot mode select 5 FPGA Registers Reference Table 2 FPGA Register Map FPGA Registers Reference Address WRITE READ 0x900000 DAO DA_STAT 0x900001 DAI ADO udc 0x900002 ADCRTL ADI il 0x900003 TXO AD2 13 0x900004 CTRL AD3 mux 0x900005 W MOD PER RXO 0x900006 W MOD TI RS STAT 0x900007 W MOD T2 R INC POS 0x900008 W MOD T3 R INC TIME 0x900009 W MOD TM R CAN STAT 0x90000A W CAN CTRL Reserved 0x90000B Reserved Reserved 0x90000C Reserved Reserved 0x90000D Reserved Reserved 0x90000E W DC R DC 0x90000F W FLASH R MOD STAT 0x900800 W CAN R CAN Ox9008ff 5 1 AD Unit Figure 2 Analog Input Configuration Note Analogue VCC is separated Internal voltage reference is used Vss pin is connected to 5V for bipolar operation 11 13 Leading bits for udc are zero except MSB bit 15 which is 1 during A D conversion unsigned extension to 16 bits For currents measurement il and 13 leading bits bit 15 14 13 and 12 are equal to bit 11 signed extension to
12. H3 6 VCC 10 EMUO 3 GND 7 GND 11 GND 4 EMU3 8 EMU2 12 EMUI This connector is provided for C3x emulator head Emulator use simplified JTAG interface 6 8 J5 DSP Watch dog enable Pin Signal Pin Signal 1 WDI ADM705 2 XFI DSP Watchdog input on ADM705 request state change on WDI input at least every 1 6 second If this is not ensured reset signal for DSP is generated If jumper is not inserted this function did not work Current boot loader Version x xx written in FLASH did not support this function Jumper mustn t be inserted XF1 is user programmable i o pin of DSP 6 9 J6 Serial interface RS485 Pin Signal Pin Signal 1 VCC 3 A 2 A 4 GND 19 Connectors and Jumpers Locations Connector J6 provides standard RS485 serial interface with 5V power supply Firmware in FPGA April 17 2000 did not support this feature 6 10 J7 EEPROM write enable Pin Signal Pin Signal 1 WE EEPROM 2 GND If jumper is not inserted upper half Microchip or entire ST EEPROM memory is write protected 6 11 J8 optically isolated three inputs and one output Pin Signal Pin Signal Pin Signal 1 INI 5 IN3 9 OUT 2 INI 6 IN3 10 OUT 3 IN2 7 J 4 IN2 8 Those optic isolated signals are passive All Inputs request 12V Output current must be u
13. W W W 7 6 5 4 3 2 1 0 B7 B6 BS B4 B3 B2 BI BO JW JW W W JW JW JW JW B11 BO 12 bit unsigned value 0 OV 4095 4 095V Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware 13 FPGA Registers Reference Analog Output 1 Register DA1 address 0x900001 15 14 13 12 11 10 9 8 NC NC NC NC Bll B10 B9 B8 JW JW W W W W W W 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 BO JW JW W W W W W W B11 BO 12 bit unsigned value 0 OV 4095 4 095V Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware Analog Output Status Register DASTAT address 0x900000 15 14 13 12 11 10 9 8 DA_BUSY 1 1 1 1 1 1 1 R R R R R R R R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R R R R R R R R DA BUSY 1 interface busy When data is writen to second D A register serial transmit to D A converter is started and bit 15 in DASTAT is set to 1 This bit is cleared to zero when both channels are transmitted and interface is ready for new data When bit 15 in DASTAT is set writing to any of DAO or DAI is prohibited and can cause transmit of void data to DA converter 5 7 Incremental Encoder Interface Incremental Encoder Position Read Register R INC POS address
14. al active high level is used to shortcut charge resistor in DC bus ERROR is an input signal active low level to detect errors in IGBT bridge drive VCC and GND is 5V supply for this card 6 5 J1 Analogue outputs analogue inputs Pin Signal Pin Signal Pin Signal 1 V 6 OUTO 11 CH_6 2 AVSS 7 CH_2 12 CH_7 3 AGND 8 CH3 13 AGND 4 AOUT 9 CH4 14 AVCC 5 OUTI 10 CH_5 V is power supply for op amp to generate AoutZOUTO OUTI 15V OUTO OUTI 12 bit analogue outputs 0 4 095V AVSS power supply for bipolar analogue inputs 5V 18 AVCC power supply for analogue inputs 5V AGND analogue ground CH 2 3 7 slow bipolar analogue inputs input RC filter 1 1KOHM 100nF 6 6 J2DSP serial communication Pin Signal Pin Signal Pin Signal 1 VCC 4 CLKXO 7 CLKRO 2 FSXO 5 FSRO 8 GND 3 DXO 6 DRO See TMS320C32 data sheet VCC and GND is supply voltage from card 100mA max 6 7 J3 Jumpers for DSP Boot mode select Pin Signal Pin Signal Pin Signal INTO 4 GND 7 INT3 2 GND 5 ANT2 8 GND 3 ANTI 6 GND Normally jumper between pin 3 and pin 4 must be placed This causes DSP to boot from FLASH memory and starts monitor program in it 6 6 J4 MPSD emulator interface Pin Signal Pin Signal Pin Signal GND 5 NO PIN 9 GND 2
15. arge resistor for DC link OM Osingle interrupt request in one period of PWM 1 interrupt request in each half period of PWM I EN PWM interrupt enable 11 FPGA Registers Reference Important Between bridge on and hardware flip flop RC differentiator is used to prevent override of bridge error or bridge off signal Bridge on signal MUST be low few tens of microseconds before go to high to switch flip flop ON Modulator Phase 1 Pulse Width Register W_MOD_T1 address 0x900006 Modulator Phase 2 Pulse Width Register W_MOD_T2 address 0x900007 Modulator Phase 3 Pulse Width Register W MOD T3 address 0x900008 15 14 13 12 11 10 9 8 NC NC NC NC B11 B10 B9 B8 JW JW JW JW JW JW JW JW 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO W JW JW JW JW JW JW JW B11 0 modulator phase 1 2 and 3 pulse width Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware With register W_MOD_T1 output pulse width for first phase is set Unit is 66 6ns Value is between 0 and 2000 When output is I TOP IGBT is active when output is 0 active is bottom one When transition of signal appear then immediately active IGBT is inactivated and then after dead time another one is activated Modulator Status Register W_MOD_STAT address 0x90000F 15 14 13 12 11 10 9 8 B_EN 1 1 1 1
16. atel BaudRate2 Error 195 9600 9615 38 0 16 98 19200 19132 65 0 35 49 38400 38265 31 0 35 33 57600 56818 18 1 36 16 115200 117187 50 1 73 8 230400 234375 00 1 73 4 460800 468750 00 1 73 Note This feature is not implemented in firmware version April 17 2000 in FPGA Serial Receive Register RX0 address 0x900005 15 14 13 12 1 10 9 8 1 1 1 1 1 1 1 1 R R R R R R R R 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO R R R R R R R R B7 0 received byte Serial Transmit Register TX0 address 0x900003 15 14 13 12 11 10 9 8 NC NC NC NC NC NC NC NC JW JW JW JW JN JW JW JW 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO JW JW JW JW JW JW JW JW B7 0 byte to transmit Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware Receive and transmit registers are double buffered This mean that another character can be received while previous one is in the receive register You must read previous character just before next one is complete received Same thing is with transmit register When the output shift register is empty then serial transmit register is empty for new character in less than 1 16 BAUD RATE Transmission time for one character is 10 BAUD RATE 10 FPGA Registers Reference 5 4 Three Pha
17. ed by DSP 6 15 J12 FPGA external programming interface Pin Signal Pin Signal Pin Signal 1 VCC 4 Dout 7 CCLK 2 VCC 5 GND 8 Din 3 PGM 6 GND See J11 explanation 6 16 J13 two DSP timer outputs Pin Signal Pin Signal 1 TCLKO 2 TCLKI The C3x has two 32 bit general purpose timer modules Each timer has an I O pin that you can be used as an input clock to the timer as an output clock signal or as a general purpose I O pin See DSP data sheet 6 17 Power supply For board operation folowing power supply voltages must be connected Table 4 DSP2 Power supply connections Name Connector Pin V JI 1 AVSS JI AGND JI AGND JI 13 AVCC JI GND Pl 1 V P1 2 AGND Pl 3 21 Connectors and Jumpers Locations Warning Analog AGND and digital ground GND MUST be connected together 22 Name Connector Pin AGND P1 5 Vpf P5 1 GND P5 5 GND P5 6 GND PS 9 VCC P5 11 VCC P5 13 Table 5 Power supply signals explanation Name Voltage Current Explanations Vpf gt 18V 3mA Power fail detect VCC 5V 1 5A Logic power supply GND OV Logic ground V 15V 25mA Pos supply voltage for op amp AVCC 5V 150mA Pos analog supply voltage AGND OV Analog ground AVSS 5V 25mA Neg Analog supply voltage V 15V 25mA Neg
18. en previous interrupt pulse and last pulse from incremental encoder Units are same as units for PWM 66 6ns This additional register improves speed measurement particularly for low speed range 5 8 Extension IO pins on FPGA Flash PROM Register W_FLASH address 0x90000F 15 14 13 12 11 10 9 8 NC NC NC NC Bll B10 B9 B8 JW JW W JW JW JW JW JW 7 6 5 4 3 2 1 0 NC NC NC NC XX1 XX6 A17_F A16_F JW JW W JW JW JW JW JW Logical outputs A16 F A16 FLASH A17 F A17 FLASH XX6 test pin xx6 15 FPGA Registers Reference XXI test pin xxl Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware For A16 F and A17 F see section FLASH PROM Interface Figure 5 Connector with Test Pins on DSP2 Board Detail Also the other XX pins are connected to FPGA but firmware version April 17 2000 in FPGA supports only XX4 with 1 19 Hz output signal We use signals XX1 and XX6 for detection of execution times for different parts of software We connect two led diodes between XX6 pin 9 and GND pin 7 and XX4 pin 5 and GND XX1 is used to connect oscilloscope 5 9 CAN Interface Write CAN Register W_CAN address 0x900800F Read CAN Register R_CAN address 0x900800F CAN Control Register W_CAN CTRL address 0x9000A CAN Status Register W_CAN STAT address 0x900009 Firmware for CAN is implemented but is not tested yet We
19. ents of the memory from inadvertent write operations Write operations are disabled to the entire memory array when Write Control WC is driven High Jumper J7 is not inserted When Write Control WC is driven High Device Select and Address bytes are acknowledged Data bytes are not acknowledged 5 3 Asynchronous Serial Communications Interface Receiver Status Register RS STAT address 0x900006 15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 R R R R R R R R 7 6 5 4 3 2 1 0 TRF RRF OV FE 1 1 SDA 1 R R R R R R R R FE framing error invalid stop bit OV overflow previous byte is not read while new received RRF receive register full unread byte is in receive register AI three bits are cleared when receive register is read TRF transmit register full Serial Control Register CRTL address 0x900004 15 14 13 12 11 10 9 8 NC NC NC NC NC NC NC NC JW JW W JW JW JW JW JW 7 6 5 4 3 2 1 0 SRG7 SRG6 SRG5 SRG4 SRG3 SRG2 SRGI SRGO JW JW W JW JW JW JW JW SRG7 0 SELECT Baud Rate Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware Figure 4 Asynchronous Serial Communications Baud Rate Select SRG BaudRatel BaudRate2 Error FPGA Registers Reference SRG BaudR
20. er CRTL address 0x900004 ore oov v Serial Receive Register RXO address 0x900005 Serial Transmit Register TXO address 0x900003 Three Phase Pulse Width Modulator Modulator Period Register W_MOD_PER address 0x900005 Modulator Dead Time Set Register W_MOD_TM address 0x900009 Modulator Phase 1 Pulse Width Register W MOD TI address 0x900006 Modulator Phase 2 Pulse Width Register W MOD T2 address 0x900007 Modulator Phase 3 Pulse Width Register W MOD T3 address 0x900008 Modulator Status Register W MOD STAT address 0x90000F FLASH PROM Interface Flash PROM Register W FLASH address 0x90000F Analog Output Unit Analog Output 0 Register DAO address 0x900000 Analog Output 1 Register DA1 address 0x900001 Analog Output Status Register DASTAT address 0x900000 Incremental Encoder Interface Incremental Encoder Position Read Register R INC POS address 0x900007 __ Incremental Encoder Time Read Register R INC TIME address 0x900008 Extension IO pins on FPGA Flash PROM Register W FLASH address 0x90000F CAN Interface Write CAN Register W CAN address 0x900800F Read CAN Register R CAN address 0x900800F CAN Control Register W CAN CTRL address 0x9000A 10 10 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 16 16 16 16 Contents CAN Statu
21. ion DIJPrami s 5e Seq es 2 Figure 2 Analog Input Confer ation z zu esn ko uidetur Oe ee eee PA es 5 Figure 3 2C Implementation Detail irt edi Lele ride eee 8 Figure 4 Asynchronous Serial Communications Baud Rate Select eee 9 Figure 5 Connector with Test Pins on DSP2 Board Detail eese 16 Figure 6 Connectors and Jumpers Locations s oed ee sands usa sedes es ties eee de nee ol nean eed ebd a 17 Fipute 7 Power Paul Input Delall 4 3 05 hebt edei ttai lute een static 18 iii DSP board overview 1 DSP board overview The DSP 2 board is a high performance floating point digital signal processor DSP based inverter controller designed primarily to control a three phase AC motor The board is based on Texas Instruments TMS320C32 DSP and Field Programmable Gate Array FPGA XCS40 4PQ240C member of Xilinx Spartan Family DSP TMS320C32 60MHz o DSP serial interface o Two timer general purpose io pins o DSP MPSD interface for XDS510 emulator FLASH 256K x 8 70ns SRAM 128K x 32 OWS 4 channel simultaneous 12bit A D with serial output o Conversion and transfer to register in FPGA 2 6us for all four channels o One channel has unipolar input range 0 to 4 095V or 0 to 40 95mA with 100OHM shunt resistor udc o Two have bipolar input range 2 096 to 4 094V or 40 96mA to 40 94mA with 1OOOHM shunt resistor o One channel has input multiplexer to select one of eight voltage input signals o
22. me busy bit ADO BUSY is used for all four analog converters because the conversion is simultaneous FPGA Registers Reference 5 2 1 C EEPROM Register W I2C address 0x90000E 15 14 13 12 n 10 9 8 NC NC NC NC NC NC NC NC JW JN JW JW JW JW JW JW 7 6 5 4 3 2 1 0 NC NC NC NC NC NC SDA SCL JW JW JW JW JW JW JW JW Bit 0 connected to SCL line Bit 1 0 SDA pin is in THREE STATE external pull up resistor apply high logic level 1 SDA shorted to ground low logic level Note NC means not care for this firmware For future compatibility write always write 0 to NC bits Register R I2C address 0x90000E 15 14 13 12 1 10 9 8 1 1 1 1 1 1 1 1 R R R R R R R R 7 6 5 4 3 2 1 0 1 1 1 1 1 1 SDA 1 R R R R R R R R Bit 1 connected to SDA line Note Use only level of Bit 1 SDA for future compatibility I2C sck scl bscl s OBUF OPAD wr iic BUFE IBUF Figure 3 I2C Implementation Detail FPGA Registers Reference Because pin compatibility of serial I2C EEPROMs any type of memory in 8 pin SO package can be used for example M24C01 M24C02 M24C04 M24C08 M24C16 M24C32 M24C64 M24C128 M24C256 or M24512 ST Microelectronics On DSP2 M24C04 is implemented 512 bytes x 8 bits Write Control WC This input signal is useful for protecting the entire cont
23. nder 100mA 6 12 J9 CAN interface before and after line driver 16 I O user defined pins Pin Signal Pin Signal Pin Signal 1 P16 10 VCC 19 P20 2 P17 11 CRXI 20 P21 3 Pl4 12 GND 21 P22 4 P15 13 CANH 22 P23 5 P12 14 CANL 23 P24 6 P13 15 GND 24 P25 7 P10 16 GND 25 P26 8 Pll 17 CRXO 26 P27 9 VCC 18 CTX0 CAN controller is connected directly to this connector and through CAN transceiver Part of CAN controller is also 16 IO pins that are directly connected 6 13 J10 FPGA extension pins Pin Signal Pin Signal Pin Signal 1 VCC 5 XX4 P92 9 XX6 P94 2 XXI P86 FPGA 6 XX5 P89 10 XX9 P95 3 XX2 P88 7 GND 1 XX10 P97 4 XX3 P87 8 XX7 P93 12 XX8 P95 All pins can be freely configurable by FPGA firmware 20 FPGA Firmware version April 17 2000 supports only 1 19 Hz output signal on XX4 and signals XX1 and XX6 as test pins see Flash PROM Register W FLASH For example we can use one test pin for detection of execution times for different parts of software 6 14 J11 FPGA JTAG interface Pin Signal Pin Signal Pin Signal 1 TMS 4 VCC 7 RST 2 TDO 5 TDI 8 GND 3 TCK 6 This interface is provided for FPGA firmware development and is not needed in regular operation of the DSP2 board FPGA is initialis
24. not implemented yet Board dimensions 161 x 130 mm Simplified Function Diagram 2 Simplified Function Diagram n Power supply E 256x8 i supervisor Q RA insane 60 z 128K x 32 h x a EEPROM L 5 4 256kb 9o 2 oo re 16 XDS510 oo oo MPSD Port ZK SAE81C90 Z IIS as HW interface O 3 m MT INTERLOCK P nik gt x ADM232A R5252 DEAD Z e K interface PERIOD r XilinX O a XCS40PQ240 INCR ENC A E ES LTC485 RD interface RS422 KO Y interface Z T Nn lt K Boundary A D D A Dl E Scan Logic interface interface a Y lt A D A D A D A D ees E ES ed ee alae D A D A OOkS s 12bit 12bit 12bit 12bit 12bic d2tsit MUX LPF LPF LPF LPF V 0 10V 10V 10V 8x 10V r 10 5V 5 5V 0 5 V 43xIN IxouT Figure 1 DSP2 Function Diagram DSP2 Memory Map Table 1 DSP2 Memory Map 0x810000 Ox82FFFF FLASH 128K 8 bits
25. s Register W_CAN STAT address 0x900009 16 6 Connectors and Jumpers Locations 17 6 1 P1 IGBT Bridge Analogue inputs 17 6 2 P3 Serial communication RS232 17 6 3 P4 Incremental encoder input 17 6 4 P5 IGBT Bridge digital I O 18 6 5 J1 Analogue outputs analogue inputs 18 6 6 J2 DSP serial communication 19 6 7 J3 Jumpers for DSP Boot mode select 19 6 6 J4 MPSD emulator interface 19 6 8 J5 DSP Watch dog enable 19 6 9 X J6 Serial interface RS485 19 6 10 J7 EEPROM write enable 20 6 11 J8 optically isolated three inputs and one output 20 6 12 J9 CAN interface before and after line driver 16 I O user defined pins 20 6 13 J10 FPGA extension pins 20 6 14 J11 FPGA JTAG interface 21 6 15 J12 FPGA external programming interface 21 6 16 J13 two DSP timer outputs 21 6 17 Power supply 21 7 Fast analog inputs modifications 23 8 References 25 Tables able lis DSP2 Memory Map marianna eet Secon oc om t a k east fee idees dates 3 Table 2 FPGA Register Map netto doku ba end eM lee eA tel oa eda 5 Table 3 AD3 Input selection table anu eiecti e ae Geile ee 6 Table 4 DSP2 Power supply connections pee persto ter ted aerei ada Poeta bd aer laren 2l Table 5 Power supply signals explanation 2 20020 tide rl erit eee eae a ee 22 Table 6 Normal current fast analogue input configuration eee 23 Table 7 Modified fast analogue input configuration for use with MiniSKiiP IGBT module 23 Figures Figure 1 DSP2 Funct
26. se Pulse Width Modulator Modulator Period Register W_MOD_PER address 0x900005 15 14 13 12 11 10 9 8 NC NC NC NC Bll B10 B9 B8 JW JW JW JW JW JW JW JW 7 6 3 4 3 2 1 0 B7 B6 BS B4 B3 B2 BI BO JW JW JW W JW JW JW JW B11 0 modulator period Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware PERIOD register Half period of PWM is equal PERIOD 1 while whole period is 2 PERIOD 1 Values for this register must be between 2 and 2000 Unit for period is 1 60MHz 4 66 6ns Modulator Dead Time Set Register W_MOD_TM address 0x900009 15 14 13 12 1 10 9 8 NC NC NC LEN OM RELAY BOFF BON JW JW JW W W JW JW JW 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 Bl BO JW JW JW JW JW JW JW JW B7 0 modulator period Note Use 0 for all unused bits for future FPGA configurations compatibility NC means not care for this firmware TM register B7 0 dead time between top and bottom switch in bridge another hardware protection implemented in GAL circuit limit dead time to about 3 5micro second minimum RC time constant TM is used because RC constant is not enough accurate approximately 10 Unit is 50ns Value must be between 0 and 255 Same register contain logic output bits B ON bridge on B OFF bridge off RELAY relay for by pass ch
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