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1. PORT declarations input input 15 0 DATA1 input 15 0 DATA2 output OREAD_SDRAM_EN output 7 0 oLCD output 7 0 oLCD G output 7 0 oLCD B output oHD output oVD output oDEN EE e REG WIRE declarations fe reg 10 0 x cnt reg 9 0 y cnt wire 7 0 read red wire 7 0 read green wire 7 0 read blue wire display area wire oREAD SDRAM EN reg mhd reg mvd reg oHD reg oVD reg oDEN reg 7 0 oLCD R reg 7 0 oLCD G reg 7 0 oLCD B ________________________________________________ Structural coding EE e This signal control reading data form SDRAM if high read color data form sdram assign oREAD SDRAM EN x_cnt gt Hsync_Blank 2 amp amp x_cnt lt H_LlNE Hsync_Front_Porch 1 amp amp y_cnt gt Vertical_Back_Porch 1 amp amp y_cnt lt V_LINE Vertical_Front_Porch 1 b1 1 bO This signal indicate the display area assign display area x_cnt gt Hsync_Blank 1 amp amp gt 215 x_cnt lt H_LINE Hsync_Front_Porch amp amp lt 1016 y_cnt gt Vertical_ Back Porch 1 amp amp cnt V LINE Vertical Front Porch 1 b1 1 b0 PED S D Ina pip
2. Figure 3 3 System Structure The LTM consists of three major components LCD touch panel module AD converter and 40 pin expansion header All of the interfaces on the LTM are connected to Altera DE2 board via the 40 pin expansion connector The LCD and touch panel module will take the control signals provided directly from FPGA as input and display images on the LCD panel Finally AD converter will convert the coordinates of the touch point to its corresponding digital data and output to the FPGA via the expansion header The feature set of the LTM is listed below 1 Equipped with Toppoly TD043MTEA active matrix color LCD module 2 Support 24 bit parallel RGB interface 3 3 wire register control for display and function selection 4 Built in contrast brightness and gamma modulation 5 Converting the X Y coordination of the touch point to its corresponding digital data via the Analog Devices AD7843 AD converter 6 The general specifications of the LTM are listed below Item Description Unit Display Size Diagonal 4 3 Inch Aspect ratio 15 9 Display Transmissive Active Area HxV 93 6 x 56 16 mm Number of Dots HxV 800 x RGB x480 dot Table 3 1 general specifications of the LTM 4 Design 4 1 Game Logic 4 1 1 Introduction The game is an extension of the real Ping Pong game There are two players fighting against each other Players would use their fi
3. LO QN DRALUOGM TRALCARN TRALRARN DRAULCSN port 31 0 4 3 Software In the whole project the most important is the FPGA and the touch panel part Hence we didn t put our main effort on the software part Although we just designed the basic function of the gain it still took loads of efforts Our software part can be divided into two parts interrupt part game control part 4 3 1 Interruption Design In order to acknowledge the touch on touch panel we write this the interrupt code Actually there existing a transform mechanism in DE2 which can transfer the interrupt from the touch panel to the PIO interrupt Thus using interrupt from PIO ports is indirectly use interrupt from the touch panel which makes the design work much easier In this code we referenced the interrupt of using key to control LED Edge capture register Synchronously capture 2 Rising edge O Falling edge Either edge Enable bit clearing for edge capture register Interrupt Generate IRQ O Level interrupt CPU when any unmasked pin is logic true Edge Interrupt CPU when any unmasked bit in the edge capture register is logic true Interruption setting of PIO edgecapture Register in the edgecapture register is set to 1 whenever edge is detected on input port n An Avalon MM master
4. EERE f wire 10 0 x_cord_pong wire 9 0 y_cord_pong assign x_cord_pong pio_pingpang 10 0 215 11 d400 assign y_cord_pong pio_pingpang 20 11 35 10 d150 wire en_pong assign en_pong x_cnt gt x_cord_pong amp amp x_cnt lt x_cord_pong 30 amp amp y_cnt gt y_cord_pong amp amp y_cnt lt y_cord_pong 30 1 b1 1 b0 wire 9 0 addr_pong assign addr_pong x_cnt x_cord_pong y_cnt y_cord_pong 30 wire 7 0 red_pong rom pong ii address addr pong clock iCLK q red pong IIT T TH T T VIII MIT M IM I T I OCIO IO REELS EL wire 10 0 1 wire 9 0 y cord score1 assign x cord score1 11 d520 assign y cord score1 10 d50 wire en 5 1 assign en 5 1 cnt x cord scorel amp amp x cnt zx cord 5 1 20 amp amp y_cnt gt y_cord_score1 amp amp y_cnt lt y_cord_score1 20 1 b1 1 b0 wire 9 0 addr_score1 assign addr_score1 x_cnt x_cord_score1 y_cnt y_cord_score1 20 EEA re 2 a a wire 10 0 x_cord_score2 wire 9 0 y_cord_score2 assign x_cord_score2 11 d540 assign y_cord_score2 10 d50 wire en_score2 assign en_score2 x_cnt gt x_cord_score2 amp amp x_cnt lt x_cord_score2 20 amp amp y_cnt gt y_cord_score2 amp amp y_cnt lt y_cord_score2 20 1
5. Sdram write enable control always posedge iF_CLK or negedge iRST_n begin if liRST n oSDRAM WRITE EN lt 0 else if flash lt flash max 1 amp amp write cnt lt DISP MODE begin oSDRAM WRITE EN lt 1 end else oSDRAM WRITE EN lt 0 end delay flash data for aligning RGB data always posedge iF or negedge iRST n begin if liRST n begin fl dq delay1 lt 0 fl dq delay2 lt O fl dq delay3 lt O end else begin fl dq delay1 lt FL DQ fl delay2 lt fl dq delavi fl delay3 lt fl dq delay2 end end always posedge iF or negedge iRST begin if liRST n flash addr cnt lt 0 else if flash addr lt flash addr begin if flash addr cnt 2 flash_addr_cnt lt 0 else flash_addr_cnt lt flash_addr_cnt 1 end else flash_addr_cnt lt 0 end always posedge iF_CLK or negedge iRST_n begin if iRST n begin write cnt lt 0 mrgb sync 0 end else if oBDRAM WRITE begin if flash addr cnt 1 begin write cnt lt write cnt 1 mrgb sync 1 end else mrgb sync 0 end else begin write cnt lt 0 mrgb sync 0 end end always posedge iF or negedge iRST n begin if iRST n rgb sync lt 0 else rgb sync lt mrgb sync end always posedge iF or negedge iRST n begin if iRST_n beg
6. 7 SEG Dispaly output 6 0 HEXO Seven Segment Digit 0 output 6 0 HEX1 Seven Segment Digit 1 output 6 0 HEX2 Seven Segment Digit 2 output 6 0 HEX3 Seven Segment Digit 3 output 6 0 HEX4 Seven Segment Digit 4 output 6 0 HEX5 Seven Segment Digit 5 output 6 0 HEX6 Seven Segment Digit 6 output 6 0 HEX7 Seven Segment Digit 7 SDRAM Interface inout 15 0 DRAM DQ SDRAM Data bus 16 Bits output 11 0 DRAM_ADDR SDRAM Address bus 12 Bits output DRAM_LDQM SDRAM Low byte Data Mask output DRAM_UDQM SDRAM High byte Data Mask output DRAM_WE_N SDRAM Write Enable output DRAM CAS N SDRAM Column Address Strobe output DRAM RAS N SDRAM Row Address Strobe output DRAM CS N SDRAM Chip Select output DRAM_BA_0 SDRAM Bank Address 0 output _ _1 SDRAM Bank Address 0 output DRAM_CLK SDRAM Clock output DRAM_CKE SDRAM Clock Enable Flash Interface inout 7 0 FL_DQ FLASH Data bus 8 Bits output 21 0 FL ADDR FLASH Address bus 22 Bits output FL WE N FLASH Write Enable output FL_RST_N output FL_OE_N output FL_CE_N GPIO inout 350 0 SRAM Interface FLASH Reset FLASH Output Enable FLASH Chip Enable GPIO Connection 0
7. Internal refresh timer refresh request REF_ACK lt 1 else if do_refresh 1 do_reada 1 do_writea 1 do_precharge 1 externa commands do_load_mode CM_ACK lt 1 else begin REF_ACK lt 0 CM_ACK lt 0 end end end This always block generates the address cs cke and command signals ras cas wen always posedge CLK begin if RESET_N 0 begin SA lt 0 BA lt 0 CSN lt 1 RAS_N lt 1 CAS N lt 1 WEN lt 1 lt 0 else begin CKE lt 1 Generate SA if do_writea 1 do_reada 1 so present the row address SA lt rowaddr else SA lt coladdr address if do_rw 1 do_precharge SA 10 lt ISC PM read write or for a precharge all command is in page mode ACTIVATE command is being issued else alway present column set SA 10 for autoprecharge don t set it if the controller if do_precharge 1 do_load_mode 1 BA lt 0 precharge or load_mode command else BA lt bankaddr 1 0 address bits Set BA 0 if performing a else set it with the appropriate if do_refresh 1 do_precharge 1 do_load_mode 1 do_initial 1 CS_N lt 0 both chip selects if performing else precharge all or load_mode begin CS N 0 lt SADDR ASIZE 1 chip selects based off of the Select refresh else set the CS N 1 lt SADDR ASIZE 1 msb address
8. else score1 0 score2 count_l if count_r 11 count_l 11 flag 0 x_pingpong center_x y_pingpong center_y right_x 650 right_y 150 left_x 100 left_y 150 Icd_spi_controller module Icd_spi_cotroller Host Side iCLK iRST n 3wire interface side SCLK io3WIRE_SDAT o3WIRE_SCEN o3WIRE_BUSY_n parameter LUT_SIZE 20 Total setting register numbers PORT declarations Host Side output o3WIRE_BUSY_n input iCLK input iRST_n 3wire interface side output 5 inout io3WIRE SDAT output SCEN Internal Registers Wires REG WIRE declarations reg m3wire str wire m3wire rdy wire m3wire ack wire m3wire clk reg 15 0 m3wire data reg 15 0 lut data reg 5 0 lut index reg 3 0 msetup st reg BUSY n wire v reverse display Vertical reverse function wire h reverse display Horizontal reverse function wire 9 0 g0 wire 9 0 g1 wire 9 0 g2 wire 9 0 g3 wire 9 0 g4 wire 9 0 g5 wire 9 0 g6 wire 9 0 g7 wire 9 0 g8 wire 9 0 g9 wire 9 0 210 wire 9 0 g11 assign h reverse 1 b0 assign v reverse 1 b1 enable vertical reverse display function three wire controller uO HostSide iCLK iCLK iRST iRST_n iDATA m3wire data iSTR m3wire str oACK m3wire oRDY m3wire oCLK m3wire SerialSide
9. rRD1_ADDR rRD1_MAX_ADDR rRD2_ADDR rRD2_MAX_ADDR lt rWR1_LENGTH rRD1_LENGTH rWR2_LENGTH rRD2_LENGTH begin Write Side 1 if WR1_LOAD begin rWR1_ADDR lt rWR1_LENGTH end 0 800 480 22 h100000 22 h100000 800 480 0 800 480 22 h100000 22 h100000 800 480 lt 128 lt 128 128 128 WR1_ADDR lt WR1_LENGTH else if MWR_DONE amp WR_MASK 0 begin if rWR1 ADDR rWR1 MAX ADDR rWR1 LENGTH rWR1_ADDR lt rWR1 ADDR rWR1 LENGTH else rWR1_ADDR lt WR1_ADDR end Write Side 2 if WR2 LOAD begin rWR2 ADDR lt WR2 ADDR rWR2 LENGTH lt WR2 LENGTH end else if mwWR DONE amp WR MASKILI begin 2 ADDR rWR2 MAX ADDR rWR2 LENGTH rWR2 ADDR lt rWR2 ADDR rWR2_ LENGTH else rWR2 ADDR lt WR2 ADDR end Read Side 1 if RD1_LOAD begin rRD1 ADDR lt RD1 ADDR rRD1_LENGTH lt RD1_LENGTH end else ifmRD_DONE amp RD_MASK 0O begin if rRD1_ADDR lt rRD1_MAX_ADDR rRD1_LENGTH rRD1_ADDR lt rRD1_ADDR rRD1_LENGTH else rRD1_ADDR lt RD1_ADDR end Read Side 2 if RD2_LOAD begin rRD2_ADDR lt RD2_ADDR rRD2_LENGTH lt RD2 LENGTH end else if mRD_DONE amp RD_MASK 1 begin if rRD2_ADDR lt rRD2_MAX_ADDR rRD2_LENGTH rRD2_ADDR lt rRD2 ADDR rRD2 LENGTH else rRD2_ADDR lt RD2 ADDR end end end Auto Read Write Control alwaysO posedge CLK negedge RESET N begin if IRESET N begin mWR mR
10. 4100 end else begin if iSTR begin if mST lt 17 mST lt mST 1 b1 if mST 0 begin mSEN lt 120 mSCLK lt 191 end else if mST 8 mACK lt SDA else if mST 16 amp amp mSCLK begin mSEN lt 1 bl mSCLK lt 1 b0 end if mST lt 16 mSDATA lt iDATA 15 mST end else begin mSEN lt 1 b1 mSCLK lt 1 b0 mSDATA lt l bz mACK lt 1 b0 mST lt 4400 end end end assign oACK assign oRDY 17 assign oSCEN mSEN assign oSCLK mSCLK amp assign SDA mST 8 1 bz mST 17 assign oCLK endmodule Icd_timing_controller module Icd timing controller iCLK LCD display clock iRST_n systen reset SDRAM SIDE iREAD_DATA1 G color data form sdram iREAD_DATA2 B color data form sdram oREAD SDRAM EN read sdram data control signal LCD SIDE oHD LCD Horizontal sync oVD LCD Vertical sync oDEN LCD Data Enable OLCD_R LCD Red color data oLCD G LCD Green color data oLCD B LCD Blue color data pio racket left pio racket right pio pingpang pio hex input 31 0 pio racket left input 31 0 pio racket right input 31 0 pio pingpang input 15 0 pio hex parameter H LINE 1056 parameter V LINE 525 parameter Hsync Blank 216 parameter Hsync Front Porch 40 parameter Vertical Back Porch 35 parameter Vertical Front Porch 10
11. 6 h11 2 b01 g0 9 8 g1 9 8 g2 9 8 g3 9 8 6 h12 2 b01 g4 9 8 g5 9 8 g6 9 8 g7 9 8 6 h13 2 b01 g8 9 8 g9 9 8 g10 9 8 g11 9 8 6 h14 2 b01 g0 7 0 6 h15 2 b01 g1 7 0 6 h16 2 b01 g2 7 0 6 h17 2 b01 g3 7 0 6 h18 2 b01 g4 7 0 6 h19 2 b01 g5 7 0 6 h1a 2 b01 g6 7 0 6 h1b 2 b01 g7 7 0 6 h1c 2 b01 g8 7 0 6 h1d 2 b01 g9 7 0 6 h1e 2 b01 g10 7 0 6 h1f 2 D01 g11 7 0 6 n20 2 b01 4 hf 4 hO 6 h21 2 b01 4 hf 4 h0 6103 2 b01 8 hdf 6 102 2 b01 8 h07 6 h04 2 b01 6 b000101 v_reverse h_reverse 16 h0000 VIII TT TH T T endmodule DE2 LTM Ephoto module DE2 LTM Ephoto Clock Input CLOCK 27 27 MHz CLOCK_50 50MHz EXT_CLOCK External Clock III 1111111111111 Push Button KEY Pushbutton 3 0 Switch SW Toggle Switch 17 0 7 SEG Dispaly HEXO Seven Segment Digit 0 HEX1 Seven Segment Digit 1 HEX2 Seven Segment Digit 2 HEX3 Seven Segment Digit 3 HEX4 HEX5 HEX6 HEX7 ITT DRAM_DQ DRAM_ADDR DRAM_LDQM DRAM_UDQM DRAM_WE_N DRAM_CAS_N DRAM_RAS_N DRAM_CS_N 0 1 Flash Interface FL_DQ FL_ADDR FL_WE_N FL_RST_N FL_OE_N FL CE GPIO 0 III 1111111111111 SRAM Interface SRAM DQ SRAM_ADDR SRAM_UB_N
12. delay3 reg 18 0 write reg 7 0 oRED reg 7 0 OGREEN reg 7 0 oBLUE reg 22 0 flash_addr_o wire 22 0 flash_addr_max wire 22 0 flash_addr_min reg 2 0 d1_photo_num reg 2 0 d2_photo_num reg photo_change reg rgb_sync reg mrgb_sync assign assign assign assign assign assign oFLWE_N 1 oFL RST n 1 oFLOEN 0 oFL O oFL ADDR sflash o flash addr max 54 3 DISP_MODE 92 photo 1 54 bmp file header 3 x 800x480 3 800x480 pictures assign flash addr 54 3 DISP_MODE NUM always posedge iF CLK or negedge iRST_n begin end if iRST_n begin d1_photo_num lt 0 d2_photo_num lt 0 else begin d1_photo_num lt iPHOTO_NUM d2_photo_num lt d1_photo_num end This is photo change detection always posedge iF_CLK or negedge iRST_n begin end if iRST_n photo_change lt 0 else if d1_photo_num iPHOTO_NUM photo_change lt 1 else photo_change lt 0 If changing photo flash min amp flash_addr_max amp flash_addr_owill chagne if flash addr o lt flash_addr_max starting read flash data always posedge iF_CLK or negedge iRST_n begin if HiRST n flash_addr_o lt flash_addr_min else if photo_change flash_addr_o lt flash_addr_min else if flash_addr_o lt flash addr max flash addr o lt flash_addr_o 1 end
13. en_score lt 1 num lt HEX 15 12 end else begin addr_score lt 0 en_score lt 0 end wire 7 0 reg_score choose_display ii3 CIK iCLK rstn iRST_n num num addr addr score data out reg score g gt el cL lt ET ERLE wire 10 0 x_cord_racket1 wire 9 0 y_cord_racket1 assign x_cord_racket1 pio_racket_left 10 0 215 11 d300 assign y_cord_racket1 pio_racket_left 20 11 35 10 d150 wire en_racket1 assign en_racket1 x_cnt gt x_cord_racket1 amp amp x_cnt lt x_cord_racket1 50 amp amp y_cnt gt y_cord_racket1 amp amp y_cnt lt y_cord_racket1 50 1 b1 1 b0 wire 14 0 addr_racket1 assign addr_racket1 x_cnt x_cord_racket1 y_cnt y_cord_racket1 50 wire 10 0 x_cord_racket2 wire 9 0 y_cord_racket2 assign x_cord_racket2 pio_racket_right 10 0 215 11 d800 assign y_cord_racket2 pio_racket_right 20 11 35 10 d150 wire en_racket2 assign en_racket2 x_cnt gt x_cord_racket2 amp amp x_cnt lt x_cord_racket2 50 amp amp y_cnt gt y_cord_racket2 amp amp y_cnt lt y_cord_racket2 50 1 b1 1 b0 wire 14 0 addr_racket2 assign addr_racket2 x_cnt x_cord_racket2 y_cnt y_cord_racket2 50 wire en_racket en_racket1 en_racket2 reg 14 0 addr racket always if en racket1 addr_ra
14. 1 0 1 0 inout DSIZE 1 0 output output output output Internal Registers Wires DSIZE 8 1 0 Controller reg reg reg reg reg reg reg reg reg reg reg reg reg reg reg reg reg SDR_CLK reg SDR_CLK reg capture reg reg 9 0 T ASIZE 1 0 8 0 T ASIZE 1 0 ASIZE 1 0 8 0 ASIZE 1 0 ASIZE 1 0 8 0 ASIZE 1 0 ASIZE 1 0 8 0 ASIZE 1 0 ASIZE 1 0 8 0 1 0 1 0 BA CS N CKE RAS N CAS N WE N DQ DQM SDR_CLK CLK_33 CLK mADDR mLENGTH rWR1 ADDR MAX ADDR rWR1 LENGTH rWR2 ADDR rWR2 ADDR rWR2 LENGTH rRD1 ADDR rRD1 ADDR rRD1 LENGTH rRD2_ADDR rRD2_MAX_ADDR rRD2_LENGTH WR_MASK RD_MASK mWR_DONE mRD_DONE mWR Pre_WR mRD Pre_RD ST SDRAM bank address SDRAM Chip Selects SDRAM clock enable SDRAM Row address SDRAM Column address SDRAM write enable SDRAM data bus SDRAM data mask lines SDRAM clock LCD clock nternal address Internal length Register write address Register max write address Register write length Register write address Register max write address Register write length Register read address Register max read address Register read length Register read address Register max read address Register read length Write port active mask Read port active mask Flag write done
15. 1 pulse Flag read done 1 pulse Internal WR edge Internal RD edge capture Controller status reg 1 0 reg reg reg reg reg DSIZE 1 0 wire DSIZE 1 0 wire f DSIZE 1 0 wire DSIZE 1 0 wire acknowledgement DRAM Control reg DSIZE 8 1 0 reg 11 0 reg 1 0 reg 1 0 reg reg Strobe reg Strobe reg wire DSIZE 1 0 wire DSIZE 8 1 0 wire 11 0 wire 1 0 wire 1 0 wire wire Strobe wire Strobe wire FIFO Control reg read side fifo reg write side fifo wire 15 0 wire 15 0 wire 15 0 wire 15 0 DRAM Internal Control wire ASIZE 1 0 CMD STOP PM DONE Read Write mDATAOUT mDATAIN mDATAIN1 mDATAIN2 CMDACK 5 CS_N CKE RAS_N 5 WE DQOUT IDQM ISA IBA ICS_N ICKE IRAS_N ICAS_N IWE_N OUT_VALID IN_REQ write side fifo rusedwi read side fifo wusedwi write side rusedw2 read side fifo wusedw2 saddr Controller command Flag page mode stop Flag page mode done Flag read active Flag write active Controller Data output Controller Data input Controller Data input 1 Controller Data input 2 Controller command SDRAM data mask lines SDRAM address output SDRAM bank address SDRAM Chip Selects SDRAM clock enable SDRAM Row address SDRAM Column address SDRAM write enable SDRAM data out link SDRAM data mas
16. ASIZE 1 0 input 8 0 input clear input output output 15 0 FIFO Read Side 2 output DSIZE 1 0 input input ASIZE 1 0 input ASIZE 1 0 input 8 0 input clear input output output 15 0 SDRAM Side output 11 0 WR1 WR1_ADDR WR1_MAX_ADDR WR1_LENGTH WR1_LOAD WR1_CLK WR1_FULL WR1_USE WR2_DATA WR2 WR2_ADDR WR2_MAX_ADDR WR2_LENGTH WR2_LOAD WR2_CLK WR2_FULL WR2_USE RD1_DATA RD1 RD1_ADDR RD1_MAX_ADDR RD1_LENGTH RD1_LOAD RD1 CLK RD1 RD1 USE 2 DATA RD2 RD2 ADDR RD2 MAX ADDR RD2 LENGTH 2 LOAD RD2_CLK RD2_EMPTY RD2_USE SA Write Reguest Write start address Write max address Write length Write register load amp fifo Write fifo clock Write fifo full Write fifo usedw Data input Write Reguest Write start address Write max address Write length Write register load amp fifo Write fifo clock Write fifo full Write fifo usedw Data output Read Reguest Read start address Read max address Read length Read register load amp fifo Read fifo clock Read fifo empty Read fifo usedw Data output Read Reguest Read start address Read max address Read length Read register load amp fifo Read fifo clock Read fifo empty Read fifo usedw SDRAM address output output output output output Strobe output Strobe output
17. As soon as the bit stream is downloaded into the FPGA the register values of the LCD driver IC using to control the LCD display function will be configured by the LCD_SPI_Controller block which uses the serial port interface to communicate with the LCD driver IC Meanwhile the Flash to SDRAM Controller block will read the RGB data of one picture stored in the Flash and then write the data into SDRAM buffer Accordingly both the synchronous control signals and the picture data stored in the SDRAM buffer will be sent to the LTM via the LCD_Timing_Controller block When users touch LTM screens the x and y coordinates of the touch point will be obtained by the ADC_SPI Controller block through the serial port interface Then the Touch_Point_Detector block will determine whether these coordinates are in a specific range If the coordinates fit the range the Touch_Point_Detector block will control the Flash to SDRAM Controller block to read the next or previous picture s data from the Flash and repeat the steps as mentioned before to command the LTM to display the next or previous picture The block diagram of the system is listed below 40 pin expansion connectore Serial port interface s LCD touch Synchronous timing signals and panel RGB data wo To Altera DE2 DE1 expansion connector Analog coordinates signals AD convertere Serial port interface
18. if do_writea 1 OE generation for page mode accesses oe4 1 else if do_precharge 1 do_reada 1 do_refresh 1 do_initial 1 PM_STOP 1 oe4 lt 0 OE lt 0 4 This always block tracks the time between the activate command and the subsequent WRITEA or READA command RC shift register is set using the configuration register setting SC_RCD The shift register is loaded with a single 1 with the position within the register dependent SC_RCD When the 1 is shifted out of the register it sets so_rw which triggers a writea or reada command always posedge CLK negedge RESET_N begin if RESET_N 0 begin rw_shift lt 0 do_rw lt 0 end else begin if do_reada 1 do_writea 1 begin if SC_RCD 1 Set the shift register do_rw lt 1 else if SC_RCD 2 rw_shift lt 1 else if SC_RCD 3 rw_shift lt 2 end else begin rw_shift lt rw_shift gt gt 1 do_rw lt rw_shift 0 end end end This always block generates the command acknowledge _ signal also generates the acknowledge signal REF_ACK that acknowledges a refresh request that was generated by the internal refresh timer circuit always posedge CLK or negedge RESET_N begin if RESET_N 0 begin lt 0 lt 0 else begin if do_refresh 1 amp REF_REQ 1
19. oFL_ADDR oFL_WE_N oFL_RST_n oFL_OE_N oFL_CE_N Sdram side oSDRAM_WRITE_EN oSDRAM_WRITE ORED OGREEN PARAMETER declarations parameter DISP_MODE 800 480 PORT declarations input iRST_n System reset input 3 0 iPHOTO NUM Picture status input iF_CLK Flash read clcok inout 7 0 FL DO FLASH Data bus 8 Bits output 22 0 oFL ADDR FLASH Address bus 22 Bits output oFL FLASH Write Enable output oFL_RST_n FLASH Reset output oFL_OE_N FLASH Output Enable output oFL_CE_N FLASH Chip Enable output oSDRAM WRITE EN SDRAM write enable control signal output oSDRAM WRITE SDRAM write signal output 7 0 oRED Image red color data to sdram output 7 0 OGREEN Image green color data to sdram output 7 0 OBLUE Image blue color data to sdram REG WIRE declarations reg oSDRAM_WRITE_EN reg oSDRAM_WRITE reg 1 0 flash_addr_cnt reg 7 0 delavi reg 7 0 fl delay2 reg 7 0 fl
20. the project will involve both hardware set up and software programming Especially due to the control of the touch screen the hardware set up will take the most of the work For the hardware part the major workload is to set up the touch screen and interface Moreover the display of the game graphics can also take some efforts For the software part the difficulty lies in how we realize the algorithm of the Ping pong Game What s more we need add interruption to transmit the coordinate of racket and ball 3 Architecture In this project there are two major hardware devices FPGA board and LTM touch screen Incorporate VGA display with the TRDB_LTM Kit to develop the application using a digital touch panel on an Altera DE2 board VHDL compiled with Quartus 7 2 and Nios ID will be used for the inter connections of hardware C will be also employed to handle the hardware implementation Terasic LCD Touch Panel Module LTM board is a displayer and a controller A40 pin IDE cable will be used for connecting between the LTM and the board The figure below is the block diagram of the Touch Screen Processor architecture Figure 3 1 Touch Screen Processor The figure below shows the block diagram of the photo demonstration Borad TCN SPI Controller AHC SPI Controller LCD Timing Muti Port Flash to Controller SDRAM SDRAM _ Figure 3 2 block diagram of the photo demonstration
21. 0 do_refresh lt 1 else do_refresh lt 0 if READA 1 amp command done 0 amp do_reada 0 amp rp_done 0 amp REF REQ 0 begin do_reada lt 1 ex_read lt 1 end else do_reada lt 0 if WRITEA 1 amp command_done 0 amp do_writea 0 amp rp_done 0 _ 0 WRITEA begin do_writea lt 1 ex_write lt 1 end else do_writea lt 0 if PRECHARGE 1 amp command_done 0 amp do_precharge 0 PRECHARGE do_precharge lt 1 else do_precharge lt 0 if LOAD_MODE 1 amp command_done 0 do_load_mode 0 LOADMODE do_load_mode lt 1 else do_load_mode lt 0 set command_delay shift register and command_done flag The command delay shift register is a timer that is used to ensure that the SDRAM devices have had sufficient time to finish the last command if do_refresh 1 do_reada 1 do_writea 1 do_precharge 1 do_load_mode 1 begin command_delay lt 8 b11111111 command done lt 1 rw_flag lt do_reada end else begin command_done lt command delay 0 the command delay shift operation command delay lt command delay 1 end start additional timer that is used for the refresh writea reada commands if command delay 0 0 amp command done 1 begin shift lt 4 b1111 rp done lt 1 end el
22. OSCEN o3WIRE SCEN SDA io3WIRE_SDAT oSCLK o3WIRE_SCLK UNIT Config Control always posedge m3wire_clk or negedge iRST_n begin if liRST n begin lut lt 0 msetup_st lt 0 m3wire_str lt 0 O3WIRE_BUSY_n lt 0 end else begin if lut_index lt LUT_SIZE begin O3WIRE_BUSY_n lt 0 case msetup_st 0 begin msetup_st lt 1 end 1 begin msetup_st lt 2 end 2 begin m3wire data lt lut data m3wire str lt 1 msetup st lt 3 end 3 begin if m3wire_rdy begin if m3wire_ack msetup_st lt 4 else msetup_st lt 0 m3wire_str lt 0 end end 4 begin lut_index lt index 1 msetup_st lt 0 end endcase end else O3WIRE_BUSY_n lt 1 end end assign 60 106 assign 61 200 assign 62 289 assign 63 375 assign 64 460 assign 65 543 assign 66 625 assign 67 705 assign 68 785 assign 69 864 assign 610 942 assign 611 1020 Config Data LUT IM always begin case lut_index 0 lut_data 1 lut_data 2 lut_data 3 lut_data 4 lut_data 5 lut_data 6 lut_data 7 lut_data 8 lut_data 9 lut_data 10 lut_data 11 lut_data 12 lut_data 13 lut_data 14 lut_data 15 lut_data 16 lut_data 17 lut_data 18 lut_data 19 lut_data default lut_data endcase end lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt
23. SRAM_LB_N SRAM_WE_N SRAM_CE_N SRAM_OE_N pio_racket_left pio_racket_right pio_pingpong pio_hex SDRAM Interface Seven Segment Digit 4 Seven Segment Digit 5 Seven Segment Digit 6 Seven Segment Digit 7 SDRAM Data bus 16 Bits SDRAM Address bus 12 Bits SDRAM Low byte Data Mask SDRAM High byte Data Mask SDRAM Write Enable SDRAM Column Address Strobe SDRAM Row Address Strobe SDRAM Chip Select SDRAM Bank Address 0 SDRAM Bank Address 0 SDRAM Clock SDRAM Clock Enable FLASH Data bus 8 Bits FLASH Address bus 22 Bits FLASH Write Enable FLASH Reset FLASH Output Enable FLASH Chip Enable SRAM Data bus 16 Bits SRAM Address bus 18 Bits SRAM High byte Data Mask SRAM Low byte Data Mask SRAM Write Enable SRAM Chip Enable SRAM Output Enable pio_sw pio_key PORT declarations _ Clock Input TIMI HI TI input CLOCK 27 27 MHz input CLOCK_50 50 MHz input EXT_CLOCK External Clock Push Button MIAMI M M TN input 3 0 KEY Pushbutton 3 0 DPDT Switch input 17 0 SW Toggle Switch 17 0
24. aclr WR1_LOAD rdreq IN_REQ amp WR_MASK 0 rdclk CLK q mDATAIN1 wrfull WR1_FULL wrusedw WR1_USE rdusedw write_side_fifo_rusedw1 Sdram_WR_FIFO assign mDATAIN Sdram_RD_FIFO Sdram_RD_FIFO write_fifo2 data WR2_DATA wrreq WR2 wrcik WR2_CLK aclr WR2_LOAD rdreq IN REQEWR MASKILI q mDATAIN2 wrfull WR2_FULL wrusedw WR2_USE rdusedw write_side_fifo_rusedw2 WR 5 0 2 mDATAIN1 mDATAIN2 read_fifo1 data mDATAOUT wrreq OUT VALIDERD MASKIOJ wrclk CLK aclr RD1_ LOAD rdreq RD1 rdclk RD1 q RD1 DATA wrusedw read side fifo wusedw1 rdempty RD1 EMPTY rdusedw RD1 USE y read fifo2 data mDATAOUT wrreq OUT VALID amp RD MASKILI wrclk CLK aclr RD2 LOAD rdreg RD2 rdclk RD2 802 DATA wrusedw read side fifo wusedw2 rdempty RD2 EMPTY rdusedw RD2 USE always posedge CLK begin SA lt ST SC_CL mLENGTH BA lt CS_N lt ICS_N CKE lt ICKE RAS_N lt 5 5 CL mLENGTH CAS_N lt ST SC_CL mLENGTH lt ST SC_CL mLENGTH PM_STOP lt ST SC_CL mLENGTH WE_N PM_DONE 2511 lt ST SC_CL SC_RCD mLENGTH 2 lt active amp amp ST gt SC CL 2500 mDATAOUT lt DQ end 2 b11 assign DO oe DQOUT DSIZE hzzzz assign active Read Write always posedge CLK or negedge RESET_N begi
25. and speed of the ball in y axis volatile alt u32 center x ball default value in x axis volatile alt_u32 center y ball default value in y axis volatile alt u32 count 1 score of the left side volatile alt 132 count score of the right side volatile alt u32 right x x axis position of right racket volatile alt u32 right y y axis position of right racket volatile alt u32 left x x axis position of left racket volatile alt u32 reft y y axis position of left racket volatile alt u32 x x axis position of either racket volatile alt u32 Itm y y axis position of either racket volatile alt u321tm y x rackets coordinates get from Verilog code alt busy sleep delay for the ball The first thing code should do is to get the coordinates of both the ball and the rackets Already do the signal transformation in the Verilog part we just use the coordinates of x pingpong and Itm y x But the format of these coordinates which is 20 bits long with the x and y combined together is different from the nomal coordinates X y_pingpong y_pingpong 2048 x_pingpong x Itm y 2048 ltm x By using the equations above we can conveniently transform the original coordinates to the ones we use in codes Then a big problem come into our eyesight we only get one coordinate from the touch panel at a moment how can we decide which one is for the left rackets which one is for the other racket In orde
26. bit end if do_load_mode 1 SA lt 2 b00 SDR_CL SDR_BT SDR_BL Generate the appropriate logic levels on RAS_N CAS_N and WE_N depending on the issued command if do_refresh 1 begin Refresh S 00 RAS 0 CAS 0 WE 1 RAS lt 0 5 lt 0 WEN lt 1 else if do_precharge 1 4 1 rw_flag 1 begin burst terminate if write is active RAS N lt 1 CAS_N lt 1 WEN lt 0 else if do_precharge 1 begin Precharge All 5 00 RAS 0 5 1 WE 0 RAS lt 0 CAS N lt 1 WEN 0 end else if do load mode 1 begin Mode Write 5 00 RAS 0 5 0 0 RAS lt 0 5 lt 0 WEN lt 0 else if do_reada 1 writea 1 begin Activate 5 01 10 RAS 0 5 1 1 RAS lt 0 5 lt 1 WEN lt 1 else if do_rw 1 Read Write S 01 or 10 RAS 1 CAS 0 WE 0 or 1 RAS_N lt 1 CAS N lt 0 WE_N lt rw flag end else if do_initial 1 begin RAS_N lt 1 CAS_N lt 1 WEN lt 1 else begin No Operation RAS 1 CAS 1 WE 1 RAS N lt 1 CAS_N lt 1 WEN lt 1 endmodule
27. include Sdram_Params h input CLK System Clock input input DSIZE 1 0 input DSIZE 8 1 0 output DSIZE 1 0 output DSIZE 8 1 0 reg DSIZE 8 1 0 Allign the input and output data to the SDRAM control path RESET N DATAIN DM DQOUT DQM DQM always posedge CLK negedge RESET begin if RESET_N 0 lt else lt end assign DQOUT DATAIN endmodule DSIZE 8 1 hF DM Sdram Control 4Port control interface module control interface CLK RESET N CMD ADDR REF ACK INIT CM ACK NOP READA WRITEA REFRESH PRECHARGE LOAD MODE SADDR REF REQ INIT REO CMD ACK y include Sdram Params h System Reset Data input from the host byte data masks SDRAM data mask ouputs input input input 2 0 input l ASIZE 1 0 input acknowledge input acknowledge input output output command output command output command output command output command output ASIZE 1 0 output output output reg reg reg reg reg reg reg ASIZE 1 0 reg reg reg Internal signals reg 15 0 reg 15 0 CLK RESET_N CMD ADDR REF_ACK INIT_ACK CM READA WRITEA REFRESH PRECHARGE LOAD_MODE SADDR REF REQ INIT READA WRITEA REFRESH PRECHARGE LOAD_MODE SADDR REF_REQ INIT timer init
28. peripheral can read the edascapture register to determine if an edge has occurred on any of the PIO input ports for edge capture registe iti in the register to the edgecapture register Edgecapture Register The interrupt code can be divided into three parts First part is KeyDown_interrupts when the key is pressed the function will set a flag to inform the outside code Second part is InitPIO One function of it is to initialize the PIO_KEY as the input and PIO_LED as output Another function is opening interruption and clear the edge capturing register The third part is main function It is used to wait for key interrupt and output signal to control the LED Their existing a while loop in this code to keep detecting if a interrupt is happening What s more we can only use sprintf to debug the interruption not printf 4 3 2 Game Control Design The basic purpose for the c code is control the movement of the ball and rackets thereby realizing the rule of the game Firstly we show all the important parameters in this paper volatile alt_u32 flag Indicate the beginning and end of the whole game volatile alt_u32 pingpong s coordinate for transmitting volatile alt_u32 x pingpong pingpoing s x axis coordinate volatile alt_u32 y pingpong 5 y axis coordinate volatile alt_u32 x_count direction and speed of the ball in x axis volatile alt_u32 y_count direction
29. protocol and build Nios system from the beginning instead of using the work already done by professor We use interruption function given by PIO which makes later work more convenient Even though we thought we finished the hardware we had to keep going back to debug it as we implemented more software features We ve learned a lot from project Thanks for Prof Edwards and our TA Shangru Li for all the help and suggestion 6 Codes C code include lt stdio h gt include system h include altera_avalon_pio_regs h include alt_types h include sys alt_irq h include priv alt_busy_sleep h define LEDCON 0x01 define KEYCON 0x01 define left 5 define right 700 define down 50 Hdefine up 450 Hdefine center_x 340 Hdefine center_y 250 Hdefine speed_normal 5000 Hdefine speed_high 2500 Hdefine speed_low 10000 volatile alt_u32 done 0 flag 2inform the occurrance of interrupt volatile alt_u32 x_pingpong 400 volatile alt_u32 pingpong 150 volatile alt u32 pingpong 0 volatile alt u32 Itm x volatile alt u32 volatile alt u32 y x volatile alt u32 left_x 100 volatile alt u32 v 150 volatile alt u32 left y x volatile alt u32 right x 600 volatile alt u32 right v 150 volatile alt u32 right y x volatile alt u32 1 0 volatile alt u32 2 0 volatile alt u32 score3 0 volatile alt u32 4 0 volatile alt u32 score volatile alt
30. timer lt timer 1 b1 if timer 0 REF_REQ lt 1 always posedge CLK or negedge 5 begin if _ 0 begin init_timer lt 0 REFRESH lt 0 PRECHARGE lt 0 LOAD_MODE lt 0 end else begin INIT_REQ lt 0 if init_timer lt INIT_PER 201 init_timer lt init_timer 1 if init_timer lt INIT_PER begin REFRESH lt 0 lt 0 LOAD_MODE lt 0 INIT_REQ lt 1 end else if init timer INIT_PER 20 begin REFRESH lt 0 PRECHARGE lt 1 LOAD MODE 0 INIT_REQ lt 0 end else if init timer INIT_PER 40 init_timer INIT_PER 60 init_timer INIT_PER 80 init_timer INIT_PER 100 init_timer INIT_PER 120 init_timer INIT_PER 140 init_timer INIT_PER 160 init_timer INIT_PER 180 begin REFRESH lt 1 PRECHARGE lt 0 LOAD_MODE lt 0 INIT_REQ lt 0 end else if init timer INIT_PER 200 begin REFRESH lt 0 PRECHARGE 20 LOAD MODE lt 1 INIT REQ lt 0 end else begin REFRESH lt 0 PRECHARGE lt 0 LOAD_MODE lt 0 INIT_REQ lt 0 end end end endmodule Sdram_Control_4Port command module command CLK RESET_N SADDR NOP READA WRITEA REFRESH PRECHARGE LOAD_MODE REF_REQ INIT_REQ PM_STOP PM_DONE REF_ACK CM_ACK OE SA BA CS_N CKE RAS_N CAS_N WE_N include Sdram_Params h input CLK input RESET_N input l AS
31. u32 count volatile alt u32 count volatile alt u32 flag volatile alt u32 flagl volatile alt u32 count r 0 volatile alt 132 count 0 score of the left side volatile alt u32 speed speed normal define LED BASE 0x00101020 static void KeyDown interrupts void context alt u32 id IOWR_ALTERA_AVALON_PIO_EDGE_CAP PIO_KEY_BASE KEYCON clear the edge capturing register Itm_y_x IORD_ALTERA_AVALON_PIO_DATA PIO_SW_BASE Itm_x Itm_y_x gt gt 12 800 4095 Itm_y Itm_y_x Oxfff 480 4095 if x_pingpong lt center_x amp amp Itm x center x left_x Itm_x 20 left_y ltm_y if X pingpong center x amp amp Itm x center x right x Itm x right v Itm if flag 0 flag 1 score1 0 score2 0 score3 0 score4 0 count_r 0 count_l 0 flag1 1 if Itm_x gt 0 amp amp Itm x 100 amp amp Itm gt 0 amp amp Itm y 60 speed speed low if Itm_x gt center_x 30 amp amp Itm x center 80 amp amp Itm gt 0 amp amp Itm y 60 speed speed normal if Itm right amp amp Itm x right 60 amp amp Itm gt 0 amp amp Itm lt 60 speed speed high void InitPlO void initializing the as the input and LED as output IOWR_ALTERA_AVALON_PIO_DIRECTION PIO_KEY_BASE 0 means input IOWR_ALTERA_AVALON_PIO_DIRECTION PIO_LED_BASE LEDCON 1 means output IOWR_ALTERA_AVALON_PIO_IRQ_MASK PIO_KEY
32. D mADDR mLENGTH end else begin lt 0 lt 0 lt 0 if mwR 0 8 mRD 0 amp amp ST 0 amp amp WR_MASK 0 WR1_LOAD 0 WR2_LOAD 0 begin Read Side 1 amp amp RD_MASK 0 amp amp amp amp RD1_LOAD 0 amp amp amp amp RD2 LOAD 0 if read side fifo wusedw1 lt rRD1_LENGTH begin end mADDR lt mLENGTH WR_MASK RD_MASK mWR mRD lt Read Side 2 rRD1_ADDR lt rRD1 LENGTH lt 2400 lt 2401 lt 0 1 else if read_side_fifo_wusedw2 lt rRD2_LENGTH begin end mADDR lt mLENGTH WR_MASK RD_MASK mWR mRD Write Side 1 rRD2_ADDR lt rRD2 LENGTH lt 2 600 lt 2410 lt 0 1 else if write_side_fifo_rusedw1 gt rWR1_LENGTH amp amp rWR1_LENGTH 0 begin mADDR lt rWR1 ADDR mLENGTH WR_MASK RD_MASK mWR mRD lt end Write Side 2 lt rWR1_LENGTH lt 2 601 lt 2 600 lt 1 0 else if write_side_fifo_rusedw2 gt rWR2_LENGTH amp amp rWR2_LENGTH 0 begin mADDR lt mLENGTH WR_MASK RD_MASK mWR mRD lt end end if MWR DONE begin WR_MASK lt mWR lt end if mRD DONE begin RD MASK lt mRD lt 0 end end end endmodule rWR2_ADDR lt rWR2_LENGTH lt 2 b10 lt 2 b00 lt 1 0 0 0 Sdram_Control_4Port sdr_data_path module sdr_data_path CLK RESET_N DATAIN DM DQOUT DQM
33. ITCIICS OFF ON OFF SERIDFR LOW F Figure4 5 Conversion timing of the serial port interface Figure 4 5 shows the typical operation of the serial interface of the ADC The serial clock provides the conversion clock and also controls the transfer of information to and from the ADC One complete conversion can be achieved with 24 ADC_DCLK cycles The detailed behavior of the serial port interface can be found in the datasheet of the ADC Note that the clock ADC_DCLK and chip enable signals SCEN of the serial port interface SHRAE the same signal with LCD driver IC Users should avoid controlling the LCD driver IC and ADC at the same time when designing the serial port interface controller Also because the chip enable signal SCEN inputted to the ADC comes up with a logic inverter the logic level of the SCEN should be inverse when it is used to control the ADC ADC_DIN is pattern control signal of AD converter and ADC_DOUT is the coordinate of X or Y Data can be transmitted when signal ADC_PENIRQ_n falls ADC_BUSY controls the pattern of AD converter which enables to receive data when it keeps low 4 2 2 DE2 Controller 4 2 2 1 Loading background into the Flash 1 Make sure the USB Blaster download cable is connected into the host PC 2 Load the Control Panel bit stream DE2_USB_API DEI USB API into the FPGA Please also refer to Chapter 3 DE2 DE1 Control Panel in the Altera DE2 DE1 User Manual for more details in the Control Panel S
34. IZE 1 0 SADDR input NOP input READA command System Clock System Reset Address Decoded NOP command Decoded READA input command input command input command input command input input input input output acknowledge output output module output 11 0 output 1 0 output 1 0 output output output output reg reg reg reg 11 0 reg 1 0 reg 1 0 reg reg reg reg Internal signals reg reg reg reg WRITEA REFRESH PRECHARGE LOAD_MODE REF_REQ INIT REQ STOP DONE OE SA BA CS_N CKE RAS_N CAS_N WE_N CM_ACK REF_ACK OE SA BA CS_N CKE RAS_N CAS_N WE_N do_reada do_writea do_refresh do_precharge Decoded WRITEA Decoded REFRESH Decoded PRECHARGE Decoded LOAD_MODE Hidden refresh request Hidden initial request Page mode stop Page mode done Refresh request Command acknowledge OE signal for data path SDRAM address SDRAM bank address SDRAM chip selects SDRAM clock enable SDRAM RAS SDRAM CAS SDRAM WE_N reg do_load_mode reg do_initial reg command_done reg 7 0 command_delay reg 1 0 rw_shift reg do_act reg rw_flag reg do_rw reg 6 0 oe_shift reg oel reg oe2 reg 0e3 reg 4 3 0 rp_shift reg rp_done reg ex_read reg ex_write wire ROWSIZE 1 0 ro
35. LTERA AVALON DATA PIO RIGHT BASE right while flag amp amp flag1 x_pingpong x_pingpong x_count y_pingpong y_pingpong y_count if right lt x_pingpong x_count 1 if x_pingpong gt right_x 20 amp amp pingpong lt right_x 20 88 y_pingpong gt right_y 20 amp amp y_pingpong lt right_y 20 x_count 1 if left gt x_pingpong x_count 1 if x_pingpong gt left_x 20 amp amp x pingpong left 20 amp amp y 20 amp amp pingpong left 20 x_count 1 if up lt y_pingpong y_count 1 if down gt y_pingpong y_count 1 right_y_x right_x right_y 2048 left_y_x left_x left_y 2048 score score1 score2 lt lt 4 score3 lt lt 8 score4 lt lt 12 x_y_pingpong y_pingpong 2048 x_pingpong IOWR_ALTERA_AVALON_PIO_DATA PIO_LED_BASE score IOWR_ALTERA_AVALON_PIO_DATA PIO_PINGPONG_BASE x_y_pingpong IOWR_ALTERA_AVALON_PIO_DATA PIO_LEFT_BASE left_y_x IOWR_ALTERA_AVALON_PIO_DATA PIO_RIGHT_BASE right_y_x alt_busy_sleep speed sudu if x_pingpong lt left count_r x_pingpong center_x y_pingpong center_y x_count 1 y_count 1 flag1 0 if x_pingpong gt right count_l x_pingpong center_x y_pingpong center_y x_count 1 y_count 1 flag1 0 if count_r gt 10 score3 1 score4 count_r 10 else score3 0 score4 count_r if count_l gt 10 5 1 1 score2 count_l 10
36. Touch Pong CSEE 4840 Embedded System Design Final Report Xiang Zhou xz2266 Hao Zheng hz2256 Ran Zheng rz2228 Younggyun Cho yc2704 Contents IV VI Abstract Introduction Architecture Design 4 1 Game Logic 4 1 1 Introduction 4 2 Hardware 4 2 1 LTM Controller 4 2 2 DE2 Controller 4 2 2 1 Loading background into the Flash 4 2 2 2 Generate mif file 4 2 2 3 Generate the whole system in Schematic form 4 3 Software 4 3 1 Interruption Design 4 3 2 Game Control Design Conclusion 5 1 Responsibilities 5 2 Lessons Learned Relevant Code 1 Abstract This project is conducted using the Altera DE2 development board We are aiming at implementing a touch screen ping pong game It will be a player vs player game with a specified rule Player serves and receives the ball by touching the screen connected to DE2 board To do so we need to set up the interface between touch screen and DE2 board 2 Introduction The Ping Pong game is an extension of the real Ping Pong game We set a few new rules for the game for example the ball can bounce on the two horizontal sides of the screen and once the ball hits the perpendicular side of the screen the game is over In terms of movement of the bat it can move in 2D screen by following the moving trajectory of the hand on the touch screen The horizontal rebound velocity of the ball depends on the direction of the moving racket when batting OCCUIS To implement the Ping pong game
37. VEIT TIT T TI inout 15 0 SRAM DO SRAM Data bus 16 Bits output 17 0 SRAM ADDR SRAM Address bus 18 Bits output SRAM UB N SRAM High byte Data Mask output SRAM LB N SRAM Low byte Data Mask output SRAM WE N SRAM Write Enable output SRAM CE N SRAM Chip Enable output SRAM OE N SRAM Output Enable VIII MI TI All inout port turn to tri state assign DRAM DQ assign DATA assign LCD DATA assign 50 DAT assign DATA assign AUD_ADCLRCK assign AUD DACLRCK assign AUD BCLK assign GPIO 1 Touch panel signal wire 7 0 ltm_r wire 7 0 ltm_g wire 7 0 ltm_b wire Itm_nclk wire Itm hd wire vd wire Itm den wire adc wire adc cs 16 hzzzz 16 hzzzz 8 hzz 1 bz 16 hzzzz 1 bz 1 bz 1 bz 36 777777777 LTM Red Data 8 Bits LTM Green Data 8 Bits LTM Blue Data 8 Bits LTM Clcok wire adc_penirq_n wire adc_busy wire adc_din wire adc dout wire adc Itm sclk wire Itm grst LTM Config wire Itm sclk wire Itm sda wire Itm scen wire Itm 3wirebusy n wire 11 0 x coord wire 11 0 coord wire new coord wire 2 0 photo cnt clock wire F CLK flash read clock reg 31 0 div sdram to touch panel timing wire mRead wire 15 0 Read_DATA1 wire 15 0 Read_DATA2 flash to sdram sdram wire 7 0 _ sRED flash to sdram red pixel data wire 7 0 SGREEN fl
38. _BASE open KEY interrupt IOWR ALTERA AVALON PIO EDGE CAP PIO KEY BASE KEYCON clear the edge capturing register register the interrupts register PIO KEY NULL KeyDown interrupts void main void flag 0 x_count 1 y_count 1 int start 0 beging of the whole game int beginL 0 beginR 0 flag for the serve side int play 1 flag of the whole game volatile alt_u32 key_state old_state new_state old_state KEYCON IOWR ALTERA AVALON PIO DATA PIO LED BASE old state initializing LED extinguish it InitPIO right x right x rright y 2048 left y x left y 2048 score score1 score2 lt lt 4 score3 lt lt 8 score4 lt lt 12 X_pingpong center_x y_pingpong center_y while 1 right_y_x ltm_x ltm_y 2048 left_y_x left_x left_y 2048 score score1 score2 lt lt 4 score3 lt lt 8 score4 lt lt 12 x_y_pingpong y_pingpong 2048 x_pingpong alt_busy_sleep 50000 delaySms key state IORD ALTERA AVALON DATA PIO KEY BASE amp KEYCON if key state OxFF interrupt caused by pulse continue remove keyboard jitter new state old state key state get the new state old state new state save the status of LED IOWR ALTERA AVALON DATA PIO LED BASE score IOWR ALTERA AVALON DATA PIO PINGPONG pingpong IOWR ALTERA AVALON DATA PIO LEFT BASE left y IOWR A
39. a KEY 0 div 3 assign adc Itm 5 adc amp Itm 3wirebusy n always posedge CLOCK 50 begin end div lt div 1 3wirebusy Itm sclk output 31 0 pio_racket_left output 31 0 pio_racket_right output 31 0 pio_pingpong output 15 0 output 31 0 pio_sw output pio_key hope 1 1 global signals clk CLOCK_50 reset n KEY O the pio hex out port from the pio hex pio hex the pio key port to the pio key pio key the pio left out port from the pio left pio racket left the pio pingpong out port from the pio pingpong pio pingpong the pio right out port from the pio right pio racket right the pio sw port to the pio sw pio sw the sram 16bit 512k 0 5 ADDR from the sram 16bit 512k 0 5 ADDR SRAM CE from the sram 16bit 512k O SRAM CE SRAM to and from the sram 16bit 512k O SRAM DO SRAM LB from the sram 16bit 512k O SRAM LB SRAM OE from the sram 16bit 512k O SRAM OE SRAM UB from the sram 16bit 512k O SRAM UB SRAM WE from the sram 16bit 512k O SRAM WE assign pio sw 8 dO y coord x assign pio keyznew coord lcd spi cotroller ul adc_spi_controller u2 touch point detector u3 flash to sdram c
40. ash to sdram green pixel data wire 7 0 sBLUE flash to sdram blue pixel data wire sdram write en flash to sdram write control wire sdram write sdram write signal system reset wire DLYO wire DLY1 wire DLY2 Structural coding WM assign penirq n GPIO_0 0 assign 0111 assign busy GPIO_0 2 assign 0131 zadc din assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign assign GPIO_0 4 GPIO_0 5 GPIO_0 6 GPIO_0 7 GPIO_0 8 GPIO 019 GPIO 0110 GPIO 0111 GPIO 0 12 0 13 GPIO 0114 0 15 0 16 GPIO 0 17 GPIO 0118 GPIO 0 19 GPIO 0 20 GPIO 0121 0 22 GPIO 0123 GPIO 0124 GPIO 0125 0 26 GPIO 0 27 GPIO 0128 GPIO 0 29 GPIO 0130 GPIO 0131 GPIO 0132 GPIO 0133 GPIO 0134 GPIO 0135 assign ltm_grst assign F_CLK adc Itm sclk Itm_b 3 Itm_b 2 Itm_b 1 Itm_b 0 tm nclk tm den tm hd tm vd Itm_b 4 Itm_b 5 Itm_b 6 Itm_b 7 ltm_g 0 ltm_g 1 ltm_g 2 ltm_g 3 ltm_g 4 ltm_g 5 ltm_g 6 Itm g 7 r 0 Itm_r 1 Itm_r 2 Itm_r 3 tm r 4 tm r 5 Itm_r 6 Itm_r 7 tm grst tm scen tm sd
41. b1 1 b0 wire 9 0 addr_score2 assign addr_score2 x_cnt x_cord_score2 y_cnt y_cord_score2 20 AV cZ O wire 10 0 x_cord_score3 wire 9 0 y_cord_score3 assign x_cord_score3 11 d600 assign y_cord_score3 10 d50 wire en_score3 assign en_score3 x_cnt gt x_cord_score3 amp amp x_cnt lt x_cord_score3 20 amp amp y_cnt gt y_cord_score3 amp amp y_cnt lt y_cord_score3 20 1 b1 1 b0 wire 9 0 addr_score3 assign addr_score3 x_cnt x_cord_score3 y_cnt y_cord_score3 20 K SCOPES TEAR wire 10 0 x_cord_score4 wire 9 0 y_cord_score4 assign x_cord_score4 11 d620 assign y_cord_score4 10 d50 wire en_score4 assign en_score4 x_cnt gt x_cord_score4 amp amp x_cnt lt x_cord_score4 20 y_cnt gt y_cord_score4 amp amp y_cnt lt y_cord_score4 20 1 b1 1 b0 wire 9 0 addr_score4 assign addr_score4 x_cnt x_cord_score4 y_cnt y_cord_score4 20 wire 15 0 HEX assign HEX pio_hex 16 H1234 reg 9 0 addr_score reg 3 0 num reg en_score always if en_score1 begin addr_score lt addr_score1 en_score lt 1 num lt HEX 3 0 end else if en_score2 begin addr_score lt addr_score2 en_score lt 1 num lt HEX 7 4 end else if en_score3 begin addr_score lt addr_score3 en_score lt 1 num lt HEX 11 8 end else if en_score4 begin addr_score lt addr_score4
42. ch panel The code below shows how we transform the needed data out IOWR_ALTERA_AVALON_PIO_DATA PIO_LED_BASE score IOWR_ALTERA_AVALON_PIO_DATA PIO_PINGPONG_BASE x_y_pingpong IOWR_ALTERA_AVALON_PIO_DATA PIO_LEFT_BASE left_y_x IOWR_ALTERA_AVALON_PIO_DATA PIO_RIGHT_BASE right_y_x 5 Conclusion 5 1 Responsibilities Ran Zheng drafted original proposal researched guide book and helped with whole system construction Hao Zheng developed all aspects of hardware modified Verilog code built NIOS system and set up interruption contributed to presentation slides and final report Xiang Zhou developed algorithm wrote software for control of game Write part of the final report Helped set hardware Younggyun Cho helped write game logic researched and initially implemented displaying image using ROM loaded background into the DE2 Flash Detected and fixed bugs contributed to final report Actually as a team we work together It s pretty hard to tell exactly what a single team member did in this project 5 2 Lessons Learned This game was successfully implemented Although this was a simple game and we believe it was a success it was definitely a lot harder to implement than we imagined In displaying image step it took a long time to figure out that using ROM to store picture is better We need to think from hardware perspective In system building step it is difficult to learn Verilog alone understand communication
43. circuits To control these functions users can use FPGA to configure the registers in the LCD driver IC via serial port interface Also there is an analog to digital converter ADC on the LTM to convert the analog X Y coordinates of the touch point to digital data and output to through the serial port interface of the ADC Both LCD driver IC and ADC serial port interfaces are connected to the FPGA via the 40 pin expansion header and IDE cable Because of the limited number of the expansion header the serial interfaces of the LCD driver IC and ADC need to share the same clock ADC_DCLK and chip enable SCEN signal on the expansion header To avoid both the serial port interfaces may interfere with each other when sharing the same clock and chip enable signals the chip enable signal CS which is inputted into the ADC will come up with a logic inverter as shown in Figure 4 1 Users need to pay attention controlling the shared signals when designing the serial port interface controller The detailed register maps of the LCD driver IC are listed in appendix chapter The specifications of the serial port interface of the LCD driver IC are described below Expansion leader LCD and touch panel module SDA DCLK SCEN 74HC1G04 ANC_DIN DOUT DOUT ADC_BUSY BUSY ADC PENIRQ K PENIRQ Figure4 1 Serial interface of the LCD touch panel module and AD7843 Timing Contro
44. cket lt addr_racket1 else addr_racket lt addr_racket2 wire 14 0 red_racket qiupai rom i14 address addr racket clock iCLK q red racket VIII T T T T assign read red display_area en_pong red_pong en_score reg_score iREAD_DATA1 15 8 en_racket iREA D_DATA1 15 8 red_racket iREAD_DATA1 15 8 8 b0 assign read green display_area en_score reg_score READ_DATA1 7 0 en_racket iREAD_DATA1 7 0 red_racket iREAD_DATA1 7 0 8 b0 assign read blue display_area en_score reg_score iREAD DATA2 7 0 en racket iREAD DATA2 7 0 red racket iREAD DATA2 7 0 8 bO HT TU x y counter and hd generator alwaysO posedge or negedge iRST n begin if liRST n begin x cnt lt 11 d0 mhd lt 140 else if x_cnt H_LINE 1 begin x_ent lt 11 d0 mhd lt 140 else begin x_cnt lt x_cnt 11 d1 mhd lt 1 d1 end end always posedge or negedge iRST_n begin if liRST n y cnt lt 10 d0 else if x cnt H_LINE 1 begin if y cnt LINE 1 cnt lt 1040 else y cnt lt y cnt 10 d1 end end MINIMI III touch panel timing always posedge or negedge iRST n begin if iRST_n mvd lt 1 b1 else if y cnt 1040 lt 10 else mvd lt 1 b1 end always posedge or negedge iRST n begin if liRST n begin
45. coord wire nextpic_en wire prepic_en reg nextpic_set reg prepic_set reg 2 0 photo_cnt Structural coding if incoming x and y coordinates fit next picture command area nextpic_en goes high assign nextpic en iX COORD gt NEXT PIC XBD1 amp amp iX lt NEXT PIC XBD2 amp amp COORD gt NEXT PIC YBD1 amp amp iY COORD lt NEXT PIC YBD2 1 0 if incoming x and y coordinates fit previous picture command area nextpic en goes high assign prepic 1 gt PRE_PIC_XBD1 amp amp iX lt PRE PIC XBD2 amp amp iY_COORD gt PRE PIC YBD1 amp amp iY lt PRE_PIC_YBD2 1 0 always posedge or negedge 5 n begin if iRST n mnew lt 0 mnew_coord lt iNEW_COORD always posedge negedge iRST n begin if iRST n nextpic set lt 0 else if mnew coord amp amp nextpic en amp amp liSDRAM WRITE nextpic set 1 else nextpic set 0 end always posedge or negedge 5 n begin if iRST n prepic set lt 0 else if mnew coord amp amp amp amp liSDRAM WRITE prepic set 1 else prepic set lt 0 end always posedge or neged
46. en SDRAM frame buffer Sdram_Control_4Port 7 pio_racket_left pio_racket_left pio_racket_right pio_racket_right pio pingpang pio pingpong hex HOST Side REF_CLK CLOCK_50 RESET_N 1 b1 Write Side 1 WR1_DATA sRED sGREEN WR1 sdram_write WR1_FULL WR1_FULL WR1_ADDR O WR1_MAX_ADDR 800 480 WR1_LENGTH 9 h80 WR1_LOAD DLYO WR1_CLK F_CLK Write Side 2 WR2 DATA 8 hO sBLUE WR2 sdram write WR2_ADDR 22 h100000 MWR2_MAX_ADDR 22 h100000 800 480 WR2_LENGTH 9 h80 WR2_LOAD DLYO WR2_CLK F_CLK FIFO Read Side 1 RD1_DATA Read_DATA1 RD1 mRead RD1 ADDR O RD1 MAX ADDR 800 480 RD1 LENGTH 9 h80 RD1_LOAD DLYO RD1 CLK Itm nclk Read Side 2 RD2 DATA Read DATA2 RD2 mRead RD2_ADDR 22 h100000 RD2_MAX_ADDR 22 h100000 800 480 Reset_Delay endmodule RD2_LENGTH 9 h80 RD2_LOAD DLYO RD2_CLK Itm_nclk SDRAM Side SA DRAM_ADDR BA DRAM_BA_1 DRAM_BA_0 CS_N DRAM_CS_N CKE DRAM_CKE RAS_N DRAM_RAS_N CAS_N DRAM_CAS_N WE_N DRAM_WE_N DQ DRAM DQM DRAM_UDQM DRAM_LDQM CLK DRAM 33 Itm u8 iCLK CLOCK_50 iRST KEY O ORST O DLYO oRST 1 DLY1 oRST 2 DLY2 flash_to_sdram_controller module flash_to_sdram_controller iRST_n iPHOTO_NUM Flash side iF_CLK FL_DQ
47. ge 5 n begin if iRST n photo cnt 0 else begin if nextpic set begin if photo cnt PHOTO NUM 1 photo cnt lt 0 else photo cnt lt photo cnt 1 end if prepic_set begin if photo cnt 0 photo_cnt lt PHOTO_NUM 1 else photo_cnt lt photo_cnt 1 end end end assign oPHOTO_CNT photo_cnt endmodule adc_spi_controller module adc_spi_controller iCLK iRST_n oADC_DIN oADC_DCLK oADC_CS iADC_DOUT iADC_BUSY iADC PENIRQ n oX COORD oY COORD oNEW COORD parameter SYSCLK FRO 50000000 parameter ADC DCLK FRO 1000 parameter ADC DCLK CNT SYSCLK_FRQ ADC_DCLK_FRQ 2 PORT declarations input iCLK input iRST n input ADC DOUT input iADC_PENIRQ_n input iADC_BUSY output oADC_DIN output oADC_DCLK output oADC_CS output 11 0 oX_COORD output 11 0 oY_COORD output oNEW_COORD Ps _________________________________________ REG WIRE declarations sss SS Z ss reg d1_PENIRQ_n reg d2_PENIRQ_n wire touch_irq reg 15 0 dclk_cnt wire dclk reg transmit_en reg 6 0 spi_ctrl_cnt wire oADC CS reg mcs reg wire 7 0 config reg wire 7 0 y_config_reg wire 7 0 ctrl_reg reg 7 0 mdata_in reg y_coordinate_config wire eof_transmition reg 5 0 bit_cnt reg madc out reg 11 0 mx_coordinate reg 11 0 my_coordinate reg 11 0 oX_COORD reg 11 0 oY_COORD wire rd_c
48. in end oSDRAM WRITE lt 0 ORED lt 0 OGREEN lt 0 OBLUE lt 0 else if rgb_sync begin oSDRAM WRITE lt 1 ORED lt fl_dq_delay1 OGREEN lt dq delay2 oBLUE lt dq delay3 end else begin OSDRAM WRITE lt 0 oRED lt 0 OGREEN lt 0 oBLUE lt 0 endmodule three_wire_controller module three wire controller Host Side Host Side input input input input 15 0 output output iRST iDATA iSTR oRDY oCLK Serial Side 5 SDA oSCLK RST iSTR DATA oRDY output oCLK Serial Side output 5 inout SDA output oSCLK Internal Register and Wire reg mSPI reg 15 0 mSPI DIV reg mSEN reg mSDATA reg mSCLK reg mACK reg 4 0 mST parameter Freq 50000000 50 MHz parameter SPI 20000 20 KHz Serial Clock Generator alwaysO posedge or negedge iRST begin if iRST begin mSPI_CLK lt 0 mSPI_CLK_DIV lt 0 end else begin mSPI_CLK_DIV lt CLK_Freq SPI_Freq mSPI_CLK_DIV lt mSPI CLK DIV 1 else begin mSPI CLK DIV 0 mSPI_CLK lt mSPI end end end Parallel to Serial always negedge mSPI CLK or negedge iRST begin if iRST begin mSEN lt 1 b1 mSCLK lt 1 b0 mSDATA lt 1 bz 1 b1 1 b0 mSPI CLK 17 mSDATA mACK lt 1 b0 mST lt
49. k lines SDRAM address output SDRAM bank address SDRAM Chip Selects SDRAM clock enable SDRAM Row address SDRAM Column address SDRAM write enable Output data request to input data request to wire wire wire wire wire wire wire wire wire wire wire wire load_mode Sdram PLL sdram pll1 control interface control1 nop reada writea refresh precharge oe ref_ack ref_req init req cm ack active inclkO REF CO CLK c1 SDR_CLK C2 CLK 33 CLK CLK RESET N RESET CMD CMD ADDR mADDR REF ACK ref ack READA reada WRITEA writea REFRESH refresh PRECHARGE precharge LOAD_MODE load_mode SADDR saddr REF_REQ ref_req INIT_REQ init_req CMD_ACK CMDACK command command1 CLK CLK RESET_N RESET_N SADDR saddr NOP nop READA reada WRITEA writea REFRESH refresh LOAD_MODE load_mode PRECHARGE precharge REF_REQ ref_req INIT_REQ init_req REF ACK ref ack OE oe PM_STOP PM_STOP PM_DONE PM_DONE SA ISA BA IBA CS_N ICS_N CKE ICKE RAS_N IRAS_N CAS_N ICAS_N WE N IWE data path data path1 CLK CLK RESET_N RESET_N DATAIN mDATAIN DM 2 b00 DQOUT DQOUT DQM IDQM Sdram WR FIFO _ write fifo1 data WR1 DATA wrreq WR1 wrclk WR1_CLK
50. l 1 The Serial Port Interface of the LCD Driver IC Figure4 2 Frame format and timing diagram of the serial port interface The figure above shows the frame format and timing diagram of the serial port interface The LCD driver IC recognizes the start of data transfer on the falling edge of SCEN input and starts data transfer When setting instruction theTPG110 inputs the setting values via SDA on the rising edge of input SCL The first 6 bits A5 A0 specify the address of the register The next bit means Read Write command 0 15 write command 1 is read command Then the next cycle is turn round cycle Finally the last 8 bits are for Data setting D7 DO The address and data are transferred from the MSB to LSB sequentially The data is written to the register of assigned address when End of transfer is detected after the 16th SCL rising cycles Data is not accepted if there are less or more than 16 cycles for one transaction 2 Input timing of the LCD panel display function This section will describe the timing specification of the LCD synchronous signals and RGB data Figure below illustrates the basic timing requirements for each row horizontal that is displayed on the LCD panel active low pulse of specific duration time in the figure is applied to the horizontal synchronization HD input of the LCD panel which signifies the end of one row of data and the start of the next The data RGB inputs
51. n if RESET_N 0 begin CMD lt 5 lt 0 Pre RD lt 0 Pre_WR lt 0 Read lt 0 Write lt 0 OUT_VALID lt 0 IN_REQ lt 0 mWR_DONE lt 0 mRD_DONE lt 0 end else begin Pre lt mRD Pre WR lt mWR case 0 ST begin if Pre RD mRD 2 b01 begin Read Write lt lt 12 1200 1 bO 1 b1 160 1 b1 ISA IRAS_N ICAS_N IWE_N 1 b0 1 b1 1 b0 ST SC_CL mLENGTH amp amp Write CMD lt 2 501 ST lt 1 end else if Pre_WR mWR 2 b01 begin Read lt 0 Write lt 1 CMD lt 2710 ST lt 1 1 begin if CMDACK 1 begin CMD lt 2 b00 ST lt 2 end end default begin if ST SC_CL SC_RCD mLENGTH 1 ST lt ST 1 else ST lt 0 end endcase if Read begin if ST SC_CL SC_RCD 1 OUT_VALID lt 1 else if ST SC_CL SC_RCD mLENGTH 1 begin OUT_VALID lt 0 Read lt 0 mRD_DONE lt 1 end end else mRD_DONE lt 0 if Write begin if ST SC_CL 1 end end lt 1 else if ST SC_CL mLENGTH 1 lt 0 else if ST SC_CL SC_RCD mLENGTH begin Write lt 0 mWR_DONE lt 1 else mWR_DONE lt 0 Internal Address amp Length Control always posedge CLK or negedge RESET_N begin if IRESET N begin end else rWR1_ADDR lt rWR1_MAX_ADDR rWR2_ADDR rWR2_MAX_ADDR lt
52. nger to control ping pong bat through touching on the screen and the racket in the game would move along with movement of the touching trace The ball would bounce when hitting the upper and down wall or the rackets just like the bouncing ball in lab3 while when the ball hit the left and right side of the wall that round of game will be over and the ball and bats would get back to the default position 4 2 2 Playing rules 1 In order to be fair for both players the players would serve alternately by touching any point of the panel and the initial moving angle of the ball would be 45 degree 2 The player can only move their rackets in his own half side of the table and players have several chances to hit the ball before the ball runs out of the boundary 3 Racket can only be moved when the ball get into the corresponding side of the table 4 The one who misses the ball through letting it run out of the boundary in his own side would lose that round and the opposite side would gain one point 5 The one who gains 11 points first would win the whole game 6 If the players want to continue playing they just need to touch the left corner of the panel and the score would be set to zero 4 2 Hardware 4 2 1 LTM Controller The LCD and touch panel module on the LTM is equipped with a LCD driver IC to support three display resolutions and with functions of source driver serial port interface timing controller and power supply
53. nt 49 spi ctrl cnt lt 0 else spi ctrl cnt lt spi ctrl cnt 1 end end always posedge or negedge 5 n begin if iRST n begin mcs lt 1 mdclk 0 mdata_in lt 0 y_coordinate_config lt 0 mx_coordinate lt 0 my_coordinate lt 0 end else if transmit_en begin if dclk begin if spi_ctrl_cnt 0 begin mcs lt 0 mdata_in lt ctrl_reg end else if spi_ctrl_cnt 49 begin mdclk lt 0 y coordinate config lt y coordinate config if coordinate config mcs lt 1 else mcs lt 0 end else if spi_ctrl_cnt 0 mdclk lt mdclk if mdclk mdata in lt mdata_in 6 0 1 bO if mdclk begin if rd_coord_strob begin if y_coordinate_config my_coordinate lt my coordinate 10 0 madc out else mx coordinate lt mx coordinate 10 0 madc out end end end end end assign oADC 5 mcs assign OADC_DIN mdata in 7 assign oADC DCLK mdclk assign ctrl reg y coordinate config 7 y config reg x config reg assign eof transmition y coordinate config amp spi cnt 49 dclk assign coord strob spi cnt 19 amp amp spi cnt 241 1 0 always posedge or negedge iRST n begin if liRST n begin oX COORD 0 oY_COORD lt 0 else if eof_transmition amp amp my_coordinate 0 begin oX COORD lt mx_coordinate oY_COORD lt my_coordina
54. oHD lt 1 d0 oVD lt 1 d0 lt 1 d0 oLCD_R lt 8 d0 oLCD G lt 8 d0 oLCD_B lt 8 d0 end else begin oHD lt mhd oVD lt mvd ODEN lt display_area oLCD_R lt read red oLCD_G read green oLCD B lt read blue end end endmodule touch point detector module touch point detector iCLK iRST n iX COORD iY COORD COORD 5 WRITE oPHOTO_CNT parameter PHOTO NUM 3 total photo numbers parameter NEXT_PIC_XBD1 12 h0 parameter NEXT_PIC_XBD2 12 h300 parameter NEXT_PIC_YBD1 12 he00 parameter NEXT_PIC_YBD2 12 hfff parameter PRE_PIC_XBD1 12 hd00 parameter PRE_PIC_XBD2 12 hfff parameter PRE_PIC_YBD1 12 h000 parameter PRE_PIC_YBD2 12 h200 PORT declarations input iCLK system clock 50Mhz input iRST_n system reset input 11 0 COORD X coordinate form touch panel input 11 0 COORD Y coordinate form touch panel input iNEW COORD new coordinates indicate input iSDRAM WRITE EN sdram write enable output 2 0 _ displaed photo number REG WIRE declarations reg mnew_
55. oftware 3 Execute the Control Panel application software 4 Open the USB port by clicking Open gt Open USB Port 0 The DE2 DE1 Control Panel application will list all the USB ports that connect to DE2 DE1 board 5 Switch to FLASH page and click on the Chip Erase 40 Sec bottom to erase Flash data DB DE Control Panel Open Help About PS2 Keyboard Figure4 6 Loading picture 6 Click on the File Length checkbox to indicate that you want to load the entire file 7 Click on the Write a File to FLASH bottom When the Control Panel responds with the standard Windows dialog box and asks for the source file select the tab222_2 bmp file in the Photo directory Figure4 7 Background 4 2 2 2 Generate mif file A memory Initialization File mif is an ASCII text file with the extension mif that specifies the initial content of a memory block CAM RAM or ROM that is the initial values for each address This file is used during Quartus project compilation and or simulation The MIF file serves as an input file for memory initialization in the Quartus compiler and simulator You can also use a Hexadecimal Intel Format File hex to provide memory initialization data MATLAB code Img imread PINGPONG BMP BW Img R BW 1 4 2 2 3 Generate block diagram of system 0 nens q 0 vee 0 O 0
56. on the LCD panel are not valid for a time period called the hsync back porch after the hsync pulse occurs which is followed by the display area tna During the data display area the RGB data drives each pixel in turn across the row being displayed Also during the period of the data display area the data enable signal DEN must be driven to logic high Finally there is a time period called the hsync front porch where the RGB signals are not valid again before the next hsync pulse can occur Ud Y sas R0 R7 G0 G7 Valid Data 0 7 Display Area th bp fp Horizontal Linef t p ten DEN _ Lo Figure4 3 LCD horizontal timing specification The timing of the vertical synchronization is the same as shown in Figure 4 4 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Tables 3 2 and 3 3 in reference UTM_User_Manual show for different resolutions the durations of time periods tipw tha and for both horizontal and vertical timing Finally the timing specification of the synchronous signals is shown in the Table 3 4 1 Vertical Line Figure4 4 LCD vertical timing specification 3 The serial interface of the AD converter This section will describe how to obtain the X Y coordinates of the touch poin
57. ontroller u4 Host Side 50 iRST_n DLYO 3 wire Side O3WIRE SCLK Itm sclk io3WIRE SDAT Itm sda O3WIRE SCEN Itm scen 03WIRE BUSY n ltm 3wirebusy n iCLK CLOCK_50 iRST_n DLYO oADC DIN adc din OADC DCLK adc dclk oADC CS adc cs ADC_DOUT adc_dout ADC_BUSY adc_busy ADC_PENIRQ_n adc_penirq_n oX_COORD x_coord COORD y ONEW COORD new coord iCLK CLOCK_50 iRST_n DLYO iX_COORD x_coord iY_COORD y_coord iNEW COORD new coord WRITE EN sdram write en OPHOTO CNT photo cnt SEG7_LUT_8 Icd_timing_controller u5 u6 iPHOTO_NUM 2 jRST n DLY1 DO FL OFL_ADDR FL_ADDR oFL WE N FL WE N oFL RST n FL RST oFL OE OE oFL CE N FL CE OSDRAM WRITE EN sdram write OSDRAM WhRITE sdram write oRED sRED oGREEN sGREEN oBLUE sBLUE y 5 oSEG1 HEX1 OSEG2 HEX2 5 OSEGA HEXA OSEG5 HEXS oSEG6 HEX6 OSEG7 HEX7 DIG 4 h0 x_coord 4 h0 y_coord ON_OFF 8 b01110111 iCLK Itm nclk JRST n DLY2 sdram side iREAD DATA1 Read DATA iREAD DATA2 Read DATA2 oREAD SDRAM EN mRead side OLCD R ltm OLCD G Itm OLCD B ltm b OHD Itm hd oVD Itm oDEN Itm d
58. oord_strob reg oNEW COORD reg 5 0 irg_cnt reg 15 0 clk_cnt EE Structural coding f assign config reg 8 h92 assign config reg 8 hd2 always posedge or negedge iRST n begin if iRST_n madc_out lt 0 else madc_out lt iADC_DOUT end HMM detect always posedge or negedge iRST_n begin if begin d1_PENIRQ_n lt 0 92_ _ lt 0 else begin d1_PENIRQ_n lt iADC_PENIRQ_n d2_PENIRQ_n lt d1_PENIRQ_n end end if iADC_PENIRQ_n form high to low touch_irq goes high assign touch_irq d2 PENIRQ n amp d1 n if touch goes high starting transmit procedure transmit en goes high if end of transmition and no penirq transmit procedure stop always posedge or negedge 5 n begin if iRST n transmit en lt 0 else if eof transmition amp amp iADC n transmit en lt 0 else if touch transmit en 1 end always posedge or negedge 5 n begin if lRST n dclk_cnt lt 0 else if transmit_en begin if dclk_cnt ADC_DCLK_CNT dclk_cnt lt 0 else dclk cnt lt dclk cnt 1 end else dclk cnt lt 0 end assign dclk2 cnt ADC DCLK 1 0 always posedge or negedge iRST n begin if liRST n spi ctrl cnt lt 0 else if dclk begin if spi ctrl c
59. r to settle this problem we set a rule for the game racket can t move until the ball and the touch point reach the corresponding side The code is as follows if x_pingpong gt center_x amp amp lem_x gt center_x right_x ltm_x rght yzltm y What we need do now is the easy part designing the rules of game As we already know the trace of rackets is the same with the touch position and what s left is the movement of the ball By setting the movement step and the direction of the ball and then adding then to the previous position we can get the instant position of the ball For example for the ball moving towards left direction we have if x_pingpong gt right_x 20 amp amp x pingpong right x 20 amp amp pingpong right y 20 amp amp y pingpong right 20 x_count 1 By considering all the situations the ball would move towards left we can get the direction needed for realizing the ball s trace Then just by adding the data with the the previous x axis position we can get the x_pingpong which is shown below x_poingpong x_pingpong x_count y_poingpong y_pingpong y_count In terms of the score of the game we just need to count the number of ball being out of boundary on each side Whoever get the 11 points would win this game The final part of the C code is to transmit the controlled data from the nios system to the LCD_Timing_Controller so that the reprocessed pictures can be sent to the tou
60. se begin if SC PM 0 begin rp shift lt rp_shift gt gt 1 done lt shift 0 end else begin if read 0 amp amp ex write 0 begin rp shift lt rp_shift gt gt 1 rp done lt lt shift 0 end else begin if PM_STOP 1 begin rp shift lt rp_shift gt gt 1 rp_done lt rp_shift 0 ex_read lt 1 b0 ex_write lt 1 b0 end end end end end end end logic that generates the OE signal for the data path module For normal burst write he duration of OE is dependent on the configured burst length For page mode accesses SC_PM 1 the OE signal is turned on at the start of the write command and is left on until a PRECHARGE page burst terminate is detected always posedge CLK or negedge 5 begin if RESET_N 0 begin oe_shift lt 0 1 lt 0 2 lt 0 lt 0 else begin if SC_PM 0 begin if do_writea 1 begin if SC_BL 1 Set the shift register to the appropriate on burst length end else begin end end else begin oe_shift lt 0 value based else if SC_BL 2 oe_shift lt 1 else if SC_BL 4 oe_shift lt 7 else if SC_BL 8 oe_shift lt 127 oel lt 1 oe_shift lt oe_shift gt gt 1 oe1 oe2 4 lt oe shift 0 oe1 lt 0 2 lt 0e3 if SC_RCD 2 else lt oe3 OE lt 0 4
61. t from the AD converter The LTM also equipped with an Analog Devices AD7843 touch screen digitizer chip The AD7843 is a 12 bit analog to digital converter ADC for digitizing x and y coordinates of touch points applied to the touch screen To obtain the coordinate from the ADC the first thing users need to do is monitor the interrupt signal ADC_PENIRQ_n outputted from the ADC By connecting a pull high resistor the ADC_PENIRQ_n output remains high normally When the touch screen connected to the ADC is touched via a pen or finger the ADC_PENIRQ_n output goes low initiating an interrupt to a FPGA that can then instruct a control word to be written to the ADC via the serial port interface The control word provided to the ADC via the DIN pin is shown in reference The control word provided to the ADC via the DIN pin is shown in Table 3 5 in reference LIM User Manual This provides the conversion start channel addressing ADC conversion resolution configuration and power down of the ADC The detailed information on the order and description of these control bits can be found from the datasheet of the ADC in the DATASHEET folder on the LTM System CD ROM ADC DCLK 1 l 8 1 8 1 ioc pi A2 At 40 Por poo H CONVERSION IDLE ADG BUSY n ome l THREE THREESTATE i i Lor i THREE STATE 1 o ZERO RLLED 159 XN SWTCHFS OFF ON OFF SERIDFR HIGH XN SW
62. te end end alwaysO or negedge iRST_n begin if iRST_n _ lt 0 else if eof_transmition amp amp my_coordinate 0 _ lt 1 else ONEW_COORD lt 0 end endmodule Sdram_Control_4Port Sdram_Control_4Port module Sdram_Control_4Port HOST Side REF_CLK RESET_N CLK CLK_33 FIFO Write Side 1 WR1_DATA WR1 WR1 ADDR WR1 MAX ADDR WR1 LENGTH WR1 LOAD WR1 WR1 FULL WR1 USE Write Side 2 2 DATA WR2 WR2 ADDR WR2 MAX ADDR 2 LENGTH WR2_LOAD WR2_CLK WR2_FULL WR2_USE FIFO Read Side 1 RD1_DATA RD1 RD1_ADDR RD1_MAX_ADDR RD1_LENGTH RD1_LOAD RD1_CLK RD1_EMPTY RD1_USE FIFO Read Side 2 RD2_DATA RD2 RD2 ADDR RD2 MAX ADDR RD2 LENGTH RD2 LOAD RD2_CLK RD2_EMPTY RD2_USE SDRAM Side SA BA CS N CKE RAS N CAS N WE N DQ DQM SDR_CLK include Sdram_Params h HOST Side input REF_CLK input RESET_N Write Side 1 input DSIZE 1 0 WR1_DATA System Clock System Reset Data input input input ASIZE 1 0 input ASIZE 1 0 input 8 0 input clear input output output 15 0 Write Side 2 input DSIZE 1 0 input input ASIZE 1 0 input ASIZE 1 0 input 8 0 input clear input output output 15 0 FIFO Read Side 1 output DSIZE 1 0 input input ASIZE 1 0 input
63. timer Svstem Clock System Reset Command input Address Refresh request Initial request Command acknowledge Decoded NOP command Decoded READA Decoded WRITEA Decoded REFRESH Decoded PRECHARGE Decoded LOAD_MODE Registered version of ADDR Hidden refresh request Hidden initial request Command acknowledge Command decode and ADDR register always posedge CLK or negedge RESET_N begin if RESET_N 0 begin NOP lt 0 READA lt 0 WRITEA lt 0 SADDR lt 0 end else begin SADDR lt ADDR address to keep proper the command if CMD 3 b000 NOP lt 1 else NOP lt 0 if CMD 3 b001 READA lt else READA lt 0 if CMD 3 b010 WRITEA lt 1 else WRITEA lt 0 end end Generate CMD_ACK always posedge CLK or negedge RESET_N begin if RESET_N 0 _ lt 0 register the alignment with NOP command READA command WRITEA command else end refresh timer if CM_ACK 1 amp CMD_ACK 0 CMD_ACK lt 1 else CMD_ACK lt 0 always posedge CLK or negedge _ begin if RESET_N 0 begin timer lt 0 REF_REQ lt 0 else begin end end initial timer if REF_ACK 1 begin timer lt REF_PER REF REQ lt 0 end else if INIT REQ 1 begin timer lt REF 200 REF REQ lt 0 end else
64. waddr wire COLSIZE 1 0 coladdr wire BANKSIZE 1 0 bankaddr assign rowaddr SADDR ROWSTART ROWSIZE 1 ROWSTART assignment of the row address bits from SADDR assign coladdr SADDR COLSTART COLSIZE 1 COLSTARTI assignment of the column address bits assign bankaddr SADDR BANKSTART BANKSIZE 1 BANKSTARTI assignment of the bank address bits This always block monitors the individual command lines and issues a command to the next stage if there currently another command already running always posedge CLK negedge RESET begin if RESET_N 0 begin do_reada lt 0 do_writea lt 0 do_refresh lt 0 do_precharge lt 0 do_load_mode lt 0 do_initial lt 0 command_done lt 0 command delay lt 0 rw flag lt 0 rp_shift lt 0 rp_done lt 0 ex_read lt 0 ex_write lt 0 else begin Issue the appropriate command if the sdram is not currently busy if INIT_REQ 1 begin do_reada lt 0 do_writea lt 0 do_refresh lt 0 do precharge lt 0 do_load_mode lt 0 do initial lt 1 command_done lt 0 command delay lt 0 rw flag lt 0 rp_shift lt 0 rp_done lt 0 ex_read lt 0 ex_write lt 0 else begin do_initial lt 0 if REF_REQ 1 REFRESH 1 amp command_done 0 amp do_refresh amp rp_done Refresh amp do_reada 0 amp do_writea

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